1 /* Definitions of target machine for GNU compiler.
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by James E. Wilson <wilson@cygnus.com> and
5 David Mosberger <davidm@hpl.hp.com>.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
46 #include "sched-int.h"
49 #include "target-def.h"
52 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "tree-gimple.h"
56 /* This is used for communication between ASM_OUTPUT_LABEL and
57 ASM_OUTPUT_LABELREF. */
58 int ia64_asm_output_label
= 0;
60 /* Define the information needed to generate branch and scc insns. This is
61 stored from the compare operation. */
62 struct rtx_def
* ia64_compare_op0
;
63 struct rtx_def
* ia64_compare_op1
;
65 /* Register names for ia64_expand_prologue. */
66 static const char * const ia64_reg_numbers
[96] =
67 { "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
68 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
69 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
70 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
71 "r64", "r65", "r66", "r67", "r68", "r69", "r70", "r71",
72 "r72", "r73", "r74", "r75", "r76", "r77", "r78", "r79",
73 "r80", "r81", "r82", "r83", "r84", "r85", "r86", "r87",
74 "r88", "r89", "r90", "r91", "r92", "r93", "r94", "r95",
75 "r96", "r97", "r98", "r99", "r100","r101","r102","r103",
76 "r104","r105","r106","r107","r108","r109","r110","r111",
77 "r112","r113","r114","r115","r116","r117","r118","r119",
78 "r120","r121","r122","r123","r124","r125","r126","r127"};
80 /* ??? These strings could be shared with REGISTER_NAMES. */
81 static const char * const ia64_input_reg_names
[8] =
82 { "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7" };
84 /* ??? These strings could be shared with REGISTER_NAMES. */
85 static const char * const ia64_local_reg_names
[80] =
86 { "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7",
87 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15",
88 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23",
89 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31",
90 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39",
91 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47",
92 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55",
93 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63",
94 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71",
95 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79" };
97 /* ??? These strings could be shared with REGISTER_NAMES. */
98 static const char * const ia64_output_reg_names
[8] =
99 { "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7" };
101 /* String used with the -mfixed-range= option. */
102 const char *ia64_fixed_range_string
;
104 /* Determines whether we use adds, addl, or movl to generate our
105 TLS immediate offsets. */
106 int ia64_tls_size
= 22;
108 /* String used with the -mtls-size= option. */
109 const char *ia64_tls_size_string
;
111 /* Which cpu are we scheduling for. */
112 enum processor_type ia64_tune
;
114 /* String used with the -tune= option. */
115 const char *ia64_tune_string
;
117 /* Determines whether we run our final scheduling pass or not. We always
118 avoid the normal second scheduling pass. */
119 static int ia64_flag_schedule_insns2
;
121 /* Determines whether we run variable tracking in machine dependent
123 static int ia64_flag_var_tracking
;
125 /* Variables which are this size or smaller are put in the sdata/sbss
128 unsigned int ia64_section_threshold
;
130 /* The following variable is used by the DFA insn scheduler. The value is
131 TRUE if we do insn bundling instead of insn scheduling. */
134 /* Structure to be filled in by ia64_compute_frame_size with register
135 save masks and offsets for the current function. */
137 struct ia64_frame_info
139 HOST_WIDE_INT total_size
; /* size of the stack frame, not including
140 the caller's scratch area. */
141 HOST_WIDE_INT spill_cfa_off
; /* top of the reg spill area from the cfa. */
142 HOST_WIDE_INT spill_size
; /* size of the gr/br/fr spill area. */
143 HOST_WIDE_INT extra_spill_size
; /* size of spill area for others. */
144 HARD_REG_SET mask
; /* mask of saved registers. */
145 unsigned int gr_used_mask
; /* mask of registers in use as gr spill
146 registers or long-term scratches. */
147 int n_spilled
; /* number of spilled registers. */
148 int reg_fp
; /* register for fp. */
149 int reg_save_b0
; /* save register for b0. */
150 int reg_save_pr
; /* save register for prs. */
151 int reg_save_ar_pfs
; /* save register for ar.pfs. */
152 int reg_save_ar_unat
; /* save register for ar.unat. */
153 int reg_save_ar_lc
; /* save register for ar.lc. */
154 int reg_save_gp
; /* save register for gp. */
155 int n_input_regs
; /* number of input registers used. */
156 int n_local_regs
; /* number of local registers used. */
157 int n_output_regs
; /* number of output registers used. */
158 int n_rotate_regs
; /* number of rotating registers used. */
160 char need_regstk
; /* true if a .regstk directive needed. */
161 char initialized
; /* true if the data is finalized. */
164 /* Current frame information calculated by ia64_compute_frame_size. */
165 static struct ia64_frame_info current_frame_info
;
167 static int ia64_use_dfa_pipeline_interface (void);
168 static int ia64_first_cycle_multipass_dfa_lookahead (void);
169 static void ia64_dependencies_evaluation_hook (rtx
, rtx
);
170 static void ia64_init_dfa_pre_cycle_insn (void);
171 static rtx
ia64_dfa_pre_cycle_insn (void);
172 static int ia64_first_cycle_multipass_dfa_lookahead_guard (rtx
);
173 static int ia64_dfa_new_cycle (FILE *, int, rtx
, int, int, int *);
174 static rtx
gen_tls_get_addr (void);
175 static rtx
gen_thread_pointer (void);
176 static rtx
ia64_expand_tls_address (enum tls_model
, rtx
, rtx
);
177 static int find_gr_spill (int);
178 static int next_scratch_gr_reg (void);
179 static void mark_reg_gr_used_mask (rtx
, void *);
180 static void ia64_compute_frame_size (HOST_WIDE_INT
);
181 static void setup_spill_pointers (int, rtx
, HOST_WIDE_INT
);
182 static void finish_spill_pointers (void);
183 static rtx
spill_restore_mem (rtx
, HOST_WIDE_INT
);
184 static void do_spill (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
, rtx
);
185 static void do_restore (rtx (*)(rtx
, rtx
, rtx
), rtx
, HOST_WIDE_INT
);
186 static rtx
gen_movdi_x (rtx
, rtx
, rtx
);
187 static rtx
gen_fr_spill_x (rtx
, rtx
, rtx
);
188 static rtx
gen_fr_restore_x (rtx
, rtx
, rtx
);
190 static enum machine_mode
hfa_element_mode (tree
, int);
191 static void ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*, enum machine_mode
,
193 static bool ia64_function_ok_for_sibcall (tree
, tree
);
194 static bool ia64_return_in_memory (tree
, tree
);
195 static bool ia64_rtx_costs (rtx
, int, int, int *);
196 static void fix_range (const char *);
197 static struct machine_function
* ia64_init_machine_status (void);
198 static void emit_insn_group_barriers (FILE *);
199 static void emit_all_insn_group_barriers (FILE *);
200 static void final_emit_insn_group_barriers (FILE *);
201 static void emit_predicate_relation_info (void);
202 static void ia64_reorg (void);
203 static bool ia64_in_small_data_p (tree
);
204 static void process_epilogue (void);
205 static int process_set (FILE *, rtx
);
207 static rtx
ia64_expand_fetch_and_op (optab
, enum machine_mode
, tree
, rtx
);
208 static rtx
ia64_expand_op_and_fetch (optab
, enum machine_mode
, tree
, rtx
);
209 static rtx
ia64_expand_compare_and_swap (enum machine_mode
, enum machine_mode
,
211 static rtx
ia64_expand_lock_test_and_set (enum machine_mode
, tree
, rtx
);
212 static rtx
ia64_expand_lock_release (enum machine_mode
, tree
, rtx
);
213 static bool ia64_assemble_integer (rtx
, unsigned int, int);
214 static void ia64_output_function_prologue (FILE *, HOST_WIDE_INT
);
215 static void ia64_output_function_epilogue (FILE *, HOST_WIDE_INT
);
216 static void ia64_output_function_end_prologue (FILE *);
218 static int ia64_issue_rate (void);
219 static int ia64_adjust_cost (rtx
, rtx
, rtx
, int);
220 static void ia64_sched_init (FILE *, int, int);
221 static void ia64_sched_finish (FILE *, int);
222 static int ia64_dfa_sched_reorder (FILE *, int, rtx
*, int *, int, int);
223 static int ia64_sched_reorder (FILE *, int, rtx
*, int *, int);
224 static int ia64_sched_reorder2 (FILE *, int, rtx
*, int *, int);
225 static int ia64_variable_issue (FILE *, int, rtx
, int);
227 static struct bundle_state
*get_free_bundle_state (void);
228 static void free_bundle_state (struct bundle_state
*);
229 static void initiate_bundle_states (void);
230 static void finish_bundle_states (void);
231 static unsigned bundle_state_hash (const void *);
232 static int bundle_state_eq_p (const void *, const void *);
233 static int insert_bundle_state (struct bundle_state
*);
234 static void initiate_bundle_state_table (void);
235 static void finish_bundle_state_table (void);
236 static int try_issue_nops (struct bundle_state
*, int);
237 static int try_issue_insn (struct bundle_state
*, rtx
);
238 static void issue_nops_and_insn (struct bundle_state
*, int, rtx
, int, int);
239 static int get_max_pos (state_t
);
240 static int get_template (state_t
, int);
242 static rtx
get_next_important_insn (rtx
, rtx
);
243 static void bundling (FILE *, int, rtx
, rtx
);
245 static void ia64_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
246 HOST_WIDE_INT
, tree
);
247 static void ia64_file_start (void);
249 static void ia64_select_rtx_section (enum machine_mode
, rtx
,
250 unsigned HOST_WIDE_INT
);
251 static void ia64_rwreloc_select_section (tree
, int, unsigned HOST_WIDE_INT
)
253 static void ia64_rwreloc_unique_section (tree
, int)
255 static void ia64_rwreloc_select_rtx_section (enum machine_mode
, rtx
,
256 unsigned HOST_WIDE_INT
)
258 static unsigned int ia64_rwreloc_section_type_flags (tree
, const char *, int)
261 static void ia64_hpux_add_extern_decl (tree decl
)
263 static void ia64_hpux_file_end (void)
265 static void ia64_init_libfuncs (void)
267 static void ia64_hpux_init_libfuncs (void)
269 static void ia64_sysv4_init_libfuncs (void)
271 static void ia64_vms_init_libfuncs (void)
274 static tree
ia64_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
275 static void ia64_encode_section_info (tree
, rtx
, int);
276 static rtx
ia64_struct_value_rtx (tree
, int);
277 static tree
ia64_gimplify_va_arg (tree
, tree
, tree
*, tree
*);
280 /* Table of valid machine attributes. */
281 static const struct attribute_spec ia64_attribute_table
[] =
283 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
284 { "syscall_linkage", 0, 0, false, true, true, NULL
},
285 { "model", 1, 1, true, false, false, ia64_handle_model_attribute
},
286 { NULL
, 0, 0, false, false, false, NULL
}
289 /* Initialize the GCC target structure. */
290 #undef TARGET_ATTRIBUTE_TABLE
291 #define TARGET_ATTRIBUTE_TABLE ia64_attribute_table
293 #undef TARGET_INIT_BUILTINS
294 #define TARGET_INIT_BUILTINS ia64_init_builtins
296 #undef TARGET_EXPAND_BUILTIN
297 #define TARGET_EXPAND_BUILTIN ia64_expand_builtin
299 #undef TARGET_ASM_BYTE_OP
300 #define TARGET_ASM_BYTE_OP "\tdata1\t"
301 #undef TARGET_ASM_ALIGNED_HI_OP
302 #define TARGET_ASM_ALIGNED_HI_OP "\tdata2\t"
303 #undef TARGET_ASM_ALIGNED_SI_OP
304 #define TARGET_ASM_ALIGNED_SI_OP "\tdata4\t"
305 #undef TARGET_ASM_ALIGNED_DI_OP
306 #define TARGET_ASM_ALIGNED_DI_OP "\tdata8\t"
307 #undef TARGET_ASM_UNALIGNED_HI_OP
308 #define TARGET_ASM_UNALIGNED_HI_OP "\tdata2.ua\t"
309 #undef TARGET_ASM_UNALIGNED_SI_OP
310 #define TARGET_ASM_UNALIGNED_SI_OP "\tdata4.ua\t"
311 #undef TARGET_ASM_UNALIGNED_DI_OP
312 #define TARGET_ASM_UNALIGNED_DI_OP "\tdata8.ua\t"
313 #undef TARGET_ASM_INTEGER
314 #define TARGET_ASM_INTEGER ia64_assemble_integer
316 #undef TARGET_ASM_FUNCTION_PROLOGUE
317 #define TARGET_ASM_FUNCTION_PROLOGUE ia64_output_function_prologue
318 #undef TARGET_ASM_FUNCTION_END_PROLOGUE
319 #define TARGET_ASM_FUNCTION_END_PROLOGUE ia64_output_function_end_prologue
320 #undef TARGET_ASM_FUNCTION_EPILOGUE
321 #define TARGET_ASM_FUNCTION_EPILOGUE ia64_output_function_epilogue
323 #undef TARGET_IN_SMALL_DATA_P
324 #define TARGET_IN_SMALL_DATA_P ia64_in_small_data_p
326 #undef TARGET_SCHED_ADJUST_COST
327 #define TARGET_SCHED_ADJUST_COST ia64_adjust_cost
328 #undef TARGET_SCHED_ISSUE_RATE
329 #define TARGET_SCHED_ISSUE_RATE ia64_issue_rate
330 #undef TARGET_SCHED_VARIABLE_ISSUE
331 #define TARGET_SCHED_VARIABLE_ISSUE ia64_variable_issue
332 #undef TARGET_SCHED_INIT
333 #define TARGET_SCHED_INIT ia64_sched_init
334 #undef TARGET_SCHED_FINISH
335 #define TARGET_SCHED_FINISH ia64_sched_finish
336 #undef TARGET_SCHED_REORDER
337 #define TARGET_SCHED_REORDER ia64_sched_reorder
338 #undef TARGET_SCHED_REORDER2
339 #define TARGET_SCHED_REORDER2 ia64_sched_reorder2
341 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
342 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ia64_dependencies_evaluation_hook
344 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
345 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE ia64_use_dfa_pipeline_interface
347 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
348 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD ia64_first_cycle_multipass_dfa_lookahead
350 #undef TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN
351 #define TARGET_SCHED_INIT_DFA_PRE_CYCLE_INSN ia64_init_dfa_pre_cycle_insn
352 #undef TARGET_SCHED_DFA_PRE_CYCLE_INSN
353 #define TARGET_SCHED_DFA_PRE_CYCLE_INSN ia64_dfa_pre_cycle_insn
355 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
356 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD\
357 ia64_first_cycle_multipass_dfa_lookahead_guard
359 #undef TARGET_SCHED_DFA_NEW_CYCLE
360 #define TARGET_SCHED_DFA_NEW_CYCLE ia64_dfa_new_cycle
362 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
363 #define TARGET_FUNCTION_OK_FOR_SIBCALL ia64_function_ok_for_sibcall
365 #undef TARGET_ASM_OUTPUT_MI_THUNK
366 #define TARGET_ASM_OUTPUT_MI_THUNK ia64_output_mi_thunk
367 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
368 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
370 #undef TARGET_ASM_FILE_START
371 #define TARGET_ASM_FILE_START ia64_file_start
373 #undef TARGET_RTX_COSTS
374 #define TARGET_RTX_COSTS ia64_rtx_costs
375 #undef TARGET_ADDRESS_COST
376 #define TARGET_ADDRESS_COST hook_int_rtx_0
378 #undef TARGET_MACHINE_DEPENDENT_REORG
379 #define TARGET_MACHINE_DEPENDENT_REORG ia64_reorg
381 #undef TARGET_ENCODE_SECTION_INFO
382 #define TARGET_ENCODE_SECTION_INFO ia64_encode_section_info
384 /* ??? ABI doesn't allow us to define this. */
386 #undef TARGET_PROMOTE_FUNCTION_ARGS
387 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
390 /* ??? ABI doesn't allow us to define this. */
392 #undef TARGET_PROMOTE_FUNCTION_RETURN
393 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
396 /* ??? Investigate. */
398 #undef TARGET_PROMOTE_PROTOTYPES
399 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
402 #undef TARGET_STRUCT_VALUE_RTX
403 #define TARGET_STRUCT_VALUE_RTX ia64_struct_value_rtx
404 #undef TARGET_RETURN_IN_MEMORY
405 #define TARGET_RETURN_IN_MEMORY ia64_return_in_memory
407 #undef TARGET_SETUP_INCOMING_VARARGS
408 #define TARGET_SETUP_INCOMING_VARARGS ia64_setup_incoming_varargs
409 #undef TARGET_STRICT_ARGUMENT_NAMING
410 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
412 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
413 #define TARGET_GIMPLIFY_VA_ARG_EXPR ia64_gimplify_va_arg
415 struct gcc_target targetm
= TARGET_INITIALIZER
;
417 /* Return 1 if OP is a valid operand for the MEM of a CALL insn. */
420 call_operand (rtx op
, enum machine_mode mode
)
422 if (mode
!= GET_MODE (op
) && mode
!= VOIDmode
)
425 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == REG
426 || (GET_CODE (op
) == SUBREG
&& GET_CODE (XEXP (op
, 0)) == REG
));
429 /* Return 1 if OP refers to a symbol in the sdata section. */
432 sdata_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
434 switch (GET_CODE (op
))
437 if (GET_CODE (XEXP (op
, 0)) != PLUS
438 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
)
440 op
= XEXP (XEXP (op
, 0), 0);
444 if (CONSTANT_POOL_ADDRESS_P (op
))
445 return GET_MODE_SIZE (get_pool_mode (op
)) <= ia64_section_threshold
;
447 return SYMBOL_REF_LOCAL_P (op
) && SYMBOL_REF_SMALL_P (op
);
457 small_addr_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
459 return SYMBOL_REF_SMALL_ADDR_P (op
);
462 /* Return 1 if OP refers to a symbol, and is appropriate for a GOT load. */
465 got_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
467 switch (GET_CODE (op
))
471 if (GET_CODE (op
) != PLUS
)
473 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
476 if (GET_CODE (op
) != CONST_INT
)
481 /* Ok if we're not using GOT entries at all. */
482 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
485 /* "Ok" while emitting rtl, since otherwise we won't be provided
486 with the entire offset during emission, which makes it very
487 hard to split the offset into high and low parts. */
488 if (rtx_equal_function_value_matters
)
491 /* Force the low 14 bits of the constant to zero so that we do not
492 use up so many GOT entries. */
493 return (INTVAL (op
) & 0x3fff) == 0;
496 if (SYMBOL_REF_SMALL_ADDR_P (op
))
507 /* Return 1 if OP refers to a symbol. */
510 symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
512 switch (GET_CODE (op
))
525 /* Return tls_model if OP refers to a TLS symbol. */
528 tls_symbolic_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
530 if (GET_CODE (op
) != SYMBOL_REF
)
532 return SYMBOL_REF_TLS_MODEL (op
);
536 /* Return 1 if OP refers to a function. */
539 function_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
541 if (GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (op
))
547 /* Return 1 if OP is setjmp or a similar function. */
549 /* ??? This is an unsatisfying solution. Should rethink. */
552 setjmp_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
557 if (GET_CODE (op
) != SYMBOL_REF
)
562 /* The following code is borrowed from special_function_p in calls.c. */
564 /* Disregard prefix _, __ or __x. */
567 if (name
[1] == '_' && name
[2] == 'x')
569 else if (name
[1] == '_')
579 && (! strcmp (name
, "setjmp")
580 || ! strcmp (name
, "setjmp_syscall")))
582 && ! strcmp (name
, "sigsetjmp"))
584 && ! strcmp (name
, "savectx")));
586 else if ((name
[0] == 'q' && name
[1] == 's'
587 && ! strcmp (name
, "qsetjmp"))
588 || (name
[0] == 'v' && name
[1] == 'f'
589 && ! strcmp (name
, "vfork")))
595 /* Return 1 if OP is a general operand, excluding tls symbolic operands. */
598 move_operand (rtx op
, enum machine_mode mode
)
600 return general_operand (op
, mode
) && !tls_symbolic_operand (op
, mode
);
603 /* Return 1 if OP is a register operand that is (or could be) a GR reg. */
606 gr_register_operand (rtx op
, enum machine_mode mode
)
608 if (! register_operand (op
, mode
))
610 if (GET_CODE (op
) == SUBREG
)
611 op
= SUBREG_REG (op
);
612 if (GET_CODE (op
) == REG
)
614 unsigned int regno
= REGNO (op
);
615 if (regno
< FIRST_PSEUDO_REGISTER
)
616 return GENERAL_REGNO_P (regno
);
621 /* Return 1 if OP is a register operand that is (or could be) an FR reg. */
624 fr_register_operand (rtx op
, enum machine_mode mode
)
626 if (! register_operand (op
, mode
))
628 if (GET_CODE (op
) == SUBREG
)
629 op
= SUBREG_REG (op
);
630 if (GET_CODE (op
) == REG
)
632 unsigned int regno
= REGNO (op
);
633 if (regno
< FIRST_PSEUDO_REGISTER
)
634 return FR_REGNO_P (regno
);
639 /* Return 1 if OP is a register operand that is (or could be) a GR/FR reg. */
642 grfr_register_operand (rtx op
, enum machine_mode mode
)
644 if (! register_operand (op
, mode
))
646 if (GET_CODE (op
) == SUBREG
)
647 op
= SUBREG_REG (op
);
648 if (GET_CODE (op
) == REG
)
650 unsigned int regno
= REGNO (op
);
651 if (regno
< FIRST_PSEUDO_REGISTER
)
652 return GENERAL_REGNO_P (regno
) || FR_REGNO_P (regno
);
657 /* Return 1 if OP is a nonimmediate operand that is (or could be) a GR reg. */
660 gr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
662 if (! nonimmediate_operand (op
, mode
))
664 if (GET_CODE (op
) == SUBREG
)
665 op
= SUBREG_REG (op
);
666 if (GET_CODE (op
) == REG
)
668 unsigned int regno
= REGNO (op
);
669 if (regno
< FIRST_PSEUDO_REGISTER
)
670 return GENERAL_REGNO_P (regno
);
675 /* Return 1 if OP is a nonimmediate operand that is (or could be) a FR reg. */
678 fr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
680 if (! nonimmediate_operand (op
, mode
))
682 if (GET_CODE (op
) == SUBREG
)
683 op
= SUBREG_REG (op
);
684 if (GET_CODE (op
) == REG
)
686 unsigned int regno
= REGNO (op
);
687 if (regno
< FIRST_PSEUDO_REGISTER
)
688 return FR_REGNO_P (regno
);
693 /* Return 1 if OP is a nonimmediate operand that is a GR/FR reg. */
696 grfr_nonimmediate_operand (rtx op
, enum machine_mode mode
)
698 if (! nonimmediate_operand (op
, mode
))
700 if (GET_CODE (op
) == SUBREG
)
701 op
= SUBREG_REG (op
);
702 if (GET_CODE (op
) == REG
)
704 unsigned int regno
= REGNO (op
);
705 if (regno
< FIRST_PSEUDO_REGISTER
)
706 return GENERAL_REGNO_P (regno
) || FR_REGNO_P (regno
);
711 /* Return 1 if OP is a GR register operand, or zero. */
714 gr_reg_or_0_operand (rtx op
, enum machine_mode mode
)
716 return (op
== const0_rtx
|| gr_register_operand (op
, mode
));
719 /* Return 1 if OP is a GR register operand, or a 5 bit immediate operand. */
722 gr_reg_or_5bit_operand (rtx op
, enum machine_mode mode
)
724 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0 && INTVAL (op
) < 32)
725 || gr_register_operand (op
, mode
));
728 /* Return 1 if OP is a GR register operand, or a 6 bit immediate operand. */
731 gr_reg_or_6bit_operand (rtx op
, enum machine_mode mode
)
733 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)))
734 || gr_register_operand (op
, mode
));
737 /* Return 1 if OP is a GR register operand, or an 8 bit immediate operand. */
740 gr_reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
742 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
743 || gr_register_operand (op
, mode
));
746 /* Return 1 if OP is a GR/FR register operand, or an 8 bit immediate. */
749 grfr_reg_or_8bit_operand (rtx op
, enum machine_mode mode
)
751 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
)))
752 || grfr_register_operand (op
, mode
));
755 /* Return 1 if OP is a register operand, or an 8 bit adjusted immediate
759 gr_reg_or_8bit_adjusted_operand (rtx op
, enum machine_mode mode
)
761 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
762 || gr_register_operand (op
, mode
));
765 /* Return 1 if OP is a register operand, or is valid for both an 8 bit
766 immediate and an 8 bit adjusted immediate operand. This is necessary
767 because when we emit a compare, we don't know what the condition will be,
768 so we need the union of the immediates accepted by GT and LT. */
771 gr_reg_or_8bit_and_adjusted_operand (rtx op
, enum machine_mode mode
)
773 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_K (INTVAL (op
))
774 && CONST_OK_FOR_L (INTVAL (op
)))
775 || gr_register_operand (op
, mode
));
778 /* Return 1 if OP is a register operand, or a 14 bit immediate operand. */
781 gr_reg_or_14bit_operand (rtx op
, enum machine_mode mode
)
783 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
784 || gr_register_operand (op
, mode
));
787 /* Return 1 if OP is a register operand, or a 22 bit immediate operand. */
790 gr_reg_or_22bit_operand (rtx op
, enum machine_mode mode
)
792 return ((GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_J (INTVAL (op
)))
793 || gr_register_operand (op
, mode
));
796 /* Return 1 if OP is a 6 bit immediate operand. */
799 shift_count_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
801 return (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (INTVAL (op
)));
804 /* Return 1 if OP is a 5 bit immediate operand. */
807 shift_32bit_count_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
809 return (GET_CODE (op
) == CONST_INT
810 && (INTVAL (op
) >= 0 && INTVAL (op
) < 32));
813 /* Return 1 if OP is a 2, 4, 8, or 16 immediate operand. */
816 shladd_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
818 return (GET_CODE (op
) == CONST_INT
819 && (INTVAL (op
) == 2 || INTVAL (op
) == 4
820 || INTVAL (op
) == 8 || INTVAL (op
) == 16));
823 /* Return 1 if OP is a -16, -8, -4, -1, 1, 4, 8, or 16 immediate operand. */
826 fetchadd_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
828 return (GET_CODE (op
) == CONST_INT
829 && (INTVAL (op
) == -16 || INTVAL (op
) == -8 ||
830 INTVAL (op
) == -4 || INTVAL (op
) == -1 ||
831 INTVAL (op
) == 1 || INTVAL (op
) == 4 ||
832 INTVAL (op
) == 8 || INTVAL (op
) == 16));
835 /* Return 1 if OP is a floating-point constant zero, one, or a register. */
838 fr_reg_or_fp01_operand (rtx op
, enum machine_mode mode
)
840 return ((GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (op
))
841 || fr_register_operand (op
, mode
));
844 /* Like nonimmediate_operand, but don't allow MEMs that try to use a
845 POST_MODIFY with a REG as displacement. */
848 destination_operand (rtx op
, enum machine_mode mode
)
850 if (! nonimmediate_operand (op
, mode
))
852 if (GET_CODE (op
) == MEM
853 && GET_CODE (XEXP (op
, 0)) == POST_MODIFY
854 && GET_CODE (XEXP (XEXP (XEXP (op
, 0), 1), 1)) == REG
)
859 /* Like memory_operand, but don't allow post-increments. */
862 not_postinc_memory_operand (rtx op
, enum machine_mode mode
)
864 return (memory_operand (op
, mode
)
865 && GET_RTX_CLASS (GET_CODE (XEXP (op
, 0))) != RTX_AUTOINC
);
868 /* Return 1 if this is a comparison operator, which accepts a normal 8-bit
869 signed immediate operand. */
872 normal_comparison_operator (register rtx op
, enum machine_mode mode
)
874 enum rtx_code code
= GET_CODE (op
);
875 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
876 && (code
== EQ
|| code
== NE
877 || code
== GT
|| code
== LE
|| code
== GTU
|| code
== LEU
));
880 /* Return 1 if this is a comparison operator, which accepts an adjusted 8-bit
881 signed immediate operand. */
884 adjusted_comparison_operator (register rtx op
, enum machine_mode mode
)
886 enum rtx_code code
= GET_CODE (op
);
887 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
888 && (code
== LT
|| code
== GE
|| code
== LTU
|| code
== GEU
));
891 /* Return 1 if this is a signed inequality operator. */
894 signed_inequality_operator (register rtx op
, enum machine_mode mode
)
896 enum rtx_code code
= GET_CODE (op
);
897 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
898 && (code
== GE
|| code
== GT
899 || code
== LE
|| code
== LT
));
902 /* Return 1 if this operator is valid for predication. */
905 predicate_operator (register rtx op
, enum machine_mode mode
)
907 enum rtx_code code
= GET_CODE (op
);
908 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
909 && (code
== EQ
|| code
== NE
));
912 /* Return 1 if this operator can be used in a conditional operation. */
915 condop_operator (register rtx op
, enum machine_mode mode
)
917 enum rtx_code code
= GET_CODE (op
);
918 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
919 && (code
== PLUS
|| code
== MINUS
|| code
== AND
920 || code
== IOR
|| code
== XOR
));
923 /* Return 1 if this is the ar.lc register. */
926 ar_lc_reg_operand (register rtx op
, enum machine_mode mode
)
928 return (GET_MODE (op
) == DImode
929 && (mode
== DImode
|| mode
== VOIDmode
)
930 && GET_CODE (op
) == REG
931 && REGNO (op
) == AR_LC_REGNUM
);
934 /* Return 1 if this is the ar.ccv register. */
937 ar_ccv_reg_operand (register rtx op
, enum machine_mode mode
)
939 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
940 && GET_CODE (op
) == REG
941 && REGNO (op
) == AR_CCV_REGNUM
);
944 /* Return 1 if this is the ar.pfs register. */
947 ar_pfs_reg_operand (register rtx op
, enum machine_mode mode
)
949 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
950 && GET_CODE (op
) == REG
951 && REGNO (op
) == AR_PFS_REGNUM
);
954 /* Like general_operand, but don't allow (mem (addressof)). */
957 general_xfmode_operand (rtx op
, enum machine_mode mode
)
959 if (! general_operand (op
, mode
))
961 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
969 destination_xfmode_operand (rtx op
, enum machine_mode mode
)
971 if (! destination_operand (op
, mode
))
973 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == ADDRESSOF
)
981 xfreg_or_fp01_operand (rtx op
, enum machine_mode mode
)
983 if (GET_CODE (op
) == SUBREG
)
985 return fr_reg_or_fp01_operand (op
, mode
);
988 /* Return 1 if OP is valid as a base register in a reg + offset address. */
991 basereg_operand (rtx op
, enum machine_mode mode
)
993 /* ??? Should I copy the flag_omit_frame_pointer and cse_not_expected
994 checks from pa.c basereg_operand as well? Seems to be OK without them
997 return (register_operand (op
, mode
) &&
998 REG_POINTER ((GET_CODE (op
) == SUBREG
) ? SUBREG_REG (op
) : op
));
1003 ADDR_AREA_NORMAL
, /* normal address area */
1004 ADDR_AREA_SMALL
/* addressable by "addl" (-2MB < addr < 2MB) */
1008 static GTY(()) tree small_ident1
;
1009 static GTY(()) tree small_ident2
;
1014 if (small_ident1
== 0)
1016 small_ident1
= get_identifier ("small");
1017 small_ident2
= get_identifier ("__small__");
1021 /* Retrieve the address area that has been chosen for the given decl. */
1023 static ia64_addr_area
1024 ia64_get_addr_area (tree decl
)
1028 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
1034 id
= TREE_VALUE (TREE_VALUE (model_attr
));
1035 if (id
== small_ident1
|| id
== small_ident2
)
1036 return ADDR_AREA_SMALL
;
1038 return ADDR_AREA_NORMAL
;
1042 ia64_handle_model_attribute (tree
*node
, tree name
, tree args
, int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
1044 ia64_addr_area addr_area
= ADDR_AREA_NORMAL
;
1045 ia64_addr_area area
;
1046 tree arg
, decl
= *node
;
1049 arg
= TREE_VALUE (args
);
1050 if (arg
== small_ident1
|| arg
== small_ident2
)
1052 addr_area
= ADDR_AREA_SMALL
;
1056 warning ("invalid argument of `%s' attribute",
1057 IDENTIFIER_POINTER (name
));
1058 *no_add_attrs
= true;
1061 switch (TREE_CODE (decl
))
1064 if ((DECL_CONTEXT (decl
) && TREE_CODE (DECL_CONTEXT (decl
))
1066 && !TREE_STATIC (decl
))
1068 error ("%Jan address area attribute cannot be specified for "
1069 "local variables", decl
, decl
);
1070 *no_add_attrs
= true;
1072 area
= ia64_get_addr_area (decl
);
1073 if (area
!= ADDR_AREA_NORMAL
&& addr_area
!= area
)
1075 error ("%Jaddress area of '%s' conflicts with previous "
1076 "declaration", decl
, decl
);
1077 *no_add_attrs
= true;
1082 error ("%Jaddress area attribute cannot be specified for functions",
1084 *no_add_attrs
= true;
1088 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
1089 *no_add_attrs
= true;
1097 ia64_encode_addr_area (tree decl
, rtx symbol
)
1101 flags
= SYMBOL_REF_FLAGS (symbol
);
1102 switch (ia64_get_addr_area (decl
))
1104 case ADDR_AREA_NORMAL
: break;
1105 case ADDR_AREA_SMALL
: flags
|= SYMBOL_FLAG_SMALL_ADDR
; break;
1108 SYMBOL_REF_FLAGS (symbol
) = flags
;
1112 ia64_encode_section_info (tree decl
, rtx rtl
, int first
)
1114 default_encode_section_info (decl
, rtl
, first
);
1116 /* Careful not to prod global register variables. */
1117 if (TREE_CODE (decl
) == VAR_DECL
1118 && GET_CODE (DECL_RTL (decl
)) == MEM
1119 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == SYMBOL_REF
1120 && (TREE_STATIC (decl
) || DECL_EXTERNAL (decl
)))
1121 ia64_encode_addr_area (decl
, XEXP (rtl
, 0));
1124 /* Return 1 if the operands of a move are ok. */
1127 ia64_move_ok (rtx dst
, rtx src
)
1129 /* If we're under init_recog_no_volatile, we'll not be able to use
1130 memory_operand. So check the code directly and don't worry about
1131 the validity of the underlying address, which should have been
1132 checked elsewhere anyway. */
1133 if (GET_CODE (dst
) != MEM
)
1135 if (GET_CODE (src
) == MEM
)
1137 if (register_operand (src
, VOIDmode
))
1140 /* Otherwise, this must be a constant, and that either 0 or 0.0 or 1.0. */
1141 if (INTEGRAL_MODE_P (GET_MODE (dst
)))
1142 return src
== const0_rtx
;
1144 return GET_CODE (src
) == CONST_DOUBLE
&& CONST_DOUBLE_OK_FOR_G (src
);
1148 addp4_optimize_ok (rtx op1
, rtx op2
)
1150 return (basereg_operand (op1
, GET_MODE(op1
)) !=
1151 basereg_operand (op2
, GET_MODE(op2
)));
1154 /* Check if OP is a mask suitable for use with SHIFT in a dep.z instruction.
1155 Return the length of the field, or <= 0 on failure. */
1158 ia64_depz_field_mask (rtx rop
, rtx rshift
)
1160 unsigned HOST_WIDE_INT op
= INTVAL (rop
);
1161 unsigned HOST_WIDE_INT shift
= INTVAL (rshift
);
1163 /* Get rid of the zero bits we're shifting in. */
1166 /* We must now have a solid block of 1's at bit 0. */
1167 return exact_log2 (op
+ 1);
1170 /* Expand a symbolic constant load. */
1173 ia64_expand_load_address (rtx dest
, rtx src
)
1175 if (tls_symbolic_operand (src
, VOIDmode
))
1177 if (GET_CODE (dest
) != REG
)
1180 /* ILP32 mode still loads 64-bits of data from the GOT. This avoids
1181 having to pointer-extend the value afterward. Other forms of address
1182 computation below are also more natural to compute as 64-bit quantities.
1183 If we've been given an SImode destination register, change it. */
1184 if (GET_MODE (dest
) != Pmode
)
1185 dest
= gen_rtx_REG (Pmode
, REGNO (dest
));
1187 if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_ADDR_P (src
))
1189 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
1192 else if (TARGET_AUTO_PIC
)
1194 emit_insn (gen_load_gprel64 (dest
, src
));
1197 else if (GET_CODE (src
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (src
))
1199 emit_insn (gen_load_fptr (dest
, src
));
1202 else if (sdata_symbolic_operand (src
, VOIDmode
))
1204 emit_insn (gen_load_gprel (dest
, src
));
1208 if (GET_CODE (src
) == CONST
1209 && GET_CODE (XEXP (src
, 0)) == PLUS
1210 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
1211 && (INTVAL (XEXP (XEXP (src
, 0), 1)) & 0x1fff) != 0)
1213 rtx sym
= XEXP (XEXP (src
, 0), 0);
1214 HOST_WIDE_INT ofs
, hi
, lo
;
1216 /* Split the offset into a sign extended 14-bit low part
1217 and a complementary high part. */
1218 ofs
= INTVAL (XEXP (XEXP (src
, 0), 1));
1219 lo
= ((ofs
& 0x3fff) ^ 0x2000) - 0x2000;
1222 ia64_expand_load_address (dest
, plus_constant (sym
, hi
));
1223 emit_insn (gen_adddi3 (dest
, dest
, GEN_INT (lo
)));
1229 tmp
= gen_rtx_HIGH (Pmode
, src
);
1230 tmp
= gen_rtx_PLUS (Pmode
, tmp
, pic_offset_table_rtx
);
1231 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1233 tmp
= gen_rtx_LO_SUM (GET_MODE (dest
), dest
, src
);
1234 emit_insn (gen_rtx_SET (VOIDmode
, dest
, tmp
));
1238 static GTY(()) rtx gen_tls_tga
;
1240 gen_tls_get_addr (void)
1243 gen_tls_tga
= init_one_libfunc ("__tls_get_addr");
1247 static GTY(()) rtx thread_pointer_rtx
;
1249 gen_thread_pointer (void)
1251 if (!thread_pointer_rtx
)
1253 thread_pointer_rtx
= gen_rtx_REG (Pmode
, 13);
1254 RTX_UNCHANGING_P (thread_pointer_rtx
) = 1;
1256 return thread_pointer_rtx
;
1260 ia64_expand_tls_address (enum tls_model tls_kind
, rtx op0
, rtx op1
)
1262 rtx tga_op1
, tga_op2
, tga_ret
, tga_eqv
, tmp
, insns
;
1267 case TLS_MODEL_GLOBAL_DYNAMIC
:
1270 tga_op1
= gen_reg_rtx (Pmode
);
1271 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
1272 tga_op1
= gen_rtx_MEM (Pmode
, tga_op1
);
1273 RTX_UNCHANGING_P (tga_op1
) = 1;
1275 tga_op2
= gen_reg_rtx (Pmode
);
1276 emit_insn (gen_load_ltoff_dtprel (tga_op2
, op1
));
1277 tga_op2
= gen_rtx_MEM (Pmode
, tga_op2
);
1278 RTX_UNCHANGING_P (tga_op2
) = 1;
1280 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1281 LCT_CONST
, Pmode
, 2, tga_op1
,
1282 Pmode
, tga_op2
, Pmode
);
1284 insns
= get_insns ();
1287 if (GET_MODE (op0
) != Pmode
)
1289 emit_libcall_block (insns
, op0
, tga_ret
, op1
);
1292 case TLS_MODEL_LOCAL_DYNAMIC
:
1293 /* ??? This isn't the completely proper way to do local-dynamic
1294 If the call to __tls_get_addr is used only by a single symbol,
1295 then we should (somehow) move the dtprel to the second arg
1296 to avoid the extra add. */
1299 tga_op1
= gen_reg_rtx (Pmode
);
1300 emit_insn (gen_load_ltoff_dtpmod (tga_op1
, op1
));
1301 tga_op1
= gen_rtx_MEM (Pmode
, tga_op1
);
1302 RTX_UNCHANGING_P (tga_op1
) = 1;
1304 tga_op2
= const0_rtx
;
1306 tga_ret
= emit_library_call_value (gen_tls_get_addr (), NULL_RTX
,
1307 LCT_CONST
, Pmode
, 2, tga_op1
,
1308 Pmode
, tga_op2
, Pmode
);
1310 insns
= get_insns ();
1313 tga_eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
1315 tmp
= gen_reg_rtx (Pmode
);
1316 emit_libcall_block (insns
, tmp
, tga_ret
, tga_eqv
);
1318 if (!register_operand (op0
, Pmode
))
1319 op0
= gen_reg_rtx (Pmode
);
1322 emit_insn (gen_load_dtprel (op0
, op1
));
1323 emit_insn (gen_adddi3 (op0
, tmp
, op0
));
1326 emit_insn (gen_add_dtprel (op0
, tmp
, op1
));
1329 case TLS_MODEL_INITIAL_EXEC
:
1330 tmp
= gen_reg_rtx (Pmode
);
1331 emit_insn (gen_load_ltoff_tprel (tmp
, op1
));
1332 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1333 RTX_UNCHANGING_P (tmp
) = 1;
1334 tmp
= force_reg (Pmode
, tmp
);
1336 if (!register_operand (op0
, Pmode
))
1337 op0
= gen_reg_rtx (Pmode
);
1338 emit_insn (gen_adddi3 (op0
, tmp
, gen_thread_pointer ()));
1341 case TLS_MODEL_LOCAL_EXEC
:
1342 if (!register_operand (op0
, Pmode
))
1343 op0
= gen_reg_rtx (Pmode
);
1346 emit_insn (gen_load_tprel (op0
, op1
));
1347 emit_insn (gen_adddi3 (op0
, gen_thread_pointer (), op0
));
1350 emit_insn (gen_add_tprel (op0
, gen_thread_pointer (), op1
));
1357 if (orig_op0
== op0
)
1359 if (GET_MODE (orig_op0
) == Pmode
)
1361 return gen_lowpart (GET_MODE (orig_op0
), op0
);
1365 ia64_expand_move (rtx op0
, rtx op1
)
1367 enum machine_mode mode
= GET_MODE (op0
);
1369 if (!reload_in_progress
&& !reload_completed
&& !ia64_move_ok (op0
, op1
))
1370 op1
= force_reg (mode
, op1
);
1372 if ((mode
== Pmode
|| mode
== ptr_mode
) && symbolic_operand (op1
, VOIDmode
))
1374 enum tls_model tls_kind
;
1375 if ((tls_kind
= tls_symbolic_operand (op1
, VOIDmode
)))
1376 return ia64_expand_tls_address (tls_kind
, op0
, op1
);
1378 if (!TARGET_NO_PIC
&& reload_completed
)
1380 ia64_expand_load_address (op0
, op1
);
1388 /* Split a move from OP1 to OP0 conditional on COND. */
1391 ia64_emit_cond_move (rtx op0
, rtx op1
, rtx cond
)
1393 rtx insn
, first
= get_last_insn ();
1395 emit_move_insn (op0
, op1
);
1397 for (insn
= get_last_insn (); insn
!= first
; insn
= PREV_INSN (insn
))
1399 PATTERN (insn
) = gen_rtx_COND_EXEC (VOIDmode
, copy_rtx (cond
),
1403 /* Split a post-reload TImode or TFmode reference into two DImode
1404 components. This is made extra difficult by the fact that we do
1405 not get any scratch registers to work with, because reload cannot
1406 be prevented from giving us a scratch that overlaps the register
1407 pair involved. So instead, when addressing memory, we tweak the
1408 pointer register up and back down with POST_INCs. Or up and not
1409 back down when we can get away with it.
1411 REVERSED is true when the loads must be done in reversed order
1412 (high word first) for correctness. DEAD is true when the pointer
1413 dies with the second insn we generate and therefore the second
1414 address must not carry a postmodify.
1416 May return an insn which is to be emitted after the moves. */
1419 ia64_split_tmode (rtx out
[2], rtx in
, bool reversed
, bool dead
)
1423 switch (GET_CODE (in
))
1426 out
[reversed
] = gen_rtx_REG (DImode
, REGNO (in
));
1427 out
[!reversed
] = gen_rtx_REG (DImode
, REGNO (in
) + 1);
1432 /* Cannot occur reversed. */
1433 if (reversed
) abort ();
1435 if (GET_MODE (in
) != TFmode
)
1436 split_double (in
, &out
[0], &out
[1]);
1438 /* split_double does not understand how to split a TFmode
1439 quantity into a pair of DImode constants. */
1442 unsigned HOST_WIDE_INT p
[2];
1443 long l
[4]; /* TFmode is 128 bits */
1445 REAL_VALUE_FROM_CONST_DOUBLE (r
, in
);
1446 real_to_target (l
, &r
, TFmode
);
1448 if (FLOAT_WORDS_BIG_ENDIAN
)
1450 p
[0] = (((unsigned HOST_WIDE_INT
) l
[0]) << 32) + l
[1];
1451 p
[1] = (((unsigned HOST_WIDE_INT
) l
[2]) << 32) + l
[3];
1455 p
[0] = (((unsigned HOST_WIDE_INT
) l
[3]) << 32) + l
[2];
1456 p
[1] = (((unsigned HOST_WIDE_INT
) l
[1]) << 32) + l
[0];
1458 out
[0] = GEN_INT (p
[0]);
1459 out
[1] = GEN_INT (p
[1]);
1465 rtx base
= XEXP (in
, 0);
1468 switch (GET_CODE (base
))
1473 out
[0] = adjust_automodify_address
1474 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1475 out
[1] = adjust_automodify_address
1476 (in
, DImode
, dead
? 0 : gen_rtx_POST_DEC (Pmode
, base
), 8);
1480 /* Reversal requires a pre-increment, which can only
1481 be done as a separate insn. */
1482 emit_insn (gen_adddi3 (base
, base
, GEN_INT (8)));
1483 out
[0] = adjust_automodify_address
1484 (in
, DImode
, gen_rtx_POST_DEC (Pmode
, base
), 8);
1485 out
[1] = adjust_address (in
, DImode
, 0);
1490 if (reversed
|| dead
) abort ();
1491 /* Just do the increment in two steps. */
1492 out
[0] = adjust_automodify_address (in
, DImode
, 0, 0);
1493 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1497 if (reversed
|| dead
) abort ();
1498 /* Add 8, subtract 24. */
1499 base
= XEXP (base
, 0);
1500 out
[0] = adjust_automodify_address
1501 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1502 out
[1] = adjust_automodify_address
1504 gen_rtx_POST_MODIFY (Pmode
, base
, plus_constant (base
, -24)),
1509 if (reversed
|| dead
) abort ();
1510 /* Extract and adjust the modification. This case is
1511 trickier than the others, because we might have an
1512 index register, or we might have a combined offset that
1513 doesn't fit a signed 9-bit displacement field. We can
1514 assume the incoming expression is already legitimate. */
1515 offset
= XEXP (base
, 1);
1516 base
= XEXP (base
, 0);
1518 out
[0] = adjust_automodify_address
1519 (in
, DImode
, gen_rtx_POST_INC (Pmode
, base
), 0);
1521 if (GET_CODE (XEXP (offset
, 1)) == REG
)
1523 /* Can't adjust the postmodify to match. Emit the
1524 original, then a separate addition insn. */
1525 out
[1] = adjust_automodify_address (in
, DImode
, 0, 8);
1526 fixup
= gen_adddi3 (base
, base
, GEN_INT (-8));
1528 else if (GET_CODE (XEXP (offset
, 1)) != CONST_INT
)
1530 else if (INTVAL (XEXP (offset
, 1)) < -256 + 8)
1532 /* Again the postmodify cannot be made to match, but
1533 in this case it's more efficient to get rid of the
1534 postmodify entirely and fix up with an add insn. */
1535 out
[1] = adjust_automodify_address (in
, DImode
, base
, 8);
1536 fixup
= gen_adddi3 (base
, base
,
1537 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8));
1541 /* Combined offset still fits in the displacement field.
1542 (We cannot overflow it at the high end.) */
1543 out
[1] = adjust_automodify_address
1545 gen_rtx_POST_MODIFY (Pmode
, base
,
1546 gen_rtx_PLUS (Pmode
, base
,
1547 GEN_INT (INTVAL (XEXP (offset
, 1)) - 8))),
1565 /* Split a TImode or TFmode move instruction after reload.
1566 This is used by *movtf_internal and *movti_internal. */
1568 ia64_split_tmode_move (rtx operands
[])
1570 rtx in
[2], out
[2], insn
;
1573 bool reversed
= false;
1575 /* It is possible for reload to decide to overwrite a pointer with
1576 the value it points to. In that case we have to do the loads in
1577 the appropriate order so that the pointer is not destroyed too
1578 early. Also we must not generate a postmodify for that second
1579 load, or rws_access_regno will abort. */
1580 if (GET_CODE (operands
[1]) == MEM
1581 && reg_overlap_mentioned_p (operands
[0], operands
[1]))
1583 rtx base
= XEXP (operands
[1], 0);
1584 while (GET_CODE (base
) != REG
)
1585 base
= XEXP (base
, 0);
1587 if (REGNO (base
) == REGNO (operands
[0]))
1591 /* Another reason to do the moves in reversed order is if the first
1592 element of the target register pair is also the second element of
1593 the source register pair. */
1594 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == REG
1595 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
1598 fixup
[0] = ia64_split_tmode (in
, operands
[1], reversed
, dead
);
1599 fixup
[1] = ia64_split_tmode (out
, operands
[0], reversed
, dead
);
1601 #define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
1602 if (GET_CODE (EXP) == MEM \
1603 && (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
1604 || GET_CODE (XEXP (EXP, 0)) == POST_INC \
1605 || GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
1606 REG_NOTES (INSN) = gen_rtx_EXPR_LIST (REG_INC, \
1607 XEXP (XEXP (EXP, 0), 0), \
1610 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[0], in
[0]));
1611 MAYBE_ADD_REG_INC_NOTE (insn
, in
[0]);
1612 MAYBE_ADD_REG_INC_NOTE (insn
, out
[0]);
1614 insn
= emit_insn (gen_rtx_SET (VOIDmode
, out
[1], in
[1]));
1615 MAYBE_ADD_REG_INC_NOTE (insn
, in
[1]);
1616 MAYBE_ADD_REG_INC_NOTE (insn
, out
[1]);
1619 emit_insn (fixup
[0]);
1621 emit_insn (fixup
[1]);
1623 #undef MAYBE_ADD_REG_INC_NOTE
1626 /* ??? Fixing GR->FR XFmode moves during reload is hard. You need to go
1627 through memory plus an extra GR scratch register. Except that you can
1628 either get the first from SECONDARY_MEMORY_NEEDED or the second from
1629 SECONDARY_RELOAD_CLASS, but not both.
1631 We got into problems in the first place by allowing a construct like
1632 (subreg:XF (reg:TI)), which we got from a union containing a long double.
1633 This solution attempts to prevent this situation from occurring. When
1634 we see something like the above, we spill the inner register to memory. */
1637 spill_xfmode_operand (rtx in
, int force
)
1639 if (GET_CODE (in
) == SUBREG
1640 && GET_MODE (SUBREG_REG (in
)) == TImode
1641 && GET_CODE (SUBREG_REG (in
)) == REG
)
1643 rtx memt
= assign_stack_temp (TImode
, 16, 0);
1644 emit_move_insn (memt
, SUBREG_REG (in
));
1645 return adjust_address (memt
, XFmode
, 0);
1647 else if (force
&& GET_CODE (in
) == REG
)
1649 rtx memx
= assign_stack_temp (XFmode
, 16, 0);
1650 emit_move_insn (memx
, in
);
1657 /* Emit comparison instruction if necessary, returning the expression
1658 that holds the compare result in the proper mode. */
1660 static GTY(()) rtx cmptf_libfunc
;
1663 ia64_expand_compare (enum rtx_code code
, enum machine_mode mode
)
1665 rtx op0
= ia64_compare_op0
, op1
= ia64_compare_op1
;
1668 /* If we have a BImode input, then we already have a compare result, and
1669 do not need to emit another comparison. */
1670 if (GET_MODE (op0
) == BImode
)
1672 if ((code
== NE
|| code
== EQ
) && op1
== const0_rtx
)
1677 /* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
1678 magic number as its third argument, that indicates what to do.
1679 The return value is an integer to be compared against zero. */
1680 else if (GET_MODE (op0
) == TFmode
)
1683 QCMP_INV
= 1, /* Raise FP_INVALID on SNaN as a side effect. */
1689 enum rtx_code ncode
;
1691 if (!cmptf_libfunc
|| GET_MODE (op1
) != TFmode
)
1695 /* 1 = equal, 0 = not equal. Equality operators do
1696 not raise FP_INVALID when given an SNaN operand. */
1697 case EQ
: magic
= QCMP_EQ
; ncode
= NE
; break;
1698 case NE
: magic
= QCMP_EQ
; ncode
= EQ
; break;
1699 /* isunordered() from C99. */
1700 case UNORDERED
: magic
= QCMP_UNORD
; ncode
= NE
; break;
1701 /* Relational operators raise FP_INVALID when given
1703 case LT
: magic
= QCMP_LT
|QCMP_INV
; ncode
= NE
; break;
1704 case LE
: magic
= QCMP_LT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1705 case GT
: magic
= QCMP_GT
|QCMP_INV
; ncode
= NE
; break;
1706 case GE
: magic
= QCMP_GT
|QCMP_EQ
|QCMP_INV
; ncode
= NE
; break;
1707 /* FUTURE: Implement UNEQ, UNLT, UNLE, UNGT, UNGE, LTGT.
1708 Expanders for buneq etc. weuld have to be added to ia64.md
1709 for this to be useful. */
1715 ret
= emit_library_call_value (cmptf_libfunc
, 0, LCT_CONST
, DImode
, 3,
1716 op0
, TFmode
, op1
, TFmode
,
1717 GEN_INT (magic
), DImode
);
1718 cmp
= gen_reg_rtx (BImode
);
1719 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1720 gen_rtx_fmt_ee (ncode
, BImode
,
1723 insns
= get_insns ();
1726 emit_libcall_block (insns
, cmp
, cmp
,
1727 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
));
1732 cmp
= gen_reg_rtx (BImode
);
1733 emit_insn (gen_rtx_SET (VOIDmode
, cmp
,
1734 gen_rtx_fmt_ee (code
, BImode
, op0
, op1
)));
1738 return gen_rtx_fmt_ee (code
, mode
, cmp
, const0_rtx
);
1741 /* Emit the appropriate sequence for a call. */
1744 ia64_expand_call (rtx retval
, rtx addr
, rtx nextarg ATTRIBUTE_UNUSED
,
1749 addr
= XEXP (addr
, 0);
1750 addr
= convert_memory_address (DImode
, addr
);
1751 b0
= gen_rtx_REG (DImode
, R_BR (0));
1753 /* ??? Should do this for functions known to bind local too. */
1754 if (TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
1757 insn
= gen_sibcall_nogp (addr
);
1759 insn
= gen_call_nogp (addr
, b0
);
1761 insn
= gen_call_value_nogp (retval
, addr
, b0
);
1762 insn
= emit_call_insn (insn
);
1767 insn
= gen_sibcall_gp (addr
);
1769 insn
= gen_call_gp (addr
, b0
);
1771 insn
= gen_call_value_gp (retval
, addr
, b0
);
1772 insn
= emit_call_insn (insn
);
1774 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
1778 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), b0
);
1782 ia64_reload_gp (void)
1786 if (current_frame_info
.reg_save_gp
)
1787 tmp
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_gp
);
1790 HOST_WIDE_INT offset
;
1792 offset
= (current_frame_info
.spill_cfa_off
1793 + current_frame_info
.spill_size
);
1794 if (frame_pointer_needed
)
1796 tmp
= hard_frame_pointer_rtx
;
1801 tmp
= stack_pointer_rtx
;
1802 offset
= current_frame_info
.total_size
- offset
;
1805 if (CONST_OK_FOR_I (offset
))
1806 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1807 tmp
, GEN_INT (offset
)));
1810 emit_move_insn (pic_offset_table_rtx
, GEN_INT (offset
));
1811 emit_insn (gen_adddi3 (pic_offset_table_rtx
,
1812 pic_offset_table_rtx
, tmp
));
1815 tmp
= gen_rtx_MEM (DImode
, pic_offset_table_rtx
);
1818 emit_move_insn (pic_offset_table_rtx
, tmp
);
1822 ia64_split_call (rtx retval
, rtx addr
, rtx retaddr
, rtx scratch_r
,
1823 rtx scratch_b
, int noreturn_p
, int sibcall_p
)
1826 bool is_desc
= false;
1828 /* If we find we're calling through a register, then we're actually
1829 calling through a descriptor, so load up the values. */
1830 if (REG_P (addr
) && GR_REGNO_P (REGNO (addr
)))
1835 /* ??? We are currently constrained to *not* use peep2, because
1836 we can legitimately change the global lifetime of the GP
1837 (in the form of killing where previously live). This is
1838 because a call through a descriptor doesn't use the previous
1839 value of the GP, while a direct call does, and we do not
1840 commit to either form until the split here.
1842 That said, this means that we lack precise life info for
1843 whether ADDR is dead after this call. This is not terribly
1844 important, since we can fix things up essentially for free
1845 with the POST_DEC below, but it's nice to not use it when we
1846 can immediately tell it's not necessary. */
1847 addr_dead_p
= ((noreturn_p
|| sibcall_p
1848 || TEST_HARD_REG_BIT (regs_invalidated_by_call
,
1850 && !FUNCTION_ARG_REGNO_P (REGNO (addr
)));
1852 /* Load the code address into scratch_b. */
1853 tmp
= gen_rtx_POST_INC (Pmode
, addr
);
1854 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1855 emit_move_insn (scratch_r
, tmp
);
1856 emit_move_insn (scratch_b
, scratch_r
);
1858 /* Load the GP address. If ADDR is not dead here, then we must
1859 revert the change made above via the POST_INCREMENT. */
1861 tmp
= gen_rtx_POST_DEC (Pmode
, addr
);
1864 tmp
= gen_rtx_MEM (Pmode
, tmp
);
1865 emit_move_insn (pic_offset_table_rtx
, tmp
);
1872 insn
= gen_sibcall_nogp (addr
);
1874 insn
= gen_call_value_nogp (retval
, addr
, retaddr
);
1876 insn
= gen_call_nogp (addr
, retaddr
);
1877 emit_call_insn (insn
);
1879 if ((!TARGET_CONST_GP
|| is_desc
) && !noreturn_p
&& !sibcall_p
)
1883 /* Begin the assembly file. */
1886 ia64_file_start (void)
1888 default_file_start ();
1889 emit_safe_across_calls ();
1893 emit_safe_across_calls (void)
1895 unsigned int rs
, re
;
1902 while (rs
< 64 && call_used_regs
[PR_REG (rs
)])
1906 for (re
= rs
+ 1; re
< 64 && ! call_used_regs
[PR_REG (re
)]; re
++)
1910 fputs ("\t.pred.safe_across_calls ", asm_out_file
);
1914 fputc (',', asm_out_file
);
1916 fprintf (asm_out_file
, "p%u", rs
);
1918 fprintf (asm_out_file
, "p%u-p%u", rs
, re
- 1);
1922 fputc ('\n', asm_out_file
);
1925 /* Helper function for ia64_compute_frame_size: find an appropriate general
1926 register to spill some special register to. SPECIAL_SPILL_MASK contains
1927 bits in GR0 to GR31 that have already been allocated by this routine.
1928 TRY_LOCALS is true if we should attempt to locate a local regnum. */
1931 find_gr_spill (int try_locals
)
1935 /* If this is a leaf function, first try an otherwise unused
1936 call-clobbered register. */
1937 if (current_function_is_leaf
)
1939 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
1940 if (! regs_ever_live
[regno
]
1941 && call_used_regs
[regno
]
1942 && ! fixed_regs
[regno
]
1943 && ! global_regs
[regno
]
1944 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1946 current_frame_info
.gr_used_mask
|= 1 << regno
;
1953 regno
= current_frame_info
.n_local_regs
;
1954 /* If there is a frame pointer, then we can't use loc79, because
1955 that is HARD_FRAME_POINTER_REGNUM. In particular, see the
1956 reg_name switching code in ia64_expand_prologue. */
1957 if (regno
< (80 - frame_pointer_needed
))
1959 current_frame_info
.n_local_regs
= regno
+ 1;
1960 return LOC_REG (0) + regno
;
1964 /* Failed to find a general register to spill to. Must use stack. */
1968 /* In order to make for nice schedules, we try to allocate every temporary
1969 to a different register. We must of course stay away from call-saved,
1970 fixed, and global registers. We must also stay away from registers
1971 allocated in current_frame_info.gr_used_mask, since those include regs
1972 used all through the prologue.
1974 Any register allocated here must be used immediately. The idea is to
1975 aid scheduling, not to solve data flow problems. */
1977 static int last_scratch_gr_reg
;
1980 next_scratch_gr_reg (void)
1984 for (i
= 0; i
< 32; ++i
)
1986 regno
= (last_scratch_gr_reg
+ i
+ 1) & 31;
1987 if (call_used_regs
[regno
]
1988 && ! fixed_regs
[regno
]
1989 && ! global_regs
[regno
]
1990 && ((current_frame_info
.gr_used_mask
>> regno
) & 1) == 0)
1992 last_scratch_gr_reg
= regno
;
1997 /* There must be _something_ available. */
2001 /* Helper function for ia64_compute_frame_size, called through
2002 diddle_return_value. Mark REG in current_frame_info.gr_used_mask. */
2005 mark_reg_gr_used_mask (rtx reg
, void *data ATTRIBUTE_UNUSED
)
2007 unsigned int regno
= REGNO (reg
);
2010 unsigned int i
, n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
2011 for (i
= 0; i
< n
; ++i
)
2012 current_frame_info
.gr_used_mask
|= 1 << (regno
+ i
);
2016 /* Returns the number of bytes offset between the frame pointer and the stack
2017 pointer for the current function. SIZE is the number of bytes of space
2018 needed for local variables. */
2021 ia64_compute_frame_size (HOST_WIDE_INT size
)
2023 HOST_WIDE_INT total_size
;
2024 HOST_WIDE_INT spill_size
= 0;
2025 HOST_WIDE_INT extra_spill_size
= 0;
2026 HOST_WIDE_INT pretend_args_size
;
2029 int spilled_gr_p
= 0;
2030 int spilled_fr_p
= 0;
2034 if (current_frame_info
.initialized
)
2037 memset (¤t_frame_info
, 0, sizeof current_frame_info
);
2038 CLEAR_HARD_REG_SET (mask
);
2040 /* Don't allocate scratches to the return register. */
2041 diddle_return_value (mark_reg_gr_used_mask
, NULL
);
2043 /* Don't allocate scratches to the EH scratch registers. */
2044 if (cfun
->machine
->ia64_eh_epilogue_sp
)
2045 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_sp
, NULL
);
2046 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
2047 mark_reg_gr_used_mask (cfun
->machine
->ia64_eh_epilogue_bsp
, NULL
);
2049 /* Find the size of the register stack frame. We have only 80 local
2050 registers, because we reserve 8 for the inputs and 8 for the
2053 /* Skip HARD_FRAME_POINTER_REGNUM (loc79) when frame_pointer_needed,
2054 since we'll be adjusting that down later. */
2055 regno
= LOC_REG (78) + ! frame_pointer_needed
;
2056 for (; regno
>= LOC_REG (0); regno
--)
2057 if (regs_ever_live
[regno
])
2059 current_frame_info
.n_local_regs
= regno
- LOC_REG (0) + 1;
2061 /* For functions marked with the syscall_linkage attribute, we must mark
2062 all eight input registers as in use, so that locals aren't visible to
2065 if (cfun
->machine
->n_varargs
> 0
2066 || lookup_attribute ("syscall_linkage",
2067 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))))
2068 current_frame_info
.n_input_regs
= 8;
2071 for (regno
= IN_REG (7); regno
>= IN_REG (0); regno
--)
2072 if (regs_ever_live
[regno
])
2074 current_frame_info
.n_input_regs
= regno
- IN_REG (0) + 1;
2077 for (regno
= OUT_REG (7); regno
>= OUT_REG (0); regno
--)
2078 if (regs_ever_live
[regno
])
2080 i
= regno
- OUT_REG (0) + 1;
2082 /* When -p profiling, we need one output register for the mcount argument.
2083 Likewise for -a profiling for the bb_init_func argument. For -ax
2084 profiling, we need two output registers for the two bb_init_trace_func
2086 if (current_function_profile
)
2088 current_frame_info
.n_output_regs
= i
;
2090 /* ??? No rotating register support yet. */
2091 current_frame_info
.n_rotate_regs
= 0;
2093 /* Discover which registers need spilling, and how much room that
2094 will take. Begin with floating point and general registers,
2095 which will always wind up on the stack. */
2097 for (regno
= FR_REG (2); regno
<= FR_REG (127); regno
++)
2098 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2100 SET_HARD_REG_BIT (mask
, regno
);
2106 for (regno
= GR_REG (1); regno
<= GR_REG (31); regno
++)
2107 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2109 SET_HARD_REG_BIT (mask
, regno
);
2115 for (regno
= BR_REG (1); regno
<= BR_REG (7); regno
++)
2116 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2118 SET_HARD_REG_BIT (mask
, regno
);
2123 /* Now come all special registers that might get saved in other
2124 general registers. */
2126 if (frame_pointer_needed
)
2128 current_frame_info
.reg_fp
= find_gr_spill (1);
2129 /* If we did not get a register, then we take LOC79. This is guaranteed
2130 to be free, even if regs_ever_live is already set, because this is
2131 HARD_FRAME_POINTER_REGNUM. This requires incrementing n_local_regs,
2132 as we don't count loc79 above. */
2133 if (current_frame_info
.reg_fp
== 0)
2135 current_frame_info
.reg_fp
= LOC_REG (79);
2136 current_frame_info
.n_local_regs
++;
2140 if (! current_function_is_leaf
)
2142 /* Emit a save of BR0 if we call other functions. Do this even
2143 if this function doesn't return, as EH depends on this to be
2144 able to unwind the stack. */
2145 SET_HARD_REG_BIT (mask
, BR_REG (0));
2147 current_frame_info
.reg_save_b0
= find_gr_spill (1);
2148 if (current_frame_info
.reg_save_b0
== 0)
2154 /* Similarly for ar.pfs. */
2155 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2156 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
2157 if (current_frame_info
.reg_save_ar_pfs
== 0)
2159 extra_spill_size
+= 8;
2163 /* Similarly for gp. Note that if we're calling setjmp, the stacked
2164 registers are clobbered, so we fall back to the stack. */
2165 current_frame_info
.reg_save_gp
2166 = (current_function_calls_setjmp
? 0 : find_gr_spill (1));
2167 if (current_frame_info
.reg_save_gp
== 0)
2169 SET_HARD_REG_BIT (mask
, GR_REG (1));
2176 if (regs_ever_live
[BR_REG (0)] && ! call_used_regs
[BR_REG (0)])
2178 SET_HARD_REG_BIT (mask
, BR_REG (0));
2183 if (regs_ever_live
[AR_PFS_REGNUM
])
2185 SET_HARD_REG_BIT (mask
, AR_PFS_REGNUM
);
2186 current_frame_info
.reg_save_ar_pfs
= find_gr_spill (1);
2187 if (current_frame_info
.reg_save_ar_pfs
== 0)
2189 extra_spill_size
+= 8;
2195 /* Unwind descriptor hackery: things are most efficient if we allocate
2196 consecutive GR save registers for RP, PFS, FP in that order. However,
2197 it is absolutely critical that FP get the only hard register that's
2198 guaranteed to be free, so we allocated it first. If all three did
2199 happen to be allocated hard regs, and are consecutive, rearrange them
2200 into the preferred order now. */
2201 if (current_frame_info
.reg_fp
!= 0
2202 && current_frame_info
.reg_save_b0
== current_frame_info
.reg_fp
+ 1
2203 && current_frame_info
.reg_save_ar_pfs
== current_frame_info
.reg_fp
+ 2)
2205 current_frame_info
.reg_save_b0
= current_frame_info
.reg_fp
;
2206 current_frame_info
.reg_save_ar_pfs
= current_frame_info
.reg_fp
+ 1;
2207 current_frame_info
.reg_fp
= current_frame_info
.reg_fp
+ 2;
2210 /* See if we need to store the predicate register block. */
2211 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2212 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
2214 if (regno
<= PR_REG (63))
2216 SET_HARD_REG_BIT (mask
, PR_REG (0));
2217 current_frame_info
.reg_save_pr
= find_gr_spill (1);
2218 if (current_frame_info
.reg_save_pr
== 0)
2220 extra_spill_size
+= 8;
2224 /* ??? Mark them all as used so that register renaming and such
2225 are free to use them. */
2226 for (regno
= PR_REG (0); regno
<= PR_REG (63); regno
++)
2227 regs_ever_live
[regno
] = 1;
2230 /* If we're forced to use st8.spill, we're forced to save and restore
2231 ar.unat as well. The check for existing liveness allows inline asm
2232 to touch ar.unat. */
2233 if (spilled_gr_p
|| cfun
->machine
->n_varargs
2234 || regs_ever_live
[AR_UNAT_REGNUM
])
2236 regs_ever_live
[AR_UNAT_REGNUM
] = 1;
2237 SET_HARD_REG_BIT (mask
, AR_UNAT_REGNUM
);
2238 current_frame_info
.reg_save_ar_unat
= find_gr_spill (spill_size
== 0);
2239 if (current_frame_info
.reg_save_ar_unat
== 0)
2241 extra_spill_size
+= 8;
2246 if (regs_ever_live
[AR_LC_REGNUM
])
2248 SET_HARD_REG_BIT (mask
, AR_LC_REGNUM
);
2249 current_frame_info
.reg_save_ar_lc
= find_gr_spill (spill_size
== 0);
2250 if (current_frame_info
.reg_save_ar_lc
== 0)
2252 extra_spill_size
+= 8;
2257 /* If we have an odd number of words of pretend arguments written to
2258 the stack, then the FR save area will be unaligned. We round the
2259 size of this area up to keep things 16 byte aligned. */
2261 pretend_args_size
= IA64_STACK_ALIGN (current_function_pretend_args_size
);
2263 pretend_args_size
= current_function_pretend_args_size
;
2265 total_size
= (spill_size
+ extra_spill_size
+ size
+ pretend_args_size
2266 + current_function_outgoing_args_size
);
2267 total_size
= IA64_STACK_ALIGN (total_size
);
2269 /* We always use the 16-byte scratch area provided by the caller, but
2270 if we are a leaf function, there's no one to which we need to provide
2272 if (current_function_is_leaf
)
2273 total_size
= MAX (0, total_size
- 16);
2275 current_frame_info
.total_size
= total_size
;
2276 current_frame_info
.spill_cfa_off
= pretend_args_size
- 16;
2277 current_frame_info
.spill_size
= spill_size
;
2278 current_frame_info
.extra_spill_size
= extra_spill_size
;
2279 COPY_HARD_REG_SET (current_frame_info
.mask
, mask
);
2280 current_frame_info
.n_spilled
= n_spilled
;
2281 current_frame_info
.initialized
= reload_completed
;
2284 /* Compute the initial difference between the specified pair of registers. */
2287 ia64_initial_elimination_offset (int from
, int to
)
2289 HOST_WIDE_INT offset
;
2291 ia64_compute_frame_size (get_frame_size ());
2294 case FRAME_POINTER_REGNUM
:
2295 if (to
== HARD_FRAME_POINTER_REGNUM
)
2297 if (current_function_is_leaf
)
2298 offset
= -current_frame_info
.total_size
;
2300 offset
= -(current_frame_info
.total_size
2301 - current_function_outgoing_args_size
- 16);
2303 else if (to
== STACK_POINTER_REGNUM
)
2305 if (current_function_is_leaf
)
2308 offset
= 16 + current_function_outgoing_args_size
;
2314 case ARG_POINTER_REGNUM
:
2315 /* Arguments start above the 16 byte save area, unless stdarg
2316 in which case we store through the 16 byte save area. */
2317 if (to
== HARD_FRAME_POINTER_REGNUM
)
2318 offset
= 16 - current_function_pretend_args_size
;
2319 else if (to
== STACK_POINTER_REGNUM
)
2320 offset
= (current_frame_info
.total_size
2321 + 16 - current_function_pretend_args_size
);
2333 /* If there are more than a trivial number of register spills, we use
2334 two interleaved iterators so that we can get two memory references
2337 In order to simplify things in the prologue and epilogue expanders,
2338 we use helper functions to fix up the memory references after the
2339 fact with the appropriate offsets to a POST_MODIFY memory mode.
2340 The following data structure tracks the state of the two iterators
2341 while insns are being emitted. */
2343 struct spill_fill_data
2345 rtx init_after
; /* point at which to emit initializations */
2346 rtx init_reg
[2]; /* initial base register */
2347 rtx iter_reg
[2]; /* the iterator registers */
2348 rtx
*prev_addr
[2]; /* address of last memory use */
2349 rtx prev_insn
[2]; /* the insn corresponding to prev_addr */
2350 HOST_WIDE_INT prev_off
[2]; /* last offset */
2351 int n_iter
; /* number of iterators in use */
2352 int next_iter
; /* next iterator to use */
2353 unsigned int save_gr_used_mask
;
2356 static struct spill_fill_data spill_fill_data
;
2359 setup_spill_pointers (int n_spills
, rtx init_reg
, HOST_WIDE_INT cfa_off
)
2363 spill_fill_data
.init_after
= get_last_insn ();
2364 spill_fill_data
.init_reg
[0] = init_reg
;
2365 spill_fill_data
.init_reg
[1] = init_reg
;
2366 spill_fill_data
.prev_addr
[0] = NULL
;
2367 spill_fill_data
.prev_addr
[1] = NULL
;
2368 spill_fill_data
.prev_insn
[0] = NULL
;
2369 spill_fill_data
.prev_insn
[1] = NULL
;
2370 spill_fill_data
.prev_off
[0] = cfa_off
;
2371 spill_fill_data
.prev_off
[1] = cfa_off
;
2372 spill_fill_data
.next_iter
= 0;
2373 spill_fill_data
.save_gr_used_mask
= current_frame_info
.gr_used_mask
;
2375 spill_fill_data
.n_iter
= 1 + (n_spills
> 2);
2376 for (i
= 0; i
< spill_fill_data
.n_iter
; ++i
)
2378 int regno
= next_scratch_gr_reg ();
2379 spill_fill_data
.iter_reg
[i
] = gen_rtx_REG (DImode
, regno
);
2380 current_frame_info
.gr_used_mask
|= 1 << regno
;
2385 finish_spill_pointers (void)
2387 current_frame_info
.gr_used_mask
= spill_fill_data
.save_gr_used_mask
;
2391 spill_restore_mem (rtx reg
, HOST_WIDE_INT cfa_off
)
2393 int iter
= spill_fill_data
.next_iter
;
2394 HOST_WIDE_INT disp
= spill_fill_data
.prev_off
[iter
] - cfa_off
;
2395 rtx disp_rtx
= GEN_INT (disp
);
2398 if (spill_fill_data
.prev_addr
[iter
])
2400 if (CONST_OK_FOR_N (disp
))
2402 *spill_fill_data
.prev_addr
[iter
]
2403 = gen_rtx_POST_MODIFY (DImode
, spill_fill_data
.iter_reg
[iter
],
2404 gen_rtx_PLUS (DImode
,
2405 spill_fill_data
.iter_reg
[iter
],
2407 REG_NOTES (spill_fill_data
.prev_insn
[iter
])
2408 = gen_rtx_EXPR_LIST (REG_INC
, spill_fill_data
.iter_reg
[iter
],
2409 REG_NOTES (spill_fill_data
.prev_insn
[iter
]));
2413 /* ??? Could use register post_modify for loads. */
2414 if (! CONST_OK_FOR_I (disp
))
2416 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2417 emit_move_insn (tmp
, disp_rtx
);
2420 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2421 spill_fill_data
.iter_reg
[iter
], disp_rtx
));
2424 /* Micro-optimization: if we've created a frame pointer, it's at
2425 CFA 0, which may allow the real iterator to be initialized lower,
2426 slightly increasing parallelism. Also, if there are few saves
2427 it may eliminate the iterator entirely. */
2429 && spill_fill_data
.init_reg
[iter
] == stack_pointer_rtx
2430 && frame_pointer_needed
)
2432 mem
= gen_rtx_MEM (GET_MODE (reg
), hard_frame_pointer_rtx
);
2433 set_mem_alias_set (mem
, get_varargs_alias_set ());
2441 seq
= gen_movdi (spill_fill_data
.iter_reg
[iter
],
2442 spill_fill_data
.init_reg
[iter
]);
2447 if (! CONST_OK_FOR_I (disp
))
2449 rtx tmp
= gen_rtx_REG (DImode
, next_scratch_gr_reg ());
2450 emit_move_insn (tmp
, disp_rtx
);
2454 emit_insn (gen_adddi3 (spill_fill_data
.iter_reg
[iter
],
2455 spill_fill_data
.init_reg
[iter
],
2462 /* Careful for being the first insn in a sequence. */
2463 if (spill_fill_data
.init_after
)
2464 insn
= emit_insn_after (seq
, spill_fill_data
.init_after
);
2467 rtx first
= get_insns ();
2469 insn
= emit_insn_before (seq
, first
);
2471 insn
= emit_insn (seq
);
2473 spill_fill_data
.init_after
= insn
;
2475 /* If DISP is 0, we may or may not have a further adjustment
2476 afterward. If we do, then the load/store insn may be modified
2477 to be a post-modify. If we don't, then this copy may be
2478 eliminated by copyprop_hardreg_forward, which makes this
2479 insn garbage, which runs afoul of the sanity check in
2480 propagate_one_insn. So mark this insn as legal to delete. */
2482 REG_NOTES(insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
,
2486 mem
= gen_rtx_MEM (GET_MODE (reg
), spill_fill_data
.iter_reg
[iter
]);
2488 /* ??? Not all of the spills are for varargs, but some of them are.
2489 The rest of the spills belong in an alias set of their own. But
2490 it doesn't actually hurt to include them here. */
2491 set_mem_alias_set (mem
, get_varargs_alias_set ());
2493 spill_fill_data
.prev_addr
[iter
] = &XEXP (mem
, 0);
2494 spill_fill_data
.prev_off
[iter
] = cfa_off
;
2496 if (++iter
>= spill_fill_data
.n_iter
)
2498 spill_fill_data
.next_iter
= iter
;
2504 do_spill (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
,
2507 int iter
= spill_fill_data
.next_iter
;
2510 mem
= spill_restore_mem (reg
, cfa_off
);
2511 insn
= emit_insn ((*move_fn
) (mem
, reg
, GEN_INT (cfa_off
)));
2512 spill_fill_data
.prev_insn
[iter
] = insn
;
2519 RTX_FRAME_RELATED_P (insn
) = 1;
2521 /* Don't even pretend that the unwind code can intuit its way
2522 through a pair of interleaved post_modify iterators. Just
2523 provide the correct answer. */
2525 if (frame_pointer_needed
)
2527 base
= hard_frame_pointer_rtx
;
2532 base
= stack_pointer_rtx
;
2533 off
= current_frame_info
.total_size
- cfa_off
;
2537 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2538 gen_rtx_SET (VOIDmode
,
2539 gen_rtx_MEM (GET_MODE (reg
),
2540 plus_constant (base
, off
)),
2547 do_restore (rtx (*move_fn
) (rtx
, rtx
, rtx
), rtx reg
, HOST_WIDE_INT cfa_off
)
2549 int iter
= spill_fill_data
.next_iter
;
2552 insn
= emit_insn ((*move_fn
) (reg
, spill_restore_mem (reg
, cfa_off
),
2553 GEN_INT (cfa_off
)));
2554 spill_fill_data
.prev_insn
[iter
] = insn
;
2557 /* Wrapper functions that discards the CONST_INT spill offset. These
2558 exist so that we can give gr_spill/gr_fill the offset they need and
2559 use a consistent function interface. */
2562 gen_movdi_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2564 return gen_movdi (dest
, src
);
2568 gen_fr_spill_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2570 return gen_fr_spill (dest
, src
);
2574 gen_fr_restore_x (rtx dest
, rtx src
, rtx offset ATTRIBUTE_UNUSED
)
2576 return gen_fr_restore (dest
, src
);
2579 /* Called after register allocation to add any instructions needed for the
2580 prologue. Using a prologue insn is favored compared to putting all of the
2581 instructions in output_function_prologue(), since it allows the scheduler
2582 to intermix instructions with the saves of the caller saved registers. In
2583 some cases, it might be necessary to emit a barrier instruction as the last
2584 insn to prevent such scheduling.
2586 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
2587 so that the debug info generation code can handle them properly.
2589 The register save area is layed out like so:
2591 [ varargs spill area ]
2592 [ fr register spill area ]
2593 [ br register spill area ]
2594 [ ar register spill area ]
2595 [ pr register spill area ]
2596 [ gr register spill area ] */
2598 /* ??? Get inefficient code when the frame size is larger than can fit in an
2599 adds instruction. */
2602 ia64_expand_prologue (void)
2604 rtx insn
, ar_pfs_save_reg
, ar_unat_save_reg
;
2605 int i
, epilogue_p
, regno
, alt_regno
, cfa_off
, n_varargs
;
2608 ia64_compute_frame_size (get_frame_size ());
2609 last_scratch_gr_reg
= 15;
2611 /* If there is no epilogue, then we don't need some prologue insns.
2612 We need to avoid emitting the dead prologue insns, because flow
2613 will complain about them. */
2618 for (e
= EXIT_BLOCK_PTR
->pred
; e
; e
= e
->pred_next
)
2619 if ((e
->flags
& EDGE_FAKE
) == 0
2620 && (e
->flags
& EDGE_FALLTHRU
) != 0)
2622 epilogue_p
= (e
!= NULL
);
2627 /* Set the local, input, and output register names. We need to do this
2628 for GNU libc, which creates crti.S/crtn.S by splitting initfini.c in
2629 half. If we use in/loc/out register names, then we get assembler errors
2630 in crtn.S because there is no alloc insn or regstk directive in there. */
2631 if (! TARGET_REG_NAMES
)
2633 int inputs
= current_frame_info
.n_input_regs
;
2634 int locals
= current_frame_info
.n_local_regs
;
2635 int outputs
= current_frame_info
.n_output_regs
;
2637 for (i
= 0; i
< inputs
; i
++)
2638 reg_names
[IN_REG (i
)] = ia64_reg_numbers
[i
];
2639 for (i
= 0; i
< locals
; i
++)
2640 reg_names
[LOC_REG (i
)] = ia64_reg_numbers
[inputs
+ i
];
2641 for (i
= 0; i
< outputs
; i
++)
2642 reg_names
[OUT_REG (i
)] = ia64_reg_numbers
[inputs
+ locals
+ i
];
2645 /* Set the frame pointer register name. The regnum is logically loc79,
2646 but of course we'll not have allocated that many locals. Rather than
2647 worrying about renumbering the existing rtxs, we adjust the name. */
2648 /* ??? This code means that we can never use one local register when
2649 there is a frame pointer. loc79 gets wasted in this case, as it is
2650 renamed to a register that will never be used. See also the try_locals
2651 code in find_gr_spill. */
2652 if (current_frame_info
.reg_fp
)
2654 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
2655 reg_names
[HARD_FRAME_POINTER_REGNUM
]
2656 = reg_names
[current_frame_info
.reg_fp
];
2657 reg_names
[current_frame_info
.reg_fp
] = tmp
;
2660 /* We don't need an alloc instruction if we've used no outputs or locals. */
2661 if (current_frame_info
.n_local_regs
== 0
2662 && current_frame_info
.n_output_regs
== 0
2663 && current_frame_info
.n_input_regs
<= current_function_args_info
.int_regs
2664 && !TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
2666 /* If there is no alloc, but there are input registers used, then we
2667 need a .regstk directive. */
2668 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
2669 ar_pfs_save_reg
= NULL_RTX
;
2673 current_frame_info
.need_regstk
= 0;
2675 if (current_frame_info
.reg_save_ar_pfs
)
2676 regno
= current_frame_info
.reg_save_ar_pfs
;
2678 regno
= next_scratch_gr_reg ();
2679 ar_pfs_save_reg
= gen_rtx_REG (DImode
, regno
);
2681 insn
= emit_insn (gen_alloc (ar_pfs_save_reg
,
2682 GEN_INT (current_frame_info
.n_input_regs
),
2683 GEN_INT (current_frame_info
.n_local_regs
),
2684 GEN_INT (current_frame_info
.n_output_regs
),
2685 GEN_INT (current_frame_info
.n_rotate_regs
)));
2686 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_pfs
!= 0);
2689 /* Set up frame pointer, stack pointer, and spill iterators. */
2691 n_varargs
= cfun
->machine
->n_varargs
;
2692 setup_spill_pointers (current_frame_info
.n_spilled
+ n_varargs
,
2693 stack_pointer_rtx
, 0);
2695 if (frame_pointer_needed
)
2697 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2698 RTX_FRAME_RELATED_P (insn
) = 1;
2701 if (current_frame_info
.total_size
!= 0)
2703 rtx frame_size_rtx
= GEN_INT (- current_frame_info
.total_size
);
2706 if (CONST_OK_FOR_I (- current_frame_info
.total_size
))
2707 offset
= frame_size_rtx
;
2710 regno
= next_scratch_gr_reg ();
2711 offset
= gen_rtx_REG (DImode
, regno
);
2712 emit_move_insn (offset
, frame_size_rtx
);
2715 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
,
2716 stack_pointer_rtx
, offset
));
2718 if (! frame_pointer_needed
)
2720 RTX_FRAME_RELATED_P (insn
) = 1;
2721 if (GET_CODE (offset
) != CONST_INT
)
2724 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2725 gen_rtx_SET (VOIDmode
,
2727 gen_rtx_PLUS (DImode
,
2734 /* ??? At this point we must generate a magic insn that appears to
2735 modify the stack pointer, the frame pointer, and all spill
2736 iterators. This would allow the most scheduling freedom. For
2737 now, just hard stop. */
2738 emit_insn (gen_blockage ());
2741 /* Must copy out ar.unat before doing any integer spills. */
2742 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
2744 if (current_frame_info
.reg_save_ar_unat
)
2746 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
2749 alt_regno
= next_scratch_gr_reg ();
2750 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
2751 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
2754 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2755 insn
= emit_move_insn (ar_unat_save_reg
, reg
);
2756 RTX_FRAME_RELATED_P (insn
) = (current_frame_info
.reg_save_ar_unat
!= 0);
2758 /* Even if we're not going to generate an epilogue, we still
2759 need to save the register so that EH works. */
2760 if (! epilogue_p
&& current_frame_info
.reg_save_ar_unat
)
2761 emit_insn (gen_prologue_use (ar_unat_save_reg
));
2764 ar_unat_save_reg
= NULL_RTX
;
2766 /* Spill all varargs registers. Do this before spilling any GR registers,
2767 since we want the UNAT bits for the GR registers to override the UNAT
2768 bits from varargs, which we don't care about. */
2771 for (regno
= GR_ARG_FIRST
+ 7; n_varargs
> 0; --n_varargs
, --regno
)
2773 reg
= gen_rtx_REG (DImode
, regno
);
2774 do_spill (gen_gr_spill
, reg
, cfa_off
+= 8, NULL_RTX
);
2777 /* Locate the bottom of the register save area. */
2778 cfa_off
= (current_frame_info
.spill_cfa_off
2779 + current_frame_info
.spill_size
2780 + current_frame_info
.extra_spill_size
);
2782 /* Save the predicate register block either in a register or in memory. */
2783 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2785 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2786 if (current_frame_info
.reg_save_pr
!= 0)
2788 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2789 insn
= emit_move_insn (alt_reg
, reg
);
2791 /* ??? Denote pr spill/fill by a DImode move that modifies all
2792 64 hard registers. */
2793 RTX_FRAME_RELATED_P (insn
) = 1;
2795 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2796 gen_rtx_SET (VOIDmode
, alt_reg
, reg
),
2799 /* Even if we're not going to generate an epilogue, we still
2800 need to save the register so that EH works. */
2802 emit_insn (gen_prologue_use (alt_reg
));
2806 alt_regno
= next_scratch_gr_reg ();
2807 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2808 insn
= emit_move_insn (alt_reg
, reg
);
2809 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2814 /* Handle AR regs in numerical order. All of them get special handling. */
2815 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
)
2816 && current_frame_info
.reg_save_ar_unat
== 0)
2818 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
2819 do_spill (gen_movdi_x
, ar_unat_save_reg
, cfa_off
, reg
);
2823 /* The alloc insn already copied ar.pfs into a general register. The
2824 only thing we have to do now is copy that register to a stack slot
2825 if we'd not allocated a local register for the job. */
2826 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
)
2827 && current_frame_info
.reg_save_ar_pfs
== 0)
2829 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
2830 do_spill (gen_movdi_x
, ar_pfs_save_reg
, cfa_off
, reg
);
2834 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
2836 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
2837 if (current_frame_info
.reg_save_ar_lc
!= 0)
2839 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
2840 insn
= emit_move_insn (alt_reg
, reg
);
2841 RTX_FRAME_RELATED_P (insn
) = 1;
2843 /* Even if we're not going to generate an epilogue, we still
2844 need to save the register so that EH works. */
2846 emit_insn (gen_prologue_use (alt_reg
));
2850 alt_regno
= next_scratch_gr_reg ();
2851 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2852 emit_move_insn (alt_reg
, reg
);
2853 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2858 if (current_frame_info
.reg_save_gp
)
2860 insn
= emit_move_insn (gen_rtx_REG (DImode
,
2861 current_frame_info
.reg_save_gp
),
2862 pic_offset_table_rtx
);
2863 /* We don't know for sure yet if this is actually needed, since
2864 we've not split the PIC call patterns. If all of the calls
2865 are indirect, and not followed by any uses of the gp, then
2866 this save is dead. Allow it to go away. */
2868 = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
, const0_rtx
, REG_NOTES (insn
));
2871 /* We should now be at the base of the gr/br/fr spill area. */
2872 if (cfa_off
!= (current_frame_info
.spill_cfa_off
2873 + current_frame_info
.spill_size
))
2876 /* Spill all general registers. */
2877 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
2878 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2880 reg
= gen_rtx_REG (DImode
, regno
);
2881 do_spill (gen_gr_spill
, reg
, cfa_off
, reg
);
2885 /* Handle BR0 specially -- it may be getting stored permanently in
2886 some GR register. */
2887 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
2889 reg
= gen_rtx_REG (DImode
, BR_REG (0));
2890 if (current_frame_info
.reg_save_b0
!= 0)
2892 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
2893 insn
= emit_move_insn (alt_reg
, reg
);
2894 RTX_FRAME_RELATED_P (insn
) = 1;
2896 /* Even if we're not going to generate an epilogue, we still
2897 need to save the register so that EH works. */
2899 emit_insn (gen_prologue_use (alt_reg
));
2903 alt_regno
= next_scratch_gr_reg ();
2904 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2905 emit_move_insn (alt_reg
, reg
);
2906 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2911 /* Spill the rest of the BR registers. */
2912 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
2913 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2915 alt_regno
= next_scratch_gr_reg ();
2916 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2917 reg
= gen_rtx_REG (DImode
, regno
);
2918 emit_move_insn (alt_reg
, reg
);
2919 do_spill (gen_movdi_x
, alt_reg
, cfa_off
, reg
);
2923 /* Align the frame and spill all FR registers. */
2924 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
2925 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
2929 reg
= gen_rtx_REG (XFmode
, regno
);
2930 do_spill (gen_fr_spill_x
, reg
, cfa_off
, reg
);
2934 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
2937 finish_spill_pointers ();
2940 /* Called after register allocation to add any instructions needed for the
2941 epilogue. Using an epilogue insn is favored compared to putting all of the
2942 instructions in output_function_prologue(), since it allows the scheduler
2943 to intermix instructions with the saves of the caller saved registers. In
2944 some cases, it might be necessary to emit a barrier instruction as the last
2945 insn to prevent such scheduling. */
2948 ia64_expand_epilogue (int sibcall_p
)
2950 rtx insn
, reg
, alt_reg
, ar_unat_save_reg
;
2951 int regno
, alt_regno
, cfa_off
;
2953 ia64_compute_frame_size (get_frame_size ());
2955 /* If there is a frame pointer, then we use it instead of the stack
2956 pointer, so that the stack pointer does not need to be valid when
2957 the epilogue starts. See EXIT_IGNORE_STACK. */
2958 if (frame_pointer_needed
)
2959 setup_spill_pointers (current_frame_info
.n_spilled
,
2960 hard_frame_pointer_rtx
, 0);
2962 setup_spill_pointers (current_frame_info
.n_spilled
, stack_pointer_rtx
,
2963 current_frame_info
.total_size
);
2965 if (current_frame_info
.total_size
!= 0)
2967 /* ??? At this point we must generate a magic insn that appears to
2968 modify the spill iterators and the frame pointer. This would
2969 allow the most scheduling freedom. For now, just hard stop. */
2970 emit_insn (gen_blockage ());
2973 /* Locate the bottom of the register save area. */
2974 cfa_off
= (current_frame_info
.spill_cfa_off
2975 + current_frame_info
.spill_size
2976 + current_frame_info
.extra_spill_size
);
2978 /* Restore the predicate registers. */
2979 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, PR_REG (0)))
2981 if (current_frame_info
.reg_save_pr
!= 0)
2982 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_pr
);
2985 alt_regno
= next_scratch_gr_reg ();
2986 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
2987 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
2990 reg
= gen_rtx_REG (DImode
, PR_REG (0));
2991 emit_move_insn (reg
, alt_reg
);
2994 /* Restore the application registers. */
2996 /* Load the saved unat from the stack, but do not restore it until
2997 after the GRs have been restored. */
2998 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3000 if (current_frame_info
.reg_save_ar_unat
!= 0)
3002 = gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_unat
);
3005 alt_regno
= next_scratch_gr_reg ();
3006 ar_unat_save_reg
= gen_rtx_REG (DImode
, alt_regno
);
3007 current_frame_info
.gr_used_mask
|= 1 << alt_regno
;
3008 do_restore (gen_movdi_x
, ar_unat_save_reg
, cfa_off
);
3013 ar_unat_save_reg
= NULL_RTX
;
3015 if (current_frame_info
.reg_save_ar_pfs
!= 0)
3017 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_pfs
);
3018 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3019 emit_move_insn (reg
, alt_reg
);
3021 else if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_PFS_REGNUM
))
3023 alt_regno
= next_scratch_gr_reg ();
3024 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3025 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3027 reg
= gen_rtx_REG (DImode
, AR_PFS_REGNUM
);
3028 emit_move_insn (reg
, alt_reg
);
3031 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_LC_REGNUM
))
3033 if (current_frame_info
.reg_save_ar_lc
!= 0)
3034 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_ar_lc
);
3037 alt_regno
= next_scratch_gr_reg ();
3038 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3039 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3042 reg
= gen_rtx_REG (DImode
, AR_LC_REGNUM
);
3043 emit_move_insn (reg
, alt_reg
);
3046 /* We should now be at the base of the gr/br/fr spill area. */
3047 if (cfa_off
!= (current_frame_info
.spill_cfa_off
3048 + current_frame_info
.spill_size
))
3051 /* The GP may be stored on the stack in the prologue, but it's
3052 never restored in the epilogue. Skip the stack slot. */
3053 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, GR_REG (1)))
3056 /* Restore all general registers. */
3057 for (regno
= GR_REG (2); regno
<= GR_REG (31); ++regno
)
3058 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3060 reg
= gen_rtx_REG (DImode
, regno
);
3061 do_restore (gen_gr_restore
, reg
, cfa_off
);
3065 /* Restore the branch registers. Handle B0 specially, as it may
3066 have gotten stored in some GR register. */
3067 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3069 if (current_frame_info
.reg_save_b0
!= 0)
3070 alt_reg
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
3073 alt_regno
= next_scratch_gr_reg ();
3074 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3075 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3078 reg
= gen_rtx_REG (DImode
, BR_REG (0));
3079 emit_move_insn (reg
, alt_reg
);
3082 for (regno
= BR_REG (1); regno
<= BR_REG (7); ++regno
)
3083 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3085 alt_regno
= next_scratch_gr_reg ();
3086 alt_reg
= gen_rtx_REG (DImode
, alt_regno
);
3087 do_restore (gen_movdi_x
, alt_reg
, cfa_off
);
3089 reg
= gen_rtx_REG (DImode
, regno
);
3090 emit_move_insn (reg
, alt_reg
);
3093 /* Restore floating point registers. */
3094 for (regno
= FR_REG (2); regno
<= FR_REG (127); ++regno
)
3095 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3099 reg
= gen_rtx_REG (XFmode
, regno
);
3100 do_restore (gen_fr_restore_x
, reg
, cfa_off
);
3104 /* Restore ar.unat for real. */
3105 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, AR_UNAT_REGNUM
))
3107 reg
= gen_rtx_REG (DImode
, AR_UNAT_REGNUM
);
3108 emit_move_insn (reg
, ar_unat_save_reg
);
3111 if (cfa_off
!= current_frame_info
.spill_cfa_off
)
3114 finish_spill_pointers ();
3116 if (current_frame_info
.total_size
|| cfun
->machine
->ia64_eh_epilogue_sp
)
3118 /* ??? At this point we must generate a magic insn that appears to
3119 modify the spill iterators, the stack pointer, and the frame
3120 pointer. This would allow the most scheduling freedom. For now,
3122 emit_insn (gen_blockage ());
3125 if (cfun
->machine
->ia64_eh_epilogue_sp
)
3126 emit_move_insn (stack_pointer_rtx
, cfun
->machine
->ia64_eh_epilogue_sp
);
3127 else if (frame_pointer_needed
)
3129 insn
= emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
3130 RTX_FRAME_RELATED_P (insn
) = 1;
3132 else if (current_frame_info
.total_size
)
3134 rtx offset
, frame_size_rtx
;
3136 frame_size_rtx
= GEN_INT (current_frame_info
.total_size
);
3137 if (CONST_OK_FOR_I (current_frame_info
.total_size
))
3138 offset
= frame_size_rtx
;
3141 regno
= next_scratch_gr_reg ();
3142 offset
= gen_rtx_REG (DImode
, regno
);
3143 emit_move_insn (offset
, frame_size_rtx
);
3146 insn
= emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
3149 RTX_FRAME_RELATED_P (insn
) = 1;
3150 if (GET_CODE (offset
) != CONST_INT
)
3153 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
3154 gen_rtx_SET (VOIDmode
,
3156 gen_rtx_PLUS (DImode
,
3163 if (cfun
->machine
->ia64_eh_epilogue_bsp
)
3164 emit_insn (gen_set_bsp (cfun
->machine
->ia64_eh_epilogue_bsp
));
3167 emit_jump_insn (gen_return_internal (gen_rtx_REG (DImode
, BR_REG (0))));
3170 int fp
= GR_REG (2);
3171 /* We need a throw away register here, r0 and r1 are reserved, so r2 is the
3172 first available call clobbered register. If there was a frame_pointer
3173 register, we may have swapped the names of r2 and HARD_FRAME_POINTER_REGNUM,
3174 so we have to make sure we're using the string "r2" when emitting
3175 the register name for the assembler. */
3176 if (current_frame_info
.reg_fp
&& current_frame_info
.reg_fp
== GR_REG (2))
3177 fp
= HARD_FRAME_POINTER_REGNUM
;
3179 /* We must emit an alloc to force the input registers to become output
3180 registers. Otherwise, if the callee tries to pass its parameters
3181 through to another call without an intervening alloc, then these
3183 /* ??? We don't need to preserve all input registers. We only need to
3184 preserve those input registers used as arguments to the sibling call.
3185 It is unclear how to compute that number here. */
3186 if (current_frame_info
.n_input_regs
!= 0)
3187 emit_insn (gen_alloc (gen_rtx_REG (DImode
, fp
),
3188 const0_rtx
, const0_rtx
,
3189 GEN_INT (current_frame_info
.n_input_regs
),
3194 /* Return 1 if br.ret can do all the work required to return from a
3198 ia64_direct_return (void)
3200 if (reload_completed
&& ! frame_pointer_needed
)
3202 ia64_compute_frame_size (get_frame_size ());
3204 return (current_frame_info
.total_size
== 0
3205 && current_frame_info
.n_spilled
== 0
3206 && current_frame_info
.reg_save_b0
== 0
3207 && current_frame_info
.reg_save_pr
== 0
3208 && current_frame_info
.reg_save_ar_pfs
== 0
3209 && current_frame_info
.reg_save_ar_unat
== 0
3210 && current_frame_info
.reg_save_ar_lc
== 0);
3215 /* Return the magic cookie that we use to hold the return address
3216 during early compilation. */
3219 ia64_return_addr_rtx (HOST_WIDE_INT count
, rtx frame ATTRIBUTE_UNUSED
)
3223 return gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_RET_ADDR
);
3226 /* Split this value after reload, now that we know where the return
3227 address is saved. */
3230 ia64_split_return_addr_rtx (rtx dest
)
3234 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, BR_REG (0)))
3236 if (current_frame_info
.reg_save_b0
!= 0)
3237 src
= gen_rtx_REG (DImode
, current_frame_info
.reg_save_b0
);
3243 /* Compute offset from CFA for BR0. */
3244 /* ??? Must be kept in sync with ia64_expand_prologue. */
3245 off
= (current_frame_info
.spill_cfa_off
3246 + current_frame_info
.spill_size
);
3247 for (regno
= GR_REG (1); regno
<= GR_REG (31); ++regno
)
3248 if (TEST_HARD_REG_BIT (current_frame_info
.mask
, regno
))
3251 /* Convert CFA offset to a register based offset. */
3252 if (frame_pointer_needed
)
3253 src
= hard_frame_pointer_rtx
;
3256 src
= stack_pointer_rtx
;
3257 off
+= current_frame_info
.total_size
;
3260 /* Load address into scratch register. */
3261 if (CONST_OK_FOR_I (off
))
3262 emit_insn (gen_adddi3 (dest
, src
, GEN_INT (off
)));
3265 emit_move_insn (dest
, GEN_INT (off
));
3266 emit_insn (gen_adddi3 (dest
, src
, dest
));
3269 src
= gen_rtx_MEM (Pmode
, dest
);
3273 src
= gen_rtx_REG (DImode
, BR_REG (0));
3275 emit_move_insn (dest
, src
);
3279 ia64_hard_regno_rename_ok (int from
, int to
)
3281 /* Don't clobber any of the registers we reserved for the prologue. */
3282 if (to
== current_frame_info
.reg_fp
3283 || to
== current_frame_info
.reg_save_b0
3284 || to
== current_frame_info
.reg_save_pr
3285 || to
== current_frame_info
.reg_save_ar_pfs
3286 || to
== current_frame_info
.reg_save_ar_unat
3287 || to
== current_frame_info
.reg_save_ar_lc
)
3290 if (from
== current_frame_info
.reg_fp
3291 || from
== current_frame_info
.reg_save_b0
3292 || from
== current_frame_info
.reg_save_pr
3293 || from
== current_frame_info
.reg_save_ar_pfs
3294 || from
== current_frame_info
.reg_save_ar_unat
3295 || from
== current_frame_info
.reg_save_ar_lc
)
3298 /* Don't use output registers outside the register frame. */
3299 if (OUT_REGNO_P (to
) && to
>= OUT_REG (current_frame_info
.n_output_regs
))
3302 /* Retain even/oddness on predicate register pairs. */
3303 if (PR_REGNO_P (from
) && PR_REGNO_P (to
))
3304 return (from
& 1) == (to
& 1);
3309 /* Target hook for assembling integer objects. Handle word-sized
3310 aligned objects and detect the cases when @fptr is needed. */
3313 ia64_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
3315 if (size
== POINTER_SIZE
/ BITS_PER_UNIT
3317 && !(TARGET_NO_PIC
|| TARGET_AUTO_PIC
)
3318 && GET_CODE (x
) == SYMBOL_REF
3319 && SYMBOL_REF_FUNCTION_P (x
))
3321 if (POINTER_SIZE
== 32)
3322 fputs ("\tdata4\t@fptr(", asm_out_file
);
3324 fputs ("\tdata8\t@fptr(", asm_out_file
);
3325 output_addr_const (asm_out_file
, x
);
3326 fputs (")\n", asm_out_file
);
3329 return default_assemble_integer (x
, size
, aligned_p
);
3332 /* Emit the function prologue. */
3335 ia64_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3337 int mask
, grsave
, grsave_prev
;
3339 if (current_frame_info
.need_regstk
)
3340 fprintf (file
, "\t.regstk %d, %d, %d, %d\n",
3341 current_frame_info
.n_input_regs
,
3342 current_frame_info
.n_local_regs
,
3343 current_frame_info
.n_output_regs
,
3344 current_frame_info
.n_rotate_regs
);
3346 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3349 /* Emit the .prologue directive. */
3352 grsave
= grsave_prev
= 0;
3353 if (current_frame_info
.reg_save_b0
!= 0)
3356 grsave
= grsave_prev
= current_frame_info
.reg_save_b0
;
3358 if (current_frame_info
.reg_save_ar_pfs
!= 0
3359 && (grsave_prev
== 0
3360 || current_frame_info
.reg_save_ar_pfs
== grsave_prev
+ 1))
3363 if (grsave_prev
== 0)
3364 grsave
= current_frame_info
.reg_save_ar_pfs
;
3365 grsave_prev
= current_frame_info
.reg_save_ar_pfs
;
3367 if (current_frame_info
.reg_fp
!= 0
3368 && (grsave_prev
== 0
3369 || current_frame_info
.reg_fp
== grsave_prev
+ 1))
3372 if (grsave_prev
== 0)
3373 grsave
= HARD_FRAME_POINTER_REGNUM
;
3374 grsave_prev
= current_frame_info
.reg_fp
;
3376 if (current_frame_info
.reg_save_pr
!= 0
3377 && (grsave_prev
== 0
3378 || current_frame_info
.reg_save_pr
== grsave_prev
+ 1))
3381 if (grsave_prev
== 0)
3382 grsave
= current_frame_info
.reg_save_pr
;
3385 if (mask
&& TARGET_GNU_AS
)
3386 fprintf (file
, "\t.prologue %d, %d\n", mask
,
3387 ia64_dbx_register_number (grsave
));
3389 fputs ("\t.prologue\n", file
);
3391 /* Emit a .spill directive, if necessary, to relocate the base of
3392 the register spill area. */
3393 if (current_frame_info
.spill_cfa_off
!= -16)
3394 fprintf (file
, "\t.spill %ld\n",
3395 (long) (current_frame_info
.spill_cfa_off
3396 + current_frame_info
.spill_size
));
3399 /* Emit the .body directive at the scheduled end of the prologue. */
3402 ia64_output_function_end_prologue (FILE *file
)
3404 if (!flag_unwind_tables
&& (!flag_exceptions
|| USING_SJLJ_EXCEPTIONS
))
3407 fputs ("\t.body\n", file
);
3410 /* Emit the function epilogue. */
3413 ia64_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
3414 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
3418 if (current_frame_info
.reg_fp
)
3420 const char *tmp
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
3421 reg_names
[HARD_FRAME_POINTER_REGNUM
]
3422 = reg_names
[current_frame_info
.reg_fp
];
3423 reg_names
[current_frame_info
.reg_fp
] = tmp
;
3425 if (! TARGET_REG_NAMES
)
3427 for (i
= 0; i
< current_frame_info
.n_input_regs
; i
++)
3428 reg_names
[IN_REG (i
)] = ia64_input_reg_names
[i
];
3429 for (i
= 0; i
< current_frame_info
.n_local_regs
; i
++)
3430 reg_names
[LOC_REG (i
)] = ia64_local_reg_names
[i
];
3431 for (i
= 0; i
< current_frame_info
.n_output_regs
; i
++)
3432 reg_names
[OUT_REG (i
)] = ia64_output_reg_names
[i
];
3435 current_frame_info
.initialized
= 0;
3439 ia64_dbx_register_number (int regno
)
3441 /* In ia64_expand_prologue we quite literally renamed the frame pointer
3442 from its home at loc79 to something inside the register frame. We
3443 must perform the same renumbering here for the debug info. */
3444 if (current_frame_info
.reg_fp
)
3446 if (regno
== HARD_FRAME_POINTER_REGNUM
)
3447 regno
= current_frame_info
.reg_fp
;
3448 else if (regno
== current_frame_info
.reg_fp
)
3449 regno
= HARD_FRAME_POINTER_REGNUM
;
3452 if (IN_REGNO_P (regno
))
3453 return 32 + regno
- IN_REG (0);
3454 else if (LOC_REGNO_P (regno
))
3455 return 32 + current_frame_info
.n_input_regs
+ regno
- LOC_REG (0);
3456 else if (OUT_REGNO_P (regno
))
3457 return (32 + current_frame_info
.n_input_regs
3458 + current_frame_info
.n_local_regs
+ regno
- OUT_REG (0));
3464 ia64_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx static_chain
)
3466 rtx addr_reg
, eight
= GEN_INT (8);
3468 /* The Intel assembler requires that the global __ia64_trampoline symbol
3469 be declared explicitly */
3472 static bool declared_ia64_trampoline
= false;
3474 if (!declared_ia64_trampoline
)
3476 declared_ia64_trampoline
= true;
3477 (*targetm
.asm_out
.globalize_label
) (asm_out_file
,
3478 "__ia64_trampoline");
3482 /* Load up our iterator. */
3483 addr_reg
= gen_reg_rtx (Pmode
);
3484 emit_move_insn (addr_reg
, addr
);
3486 /* The first two words are the fake descriptor:
3487 __ia64_trampoline, ADDR+16. */
3488 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3489 gen_rtx_SYMBOL_REF (Pmode
, "__ia64_trampoline"));
3490 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3492 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
),
3493 copy_to_reg (plus_constant (addr
, 16)));
3494 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3496 /* The third word is the target descriptor. */
3497 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), fnaddr
);
3498 emit_insn (gen_adddi3 (addr_reg
, addr_reg
, eight
));
3500 /* The fourth word is the static chain. */
3501 emit_move_insn (gen_rtx_MEM (Pmode
, addr_reg
), static_chain
);
3504 /* Do any needed setup for a variadic function. CUM has not been updated
3505 for the last named argument which has type TYPE and mode MODE.
3507 We generate the actual spill instructions during prologue generation. */
3510 ia64_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3511 tree type
, int * pretend_size
,
3512 int second_time ATTRIBUTE_UNUSED
)
3514 CUMULATIVE_ARGS next_cum
= *cum
;
3516 /* Skip the current argument. */
3517 ia64_function_arg_advance (&next_cum
, mode
, type
, 1);
3519 if (next_cum
.words
< MAX_ARGUMENT_SLOTS
)
3521 int n
= MAX_ARGUMENT_SLOTS
- next_cum
.words
;
3522 *pretend_size
= n
* UNITS_PER_WORD
;
3523 cfun
->machine
->n_varargs
= n
;
3527 /* Check whether TYPE is a homogeneous floating point aggregate. If
3528 it is, return the mode of the floating point type that appears
3529 in all leafs. If it is not, return VOIDmode.
3531 An aggregate is a homogeneous floating point aggregate is if all
3532 fields/elements in it have the same floating point type (e.g,
3533 SFmode). 128-bit quad-precision floats are excluded. */
3535 static enum machine_mode
3536 hfa_element_mode (tree type
, int nested
)
3538 enum machine_mode element_mode
= VOIDmode
;
3539 enum machine_mode mode
;
3540 enum tree_code code
= TREE_CODE (type
);
3541 int know_element_mode
= 0;
3546 case VOID_TYPE
: case INTEGER_TYPE
: case ENUMERAL_TYPE
:
3547 case BOOLEAN_TYPE
: case CHAR_TYPE
: case POINTER_TYPE
:
3548 case OFFSET_TYPE
: case REFERENCE_TYPE
: case METHOD_TYPE
:
3549 case FILE_TYPE
: case SET_TYPE
: case LANG_TYPE
:
3553 /* Fortran complex types are supposed to be HFAs, so we need to handle
3554 gcc's COMPLEX_TYPEs as HFAs. We need to exclude the integral complex
3557 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
3558 && TYPE_MODE (type
) != TCmode
)
3559 return GET_MODE_INNER (TYPE_MODE (type
));
3564 /* We want to return VOIDmode for raw REAL_TYPEs, but the actual
3565 mode if this is contained within an aggregate. */
3566 if (nested
&& TYPE_MODE (type
) != TFmode
)
3567 return TYPE_MODE (type
);
3572 return hfa_element_mode (TREE_TYPE (type
), 1);
3576 case QUAL_UNION_TYPE
:
3577 for (t
= TYPE_FIELDS (type
); t
; t
= TREE_CHAIN (t
))
3579 if (TREE_CODE (t
) != FIELD_DECL
)
3582 mode
= hfa_element_mode (TREE_TYPE (t
), 1);
3583 if (know_element_mode
)
3585 if (mode
!= element_mode
)
3588 else if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
3592 know_element_mode
= 1;
3593 element_mode
= mode
;
3596 return element_mode
;
3599 /* If we reach here, we probably have some front-end specific type
3600 that the backend doesn't know about. This can happen via the
3601 aggregate_value_p call in init_function_start. All we can do is
3602 ignore unknown tree types. */
3609 /* Return the number of words required to hold a quantity of TYPE and MODE
3610 when passed as an argument. */
3612 ia64_function_arg_words (tree type
, enum machine_mode mode
)
3616 if (mode
== BLKmode
)
3617 words
= int_size_in_bytes (type
);
3619 words
= GET_MODE_SIZE (mode
);
3621 return (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
; /* round up */
3624 /* Return the number of registers that should be skipped so the current
3625 argument (described by TYPE and WORDS) will be properly aligned.
3627 Integer and float arguments larger than 8 bytes start at the next
3628 even boundary. Aggregates larger than 8 bytes start at the next
3629 even boundary if the aggregate has 16 byte alignment. Note that
3630 in the 32-bit ABI, TImode and TFmode have only 8-byte alignment
3631 but are still to be aligned in registers.
3633 ??? The ABI does not specify how to handle aggregates with
3634 alignment from 9 to 15 bytes, or greater than 16. We handle them
3635 all as if they had 16 byte alignment. Such aggregates can occur
3636 only if gcc extensions are used. */
3638 ia64_function_arg_offset (CUMULATIVE_ARGS
*cum
, tree type
, int words
)
3640 if ((cum
->words
& 1) == 0)
3644 && TREE_CODE (type
) != INTEGER_TYPE
3645 && TREE_CODE (type
) != REAL_TYPE
)
3646 return TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
;
3651 /* Return rtx for register where argument is passed, or zero if it is passed
3653 /* ??? 128-bit quad-precision floats are always passed in general
3657 ia64_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
3658 int named
, int incoming
)
3660 int basereg
= (incoming
? GR_ARG_FIRST
: AR_ARG_FIRST
);
3661 int words
= ia64_function_arg_words (type
, mode
);
3662 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3663 enum machine_mode hfa_mode
= VOIDmode
;
3665 /* If all argument slots are used, then it must go on the stack. */
3666 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3669 /* Check for and handle homogeneous FP aggregates. */
3671 hfa_mode
= hfa_element_mode (type
, 0);
3673 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3674 and unprototyped hfas are passed specially. */
3675 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3679 int fp_regs
= cum
->fp_regs
;
3680 int int_regs
= cum
->words
+ offset
;
3681 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3685 /* If prototyped, pass it in FR regs then GR regs.
3686 If not prototyped, pass it in both FR and GR regs.
3688 If this is an SFmode aggregate, then it is possible to run out of
3689 FR regs while GR regs are still left. In that case, we pass the
3690 remaining part in the GR regs. */
3692 /* Fill the FP regs. We do this always. We stop if we reach the end
3693 of the argument, the last FP register, or the last argument slot. */
3695 byte_size
= ((mode
== BLKmode
)
3696 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3697 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3699 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3700 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
)); i
++)
3702 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3703 gen_rtx_REG (hfa_mode
, (FR_ARG_FIRST
3707 args_byte_size
+= hfa_size
;
3711 /* If no prototype, then the whole thing must go in GR regs. */
3712 if (! cum
->prototype
)
3714 /* If this is an SFmode aggregate, then we might have some left over
3715 that needs to go in GR regs. */
3716 else if (byte_size
!= offset
)
3717 int_regs
+= offset
/ UNITS_PER_WORD
;
3719 /* Fill in the GR regs. We must use DImode here, not the hfa mode. */
3721 for (; offset
< byte_size
&& int_regs
< MAX_ARGUMENT_SLOTS
; i
++)
3723 enum machine_mode gr_mode
= DImode
;
3724 unsigned int gr_size
;
3726 /* If we have an odd 4 byte hunk because we ran out of FR regs,
3727 then this goes in a GR reg left adjusted/little endian, right
3728 adjusted/big endian. */
3729 /* ??? Currently this is handled wrong, because 4-byte hunks are
3730 always right adjusted/little endian. */
3733 /* If we have an even 4 byte hunk because the aggregate is a
3734 multiple of 4 bytes in size, then this goes in a GR reg right
3735 adjusted/little endian. */
3736 else if (byte_size
- offset
== 4)
3739 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
3740 gen_rtx_REG (gr_mode
, (basereg
3744 gr_size
= GET_MODE_SIZE (gr_mode
);
3746 if (gr_size
== UNITS_PER_WORD
3747 || (gr_size
< UNITS_PER_WORD
&& offset
% UNITS_PER_WORD
== 0))
3749 else if (gr_size
> UNITS_PER_WORD
)
3750 int_regs
+= gr_size
/ UNITS_PER_WORD
;
3753 /* If we ended up using just one location, just return that one loc, but
3754 change the mode back to the argument mode. */
3756 return gen_rtx_REG (mode
, REGNO (XEXP (loc
[0], 0)));
3758 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
3761 /* Integral and aggregates go in general registers. If we have run out of
3762 FR registers, then FP values must also go in general registers. This can
3763 happen when we have a SFmode HFA. */
3764 else if (mode
== TFmode
|| mode
== TCmode
3765 || (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
))
3767 int byte_size
= ((mode
== BLKmode
)
3768 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3769 if (BYTES_BIG_ENDIAN
3770 && (mode
== BLKmode
|| (type
&& AGGREGATE_TYPE_P (type
)))
3771 && byte_size
< UNITS_PER_WORD
3774 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3775 gen_rtx_REG (DImode
,
3776 (basereg
+ cum
->words
3779 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, gr_reg
));
3782 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3786 /* If there is a prototype, then FP values go in a FR register when
3787 named, and in a GR register when unnamed. */
3788 else if (cum
->prototype
)
3791 return gen_rtx_REG (mode
, FR_ARG_FIRST
+ cum
->fp_regs
);
3792 /* In big-endian mode, an anonymous SFmode value must be represented
3793 as (parallel:SF [(expr_list (reg:DI n) (const_int 0))]) to force
3794 the value into the high half of the general register. */
3795 else if (BYTES_BIG_ENDIAN
&& mode
== SFmode
)
3796 return gen_rtx_PARALLEL (mode
,
3798 gen_rtx_EXPR_LIST (VOIDmode
,
3799 gen_rtx_REG (DImode
, basereg
+ cum
->words
+ offset
),
3802 return gen_rtx_REG (mode
, basereg
+ cum
->words
+ offset
);
3804 /* If there is no prototype, then FP values go in both FR and GR
3808 /* See comment above. */
3809 enum machine_mode inner_mode
=
3810 (BYTES_BIG_ENDIAN
&& mode
== SFmode
) ? DImode
: mode
;
3812 rtx fp_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3813 gen_rtx_REG (mode
, (FR_ARG_FIRST
3816 rtx gr_reg
= gen_rtx_EXPR_LIST (VOIDmode
,
3817 gen_rtx_REG (inner_mode
,
3818 (basereg
+ cum
->words
3822 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, fp_reg
, gr_reg
));
3826 /* Return number of words, at the beginning of the argument, that must be
3827 put in registers. 0 is the argument is entirely in registers or entirely
3831 ia64_function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3832 tree type
, int named ATTRIBUTE_UNUSED
)
3834 int words
= ia64_function_arg_words (type
, mode
);
3835 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3837 /* If all argument slots are used, then it must go on the stack. */
3838 if (cum
->words
+ offset
>= MAX_ARGUMENT_SLOTS
)
3841 /* It doesn't matter whether the argument goes in FR or GR regs. If
3842 it fits within the 8 argument slots, then it goes entirely in
3843 registers. If it extends past the last argument slot, then the rest
3844 goes on the stack. */
3846 if (words
+ cum
->words
+ offset
<= MAX_ARGUMENT_SLOTS
)
3849 return MAX_ARGUMENT_SLOTS
- cum
->words
- offset
;
3852 /* Update CUM to point after this argument. This is patterned after
3853 ia64_function_arg. */
3856 ia64_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
3857 tree type
, int named
)
3859 int words
= ia64_function_arg_words (type
, mode
);
3860 int offset
= ia64_function_arg_offset (cum
, type
, words
);
3861 enum machine_mode hfa_mode
= VOIDmode
;
3863 /* If all arg slots are already full, then there is nothing to do. */
3864 if (cum
->words
>= MAX_ARGUMENT_SLOTS
)
3867 cum
->words
+= words
+ offset
;
3869 /* Check for and handle homogeneous FP aggregates. */
3871 hfa_mode
= hfa_element_mode (type
, 0);
3873 /* Unnamed prototyped hfas are passed as usual. Named prototyped hfas
3874 and unprototyped hfas are passed specially. */
3875 if (hfa_mode
!= VOIDmode
&& (! cum
->prototype
|| named
))
3877 int fp_regs
= cum
->fp_regs
;
3878 /* This is the original value of cum->words + offset. */
3879 int int_regs
= cum
->words
- words
;
3880 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
3884 /* If prototyped, pass it in FR regs then GR regs.
3885 If not prototyped, pass it in both FR and GR regs.
3887 If this is an SFmode aggregate, then it is possible to run out of
3888 FR regs while GR regs are still left. In that case, we pass the
3889 remaining part in the GR regs. */
3891 /* Fill the FP regs. We do this always. We stop if we reach the end
3892 of the argument, the last FP register, or the last argument slot. */
3894 byte_size
= ((mode
== BLKmode
)
3895 ? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
));
3896 args_byte_size
= int_regs
* UNITS_PER_WORD
;
3898 for (; (offset
< byte_size
&& fp_regs
< MAX_ARGUMENT_SLOTS
3899 && args_byte_size
< (MAX_ARGUMENT_SLOTS
* UNITS_PER_WORD
));)
3902 args_byte_size
+= hfa_size
;
3906 cum
->fp_regs
= fp_regs
;
3909 /* Integral and aggregates go in general registers. If we have run out of
3910 FR registers, then FP values must also go in general registers. This can
3911 happen when we have a SFmode HFA. */
3912 else if (! FLOAT_MODE_P (mode
) || cum
->fp_regs
== MAX_ARGUMENT_SLOTS
)
3913 cum
->int_regs
= cum
->words
;
3915 /* If there is a prototype, then FP values go in a FR register when
3916 named, and in a GR register when unnamed. */
3917 else if (cum
->prototype
)
3920 cum
->int_regs
= cum
->words
;
3922 /* ??? Complex types should not reach here. */
3923 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3925 /* If there is no prototype, then FP values go in both FR and GR
3929 /* ??? Complex types should not reach here. */
3930 cum
->fp_regs
+= (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
? 2 : 1);
3931 cum
->int_regs
= cum
->words
;
3935 /* Variable sized types are passed by reference. */
3936 /* ??? At present this is a GCC extension to the IA-64 ABI. */
3939 ia64_function_arg_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
3940 enum machine_mode mode ATTRIBUTE_UNUSED
,
3941 tree type
, int named ATTRIBUTE_UNUSED
)
3943 return type
&& TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
;
3946 /* True if it is OK to do sibling call optimization for the specified
3947 call expression EXP. DECL will be the called function, or NULL if
3948 this is an indirect call. */
3950 ia64_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
3952 /* We must always return with our current GP. This means we can
3953 only sibcall to functions defined in the current module. */
3954 return decl
&& (*targetm
.binds_local_p
) (decl
);
3958 /* Implement va_arg. */
3961 ia64_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
, tree
*post_p
)
3963 /* Variable sized types are passed by reference. */
3964 if (TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
3966 tree ptrtype
= build_pointer_type (type
);
3967 tree addr
= std_gimplify_va_arg_expr (valist
, ptrtype
, pre_p
, post_p
);
3968 return build_fold_indirect_ref (addr
);
3971 /* Aggregate arguments with alignment larger than 8 bytes start at
3972 the next even boundary. Integer and floating point arguments
3973 do so if they are larger than 8 bytes, whether or not they are
3974 also aligned larger than 8 bytes. */
3975 if ((TREE_CODE (type
) == REAL_TYPE
|| TREE_CODE (type
) == INTEGER_TYPE
)
3976 ? int_size_in_bytes (type
) > 8 : TYPE_ALIGN (type
) > 8 * BITS_PER_UNIT
)
3978 tree t
= build (PLUS_EXPR
, TREE_TYPE (valist
), valist
,
3979 build_int_2 (2 * UNITS_PER_WORD
- 1, 0));
3980 t
= build (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
3981 build_int_2 (-2 * UNITS_PER_WORD
, -1));
3982 t
= build (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
3983 gimplify_and_add (t
, pre_p
);
3986 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
3989 /* Return 1 if function return value returned in memory. Return 0 if it is
3993 ia64_return_in_memory (tree valtype
, tree fntype ATTRIBUTE_UNUSED
)
3995 enum machine_mode mode
;
3996 enum machine_mode hfa_mode
;
3997 HOST_WIDE_INT byte_size
;
3999 mode
= TYPE_MODE (valtype
);
4000 byte_size
= GET_MODE_SIZE (mode
);
4001 if (mode
== BLKmode
)
4003 byte_size
= int_size_in_bytes (valtype
);
4008 /* Hfa's with up to 8 elements are returned in the FP argument registers. */
4010 hfa_mode
= hfa_element_mode (valtype
, 0);
4011 if (hfa_mode
!= VOIDmode
)
4013 int hfa_size
= GET_MODE_SIZE (hfa_mode
);
4015 if (byte_size
/ hfa_size
> MAX_ARGUMENT_SLOTS
)
4020 else if (byte_size
> UNITS_PER_WORD
* MAX_INT_RETURN_SLOTS
)
4026 /* Return rtx for register that holds the function return value. */
4029 ia64_function_value (tree valtype
, tree func ATTRIBUTE_UNUSED
)
4031 enum machine_mode mode
;
4032 enum machine_mode hfa_mode
;
4034 mode
= TYPE_MODE (valtype
);
4035 hfa_mode
= hfa_element_mode (valtype
, 0);
4037 if (hfa_mode
!= VOIDmode
)
4045 hfa_size
= GET_MODE_SIZE (hfa_mode
);
4046 byte_size
= ((mode
== BLKmode
)
4047 ? int_size_in_bytes (valtype
) : GET_MODE_SIZE (mode
));
4049 for (i
= 0; offset
< byte_size
; i
++)
4051 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4052 gen_rtx_REG (hfa_mode
, FR_ARG_FIRST
+ i
),
4058 return XEXP (loc
[0], 0);
4060 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4062 else if (FLOAT_TYPE_P (valtype
) && mode
!= TFmode
&& mode
!= TCmode
)
4063 return gen_rtx_REG (mode
, FR_ARG_FIRST
);
4066 if (BYTES_BIG_ENDIAN
4067 && (mode
== BLKmode
|| (valtype
&& AGGREGATE_TYPE_P (valtype
))))
4075 bytesize
= int_size_in_bytes (valtype
);
4076 for (i
= 0; offset
< bytesize
; i
++)
4078 loc
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
4079 gen_rtx_REG (DImode
,
4082 offset
+= UNITS_PER_WORD
;
4084 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (i
, loc
));
4087 return gen_rtx_REG (mode
, GR_RET_FIRST
);
4091 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
4092 We need to emit DTP-relative relocations. */
4095 ia64_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4099 fputs ("\tdata8.ua\t@dtprel(", file
);
4100 output_addr_const (file
, x
);
4104 /* Print a memory address as an operand to reference that memory location. */
4106 /* ??? Do we need this? It gets used only for 'a' operands. We could perhaps
4107 also call this from ia64_print_operand for memory addresses. */
4110 ia64_print_operand_address (FILE * stream ATTRIBUTE_UNUSED
,
4111 rtx address ATTRIBUTE_UNUSED
)
4115 /* Print an operand to an assembler instruction.
4116 C Swap and print a comparison operator.
4117 D Print an FP comparison operator.
4118 E Print 32 - constant, for SImode shifts as extract.
4119 e Print 64 - constant, for DImode rotates.
4120 F A floating point constant 0.0 emitted as f0, or 1.0 emitted as f1, or
4121 a floating point register emitted normally.
4122 I Invert a predicate register by adding 1.
4123 J Select the proper predicate register for a condition.
4124 j Select the inverse predicate register for a condition.
4125 O Append .acq for volatile load.
4126 P Postincrement of a MEM.
4127 Q Append .rel for volatile store.
4128 S Shift amount for shladd instruction.
4129 T Print an 8-bit sign extended number (K) as a 32-bit unsigned number
4130 for Intel assembler.
4131 U Print an 8-bit sign extended number (K) as a 64-bit unsigned number
4132 for Intel assembler.
4133 r Print register name, or constant 0 as r0. HP compatibility for
4136 ia64_print_operand (FILE * file
, rtx x
, int code
)
4143 /* Handled below. */
4148 enum rtx_code c
= swap_condition (GET_CODE (x
));
4149 fputs (GET_RTX_NAME (c
), file
);
4154 switch (GET_CODE (x
))
4166 str
= GET_RTX_NAME (GET_CODE (x
));
4173 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
4177 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, 64 - INTVAL (x
));
4181 if (x
== CONST0_RTX (GET_MODE (x
)))
4182 str
= reg_names
[FR_REG (0)];
4183 else if (x
== CONST1_RTX (GET_MODE (x
)))
4184 str
= reg_names
[FR_REG (1)];
4185 else if (GET_CODE (x
) == REG
)
4186 str
= reg_names
[REGNO (x
)];
4193 fputs (reg_names
[REGNO (x
) + 1], file
);
4199 unsigned int regno
= REGNO (XEXP (x
, 0));
4200 if (GET_CODE (x
) == EQ
)
4204 fputs (reg_names
[regno
], file
);
4209 if (MEM_VOLATILE_P (x
))
4210 fputs(".acq", file
);
4215 HOST_WIDE_INT value
;
4217 switch (GET_CODE (XEXP (x
, 0)))
4223 x
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
4224 if (GET_CODE (x
) == CONST_INT
)
4226 else if (GET_CODE (x
) == REG
)
4228 fprintf (file
, ", %s", reg_names
[REGNO (x
)]);
4236 value
= GET_MODE_SIZE (GET_MODE (x
));
4240 value
= - (HOST_WIDE_INT
) GET_MODE_SIZE (GET_MODE (x
));
4244 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
, value
);
4249 if (MEM_VOLATILE_P (x
))
4250 fputs(".rel", file
);
4254 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
4258 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4260 fprintf (file
, "0x%x", (int) INTVAL (x
) & 0xffffffff);
4266 if (! TARGET_GNU_AS
&& GET_CODE (x
) == CONST_INT
)
4268 const char *prefix
= "0x";
4269 if (INTVAL (x
) & 0x80000000)
4271 fprintf (file
, "0xffffffff");
4274 fprintf (file
, "%s%x", prefix
, (int) INTVAL (x
) & 0xffffffff);
4280 /* If this operand is the constant zero, write it as register zero.
4281 Any register, zero, or CONST_INT value is OK here. */
4282 if (GET_CODE (x
) == REG
)
4283 fputs (reg_names
[REGNO (x
)], file
);
4284 else if (x
== CONST0_RTX (GET_MODE (x
)))
4286 else if (GET_CODE (x
) == CONST_INT
)
4287 output_addr_const (file
, x
);
4289 output_operand_lossage ("invalid %%r value");
4296 /* For conditional branches, returns or calls, substitute
4297 sptk, dptk, dpnt, or spnt for %s. */
4298 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
4301 int pred_val
= INTVAL (XEXP (x
, 0));
4303 /* Guess top and bottom 10% statically predicted. */
4304 if (pred_val
< REG_BR_PROB_BASE
/ 50)
4306 else if (pred_val
< REG_BR_PROB_BASE
/ 2)
4308 else if (pred_val
< REG_BR_PROB_BASE
/ 100 * 98)
4313 else if (GET_CODE (current_output_insn
) == CALL_INSN
)
4318 fputs (which
, file
);
4323 x
= current_insn_predicate
;
4326 unsigned int regno
= REGNO (XEXP (x
, 0));
4327 if (GET_CODE (x
) == EQ
)
4329 fprintf (file
, "(%s) ", reg_names
[regno
]);
4334 output_operand_lossage ("ia64_print_operand: unknown code");
4338 switch (GET_CODE (x
))
4340 /* This happens for the spill/restore instructions. */
4345 /* ... fall through ... */
4348 fputs (reg_names
[REGNO (x
)], file
);
4353 rtx addr
= XEXP (x
, 0);
4354 if (GET_RTX_CLASS (GET_CODE (addr
)) == RTX_AUTOINC
)
4355 addr
= XEXP (addr
, 0);
4356 fprintf (file
, "[%s]", reg_names
[REGNO (addr
)]);
4361 output_addr_const (file
, x
);
4368 /* Compute a (partial) cost for rtx X. Return true if the complete
4369 cost has been computed, and false if subexpressions should be
4370 scanned. In either case, *TOTAL contains the cost result. */
4371 /* ??? This is incomplete. */
4374 ia64_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
4382 *total
= CONST_OK_FOR_J (INTVAL (x
)) ? 0 : COSTS_N_INSNS (1);
4385 if (CONST_OK_FOR_I (INTVAL (x
)))
4387 else if (CONST_OK_FOR_J (INTVAL (x
)))
4390 *total
= COSTS_N_INSNS (1);
4393 if (CONST_OK_FOR_K (INTVAL (x
)) || CONST_OK_FOR_L (INTVAL (x
)))
4396 *total
= COSTS_N_INSNS (1);
4401 *total
= COSTS_N_INSNS (1);
4407 *total
= COSTS_N_INSNS (3);
4411 /* For multiplies wider than HImode, we have to go to the FPU,
4412 which normally involves copies. Plus there's the latency
4413 of the multiply itself, and the latency of the instructions to
4414 transfer integer regs to FP regs. */
4415 /* ??? Check for FP mode. */
4416 if (GET_MODE_SIZE (GET_MODE (x
)) > 2)
4417 *total
= COSTS_N_INSNS (10);
4419 *total
= COSTS_N_INSNS (2);
4427 *total
= COSTS_N_INSNS (1);
4434 /* We make divide expensive, so that divide-by-constant will be
4435 optimized to a multiply. */
4436 *total
= COSTS_N_INSNS (60);
4444 /* Calculate the cost of moving data from a register in class FROM to
4445 one in class TO, using MODE. */
4448 ia64_register_move_cost (enum machine_mode mode
, enum reg_class from
,
4451 /* ADDL_REGS is the same as GR_REGS for movement purposes. */
4452 if (to
== ADDL_REGS
)
4454 if (from
== ADDL_REGS
)
4457 /* All costs are symmetric, so reduce cases by putting the
4458 lower number class as the destination. */
4461 enum reg_class tmp
= to
;
4462 to
= from
, from
= tmp
;
4465 /* Moving from FR<->GR in XFmode must be more expensive than 2,
4466 so that we get secondary memory reloads. Between FR_REGS,
4467 we have to make this at least as expensive as MEMORY_MOVE_COST
4468 to avoid spectacularly poor register class preferencing. */
4471 if (to
!= GR_REGS
|| from
!= GR_REGS
)
4472 return MEMORY_MOVE_COST (mode
, to
, 0);
4480 /* Moving between PR registers takes two insns. */
4481 if (from
== PR_REGS
)
4483 /* Moving between PR and anything but GR is impossible. */
4484 if (from
!= GR_REGS
)
4485 return MEMORY_MOVE_COST (mode
, to
, 0);
4489 /* Moving between BR and anything but GR is impossible. */
4490 if (from
!= GR_REGS
&& from
!= GR_AND_BR_REGS
)
4491 return MEMORY_MOVE_COST (mode
, to
, 0);
4496 /* Moving between AR and anything but GR is impossible. */
4497 if (from
!= GR_REGS
)
4498 return MEMORY_MOVE_COST (mode
, to
, 0);
4503 case GR_AND_FR_REGS
:
4504 case GR_AND_BR_REGS
:
4515 /* This function returns the register class required for a secondary
4516 register when copying between one of the registers in CLASS, and X,
4517 using MODE. A return value of NO_REGS means that no secondary register
4521 ia64_secondary_reload_class (enum reg_class
class,
4522 enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
4526 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
4527 regno
= true_regnum (x
);
4534 /* ??? BR<->BR register copies can happen due to a bad gcse/cse/global
4535 interaction. We end up with two pseudos with overlapping lifetimes
4536 both of which are equiv to the same constant, and both which need
4537 to be in BR_REGS. This seems to be a cse bug. cse_basic_block_end
4538 changes depending on the path length, which means the qty_first_reg
4539 check in make_regs_eqv can give different answers at different times.
4540 At some point I'll probably need a reload_indi pattern to handle
4543 We can also get GR_AND_FR_REGS to BR_REGS/AR_REGS copies, where we
4544 wound up with a FP register from GR_AND_FR_REGS. Extend that to all
4545 non-general registers for good measure. */
4546 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
))
4549 /* This is needed if a pseudo used as a call_operand gets spilled to a
4551 if (GET_CODE (x
) == MEM
)
4556 /* Need to go through general registers to get to other class regs. */
4557 if (regno
>= 0 && ! (FR_REGNO_P (regno
) || GENERAL_REGNO_P (regno
)))
4560 /* This can happen when a paradoxical subreg is an operand to the
4562 /* ??? This shouldn't be necessary after instruction scheduling is
4563 enabled, because paradoxical subregs are not accepted by
4564 register_operand when INSN_SCHEDULING is defined. Or alternatively,
4565 stop the paradoxical subreg stupidity in the *_operand functions
4567 if (GET_CODE (x
) == MEM
4568 && (GET_MODE (x
) == SImode
|| GET_MODE (x
) == HImode
4569 || GET_MODE (x
) == QImode
))
4572 /* This can happen because of the ior/and/etc patterns that accept FP
4573 registers as operands. If the third operand is a constant, then it
4574 needs to be reloaded into a FP register. */
4575 if (GET_CODE (x
) == CONST_INT
)
4578 /* This can happen because of register elimination in a muldi3 insn.
4579 E.g. `26107 * (unsigned long)&u'. */
4580 if (GET_CODE (x
) == PLUS
)
4585 /* ??? This happens if we cse/gcse a BImode value across a call,
4586 and the function has a nonlocal goto. This is because global
4587 does not allocate call crossing pseudos to hard registers when
4588 current_function_has_nonlocal_goto is true. This is relatively
4589 common for C++ programs that use exceptions. To reproduce,
4590 return NO_REGS and compile libstdc++. */
4591 if (GET_CODE (x
) == MEM
)
4594 /* This can happen when we take a BImode subreg of a DImode value,
4595 and that DImode value winds up in some non-GR register. */
4596 if (regno
>= 0 && ! GENERAL_REGNO_P (regno
) && ! PR_REGNO_P (regno
))
4608 /* Emit text to declare externally defined variables and functions, because
4609 the Intel assembler does not support undefined externals. */
4612 ia64_asm_output_external (FILE *file
, tree decl
, const char *name
)
4614 int save_referenced
;
4616 /* GNU as does not need anything here, but the HP linker does need
4617 something for external functions. */
4621 || TREE_CODE (decl
) != FUNCTION_DECL
4622 || strstr (name
, "__builtin_") == name
))
4625 /* ??? The Intel assembler creates a reference that needs to be satisfied by
4626 the linker when we do this, so we need to be careful not to do this for
4627 builtin functions which have no library equivalent. Unfortunately, we
4628 can't tell here whether or not a function will actually be called by
4629 expand_expr, so we pull in library functions even if we may not need
4631 if (! strcmp (name
, "__builtin_next_arg")
4632 || ! strcmp (name
, "alloca")
4633 || ! strcmp (name
, "__builtin_constant_p")
4634 || ! strcmp (name
, "__builtin_args_info"))
4638 ia64_hpux_add_extern_decl (decl
);
4641 /* assemble_name will set TREE_SYMBOL_REFERENCED, so we must save and
4643 save_referenced
= TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
));
4644 if (TREE_CODE (decl
) == FUNCTION_DECL
)
4645 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
4646 (*targetm
.asm_out
.globalize_label
) (file
, name
);
4647 TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)) = save_referenced
;
4651 /* Parse the -mfixed-range= option string. */
4654 fix_range (const char *const_str
)
4657 char *str
, *dash
, *comma
;
4659 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
4660 REG2 are either register names or register numbers. The effect
4661 of this option is to mark the registers in the range from REG1 to
4662 REG2 as ``fixed'' so they won't be used by the compiler. This is
4663 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
4665 i
= strlen (const_str
);
4666 str
= (char *) alloca (i
+ 1);
4667 memcpy (str
, const_str
, i
+ 1);
4671 dash
= strchr (str
, '-');
4674 warning ("value of -mfixed-range must have form REG1-REG2");
4679 comma
= strchr (dash
+ 1, ',');
4683 first
= decode_reg_name (str
);
4686 warning ("unknown register name: %s", str
);
4690 last
= decode_reg_name (dash
+ 1);
4693 warning ("unknown register name: %s", dash
+ 1);
4701 warning ("%s-%s is an empty range", str
, dash
+ 1);
4705 for (i
= first
; i
<= last
; ++i
)
4706 fixed_regs
[i
] = call_used_regs
[i
] = 1;
4716 static struct machine_function
*
4717 ia64_init_machine_status (void)
4719 return ggc_alloc_cleared (sizeof (struct machine_function
));
4722 /* Handle TARGET_OPTIONS switches. */
4725 ia64_override_options (void)
4729 const char *const name
; /* processor name or nickname. */
4730 const enum processor_type processor
;
4732 const processor_alias_table
[] =
4734 {"itanium", PROCESSOR_ITANIUM
},
4735 {"itanium1", PROCESSOR_ITANIUM
},
4736 {"merced", PROCESSOR_ITANIUM
},
4737 {"itanium2", PROCESSOR_ITANIUM2
},
4738 {"mckinley", PROCESSOR_ITANIUM2
},
4741 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
4744 if (TARGET_AUTO_PIC
)
4745 target_flags
|= MASK_CONST_GP
;
4747 if (TARGET_INLINE_FLOAT_DIV_LAT
&& TARGET_INLINE_FLOAT_DIV_THR
)
4749 if ((target_flags_explicit
& MASK_INLINE_FLOAT_DIV_LAT
)
4750 && (target_flags_explicit
& MASK_INLINE_FLOAT_DIV_THR
))
4752 warning ("cannot optimize floating point division for both latency and throughput");
4753 target_flags
&= ~MASK_INLINE_FLOAT_DIV_THR
;
4757 if (target_flags_explicit
& MASK_INLINE_FLOAT_DIV_THR
)
4758 target_flags
&= ~MASK_INLINE_FLOAT_DIV_LAT
;
4760 target_flags
&= ~MASK_INLINE_FLOAT_DIV_THR
;
4764 if (TARGET_INLINE_INT_DIV_LAT
&& TARGET_INLINE_INT_DIV_THR
)
4766 if ((target_flags_explicit
& MASK_INLINE_INT_DIV_LAT
)
4767 && (target_flags_explicit
& MASK_INLINE_INT_DIV_THR
))
4769 warning ("cannot optimize integer division for both latency and throughput");
4770 target_flags
&= ~MASK_INLINE_INT_DIV_THR
;
4774 if (target_flags_explicit
& MASK_INLINE_INT_DIV_THR
)
4775 target_flags
&= ~MASK_INLINE_INT_DIV_LAT
;
4777 target_flags
&= ~MASK_INLINE_INT_DIV_THR
;
4781 if (TARGET_INLINE_SQRT_LAT
&& TARGET_INLINE_SQRT_THR
)
4783 if ((target_flags_explicit
& MASK_INLINE_SQRT_LAT
)
4784 && (target_flags_explicit
& MASK_INLINE_SQRT_THR
))
4786 warning ("cannot optimize square root for both latency and throughput");
4787 target_flags
&= ~MASK_INLINE_SQRT_THR
;
4791 if (target_flags_explicit
& MASK_INLINE_SQRT_THR
)
4792 target_flags
&= ~MASK_INLINE_SQRT_LAT
;
4794 target_flags
&= ~MASK_INLINE_SQRT_THR
;
4798 if (TARGET_INLINE_SQRT_LAT
)
4800 warning ("not yet implemented: latency-optimized inline square root");
4801 target_flags
&= ~MASK_INLINE_SQRT_LAT
;
4804 if (ia64_fixed_range_string
)
4805 fix_range (ia64_fixed_range_string
);
4807 if (ia64_tls_size_string
)
4810 unsigned long tmp
= strtoul (ia64_tls_size_string
, &end
, 10);
4811 if (*end
|| (tmp
!= 14 && tmp
!= 22 && tmp
!= 64))
4812 error ("bad value (%s) for -mtls-size= switch", ia64_tls_size_string
);
4814 ia64_tls_size
= tmp
;
4817 if (!ia64_tune_string
)
4818 ia64_tune_string
= "itanium2";
4820 for (i
= 0; i
< pta_size
; i
++)
4821 if (! strcmp (ia64_tune_string
, processor_alias_table
[i
].name
))
4823 ia64_tune
= processor_alias_table
[i
].processor
;
4828 error ("bad value (%s) for -tune= switch", ia64_tune_string
);
4830 ia64_flag_schedule_insns2
= flag_schedule_insns_after_reload
;
4831 flag_schedule_insns_after_reload
= 0;
4833 /* Variable tracking should be run after all optimizations which change order
4834 of insns. It also needs a valid CFG. */
4835 ia64_flag_var_tracking
= flag_var_tracking
;
4836 flag_var_tracking
= 0;
4838 ia64_section_threshold
= g_switch_set
? g_switch_value
: IA64_DEFAULT_GVALUE
;
4840 init_machine_status
= ia64_init_machine_status
;
4843 static enum attr_itanium_class
ia64_safe_itanium_class (rtx
);
4844 static enum attr_type
ia64_safe_type (rtx
);
4846 static enum attr_itanium_class
4847 ia64_safe_itanium_class (rtx insn
)
4849 if (recog_memoized (insn
) >= 0)
4850 return get_attr_itanium_class (insn
);
4852 return ITANIUM_CLASS_UNKNOWN
;
4855 static enum attr_type
4856 ia64_safe_type (rtx insn
)
4858 if (recog_memoized (insn
) >= 0)
4859 return get_attr_type (insn
);
4861 return TYPE_UNKNOWN
;
4864 /* The following collection of routines emit instruction group stop bits as
4865 necessary to avoid dependencies. */
4867 /* Need to track some additional registers as far as serialization is
4868 concerned so we can properly handle br.call and br.ret. We could
4869 make these registers visible to gcc, but since these registers are
4870 never explicitly used in gcc generated code, it seems wasteful to
4871 do so (plus it would make the call and return patterns needlessly
4873 #define REG_RP (BR_REG (0))
4874 #define REG_AR_CFM (FIRST_PSEUDO_REGISTER + 1)
4875 /* This is used for volatile asms which may require a stop bit immediately
4876 before and after them. */
4877 #define REG_VOLATILE (FIRST_PSEUDO_REGISTER + 2)
4878 #define AR_UNAT_BIT_0 (FIRST_PSEUDO_REGISTER + 3)
4879 #define NUM_REGS (AR_UNAT_BIT_0 + 64)
4881 /* For each register, we keep track of how it has been written in the
4882 current instruction group.
4884 If a register is written unconditionally (no qualifying predicate),
4885 WRITE_COUNT is set to 2 and FIRST_PRED is ignored.
4887 If a register is written if its qualifying predicate P is true, we
4888 set WRITE_COUNT to 1 and FIRST_PRED to P. Later on, the same register
4889 may be written again by the complement of P (P^1) and when this happens,
4890 WRITE_COUNT gets set to 2.
4892 The result of this is that whenever an insn attempts to write a register
4893 whose WRITE_COUNT is two, we need to issue an insn group barrier first.
4895 If a predicate register is written by a floating-point insn, we set
4896 WRITTEN_BY_FP to true.
4898 If a predicate register is written by an AND.ORCM we set WRITTEN_BY_AND
4899 to true; if it was written by an OR.ANDCM we set WRITTEN_BY_OR to true. */
4901 struct reg_write_state
4903 unsigned int write_count
: 2;
4904 unsigned int first_pred
: 16;
4905 unsigned int written_by_fp
: 1;
4906 unsigned int written_by_and
: 1;
4907 unsigned int written_by_or
: 1;
4910 /* Cumulative info for the current instruction group. */
4911 struct reg_write_state rws_sum
[NUM_REGS
];
4912 /* Info for the current instruction. This gets copied to rws_sum after a
4913 stop bit is emitted. */
4914 struct reg_write_state rws_insn
[NUM_REGS
];
4916 /* Indicates whether this is the first instruction after a stop bit,
4917 in which case we don't need another stop bit. Without this, we hit
4918 the abort in ia64_variable_issue when scheduling an alloc. */
4919 static int first_instruction
;
4921 /* Misc flags needed to compute RAW/WAW dependencies while we are traversing
4922 RTL for one instruction. */
4925 unsigned int is_write
: 1; /* Is register being written? */
4926 unsigned int is_fp
: 1; /* Is register used as part of an fp op? */
4927 unsigned int is_branch
: 1; /* Is register used as part of a branch? */
4928 unsigned int is_and
: 1; /* Is register used as part of and.orcm? */
4929 unsigned int is_or
: 1; /* Is register used as part of or.andcm? */
4930 unsigned int is_sibcall
: 1; /* Is this a sibling or normal call? */
4933 static void rws_update (struct reg_write_state
*, int, struct reg_flags
, int);
4934 static int rws_access_regno (int, struct reg_flags
, int);
4935 static int rws_access_reg (rtx
, struct reg_flags
, int);
4936 static void update_set_flags (rtx
, struct reg_flags
*, int *, rtx
*);
4937 static int set_src_needs_barrier (rtx
, struct reg_flags
, int, rtx
);
4938 static int rtx_needs_barrier (rtx
, struct reg_flags
, int);
4939 static void init_insn_group_barriers (void);
4940 static int group_barrier_needed_p (rtx
);
4941 static int safe_group_barrier_needed_p (rtx
);
4943 /* Update *RWS for REGNO, which is being written by the current instruction,
4944 with predicate PRED, and associated register flags in FLAGS. */
4947 rws_update (struct reg_write_state
*rws
, int regno
, struct reg_flags flags
, int pred
)
4950 rws
[regno
].write_count
++;
4952 rws
[regno
].write_count
= 2;
4953 rws
[regno
].written_by_fp
|= flags
.is_fp
;
4954 /* ??? Not tracking and/or across differing predicates. */
4955 rws
[regno
].written_by_and
= flags
.is_and
;
4956 rws
[regno
].written_by_or
= flags
.is_or
;
4957 rws
[regno
].first_pred
= pred
;
4960 /* Handle an access to register REGNO of type FLAGS using predicate register
4961 PRED. Update rws_insn and rws_sum arrays. Return 1 if this access creates
4962 a dependency with an earlier instruction in the same group. */
4965 rws_access_regno (int regno
, struct reg_flags flags
, int pred
)
4967 int need_barrier
= 0;
4969 if (regno
>= NUM_REGS
)
4972 if (! PR_REGNO_P (regno
))
4973 flags
.is_and
= flags
.is_or
= 0;
4979 /* One insn writes same reg multiple times? */
4980 if (rws_insn
[regno
].write_count
> 0)
4983 /* Update info for current instruction. */
4984 rws_update (rws_insn
, regno
, flags
, pred
);
4985 write_count
= rws_sum
[regno
].write_count
;
4987 switch (write_count
)
4990 /* The register has not been written yet. */
4991 rws_update (rws_sum
, regno
, flags
, pred
);
4995 /* The register has been written via a predicate. If this is
4996 not a complementary predicate, then we need a barrier. */
4997 /* ??? This assumes that P and P+1 are always complementary
4998 predicates for P even. */
4999 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5001 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5003 else if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
5005 rws_update (rws_sum
, regno
, flags
, pred
);
5009 /* The register has been unconditionally written already. We
5011 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5013 else if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5017 rws_sum
[regno
].written_by_and
= flags
.is_and
;
5018 rws_sum
[regno
].written_by_or
= flags
.is_or
;
5027 if (flags
.is_branch
)
5029 /* Branches have several RAW exceptions that allow to avoid
5032 if (REGNO_REG_CLASS (regno
) == BR_REGS
|| regno
== AR_PFS_REGNUM
)
5033 /* RAW dependencies on branch regs are permissible as long
5034 as the writer is a non-branch instruction. Since we
5035 never generate code that uses a branch register written
5036 by a branch instruction, handling this case is
5040 if (REGNO_REG_CLASS (regno
) == PR_REGS
5041 && ! rws_sum
[regno
].written_by_fp
)
5042 /* The predicates of a branch are available within the
5043 same insn group as long as the predicate was written by
5044 something other than a floating-point instruction. */
5048 if (flags
.is_and
&& rws_sum
[regno
].written_by_and
)
5050 if (flags
.is_or
&& rws_sum
[regno
].written_by_or
)
5053 switch (rws_sum
[regno
].write_count
)
5056 /* The register has not been written yet. */
5060 /* The register has been written via a predicate. If this is
5061 not a complementary predicate, then we need a barrier. */
5062 /* ??? This assumes that P and P+1 are always complementary
5063 predicates for P even. */
5064 if ((rws_sum
[regno
].first_pred
^ 1) != pred
)
5069 /* The register has been unconditionally written already. We
5079 return need_barrier
;
5083 rws_access_reg (rtx reg
, struct reg_flags flags
, int pred
)
5085 int regno
= REGNO (reg
);
5086 int n
= HARD_REGNO_NREGS (REGNO (reg
), GET_MODE (reg
));
5089 return rws_access_regno (regno
, flags
, pred
);
5092 int need_barrier
= 0;
5094 need_barrier
|= rws_access_regno (regno
+ n
, flags
, pred
);
5095 return need_barrier
;
5099 /* Examine X, which is a SET rtx, and update the flags, the predicate, and
5100 the condition, stored in *PFLAGS, *PPRED and *PCOND. */
5103 update_set_flags (rtx x
, struct reg_flags
*pflags
, int *ppred
, rtx
*pcond
)
5105 rtx src
= SET_SRC (x
);
5109 switch (GET_CODE (src
))
5115 if (SET_DEST (x
) == pc_rtx
)
5116 /* X is a conditional branch. */
5120 int is_complemented
= 0;
5122 /* X is a conditional move. */
5123 rtx cond
= XEXP (src
, 0);
5124 if (GET_CODE (cond
) == EQ
)
5125 is_complemented
= 1;
5126 cond
= XEXP (cond
, 0);
5127 if (GET_CODE (cond
) != REG
5128 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
5131 if (XEXP (src
, 1) == SET_DEST (x
)
5132 || XEXP (src
, 2) == SET_DEST (x
))
5134 /* X is a conditional move that conditionally writes the
5137 /* We need another complement in this case. */
5138 if (XEXP (src
, 1) == SET_DEST (x
))
5139 is_complemented
= ! is_complemented
;
5141 *ppred
= REGNO (cond
);
5142 if (is_complemented
)
5146 /* ??? If this is a conditional write to the dest, then this
5147 instruction does not actually read one source. This probably
5148 doesn't matter, because that source is also the dest. */
5149 /* ??? Multiple writes to predicate registers are allowed
5150 if they are all AND type compares, or if they are all OR
5151 type compares. We do not generate such instructions
5154 /* ... fall through ... */
5157 if (COMPARISON_P (src
)
5158 && GET_MODE_CLASS (GET_MODE (XEXP (src
, 0))) == MODE_FLOAT
)
5159 /* Set pflags->is_fp to 1 so that we know we're dealing
5160 with a floating point comparison when processing the
5161 destination of the SET. */
5164 /* Discover if this is a parallel comparison. We only handle
5165 and.orcm and or.andcm at present, since we must retain a
5166 strict inverse on the predicate pair. */
5167 else if (GET_CODE (src
) == AND
)
5169 else if (GET_CODE (src
) == IOR
)
5176 /* Subroutine of rtx_needs_barrier; this function determines whether the
5177 source of a given SET rtx found in X needs a barrier. FLAGS and PRED
5178 are as in rtx_needs_barrier. COND is an rtx that holds the condition
5182 set_src_needs_barrier (rtx x
, struct reg_flags flags
, int pred
, rtx cond
)
5184 int need_barrier
= 0;
5186 rtx src
= SET_SRC (x
);
5188 if (GET_CODE (src
) == CALL
)
5189 /* We don't need to worry about the result registers that
5190 get written by subroutine call. */
5191 return rtx_needs_barrier (src
, flags
, pred
);
5192 else if (SET_DEST (x
) == pc_rtx
)
5194 /* X is a conditional branch. */
5195 /* ??? This seems redundant, as the caller sets this bit for
5197 flags
.is_branch
= 1;
5198 return rtx_needs_barrier (src
, flags
, pred
);
5201 need_barrier
= rtx_needs_barrier (src
, flags
, pred
);
5203 /* This instruction unconditionally uses a predicate register. */
5205 need_barrier
|= rws_access_reg (cond
, flags
, 0);
5208 if (GET_CODE (dst
) == ZERO_EXTRACT
)
5210 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 1), flags
, pred
);
5211 need_barrier
|= rtx_needs_barrier (XEXP (dst
, 2), flags
, pred
);
5212 dst
= XEXP (dst
, 0);
5214 return need_barrier
;
5217 /* Handle an access to rtx X of type FLAGS using predicate register
5218 PRED. Return 1 if this access creates a dependency with an earlier
5219 instruction in the same group. */
5222 rtx_needs_barrier (rtx x
, struct reg_flags flags
, int pred
)
5225 int is_complemented
= 0;
5226 int need_barrier
= 0;
5227 const char *format_ptr
;
5228 struct reg_flags new_flags
;
5236 switch (GET_CODE (x
))
5239 update_set_flags (x
, &new_flags
, &pred
, &cond
);
5240 need_barrier
= set_src_needs_barrier (x
, new_flags
, pred
, cond
);
5241 if (GET_CODE (SET_SRC (x
)) != CALL
)
5243 new_flags
.is_write
= 1;
5244 need_barrier
|= rtx_needs_barrier (SET_DEST (x
), new_flags
, pred
);
5249 new_flags
.is_write
= 0;
5250 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5252 /* Avoid multiple register writes, in case this is a pattern with
5253 multiple CALL rtx. This avoids an abort in rws_access_reg. */
5254 if (! flags
.is_sibcall
&& ! rws_insn
[REG_AR_CFM
].write_count
)
5256 new_flags
.is_write
= 1;
5257 need_barrier
|= rws_access_regno (REG_RP
, new_flags
, pred
);
5258 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, new_flags
, pred
);
5259 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5264 /* X is a predicated instruction. */
5266 cond
= COND_EXEC_TEST (x
);
5269 need_barrier
= rtx_needs_barrier (cond
, flags
, 0);
5271 if (GET_CODE (cond
) == EQ
)
5272 is_complemented
= 1;
5273 cond
= XEXP (cond
, 0);
5274 if (GET_CODE (cond
) != REG
5275 && REGNO_REG_CLASS (REGNO (cond
)) != PR_REGS
)
5277 pred
= REGNO (cond
);
5278 if (is_complemented
)
5281 need_barrier
|= rtx_needs_barrier (COND_EXEC_CODE (x
), flags
, pred
);
5282 return need_barrier
;
5286 /* Clobber & use are for earlier compiler-phases only. */
5291 /* We always emit stop bits for traditional asms. We emit stop bits
5292 for volatile extended asms if TARGET_VOL_ASM_STOP is true. */
5293 if (GET_CODE (x
) != ASM_OPERANDS
5294 || (MEM_VOLATILE_P (x
) && TARGET_VOL_ASM_STOP
))
5296 /* Avoid writing the register multiple times if we have multiple
5297 asm outputs. This avoids an abort in rws_access_reg. */
5298 if (! rws_insn
[REG_VOLATILE
].write_count
)
5300 new_flags
.is_write
= 1;
5301 rws_access_regno (REG_VOLATILE
, new_flags
, pred
);
5306 /* For all ASM_OPERANDS, we must traverse the vector of input operands.
5307 We can not just fall through here since then we would be confused
5308 by the ASM_INPUT rtx inside ASM_OPERANDS, which do not indicate
5309 traditional asms unlike their normal usage. */
5311 for (i
= ASM_OPERANDS_INPUT_LENGTH (x
) - 1; i
>= 0; --i
)
5312 if (rtx_needs_barrier (ASM_OPERANDS_INPUT (x
, i
), flags
, pred
))
5317 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5319 rtx pat
= XVECEXP (x
, 0, i
);
5320 if (GET_CODE (pat
) == SET
)
5322 update_set_flags (pat
, &new_flags
, &pred
, &cond
);
5323 need_barrier
|= set_src_needs_barrier (pat
, new_flags
, pred
, cond
);
5325 else if (GET_CODE (pat
) == USE
5326 || GET_CODE (pat
) == CALL
5327 || GET_CODE (pat
) == ASM_OPERANDS
)
5328 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5329 else if (GET_CODE (pat
) != CLOBBER
&& GET_CODE (pat
) != RETURN
)
5332 for (i
= XVECLEN (x
, 0) - 1; i
>= 0; --i
)
5334 rtx pat
= XVECEXP (x
, 0, i
);
5335 if (GET_CODE (pat
) == SET
)
5337 if (GET_CODE (SET_SRC (pat
)) != CALL
)
5339 new_flags
.is_write
= 1;
5340 need_barrier
|= rtx_needs_barrier (SET_DEST (pat
), new_flags
,
5344 else if (GET_CODE (pat
) == CLOBBER
|| GET_CODE (pat
) == RETURN
)
5345 need_barrier
|= rtx_needs_barrier (pat
, flags
, pred
);
5353 if (REGNO (x
) == AR_UNAT_REGNUM
)
5355 for (i
= 0; i
< 64; ++i
)
5356 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ i
, flags
, pred
);
5359 need_barrier
= rws_access_reg (x
, flags
, pred
);
5363 /* Find the regs used in memory address computation. */
5364 new_flags
.is_write
= 0;
5365 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5368 case CONST_INT
: case CONST_DOUBLE
:
5369 case SYMBOL_REF
: case LABEL_REF
: case CONST
:
5372 /* Operators with side-effects. */
5373 case POST_INC
: case POST_DEC
:
5374 if (GET_CODE (XEXP (x
, 0)) != REG
)
5377 new_flags
.is_write
= 0;
5378 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5379 new_flags
.is_write
= 1;
5380 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5384 if (GET_CODE (XEXP (x
, 0)) != REG
)
5387 new_flags
.is_write
= 0;
5388 need_barrier
= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5389 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5390 new_flags
.is_write
= 1;
5391 need_barrier
|= rws_access_reg (XEXP (x
, 0), new_flags
, pred
);
5394 /* Handle common unary and binary ops for efficiency. */
5395 case COMPARE
: case PLUS
: case MINUS
: case MULT
: case DIV
:
5396 case MOD
: case UDIV
: case UMOD
: case AND
: case IOR
:
5397 case XOR
: case ASHIFT
: case ROTATE
: case ASHIFTRT
: case LSHIFTRT
:
5398 case ROTATERT
: case SMIN
: case SMAX
: case UMIN
: case UMAX
:
5399 case NE
: case EQ
: case GE
: case GT
: case LE
:
5400 case LT
: case GEU
: case GTU
: case LEU
: case LTU
:
5401 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), new_flags
, pred
);
5402 need_barrier
|= rtx_needs_barrier (XEXP (x
, 1), new_flags
, pred
);
5405 case NEG
: case NOT
: case SIGN_EXTEND
: case ZERO_EXTEND
:
5406 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
: case FLOAT
:
5407 case FIX
: case UNSIGNED_FLOAT
: case UNSIGNED_FIX
: case ABS
:
5408 case SQRT
: case FFS
: case POPCOUNT
:
5409 need_barrier
= rtx_needs_barrier (XEXP (x
, 0), flags
, pred
);
5413 switch (XINT (x
, 1))
5415 case UNSPEC_LTOFF_DTPMOD
:
5416 case UNSPEC_LTOFF_DTPREL
:
5418 case UNSPEC_LTOFF_TPREL
:
5420 case UNSPEC_PRED_REL_MUTEX
:
5421 case UNSPEC_PIC_CALL
:
5423 case UNSPEC_FETCHADD_ACQ
:
5424 case UNSPEC_BSP_VALUE
:
5425 case UNSPEC_FLUSHRS
:
5426 case UNSPEC_BUNDLE_SELECTOR
:
5429 case UNSPEC_GR_SPILL
:
5430 case UNSPEC_GR_RESTORE
:
5432 HOST_WIDE_INT offset
= INTVAL (XVECEXP (x
, 0, 1));
5433 HOST_WIDE_INT bit
= (offset
>> 3) & 63;
5435 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5436 new_flags
.is_write
= (XINT (x
, 1) == 1);
5437 need_barrier
|= rws_access_regno (AR_UNAT_BIT_0
+ bit
,
5442 case UNSPEC_FR_SPILL
:
5443 case UNSPEC_FR_RESTORE
:
5444 case UNSPEC_GETF_EXP
:
5445 case UNSPEC_SETF_EXP
:
5447 case UNSPEC_FR_SQRT_RECIP_APPROX
:
5448 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5451 case UNSPEC_FR_RECIP_APPROX
:
5452 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 0), flags
, pred
);
5453 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5456 case UNSPEC_CMPXCHG_ACQ
:
5457 need_barrier
= rtx_needs_barrier (XVECEXP (x
, 0, 1), flags
, pred
);
5458 need_barrier
|= rtx_needs_barrier (XVECEXP (x
, 0, 2), flags
, pred
);
5466 case UNSPEC_VOLATILE
:
5467 switch (XINT (x
, 1))
5470 /* Alloc must always be the first instruction of a group.
5471 We force this by always returning true. */
5472 /* ??? We might get better scheduling if we explicitly check for
5473 input/local/output register dependencies, and modify the
5474 scheduler so that alloc is always reordered to the start of
5475 the current group. We could then eliminate all of the
5476 first_instruction code. */
5477 rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5479 new_flags
.is_write
= 1;
5480 rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5483 case UNSPECV_SET_BSP
:
5487 case UNSPECV_BLOCKAGE
:
5488 case UNSPECV_INSN_GROUP_BARRIER
:
5490 case UNSPECV_PSAC_ALL
:
5491 case UNSPECV_PSAC_NORMAL
:
5500 new_flags
.is_write
= 0;
5501 need_barrier
= rws_access_regno (REG_RP
, flags
, pred
);
5502 need_barrier
|= rws_access_regno (AR_PFS_REGNUM
, flags
, pred
);
5504 new_flags
.is_write
= 1;
5505 need_barrier
|= rws_access_regno (AR_EC_REGNUM
, new_flags
, pred
);
5506 need_barrier
|= rws_access_regno (REG_AR_CFM
, new_flags
, pred
);
5510 format_ptr
= GET_RTX_FORMAT (GET_CODE (x
));
5511 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5512 switch (format_ptr
[i
])
5514 case '0': /* unused field */
5515 case 'i': /* integer */
5516 case 'n': /* note */
5517 case 'w': /* wide integer */
5518 case 's': /* pointer to string */
5519 case 'S': /* optional pointer to string */
5523 if (rtx_needs_barrier (XEXP (x
, i
), flags
, pred
))
5528 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
5529 if (rtx_needs_barrier (XVECEXP (x
, i
, j
), flags
, pred
))
5538 return need_barrier
;
5541 /* Clear out the state for group_barrier_needed_p at the start of a
5542 sequence of insns. */
5545 init_insn_group_barriers (void)
5547 memset (rws_sum
, 0, sizeof (rws_sum
));
5548 first_instruction
= 1;
5551 /* Given the current state, recorded by previous calls to this function,
5552 determine whether a group barrier (a stop bit) is necessary before INSN.
5553 Return nonzero if so. */
5556 group_barrier_needed_p (rtx insn
)
5559 int need_barrier
= 0;
5560 struct reg_flags flags
;
5562 memset (&flags
, 0, sizeof (flags
));
5563 switch (GET_CODE (insn
))
5569 /* A barrier doesn't imply an instruction group boundary. */
5573 memset (rws_insn
, 0, sizeof (rws_insn
));
5577 flags
.is_branch
= 1;
5578 flags
.is_sibcall
= SIBLING_CALL_P (insn
);
5579 memset (rws_insn
, 0, sizeof (rws_insn
));
5581 /* Don't bundle a call following another call. */
5582 if ((pat
= prev_active_insn (insn
))
5583 && GET_CODE (pat
) == CALL_INSN
)
5589 need_barrier
= rtx_needs_barrier (PATTERN (insn
), flags
, 0);
5593 flags
.is_branch
= 1;
5595 /* Don't bundle a jump following a call. */
5596 if ((pat
= prev_active_insn (insn
))
5597 && GET_CODE (pat
) == CALL_INSN
)
5605 if (GET_CODE (PATTERN (insn
)) == USE
5606 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
5607 /* Don't care about USE and CLOBBER "insns"---those are used to
5608 indicate to the optimizer that it shouldn't get rid of
5609 certain operations. */
5612 pat
= PATTERN (insn
);
5614 /* Ug. Hack hacks hacked elsewhere. */
5615 switch (recog_memoized (insn
))
5617 /* We play dependency tricks with the epilogue in order
5618 to get proper schedules. Undo this for dv analysis. */
5619 case CODE_FOR_epilogue_deallocate_stack
:
5620 case CODE_FOR_prologue_allocate_stack
:
5621 pat
= XVECEXP (pat
, 0, 0);
5624 /* The pattern we use for br.cloop confuses the code above.
5625 The second element of the vector is representative. */
5626 case CODE_FOR_doloop_end_internal
:
5627 pat
= XVECEXP (pat
, 0, 1);
5630 /* Doesn't generate code. */
5631 case CODE_FOR_pred_rel_mutex
:
5632 case CODE_FOR_prologue_use
:
5639 memset (rws_insn
, 0, sizeof (rws_insn
));
5640 need_barrier
= rtx_needs_barrier (pat
, flags
, 0);
5642 /* Check to see if the previous instruction was a volatile
5645 need_barrier
= rws_access_regno (REG_VOLATILE
, flags
, 0);
5652 if (first_instruction
&& INSN_P (insn
)
5653 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
5654 && GET_CODE (PATTERN (insn
)) != USE
5655 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
5658 first_instruction
= 0;
5661 return need_barrier
;
5664 /* Like group_barrier_needed_p, but do not clobber the current state. */
5667 safe_group_barrier_needed_p (rtx insn
)
5669 struct reg_write_state rws_saved
[NUM_REGS
];
5670 int saved_first_instruction
;
5673 memcpy (rws_saved
, rws_sum
, NUM_REGS
* sizeof *rws_saved
);
5674 saved_first_instruction
= first_instruction
;
5676 t
= group_barrier_needed_p (insn
);
5678 memcpy (rws_sum
, rws_saved
, NUM_REGS
* sizeof *rws_saved
);
5679 first_instruction
= saved_first_instruction
;
5684 /* Scan the current function and insert stop bits as necessary to
5685 eliminate dependencies. This function assumes that a final
5686 instruction scheduling pass has been run which has already
5687 inserted most of the necessary stop bits. This function only
5688 inserts new ones at basic block boundaries, since these are
5689 invisible to the scheduler. */
5692 emit_insn_group_barriers (FILE *dump
)
5696 int insns_since_last_label
= 0;
5698 init_insn_group_barriers ();
5700 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5702 if (GET_CODE (insn
) == CODE_LABEL
)
5704 if (insns_since_last_label
)
5706 insns_since_last_label
= 0;
5708 else if (GET_CODE (insn
) == NOTE
5709 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
5711 if (insns_since_last_label
)
5713 insns_since_last_label
= 0;
5715 else if (GET_CODE (insn
) == INSN
5716 && GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
5717 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
5719 init_insn_group_barriers ();
5722 else if (INSN_P (insn
))
5724 insns_since_last_label
= 1;
5726 if (group_barrier_needed_p (insn
))
5731 fprintf (dump
, "Emitting stop before label %d\n",
5732 INSN_UID (last_label
));
5733 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), last_label
);
5736 init_insn_group_barriers ();
5744 /* Like emit_insn_group_barriers, but run if no final scheduling pass was run.
5745 This function has to emit all necessary group barriers. */
5748 emit_all_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
5752 init_insn_group_barriers ();
5754 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5756 if (GET_CODE (insn
) == BARRIER
)
5758 rtx last
= prev_active_insn (insn
);
5762 if (GET_CODE (last
) == JUMP_INSN
5763 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
5764 last
= prev_active_insn (last
);
5765 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
5766 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
5768 init_insn_group_barriers ();
5770 else if (INSN_P (insn
))
5772 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
5773 init_insn_group_barriers ();
5774 else if (group_barrier_needed_p (insn
))
5776 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5777 init_insn_group_barriers ();
5778 group_barrier_needed_p (insn
);
5785 static int errata_find_address_regs (rtx
*, void *);
5786 static void errata_emit_nops (rtx
);
5787 static void fixup_errata (void);
5789 /* This structure is used to track some details about the previous insns
5790 groups so we can determine if it may be necessary to insert NOPs to
5791 workaround hardware errata. */
5794 HARD_REG_SET p_reg_set
;
5795 HARD_REG_SET gr_reg_conditionally_set
;
5798 /* Index into the last_group array. */
5799 static int group_idx
;
5801 /* Called through for_each_rtx; determines if a hard register that was
5802 conditionally set in the previous group is used as an address register.
5803 It ensures that for_each_rtx returns 1 in that case. */
5805 errata_find_address_regs (rtx
*xp
, void *data ATTRIBUTE_UNUSED
)
5808 if (GET_CODE (x
) != MEM
)
5811 if (GET_CODE (x
) == POST_MODIFY
)
5813 if (GET_CODE (x
) == REG
)
5815 struct group
*prev_group
= last_group
+ (group_idx
^ 1);
5816 if (TEST_HARD_REG_BIT (prev_group
->gr_reg_conditionally_set
,
5824 /* Called for each insn; this function keeps track of the state in
5825 last_group and emits additional NOPs if necessary to work around
5826 an Itanium A/B step erratum. */
5828 errata_emit_nops (rtx insn
)
5830 struct group
*this_group
= last_group
+ group_idx
;
5831 struct group
*prev_group
= last_group
+ (group_idx
^ 1);
5832 rtx pat
= PATTERN (insn
);
5833 rtx cond
= GET_CODE (pat
) == COND_EXEC
? COND_EXEC_TEST (pat
) : 0;
5834 rtx real_pat
= cond
? COND_EXEC_CODE (pat
) : pat
;
5835 enum attr_type type
;
5838 if (GET_CODE (real_pat
) == USE
5839 || GET_CODE (real_pat
) == CLOBBER
5840 || GET_CODE (real_pat
) == ASM_INPUT
5841 || GET_CODE (real_pat
) == ADDR_VEC
5842 || GET_CODE (real_pat
) == ADDR_DIFF_VEC
5843 || asm_noperands (PATTERN (insn
)) >= 0)
5846 /* single_set doesn't work for COND_EXEC insns, so we have to duplicate
5849 if (GET_CODE (set
) == PARALLEL
)
5852 set
= XVECEXP (real_pat
, 0, 0);
5853 for (i
= 1; i
< XVECLEN (real_pat
, 0); i
++)
5854 if (GET_CODE (XVECEXP (real_pat
, 0, i
)) != USE
5855 && GET_CODE (XVECEXP (real_pat
, 0, i
)) != CLOBBER
)
5862 if (set
&& GET_CODE (set
) != SET
)
5865 type
= get_attr_type (insn
);
5868 && set
&& REG_P (SET_DEST (set
)) && PR_REGNO_P (REGNO (SET_DEST (set
))))
5869 SET_HARD_REG_BIT (this_group
->p_reg_set
, REGNO (SET_DEST (set
)));
5871 if ((type
== TYPE_M
|| type
== TYPE_A
) && cond
&& set
5872 && REG_P (SET_DEST (set
))
5873 && GET_CODE (SET_SRC (set
)) != PLUS
5874 && GET_CODE (SET_SRC (set
)) != MINUS
5875 && (GET_CODE (SET_SRC (set
)) != ASHIFT
5876 || !shladd_operand (XEXP (SET_SRC (set
), 1), VOIDmode
))
5877 && (GET_CODE (SET_SRC (set
)) != MEM
5878 || GET_CODE (XEXP (SET_SRC (set
), 0)) != POST_MODIFY
)
5879 && GENERAL_REGNO_P (REGNO (SET_DEST (set
))))
5881 if (!COMPARISON_P (cond
)
5882 || !REG_P (XEXP (cond
, 0)))
5885 if (TEST_HARD_REG_BIT (prev_group
->p_reg_set
, REGNO (XEXP (cond
, 0))))
5886 SET_HARD_REG_BIT (this_group
->gr_reg_conditionally_set
, REGNO (SET_DEST (set
)));
5888 if (for_each_rtx (&real_pat
, errata_find_address_regs
, NULL
))
5890 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5891 emit_insn_before (gen_nop (), insn
);
5892 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn
);
5894 memset (last_group
, 0, sizeof last_group
);
5898 /* Emit extra nops if they are required to work around hardware errata. */
5905 if (! TARGET_B_STEP
)
5909 memset (last_group
, 0, sizeof last_group
);
5911 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5916 if (ia64_safe_type (insn
) == TYPE_S
)
5919 memset (last_group
+ group_idx
, 0, sizeof last_group
[group_idx
]);
5922 errata_emit_nops (insn
);
5927 /* Instruction scheduling support. */
5929 #define NR_BUNDLES 10
5931 /* A list of names of all available bundles. */
5933 static const char *bundle_name
[NR_BUNDLES
] =
5939 #if NR_BUNDLES == 10
5949 /* Nonzero if we should insert stop bits into the schedule. */
5951 int ia64_final_schedule
= 0;
5953 /* Codes of the corresponding quieryied units: */
5955 static int _0mii_
, _0mmi_
, _0mfi_
, _0mmf_
;
5956 static int _0bbb_
, _0mbb_
, _0mib_
, _0mmb_
, _0mfb_
, _0mlx_
;
5958 static int _1mii_
, _1mmi_
, _1mfi_
, _1mmf_
;
5959 static int _1bbb_
, _1mbb_
, _1mib_
, _1mmb_
, _1mfb_
, _1mlx_
;
5961 static int pos_1
, pos_2
, pos_3
, pos_4
, pos_5
, pos_6
;
5963 /* The following variable value is an insn group barrier. */
5965 static rtx dfa_stop_insn
;
5967 /* The following variable value is the last issued insn. */
5969 static rtx last_scheduled_insn
;
5971 /* The following variable value is size of the DFA state. */
5973 static size_t dfa_state_size
;
5975 /* The following variable value is pointer to a DFA state used as
5976 temporary variable. */
5978 static state_t temp_dfa_state
= NULL
;
5980 /* The following variable value is DFA state after issuing the last
5983 static state_t prev_cycle_state
= NULL
;
5985 /* The following array element values are TRUE if the corresponding
5986 insn requires to add stop bits before it. */
5988 static char *stops_p
;
5990 /* The following variable is used to set up the mentioned above array. */
5992 static int stop_before_p
= 0;
5994 /* The following variable value is length of the arrays `clocks' and
5997 static int clocks_length
;
5999 /* The following array element values are cycles on which the
6000 corresponding insn will be issued. The array is used only for
6005 /* The following array element values are numbers of cycles should be
6006 added to improve insn scheduling for MM_insns for Itanium1. */
6008 static int *add_cycles
;
6010 static rtx
ia64_single_set (rtx
);
6011 static void ia64_emit_insn_before (rtx
, rtx
);
6013 /* Map a bundle number to its pseudo-op. */
6016 get_bundle_name (int b
)
6018 return bundle_name
[b
];
6022 /* Return the maximum number of instructions a cpu can issue. */
6025 ia64_issue_rate (void)
6030 /* Helper function - like single_set, but look inside COND_EXEC. */
6033 ia64_single_set (rtx insn
)
6035 rtx x
= PATTERN (insn
), ret
;
6036 if (GET_CODE (x
) == COND_EXEC
)
6037 x
= COND_EXEC_CODE (x
);
6038 if (GET_CODE (x
) == SET
)
6041 /* Special case here prologue_allocate_stack and epilogue_deallocate_stack.
6042 Although they are not classical single set, the second set is there just
6043 to protect it from moving past FP-relative stack accesses. */
6044 switch (recog_memoized (insn
))
6046 case CODE_FOR_prologue_allocate_stack
:
6047 case CODE_FOR_epilogue_deallocate_stack
:
6048 ret
= XVECEXP (x
, 0, 0);
6052 ret
= single_set_2 (insn
, x
);
6059 /* Adjust the cost of a scheduling dependency. Return the new cost of
6060 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
6063 ia64_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
6065 enum attr_itanium_class dep_class
;
6066 enum attr_itanium_class insn_class
;
6068 if (REG_NOTE_KIND (link
) != REG_DEP_OUTPUT
)
6071 insn_class
= ia64_safe_itanium_class (insn
);
6072 dep_class
= ia64_safe_itanium_class (dep_insn
);
6073 if (dep_class
== ITANIUM_CLASS_ST
|| dep_class
== ITANIUM_CLASS_STF
6074 || insn_class
== ITANIUM_CLASS_ST
|| insn_class
== ITANIUM_CLASS_STF
)
6080 /* Like emit_insn_before, but skip cycle_display notes.
6081 ??? When cycle display notes are implemented, update this. */
6084 ia64_emit_insn_before (rtx insn
, rtx before
)
6086 emit_insn_before (insn
, before
);
6089 /* The following function marks insns who produce addresses for load
6090 and store insns. Such insns will be placed into M slots because it
6091 decrease latency time for Itanium1 (see function
6092 `ia64_produce_address_p' and the DFA descriptions). */
6095 ia64_dependencies_evaluation_hook (rtx head
, rtx tail
)
6097 rtx insn
, link
, next
, next_tail
;
6099 next_tail
= NEXT_INSN (tail
);
6100 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
6103 for (insn
= head
; insn
!= next_tail
; insn
= NEXT_INSN (insn
))
6105 && ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IALU
)
6107 for (link
= INSN_DEPEND (insn
); link
!= 0; link
= XEXP (link
, 1))
6109 next
= XEXP (link
, 0);
6110 if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_ST
6111 || ia64_safe_itanium_class (next
) == ITANIUM_CLASS_STF
)
6112 && ia64_st_address_bypass_p (insn
, next
))
6114 else if ((ia64_safe_itanium_class (next
) == ITANIUM_CLASS_LD
6115 || ia64_safe_itanium_class (next
)
6116 == ITANIUM_CLASS_FLD
)
6117 && ia64_ld_address_bypass_p (insn
, next
))
6120 insn
->call
= link
!= 0;
6124 /* We're beginning a new block. Initialize data structures as necessary. */
6127 ia64_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
6128 int sched_verbose ATTRIBUTE_UNUSED
,
6129 int max_ready ATTRIBUTE_UNUSED
)
6131 #ifdef ENABLE_CHECKING
6134 if (reload_completed
)
6135 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
6136 insn
!= current_sched_info
->next_tail
;
6137 insn
= NEXT_INSN (insn
))
6138 if (SCHED_GROUP_P (insn
))
6141 last_scheduled_insn
= NULL_RTX
;
6142 init_insn_group_barriers ();
6145 /* We are about to being issuing insns for this clock cycle.
6146 Override the default sort algorithm to better slot instructions. */
6149 ia64_dfa_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
,
6150 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
,
6154 int n_ready
= *pn_ready
;
6155 rtx
*e_ready
= ready
+ n_ready
;
6159 fprintf (dump
, "// ia64_dfa_sched_reorder (type %d):\n", reorder_type
);
6161 if (reorder_type
== 0)
6163 /* First, move all USEs, CLOBBERs and other crud out of the way. */
6165 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
6166 if (insnp
< e_ready
)
6169 enum attr_type t
= ia64_safe_type (insn
);
6170 if (t
== TYPE_UNKNOWN
)
6172 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6173 || asm_noperands (PATTERN (insn
)) >= 0)
6175 rtx lowest
= ready
[n_asms
];
6176 ready
[n_asms
] = insn
;
6182 rtx highest
= ready
[n_ready
- 1];
6183 ready
[n_ready
- 1] = insn
;
6190 if (n_asms
< n_ready
)
6192 /* Some normal insns to process. Skip the asms. */
6196 else if (n_ready
> 0)
6200 if (ia64_final_schedule
)
6203 int nr_need_stop
= 0;
6205 for (insnp
= ready
; insnp
< e_ready
; insnp
++)
6206 if (safe_group_barrier_needed_p (*insnp
))
6209 if (reorder_type
== 1 && n_ready
== nr_need_stop
)
6211 if (reorder_type
== 0)
6214 /* Move down everything that needs a stop bit, preserving
6216 while (insnp
-- > ready
+ deleted
)
6217 while (insnp
>= ready
+ deleted
)
6220 if (! safe_group_barrier_needed_p (insn
))
6222 memmove (ready
+ 1, ready
, (insnp
- ready
) * sizeof (rtx
));
6233 /* We are about to being issuing insns for this clock cycle. Override
6234 the default sort algorithm to better slot instructions. */
6237 ia64_sched_reorder (FILE *dump
, int sched_verbose
, rtx
*ready
, int *pn_ready
,
6240 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
,
6241 pn_ready
, clock_var
, 0);
6244 /* Like ia64_sched_reorder, but called after issuing each insn.
6245 Override the default sort algorithm to better slot instructions. */
6248 ia64_sched_reorder2 (FILE *dump ATTRIBUTE_UNUSED
,
6249 int sched_verbose ATTRIBUTE_UNUSED
, rtx
*ready
,
6250 int *pn_ready
, int clock_var
)
6252 if (ia64_tune
== PROCESSOR_ITANIUM
&& reload_completed
&& last_scheduled_insn
)
6253 clocks
[INSN_UID (last_scheduled_insn
)] = clock_var
;
6254 return ia64_dfa_sched_reorder (dump
, sched_verbose
, ready
, pn_ready
,
6258 /* We are about to issue INSN. Return the number of insns left on the
6259 ready queue that can be issued this cycle. */
6262 ia64_variable_issue (FILE *dump ATTRIBUTE_UNUSED
,
6263 int sched_verbose ATTRIBUTE_UNUSED
,
6264 rtx insn ATTRIBUTE_UNUSED
,
6265 int can_issue_more ATTRIBUTE_UNUSED
)
6267 last_scheduled_insn
= insn
;
6268 memcpy (prev_cycle_state
, curr_state
, dfa_state_size
);
6269 if (reload_completed
)
6271 if (group_barrier_needed_p (insn
))
6273 if (GET_CODE (insn
) == CALL_INSN
)
6274 init_insn_group_barriers ();
6275 stops_p
[INSN_UID (insn
)] = stop_before_p
;
6281 /* We are choosing insn from the ready queue. Return nonzero if INSN
6285 ia64_first_cycle_multipass_dfa_lookahead_guard (rtx insn
)
6287 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6289 return (!reload_completed
6290 || !safe_group_barrier_needed_p (insn
));
6293 /* The following variable value is pseudo-insn used by the DFA insn
6294 scheduler to change the DFA state when the simulated clock is
6297 static rtx dfa_pre_cycle_insn
;
6299 /* We are about to being issuing INSN. Return nonzero if we can not
6300 issue it on given cycle CLOCK and return zero if we should not sort
6301 the ready queue on the next clock start. */
6304 ia64_dfa_new_cycle (FILE *dump
, int verbose
, rtx insn
, int last_clock
,
6305 int clock
, int *sort_p
)
6307 int setup_clocks_p
= FALSE
;
6309 if (insn
== NULL_RTX
|| !INSN_P (insn
))
6311 if ((reload_completed
&& safe_group_barrier_needed_p (insn
))
6312 || (last_scheduled_insn
6313 && (GET_CODE (last_scheduled_insn
) == CALL_INSN
6314 || GET_CODE (PATTERN (last_scheduled_insn
)) == ASM_INPUT
6315 || asm_noperands (PATTERN (last_scheduled_insn
)) >= 0)))
6317 init_insn_group_barriers ();
6318 if (verbose
&& dump
)
6319 fprintf (dump
, "// Stop should be before %d%s\n", INSN_UID (insn
),
6320 last_clock
== clock
? " + cycle advance" : "");
6322 if (last_clock
== clock
)
6324 state_transition (curr_state
, dfa_stop_insn
);
6325 if (TARGET_EARLY_STOP_BITS
)
6326 *sort_p
= (last_scheduled_insn
== NULL_RTX
6327 || GET_CODE (last_scheduled_insn
) != CALL_INSN
);
6332 else if (reload_completed
)
6333 setup_clocks_p
= TRUE
;
6334 memcpy (curr_state
, prev_cycle_state
, dfa_state_size
);
6335 state_transition (curr_state
, dfa_stop_insn
);
6336 state_transition (curr_state
, dfa_pre_cycle_insn
);
6337 state_transition (curr_state
, NULL
);
6339 else if (reload_completed
)
6340 setup_clocks_p
= TRUE
;
6341 if (setup_clocks_p
&& ia64_tune
== PROCESSOR_ITANIUM
6342 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
6343 && asm_noperands (PATTERN (insn
)) == 0)
6345 enum attr_itanium_class c
= ia64_safe_itanium_class (insn
);
6347 if (c
!= ITANIUM_CLASS_MMMUL
&& c
!= ITANIUM_CLASS_MMSHF
)
6352 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
6353 if (REG_NOTE_KIND (link
) == 0)
6355 enum attr_itanium_class dep_class
;
6356 rtx dep_insn
= XEXP (link
, 0);
6358 dep_class
= ia64_safe_itanium_class (dep_insn
);
6359 if ((dep_class
== ITANIUM_CLASS_MMMUL
6360 || dep_class
== ITANIUM_CLASS_MMSHF
)
6361 && last_clock
- clocks
[INSN_UID (dep_insn
)] < 4
6363 || last_clock
- clocks
[INSN_UID (dep_insn
)] < d
))
6364 d
= last_clock
- clocks
[INSN_UID (dep_insn
)];
6367 add_cycles
[INSN_UID (insn
)] = 3 - d
;
6375 /* The following page contains abstract data `bundle states' which are
6376 used for bundling insns (inserting nops and template generation). */
6378 /* The following describes state of insn bundling. */
6382 /* Unique bundle state number to identify them in the debugging
6385 rtx insn
; /* corresponding insn, NULL for the 1st and the last state */
6386 /* number nops before and after the insn */
6387 short before_nops_num
, after_nops_num
;
6388 int insn_num
; /* insn number (0 - for initial state, 1 - for the 1st
6390 int cost
; /* cost of the state in cycles */
6391 int accumulated_insns_num
; /* number of all previous insns including
6392 nops. L is considered as 2 insns */
6393 int branch_deviation
; /* deviation of previous branches from 3rd slots */
6394 struct bundle_state
*next
; /* next state with the same insn_num */
6395 struct bundle_state
*originator
; /* originator (previous insn state) */
6396 /* All bundle states are in the following chain. */
6397 struct bundle_state
*allocated_states_chain
;
6398 /* The DFA State after issuing the insn and the nops. */
6402 /* The following is map insn number to the corresponding bundle state. */
6404 static struct bundle_state
**index_to_bundle_states
;
6406 /* The unique number of next bundle state. */
6408 static int bundle_states_num
;
6410 /* All allocated bundle states are in the following chain. */
6412 static struct bundle_state
*allocated_bundle_states_chain
;
6414 /* All allocated but not used bundle states are in the following
6417 static struct bundle_state
*free_bundle_state_chain
;
6420 /* The following function returns a free bundle state. */
6422 static struct bundle_state
*
6423 get_free_bundle_state (void)
6425 struct bundle_state
*result
;
6427 if (free_bundle_state_chain
!= NULL
)
6429 result
= free_bundle_state_chain
;
6430 free_bundle_state_chain
= result
->next
;
6434 result
= xmalloc (sizeof (struct bundle_state
));
6435 result
->dfa_state
= xmalloc (dfa_state_size
);
6436 result
->allocated_states_chain
= allocated_bundle_states_chain
;
6437 allocated_bundle_states_chain
= result
;
6439 result
->unique_num
= bundle_states_num
++;
6444 /* The following function frees given bundle state. */
6447 free_bundle_state (struct bundle_state
*state
)
6449 state
->next
= free_bundle_state_chain
;
6450 free_bundle_state_chain
= state
;
6453 /* Start work with abstract data `bundle states'. */
6456 initiate_bundle_states (void)
6458 bundle_states_num
= 0;
6459 free_bundle_state_chain
= NULL
;
6460 allocated_bundle_states_chain
= NULL
;
6463 /* Finish work with abstract data `bundle states'. */
6466 finish_bundle_states (void)
6468 struct bundle_state
*curr_state
, *next_state
;
6470 for (curr_state
= allocated_bundle_states_chain
;
6472 curr_state
= next_state
)
6474 next_state
= curr_state
->allocated_states_chain
;
6475 free (curr_state
->dfa_state
);
6480 /* Hash table of the bundle states. The key is dfa_state and insn_num
6481 of the bundle states. */
6483 static htab_t bundle_state_table
;
6485 /* The function returns hash of BUNDLE_STATE. */
6488 bundle_state_hash (const void *bundle_state
)
6490 const struct bundle_state
*state
= (struct bundle_state
*) bundle_state
;
6493 for (result
= i
= 0; i
< dfa_state_size
; i
++)
6494 result
+= (((unsigned char *) state
->dfa_state
) [i
]
6495 << ((i
% CHAR_BIT
) * 3 + CHAR_BIT
));
6496 return result
+ state
->insn_num
;
6499 /* The function returns nonzero if the bundle state keys are equal. */
6502 bundle_state_eq_p (const void *bundle_state_1
, const void *bundle_state_2
)
6504 const struct bundle_state
* state1
= (struct bundle_state
*) bundle_state_1
;
6505 const struct bundle_state
* state2
= (struct bundle_state
*) bundle_state_2
;
6507 return (state1
->insn_num
== state2
->insn_num
6508 && memcmp (state1
->dfa_state
, state2
->dfa_state
,
6509 dfa_state_size
) == 0);
6512 /* The function inserts the BUNDLE_STATE into the hash table. The
6513 function returns nonzero if the bundle has been inserted into the
6514 table. The table contains the best bundle state with given key. */
6517 insert_bundle_state (struct bundle_state
*bundle_state
)
6521 entry_ptr
= htab_find_slot (bundle_state_table
, bundle_state
, 1);
6522 if (*entry_ptr
== NULL
)
6524 bundle_state
->next
= index_to_bundle_states
[bundle_state
->insn_num
];
6525 index_to_bundle_states
[bundle_state
->insn_num
] = bundle_state
;
6526 *entry_ptr
= (void *) bundle_state
;
6529 else if (bundle_state
->cost
< ((struct bundle_state
*) *entry_ptr
)->cost
6530 || (bundle_state
->cost
== ((struct bundle_state
*) *entry_ptr
)->cost
6531 && (((struct bundle_state
*)*entry_ptr
)->accumulated_insns_num
6532 > bundle_state
->accumulated_insns_num
6533 || (((struct bundle_state
*)
6534 *entry_ptr
)->accumulated_insns_num
6535 == bundle_state
->accumulated_insns_num
6536 && ((struct bundle_state
*)
6537 *entry_ptr
)->branch_deviation
6538 > bundle_state
->branch_deviation
))))
6541 struct bundle_state temp
;
6543 temp
= *(struct bundle_state
*) *entry_ptr
;
6544 *(struct bundle_state
*) *entry_ptr
= *bundle_state
;
6545 ((struct bundle_state
*) *entry_ptr
)->next
= temp
.next
;
6546 *bundle_state
= temp
;
6551 /* Start work with the hash table. */
6554 initiate_bundle_state_table (void)
6556 bundle_state_table
= htab_create (50, bundle_state_hash
, bundle_state_eq_p
,
6560 /* Finish work with the hash table. */
6563 finish_bundle_state_table (void)
6565 htab_delete (bundle_state_table
);
6570 /* The following variable is a insn `nop' used to check bundle states
6571 with different number of inserted nops. */
6573 static rtx ia64_nop
;
6575 /* The following function tries to issue NOPS_NUM nops for the current
6576 state without advancing processor cycle. If it failed, the
6577 function returns FALSE and frees the current state. */
6580 try_issue_nops (struct bundle_state
*curr_state
, int nops_num
)
6584 for (i
= 0; i
< nops_num
; i
++)
6585 if (state_transition (curr_state
->dfa_state
, ia64_nop
) >= 0)
6587 free_bundle_state (curr_state
);
6593 /* The following function tries to issue INSN for the current
6594 state without advancing processor cycle. If it failed, the
6595 function returns FALSE and frees the current state. */
6598 try_issue_insn (struct bundle_state
*curr_state
, rtx insn
)
6600 if (insn
&& state_transition (curr_state
->dfa_state
, insn
) >= 0)
6602 free_bundle_state (curr_state
);
6608 /* The following function tries to issue BEFORE_NOPS_NUM nops and INSN
6609 starting with ORIGINATOR without advancing processor cycle. If
6610 TRY_BUNDLE_END_P is TRUE, the function also/only (if
6611 ONLY_BUNDLE_END_P is TRUE) tries to issue nops to fill all bundle.
6612 If it was successful, the function creates new bundle state and
6613 insert into the hash table and into `index_to_bundle_states'. */
6616 issue_nops_and_insn (struct bundle_state
*originator
, int before_nops_num
,
6617 rtx insn
, int try_bundle_end_p
, int only_bundle_end_p
)
6619 struct bundle_state
*curr_state
;
6621 curr_state
= get_free_bundle_state ();
6622 memcpy (curr_state
->dfa_state
, originator
->dfa_state
, dfa_state_size
);
6623 curr_state
->insn
= insn
;
6624 curr_state
->insn_num
= originator
->insn_num
+ 1;
6625 curr_state
->cost
= originator
->cost
;
6626 curr_state
->originator
= originator
;
6627 curr_state
->before_nops_num
= before_nops_num
;
6628 curr_state
->after_nops_num
= 0;
6629 curr_state
->accumulated_insns_num
6630 = originator
->accumulated_insns_num
+ before_nops_num
;
6631 curr_state
->branch_deviation
= originator
->branch_deviation
;
6632 if (insn
== NULL_RTX
)
6634 else if (INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
)
6636 if (GET_MODE (insn
) == TImode
)
6638 if (!try_issue_nops (curr_state
, before_nops_num
))
6640 if (!try_issue_insn (curr_state
, insn
))
6642 memcpy (temp_dfa_state
, curr_state
->dfa_state
, dfa_state_size
);
6643 if (state_transition (temp_dfa_state
, dfa_pre_cycle_insn
) >= 0
6644 && curr_state
->accumulated_insns_num
% 3 != 0)
6646 free_bundle_state (curr_state
);
6650 else if (GET_MODE (insn
) != TImode
)
6652 if (!try_issue_nops (curr_state
, before_nops_num
))
6654 if (!try_issue_insn (curr_state
, insn
))
6656 curr_state
->accumulated_insns_num
++;
6657 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6658 || asm_noperands (PATTERN (insn
)) >= 0)
6660 if (ia64_safe_type (insn
) == TYPE_L
)
6661 curr_state
->accumulated_insns_num
++;
6665 state_transition (curr_state
->dfa_state
, dfa_pre_cycle_insn
);
6666 state_transition (curr_state
->dfa_state
, NULL
);
6668 if (!try_issue_nops (curr_state
, before_nops_num
))
6670 if (!try_issue_insn (curr_state
, insn
))
6672 curr_state
->accumulated_insns_num
++;
6673 if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6674 || asm_noperands (PATTERN (insn
)) >= 0)
6676 /* Finish bundle containing asm insn. */
6677 curr_state
->after_nops_num
6678 = 3 - curr_state
->accumulated_insns_num
% 3;
6679 curr_state
->accumulated_insns_num
6680 += 3 - curr_state
->accumulated_insns_num
% 3;
6682 else if (ia64_safe_type (insn
) == TYPE_L
)
6683 curr_state
->accumulated_insns_num
++;
6685 if (ia64_safe_type (insn
) == TYPE_B
)
6686 curr_state
->branch_deviation
6687 += 2 - (curr_state
->accumulated_insns_num
- 1) % 3;
6688 if (try_bundle_end_p
&& curr_state
->accumulated_insns_num
% 3 != 0)
6690 if (!only_bundle_end_p
&& insert_bundle_state (curr_state
))
6693 struct bundle_state
*curr_state1
;
6694 struct bundle_state
*allocated_states_chain
;
6696 curr_state1
= get_free_bundle_state ();
6697 dfa_state
= curr_state1
->dfa_state
;
6698 allocated_states_chain
= curr_state1
->allocated_states_chain
;
6699 *curr_state1
= *curr_state
;
6700 curr_state1
->dfa_state
= dfa_state
;
6701 curr_state1
->allocated_states_chain
= allocated_states_chain
;
6702 memcpy (curr_state1
->dfa_state
, curr_state
->dfa_state
,
6704 curr_state
= curr_state1
;
6706 if (!try_issue_nops (curr_state
,
6707 3 - curr_state
->accumulated_insns_num
% 3))
6709 curr_state
->after_nops_num
6710 = 3 - curr_state
->accumulated_insns_num
% 3;
6711 curr_state
->accumulated_insns_num
6712 += 3 - curr_state
->accumulated_insns_num
% 3;
6714 if (!insert_bundle_state (curr_state
))
6715 free_bundle_state (curr_state
);
6719 /* The following function returns position in the two window bundle
6723 get_max_pos (state_t state
)
6725 if (cpu_unit_reservation_p (state
, pos_6
))
6727 else if (cpu_unit_reservation_p (state
, pos_5
))
6729 else if (cpu_unit_reservation_p (state
, pos_4
))
6731 else if (cpu_unit_reservation_p (state
, pos_3
))
6733 else if (cpu_unit_reservation_p (state
, pos_2
))
6735 else if (cpu_unit_reservation_p (state
, pos_1
))
6741 /* The function returns code of a possible template for given position
6742 and state. The function should be called only with 2 values of
6743 position equal to 3 or 6. */
6746 get_template (state_t state
, int pos
)
6751 if (cpu_unit_reservation_p (state
, _0mii_
))
6753 else if (cpu_unit_reservation_p (state
, _0mmi_
))
6755 else if (cpu_unit_reservation_p (state
, _0mfi_
))
6757 else if (cpu_unit_reservation_p (state
, _0mmf_
))
6759 else if (cpu_unit_reservation_p (state
, _0bbb_
))
6761 else if (cpu_unit_reservation_p (state
, _0mbb_
))
6763 else if (cpu_unit_reservation_p (state
, _0mib_
))
6765 else if (cpu_unit_reservation_p (state
, _0mmb_
))
6767 else if (cpu_unit_reservation_p (state
, _0mfb_
))
6769 else if (cpu_unit_reservation_p (state
, _0mlx_
))
6774 if (cpu_unit_reservation_p (state
, _1mii_
))
6776 else if (cpu_unit_reservation_p (state
, _1mmi_
))
6778 else if (cpu_unit_reservation_p (state
, _1mfi_
))
6780 else if (_1mmf_
>= 0 && cpu_unit_reservation_p (state
, _1mmf_
))
6782 else if (cpu_unit_reservation_p (state
, _1bbb_
))
6784 else if (cpu_unit_reservation_p (state
, _1mbb_
))
6786 else if (cpu_unit_reservation_p (state
, _1mib_
))
6788 else if (cpu_unit_reservation_p (state
, _1mmb_
))
6790 else if (cpu_unit_reservation_p (state
, _1mfb_
))
6792 else if (cpu_unit_reservation_p (state
, _1mlx_
))
6801 /* The following function returns an insn important for insn bundling
6802 followed by INSN and before TAIL. */
6805 get_next_important_insn (rtx insn
, rtx tail
)
6807 for (; insn
&& insn
!= tail
; insn
= NEXT_INSN (insn
))
6809 && ia64_safe_itanium_class (insn
) != ITANIUM_CLASS_IGNORE
6810 && GET_CODE (PATTERN (insn
)) != USE
6811 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6816 /* The following function does insn bundling. Bundling means
6817 inserting templates and nop insns to fit insn groups into permitted
6818 templates. Instruction scheduling uses NDFA (non-deterministic
6819 finite automata) encoding informations about the templates and the
6820 inserted nops. Nondeterminism of the automata permits follows
6821 all possible insn sequences very fast.
6823 Unfortunately it is not possible to get information about inserting
6824 nop insns and used templates from the automata states. The
6825 automata only says that we can issue an insn possibly inserting
6826 some nops before it and using some template. Therefore insn
6827 bundling in this function is implemented by using DFA
6828 (deterministic finite automata). We follows all possible insn
6829 sequences by inserting 0-2 nops (that is what the NDFA describe for
6830 insn scheduling) before/after each insn being bundled. We know the
6831 start of simulated processor cycle from insn scheduling (insn
6832 starting a new cycle has TImode).
6834 Simple implementation of insn bundling would create enormous
6835 number of possible insn sequences satisfying information about new
6836 cycle ticks taken from the insn scheduling. To make the algorithm
6837 practical we use dynamic programming. Each decision (about
6838 inserting nops and implicitly about previous decisions) is described
6839 by structure bundle_state (see above). If we generate the same
6840 bundle state (key is automaton state after issuing the insns and
6841 nops for it), we reuse already generated one. As consequence we
6842 reject some decisions which can not improve the solution and
6843 reduce memory for the algorithm.
6845 When we reach the end of EBB (extended basic block), we choose the
6846 best sequence and then, moving back in EBB, insert templates for
6847 the best alternative. The templates are taken from querying
6848 automaton state for each insn in chosen bundle states.
6850 So the algorithm makes two (forward and backward) passes through
6851 EBB. There is an additional forward pass through EBB for Itanium1
6852 processor. This pass inserts more nops to make dependency between
6853 a producer insn and MMMUL/MMSHF at least 4 cycles long. */
6856 bundling (FILE *dump
, int verbose
, rtx prev_head_insn
, rtx tail
)
6858 struct bundle_state
*curr_state
, *next_state
, *best_state
;
6859 rtx insn
, next_insn
;
6861 int i
, bundle_end_p
, only_bundle_end_p
, asm_p
;
6862 int pos
= 0, max_pos
, template0
, template1
;
6865 enum attr_type type
;
6868 /* Count insns in the EBB. */
6869 for (insn
= NEXT_INSN (prev_head_insn
);
6870 insn
&& insn
!= tail
;
6871 insn
= NEXT_INSN (insn
))
6877 dfa_clean_insn_cache ();
6878 initiate_bundle_state_table ();
6879 index_to_bundle_states
= xmalloc ((insn_num
+ 2)
6880 * sizeof (struct bundle_state
*));
6881 /* First (forward) pass -- generation of bundle states. */
6882 curr_state
= get_free_bundle_state ();
6883 curr_state
->insn
= NULL
;
6884 curr_state
->before_nops_num
= 0;
6885 curr_state
->after_nops_num
= 0;
6886 curr_state
->insn_num
= 0;
6887 curr_state
->cost
= 0;
6888 curr_state
->accumulated_insns_num
= 0;
6889 curr_state
->branch_deviation
= 0;
6890 curr_state
->next
= NULL
;
6891 curr_state
->originator
= NULL
;
6892 state_reset (curr_state
->dfa_state
);
6893 index_to_bundle_states
[0] = curr_state
;
6895 /* Shift cycle mark if it is put on insn which could be ignored. */
6896 for (insn
= NEXT_INSN (prev_head_insn
);
6898 insn
= NEXT_INSN (insn
))
6900 && (ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6901 || GET_CODE (PATTERN (insn
)) == USE
6902 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6903 && GET_MODE (insn
) == TImode
)
6905 PUT_MODE (insn
, VOIDmode
);
6906 for (next_insn
= NEXT_INSN (insn
);
6908 next_insn
= NEXT_INSN (next_insn
))
6909 if (INSN_P (next_insn
)
6910 && ia64_safe_itanium_class (next_insn
) != ITANIUM_CLASS_IGNORE
6911 && GET_CODE (PATTERN (next_insn
)) != USE
6912 && GET_CODE (PATTERN (next_insn
)) != CLOBBER
)
6914 PUT_MODE (next_insn
, TImode
);
6918 /* Froward pass: generation of bundle states. */
6919 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
6924 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
6925 || GET_CODE (PATTERN (insn
)) == USE
6926 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
6928 type
= ia64_safe_type (insn
);
6929 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
6931 index_to_bundle_states
[insn_num
] = NULL
;
6932 for (curr_state
= index_to_bundle_states
[insn_num
- 1];
6934 curr_state
= next_state
)
6936 pos
= curr_state
->accumulated_insns_num
% 3;
6937 next_state
= curr_state
->next
;
6938 /* We must fill up the current bundle in order to start a
6939 subsequent asm insn in a new bundle. Asm insn is always
6940 placed in a separate bundle. */
6942 = (next_insn
!= NULL_RTX
6943 && INSN_CODE (insn
) == CODE_FOR_insn_group_barrier
6944 && ia64_safe_type (next_insn
) == TYPE_UNKNOWN
);
6945 /* We may fill up the current bundle if it is the cycle end
6946 without a group barrier. */
6948 = (only_bundle_end_p
|| next_insn
== NULL_RTX
6949 || (GET_MODE (next_insn
) == TImode
6950 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
));
6951 if (type
== TYPE_F
|| type
== TYPE_B
|| type
== TYPE_L
6953 /* We need to insert 2 nops for cases like M_MII. To
6954 guarantee issuing all insns on the same cycle for
6955 Itanium 1, we need to issue 2 nops after the first M
6956 insn (MnnMII where n is a nop insn). */
6957 || ((type
== TYPE_M
|| type
== TYPE_A
)
6958 && ia64_tune
== PROCESSOR_ITANIUM
6959 && !bundle_end_p
&& pos
== 1))
6960 issue_nops_and_insn (curr_state
, 2, insn
, bundle_end_p
,
6962 issue_nops_and_insn (curr_state
, 1, insn
, bundle_end_p
,
6964 issue_nops_and_insn (curr_state
, 0, insn
, bundle_end_p
,
6967 if (index_to_bundle_states
[insn_num
] == NULL
)
6969 for (curr_state
= index_to_bundle_states
[insn_num
];
6971 curr_state
= curr_state
->next
)
6972 if (verbose
>= 2 && dump
)
6974 /* This structure is taken from generated code of the
6975 pipeline hazard recognizer (see file insn-attrtab.c).
6976 Please don't forget to change the structure if a new
6977 automaton is added to .md file. */
6980 unsigned short one_automaton_state
;
6981 unsigned short oneb_automaton_state
;
6982 unsigned short two_automaton_state
;
6983 unsigned short twob_automaton_state
;
6988 "// Bundle state %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
6989 curr_state
->unique_num
,
6990 (curr_state
->originator
== NULL
6991 ? -1 : curr_state
->originator
->unique_num
),
6993 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
6994 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
6995 (ia64_tune
== PROCESSOR_ITANIUM
6996 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
6997 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
7001 if (index_to_bundle_states
[insn_num
] == NULL
)
7002 /* We should find a solution because the 2nd insn scheduling has
7005 /* Find a state corresponding to the best insn sequence. */
7007 for (curr_state
= index_to_bundle_states
[insn_num
];
7009 curr_state
= curr_state
->next
)
7010 /* We are just looking at the states with fully filled up last
7011 bundle. The first we prefer insn sequences with minimal cost
7012 then with minimal inserted nops and finally with branch insns
7013 placed in the 3rd slots. */
7014 if (curr_state
->accumulated_insns_num
% 3 == 0
7015 && (best_state
== NULL
|| best_state
->cost
> curr_state
->cost
7016 || (best_state
->cost
== curr_state
->cost
7017 && (curr_state
->accumulated_insns_num
7018 < best_state
->accumulated_insns_num
7019 || (curr_state
->accumulated_insns_num
7020 == best_state
->accumulated_insns_num
7021 && curr_state
->branch_deviation
7022 < best_state
->branch_deviation
)))))
7023 best_state
= curr_state
;
7024 /* Second (backward) pass: adding nops and templates. */
7025 insn_num
= best_state
->before_nops_num
;
7026 template0
= template1
= -1;
7027 for (curr_state
= best_state
;
7028 curr_state
->originator
!= NULL
;
7029 curr_state
= curr_state
->originator
)
7031 insn
= curr_state
->insn
;
7032 asm_p
= (GET_CODE (PATTERN (insn
)) == ASM_INPUT
7033 || asm_noperands (PATTERN (insn
)) >= 0);
7035 if (verbose
>= 2 && dump
)
7039 unsigned short one_automaton_state
;
7040 unsigned short oneb_automaton_state
;
7041 unsigned short two_automaton_state
;
7042 unsigned short twob_automaton_state
;
7047 "// Best %d (orig %d, cost %d, nops %d/%d, insns %d, branch %d, state %d) for %d\n",
7048 curr_state
->unique_num
,
7049 (curr_state
->originator
== NULL
7050 ? -1 : curr_state
->originator
->unique_num
),
7052 curr_state
->before_nops_num
, curr_state
->after_nops_num
,
7053 curr_state
->accumulated_insns_num
, curr_state
->branch_deviation
,
7054 (ia64_tune
== PROCESSOR_ITANIUM
7055 ? ((struct DFA_chip
*) curr_state
->dfa_state
)->oneb_automaton_state
7056 : ((struct DFA_chip
*) curr_state
->dfa_state
)->twob_automaton_state
),
7059 /* Find the position in the current bundle window. The window can
7060 contain at most two bundles. Two bundle window means that
7061 the processor will make two bundle rotation. */
7062 max_pos
= get_max_pos (curr_state
->dfa_state
);
7064 /* The following (negative template number) means that the
7065 processor did one bundle rotation. */
7066 || (max_pos
== 3 && template0
< 0))
7068 /* We are at the end of the window -- find template(s) for
7072 template0
= get_template (curr_state
->dfa_state
, 3);
7075 template1
= get_template (curr_state
->dfa_state
, 3);
7076 template0
= get_template (curr_state
->dfa_state
, 6);
7079 if (max_pos
> 3 && template1
< 0)
7080 /* It may happen when we have the stop inside a bundle. */
7084 template1
= get_template (curr_state
->dfa_state
, 3);
7088 /* Emit nops after the current insn. */
7089 for (i
= 0; i
< curr_state
->after_nops_num
; i
++)
7092 emit_insn_after (nop
, insn
);
7098 /* We are at the start of a bundle: emit the template
7099 (it should be defined). */
7102 b
= gen_bundle_selector (GEN_INT (template0
));
7103 ia64_emit_insn_before (b
, nop
);
7104 /* If we have two bundle window, we make one bundle
7105 rotation. Otherwise template0 will be undefined
7106 (negative value). */
7107 template0
= template1
;
7111 /* Move the position backward in the window. Group barrier has
7112 no slot. Asm insn takes all bundle. */
7113 if (INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
7114 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
7115 && asm_noperands (PATTERN (insn
)) < 0)
7117 /* Long insn takes 2 slots. */
7118 if (ia64_safe_type (insn
) == TYPE_L
)
7123 && INSN_CODE (insn
) != CODE_FOR_insn_group_barrier
7124 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
7125 && asm_noperands (PATTERN (insn
)) < 0)
7127 /* The current insn is at the bundle start: emit the
7131 b
= gen_bundle_selector (GEN_INT (template0
));
7132 ia64_emit_insn_before (b
, insn
);
7133 b
= PREV_INSN (insn
);
7135 /* See comment above in analogous place for emitting nops
7137 template0
= template1
;
7140 /* Emit nops after the current insn. */
7141 for (i
= 0; i
< curr_state
->before_nops_num
; i
++)
7144 ia64_emit_insn_before (nop
, insn
);
7145 nop
= PREV_INSN (insn
);
7152 /* See comment above in analogous place for emitting nops
7156 b
= gen_bundle_selector (GEN_INT (template0
));
7157 ia64_emit_insn_before (b
, insn
);
7158 b
= PREV_INSN (insn
);
7160 template0
= template1
;
7165 if (ia64_tune
== PROCESSOR_ITANIUM
)
7166 /* Insert additional cycles for MM-insns (MMMUL and MMSHF).
7167 Itanium1 has a strange design, if the distance between an insn
7168 and dependent MM-insn is less 4 then we have a 6 additional
7169 cycles stall. So we make the distance equal to 4 cycles if it
7171 for (insn
= get_next_important_insn (NEXT_INSN (prev_head_insn
), tail
);
7176 || ia64_safe_itanium_class (insn
) == ITANIUM_CLASS_IGNORE
7177 || GET_CODE (PATTERN (insn
)) == USE
7178 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
7180 next_insn
= get_next_important_insn (NEXT_INSN (insn
), tail
);
7181 if (INSN_UID (insn
) < clocks_length
&& add_cycles
[INSN_UID (insn
)])
7182 /* We found a MM-insn which needs additional cycles. */
7188 /* Now we are searching for a template of the bundle in
7189 which the MM-insn is placed and the position of the
7190 insn in the bundle (0, 1, 2). Also we are searching
7191 for that there is a stop before the insn. */
7192 last
= prev_active_insn (insn
);
7193 pred_stop_p
= recog_memoized (last
) == CODE_FOR_insn_group_barrier
;
7195 last
= prev_active_insn (last
);
7197 for (;; last
= prev_active_insn (last
))
7198 if (recog_memoized (last
) == CODE_FOR_bundle_selector
)
7200 template0
= XINT (XVECEXP (PATTERN (last
), 0, 0), 0);
7202 /* The insn is in MLX bundle. Change the template
7203 onto MFI because we will add nops before the
7204 insn. It simplifies subsequent code a lot. */
7206 = gen_bundle_selector (const2_rtx
); /* -> MFI */
7209 else if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7211 /* Some check of correctness: the stop is not at the
7212 bundle start, there are no more 3 insns in the bundle,
7213 and the MM-insn is not at the start of bundle with
7215 if ((pred_stop_p
&& n
== 0) || n
> 2
7216 || (template0
== 9 && n
!= 0))
7218 /* Put nops after the insn in the bundle. */
7219 for (j
= 3 - n
; j
> 0; j
--)
7220 ia64_emit_insn_before (gen_nop (), insn
);
7221 /* It takes into account that we will add more N nops
7222 before the insn lately -- please see code below. */
7223 add_cycles
[INSN_UID (insn
)]--;
7224 if (!pred_stop_p
|| add_cycles
[INSN_UID (insn
)])
7225 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7228 add_cycles
[INSN_UID (insn
)]--;
7229 for (i
= add_cycles
[INSN_UID (insn
)]; i
> 0; i
--)
7231 /* Insert "MII;" template. */
7232 ia64_emit_insn_before (gen_bundle_selector (const0_rtx
),
7234 ia64_emit_insn_before (gen_nop (), insn
);
7235 ia64_emit_insn_before (gen_nop (), insn
);
7238 /* To decrease code size, we use "MI;I;"
7240 ia64_emit_insn_before
7241 (gen_insn_group_barrier (GEN_INT (3)), insn
);
7244 ia64_emit_insn_before (gen_nop (), insn
);
7245 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7248 /* Put the MM-insn in the same slot of a bundle with the
7249 same template as the original one. */
7250 ia64_emit_insn_before (gen_bundle_selector (GEN_INT (template0
)),
7252 /* To put the insn in the same slot, add necessary number
7254 for (j
= n
; j
> 0; j
--)
7255 ia64_emit_insn_before (gen_nop (), insn
);
7256 /* Put the stop if the original bundle had it. */
7258 ia64_emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7262 free (index_to_bundle_states
);
7263 finish_bundle_state_table ();
7265 dfa_clean_insn_cache ();
7268 /* The following function is called at the end of scheduling BB or
7269 EBB. After reload, it inserts stop bits and does insn bundling. */
7272 ia64_sched_finish (FILE *dump
, int sched_verbose
)
7275 fprintf (dump
, "// Finishing schedule.\n");
7276 if (!reload_completed
)
7278 if (reload_completed
)
7280 final_emit_insn_group_barriers (dump
);
7281 bundling (dump
, sched_verbose
, current_sched_info
->prev_head
,
7282 current_sched_info
->next_tail
);
7283 if (sched_verbose
&& dump
)
7284 fprintf (dump
, "// finishing %d-%d\n",
7285 INSN_UID (NEXT_INSN (current_sched_info
->prev_head
)),
7286 INSN_UID (PREV_INSN (current_sched_info
->next_tail
)));
7292 /* The following function inserts stop bits in scheduled BB or EBB. */
7295 final_emit_insn_group_barriers (FILE *dump ATTRIBUTE_UNUSED
)
7298 int need_barrier_p
= 0;
7299 rtx prev_insn
= NULL_RTX
;
7301 init_insn_group_barriers ();
7303 for (insn
= NEXT_INSN (current_sched_info
->prev_head
);
7304 insn
!= current_sched_info
->next_tail
;
7305 insn
= NEXT_INSN (insn
))
7307 if (GET_CODE (insn
) == BARRIER
)
7309 rtx last
= prev_active_insn (insn
);
7313 if (GET_CODE (last
) == JUMP_INSN
7314 && GET_CODE (PATTERN (last
)) == ADDR_DIFF_VEC
)
7315 last
= prev_active_insn (last
);
7316 if (recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7317 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)), last
);
7319 init_insn_group_barriers ();
7321 prev_insn
= NULL_RTX
;
7323 else if (INSN_P (insn
))
7325 if (recog_memoized (insn
) == CODE_FOR_insn_group_barrier
)
7327 init_insn_group_barriers ();
7329 prev_insn
= NULL_RTX
;
7331 else if (need_barrier_p
|| group_barrier_needed_p (insn
))
7333 if (TARGET_EARLY_STOP_BITS
)
7338 last
!= current_sched_info
->prev_head
;
7339 last
= PREV_INSN (last
))
7340 if (INSN_P (last
) && GET_MODE (last
) == TImode
7341 && stops_p
[INSN_UID (last
)])
7343 if (last
== current_sched_info
->prev_head
)
7345 last
= prev_active_insn (last
);
7347 && recog_memoized (last
) != CODE_FOR_insn_group_barrier
)
7348 emit_insn_after (gen_insn_group_barrier (GEN_INT (3)),
7350 init_insn_group_barriers ();
7351 for (last
= NEXT_INSN (last
);
7353 last
= NEXT_INSN (last
))
7355 group_barrier_needed_p (last
);
7359 emit_insn_before (gen_insn_group_barrier (GEN_INT (3)),
7361 init_insn_group_barriers ();
7363 group_barrier_needed_p (insn
);
7364 prev_insn
= NULL_RTX
;
7366 else if (recog_memoized (insn
) >= 0)
7368 need_barrier_p
= (GET_CODE (insn
) == CALL_INSN
7369 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
7370 || asm_noperands (PATTERN (insn
)) >= 0);
7377 /* If the following function returns TRUE, we will use the the DFA
7381 ia64_use_dfa_pipeline_interface (void)
7386 /* If the following function returns TRUE, we will use the the DFA
7390 ia64_first_cycle_multipass_dfa_lookahead (void)
7392 return (reload_completed
? 6 : 4);
7395 /* The following function initiates variable `dfa_pre_cycle_insn'. */
7398 ia64_init_dfa_pre_cycle_insn (void)
7400 if (temp_dfa_state
== NULL
)
7402 dfa_state_size
= state_size ();
7403 temp_dfa_state
= xmalloc (dfa_state_size
);
7404 prev_cycle_state
= xmalloc (dfa_state_size
);
7406 dfa_pre_cycle_insn
= make_insn_raw (gen_pre_cycle ());
7407 PREV_INSN (dfa_pre_cycle_insn
) = NEXT_INSN (dfa_pre_cycle_insn
) = NULL_RTX
;
7408 recog_memoized (dfa_pre_cycle_insn
);
7409 dfa_stop_insn
= make_insn_raw (gen_insn_group_barrier (GEN_INT (3)));
7410 PREV_INSN (dfa_stop_insn
) = NEXT_INSN (dfa_stop_insn
) = NULL_RTX
;
7411 recog_memoized (dfa_stop_insn
);
7414 /* The following function returns the pseudo insn DFA_PRE_CYCLE_INSN
7415 used by the DFA insn scheduler. */
7418 ia64_dfa_pre_cycle_insn (void)
7420 return dfa_pre_cycle_insn
;
7423 /* The following function returns TRUE if PRODUCER (of type ilog or
7424 ld) produces address for CONSUMER (of type st or stf). */
7427 ia64_st_address_bypass_p (rtx producer
, rtx consumer
)
7431 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7433 dest
= ia64_single_set (producer
);
7434 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7435 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7437 if (GET_CODE (reg
) == SUBREG
)
7438 reg
= SUBREG_REG (reg
);
7439 dest
= ia64_single_set (consumer
);
7440 if (dest
== NULL_RTX
|| (mem
= SET_DEST (dest
)) == NULL_RTX
7441 || GET_CODE (mem
) != MEM
)
7443 return reg_mentioned_p (reg
, mem
);
7446 /* The following function returns TRUE if PRODUCER (of type ilog or
7447 ld) produces address for CONSUMER (of type ld or fld). */
7450 ia64_ld_address_bypass_p (rtx producer
, rtx consumer
)
7452 rtx dest
, src
, reg
, mem
;
7454 if (producer
== NULL_RTX
|| consumer
== NULL_RTX
)
7456 dest
= ia64_single_set (producer
);
7457 if (dest
== NULL_RTX
|| (reg
= SET_DEST (dest
)) == NULL_RTX
7458 || (GET_CODE (reg
) != REG
&& GET_CODE (reg
) != SUBREG
))
7460 if (GET_CODE (reg
) == SUBREG
)
7461 reg
= SUBREG_REG (reg
);
7462 src
= ia64_single_set (consumer
);
7463 if (src
== NULL_RTX
|| (mem
= SET_SRC (src
)) == NULL_RTX
)
7465 if (GET_CODE (mem
) == UNSPEC
&& XVECLEN (mem
, 0) > 0)
7466 mem
= XVECEXP (mem
, 0, 0);
7467 while (GET_CODE (mem
) == SUBREG
|| GET_CODE (mem
) == ZERO_EXTEND
)
7468 mem
= XEXP (mem
, 0);
7470 /* Note that LO_SUM is used for GOT loads. */
7471 if (GET_CODE (mem
) != LO_SUM
&& GET_CODE (mem
) != MEM
)
7474 return reg_mentioned_p (reg
, mem
);
7477 /* The following function returns TRUE if INSN produces address for a
7478 load/store insn. We will place such insns into M slot because it
7479 decreases its latency time. */
7482 ia64_produce_address_p (rtx insn
)
7488 /* Emit pseudo-ops for the assembler to describe predicate relations.
7489 At present this assumes that we only consider predicate pairs to
7490 be mutex, and that the assembler can deduce proper values from
7491 straight-line code. */
7494 emit_predicate_relation_info (void)
7498 FOR_EACH_BB_REVERSE (bb
)
7501 rtx head
= BB_HEAD (bb
);
7503 /* We only need such notes at code labels. */
7504 if (GET_CODE (head
) != CODE_LABEL
)
7506 if (GET_CODE (NEXT_INSN (head
)) == NOTE
7507 && NOTE_LINE_NUMBER (NEXT_INSN (head
)) == NOTE_INSN_BASIC_BLOCK
)
7508 head
= NEXT_INSN (head
);
7510 for (r
= PR_REG (0); r
< PR_REG (64); r
+= 2)
7511 if (REGNO_REG_SET_P (bb
->global_live_at_start
, r
))
7513 rtx p
= gen_rtx_REG (BImode
, r
);
7514 rtx n
= emit_insn_after (gen_pred_rel_mutex (p
), head
);
7515 if (head
== BB_END (bb
))
7521 /* Look for conditional calls that do not return, and protect predicate
7522 relations around them. Otherwise the assembler will assume the call
7523 returns, and complain about uses of call-clobbered predicates after
7525 FOR_EACH_BB_REVERSE (bb
)
7527 rtx insn
= BB_HEAD (bb
);
7531 if (GET_CODE (insn
) == CALL_INSN
7532 && GET_CODE (PATTERN (insn
)) == COND_EXEC
7533 && find_reg_note (insn
, REG_NORETURN
, NULL_RTX
))
7535 rtx b
= emit_insn_before (gen_safe_across_calls_all (), insn
);
7536 rtx a
= emit_insn_after (gen_safe_across_calls_normal (), insn
);
7537 if (BB_HEAD (bb
) == insn
)
7539 if (BB_END (bb
) == insn
)
7543 if (insn
== BB_END (bb
))
7545 insn
= NEXT_INSN (insn
);
7550 /* Perform machine dependent operations on the rtl chain INSNS. */
7555 /* We are freeing block_for_insn in the toplev to keep compatibility
7556 with old MDEP_REORGS that are not CFG based. Recompute it now. */
7557 compute_bb_for_insn ();
7559 /* If optimizing, we'll have split before scheduling. */
7561 split_all_insns (0);
7563 /* ??? update_life_info_in_dirty_blocks fails to terminate during
7564 non-optimizing bootstrap. */
7565 update_life_info (NULL
, UPDATE_LIFE_GLOBAL_RM_NOTES
, PROP_DEATH_NOTES
);
7567 if (ia64_flag_schedule_insns2
)
7569 timevar_push (TV_SCHED2
);
7570 ia64_final_schedule
= 1;
7572 initiate_bundle_states ();
7573 ia64_nop
= make_insn_raw (gen_nop ());
7574 PREV_INSN (ia64_nop
) = NEXT_INSN (ia64_nop
) = NULL_RTX
;
7575 recog_memoized (ia64_nop
);
7576 clocks_length
= get_max_uid () + 1;
7577 stops_p
= xcalloc (1, clocks_length
);
7578 if (ia64_tune
== PROCESSOR_ITANIUM
)
7580 clocks
= xcalloc (clocks_length
, sizeof (int));
7581 add_cycles
= xcalloc (clocks_length
, sizeof (int));
7583 if (ia64_tune
== PROCESSOR_ITANIUM2
)
7585 pos_1
= get_cpu_unit_code ("2_1");
7586 pos_2
= get_cpu_unit_code ("2_2");
7587 pos_3
= get_cpu_unit_code ("2_3");
7588 pos_4
= get_cpu_unit_code ("2_4");
7589 pos_5
= get_cpu_unit_code ("2_5");
7590 pos_6
= get_cpu_unit_code ("2_6");
7591 _0mii_
= get_cpu_unit_code ("2b_0mii.");
7592 _0mmi_
= get_cpu_unit_code ("2b_0mmi.");
7593 _0mfi_
= get_cpu_unit_code ("2b_0mfi.");
7594 _0mmf_
= get_cpu_unit_code ("2b_0mmf.");
7595 _0bbb_
= get_cpu_unit_code ("2b_0bbb.");
7596 _0mbb_
= get_cpu_unit_code ("2b_0mbb.");
7597 _0mib_
= get_cpu_unit_code ("2b_0mib.");
7598 _0mmb_
= get_cpu_unit_code ("2b_0mmb.");
7599 _0mfb_
= get_cpu_unit_code ("2b_0mfb.");
7600 _0mlx_
= get_cpu_unit_code ("2b_0mlx.");
7601 _1mii_
= get_cpu_unit_code ("2b_1mii.");
7602 _1mmi_
= get_cpu_unit_code ("2b_1mmi.");
7603 _1mfi_
= get_cpu_unit_code ("2b_1mfi.");
7604 _1mmf_
= get_cpu_unit_code ("2b_1mmf.");
7605 _1bbb_
= get_cpu_unit_code ("2b_1bbb.");
7606 _1mbb_
= get_cpu_unit_code ("2b_1mbb.");
7607 _1mib_
= get_cpu_unit_code ("2b_1mib.");
7608 _1mmb_
= get_cpu_unit_code ("2b_1mmb.");
7609 _1mfb_
= get_cpu_unit_code ("2b_1mfb.");
7610 _1mlx_
= get_cpu_unit_code ("2b_1mlx.");
7614 pos_1
= get_cpu_unit_code ("1_1");
7615 pos_2
= get_cpu_unit_code ("1_2");
7616 pos_3
= get_cpu_unit_code ("1_3");
7617 pos_4
= get_cpu_unit_code ("1_4");
7618 pos_5
= get_cpu_unit_code ("1_5");
7619 pos_6
= get_cpu_unit_code ("1_6");
7620 _0mii_
= get_cpu_unit_code ("1b_0mii.");
7621 _0mmi_
= get_cpu_unit_code ("1b_0mmi.");
7622 _0mfi_
= get_cpu_unit_code ("1b_0mfi.");
7623 _0mmf_
= get_cpu_unit_code ("1b_0mmf.");
7624 _0bbb_
= get_cpu_unit_code ("1b_0bbb.");
7625 _0mbb_
= get_cpu_unit_code ("1b_0mbb.");
7626 _0mib_
= get_cpu_unit_code ("1b_0mib.");
7627 _0mmb_
= get_cpu_unit_code ("1b_0mmb.");
7628 _0mfb_
= get_cpu_unit_code ("1b_0mfb.");
7629 _0mlx_
= get_cpu_unit_code ("1b_0mlx.");
7630 _1mii_
= get_cpu_unit_code ("1b_1mii.");
7631 _1mmi_
= get_cpu_unit_code ("1b_1mmi.");
7632 _1mfi_
= get_cpu_unit_code ("1b_1mfi.");
7633 _1mmf_
= get_cpu_unit_code ("1b_1mmf.");
7634 _1bbb_
= get_cpu_unit_code ("1b_1bbb.");
7635 _1mbb_
= get_cpu_unit_code ("1b_1mbb.");
7636 _1mib_
= get_cpu_unit_code ("1b_1mib.");
7637 _1mmb_
= get_cpu_unit_code ("1b_1mmb.");
7638 _1mfb_
= get_cpu_unit_code ("1b_1mfb.");
7639 _1mlx_
= get_cpu_unit_code ("1b_1mlx.");
7641 schedule_ebbs (dump_file
);
7642 finish_bundle_states ();
7643 if (ia64_tune
== PROCESSOR_ITANIUM
)
7649 emit_insn_group_barriers (dump_file
);
7651 ia64_final_schedule
= 0;
7652 timevar_pop (TV_SCHED2
);
7655 emit_all_insn_group_barriers (dump_file
);
7657 /* A call must not be the last instruction in a function, so that the
7658 return address is still within the function, so that unwinding works
7659 properly. Note that IA-64 differs from dwarf2 on this point. */
7660 if (flag_unwind_tables
|| (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
7665 insn
= get_last_insn ();
7666 if (! INSN_P (insn
))
7667 insn
= prev_active_insn (insn
);
7668 /* Skip over insns that expand to nothing. */
7669 while (GET_CODE (insn
) == INSN
&& get_attr_empty (insn
) == EMPTY_YES
)
7671 if (GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
7672 && XINT (PATTERN (insn
), 1) == UNSPECV_INSN_GROUP_BARRIER
)
7674 insn
= prev_active_insn (insn
);
7676 if (GET_CODE (insn
) == CALL_INSN
)
7679 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7680 emit_insn (gen_break_f ());
7681 emit_insn (gen_insn_group_barrier (GEN_INT (3)));
7686 emit_predicate_relation_info ();
7688 if (ia64_flag_var_tracking
)
7690 timevar_push (TV_VAR_TRACKING
);
7691 variable_tracking_main ();
7692 timevar_pop (TV_VAR_TRACKING
);
7696 /* Return true if REGNO is used by the epilogue. */
7699 ia64_epilogue_uses (int regno
)
7704 /* With a call to a function in another module, we will write a new
7705 value to "gp". After returning from such a call, we need to make
7706 sure the function restores the original gp-value, even if the
7707 function itself does not use the gp anymore. */
7708 return !(TARGET_AUTO_PIC
|| TARGET_NO_PIC
);
7710 case IN_REG (0): case IN_REG (1): case IN_REG (2): case IN_REG (3):
7711 case IN_REG (4): case IN_REG (5): case IN_REG (6): case IN_REG (7):
7712 /* For functions defined with the syscall_linkage attribute, all
7713 input registers are marked as live at all function exits. This
7714 prevents the register allocator from using the input registers,
7715 which in turn makes it possible to restart a system call after
7716 an interrupt without having to save/restore the input registers.
7717 This also prevents kernel data from leaking to application code. */
7718 return lookup_attribute ("syscall_linkage",
7719 TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl
))) != NULL
;
7722 /* Conditional return patterns can't represent the use of `b0' as
7723 the return address, so we force the value live this way. */
7727 /* Likewise for ar.pfs, which is used by br.ret. */
7735 /* Return true if REGNO is used by the frame unwinder. */
7738 ia64_eh_uses (int regno
)
7740 if (! reload_completed
)
7743 if (current_frame_info
.reg_save_b0
7744 && regno
== current_frame_info
.reg_save_b0
)
7746 if (current_frame_info
.reg_save_pr
7747 && regno
== current_frame_info
.reg_save_pr
)
7749 if (current_frame_info
.reg_save_ar_pfs
7750 && regno
== current_frame_info
.reg_save_ar_pfs
)
7752 if (current_frame_info
.reg_save_ar_unat
7753 && regno
== current_frame_info
.reg_save_ar_unat
)
7755 if (current_frame_info
.reg_save_ar_lc
7756 && regno
== current_frame_info
.reg_save_ar_lc
)
7762 /* Return true if this goes in small data/bss. */
7764 /* ??? We could also support own long data here. Generating movl/add/ld8
7765 instead of addl,ld8/ld8. This makes the code bigger, but should make the
7766 code faster because there is one less load. This also includes incomplete
7767 types which can't go in sdata/sbss. */
7770 ia64_in_small_data_p (tree exp
)
7772 if (TARGET_NO_SDATA
)
7775 /* We want to merge strings, so we never consider them small data. */
7776 if (TREE_CODE (exp
) == STRING_CST
)
7779 /* Functions are never small data. */
7780 if (TREE_CODE (exp
) == FUNCTION_DECL
)
7783 if (TREE_CODE (exp
) == VAR_DECL
&& DECL_SECTION_NAME (exp
))
7785 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (exp
));
7786 if (strcmp (section
, ".sdata") == 0
7787 || strcmp (section
, ".sbss") == 0)
7792 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (exp
));
7794 /* If this is an incomplete type with size 0, then we can't put it
7795 in sdata because it might be too big when completed. */
7796 if (size
> 0 && size
<= ia64_section_threshold
)
7803 /* Output assembly directives for prologue regions. */
7805 /* The current basic block number. */
7807 static bool last_block
;
7809 /* True if we need a copy_state command at the start of the next block. */
7811 static bool need_copy_state
;
7813 /* The function emits unwind directives for the start of an epilogue. */
7816 process_epilogue (void)
7818 /* If this isn't the last block of the function, then we need to label the
7819 current state, and copy it back in at the start of the next block. */
7823 fprintf (asm_out_file
, "\t.label_state 1\n");
7824 need_copy_state
= true;
7827 fprintf (asm_out_file
, "\t.restore sp\n");
7830 /* This function processes a SET pattern looking for specific patterns
7831 which result in emitting an assembly directive required for unwinding. */
7834 process_set (FILE *asm_out_file
, rtx pat
)
7836 rtx src
= SET_SRC (pat
);
7837 rtx dest
= SET_DEST (pat
);
7838 int src_regno
, dest_regno
;
7840 /* Look for the ALLOC insn. */
7841 if (GET_CODE (src
) == UNSPEC_VOLATILE
7842 && XINT (src
, 1) == UNSPECV_ALLOC
7843 && GET_CODE (dest
) == REG
)
7845 dest_regno
= REGNO (dest
);
7847 /* If this isn't the final destination for ar.pfs, the alloc
7848 shouldn't have been marked frame related. */
7849 if (dest_regno
!= current_frame_info
.reg_save_ar_pfs
)
7852 fprintf (asm_out_file
, "\t.save ar.pfs, r%d\n",
7853 ia64_dbx_register_number (dest_regno
));
7857 /* Look for SP = .... */
7858 if (GET_CODE (dest
) == REG
&& REGNO (dest
) == STACK_POINTER_REGNUM
)
7860 if (GET_CODE (src
) == PLUS
)
7862 rtx op0
= XEXP (src
, 0);
7863 rtx op1
= XEXP (src
, 1);
7864 if (op0
== dest
&& GET_CODE (op1
) == CONST_INT
)
7866 if (INTVAL (op1
) < 0)
7867 fprintf (asm_out_file
, "\t.fframe "HOST_WIDE_INT_PRINT_DEC
"\n",
7870 process_epilogue ();
7875 else if (GET_CODE (src
) == REG
7876 && REGNO (src
) == HARD_FRAME_POINTER_REGNUM
)
7877 process_epilogue ();
7884 /* Register move we need to look at. */
7885 if (GET_CODE (dest
) == REG
&& GET_CODE (src
) == REG
)
7887 src_regno
= REGNO (src
);
7888 dest_regno
= REGNO (dest
);
7893 /* Saving return address pointer. */
7894 if (dest_regno
!= current_frame_info
.reg_save_b0
)
7896 fprintf (asm_out_file
, "\t.save rp, r%d\n",
7897 ia64_dbx_register_number (dest_regno
));
7901 if (dest_regno
!= current_frame_info
.reg_save_pr
)
7903 fprintf (asm_out_file
, "\t.save pr, r%d\n",
7904 ia64_dbx_register_number (dest_regno
));
7907 case AR_UNAT_REGNUM
:
7908 if (dest_regno
!= current_frame_info
.reg_save_ar_unat
)
7910 fprintf (asm_out_file
, "\t.save ar.unat, r%d\n",
7911 ia64_dbx_register_number (dest_regno
));
7915 if (dest_regno
!= current_frame_info
.reg_save_ar_lc
)
7917 fprintf (asm_out_file
, "\t.save ar.lc, r%d\n",
7918 ia64_dbx_register_number (dest_regno
));
7921 case STACK_POINTER_REGNUM
:
7922 if (dest_regno
!= HARD_FRAME_POINTER_REGNUM
7923 || ! frame_pointer_needed
)
7925 fprintf (asm_out_file
, "\t.vframe r%d\n",
7926 ia64_dbx_register_number (dest_regno
));
7930 /* Everything else should indicate being stored to memory. */
7935 /* Memory store we need to look at. */
7936 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
)
7942 if (GET_CODE (XEXP (dest
, 0)) == REG
)
7944 base
= XEXP (dest
, 0);
7947 else if (GET_CODE (XEXP (dest
, 0)) == PLUS
7948 && GET_CODE (XEXP (XEXP (dest
, 0), 1)) == CONST_INT
)
7950 base
= XEXP (XEXP (dest
, 0), 0);
7951 off
= INTVAL (XEXP (XEXP (dest
, 0), 1));
7956 if (base
== hard_frame_pointer_rtx
)
7958 saveop
= ".savepsp";
7961 else if (base
== stack_pointer_rtx
)
7966 src_regno
= REGNO (src
);
7970 if (current_frame_info
.reg_save_b0
!= 0)
7972 fprintf (asm_out_file
, "\t%s rp, %ld\n", saveop
, off
);
7976 if (current_frame_info
.reg_save_pr
!= 0)
7978 fprintf (asm_out_file
, "\t%s pr, %ld\n", saveop
, off
);
7982 if (current_frame_info
.reg_save_ar_lc
!= 0)
7984 fprintf (asm_out_file
, "\t%s ar.lc, %ld\n", saveop
, off
);
7988 if (current_frame_info
.reg_save_ar_pfs
!= 0)
7990 fprintf (asm_out_file
, "\t%s ar.pfs, %ld\n", saveop
, off
);
7993 case AR_UNAT_REGNUM
:
7994 if (current_frame_info
.reg_save_ar_unat
!= 0)
7996 fprintf (asm_out_file
, "\t%s ar.unat, %ld\n", saveop
, off
);
8003 fprintf (asm_out_file
, "\t.save.g 0x%x\n",
8004 1 << (src_regno
- GR_REG (4)));
8012 fprintf (asm_out_file
, "\t.save.b 0x%x\n",
8013 1 << (src_regno
- BR_REG (1)));
8020 fprintf (asm_out_file
, "\t.save.f 0x%x\n",
8021 1 << (src_regno
- FR_REG (2)));
8024 case FR_REG (16): case FR_REG (17): case FR_REG (18): case FR_REG (19):
8025 case FR_REG (20): case FR_REG (21): case FR_REG (22): case FR_REG (23):
8026 case FR_REG (24): case FR_REG (25): case FR_REG (26): case FR_REG (27):
8027 case FR_REG (28): case FR_REG (29): case FR_REG (30): case FR_REG (31):
8028 fprintf (asm_out_file
, "\t.save.gf 0x0, 0x%x\n",
8029 1 << (src_regno
- FR_REG (12)));
8041 /* This function looks at a single insn and emits any directives
8042 required to unwind this insn. */
8044 process_for_unwind_directive (FILE *asm_out_file
, rtx insn
)
8046 if (flag_unwind_tables
8047 || (flag_exceptions
&& !USING_SJLJ_EXCEPTIONS
))
8051 if (GET_CODE (insn
) == NOTE
8052 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_BASIC_BLOCK
)
8054 last_block
= NOTE_BASIC_BLOCK (insn
)->next_bb
== EXIT_BLOCK_PTR
;
8056 /* Restore unwind state from immediately before the epilogue. */
8057 if (need_copy_state
)
8059 fprintf (asm_out_file
, "\t.body\n");
8060 fprintf (asm_out_file
, "\t.copy_state 1\n");
8061 need_copy_state
= false;
8065 if (GET_CODE (insn
) == NOTE
|| ! RTX_FRAME_RELATED_P (insn
))
8068 pat
= find_reg_note (insn
, REG_FRAME_RELATED_EXPR
, NULL_RTX
);
8070 pat
= XEXP (pat
, 0);
8072 pat
= PATTERN (insn
);
8074 switch (GET_CODE (pat
))
8077 process_set (asm_out_file
, pat
);
8083 int limit
= XVECLEN (pat
, 0);
8084 for (par_index
= 0; par_index
< limit
; par_index
++)
8086 rtx x
= XVECEXP (pat
, 0, par_index
);
8087 if (GET_CODE (x
) == SET
)
8088 process_set (asm_out_file
, x
);
8101 ia64_init_builtins (void)
8103 tree psi_type_node
= build_pointer_type (integer_type_node
);
8104 tree pdi_type_node
= build_pointer_type (long_integer_type_node
);
8106 /* __sync_val_compare_and_swap_si, __sync_bool_compare_and_swap_si */
8107 tree si_ftype_psi_si_si
8108 = build_function_type_list (integer_type_node
,
8109 psi_type_node
, integer_type_node
,
8110 integer_type_node
, NULL_TREE
);
8112 /* __sync_val_compare_and_swap_di */
8113 tree di_ftype_pdi_di_di
8114 = build_function_type_list (long_integer_type_node
,
8115 pdi_type_node
, long_integer_type_node
,
8116 long_integer_type_node
, NULL_TREE
);
8117 /* __sync_bool_compare_and_swap_di */
8118 tree si_ftype_pdi_di_di
8119 = build_function_type_list (integer_type_node
,
8120 pdi_type_node
, long_integer_type_node
,
8121 long_integer_type_node
, NULL_TREE
);
8122 /* __sync_synchronize */
8123 tree void_ftype_void
8124 = build_function_type (void_type_node
, void_list_node
);
8126 /* __sync_lock_test_and_set_si */
8127 tree si_ftype_psi_si
8128 = build_function_type_list (integer_type_node
,
8129 psi_type_node
, integer_type_node
, NULL_TREE
);
8131 /* __sync_lock_test_and_set_di */
8132 tree di_ftype_pdi_di
8133 = build_function_type_list (long_integer_type_node
,
8134 pdi_type_node
, long_integer_type_node
,
8137 /* __sync_lock_release_si */
8139 = build_function_type_list (void_type_node
, psi_type_node
, NULL_TREE
);
8141 /* __sync_lock_release_di */
8143 = build_function_type_list (void_type_node
, pdi_type_node
, NULL_TREE
);
8148 /* The __fpreg type. */
8149 fpreg_type
= make_node (REAL_TYPE
);
8150 /* ??? The back end should know to load/save __fpreg variables using
8151 the ldf.fill and stf.spill instructions. */
8152 TYPE_PRECISION (fpreg_type
) = 96;
8153 layout_type (fpreg_type
);
8154 (*lang_hooks
.types
.register_builtin_type
) (fpreg_type
, "__fpreg");
8156 /* The __float80 type. */
8157 float80_type
= make_node (REAL_TYPE
);
8158 TYPE_PRECISION (float80_type
) = 96;
8159 layout_type (float80_type
);
8160 (*lang_hooks
.types
.register_builtin_type
) (float80_type
, "__float80");
8162 /* The __float128 type. */
8165 tree float128_type
= make_node (REAL_TYPE
);
8166 TYPE_PRECISION (float128_type
) = 128;
8167 layout_type (float128_type
);
8168 (*lang_hooks
.types
.register_builtin_type
) (float128_type
, "__float128");
8171 /* Under HPUX, this is a synonym for "long double". */
8172 (*lang_hooks
.types
.register_builtin_type
) (long_double_type_node
,
8175 #define def_builtin(name, type, code) \
8176 builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL_TREE)
8178 def_builtin ("__sync_val_compare_and_swap_si", si_ftype_psi_si_si
,
8179 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
);
8180 def_builtin ("__sync_val_compare_and_swap_di", di_ftype_pdi_di_di
,
8181 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
);
8182 def_builtin ("__sync_bool_compare_and_swap_si", si_ftype_psi_si_si
,
8183 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
);
8184 def_builtin ("__sync_bool_compare_and_swap_di", si_ftype_pdi_di_di
,
8185 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
);
8187 def_builtin ("__sync_synchronize", void_ftype_void
,
8188 IA64_BUILTIN_SYNCHRONIZE
);
8190 def_builtin ("__sync_lock_test_and_set_si", si_ftype_psi_si
,
8191 IA64_BUILTIN_LOCK_TEST_AND_SET_SI
);
8192 def_builtin ("__sync_lock_test_and_set_di", di_ftype_pdi_di
,
8193 IA64_BUILTIN_LOCK_TEST_AND_SET_DI
);
8194 def_builtin ("__sync_lock_release_si", void_ftype_psi
,
8195 IA64_BUILTIN_LOCK_RELEASE_SI
);
8196 def_builtin ("__sync_lock_release_di", void_ftype_pdi
,
8197 IA64_BUILTIN_LOCK_RELEASE_DI
);
8199 def_builtin ("__builtin_ia64_bsp",
8200 build_function_type (ptr_type_node
, void_list_node
),
8203 def_builtin ("__builtin_ia64_flushrs",
8204 build_function_type (void_type_node
, void_list_node
),
8205 IA64_BUILTIN_FLUSHRS
);
8207 def_builtin ("__sync_fetch_and_add_si", si_ftype_psi_si
,
8208 IA64_BUILTIN_FETCH_AND_ADD_SI
);
8209 def_builtin ("__sync_fetch_and_sub_si", si_ftype_psi_si
,
8210 IA64_BUILTIN_FETCH_AND_SUB_SI
);
8211 def_builtin ("__sync_fetch_and_or_si", si_ftype_psi_si
,
8212 IA64_BUILTIN_FETCH_AND_OR_SI
);
8213 def_builtin ("__sync_fetch_and_and_si", si_ftype_psi_si
,
8214 IA64_BUILTIN_FETCH_AND_AND_SI
);
8215 def_builtin ("__sync_fetch_and_xor_si", si_ftype_psi_si
,
8216 IA64_BUILTIN_FETCH_AND_XOR_SI
);
8217 def_builtin ("__sync_fetch_and_nand_si", si_ftype_psi_si
,
8218 IA64_BUILTIN_FETCH_AND_NAND_SI
);
8220 def_builtin ("__sync_add_and_fetch_si", si_ftype_psi_si
,
8221 IA64_BUILTIN_ADD_AND_FETCH_SI
);
8222 def_builtin ("__sync_sub_and_fetch_si", si_ftype_psi_si
,
8223 IA64_BUILTIN_SUB_AND_FETCH_SI
);
8224 def_builtin ("__sync_or_and_fetch_si", si_ftype_psi_si
,
8225 IA64_BUILTIN_OR_AND_FETCH_SI
);
8226 def_builtin ("__sync_and_and_fetch_si", si_ftype_psi_si
,
8227 IA64_BUILTIN_AND_AND_FETCH_SI
);
8228 def_builtin ("__sync_xor_and_fetch_si", si_ftype_psi_si
,
8229 IA64_BUILTIN_XOR_AND_FETCH_SI
);
8230 def_builtin ("__sync_nand_and_fetch_si", si_ftype_psi_si
,
8231 IA64_BUILTIN_NAND_AND_FETCH_SI
);
8233 def_builtin ("__sync_fetch_and_add_di", di_ftype_pdi_di
,
8234 IA64_BUILTIN_FETCH_AND_ADD_DI
);
8235 def_builtin ("__sync_fetch_and_sub_di", di_ftype_pdi_di
,
8236 IA64_BUILTIN_FETCH_AND_SUB_DI
);
8237 def_builtin ("__sync_fetch_and_or_di", di_ftype_pdi_di
,
8238 IA64_BUILTIN_FETCH_AND_OR_DI
);
8239 def_builtin ("__sync_fetch_and_and_di", di_ftype_pdi_di
,
8240 IA64_BUILTIN_FETCH_AND_AND_DI
);
8241 def_builtin ("__sync_fetch_and_xor_di", di_ftype_pdi_di
,
8242 IA64_BUILTIN_FETCH_AND_XOR_DI
);
8243 def_builtin ("__sync_fetch_and_nand_di", di_ftype_pdi_di
,
8244 IA64_BUILTIN_FETCH_AND_NAND_DI
);
8246 def_builtin ("__sync_add_and_fetch_di", di_ftype_pdi_di
,
8247 IA64_BUILTIN_ADD_AND_FETCH_DI
);
8248 def_builtin ("__sync_sub_and_fetch_di", di_ftype_pdi_di
,
8249 IA64_BUILTIN_SUB_AND_FETCH_DI
);
8250 def_builtin ("__sync_or_and_fetch_di", di_ftype_pdi_di
,
8251 IA64_BUILTIN_OR_AND_FETCH_DI
);
8252 def_builtin ("__sync_and_and_fetch_di", di_ftype_pdi_di
,
8253 IA64_BUILTIN_AND_AND_FETCH_DI
);
8254 def_builtin ("__sync_xor_and_fetch_di", di_ftype_pdi_di
,
8255 IA64_BUILTIN_XOR_AND_FETCH_DI
);
8256 def_builtin ("__sync_nand_and_fetch_di", di_ftype_pdi_di
,
8257 IA64_BUILTIN_NAND_AND_FETCH_DI
);
8262 /* Expand fetch_and_op intrinsics. The basic code sequence is:
8270 cmpxchgsz.acq tmp = [ptr], tmp
8271 } while (tmp != ret)
8275 ia64_expand_fetch_and_op (optab binoptab
, enum machine_mode mode
,
8276 tree arglist
, rtx target
)
8278 rtx ret
, label
, tmp
, ccv
, insn
, mem
, value
;
8281 arg0
= TREE_VALUE (arglist
);
8282 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8283 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
8284 #ifdef POINTERS_EXTEND_UNSIGNED
8285 if (GET_MODE(mem
) != Pmode
)
8286 mem
= convert_memory_address (Pmode
, mem
);
8288 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8290 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
8291 MEM_VOLATILE_P (mem
) = 1;
8293 if (target
&& register_operand (target
, mode
))
8296 ret
= gen_reg_rtx (mode
);
8298 emit_insn (gen_mf ());
8300 /* Special case for fetchadd instructions. */
8301 if (binoptab
== add_optab
&& fetchadd_operand (value
, VOIDmode
))
8304 insn
= gen_fetchadd_acq_si (ret
, mem
, value
);
8306 insn
= gen_fetchadd_acq_di (ret
, mem
, value
);
8311 tmp
= gen_reg_rtx (mode
);
8312 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8313 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8314 emit_move_insn (tmp
, mem
);
8316 label
= gen_label_rtx ();
8318 emit_move_insn (ret
, tmp
);
8319 convert_move (ccv
, tmp
, /*unsignedp=*/1);
8321 /* Perform the specific operation. Special case NAND by noticing
8322 one_cmpl_optab instead. */
8323 if (binoptab
== one_cmpl_optab
)
8325 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
8326 binoptab
= and_optab
;
8328 tmp
= expand_binop (mode
, binoptab
, tmp
, value
, tmp
, 1, OPTAB_WIDEN
);
8331 insn
= gen_cmpxchg_acq_si (tmp
, mem
, tmp
, ccv
);
8333 insn
= gen_cmpxchg_acq_di (tmp
, mem
, tmp
, ccv
);
8336 emit_cmp_and_jump_insns (tmp
, ret
, NE
, 0, mode
, 1, label
);
8341 /* Expand op_and_fetch intrinsics. The basic code sequence is:
8348 ret = tmp <op> value;
8349 cmpxchgsz.acq tmp = [ptr], ret
8350 } while (tmp != old)
8354 ia64_expand_op_and_fetch (optab binoptab
, enum machine_mode mode
,
8355 tree arglist
, rtx target
)
8357 rtx old
, label
, tmp
, ret
, ccv
, insn
, mem
, value
;
8360 arg0
= TREE_VALUE (arglist
);
8361 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8362 mem
= expand_expr (arg0
, NULL_RTX
, Pmode
, 0);
8363 #ifdef POINTERS_EXTEND_UNSIGNED
8364 if (GET_MODE(mem
) != Pmode
)
8365 mem
= convert_memory_address (Pmode
, mem
);
8368 value
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8370 mem
= gen_rtx_MEM (mode
, force_reg (Pmode
, mem
));
8371 MEM_VOLATILE_P (mem
) = 1;
8373 if (target
&& ! register_operand (target
, mode
))
8376 emit_insn (gen_mf ());
8377 tmp
= gen_reg_rtx (mode
);
8378 old
= gen_reg_rtx (mode
);
8379 /* ar.ccv must always be loaded with a zero-extended DImode value. */
8380 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8382 emit_move_insn (tmp
, mem
);
8384 label
= gen_label_rtx ();
8386 emit_move_insn (old
, tmp
);
8387 convert_move (ccv
, tmp
, /*unsignedp=*/1);
8389 /* Perform the specific operation. Special case NAND by noticing
8390 one_cmpl_optab instead. */
8391 if (binoptab
== one_cmpl_optab
)
8393 tmp
= expand_unop (mode
, binoptab
, tmp
, NULL
, OPTAB_WIDEN
);
8394 binoptab
= and_optab
;
8396 ret
= expand_binop (mode
, binoptab
, tmp
, value
, target
, 1, OPTAB_WIDEN
);
8399 insn
= gen_cmpxchg_acq_si (tmp
, mem
, ret
, ccv
);
8401 insn
= gen_cmpxchg_acq_di (tmp
, mem
, ret
, ccv
);
8404 emit_cmp_and_jump_insns (tmp
, old
, NE
, 0, mode
, 1, label
);
8409 /* Expand val_ and bool_compare_and_swap. For val_ we want:
8413 cmpxchgsz.acq ret = [ptr], newval, ar.ccv
8416 For bool_ it's the same except return ret == oldval.
8420 ia64_expand_compare_and_swap (enum machine_mode rmode
, enum machine_mode mode
,
8421 int boolp
, tree arglist
, rtx target
)
8423 tree arg0
, arg1
, arg2
;
8424 rtx mem
, old
, new, ccv
, tmp
, insn
;
8426 arg0
= TREE_VALUE (arglist
);
8427 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8428 arg2
= TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist
)));
8429 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8430 old
= expand_expr (arg1
, NULL_RTX
, mode
, 0);
8431 new = expand_expr (arg2
, NULL_RTX
, mode
, 0);
8433 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8434 MEM_VOLATILE_P (mem
) = 1;
8436 if (GET_MODE (old
) != mode
)
8437 old
= convert_to_mode (mode
, old
, /*unsignedp=*/1);
8438 if (GET_MODE (new) != mode
)
8439 new = convert_to_mode (mode
, new, /*unsignedp=*/1);
8441 if (! register_operand (old
, mode
))
8442 old
= copy_to_mode_reg (mode
, old
);
8443 if (! register_operand (new, mode
))
8444 new = copy_to_mode_reg (mode
, new);
8446 if (! boolp
&& target
&& register_operand (target
, mode
))
8449 tmp
= gen_reg_rtx (mode
);
8451 ccv
= gen_rtx_REG (DImode
, AR_CCV_REGNUM
);
8452 convert_move (ccv
, old
, /*unsignedp=*/1);
8453 emit_insn (gen_mf ());
8455 insn
= gen_cmpxchg_acq_si (tmp
, mem
, new, ccv
);
8457 insn
= gen_cmpxchg_acq_di (tmp
, mem
, new, ccv
);
8463 target
= gen_reg_rtx (rmode
);
8464 return emit_store_flag_force (target
, EQ
, tmp
, old
, mode
, 1, 1);
8470 /* Expand lock_test_and_set. I.e. `xchgsz ret = [ptr], new'. */
8473 ia64_expand_lock_test_and_set (enum machine_mode mode
, tree arglist
,
8477 rtx mem
, new, ret
, insn
;
8479 arg0
= TREE_VALUE (arglist
);
8480 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
8481 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8482 new = expand_expr (arg1
, NULL_RTX
, mode
, 0);
8484 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8485 MEM_VOLATILE_P (mem
) = 1;
8486 if (! register_operand (new, mode
))
8487 new = copy_to_mode_reg (mode
, new);
8489 if (target
&& register_operand (target
, mode
))
8492 ret
= gen_reg_rtx (mode
);
8495 insn
= gen_xchgsi (ret
, mem
, new);
8497 insn
= gen_xchgdi (ret
, mem
, new);
8503 /* Expand lock_release. I.e. `stsz.rel [ptr] = r0'. */
8506 ia64_expand_lock_release (enum machine_mode mode
, tree arglist
,
8507 rtx target ATTRIBUTE_UNUSED
)
8512 arg0
= TREE_VALUE (arglist
);
8513 mem
= expand_expr (arg0
, NULL_RTX
, ptr_mode
, 0);
8515 mem
= gen_rtx_MEM (mode
, force_reg (ptr_mode
, mem
));
8516 MEM_VOLATILE_P (mem
) = 1;
8518 emit_move_insn (mem
, const0_rtx
);
8524 ia64_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8525 enum machine_mode mode ATTRIBUTE_UNUSED
,
8526 int ignore ATTRIBUTE_UNUSED
)
8528 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
8529 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8530 tree arglist
= TREE_OPERAND (exp
, 1);
8531 enum machine_mode rmode
= VOIDmode
;
8535 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8536 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8541 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8542 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8543 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8544 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8545 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8546 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8547 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8548 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8549 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8550 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8551 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8552 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8553 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8554 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8558 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8563 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8568 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8569 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8570 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8571 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8572 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8573 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8574 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8575 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8576 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8577 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8578 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8579 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8580 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8581 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8591 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI
:
8592 case IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI
:
8593 return ia64_expand_compare_and_swap (rmode
, mode
, 1, arglist
,
8596 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI
:
8597 case IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI
:
8598 return ia64_expand_compare_and_swap (rmode
, mode
, 0, arglist
,
8601 case IA64_BUILTIN_SYNCHRONIZE
:
8602 emit_insn (gen_mf ());
8605 case IA64_BUILTIN_LOCK_TEST_AND_SET_SI
:
8606 case IA64_BUILTIN_LOCK_TEST_AND_SET_DI
:
8607 return ia64_expand_lock_test_and_set (mode
, arglist
, target
);
8609 case IA64_BUILTIN_LOCK_RELEASE_SI
:
8610 case IA64_BUILTIN_LOCK_RELEASE_DI
:
8611 return ia64_expand_lock_release (mode
, arglist
, target
);
8613 case IA64_BUILTIN_BSP
:
8614 if (! target
|| ! register_operand (target
, DImode
))
8615 target
= gen_reg_rtx (DImode
);
8616 emit_insn (gen_bsp_value (target
));
8617 #ifdef POINTERS_EXTEND_UNSIGNED
8618 target
= convert_memory_address (ptr_mode
, target
);
8622 case IA64_BUILTIN_FLUSHRS
:
8623 emit_insn (gen_flushrs ());
8626 case IA64_BUILTIN_FETCH_AND_ADD_SI
:
8627 case IA64_BUILTIN_FETCH_AND_ADD_DI
:
8628 return ia64_expand_fetch_and_op (add_optab
, mode
, arglist
, target
);
8630 case IA64_BUILTIN_FETCH_AND_SUB_SI
:
8631 case IA64_BUILTIN_FETCH_AND_SUB_DI
:
8632 return ia64_expand_fetch_and_op (sub_optab
, mode
, arglist
, target
);
8634 case IA64_BUILTIN_FETCH_AND_OR_SI
:
8635 case IA64_BUILTIN_FETCH_AND_OR_DI
:
8636 return ia64_expand_fetch_and_op (ior_optab
, mode
, arglist
, target
);
8638 case IA64_BUILTIN_FETCH_AND_AND_SI
:
8639 case IA64_BUILTIN_FETCH_AND_AND_DI
:
8640 return ia64_expand_fetch_and_op (and_optab
, mode
, arglist
, target
);
8642 case IA64_BUILTIN_FETCH_AND_XOR_SI
:
8643 case IA64_BUILTIN_FETCH_AND_XOR_DI
:
8644 return ia64_expand_fetch_and_op (xor_optab
, mode
, arglist
, target
);
8646 case IA64_BUILTIN_FETCH_AND_NAND_SI
:
8647 case IA64_BUILTIN_FETCH_AND_NAND_DI
:
8648 return ia64_expand_fetch_and_op (one_cmpl_optab
, mode
, arglist
, target
);
8650 case IA64_BUILTIN_ADD_AND_FETCH_SI
:
8651 case IA64_BUILTIN_ADD_AND_FETCH_DI
:
8652 return ia64_expand_op_and_fetch (add_optab
, mode
, arglist
, target
);
8654 case IA64_BUILTIN_SUB_AND_FETCH_SI
:
8655 case IA64_BUILTIN_SUB_AND_FETCH_DI
:
8656 return ia64_expand_op_and_fetch (sub_optab
, mode
, arglist
, target
);
8658 case IA64_BUILTIN_OR_AND_FETCH_SI
:
8659 case IA64_BUILTIN_OR_AND_FETCH_DI
:
8660 return ia64_expand_op_and_fetch (ior_optab
, mode
, arglist
, target
);
8662 case IA64_BUILTIN_AND_AND_FETCH_SI
:
8663 case IA64_BUILTIN_AND_AND_FETCH_DI
:
8664 return ia64_expand_op_and_fetch (and_optab
, mode
, arglist
, target
);
8666 case IA64_BUILTIN_XOR_AND_FETCH_SI
:
8667 case IA64_BUILTIN_XOR_AND_FETCH_DI
:
8668 return ia64_expand_op_and_fetch (xor_optab
, mode
, arglist
, target
);
8670 case IA64_BUILTIN_NAND_AND_FETCH_SI
:
8671 case IA64_BUILTIN_NAND_AND_FETCH_DI
:
8672 return ia64_expand_op_and_fetch (one_cmpl_optab
, mode
, arglist
, target
);
8681 /* For the HP-UX IA64 aggregate parameters are passed stored in the
8682 most significant bits of the stack slot. */
8685 ia64_hpux_function_arg_padding (enum machine_mode mode
, tree type
)
8687 /* Exception to normal case for structures/unions/etc. */
8689 if (type
&& AGGREGATE_TYPE_P (type
)
8690 && int_size_in_bytes (type
) < UNITS_PER_WORD
)
8693 /* Fall back to the default. */
8694 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8697 /* Linked list of all external functions that are to be emitted by GCC.
8698 We output the name if and only if TREE_SYMBOL_REFERENCED is set in
8699 order to avoid putting out names that are never really used. */
8701 struct extern_func_list
GTY(())
8703 struct extern_func_list
*next
;
8707 static GTY(()) struct extern_func_list
*extern_func_head
;
8710 ia64_hpux_add_extern_decl (tree decl
)
8712 struct extern_func_list
*p
= ggc_alloc (sizeof (struct extern_func_list
));
8715 p
->next
= extern_func_head
;
8716 extern_func_head
= p
;
8719 /* Print out the list of used global functions. */
8722 ia64_hpux_file_end (void)
8724 struct extern_func_list
*p
;
8726 for (p
= extern_func_head
; p
; p
= p
->next
)
8728 tree decl
= p
->decl
;
8729 tree id
= DECL_ASSEMBLER_NAME (decl
);
8734 if (!TREE_ASM_WRITTEN (decl
) && TREE_SYMBOL_REFERENCED (id
))
8736 const char *name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8738 TREE_ASM_WRITTEN (decl
) = 1;
8739 (*targetm
.asm_out
.globalize_label
) (asm_out_file
, name
);
8740 fputs (TYPE_ASM_OP
, asm_out_file
);
8741 assemble_name (asm_out_file
, name
);
8742 fprintf (asm_out_file
, "," TYPE_OPERAND_FMT
"\n", "function");
8746 extern_func_head
= 0;
8749 /* Set SImode div/mod functions, init_integral_libfuncs only initializes
8750 modes of word_mode and larger. Rename the TFmode libfuncs using the
8751 HPUX conventions. __divtf3 is used for XFmode. We need to keep it for
8752 backward compatibility. */
8755 ia64_init_libfuncs (void)
8757 set_optab_libfunc (sdiv_optab
, SImode
, "__divsi3");
8758 set_optab_libfunc (udiv_optab
, SImode
, "__udivsi3");
8759 set_optab_libfunc (smod_optab
, SImode
, "__modsi3");
8760 set_optab_libfunc (umod_optab
, SImode
, "__umodsi3");
8762 set_optab_libfunc (add_optab
, TFmode
, "_U_Qfadd");
8763 set_optab_libfunc (sub_optab
, TFmode
, "_U_Qfsub");
8764 set_optab_libfunc (smul_optab
, TFmode
, "_U_Qfmpy");
8765 set_optab_libfunc (sdiv_optab
, TFmode
, "_U_Qfdiv");
8766 set_optab_libfunc (neg_optab
, TFmode
, "_U_Qfneg");
8768 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_U_Qfcnvff_sgl_to_quad");
8769 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_U_Qfcnvff_dbl_to_quad");
8770 set_conv_libfunc (sext_optab
, TFmode
, XFmode
, "_U_Qfcnvff_f80_to_quad");
8771 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_U_Qfcnvff_quad_to_sgl");
8772 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_U_Qfcnvff_quad_to_dbl");
8773 set_conv_libfunc (trunc_optab
, XFmode
, TFmode
, "_U_Qfcnvff_quad_to_f80");
8775 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_U_Qfcnvfxt_quad_to_sgl");
8776 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_U_Qfcnvfxt_quad_to_dbl");
8777 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_U_Qfcnvfxut_quad_to_sgl");
8778 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_U_Qfcnvfxut_quad_to_dbl");
8780 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_U_Qfcnvxf_sgl_to_quad");
8781 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_U_Qfcnvxf_dbl_to_quad");
8784 /* Rename all the TFmode libfuncs using the HPUX conventions. */
8787 ia64_hpux_init_libfuncs (void)
8789 ia64_init_libfuncs ();
8791 set_optab_libfunc (smin_optab
, TFmode
, "_U_Qfmin");
8792 set_optab_libfunc (smax_optab
, TFmode
, "_U_Qfmax");
8793 set_optab_libfunc (abs_optab
, TFmode
, "_U_Qfabs");
8795 /* ia64_expand_compare uses this. */
8796 cmptf_libfunc
= init_one_libfunc ("_U_Qfcmp");
8798 /* These should never be used. */
8799 set_optab_libfunc (eq_optab
, TFmode
, 0);
8800 set_optab_libfunc (ne_optab
, TFmode
, 0);
8801 set_optab_libfunc (gt_optab
, TFmode
, 0);
8802 set_optab_libfunc (ge_optab
, TFmode
, 0);
8803 set_optab_libfunc (lt_optab
, TFmode
, 0);
8804 set_optab_libfunc (le_optab
, TFmode
, 0);
8807 /* Rename the division and modulus functions in VMS. */
8810 ia64_vms_init_libfuncs (void)
8812 set_optab_libfunc (sdiv_optab
, SImode
, "OTS$DIV_I");
8813 set_optab_libfunc (sdiv_optab
, DImode
, "OTS$DIV_L");
8814 set_optab_libfunc (udiv_optab
, SImode
, "OTS$DIV_UI");
8815 set_optab_libfunc (udiv_optab
, DImode
, "OTS$DIV_UL");
8816 set_optab_libfunc (smod_optab
, SImode
, "OTS$REM_I");
8817 set_optab_libfunc (smod_optab
, DImode
, "OTS$REM_L");
8818 set_optab_libfunc (umod_optab
, SImode
, "OTS$REM_UI");
8819 set_optab_libfunc (umod_optab
, DImode
, "OTS$REM_UL");
8822 /* Rename the TFmode libfuncs available from soft-fp in glibc using
8823 the HPUX conventions. */
8826 ia64_sysv4_init_libfuncs (void)
8828 ia64_init_libfuncs ();
8830 /* These functions are not part of the HPUX TFmode interface. We
8831 use them instead of _U_Qfcmp, which doesn't work the way we
8833 set_optab_libfunc (eq_optab
, TFmode
, "_U_Qfeq");
8834 set_optab_libfunc (ne_optab
, TFmode
, "_U_Qfne");
8835 set_optab_libfunc (gt_optab
, TFmode
, "_U_Qfgt");
8836 set_optab_libfunc (ge_optab
, TFmode
, "_U_Qfge");
8837 set_optab_libfunc (lt_optab
, TFmode
, "_U_Qflt");
8838 set_optab_libfunc (le_optab
, TFmode
, "_U_Qfle");
8840 /* We leave out _U_Qfmin, _U_Qfmax and _U_Qfabs since soft-fp in
8841 glibc doesn't have them. */
8844 /* Switch to the section to which we should output X. The only thing
8845 special we do here is to honor small data. */
8848 ia64_select_rtx_section (enum machine_mode mode
, rtx x
,
8849 unsigned HOST_WIDE_INT align
)
8851 if (GET_MODE_SIZE (mode
) > 0
8852 && GET_MODE_SIZE (mode
) <= ia64_section_threshold
)
8855 default_elf_select_rtx_section (mode
, x
, align
);
8858 /* It is illegal to have relocations in shared segments on AIX and HPUX.
8859 Pretend flag_pic is always set. */
8862 ia64_rwreloc_select_section (tree exp
, int reloc
, unsigned HOST_WIDE_INT align
)
8864 default_elf_select_section_1 (exp
, reloc
, align
, true);
8868 ia64_rwreloc_unique_section (tree decl
, int reloc
)
8870 default_unique_section_1 (decl
, reloc
, true);
8874 ia64_rwreloc_select_rtx_section (enum machine_mode mode
, rtx x
,
8875 unsigned HOST_WIDE_INT align
)
8877 int save_pic
= flag_pic
;
8879 ia64_select_rtx_section (mode
, x
, align
);
8880 flag_pic
= save_pic
;
8884 ia64_rwreloc_section_type_flags (tree decl
, const char *name
, int reloc
)
8886 return default_section_type_flags_1 (decl
, name
, reloc
, true);
8889 /* Returns true if FNTYPE (a FUNCTION_TYPE or a METHOD_TYPE) returns a
8890 structure type and that the address of that type should be passed
8891 in out0, rather than in r8. */
8894 ia64_struct_retval_addr_is_first_parm_p (tree fntype
)
8896 tree ret_type
= TREE_TYPE (fntype
);
8898 /* The Itanium C++ ABI requires that out0, rather than r8, be used
8899 as the structure return address parameter, if the return value
8900 type has a non-trivial copy constructor or destructor. It is not
8901 clear if this same convention should be used for other
8902 programming languages. Until G++ 3.4, we incorrectly used r8 for
8903 these return values. */
8904 return (abi_version_at_least (2)
8906 && TYPE_MODE (ret_type
) == BLKmode
8907 && TREE_ADDRESSABLE (ret_type
)
8908 && strcmp (lang_hooks
.name
, "GNU C++") == 0);
8911 /* Output the assembler code for a thunk function. THUNK_DECL is the
8912 declaration for the thunk function itself, FUNCTION is the decl for
8913 the target function. DELTA is an immediate constant offset to be
8914 added to THIS. If VCALL_OFFSET is nonzero, the word at
8915 *(*this + vcall_offset) should be added to THIS. */
8918 ia64_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
8919 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8922 rtx
this, insn
, funexp
;
8923 unsigned int this_parmno
;
8924 unsigned int this_regno
;
8926 reload_completed
= 1;
8927 epilogue_completed
= 1;
8929 reset_block_changes ();
8931 /* Set things up as ia64_expand_prologue might. */
8932 last_scratch_gr_reg
= 15;
8934 memset (¤t_frame_info
, 0, sizeof (current_frame_info
));
8935 current_frame_info
.spill_cfa_off
= -16;
8936 current_frame_info
.n_input_regs
= 1;
8937 current_frame_info
.need_regstk
= (TARGET_REG_NAMES
!= 0);
8939 /* Mark the end of the (empty) prologue. */
8940 emit_note (NOTE_INSN_PROLOGUE_END
);
8942 /* Figure out whether "this" will be the first parameter (the
8943 typical case) or the second parameter (as happens when the
8944 virtual function returns certain class objects). */
8946 = (ia64_struct_retval_addr_is_first_parm_p (TREE_TYPE (thunk
))
8948 this_regno
= IN_REG (this_parmno
);
8949 if (!TARGET_REG_NAMES
)
8950 reg_names
[this_regno
] = ia64_reg_numbers
[this_parmno
];
8952 this = gen_rtx_REG (Pmode
, this_regno
);
8955 rtx tmp
= gen_rtx_REG (ptr_mode
, this_regno
);
8956 REG_POINTER (tmp
) = 1;
8957 if (delta
&& CONST_OK_FOR_I (delta
))
8959 emit_insn (gen_ptr_extend_plus_imm (this, tmp
, GEN_INT (delta
)));
8963 emit_insn (gen_ptr_extend (this, tmp
));
8966 /* Apply the constant offset, if required. */
8969 rtx delta_rtx
= GEN_INT (delta
);
8971 if (!CONST_OK_FOR_I (delta
))
8973 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8974 emit_move_insn (tmp
, delta_rtx
);
8977 emit_insn (gen_adddi3 (this, this, delta_rtx
));
8980 /* Apply the offset from the vtable, if required. */
8983 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
8984 rtx tmp
= gen_rtx_REG (Pmode
, 2);
8988 rtx t
= gen_rtx_REG (ptr_mode
, 2);
8989 REG_POINTER (t
) = 1;
8990 emit_move_insn (t
, gen_rtx_MEM (ptr_mode
, this));
8991 if (CONST_OK_FOR_I (vcall_offset
))
8993 emit_insn (gen_ptr_extend_plus_imm (tmp
, t
,
8998 emit_insn (gen_ptr_extend (tmp
, t
));
9001 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this));
9005 if (!CONST_OK_FOR_J (vcall_offset
))
9007 rtx tmp2
= gen_rtx_REG (Pmode
, next_scratch_gr_reg ());
9008 emit_move_insn (tmp2
, vcall_offset_rtx
);
9009 vcall_offset_rtx
= tmp2
;
9011 emit_insn (gen_adddi3 (tmp
, tmp
, vcall_offset_rtx
));
9015 emit_move_insn (gen_rtx_REG (ptr_mode
, 2),
9016 gen_rtx_MEM (ptr_mode
, tmp
));
9018 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
9020 emit_insn (gen_adddi3 (this, this, tmp
));
9023 /* Generate a tail call to the target function. */
9024 if (! TREE_USED (function
))
9026 assemble_external (function
);
9027 TREE_USED (function
) = 1;
9029 funexp
= XEXP (DECL_RTL (function
), 0);
9030 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
9031 ia64_expand_call (NULL_RTX
, funexp
, NULL_RTX
, 1);
9032 insn
= get_last_insn ();
9033 SIBLING_CALL_P (insn
) = 1;
9035 /* Code generation for calls relies on splitting. */
9036 reload_completed
= 1;
9037 epilogue_completed
= 1;
9038 try_split (PATTERN (insn
), insn
, 0);
9042 /* Run just enough of rest_of_compilation to get the insns emitted.
9043 There's not really enough bulk here to make other passes such as
9044 instruction scheduling worth while. Note that use_thunk calls
9045 assemble_start_function and assemble_end_function. */
9047 insn_locators_initialize ();
9048 emit_all_insn_group_barriers (NULL
);
9049 insn
= get_insns ();
9050 shorten_branches (insn
);
9051 final_start_function (insn
, file
, 1);
9052 final (insn
, file
, 1, 0);
9053 final_end_function ();
9055 reload_completed
= 0;
9056 epilogue_completed
= 0;
9060 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9063 ia64_struct_value_rtx (tree fntype
,
9064 int incoming ATTRIBUTE_UNUSED
)
9066 if (fntype
&& ia64_struct_retval_addr_is_first_parm_p (fntype
))
9068 return gen_rtx_REG (Pmode
, GR_REG (8));
9071 #include "gt-ia64.h"