1 ;; IA-64 Machine description template
2 ;; Copyright (C) 1999, 2000 Free Software Foundation, Inc.
3 ;; Contributed by James E. Wilson <wilson@cygnus.com> and
4 ;; David Mosberger <davidm@hpl.hp.com>.
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; ??? Add support for long double XFmode patterns.
27 ;; ??? register_operand accepts (subreg:DI (mem:SI X)) which forces later
28 ;; reload. This will be fixed once scheduling support is turned on.
30 ;; ??? Optimize for post-increment addressing modes.
32 ;; ??? fselect is not supported, because there is no integer register
35 ;; ??? fp abs/min/max instructions may also work for integer values.
37 ;; ??? Would a predicate_reg_operand predicate be useful? The HP one is buggy,
38 ;; it assumes the operand is a register and takes REGNO of it without checking.
40 ;; ??? Would a branch_reg_operand predicate be useful? The HP one is buggy,
41 ;; it assumes the operand is a register and takes REGNO of it without checking.
43 ;; ??? Go through list of documented named patterns and look for more to
46 ;; ??? Go through instruction manual and look for more instructions that
49 ;; ??? Add function unit scheduling info for Itanium (TM) processor.
51 ;; ??? The explicit stop in the flushrs pattern is not ideal. It
52 ;; would be better if rtx_needs_barrier took care of this, but this is
53 ;; something that can be fixed later.
67 ;; 14 val_compare_and_swap
68 ;; 16 lock_test_and_set
78 ;; 2 insn_group_barrier
84 ;; ::::::::::::::::::::
88 ;; ::::::::::::::::::::
90 ;; Instruction type. This primarily determines how instructions can be
91 ;; packed in bundles, and secondarily affects scheduling to function units.
93 ;; A alu, can go in I or M syllable of a bundle
98 ;; L long immediate, takes two syllables
101 ;; ??? Should not have any pattern with type unknown. Perhaps add code to
102 ;; check this in md_reorg? Currently use unknown for patterns which emit
103 ;; multiple instructions, patterns which emit 0 instructions, and patterns
104 ;; which emit instruction that can go in any slot (e.g. nop).
106 (define_attr "type" "unknown,A,I,M,F,B,L,S" (const_string "unknown"))
108 ;; Predication. True iff this instruction can be predicated.
110 (define_attr "predicable" "no,yes" (const_string "yes"))
113 ;; ::::::::::::::::::::
117 ;; ::::::::::::::::::::
119 ;; Each usage of a function units by a class of insns is specified with a
120 ;; `define_function_unit' expression, which looks like this:
121 ;; (define_function_unit NAME MULTIPLICITY SIMULTANEITY TEST READY-DELAY
122 ;; ISSUE-DELAY [CONFLICT-LIST])
124 ;; This default scheduling info seeks to pack instructions into bundles
125 ;; efficiently to reduce code size, so we just list how many of each
126 ;; instruction type can go in a bundle. ISSUE_RATE is set to 3.
128 ;; ??? Add scheduler ready-list hook (MD_SCHED_REORDER) that orders
129 ;; instructions, so that the next instruction can fill the next bundle slot.
130 ;; This really needs to know where the stop bits are though.
132 ;; ??? Use MD_SCHED_REORDER to put alloc first instead of using an unspec
133 ;; volatile. Use ADJUST_PRIORITY to set the priority of alloc very high to
134 ;; make it schedule first.
136 ;; ??? Modify the md_reorg code that emits stop bits so that instead of putting
137 ;; them in the last possible place, we put them in places where bundles allow
138 ;; them. This should reduce code size, but may decrease performance if we end
139 ;; up with more stop bits than the minimum we need.
141 ;; Alu instructions can execute on either the integer or memory function
142 ;; unit. We indicate this by defining an alu function unit, and then marking
143 ;; it as busy everytime we issue a integer or memory type instruction.
145 (define_function_unit "alu" 3 1 (eq_attr "type" "A,I,M") 1 0)
147 (define_function_unit "integer" 2 1 (eq_attr "type" "I") 1 0)
149 (define_function_unit "memory" 3 1 (eq_attr "type" "M") 1 0)
151 (define_function_unit "floating_point" 1 1 (eq_attr "type" "F") 1 0)
153 (define_function_unit "branch" 3 1 (eq_attr "type" "B") 1 0)
155 ;; ??? This isn't quite right, because we can only fit two insns in a bundle
156 ;; when using an L type instruction. That isn't modeled currently.
158 (define_function_unit "long_immediate" 1 1 (eq_attr "type" "L") 1 0)
161 ;; ::::::::::::::::::::
165 ;; ::::::::::::::::::::
167 (define_expand "movqi"
168 [(set (match_operand:QI 0 "general_operand" "")
169 (match_operand:QI 1 "general_operand" ""))]
173 if (! reload_in_progress && ! reload_completed
174 && GET_CODE (operands[0]) == MEM
175 && GET_CODE (operands[1]) == MEM)
176 operands[1] = copy_to_mode_reg (QImode, operands[1]);
179 (define_insn "*movqi_internal"
180 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f")
181 (match_operand:QI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
182 "! memory_operand (operands[0], QImode)
183 || ! memory_operand (operands[1], QImode)"
192 [(set_attr "type" "A,A,M,M,M,M,F")])
194 (define_expand "movhi"
195 [(set (match_operand:HI 0 "general_operand" "")
196 (match_operand:HI 1 "general_operand" ""))]
200 if (! reload_in_progress && ! reload_completed
201 && GET_CODE (operands[0]) == MEM
202 && GET_CODE (operands[1]) == MEM)
203 operands[1] = copy_to_mode_reg (HImode, operands[1]);
206 (define_insn "*movhi_internal"
207 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, r,*f,*f")
208 (match_operand:HI 1 "move_operand" "rO,J,m,rO,*f,rO,*f"))]
209 "! memory_operand (operands[0], HImode)
210 || !memory_operand (operands[1], HImode)"
219 [(set_attr "type" "A,A,M,M,M,M,F")])
221 (define_expand "movsi"
222 [(set (match_operand:SI 0 "general_operand" "")
223 (match_operand:SI 1 "general_operand" ""))]
227 if (! reload_in_progress && ! reload_completed
228 && GET_CODE (operands[0]) == MEM
229 && GET_CODE (operands[1]) == MEM)
230 operands[1] = copy_to_mode_reg (SImode, operands[1]);
233 (define_insn "*movsi_internal"
234 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f")
235 (match_operand:SI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f"))]
236 "! memory_operand (operands[0], SImode)
237 || ! memory_operand (operands[1], SImode)"
247 [(set_attr "type" "A,A,L,M,M,M,M,F")])
249 (define_expand "movdi"
250 [(set (match_operand:DI 0 "general_operand" "")
251 (match_operand:DI 1 "general_operand" ""))]
255 /* ??? Should generalize this, so that we can also support 32 bit
257 if (! TARGET_NO_PIC && symbolic_operand (operands[1], DImode))
261 /* Operand[0] could be a MEM, which isn't a valid destination for the
262 PIC load address patterns. */
263 if (! register_operand (operands[0], DImode))
264 temp = gen_reg_rtx (DImode);
269 emit_insn (gen_load_gprel64 (temp, operands[1]));
270 else if (GET_CODE (operands[1]) == SYMBOL_REF
271 && SYMBOL_REF_FLAG (operands[1]))
272 emit_insn (gen_load_fptr (temp, operands[1]));
273 else if (sdata_symbolic_operand (operands[1], DImode))
274 emit_insn (gen_load_gprel (temp, operands[1]));
276 emit_insn (gen_load_symptr (temp, operands[1]));
278 if (temp == operands[0])
284 if (! reload_in_progress && ! reload_completed
285 && GET_CODE (operands[0]) == MEM
286 && GET_CODE (operands[1]) == MEM)
287 operands[1] = copy_to_mode_reg (DImode, operands[1]);
290 (define_insn "*movdi_internal"
291 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r, m, r,*f,*f,*f, m, r,*b")
292 (match_operand:DI 1 "move_operand" "rO,J,i,m,rO,*f,rO,*f, m,*f,*b,rO"))]
293 "! memory_operand (operands[0], DImode)
294 || ! memory_operand (operands[1], DImode)"
308 [(set_attr "type" "A,A,L,M,M,M,M,F,M,M,I,I")])
310 (define_expand "load_fptr"
312 (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "")))
313 (set (match_operand:DI 0 "register_operand" "") (mem:DI (match_dup 2)))]
317 if (reload_in_progress)
318 operands[2] = operands[0];
320 operands[2] = gen_reg_rtx (DImode);
323 (define_insn "*load_fptr_internal1"
324 [(set (match_operand:DI 0 "register_operand" "=r")
325 (plus:DI (reg:DI 1) (match_operand:DI 1 "function_operand" "s")))]
327 "addl %0 = @ltoff(@fptr(%1)), gp"
328 [(set_attr "type" "A")])
330 (define_insn "load_gprel"
331 [(set (match_operand:DI 0 "register_operand" "=r")
332 (plus:DI (reg:DI 1) (match_operand:DI 1 "sdata_symbolic_operand" "s")))]
334 "addl %0 = @gprel(%1), gp"
335 [(set_attr "type" "A")])
337 (define_insn "gprel64_offset"
338 [(set (match_operand:DI 0 "register_operand" "=r")
339 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))]
341 "movl %0 = @gprel(%1)"
342 [(set_attr "type" "L")])
344 (define_expand "load_gprel64"
346 (minus:DI (match_operand:DI 1 "symbolic_operand" "") (reg:DI 1)))
347 (set (match_operand:DI 0 "register_operand" "")
348 (plus:DI (reg:DI 1) (match_dup 2)))]
351 if (reload_in_progress)
352 operands[2] = operands[0];
354 operands[2] = gen_reg_rtx (DImode);
357 (define_expand "load_symptr"
359 (plus:DI (reg:DI 1) (match_operand:DI 1 "symbolic_operand" "")))
360 (set (match_operand:DI 0 "register_operand" "") (mem:DI (match_dup 2)))]
364 if (reload_in_progress)
365 operands[2] = operands[0];
367 operands[2] = gen_reg_rtx (DImode);
370 (define_insn "*load_symptr_internal1"
371 [(set (match_operand:DI 0 "register_operand" "=r")
372 (plus:DI (reg:DI 1) (match_operand:DI 1 "symbolic_operand" "s")))]
374 "addl %0 = @ltoff(%1), gp"
375 [(set_attr "type" "A")])
377 ;; Floating Point Moves
379 ;; Note - Patterns for SF mode moves are compulsory, but
380 ;; patterns for DF are optional, as GCC can synthesise them.
382 (define_expand "movsf"
383 [(set (match_operand:SF 0 "general_operand" "")
384 (match_operand:SF 1 "general_operand" ""))]
388 if (! reload_in_progress && ! reload_completed
389 && GET_CODE (operands[0]) == MEM
390 && GET_CODE (operands[1]) == MEM)
391 operands[1] = copy_to_mode_reg (SFmode, operands[1]);
394 (define_insn "*movsf_internal"
395 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
396 (match_operand:SF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
397 "! memory_operand (operands[0], SFmode)
398 || ! memory_operand (operands[1], SFmode)"
408 [(set_attr "type" "F,M,M,M,M,A,M,M")])
410 (define_expand "movdf"
411 [(set (match_operand:DF 0 "general_operand" "")
412 (match_operand:DF 1 "general_operand" ""))]
416 if (! reload_in_progress && ! reload_completed
417 && GET_CODE (operands[0]) == MEM
418 && GET_CODE (operands[1]) == MEM)
419 operands[1] = copy_to_mode_reg (DFmode, operands[1]);
422 (define_insn "*movdf_internal"
423 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f, m,*r, f,*r,*r, m")
424 (match_operand:DF 1 "general_operand" "fG,m,fG,fG,*r,*r, m,*r"))]
425 "! memory_operand (operands[0], DFmode)
426 || ! memory_operand (operands[1], DFmode)"
436 [(set_attr "type" "F,M,M,M,M,A,M,M")])
438 (define_expand "movxf"
439 [(set (match_operand:XF 0 "general_operand" "")
440 (match_operand:XF 1 "general_operand" ""))]
444 if (! reload_in_progress && ! reload_completed
445 && GET_CODE (operands[0]) == MEM
446 && GET_CODE (operands[1]) == MEM)
447 operands[1] = copy_to_mode_reg (XFmode, operands[1]);
450 (define_insn "*movxf_internal"
451 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f, m")
452 (match_operand:XF 1 "general_operand" "fG,m,fG"))]
453 "! memory_operand (operands[0], XFmode)
454 || ! memory_operand (operands[1], XFmode)"
459 [(set_attr "type" "F,M,M")])
462 ;; ::::::::::::::::::::
466 ;; ::::::::::::::::::::
468 ;; Signed conversions from a smaller integer to a larger integer
470 (define_insn "extendqidi2"
471 [(set (match_operand:DI 0 "register_operand" "=r")
472 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
475 [(set_attr "type" "I")])
477 (define_insn "extendhidi2"
478 [(set (match_operand:DI 0 "register_operand" "=r")
479 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
482 [(set_attr "type" "I")])
484 (define_insn "extendsidi2"
485 [(set (match_operand:DI 0 "register_operand" "=r,*f")
486 (sign_extend:DI (match_operand:SI 1 "register_operand" "r,*f")))]
490 fsxt.r %0 = %1, %1%B0"
491 [(set_attr "type" "I,F")])
493 ;; Unsigned conversions from a smaller integer to a larger integer
495 (define_insn "zero_extendqidi2"
496 [(set (match_operand:DI 0 "register_operand" "=r,r")
497 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
502 [(set_attr "type" "I,M")])
504 (define_insn "zero_extendhidi2"
505 [(set (match_operand:DI 0 "register_operand" "=r,r")
506 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
511 [(set_attr "type" "I,M")])
513 (define_insn "zero_extendsidi2"
514 [(set (match_operand:DI 0 "register_operand" "=r,r,*f")
515 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m,*f")))]
520 fsxt.r %0 = f1, %1%B0"
521 [(set_attr "type" "I,M,F")])
523 ;; Convert between floating point types of different sizes.
525 ;; ??? Optimization opportunity here. Get rid of the insn altogether
526 ;; when we can. Should probably use a scheme like has been proposed
527 ;; for ia32 in dealing with operands that match unary operators. This
528 ;; would let combine merge the thing into adjacent insns.
530 (define_insn_and_split "extendsfdf2"
531 [(set (match_operand:DF 0 "register_operand" "=f,f")
532 (float_extend:DF (match_operand:SF 1 "register_operand" "0,f")))]
536 [(set (match_dup 0) (float_extend:DF (match_dup 1)))]
537 "if (true_regnum (operands[0]) == true_regnum (operands[1])) DONE;"
538 [(set_attr "type" "F")])
540 (define_insn "truncdfsf2"
541 [(set (match_operand:SF 0 "register_operand" "=f")
542 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
545 [(set_attr "type" "F")])
547 (define_insn "truncxfsf2"
548 [(set (match_operand:SF 0 "register_operand" "=f")
549 (float_truncate:SF (match_operand:XF 1 "register_operand" "f")))]
552 [(set_attr "type" "F")])
554 (define_insn "truncxfdf2"
555 [(set (match_operand:DF 0 "register_operand" "=f")
556 (float_truncate:DF (match_operand:XF 1 "register_operand" "f")))]
559 [(set_attr "type" "F")])
561 ;; Convert between signed integer types and floating point.
563 (define_insn "floatdixf2"
564 [(set (match_operand:XF 0 "register_operand" "=f")
565 (float:XF (match_operand:DI 1 "register_operand" "f")))]
568 [(set_attr "type" "F")])
570 (define_insn "fix_truncsfdi2"
571 [(set (match_operand:DI 0 "register_operand" "=f")
572 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
574 "fcvt.fx.trunc %0 = %1%B0"
575 [(set_attr "type" "F")])
577 (define_insn "fix_truncdfdi2"
578 [(set (match_operand:DI 0 "register_operand" "=f")
579 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
581 "fcvt.fx.trunc %0 = %1%B0"
582 [(set_attr "type" "F")])
584 ;; Convert between unsigned integer types and floating point.
586 (define_insn "floatunsdisf2"
587 [(set (match_operand:SF 0 "register_operand" "=f")
588 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
590 "fcvt.xuf.s %0 = %1%B0"
591 [(set_attr "type" "F")])
593 (define_insn "floatunsdidf2"
594 [(set (match_operand:DF 0 "register_operand" "=f")
595 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
597 "fcvt.xuf.d %0 = %1%B0"
598 [(set_attr "type" "F")])
600 (define_insn "fixuns_truncsfdi2"
601 [(set (match_operand:DI 0 "register_operand" "=f")
602 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "f")))]
604 "fcvt.fxu.trunc %0 = %1%B0"
605 [(set_attr "type" "F")])
607 (define_insn "fixuns_truncdfdi2"
608 [(set (match_operand:DI 0 "register_operand" "=f")
609 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f")))]
611 "fcvt.fxu.trunc %0 = %1%B0"
612 [(set_attr "type" "F")])
615 ;; ::::::::::::::::::::
617 ;; :: Bit field extraction
619 ;; ::::::::::::::::::::
621 ;; ??? It would be useful to have SImode versions of the extract and insert
625 [(set (match_operand:DI 0 "register_operand" "=r")
626 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
627 (match_operand:DI 2 "const_int_operand" "n")
628 (match_operand:DI 3 "const_int_operand" "n")))]
630 "extr %0 = %1, %3, %2"
631 [(set_attr "type" "I")])
634 [(set (match_operand:DI 0 "register_operand" "=r")
635 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
636 (match_operand:DI 2 "const_int_operand" "n")
637 (match_operand:DI 3 "const_int_operand" "n")))]
639 "extr.u %0 = %1, %3, %2"
640 [(set_attr "type" "I")])
642 ;; Insert a bit field.
643 ;; Can have 3 operands, source1 (inserter), source2 (insertee), dest.
644 ;; Source1 can be 0 or -1.
647 ;; ??? Actual dep instruction is more powerful than what these insv
648 ;; patterns support. Unfortunately, combine is unable to create patterns
649 ;; where source2 != dest.
651 (define_expand "insv"
652 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
653 (match_operand:DI 1 "const_int_operand" "")
654 (match_operand:DI 2 "const_int_operand" ""))
655 (match_operand:DI 3 "nonmemory_operand" ""))]
659 int width = INTVAL (operands[1]);
660 int shift = INTVAL (operands[2]);
662 /* If operand[3] is a constant, and isn't 0 or -1, then load it into a
664 if (! register_operand (operands[3], DImode)
665 && operands[3] != const0_rtx && operands[3] != constm1_rtx)
666 operands[3] = force_reg (DImode, operands[3]);
668 /* If this is a single dep instruction, we have nothing to do. */
669 if (! ((register_operand (operands[3], DImode) && width <= 16)
670 || operands[3] == const0_rtx || operands[3] == constm1_rtx))
672 /* Check for cases that can be implemented with a mix instruction. */
673 if (width == 32 && shift == 0)
675 /* Directly generating the mix4left instruction confuses
676 optimize_bit_field in function.c. Since this is performing
677 a useful optimization, we defer generation of the complicated
678 mix4left RTL to the first splitting phase. */
679 rtx tmp = gen_reg_rtx (DImode);
680 emit_insn (gen_shift_mix4left (operands[0], operands[3], tmp));
683 else if (width == 32 && shift == 32)
685 emit_insn (gen_mix4right (operands[0], operands[3]));
689 /* We could handle remaining cases by emitting multiple dep
692 If we need more than two dep instructions then we lose. A 6
693 insn sequence mov mask1,mov mask2,shl;;and,and;;or is better than
694 mov;;dep,shr;;dep,shr;;dep. The former can be executed in 3 cycles,
695 the latter is 6 cycles on an Itanium (TM) processor, because there is
696 only one function unit that can execute dep and shr immed.
698 If we only need two dep instruction, then we still lose.
699 mov;;dep,shr;;dep is still 4 cycles. Even if we optimize away
700 the unnecessary mov, this is still undesirable because it will be
701 hard to optimize, and it creates unnecessary pressure on the I0
707 /* This code may be useful for other IA-64 processors, so we leave it in
713 emit_insn (gen_insv (operands[0], GEN_INT (16), GEN_INT (shift),
717 tmp = gen_reg_rtx (DImode);
718 emit_insn (gen_lshrdi3 (tmp, operands[3], GEN_INT (16)));
721 operands[1] = GEN_INT (width);
722 operands[2] = GEN_INT (shift);
727 (define_insn "*insv_internal"
728 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
729 (match_operand:DI 1 "const_int_operand" "n")
730 (match_operand:DI 2 "const_int_operand" "n"))
731 (match_operand:DI 3 "nonmemory_operand" "rP"))]
732 "(register_operand (operands[3], DImode) && INTVAL (operands[1]) <= 16)
733 || operands[3] == const0_rtx || operands[3] == constm1_rtx"
734 "dep %0 = %3, %0, %2, %1"
735 [(set_attr "type" "I")])
737 (define_insn "shift_mix4left"
738 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
739 (const_int 32) (const_int 0))
740 (match_operand:DI 1 "register_operand" "r"))
741 (clobber (match_operand:DI 2 "register_operand" "=r"))]
744 [(set_attr "type" "unknown")])
746 ;; ??? Need to emit an instruction group barrier here because this gets split
750 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
751 (const_int 32) (const_int 0))
752 (match_operand:DI 1 "register_operand" ""))
753 (clobber (match_operand:DI 2 "register_operand" ""))]
755 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
756 (unspec_volatile [(const_int 0)] 2)
757 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
758 (lshiftrt:DI (match_dup 3) (const_int 32)))]
759 "operands[3] = operands[2];")
762 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "")
763 (const_int 32) (const_int 0))
764 (match_operand:DI 1 "register_operand" ""))
765 (clobber (match_operand:DI 2 "register_operand" ""))]
767 [(set (match_dup 3) (ashift:DI (match_dup 1) (const_int 32)))
768 (set (zero_extract:DI (match_dup 0) (const_int 32) (const_int 0))
769 (lshiftrt:DI (match_dup 3) (const_int 32)))]
770 "operands[3] = operands[2];")
772 (define_insn "*mix4left"
773 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
774 (const_int 32) (const_int 0))
775 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
778 "mix4.l %0 = %0, %r1"
779 [(set_attr "type" "I")])
781 (define_insn "mix4right"
782 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
783 (const_int 32) (const_int 32))
784 (match_operand:DI 1 "reg_or_0_operand" "rO"))]
786 "mix4.r %0 = %r1, %0"
787 [(set_attr "type" "I")])
789 ;; This is used by the rotrsi3 pattern.
791 (define_insn "*mix4right_3op"
792 [(set (match_operand:DI 0 "register_operand" "=r")
793 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
794 (ashift:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))
798 [(set_attr "type" "I")])
801 ;; ::::::::::::::::::::
803 ;; :: 32 bit Integer arithmetic
805 ;; ::::::::::::::::::::
807 ;; We handle 32-bit arithmetic just like the alpha port does.
809 (define_expand "addsi3"
810 [(set (match_operand:SI 0 "register_operand" "")
811 (plus:SI (match_operand:SI 1 "register_operand" "")
812 (match_operand:SI 2 "reg_or_22bit_operand" "")))]
818 rtx op1 = gen_lowpart (DImode, operands[1]);
819 rtx op2 = gen_lowpart (DImode, operands[2]);
821 if (! cse_not_expected)
823 rtx tmp = gen_reg_rtx (DImode);
824 emit_insn (gen_adddi3 (tmp, op1, op2));
825 emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
828 emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
833 (define_insn "*addsi3_internal"
834 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
835 (plus:SI (match_operand:SI 1 "register_operand" "%r,r,a")
836 (match_operand:SI 2 "reg_or_22bit_operand" "r,I,J")))]
842 [(set_attr "type" "A")])
844 (define_insn "*addsi3_plus1"
845 [(set (match_operand:SI 0 "register_operand" "=r")
846 (plus:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
847 (match_operand:SI 2 "register_operand" "r"))
851 [(set_attr "type" "A")])
853 (define_expand "subsi3"
854 [(set (match_operand:SI 0 "register_operand" "")
855 (minus:SI (match_operand:SI 1 "reg_or_8bit_operand" "")
856 (match_operand:SI 2 "register_operand" "")))]
862 rtx op1 = gen_lowpart (DImode, operands[1]);
863 rtx op2 = gen_lowpart (DImode, operands[2]);
865 if (! cse_not_expected)
867 rtx tmp = gen_reg_rtx (DImode);
868 emit_insn (gen_subdi3 (tmp, op1, op2));
869 emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
872 emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
877 (define_insn "*subsi3_internal"
878 [(set (match_operand:SI 0 "register_operand" "=r")
879 (minus:SI (match_operand:SI 1 "reg_or_8bit_operand" "rK")
880 (match_operand:SI 2 "register_operand" "r")))]
883 [(set_attr "type" "A")])
885 (define_insn "*subsi3_minus1"
886 [(set (match_operand:SI 0 "register_operand" "=r")
887 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
888 (match_operand:SI 2 "register_operand" "r")))]
891 [(set_attr "type" "A")])
893 (define_expand "mulsi3"
894 [(set (match_operand:SI 0 "register_operand" "")
895 (mult:SI (match_operand:SI 1 "register_operand" "")
896 (match_operand:SI 2 "register_operand" "")))]
902 rtx op1 = gen_lowpart (DImode, operands[1]);
903 rtx op2 = gen_lowpart (DImode, operands[2]);
905 if (! cse_not_expected)
907 rtx tmp = gen_reg_rtx (DImode);
908 emit_insn (gen_muldi3 (tmp, op1, op2));
909 emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
912 emit_insn (gen_muldi3 (gen_lowpart (DImode, operands[0]), op1, op2));
917 ;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
919 (define_insn "*mulsi3_internal"
920 [(set (match_operand:SI 0 "register_operand" "=f")
921 (mult:SI (match_operand:SI 1 "register_operand" "f")
922 (match_operand:SI 2 "nonmemory_operand" "f")))]
924 "xma.l %0 = %1, %2, f0%B0"
925 [(set_attr "type" "F")])
927 (define_expand "negsi2"
928 [(set (match_operand:SI 0 "register_operand" "")
929 (neg:SI (match_operand:SI 1 "register_operand" "")))]
935 rtx op1 = gen_lowpart (DImode, operands[1]);
937 if (! cse_not_expected)
939 rtx tmp = gen_reg_rtx (DImode);
940 emit_insn (gen_negdi2 (tmp, op1));
941 emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
944 emit_insn (gen_negdi2 (gen_lowpart (DImode, operands[0]), op1));
949 (define_insn "*negsi2_internal"
950 [(set (match_operand:SI 0 "register_operand" "=r")
951 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
954 [(set_attr "type" "A")])
956 (define_expand "abssi2"
958 (ge:CC (match_operand:SI 1 "register_operand" "") (const_int 0)))
959 (set (match_operand:SI 0 "register_operand" "")
960 (if_then_else:SI (eq:CC (match_dup 2) (const_int 0))
961 (neg:SI (match_dup 1))
966 operands[2] = gen_reg_rtx (CCmode);
969 (define_expand "sminsi3"
971 (ge:CC (match_operand:SI 1 "register_operand" "")
972 (match_operand:SI 2 "register_operand" "")))
973 (set (match_operand:SI 0 "register_operand" "")
974 (if_then_else:SI (ne:CC (match_dup 3) (const_int 0))
975 (match_dup 2) (match_dup 1)))]
979 operands[3] = gen_reg_rtx (CCmode);
982 (define_expand "smaxsi3"
984 (ge:CC (match_operand:SI 1 "register_operand" "")
985 (match_operand:SI 2 "register_operand" "")))
986 (set (match_operand:SI 0 "register_operand" "")
987 (if_then_else:SI (ne:CC (match_dup 3) (const_int 0))
988 (match_dup 1) (match_dup 2)))]
992 operands[3] = gen_reg_rtx (CCmode);
995 (define_expand "uminsi3"
997 (geu:CC (match_operand:SI 1 "register_operand" "")
998 (match_operand:SI 2 "register_operand" "")))
999 (set (match_operand:SI 0 "register_operand" "")
1000 (if_then_else:SI (ne:CC (match_dup 3) (const_int 0))
1001 (match_dup 2) (match_dup 1)))]
1005 operands[3] = gen_reg_rtx (CCmode);
1008 (define_expand "umaxsi3"
1010 (geu:CC (match_operand:SI 1 "register_operand" "")
1011 (match_operand:SI 2 "register_operand" "")))
1012 (set (match_operand:SI 0 "register_operand" "")
1013 (if_then_else:SI (ne:CC (match_dup 3) (const_int 0))
1014 (match_dup 1) (match_dup 2)))]
1018 operands[3] = gen_reg_rtx (CCmode);
1022 ;; ::::::::::::::::::::
1024 ;; :: 64 bit Integer arithmetic
1026 ;; ::::::::::::::::::::
1028 (define_insn "adddi3"
1029 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1030 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
1031 (match_operand:DI 2 "reg_or_22bit_operand" "r,I,J")))]
1037 [(set_attr "type" "A")])
1039 (define_insn "*adddi3_plus1"
1040 [(set (match_operand:DI 0 "register_operand" "=r")
1041 (plus:DI (plus:DI (match_operand:DI 1 "register_operand" "r")
1042 (match_operand:DI 2 "register_operand" "r"))
1045 "add %0 = %1, %2, 1"
1046 [(set_attr "type" "A")])
1048 (define_insn "subdi3"
1049 [(set (match_operand:DI 0 "register_operand" "=r")
1050 (minus:DI (match_operand:DI 1 "reg_or_8bit_operand" "rK")
1051 (match_operand:DI 2 "register_operand" "r")))]
1054 [(set_attr "type" "A")])
1056 (define_insn "*subdi3_minus1"
1057 [(set (match_operand:DI 0 "register_operand" "=r")
1058 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
1059 (match_operand:DI 2 "register_operand" "r")))]
1061 "sub %0 = %2, %1, 1"
1062 [(set_attr "type" "A")])
1064 (define_insn "muldi3"
1065 [(set (match_operand:DI 0 "register_operand" "=f")
1066 (mult:DI (match_operand:DI 1 "register_operand" "f")
1067 (match_operand:DI 2 "register_operand" "f")))]
1069 "xma.l %0 = %1, %2, f0%B0"
1070 [(set_attr "type" "F")])
1072 ;; ??? If operand 3 is an eliminable reg, then register elimination causes the
1073 ;; same problem that we have with shladd below. Unfortunately, this case is
1074 ;; much harder to fix because the multiply puts the result in an FP register,
1075 ;; but the add needs inputs from a general register. We add a spurious clobber
1076 ;; here so that it will be present just in case register elimination gives us
1077 ;; the funny result.
1079 ;; ??? Maybe validate_changes should try adding match_scratch clobbers?
1081 ;; ??? Maybe we should change how adds are canonicalized.
1083 (define_insn "*madddi3"
1084 [(set (match_operand:DI 0 "register_operand" "=f")
1085 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
1086 (match_operand:DI 2 "register_operand" "f"))
1087 (match_operand:DI 3 "register_operand" "f")))
1088 (clobber (match_scratch:DI 4 "=X"))]
1090 "xma.l %0 = %1, %2, %3%B0"
1091 [(set_attr "type" "F")])
1093 ;; This can be created by register elimination if operand3 of shladd is an
1094 ;; eliminable register or has reg_equiv_constant set.
1096 ;; We have to use nonmemory_operand for operand 4, to ensure that the
1097 ;; validate_changes call inside eliminate_regs will always succeed. If it
1098 ;; doesn't succeed, then this remain a madddi3 pattern, and will be reloaded
1101 (define_insn "*madddi3_elim"
1102 [(set (match_operand:DI 0 "register_operand" "=&r")
1103 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "f")
1104 (match_operand:DI 2 "register_operand" "f"))
1105 (match_operand:DI 3 "register_operand" "f"))
1106 (match_operand:DI 4 "nonmemory_operand" "rI")))
1107 (clobber (match_scratch:DI 5 "=f"))]
1108 "reload_in_progress"
1110 [(set_attr "type" "unknown")])
1112 ;; ??? Need to emit an instruction group barrier here because this gets split
1116 [(set (match_operand:DI 0 "register_operand" "")
1117 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
1118 (match_operand:DI 2 "register_operand" ""))
1119 (match_operand:DI 3 "register_operand" ""))
1120 (match_operand:DI 4 "reg_or_14bit_operand" "")))
1121 (clobber (match_scratch:DI 5 ""))]
1123 [(parallel [(set (match_dup 5) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
1125 (clobber (match_dup 0))])
1126 (unspec_volatile [(const_int 0)] 2)
1127 (set (match_dup 0) (match_dup 5))
1128 (unspec_volatile [(const_int 0)] 2)
1129 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
1132 ;; ??? There are highpart multiply and add instructions, but we have no way
1133 ;; to generate them.
1135 (define_insn "smuldi3_highpart"
1136 [(set (match_operand:DI 0 "register_operand" "=f")
1139 (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "f"))
1140 (sign_extend:TI (match_operand:DI 2 "register_operand" "f")))
1143 "xma.h %0 = %1, %2, f0%B0"
1144 [(set_attr "type" "F")])
1146 (define_insn "umuldi3_highpart"
1147 [(set (match_operand:DI 0 "register_operand" "=f")
1150 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "f"))
1151 (zero_extend:TI (match_operand:DI 2 "register_operand" "f")))
1154 "xma.hu %0 = %1, %2, f0%B0"
1155 [(set_attr "type" "F")])
1157 (define_insn "negdi2"
1158 [(set (match_operand:DI 0 "register_operand" "=r")
1159 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
1162 [(set_attr "type" "A")])
1164 (define_expand "absdi2"
1166 (ge:CC (match_operand:DI 1 "register_operand" "") (const_int 0)))
1167 (set (match_operand:DI 0 "register_operand" "")
1168 (if_then_else:DI (eq:CC (match_dup 2) (const_int 0))
1169 (neg:DI (match_dup 1))
1174 operands[2] = gen_reg_rtx (CCmode);
1177 (define_expand "smindi3"
1179 (ge:CC (match_operand:DI 1 "register_operand" "")
1180 (match_operand:DI 2 "register_operand" "")))
1181 (set (match_operand:DI 0 "register_operand" "")
1182 (if_then_else:DI (ne:CC (match_dup 3) (const_int 0))
1183 (match_dup 2) (match_dup 1)))]
1187 operands[3] = gen_reg_rtx (CCmode);
1190 (define_expand "smaxdi3"
1192 (ge:CC (match_operand:DI 1 "register_operand" "")
1193 (match_operand:DI 2 "register_operand" "")))
1194 (set (match_operand:DI 0 "register_operand" "")
1195 (if_then_else:DI (ne:CC (match_dup 3) (const_int 0))
1196 (match_dup 1) (match_dup 2)))]
1200 operands[3] = gen_reg_rtx (CCmode);
1203 (define_expand "umindi3"
1205 (geu:CC (match_operand:DI 1 "register_operand" "")
1206 (match_operand:DI 2 "register_operand" "")))
1207 (set (match_operand:DI 0 "register_operand" "")
1208 (if_then_else:DI (ne:CC (match_dup 3) (const_int 0))
1209 (match_dup 2) (match_dup 1)))]
1213 operands[3] = gen_reg_rtx (CCmode);
1216 (define_expand "umaxdi3"
1218 (geu:CC (match_operand:DI 1 "register_operand" "")
1219 (match_operand:DI 2 "register_operand" "")))
1220 (set (match_operand:DI 0 "register_operand" "")
1221 (if_then_else:DI (ne:CC (match_dup 3) (const_int 0))
1222 (match_dup 1) (match_dup 2)))]
1226 operands[3] = gen_reg_rtx (CCmode);
1229 (define_expand "ffsdi2"
1231 (eq:CC (match_operand:DI 1 "register_operand" "") (const_int 0)))
1232 (set (match_dup 2) (plus:DI (match_dup 1) (const_int -1)))
1233 (set (match_dup 5) (const_int 0))
1234 (set (match_dup 3) (xor:DI (match_dup 1) (match_dup 2)))
1235 (set (match_dup 4) (unspec:DI [(match_dup 3)] 8))
1236 (set (match_operand:DI 0 "register_operand" "")
1237 (if_then_else:DI (ne:CC (match_dup 6) (const_int 0))
1238 (match_dup 5) (match_dup 4)))]
1242 operands[2] = gen_reg_rtx (DImode);
1243 operands[3] = gen_reg_rtx (DImode);
1244 operands[4] = gen_reg_rtx (DImode);
1245 operands[5] = gen_reg_rtx (DImode);
1246 operands[6] = gen_reg_rtx (CCmode);
1249 (define_insn "*popcnt"
1250 [(set (match_operand:DI 0 "register_operand" "=r")
1251 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 8))]
1254 [(set_attr "type" "I")])
1257 ;; ::::::::::::::::::::
1259 ;; :: 32 bit floating point arithmetic
1261 ;; ::::::::::::::::::::
1263 (define_insn "addsf3"
1264 [(set (match_operand:SF 0 "register_operand" "=f")
1265 (plus:SF (match_operand:SF 1 "register_operand" "%f")
1266 (match_operand:SF 2 "reg_or_fp01_operand" "fG")))]
1268 "fadd.s %0 = %1, %F2%B0"
1269 [(set_attr "type" "F")])
1271 (define_insn "subsf3"
1272 [(set (match_operand:SF 0 "register_operand" "=f")
1273 (minus:SF (match_operand:SF 1 "reg_or_fp01_operand" "fG")
1274 (match_operand:SF 2 "reg_or_fp01_operand" "fG")))]
1276 "fsub.s %0 = %F1, %F2%B0"
1277 [(set_attr "type" "F")])
1279 (define_insn "mulsf3"
1280 [(set (match_operand:SF 0 "register_operand" "=f")
1281 (mult:SF (match_operand:SF 1 "register_operand" "%f")
1282 (match_operand:SF 2 "register_operand" "f")))]
1284 "fmpy.s %0 = %1, %2%B0"
1285 [(set_attr "type" "F")])
1287 (define_insn "abssf2"
1288 [(set (match_operand:SF 0 "register_operand" "=f")
1289 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
1292 [(set_attr "type" "F")])
1294 (define_insn "negsf2"
1295 [(set (match_operand:SF 0 "register_operand" "=f")
1296 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
1299 [(set_attr "type" "F")])
1301 (define_insn "*nabssf2"
1302 [(set (match_operand:SF 0 "register_operand" "=f")
1303 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
1305 "fnegabs %0 = %1%B0"
1306 [(set_attr "type" "F")])
1308 (define_insn "minsf3"
1309 [(set (match_operand:SF 0 "register_operand" "=f")
1310 (smin:SF (match_operand:SF 1 "register_operand" "f")
1311 (match_operand:SF 2 "reg_or_fp01_operand" "fG")))]
1313 "fmin %0 = %1, %F2%B0"
1314 [(set_attr "type" "F")])
1316 (define_insn "maxsf3"
1317 [(set (match_operand:SF 0 "register_operand" "=f")
1318 (smax:SF (match_operand:SF 1 "register_operand" "f")
1319 (match_operand:SF 2 "reg_or_fp01_operand" "fG")))]
1321 "fmax %0 = %1, %F2%B0"
1322 [(set_attr "type" "F")])
1324 (define_insn "*maddsf3"
1325 [(set (match_operand:SF 0 "register_operand" "=f")
1326 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
1327 (match_operand:SF 2 "register_operand" "f"))
1328 (match_operand:SF 3 "reg_or_fp01_operand" "fG")))]
1330 "fma.s %0 = %1, %2, %F3%B0"
1331 [(set_attr "type" "F")])
1333 (define_insn "*msubsf3"
1334 [(set (match_operand:SF 0 "register_operand" "=f")
1335 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
1336 (match_operand:SF 2 "register_operand" "f"))
1337 (match_operand:SF 3 "reg_or_fp01_operand" "fG")))]
1339 "fms.s %0 = %1, %2, %F3%B0"
1340 [(set_attr "type" "F")])
1342 (define_insn "*nmulsf3"
1343 [(set (match_operand:SF 0 "register_operand" "=f")
1344 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
1345 (match_operand:SF 2 "register_operand" "f"))))]
1347 "fnmpy.s %0 = %1, %2%B0"
1348 [(set_attr "type" "F")])
1350 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
1352 (define_insn "*nmaddsf3"
1353 [(set (match_operand:SF 0 "register_operand" "=f")
1354 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
1355 (match_operand:SF 2 "register_operand" "f")))
1356 (match_operand:SF 3 "reg_or_fp01_operand" "fG")))]
1358 "fnma.s %0 = %1, %2, %F3%B0"
1359 [(set_attr "type" "F")])
1362 ;; ::::::::::::::::::::
1364 ;; :: 64 bit floating point arithmetic
1366 ;; ::::::::::::::::::::
1368 (define_insn "adddf3"
1369 [(set (match_operand:DF 0 "register_operand" "=f")
1370 (plus:DF (match_operand:DF 1 "register_operand" "%f")
1371 (match_operand:DF 2 "reg_or_fp01_operand" "fG")))]
1373 "fadd.d %0 = %1, %F2%B0"
1374 [(set_attr "type" "F")])
1376 (define_insn "subdf3"
1377 [(set (match_operand:DF 0 "register_operand" "=f")
1378 (minus:DF (match_operand:DF 1 "reg_or_fp01_operand" "fG")
1379 (match_operand:DF 2 "reg_or_fp01_operand" "fG")))]
1381 "fsub.d %0 = %F1, %F2%B0"
1382 [(set_attr "type" "F")])
1384 (define_insn "muldf3"
1385 [(set (match_operand:DF 0 "register_operand" "=f")
1386 (mult:DF (match_operand:DF 1 "register_operand" "f")
1387 (match_operand:DF 2 "register_operand" "f")))]
1389 "fmpy.d %0 = %1, %2%B0"
1390 [(set_attr "type" "F")])
1392 (define_insn "absdf2"
1393 [(set (match_operand:DF 0 "register_operand" "=f")
1394 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
1397 [(set_attr "type" "F")])
1399 (define_insn "negdf2"
1400 [(set (match_operand:DF 0 "register_operand" "=f")
1401 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
1404 [(set_attr "type" "F")])
1406 (define_insn "*nabsdf2"
1407 [(set (match_operand:DF 0 "register_operand" "=f")
1408 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
1410 "fnegabs %0 = %1%B0"
1411 [(set_attr "type" "F")])
1413 (define_insn "mindf3"
1414 [(set (match_operand:DF 0 "register_operand" "=f")
1415 (smin:DF (match_operand:DF 1 "register_operand" "f")
1416 (match_operand:DF 2 "reg_or_fp01_operand" "fG")))]
1418 "fmin %0 = %1, %F2%B0"
1419 [(set_attr "type" "F")])
1421 (define_insn "maxdf3"
1422 [(set (match_operand:DF 0 "register_operand" "=f")
1423 (smax:DF (match_operand:DF 1 "register_operand" "f")
1424 (match_operand:DF 2 "reg_or_fp01_operand" "fG")))]
1426 "fmax %0 = %1, %F2%B0"
1427 [(set_attr "type" "F")])
1429 (define_insn "*madddf3"
1430 [(set (match_operand:DF 0 "register_operand" "=f")
1431 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
1432 (match_operand:DF 2 "register_operand" "f"))
1433 (match_operand:DF 3 "reg_or_fp01_operand" "fG")))]
1435 "fma.d %0 = %1, %2, %F3%B0"
1436 [(set_attr "type" "F")])
1438 (define_insn "*msubdf3"
1439 [(set (match_operand:DF 0 "register_operand" "=f")
1440 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
1441 (match_operand:DF 2 "register_operand" "f"))
1442 (match_operand:DF 3 "reg_or_fp01_operand" "fG")))]
1444 "fms.d %0 = %1, %2, %F3%B0"
1445 [(set_attr "type" "F")])
1447 (define_insn "*nmuldf3"
1448 [(set (match_operand:DF 0 "register_operand" "=f")
1449 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
1450 (match_operand:DF 2 "register_operand" "f"))))]
1452 "fnmpy.d %0 = %1, %2%B0"
1453 [(set_attr "type" "F")])
1455 ;; ??? Is it possible to canonicalize this as (minus (reg) (mult))?
1457 (define_insn "*nmadddf3"
1458 [(set (match_operand:DF 0 "register_operand" "=f")
1459 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
1460 (match_operand:DF 2 "register_operand" "f")))
1461 (match_operand:DF 3 "reg_or_fp01_operand" "fG")))]
1463 "fnma.d %0 = %1, %2, %F3%B0"
1464 [(set_attr "type" "F")])
1467 ;; ::::::::::::::::::::
1469 ;; :: 32 bit Integer Shifts and Rotates
1471 ;; ::::::::::::::::::::
1473 ;; There is no sign-extend form of dep, so we only get 32 bits of valid result
1474 ;; instead of 64 like the patterns below.
1476 ;; Using a predicate that accepts only constants doesn't work, because optabs
1477 ;; will load the operand into a register and call the pattern if the predicate
1478 ;; did not accept it on the first try. So we use nonmemory_operand and then
1479 ;; verify that we have an appropriate constant in the expander.
1481 (define_expand "ashlsi3"
1482 [(set (match_operand:SI 0 "register_operand" "")
1483 (ashift:SI (match_operand:SI 1 "register_operand" "")
1484 (match_operand:SI 2 "nonmemory_operand" "")))]
1488 if (! shift_32bit_count_operand (operands[2], SImode))
1492 (define_insn "*ashlsi3_internal"
1493 [(set (match_operand:SI 0 "register_operand" "=r")
1494 (ashift:SI (match_operand:SI 1 "register_operand" "r")
1495 (match_operand:SI 2 "shift_32bit_count_operand" "n")))]
1497 "dep.z %0 = %1, %2, %E2"
1498 [(set_attr "type" "I")])
1500 ;; This is really an extract, but this is how combine canonicalizes the
1503 (define_expand "ashrsi3"
1505 (ashiftrt:DI (sign_extend:DI
1506 (match_operand:SI 1 "register_operand" ""))
1507 (match_operand:DI 2 "nonmemory_operand" "")))
1508 (set (match_operand:SI 0 "register_operand" "") (match_dup 4))]
1512 if (! shift_32bit_count_operand (operands[2], SImode))
1515 operands[3] = gen_reg_rtx (DImode);
1516 operands[4] = gen_lowpart (SImode, operands[3]);
1519 (define_insn "*ashrsi3_internal"
1520 [(set (match_operand:DI 0 "register_operand" "=r")
1521 (ashiftrt:DI (sign_extend:DI
1522 (match_operand:SI 1 "register_operand" "r"))
1523 (match_operand:DI 2 "shift_32bit_count_operand" "n")))]
1525 "extr %0 = %1, %2, %E2"
1526 [(set_attr "type" "I")])
1528 ;; This is really an extract, but this is how combine canonicalizes the
1531 (define_expand "lshrsi3"
1533 (lshiftrt:DI (zero_extend:DI
1534 (match_operand:SI 1 "register_operand" ""))
1535 (match_operand:DI 2 "nonmemory_operand" "")))
1536 (set (match_operand:SI 0 "register_operand" "") (match_dup 4))]
1540 if (! shift_32bit_count_operand (operands[2], SImode))
1543 operands[3] = gen_reg_rtx (DImode);
1544 operands[4] = gen_lowpart (SImode, operands[3]);
1547 (define_insn "*lshrsi3_internal"
1548 [(set (match_operand:DI 0 "register_operand" "=r")
1549 (lshiftrt:DI (zero_extend:DI
1550 (match_operand:SI 1 "register_operand" "r"))
1551 (match_operand:DI 2 "shift_32bit_count_operand" "n")))]
1553 "extr.u %0 = %1, %2, %E2"
1554 [(set_attr "type" "I")])
1556 ;; Use mix4.r/shr to implement rotrsi3. We only get 32 bits of valid result
1557 ;; here, instead of 64 like the patterns above.
1559 (define_expand "rotrsi3"
1561 (ior:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
1562 (ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
1564 (lshiftrt:DI (match_dup 3)
1565 (match_operand:DI 2 "nonmemory_operand" "")))
1566 (set (match_operand:SI 0 "register_operand" "") (match_dup 4))]
1570 if (! shift_32bit_count_operand (operands[2], SImode))
1573 operands[3] = gen_reg_rtx (DImode);
1574 operands[4] = gen_lowpart (SImode, operands[3]);
1578 ;; ::::::::::::::::::::
1580 ;; :: 64 bit Integer Shifts and Rotates
1582 ;; ::::::::::::::::::::
1584 (define_insn "ashldi3"
1585 [(set (match_operand:DI 0 "register_operand" "=r")
1586 (ashift:DI (match_operand:DI 1 "register_operand" "r")
1587 (match_operand:DI 2 "reg_or_6bit_operand" "rM")))]
1590 [(set_attr "type" "I")])
1592 ;; ??? Maybe combine this with the multiply and add instruction?
1594 (define_insn "*shladd"
1595 [(set (match_operand:DI 0 "register_operand" "=r")
1596 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "r")
1597 (match_operand:DI 2 "shladd_operand" "n"))
1598 (match_operand:DI 3 "register_operand" "r")))]
1600 "shladd %0 = %1, %S2, %3"
1601 [(set_attr "type" "A")])
1603 ;; This can be created by register elimination if operand3 of shladd is an
1604 ;; eliminable register or has reg_equiv_constant set.
1606 ;; We have to use nonmemory_operand for operand 4, to ensure that the
1607 ;; validate_changes call inside eliminate_regs will always succeed. If it
1608 ;; doesn't succeed, then this remain a shladd pattern, and will be reloaded
1611 (define_insn "*shladd_elim"
1612 [(set (match_operand:DI 0 "register_operand" "=&r")
1613 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "r")
1614 (match_operand:DI 2 "shladd_operand" "n"))
1615 (match_operand:DI 3 "register_operand" "r"))
1616 (match_operand:DI 4 "nonmemory_operand" "rI")))]
1617 "reload_in_progress"
1619 [(set_attr "type" "unknown")])
1621 ;; ??? Need to emit an instruction group barrier here because this gets split
1625 [(set (match_operand:DI 0 "register_operand" "")
1626 (plus:DI (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
1627 (match_operand:DI 2 "shladd_operand" ""))
1628 (match_operand:DI 3 "register_operand" ""))
1629 (match_operand:DI 4 "reg_or_14bit_operand" "")))]
1631 [(set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (match_dup 2))
1633 (unspec_volatile [(const_int 0)] 2)
1634 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
1637 (define_insn "ashrdi3"
1638 [(set (match_operand:DI 0 "register_operand" "=r")
1639 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
1640 (match_operand:DI 2 "reg_or_6bit_operand" "rM")))]
1643 [(set_attr "type" "I")])
1645 (define_insn "lshrdi3"
1646 [(set (match_operand:DI 0 "register_operand" "=r")
1647 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
1648 (match_operand:DI 2 "reg_or_6bit_operand" "rM")))]
1651 [(set_attr "type" "I")])
1653 ;; Using a predicate that accepts only constants doesn't work, because optabs
1654 ;; will load the operand into a register and call the pattern if the predicate
1655 ;; did not accept it on the first try. So we use nonmemory_operand and then
1656 ;; verify that we have an appropriate constant in the expander.
1658 (define_expand "rotrdi3"
1659 [(set (match_operand:DI 0 "register_operand" "")
1660 (rotatert:DI (match_operand:DI 1 "register_operand" "")
1661 (match_operand:DI 2 "nonmemory_operand" "")))]
1665 if (! shift_count_operand (operands[2], DImode))
1669 (define_insn "*rotrdi3_internal"
1670 [(set (match_operand:DI 0 "register_operand" "=r")
1671 (rotatert:DI (match_operand:DI 1 "register_operand" "r")
1672 (match_operand:DI 2 "shift_count_operand" "M")))]
1674 "shrp %0 = %1, %1, %2"
1675 [(set_attr "type" "I")])
1678 ;; ::::::::::::::::::::
1680 ;; :: 32 Bit Integer Logical operations
1682 ;; ::::::::::::::::::::
1684 ;; We don't seem to need any other 32-bit logical operations, because gcc
1685 ;; generates zero-extend;zero-extend;DImode-op, which combine optimizes to
1686 ;; DImode-op;zero-extend, and then we can optimize away the zero-extend.
1687 ;; This doesn't work for unary logical operations, because we don't call
1688 ;; apply_distributive_law for them.
1690 ;; ??? Likewise, this doesn't work for andnot, which isn't handled by
1691 ;; apply_distributive_law. We get inefficient code for
1692 ;; int sub4 (int i, int j) { return i & ~j; }
1693 ;; We could convert (and (not (sign_extend A)) (sign_extend B)) to
1694 ;; (zero_extend (and (not A) B)) in combine.
1695 ;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
1696 ;; one_cmplsi2 pattern.
1698 (define_expand "one_cmplsi2"
1699 [(set (match_operand:SI 0 "register_operand" "")
1700 (not:SI (match_operand:SI 1 "register_operand" "")))]
1706 rtx op1 = gen_lowpart (DImode, operands[1]);
1708 if (! cse_not_expected)
1710 rtx tmp = gen_reg_rtx (DImode);
1711 emit_insn (gen_one_cmpldi2 (tmp, op1));
1712 emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
1715 emit_insn (gen_one_cmpldi2 (gen_lowpart (DImode, operands[0]), op1));
1720 (define_insn "*one_cmplsi2_internal"
1721 [(set (match_operand:SI 0 "register_operand" "=r")
1722 (not:SI (match_operand:SI 1 "register_operand" "r")))]
1725 [(set_attr "type" "A")])
1728 ;; ::::::::::::::::::::
1730 ;; :: 64 Bit Integer Logical operations
1732 ;; ::::::::::::::::::::
1734 (define_insn "anddi3"
1735 [(set (match_operand:DI 0 "register_operand" "=r,*f")
1736 (and:DI (match_operand:DI 1 "register_operand" "%r,*f")
1737 (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
1741 fand %0 = %2, %1%B0"
1742 [(set_attr "type" "A,F")])
1744 (define_insn "*andnot"
1745 [(set (match_operand:DI 0 "register_operand" "=r,*f")
1746 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r,*f"))
1747 (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
1751 fandcm %0 = %2, %1%B0"
1752 [(set_attr "type" "A,F")])
1754 (define_insn "iordi3"
1755 [(set (match_operand:DI 0 "register_operand" "=r,*f")
1756 (ior:DI (match_operand:DI 1 "register_operand" "%r,*f")
1757 (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
1762 [(set_attr "type" "A,F")])
1764 (define_insn "xordi3"
1765 [(set (match_operand:DI 0 "register_operand" "=r,*f")
1766 (xor:DI (match_operand:DI 1 "register_operand" "%r,*f")
1767 (match_operand:DI 2 "reg_or_8bit_operand" "rK,*f")))]
1771 fxor %0 = %2, %1%B0"
1772 [(set_attr "type" "A,F")])
1774 (define_insn "one_cmpldi2"
1775 [(set (match_operand:DI 0 "register_operand" "=r")
1776 (not:DI (match_operand:DI 1 "register_operand" "r")))]
1779 [(set_attr "type" "A")])
1781 ;; ::::::::::::::::::::
1785 ;; ::::::::::::::::::::
1787 (define_expand "cmpsi"
1789 (compare (match_operand:SI 0 "register_operand" "")
1790 (match_operand:SI 1 "reg_or_8bit_and_adjusted_operand" "")))]
1794 ia64_compare_op0 = operands[0];
1795 ia64_compare_op1 = operands[1];
1799 (define_expand "cmpdi"
1801 (compare (match_operand:DI 0 "register_operand" "")
1802 (match_operand:DI 1 "reg_or_8bit_and_adjusted_operand" "")))]
1806 ia64_compare_op0 = operands[0];
1807 ia64_compare_op1 = operands[1];
1811 (define_expand "cmpsf"
1813 (compare (match_operand:SF 0 "reg_or_fp01_operand" "")
1814 (match_operand:SF 1 "reg_or_fp01_operand" "")))]
1818 ia64_compare_op0 = operands[0];
1819 ia64_compare_op1 = operands[1];
1823 (define_expand "cmpdf"
1825 (compare (match_operand:DF 0 "reg_or_fp01_operand" "")
1826 (match_operand:DF 1 "reg_or_fp01_operand" "")))]
1830 ia64_compare_op0 = operands[0];
1831 ia64_compare_op1 = operands[1];
1835 ;; ??? Enable this for XFmode support.
1837 (define_expand "cmpxf"
1839 (compare (match_operand:XF 0 "reg_or_fp01_operand" "")
1840 (match_operand:XF 1 "reg_or_fp01_operand" "")))]
1844 ia64_compare_op0 = operands[0];
1845 ia64_compare_op1 = operands[1];
1849 (define_insn "*cmpsi_normal"
1850 [(set (match_operand:CC 0 "register_operand" "=c")
1851 (match_operator:CC 1 "normal_comparison_operator"
1852 [(match_operand:SI 2 "register_operand" "r")
1853 (match_operand:SI 3 "reg_or_8bit_operand" "rK")]))]
1855 "cmp4.%C1 %0, %I0 = %3, %2"
1856 [(set_attr "type" "A")])
1858 (define_insn "*cmpsi_adjusted"
1859 [(set (match_operand:CC 0 "register_operand" "=c")
1860 (match_operator:CC 1 "adjusted_comparison_operator"
1861 [(match_operand:SI 2 "register_operand" "r")
1862 (match_operand:SI 3 "reg_or_8bit_adjusted_operand"
1865 "cmp4.%C1 %0, %I0 = %3, %2"
1866 [(set_attr "type" "A")])
1868 (define_insn "*cmpdi_normal"
1869 [(set (match_operand:CC 0 "register_operand" "=c")
1870 (match_operator:CC 1 "normal_comparison_operator"
1871 [(match_operand:DI 2 "register_operand" "r")
1872 (match_operand:DI 3 "reg_or_8bit_operand" "rK")]))]
1874 "cmp.%C1 %0, %I0 = %3, %2"
1875 [(set_attr "type" "A")])
1877 (define_insn "*cmpdi_adjusted"
1878 [(set (match_operand:CC 0 "register_operand" "=c")
1879 (match_operator:CC 1 "adjusted_comparison_operator"
1880 [(match_operand:DI 2 "register_operand" "r")
1881 (match_operand:DI 3 "reg_or_8bit_adjusted_operand"
1884 "cmp.%C1 %0, %I0 = %3, %2"
1885 [(set_attr "type" "A")])
1887 (define_insn "*cmpsf_internal"
1888 [(set (match_operand:CC 0 "register_operand" "=c")
1889 (match_operator:CC 1 "comparison_operator"
1890 [(match_operand:SF 2 "reg_or_fp01_operand" "fG")
1891 (match_operand:SF 3 "reg_or_fp01_operand" "fG")]))]
1893 "fcmp.%D1 %0, %I0 = %F2, %F3"
1894 [(set_attr "type" "F")])
1896 (define_insn "*cmpdf_internal"
1897 [(set (match_operand:CC 0 "register_operand" "=c")
1898 (match_operator:CC 1 "comparison_operator"
1899 [(match_operand:DF 2 "reg_or_fp01_operand" "fG")
1900 (match_operand:DF 3 "reg_or_fp01_operand" "fG")]))]
1902 "fcmp.%D1 %0, %I0 = %F2, %F3"
1903 [(set_attr "type" "F")])
1905 ;; ??? Can this pattern be generated?
1907 (define_insn "*bit_zero"
1908 [(set (match_operand:CC 0 "register_operand" "=c")
1909 (eq:CC (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
1911 (match_operand:DI 2 "immediate_operand" "n"))
1914 "tbit.z %0, %I0 = %1, %2"
1915 [(set_attr "type" "I")])
1917 (define_insn "*bit_one"
1918 [(set (match_operand:CC 0 "register_operand" "=c")
1919 (ne:CC (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
1921 (match_operand:DI 2 "immediate_operand" "n"))
1924 "tbit.nz %0, %I0 = %1, %2"
1925 [(set_attr "type" "I")])
1927 ;; ??? We also need this if we run out of PR regs and need to spill some.
1929 ;; ??? We need this if a CCmode value does not get allocated to a hard
1930 ;; register. This happens if we cse/gcse a CCmode value across a call, and the
1931 ;; function has a nonlocal goto. This is because global does not allocate
1932 ;; call crossing pseudos to hard registers when current_function_has_
1933 ;; nonlocal_goto is true. This is relatively common for C++ programs that
1934 ;; use exceptions. See ia64_secondary_reload_class.
1936 ;; We use a define_expand here so that cse/gcse/combine can't accidentally
1937 ;; create movcc insns. If this was a named define_insn, we would not be able
1938 ;; to make it conditional on reload.
1940 (define_expand "movcc"
1941 [(set (match_operand:CC 0 "nonimmediate_operand" "")
1942 (match_operand:CC 1 "move_operand" ""))]
1946 if (! reload_in_progress && ! reload_completed)
1950 (define_insn "*movcc_internal"
1951 [(set (match_operand:CC 0 "nonimmediate_operand" "=r,c,r,m")
1952 (match_operand:CC 1 "move_operand" "c,r,m,r"))]
1953 "reload_in_progress || reload_completed"
1956 cmp4.ne %0, %I0 = %1, r0
1959 [(set_attr "type" "unknown,A,M,M")])
1962 [(set (match_operand:CC 0 "register_operand" "")
1963 (match_operand:CC 1 "register_operand" ""))]
1965 && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
1966 && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
1968 (if_then_else:DI (ne:CC (match_dup 1) (const_int 0))
1972 (if_then_else:DI (ne:CC (match_dup 1) (const_int 0))
1975 "operands[2] = gen_rtx_SUBREG (DImode, operands[0], 0);")
1978 ;; ::::::::::::::::::::
1982 ;; ::::::::::::::::::::
1984 (define_expand "beq"
1986 (eq:CC (match_dup 2)
1989 (if_then_else (ne:CC (match_dup 1)
1991 (label_ref (match_operand 0 "" ""))
1996 operands[1] = gen_reg_rtx (CCmode);
1997 operands[2] = ia64_compare_op0;
1998 operands[3] = ia64_compare_op1;
2001 (define_expand "bne"
2003 (ne:CC (match_dup 2)
2006 (if_then_else (ne:CC (match_dup 1)
2008 (label_ref (match_operand 0 "" ""))
2013 operands[1] = gen_reg_rtx (CCmode);
2014 operands[2] = ia64_compare_op0;
2015 operands[3] = ia64_compare_op1;
2018 (define_expand "blt"
2020 (lt:CC (match_dup 2)
2023 (if_then_else (ne:CC (match_dup 1)
2025 (label_ref (match_operand 0 "" ""))
2030 operands[1] = gen_reg_rtx (CCmode);
2031 operands[2] = ia64_compare_op0;
2032 operands[3] = ia64_compare_op1;
2035 (define_expand "ble"
2037 (le:CC (match_dup 2)
2040 (if_then_else (ne:CC (match_dup 1)
2042 (label_ref (match_operand 0 "" ""))
2047 operands[1] = gen_reg_rtx (CCmode);
2048 operands[2] = ia64_compare_op0;
2049 operands[3] = ia64_compare_op1;
2052 (define_expand "bgt"
2054 (gt:CC (match_dup 2)
2057 (if_then_else (ne:CC (match_dup 1)
2059 (label_ref (match_operand 0 "" ""))
2064 operands[1] = gen_reg_rtx (CCmode);
2065 operands[2] = ia64_compare_op0;
2066 operands[3] = ia64_compare_op1;
2069 (define_expand "bge"
2071 (ge:CC (match_dup 2)
2074 (if_then_else (ne:CC (match_dup 1)
2076 (label_ref (match_operand 0 "" ""))
2081 operands[1] = gen_reg_rtx (CCmode);
2082 operands[2] = ia64_compare_op0;
2083 operands[3] = ia64_compare_op1;
2086 (define_expand "bltu"
2088 (ltu:CC (match_dup 2)
2091 (if_then_else (ne:CC (match_dup 1)
2093 (label_ref (match_operand 0 "" ""))
2098 operands[1] = gen_reg_rtx (CCmode);
2099 operands[2] = ia64_compare_op0;
2100 operands[3] = ia64_compare_op1;
2103 (define_expand "bleu"
2105 (leu:CC (match_dup 2)
2108 (if_then_else (ne:CC (match_dup 1)
2110 (label_ref (match_operand 0 "" ""))
2115 operands[1] = gen_reg_rtx (CCmode);
2116 operands[2] = ia64_compare_op0;
2117 operands[3] = ia64_compare_op1;
2120 (define_expand "bgtu"
2122 (gtu:CC (match_dup 2)
2125 (if_then_else (ne:CC (match_dup 1)
2127 (label_ref (match_operand 0 "" ""))
2132 operands[1] = gen_reg_rtx (CCmode);
2133 operands[2] = ia64_compare_op0;
2134 operands[3] = ia64_compare_op1;
2137 (define_expand "bgeu"
2139 (geu:CC (match_dup 2)
2142 (if_then_else (ne:CC (match_dup 1)
2144 (label_ref (match_operand 0 "" ""))
2149 operands[1] = gen_reg_rtx (CCmode);
2150 operands[2] = ia64_compare_op0;
2151 operands[3] = ia64_compare_op1;
2154 (define_insn "*br_true"
2156 (if_then_else (match_operator 0 "predicate_operator"
2157 [(match_operand:CC 1 "register_operand" "c")
2159 (label_ref (match_operand 2 "" ""))
2162 "(%J0) br.cond%+ %l2"
2163 [(set_attr "type" "B")
2164 (set_attr "predicable" "no")])
2166 (define_insn "*br_false"
2168 (if_then_else (match_operator 0 "predicate_operator"
2169 [(match_operand:CC 1 "register_operand" "c")
2172 (label_ref (match_operand 2 "" ""))))]
2174 "(%j0) br.cond%+ %l2"
2175 [(set_attr "type" "B")
2176 (set_attr "predicable" "no")])
2178 ;; ::::::::::::::::::::
2180 ;; :: Set flag operations
2182 ;; ::::::::::::::::::::
2184 (define_expand "seq"
2186 (eq:CC (match_dup 2)
2188 (set (match_operand:DI 0 "register_operand" "")
2189 (ne:DI (match_dup 1) (const_int 0)))]
2193 operands[1] = gen_reg_rtx (CCmode);
2194 operands[2] = ia64_compare_op0;
2195 operands[3] = ia64_compare_op1;
2198 (define_expand "sne"
2200 (ne:CC (match_dup 2)
2202 (set (match_operand:DI 0 "register_operand" "")
2203 (ne:DI (match_dup 1) (const_int 0)))]
2207 operands[1] = gen_reg_rtx (CCmode);
2208 operands[2] = ia64_compare_op0;
2209 operands[3] = ia64_compare_op1;
2212 (define_expand "slt"
2214 (lt:CC (match_dup 2)
2216 (set (match_operand:DI 0 "register_operand" "")
2217 (ne:DI (match_dup 1) (const_int 0)))]
2221 operands[1] = gen_reg_rtx (CCmode);
2222 operands[2] = ia64_compare_op0;
2223 operands[3] = ia64_compare_op1;
2226 (define_expand "sle"
2228 (le:CC (match_dup 2)
2230 (set (match_operand:DI 0 "register_operand" "")
2231 (ne:DI (match_dup 1) (const_int 0)))]
2235 operands[1] = gen_reg_rtx (CCmode);
2236 operands[2] = ia64_compare_op0;
2237 operands[3] = ia64_compare_op1;
2240 (define_expand "sgt"
2242 (gt:CC (match_dup 2)
2244 (set (match_operand:DI 0 "register_operand" "")
2245 (ne:DI (match_dup 1) (const_int 0)))]
2249 operands[1] = gen_reg_rtx (CCmode);
2250 operands[2] = ia64_compare_op0;
2251 operands[3] = ia64_compare_op1;
2254 (define_expand "sge"
2256 (ge:CC (match_dup 2)
2258 (set (match_operand:DI 0 "register_operand" "")
2259 (ne:DI (match_dup 1) (const_int 0)))]
2263 operands[1] = gen_reg_rtx (CCmode);
2264 operands[2] = ia64_compare_op0;
2265 operands[3] = ia64_compare_op1;
2268 (define_expand "sltu"
2270 (ltu:CC (match_dup 2)
2272 (set (match_operand:DI 0 "register_operand" "")
2273 (ne:DI (match_dup 1) (const_int 0)))]
2277 operands[1] = gen_reg_rtx (CCmode);
2278 operands[2] = ia64_compare_op0;
2279 operands[3] = ia64_compare_op1;
2282 (define_expand "sleu"
2284 (leu:CC (match_dup 2)
2286 (set (match_operand:DI 0 "register_operand" "")
2287 (ne:DI (match_dup 1) (const_int 0)))]
2291 operands[1] = gen_reg_rtx (CCmode);
2292 operands[2] = ia64_compare_op0;
2293 operands[3] = ia64_compare_op1;
2296 (define_expand "sgtu"
2298 (gtu:CC (match_dup 2)
2300 (set (match_operand:DI 0 "register_operand" "")
2301 (ne:DI (match_dup 1) (const_int 0)))]
2305 operands[1] = gen_reg_rtx (CCmode);
2306 operands[2] = ia64_compare_op0;
2307 operands[3] = ia64_compare_op1;
2310 (define_expand "sgeu"
2312 (geu:CC (match_dup 2)
2314 (set (match_operand:DI 0 "register_operand" "")
2315 (ne:DI (match_dup 1) (const_int 0)))]
2319 operands[1] = gen_reg_rtx (CCmode);
2320 operands[2] = ia64_compare_op0;
2321 operands[3] = ia64_compare_op1;
2324 ;; Don't allow memory as destination here, because cmov/cmov/st is more
2325 ;; efficient than mov/mov/cst/cst.
2327 (define_insn "*sne_internal"
2328 [(set (match_operand:DI 0 "register_operand" "=r")
2329 (ne:DI (match_operand:CC 1 "register_operand" "c")
2333 [(set_attr "type" "unknown")])
2336 [(set (match_operand:DI 0 "register_operand" "")
2337 (ne:DI (match_operand:CC 1 "register_operand" "")
2341 (if_then_else:DI (ne:CC (match_dup 1) (const_int 0))
2345 (if_then_else:DI (ne:CC (match_dup 1) (const_int 0))
2350 ;; ??? Unknown if this can be matched.
2352 (define_insn "*seq_internal"
2353 [(set (match_operand:DI 0 "register_operand" "=r")
2354 (eq:DI (match_operand:CC 1 "register_operand" "c")
2358 [(set_attr "type" "unknown")])
2360 ;; ??? Unknown if this can be matched.
2363 [(set (match_operand:DI 0 "register_operand" "")
2364 (eq:DI (match_operand:CC 1 "register_operand" "")
2368 (if_then_else:DI (eq:CC (match_dup 1) (const_int 0))
2372 (if_then_else:DI (eq:CC (match_dup 1) (const_int 0))
2378 ;; ::::::::::::::::::::
2380 ;; :: Conditional move instructions.
2382 ;; ::::::::::::::::::::
2384 ;; ??? Add movXXcc patterns?
2386 ;; ??? The predicates don't match the constraints.
2388 ;; ??? r/c/m/m and m/c/r/r alternatives make sense, but won't work until the
2389 ;; predicates are fixed, because the define_splits won't recognize them.
2392 ;; DImode if_then_else patterns.
2395 (define_insn "*cmovdi_internal"
2396 [(set (match_operand:DI 0 "register_operand" "=r,r,m,r,r,m,r")
2398 (match_operator:CC 4 "predicate_operator"
2399 [(match_operand:CC 1 "register_operand" "c,c,c,c,c,c,c")
2401 (match_operand:DI 2 "reg_or_22bit_operand" "0,0,0,rI,m,r,rI")
2402 (match_operand:DI 3 "reg_or_22bit_operand" "rI,m,r,0,0,0,rI")))]
2405 [(set_attr "type" "A,M,M,A,M,M,unknown")])
2408 [(set (match_operand:DI 0 "register_operand" "")
2410 (match_operator:CC 4 "predicate_operator"
2411 [(match_operand:CC 1 "register_operand" "")
2413 (match_operand:DI 2 "reg_or_22bit_operand" "")
2414 (match_operand:DI 3 "reg_or_22bit_operand" "")))]
2416 && (rtx_equal_p (operands[0], operands[2])
2417 || rtx_equal_p (operands[0], operands[3])))"
2420 (set (match_dup 0) (match_dup 2)))]
2423 if (rtx_equal_p (operands[0], operands[2]))
2425 operands[2] = operands[3];
2426 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
2427 CCmode, operands[1], const0_rtx);
2432 [(set (match_operand:DI 0 "register_operand" "")
2434 (match_operator:CC 4 "predicate_operator"
2435 [(match_operand:CC 1 "register_operand" "")
2437 (match_operand:DI 2 "reg_or_22bit_operand" "")
2438 (match_operand:DI 3 "reg_or_22bit_operand" "")))]
2442 (set (match_dup 0) (match_dup 2)))
2445 (set (match_dup 0) (match_dup 3)))]
2448 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
2449 CCmode, operands[1], const0_rtx);
2452 ;; Absolute value pattern.
2454 (define_insn "*absdi2_internal"
2455 [(set (match_operand:DI 0 "register_operand" "=r,r")
2457 (match_operator:CC 4 "predicate_operator"
2458 [(match_operand:CC 1 "register_operand" "c,c")
2460 (neg:DI (match_operand:DI 2 "reg_or_22bit_operand" "rI,rI"))
2461 (match_operand:DI 3 "reg_or_22bit_operand" "0,rI")))]
2464 [(set_attr "type" "A,unknown")])
2467 [(set (match_operand:DI 0 "register_operand" "")
2469 (match_operator:CC 4 "predicate_operator"
2470 [(match_operand:CC 1 "register_operand" "c,c")
2472 (neg:DI (match_operand:DI 2 "reg_or_22bit_operand" ""))
2473 (match_operand:DI 3 "reg_or_22bit_operand" "")))]
2474 "reload_completed && rtx_equal_p (operands[0], operands[3])"
2478 (neg:DI (match_dup 2))))]
2482 [(set (match_operand:DI 0 "register_operand" "")
2484 (match_operator:CC 4 "predicate_operator"
2485 [(match_operand:CC 1 "register_operand" "c,c")
2487 (neg:DI (match_operand:DI 2 "reg_or_22bit_operand" ""))
2488 (match_operand:DI 3 "reg_or_22bit_operand" "")))]
2492 (set (match_dup 0) (neg:DI (match_dup 2))))
2495 (set (match_dup 0) (match_dup 3)))]
2498 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
2499 CCmode, operands[1], const0_rtx);
2503 ;; SImode if_then_else patterns.
2506 (define_insn "*cmovsi_internal"
2507 [(set (match_operand:SI 0 "register_operand" "=r,r,m,r,r,m,r")
2509 (match_operator:CC 4 "predicate_operator"
2510 [(match_operand:CC 1 "register_operand" "c,c,c,c,c,c,c")
2512 (match_operand:SI 2 "reg_or_22bit_operand" "0,0,0,rI,m,r,rI")
2513 (match_operand:SI 3 "reg_or_22bit_operand" "rI,m,r,0,0,0,rI")))]
2516 [(set_attr "type" "A,M,M,A,M,M,unknown")])
2519 [(set (match_operand:SI 0 "register_operand" "")
2521 (match_operator:CC 4 "predicate_operator"
2522 [(match_operand:CC 1 "register_operand" "")
2524 (match_operand:SI 2 "reg_or_22bit_operand" "")
2525 (match_operand:SI 3 "reg_or_22bit_operand" "")))]
2527 && (rtx_equal_p (operands[0], operands[2])
2528 || rtx_equal_p (operands[0], operands[3])))"
2531 (set (match_dup 0) (match_dup 2)))]
2534 if (rtx_equal_p (operands[0], operands[2]))
2536 operands[2] = operands[3];
2537 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
2538 CCmode, operands[1], const0_rtx);
2543 [(set (match_operand:SI 0 "register_operand" "")
2545 (match_operator:CC 4 "predicate_operator"
2546 [(match_operand:CC 1 "register_operand" "")
2548 (match_operand:SI 2 "reg_or_22bit_operand" "")
2549 (match_operand:SI 3 "reg_or_22bit_operand" "")))]
2553 (set (match_dup 0) (match_dup 2)))
2556 (set (match_dup 0) (match_dup 3)))]
2559 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
2560 CCmode, operands[1], const0_rtx);
2563 (define_insn "*abssi2_internal"
2564 [(set (match_operand:SI 0 "register_operand" "=r,r")
2566 (match_operator:CC 4 "predicate_operator"
2567 [(match_operand:CC 1 "register_operand" "c,c")
2569 (neg:SI (match_operand:SI 3 "reg_or_22bit_operand" "rI,rI"))
2570 (match_operand:SI 2 "reg_or_22bit_operand" "0,rI")))]
2573 [(set_attr "type" "A,unknown")])
2576 [(set (match_operand:SI 0 "register_operand" "")
2578 (match_operator:CC 4 "predicate_operator"
2579 [(match_operand:CC 1 "register_operand" "c,c")
2581 (neg:SI (match_operand:SI 2 "reg_or_22bit_operand" ""))
2582 (match_operand:SI 3 "reg_or_22bit_operand" "")))]
2583 "reload_completed && rtx_equal_p (operands[0], operands[3])"
2587 (neg:SI (match_dup 2))))]
2591 [(set (match_operand:SI 0 "register_operand" "")
2593 (match_operator:CC 4 "predicate_operator"
2594 [(match_operand:CC 1 "register_operand" "c,c")
2596 (neg:SI (match_operand:SI 2 "reg_or_22bit_operand" ""))
2597 (match_operand:SI 3 "reg_or_22bit_operand" "")))]
2601 (set (match_dup 0) (neg:SI (match_dup 2))))
2604 (set (match_dup 0) (match_dup 3)))]
2607 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
2608 CCmode, operands[1], const0_rtx);
2612 ;; ::::::::::::::::::::
2614 ;; :: Call and branch instructions
2616 ;; ::::::::::::::::::::
2618 ;; Subroutine call instruction returning no value. Operand 0 is the function
2619 ;; to call; operand 1 is the number of bytes of arguments pushed (in mode
2620 ;; `SImode', except it is normally a `const_int'); operand 2 is the number of
2621 ;; registers used as operands.
2623 ;; On most machines, operand 2 is not actually stored into the RTL pattern. It
2624 ;; is supplied for the sake of some RISC machines which need to put this
2625 ;; information into the assembler code; they can put it in the RTL instead of
2628 (define_expand "call"
2629 [(use (match_operand:DI 0 "" ""))
2630 (use (match_operand 1 "" ""))
2631 (use (match_operand 2 "" ""))
2632 (use (match_operand 3 "" ""))]
2636 /* ??? Stripping off the MEM isn't correct. Will lose alias info. */
2637 rtx addr = XEXP (operands[0], 0);
2638 enum machine_mode mode = GET_MODE (addr);
2640 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
2641 emit_call_insn (gen_call_internal (addr, operands[1],
2642 gen_rtx_REG (DImode, R_BR (0))));
2644 /* If this is an indirect call, then we have the address of a descriptor. */
2645 else if (! symbolic_operand (addr, mode))
2646 emit_insn (gen_indirect_call_pic (addr, operands[1]));
2647 else if (TARGET_CONST_GP)
2648 emit_call_insn (gen_call_internal (addr, operands[1],
2649 gen_rtx_REG (DImode, R_BR (0))));
2650 /* ??? This is an unsatisfying solution. Should rethink. */
2651 else if (setjmp_operand (addr, mode))
2652 emit_insn (gen_setjmp_call_pic (addr, operands[1]));
2654 emit_insn (gen_call_pic (addr, operands[1]));
2659 (define_expand "indirect_call_pic"
2660 [(set (match_dup 2) (reg:DI 1))
2661 (set (match_dup 3) (mem:DI (match_operand 0 "" "")))
2662 (set (match_dup 4) (plus:DI (match_dup 0) (const_int 8)))
2663 (set (reg:DI 1) (mem:DI (match_dup 4)))
2664 (parallel [(call (mem:DI (match_dup 3)) (match_operand 1 "" ""))
2666 (clobber (reg:DI 320))])
2667 (set (reg:DI 1) (match_dup 2))]
2671 operands[2] = gen_reg_rtx (DImode);
2672 operands[3] = gen_reg_rtx (DImode);
2673 operands[4] = gen_reg_rtx (DImode);
2676 ;; We can't save GP in a pseudo if we are calling setjmp, because pseudos
2677 ;; won't be restored by longjmp. For now, we save it in r4.
2679 ;; ??? It would be more efficient to save this directly into a stack slot.
2680 ;; Unfortunately, the stack slot address gets cse'd across the setjmp call
2681 ;; because the NOTE_INSN_SETJMP note is in the wrong place.
2683 ;; ??? This is an unsatisfying solution. Should rethink.
2685 (define_expand "setjmp_call_pic"
2686 [(set (match_dup 2) (reg:DI 1))
2687 (parallel [(call (mem:DI (match_operand 0 "" "")) (match_operand 1 "" ""))
2689 (clobber (reg:DI 320))])
2690 (set (reg:DI 1) (match_dup 2))]
2694 operands[2] = gen_rtx_REG (DImode, GR_REG (4));
2697 ;; ??? Saving/restoring the GP register is not needed if we are calling
2698 ;; a function in the same module.
2700 (define_expand "call_pic"
2701 [(set (match_dup 2) (reg:DI 1))
2702 (parallel [(call (mem:DI (match_operand 0 "" "")) (match_operand 1 "" ""))
2704 (clobber (reg:DI 320))])
2705 (set (reg:DI 1) (match_dup 2))]
2709 operands[2] = gen_reg_rtx (DImode);
2712 (define_insn "call_internal"
2713 [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
2714 (match_operand 1 "" ""))
2715 (clobber (match_operand:DI 2 "register_operand" "=b"))]
2717 "br.call%+.many %2 = %0"
2718 [(set_attr "type" "B")])
2720 (define_insn "*call_internal1"
2721 [(call (mem:DI (match_operand:DI 0 "call_operand" "bi"))
2722 (match_operand 1 "" ""))
2724 (clobber (match_operand:DI 2 "register_operand" "=b"))]
2726 "br.call%+.many %2 = %0"
2727 [(set_attr "type" "B")])
2729 ;; Subroutine call instruction returning a value. Operand 0 is the hard
2730 ;; register in which the value is returned. There are three more operands, the
2731 ;; same as the three operands of the `call' instruction (but with numbers
2732 ;; increased by one).
2734 ;; Subroutines that return `BLKmode' objects use the `call' insn.
2736 (define_expand "call_value"
2737 [(use (match_operand 0 "" ""))
2738 (use (match_operand:DI 1 "" ""))
2739 (use (match_operand 2 "" ""))
2740 (use (match_operand 3 "" ""))
2741 (use (match_operand 4 "" ""))]
2745 /* ??? Stripping off the MEM isn't correct. Will lose alias info. */
2746 rtx addr = XEXP (operands[1], 0);
2747 enum machine_mode mode = GET_MODE (addr);
2749 if (TARGET_NO_PIC || TARGET_AUTO_PIC)
2750 emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
2751 gen_rtx_REG (DImode, R_BR (0))));
2753 /* If this is an indirect call, then we have the address of a descriptor. */
2754 else if (! symbolic_operand (addr, mode))
2756 /* This is for HFA returns. */
2757 if (GET_CODE (operands[0]) == PARALLEL)
2758 emit_insn (gen_indirect_call_multiple_values_pic (operands[0], addr,
2761 emit_insn (gen_indirect_call_value_pic (operands[0], addr,
2764 else if (TARGET_CONST_GP)
2765 emit_call_insn (gen_call_value_internal (operands[0], addr, operands[2],
2766 gen_rtx_REG (DImode, R_BR (0))));
2767 /* ??? This is an unsatisfying solution. Should rethink. */
2768 else if (setjmp_operand (addr, mode))
2769 emit_insn (gen_setjmp_call_value_pic (operands[0], addr, operands[2]));
2770 /* This is for HFA returns. */
2771 else if (GET_CODE (operands[0]) == PARALLEL)
2772 emit_insn (gen_call_multiple_values_pic (operands[0], addr, operands[2]));
2774 emit_insn (gen_call_value_pic (operands[0], addr, operands[2]));
2779 (define_expand "indirect_call_value_pic"
2780 [(set (match_dup 3) (reg:DI 1))
2781 (set (match_dup 4) (mem:DI (match_operand 1 "" "")))
2782 (set (match_dup 5) (plus:DI (match_dup 1) (const_int 8)))
2783 (set (reg:DI 1) (mem:DI (match_dup 5)))
2784 (parallel [(set (match_operand 0 "" "")
2785 (call (mem:DI (match_dup 4)) (match_operand 2 "" "")))
2787 (clobber (reg:DI 320))])
2788 (set (reg:DI 1) (match_dup 3))]
2792 operands[3] = gen_reg_rtx (DImode);
2793 operands[4] = gen_reg_rtx (DImode);
2794 operands[5] = gen_reg_rtx (DImode);
2797 (define_expand "indirect_call_multiple_values_pic"
2798 [(set (match_dup 3) (reg:DI 1))
2799 (set (match_dup 4) (mem:DI (match_operand 1 "" "")))
2800 (set (match_dup 5) (plus:DI (match_dup 1) (const_int 8)))
2801 (set (reg:DI 1) (mem:DI (match_dup 5)))
2802 (match_par_dup 6 [(set (match_operand 0 "" "")
2803 (call (mem:DI (match_dup 4))
2804 (match_operand 2 "" "")))
2806 (clobber (reg:DI 320))])
2807 (set (reg:DI 1) (match_dup 3))]
2815 operands[3] = gen_reg_rtx (DImode);
2816 operands[4] = gen_reg_rtx (DImode);
2817 operands[5] = gen_reg_rtx (DImode);
2819 /* This code is the same as the code in call_multiple_values_pic, except
2820 that op3 was replaced with op6 and op1 was replaced with op4. */
2821 call = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (DImode, operands[4]),
2824 count = XVECLEN (operands[0], 0);
2825 operands[6] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 2));
2827 XVECEXP (operands[6], 0, 0)
2828 = gen_rtx_SET (VOIDmode, XEXP (XVECEXP (operands[0], 0, 0), 0), call);
2830 XVECEXP (operands[6], 0, 1)
2831 = gen_rtx_USE (DImode, gen_rtx_REG (DImode, GR_REG (1)));
2832 XVECEXP (operands[6], 0, 2)
2833 = gen_rtx_CLOBBER (DImode, gen_rtx_REG (DImode, BR_REG (0)));
2835 for (i = 1; i < count; i++)
2836 XVECEXP (operands[6], 0, i + 2)
2837 = gen_rtx_SET (VOIDmode, XEXP (XVECEXP (operands[0], 0, i), 0), call);
2841 ;; We can't save GP in a pseudo if we are calling setjmp, because pseudos
2842 ;; won't be restored by longjmp. For now, we save it in r4.
2844 ;; ??? It would be more efficient to save this directly into a stack slot.
2845 ;; Unfortunately, the stack slot address gets cse'd across the setjmp call
2846 ;; because the NOTE_INSN_SETJMP note is in the wrong place.
2848 ;; ??? This is an unsatisfying solution. Should rethink.
2850 (define_expand "setjmp_call_value_pic"
2851 [(set (match_dup 3) (reg:DI 1))
2852 (parallel [(set (match_operand 0 "" "")
2853 (call (mem:DI (match_operand 1 "" ""))
2854 (match_operand 2 "" "")))
2856 (clobber (reg:DI 320))])
2857 (set (reg:DI 1) (match_dup 3))]
2861 operands[3] = gen_rtx_REG (DImode, GR_REG (4));
2864 ;; ??? Saving/restoring the GP register is not needed if we are calling
2865 ;; a function in the same module.
2867 (define_expand "call_value_pic"
2868 [(set (match_dup 3) (reg:DI 1))
2869 (parallel [(set (match_operand 0 "" "")
2870 (call (mem:DI (match_operand 1 "" ""))
2871 (match_operand 2 "" "")))
2873 (clobber (reg:DI 320))])
2874 (set (reg:DI 1) (match_dup 3))]
2878 operands[3] = gen_reg_rtx (DImode);
2881 ;; ??? Saving/restoring the GP register is not needed if we are calling
2882 ;; a function in the same module.
2884 (define_expand "call_multiple_values_pic"
2885 [(set (match_dup 4) (reg:DI 1))
2886 (match_par_dup 3 [(set (match_operand 0 "" "")
2887 (call (mem:DI (match_operand 1 "" ""))
2888 (match_operand 2 "" "")))
2890 (clobber (reg:DI 320))])
2891 (set (reg:DI 1) (match_dup 4))]
2899 operands[4] = gen_reg_rtx (DImode);
2901 call = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (DImode, operands[1]),
2904 count = XVECLEN (operands[0], 0);
2905 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 2));
2907 XVECEXP (operands[3], 0, 0)
2908 = gen_rtx_SET (VOIDmode, XEXP (XVECEXP (operands[0], 0, 0), 0), call);
2910 XVECEXP (operands[3], 0, 1)
2911 = gen_rtx_USE (DImode, gen_rtx_REG (DImode, GR_REG (1)));
2912 XVECEXP (operands[3], 0, 2)
2913 = gen_rtx_CLOBBER (DImode, gen_rtx_REG (DImode, BR_REG (0)));
2915 for (i = 1; i < count; i++)
2916 XVECEXP (operands[3], 0, i + 2)
2917 = gen_rtx_SET (VOIDmode, XEXP (XVECEXP (operands[0], 0, i), 0), call);
2920 (define_insn "call_value_internal"
2921 [(set (match_operand 0 "register_operand" "=rf")
2922 (call (mem:DI (match_operand:DI 1 "call_operand" "bi"))
2923 (match_operand 2 "" "")))
2924 (clobber (match_operand:DI 3 "register_operand" "=b"))]
2926 "br.call%+.many %3 = %1"
2927 [(set_attr "type" "B")])
2929 (define_insn "*call_value_internal1"
2930 [(set (match_operand 0 "register_operand" "=rf")
2931 (call (mem:DI (match_operand:DI 1 "call_operand" "bi"))
2932 (match_operand 2 "" "")))
2934 (clobber (match_operand:DI 3 "register_operand" "=b"))]
2936 "br.call%+.many %3 = %1"
2937 [(set_attr "type" "B")])
2939 (define_insn "*call_multiple_values_internal1"
2940 [(match_parallel 0 "call_multiple_values_operation"
2941 [(set (match_operand 1 "register_operand" "=rf")
2942 (call (mem:DI (match_operand:DI 2 "call_operand" "bi"))
2943 (match_operand 3 "" "")))
2945 (clobber (match_operand:DI 4 "register_operand" "=b"))])]
2947 "br.call%+.many %4 = %2"
2948 [(set_attr "type" "B")])
2950 ;; Call subroutine returning any type.
2952 (define_expand "untyped_call"
2953 [(parallel [(call (match_operand 0 "" "")
2955 (match_operand 1 "" "")
2956 (match_operand 2 "" "")])]
2962 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2964 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2966 rtx set = XVECEXP (operands[2], 0, i);
2967 emit_move_insn (SET_DEST (set), SET_SRC (set));
2970 /* The optimizer does not know that the call sets the function value
2971 registers we stored in the result block. We avoid problems by
2972 claiming that all hard registers are used and clobbered at this
2974 emit_insn (gen_blockage ());
2979 (define_insn "return_internal"
2981 (use (match_operand:DI 0 "register_operand" "b"))]
2983 "br.ret.sptk.many %0"
2984 [(set_attr "type" "B")])
2986 (define_insn "return"
2988 "ia64_direct_return ()"
2989 "br.ret.sptk.many rp"
2990 [(set_attr "type" "B")])
2992 (define_insn "*return_true"
2994 (if_then_else (match_operator 0 "predicate_operator"
2995 [(match_operand:CC 1 "register_operand" "c")
2999 "ia64_direct_return ()"
3000 "(%J0) br.ret%+.many rp"
3001 [(set_attr "type" "B")
3002 (set_attr "predicable" "no")])
3004 (define_insn "*return_false"
3006 (if_then_else (match_operator 0 "predicate_operator"
3007 [(match_operand:CC 1 "register_operand" "c")
3011 "ia64_direct_return ()"
3012 "(%j0) br.ret%+.many rp"
3013 [(set_attr "type" "B")
3014 (set_attr "predicable" "no")])
3017 [(set (pc) (label_ref (match_operand 0 "" "")))]
3020 [(set_attr "type" "B")])
3022 (define_insn "indirect_jump"
3023 [(set (pc) (match_operand:DI 0 "register_operand" "b"))]
3026 [(set_attr "type" "B")])
3028 (define_expand "tablejump"
3029 [(match_operand:DI 0 "register_operand" "")
3030 (match_operand 1 "" "")]
3034 rtx tmp1 = gen_reg_rtx (DImode);
3035 rtx tmp2 = gen_reg_rtx (DImode);
3037 emit_move_insn (tmp1, gen_rtx_LABEL_REF (Pmode, operands[1]));
3038 emit_insn (gen_adddi3 (tmp2, operands[0], tmp1));
3039 emit_jump_insn (gen_tablejump_internal (tmp2, operands[1]));
3043 (define_insn "tablejump_internal"
3044 [(set (pc) (match_operand:DI 0 "register_operand" "b"))
3045 (use (label_ref (match_operand 1 "" "")))]
3048 [(set_attr "type" "B")])
3051 ;; ::::::::::::::::::::
3053 ;; :: Prologue and Epilogue instructions
3055 ;; ::::::::::::::::::::
3057 (define_expand "prologue"
3062 ia64_expand_prologue ();
3066 (define_expand "epilogue"
3071 ia64_expand_epilogue ();
3075 ;; This prevents the scheduler from moving the SP decrement past FP-relative
3076 ;; stack accesses. This is the same as adddi3 plus the extra set.
3078 (define_insn "prologue_allocate_stack"
3079 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
3080 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,a")
3081 (match_operand:DI 2 "reg_or_22bit_operand" "r,I,J")))
3082 (set (match_operand:DI 3 "register_operand" "=r,r,r")
3089 [(set_attr "type" "A")])
3091 ;; This prevents the scheduler from moving the SP restore past FP-relative
3092 ;; stack accesses. This is similar to movdi plus the extra set.
3094 (define_insn "epilogue_deallocate_stack"
3095 [(set (match_operand:DI 0 "register_operand" "=r")
3096 (match_operand:DI 1 "register_operand" "+r"))
3097 (set (match_dup 1) (match_dup 1))]
3100 [(set_attr "type" "A")])
3102 ;; Allocate a new register frame.
3104 (define_insn "alloc"
3105 [(set (match_operand:DI 0 "register_operand" "=r")
3106 (unspec_volatile:DI [(const_int 0)] 0))
3107 (use (match_operand:DI 1 "const_int_operand" "i"))
3108 (use (match_operand:DI 2 "const_int_operand" "i"))
3109 (use (match_operand:DI 3 "const_int_operand" "i"))
3110 (use (match_operand:DI 4 "const_int_operand" "i"))]
3112 "alloc %0 = ar.pfs, %1, %2, %3, %4"
3113 [(set_attr "type" "M")
3114 (set_attr "predicable" "no")])
3116 (define_insn "gr_spill"
3117 [(set (match_operand:DI 0 "memory_operand" "=m")
3118 (unspec:DI [(match_operand:DI 1 "register_operand" "r")] 1))]
3120 "st8.spill %0 = %1%P0"
3121 [(set_attr "type" "M")])
3123 (define_insn "gr_restore"
3124 [(set (match_operand:DI 0 "register_operand" "=r")
3125 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] 2))]
3127 "ld8.fill %0 = %1%P1"
3128 [(set_attr "type" "M")])
3130 (define_insn "fr_spill"
3131 [(set (match_operand:XF 0 "memory_operand" "=m")
3132 (unspec:XF [(match_operand:XF 1 "register_operand" "f")] 3))]
3134 "stf.spill %0 = %1%P0"
3135 [(set_attr "type" "M")])
3137 (define_insn "fr_restore"
3138 [(set (match_operand:XF 0 "register_operand" "=f")
3139 (unspec:XF [(match_operand:XF 1 "memory_operand" "m")] 4))]
3141 "ldf.fill %0 = %1%P1"
3142 [(set_attr "type" "M")])
3144 (define_insn "pr_spill"
3145 [(set (match_operand:DI 0 "register_operand" "=r")
3146 (unspec:DI [(const_int 0)] 5))]
3149 [(set_attr "type" "I")])
3151 ;; ??? This is volatile to prevent it from being moved before a conditional
3152 ;; expression that calculates the return value.
3154 (define_insn "pr_restore"
3155 [(unspec_volatile [(const_int 0)] 6)
3156 (use (match_operand:DI 0 "register_operand" "r"))]
3159 [(set_attr "type" "I")])
3161 ;; ??? This is volatile to prevent it from being moved before a call.
3162 ;; Should instead add a ar.pfs hard register which is call clobbered.
3164 (define_insn "pfs_restore"
3165 [(unspec_volatile [(const_int 0)] 4)
3166 (use (match_operand:DI 0 "register_operand" "r"))]
3169 [(set_attr "type" "I")])
3171 (define_insn "unat_spill"
3172 [(set (match_operand:DI 0 "register_operand" "=r")
3173 (unspec:DI [(const_int 0)] 9))]
3176 [(set_attr "type" "M")])
3178 (define_insn "unat_restore"
3179 [(unspec [(const_int 0)] 10)
3180 (use (match_operand:DI 0 "register_operand" "r"))]
3183 [(set_attr "type" "M")])
3185 (define_insn "bsp_value"
3186 [(set (match_operand:DI 0 "register_operand" "=r")
3187 (unspec:DI [(const_int 0)] 20))]
3190 [(set_attr "type" "I")])
3192 (define_insn "set_bsp"
3193 [(unspec_volatile [(const_int 0)] 5)
3194 (use (match_operand:DI 0 "register_operand" "r"))]
3196 "flushrs\;mov r19=ar.rsc\;;;\;and r19=0x1c,r19\;;;\;mov ar.rsc=r19\;;;\;mov ar.bspstore=%0\;;;\;or r19=0x3,r19\;;;\;loadrs\;invala\;;;\;mov ar.rsc=r19"
3197 [(set_attr "type" "unknown")
3198 (set_attr "predicable" "no")])
3200 (define_insn "flushrs"
3201 [(unspec [(const_int 0)] 21)]
3204 [(set_attr "type" "M")])
3206 ;; ::::::::::::::::::::
3208 ;; :: Miscellaneous instructions
3210 ;; ::::::::::::::::::::
3212 ;; ??? Emiting a NOP instruction isn't very useful. This should probably
3213 ;; be emitting ";;" to force a break in the instruction packing.
3215 ;; No operation, needed in case the user uses -g but not -O.
3220 [(set_attr "type" "unknown")])
3222 ;; Pseudo instruction that prevents the scheduler from moving code above this
3224 (define_insn "blockage"
3225 [(unspec_volatile [(const_int 0)] 1)]
3228 [(set_attr "type" "unknown")
3229 (set_attr "predicable" "no")])
3231 (define_insn "insn_group_barrier"
3232 [(unspec_volatile [(const_int 0)] 2)]
3235 [(set_attr "type" "S")
3236 (set_attr "predicable" "no")])
3239 ;; Non-local goto support.
3241 (define_expand "save_stack_nonlocal"
3242 [(use (match_operand:OI 0 "memory_operand" ""))
3243 (use (match_operand:DI 1 "register_operand" ""))]
3247 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
3248 \"__ia64_save_stack_nonlocal\"),
3249 0, VOIDmode, 2, XEXP (operands[0], 0), Pmode,
3250 operands[1], Pmode);
3254 (define_expand "nonlocal_goto"
3255 [(use (match_operand 0 "general_operand" ""))
3256 (use (match_operand 1 "general_operand" ""))
3257 (use (match_operand 2 "general_operand" ""))
3258 (use (match_operand 3 "general_operand" ""))]
3262 if (GET_CODE (operands[0]) != REG)
3263 operands[0] = force_reg (Pmode, operands[0]);
3264 emit_move_insn (virtual_stack_vars_rtx, operands[0]);
3265 emit_insn (gen_rtx_USE (VOIDmode, frame_pointer_rtx));
3266 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
3267 emit_insn (gen_rtx_USE (VOIDmode, static_chain_rtx));
3268 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, \"__ia64_nonlocal_goto\"),
3270 operands[0], Pmode, operands[1], Pmode,
3271 copy_to_reg (XEXP (operands[2], 0)), Pmode,
3272 operands[3], Pmode);
3277 ;; ??? We need this because the function __ia64_nonlocal_goto can't easily
3278 ;; access the FP which is currently stored in a local register. Maybe move
3279 ;; the FP to a global register to avoid this problem?
3281 (define_expand "nonlocal_goto_receiver"
3282 [(use (const_int 0))]
3286 emit_move_insn (frame_pointer_rtx, gen_rtx_REG (DImode, GR_REG (7)));
3290 (define_expand "eh_epilogue"
3291 [(use (match_operand:DI 0 "register_operand" "r"))
3292 (use (match_operand:DI 1 "register_operand" "r"))
3293 (use (match_operand:DI 2 "register_operand" "r"))]
3297 rtx bsp = gen_rtx_REG (Pmode, 10);
3298 rtx sp = gen_rtx_REG (Pmode, 9);
3300 if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
3302 emit_move_insn (bsp, operands[0]);
3305 if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
3307 emit_move_insn (sp, operands[2]);
3310 emit_insn (gen_rtx_USE (VOIDmode, sp));
3311 emit_insn (gen_rtx_USE (VOIDmode, bsp));
3313 cfun->machine->ia64_eh_epilogue_sp = sp;
3314 cfun->machine->ia64_eh_epilogue_bsp = bsp;
3318 ;; This flushes at least 64 bytes starting from the address pointed
3319 ;; to by operand[0].
3321 ;; ??? This should be a define expand.
3323 (define_insn "flush_cache"
3324 [(unspec_volatile [(match_operand:DI 0 "register_operand" "=&r")] 3)]
3326 "fc %0\;;;\;adds %0=31,%0\;;;\;fc %0\;;;\;sync.i\;srlz.i"
3327 [(set_attr "type" "unknown")
3328 (set_attr "predicable" "no")])
3330 ;; Builtin apply support.
3332 (define_expand "restore_stack_nonlocal"
3333 [(use (match_operand:DI 0 "register_operand" ""))
3334 (use (match_operand:OI 1 "memory_operand" ""))]
3338 emit_library_call (gen_rtx_SYMBOL_REF (Pmode,
3339 \"__ia64_restore_stack_nonlocal\"),
3341 copy_to_reg (XEXP (operands[1], 0)), Pmode);
3346 ;;; Intrinsics support.
3348 (define_insn "ccv_restore_si"
3349 [(unspec [(const_int 0)] 11)
3350 (use (match_operand:SI 0 "register_operand" "r"))]
3353 [(set_attr "type" "M")])
3355 (define_insn "ccv_restore_di"
3356 [(unspec [(const_int 0)] 11)
3357 (use (match_operand:DI 0 "register_operand" "r"))]
3360 [(set_attr "type" "M")])
3363 [(unspec [(match_operand:BLK 0 "memory_operand" "m")] 12)]
3366 [(set_attr "type" "M")])
3368 (define_insn "fetchadd_acq_si"
3369 [(set (match_operand:SI 0 "register_operand" "=r")
3370 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3371 (match_operand:SI 2 "fetchadd_operand" "n")] 19))]
3373 "fetchadd4.acq %0 = %1, %2"
3374 [(set_attr "type" "M")])
3376 (define_insn "fetchadd_acq_di"
3377 [(set (match_operand:DI 0 "register_operand" "=r")
3378 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3379 (match_operand:DI 2 "fetchadd_operand" "n")] 19))]
3381 "fetchadd8.acq %0 = %1, %2"
3382 [(set_attr "type" "M")])
3384 (define_insn "cmpxchg_acq_si"
3385 [(set (match_operand:SI 0 "register_operand" "=r")
3386 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3387 (match_operand:SI 2 "register_operand" "r")] 13))]
3389 "cmpxchg4.acq %0 = %1, %2, ar.ccv"
3390 [(set_attr "type" "M")])
3392 (define_insn "cmpxchg_acq_di"
3393 [(set (match_operand:DI 0 "register_operand" "=r")
3394 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3395 (match_operand:DI 2 "register_operand" "r")] 13))]
3397 "cmpxchg8.acq %0 = %1, %2, ar.ccv"
3398 [(set_attr "type" "M")])
3400 (define_expand "val_compare_and_swap_si"
3401 [(set (match_operand:SI 0 "register_operand" "=r")
3402 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3403 (match_operand:SI 2 "register_operand" "r")
3404 (match_operand:SI 3 "register_operand" "r")] 14))]
3408 rtx tmp_reg = gen_rtx_REG (DImode, GR_REG(0));
3409 rtx target = gen_rtx_MEM (BLKmode, tmp_reg);
3410 RTX_UNCHANGING_P (target) = 1;
3411 emit_insn (gen_ccv_restore_si (operands[2]));
3412 emit_insn (gen_mf (target));
3413 emit_insn (gen_cmpxchg_acq_si (operands[0], operands[1], operands[3]));
3417 (define_expand "val_compare_and_swap_di"
3418 [(set (match_operand:DI 0 "register_operand" "=r")
3419 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3420 (match_operand:DI 2 "register_operand" "r")
3421 (match_operand:DI 3 "register_operand" "r")] 14))]
3425 rtx tmp_reg = gen_rtx_REG (DImode, GR_REG(0));
3426 rtx target = gen_rtx_MEM (BLKmode, tmp_reg);
3427 RTX_UNCHANGING_P (target) = 1;
3428 emit_insn (gen_ccv_restore_di (operands[2]));
3429 emit_insn (gen_mf (target));
3430 emit_insn (gen_cmpxchg_acq_di (operands[0], operands[1], operands[3]));
3434 (define_insn "xchgsi"
3435 [(set (match_operand:SI 0 "register_operand" "=r")
3436 (match_operand:SI 1 "memory_operand" "+m"))
3438 (match_operand:SI 2 "register_operand" "r"))]
3441 [(set_attr "type" "M")])
3443 (define_insn "xchgdi"
3444 [(set (match_operand:DI 0 "register_operand" "=r")
3445 (match_operand:DI 1 "memory_operand" "+m"))
3447 (match_operand:DI 2 "register_operand" "r"))]
3450 [(set_attr "type" "M")])
3452 (define_expand "lock_test_and_set_si"
3453 [(set (match_operand:SI 0 "register_operand" "r")
3454 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3455 (match_operand:SI 2 "register_operand" "r")] 16))]
3459 emit_insn (gen_xchgsi (operands[0], operands[1], operands[2]));
3463 (define_expand "lock_test_and_set_di"
3464 [(set (match_operand:DI 0 "register_operand" "r")
3465 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3466 (match_operand:DI 2 "register_operand" "r")] 16))]
3470 emit_insn (gen_xchgdi (operands[0], operands[1], operands[2]));
3474 (define_expand "fetch_and_add_si"
3475 [(set (match_operand:SI 0 "register_operand" "r")
3476 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3477 (match_operand:SI 2 "nonmemory_operand" "")] 18))]
3483 if (GET_CODE (operands[2]) == CONST_INT)
3485 x = INTVAL(operands[2]);
3486 if (x == -16 || x == -8 || x == -4 || x == -1 ||
3487 x == 16 || x == 8 || x == 4 || x == 1)
3489 emit_insn (gen_fetchadd_acq_si (operands[0], operands[1], operands[2]));
3494 ia64_expand_fetch_and_op (IA64_ADD_OP, SImode, operands);
3498 (define_expand "fetch_and_sub_si"
3499 [(set (match_operand:SI 0 "register_operand" "r")
3500 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3501 (match_operand:SI 2 "register_operand" "r")] 18))]
3505 ia64_expand_fetch_and_op (IA64_SUB_OP, SImode, operands);
3509 (define_expand "fetch_and_or_si"
3510 [(set (match_operand:SI 0 "register_operand" "r")
3511 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3512 (match_operand:SI 2 "register_operand" "r")] 18))]
3516 ia64_expand_fetch_and_op (IA64_OR_OP, SImode, operands);
3520 (define_expand "fetch_and_and_si"
3521 [(set (match_operand:SI 0 "register_operand" "r")
3522 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3523 (match_operand:SI 2 "register_operand" "r")] 18))]
3527 ia64_expand_fetch_and_op (IA64_AND_OP, SImode, operands);
3531 (define_expand "fetch_and_xor_si"
3532 [(set (match_operand:SI 0 "register_operand" "r")
3533 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3534 (match_operand:SI 2 "register_operand" "r")] 18))]
3538 ia64_expand_fetch_and_op (IA64_XOR_OP, SImode, operands);
3542 (define_expand "fetch_and_nand_si"
3543 [(set (match_operand:SI 0 "register_operand" "r")
3544 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3545 (match_operand:SI 2 "register_operand" "r")] 18))]
3549 ia64_expand_fetch_and_op (IA64_NAND_OP, SImode, operands);
3553 (define_expand "fetch_and_add_di"
3554 [(set (match_operand:DI 0 "register_operand" "r")
3555 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3556 (match_operand:DI 2 "nonmemory_operand" "")] 18))]
3562 if (GET_CODE (operands[2]) == CONST_INT)
3564 x = INTVAL(operands[2]);
3565 if (x == -16 || x == -8 || x == -4 || x == -1 ||
3566 x == 16 || x == 8 || x == 4 || x == 1)
3568 emit_insn (gen_fetchadd_acq_di (operands[0], operands[1], operands[2]));
3573 ia64_expand_fetch_and_op (IA64_ADD_OP, DImode, operands);
3577 (define_expand "fetch_and_sub_di"
3578 [(set (match_operand:DI 0 "register_operand" "r")
3579 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3580 (match_operand:DI 2 "register_operand" "r")] 18))]
3584 ia64_expand_fetch_and_op (IA64_SUB_OP, DImode, operands);
3588 (define_expand "fetch_and_or_di"
3589 [(set (match_operand:DI 0 "register_operand" "r")
3590 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3591 (match_operand:DI 2 "register_operand" "r")] 18))]
3595 ia64_expand_fetch_and_op (IA64_OR_OP, DImode, operands);
3599 (define_expand "fetch_and_and_di"
3600 [(set (match_operand:DI 0 "register_operand" "r")
3601 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3602 (match_operand:DI 2 "register_operand" "r")] 18))]
3606 ia64_expand_fetch_and_op (IA64_AND_OP, DImode, operands);
3610 (define_expand "fetch_and_xor_di"
3611 [(set (match_operand:DI 0 "register_operand" "r")
3612 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3613 (match_operand:DI 2 "register_operand" "r")] 18))]
3617 ia64_expand_fetch_and_op (IA64_XOR_OP, DImode, operands);
3621 (define_expand "fetch_and_nand_di"
3622 [(set (match_operand:DI 0 "register_operand" "r")
3623 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3624 (match_operand:DI 2 "register_operand" "r")] 18))]
3628 ia64_expand_fetch_and_op (IA64_NAND_OP, DImode, operands);
3632 (define_expand "add_and_fetch_di"
3633 [(set (match_operand:DI 0 "register_operand" "r")
3634 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3635 (match_operand:DI 2 "register_operand" "r")] 17))]
3639 ia64_expand_op_and_fetch (IA64_ADD_OP, DImode, operands);
3643 (define_expand "sub_and_fetch_di"
3644 [(set (match_operand:DI 0 "register_operand" "r")
3645 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3646 (match_operand:DI 2 "register_operand" "r")] 17))]
3650 ia64_expand_op_and_fetch (IA64_SUB_OP, DImode, operands);
3654 (define_expand "or_and_fetch_di"
3655 [(set (match_operand:DI 0 "register_operand" "r")
3656 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3657 (match_operand:DI 2 "register_operand" "r")] 17))]
3661 ia64_expand_op_and_fetch (IA64_OR_OP, DImode, operands);
3665 (define_expand "and_and_fetch_di"
3666 [(set (match_operand:DI 0 "register_operand" "r")
3667 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3668 (match_operand:DI 2 "register_operand" "r")] 17))]
3672 ia64_expand_op_and_fetch (IA64_AND_OP, DImode, operands);
3676 (define_expand "xor_and_fetch_di"
3677 [(set (match_operand:DI 0 "register_operand" "r")
3678 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3679 (match_operand:DI 2 "register_operand" "r")] 17))]
3683 ia64_expand_op_and_fetch (IA64_XOR_OP, DImode, operands);
3687 (define_expand "nand_and_fetch_di"
3688 [(set (match_operand:DI 0 "register_operand" "r")
3689 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
3690 (match_operand:DI 2 "register_operand" "r")] 17))]
3694 ia64_expand_op_and_fetch (IA64_NAND_OP, DImode, operands);
3698 (define_expand "add_and_fetch_si"
3699 [(set (match_operand:SI 0 "register_operand" "r")
3700 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3701 (match_operand:SI 2 "register_operand" "r")] 17))]
3705 ia64_expand_op_and_fetch (IA64_ADD_OP, SImode, operands);
3709 (define_expand "sub_and_fetch_si"
3710 [(set (match_operand:SI 0 "register_operand" "r")
3711 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3712 (match_operand:SI 2 "register_operand" "r")] 17))]
3716 ia64_expand_op_and_fetch (IA64_SUB_OP, SImode, operands);
3720 (define_expand "or_and_fetch_si"
3721 [(set (match_operand:SI 0 "register_operand" "r")
3722 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3723 (match_operand:SI 2 "register_operand" "r")] 17))]
3727 ia64_expand_op_and_fetch (IA64_OR_OP, SImode, operands);
3731 (define_expand "and_and_fetch_si"
3732 [(set (match_operand:SI 0 "register_operand" "r")
3733 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3734 (match_operand:SI 2 "register_operand" "r")] 17))]
3738 ia64_expand_op_and_fetch (IA64_AND_OP, SImode, operands);
3742 (define_expand "xor_and_fetch_si"
3743 [(set (match_operand:SI 0 "register_operand" "r")
3744 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3745 (match_operand:SI 2 "register_operand" "r")] 17))]
3749 ia64_expand_op_and_fetch (IA64_XOR_OP, SImode, operands);
3753 (define_expand "nand_and_fetch_si"
3754 [(set (match_operand:SI 0 "register_operand" "r")
3755 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")
3756 (match_operand:SI 2 "register_operand" "r")] 17))]
3760 ia64_expand_op_and_fetch (IA64_NAND_OP, SImode, operands);
3767 [(match_operator 0 "predicate_operator"
3768 [(match_operand:CC 1 "register_operand" "c")