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1 /* Subroutines used for code generation on Vitesse IQ2000 processors
2 Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "tm.h"
25 #include "tree.h"
26 #include "rtl.h"
27 #include "regs.h"
28 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "output.h"
32 #include "insn-attr.h"
33 #include "flags.h"
34 #include "function.h"
35 #include "expr.h"
36 #include "optabs.h"
37 #include "libfuncs.h"
38 #include "recog.h"
39 #include "diagnostic-core.h"
40 #include "reload.h"
41 #include "ggc.h"
42 #include "tm_p.h"
43 #include "debug.h"
44 #include "target.h"
45 #include "target-def.h"
46 #include "langhooks.h"
47 #include "df.h"
48
49 /* Enumeration for all of the relational tests, so that we can build
50 arrays indexed by the test type, and not worry about the order
51 of EQ, NE, etc. */
52
53 enum internal_test
54 {
55 ITEST_EQ,
56 ITEST_NE,
57 ITEST_GT,
58 ITEST_GE,
59 ITEST_LT,
60 ITEST_LE,
61 ITEST_GTU,
62 ITEST_GEU,
63 ITEST_LTU,
64 ITEST_LEU,
65 ITEST_MAX
66 };
67
68 struct constant;
69
70 \f
71 /* Structure to be filled in by compute_frame_size with register
72 save masks, and offsets for the current function. */
73
74 struct iq2000_frame_info
75 {
76 long total_size; /* # bytes that the entire frame takes up. */
77 long var_size; /* # bytes that variables take up. */
78 long args_size; /* # bytes that outgoing arguments take up. */
79 long extra_size; /* # bytes of extra gunk. */
80 int gp_reg_size; /* # bytes needed to store gp regs. */
81 int fp_reg_size; /* # bytes needed to store fp regs. */
82 long mask; /* Mask of saved gp registers. */
83 long gp_save_offset; /* Offset from vfp to store gp registers. */
84 long fp_save_offset; /* Offset from vfp to store fp registers. */
85 long gp_sp_offset; /* Offset from new sp to store gp registers. */
86 long fp_sp_offset; /* Offset from new sp to store fp registers. */
87 int initialized; /* != 0 if frame size already calculated. */
88 int num_gp; /* Number of gp registers saved. */
89 } iq2000_frame_info;
90
91 struct GTY(()) machine_function
92 {
93 /* Current frame information, calculated by compute_frame_size. */
94 long total_size; /* # bytes that the entire frame takes up. */
95 long var_size; /* # bytes that variables take up. */
96 long args_size; /* # bytes that outgoing arguments take up. */
97 long extra_size; /* # bytes of extra gunk. */
98 int gp_reg_size; /* # bytes needed to store gp regs. */
99 int fp_reg_size; /* # bytes needed to store fp regs. */
100 long mask; /* Mask of saved gp registers. */
101 long gp_save_offset; /* Offset from vfp to store gp registers. */
102 long fp_save_offset; /* Offset from vfp to store fp registers. */
103 long gp_sp_offset; /* Offset from new sp to store gp registers. */
104 long fp_sp_offset; /* Offset from new sp to store fp registers. */
105 int initialized; /* != 0 if frame size already calculated. */
106 int num_gp; /* Number of gp registers saved. */
107 };
108
109 /* Global variables for machine-dependent things. */
110
111 /* List of all IQ2000 punctuation characters used by iq2000_print_operand. */
112 static char iq2000_print_operand_punct[256];
113
114 /* Which instruction set architecture to use. */
115 int iq2000_isa;
116
117 /* Local variables. */
118
119 /* The next branch instruction is a branch likely, not branch normal. */
120 static int iq2000_branch_likely;
121
122 /* Count of delay slots and how many are filled. */
123 static int dslots_load_total;
124 static int dslots_load_filled;
125 static int dslots_jump_total;
126
127 /* # of nops needed by previous insn. */
128 static int dslots_number_nops;
129
130 /* Number of 1/2/3 word references to data items (i.e., not jal's). */
131 static int num_refs[3];
132
133 /* Registers to check for load delay. */
134 static rtx iq2000_load_reg;
135 static rtx iq2000_load_reg2;
136 static rtx iq2000_load_reg3;
137 static rtx iq2000_load_reg4;
138
139 /* Mode used for saving/restoring general purpose registers. */
140 static enum machine_mode gpr_mode;
141
142 \f
143 /* Initialize the GCC target structure. */
144 static struct machine_function* iq2000_init_machine_status (void);
145 static void iq2000_option_override (void);
146 static section *iq2000_select_rtx_section (enum machine_mode, rtx,
147 unsigned HOST_WIDE_INT);
148 static void iq2000_init_builtins (void);
149 static rtx iq2000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
150 static bool iq2000_return_in_memory (const_tree, const_tree);
151 static void iq2000_setup_incoming_varargs (CUMULATIVE_ARGS *,
152 enum machine_mode, tree, int *,
153 int);
154 static bool iq2000_rtx_costs (rtx, int, int, int *, bool);
155 static int iq2000_address_cost (rtx, bool);
156 static section *iq2000_select_section (tree, int, unsigned HOST_WIDE_INT);
157 static rtx iq2000_legitimize_address (rtx, rtx, enum machine_mode);
158 static bool iq2000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
159 const_tree, bool);
160 static int iq2000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
161 tree, bool);
162 static rtx iq2000_function_arg (CUMULATIVE_ARGS *,
163 enum machine_mode, const_tree, bool);
164 static void iq2000_function_arg_advance (CUMULATIVE_ARGS *,
165 enum machine_mode, const_tree, bool);
166 static unsigned int iq2000_function_arg_boundary (enum machine_mode,
167 const_tree);
168 static void iq2000_va_start (tree, rtx);
169 static bool iq2000_legitimate_address_p (enum machine_mode, rtx, bool);
170 static bool iq2000_can_eliminate (const int, const int);
171 static void iq2000_asm_trampoline_template (FILE *);
172 static void iq2000_trampoline_init (rtx, tree, rtx);
173 static rtx iq2000_function_value (const_tree, const_tree, bool);
174 static rtx iq2000_libcall_value (enum machine_mode, const_rtx);
175 static void iq2000_print_operand (FILE *, rtx, int);
176 static void iq2000_print_operand_address (FILE *, rtx);
177 static bool iq2000_print_operand_punct_valid_p (unsigned char code);
178
179 #undef TARGET_INIT_BUILTINS
180 #define TARGET_INIT_BUILTINS iq2000_init_builtins
181 #undef TARGET_EXPAND_BUILTIN
182 #define TARGET_EXPAND_BUILTIN iq2000_expand_builtin
183 #undef TARGET_ASM_SELECT_RTX_SECTION
184 #define TARGET_ASM_SELECT_RTX_SECTION iq2000_select_rtx_section
185 #undef TARGET_OPTION_OVERRIDE
186 #define TARGET_OPTION_OVERRIDE iq2000_option_override
187 #undef TARGET_RTX_COSTS
188 #define TARGET_RTX_COSTS iq2000_rtx_costs
189 #undef TARGET_ADDRESS_COST
190 #define TARGET_ADDRESS_COST iq2000_address_cost
191 #undef TARGET_ASM_SELECT_SECTION
192 #define TARGET_ASM_SELECT_SECTION iq2000_select_section
193
194 #undef TARGET_LEGITIMIZE_ADDRESS
195 #define TARGET_LEGITIMIZE_ADDRESS iq2000_legitimize_address
196
197 /* The assembler supports switchable .bss sections, but
198 iq2000_select_section doesn't yet make use of them. */
199 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
200 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS false
201
202 #undef TARGET_PRINT_OPERAND
203 #define TARGET_PRINT_OPERAND iq2000_print_operand
204 #undef TARGET_PRINT_OPERAND_ADDRESS
205 #define TARGET_PRINT_OPERAND_ADDRESS iq2000_print_operand_address
206 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
207 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P iq2000_print_operand_punct_valid_p
208
209 #undef TARGET_PROMOTE_FUNCTION_MODE
210 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
211 #undef TARGET_PROMOTE_PROTOTYPES
212 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
213
214 #undef TARGET_FUNCTION_VALUE
215 #define TARGET_FUNCTION_VALUE iq2000_function_value
216 #undef TARGET_LIBCALL_VALUE
217 #define TARGET_LIBCALL_VALUE iq2000_libcall_value
218 #undef TARGET_RETURN_IN_MEMORY
219 #define TARGET_RETURN_IN_MEMORY iq2000_return_in_memory
220 #undef TARGET_PASS_BY_REFERENCE
221 #define TARGET_PASS_BY_REFERENCE iq2000_pass_by_reference
222 #undef TARGET_CALLEE_COPIES
223 #define TARGET_CALLEE_COPIES hook_callee_copies_named
224 #undef TARGET_ARG_PARTIAL_BYTES
225 #define TARGET_ARG_PARTIAL_BYTES iq2000_arg_partial_bytes
226 #undef TARGET_FUNCTION_ARG
227 #define TARGET_FUNCTION_ARG iq2000_function_arg
228 #undef TARGET_FUNCTION_ARG_ADVANCE
229 #define TARGET_FUNCTION_ARG_ADVANCE iq2000_function_arg_advance
230 #undef TARGET_FUNCTION_ARG_BOUNDARY
231 #define TARGET_FUNCTION_ARG_BOUNDARY iq2000_function_arg_boundary
232
233 #undef TARGET_SETUP_INCOMING_VARARGS
234 #define TARGET_SETUP_INCOMING_VARARGS iq2000_setup_incoming_varargs
235 #undef TARGET_STRICT_ARGUMENT_NAMING
236 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
237
238 #undef TARGET_EXPAND_BUILTIN_VA_START
239 #define TARGET_EXPAND_BUILTIN_VA_START iq2000_va_start
240
241 #undef TARGET_LEGITIMATE_ADDRESS_P
242 #define TARGET_LEGITIMATE_ADDRESS_P iq2000_legitimate_address_p
243
244 #undef TARGET_CAN_ELIMINATE
245 #define TARGET_CAN_ELIMINATE iq2000_can_eliminate
246
247 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
248 #define TARGET_ASM_TRAMPOLINE_TEMPLATE iq2000_asm_trampoline_template
249 #undef TARGET_TRAMPOLINE_INIT
250 #define TARGET_TRAMPOLINE_INIT iq2000_trampoline_init
251
252 struct gcc_target targetm = TARGET_INITIALIZER;
253 \f
254 /* Return nonzero if we split the address into high and low parts. */
255
256 int
257 iq2000_check_split (rtx address, enum machine_mode mode)
258 {
259 /* This is the same check used in simple_memory_operand.
260 We use it here because LO_SUM is not offsettable. */
261 if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
262 return 0;
263
264 if ((GET_CODE (address) == SYMBOL_REF)
265 || (GET_CODE (address) == CONST
266 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF)
267 || GET_CODE (address) == LABEL_REF)
268 return 1;
269
270 return 0;
271 }
272
273 /* Return nonzero if REG is valid for MODE. */
274
275 int
276 iq2000_reg_mode_ok_for_base_p (rtx reg,
277 enum machine_mode mode ATTRIBUTE_UNUSED,
278 int strict)
279 {
280 return (strict
281 ? REGNO_MODE_OK_FOR_BASE_P (REGNO (reg), mode)
282 : GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (reg), mode));
283 }
284
285 /* Return a nonzero value if XINSN is a legitimate address for a
286 memory operand of the indicated MODE. STRICT is nonzero if this
287 function is called during reload. */
288
289 bool
290 iq2000_legitimate_address_p (enum machine_mode mode, rtx xinsn, bool strict)
291 {
292 if (TARGET_DEBUG_A_MODE)
293 {
294 GO_PRINTF2 ("\n========== legitimate_address_p, %sstrict\n",
295 strict ? "" : "not ");
296 GO_DEBUG_RTX (xinsn);
297 }
298
299 /* Check for constant before stripping off SUBREG, so that we don't
300 accept (subreg (const_int)) which will fail to reload. */
301 if (CONSTANT_ADDRESS_P (xinsn)
302 && ! (iq2000_check_split (xinsn, mode))
303 && ! (GET_CODE (xinsn) == CONST_INT && ! SMALL_INT (xinsn)))
304 return 1;
305
306 while (GET_CODE (xinsn) == SUBREG)
307 xinsn = SUBREG_REG (xinsn);
308
309 if (GET_CODE (xinsn) == REG
310 && iq2000_reg_mode_ok_for_base_p (xinsn, mode, strict))
311 return 1;
312
313 if (GET_CODE (xinsn) == LO_SUM)
314 {
315 rtx xlow0 = XEXP (xinsn, 0);
316 rtx xlow1 = XEXP (xinsn, 1);
317
318 while (GET_CODE (xlow0) == SUBREG)
319 xlow0 = SUBREG_REG (xlow0);
320 if (GET_CODE (xlow0) == REG
321 && iq2000_reg_mode_ok_for_base_p (xlow0, mode, strict)
322 && iq2000_check_split (xlow1, mode))
323 return 1;
324 }
325
326 if (GET_CODE (xinsn) == PLUS)
327 {
328 rtx xplus0 = XEXP (xinsn, 0);
329 rtx xplus1 = XEXP (xinsn, 1);
330 enum rtx_code code0;
331 enum rtx_code code1;
332
333 while (GET_CODE (xplus0) == SUBREG)
334 xplus0 = SUBREG_REG (xplus0);
335 code0 = GET_CODE (xplus0);
336
337 while (GET_CODE (xplus1) == SUBREG)
338 xplus1 = SUBREG_REG (xplus1);
339 code1 = GET_CODE (xplus1);
340
341 if (code0 == REG
342 && iq2000_reg_mode_ok_for_base_p (xplus0, mode, strict))
343 {
344 if (code1 == CONST_INT && SMALL_INT (xplus1)
345 && SMALL_INT_UNSIGNED (xplus1) /* No negative offsets */)
346 return 1;
347 }
348 }
349
350 if (TARGET_DEBUG_A_MODE)
351 GO_PRINTF ("Not a enum machine_mode mode, legitimate address\n");
352
353 /* The address was not legitimate. */
354 return 0;
355 }
356 \f
357 /* Returns an operand string for the given instruction's delay slot,
358 after updating filled delay slot statistics.
359
360 We assume that operands[0] is the target register that is set.
361
362 In order to check the next insn, most of this functionality is moved
363 to FINAL_PRESCAN_INSN, and we just set the global variables that
364 it needs. */
365
366 const char *
367 iq2000_fill_delay_slot (const char *ret, enum delay_type type, rtx operands[],
368 rtx cur_insn)
369 {
370 rtx set_reg;
371 enum machine_mode mode;
372 rtx next_insn = cur_insn ? NEXT_INSN (cur_insn) : NULL_RTX;
373 int num_nops;
374
375 if (type == DELAY_LOAD || type == DELAY_FCMP)
376 num_nops = 1;
377
378 else
379 num_nops = 0;
380
381 /* Make sure that we don't put nop's after labels. */
382 next_insn = NEXT_INSN (cur_insn);
383 while (next_insn != 0
384 && (GET_CODE (next_insn) == NOTE
385 || GET_CODE (next_insn) == CODE_LABEL))
386 next_insn = NEXT_INSN (next_insn);
387
388 dslots_load_total += num_nops;
389 if (TARGET_DEBUG_C_MODE
390 || type == DELAY_NONE
391 || operands == 0
392 || cur_insn == 0
393 || next_insn == 0
394 || GET_CODE (next_insn) == CODE_LABEL
395 || (set_reg = operands[0]) == 0)
396 {
397 dslots_number_nops = 0;
398 iq2000_load_reg = 0;
399 iq2000_load_reg2 = 0;
400 iq2000_load_reg3 = 0;
401 iq2000_load_reg4 = 0;
402
403 return ret;
404 }
405
406 set_reg = operands[0];
407 if (set_reg == 0)
408 return ret;
409
410 while (GET_CODE (set_reg) == SUBREG)
411 set_reg = SUBREG_REG (set_reg);
412
413 mode = GET_MODE (set_reg);
414 dslots_number_nops = num_nops;
415 iq2000_load_reg = set_reg;
416 if (GET_MODE_SIZE (mode)
417 > (unsigned) (UNITS_PER_WORD))
418 iq2000_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1);
419 else
420 iq2000_load_reg2 = 0;
421
422 return ret;
423 }
424 \f
425 /* Determine whether a memory reference takes one (based off of the GP
426 pointer), two (normal), or three (label + reg) instructions, and bump the
427 appropriate counter for -mstats. */
428
429 static void
430 iq2000_count_memory_refs (rtx op, int num)
431 {
432 int additional = 0;
433 int n_words = 0;
434 rtx addr, plus0, plus1;
435 enum rtx_code code0, code1;
436 int looping;
437
438 if (TARGET_DEBUG_B_MODE)
439 {
440 fprintf (stderr, "\n========== iq2000_count_memory_refs:\n");
441 debug_rtx (op);
442 }
443
444 /* Skip MEM if passed, otherwise handle movsi of address. */
445 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
446
447 /* Loop, going through the address RTL. */
448 do
449 {
450 looping = FALSE;
451 switch (GET_CODE (addr))
452 {
453 case REG:
454 case CONST_INT:
455 case LO_SUM:
456 break;
457
458 case PLUS:
459 plus0 = XEXP (addr, 0);
460 plus1 = XEXP (addr, 1);
461 code0 = GET_CODE (plus0);
462 code1 = GET_CODE (plus1);
463
464 if (code0 == REG)
465 {
466 additional++;
467 addr = plus1;
468 looping = 1;
469 continue;
470 }
471
472 if (code0 == CONST_INT)
473 {
474 addr = plus1;
475 looping = 1;
476 continue;
477 }
478
479 if (code1 == REG)
480 {
481 additional++;
482 addr = plus0;
483 looping = 1;
484 continue;
485 }
486
487 if (code1 == CONST_INT)
488 {
489 addr = plus0;
490 looping = 1;
491 continue;
492 }
493
494 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
495 {
496 addr = plus0;
497 looping = 1;
498 continue;
499 }
500
501 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
502 {
503 addr = plus1;
504 looping = 1;
505 continue;
506 }
507
508 break;
509
510 case LABEL_REF:
511 n_words = 2; /* Always 2 words. */
512 break;
513
514 case CONST:
515 addr = XEXP (addr, 0);
516 looping = 1;
517 continue;
518
519 case SYMBOL_REF:
520 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
521 break;
522
523 default:
524 break;
525 }
526 }
527 while (looping);
528
529 if (n_words == 0)
530 return;
531
532 n_words += additional;
533 if (n_words > 3)
534 n_words = 3;
535
536 num_refs[n_words-1] += num;
537 }
538 \f
539 /* Abort after printing out a specific insn. */
540
541 static void
542 abort_with_insn (rtx insn, const char * reason)
543 {
544 error (reason);
545 debug_rtx (insn);
546 fancy_abort (__FILE__, __LINE__, __FUNCTION__);
547 }
548 \f
549 /* Return the appropriate instructions to move one operand to another. */
550
551 const char *
552 iq2000_move_1word (rtx operands[], rtx insn, int unsignedp)
553 {
554 const char *ret = 0;
555 rtx op0 = operands[0];
556 rtx op1 = operands[1];
557 enum rtx_code code0 = GET_CODE (op0);
558 enum rtx_code code1 = GET_CODE (op1);
559 enum machine_mode mode = GET_MODE (op0);
560 int subreg_offset0 = 0;
561 int subreg_offset1 = 0;
562 enum delay_type delay = DELAY_NONE;
563
564 while (code0 == SUBREG)
565 {
566 subreg_offset0 += subreg_regno_offset (REGNO (SUBREG_REG (op0)),
567 GET_MODE (SUBREG_REG (op0)),
568 SUBREG_BYTE (op0),
569 GET_MODE (op0));
570 op0 = SUBREG_REG (op0);
571 code0 = GET_CODE (op0);
572 }
573
574 while (code1 == SUBREG)
575 {
576 subreg_offset1 += subreg_regno_offset (REGNO (SUBREG_REG (op1)),
577 GET_MODE (SUBREG_REG (op1)),
578 SUBREG_BYTE (op1),
579 GET_MODE (op1));
580 op1 = SUBREG_REG (op1);
581 code1 = GET_CODE (op1);
582 }
583
584 /* For our purposes, a condition code mode is the same as SImode. */
585 if (mode == CCmode)
586 mode = SImode;
587
588 if (code0 == REG)
589 {
590 int regno0 = REGNO (op0) + subreg_offset0;
591
592 if (code1 == REG)
593 {
594 int regno1 = REGNO (op1) + subreg_offset1;
595
596 /* Do not do anything for assigning a register to itself */
597 if (regno0 == regno1)
598 ret = "";
599
600 else if (GP_REG_P (regno0))
601 {
602 if (GP_REG_P (regno1))
603 ret = "or\t%0,%%0,%1";
604 }
605
606 }
607
608 else if (code1 == MEM)
609 {
610 delay = DELAY_LOAD;
611
612 if (TARGET_STATS)
613 iq2000_count_memory_refs (op1, 1);
614
615 if (GP_REG_P (regno0))
616 {
617 /* For loads, use the mode of the memory item, instead of the
618 target, so zero/sign extend can use this code as well. */
619 switch (GET_MODE (op1))
620 {
621 default:
622 break;
623 case SFmode:
624 ret = "lw\t%0,%1";
625 break;
626 case SImode:
627 case CCmode:
628 ret = "lw\t%0,%1";
629 break;
630 case HImode:
631 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
632 break;
633 case QImode:
634 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
635 break;
636 }
637 }
638 }
639
640 else if (code1 == CONST_INT
641 || (code1 == CONST_DOUBLE
642 && GET_MODE (op1) == VOIDmode))
643 {
644 if (code1 == CONST_DOUBLE)
645 {
646 /* This can happen when storing constants into long long
647 bitfields. Just store the least significant word of
648 the value. */
649 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
650 }
651
652 if (INTVAL (op1) == 0)
653 {
654 if (GP_REG_P (regno0))
655 ret = "or\t%0,%%0,%z1";
656 }
657 else if (GP_REG_P (regno0))
658 {
659 if (SMALL_INT_UNSIGNED (op1))
660 ret = "ori\t%0,%%0,%x1\t\t\t# %1";
661 else if (SMALL_INT (op1))
662 ret = "addiu\t%0,%%0,%1\t\t\t# %1";
663 else
664 ret = "lui\t%0,%X1\t\t\t# %1\n\tori\t%0,%0,%x1";
665 }
666 }
667
668 else if (code1 == CONST_DOUBLE && mode == SFmode)
669 {
670 if (op1 == CONST0_RTX (SFmode))
671 {
672 if (GP_REG_P (regno0))
673 ret = "or\t%0,%%0,%.";
674 }
675
676 else
677 {
678 delay = DELAY_LOAD;
679 ret = "li.s\t%0,%1";
680 }
681 }
682
683 else if (code1 == LABEL_REF)
684 {
685 if (TARGET_STATS)
686 iq2000_count_memory_refs (op1, 1);
687
688 ret = "la\t%0,%a1";
689 }
690
691 else if (code1 == SYMBOL_REF || code1 == CONST)
692 {
693 if (TARGET_STATS)
694 iq2000_count_memory_refs (op1, 1);
695
696 ret = "la\t%0,%a1";
697 }
698
699 else if (code1 == PLUS)
700 {
701 rtx add_op0 = XEXP (op1, 0);
702 rtx add_op1 = XEXP (op1, 1);
703
704 if (GET_CODE (XEXP (op1, 1)) == REG
705 && GET_CODE (XEXP (op1, 0)) == CONST_INT)
706 add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
707
708 operands[2] = add_op0;
709 operands[3] = add_op1;
710 ret = "add%:\t%0,%2,%3";
711 }
712
713 else if (code1 == HIGH)
714 {
715 operands[1] = XEXP (op1, 0);
716 ret = "lui\t%0,%%hi(%1)";
717 }
718 }
719
720 else if (code0 == MEM)
721 {
722 if (TARGET_STATS)
723 iq2000_count_memory_refs (op0, 1);
724
725 if (code1 == REG)
726 {
727 int regno1 = REGNO (op1) + subreg_offset1;
728
729 if (GP_REG_P (regno1))
730 {
731 switch (mode)
732 {
733 case SFmode: ret = "sw\t%1,%0"; break;
734 case SImode: ret = "sw\t%1,%0"; break;
735 case HImode: ret = "sh\t%1,%0"; break;
736 case QImode: ret = "sb\t%1,%0"; break;
737 default: break;
738 }
739 }
740 }
741
742 else if (code1 == CONST_INT && INTVAL (op1) == 0)
743 {
744 switch (mode)
745 {
746 case SFmode: ret = "sw\t%z1,%0"; break;
747 case SImode: ret = "sw\t%z1,%0"; break;
748 case HImode: ret = "sh\t%z1,%0"; break;
749 case QImode: ret = "sb\t%z1,%0"; break;
750 default: break;
751 }
752 }
753
754 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
755 {
756 switch (mode)
757 {
758 case SFmode: ret = "sw\t%.,%0"; break;
759 case SImode: ret = "sw\t%.,%0"; break;
760 case HImode: ret = "sh\t%.,%0"; break;
761 case QImode: ret = "sb\t%.,%0"; break;
762 default: break;
763 }
764 }
765 }
766
767 if (ret == 0)
768 {
769 abort_with_insn (insn, "Bad move");
770 return 0;
771 }
772
773 if (delay != DELAY_NONE)
774 return iq2000_fill_delay_slot (ret, delay, operands, insn);
775
776 return ret;
777 }
778 \f
779 /* Provide the costs of an addressing mode that contains ADDR. */
780
781 static int
782 iq2000_address_cost (rtx addr, bool speed)
783 {
784 switch (GET_CODE (addr))
785 {
786 case LO_SUM:
787 return 1;
788
789 case LABEL_REF:
790 return 2;
791
792 case CONST:
793 {
794 rtx offset = const0_rtx;
795
796 addr = eliminate_constant_term (XEXP (addr, 0), & offset);
797 if (GET_CODE (addr) == LABEL_REF)
798 return 2;
799
800 if (GET_CODE (addr) != SYMBOL_REF)
801 return 4;
802
803 if (! SMALL_INT (offset))
804 return 2;
805 }
806
807 /* Fall through. */
808
809 case SYMBOL_REF:
810 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
811
812 case PLUS:
813 {
814 rtx plus0 = XEXP (addr, 0);
815 rtx plus1 = XEXP (addr, 1);
816
817 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
818 plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
819
820 if (GET_CODE (plus0) != REG)
821 break;
822
823 switch (GET_CODE (plus1))
824 {
825 case CONST_INT:
826 return SMALL_INT (plus1) ? 1 : 2;
827
828 case CONST:
829 case SYMBOL_REF:
830 case LABEL_REF:
831 case HIGH:
832 case LO_SUM:
833 return iq2000_address_cost (plus1, speed) + 1;
834
835 default:
836 break;
837 }
838 }
839
840 default:
841 break;
842 }
843
844 return 4;
845 }
846 \f
847 /* Make normal rtx_code into something we can index from an array. */
848
849 static enum internal_test
850 map_test_to_internal_test (enum rtx_code test_code)
851 {
852 enum internal_test test = ITEST_MAX;
853
854 switch (test_code)
855 {
856 case EQ: test = ITEST_EQ; break;
857 case NE: test = ITEST_NE; break;
858 case GT: test = ITEST_GT; break;
859 case GE: test = ITEST_GE; break;
860 case LT: test = ITEST_LT; break;
861 case LE: test = ITEST_LE; break;
862 case GTU: test = ITEST_GTU; break;
863 case GEU: test = ITEST_GEU; break;
864 case LTU: test = ITEST_LTU; break;
865 case LEU: test = ITEST_LEU; break;
866 default: break;
867 }
868
869 return test;
870 }
871 \f
872 /* Generate the code to do a TEST_CODE comparison on two integer values CMP0
873 and CMP1. P_INVERT is NULL or ptr if branch needs to reverse its test.
874 The return value RESULT is:
875 (reg:SI xx) The pseudo register the comparison is in
876 0 No register, generate a simple branch. */
877
878 rtx
879 gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
880 int *p_invert)
881 {
882 struct cmp_info
883 {
884 enum rtx_code test_code; /* Code to use in instruction (LT vs. LTU). */
885 int const_low; /* Low bound of constant we can accept. */
886 int const_high; /* High bound of constant we can accept. */
887 int const_add; /* Constant to add (convert LE -> LT). */
888 int reverse_regs; /* Reverse registers in test. */
889 int invert_const; /* != 0 if invert value if cmp1 is constant. */
890 int invert_reg; /* != 0 if invert value if cmp1 is register. */
891 int unsignedp; /* != 0 for unsigned comparisons. */
892 };
893
894 static struct cmp_info info[ (int)ITEST_MAX ] =
895 {
896 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
897 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
898 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
899 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
900 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
901 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
902 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
903 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
904 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
905 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
906 };
907
908 enum internal_test test;
909 enum machine_mode mode;
910 struct cmp_info *p_info;
911 int branch_p;
912 int eqne_p;
913 int invert;
914 rtx reg;
915 rtx reg2;
916
917 test = map_test_to_internal_test (test_code);
918 gcc_assert (test != ITEST_MAX);
919
920 p_info = &info[(int) test];
921 eqne_p = (p_info->test_code == XOR);
922
923 mode = GET_MODE (cmp0);
924 if (mode == VOIDmode)
925 mode = GET_MODE (cmp1);
926
927 /* Eliminate simple branches. */
928 branch_p = (result == 0);
929 if (branch_p)
930 {
931 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
932 {
933 /* Comparisons against zero are simple branches. */
934 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
935 return 0;
936
937 /* Test for beq/bne. */
938 if (eqne_p)
939 return 0;
940 }
941
942 /* Allocate a pseudo to calculate the value in. */
943 result = gen_reg_rtx (mode);
944 }
945
946 /* Make sure we can handle any constants given to us. */
947 if (GET_CODE (cmp0) == CONST_INT)
948 cmp0 = force_reg (mode, cmp0);
949
950 if (GET_CODE (cmp1) == CONST_INT)
951 {
952 HOST_WIDE_INT value = INTVAL (cmp1);
953
954 if (value < p_info->const_low
955 || value > p_info->const_high)
956 cmp1 = force_reg (mode, cmp1);
957 }
958
959 /* See if we need to invert the result. */
960 invert = (GET_CODE (cmp1) == CONST_INT
961 ? p_info->invert_const : p_info->invert_reg);
962
963 if (p_invert != (int *)0)
964 {
965 *p_invert = invert;
966 invert = 0;
967 }
968
969 /* Comparison to constants, may involve adding 1 to change a LT into LE.
970 Comparison between two registers, may involve switching operands. */
971 if (GET_CODE (cmp1) == CONST_INT)
972 {
973 if (p_info->const_add != 0)
974 {
975 HOST_WIDE_INT new_const = INTVAL (cmp1) + p_info->const_add;
976
977 /* If modification of cmp1 caused overflow,
978 we would get the wrong answer if we follow the usual path;
979 thus, x > 0xffffffffU would turn into x > 0U. */
980 if ((p_info->unsignedp
981 ? (unsigned HOST_WIDE_INT) new_const >
982 (unsigned HOST_WIDE_INT) INTVAL (cmp1)
983 : new_const > INTVAL (cmp1))
984 != (p_info->const_add > 0))
985 {
986 /* This test is always true, but if INVERT is true then
987 the result of the test needs to be inverted so 0 should
988 be returned instead. */
989 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
990 return result;
991 }
992 else
993 cmp1 = GEN_INT (new_const);
994 }
995 }
996
997 else if (p_info->reverse_regs)
998 {
999 rtx temp = cmp0;
1000 cmp0 = cmp1;
1001 cmp1 = temp;
1002 }
1003
1004 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
1005 reg = cmp0;
1006 else
1007 {
1008 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
1009 convert_move (reg, gen_rtx_fmt_ee (p_info->test_code, mode, cmp0, cmp1), 0);
1010 }
1011
1012 if (test == ITEST_NE)
1013 {
1014 convert_move (result, gen_rtx_GTU (mode, reg, const0_rtx), 0);
1015 if (p_invert != NULL)
1016 *p_invert = 0;
1017 invert = 0;
1018 }
1019
1020 else if (test == ITEST_EQ)
1021 {
1022 reg2 = invert ? gen_reg_rtx (mode) : result;
1023 convert_move (reg2, gen_rtx_LTU (mode, reg, const1_rtx), 0);
1024 reg = reg2;
1025 }
1026
1027 if (invert)
1028 {
1029 rtx one;
1030
1031 one = const1_rtx;
1032 convert_move (result, gen_rtx_XOR (mode, reg, one), 0);
1033 }
1034
1035 return result;
1036 }
1037 \f
1038 /* Emit the common code for doing conditional branches.
1039 operand[0] is the label to jump to.
1040 The comparison operands are saved away by cmp{si,di,sf,df}. */
1041
1042 void
1043 gen_conditional_branch (rtx operands[], enum machine_mode mode)
1044 {
1045 enum rtx_code test_code = GET_CODE (operands[0]);
1046 rtx cmp0 = operands[1];
1047 rtx cmp1 = operands[2];
1048 rtx reg;
1049 int invert;
1050 rtx label1, label2;
1051
1052 invert = 0;
1053 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
1054
1055 if (reg)
1056 {
1057 cmp0 = reg;
1058 cmp1 = const0_rtx;
1059 test_code = NE;
1060 }
1061 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
1062 /* We don't want to build a comparison against a nonzero
1063 constant. */
1064 cmp1 = force_reg (mode, cmp1);
1065
1066 /* Generate the branch. */
1067 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]);
1068 label2 = pc_rtx;
1069
1070 if (invert)
1071 {
1072 label2 = label1;
1073 label1 = pc_rtx;
1074 }
1075
1076 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
1077 gen_rtx_IF_THEN_ELSE (VOIDmode,
1078 gen_rtx_fmt_ee (test_code,
1079 mode,
1080 cmp0, cmp1),
1081 label1, label2)));
1082 }
1083 \f
1084 /* Initialize CUM for a function FNTYPE. */
1085
1086 void
1087 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
1088 rtx libname ATTRIBUTE_UNUSED)
1089 {
1090 static CUMULATIVE_ARGS zero_cum;
1091 tree param;
1092 tree next_param;
1093
1094 if (TARGET_DEBUG_D_MODE)
1095 {
1096 fprintf (stderr,
1097 "\ninit_cumulative_args, fntype = 0x%.8lx", (long) fntype);
1098
1099 if (!fntype)
1100 fputc ('\n', stderr);
1101
1102 else
1103 {
1104 tree ret_type = TREE_TYPE (fntype);
1105
1106 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
1107 tree_code_name[(int)TREE_CODE (fntype)],
1108 tree_code_name[(int)TREE_CODE (ret_type)]);
1109 }
1110 }
1111
1112 *cum = zero_cum;
1113
1114 /* Determine if this function has variable arguments. This is
1115 indicated by the last argument being 'void_type_mode' if there
1116 are no variable arguments. The standard IQ2000 calling sequence
1117 passes all arguments in the general purpose registers in this case. */
1118
1119 for (param = fntype ? TYPE_ARG_TYPES (fntype) : 0;
1120 param != 0; param = next_param)
1121 {
1122 next_param = TREE_CHAIN (param);
1123 if (next_param == 0 && TREE_VALUE (param) != void_type_node)
1124 cum->gp_reg_found = 1;
1125 }
1126 }
1127
1128 /* Advance the argument of type TYPE and mode MODE to the next argument
1129 position in CUM. */
1130
1131 static void
1132 iq2000_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1133 const_tree type, bool named)
1134 {
1135 if (TARGET_DEBUG_D_MODE)
1136 {
1137 fprintf (stderr,
1138 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
1139 cum->gp_reg_found, cum->arg_number, cum->arg_words,
1140 GET_MODE_NAME (mode));
1141 fprintf (stderr, "%p", CONST_CAST2 (void *, const_tree, type));
1142 fprintf (stderr, ", %d )\n\n", named);
1143 }
1144
1145 cum->arg_number++;
1146 switch (mode)
1147 {
1148 case VOIDmode:
1149 break;
1150
1151 default:
1152 gcc_assert (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
1153 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT);
1154
1155 cum->gp_reg_found = 1;
1156 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
1157 / UNITS_PER_WORD);
1158 break;
1159
1160 case BLKmode:
1161 cum->gp_reg_found = 1;
1162 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
1163 / UNITS_PER_WORD);
1164 break;
1165
1166 case SFmode:
1167 cum->arg_words ++;
1168 if (! cum->gp_reg_found && cum->arg_number <= 2)
1169 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
1170 break;
1171
1172 case DFmode:
1173 cum->arg_words += 2;
1174 if (! cum->gp_reg_found && cum->arg_number <= 2)
1175 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
1176 break;
1177
1178 case DImode:
1179 cum->gp_reg_found = 1;
1180 cum->arg_words += 2;
1181 break;
1182
1183 case TImode:
1184 cum->gp_reg_found = 1;
1185 cum->arg_words += 4;
1186 break;
1187
1188 case QImode:
1189 case HImode:
1190 case SImode:
1191 cum->gp_reg_found = 1;
1192 cum->arg_words ++;
1193 break;
1194 }
1195 }
1196
1197 /* Return an RTL expression containing the register for the given mode MODE
1198 and type TYPE in CUM, or 0 if the argument is to be passed on the stack. */
1199
1200 static rtx
1201 iq2000_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1202 const_tree type, bool named)
1203 {
1204 rtx ret;
1205 int regbase = -1;
1206 int bias = 0;
1207 unsigned int *arg_words = &cum->arg_words;
1208 int struct_p = (type != 0
1209 && (TREE_CODE (type) == RECORD_TYPE
1210 || TREE_CODE (type) == UNION_TYPE
1211 || TREE_CODE (type) == QUAL_UNION_TYPE));
1212
1213 if (TARGET_DEBUG_D_MODE)
1214 {
1215 fprintf (stderr,
1216 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, ",
1217 cum->gp_reg_found, cum->arg_number, cum->arg_words,
1218 GET_MODE_NAME (mode));
1219 fprintf (stderr, "%p", (const void *) type);
1220 fprintf (stderr, ", %d ) = ", named);
1221 }
1222
1223
1224 cum->last_arg_fp = 0;
1225 switch (mode)
1226 {
1227 case SFmode:
1228 regbase = GP_ARG_FIRST;
1229 break;
1230
1231 case DFmode:
1232 cum->arg_words += cum->arg_words & 1;
1233
1234 regbase = GP_ARG_FIRST;
1235 break;
1236
1237 default:
1238 gcc_assert (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
1239 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT);
1240
1241 /* Drops through. */
1242 case BLKmode:
1243 if (type != NULL_TREE && TYPE_ALIGN (type) > (unsigned) BITS_PER_WORD)
1244 cum->arg_words += (cum->arg_words & 1);
1245 regbase = GP_ARG_FIRST;
1246 break;
1247
1248 case VOIDmode:
1249 case QImode:
1250 case HImode:
1251 case SImode:
1252 regbase = GP_ARG_FIRST;
1253 break;
1254
1255 case DImode:
1256 cum->arg_words += (cum->arg_words & 1);
1257 regbase = GP_ARG_FIRST;
1258 break;
1259
1260 case TImode:
1261 cum->arg_words += (cum->arg_words & 3);
1262 regbase = GP_ARG_FIRST;
1263 break;
1264 }
1265
1266 if (*arg_words >= (unsigned) MAX_ARGS_IN_REGISTERS)
1267 {
1268 if (TARGET_DEBUG_D_MODE)
1269 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
1270
1271 ret = 0;
1272 }
1273 else
1274 {
1275 gcc_assert (regbase != -1);
1276
1277 if (! type || TREE_CODE (type) != RECORD_TYPE
1278 || ! named || ! TYPE_SIZE_UNIT (type)
1279 || ! host_integerp (TYPE_SIZE_UNIT (type), 1))
1280 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
1281 else
1282 {
1283 tree field;
1284
1285 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
1286 if (TREE_CODE (field) == FIELD_DECL
1287 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
1288 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
1289 && host_integerp (bit_position (field), 0)
1290 && int_bit_position (field) % BITS_PER_WORD == 0)
1291 break;
1292
1293 /* If the whole struct fits a DFmode register,
1294 we don't need the PARALLEL. */
1295 if (! field || mode == DFmode)
1296 ret = gen_rtx_REG (mode, regbase + *arg_words + bias);
1297 else
1298 {
1299 unsigned int chunks;
1300 HOST_WIDE_INT bitpos;
1301 unsigned int regno;
1302 unsigned int i;
1303
1304 /* ??? If this is a packed structure, then the last hunk won't
1305 be 64 bits. */
1306 chunks
1307 = tree_low_cst (TYPE_SIZE_UNIT (type), 1) / UNITS_PER_WORD;
1308 if (chunks + *arg_words + bias > (unsigned) MAX_ARGS_IN_REGISTERS)
1309 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
1310
1311 /* Assign_parms checks the mode of ENTRY_PARM, so we must
1312 use the actual mode here. */
1313 ret = gen_rtx_PARALLEL (mode, rtvec_alloc (chunks));
1314
1315 bitpos = 0;
1316 regno = regbase + *arg_words + bias;
1317 field = TYPE_FIELDS (type);
1318 for (i = 0; i < chunks; i++)
1319 {
1320 rtx reg;
1321
1322 for (; field; field = DECL_CHAIN (field))
1323 if (TREE_CODE (field) == FIELD_DECL
1324 && int_bit_position (field) >= bitpos)
1325 break;
1326
1327 if (field
1328 && int_bit_position (field) == bitpos
1329 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
1330 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
1331 reg = gen_rtx_REG (DFmode, regno++);
1332 else
1333 reg = gen_rtx_REG (word_mode, regno);
1334
1335 XVECEXP (ret, 0, i)
1336 = gen_rtx_EXPR_LIST (VOIDmode, reg,
1337 GEN_INT (bitpos / BITS_PER_UNIT));
1338
1339 bitpos += 64;
1340 regno++;
1341 }
1342 }
1343 }
1344
1345 if (TARGET_DEBUG_D_MODE)
1346 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
1347 struct_p ? ", [struct]" : "");
1348 }
1349
1350 /* We will be called with a mode of VOIDmode after the last argument
1351 has been seen. Whatever we return will be passed to the call
1352 insn. If we need any shifts for small structures, return them in
1353 a PARALLEL. */
1354 if (mode == VOIDmode)
1355 {
1356 if (cum->num_adjusts > 0)
1357 ret = gen_rtx_PARALLEL ((enum machine_mode) cum->fp_code,
1358 gen_rtvec_v (cum->num_adjusts, cum->adjust));
1359 }
1360
1361 return ret;
1362 }
1363
1364 static unsigned int
1365 iq2000_function_arg_boundary (enum machine_mode mode, const_tree type)
1366 {
1367 return (type != NULL_TREE
1368 ? (TYPE_ALIGN (type) <= PARM_BOUNDARY
1369 ? PARM_BOUNDARY
1370 : TYPE_ALIGN (type))
1371 : (GET_MODE_ALIGNMENT (mode) <= PARM_BOUNDARY
1372 ? PARM_BOUNDARY
1373 : GET_MODE_ALIGNMENT (mode)));
1374 }
1375
1376 static int
1377 iq2000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1378 tree type ATTRIBUTE_UNUSED,
1379 bool named ATTRIBUTE_UNUSED)
1380 {
1381 if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS - 1)
1382 {
1383 if (TARGET_DEBUG_D_MODE)
1384 fprintf (stderr, "iq2000_arg_partial_bytes=%d\n", UNITS_PER_WORD);
1385 return UNITS_PER_WORD;
1386 }
1387
1388 return 0;
1389 }
1390 \f
1391 /* Implement va_start. */
1392
1393 static void
1394 iq2000_va_start (tree valist, rtx nextarg)
1395 {
1396 int int_arg_words;
1397 /* Find out how many non-float named formals. */
1398 int gpr_save_area_size;
1399 /* Note UNITS_PER_WORD is 4 bytes. */
1400 int_arg_words = crtl->args.info.arg_words;
1401
1402 if (int_arg_words < 8 )
1403 /* Adjust for the prologue's economy measure. */
1404 gpr_save_area_size = (8 - int_arg_words) * UNITS_PER_WORD;
1405 else
1406 gpr_save_area_size = 0;
1407
1408 /* Everything is in the GPR save area, or in the overflow
1409 area which is contiguous with it. */
1410 nextarg = plus_constant (nextarg, - gpr_save_area_size);
1411 std_expand_builtin_va_start (valist, nextarg);
1412 }
1413 \f
1414 /* Allocate a chunk of memory for per-function machine-dependent data. */
1415
1416 static struct machine_function *
1417 iq2000_init_machine_status (void)
1418 {
1419 return ggc_alloc_cleared_machine_function ();
1420 }
1421
1422 /* Detect any conflicts in the switches. */
1423
1424 static void
1425 iq2000_option_override (void)
1426 {
1427 target_flags &= ~MASK_GPOPT;
1428
1429 iq2000_isa = IQ2000_ISA_DEFAULT;
1430
1431 /* Identify the processor type. */
1432
1433 iq2000_print_operand_punct['?'] = 1;
1434 iq2000_print_operand_punct['#'] = 1;
1435 iq2000_print_operand_punct['&'] = 1;
1436 iq2000_print_operand_punct['!'] = 1;
1437 iq2000_print_operand_punct['*'] = 1;
1438 iq2000_print_operand_punct['@'] = 1;
1439 iq2000_print_operand_punct['.'] = 1;
1440 iq2000_print_operand_punct['('] = 1;
1441 iq2000_print_operand_punct[')'] = 1;
1442 iq2000_print_operand_punct['['] = 1;
1443 iq2000_print_operand_punct[']'] = 1;
1444 iq2000_print_operand_punct['<'] = 1;
1445 iq2000_print_operand_punct['>'] = 1;
1446 iq2000_print_operand_punct['{'] = 1;
1447 iq2000_print_operand_punct['}'] = 1;
1448 iq2000_print_operand_punct['^'] = 1;
1449 iq2000_print_operand_punct['$'] = 1;
1450 iq2000_print_operand_punct['+'] = 1;
1451 iq2000_print_operand_punct['~'] = 1;
1452
1453 /* Save GPR registers in word_mode sized hunks. word_mode hasn't been
1454 initialized yet, so we can't use that here. */
1455 gpr_mode = SImode;
1456
1457 /* Function to allocate machine-dependent function status. */
1458 init_machine_status = iq2000_init_machine_status;
1459 }
1460 \f
1461 /* The arg pointer (which is eliminated) points to the virtual frame pointer,
1462 while the frame pointer (which may be eliminated) points to the stack
1463 pointer after the initial adjustments. */
1464
1465 HOST_WIDE_INT
1466 iq2000_debugger_offset (rtx addr, HOST_WIDE_INT offset)
1467 {
1468 rtx offset2 = const0_rtx;
1469 rtx reg = eliminate_constant_term (addr, & offset2);
1470
1471 if (offset == 0)
1472 offset = INTVAL (offset2);
1473
1474 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
1475 || reg == hard_frame_pointer_rtx)
1476 {
1477 HOST_WIDE_INT frame_size = (!cfun->machine->initialized)
1478 ? compute_frame_size (get_frame_size ())
1479 : cfun->machine->total_size;
1480
1481 offset = offset - frame_size;
1482 }
1483
1484 return offset;
1485 }
1486 \f
1487 /* If defined, a C statement to be executed just prior to the output of
1488 assembler code for INSN, to modify the extracted operands so they will be
1489 output differently.
1490
1491 Here the argument OPVEC is the vector containing the operands extracted
1492 from INSN, and NOPERANDS is the number of elements of the vector which
1493 contain meaningful data for this insn. The contents of this vector are
1494 what will be used to convert the insn template into assembler code, so you
1495 can change the assembler output by changing the contents of the vector.
1496
1497 We use it to check if the current insn needs a nop in front of it because
1498 of load delays, and also to update the delay slot statistics. */
1499
1500 void
1501 final_prescan_insn (rtx insn, rtx opvec[] ATTRIBUTE_UNUSED,
1502 int noperands ATTRIBUTE_UNUSED)
1503 {
1504 if (dslots_number_nops > 0)
1505 {
1506 rtx pattern = PATTERN (insn);
1507 int length = get_attr_length (insn);
1508
1509 /* Do we need to emit a NOP? */
1510 if (length == 0
1511 || (iq2000_load_reg != 0 && reg_mentioned_p (iq2000_load_reg, pattern))
1512 || (iq2000_load_reg2 != 0 && reg_mentioned_p (iq2000_load_reg2, pattern))
1513 || (iq2000_load_reg3 != 0 && reg_mentioned_p (iq2000_load_reg3, pattern))
1514 || (iq2000_load_reg4 != 0
1515 && reg_mentioned_p (iq2000_load_reg4, pattern)))
1516 fputs ("\tnop\n", asm_out_file);
1517
1518 else
1519 dslots_load_filled ++;
1520
1521 while (--dslots_number_nops > 0)
1522 fputs ("\tnop\n", asm_out_file);
1523
1524 iq2000_load_reg = 0;
1525 iq2000_load_reg2 = 0;
1526 iq2000_load_reg3 = 0;
1527 iq2000_load_reg4 = 0;
1528 }
1529
1530 if ( (GET_CODE (insn) == JUMP_INSN
1531 || GET_CODE (insn) == CALL_INSN
1532 || (GET_CODE (PATTERN (insn)) == RETURN))
1533 && NEXT_INSN (PREV_INSN (insn)) == insn)
1534 {
1535 rtx nop_insn = emit_insn_after (gen_nop (), insn);
1536
1537 INSN_ADDRESSES_NEW (nop_insn, -1);
1538 }
1539
1540 if (TARGET_STATS
1541 && (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CALL_INSN))
1542 dslots_jump_total ++;
1543 }
1544 \f
1545 /* Return the bytes needed to compute the frame pointer from the current
1546 stack pointer where SIZE is the # of var. bytes allocated.
1547
1548 IQ2000 stack frames look like:
1549
1550 Before call After call
1551 +-----------------------+ +-----------------------+
1552 high | | | |
1553 mem. | | | |
1554 | caller's temps. | | caller's temps. |
1555 | | | |
1556 +-----------------------+ +-----------------------+
1557 | | | |
1558 | arguments on stack. | | arguments on stack. |
1559 | | | |
1560 +-----------------------+ +-----------------------+
1561 | 4 words to save | | 4 words to save |
1562 | arguments passed | | arguments passed |
1563 | in registers, even | | in registers, even |
1564 SP->| if not passed. | VFP->| if not passed. |
1565 +-----------------------+ +-----------------------+
1566 | |
1567 | fp register save |
1568 | |
1569 +-----------------------+
1570 | |
1571 | gp register save |
1572 | |
1573 +-----------------------+
1574 | |
1575 | local variables |
1576 | |
1577 +-----------------------+
1578 | |
1579 | alloca allocations |
1580 | |
1581 +-----------------------+
1582 | |
1583 | GP save for V.4 abi |
1584 | |
1585 +-----------------------+
1586 | |
1587 | arguments on stack |
1588 | |
1589 +-----------------------+
1590 | 4 words to save |
1591 | arguments passed |
1592 | in registers, even |
1593 low SP->| if not passed. |
1594 memory +-----------------------+ */
1595
1596 HOST_WIDE_INT
1597 compute_frame_size (HOST_WIDE_INT size)
1598 {
1599 int regno;
1600 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
1601 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
1602 HOST_WIDE_INT args_size; /* # bytes that outgoing arguments take up. */
1603 HOST_WIDE_INT extra_size; /* # extra bytes. */
1604 HOST_WIDE_INT gp_reg_rounded; /* # bytes needed to store gp after rounding. */
1605 HOST_WIDE_INT gp_reg_size; /* # bytes needed to store gp regs. */
1606 HOST_WIDE_INT fp_reg_size; /* # bytes needed to store fp regs. */
1607 long mask; /* mask of saved gp registers. */
1608
1609 gp_reg_size = 0;
1610 fp_reg_size = 0;
1611 mask = 0;
1612 extra_size = IQ2000_STACK_ALIGN ((0));
1613 var_size = IQ2000_STACK_ALIGN (size);
1614 args_size = IQ2000_STACK_ALIGN (crtl->outgoing_args_size);
1615
1616 /* If a function dynamically allocates the stack and
1617 has 0 for STACK_DYNAMIC_OFFSET then allocate some stack space. */
1618 if (args_size == 0 && cfun->calls_alloca)
1619 args_size = 4 * UNITS_PER_WORD;
1620
1621 total_size = var_size + args_size + extra_size;
1622
1623 /* Calculate space needed for gp registers. */
1624 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
1625 {
1626 if (MUST_SAVE_REGISTER (regno))
1627 {
1628 gp_reg_size += GET_MODE_SIZE (gpr_mode);
1629 mask |= 1L << (regno - GP_REG_FIRST);
1630 }
1631 }
1632
1633 /* We need to restore these for the handler. */
1634 if (crtl->calls_eh_return)
1635 {
1636 unsigned int i;
1637
1638 for (i = 0; ; ++i)
1639 {
1640 regno = EH_RETURN_DATA_REGNO (i);
1641 if (regno == (int) INVALID_REGNUM)
1642 break;
1643 gp_reg_size += GET_MODE_SIZE (gpr_mode);
1644 mask |= 1L << (regno - GP_REG_FIRST);
1645 }
1646 }
1647
1648 gp_reg_rounded = IQ2000_STACK_ALIGN (gp_reg_size);
1649 total_size += gp_reg_rounded + IQ2000_STACK_ALIGN (fp_reg_size);
1650
1651 /* The gp reg is caller saved, so there is no need for leaf routines
1652 (total_size == extra_size) to save the gp reg. */
1653 if (total_size == extra_size
1654 && ! profile_flag)
1655 total_size = extra_size = 0;
1656
1657 total_size += IQ2000_STACK_ALIGN (crtl->args.pretend_args_size);
1658
1659 /* Save other computed information. */
1660 cfun->machine->total_size = total_size;
1661 cfun->machine->var_size = var_size;
1662 cfun->machine->args_size = args_size;
1663 cfun->machine->extra_size = extra_size;
1664 cfun->machine->gp_reg_size = gp_reg_size;
1665 cfun->machine->fp_reg_size = fp_reg_size;
1666 cfun->machine->mask = mask;
1667 cfun->machine->initialized = reload_completed;
1668 cfun->machine->num_gp = gp_reg_size / UNITS_PER_WORD;
1669
1670 if (mask)
1671 {
1672 unsigned long offset;
1673
1674 offset = (args_size + extra_size + var_size
1675 + gp_reg_size - GET_MODE_SIZE (gpr_mode));
1676
1677 cfun->machine->gp_sp_offset = offset;
1678 cfun->machine->gp_save_offset = offset - total_size;
1679 }
1680 else
1681 {
1682 cfun->machine->gp_sp_offset = 0;
1683 cfun->machine->gp_save_offset = 0;
1684 }
1685
1686 cfun->machine->fp_sp_offset = 0;
1687 cfun->machine->fp_save_offset = 0;
1688
1689 /* Ok, we're done. */
1690 return total_size;
1691 }
1692 \f
1693
1694 /* We can always eliminate to the frame pointer. We can eliminate to the
1695 stack pointer unless a frame pointer is needed. */
1696
1697 bool
1698 iq2000_can_eliminate (const int from, const int to)
1699 {
1700 return (from == RETURN_ADDRESS_POINTER_REGNUM
1701 && (! leaf_function_p ()
1702 || (to == GP_REG_FIRST + 31 && leaf_function_p ())))
1703 || (from != RETURN_ADDRESS_POINTER_REGNUM
1704 && (to == HARD_FRAME_POINTER_REGNUM
1705 || (to == STACK_POINTER_REGNUM
1706 && ! frame_pointer_needed)));
1707 }
1708
1709 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame
1710 pointer, argument pointer, or return address pointer. TO is either
1711 the stack pointer or hard frame pointer. */
1712
1713 int
1714 iq2000_initial_elimination_offset (int from, int to ATTRIBUTE_UNUSED)
1715 {
1716 int offset;
1717
1718 compute_frame_size (get_frame_size ());
1719 if ((from) == FRAME_POINTER_REGNUM)
1720 (offset) = 0;
1721 else if ((from) == ARG_POINTER_REGNUM)
1722 (offset) = (cfun->machine->total_size);
1723 else if ((from) == RETURN_ADDRESS_POINTER_REGNUM)
1724 {
1725 if (leaf_function_p ())
1726 (offset) = 0;
1727 else (offset) = cfun->machine->gp_sp_offset
1728 + ((UNITS_PER_WORD - (POINTER_SIZE / BITS_PER_UNIT))
1729 * (BYTES_BIG_ENDIAN != 0));
1730 }
1731 else
1732 gcc_unreachable ();
1733
1734 return offset;
1735 }
1736 \f
1737 /* Common code to emit the insns (or to write the instructions to a file)
1738 to save/restore registers.
1739 Other parts of the code assume that IQ2000_TEMP1_REGNUM (aka large_reg)
1740 is not modified within save_restore_insns. */
1741
1742 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
1743
1744 /* Emit instructions to load the value (SP + OFFSET) into IQ2000_TEMP2_REGNUM
1745 and return an rtl expression for the register. Write the assembly
1746 instructions directly to FILE if it is not null, otherwise emit them as
1747 rtl.
1748
1749 This function is a subroutine of save_restore_insns. It is used when
1750 OFFSET is too large to add in a single instruction. */
1751
1752 static rtx
1753 iq2000_add_large_offset_to_sp (HOST_WIDE_INT offset)
1754 {
1755 rtx reg = gen_rtx_REG (Pmode, IQ2000_TEMP2_REGNUM);
1756 rtx offset_rtx = GEN_INT (offset);
1757
1758 emit_move_insn (reg, offset_rtx);
1759 emit_insn (gen_addsi3 (reg, reg, stack_pointer_rtx));
1760 return reg;
1761 }
1762
1763 /* Make INSN frame related and note that it performs the frame-related
1764 operation DWARF_PATTERN. */
1765
1766 static void
1767 iq2000_annotate_frame_insn (rtx insn, rtx dwarf_pattern)
1768 {
1769 RTX_FRAME_RELATED_P (insn) = 1;
1770 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR,
1771 dwarf_pattern,
1772 REG_NOTES (insn));
1773 }
1774
1775 /* Emit a move instruction that stores REG in MEM. Make the instruction
1776 frame related and note that it stores REG at (SP + OFFSET). */
1777
1778 static void
1779 iq2000_emit_frame_related_store (rtx mem, rtx reg, HOST_WIDE_INT offset)
1780 {
1781 rtx dwarf_address = plus_constant (stack_pointer_rtx, offset);
1782 rtx dwarf_mem = gen_rtx_MEM (GET_MODE (reg), dwarf_address);
1783
1784 iq2000_annotate_frame_insn (emit_move_insn (mem, reg),
1785 gen_rtx_SET (GET_MODE (reg), dwarf_mem, reg));
1786 }
1787
1788 /* Emit instructions to save/restore registers, as determined by STORE_P. */
1789
1790 static void
1791 save_restore_insns (int store_p)
1792 {
1793 long mask = cfun->machine->mask;
1794 int regno;
1795 rtx base_reg_rtx;
1796 HOST_WIDE_INT base_offset;
1797 HOST_WIDE_INT gp_offset;
1798 HOST_WIDE_INT end_offset;
1799
1800 gcc_assert (!frame_pointer_needed
1801 || BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST));
1802
1803 if (mask == 0)
1804 {
1805 base_reg_rtx = 0, base_offset = 0;
1806 return;
1807 }
1808
1809 /* Save registers starting from high to low. The debuggers prefer at least
1810 the return register be stored at func+4, and also it allows us not to
1811 need a nop in the epilog if at least one register is reloaded in
1812 addition to return address. */
1813
1814 /* Save GP registers if needed. */
1815 /* Pick which pointer to use as a base register. For small frames, just
1816 use the stack pointer. Otherwise, use a temporary register. Save 2
1817 cycles if the save area is near the end of a large frame, by reusing
1818 the constant created in the prologue/epilogue to adjust the stack
1819 frame. */
1820
1821 gp_offset = cfun->machine->gp_sp_offset;
1822 end_offset
1823 = gp_offset - (cfun->machine->gp_reg_size
1824 - GET_MODE_SIZE (gpr_mode));
1825
1826 if (gp_offset < 0 || end_offset < 0)
1827 internal_error
1828 ("gp_offset (%ld) or end_offset (%ld) is less than zero",
1829 (long) gp_offset, (long) end_offset);
1830
1831 else if (gp_offset < 32768)
1832 base_reg_rtx = stack_pointer_rtx, base_offset = 0;
1833 else
1834 {
1835 int regno;
1836 int reg_save_count = 0;
1837
1838 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
1839 if (BITSET_P (mask, regno - GP_REG_FIRST)) reg_save_count += 1;
1840 base_offset = gp_offset - ((reg_save_count - 1) * 4);
1841 base_reg_rtx = iq2000_add_large_offset_to_sp (base_offset);
1842 }
1843
1844 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
1845 {
1846 if (BITSET_P (mask, regno - GP_REG_FIRST))
1847 {
1848 rtx reg_rtx;
1849 rtx mem_rtx
1850 = gen_rtx_MEM (gpr_mode,
1851 gen_rtx_PLUS (Pmode, base_reg_rtx,
1852 GEN_INT (gp_offset - base_offset)));
1853
1854 reg_rtx = gen_rtx_REG (gpr_mode, regno);
1855
1856 if (store_p)
1857 iq2000_emit_frame_related_store (mem_rtx, reg_rtx, gp_offset);
1858 else
1859 {
1860 emit_move_insn (reg_rtx, mem_rtx);
1861 }
1862 gp_offset -= GET_MODE_SIZE (gpr_mode);
1863 }
1864 }
1865 }
1866 \f
1867 /* Expand the prologue into a bunch of separate insns. */
1868
1869 void
1870 iq2000_expand_prologue (void)
1871 {
1872 int regno;
1873 HOST_WIDE_INT tsize;
1874 int last_arg_is_vararg_marker = 0;
1875 tree fndecl = current_function_decl;
1876 tree fntype = TREE_TYPE (fndecl);
1877 tree fnargs = DECL_ARGUMENTS (fndecl);
1878 rtx next_arg_reg;
1879 int i;
1880 tree next_arg;
1881 tree cur_arg;
1882 CUMULATIVE_ARGS args_so_far;
1883 int store_args_on_stack = (iq2000_can_use_return_insn ());
1884
1885 /* If struct value address is treated as the first argument. */
1886 if (aggregate_value_p (DECL_RESULT (fndecl), fndecl)
1887 && !cfun->returns_pcc_struct
1888 && targetm.calls.struct_value_rtx (TREE_TYPE (fndecl), 1) == 0)
1889 {
1890 tree type = build_pointer_type (fntype);
1891 tree function_result_decl = build_decl (BUILTINS_LOCATION,
1892 PARM_DECL, NULL_TREE, type);
1893
1894 DECL_ARG_TYPE (function_result_decl) = type;
1895 DECL_CHAIN (function_result_decl) = fnargs;
1896 fnargs = function_result_decl;
1897 }
1898
1899 /* For arguments passed in registers, find the register number
1900 of the first argument in the variable part of the argument list,
1901 otherwise GP_ARG_LAST+1. Note also if the last argument is
1902 the varargs special argument, and treat it as part of the
1903 variable arguments.
1904
1905 This is only needed if store_args_on_stack is true. */
1906 INIT_CUMULATIVE_ARGS (args_so_far, fntype, NULL_RTX, 0, 0);
1907 regno = GP_ARG_FIRST;
1908
1909 for (cur_arg = fnargs; cur_arg != 0; cur_arg = next_arg)
1910 {
1911 tree passed_type = DECL_ARG_TYPE (cur_arg);
1912 enum machine_mode passed_mode = TYPE_MODE (passed_type);
1913 rtx entry_parm;
1914
1915 if (TREE_ADDRESSABLE (passed_type))
1916 {
1917 passed_type = build_pointer_type (passed_type);
1918 passed_mode = Pmode;
1919 }
1920
1921 entry_parm = iq2000_function_arg (&args_so_far, passed_mode,
1922 passed_type, true);
1923
1924 iq2000_function_arg_advance (&args_so_far, passed_mode,
1925 passed_type, true);
1926 next_arg = DECL_CHAIN (cur_arg);
1927
1928 if (entry_parm && store_args_on_stack)
1929 {
1930 if (next_arg == 0
1931 && DECL_NAME (cur_arg)
1932 && ((0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
1933 "__builtin_va_alist"))
1934 || (0 == strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg)),
1935 "va_alist"))))
1936 {
1937 last_arg_is_vararg_marker = 1;
1938 break;
1939 }
1940 else
1941 {
1942 int words;
1943
1944 gcc_assert (GET_CODE (entry_parm) == REG);
1945
1946 /* Passed in a register, so will get homed automatically. */
1947 if (GET_MODE (entry_parm) == BLKmode)
1948 words = (int_size_in_bytes (passed_type) + 3) / 4;
1949 else
1950 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
1951
1952 regno = REGNO (entry_parm) + words - 1;
1953 }
1954 }
1955 else
1956 {
1957 regno = GP_ARG_LAST+1;
1958 break;
1959 }
1960 }
1961
1962 /* In order to pass small structures by value in registers we need to
1963 shift the value into the high part of the register.
1964 iq2000_unction_arg has encoded a PARALLEL rtx, holding a vector of
1965 adjustments to be made as the next_arg_reg variable, so we split up
1966 the insns, and emit them separately. */
1967 next_arg_reg = iq2000_function_arg (&args_so_far, VOIDmode,
1968 void_type_node, true);
1969 if (next_arg_reg != 0 && GET_CODE (next_arg_reg) == PARALLEL)
1970 {
1971 rtvec adjust = XVEC (next_arg_reg, 0);
1972 int num = GET_NUM_ELEM (adjust);
1973
1974 for (i = 0; i < num; i++)
1975 {
1976 rtx pattern;
1977
1978 pattern = RTVEC_ELT (adjust, i);
1979 if (GET_CODE (pattern) != SET
1980 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
1981 abort_with_insn (pattern, "Insn is not a shift");
1982 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
1983
1984 emit_insn (pattern);
1985 }
1986 }
1987
1988 tsize = compute_frame_size (get_frame_size ());
1989
1990 /* If this function is a varargs function, store any registers that
1991 would normally hold arguments ($4 - $7) on the stack. */
1992 if (store_args_on_stack
1993 && (stdarg_p (fntype)
1994 || last_arg_is_vararg_marker))
1995 {
1996 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
1997 rtx ptr = stack_pointer_rtx;
1998
1999 for (; regno <= GP_ARG_LAST; regno++)
2000 {
2001 if (offset != 0)
2002 ptr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset));
2003 emit_move_insn (gen_rtx_MEM (gpr_mode, ptr),
2004 gen_rtx_REG (gpr_mode, regno));
2005
2006 offset += GET_MODE_SIZE (gpr_mode);
2007 }
2008 }
2009
2010 if (tsize > 0)
2011 {
2012 rtx tsize_rtx = GEN_INT (tsize);
2013 rtx adjustment_rtx, insn, dwarf_pattern;
2014
2015 if (tsize > 32767)
2016 {
2017 adjustment_rtx = gen_rtx_REG (Pmode, IQ2000_TEMP1_REGNUM);
2018 emit_move_insn (adjustment_rtx, tsize_rtx);
2019 }
2020 else
2021 adjustment_rtx = tsize_rtx;
2022
2023 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
2024 adjustment_rtx));
2025
2026 dwarf_pattern = gen_rtx_SET (Pmode, stack_pointer_rtx,
2027 plus_constant (stack_pointer_rtx, -tsize));
2028
2029 iq2000_annotate_frame_insn (insn, dwarf_pattern);
2030
2031 save_restore_insns (1);
2032
2033 if (frame_pointer_needed)
2034 {
2035 rtx insn = 0;
2036
2037 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx,
2038 stack_pointer_rtx));
2039
2040 if (insn)
2041 RTX_FRAME_RELATED_P (insn) = 1;
2042 }
2043 }
2044
2045 emit_insn (gen_blockage ());
2046 }
2047 \f
2048 /* Expand the epilogue into a bunch of separate insns. */
2049
2050 void
2051 iq2000_expand_epilogue (void)
2052 {
2053 HOST_WIDE_INT tsize = cfun->machine->total_size;
2054 rtx tsize_rtx = GEN_INT (tsize);
2055 rtx tmp_rtx = (rtx)0;
2056
2057 if (iq2000_can_use_return_insn ())
2058 {
2059 emit_jump_insn (gen_return ());
2060 return;
2061 }
2062
2063 if (tsize > 32767)
2064 {
2065 tmp_rtx = gen_rtx_REG (Pmode, IQ2000_TEMP1_REGNUM);
2066 emit_move_insn (tmp_rtx, tsize_rtx);
2067 tsize_rtx = tmp_rtx;
2068 }
2069
2070 if (tsize > 0)
2071 {
2072 if (frame_pointer_needed)
2073 {
2074 emit_insn (gen_blockage ());
2075
2076 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
2077 }
2078
2079 save_restore_insns (0);
2080
2081 if (crtl->calls_eh_return)
2082 {
2083 rtx eh_ofs = EH_RETURN_STACKADJ_RTX;
2084 emit_insn (gen_addsi3 (eh_ofs, eh_ofs, tsize_rtx));
2085 tsize_rtx = eh_ofs;
2086 }
2087
2088 emit_insn (gen_blockage ());
2089
2090 if (tsize != 0 || crtl->calls_eh_return)
2091 {
2092 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
2093 tsize_rtx));
2094 }
2095 }
2096
2097 if (crtl->calls_eh_return)
2098 {
2099 /* Perform the additional bump for __throw. */
2100 emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
2101 stack_pointer_rtx);
2102 emit_use (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM));
2103 emit_jump_insn (gen_eh_return_internal ());
2104 }
2105 else
2106 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode,
2107 GP_REG_FIRST + 31)));
2108 }
2109
2110 void
2111 iq2000_expand_eh_return (rtx address)
2112 {
2113 HOST_WIDE_INT gp_offset = cfun->machine->gp_sp_offset;
2114 rtx scratch;
2115
2116 scratch = plus_constant (stack_pointer_rtx, gp_offset);
2117 emit_move_insn (gen_rtx_MEM (GET_MODE (address), scratch), address);
2118 }
2119 \f
2120 /* Return nonzero if this function is known to have a null epilogue.
2121 This allows the optimizer to omit jumps to jumps if no stack
2122 was created. */
2123
2124 int
2125 iq2000_can_use_return_insn (void)
2126 {
2127 if (! reload_completed)
2128 return 0;
2129
2130 if (df_regs_ever_live_p (31) || profile_flag)
2131 return 0;
2132
2133 if (cfun->machine->initialized)
2134 return cfun->machine->total_size == 0;
2135
2136 return compute_frame_size (get_frame_size ()) == 0;
2137 }
2138 \f
2139 /* Choose the section to use for the constant rtx expression X that has
2140 mode MODE. */
2141
2142 static section *
2143 iq2000_select_rtx_section (enum machine_mode mode, rtx x ATTRIBUTE_UNUSED,
2144 unsigned HOST_WIDE_INT align)
2145 {
2146 /* For embedded applications, always put constants in read-only data,
2147 in order to reduce RAM usage. */
2148 return mergeable_constant_section (mode, align, 0);
2149 }
2150
2151 /* Choose the section to use for DECL. RELOC is true if its value contains
2152 any relocatable expression.
2153
2154 Some of the logic used here needs to be replicated in
2155 ENCODE_SECTION_INFO in iq2000.h so that references to these symbols
2156 are done correctly. */
2157
2158 static section *
2159 iq2000_select_section (tree decl, int reloc ATTRIBUTE_UNUSED,
2160 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
2161 {
2162 if (TARGET_EMBEDDED_DATA)
2163 {
2164 /* For embedded applications, always put an object in read-only data
2165 if possible, in order to reduce RAM usage. */
2166 if ((TREE_CODE (decl) == VAR_DECL
2167 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
2168 && DECL_INITIAL (decl)
2169 && (DECL_INITIAL (decl) == error_mark_node
2170 || TREE_CONSTANT (DECL_INITIAL (decl))))
2171 /* Deal with calls from output_constant_def_contents. */
2172 || TREE_CODE (decl) != VAR_DECL)
2173 return readonly_data_section;
2174 else
2175 return data_section;
2176 }
2177 else
2178 {
2179 /* For hosted applications, always put an object in small data if
2180 possible, as this gives the best performance. */
2181 if ((TREE_CODE (decl) == VAR_DECL
2182 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
2183 && DECL_INITIAL (decl)
2184 && (DECL_INITIAL (decl) == error_mark_node
2185 || TREE_CONSTANT (DECL_INITIAL (decl))))
2186 /* Deal with calls from output_constant_def_contents. */
2187 || TREE_CODE (decl) != VAR_DECL)
2188 return readonly_data_section;
2189 else
2190 return data_section;
2191 }
2192 }
2193 /* Return register to use for a function return value with VALTYPE for function
2194 FUNC. */
2195
2196 static rtx
2197 iq2000_function_value (const_tree valtype,
2198 const_tree fn_decl_or_type,
2199 bool outgoing ATTRIBUTE_UNUSED)
2200 {
2201 int reg = GP_RETURN;
2202 enum machine_mode mode = TYPE_MODE (valtype);
2203 int unsignedp = TYPE_UNSIGNED (valtype);
2204 const_tree func = fn_decl_or_type;
2205
2206 if (fn_decl_or_type
2207 && !DECL_P (fn_decl_or_type))
2208 fn_decl_or_type = NULL;
2209
2210 /* Since we promote return types, we must promote the mode here too. */
2211 mode = promote_function_mode (valtype, mode, &unsignedp, func, 1);
2212
2213 return gen_rtx_REG (mode, reg);
2214 }
2215
2216 /* Worker function for TARGET_LIBCALL_VALUE. */
2217
2218 static rtx
2219 iq2000_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
2220 {
2221 return gen_rtx_REG (((GET_MODE_CLASS (mode) != MODE_INT
2222 || GET_MODE_SIZE (mode) >= 4)
2223 ? mode : SImode),
2224 GP_RETURN);
2225 }
2226
2227 /* Worker function for FUNCTION_VALUE_REGNO_P.
2228
2229 On the IQ2000, R2 and R3 are the only register thus used. */
2230
2231 bool
2232 iq2000_function_value_regno_p (const unsigned int regno)
2233 {
2234 return (regno == GP_RETURN);
2235 }
2236
2237 \f
2238 /* Return true when an argument must be passed by reference. */
2239
2240 static bool
2241 iq2000_pass_by_reference (CUMULATIVE_ARGS *cum, enum machine_mode mode,
2242 const_tree type, bool named ATTRIBUTE_UNUSED)
2243 {
2244 int size;
2245
2246 /* We must pass by reference if we would be both passing in registers
2247 and the stack. This is because any subsequent partial arg would be
2248 handled incorrectly in this case. */
2249 if (cum && targetm.calls.must_pass_in_stack (mode, type))
2250 {
2251 /* Don't pass the actual CUM to FUNCTION_ARG, because we would
2252 get double copies of any offsets generated for small structs
2253 passed in registers. */
2254 CUMULATIVE_ARGS temp;
2255
2256 temp = *cum;
2257 if (iq2000_function_arg (&temp, mode, type, named) != 0)
2258 return 1;
2259 }
2260
2261 if (type == NULL_TREE || mode == DImode || mode == DFmode)
2262 return 0;
2263
2264 size = int_size_in_bytes (type);
2265 return size == -1 || size > UNITS_PER_WORD;
2266 }
2267
2268 /* Return the length of INSN. LENGTH is the initial length computed by
2269 attributes in the machine-description file. */
2270
2271 int
2272 iq2000_adjust_insn_length (rtx insn, int length)
2273 {
2274 /* A unconditional jump has an unfilled delay slot if it is not part
2275 of a sequence. A conditional jump normally has a delay slot. */
2276 if (simplejump_p (insn)
2277 || ( (GET_CODE (insn) == JUMP_INSN
2278 || GET_CODE (insn) == CALL_INSN)))
2279 length += 4;
2280
2281 return length;
2282 }
2283
2284 /* Output assembly instructions to perform a conditional branch.
2285
2286 INSN is the branch instruction. OPERANDS[0] is the condition.
2287 OPERANDS[1] is the target of the branch. OPERANDS[2] is the target
2288 of the first operand to the condition. If TWO_OPERANDS_P is
2289 nonzero the comparison takes two operands; OPERANDS[3] will be the
2290 second operand.
2291
2292 If INVERTED_P is nonzero we are to branch if the condition does
2293 not hold. If FLOAT_P is nonzero this is a floating-point comparison.
2294
2295 LENGTH is the length (in bytes) of the sequence we are to generate.
2296 That tells us whether to generate a simple conditional branch, or a
2297 reversed conditional branch around a `jr' instruction. */
2298
2299 char *
2300 iq2000_output_conditional_branch (rtx insn, rtx * operands, int two_operands_p,
2301 int float_p, int inverted_p, int length)
2302 {
2303 static char buffer[200];
2304 /* The kind of comparison we are doing. */
2305 enum rtx_code code = GET_CODE (operands[0]);
2306 /* Nonzero if the opcode for the comparison needs a `z' indicating
2307 that it is a comparison against zero. */
2308 int need_z_p;
2309 /* A string to use in the assembly output to represent the first
2310 operand. */
2311 const char *op1 = "%z2";
2312 /* A string to use in the assembly output to represent the second
2313 operand. Use the hard-wired zero register if there's no second
2314 operand. */
2315 const char *op2 = (two_operands_p ? ",%z3" : ",%.");
2316 /* The operand-printing string for the comparison. */
2317 const char *comp = (float_p ? "%F0" : "%C0");
2318 /* The operand-printing string for the inverted comparison. */
2319 const char *inverted_comp = (float_p ? "%W0" : "%N0");
2320
2321 /* Likely variants of each branch instruction annul the instruction
2322 in the delay slot if the branch is not taken. */
2323 iq2000_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
2324
2325 if (!two_operands_p)
2326 {
2327 /* To compute whether than A > B, for example, we normally
2328 subtract B from A and then look at the sign bit. But, if we
2329 are doing an unsigned comparison, and B is zero, we don't
2330 have to do the subtraction. Instead, we can just check to
2331 see if A is nonzero. Thus, we change the CODE here to
2332 reflect the simpler comparison operation. */
2333 switch (code)
2334 {
2335 case GTU:
2336 code = NE;
2337 break;
2338
2339 case LEU:
2340 code = EQ;
2341 break;
2342
2343 case GEU:
2344 /* A condition which will always be true. */
2345 code = EQ;
2346 op1 = "%.";
2347 break;
2348
2349 case LTU:
2350 /* A condition which will always be false. */
2351 code = NE;
2352 op1 = "%.";
2353 break;
2354
2355 default:
2356 /* Not a special case. */
2357 break;
2358 }
2359 }
2360
2361 /* Relative comparisons are always done against zero. But
2362 equality comparisons are done between two operands, and therefore
2363 do not require a `z' in the assembly language output. */
2364 need_z_p = (!float_p && code != EQ && code != NE);
2365 /* For comparisons against zero, the zero is not provided
2366 explicitly. */
2367 if (need_z_p)
2368 op2 = "";
2369
2370 /* Begin by terminating the buffer. That way we can always use
2371 strcat to add to it. */
2372 buffer[0] = '\0';
2373
2374 switch (length)
2375 {
2376 case 4:
2377 case 8:
2378 /* Just a simple conditional branch. */
2379 if (float_p)
2380 sprintf (buffer, "b%s%%?\t%%Z2%%1",
2381 inverted_p ? inverted_comp : comp);
2382 else
2383 sprintf (buffer, "b%s%s%%?\t%s%s,%%1",
2384 inverted_p ? inverted_comp : comp,
2385 need_z_p ? "z" : "",
2386 op1,
2387 op2);
2388 return buffer;
2389
2390 case 12:
2391 case 16:
2392 {
2393 /* Generate a reversed conditional branch around ` j'
2394 instruction:
2395
2396 .set noreorder
2397 .set nomacro
2398 bc l
2399 nop
2400 j target
2401 .set macro
2402 .set reorder
2403 l:
2404
2405 Because we have to jump four bytes *past* the following
2406 instruction if this branch was annulled, we can't just use
2407 a label, as in the picture above; there's no way to put the
2408 label after the next instruction, as the assembler does not
2409 accept `.L+4' as the target of a branch. (We can't just
2410 wait until the next instruction is output; it might be a
2411 macro and take up more than four bytes. Once again, we see
2412 why we want to eliminate macros.)
2413
2414 If the branch is annulled, we jump four more bytes that we
2415 would otherwise; that way we skip the annulled instruction
2416 in the delay slot. */
2417
2418 const char *target
2419 = ((iq2000_branch_likely || length == 16) ? ".+16" : ".+12");
2420 char *c;
2421
2422 c = strchr (buffer, '\0');
2423 /* Generate the reversed comparison. This takes four
2424 bytes. */
2425 if (float_p)
2426 sprintf (c, "b%s\t%%Z2%s",
2427 inverted_p ? comp : inverted_comp,
2428 target);
2429 else
2430 sprintf (c, "b%s%s\t%s%s,%s",
2431 inverted_p ? comp : inverted_comp,
2432 need_z_p ? "z" : "",
2433 op1,
2434 op2,
2435 target);
2436 strcat (c, "\n\tnop\n\tj\t%1");
2437 if (length == 16)
2438 /* The delay slot was unfilled. Since we're inside
2439 .noreorder, the assembler will not fill in the NOP for
2440 us, so we must do it ourselves. */
2441 strcat (buffer, "\n\tnop");
2442 return buffer;
2443 }
2444
2445 default:
2446 gcc_unreachable ();
2447 }
2448
2449 /* NOTREACHED */
2450 return 0;
2451 }
2452
2453 #define def_builtin(NAME, TYPE, CODE) \
2454 add_builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
2455 NULL, NULL_TREE)
2456
2457 static void
2458 iq2000_init_builtins (void)
2459 {
2460 tree void_ftype, void_ftype_int, void_ftype_int_int;
2461 tree void_ftype_int_int_int;
2462 tree int_ftype_int, int_ftype_int_int, int_ftype_int_int_int;
2463 tree int_ftype_int_int_int_int;
2464
2465 /* func () */
2466 void_ftype
2467 = build_function_type_list (void_type_node, NULL_TREE);
2468
2469 /* func (int) */
2470 void_ftype_int
2471 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
2472
2473 /* void func (int, int) */
2474 void_ftype_int_int
2475 = build_function_type_list (void_type_node,
2476 integer_type_node,
2477 integer_type_node,
2478 NULL_TREE);
2479
2480 /* int func (int) */
2481 int_ftype_int
2482 = build_function_type_list (integer_type_node,
2483 integer_type_node, NULL_TREE);
2484
2485 /* int func (int, int) */
2486 int_ftype_int_int
2487 = build_function_type_list (integer_type_node,
2488 integer_type_node,
2489 integer_type_node,
2490 NULL_TREE);
2491
2492 /* void func (int, int, int) */
2493 void_ftype_int_int_int
2494 = build_function_type_list (void_type_node,
2495 integer_type_node,
2496 integer_type_node,
2497 integer_type_node,
2498 NULL_TREE);
2499
2500 /* int func (int, int, int) */
2501 int_ftype_int_int_int
2502 = build_function_type_list (integer_type_node,
2503 integer_type_node,
2504 integer_type_node,
2505 integer_type_node,
2506 NULL_TREE);
2507
2508 /* int func (int, int, int, int) */
2509 int_ftype_int_int_int_int
2510 = build_function_type_list (integer_type_node,
2511 integer_type_node,
2512 integer_type_node,
2513 integer_type_node,
2514 integer_type_node,
2515 NULL_TREE);
2516
2517 def_builtin ("__builtin_ado16", int_ftype_int_int, IQ2000_BUILTIN_ADO16);
2518 def_builtin ("__builtin_ram", int_ftype_int_int_int_int, IQ2000_BUILTIN_RAM);
2519 def_builtin ("__builtin_chkhdr", void_ftype_int_int, IQ2000_BUILTIN_CHKHDR);
2520 def_builtin ("__builtin_pkrl", void_ftype_int_int, IQ2000_BUILTIN_PKRL);
2521 def_builtin ("__builtin_cfc0", int_ftype_int, IQ2000_BUILTIN_CFC0);
2522 def_builtin ("__builtin_cfc1", int_ftype_int, IQ2000_BUILTIN_CFC1);
2523 def_builtin ("__builtin_cfc2", int_ftype_int, IQ2000_BUILTIN_CFC2);
2524 def_builtin ("__builtin_cfc3", int_ftype_int, IQ2000_BUILTIN_CFC3);
2525 def_builtin ("__builtin_ctc0", void_ftype_int_int, IQ2000_BUILTIN_CTC0);
2526 def_builtin ("__builtin_ctc1", void_ftype_int_int, IQ2000_BUILTIN_CTC1);
2527 def_builtin ("__builtin_ctc2", void_ftype_int_int, IQ2000_BUILTIN_CTC2);
2528 def_builtin ("__builtin_ctc3", void_ftype_int_int, IQ2000_BUILTIN_CTC3);
2529 def_builtin ("__builtin_mfc0", int_ftype_int, IQ2000_BUILTIN_MFC0);
2530 def_builtin ("__builtin_mfc1", int_ftype_int, IQ2000_BUILTIN_MFC1);
2531 def_builtin ("__builtin_mfc2", int_ftype_int, IQ2000_BUILTIN_MFC2);
2532 def_builtin ("__builtin_mfc3", int_ftype_int, IQ2000_BUILTIN_MFC3);
2533 def_builtin ("__builtin_mtc0", void_ftype_int_int, IQ2000_BUILTIN_MTC0);
2534 def_builtin ("__builtin_mtc1", void_ftype_int_int, IQ2000_BUILTIN_MTC1);
2535 def_builtin ("__builtin_mtc2", void_ftype_int_int, IQ2000_BUILTIN_MTC2);
2536 def_builtin ("__builtin_mtc3", void_ftype_int_int, IQ2000_BUILTIN_MTC3);
2537 def_builtin ("__builtin_lur", void_ftype_int_int, IQ2000_BUILTIN_LUR);
2538 def_builtin ("__builtin_rb", void_ftype_int_int, IQ2000_BUILTIN_RB);
2539 def_builtin ("__builtin_rx", void_ftype_int_int, IQ2000_BUILTIN_RX);
2540 def_builtin ("__builtin_srrd", void_ftype_int, IQ2000_BUILTIN_SRRD);
2541 def_builtin ("__builtin_srwr", void_ftype_int_int, IQ2000_BUILTIN_SRWR);
2542 def_builtin ("__builtin_wb", void_ftype_int_int, IQ2000_BUILTIN_WB);
2543 def_builtin ("__builtin_wx", void_ftype_int_int, IQ2000_BUILTIN_WX);
2544 def_builtin ("__builtin_luc32l", void_ftype_int_int, IQ2000_BUILTIN_LUC32L);
2545 def_builtin ("__builtin_luc64", void_ftype_int_int, IQ2000_BUILTIN_LUC64);
2546 def_builtin ("__builtin_luc64l", void_ftype_int_int, IQ2000_BUILTIN_LUC64L);
2547 def_builtin ("__builtin_luk", void_ftype_int_int, IQ2000_BUILTIN_LUK);
2548 def_builtin ("__builtin_lulck", void_ftype_int, IQ2000_BUILTIN_LULCK);
2549 def_builtin ("__builtin_lum32", void_ftype_int_int, IQ2000_BUILTIN_LUM32);
2550 def_builtin ("__builtin_lum32l", void_ftype_int_int, IQ2000_BUILTIN_LUM32L);
2551 def_builtin ("__builtin_lum64", void_ftype_int_int, IQ2000_BUILTIN_LUM64);
2552 def_builtin ("__builtin_lum64l", void_ftype_int_int, IQ2000_BUILTIN_LUM64L);
2553 def_builtin ("__builtin_lurl", void_ftype_int_int, IQ2000_BUILTIN_LURL);
2554 def_builtin ("__builtin_mrgb", int_ftype_int_int_int, IQ2000_BUILTIN_MRGB);
2555 def_builtin ("__builtin_srrdl", void_ftype_int, IQ2000_BUILTIN_SRRDL);
2556 def_builtin ("__builtin_srulck", void_ftype_int, IQ2000_BUILTIN_SRULCK);
2557 def_builtin ("__builtin_srwru", void_ftype_int_int, IQ2000_BUILTIN_SRWRU);
2558 def_builtin ("__builtin_trapqfl", void_ftype, IQ2000_BUILTIN_TRAPQFL);
2559 def_builtin ("__builtin_trapqne", void_ftype, IQ2000_BUILTIN_TRAPQNE);
2560 def_builtin ("__builtin_traprel", void_ftype_int, IQ2000_BUILTIN_TRAPREL);
2561 def_builtin ("__builtin_wbu", void_ftype_int_int_int, IQ2000_BUILTIN_WBU);
2562 def_builtin ("__builtin_syscall", void_ftype, IQ2000_BUILTIN_SYSCALL);
2563 }
2564
2565 /* Builtin for ICODE having ARGCOUNT args in EXP where each arg
2566 has an rtx CODE. */
2567
2568 static rtx
2569 expand_one_builtin (enum insn_code icode, rtx target, tree exp,
2570 enum rtx_code *code, int argcount)
2571 {
2572 rtx pat;
2573 tree arg [5];
2574 rtx op [5];
2575 enum machine_mode mode [5];
2576 int i;
2577
2578 mode[0] = insn_data[icode].operand[0].mode;
2579 for (i = 0; i < argcount; i++)
2580 {
2581 arg[i] = CALL_EXPR_ARG (exp, i);
2582 op[i] = expand_normal (arg[i]);
2583 mode[i] = insn_data[icode].operand[i].mode;
2584 if (code[i] == CONST_INT && GET_CODE (op[i]) != CONST_INT)
2585 error ("argument %qd is not a constant", i + 1);
2586 if (code[i] == REG
2587 && ! (*insn_data[icode].operand[i].predicate) (op[i], mode[i]))
2588 op[i] = copy_to_mode_reg (mode[i], op[i]);
2589 }
2590
2591 if (insn_data[icode].operand[0].constraint[0] == '=')
2592 {
2593 if (target == 0
2594 || GET_MODE (target) != mode[0]
2595 || ! (*insn_data[icode].operand[0].predicate) (target, mode[0]))
2596 target = gen_reg_rtx (mode[0]);
2597 }
2598 else
2599 target = 0;
2600
2601 switch (argcount)
2602 {
2603 case 0:
2604 pat = GEN_FCN (icode) (target);
2605 case 1:
2606 if (target)
2607 pat = GEN_FCN (icode) (target, op[0]);
2608 else
2609 pat = GEN_FCN (icode) (op[0]);
2610 break;
2611 case 2:
2612 if (target)
2613 pat = GEN_FCN (icode) (target, op[0], op[1]);
2614 else
2615 pat = GEN_FCN (icode) (op[0], op[1]);
2616 break;
2617 case 3:
2618 if (target)
2619 pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
2620 else
2621 pat = GEN_FCN (icode) (op[0], op[1], op[2]);
2622 break;
2623 case 4:
2624 if (target)
2625 pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
2626 else
2627 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
2628 break;
2629 default:
2630 gcc_unreachable ();
2631 }
2632
2633 if (! pat)
2634 return 0;
2635 emit_insn (pat);
2636 return target;
2637 }
2638
2639 /* Expand an expression EXP that calls a built-in function,
2640 with result going to TARGET if that's convenient
2641 (and in mode MODE if that's convenient).
2642 SUBTARGET may be used as the target for computing one of EXP's operands.
2643 IGNORE is nonzero if the value is to be ignored. */
2644
2645 static rtx
2646 iq2000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
2647 enum machine_mode mode ATTRIBUTE_UNUSED,
2648 int ignore ATTRIBUTE_UNUSED)
2649 {
2650 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
2651 int fcode = DECL_FUNCTION_CODE (fndecl);
2652 enum rtx_code code [5];
2653
2654 code[0] = REG;
2655 code[1] = REG;
2656 code[2] = REG;
2657 code[3] = REG;
2658 code[4] = REG;
2659 switch (fcode)
2660 {
2661 default:
2662 break;
2663
2664 case IQ2000_BUILTIN_ADO16:
2665 return expand_one_builtin (CODE_FOR_ado16, target, exp, code, 2);
2666
2667 case IQ2000_BUILTIN_RAM:
2668 code[1] = CONST_INT;
2669 code[2] = CONST_INT;
2670 code[3] = CONST_INT;
2671 return expand_one_builtin (CODE_FOR_ram, target, exp, code, 4);
2672
2673 case IQ2000_BUILTIN_CHKHDR:
2674 return expand_one_builtin (CODE_FOR_chkhdr, target, exp, code, 2);
2675
2676 case IQ2000_BUILTIN_PKRL:
2677 return expand_one_builtin (CODE_FOR_pkrl, target, exp, code, 2);
2678
2679 case IQ2000_BUILTIN_CFC0:
2680 code[0] = CONST_INT;
2681 return expand_one_builtin (CODE_FOR_cfc0, target, exp, code, 1);
2682
2683 case IQ2000_BUILTIN_CFC1:
2684 code[0] = CONST_INT;
2685 return expand_one_builtin (CODE_FOR_cfc1, target, exp, code, 1);
2686
2687 case IQ2000_BUILTIN_CFC2:
2688 code[0] = CONST_INT;
2689 return expand_one_builtin (CODE_FOR_cfc2, target, exp, code, 1);
2690
2691 case IQ2000_BUILTIN_CFC3:
2692 code[0] = CONST_INT;
2693 return expand_one_builtin (CODE_FOR_cfc3, target, exp, code, 1);
2694
2695 case IQ2000_BUILTIN_CTC0:
2696 code[1] = CONST_INT;
2697 return expand_one_builtin (CODE_FOR_ctc0, target, exp, code, 2);
2698
2699 case IQ2000_BUILTIN_CTC1:
2700 code[1] = CONST_INT;
2701 return expand_one_builtin (CODE_FOR_ctc1, target, exp, code, 2);
2702
2703 case IQ2000_BUILTIN_CTC2:
2704 code[1] = CONST_INT;
2705 return expand_one_builtin (CODE_FOR_ctc2, target, exp, code, 2);
2706
2707 case IQ2000_BUILTIN_CTC3:
2708 code[1] = CONST_INT;
2709 return expand_one_builtin (CODE_FOR_ctc3, target, exp, code, 2);
2710
2711 case IQ2000_BUILTIN_MFC0:
2712 code[0] = CONST_INT;
2713 return expand_one_builtin (CODE_FOR_mfc0, target, exp, code, 1);
2714
2715 case IQ2000_BUILTIN_MFC1:
2716 code[0] = CONST_INT;
2717 return expand_one_builtin (CODE_FOR_mfc1, target, exp, code, 1);
2718
2719 case IQ2000_BUILTIN_MFC2:
2720 code[0] = CONST_INT;
2721 return expand_one_builtin (CODE_FOR_mfc2, target, exp, code, 1);
2722
2723 case IQ2000_BUILTIN_MFC3:
2724 code[0] = CONST_INT;
2725 return expand_one_builtin (CODE_FOR_mfc3, target, exp, code, 1);
2726
2727 case IQ2000_BUILTIN_MTC0:
2728 code[1] = CONST_INT;
2729 return expand_one_builtin (CODE_FOR_mtc0, target, exp, code, 2);
2730
2731 case IQ2000_BUILTIN_MTC1:
2732 code[1] = CONST_INT;
2733 return expand_one_builtin (CODE_FOR_mtc1, target, exp, code, 2);
2734
2735 case IQ2000_BUILTIN_MTC2:
2736 code[1] = CONST_INT;
2737 return expand_one_builtin (CODE_FOR_mtc2, target, exp, code, 2);
2738
2739 case IQ2000_BUILTIN_MTC3:
2740 code[1] = CONST_INT;
2741 return expand_one_builtin (CODE_FOR_mtc3, target, exp, code, 2);
2742
2743 case IQ2000_BUILTIN_LUR:
2744 return expand_one_builtin (CODE_FOR_lur, target, exp, code, 2);
2745
2746 case IQ2000_BUILTIN_RB:
2747 return expand_one_builtin (CODE_FOR_rb, target, exp, code, 2);
2748
2749 case IQ2000_BUILTIN_RX:
2750 return expand_one_builtin (CODE_FOR_rx, target, exp, code, 2);
2751
2752 case IQ2000_BUILTIN_SRRD:
2753 return expand_one_builtin (CODE_FOR_srrd, target, exp, code, 1);
2754
2755 case IQ2000_BUILTIN_SRWR:
2756 return expand_one_builtin (CODE_FOR_srwr, target, exp, code, 2);
2757
2758 case IQ2000_BUILTIN_WB:
2759 return expand_one_builtin (CODE_FOR_wb, target, exp, code, 2);
2760
2761 case IQ2000_BUILTIN_WX:
2762 return expand_one_builtin (CODE_FOR_wx, target, exp, code, 2);
2763
2764 case IQ2000_BUILTIN_LUC32L:
2765 return expand_one_builtin (CODE_FOR_luc32l, target, exp, code, 2);
2766
2767 case IQ2000_BUILTIN_LUC64:
2768 return expand_one_builtin (CODE_FOR_luc64, target, exp, code, 2);
2769
2770 case IQ2000_BUILTIN_LUC64L:
2771 return expand_one_builtin (CODE_FOR_luc64l, target, exp, code, 2);
2772
2773 case IQ2000_BUILTIN_LUK:
2774 return expand_one_builtin (CODE_FOR_luk, target, exp, code, 2);
2775
2776 case IQ2000_BUILTIN_LULCK:
2777 return expand_one_builtin (CODE_FOR_lulck, target, exp, code, 1);
2778
2779 case IQ2000_BUILTIN_LUM32:
2780 return expand_one_builtin (CODE_FOR_lum32, target, exp, code, 2);
2781
2782 case IQ2000_BUILTIN_LUM32L:
2783 return expand_one_builtin (CODE_FOR_lum32l, target, exp, code, 2);
2784
2785 case IQ2000_BUILTIN_LUM64:
2786 return expand_one_builtin (CODE_FOR_lum64, target, exp, code, 2);
2787
2788 case IQ2000_BUILTIN_LUM64L:
2789 return expand_one_builtin (CODE_FOR_lum64l, target, exp, code, 2);
2790
2791 case IQ2000_BUILTIN_LURL:
2792 return expand_one_builtin (CODE_FOR_lurl, target, exp, code, 2);
2793
2794 case IQ2000_BUILTIN_MRGB:
2795 code[2] = CONST_INT;
2796 return expand_one_builtin (CODE_FOR_mrgb, target, exp, code, 3);
2797
2798 case IQ2000_BUILTIN_SRRDL:
2799 return expand_one_builtin (CODE_FOR_srrdl, target, exp, code, 1);
2800
2801 case IQ2000_BUILTIN_SRULCK:
2802 return expand_one_builtin (CODE_FOR_srulck, target, exp, code, 1);
2803
2804 case IQ2000_BUILTIN_SRWRU:
2805 return expand_one_builtin (CODE_FOR_srwru, target, exp, code, 2);
2806
2807 case IQ2000_BUILTIN_TRAPQFL:
2808 return expand_one_builtin (CODE_FOR_trapqfl, target, exp, code, 0);
2809
2810 case IQ2000_BUILTIN_TRAPQNE:
2811 return expand_one_builtin (CODE_FOR_trapqne, target, exp, code, 0);
2812
2813 case IQ2000_BUILTIN_TRAPREL:
2814 return expand_one_builtin (CODE_FOR_traprel, target, exp, code, 1);
2815
2816 case IQ2000_BUILTIN_WBU:
2817 return expand_one_builtin (CODE_FOR_wbu, target, exp, code, 3);
2818
2819 case IQ2000_BUILTIN_SYSCALL:
2820 return expand_one_builtin (CODE_FOR_syscall, target, exp, code, 0);
2821 }
2822
2823 return NULL_RTX;
2824 }
2825 \f
2826 /* Worker function for TARGET_RETURN_IN_MEMORY. */
2827
2828 static bool
2829 iq2000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
2830 {
2831 return ((int_size_in_bytes (type) > (2 * UNITS_PER_WORD))
2832 || (int_size_in_bytes (type) == -1));
2833 }
2834
2835 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2836
2837 static void
2838 iq2000_setup_incoming_varargs (CUMULATIVE_ARGS *cum,
2839 enum machine_mode mode ATTRIBUTE_UNUSED,
2840 tree type ATTRIBUTE_UNUSED, int * pretend_size,
2841 int no_rtl)
2842 {
2843 unsigned int iq2000_off = ! cum->last_arg_fp;
2844 unsigned int iq2000_fp_off = cum->last_arg_fp;
2845
2846 if ((cum->arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off))
2847 {
2848 int iq2000_save_gp_regs
2849 = MAX_ARGS_IN_REGISTERS - cum->arg_words - iq2000_off;
2850 int iq2000_save_fp_regs
2851 = (MAX_ARGS_IN_REGISTERS - cum->fp_arg_words - iq2000_fp_off);
2852
2853 if (iq2000_save_gp_regs < 0)
2854 iq2000_save_gp_regs = 0;
2855 if (iq2000_save_fp_regs < 0)
2856 iq2000_save_fp_regs = 0;
2857
2858 *pretend_size = ((iq2000_save_gp_regs * UNITS_PER_WORD)
2859 + (iq2000_save_fp_regs * UNITS_PER_FPREG));
2860
2861 if (! (no_rtl))
2862 {
2863 if (cum->arg_words < MAX_ARGS_IN_REGISTERS - iq2000_off)
2864 {
2865 rtx ptr, mem;
2866 ptr = plus_constant (virtual_incoming_args_rtx,
2867 - (iq2000_save_gp_regs
2868 * UNITS_PER_WORD));
2869 mem = gen_rtx_MEM (BLKmode, ptr);
2870 move_block_from_reg
2871 (cum->arg_words + GP_ARG_FIRST + iq2000_off,
2872 mem,
2873 iq2000_save_gp_regs);
2874 }
2875 }
2876 }
2877 }
2878 \f
2879 /* A C compound statement to output to stdio stream STREAM the
2880 assembler syntax for an instruction operand that is a memory
2881 reference whose address is ADDR. ADDR is an RTL expression. */
2882
2883 static void
2884 iq2000_print_operand_address (FILE * file, rtx addr)
2885 {
2886 if (!addr)
2887 error ("PRINT_OPERAND_ADDRESS, null pointer");
2888
2889 else
2890 switch (GET_CODE (addr))
2891 {
2892 case REG:
2893 if (REGNO (addr) == ARG_POINTER_REGNUM)
2894 abort_with_insn (addr, "Arg pointer not eliminated.");
2895
2896 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
2897 break;
2898
2899 case LO_SUM:
2900 {
2901 rtx arg0 = XEXP (addr, 0);
2902 rtx arg1 = XEXP (addr, 1);
2903
2904 if (GET_CODE (arg0) != REG)
2905 abort_with_insn (addr,
2906 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
2907
2908 fprintf (file, "%%lo(");
2909 iq2000_print_operand_address (file, arg1);
2910 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
2911 }
2912 break;
2913
2914 case PLUS:
2915 {
2916 rtx reg = 0;
2917 rtx offset = 0;
2918 rtx arg0 = XEXP (addr, 0);
2919 rtx arg1 = XEXP (addr, 1);
2920
2921 if (GET_CODE (arg0) == REG)
2922 {
2923 reg = arg0;
2924 offset = arg1;
2925 if (GET_CODE (offset) == REG)
2926 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
2927 }
2928
2929 else if (GET_CODE (arg1) == REG)
2930 reg = arg1, offset = arg0;
2931 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
2932 {
2933 output_addr_const (file, addr);
2934 break;
2935 }
2936 else
2937 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
2938
2939 if (! CONSTANT_P (offset))
2940 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
2941
2942 if (REGNO (reg) == ARG_POINTER_REGNUM)
2943 abort_with_insn (addr, "Arg pointer not eliminated.");
2944
2945 output_addr_const (file, offset);
2946 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
2947 }
2948 break;
2949
2950 case LABEL_REF:
2951 case SYMBOL_REF:
2952 case CONST_INT:
2953 case CONST:
2954 output_addr_const (file, addr);
2955 if (GET_CODE (addr) == CONST_INT)
2956 fprintf (file, "(%s)", reg_names [0]);
2957 break;
2958
2959 default:
2960 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
2961 break;
2962 }
2963 }
2964 \f
2965 /* A C compound statement to output to stdio stream FILE the
2966 assembler syntax for an instruction operand OP.
2967
2968 LETTER is a value that can be used to specify one of several ways
2969 of printing the operand. It is used when identical operands
2970 must be printed differently depending on the context. LETTER
2971 comes from the `%' specification that was used to request
2972 printing of the operand. If the specification was just `%DIGIT'
2973 then LETTER is 0; if the specification was `%LTR DIGIT' then LETTER
2974 is the ASCII code for LTR.
2975
2976 If OP is a register, this macro should print the register's name.
2977 The names can be found in an array `reg_names' whose type is
2978 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2979
2980 When the machine description has a specification `%PUNCT' (a `%'
2981 followed by a punctuation character), this macro is called with
2982 a null pointer for X and the punctuation character for LETTER.
2983
2984 The IQ2000 specific codes are:
2985
2986 'X' X is CONST_INT, prints upper 16 bits in hexadecimal format = "0x%04x",
2987 'x' X is CONST_INT, prints lower 16 bits in hexadecimal format = "0x%04x",
2988 'd' output integer constant in decimal,
2989 'z' if the operand is 0, use $0 instead of normal operand.
2990 'D' print second part of double-word register or memory operand.
2991 'L' print low-order register of double-word register operand.
2992 'M' print high-order register of double-word register operand.
2993 'C' print part of opcode for a branch condition.
2994 'F' print part of opcode for a floating-point branch condition.
2995 'N' print part of opcode for a branch condition, inverted.
2996 'W' print part of opcode for a floating-point branch condition, inverted.
2997 'A' Print part of opcode for a bit test condition.
2998 'P' Print label for a bit test.
2999 'p' Print log for a bit test.
3000 'B' print 'z' for EQ, 'n' for NE
3001 'b' print 'n' for EQ, 'z' for NE
3002 'T' print 'f' for EQ, 't' for NE
3003 't' print 't' for EQ, 'f' for NE
3004 'Z' print register and a comma, but print nothing for $fcc0
3005 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3006 '@' Print the name of the assembler temporary register (at or $1).
3007 '.' Print the name of the register with a hard-wired zero (zero or $0).
3008 '$' Print the name of the stack pointer register (sp or $29).
3009 '+' Print the name of the gp register (gp or $28). */
3010
3011 static void
3012 iq2000_print_operand (FILE *file, rtx op, int letter)
3013 {
3014 enum rtx_code code;
3015
3016 if (iq2000_print_operand_punct_valid_p (letter))
3017 {
3018 switch (letter)
3019 {
3020 case '?':
3021 if (iq2000_branch_likely)
3022 putc ('l', file);
3023 break;
3024
3025 case '@':
3026 fputs (reg_names [GP_REG_FIRST + 1], file);
3027 break;
3028
3029 case '.':
3030 fputs (reg_names [GP_REG_FIRST + 0], file);
3031 break;
3032
3033 case '$':
3034 fputs (reg_names[STACK_POINTER_REGNUM], file);
3035 break;
3036
3037 case '+':
3038 fputs (reg_names[GP_REG_FIRST + 28], file);
3039 break;
3040
3041 default:
3042 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
3043 break;
3044 }
3045
3046 return;
3047 }
3048
3049 if (! op)
3050 {
3051 error ("PRINT_OPERAND null pointer");
3052 return;
3053 }
3054
3055 code = GET_CODE (op);
3056
3057 if (code == SIGN_EXTEND)
3058 op = XEXP (op, 0), code = GET_CODE (op);
3059
3060 if (letter == 'C')
3061 switch (code)
3062 {
3063 case EQ: fputs ("eq", file); break;
3064 case NE: fputs ("ne", file); break;
3065 case GT: fputs ("gt", file); break;
3066 case GE: fputs ("ge", file); break;
3067 case LT: fputs ("lt", file); break;
3068 case LE: fputs ("le", file); break;
3069 case GTU: fputs ("ne", file); break;
3070 case GEU: fputs ("geu", file); break;
3071 case LTU: fputs ("ltu", file); break;
3072 case LEU: fputs ("eq", file); break;
3073 default:
3074 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
3075 }
3076
3077 else if (letter == 'N')
3078 switch (code)
3079 {
3080 case EQ: fputs ("ne", file); break;
3081 case NE: fputs ("eq", file); break;
3082 case GT: fputs ("le", file); break;
3083 case GE: fputs ("lt", file); break;
3084 case LT: fputs ("ge", file); break;
3085 case LE: fputs ("gt", file); break;
3086 case GTU: fputs ("leu", file); break;
3087 case GEU: fputs ("ltu", file); break;
3088 case LTU: fputs ("geu", file); break;
3089 case LEU: fputs ("gtu", file); break;
3090 default:
3091 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
3092 }
3093
3094 else if (letter == 'F')
3095 switch (code)
3096 {
3097 case EQ: fputs ("c1f", file); break;
3098 case NE: fputs ("c1t", file); break;
3099 default:
3100 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%F");
3101 }
3102
3103 else if (letter == 'W')
3104 switch (code)
3105 {
3106 case EQ: fputs ("c1t", file); break;
3107 case NE: fputs ("c1f", file); break;
3108 default:
3109 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%W");
3110 }
3111
3112 else if (letter == 'A')
3113 fputs (code == LABEL_REF ? "i" : "in", file);
3114
3115 else if (letter == 'P')
3116 {
3117 if (code == LABEL_REF)
3118 output_addr_const (file, op);
3119 else if (code != PC)
3120 output_operand_lossage ("invalid %%P operand");
3121 }
3122
3123 else if (letter == 'p')
3124 {
3125 int value;
3126 if (code != CONST_INT
3127 || (value = exact_log2 (INTVAL (op))) < 0)
3128 output_operand_lossage ("invalid %%p value");
3129 else
3130 fprintf (file, "%d", value);
3131 }
3132
3133 else if (letter == 'Z')
3134 {
3135 gcc_unreachable ();
3136 }
3137
3138 else if (code == REG || code == SUBREG)
3139 {
3140 int regnum;
3141
3142 if (code == REG)
3143 regnum = REGNO (op);
3144 else
3145 regnum = true_regnum (op);
3146
3147 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
3148 || (letter == 'L' && WORDS_BIG_ENDIAN)
3149 || letter == 'D')
3150 regnum++;
3151
3152 fprintf (file, "%s", reg_names[regnum]);
3153 }
3154
3155 else if (code == MEM)
3156 {
3157 if (letter == 'D')
3158 output_address (plus_constant (XEXP (op, 0), 4));
3159 else
3160 output_address (XEXP (op, 0));
3161 }
3162
3163 else if (code == CONST_DOUBLE
3164 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
3165 {
3166 char s[60];
3167
3168 real_to_decimal (s, CONST_DOUBLE_REAL_VALUE (op), sizeof (s), 0, 1);
3169 fputs (s, file);
3170 }
3171
3172 else if (letter == 'x' && GET_CODE (op) == CONST_INT)
3173 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
3174
3175 else if (letter == 'X' && GET_CODE(op) == CONST_INT)
3176 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & (INTVAL (op) >> 16));
3177
3178 else if (letter == 'd' && GET_CODE(op) == CONST_INT)
3179 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
3180
3181 else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
3182 fputs (reg_names[GP_REG_FIRST], file);
3183
3184 else if (letter == 'd' || letter == 'x' || letter == 'X')
3185 output_operand_lossage ("invalid use of %%d, %%x, or %%X");
3186
3187 else if (letter == 'B')
3188 fputs (code == EQ ? "z" : "n", file);
3189 else if (letter == 'b')
3190 fputs (code == EQ ? "n" : "z", file);
3191 else if (letter == 'T')
3192 fputs (code == EQ ? "f" : "t", file);
3193 else if (letter == 't')
3194 fputs (code == EQ ? "t" : "f", file);
3195
3196 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
3197 {
3198 iq2000_print_operand (file, XEXP (op, 0), letter);
3199 }
3200
3201 else
3202 output_addr_const (file, op);
3203 }
3204
3205 static bool
3206 iq2000_print_operand_punct_valid_p (unsigned char code)
3207 {
3208 return iq2000_print_operand_punct[code];
3209 }
3210
3211 /* For the IQ2000, transform:
3212
3213 memory(X + <large int>)
3214 into:
3215 Y = <large int> & ~0x7fff;
3216 Z = X + Y
3217 memory (Z + (<large int> & 0x7fff));
3218 */
3219
3220 rtx
3221 iq2000_legitimize_address (rtx xinsn, rtx old_x ATTRIBUTE_UNUSED,
3222 enum machine_mode mode)
3223 {
3224 if (TARGET_DEBUG_B_MODE)
3225 {
3226 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n");
3227 GO_DEBUG_RTX (xinsn);
3228 }
3229
3230 if (iq2000_check_split (xinsn, mode))
3231 {
3232 return gen_rtx_LO_SUM (Pmode,
3233 copy_to_mode_reg (Pmode,
3234 gen_rtx_HIGH (Pmode, xinsn)),
3235 xinsn);
3236 }
3237
3238 if (GET_CODE (xinsn) == PLUS)
3239 {
3240 rtx xplus0 = XEXP (xinsn, 0);
3241 rtx xplus1 = XEXP (xinsn, 1);
3242 enum rtx_code code0 = GET_CODE (xplus0);
3243 enum rtx_code code1 = GET_CODE (xplus1);
3244
3245 if (code0 != REG && code1 == REG)
3246 {
3247 xplus0 = XEXP (xinsn, 1);
3248 xplus1 = XEXP (xinsn, 0);
3249 code0 = GET_CODE (xplus0);
3250 code1 = GET_CODE (xplus1);
3251 }
3252
3253 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, mode)
3254 && code1 == CONST_INT && !SMALL_INT (xplus1))
3255 {
3256 rtx int_reg = gen_reg_rtx (Pmode);
3257 rtx ptr_reg = gen_reg_rtx (Pmode);
3258
3259 emit_move_insn (int_reg,
3260 GEN_INT (INTVAL (xplus1) & ~ 0x7fff));
3261
3262 emit_insn (gen_rtx_SET (VOIDmode,
3263 ptr_reg,
3264 gen_rtx_PLUS (Pmode, xplus0, int_reg)));
3265
3266 return plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff);
3267 }
3268 }
3269
3270 if (TARGET_DEBUG_B_MODE)
3271 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n");
3272
3273 return xinsn;
3274 }
3275
3276
3277 static bool
3278 iq2000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int * total,
3279 bool speed ATTRIBUTE_UNUSED)
3280 {
3281 enum machine_mode mode = GET_MODE (x);
3282
3283 switch (code)
3284 {
3285 case MEM:
3286 {
3287 int num_words = (GET_MODE_SIZE (mode) > UNITS_PER_WORD) ? 2 : 1;
3288
3289 if (simple_memory_operand (x, mode))
3290 return COSTS_N_INSNS (num_words);
3291
3292 * total = COSTS_N_INSNS (2 * num_words);
3293 break;
3294 }
3295
3296 case FFS:
3297 * total = COSTS_N_INSNS (6);
3298 break;
3299
3300 case AND:
3301 case IOR:
3302 case XOR:
3303 case NOT:
3304 * total = COSTS_N_INSNS (mode == DImode ? 2 : 1);
3305 break;
3306
3307 case ASHIFT:
3308 case ASHIFTRT:
3309 case LSHIFTRT:
3310 if (mode == DImode)
3311 * total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT) ? 4 : 12);
3312 else
3313 * total = COSTS_N_INSNS (1);
3314 break;
3315
3316 case ABS:
3317 if (mode == SFmode || mode == DFmode)
3318 * total = COSTS_N_INSNS (1);
3319 else
3320 * total = COSTS_N_INSNS (4);
3321 break;
3322
3323 case PLUS:
3324 case MINUS:
3325 if (mode == SFmode || mode == DFmode)
3326 * total = COSTS_N_INSNS (6);
3327 else if (mode == DImode)
3328 * total = COSTS_N_INSNS (4);
3329 else
3330 * total = COSTS_N_INSNS (1);
3331 break;
3332
3333 case NEG:
3334 * total = (mode == DImode) ? 4 : 1;
3335 break;
3336
3337 case MULT:
3338 if (mode == SFmode)
3339 * total = COSTS_N_INSNS (7);
3340 else if (mode == DFmode)
3341 * total = COSTS_N_INSNS (8);
3342 else
3343 * total = COSTS_N_INSNS (10);
3344 break;
3345
3346 case DIV:
3347 case MOD:
3348 if (mode == SFmode)
3349 * total = COSTS_N_INSNS (23);
3350 else if (mode == DFmode)
3351 * total = COSTS_N_INSNS (36);
3352 else
3353 * total = COSTS_N_INSNS (69);
3354 break;
3355
3356 case UDIV:
3357 case UMOD:
3358 * total = COSTS_N_INSNS (69);
3359 break;
3360
3361 case SIGN_EXTEND:
3362 * total = COSTS_N_INSNS (2);
3363 break;
3364
3365 case ZERO_EXTEND:
3366 * total = COSTS_N_INSNS (1);
3367 break;
3368
3369 case CONST_INT:
3370 * total = 0;
3371 break;
3372
3373 case LABEL_REF:
3374 * total = COSTS_N_INSNS (2);
3375 break;
3376
3377 case CONST:
3378 {
3379 rtx offset = const0_rtx;
3380 rtx symref = eliminate_constant_term (XEXP (x, 0), & offset);
3381
3382 if (GET_CODE (symref) == LABEL_REF)
3383 * total = COSTS_N_INSNS (2);
3384 else if (GET_CODE (symref) != SYMBOL_REF)
3385 * total = COSTS_N_INSNS (4);
3386 /* Let's be paranoid.... */
3387 else if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767)
3388 * total = COSTS_N_INSNS (2);
3389 else
3390 * total = COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2);
3391 break;
3392 }
3393
3394 case SYMBOL_REF:
3395 * total = COSTS_N_INSNS (SYMBOL_REF_FLAG (x) ? 1 : 2);
3396 break;
3397
3398 case CONST_DOUBLE:
3399 {
3400 rtx high, low;
3401
3402 split_double (x, & high, & low);
3403
3404 * total = COSTS_N_INSNS ( (high == CONST0_RTX (GET_MODE (high))
3405 || low == CONST0_RTX (GET_MODE (low)))
3406 ? 2 : 4);
3407 break;
3408 }
3409
3410 default:
3411 return false;
3412 }
3413 return true;
3414 }
3415
3416 /* Worker for TARGET_ASM_TRAMPOLINE_TEMPLATE. */
3417
3418 static void
3419 iq2000_asm_trampoline_template (FILE *f)
3420 {
3421 fprintf (f, "\t.word\t0x03e00821\t\t# move $1,$31\n");
3422 fprintf (f, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n");
3423 fprintf (f, "\t.word\t0x00000000\t\t# nop\n");
3424 if (Pmode == DImode)
3425 {
3426 fprintf (f, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n");
3427 fprintf (f, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n");
3428 }
3429 else
3430 {
3431 fprintf (f, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n");
3432 fprintf (f, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n");
3433 }
3434 fprintf (f, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n");
3435 fprintf (f, "\t.word\t0x00600008\t\t# jr $3\n");
3436 fprintf (f, "\t.word\t0x0020f821\t\t# move $31,$1\n");
3437 fprintf (f, "\t.word\t0x00000000\t\t# <function address>\n");
3438 fprintf (f, "\t.word\t0x00000000\t\t# <static chain value>\n");
3439 }
3440
3441 /* Worker for TARGET_TRAMPOLINE_INIT. */
3442
3443 static void
3444 iq2000_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
3445 {
3446 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
3447 rtx mem;
3448
3449 emit_block_move (m_tramp, assemble_trampoline_template (),
3450 GEN_INT (TRAMPOLINE_CODE_SIZE), BLOCK_OP_NORMAL);
3451
3452 mem = adjust_address (m_tramp, Pmode, TRAMPOLINE_CODE_SIZE);
3453 emit_move_insn (mem, fnaddr);
3454 mem = adjust_address (m_tramp, Pmode,
3455 TRAMPOLINE_CODE_SIZE + GET_MODE_SIZE (Pmode));
3456 emit_move_insn (mem, chain_value);
3457 }
3458
3459 #include "gt-iq2000.h"
Mirror of https://gcc.gnu.org/git/gcc.git