gcc/config/loongarch/constraints.md

   1 ;; Constraint definitions for LoongArch.
   2 ;; Copyright (C) 2021-2023 Free Software Foundation, Inc.
   3 ;; Contributed by Loongson Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 ;; Register constraints
  22
  23 ;; "a" <-----unused
  24 ;; "b" "A constant call not local address."
  25 ;; "c" "A constant call local address."
  26 ;; "d" <-----unused
  27 ;; "e" JIRL_REGS
  28 ;; "f" FP_REGS
  29 ;; "g" <-----unused
  30 ;; "h" <-----unused
  31 ;; "i" "Matches a general integer constant." (Global non-architectural)
  32 ;; "j" SIBCALL_REGS
  33 ;; "k" "A memory operand whose address is formed by a base register and
  34 ;;      (optionally scaled) index register."
  35 ;; "l" "A signed 16-bit constant."
  36 ;; "m" "A memory operand whose address is formed by a base register and offset
  37 ;;      that is suitable for use in instructions with the same addressing mode
  38 ;;      as @code{st.w} and @code{ld.w}."
  39 ;; "n" "Matches a non-symbolic integer constant." (Global non-architectural)
  40 ;; "o" "Matches an offsettable memory reference." (Global non-architectural)
  41 ;; "p" "Matches a general address." (Global non-architectural)
  42 ;; "q" CSR_REGS
  43 ;; "r" GENERAL_REGS (Global non-architectural)
  44 ;; "s" "Matches a symbolic integer constant." (Global non-architectural)
  45 ;; "t" <-----unused
  46 ;; "u" "A signed 52bit constant and low 32-bit is zero (for logic instructions)"
  47 ;; "v" "A signed 64-bit constant and low 44-bit is zero (for logic instructions)."
  48 ;; "w" "Matches any valid memory."
  49 ;; "x" <-----unused
  50 ;; "y" <-----unused
  51 ;; "z" FCC_REGS
  52 ;; "A" <-----unused
  53 ;; "B" <-----unused
  54 ;; "C" <-----unused
  55 ;; "D" <-----unused
  56 ;; "E" "Matches a floating-point constant." (Global non-architectural)
  57 ;; "F" "Matches a floating-point constant." (Global non-architectural)
  58 ;; "G" "Floating-point zero."
  59 ;; "H" <-----unused
  60 ;; "I" "A signed 12-bit constant (for arithmetic instructions)."
  61 ;; "J" "Integer zero."
  62 ;; "K" "An unsigned 12-bit constant (for logic instructions)."
  63 ;; "L" <-----unused
  64 ;; "M" <-----unused
  65 ;; "N" <-----unused
  66 ;; "O" <-----unused
  67 ;; "P" <-----unused
  68 ;; "Q" <-----unused
  69 ;; "R" <-----unused
  70 ;; "S" <-----unused
  71 ;; "T" <-----unused
  72 ;; "U" <-----unused
  73 ;; "V" "Matches a non-offsettable memory reference." (Global non-architectural)
  74 ;; "W" <-----unused
  75 ;; "X" "Matches anything." (Global non-architectural)
  76 ;; "Y" -
  77 ;;    "Yd"
  78 ;;       "A constant @code{move_operand} that can be safely loaded using
  79 ;;        @code{la}."
  80 ;;    "Yx"
  81 ;; "Z" -
  82 ;;    "ZC"
  83 ;;      "A memory operand whose address is formed by a base register and offset
  84 ;;       that is suitable for use in instructions with the same addressing mode
  85 ;;       as @code{ll.w} and @code{sc.w}."
  86 ;;    "ZB"
  87 ;;      "An address that is held in a general-purpose register.
  88 ;;      The offset is zero"
  89 ;;    "ZD"
  90 ;;      "An address operand whose address is formed by a base register
  91 ;;       and offset that is suitable for use in instructions with the same
  92 ;;       addressing mode as @code{preld}."
  93 ;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural)
  94 ;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural)
  95
  96 (define_constraint "b"
  97   "@internal
  98    A constant call no local address."
  99   (match_operand 0 "is_const_call_no_local_symbol"))
 100
 101 (define_constraint "c"
 102   "@internal
 103    A constant call local address."
 104   (match_operand 0 "is_const_call_local_symbol"))
 105
 106 (define_register_constraint "e" "JIRL_REGS"
 107   "@internal")
 108
 109 (define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
 110   "A floating-point register (if available).")
 111
 112 (define_register_constraint "j" "SIBCALL_REGS"
 113   "@internal")
 114
 115 (define_memory_constraint "k"
 116   "A memory operand whose address is formed by a base register and (optionally scaled)
 117    index register."
 118   (and (match_code "mem")
 119        (match_test "loongarch_base_index_address_p (XEXP (op, 0), mode)")))
 120
 121 (define_constraint "l"
 122 "A signed 16-bit constant."
 123 (and (match_code "const_int")
 124      (match_test "IMM16_OPERAND (ival)")))
 125
 126 (define_memory_constraint "m"
 127   "A memory operand whose address is formed by a base register and offset
 128    that is suitable for use in instructions with the same addressing mode
 129    as @code{st.w} and @code{ld.w}."
 130   (and (match_code "mem")
 131        (match_test "loongarch_12bit_offset_address_p (XEXP (op, 0), mode)")))
 132
 133 (define_register_constraint "q" "CSR_REGS"
 134   "A general-purpose register except for $r0 and $r1 for lcsr.")
 135
 136 (define_constraint "u"
 137   "A signed 52bit constant and low 32-bit is zero (for logic instructions)."
 138   (and (match_code "const_int")
 139        (match_test "LU32I_OPERAND (ival)")))
 140
 141 (define_constraint "v"
 142   "A signed 64-bit constant and low 44-bit is zero (for logic instructions)."
 143   (and (match_code "const_int")
 144        (match_test "LU52I_OPERAND (ival)")))
 145
 146 (define_register_constraint "z" "FCC_REGS"
 147   "A floating-point condition code register.")
 148
 149 ;; Floating-point constraints
 150
 151 (define_constraint "G"
 152   "Floating-point zero."
 153   (and (match_code "const_double")
 154        (match_test "op == CONST0_RTX (mode)")))
 155
 156 ;; Integer constraints
 157
 158 (define_constraint "I"
 159   "A signed 12-bit constant (for arithmetic instructions)."
 160   (and (match_code "const_int")
 161        (match_test "IMM12_OPERAND (ival)")))
 162
 163 (define_constraint "J"
 164   "Integer zero."
 165   (and (match_code "const_int")
 166        (match_test "ival == 0")))
 167
 168 (define_constraint "K"
 169   "An unsigned 12-bit constant (for logic instructions)."
 170   (and (match_code "const_int")
 171        (match_test "IMM12_OPERAND_UNSIGNED (ival)")))
 172
 173 (define_constraint "Yd"
 174   "@internal
 175    A constant @code{move_operand} that can be safely loaded using
 176    @code{la}."
 177   (and (match_operand 0 "move_operand")
 178        (match_test "CONSTANT_P (op)")))
 179
 180 (define_constraint "Yx"
 181    "@internal"
 182    (match_operand 0 "low_bitmask_operand"))
 183
 184 (define_memory_constraint "ZC"
 185   "A memory operand whose address is formed by a base register and offset
 186    that is suitable for use in instructions with the same addressing mode
 187    as @code{ll.w} and @code{sc.w}."
 188   (and (match_code "mem")
 189        (match_test "loongarch_14bit_shifted_offset_address_p (XEXP (op, 0), mode)")))
 190
 191 (define_memory_constraint "ZB"
 192   "@internal
 193   An address that is held in a general-purpose register.
 194   The offset is zero"
 195   (and (match_code "mem")
 196        (match_test "REG_P (XEXP (op, 0))")))
 197
 198 (define_address_constraint "ZD"
 199   "An address operand whose address is formed by a base register
 200    and offset that is suitable for use in instructions with the same
 201    addressing mode as @code{preld}."
 202    (match_test "loongarch_12bit_offset_address_p (op, mode)"))