1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
8 by the Free Software Foundation; either version 3, or (at your
9 option) any later version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
30 #include "stringpool.h"
31 #include "insn-config.h"
34 #include "diagnostic-core.h"
36 #include "stor-layout.h"
40 #include "insn-attr.h"
43 #include "tm-constrs.h"
46 /* This file should be included last. */
47 #include "target-def.h"
49 /* Array of valid operand punctuation characters. */
50 static char m32r_punct_chars
[256];
52 /* Machine-specific symbol_ref flags. */
53 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
54 #define SYMBOL_REF_MODEL(X) \
55 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
57 /* For string literals, etc. */
58 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
60 /* Forward declaration. */
61 static void m32r_option_override (void);
62 static void init_reg_tables (void);
63 static void block_move_call (rtx
, rtx
, rtx
);
64 static int m32r_is_insn (rtx
);
65 static bool m32r_legitimate_address_p (machine_mode
, rtx
, bool);
66 static rtx
m32r_legitimize_address (rtx
, rtx
, machine_mode
);
67 static bool m32r_mode_dependent_address_p (const_rtx
, addr_space_t
);
68 static tree
m32r_handle_model_attribute (tree
*, tree
, tree
, int, bool *);
69 static void m32r_print_operand (FILE *, rtx
, int);
70 static void m32r_print_operand_address (FILE *, machine_mode
, rtx
);
71 static bool m32r_print_operand_punct_valid_p (unsigned char code
);
72 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT
);
73 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT
);
75 static void m32r_file_start (void);
77 static int m32r_adjust_priority (rtx_insn
*, int);
78 static int m32r_issue_rate (void);
80 static void m32r_encode_section_info (tree
, rtx
, int);
81 static bool m32r_in_small_data_p (const_tree
);
82 static bool m32r_return_in_memory (const_tree
, const_tree
);
83 static rtx
m32r_function_value (const_tree
, const_tree
, bool);
84 static rtx
m32r_libcall_value (machine_mode
, const_rtx
);
85 static bool m32r_function_value_regno_p (const unsigned int);
86 static void m32r_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
88 static void init_idents (void);
89 static bool m32r_rtx_costs (rtx
, machine_mode
, int, int, int *, bool speed
);
90 static int m32r_memory_move_cost (machine_mode
, reg_class_t
, bool);
91 static bool m32r_pass_by_reference (cumulative_args_t
, machine_mode
,
93 static int m32r_arg_partial_bytes (cumulative_args_t
, machine_mode
,
95 static rtx
m32r_function_arg (cumulative_args_t
, machine_mode
,
97 static void m32r_function_arg_advance (cumulative_args_t
, machine_mode
,
99 static bool m32r_can_eliminate (const int, const int);
100 static void m32r_conditional_register_usage (void);
101 static void m32r_trampoline_init (rtx
, tree
, rtx
);
102 static bool m32r_legitimate_constant_p (machine_mode
, rtx
);
103 static bool m32r_attribute_identifier (const_tree
);
105 /* M32R specific attributes. */
107 static const struct attribute_spec m32r_attribute_table
[] =
109 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
110 affects_type_identity } */
111 { "interrupt", 0, 0, true, false, false, NULL
, false },
112 { "model", 1, 1, true, false, false, m32r_handle_model_attribute
,
114 { NULL
, 0, 0, false, false, false, NULL
, false }
117 /* Initialize the GCC target structure. */
118 #undef TARGET_ATTRIBUTE_TABLE
119 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
120 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
121 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P m32r_attribute_identifier
124 #define TARGET_LRA_P hook_bool_void_false
126 #undef TARGET_LEGITIMATE_ADDRESS_P
127 #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p
128 #undef TARGET_LEGITIMIZE_ADDRESS
129 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address
130 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
131 #define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p
133 #undef TARGET_ASM_ALIGNED_HI_OP
134 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
135 #undef TARGET_ASM_ALIGNED_SI_OP
136 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
138 #undef TARGET_PRINT_OPERAND
139 #define TARGET_PRINT_OPERAND m32r_print_operand
140 #undef TARGET_PRINT_OPERAND_ADDRESS
141 #define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address
142 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
143 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p
145 #undef TARGET_ASM_FUNCTION_PROLOGUE
146 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
147 #undef TARGET_ASM_FUNCTION_EPILOGUE
148 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
150 #undef TARGET_ASM_FILE_START
151 #define TARGET_ASM_FILE_START m32r_file_start
153 #undef TARGET_SCHED_ADJUST_PRIORITY
154 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
155 #undef TARGET_SCHED_ISSUE_RATE
156 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
158 #undef TARGET_OPTION_OVERRIDE
159 #define TARGET_OPTION_OVERRIDE m32r_option_override
161 #undef TARGET_ENCODE_SECTION_INFO
162 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
163 #undef TARGET_IN_SMALL_DATA_P
164 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
167 #undef TARGET_MEMORY_MOVE_COST
168 #define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost
169 #undef TARGET_RTX_COSTS
170 #define TARGET_RTX_COSTS m32r_rtx_costs
171 #undef TARGET_ADDRESS_COST
172 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
174 #undef TARGET_PROMOTE_PROTOTYPES
175 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
176 #undef TARGET_RETURN_IN_MEMORY
177 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
179 #undef TARGET_FUNCTION_VALUE
180 #define TARGET_FUNCTION_VALUE m32r_function_value
181 #undef TARGET_LIBCALL_VALUE
182 #define TARGET_LIBCALL_VALUE m32r_libcall_value
183 #undef TARGET_FUNCTION_VALUE_REGNO_P
184 #define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p
186 #undef TARGET_SETUP_INCOMING_VARARGS
187 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
188 #undef TARGET_MUST_PASS_IN_STACK
189 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
190 #undef TARGET_PASS_BY_REFERENCE
191 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
192 #undef TARGET_ARG_PARTIAL_BYTES
193 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
194 #undef TARGET_FUNCTION_ARG
195 #define TARGET_FUNCTION_ARG m32r_function_arg
196 #undef TARGET_FUNCTION_ARG_ADVANCE
197 #define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance
199 #undef TARGET_CAN_ELIMINATE
200 #define TARGET_CAN_ELIMINATE m32r_can_eliminate
202 #undef TARGET_CONDITIONAL_REGISTER_USAGE
203 #define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage
205 #undef TARGET_TRAMPOLINE_INIT
206 #define TARGET_TRAMPOLINE_INIT m32r_trampoline_init
208 #undef TARGET_LEGITIMATE_CONSTANT_P
209 #define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p
211 struct gcc_target targetm
= TARGET_INITIALIZER
;
213 /* Called by m32r_option_override to initialize various things. */
220 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
221 memset (m32r_punct_chars
, 0, sizeof (m32r_punct_chars
));
222 m32r_punct_chars
['#'] = 1;
223 m32r_punct_chars
['@'] = 1; /* ??? no longer used */
225 /* Provide default value if not specified. */
226 if (!global_options_set
.x_g_switch_value
)
227 g_switch_value
= SDATA_DEFAULT_SIZE
;
231 m32r_option_override (void)
233 /* These need to be done at start up.
234 It's convenient to do them here. */
236 SUBTARGET_OVERRIDE_OPTIONS
;
239 /* Vectors to keep interesting information about registers where it can easily
240 be got. We use to use the actual mode value as the bit number, but there
241 is (or may be) more than 32 modes now. Instead we use two tables: one
242 indexed by hard register number, and one indexed by mode. */
244 /* The purpose of m32r_mode_class is to shrink the range of modes so that
245 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
246 mapped into one m32r_mode_class mode. */
251 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
252 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
, A_MODE
255 /* Modes for condition codes. */
256 #define C_MODES (1 << (int) C_MODE)
258 /* Modes for single-word and smaller quantities. */
259 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
261 /* Modes for double-word and smaller quantities. */
262 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
264 /* Modes for quad-word and smaller quantities. */
265 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
267 /* Modes for accumulators. */
268 #define A_MODES (1 << (int) A_MODE)
270 /* Value is 1 if register/mode pair is acceptable on arc. */
272 const unsigned int m32r_hard_regno_mode_ok
[FIRST_PSEUDO_REGISTER
] =
274 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
,
275 T_MODES
, T_MODES
, T_MODES
, T_MODES
, T_MODES
, S_MODES
, S_MODES
, S_MODES
,
276 S_MODES
, C_MODES
, A_MODES
, A_MODES
279 unsigned int m32r_mode_class
[NUM_MACHINE_MODES
];
281 enum reg_class m32r_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
284 init_reg_tables (void)
288 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
290 machine_mode m
= (machine_mode
) i
;
292 switch (GET_MODE_CLASS (m
))
295 case MODE_PARTIAL_INT
:
296 case MODE_COMPLEX_INT
:
297 if (GET_MODE_SIZE (m
) <= 4)
298 m32r_mode_class
[i
] = 1 << (int) S_MODE
;
299 else if (GET_MODE_SIZE (m
) == 8)
300 m32r_mode_class
[i
] = 1 << (int) D_MODE
;
301 else if (GET_MODE_SIZE (m
) == 16)
302 m32r_mode_class
[i
] = 1 << (int) T_MODE
;
303 else if (GET_MODE_SIZE (m
) == 32)
304 m32r_mode_class
[i
] = 1 << (int) O_MODE
;
306 m32r_mode_class
[i
] = 0;
309 case MODE_COMPLEX_FLOAT
:
310 if (GET_MODE_SIZE (m
) <= 4)
311 m32r_mode_class
[i
] = 1 << (int) SF_MODE
;
312 else if (GET_MODE_SIZE (m
) == 8)
313 m32r_mode_class
[i
] = 1 << (int) DF_MODE
;
314 else if (GET_MODE_SIZE (m
) == 16)
315 m32r_mode_class
[i
] = 1 << (int) TF_MODE
;
316 else if (GET_MODE_SIZE (m
) == 32)
317 m32r_mode_class
[i
] = 1 << (int) OF_MODE
;
319 m32r_mode_class
[i
] = 0;
322 m32r_mode_class
[i
] = 1 << (int) C_MODE
;
325 m32r_mode_class
[i
] = 0;
330 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
333 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
334 else if (i
== ARG_POINTER_REGNUM
)
335 m32r_regno_reg_class
[i
] = GENERAL_REGS
;
337 m32r_regno_reg_class
[i
] = NO_REGS
;
341 /* M32R specific attribute support.
343 interrupt - for interrupt functions
345 model - select code model used to access object
347 small: addresses use 24 bits, use bl to make calls
348 medium: addresses use 32 bits, use bl to make calls
349 large: addresses use 32 bits, use seth/add3/jl to make calls
351 Grep for MODEL in m32r.h for more info. */
353 static tree small_ident1
;
354 static tree small_ident2
;
355 static tree medium_ident1
;
356 static tree medium_ident2
;
357 static tree large_ident1
;
358 static tree large_ident2
;
363 if (small_ident1
== 0)
365 small_ident1
= get_identifier ("small");
366 small_ident2
= get_identifier ("__small__");
367 medium_ident1
= get_identifier ("medium");
368 medium_ident2
= get_identifier ("__medium__");
369 large_ident1
= get_identifier ("large");
370 large_ident2
= get_identifier ("__large__");
374 /* Handle an "model" attribute; arguments as in
375 struct attribute_spec.handler. */
377 m32r_handle_model_attribute (tree
*node ATTRIBUTE_UNUSED
, tree name
,
378 tree args
, int flags ATTRIBUTE_UNUSED
,
384 arg
= TREE_VALUE (args
);
386 if (arg
!= small_ident1
387 && arg
!= small_ident2
388 && arg
!= medium_ident1
389 && arg
!= medium_ident2
390 && arg
!= large_ident1
391 && arg
!= large_ident2
)
393 warning (OPT_Wattributes
, "invalid argument of %qs attribute",
394 IDENTIFIER_POINTER (name
));
395 *no_add_attrs
= true;
402 m32r_attribute_identifier (const_tree name
)
404 return strcmp (IDENTIFIER_POINTER (name
), "model") == 0
405 || strcmp (IDENTIFIER_POINTER (name
), "__model__") == 0;
408 /* Encode section information of DECL, which is either a VAR_DECL,
409 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
411 For the M32R we want to record:
413 - whether the object lives in .sdata/.sbss.
414 - what code model should be used to access the object
418 m32r_encode_section_info (tree decl
, rtx rtl
, int first
)
422 enum m32r_model model
;
424 default_encode_section_info (decl
, rtl
, first
);
429 model_attr
= lookup_attribute ("model", DECL_ATTRIBUTES (decl
));
436 id
= TREE_VALUE (TREE_VALUE (model_attr
));
438 if (id
== small_ident1
|| id
== small_ident2
)
439 model
= M32R_MODEL_SMALL
;
440 else if (id
== medium_ident1
|| id
== medium_ident2
)
441 model
= M32R_MODEL_MEDIUM
;
442 else if (id
== large_ident1
|| id
== large_ident2
)
443 model
= M32R_MODEL_LARGE
;
445 gcc_unreachable (); /* shouldn't happen */
449 if (TARGET_MODEL_SMALL
)
450 model
= M32R_MODEL_SMALL
;
451 else if (TARGET_MODEL_MEDIUM
)
452 model
= M32R_MODEL_MEDIUM
;
453 else if (TARGET_MODEL_LARGE
)
454 model
= M32R_MODEL_LARGE
;
456 gcc_unreachable (); /* shouldn't happen */
458 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
461 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= extra_flags
;
464 /* Only mark the object as being small data area addressable if
465 it hasn't been explicitly marked with a code model.
467 The user can explicitly put an object in the small data area with the
468 section attribute. If the object is in sdata/sbss and marked with a
469 code model do both [put the object in .sdata and mark it as being
470 addressed with a specific code model - don't mark it as being addressed
471 with an SDA reloc though]. This is ok and might be useful at times. If
472 the object doesn't fit the linker will give an error. */
475 m32r_in_small_data_p (const_tree decl
)
479 if (TREE_CODE (decl
) != VAR_DECL
)
482 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl
)))
485 section
= DECL_SECTION_NAME (decl
);
488 if (strcmp (section
, ".sdata") == 0 || strcmp (section
, ".sbss") == 0)
493 if (! TREE_READONLY (decl
) && ! TARGET_SDATA_NONE
)
495 int size
= int_size_in_bytes (TREE_TYPE (decl
));
497 if (size
> 0 && size
<= g_switch_value
)
505 /* Do anything needed before RTL is emitted for each function. */
508 m32r_init_expanders (void)
510 /* ??? At one point there was code here. The function is left in
511 to make it easy to experiment. */
515 call_operand (rtx op
, machine_mode mode
)
520 return call_address_operand (op
, mode
);
523 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
526 small_data_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
528 if (! TARGET_SDATA_USE
)
531 if (GET_CODE (op
) == SYMBOL_REF
)
532 return SYMBOL_REF_SMALL_P (op
);
534 if (GET_CODE (op
) == CONST
535 && GET_CODE (XEXP (op
, 0)) == PLUS
536 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
537 && satisfies_constraint_J (XEXP (XEXP (op
, 0), 1)))
538 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op
, 0), 0));
543 /* Return 1 if OP is a symbol that can use 24-bit addressing. */
546 addr24_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
553 if (GET_CODE (op
) == LABEL_REF
)
554 return TARGET_ADDR24
;
556 if (GET_CODE (op
) == SYMBOL_REF
)
558 else if (GET_CODE (op
) == CONST
559 && GET_CODE (XEXP (op
, 0)) == PLUS
560 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
561 && satisfies_constraint_M (XEXP (XEXP (op
, 0), 1)))
562 sym
= XEXP (XEXP (op
, 0), 0);
566 if (SYMBOL_REF_MODEL (sym
) == M32R_MODEL_SMALL
)
570 && (CONSTANT_POOL_ADDRESS_P (sym
)
571 || LIT_NAME_P (XSTR (sym
, 0))))
577 /* Return 1 if OP is a symbol that needs 32-bit addressing. */
580 addr32_operand (rtx op
, machine_mode mode
)
584 if (GET_CODE (op
) == LABEL_REF
)
585 return TARGET_ADDR32
;
587 if (GET_CODE (op
) == SYMBOL_REF
)
589 else if (GET_CODE (op
) == CONST
590 && GET_CODE (XEXP (op
, 0)) == PLUS
591 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == SYMBOL_REF
592 && CONST_INT_P (XEXP (XEXP (op
, 0), 1))
594 sym
= XEXP (XEXP (op
, 0), 0);
598 return (! addr24_operand (sym
, mode
)
599 && ! small_data_operand (sym
, mode
));
602 /* Return 1 if OP is a function that can be called with the `bl' insn. */
605 call26_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
610 if (GET_CODE (op
) == SYMBOL_REF
)
611 return SYMBOL_REF_MODEL (op
) != M32R_MODEL_LARGE
;
613 return TARGET_CALL26
;
616 /* Return 1 if OP is a DImode const we want to handle inline.
617 This must match the code in the movdi pattern.
618 It is used by the 'G' constraint. */
621 easy_di_const (rtx op
)
623 rtx high_rtx
, low_rtx
;
624 HOST_WIDE_INT high
, low
;
626 split_double (op
, &high_rtx
, &low_rtx
);
627 high
= INTVAL (high_rtx
);
628 low
= INTVAL (low_rtx
);
629 /* Pick constants loadable with 2 16-bit `ldi' insns. */
630 if (high
>= -128 && high
<= 127
631 && low
>= -128 && low
<= 127)
636 /* Return 1 if OP is a DFmode const we want to handle inline.
637 This must match the code in the movdf pattern.
638 It is used by the 'H' constraint. */
641 easy_df_const (rtx op
)
645 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
646 if (l
[0] == 0 && l
[1] == 0)
648 if ((l
[0] & 0xffff) == 0 && l
[1] == 0)
653 /* Return 1 if OP is (mem (reg ...)).
654 This is used in insn length calcs. */
657 memreg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
659 return MEM_P (op
) && REG_P (XEXP (op
, 0));
662 /* Return nonzero if TYPE must be passed by indirect reference. */
665 m32r_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
666 machine_mode mode
, const_tree type
,
667 bool named ATTRIBUTE_UNUSED
)
672 size
= int_size_in_bytes (type
);
674 size
= GET_MODE_SIZE (mode
);
676 return (size
< 0 || size
> 8);
681 /* X and Y are two things to compare using CODE. Emit the compare insn and
682 return the rtx for compare [arg0 of the if_then_else].
683 If need_compare is true then the comparison insn must be generated, rather
684 than being subsumed into the following branch instruction. */
687 gen_compare (enum rtx_code code
, rtx x
, rtx y
, int need_compare
)
689 enum rtx_code compare_code
;
690 enum rtx_code branch_code
;
691 rtx cc_reg
= gen_rtx_REG (CCmode
, CARRY_REGNUM
);
696 case EQ
: compare_code
= EQ
; branch_code
= NE
; break;
697 case NE
: compare_code
= EQ
; branch_code
= EQ
; break;
698 case LT
: compare_code
= LT
; branch_code
= NE
; break;
699 case LE
: compare_code
= LT
; branch_code
= EQ
; must_swap
= 1; break;
700 case GT
: compare_code
= LT
; branch_code
= NE
; must_swap
= 1; break;
701 case GE
: compare_code
= LT
; branch_code
= EQ
; break;
702 case LTU
: compare_code
= LTU
; branch_code
= NE
; break;
703 case LEU
: compare_code
= LTU
; branch_code
= EQ
; must_swap
= 1; break;
704 case GTU
: compare_code
= LTU
; branch_code
= NE
; must_swap
= 1; break;
705 case GEU
: compare_code
= LTU
; branch_code
= EQ
; break;
713 switch (compare_code
)
716 if (satisfies_constraint_P (y
) /* Reg equal to small const. */
719 rtx tmp
= gen_reg_rtx (SImode
);
721 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
725 else if (CONSTANT_P (y
)) /* Reg equal to const. */
727 rtx tmp
= force_reg (GET_MODE (x
), y
);
731 if (register_operand (y
, SImode
) /* Reg equal to reg. */
732 || y
== const0_rtx
) /* Reg equal to zero. */
734 emit_insn (gen_cmp_eqsi_insn (x
, y
));
736 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
741 if (register_operand (y
, SImode
)
742 || satisfies_constraint_P (y
))
744 rtx tmp
= gen_reg_rtx (SImode
); /* Reg compared to reg. */
749 emit_insn (gen_cmp_ltsi_insn (x
, y
));
756 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
757 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
762 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
764 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
765 emit_insn (gen_cmp_ltsi_insn (x
, tmp
));
769 emit_insn (gen_cmp_ltsi_insn (x
, y
));
776 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
781 if (register_operand (y
, SImode
)
782 || satisfies_constraint_P (y
))
784 rtx tmp
= gen_reg_rtx (SImode
); /* Reg (unsigned) compared to reg. */
789 emit_insn (gen_cmp_ltusi_insn (x
, y
));
796 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
797 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
802 tmp
= gen_rtx_PLUS (SImode
, y
, const1_rtx
);
804 emit_insn (gen_addsi3 (tmp
, y
, constm1_rtx
));
805 emit_insn (gen_cmp_ltusi_insn (x
, tmp
));
809 emit_insn (gen_cmp_ltusi_insn (x
, y
));
816 return gen_rtx_fmt_ee (code
, CCmode
, cc_reg
, const0_rtx
);
826 /* Reg/reg equal comparison. */
827 if (compare_code
== EQ
828 && register_operand (y
, SImode
))
829 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
831 /* Reg/zero signed comparison. */
832 if ((compare_code
== EQ
|| compare_code
== LT
)
834 return gen_rtx_fmt_ee (code
, CCmode
, x
, y
);
836 /* Reg/smallconst equal comparison. */
837 if (compare_code
== EQ
838 && satisfies_constraint_P (y
))
840 rtx tmp
= gen_reg_rtx (SImode
);
842 emit_insn (gen_addsi3 (tmp
, x
, GEN_INT (-INTVAL (y
))));
843 return gen_rtx_fmt_ee (code
, CCmode
, tmp
, const0_rtx
);
846 /* Reg/const equal comparison. */
847 if (compare_code
== EQ
850 rtx tmp
= force_reg (GET_MODE (x
), y
);
852 return gen_rtx_fmt_ee (code
, CCmode
, x
, tmp
);
859 y
= force_reg (GET_MODE (x
), y
);
862 int ok_const
= reg_or_int16_operand (y
, GET_MODE (y
));
865 y
= force_reg (GET_MODE (x
), y
);
869 switch (compare_code
)
872 emit_insn (gen_cmp_eqsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
875 emit_insn (gen_cmp_ltsi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
878 emit_insn (gen_cmp_ltusi_insn (must_swap
? y
: x
, must_swap
? x
: y
));
885 return gen_rtx_fmt_ee (branch_code
, VOIDmode
, cc_reg
, CONST0_RTX (CCmode
));
889 gen_cond_store (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
891 machine_mode mode
= GET_MODE (op0
);
893 gcc_assert (mode
== SImode
);
897 if (!register_operand (op1
, mode
))
898 op1
= force_reg (mode
, op1
);
900 if (TARGET_M32RX
|| TARGET_M32R2
)
902 if (!reg_or_zero_operand (op2
, mode
))
903 op2
= force_reg (mode
, op2
);
905 emit_insn (gen_seq_insn_m32rx (op0
, op1
, op2
));
908 if (CONST_INT_P (op2
) && INTVAL (op2
) == 0)
910 emit_insn (gen_seq_zero_insn (op0
, op1
));
914 if (!reg_or_eq_int16_operand (op2
, mode
))
915 op2
= force_reg (mode
, op2
);
917 emit_insn (gen_seq_insn (op0
, op1
, op2
));
921 if (!CONST_INT_P (op2
)
922 || (INTVAL (op2
) != 0 && satisfies_constraint_K (op2
)))
926 if (reload_completed
|| reload_in_progress
)
929 reg
= gen_reg_rtx (SImode
);
930 emit_insn (gen_xorsi3 (reg
, op1
, op2
));
933 if (!register_operand (op1
, mode
))
934 op1
= force_reg (mode
, op1
);
936 emit_insn (gen_sne_zero_insn (op0
, op1
));
951 if (!register_operand (op1
, mode
))
952 op1
= force_reg (mode
, op1
);
954 if (!reg_or_int16_operand (op2
, mode
))
955 op2
= force_reg (mode
, op2
);
957 emit_insn (gen_slt_insn (op0
, op1
, op2
));
970 if (!register_operand (op1
, mode
))
971 op1
= force_reg (mode
, op1
);
973 if (!reg_or_int16_operand (op2
, mode
))
974 op2
= force_reg (mode
, op2
);
976 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
981 if (!register_operand (op1
, mode
))
982 op1
= force_reg (mode
, op1
);
984 if (!reg_or_int16_operand (op2
, mode
))
985 op2
= force_reg (mode
, op2
);
988 emit_insn (gen_sge_insn (op0
, op1
, op2
));
990 emit_insn (gen_sgeu_insn (op0
, op1
, op2
));
995 if (!register_operand (op1
, mode
))
996 op1
= force_reg (mode
, op1
);
998 if (CONST_INT_P (op2
))
1000 HOST_WIDE_INT value
= INTVAL (op2
);
1001 if (value
>= 2147483647)
1003 emit_move_insn (op0
, const1_rtx
);
1007 op2
= GEN_INT (value
+ 1);
1008 if (value
< -32768 || value
>= 32767)
1009 op2
= force_reg (mode
, op2
);
1012 emit_insn (gen_sltu_insn (op0
, op1
, op2
));
1014 emit_insn (gen_slt_insn (op0
, op1
, op2
));
1018 if (!register_operand (op2
, mode
))
1019 op2
= force_reg (mode
, op2
);
1022 emit_insn (gen_sleu_insn (op0
, op1
, op2
));
1024 emit_insn (gen_sle_insn (op0
, op1
, op2
));
1033 /* Split a 2 word move (DI or DF) into component parts. */
1036 gen_split_move_double (rtx operands
[])
1038 machine_mode mode
= GET_MODE (operands
[0]);
1039 rtx dest
= operands
[0];
1040 rtx src
= operands
[1];
1043 /* We might have (SUBREG (MEM)) here, so just get rid of the
1044 subregs to make this code simpler. It is safe to call
1045 alter_subreg any time after reload. */
1046 if (GET_CODE (dest
) == SUBREG
)
1047 alter_subreg (&dest
, true);
1048 if (GET_CODE (src
) == SUBREG
)
1049 alter_subreg (&src
, true);
1054 int dregno
= REGNO (dest
);
1059 int sregno
= REGNO (src
);
1061 int reverse
= (dregno
== sregno
+ 1);
1063 /* We normally copy the low-numbered register first. However, if
1064 the first register operand 0 is the same as the second register of
1065 operand 1, we must copy in the opposite order. */
1066 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
1067 operand_subword (src
, reverse
, TRUE
, mode
)));
1069 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
1070 operand_subword (src
, !reverse
, TRUE
, mode
)));
1073 /* Reg = constant. */
1074 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
1077 split_double (src
, &words
[0], &words
[1]);
1078 emit_insn (gen_rtx_SET (operand_subword (dest
, 0, TRUE
, mode
),
1081 emit_insn (gen_rtx_SET (operand_subword (dest
, 1, TRUE
, mode
),
1086 else if (MEM_P (src
))
1088 /* If the high-address word is used in the address, we must load it
1089 last. Otherwise, load it first. */
1090 int reverse
= refers_to_regno_p (dregno
, XEXP (src
, 0));
1092 /* We used to optimize loads from single registers as
1096 if r3 were not used subsequently. However, the REG_NOTES aren't
1097 propagated correctly by the reload phase, and it can cause bad
1098 code to be generated. We could still try:
1100 ld r1,r3+; ld r2,r3; addi r3,-4
1102 which saves 2 bytes and doesn't force longword alignment. */
1103 emit_insn (gen_rtx_SET (operand_subword (dest
, reverse
, TRUE
, mode
),
1104 adjust_address (src
, SImode
,
1105 reverse
* UNITS_PER_WORD
)));
1107 emit_insn (gen_rtx_SET (operand_subword (dest
, !reverse
, TRUE
, mode
),
1108 adjust_address (src
, SImode
,
1109 !reverse
* UNITS_PER_WORD
)));
1116 /* We used to optimize loads from single registers as
1120 if r3 were not used subsequently. However, the REG_NOTES aren't
1121 propagated correctly by the reload phase, and it can cause bad
1122 code to be generated. We could still try:
1124 st r1,r3; st r2,+r3; addi r3,-4
1126 which saves 2 bytes and doesn't force longword alignment. */
1127 else if (MEM_P (dest
) && REG_P (src
))
1129 emit_insn (gen_rtx_SET (adjust_address (dest
, SImode
, 0),
1130 operand_subword (src
, 0, TRUE
, mode
)));
1132 emit_insn (gen_rtx_SET (adjust_address (dest
, SImode
, UNITS_PER_WORD
),
1133 operand_subword (src
, 1, TRUE
, mode
)));
1146 m32r_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
1147 tree type
, bool named ATTRIBUTE_UNUSED
)
1149 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1153 (((mode
== BLKmode
&& type
)
1154 ? (unsigned int) int_size_in_bytes (type
)
1155 : GET_MODE_SIZE (mode
)) + UNITS_PER_WORD
- 1)
1158 if (*cum
>= M32R_MAX_PARM_REGS
)
1160 else if (*cum
+ size
> M32R_MAX_PARM_REGS
)
1161 words
= (*cum
+ size
) - M32R_MAX_PARM_REGS
;
1165 return words
* UNITS_PER_WORD
;
1168 /* The ROUND_ADVANCE* macros are local to this file. */
1169 /* Round SIZE up to a word boundary. */
1170 #define ROUND_ADVANCE(SIZE) \
1171 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
1173 /* Round arg MODE/TYPE up to the next word boundary. */
1174 #define ROUND_ADVANCE_ARG(MODE, TYPE) \
1175 ((MODE) == BLKmode \
1176 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \
1177 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE)))
1179 /* Round CUM up to the necessary point for argument MODE/TYPE. */
1180 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM)
1182 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
1183 a reg. This includes arguments that have to be passed by reference as the
1184 pointer to them is passed in a reg if one is available (and that is what
1186 This macro is only used in this file. */
1187 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
1188 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS)
1190 /* Determine where to put an argument to a function.
1191 Value is zero to push the argument on the stack,
1192 or a hard register in which to store the argument.
1194 MODE is the argument's machine mode.
1195 TYPE is the data type of the argument (as a tree).
1196 This is null for libcalls where that information may
1198 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1199 the preceding args and about the function being called.
1200 NAMED is nonzero if this argument is a named parameter
1201 (otherwise it is an extra parameter matching an ellipsis). */
1202 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers
1203 and the rest are pushed. */
1206 m32r_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1207 const_tree type ATTRIBUTE_UNUSED
,
1208 bool named ATTRIBUTE_UNUSED
)
1210 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1212 return (PASS_IN_REG_P (*cum
, mode
, type
)
1213 ? gen_rtx_REG (mode
, ROUND_ADVANCE_CUM (*cum
, mode
, type
))
1217 /* Update the data in CUM to advance over an argument
1218 of mode MODE and data type TYPE.
1219 (TYPE is null for libcalls where that information may not be available.) */
1222 m32r_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1223 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1225 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1227 *cum
= (ROUND_ADVANCE_CUM (*cum
, mode
, type
)
1228 + ROUND_ADVANCE_ARG (mode
, type
));
1231 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1234 m32r_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1236 cumulative_args_t dummy
= pack_cumulative_args (NULL
);
1238 return m32r_pass_by_reference (dummy
, TYPE_MODE (type
), type
, false);
1241 /* Worker function for TARGET_FUNCTION_VALUE. */
1244 m32r_function_value (const_tree valtype
,
1245 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1246 bool outgoing ATTRIBUTE_UNUSED
)
1248 return gen_rtx_REG (TYPE_MODE (valtype
), 0);
1251 /* Worker function for TARGET_LIBCALL_VALUE. */
1254 m32r_libcall_value (machine_mode mode
,
1255 const_rtx fun ATTRIBUTE_UNUSED
)
1257 return gen_rtx_REG (mode
, 0);
1260 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1262 ??? What about r1 in DI/DF values. */
1265 m32r_function_value_regno_p (const unsigned int regno
)
1267 return (regno
== 0);
1270 /* Do any needed setup for a variadic function. For the M32R, we must
1271 create a register parameter block, and then copy any anonymous arguments
1272 in registers to memory.
1274 CUM has not been updated for the last named argument which has type TYPE
1275 and mode MODE, and we rely on this fact. */
1278 m32r_setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
1279 tree type
, int *pretend_size
, int no_rtl
)
1286 /* All BLKmode values are passed by reference. */
1287 gcc_assert (mode
!= BLKmode
);
1289 first_anon_arg
= (ROUND_ADVANCE_CUM (*get_cumulative_args (cum
), mode
, type
)
1290 + ROUND_ADVANCE_ARG (mode
, type
));
1292 if (first_anon_arg
< M32R_MAX_PARM_REGS
)
1294 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1295 int first_reg_offset
= first_anon_arg
;
1296 /* Size in words to "pretend" allocate. */
1297 int size
= M32R_MAX_PARM_REGS
- first_reg_offset
;
1300 regblock
= gen_frame_mem (BLKmode
,
1301 plus_constant (Pmode
, arg_pointer_rtx
,
1302 FIRST_PARM_OFFSET (0)));
1303 set_mem_alias_set (regblock
, get_varargs_alias_set ());
1304 move_block_from_reg (first_reg_offset
, regblock
, size
);
1306 *pretend_size
= (size
* UNITS_PER_WORD
);
1311 /* Return true if INSN is real instruction bearing insn. */
1314 m32r_is_insn (rtx insn
)
1316 return (NONDEBUG_INSN_P (insn
)
1317 && GET_CODE (PATTERN (insn
)) != USE
1318 && GET_CODE (PATTERN (insn
)) != CLOBBER
);
1321 /* Increase the priority of long instructions so that the
1322 short instructions are scheduled ahead of the long ones. */
1325 m32r_adjust_priority (rtx_insn
*insn
, int priority
)
1327 if (m32r_is_insn (insn
)
1328 && get_attr_insn_size (insn
) != INSN_SIZE_SHORT
)
1335 /* Indicate how many instructions can be issued at the same time.
1336 This is sort of a lie. The m32r can issue only 1 long insn at
1337 once, but it can issue 2 short insns. The default therefore is
1338 set at 2, but this can be overridden by the command line option
1342 m32r_issue_rate (void)
1344 return ((TARGET_LOW_ISSUE_RATE
) ? 1 : 2);
1347 /* Cost functions. */
1348 /* Memory is 3 times as expensive as registers.
1349 ??? Is that the right way to look at it? */
1352 m32r_memory_move_cost (machine_mode mode
,
1353 reg_class_t rclass ATTRIBUTE_UNUSED
,
1354 bool in ATTRIBUTE_UNUSED
)
1356 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
1363 m32r_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
1364 int outer_code ATTRIBUTE_UNUSED
,
1365 int opno ATTRIBUTE_UNUSED
, int *total
,
1366 bool speed ATTRIBUTE_UNUSED
)
1368 int code
= GET_CODE (x
);
1372 /* Small integers are as cheap as registers. 4 byte values can be
1373 fetched as immediate constants - let's give that the cost of an
1376 if (INT16_P (INTVAL (x
)))
1386 *total
= COSTS_N_INSNS (1);
1393 split_double (x
, &high
, &low
);
1394 *total
= COSTS_N_INSNS (!INT16_P (INTVAL (high
))
1395 + !INT16_P (INTVAL (low
)));
1400 *total
= COSTS_N_INSNS (3);
1407 *total
= COSTS_N_INSNS (10);
1415 /* Type of function DECL.
1417 The result is cached. To reset the cache at the end of a function,
1418 call with DECL = NULL_TREE. */
1420 enum m32r_function_type
1421 m32r_compute_function_type (tree decl
)
1424 static enum m32r_function_type fn_type
= M32R_FUNCTION_UNKNOWN
;
1425 /* Last function we were called for. */
1426 static tree last_fn
= NULL_TREE
;
1428 /* Resetting the cached value? */
1429 if (decl
== NULL_TREE
)
1431 fn_type
= M32R_FUNCTION_UNKNOWN
;
1432 last_fn
= NULL_TREE
;
1436 if (decl
== last_fn
&& fn_type
!= M32R_FUNCTION_UNKNOWN
)
1439 /* Compute function type. */
1440 fn_type
= (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
1441 ? M32R_FUNCTION_INTERRUPT
1442 : M32R_FUNCTION_NORMAL
);
1447 \f/* Function prologue/epilogue handlers. */
1449 /* M32R stack frames look like:
1451 Before call After call
1452 +-----------------------+ +-----------------------+
1454 high | local variables, | | local variables, |
1455 mem | reg save area, etc. | | reg save area, etc. |
1457 +-----------------------+ +-----------------------+
1459 | arguments on stack. | | arguments on stack. |
1461 SP+0->+-----------------------+ +-----------------------+
1462 | reg parm save area, |
1463 | only created for |
1464 | variable argument |
1466 +-----------------------+
1467 | previous frame ptr |
1468 +-----------------------+
1470 | register save area |
1472 +-----------------------+
1474 +-----------------------+
1478 +-----------------------+
1480 | alloca allocations |
1482 +-----------------------+
1484 low | arguments on stack |
1486 SP+0->+-----------------------+
1489 1) The "reg parm save area" does not exist for non variable argument fns.
1490 2) The "reg parm save area" can be eliminated completely if we saved regs
1491 containing anonymous args separately but that complicates things too
1492 much (so it's not done).
1493 3) The return address is saved after the register save area so as to have as
1494 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1496 /* Structure to be filled in by m32r_compute_frame_size with register
1497 save masks, and offsets for the current function. */
1498 struct m32r_frame_info
1500 unsigned int total_size
; /* # bytes that the entire frame takes up. */
1501 unsigned int extra_size
; /* # bytes of extra stuff. */
1502 unsigned int pretend_size
; /* # bytes we push and pretend caller did. */
1503 unsigned int args_size
; /* # bytes that outgoing arguments take up. */
1504 unsigned int reg_size
; /* # bytes needed to store regs. */
1505 unsigned int var_size
; /* # bytes that variables take up. */
1506 unsigned int gmask
; /* Mask of saved gp registers. */
1507 unsigned int save_fp
; /* Nonzero if fp must be saved. */
1508 unsigned int save_lr
; /* Nonzero if lr (return addr) must be saved. */
1509 int initialized
; /* Nonzero if frame size already calculated. */
1512 /* Current frame information calculated by m32r_compute_frame_size. */
1513 static struct m32r_frame_info current_frame_info
;
1515 /* Zero structure to initialize current_frame_info. */
1516 static struct m32r_frame_info zero_frame_info
;
1518 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1519 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1521 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1522 The return address and frame pointer are treated separately.
1523 Don't consider them here. */
1524 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1525 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1526 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p)))
1528 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM))
1529 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile)
1531 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1532 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1534 /* Return the bytes needed to compute the frame pointer from the current
1537 SIZE is the size needed for local variables. */
1540 m32r_compute_frame_size (int size
) /* # of var. bytes allocated. */
1543 unsigned int total_size
, var_size
, args_size
, pretend_size
, extra_size
;
1544 unsigned int reg_size
;
1546 enum m32r_function_type fn_type
;
1548 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1551 var_size
= M32R_STACK_ALIGN (size
);
1552 args_size
= M32R_STACK_ALIGN (crtl
->outgoing_args_size
);
1553 pretend_size
= crtl
->args
.pretend_args_size
;
1554 extra_size
= FIRST_PARM_OFFSET (0);
1555 total_size
= extra_size
+ pretend_size
+ args_size
+ var_size
;
1559 /* See if this is an interrupt handler. Call used registers must be saved
1561 fn_type
= m32r_compute_function_type (current_function_decl
);
1562 interrupt_p
= M32R_INTERRUPT_P (fn_type
);
1564 /* Calculate space needed for registers. */
1565 for (regno
= 0; regno
< M32R_MAX_INT_REGS
; regno
++)
1567 if (MUST_SAVE_REGISTER (regno
, interrupt_p
)
1568 || (regno
== PIC_OFFSET_TABLE_REGNUM
&& pic_reg_used
))
1570 reg_size
+= UNITS_PER_WORD
;
1571 gmask
|= 1 << regno
;
1575 current_frame_info
.save_fp
= MUST_SAVE_FRAME_POINTER
;
1576 current_frame_info
.save_lr
= MUST_SAVE_RETURN_ADDR
|| pic_reg_used
;
1578 reg_size
+= ((current_frame_info
.save_fp
+ current_frame_info
.save_lr
)
1580 total_size
+= reg_size
;
1582 /* ??? Not sure this is necessary, and I don't think the epilogue
1583 handler will do the right thing if this changes total_size. */
1584 total_size
= M32R_STACK_ALIGN (total_size
);
1586 /* frame_size = total_size - (pretend_size + reg_size); */
1588 /* Save computed information. */
1589 current_frame_info
.total_size
= total_size
;
1590 current_frame_info
.extra_size
= extra_size
;
1591 current_frame_info
.pretend_size
= pretend_size
;
1592 current_frame_info
.var_size
= var_size
;
1593 current_frame_info
.args_size
= args_size
;
1594 current_frame_info
.reg_size
= reg_size
;
1595 current_frame_info
.gmask
= gmask
;
1596 current_frame_info
.initialized
= reload_completed
;
1598 /* Ok, we're done. */
1602 /* Worker function for TARGET_CAN_ELIMINATE. */
1605 m32r_can_eliminate (const int from
, const int to
)
1607 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
1608 ? ! frame_pointer_needed
1613 /* The table we use to reference PIC data. */
1614 static rtx global_offset_table
;
1617 m32r_reload_lr (rtx sp
, int size
)
1619 rtx lr
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
1622 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, sp
)));
1623 else if (size
< 32768)
1624 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
,
1625 gen_rtx_PLUS (Pmode
, sp
,
1629 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1631 emit_insn (gen_movsi (tmp
, GEN_INT (size
)));
1632 emit_insn (gen_addsi3 (tmp
, tmp
, sp
));
1633 emit_insn (gen_movsi (lr
, gen_frame_mem (Pmode
, tmp
)));
1640 m32r_load_pic_register (void)
1642 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1643 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
1644 GEN_INT (TARGET_MODEL_SMALL
)));
1646 /* Need to emit this whether or not we obey regdecls,
1647 since setjmp/longjmp can cause life info to screw up. */
1648 emit_use (pic_offset_table_rtx
);
1651 /* Expand the m32r prologue as a series of insns. */
1654 m32r_expand_prologue (void)
1659 int pic_reg_used
= flag_pic
&& (crtl
->uses_pic_offset_table
1662 if (! current_frame_info
.initialized
)
1663 m32r_compute_frame_size (get_frame_size ());
1665 if (flag_stack_usage_info
)
1666 current_function_static_stack_size
= current_frame_info
.total_size
;
1668 gmask
= current_frame_info
.gmask
;
1670 /* These cases shouldn't happen. Catch them now. */
1671 gcc_assert (current_frame_info
.total_size
|| !gmask
);
1673 /* Allocate space for register arguments if this is a variadic function. */
1674 if (current_frame_info
.pretend_size
!= 0)
1676 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1677 the wrong result on a 64-bit host. */
1678 HOST_WIDE_INT pretend_size
= current_frame_info
.pretend_size
;
1679 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1681 GEN_INT (-pretend_size
)));
1684 /* Save any registers we need to and set up fp. */
1685 if (current_frame_info
.save_fp
)
1686 emit_insn (gen_movsi_push (stack_pointer_rtx
, frame_pointer_rtx
));
1688 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1690 /* Save any needed call-saved regs (and call-used if this is an
1691 interrupt handler). */
1692 for (regno
= 0; regno
<= M32R_MAX_INT_REGS
; ++regno
)
1694 if ((gmask
& (1 << regno
)) != 0)
1695 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1696 gen_rtx_REG (Pmode
, regno
)));
1699 if (current_frame_info
.save_lr
)
1700 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1701 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1703 /* Allocate the stack frame. */
1704 frame_size
= (current_frame_info
.total_size
1705 - (current_frame_info
.pretend_size
1706 + current_frame_info
.reg_size
));
1708 if (frame_size
== 0)
1709 ; /* Nothing to do. */
1710 else if (frame_size
<= 32768)
1711 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1712 GEN_INT (-frame_size
)));
1715 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1717 emit_insn (gen_movsi (tmp
, GEN_INT (frame_size
)));
1718 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
1721 if (frame_pointer_needed
)
1722 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
1725 /* Push lr for mcount (form_pc, x). */
1726 emit_insn (gen_movsi_push (stack_pointer_rtx
,
1727 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
)));
1731 m32r_load_pic_register ();
1732 m32r_reload_lr (stack_pointer_rtx
,
1733 (crtl
->profile
? 0 : frame_size
));
1736 if (crtl
->profile
&& !pic_reg_used
)
1737 emit_insn (gen_blockage ());
1741 /* Set up the stack and frame pointer (if desired) for the function.
1742 Note, if this is changed, you need to mirror the changes in
1743 m32r_compute_frame_size which calculates the prolog size. */
1746 m32r_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
1748 enum m32r_function_type fn_type
= m32r_compute_function_type (current_function_decl
);
1750 /* If this is an interrupt handler, mark it as such. */
1751 if (M32R_INTERRUPT_P (fn_type
))
1752 fprintf (file
, "\t%s interrupt handler\n", ASM_COMMENT_START
);
1754 if (! current_frame_info
.initialized
)
1755 m32r_compute_frame_size (size
);
1757 /* This is only for the human reader. */
1759 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1761 current_frame_info
.var_size
,
1762 current_frame_info
.reg_size
/ 4,
1763 current_frame_info
.args_size
,
1764 current_frame_info
.extra_size
);
1767 /* Output RTL to pop register REGNO from the stack. */
1774 x
= emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode
, regno
),
1775 stack_pointer_rtx
));
1776 add_reg_note (x
, REG_INC
, stack_pointer_rtx
);
1779 /* Expand the m32r epilogue as a series of insns. */
1782 m32r_expand_epilogue (void)
1785 int noepilogue
= FALSE
;
1788 gcc_assert (current_frame_info
.initialized
);
1789 total_size
= current_frame_info
.total_size
;
1791 if (total_size
== 0)
1793 rtx_insn
*insn
= get_last_insn ();
1795 /* If the last insn was a BARRIER, we don't have to write any code
1796 because a jump (aka return) was put there. */
1797 if (insn
&& NOTE_P (insn
))
1798 insn
= prev_nonnote_insn (insn
);
1799 if (insn
&& BARRIER_P (insn
))
1805 unsigned int var_size
= current_frame_info
.var_size
;
1806 unsigned int args_size
= current_frame_info
.args_size
;
1807 unsigned int gmask
= current_frame_info
.gmask
;
1808 int can_trust_sp_p
= !cfun
->calls_alloca
;
1810 if (flag_exceptions
)
1811 emit_insn (gen_blockage ());
1813 /* The first thing to do is point the sp at the bottom of the register
1817 unsigned int reg_offset
= var_size
+ args_size
;
1819 if (reg_offset
== 0)
1820 ; /* Nothing to do. */
1821 else if (reg_offset
< 32768)
1822 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1823 GEN_INT (reg_offset
)));
1826 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1828 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1829 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1833 else if (frame_pointer_needed
)
1835 unsigned int reg_offset
= var_size
+ args_size
;
1837 if (reg_offset
== 0)
1838 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1839 else if (reg_offset
< 32768)
1840 emit_insn (gen_addsi3 (stack_pointer_rtx
, frame_pointer_rtx
,
1841 GEN_INT (reg_offset
)));
1844 rtx tmp
= gen_rtx_REG (Pmode
, PROLOGUE_TMP_REGNUM
);
1846 emit_insn (gen_movsi (tmp
, GEN_INT (reg_offset
)));
1847 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
1848 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1855 if (current_frame_info
.save_lr
)
1856 pop (RETURN_ADDR_REGNUM
);
1858 /* Restore any saved registers, in reverse order of course. */
1859 gmask
&= ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
);
1860 for (regno
= M32R_MAX_INT_REGS
- 1; regno
>= 0; --regno
)
1862 if ((gmask
& (1L << regno
)) != 0)
1866 if (current_frame_info
.save_fp
)
1867 pop (FRAME_POINTER_REGNUM
);
1869 /* Remove varargs area if present. */
1870 if (current_frame_info
.pretend_size
!= 0)
1871 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
1872 GEN_INT (current_frame_info
.pretend_size
)));
1874 emit_insn (gen_blockage ());
1878 /* Do any necessary cleanup after a function to restore stack, frame,
1882 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED
,
1883 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1885 /* Reset state info for each function. */
1886 current_frame_info
= zero_frame_info
;
1887 m32r_compute_function_type (NULL_TREE
);
1890 /* Return nonzero if this function is known to have a null or 1 instruction
1894 direct_return (void)
1896 if (!reload_completed
)
1899 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl
)))
1902 if (! current_frame_info
.initialized
)
1903 m32r_compute_frame_size (get_frame_size ());
1905 return current_frame_info
.total_size
== 0;
1912 m32r_legitimate_pic_operand_p (rtx x
)
1914 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1917 if (GET_CODE (x
) == CONST
1918 && GET_CODE (XEXP (x
, 0)) == PLUS
1919 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1920 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
1921 && (CONST_INT_P (XEXP (XEXP (x
, 0), 1))))
1928 m32r_legitimize_pic_address (rtx orig
, rtx reg
)
1931 printf("m32r_legitimize_pic_address()\n");
1934 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1936 rtx pic_ref
, address
;
1941 gcc_assert (!reload_in_progress
&& !reload_completed
);
1942 reg
= gen_reg_rtx (Pmode
);
1948 address
= gen_reg_rtx (Pmode
);
1952 crtl
->uses_pic_offset_table
= 1;
1954 if (GET_CODE (orig
) == LABEL_REF
1955 || (GET_CODE (orig
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig
)))
1957 emit_insn (gen_gotoff_load_addr (reg
, orig
));
1958 emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1962 emit_insn (gen_pic_load_addr (address
, orig
));
1964 emit_insn (gen_addsi3 (address
, address
, pic_offset_table_rtx
));
1965 pic_ref
= gen_const_mem (Pmode
, address
);
1966 emit_move_insn (reg
, pic_ref
);
1969 else if (GET_CODE (orig
) == CONST
)
1973 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1974 && XEXP (XEXP (orig
, 0), 1) == pic_offset_table_rtx
)
1979 gcc_assert (!reload_in_progress
&& !reload_completed
);
1980 reg
= gen_reg_rtx (Pmode
);
1983 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1985 base
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
1987 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), NULL_RTX
);
1989 offset
= m32r_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), reg
);
1994 if (CONST_INT_P (offset
))
1996 if (INT16_P (INTVAL (offset
)))
1997 return plus_constant (Pmode
, base
, INTVAL (offset
));
2000 gcc_assert (! reload_in_progress
&& ! reload_completed
);
2001 offset
= force_reg (Pmode
, offset
);
2005 return gen_rtx_PLUS (Pmode
, base
, offset
);
2012 m32r_legitimize_address (rtx x
, rtx orig_x ATTRIBUTE_UNUSED
,
2013 machine_mode mode ATTRIBUTE_UNUSED
)
2016 return m32r_legitimize_pic_address (x
, NULL_RTX
);
2021 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */
2024 m32r_mode_dependent_address_p (const_rtx addr
, addr_space_t as ATTRIBUTE_UNUSED
)
2026 if (GET_CODE (addr
) == LO_SUM
)
2032 /* Nested function support. */
2034 /* Emit RTL insns to initialize the variable parts of a trampoline.
2035 FNADDR is an RTX for the address of the function's pure code.
2036 CXT is an RTX for the static chain value for the function. */
2039 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED
,
2040 rtx fnaddr ATTRIBUTE_UNUSED
,
2041 rtx cxt ATTRIBUTE_UNUSED
)
2046 m32r_file_start (void)
2048 default_file_start ();
2050 if (flag_verbose_asm
)
2051 fprintf (asm_out_file
,
2052 "%s M32R/D special options: -G %d\n",
2053 ASM_COMMENT_START
, g_switch_value
);
2055 if (TARGET_LITTLE_ENDIAN
)
2056 fprintf (asm_out_file
, "\t.little\n");
2059 /* Print operand X (an rtx) in assembler syntax to file FILE.
2060 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2061 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2064 m32r_print_operand (FILE * file
, rtx x
, int code
)
2070 /* The 's' and 'p' codes are used by output_block_move() to
2071 indicate post-increment 's'tores and 'p're-increment loads. */
2074 fprintf (file
, "@+%s", reg_names
[REGNO (x
)]);
2076 output_operand_lossage ("invalid operand to %%s code");
2081 fprintf (file
, "@%s+", reg_names
[REGNO (x
)]);
2083 output_operand_lossage ("invalid operand to %%p code");
2087 /* Write second word of DImode or DFmode reference,
2088 register or memory. */
2090 fputs (reg_names
[REGNO (x
)+1], file
);
2093 machine_mode mode
= GET_MODE (x
);
2095 fprintf (file
, "@(");
2096 /* Handle possible auto-increment. Since it is pre-increment and
2097 we have already done it, we can just use an offset of four. */
2098 /* ??? This is taken from rs6000.c I think. I don't think it is
2099 currently necessary, but keep it around. */
2100 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2101 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2102 output_address (mode
, plus_constant (Pmode
,
2103 XEXP (XEXP (x
, 0), 0), 4));
2105 output_address (mode
, plus_constant (Pmode
, XEXP (x
, 0), 4));
2109 output_operand_lossage ("invalid operand to %%R code");
2112 case 'H' : /* High word. */
2113 case 'L' : /* Low word. */
2116 /* L = least significant word, H = most significant word. */
2117 if ((WORDS_BIG_ENDIAN
!= 0) ^ (code
== 'L'))
2118 fputs (reg_names
[REGNO (x
)], file
);
2120 fputs (reg_names
[REGNO (x
)+1], file
);
2122 else if (CONST_INT_P (x
)
2123 || GET_CODE (x
) == CONST_DOUBLE
)
2127 split_double (x
, &first
, &second
);
2128 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2129 code
== 'L' ? INTVAL (first
) : INTVAL (second
));
2132 output_operand_lossage ("invalid operand to %%H/%%L code");
2139 if (GET_CODE (x
) != CONST_DOUBLE
2140 || GET_MODE_CLASS (GET_MODE (x
)) != MODE_FLOAT
)
2141 fatal_insn ("bad insn for 'A'", x
);
2143 real_to_decimal (str
, CONST_DOUBLE_REAL_VALUE (x
), sizeof (str
), 0, 1);
2144 fprintf (file
, "%s", str
);
2148 case 'B' : /* Bottom half. */
2149 case 'T' : /* Top half. */
2150 /* Output the argument to a `seth' insn (sets the Top half-word).
2151 For constants output arguments to a seth/or3 pair to set Top and
2152 Bottom halves. For symbols output arguments to a seth/add3 pair to
2153 set Top and Bottom halves. The difference exists because for
2154 constants seth/or3 is more readable but for symbols we need to use
2155 the same scheme as `ld' and `st' insns (16-bit addend is signed). */
2156 switch (GET_CODE (x
))
2163 split_double (x
, &first
, &second
);
2164 x
= WORDS_BIG_ENDIAN
? second
: first
;
2165 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
2167 ? INTVAL (x
) & 0xffff
2168 : (INTVAL (x
) >> 16) & 0xffff));
2174 && small_data_operand (x
, VOIDmode
))
2176 fputs ("sda(", file
);
2177 output_addr_const (file
, x
);
2183 fputs (code
== 'T' ? "shigh(" : "low(", file
);
2184 output_addr_const (file
, x
);
2188 output_operand_lossage ("invalid operand to %%T/%%B code");
2195 /* Output a load/store with update indicator if appropriate. */
2198 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
2199 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
2203 output_operand_lossage ("invalid operand to %%U code");
2207 /* Print a constant value negated. */
2208 if (CONST_INT_P (x
))
2209 output_addr_const (file
, GEN_INT (- INTVAL (x
)));
2211 output_operand_lossage ("invalid operand to %%N code");
2215 /* Print a const_int in hex. Used in comments. */
2216 if (CONST_INT_P (x
))
2217 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
2221 fputs (IMMEDIATE_PREFIX
, file
);
2225 /* Do nothing special. */
2230 output_operand_lossage ("invalid operand output code");
2233 switch (GET_CODE (x
))
2236 fputs (reg_names
[REGNO (x
)], file
);
2241 if (GET_CODE (addr
) == PRE_INC
)
2243 if (!REG_P (XEXP (addr
, 0)))
2244 fatal_insn ("pre-increment address is not a register", x
);
2246 fprintf (file
, "@+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2248 else if (GET_CODE (addr
) == PRE_DEC
)
2250 if (!REG_P (XEXP (addr
, 0)))
2251 fatal_insn ("pre-decrement address is not a register", x
);
2253 fprintf (file
, "@-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2255 else if (GET_CODE (addr
) == POST_INC
)
2257 if (!REG_P (XEXP (addr
, 0)))
2258 fatal_insn ("post-increment address is not a register", x
);
2260 fprintf (file
, "@%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2265 output_address (GET_MODE (x
), addr
);
2271 /* We handle SFmode constants here as output_addr_const doesn't. */
2272 if (GET_MODE (x
) == SFmode
)
2276 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
2277 fprintf (file
, "0x%08lx", l
);
2281 /* Fall through. Let output_addr_const deal with it. */
2284 output_addr_const (file
, x
);
2289 /* Print a memory address as an operand to reference that memory location. */
2292 m32r_print_operand_address (FILE * file
, machine_mode
/*mode*/, rtx addr
)
2298 switch (GET_CODE (addr
))
2301 fputs (reg_names
[REGNO (addr
)], file
);
2305 if (CONST_INT_P (XEXP (addr
, 0)))
2306 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
2307 else if (CONST_INT_P (XEXP (addr
, 1)))
2308 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
2310 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
2313 /* Print the offset first (if present) to conform to the manual. */
2317 fprintf (file
, "%d,", offset
);
2318 fputs (reg_names
[REGNO (base
)], file
);
2320 /* The chip doesn't support this, but left in for generality. */
2321 else if (REG_P (index
))
2322 fprintf (file
, "%s,%s",
2323 reg_names
[REGNO (base
)], reg_names
[REGNO (index
)]);
2324 /* Not sure this can happen, but leave in for now. */
2325 else if (GET_CODE (index
) == SYMBOL_REF
)
2327 output_addr_const (file
, index
);
2329 fputs (reg_names
[REGNO (base
)], file
);
2332 fatal_insn ("bad address", addr
);
2334 else if (GET_CODE (base
) == LO_SUM
)
2336 gcc_assert (!index
&& REG_P (XEXP (base
, 0)));
2337 if (small_data_operand (XEXP (base
, 1), VOIDmode
))
2338 fputs ("sda(", file
);
2340 fputs ("low(", file
);
2341 output_addr_const (file
, plus_constant (Pmode
, XEXP (base
, 1),
2344 fputs (reg_names
[REGNO (XEXP (base
, 0))], file
);
2347 fatal_insn ("bad address", addr
);
2351 if (!REG_P (XEXP (addr
, 0)))
2352 fatal_insn ("lo_sum not of register", addr
);
2353 if (small_data_operand (XEXP (addr
, 1), VOIDmode
))
2354 fputs ("sda(", file
);
2356 fputs ("low(", file
);
2357 output_addr_const (file
, XEXP (addr
, 1));
2359 fputs (reg_names
[REGNO (XEXP (addr
, 0))], file
);
2362 case PRE_INC
: /* Assume SImode. */
2363 fprintf (file
, "+%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2366 case PRE_DEC
: /* Assume SImode. */
2367 fprintf (file
, "-%s", reg_names
[REGNO (XEXP (addr
, 0))]);
2370 case POST_INC
: /* Assume SImode. */
2371 fprintf (file
, "%s+", reg_names
[REGNO (XEXP (addr
, 0))]);
2375 output_addr_const (file
, addr
);
2381 m32r_print_operand_punct_valid_p (unsigned char code
)
2383 return m32r_punct_chars
[code
];
2386 /* Return true if the operands are the constants 0 and 1. */
2389 zero_and_one (rtx operand1
, rtx operand2
)
2392 CONST_INT_P (operand1
)
2393 && CONST_INT_P (operand2
)
2394 && ( ((INTVAL (operand1
) == 0) && (INTVAL (operand2
) == 1))
2395 ||((INTVAL (operand1
) == 1) && (INTVAL (operand2
) == 0)));
2398 /* Generate the correct assembler code to handle the conditional loading of a
2399 value into a register. It is known that the operands satisfy the
2400 conditional_move_operand() function above. The destination is operand[0].
2401 The condition is operand [1]. The 'true' value is operand [2] and the
2402 'false' value is operand [3]. */
2405 emit_cond_move (rtx
* operands
, rtx insn ATTRIBUTE_UNUSED
)
2407 static char buffer
[100];
2408 const char * dest
= reg_names
[REGNO (operands
[0])];
2412 /* Destination must be a register. */
2413 gcc_assert (REG_P (operands
[0]));
2414 gcc_assert (conditional_move_operand (operands
[2], SImode
));
2415 gcc_assert (conditional_move_operand (operands
[3], SImode
));
2417 /* Check to see if the test is reversed. */
2418 if (GET_CODE (operands
[1]) == NE
)
2420 rtx tmp
= operands
[2];
2421 operands
[2] = operands
[3];
2425 sprintf (buffer
, "mvfc %s, cbr", dest
);
2427 /* If the true value was '0' then we need to invert the results of the move. */
2428 if (INTVAL (operands
[2]) == 0)
2429 sprintf (buffer
+ strlen (buffer
), "\n\txor3 %s, %s, #1",
2435 /* Returns true if the registers contained in the two
2436 rtl expressions are different. */
2439 m32r_not_same_reg (rtx a
, rtx b
)
2444 while (GET_CODE (a
) == SUBREG
)
2450 while (GET_CODE (b
) == SUBREG
)
2456 return reg_a
!= reg_b
;
2461 m32r_function_symbol (const char *name
)
2463 int extra_flags
= 0;
2464 enum m32r_model model
;
2465 rtx sym
= gen_rtx_SYMBOL_REF (Pmode
, name
);
2467 if (TARGET_MODEL_SMALL
)
2468 model
= M32R_MODEL_SMALL
;
2469 else if (TARGET_MODEL_MEDIUM
)
2470 model
= M32R_MODEL_MEDIUM
;
2471 else if (TARGET_MODEL_LARGE
)
2472 model
= M32R_MODEL_LARGE
;
2474 gcc_unreachable (); /* Shouldn't happen. */
2475 extra_flags
|= model
<< SYMBOL_FLAG_MODEL_SHIFT
;
2478 SYMBOL_REF_FLAGS (sym
) |= extra_flags
;
2483 /* Use a library function to move some bytes. */
2486 block_move_call (rtx dest_reg
, rtx src_reg
, rtx bytes_rtx
)
2488 /* We want to pass the size as Pmode, which will normally be SImode
2489 but will be DImode if we are using 64-bit longs and pointers. */
2490 if (GET_MODE (bytes_rtx
) != VOIDmode
2491 && GET_MODE (bytes_rtx
) != Pmode
)
2492 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2494 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL
,
2495 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2496 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2497 TYPE_UNSIGNED (sizetype
)),
2498 TYPE_MODE (sizetype
));
2501 /* Expand string/block move operations.
2503 operands[0] is the pointer to the destination.
2504 operands[1] is the pointer to the source.
2505 operands[2] is the number of bytes to move.
2506 operands[3] is the alignment.
2508 Returns 1 upon success, 0 otherwise. */
2511 m32r_expand_block_move (rtx operands
[])
2513 rtx orig_dst
= operands
[0];
2514 rtx orig_src
= operands
[1];
2515 rtx bytes_rtx
= operands
[2];
2516 rtx align_rtx
= operands
[3];
2517 int constp
= CONST_INT_P (bytes_rtx
);
2518 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2519 int align
= INTVAL (align_rtx
);
2524 if (constp
&& bytes
<= 0)
2527 /* Move the address into scratch registers. */
2528 dst_reg
= copy_addr_to_reg (XEXP (orig_dst
, 0));
2529 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2531 if (align
> UNITS_PER_WORD
)
2532 align
= UNITS_PER_WORD
;
2534 /* If we prefer size over speed, always use a function call.
2535 If we do not know the size, use a function call.
2536 If the blocks are not word aligned, use a function call. */
2537 if (optimize_size
|| ! constp
|| align
!= UNITS_PER_WORD
)
2539 block_move_call (dst_reg
, src_reg
, bytes_rtx
);
2543 leftover
= bytes
% MAX_MOVE_BYTES
;
2546 /* If necessary, generate a loop to handle the bulk of the copy. */
2549 rtx_code_label
*label
= NULL
;
2550 rtx final_src
= NULL_RTX
;
2551 rtx at_a_time
= GEN_INT (MAX_MOVE_BYTES
);
2552 rtx rounded_total
= GEN_INT (bytes
);
2553 rtx new_dst_reg
= gen_reg_rtx (SImode
);
2554 rtx new_src_reg
= gen_reg_rtx (SImode
);
2556 /* If we are going to have to perform this loop more than
2557 once, then generate a label and compute the address the
2558 source register will contain upon completion of the final
2560 if (bytes
> MAX_MOVE_BYTES
)
2562 final_src
= gen_reg_rtx (Pmode
);
2565 emit_insn (gen_addsi3 (final_src
, src_reg
, rounded_total
));
2568 emit_insn (gen_movsi (final_src
, rounded_total
));
2569 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2572 label
= gen_label_rtx ();
2576 /* It is known that output_block_move() will update src_reg to point
2577 to the word after the end of the source block, and dst_reg to point
2578 to the last word of the destination block, provided that the block
2579 is MAX_MOVE_BYTES long. */
2580 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, at_a_time
,
2581 new_dst_reg
, new_src_reg
));
2582 emit_move_insn (dst_reg
, new_dst_reg
);
2583 emit_move_insn (src_reg
, new_src_reg
);
2584 emit_insn (gen_addsi3 (dst_reg
, dst_reg
, GEN_INT (4)));
2586 if (bytes
> MAX_MOVE_BYTES
)
2588 rtx test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
2589 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
2594 emit_insn (gen_movmemsi_internal (dst_reg
, src_reg
, GEN_INT (leftover
),
2595 gen_reg_rtx (SImode
),
2596 gen_reg_rtx (SImode
)));
2601 /* Emit load/stores for a small constant word aligned block_move.
2603 operands[0] is the memory address of the destination.
2604 operands[1] is the memory address of the source.
2605 operands[2] is the number of bytes to move.
2606 operands[3] is a temp register.
2607 operands[4] is a temp register. */
2610 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
2612 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2616 gcc_assert (bytes
>= 1 && bytes
<= MAX_MOVE_BYTES
);
2618 /* We do not have a post-increment store available, so the first set of
2619 stores are done without any increment, then the remaining ones can use
2620 the pre-increment addressing mode.
2622 Note: expand_block_move() also relies upon this behavior when building
2623 loops to copy large blocks. */
2632 output_asm_insn ("ld\t%5, %p1", operands
);
2633 output_asm_insn ("ld\t%6, %p1", operands
);
2634 output_asm_insn ("st\t%5, @%0", operands
);
2635 output_asm_insn ("st\t%6, %s0", operands
);
2639 output_asm_insn ("ld\t%5, %p1", operands
);
2640 output_asm_insn ("ld\t%6, %p1", operands
);
2641 output_asm_insn ("st\t%5, %s0", operands
);
2642 output_asm_insn ("st\t%6, %s0", operands
);
2647 else if (bytes
>= 4)
2652 output_asm_insn ("ld\t%5, %p1", operands
);
2655 output_asm_insn ("ld\t%6, %p1", operands
);
2658 output_asm_insn ("st\t%5, @%0", operands
);
2660 output_asm_insn ("st\t%5, %s0", operands
);
2666 /* Get the entire next word, even though we do not want all of it.
2667 The saves us from doing several smaller loads, and we assume that
2668 we cannot cause a page fault when at least part of the word is in
2669 valid memory [since we don't get called if things aren't properly
2671 int dst_offset
= first_time
? 0 : 4;
2672 /* The amount of increment we have to make to the
2673 destination pointer. */
2674 int dst_inc_amount
= dst_offset
+ bytes
- 4;
2675 /* The same for the source pointer. */
2676 int src_inc_amount
= bytes
;
2680 /* If got_extra is true then we have already loaded
2681 the next word as part of loading and storing the previous word. */
2683 output_asm_insn ("ld\t%6, @%1", operands
);
2689 output_asm_insn ("sra3\t%5, %6, #16", operands
);
2690 my_operands
[0] = operands
[5];
2691 my_operands
[1] = GEN_INT (dst_offset
);
2692 my_operands
[2] = operands
[0];
2693 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands
);
2695 /* If there is a byte left to store then increment the
2696 destination address and shift the contents of the source
2697 register down by 8 bits. We could not do the address
2698 increment in the store half word instruction, because it does
2699 not have an auto increment mode. */
2700 if (bytes
> 0) /* assert (bytes == 1) */
2711 my_operands
[0] = operands
[6];
2712 my_operands
[1] = GEN_INT (last_shift
);
2713 output_asm_insn ("srai\t%0, #%1", my_operands
);
2714 my_operands
[0] = operands
[6];
2715 my_operands
[1] = GEN_INT (dst_offset
);
2716 my_operands
[2] = operands
[0];
2717 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands
);
2720 /* Update the destination pointer if needed. We have to do
2721 this so that the patterns matches what we output in this
2724 && !find_reg_note (insn
, REG_UNUSED
, operands
[0]))
2726 my_operands
[0] = operands
[0];
2727 my_operands
[1] = GEN_INT (dst_inc_amount
);
2728 output_asm_insn ("addi\t%0, #%1", my_operands
);
2731 /* Update the source pointer if needed. We have to do this
2732 so that the patterns matches what we output in this
2735 && !find_reg_note (insn
, REG_UNUSED
, operands
[1]))
2737 my_operands
[0] = operands
[1];
2738 my_operands
[1] = GEN_INT (src_inc_amount
);
2739 output_asm_insn ("addi\t%0, #%1", my_operands
);
2749 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2752 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
2753 unsigned int new_reg
)
2755 /* Interrupt routines can't clobber any register that isn't already used. */
2756 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl
))
2757 && !df_regs_ever_live_p (new_reg
))
2764 m32r_return_addr (int count
)
2769 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
2773 m32r_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2775 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
2776 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2777 0x017e8e17 : 0x178e7e01, SImode
));
2778 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
2779 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2780 0x0c00ae86 : 0x86ae000c, SImode
));
2781 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
2782 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2783 0xe627871e : 0x1e8727e6, SImode
));
2784 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
2785 gen_int_mode (TARGET_LITTLE_ENDIAN
?
2786 0xc616c626 : 0x26c61fc6, SImode
));
2787 emit_move_insn (adjust_address (m_tramp
, SImode
, 16),
2789 emit_move_insn (adjust_address (m_tramp
, SImode
, 20),
2790 XEXP (DECL_RTL (fndecl
), 0));
2792 if (m32r_cache_flush_trap
>= 0)
2793 emit_insn (gen_flush_icache
2794 (validize_mem (adjust_address (m_tramp
, SImode
, 0)),
2795 gen_int_mode (m32r_cache_flush_trap
, SImode
)));
2796 else if (m32r_cache_flush_func
&& m32r_cache_flush_func
[0])
2797 emit_library_call (m32r_function_symbol (m32r_cache_flush_func
),
2798 LCT_NORMAL
, VOIDmode
, 3, XEXP (m_tramp
, 0), Pmode
,
2799 gen_int_mode (TRAMPOLINE_SIZE
, SImode
), SImode
,
2800 GEN_INT (3), SImode
);
2803 /* True if X is a reg that can be used as a base reg. */
2806 m32r_rtx_ok_for_base_p (const_rtx x
, bool strict
)
2813 if (GPR_P (REGNO (x
)))
2818 if (GPR_P (REGNO (x
))
2819 || REGNO (x
) == ARG_POINTER_REGNUM
2820 || ! HARD_REGISTER_P (x
))
2828 m32r_rtx_ok_for_offset_p (const_rtx x
)
2830 return (CONST_INT_P (x
) && INT16_P (INTVAL (x
)));
2834 m32r_legitimate_offset_addres_p (machine_mode mode ATTRIBUTE_UNUSED
,
2835 const_rtx x
, bool strict
)
2837 if (GET_CODE (x
) == PLUS
2838 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2839 && m32r_rtx_ok_for_offset_p (XEXP (x
, 1)))
2845 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word,
2846 since more than one instruction will be required. */
2849 m32r_legitimate_lo_sum_addres_p (machine_mode mode
, const_rtx x
,
2852 if (GET_CODE (x
) == LO_SUM
2853 && (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2854 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
)
2855 && CONSTANT_P (XEXP (x
, 1)))
2861 /* Is this a load and increment operation. */
2864 m32r_load_postinc_p (machine_mode mode
, const_rtx x
, bool strict
)
2866 if ((mode
== SImode
|| mode
== SFmode
)
2867 && GET_CODE (x
) == POST_INC
2868 && REG_P (XEXP (x
, 0))
2869 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2875 /* Is this an increment/decrement and store operation. */
2878 m32r_store_preinc_predec_p (machine_mode mode
, const_rtx x
, bool strict
)
2880 if ((mode
== SImode
|| mode
== SFmode
)
2881 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
2882 && REG_P (XEXP (x
, 0)) \
2883 && m32r_rtx_ok_for_base_p (XEXP (x
, 0), strict
))
2889 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2892 m32r_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
2894 if (m32r_rtx_ok_for_base_p (x
, strict
)
2895 || m32r_legitimate_offset_addres_p (mode
, x
, strict
)
2896 || m32r_legitimate_lo_sum_addres_p (mode
, x
, strict
)
2897 || m32r_load_postinc_p (mode
, x
, strict
)
2898 || m32r_store_preinc_predec_p (mode
, x
, strict
))
2905 m32r_conditional_register_usage (void)
2909 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2910 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2914 /* Implement TARGET_LEGITIMATE_CONSTANT_P
2916 We don't allow (plus symbol large-constant) as the relocations can't
2917 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations.
2918 We allow all CONST_DOUBLE's as the md file patterns will force the
2919 constant to memory if they can't handle them. */
2922 m32r_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2924 return !(GET_CODE (x
) == CONST
2925 && GET_CODE (XEXP (x
, 0)) == PLUS
2926 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
2927 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)
2928 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
2929 && UINTVAL (XEXP (XEXP (x
, 0), 1)) > 32767);