1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #define IN_TARGET_CODE 1
24 #include "coretypes.h"
28 #include "stringpool.h"
33 #include "fold-const.h"
35 #include "stor-layout.h"
38 #include "insn-config.h"
39 #include "conditions.h"
41 #include "insn-attr.h"
43 #include "diagnostic-core.h"
60 #include "cfgcleanup.h"
61 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
62 #include "sched-int.h"
63 #include "insn-codes.h"
69 /* This file should be included last. */
70 #include "target-def.h"
72 enum reg_class regno_reg_class
[] =
74 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
75 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
76 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
77 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
78 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
79 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
84 /* The minimum number of integer registers that we want to save with the
85 movem instruction. Using two movel instructions instead of a single
86 moveml is about 15% faster for the 68020 and 68030 at no expense in
88 #define MIN_MOVEM_REGS 3
90 /* The minimum number of floating point registers that we want to save
91 with the fmovem instruction. */
92 #define MIN_FMOVEM_REGS 1
94 /* Structure describing stack frame layout. */
97 /* Stack pointer to frame pointer offset. */
100 /* Offset of FPU registers. */
101 HOST_WIDE_INT foffset
;
103 /* Frame size in bytes (rounded up). */
106 /* Data and address register. */
108 unsigned int reg_mask
;
112 unsigned int fpu_mask
;
114 /* Offsets relative to ARG_POINTER. */
115 HOST_WIDE_INT frame_pointer_offset
;
116 HOST_WIDE_INT stack_pointer_offset
;
118 /* Function which the above information refers to. */
122 /* Current frame information calculated by m68k_compute_frame_layout(). */
123 static struct m68k_frame current_frame
;
125 /* Structure describing an m68k address.
127 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
128 with null fields evaluating to 0. Here:
130 - BASE satisfies m68k_legitimate_base_reg_p
131 - INDEX satisfies m68k_legitimate_index_reg_p
132 - OFFSET satisfies m68k_legitimate_constant_address_p
134 INDEX is either HImode or SImode. The other fields are SImode.
136 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
137 the address is (BASE)+. */
138 struct m68k_address
{
146 static int m68k_sched_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
148 static int m68k_sched_issue_rate (void);
149 static int m68k_sched_variable_issue (FILE *, int, rtx_insn
*, int);
150 static void m68k_sched_md_init_global (FILE *, int, int);
151 static void m68k_sched_md_finish_global (FILE *, int);
152 static void m68k_sched_md_init (FILE *, int, int);
153 static void m68k_sched_dfa_pre_advance_cycle (void);
154 static void m68k_sched_dfa_post_advance_cycle (void);
155 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
157 static bool m68k_can_eliminate (const int, const int);
158 static void m68k_conditional_register_usage (void);
159 static bool m68k_legitimate_address_p (machine_mode
, rtx
, bool);
160 static void m68k_option_override (void);
161 static void m68k_override_options_after_change (void);
162 static rtx
find_addr_reg (rtx
);
163 static const char *singlemove_string (rtx
*);
164 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
165 HOST_WIDE_INT
, tree
);
166 static rtx
m68k_struct_value_rtx (tree
, int);
167 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
168 tree args
, int flags
,
170 static void m68k_compute_frame_layout (void);
171 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
172 static bool m68k_ok_for_sibcall_p (tree
, tree
);
173 static bool m68k_tls_symbol_p (rtx
);
174 static rtx
m68k_legitimize_address (rtx
, rtx
, machine_mode
);
175 static bool m68k_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
176 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
177 static bool m68k_return_in_memory (const_tree
, const_tree
);
179 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
180 static void m68k_trampoline_init (rtx
, tree
, rtx
);
181 static poly_int64
m68k_return_pops_args (tree
, tree
, poly_int64
);
182 static rtx
m68k_delegitimize_address (rtx
);
183 static void m68k_function_arg_advance (cumulative_args_t
, machine_mode
,
185 static rtx
m68k_function_arg (cumulative_args_t
, machine_mode
,
187 static bool m68k_cannot_force_const_mem (machine_mode mode
, rtx x
);
188 static bool m68k_output_addr_const_extra (FILE *, rtx
);
189 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED
;
190 static enum flt_eval_method
191 m68k_excess_precision (enum excess_precision_type
);
192 static unsigned int m68k_hard_regno_nregs (unsigned int, machine_mode
);
193 static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode
);
194 static bool m68k_modes_tieable_p (machine_mode
, machine_mode
);
196 /* Initialize the GCC target structure. */
198 #if INT_OP_GROUP == INT_OP_DOT_WORD
199 #undef TARGET_ASM_ALIGNED_HI_OP
200 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
203 #if INT_OP_GROUP == INT_OP_NO_DOT
204 #undef TARGET_ASM_BYTE_OP
205 #define TARGET_ASM_BYTE_OP "\tbyte\t"
206 #undef TARGET_ASM_ALIGNED_HI_OP
207 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
208 #undef TARGET_ASM_ALIGNED_SI_OP
209 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
212 #if INT_OP_GROUP == INT_OP_DC
213 #undef TARGET_ASM_BYTE_OP
214 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
215 #undef TARGET_ASM_ALIGNED_HI_OP
216 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
217 #undef TARGET_ASM_ALIGNED_SI_OP
218 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
221 #undef TARGET_ASM_UNALIGNED_HI_OP
222 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
223 #undef TARGET_ASM_UNALIGNED_SI_OP
224 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
226 #undef TARGET_ASM_OUTPUT_MI_THUNK
227 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
228 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
229 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
231 #undef TARGET_ASM_FILE_START_APP_OFF
232 #define TARGET_ASM_FILE_START_APP_OFF true
234 #undef TARGET_LEGITIMIZE_ADDRESS
235 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
237 #undef TARGET_SCHED_ADJUST_COST
238 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
240 #undef TARGET_SCHED_ISSUE_RATE
241 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
243 #undef TARGET_SCHED_VARIABLE_ISSUE
244 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
246 #undef TARGET_SCHED_INIT_GLOBAL
247 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
249 #undef TARGET_SCHED_FINISH_GLOBAL
250 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
252 #undef TARGET_SCHED_INIT
253 #define TARGET_SCHED_INIT m68k_sched_md_init
255 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
256 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
258 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
259 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
261 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
262 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
263 m68k_sched_first_cycle_multipass_dfa_lookahead
265 #undef TARGET_OPTION_OVERRIDE
266 #define TARGET_OPTION_OVERRIDE m68k_option_override
268 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
269 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
271 #undef TARGET_RTX_COSTS
272 #define TARGET_RTX_COSTS m68k_rtx_costs
274 #undef TARGET_ATTRIBUTE_TABLE
275 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
277 #undef TARGET_PROMOTE_PROTOTYPES
278 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
280 #undef TARGET_STRUCT_VALUE_RTX
281 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
283 #undef TARGET_CANNOT_FORCE_CONST_MEM
284 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
286 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
287 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
289 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
290 #undef TARGET_RETURN_IN_MEMORY
291 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
295 #undef TARGET_HAVE_TLS
296 #define TARGET_HAVE_TLS (true)
298 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
299 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
303 #define TARGET_LRA_P hook_bool_void_false
305 #undef TARGET_LEGITIMATE_ADDRESS_P
306 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
308 #undef TARGET_CAN_ELIMINATE
309 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
311 #undef TARGET_CONDITIONAL_REGISTER_USAGE
312 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
314 #undef TARGET_TRAMPOLINE_INIT
315 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
317 #undef TARGET_RETURN_POPS_ARGS
318 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
320 #undef TARGET_DELEGITIMIZE_ADDRESS
321 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
323 #undef TARGET_FUNCTION_ARG
324 #define TARGET_FUNCTION_ARG m68k_function_arg
326 #undef TARGET_FUNCTION_ARG_ADVANCE
327 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
329 #undef TARGET_LEGITIMATE_CONSTANT_P
330 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
332 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
333 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
335 #undef TARGET_C_EXCESS_PRECISION
336 #define TARGET_C_EXCESS_PRECISION m68k_excess_precision
338 /* The value stored by TAS. */
339 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
340 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
342 #undef TARGET_HARD_REGNO_NREGS
343 #define TARGET_HARD_REGNO_NREGS m68k_hard_regno_nregs
344 #undef TARGET_HARD_REGNO_MODE_OK
345 #define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
347 #undef TARGET_MODES_TIEABLE_P
348 #define TARGET_MODES_TIEABLE_P m68k_modes_tieable_p
350 static const struct attribute_spec m68k_attribute_table
[] =
352 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
353 affects_type_identity, handler, exclude } */
354 { "interrupt", 0, 0, true, false, false, false,
355 m68k_handle_fndecl_attribute
, NULL
},
356 { "interrupt_handler", 0, 0, true, false, false, false,
357 m68k_handle_fndecl_attribute
, NULL
},
358 { "interrupt_thread", 0, 0, true, false, false, false,
359 m68k_handle_fndecl_attribute
, NULL
},
360 { NULL
, 0, 0, false, false, false, false, NULL
, NULL
}
363 struct gcc_target targetm
= TARGET_INITIALIZER
;
365 /* Base flags for 68k ISAs. */
366 #define FL_FOR_isa_00 FL_ISA_68000
367 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
368 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
369 generated 68881 code for 68020 and 68030 targets unless explicitly told
371 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
372 | FL_BITFIELD | FL_68881 | FL_CAS)
373 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
374 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
376 /* Base flags for ColdFire ISAs. */
377 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
378 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
379 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
380 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
381 /* ISA_C is not upwardly compatible with ISA_B. */
382 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
386 /* Traditional 68000 instruction sets. */
392 /* ColdFire instruction set variants. */
400 /* Information about one of the -march, -mcpu or -mtune arguments. */
401 struct m68k_target_selection
403 /* The argument being described. */
406 /* For -mcpu, this is the device selected by the option.
407 For -mtune and -march, it is a representative device
408 for the microarchitecture or ISA respectively. */
409 enum target_device device
;
411 /* The M68K_DEVICE fields associated with DEVICE. See the comment
412 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
414 enum uarch_type microarch
;
419 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
420 static const struct m68k_target_selection all_devices
[] =
422 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
423 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
424 #include "m68k-devices.def"
426 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
429 /* A list of all ISAs, mapping each one to a representative device.
430 Used for -march selection. */
431 static const struct m68k_target_selection all_isas
[] =
433 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
434 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
435 #include "m68k-isas.def"
437 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
440 /* A list of all microarchitectures, mapping each one to a representative
441 device. Used for -mtune selection. */
442 static const struct m68k_target_selection all_microarchs
[] =
444 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
445 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
446 #include "m68k-microarchs.def"
447 #undef M68K_MICROARCH
448 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
451 /* The entries associated with the -mcpu, -march and -mtune settings,
452 or null for options that have not been used. */
453 const struct m68k_target_selection
*m68k_cpu_entry
;
454 const struct m68k_target_selection
*m68k_arch_entry
;
455 const struct m68k_target_selection
*m68k_tune_entry
;
457 /* Which CPU we are generating code for. */
458 enum target_device m68k_cpu
;
460 /* Which microarchitecture to tune for. */
461 enum uarch_type m68k_tune
;
463 /* Which FPU to use. */
464 enum fpu_type m68k_fpu
;
466 /* The set of FL_* flags that apply to the target processor. */
467 unsigned int m68k_cpu_flags
;
469 /* The set of FL_* flags that apply to the processor to be tuned for. */
470 unsigned int m68k_tune_flags
;
472 /* Asm templates for calling or jumping to an arbitrary symbolic address,
473 or NULL if such calls or jumps are not supported. The address is held
475 const char *m68k_symbolic_call
;
476 const char *m68k_symbolic_jump
;
478 /* Enum variable that corresponds to m68k_symbolic_call values. */
479 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
482 /* Implement TARGET_OPTION_OVERRIDE. */
485 m68k_option_override (void)
487 const struct m68k_target_selection
*entry
;
488 unsigned long target_mask
;
490 if (global_options_set
.x_m68k_arch_option
)
491 m68k_arch_entry
= &all_isas
[m68k_arch_option
];
493 if (global_options_set
.x_m68k_cpu_option
)
494 m68k_cpu_entry
= &all_devices
[(int) m68k_cpu_option
];
496 if (global_options_set
.x_m68k_tune_option
)
497 m68k_tune_entry
= &all_microarchs
[(int) m68k_tune_option
];
505 -march=ARCH should generate code that runs any processor
506 implementing architecture ARCH. -mcpu=CPU should override -march
507 and should generate code that runs on processor CPU, making free
508 use of any instructions that CPU understands. -mtune=UARCH applies
509 on top of -mcpu or -march and optimizes the code for UARCH. It does
510 not change the target architecture. */
513 /* Complain if the -march setting is for a different microarchitecture,
514 or includes flags that the -mcpu setting doesn't. */
516 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
517 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
518 warning (0, "-mcpu=%s conflicts with -march=%s",
519 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
521 entry
= m68k_cpu_entry
;
524 entry
= m68k_arch_entry
;
527 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
529 m68k_cpu_flags
= entry
->flags
;
531 /* Use the architecture setting to derive default values for
535 /* ColdFire is lenient about alignment. */
536 if (!TARGET_COLDFIRE
)
537 target_mask
|= MASK_STRICT_ALIGNMENT
;
539 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
540 target_mask
|= MASK_BITFIELD
;
541 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
542 target_mask
|= MASK_CF_HWDIV
;
543 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
544 target_mask
|= MASK_HARD_FLOAT
;
545 target_flags
|= target_mask
& ~target_flags_explicit
;
547 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
548 m68k_cpu
= entry
->device
;
551 m68k_tune
= m68k_tune_entry
->microarch
;
552 m68k_tune_flags
= m68k_tune_entry
->flags
;
554 #ifdef M68K_DEFAULT_TUNE
555 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
557 enum target_device dev
;
558 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
559 m68k_tune_flags
= all_devices
[dev
].flags
;
564 m68k_tune
= entry
->microarch
;
565 m68k_tune_flags
= entry
->flags
;
568 /* Set the type of FPU. */
569 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
570 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
573 /* Sanity check to ensure that msep-data and mid-sahred-library are not
574 * both specified together. Doing so simply doesn't make sense.
576 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
577 error ("cannot specify both -msep-data and -mid-shared-library");
579 /* If we're generating code for a separate A5 relative data segment,
580 * we've got to enable -fPIC as well. This might be relaxable to
581 * -fpic but it hasn't been tested properly.
583 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
586 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
587 error if the target does not support them. */
588 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
589 error ("-mpcrel -fPIC is not currently supported on selected cpu");
591 /* ??? A historic way of turning on pic, or is this intended to
592 be an embedded thing that doesn't have the same name binding
593 significance that it does on hosted ELF systems? */
594 if (TARGET_PCREL
&& flag_pic
== 0)
599 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
601 m68k_symbolic_jump
= "jra %a0";
603 else if (TARGET_ID_SHARED_LIBRARY
)
604 /* All addresses must be loaded from the GOT. */
606 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
609 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
611 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
614 /* No unconditional long branch */;
615 else if (TARGET_PCREL
)
616 m68k_symbolic_jump
= "bra%.l %c0";
618 m68k_symbolic_jump
= "bra%.l %p0";
619 /* Turn off function cse if we are doing PIC. We always want
620 function call to be done as `bsr foo@PLTPC'. */
621 /* ??? It's traditional to do this for -mpcrel too, but it isn't
622 clear how intentional that is. */
623 flag_no_function_cse
= 1;
626 switch (m68k_symbolic_call_var
)
628 case M68K_SYMBOLIC_CALL_JSR
:
629 m68k_symbolic_call
= "jsr %a0";
632 case M68K_SYMBOLIC_CALL_BSR_C
:
633 m68k_symbolic_call
= "bsr%.l %c0";
636 case M68K_SYMBOLIC_CALL_BSR_P
:
637 m68k_symbolic_call
= "bsr%.l %p0";
640 case M68K_SYMBOLIC_CALL_NONE
:
641 gcc_assert (m68k_symbolic_call
== NULL
);
648 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
649 if (align_labels
> 2)
651 warning (0, "-falign-labels=%d is not supported", align_labels
);
656 warning (0, "-falign-loops=%d is not supported", align_loops
);
661 if ((opt_fstack_limit_symbol_arg
!= NULL
|| opt_fstack_limit_register_no
>= 0)
664 warning (0, "-fstack-limit- options are not supported on this cpu");
665 opt_fstack_limit_symbol_arg
= NULL
;
666 opt_fstack_limit_register_no
= -1;
669 SUBTARGET_OVERRIDE_OPTIONS
;
671 /* Setup scheduling options. */
673 m68k_sched_cpu
= CPU_CFV1
;
675 m68k_sched_cpu
= CPU_CFV2
;
677 m68k_sched_cpu
= CPU_CFV3
;
679 m68k_sched_cpu
= CPU_CFV4
;
682 m68k_sched_cpu
= CPU_UNKNOWN
;
683 flag_schedule_insns
= 0;
684 flag_schedule_insns_after_reload
= 0;
685 flag_modulo_sched
= 0;
686 flag_live_range_shrinkage
= 0;
689 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
691 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
692 m68k_sched_mac
= MAC_CF_EMAC
;
693 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
694 m68k_sched_mac
= MAC_CF_MAC
;
696 m68k_sched_mac
= MAC_NO
;
700 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
703 m68k_override_options_after_change (void)
705 if (m68k_sched_cpu
== CPU_UNKNOWN
)
707 flag_schedule_insns
= 0;
708 flag_schedule_insns_after_reload
= 0;
709 flag_modulo_sched
= 0;
710 flag_live_range_shrinkage
= 0;
714 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
715 given argument and NAME is the argument passed to -mcpu. Return NULL
716 if -mcpu was not passed. */
719 m68k_cpp_cpu_ident (const char *prefix
)
723 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
726 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
727 given argument and NAME is the name of the representative device for
728 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
731 m68k_cpp_cpu_family (const char *prefix
)
735 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
738 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
739 "interrupt_handler" attribute and interrupt_thread if FUNC has an
740 "interrupt_thread" attribute. Otherwise, return
741 m68k_fk_normal_function. */
743 enum m68k_function_kind
744 m68k_get_function_kind (tree func
)
748 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
750 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
752 return m68k_fk_interrupt_handler
;
754 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
756 return m68k_fk_interrupt_handler
;
758 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
760 return m68k_fk_interrupt_thread
;
762 return m68k_fk_normal_function
;
765 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
766 struct attribute_spec.handler. */
768 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
769 tree args ATTRIBUTE_UNUSED
,
770 int flags ATTRIBUTE_UNUSED
,
773 if (TREE_CODE (*node
) != FUNCTION_DECL
)
775 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
777 *no_add_attrs
= true;
780 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
782 error ("multiple interrupt attributes not allowed");
783 *no_add_attrs
= true;
787 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
789 error ("interrupt_thread is available only on fido");
790 *no_add_attrs
= true;
797 m68k_compute_frame_layout (void)
801 enum m68k_function_kind func_kind
=
802 m68k_get_function_kind (current_function_decl
);
803 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
804 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
806 /* Only compute the frame once per function.
807 Don't cache information until reload has been completed. */
808 if (current_frame
.funcdef_no
== current_function_funcdef_no
812 current_frame
.size
= (get_frame_size () + 3) & -4;
816 /* Interrupt thread does not need to save any register. */
817 if (!interrupt_thread
)
818 for (regno
= 0; regno
< 16; regno
++)
819 if (m68k_save_reg (regno
, interrupt_handler
))
821 mask
|= 1 << (regno
- D0_REG
);
824 current_frame
.offset
= saved
* 4;
825 current_frame
.reg_no
= saved
;
826 current_frame
.reg_mask
= mask
;
828 current_frame
.foffset
= 0;
830 if (TARGET_HARD_FLOAT
)
832 /* Interrupt thread does not need to save any register. */
833 if (!interrupt_thread
)
834 for (regno
= 16; regno
< 24; regno
++)
835 if (m68k_save_reg (regno
, interrupt_handler
))
837 mask
|= 1 << (regno
- FP0_REG
);
840 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
841 current_frame
.offset
+= current_frame
.foffset
;
843 current_frame
.fpu_no
= saved
;
844 current_frame
.fpu_mask
= mask
;
846 /* Remember what function this frame refers to. */
847 current_frame
.funcdef_no
= current_function_funcdef_no
;
850 /* Worker function for TARGET_CAN_ELIMINATE. */
853 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
855 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
859 m68k_initial_elimination_offset (int from
, int to
)
862 /* The arg pointer points 8 bytes before the start of the arguments,
863 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
864 frame pointer in most frames. */
865 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
866 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
867 return argptr_offset
;
869 m68k_compute_frame_layout ();
871 gcc_assert (to
== STACK_POINTER_REGNUM
);
874 case ARG_POINTER_REGNUM
:
875 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
876 case FRAME_POINTER_REGNUM
:
877 return current_frame
.offset
+ current_frame
.size
;
883 /* Refer to the array `regs_ever_live' to determine which registers
884 to save; `regs_ever_live[I]' is nonzero if register number I
885 is ever used in the function. This function is responsible for
886 knowing which registers should not be saved even if used.
887 Return true if we need to save REGNO. */
890 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
892 if (flag_pic
&& regno
== PIC_REG
)
894 if (crtl
->saves_all_registers
)
896 if (crtl
->uses_pic_offset_table
)
898 /* Reload may introduce constant pool references into a function
899 that thitherto didn't need a PIC register. Note that the test
900 above will not catch that case because we will only set
901 crtl->uses_pic_offset_table when emitting
902 the address reloads. */
903 if (crtl
->uses_const_pool
)
907 if (crtl
->calls_eh_return
)
912 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
913 if (test
== INVALID_REGNUM
)
920 /* Fixed regs we never touch. */
921 if (fixed_regs
[regno
])
924 /* The frame pointer (if it is such) is handled specially. */
925 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
928 /* Interrupt handlers must also save call_used_regs
929 if they are live or when calling nested functions. */
930 if (interrupt_handler
)
932 if (df_regs_ever_live_p (regno
))
935 if (!crtl
->is_leaf
&& call_used_regs
[regno
])
939 /* Never need to save registers that aren't touched. */
940 if (!df_regs_ever_live_p (regno
))
943 /* Otherwise save everything that isn't call-clobbered. */
944 return !call_used_regs
[regno
];
947 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
948 the lowest memory address. COUNT is the number of registers to be
949 moved, with register REGNO + I being moved if bit I of MASK is set.
950 STORE_P specifies the direction of the move and ADJUST_STACK_P says
951 whether or not this is pre-decrement (if STORE_P) or post-increment
952 (if !STORE_P) operation. */
955 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
956 unsigned int count
, unsigned int regno
,
957 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
960 rtx body
, addr
, src
, operands
[2];
963 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
964 mode
= reg_raw_mode
[regno
];
969 src
= plus_constant (Pmode
, base
,
971 * GET_MODE_SIZE (mode
)
972 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
973 XVECEXP (body
, 0, i
++) = gen_rtx_SET (base
, src
);
976 for (; mask
!= 0; mask
>>= 1, regno
++)
979 addr
= plus_constant (Pmode
, base
, offset
);
980 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
981 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
982 XVECEXP (body
, 0, i
++)
983 = gen_rtx_SET (operands
[0], operands
[1]);
984 offset
+= GET_MODE_SIZE (mode
);
986 gcc_assert (i
== XVECLEN (body
, 0));
988 return emit_insn (body
);
991 /* Make INSN a frame-related instruction. */
994 m68k_set_frame_related (rtx_insn
*insn
)
999 RTX_FRAME_RELATED_P (insn
) = 1;
1000 body
= PATTERN (insn
);
1001 if (GET_CODE (body
) == PARALLEL
)
1002 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
1003 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
1006 /* Emit RTL for the "prologue" define_expand. */
1009 m68k_expand_prologue (void)
1011 HOST_WIDE_INT fsize_with_regs
;
1012 rtx limit
, src
, dest
;
1014 m68k_compute_frame_layout ();
1016 if (flag_stack_usage_info
)
1017 current_function_static_stack_size
1018 = current_frame
.size
+ current_frame
.offset
;
1020 /* If the stack limit is a symbol, we can check it here,
1021 before actually allocating the space. */
1022 if (crtl
->limit_stack
1023 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1025 limit
= plus_constant (Pmode
, stack_limit_rtx
, current_frame
.size
+ 4);
1026 if (!m68k_legitimate_constant_p (Pmode
, limit
))
1028 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1029 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1031 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1032 stack_pointer_rtx
, limit
),
1033 stack_pointer_rtx
, limit
,
1037 fsize_with_regs
= current_frame
.size
;
1038 if (TARGET_COLDFIRE
)
1040 /* ColdFire's move multiple instructions do not allow pre-decrement
1041 addressing. Add the size of movem saves to the initial stack
1042 allocation instead. */
1043 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1044 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1045 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1046 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1049 if (frame_pointer_needed
)
1051 if (fsize_with_regs
== 0 && TUNE_68040
)
1053 /* On the 68040, two separate moves are faster than link.w 0. */
1054 dest
= gen_frame_mem (Pmode
,
1055 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1056 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1057 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1058 stack_pointer_rtx
));
1060 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1061 m68k_set_frame_related
1062 (emit_insn (gen_link (frame_pointer_rtx
,
1063 GEN_INT (-4 - fsize_with_regs
))));
1066 m68k_set_frame_related
1067 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1068 m68k_set_frame_related
1069 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1071 GEN_INT (-fsize_with_regs
))));
1074 /* If the frame pointer is needed, emit a special barrier that
1075 will prevent the scheduler from moving stores to the frame
1076 before the stack adjustment. */
1077 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1079 else if (fsize_with_regs
!= 0)
1080 m68k_set_frame_related
1081 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1083 GEN_INT (-fsize_with_regs
))));
1085 if (current_frame
.fpu_mask
)
1087 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1089 m68k_set_frame_related
1090 (m68k_emit_movem (stack_pointer_rtx
,
1091 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1092 current_frame
.fpu_no
, FP0_REG
,
1093 current_frame
.fpu_mask
, true, true));
1098 /* If we're using moveml to save the integer registers,
1099 the stack pointer will point to the bottom of the moveml
1100 save area. Find the stack offset of the first FP register. */
1101 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1104 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1105 m68k_set_frame_related
1106 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1107 current_frame
.fpu_no
, FP0_REG
,
1108 current_frame
.fpu_mask
, true, false));
1112 /* If the stack limit is not a symbol, check it here.
1113 This has the disadvantage that it may be too late... */
1114 if (crtl
->limit_stack
)
1116 if (REG_P (stack_limit_rtx
))
1117 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1119 stack_pointer_rtx
, stack_limit_rtx
,
1122 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1123 warning (0, "stack limit expression is not supported");
1126 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1128 /* Store each register separately in the same order moveml does. */
1131 for (i
= 16; i
-- > 0; )
1132 if (current_frame
.reg_mask
& (1 << i
))
1134 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1135 dest
= gen_frame_mem (SImode
,
1136 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1137 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1142 if (TARGET_COLDFIRE
)
1143 /* The required register save space has already been allocated.
1144 The first register should be stored at (%sp). */
1145 m68k_set_frame_related
1146 (m68k_emit_movem (stack_pointer_rtx
, 0,
1147 current_frame
.reg_no
, D0_REG
,
1148 current_frame
.reg_mask
, true, false));
1150 m68k_set_frame_related
1151 (m68k_emit_movem (stack_pointer_rtx
,
1152 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1153 current_frame
.reg_no
, D0_REG
,
1154 current_frame
.reg_mask
, true, true));
1157 if (!TARGET_SEP_DATA
1158 && crtl
->uses_pic_offset_table
)
1159 emit_insn (gen_load_got (pic_offset_table_rtx
));
1162 /* Return true if a simple (return) instruction is sufficient for this
1163 instruction (i.e. if no epilogue is needed). */
1166 m68k_use_return_insn (void)
1168 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1171 m68k_compute_frame_layout ();
1172 return current_frame
.offset
== 0;
1175 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1176 SIBCALL_P says which.
1178 The function epilogue should not depend on the current stack pointer!
1179 It should use the frame pointer only, if there is a frame pointer.
1180 This is mandatory because of alloca; we also take advantage of it to
1181 omit stack adjustments before returning. */
1184 m68k_expand_epilogue (bool sibcall_p
)
1186 HOST_WIDE_INT fsize
, fsize_with_regs
;
1187 bool big
, restore_from_sp
;
1189 m68k_compute_frame_layout ();
1191 fsize
= current_frame
.size
;
1193 restore_from_sp
= false;
1195 /* FIXME : crtl->is_leaf below is too strong.
1196 What we really need to know there is if there could be pending
1197 stack adjustment needed at that point. */
1198 restore_from_sp
= (!frame_pointer_needed
1199 || (!cfun
->calls_alloca
&& crtl
->is_leaf
));
1201 /* fsize_with_regs is the size we need to adjust the sp when
1202 popping the frame. */
1203 fsize_with_regs
= fsize
;
1204 if (TARGET_COLDFIRE
&& restore_from_sp
)
1206 /* ColdFire's move multiple instructions do not allow post-increment
1207 addressing. Add the size of movem loads to the final deallocation
1209 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1210 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1211 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1212 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1215 if (current_frame
.offset
+ fsize
>= 0x8000
1217 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1220 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1221 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1223 /* ColdFire's move multiple instructions do not support the
1224 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1225 stack-based restore. */
1226 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1227 GEN_INT (-(current_frame
.offset
+ fsize
)));
1228 emit_insn (gen_blockage ());
1229 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1230 gen_rtx_REG (Pmode
, A1_REG
),
1231 frame_pointer_rtx
));
1232 restore_from_sp
= true;
1236 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1242 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1244 /* Restore each register separately in the same order moveml does. */
1246 HOST_WIDE_INT offset
;
1248 offset
= current_frame
.offset
+ fsize
;
1249 for (i
= 0; i
< 16; i
++)
1250 if (current_frame
.reg_mask
& (1 << i
))
1256 /* Generate the address -OFFSET(%fp,%a1.l). */
1257 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1258 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1259 addr
= plus_constant (Pmode
, addr
, -offset
);
1261 else if (restore_from_sp
)
1262 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1264 addr
= plus_constant (Pmode
, frame_pointer_rtx
, -offset
);
1265 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1266 gen_frame_mem (SImode
, addr
));
1267 offset
-= GET_MODE_SIZE (SImode
);
1270 else if (current_frame
.reg_mask
)
1273 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1274 gen_rtx_REG (Pmode
, A1_REG
),
1276 -(current_frame
.offset
+ fsize
),
1277 current_frame
.reg_no
, D0_REG
,
1278 current_frame
.reg_mask
, false, false);
1279 else if (restore_from_sp
)
1280 m68k_emit_movem (stack_pointer_rtx
, 0,
1281 current_frame
.reg_no
, D0_REG
,
1282 current_frame
.reg_mask
, false,
1285 m68k_emit_movem (frame_pointer_rtx
,
1286 -(current_frame
.offset
+ fsize
),
1287 current_frame
.reg_no
, D0_REG
,
1288 current_frame
.reg_mask
, false, false);
1291 if (current_frame
.fpu_no
> 0)
1294 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1295 gen_rtx_REG (Pmode
, A1_REG
),
1297 -(current_frame
.foffset
+ fsize
),
1298 current_frame
.fpu_no
, FP0_REG
,
1299 current_frame
.fpu_mask
, false, false);
1300 else if (restore_from_sp
)
1302 if (TARGET_COLDFIRE
)
1306 /* If we used moveml to restore the integer registers, the
1307 stack pointer will still point to the bottom of the moveml
1308 save area. Find the stack offset of the first FP
1310 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1313 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1314 m68k_emit_movem (stack_pointer_rtx
, offset
,
1315 current_frame
.fpu_no
, FP0_REG
,
1316 current_frame
.fpu_mask
, false, false);
1319 m68k_emit_movem (stack_pointer_rtx
, 0,
1320 current_frame
.fpu_no
, FP0_REG
,
1321 current_frame
.fpu_mask
, false, true);
1324 m68k_emit_movem (frame_pointer_rtx
,
1325 -(current_frame
.foffset
+ fsize
),
1326 current_frame
.fpu_no
, FP0_REG
,
1327 current_frame
.fpu_mask
, false, false);
1330 emit_insn (gen_blockage ());
1331 if (frame_pointer_needed
)
1332 emit_insn (gen_unlink (frame_pointer_rtx
));
1333 else if (fsize_with_regs
)
1334 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1336 GEN_INT (fsize_with_regs
)));
1338 if (crtl
->calls_eh_return
)
1339 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1341 EH_RETURN_STACKADJ_RTX
));
1344 emit_jump_insn (ret_rtx
);
1347 /* Return true if X is a valid comparison operator for the dbcc
1350 Note it rejects floating point comparison operators.
1351 (In the future we could use Fdbcc).
1353 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1356 valid_dbcc_comparison_p_2 (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
)
1358 switch (GET_CODE (x
))
1360 case EQ
: case NE
: case GTU
: case LTU
:
1364 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1366 case GT
: case LT
: case GE
: case LE
:
1367 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1373 /* Return nonzero if flags are currently in the 68881 flag register. */
1375 flags_in_68881 (void)
1377 /* We could add support for these in the future */
1378 return cc_status
.flags
& CC_IN_68881
;
1381 /* Return true if PARALLEL contains register REGNO. */
1383 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1387 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1390 if (GET_CODE (parallel
) != PARALLEL
)
1393 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1397 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1398 if (REG_P (x
) && REGNO (x
) == regno
)
1405 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1408 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1410 enum m68k_function_kind kind
;
1412 /* We cannot use sibcalls for nested functions because we use the
1413 static chain register for indirect calls. */
1414 if (CALL_EXPR_STATIC_CHAIN (exp
))
1417 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1419 /* Check that the return value locations are the same. For
1420 example that we aren't returning a value from the sibling in
1421 a D0 register but then need to transfer it to a A0 register. */
1425 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1427 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1429 /* Check that the values are equal or that the result the callee
1430 function returns is superset of what the current function returns. */
1431 if (!(rtx_equal_p (cfun_value
, call_value
)
1432 || (REG_P (cfun_value
)
1433 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1437 kind
= m68k_get_function_kind (current_function_decl
);
1438 if (kind
== m68k_fk_normal_function
)
1439 /* We can always sibcall from a normal function, because it's
1440 undefined if it is calling an interrupt function. */
1443 /* Otherwise we can only sibcall if the function kind is known to be
1445 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1451 /* On the m68k all args are always pushed. */
1454 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1455 machine_mode mode ATTRIBUTE_UNUSED
,
1456 const_tree type ATTRIBUTE_UNUSED
,
1457 bool named ATTRIBUTE_UNUSED
)
1463 m68k_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1464 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1466 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1468 *cum
+= (mode
!= BLKmode
1469 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1470 : (int_size_in_bytes (type
) + 3) & ~3);
1473 /* Convert X to a legitimate function call memory reference and return the
1477 m68k_legitimize_call_address (rtx x
)
1479 gcc_assert (MEM_P (x
));
1480 if (call_operand (XEXP (x
, 0), VOIDmode
))
1482 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1485 /* Likewise for sibling calls. */
1488 m68k_legitimize_sibcall_address (rtx x
)
1490 gcc_assert (MEM_P (x
));
1491 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1494 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1495 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1498 /* Convert X to a legitimate address and return it if successful. Otherwise
1501 For the 68000, we handle X+REG by loading X into a register R and
1502 using R+REG. R will go in an address reg and indexing will be used.
1503 However, if REG is a broken-out memory address or multiplication,
1504 nothing needs to be done because REG can certainly go in an address reg. */
1507 m68k_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
1509 if (m68k_tls_symbol_p (x
))
1510 return m68k_legitimize_tls_address (x
);
1512 if (GET_CODE (x
) == PLUS
)
1514 int ch
= (x
) != (oldx
);
1517 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1519 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1522 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1524 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1527 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1531 if (GET_CODE (XEXP (x
, 1)) == REG
1532 && GET_CODE (XEXP (x
, 0)) == REG
)
1534 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1537 x
= force_operand (x
, 0);
1541 if (memory_address_p (mode
, x
))
1544 if (GET_CODE (XEXP (x
, 0)) == REG
1545 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1546 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1547 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1549 rtx temp
= gen_reg_rtx (Pmode
);
1550 rtx val
= force_operand (XEXP (x
, 1), 0);
1551 emit_move_insn (temp
, val
);
1554 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1555 && GET_CODE (XEXP (x
, 0)) == REG
)
1556 x
= force_operand (x
, 0);
1558 else if (GET_CODE (XEXP (x
, 1)) == REG
1559 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1560 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1561 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1563 rtx temp
= gen_reg_rtx (Pmode
);
1564 rtx val
= force_operand (XEXP (x
, 0), 0);
1565 emit_move_insn (temp
, val
);
1568 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1569 && GET_CODE (XEXP (x
, 1)) == REG
)
1570 x
= force_operand (x
, 0);
1578 /* Output a dbCC; jCC sequence. Note we do not handle the
1579 floating point version of this sequence (Fdbcc). We also
1580 do not handle alternative conditions when CC_NO_OVERFLOW is
1581 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1582 kick those out before we get here. */
1585 output_dbcc_and_branch (rtx
*operands
)
1587 switch (GET_CODE (operands
[3]))
1590 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1594 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1598 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1602 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1606 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1610 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1614 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1618 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1622 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1626 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1633 /* If the decrement is to be done in SImode, then we have
1634 to compensate for the fact that dbcc decrements in HImode. */
1635 switch (GET_MODE (operands
[0]))
1638 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1650 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1653 enum rtx_code op_code
= GET_CODE (op
);
1655 /* This does not produce a useful cc. */
1658 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1659 below. Swap the operands and change the op if these requirements
1660 are not fulfilled. */
1661 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1665 operand1
= operand2
;
1667 op_code
= swap_condition (op_code
);
1669 loperands
[0] = operand1
;
1670 if (GET_CODE (operand1
) == REG
)
1671 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1673 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1674 if (operand2
!= const0_rtx
)
1676 loperands
[2] = operand2
;
1677 if (GET_CODE (operand2
) == REG
)
1678 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1680 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1682 loperands
[4] = gen_label_rtx ();
1683 if (operand2
!= const0_rtx
)
1684 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1687 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1688 output_asm_insn ("tst%.l %0", loperands
);
1690 output_asm_insn ("cmp%.w #0,%0", loperands
);
1692 output_asm_insn ("jne %l4", loperands
);
1694 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1695 output_asm_insn ("tst%.l %1", loperands
);
1697 output_asm_insn ("cmp%.w #0,%1", loperands
);
1700 loperands
[5] = dest
;
1705 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1706 CODE_LABEL_NUMBER (loperands
[4]));
1707 output_asm_insn ("seq %5", loperands
);
1711 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1712 CODE_LABEL_NUMBER (loperands
[4]));
1713 output_asm_insn ("sne %5", loperands
);
1717 loperands
[6] = gen_label_rtx ();
1718 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1719 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1720 CODE_LABEL_NUMBER (loperands
[4]));
1721 output_asm_insn ("sgt %5", loperands
);
1722 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1723 CODE_LABEL_NUMBER (loperands
[6]));
1727 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1728 CODE_LABEL_NUMBER (loperands
[4]));
1729 output_asm_insn ("shi %5", loperands
);
1733 loperands
[6] = gen_label_rtx ();
1734 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1735 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1736 CODE_LABEL_NUMBER (loperands
[4]));
1737 output_asm_insn ("slt %5", loperands
);
1738 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1739 CODE_LABEL_NUMBER (loperands
[6]));
1743 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1744 CODE_LABEL_NUMBER (loperands
[4]));
1745 output_asm_insn ("scs %5", loperands
);
1749 loperands
[6] = gen_label_rtx ();
1750 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1751 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1752 CODE_LABEL_NUMBER (loperands
[4]));
1753 output_asm_insn ("sge %5", loperands
);
1754 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1755 CODE_LABEL_NUMBER (loperands
[6]));
1759 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1760 CODE_LABEL_NUMBER (loperands
[4]));
1761 output_asm_insn ("scc %5", loperands
);
1765 loperands
[6] = gen_label_rtx ();
1766 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1767 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1768 CODE_LABEL_NUMBER (loperands
[4]));
1769 output_asm_insn ("sle %5", loperands
);
1770 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1771 CODE_LABEL_NUMBER (loperands
[6]));
1775 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1776 CODE_LABEL_NUMBER (loperands
[4]));
1777 output_asm_insn ("sls %5", loperands
);
1787 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx_insn
*insn
, int signpos
)
1789 operands
[0] = countop
;
1790 operands
[1] = dataop
;
1792 if (GET_CODE (countop
) == CONST_INT
)
1794 register int count
= INTVAL (countop
);
1795 /* If COUNT is bigger than size of storage unit in use,
1796 advance to the containing unit of same size. */
1797 if (count
> signpos
)
1799 int offset
= (count
& ~signpos
) / 8;
1800 count
= count
& signpos
;
1801 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1803 if (count
== signpos
)
1804 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1806 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1808 /* These three statements used to use next_insns_test_no...
1809 but it appears that this should do the same job. */
1811 && next_insn_tests_no_inequality (insn
))
1814 && next_insn_tests_no_inequality (insn
))
1817 && next_insn_tests_no_inequality (insn
))
1819 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1820 On some m68k variants unfortunately that's slower than btst.
1821 On 68000 and higher, that should also work for all HImode operands. */
1822 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1824 if (count
== 3 && DATA_REG_P (operands
[1])
1825 && next_insn_tests_no_inequality (insn
))
1827 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1828 return "move%.w %1,%%ccr";
1830 if (count
== 2 && DATA_REG_P (operands
[1])
1831 && next_insn_tests_no_inequality (insn
))
1833 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1834 return "move%.w %1,%%ccr";
1836 /* count == 1 followed by bvc/bvs and
1837 count == 0 followed by bcc/bcs are also possible, but need
1838 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1841 cc_status
.flags
= CC_NOT_NEGATIVE
;
1843 return "btst %0,%1";
1846 /* Return true if X is a legitimate base register. STRICT_P says
1847 whether we need strict checking. */
1850 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1852 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1853 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1858 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1859 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1862 /* Return true if X is a legitimate index register. STRICT_P says
1863 whether we need strict checking. */
1866 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1868 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1873 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1874 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1877 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1878 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1879 ADDRESS if so. STRICT_P says whether we need strict checking. */
1882 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1886 /* Check for a scale factor. */
1888 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1889 && GET_CODE (x
) == MULT
1890 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1891 && (INTVAL (XEXP (x
, 1)) == 2
1892 || INTVAL (XEXP (x
, 1)) == 4
1893 || (INTVAL (XEXP (x
, 1)) == 8
1894 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1896 scale
= INTVAL (XEXP (x
, 1));
1900 /* Check for a word extension. */
1901 if (!TARGET_COLDFIRE
1902 && GET_CODE (x
) == SIGN_EXTEND
1903 && GET_MODE (XEXP (x
, 0)) == HImode
)
1906 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1908 address
->scale
= scale
;
1916 /* Return true if X is an illegitimate symbolic constant. */
1919 m68k_illegitimate_symbolic_constant_p (rtx x
)
1923 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1925 split_const (x
, &base
, &offset
);
1926 if (GET_CODE (base
) == SYMBOL_REF
1927 && !offset_within_block_p (base
, INTVAL (offset
)))
1930 return m68k_tls_reference_p (x
, false);
1933 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1936 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1938 return m68k_illegitimate_symbolic_constant_p (x
);
1941 /* Return true if X is a legitimate constant address that can reach
1942 bytes in the range [X, X + REACH). STRICT_P says whether we need
1946 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1950 if (!CONSTANT_ADDRESS_P (x
))
1954 && !(strict_p
&& TARGET_PCREL
)
1955 && symbolic_operand (x
, VOIDmode
))
1958 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1960 split_const (x
, &base
, &offset
);
1961 if (GET_CODE (base
) == SYMBOL_REF
1962 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1966 return !m68k_tls_reference_p (x
, false);
1969 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1970 labels will become jump tables. */
1973 m68k_jump_table_ref_p (rtx x
)
1975 if (GET_CODE (x
) != LABEL_REF
)
1978 rtx_insn
*insn
= as_a
<rtx_insn
*> (XEXP (x
, 0));
1979 if (!NEXT_INSN (insn
) && !PREV_INSN (insn
))
1982 insn
= next_nonnote_insn (insn
);
1983 return insn
&& JUMP_TABLE_DATA_P (insn
);
1986 /* Return true if X is a legitimate address for values of mode MODE.
1987 STRICT_P says whether strict checking is needed. If the address
1988 is valid, describe its components in *ADDRESS. */
1991 m68k_decompose_address (machine_mode mode
, rtx x
,
1992 bool strict_p
, struct m68k_address
*address
)
1996 memset (address
, 0, sizeof (*address
));
1998 if (mode
== BLKmode
)
2001 reach
= GET_MODE_SIZE (mode
);
2003 /* Check for (An) (mode 2). */
2004 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2010 /* Check for -(An) and (An)+ (modes 3 and 4). */
2011 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
2012 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2014 address
->code
= GET_CODE (x
);
2015 address
->base
= XEXP (x
, 0);
2019 /* Check for (d16,An) (mode 5). */
2020 if (GET_CODE (x
) == PLUS
2021 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2022 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2023 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2025 address
->base
= XEXP (x
, 0);
2026 address
->offset
= XEXP (x
, 1);
2030 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2031 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2033 if (GET_CODE (x
) == PLUS
2034 && XEXP (x
, 0) == pic_offset_table_rtx
)
2036 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2037 they are invalid in this context. */
2038 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2040 address
->base
= XEXP (x
, 0);
2041 address
->offset
= XEXP (x
, 1);
2046 /* The ColdFire FPU only accepts addressing modes 2-5. */
2047 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2050 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2051 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2052 All these modes are variations of mode 7. */
2053 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2055 address
->offset
= x
;
2059 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2062 ??? do_tablejump creates these addresses before placing the target
2063 label, so we have to assume that unplaced labels are jump table
2064 references. It seems unlikely that we would ever generate indexed
2065 accesses to unplaced labels in other cases. */
2066 if (GET_CODE (x
) == PLUS
2067 && m68k_jump_table_ref_p (XEXP (x
, 1))
2068 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2070 address
->offset
= XEXP (x
, 1);
2074 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2075 (bd,An,Xn.SIZE*SCALE) addresses. */
2079 /* Check for a nonzero base displacement. */
2080 if (GET_CODE (x
) == PLUS
2081 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2083 address
->offset
= XEXP (x
, 1);
2087 /* Check for a suppressed index register. */
2088 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2094 /* Check for a suppressed base register. Do not allow this case
2095 for non-symbolic offsets as it effectively gives gcc freedom
2096 to treat data registers as base registers, which can generate
2099 && symbolic_operand (address
->offset
, VOIDmode
)
2100 && m68k_decompose_index (x
, strict_p
, address
))
2105 /* Check for a nonzero base displacement. */
2106 if (GET_CODE (x
) == PLUS
2107 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2108 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2110 address
->offset
= XEXP (x
, 1);
2115 /* We now expect the sum of a base and an index. */
2116 if (GET_CODE (x
) == PLUS
)
2118 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2119 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2121 address
->base
= XEXP (x
, 0);
2125 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2126 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2128 address
->base
= XEXP (x
, 1);
2135 /* Return true if X is a legitimate address for values of mode MODE.
2136 STRICT_P says whether strict checking is needed. */
2139 m68k_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
2141 struct m68k_address address
;
2143 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2146 /* Return true if X is a memory, describing its address in ADDRESS if so.
2147 Apply strict checking if called during or after reload. */
2150 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2153 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2154 reload_in_progress
|| reload_completed
,
2158 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2161 m68k_legitimate_constant_p (machine_mode mode
, rtx x
)
2163 return mode
!= XFmode
&& !m68k_illegitimate_symbolic_constant_p (x
);
2166 /* Return true if X matches the 'Q' constraint. It must be a memory
2167 with a base address and no constant offset or index. */
2170 m68k_matches_q_p (rtx x
)
2172 struct m68k_address address
;
2174 return (m68k_legitimate_mem_p (x
, &address
)
2175 && address
.code
== UNKNOWN
2181 /* Return true if X matches the 'U' constraint. It must be a base address
2182 with a constant offset and no index. */
2185 m68k_matches_u_p (rtx x
)
2187 struct m68k_address address
;
2189 return (m68k_legitimate_mem_p (x
, &address
)
2190 && address
.code
== UNKNOWN
2196 /* Return GOT pointer. */
2201 if (pic_offset_table_rtx
== NULL_RTX
)
2202 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2204 crtl
->uses_pic_offset_table
= 1;
2206 return pic_offset_table_rtx
;
2209 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2211 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2212 RELOC_TLSIE
, RELOC_TLSLE
};
2214 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2216 /* Wrap symbol X into unspec representing relocation RELOC.
2217 BASE_REG - register that should be added to the result.
2218 TEMP_REG - if non-null, temporary register. */
2221 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2225 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2227 if (TARGET_COLDFIRE
&& use_x_p
)
2228 /* When compiling with -mx{got, tls} switch the code will look like this:
2230 move.l <X>@<RELOC>,<TEMP_REG>
2231 add.l <BASE_REG>,<TEMP_REG> */
2233 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2234 to put @RELOC after reference. */
2235 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2237 x
= gen_rtx_CONST (Pmode
, x
);
2239 if (temp_reg
== NULL
)
2241 gcc_assert (can_create_pseudo_p ());
2242 temp_reg
= gen_reg_rtx (Pmode
);
2245 emit_move_insn (temp_reg
, x
);
2246 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2251 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2253 x
= gen_rtx_CONST (Pmode
, x
);
2255 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2261 /* Helper for m68k_unwrap_symbol.
2262 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2263 sets *RELOC_PTR to relocation type for the symbol. */
2266 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2267 enum m68k_reloc
*reloc_ptr
)
2269 if (GET_CODE (orig
) == CONST
)
2272 enum m68k_reloc dummy
;
2276 if (reloc_ptr
== NULL
)
2279 /* Handle an addend. */
2280 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2281 && CONST_INT_P (XEXP (x
, 1)))
2284 if (GET_CODE (x
) == UNSPEC
)
2286 switch (XINT (x
, 1))
2288 case UNSPEC_RELOC16
:
2289 orig
= XVECEXP (x
, 0, 0);
2290 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2293 case UNSPEC_RELOC32
:
2294 if (unwrap_reloc32_p
)
2296 orig
= XVECEXP (x
, 0, 0);
2297 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2310 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2311 UNSPEC_RELOC32 wrappers. */
2314 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2316 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2319 /* Prescan insn before outputing assembler for it. */
2322 m68k_final_prescan_insn (rtx_insn
*insn ATTRIBUTE_UNUSED
,
2323 rtx
*operands
, int n_operands
)
2327 /* Combine and, possibly, other optimizations may do good job
2329 (const (unspec [(symbol)]))
2331 (const (plus (unspec [(symbol)])
2333 The problem with this is emitting @TLS or @GOT decorations.
2334 The decoration is emitted when processing (unspec), so the
2335 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2337 It seems that the easiest solution to this is to convert such
2339 (const (unspec [(plus (symbol)
2341 Note, that the top level of operand remains intact, so we don't have
2342 to patch up anything outside of the operand. */
2344 subrtx_var_iterator::array_type array
;
2345 for (i
= 0; i
< n_operands
; ++i
)
2351 FOR_EACH_SUBRTX_VAR (iter
, array
, op
, ALL
)
2354 if (m68k_unwrap_symbol (x
, true) != x
)
2358 gcc_assert (GET_CODE (x
) == CONST
);
2361 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2366 unspec
= XEXP (plus
, 0);
2367 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2368 addend
= XEXP (plus
, 1);
2369 gcc_assert (CONST_INT_P (addend
));
2371 /* We now have all the pieces, rearrange them. */
2373 /* Move symbol to plus. */
2374 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2376 /* Move plus inside unspec. */
2377 XVECEXP (unspec
, 0, 0) = plus
;
2379 /* Move unspec to top level of const. */
2380 XEXP (x
, 0) = unspec
;
2382 iter
.skip_subrtxes ();
2388 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2389 If REG is non-null, use it; generate new pseudo otherwise. */
2392 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2396 if (reg
== NULL_RTX
)
2398 gcc_assert (can_create_pseudo_p ());
2399 reg
= gen_reg_rtx (Pmode
);
2402 insn
= emit_move_insn (reg
, x
);
2403 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2405 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2410 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2414 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2416 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2418 x
= gen_rtx_MEM (Pmode
, x
);
2419 MEM_READONLY_P (x
) = 1;
2424 /* Legitimize PIC addresses. If the address is already
2425 position-independent, we return ORIG. Newly generated
2426 position-independent addresses go to REG. If we need more
2427 than one register, we lose.
2429 An address is legitimized by making an indirect reference
2430 through the Global Offset Table with the name of the symbol
2433 The assembler and linker are responsible for placing the
2434 address of the symbol in the GOT. The function prologue
2435 is responsible for initializing a5 to the starting address
2438 The assembler is also responsible for translating a symbol name
2439 into a constant displacement from the start of the GOT.
2441 A quick example may make things a little clearer:
2443 When not generating PIC code to store the value 12345 into _foo
2444 we would generate the following code:
2448 When generating PIC two transformations are made. First, the compiler
2449 loads the address of foo into a register. So the first transformation makes:
2454 The code in movsi will intercept the lea instruction and call this
2455 routine which will transform the instructions into:
2457 movel a5@(_foo:w), a0
2461 That (in a nutshell) is how *all* symbol and label references are
2465 legitimize_pic_address (rtx orig
, machine_mode mode ATTRIBUTE_UNUSED
,
2470 /* First handle a simple SYMBOL_REF or LABEL_REF */
2471 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2475 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2476 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2478 else if (GET_CODE (orig
) == CONST
)
2482 /* Make sure this has not already been legitimized. */
2483 if (m68k_unwrap_symbol (orig
, true) != orig
)
2488 /* legitimize both operands of the PLUS */
2489 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2491 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2492 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2493 base
== reg
? 0 : reg
);
2495 if (GET_CODE (orig
) == CONST_INT
)
2496 pic_ref
= plus_constant (Pmode
, base
, INTVAL (orig
));
2498 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2504 /* The __tls_get_addr symbol. */
2505 static GTY(()) rtx m68k_tls_get_addr
;
2507 /* Return SYMBOL_REF for __tls_get_addr. */
2510 m68k_get_tls_get_addr (void)
2512 if (m68k_tls_get_addr
== NULL_RTX
)
2513 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2515 return m68k_tls_get_addr
;
2518 /* Return libcall result in A0 instead of usual D0. */
2519 static bool m68k_libcall_value_in_a0_p
= false;
2521 /* Emit instruction sequence that calls __tls_get_addr. X is
2522 the TLS symbol we are referencing and RELOC is the symbol type to use
2523 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2524 emitted. A pseudo register with result of __tls_get_addr call is
2528 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2534 /* Emit the call sequence. */
2537 /* FIXME: Unfortunately, emit_library_call_value does not
2538 consider (plus (%a5) (const (unspec))) to be a good enough
2539 operand for push, so it forces it into a register. The bad
2540 thing about this is that combiner, due to copy propagation and other
2541 optimizations, sometimes can not later fix this. As a consequence,
2542 additional register may be allocated resulting in a spill.
2543 For reference, see args processing loops in
2544 calls.c:emit_library_call_value_1.
2545 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2546 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2548 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2549 is the simpliest way of generating a call. The difference between
2550 __tls_get_addr() and libcall is that the result is returned in D0
2551 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2552 which temporarily switches returning the result to A0. */
2554 m68k_libcall_value_in_a0_p
= true;
2555 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2557 m68k_libcall_value_in_a0_p
= false;
2559 insns
= get_insns ();
2562 gcc_assert (can_create_pseudo_p ());
2563 dest
= gen_reg_rtx (Pmode
);
2564 emit_libcall_block (insns
, dest
, a0
, eqv
);
2569 /* The __tls_get_addr symbol. */
2570 static GTY(()) rtx m68k_read_tp
;
2572 /* Return SYMBOL_REF for __m68k_read_tp. */
2575 m68k_get_m68k_read_tp (void)
2577 if (m68k_read_tp
== NULL_RTX
)
2578 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2580 return m68k_read_tp
;
2583 /* Emit instruction sequence that calls __m68k_read_tp.
2584 A pseudo register with result of __m68k_read_tp call is returned. */
2587 m68k_call_m68k_read_tp (void)
2596 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2597 is the simpliest way of generating a call. The difference between
2598 __m68k_read_tp() and libcall is that the result is returned in D0
2599 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2600 which temporarily switches returning the result to A0. */
2602 /* Emit the call sequence. */
2603 m68k_libcall_value_in_a0_p
= true;
2604 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2606 m68k_libcall_value_in_a0_p
= false;
2607 insns
= get_insns ();
2610 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2611 share the m68k_read_tp result with other IE/LE model accesses. */
2612 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2614 gcc_assert (can_create_pseudo_p ());
2615 dest
= gen_reg_rtx (Pmode
);
2616 emit_libcall_block (insns
, dest
, a0
, eqv
);
2621 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2622 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2626 m68k_legitimize_tls_address (rtx orig
)
2628 switch (SYMBOL_REF_TLS_MODEL (orig
))
2630 case TLS_MODEL_GLOBAL_DYNAMIC
:
2631 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2634 case TLS_MODEL_LOCAL_DYNAMIC
:
2640 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2641 share the LDM result with other LD model accesses. */
2642 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2645 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2647 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2649 if (can_create_pseudo_p ())
2650 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2656 case TLS_MODEL_INITIAL_EXEC
:
2661 a0
= m68k_call_m68k_read_tp ();
2663 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2664 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2666 if (can_create_pseudo_p ())
2667 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2673 case TLS_MODEL_LOCAL_EXEC
:
2678 a0
= m68k_call_m68k_read_tp ();
2680 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2682 if (can_create_pseudo_p ())
2683 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2696 /* Return true if X is a TLS symbol. */
2699 m68k_tls_symbol_p (rtx x
)
2701 if (!TARGET_HAVE_TLS
)
2704 if (GET_CODE (x
) != SYMBOL_REF
)
2707 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2710 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2711 though illegitimate one.
2712 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2715 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2717 if (!TARGET_HAVE_TLS
)
2722 subrtx_var_iterator::array_type array
;
2723 FOR_EACH_SUBRTX_VAR (iter
, array
, x
, ALL
)
2727 /* Note: this is not the same as m68k_tls_symbol_p. */
2728 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0)
2731 /* Don't recurse into legitimate TLS references. */
2732 if (m68k_tls_reference_p (x
, true))
2733 iter
.skip_subrtxes ();
2739 enum m68k_reloc reloc
= RELOC_GOT
;
2741 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2742 && TLS_RELOC_P (reloc
));
2748 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2750 /* Return the type of move that should be used for integer I. */
2753 m68k_const_method (HOST_WIDE_INT i
)
2760 /* The ColdFire doesn't have byte or word operations. */
2761 /* FIXME: This may not be useful for the m68060 either. */
2762 if (!TARGET_COLDFIRE
)
2764 /* if -256 < N < 256 but N is not in range for a moveq
2765 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2766 if (USE_MOVQ (i
^ 0xff))
2768 /* Likewise, try with not.w */
2769 if (USE_MOVQ (i
^ 0xffff))
2771 /* This is the only value where neg.w is useful */
2776 /* Try also with swap. */
2778 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2783 /* Try using MVZ/MVS with an immediate value to load constants. */
2784 if (i
>= 0 && i
<= 65535)
2786 if (i
>= -32768 && i
<= 32767)
2790 /* Otherwise, use move.l */
2794 /* Return the cost of moving constant I into a data register. */
2797 const_int_cost (HOST_WIDE_INT i
)
2799 switch (m68k_const_method (i
))
2802 /* Constants between -128 and 127 are cheap due to moveq. */
2810 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2820 m68k_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
2821 int opno ATTRIBUTE_UNUSED
,
2822 int *total
, bool speed ATTRIBUTE_UNUSED
)
2824 int code
= GET_CODE (x
);
2829 /* Constant zero is super cheap due to clr instruction. */
2830 if (x
== const0_rtx
)
2833 *total
= const_int_cost (INTVAL (x
));
2843 /* Make 0.0 cheaper than other floating constants to
2844 encourage creating tstsf and tstdf insns. */
2845 if (outer_code
== COMPARE
2846 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2852 /* These are vaguely right for a 68020. */
2853 /* The costs for long multiply have been adjusted to work properly
2854 in synth_mult on the 68020, relative to an average of the time
2855 for add and the time for shift, taking away a little more because
2856 sometimes move insns are needed. */
2857 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2862 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2863 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2865 : TARGET_COLDFIRE ? 3 : 13)
2870 : TUNE_68000_10 ? 5 \
2871 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2872 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2874 : TARGET_COLDFIRE ? 2 : 8)
2877 (TARGET_CF_HWDIV ? 11 \
2878 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2881 /* An lea costs about three times as much as a simple add. */
2883 && GET_CODE (XEXP (x
, 1)) == REG
2884 && GET_CODE (XEXP (x
, 0)) == MULT
2885 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2886 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2887 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2888 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2889 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2891 /* lea an@(dx:l:i),am */
2892 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2902 *total
= COSTS_N_INSNS(1);
2907 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2909 if (INTVAL (XEXP (x
, 1)) < 16)
2910 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2912 /* We're using clrw + swap for these cases. */
2913 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2916 *total
= COSTS_N_INSNS (10); /* Worst case. */
2919 /* A shift by a big integer takes an extra instruction. */
2920 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2921 && (INTVAL (XEXP (x
, 1)) == 16))
2923 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2926 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2927 && !(INTVAL (XEXP (x
, 1)) > 0
2928 && INTVAL (XEXP (x
, 1)) <= 8))
2930 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2936 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2937 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2939 *total
= COSTS_N_INSNS (MULW_COST
);
2940 else if (mode
== QImode
|| mode
== HImode
)
2941 *total
= COSTS_N_INSNS (MULW_COST
);
2943 *total
= COSTS_N_INSNS (MULL_COST
);
2950 if (mode
== QImode
|| mode
== HImode
)
2951 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2952 else if (TARGET_CF_HWDIV
)
2953 *total
= COSTS_N_INSNS (18);
2955 *total
= COSTS_N_INSNS (43); /* div.l */
2959 if (outer_code
== COMPARE
)
2968 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2972 output_move_const_into_data_reg (rtx
*operands
)
2976 i
= INTVAL (operands
[1]);
2977 switch (m68k_const_method (i
))
2980 return "mvzw %1,%0";
2982 return "mvsw %1,%0";
2984 return "moveq %1,%0";
2987 operands
[1] = GEN_INT (i
^ 0xff);
2988 return "moveq %1,%0\n\tnot%.b %0";
2991 operands
[1] = GEN_INT (i
^ 0xffff);
2992 return "moveq %1,%0\n\tnot%.w %0";
2995 return "moveq #-128,%0\n\tneg%.w %0";
3000 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
3001 return "moveq %1,%0\n\tswap %0";
3004 return "move%.l %1,%0";
3010 /* Return true if I can be handled by ISA B's mov3q instruction. */
3013 valid_mov3q_const (HOST_WIDE_INT i
)
3015 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3018 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3019 I is the value of OPERANDS[1]. */
3022 output_move_simode_const (rtx
*operands
)
3028 src
= INTVAL (operands
[1]);
3030 && (DATA_REG_P (dest
) || MEM_P (dest
))
3031 /* clr insns on 68000 read before writing. */
3032 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3033 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3035 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3036 return "mov3q%.l %1,%0";
3037 else if (src
== 0 && ADDRESS_REG_P (dest
))
3038 return "sub%.l %0,%0";
3039 else if (DATA_REG_P (dest
))
3040 return output_move_const_into_data_reg (operands
);
3041 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3043 if (valid_mov3q_const (src
))
3044 return "mov3q%.l %1,%0";
3045 return "move%.w %1,%0";
3047 else if (MEM_P (dest
)
3048 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3049 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3050 && IN_RANGE (src
, -0x8000, 0x7fff))
3052 if (valid_mov3q_const (src
))
3053 return "mov3q%.l %1,%-";
3056 return "move%.l %1,%0";
3060 output_move_simode (rtx
*operands
)
3062 if (GET_CODE (operands
[1]) == CONST_INT
)
3063 return output_move_simode_const (operands
);
3064 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3065 || GET_CODE (operands
[1]) == CONST
)
3066 && push_operand (operands
[0], SImode
))
3068 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3069 || GET_CODE (operands
[1]) == CONST
)
3070 && ADDRESS_REG_P (operands
[0]))
3071 return "lea %a1,%0";
3072 return "move%.l %1,%0";
3076 output_move_himode (rtx
*operands
)
3078 if (GET_CODE (operands
[1]) == CONST_INT
)
3080 if (operands
[1] == const0_rtx
3081 && (DATA_REG_P (operands
[0])
3082 || GET_CODE (operands
[0]) == MEM
)
3083 /* clr insns on 68000 read before writing. */
3084 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3085 || !(GET_CODE (operands
[0]) == MEM
3086 && MEM_VOLATILE_P (operands
[0]))))
3088 else if (operands
[1] == const0_rtx
3089 && ADDRESS_REG_P (operands
[0]))
3090 return "sub%.l %0,%0";
3091 else if (DATA_REG_P (operands
[0])
3092 && INTVAL (operands
[1]) < 128
3093 && INTVAL (operands
[1]) >= -128)
3094 return "moveq %1,%0";
3095 else if (INTVAL (operands
[1]) < 0x8000
3096 && INTVAL (operands
[1]) >= -0x8000)
3097 return "move%.w %1,%0";
3099 else if (CONSTANT_P (operands
[1]))
3100 return "move%.l %1,%0";
3101 return "move%.w %1,%0";
3105 output_move_qimode (rtx
*operands
)
3107 /* 68k family always modifies the stack pointer by at least 2, even for
3108 byte pushes. The 5200 (ColdFire) does not do this. */
3110 /* This case is generated by pushqi1 pattern now. */
3111 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3112 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3113 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3114 && ! ADDRESS_REG_P (operands
[1])
3115 && ! TARGET_COLDFIRE
));
3117 /* clr and st insns on 68000 read before writing. */
3118 if (!ADDRESS_REG_P (operands
[0])
3119 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3120 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3122 if (operands
[1] == const0_rtx
)
3124 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3125 && GET_CODE (operands
[1]) == CONST_INT
3126 && (INTVAL (operands
[1]) & 255) == 255)
3132 if (GET_CODE (operands
[1]) == CONST_INT
3133 && DATA_REG_P (operands
[0])
3134 && INTVAL (operands
[1]) < 128
3135 && INTVAL (operands
[1]) >= -128)
3136 return "moveq %1,%0";
3137 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3138 return "sub%.l %0,%0";
3139 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3140 return "move%.l %1,%0";
3141 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3142 from address registers. */
3143 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3144 return "move%.w %1,%0";
3145 return "move%.b %1,%0";
3149 output_move_stricthi (rtx
*operands
)
3151 if (operands
[1] == const0_rtx
3152 /* clr insns on 68000 read before writing. */
3153 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3154 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3156 return "move%.w %1,%0";
3160 output_move_strictqi (rtx
*operands
)
3162 if (operands
[1] == const0_rtx
3163 /* clr insns on 68000 read before writing. */
3164 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3165 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3167 return "move%.b %1,%0";
3170 /* Return the best assembler insn template
3171 for moving operands[1] into operands[0] as a fullword. */
3174 singlemove_string (rtx
*operands
)
3176 if (GET_CODE (operands
[1]) == CONST_INT
)
3177 return output_move_simode_const (operands
);
3178 return "move%.l %1,%0";
3182 /* Output assembler or rtl code to perform a doubleword move insn
3183 with operands OPERANDS.
3184 Pointers to 3 helper functions should be specified:
3185 HANDLE_REG_ADJUST to adjust a register by a small value,
3186 HANDLE_COMPADR to compute an address and
3187 HANDLE_MOVSI to move 4 bytes. */
3190 handle_move_double (rtx operands
[2],
3191 void (*handle_reg_adjust
) (rtx
, int),
3192 void (*handle_compadr
) (rtx
[2]),
3193 void (*handle_movsi
) (rtx
[2]))
3197 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3202 rtx addreg0
= 0, addreg1
= 0;
3203 int dest_overlapped_low
= 0;
3204 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3209 /* First classify both operands. */
3211 if (REG_P (operands
[0]))
3213 else if (offsettable_memref_p (operands
[0]))
3215 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3217 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3219 else if (GET_CODE (operands
[0]) == MEM
)
3224 if (REG_P (operands
[1]))
3226 else if (CONSTANT_P (operands
[1]))
3228 else if (offsettable_memref_p (operands
[1]))
3230 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3232 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3234 else if (GET_CODE (operands
[1]) == MEM
)
3239 /* Check for the cases that the operand constraints are not supposed
3240 to allow to happen. Generating code for these cases is
3242 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3244 /* If one operand is decrementing and one is incrementing
3245 decrement the former register explicitly
3246 and change that operand into ordinary indexing. */
3248 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3250 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3252 handle_reg_adjust (operands
[0], -size
);
3254 if (GET_MODE (operands
[1]) == XFmode
)
3255 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3256 else if (GET_MODE (operands
[0]) == DFmode
)
3257 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3259 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3262 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3264 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3266 handle_reg_adjust (operands
[1], -size
);
3268 if (GET_MODE (operands
[1]) == XFmode
)
3269 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3270 else if (GET_MODE (operands
[1]) == DFmode
)
3271 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3273 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3277 /* If an operand is an unoffsettable memory ref, find a register
3278 we can increment temporarily to make it refer to the second word. */
3280 if (optype0
== MEMOP
)
3281 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3283 if (optype1
== MEMOP
)
3284 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3286 /* Ok, we can do one word at a time.
3287 Normally we do the low-numbered word first,
3288 but if either operand is autodecrementing then we
3289 do the high-numbered word first.
3291 In either case, set up in LATEHALF the operands to use
3292 for the high-numbered word and in some cases alter the
3293 operands in OPERANDS to be suitable for the low-numbered word. */
3297 if (optype0
== REGOP
)
3299 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3300 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3302 else if (optype0
== OFFSOP
)
3304 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3305 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3309 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3310 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3313 if (optype1
== REGOP
)
3315 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3316 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3318 else if (optype1
== OFFSOP
)
3320 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3321 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3323 else if (optype1
== CNSTOP
)
3325 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3329 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3330 (*CONST_DOUBLE_REAL_VALUE (operands
[1]), l
);
3331 operands
[1] = GEN_INT (l
[0]);
3332 middlehalf
[1] = GEN_INT (l
[1]);
3333 latehalf
[1] = GEN_INT (l
[2]);
3337 /* No non-CONST_DOUBLE constant should ever appear
3339 gcc_assert (!CONSTANT_P (operands
[1]));
3344 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3345 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3349 /* size is not 12: */
3351 if (optype0
== REGOP
)
3352 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3353 else if (optype0
== OFFSOP
)
3354 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3356 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3358 if (optype1
== REGOP
)
3359 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3360 else if (optype1
== OFFSOP
)
3361 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3362 else if (optype1
== CNSTOP
)
3363 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3365 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3368 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3369 word first. We should use the adjusted operand 1 (which is N+4(REG))
3370 for the low word as well, to compensate for the first decrement of
3372 if (optype0
== PUSHOP
3373 && reg_overlap_mentioned_p (XEXP (XEXP (operands
[0], 0), 0), operands
[1]))
3374 operands
[1] = middlehalf
[1] = latehalf
[1];
3376 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3377 if the upper part of reg N does not appear in the MEM, arrange to
3378 emit the move late-half first. Otherwise, compute the MEM address
3379 into the upper part of N and use that as a pointer to the memory
3381 if (optype0
== REGOP
3382 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3384 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3386 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3387 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3389 /* If both halves of dest are used in the src memory address,
3390 compute the address into latehalf of dest.
3391 Note that this can't happen if the dest is two data regs. */
3393 xops
[0] = latehalf
[0];
3394 xops
[1] = XEXP (operands
[1], 0);
3396 handle_compadr (xops
);
3397 if (GET_MODE (operands
[1]) == XFmode
)
3399 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3400 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3401 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3405 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3406 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3410 && reg_overlap_mentioned_p (middlehalf
[0],
3411 XEXP (operands
[1], 0)))
3413 /* Check for two regs used by both source and dest.
3414 Note that this can't happen if the dest is all data regs.
3415 It can happen if the dest is d6, d7, a0.
3416 But in that case, latehalf is an addr reg, so
3417 the code at compadr does ok. */
3419 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3420 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3423 /* JRV says this can't happen: */
3424 gcc_assert (!addreg0
&& !addreg1
);
3426 /* Only the middle reg conflicts; simply put it last. */
3427 handle_movsi (operands
);
3428 handle_movsi (latehalf
);
3429 handle_movsi (middlehalf
);
3433 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3434 /* If the low half of dest is mentioned in the source memory
3435 address, the arrange to emit the move late half first. */
3436 dest_overlapped_low
= 1;
3439 /* If one or both operands autodecrementing,
3440 do the two words, high-numbered first. */
3442 /* Likewise, the first move would clobber the source of the second one,
3443 do them in the other order. This happens only for registers;
3444 such overlap can't happen in memory unless the user explicitly
3445 sets it up, and that is an undefined circumstance. */
3447 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3448 || (optype0
== REGOP
&& optype1
== REGOP
3449 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3450 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3451 || dest_overlapped_low
)
3453 /* Make any unoffsettable addresses point at high-numbered word. */
3455 handle_reg_adjust (addreg0
, size
- 4);
3457 handle_reg_adjust (addreg1
, size
- 4);
3460 handle_movsi (latehalf
);
3462 /* Undo the adds we just did. */
3464 handle_reg_adjust (addreg0
, -4);
3466 handle_reg_adjust (addreg1
, -4);
3470 handle_movsi (middlehalf
);
3473 handle_reg_adjust (addreg0
, -4);
3475 handle_reg_adjust (addreg1
, -4);
3478 /* Do low-numbered word. */
3480 handle_movsi (operands
);
3484 /* Normal case: do the two words, low-numbered first. */
3486 m68k_final_prescan_insn (NULL
, operands
, 2);
3487 handle_movsi (operands
);
3489 /* Do the middle one of the three words for long double */
3493 handle_reg_adjust (addreg0
, 4);
3495 handle_reg_adjust (addreg1
, 4);
3497 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3498 handle_movsi (middlehalf
);
3501 /* Make any unoffsettable addresses point at high-numbered word. */
3503 handle_reg_adjust (addreg0
, 4);
3505 handle_reg_adjust (addreg1
, 4);
3508 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3509 handle_movsi (latehalf
);
3511 /* Undo the adds we just did. */
3513 handle_reg_adjust (addreg0
, -(size
- 4));
3515 handle_reg_adjust (addreg1
, -(size
- 4));
3520 /* Output assembler code to adjust REG by N. */
3522 output_reg_adjust (rtx reg
, int n
)
3526 gcc_assert (GET_MODE (reg
) == SImode
&& n
>= -12 && n
!= 0 && n
<= 12);
3531 s
= "add%.l #12,%0";
3535 s
= "addq%.l #8,%0";
3539 s
= "addq%.l #4,%0";
3543 s
= "sub%.l #12,%0";
3547 s
= "subq%.l #8,%0";
3551 s
= "subq%.l #4,%0";
3559 output_asm_insn (s
, ®
);
3562 /* Emit rtl code to adjust REG by N. */
3564 emit_reg_adjust (rtx reg1
, int n
)
3568 gcc_assert (GET_MODE (reg1
) == SImode
&& n
>= -12 && n
!= 0 && n
<= 12);
3570 reg1
= copy_rtx (reg1
);
3571 reg2
= copy_rtx (reg1
);
3574 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3576 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3581 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3583 output_compadr (rtx operands
[2])
3585 output_asm_insn ("lea %a1,%0", operands
);
3588 /* Output the best assembler insn for moving operands[1] into operands[0]
3591 output_movsi (rtx operands
[2])
3593 output_asm_insn (singlemove_string (operands
), operands
);
3596 /* Copy OP and change its mode to MODE. */
3598 copy_operand (rtx op
, machine_mode mode
)
3600 /* ??? This looks really ugly. There must be a better way
3601 to change a mode on the operand. */
3602 if (GET_MODE (op
) != VOIDmode
)
3605 op
= gen_rtx_REG (mode
, REGNO (op
));
3609 PUT_MODE (op
, mode
);
3616 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3618 emit_movsi (rtx operands
[2])
3620 operands
[0] = copy_operand (operands
[0], SImode
);
3621 operands
[1] = copy_operand (operands
[1], SImode
);
3623 emit_insn (gen_movsi (operands
[0], operands
[1]));
3626 /* Output assembler code to perform a doubleword move insn
3627 with operands OPERANDS. */
3629 output_move_double (rtx
*operands
)
3631 handle_move_double (operands
,
3632 output_reg_adjust
, output_compadr
, output_movsi
);
3637 /* Output rtl code to perform a doubleword move insn
3638 with operands OPERANDS. */
3640 m68k_emit_move_double (rtx operands
[2])
3642 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3645 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3646 new rtx with the correct mode. */
3649 force_mode (machine_mode mode
, rtx orig
)
3651 if (mode
== GET_MODE (orig
))
3654 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3657 return gen_rtx_REG (mode
, REGNO (orig
));
3661 fp_reg_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
3663 return reg_renumber
&& FP_REG_P (op
);
3666 /* Emit insns to move operands[1] into operands[0].
3668 Return 1 if we have written out everything that needs to be done to
3669 do the move. Otherwise, return 0 and the caller will emit the move
3672 Note SCRATCH_REG may not be in the proper mode depending on how it
3673 will be used. This routine is responsible for creating a new copy
3674 of SCRATCH_REG in the proper mode. */
3677 emit_move_sequence (rtx
*operands
, machine_mode mode
, rtx scratch_reg
)
3679 register rtx operand0
= operands
[0];
3680 register rtx operand1
= operands
[1];
3684 && reload_in_progress
&& GET_CODE (operand0
) == REG
3685 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3686 operand0
= reg_equiv_mem (REGNO (operand0
));
3687 else if (scratch_reg
3688 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3689 && GET_CODE (SUBREG_REG (operand0
)) == REG
3690 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3692 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3693 the code which tracks sets/uses for delete_output_reload. */
3694 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3695 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3696 SUBREG_BYTE (operand0
));
3697 operand0
= alter_subreg (&temp
, true);
3701 && reload_in_progress
&& GET_CODE (operand1
) == REG
3702 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3703 operand1
= reg_equiv_mem (REGNO (operand1
));
3704 else if (scratch_reg
3705 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3706 && GET_CODE (SUBREG_REG (operand1
)) == REG
3707 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3709 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3710 the code which tracks sets/uses for delete_output_reload. */
3711 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3712 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3713 SUBREG_BYTE (operand1
));
3714 operand1
= alter_subreg (&temp
, true);
3717 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3718 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3719 != XEXP (operand0
, 0)))
3720 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3721 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3722 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3723 != XEXP (operand1
, 0)))
3724 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3726 /* Handle secondary reloads for loads/stores of FP registers where
3727 the address is symbolic by using the scratch register */
3728 if (fp_reg_operand (operand0
, mode
)
3729 && ((GET_CODE (operand1
) == MEM
3730 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3731 || ((GET_CODE (operand1
) == SUBREG
3732 && GET_CODE (XEXP (operand1
, 0)) == MEM
3733 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3736 if (GET_CODE (operand1
) == SUBREG
)
3737 operand1
= XEXP (operand1
, 0);
3739 /* SCRATCH_REG will hold an address. We want
3740 it in SImode regardless of what mode it was originally given
3742 scratch_reg
= force_mode (SImode
, scratch_reg
);
3744 /* D might not fit in 14 bits either; for such cases load D into
3746 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3748 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3749 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3751 XEXP (XEXP (operand1
, 0), 0),
3755 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3756 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3759 else if (fp_reg_operand (operand1
, mode
)
3760 && ((GET_CODE (operand0
) == MEM
3761 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3762 || ((GET_CODE (operand0
) == SUBREG
)
3763 && GET_CODE (XEXP (operand0
, 0)) == MEM
3764 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3767 if (GET_CODE (operand0
) == SUBREG
)
3768 operand0
= XEXP (operand0
, 0);
3770 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3771 it in SIMODE regardless of what mode it was originally given
3773 scratch_reg
= force_mode (SImode
, scratch_reg
);
3775 /* D might not fit in 14 bits either; for such cases load D into
3777 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3779 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3780 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3783 XEXP (XEXP (operand0
, 0),
3788 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3789 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode
, scratch_reg
), operand1
));
3792 /* Handle secondary reloads for loads of FP registers from constant
3793 expressions by forcing the constant into memory.
3795 use scratch_reg to hold the address of the memory location.
3797 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3798 NO_REGS when presented with a const_int and an register class
3799 containing only FP registers. Doing so unfortunately creates
3800 more problems than it solves. Fix this for 2.5. */
3801 else if (fp_reg_operand (operand0
, mode
)
3802 && CONSTANT_P (operand1
)
3807 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3808 it in SIMODE regardless of what mode it was originally given
3810 scratch_reg
= force_mode (SImode
, scratch_reg
);
3812 /* Force the constant into memory and put the address of the
3813 memory location into scratch_reg. */
3814 xoperands
[0] = scratch_reg
;
3815 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3816 emit_insn (gen_rtx_SET (scratch_reg
, xoperands
[1]));
3818 /* Now load the destination register. */
3819 emit_insn (gen_rtx_SET (operand0
, gen_rtx_MEM (mode
, scratch_reg
)));
3823 /* Now have insn-emit do whatever it normally does. */
3827 /* Split one or more DImode RTL references into pairs of SImode
3828 references. The RTL can be REG, offsettable MEM, integer constant, or
3829 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3830 split and "num" is its length. lo_half and hi_half are output arrays
3831 that parallel "operands". */
3834 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3838 rtx op
= operands
[num
];
3840 /* simplify_subreg refuses to split volatile memory addresses,
3841 but we still have to handle it. */
3842 if (GET_CODE (op
) == MEM
)
3844 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3845 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3849 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3850 GET_MODE (op
) == VOIDmode
3851 ? DImode
: GET_MODE (op
), 4);
3852 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3853 GET_MODE (op
) == VOIDmode
3854 ? DImode
: GET_MODE (op
), 0);
3859 /* Split X into a base and a constant offset, storing them in *BASE
3860 and *OFFSET respectively. */
3863 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3866 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3868 *offset
+= INTVAL (XEXP (x
, 1));
3874 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3875 instruction. STORE_P says whether the move is a load or store.
3877 If the instruction uses post-increment or pre-decrement addressing,
3878 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3879 adjustment. This adjustment will be made by the first element of
3880 PARALLEL, with the loads or stores starting at element 1. If the
3881 instruction does not use post-increment or pre-decrement addressing,
3882 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3883 start at element 0. */
3886 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3887 HOST_WIDE_INT automod_offset
, bool store_p
)
3889 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3890 HOST_WIDE_INT offset
, mem_offset
;
3892 enum reg_class rclass
;
3894 len
= XVECLEN (pattern
, 0);
3895 first
= (automod_base
!= NULL
);
3899 /* Stores must be pre-decrement and loads must be post-increment. */
3900 if (store_p
!= (automod_offset
< 0))
3903 /* Work out the base and offset for lowest memory location. */
3904 base
= automod_base
;
3905 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3909 /* Allow any valid base and offset in the first access. */
3916 for (i
= first
; i
< len
; i
++)
3918 /* We need a plain SET. */
3919 set
= XVECEXP (pattern
, 0, i
);
3920 if (GET_CODE (set
) != SET
)
3923 /* Check that we have a memory location... */
3924 mem
= XEXP (set
, !store_p
);
3925 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3928 /* ...with the right address. */
3931 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3932 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3933 There are no mode restrictions for 680x0 besides the
3934 automodification rules enforced above. */
3936 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3941 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3942 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3946 /* Check that we have a register of the required mode and class. */
3947 reg
= XEXP (set
, store_p
);
3949 || !HARD_REGISTER_P (reg
)
3950 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3955 /* The register must belong to RCLASS and have a higher number
3956 than the register in the previous SET. */
3957 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3958 || REGNO (last_reg
) >= REGNO (reg
))
3963 /* Work out which register class we need. */
3964 if (INT_REGNO_P (REGNO (reg
)))
3965 rclass
= GENERAL_REGS
;
3966 else if (FP_REGNO_P (REGNO (reg
)))
3973 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3976 /* If we have an automodification, check whether the final offset is OK. */
3977 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3980 /* Reject unprofitable cases. */
3981 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
3987 /* Return the assembly code template for a movem or fmovem instruction
3988 whose pattern is given by PATTERN. Store the template's operands
3991 If the instruction uses post-increment or pre-decrement addressing,
3992 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3993 is true if this is a store instruction. */
3996 m68k_output_movem (rtx
*operands
, rtx pattern
,
3997 HOST_WIDE_INT automod_offset
, bool store_p
)
4002 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
4004 first
= (automod_offset
!= 0);
4005 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
4007 /* When using movem with pre-decrement addressing, register X + D0_REG
4008 is controlled by bit 15 - X. For all other addressing modes,
4009 register X + D0_REG is controlled by bit X. Confusingly, the
4010 register mask for fmovem is in the opposite order to that for
4014 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4015 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4016 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4017 if (automod_offset
< 0)
4019 if (FP_REGNO_P (regno
))
4020 mask
|= 1 << (regno
- FP0_REG
);
4022 mask
|= 1 << (15 - (regno
- D0_REG
));
4026 if (FP_REGNO_P (regno
))
4027 mask
|= 1 << (7 - (regno
- FP0_REG
));
4029 mask
|= 1 << (regno
- D0_REG
);
4034 if (automod_offset
== 0)
4035 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4036 else if (automod_offset
< 0)
4037 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4039 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4040 operands
[1] = GEN_INT (mask
);
4041 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4044 return "fmovem %1,%a0";
4046 return "fmovem %a0,%1";
4051 return "movem%.l %1,%a0";
4053 return "movem%.l %a0,%1";
4057 /* Return a REG that occurs in ADDR with coefficient 1.
4058 ADDR can be effectively incremented by incrementing REG. */
4061 find_addr_reg (rtx addr
)
4063 while (GET_CODE (addr
) == PLUS
)
4065 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4066 addr
= XEXP (addr
, 0);
4067 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4068 addr
= XEXP (addr
, 1);
4069 else if (CONSTANT_P (XEXP (addr
, 0)))
4070 addr
= XEXP (addr
, 1);
4071 else if (CONSTANT_P (XEXP (addr
, 1)))
4072 addr
= XEXP (addr
, 0);
4076 gcc_assert (GET_CODE (addr
) == REG
);
4080 /* Output assembler code to perform a 32-bit 3-operand add. */
4083 output_addsi3 (rtx
*operands
)
4085 if (! operands_match_p (operands
[0], operands
[1]))
4087 if (!ADDRESS_REG_P (operands
[1]))
4089 rtx tmp
= operands
[1];
4091 operands
[1] = operands
[2];
4095 /* These insns can result from reloads to access
4096 stack slots over 64k from the frame pointer. */
4097 if (GET_CODE (operands
[2]) == CONST_INT
4098 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4099 return "move%.l %2,%0\n\tadd%.l %1,%0";
4100 if (GET_CODE (operands
[2]) == REG
)
4101 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4102 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4104 if (GET_CODE (operands
[2]) == CONST_INT
)
4106 if (INTVAL (operands
[2]) > 0
4107 && INTVAL (operands
[2]) <= 8)
4108 return "addq%.l %2,%0";
4109 if (INTVAL (operands
[2]) < 0
4110 && INTVAL (operands
[2]) >= -8)
4112 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4113 return "subq%.l %2,%0";
4115 /* On the CPU32 it is faster to use two addql instructions to
4116 add a small integer (8 < N <= 16) to a register.
4117 Likewise for subql. */
4118 if (TUNE_CPU32
&& REG_P (operands
[0]))
4120 if (INTVAL (operands
[2]) > 8
4121 && INTVAL (operands
[2]) <= 16)
4123 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4124 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4126 if (INTVAL (operands
[2]) < -8
4127 && INTVAL (operands
[2]) >= -16)
4129 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4130 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4133 if (ADDRESS_REG_P (operands
[0])
4134 && INTVAL (operands
[2]) >= -0x8000
4135 && INTVAL (operands
[2]) < 0x8000)
4138 return "add%.w %2,%0";
4140 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4143 return "add%.l %2,%0";
4146 /* Store in cc_status the expressions that the condition codes will
4147 describe after execution of an instruction whose pattern is EXP.
4148 Do not alter them if the instruction would not alter the cc's. */
4150 /* On the 68000, all the insns to store in an address register fail to
4151 set the cc's. However, in some cases these instructions can make it
4152 possibly invalid to use the saved cc's. In those cases we clear out
4153 some or all of the saved cc's so they won't be used. */
4156 notice_update_cc (rtx exp
, rtx insn
)
4158 if (GET_CODE (exp
) == SET
)
4160 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4162 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4164 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4165 cc_status
.value1
= 0;
4166 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4167 cc_status
.value2
= 0;
4169 /* fmoves to memory or data registers do not set the condition
4170 codes. Normal moves _do_ set the condition codes, but not in
4171 a way that is appropriate for comparison with 0, because -0.0
4172 would be treated as a negative nonzero number. Note that it
4173 isn't appropriate to conditionalize this restriction on
4174 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4175 we care about the difference between -0.0 and +0.0. */
4176 else if (!FP_REG_P (SET_DEST (exp
))
4177 && SET_DEST (exp
) != cc0_rtx
4178 && (FP_REG_P (SET_SRC (exp
))
4179 || GET_CODE (SET_SRC (exp
)) == FIX
4180 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4182 /* A pair of move insns doesn't produce a useful overall cc. */
4183 else if (!FP_REG_P (SET_DEST (exp
))
4184 && !FP_REG_P (SET_SRC (exp
))
4185 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4186 && (GET_CODE (SET_SRC (exp
)) == REG
4187 || GET_CODE (SET_SRC (exp
)) == MEM
4188 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4190 else if (SET_DEST (exp
) != pc_rtx
)
4192 cc_status
.flags
= 0;
4193 cc_status
.value1
= SET_DEST (exp
);
4194 cc_status
.value2
= SET_SRC (exp
);
4197 else if (GET_CODE (exp
) == PARALLEL
4198 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4200 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4201 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4203 if (ADDRESS_REG_P (dest
))
4205 else if (dest
!= pc_rtx
)
4207 cc_status
.flags
= 0;
4208 cc_status
.value1
= dest
;
4209 cc_status
.value2
= src
;
4214 if (cc_status
.value2
!= 0
4215 && ADDRESS_REG_P (cc_status
.value2
)
4216 && GET_MODE (cc_status
.value2
) == QImode
)
4218 if (cc_status
.value2
!= 0)
4219 switch (GET_CODE (cc_status
.value2
))
4221 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4222 case ROTATE
: case ROTATERT
:
4223 /* These instructions always clear the overflow bit, and set
4224 the carry to the bit shifted out. */
4225 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4228 case PLUS
: case MINUS
: case MULT
:
4229 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4230 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4231 cc_status
.flags
|= CC_NO_OVERFLOW
;
4234 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4235 ends with a move insn moving r2 in r2's mode.
4236 Thus, the cc's are set for r2.
4237 This can set N bit spuriously. */
4238 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4243 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4245 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4246 cc_status
.value2
= 0;
4247 /* Check for PRE_DEC in dest modifying a register used in src. */
4248 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
4249 && GET_CODE (XEXP (cc_status
.value1
, 0)) == PRE_DEC
4251 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status
.value1
, 0), 0),
4253 cc_status
.value2
= 0;
4254 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4255 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4256 cc_status
.flags
= CC_IN_68881
;
4257 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4258 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4260 cc_status
.flags
= CC_IN_68881
;
4261 if (!FP_REG_P (XEXP (cc_status
.value2
, 0))
4262 && FP_REG_P (XEXP (cc_status
.value2
, 1)))
4263 cc_status
.flags
|= CC_REVERSED
;
4268 output_move_const_double (rtx
*operands
)
4270 int code
= standard_68881_constant_p (operands
[1]);
4274 static char buf
[40];
4276 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4279 return "fmove%.d %1,%0";
4283 output_move_const_single (rtx
*operands
)
4285 int code
= standard_68881_constant_p (operands
[1]);
4289 static char buf
[40];
4291 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4294 return "fmove%.s %f1,%0";
4297 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4298 from the "fmovecr" instruction.
4299 The value, anded with 0xff, gives the code to use in fmovecr
4300 to get the desired constant. */
4302 /* This code has been fixed for cross-compilation. */
4304 static int inited_68881_table
= 0;
4306 static const char *const strings_68881
[7] = {
4316 static const int codes_68881
[7] = {
4326 REAL_VALUE_TYPE values_68881
[7];
4328 /* Set up values_68881 array by converting the decimal values
4329 strings_68881 to binary. */
4332 init_68881_table (void)
4339 for (i
= 0; i
< 7; i
++)
4343 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4344 values_68881
[i
] = r
;
4346 inited_68881_table
= 1;
4350 standard_68881_constant_p (rtx x
)
4352 const REAL_VALUE_TYPE
*r
;
4355 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4356 used at all on those chips. */
4360 if (! inited_68881_table
)
4361 init_68881_table ();
4363 r
= CONST_DOUBLE_REAL_VALUE (x
);
4365 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4366 for (i
= 0; i
< 6; i
++)
4368 if (real_identical (r
, &values_68881
[i
]))
4369 return (codes_68881
[i
]);
4372 if (GET_MODE (x
) == SFmode
)
4375 if (real_equal (r
, &values_68881
[6]))
4376 return (codes_68881
[6]);
4378 /* larger powers of ten in the constants ram are not used
4379 because they are not equal to a `double' C constant. */
4383 /* If X is a floating-point constant, return the logarithm of X base 2,
4384 or 0 if X is not a power of 2. */
4387 floating_exact_log2 (rtx x
)
4389 const REAL_VALUE_TYPE
*r
;
4393 r
= CONST_DOUBLE_REAL_VALUE (x
);
4395 if (real_less (r
, &dconst1
))
4398 exp
= real_exponent (r
);
4399 real_2expN (&r1
, exp
, DFmode
);
4400 if (real_equal (&r1
, r
))
4406 /* A C compound statement to output to stdio stream STREAM the
4407 assembler syntax for an instruction operand X. X is an RTL
4410 CODE is a value that can be used to specify one of several ways
4411 of printing the operand. It is used when identical operands
4412 must be printed differently depending on the context. CODE
4413 comes from the `%' specification that was used to request
4414 printing of the operand. If the specification was just `%DIGIT'
4415 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4416 is the ASCII code for LTR.
4418 If X is a register, this macro should print the register's name.
4419 The names can be found in an array `reg_names' whose type is
4420 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4422 When the machine description has a specification `%PUNCT' (a `%'
4423 followed by a punctuation character), this macro is called with
4424 a null pointer for X and the punctuation character for CODE.
4426 The m68k specific codes are:
4428 '.' for dot needed in Motorola-style opcode names.
4429 '-' for an operand pushing on the stack:
4430 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4431 '+' for an operand pushing on the stack:
4432 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4433 '@' for a reference to the top word on the stack:
4434 sp@, (sp) or (%sp) depending on the style of syntax.
4435 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4436 but & in SGS syntax).
4437 '!' for the cc register (used in an `and to cc' insn).
4438 '$' for the letter `s' in an op code, but only on the 68040.
4439 '&' for the letter `d' in an op code, but only on the 68040.
4440 '/' for register prefix needed by longlong.h.
4441 '?' for m68k_library_id_string
4443 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4444 'd' to force memory addressing to be absolute, not relative.
4445 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4446 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4447 or print pair of registers as rx:ry.
4448 'p' print an address with @PLTPC attached, but only if the operand
4449 is not locally-bound. */
4452 print_operand (FILE *file
, rtx op
, int letter
)
4457 fprintf (file
, ".");
4459 else if (letter
== '#')
4460 asm_fprintf (file
, "%I");
4461 else if (letter
== '-')
4462 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4463 else if (letter
== '+')
4464 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4465 else if (letter
== '@')
4466 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4467 else if (letter
== '!')
4468 asm_fprintf (file
, "%Rfpcr");
4469 else if (letter
== '$')
4472 fprintf (file
, "s");
4474 else if (letter
== '&')
4477 fprintf (file
, "d");
4479 else if (letter
== '/')
4480 asm_fprintf (file
, "%R");
4481 else if (letter
== '?')
4482 asm_fprintf (file
, m68k_library_id_string
);
4483 else if (letter
== 'p')
4485 output_addr_const (file
, op
);
4486 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4487 fprintf (file
, "@PLTPC");
4489 else if (GET_CODE (op
) == REG
)
4492 /* Print out the second register name of a register pair.
4493 I.e., R (6) => 7. */
4494 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4496 fputs (M68K_REGNAME(REGNO (op
)), file
);
4498 else if (GET_CODE (op
) == MEM
)
4500 output_address (GET_MODE (op
), XEXP (op
, 0));
4501 if (letter
== 'd' && ! TARGET_68020
4502 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4503 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4504 && INTVAL (XEXP (op
, 0)) < 0x8000
4505 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4506 fprintf (file
, MOTOROLA
? ".l" : ":l");
4508 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4511 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4512 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4514 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4517 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4518 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4519 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4521 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4524 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
4525 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4529 /* Use `print_operand_address' instead of `output_addr_const'
4530 to ensure that we print relevant PIC stuff. */
4531 asm_fprintf (file
, "%I");
4533 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4534 print_operand_address (file
, op
);
4536 output_addr_const (file
, op
);
4540 /* Return string for TLS relocation RELOC. */
4543 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4545 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4546 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4553 if (flag_pic
== 1 && TARGET_68020
)
4595 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4598 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4600 if (GET_CODE (x
) == UNSPEC
)
4602 switch (XINT (x
, 1))
4604 case UNSPEC_RELOC16
:
4605 case UNSPEC_RELOC32
:
4606 output_addr_const (file
, XVECEXP (x
, 0, 0));
4607 fputs (m68k_get_reloc_decoration
4608 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4619 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4622 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4624 gcc_assert (size
== 4);
4625 fputs ("\t.long\t", file
);
4626 output_addr_const (file
, x
);
4627 fputs ("@TLSLDO+0x8000", file
);
4630 /* In the name of slightly smaller debug output, and to cater to
4631 general assembler lossage, recognize various UNSPEC sequences
4632 and turn them back into a direct symbol reference. */
4635 m68k_delegitimize_address (rtx orig_x
)
4638 struct m68k_address addr
;
4641 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4646 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4649 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4650 || addr
.offset
== NULL_RTX
4651 || GET_CODE (addr
.offset
) != CONST
)
4654 unspec
= XEXP (addr
.offset
, 0);
4655 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4656 unspec
= XEXP (unspec
, 0);
4657 if (GET_CODE (unspec
) != UNSPEC
4658 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4659 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4661 x
= XVECEXP (unspec
, 0, 0);
4662 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4663 if (unspec
!= XEXP (addr
.offset
, 0))
4664 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4667 rtx idx
= addr
.index
;
4668 if (addr
.scale
!= 1)
4669 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4670 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4673 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4675 x
= replace_equiv_address_nv (orig_x
, x
);
4680 /* A C compound statement to output to stdio stream STREAM the
4681 assembler syntax for an instruction operand that is a memory
4682 reference whose address is ADDR. ADDR is an RTL expression.
4684 Note that this contains a kludge that knows that the only reason
4685 we have an address (plus (label_ref...) (reg...)) when not generating
4686 PIC code is in the insn before a tablejump, and we know that m68k.md
4687 generates a label LInnn: on such an insn.
4689 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4690 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4692 This routine is responsible for distinguishing between -fpic and -fPIC
4693 style relocations in an address. When generating -fpic code the
4694 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4695 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4698 print_operand_address (FILE *file
, rtx addr
)
4700 struct m68k_address address
;
4702 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4705 if (address
.code
== PRE_DEC
)
4706 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4707 M68K_REGNAME (REGNO (address
.base
)));
4708 else if (address
.code
== POST_INC
)
4709 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4710 M68K_REGNAME (REGNO (address
.base
)));
4711 else if (!address
.base
&& !address
.index
)
4713 /* A constant address. */
4714 gcc_assert (address
.offset
== addr
);
4715 if (GET_CODE (addr
) == CONST_INT
)
4717 /* (xxx).w or (xxx).l. */
4718 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4719 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4721 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4723 else if (TARGET_PCREL
)
4725 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4727 output_addr_const (file
, addr
);
4728 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4732 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4733 name ends in `.<letter>', as the last 2 characters can be
4734 mistaken as a size suffix. Put the name in parentheses. */
4735 if (GET_CODE (addr
) == SYMBOL_REF
4736 && strlen (XSTR (addr
, 0)) > 2
4737 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4740 output_addr_const (file
, addr
);
4744 output_addr_const (file
, addr
);
4751 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4752 label being accessed, otherwise it is -1. */
4753 labelno
= (address
.offset
4755 && GET_CODE (address
.offset
) == LABEL_REF
4756 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4760 /* Print the "offset(base" component. */
4762 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4766 output_addr_const (file
, address
.offset
);
4770 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4772 /* Print the ",index" component, if any. */
4777 fprintf (file
, "%s.%c",
4778 M68K_REGNAME (REGNO (address
.index
)),
4779 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4780 if (address
.scale
!= 1)
4781 fprintf (file
, "*%d", address
.scale
);
4785 else /* !MOTOROLA */
4787 if (!address
.offset
&& !address
.index
)
4788 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4791 /* Print the "base@(offset" component. */
4793 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4797 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4798 fprintf (file
, "@(");
4800 output_addr_const (file
, address
.offset
);
4802 /* Print the ",index" component, if any. */
4805 fprintf (file
, ",%s:%c",
4806 M68K_REGNAME (REGNO (address
.index
)),
4807 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4808 if (address
.scale
!= 1)
4809 fprintf (file
, ":%d", address
.scale
);
4817 /* Check for cases where a clr insns can be omitted from code using
4818 strict_low_part sets. For example, the second clrl here is not needed:
4819 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4821 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4822 insn we are checking for redundancy. TARGET is the register set by the
4826 strict_low_part_peephole_ok (machine_mode mode
, rtx_insn
*first_insn
,
4829 rtx_insn
*p
= first_insn
;
4831 while ((p
= PREV_INSN (p
)))
4833 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4839 /* If it isn't an insn, then give up. */
4843 if (reg_set_p (target
, p
))
4845 rtx set
= single_set (p
);
4848 /* If it isn't an easy to recognize insn, then give up. */
4852 dest
= SET_DEST (set
);
4854 /* If this sets the entire target register to zero, then our
4855 first_insn is redundant. */
4856 if (rtx_equal_p (dest
, target
)
4857 && SET_SRC (set
) == const0_rtx
)
4859 else if (GET_CODE (dest
) == STRICT_LOW_PART
4860 && GET_CODE (XEXP (dest
, 0)) == REG
4861 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4862 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4863 <= GET_MODE_SIZE (mode
)))
4864 /* This is a strict low part set which modifies less than
4865 we are using, so it is safe. */
4875 /* Operand predicates for implementing asymmetric pc-relative addressing
4876 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4877 when used as a source operand, but not as a destination operand.
4879 We model this by restricting the meaning of the basic predicates
4880 (general_operand, memory_operand, etc) to forbid the use of this
4881 addressing mode, and then define the following predicates that permit
4882 this addressing mode. These predicates can then be used for the
4883 source operands of the appropriate instructions.
4885 n.b. While it is theoretically possible to change all machine patterns
4886 to use this addressing more where permitted by the architecture,
4887 it has only been implemented for "common" cases: SImode, HImode, and
4888 QImode operands, and only for the principle operations that would
4889 require this addressing mode: data movement and simple integer operations.
4891 In parallel with these new predicates, two new constraint letters
4892 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4893 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4894 In the pcrel case 's' is only valid in combination with 'a' registers.
4895 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4896 of how these constraints are used.
4898 The use of these predicates is strictly optional, though patterns that
4899 don't will cause an extra reload register to be allocated where one
4902 lea (abc:w,%pc),%a0 ; need to reload address
4903 moveq &1,%d1 ; since write to pc-relative space
4904 movel %d1,%a0@ ; is not allowed
4906 lea (abc:w,%pc),%a1 ; no need to reload address here
4907 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4909 For more info, consult tiemann@cygnus.com.
4912 All of the ugliness with predicates and constraints is due to the
4913 simple fact that the m68k does not allow a pc-relative addressing
4914 mode as a destination. gcc does not distinguish between source and
4915 destination addresses. Hence, if we claim that pc-relative address
4916 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4917 end up with invalid code. To get around this problem, we left
4918 pc-relative modes as invalid addresses, and then added special
4919 predicates and constraints to accept them.
4921 A cleaner way to handle this is to modify gcc to distinguish
4922 between source and destination addresses. We can then say that
4923 pc-relative is a valid source address but not a valid destination
4924 address, and hopefully avoid a lot of the predicate and constraint
4925 hackery. Unfortunately, this would be a pretty big change. It would
4926 be a useful change for a number of ports, but there aren't any current
4927 plans to undertake this.
4929 ***************************************************************************/
4933 output_andsi3 (rtx
*operands
)
4936 if (GET_CODE (operands
[2]) == CONST_INT
4937 && (INTVAL (operands
[2]) | 0xffff) == -1
4938 && (DATA_REG_P (operands
[0])
4939 || offsettable_memref_p (operands
[0]))
4940 && !TARGET_COLDFIRE
)
4942 if (GET_CODE (operands
[0]) != REG
)
4943 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4944 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4945 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4947 if (operands
[2] == const0_rtx
)
4949 return "and%.w %2,%0";
4951 if (GET_CODE (operands
[2]) == CONST_INT
4952 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4953 && (DATA_REG_P (operands
[0])
4954 || offsettable_memref_p (operands
[0])))
4956 if (DATA_REG_P (operands
[0]))
4957 operands
[1] = GEN_INT (logval
);
4960 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4961 operands
[1] = GEN_INT (logval
% 8);
4963 /* This does not set condition codes in a standard way. */
4965 return "bclr %1,%0";
4967 return "and%.l %2,%0";
4971 output_iorsi3 (rtx
*operands
)
4973 register int logval
;
4974 if (GET_CODE (operands
[2]) == CONST_INT
4975 && INTVAL (operands
[2]) >> 16 == 0
4976 && (DATA_REG_P (operands
[0])
4977 || offsettable_memref_p (operands
[0]))
4978 && !TARGET_COLDFIRE
)
4980 if (GET_CODE (operands
[0]) != REG
)
4981 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4982 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4984 if (INTVAL (operands
[2]) == 0xffff)
4985 return "mov%.w %2,%0";
4986 return "or%.w %2,%0";
4988 if (GET_CODE (operands
[2]) == CONST_INT
4989 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
4990 && (DATA_REG_P (operands
[0])
4991 || offsettable_memref_p (operands
[0])))
4993 if (DATA_REG_P (operands
[0]))
4994 operands
[1] = GEN_INT (logval
);
4997 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4998 operands
[1] = GEN_INT (logval
% 8);
5001 return "bset %1,%0";
5003 return "or%.l %2,%0";
5007 output_xorsi3 (rtx
*operands
)
5009 register int logval
;
5010 if (GET_CODE (operands
[2]) == CONST_INT
5011 && INTVAL (operands
[2]) >> 16 == 0
5012 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5013 && !TARGET_COLDFIRE
)
5015 if (! DATA_REG_P (operands
[0]))
5016 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5017 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5019 if (INTVAL (operands
[2]) == 0xffff)
5021 return "eor%.w %2,%0";
5023 if (GET_CODE (operands
[2]) == CONST_INT
5024 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5025 && (DATA_REG_P (operands
[0])
5026 || offsettable_memref_p (operands
[0])))
5028 if (DATA_REG_P (operands
[0]))
5029 operands
[1] = GEN_INT (logval
);
5032 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5033 operands
[1] = GEN_INT (logval
% 8);
5036 return "bchg %1,%0";
5038 return "eor%.l %2,%0";
5041 /* Return the instruction that should be used for a call to address X,
5042 which is known to be in operand 0. */
5047 if (symbolic_operand (x
, VOIDmode
))
5048 return m68k_symbolic_call
;
5053 /* Likewise sibling calls. */
5056 output_sibcall (rtx x
)
5058 if (symbolic_operand (x
, VOIDmode
))
5059 return m68k_symbolic_jump
;
5065 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5066 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5069 rtx this_slot
, offset
, addr
, mem
, tmp
;
5072 /* Avoid clobbering the struct value reg by using the
5073 static chain reg as a temporary. */
5074 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5076 /* Pretend to be a post-reload pass while generating rtl. */
5077 reload_completed
= 1;
5079 /* The "this" pointer is stored at 4(%sp). */
5080 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (Pmode
,
5081 stack_pointer_rtx
, 4));
5083 /* Add DELTA to THIS. */
5086 /* Make the offset a legitimate operand for memory addition. */
5087 offset
= GEN_INT (delta
);
5088 if ((delta
< -8 || delta
> 8)
5089 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5091 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5092 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5094 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5095 copy_rtx (this_slot
), offset
));
5098 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5099 if (vcall_offset
!= 0)
5101 /* Set the static chain register to *THIS. */
5102 emit_move_insn (tmp
, this_slot
);
5103 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5105 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5106 addr
= plus_constant (Pmode
, tmp
, vcall_offset
);
5107 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5109 emit_insn (gen_rtx_SET (tmp
, addr
));
5113 /* Load the offset into %d0 and add it to THIS. */
5114 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5115 gen_rtx_MEM (Pmode
, addr
));
5116 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5117 copy_rtx (this_slot
),
5118 gen_rtx_REG (Pmode
, D0_REG
)));
5121 /* Jump to the target function. Use a sibcall if direct jumps are
5122 allowed, otherwise load the address into a register first. */
5123 mem
= DECL_RTL (function
);
5124 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5126 gcc_assert (flag_pic
);
5128 if (!TARGET_SEP_DATA
)
5130 /* Use the static chain register as a temporary (call-clobbered)
5131 GOT pointer for this function. We can use the static chain
5132 register because it isn't live on entry to the thunk. */
5133 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5134 emit_insn (gen_load_got (pic_offset_table_rtx
));
5136 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5137 mem
= replace_equiv_address (mem
, tmp
);
5139 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5140 SIBLING_CALL_P (insn
) = 1;
5142 /* Run just enough of rest_of_compilation. */
5143 insn
= get_insns ();
5144 split_all_insns_noflow ();
5145 final_start_function (insn
, file
, 1);
5146 final (insn
, file
, 1);
5147 final_end_function ();
5149 /* Clean up the vars set above. */
5150 reload_completed
= 0;
5152 /* Restore the original PIC register. */
5154 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5157 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5160 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5161 int incoming ATTRIBUTE_UNUSED
)
5163 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5166 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5168 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5169 unsigned int new_reg
)
5172 /* Interrupt functions can only use registers that have already been
5173 saved by the prologue, even if they would normally be
5176 if ((m68k_get_function_kind (current_function_decl
)
5177 == m68k_fk_interrupt_handler
)
5178 && !df_regs_ever_live_p (new_reg
))
5184 /* Implement TARGET_HARD_REGNO_NREGS.
5186 On the m68k, ordinary registers hold 32 bits worth;
5187 for the 68881 registers, a single register is always enough for
5188 anything that can be stored in them at all. */
5191 m68k_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
5194 return GET_MODE_NUNITS (mode
);
5195 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
5198 /* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
5199 registers can hold any mode, but restrict the 68881 registers to
5200 floating-point modes. */
5203 m68k_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
5205 if (DATA_REGNO_P (regno
))
5207 /* Data Registers, can hold aggregate if fits in. */
5208 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5211 else if (ADDRESS_REGNO_P (regno
))
5213 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5216 else if (FP_REGNO_P (regno
))
5218 /* FPU registers, hold float or complex float of long double or
5220 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5221 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5222 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5228 /* Implement TARGET_MODES_TIEABLE_P. */
5231 m68k_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
5233 return (!TARGET_HARD_FLOAT
5234 || ((GET_MODE_CLASS (mode1
) == MODE_FLOAT
5235 || GET_MODE_CLASS (mode1
) == MODE_COMPLEX_FLOAT
)
5236 == (GET_MODE_CLASS (mode2
) == MODE_FLOAT
5237 || GET_MODE_CLASS (mode2
) == MODE_COMPLEX_FLOAT
)));
5240 /* Implement SECONDARY_RELOAD_CLASS. */
5243 m68k_secondary_reload_class (enum reg_class rclass
,
5244 machine_mode mode
, rtx x
)
5248 regno
= true_regnum (x
);
5250 /* If one operand of a movqi is an address register, the other
5251 operand must be a general register or constant. Other types
5252 of operand must be reloaded through a data register. */
5253 if (GET_MODE_SIZE (mode
) == 1
5254 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5255 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5258 /* PC-relative addresses must be loaded into an address register first. */
5260 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5261 && symbolic_operand (x
, VOIDmode
))
5267 /* Implement PREFERRED_RELOAD_CLASS. */
5270 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5272 enum reg_class secondary_class
;
5274 /* If RCLASS might need a secondary reload, try restricting it to
5275 a class that doesn't. */
5276 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5277 if (secondary_class
!= NO_REGS
5278 && reg_class_subset_p (secondary_class
, rclass
))
5279 return secondary_class
;
5281 /* Prefer to use moveq for in-range constants. */
5282 if (GET_CODE (x
) == CONST_INT
5283 && reg_class_subset_p (DATA_REGS
, rclass
)
5284 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5287 /* ??? Do we really need this now? */
5288 if (GET_CODE (x
) == CONST_DOUBLE
5289 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5291 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5300 /* Return floating point values in a 68881 register. This makes 68881 code
5301 a little bit faster. It also makes -msoft-float code incompatible with
5302 hard-float code, so people have to be careful not to mix the two.
5303 For ColdFire it was decided the ABI incompatibility is undesirable.
5304 If there is need for a hard-float ABI it is probably worth doing it
5305 properly and also passing function arguments in FP registers. */
5307 m68k_libcall_value (machine_mode mode
)
5314 return gen_rtx_REG (mode
, FP0_REG
);
5320 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5323 /* Location in which function value is returned.
5324 NOTE: Due to differences in ABIs, don't call this function directly,
5325 use FUNCTION_VALUE instead. */
5327 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5331 mode
= TYPE_MODE (valtype
);
5337 return gen_rtx_REG (mode
, FP0_REG
);
5343 /* If the function returns a pointer, push that into %a0. */
5344 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5345 /* For compatibility with the large body of existing code which
5346 does not always properly declare external functions returning
5347 pointer types, the m68k/SVR4 convention is to copy the value
5348 returned for pointer functions from a0 to d0 in the function
5349 epilogue, so that callers that have neglected to properly
5350 declare the callee can still find the correct return value in
5352 return gen_rtx_PARALLEL
5355 gen_rtx_EXPR_LIST (VOIDmode
,
5356 gen_rtx_REG (mode
, A0_REG
),
5358 gen_rtx_EXPR_LIST (VOIDmode
,
5359 gen_rtx_REG (mode
, D0_REG
),
5361 else if (POINTER_TYPE_P (valtype
))
5362 return gen_rtx_REG (mode
, A0_REG
);
5364 return gen_rtx_REG (mode
, D0_REG
);
5367 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5368 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5370 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5372 machine_mode mode
= TYPE_MODE (type
);
5374 if (mode
== BLKmode
)
5377 /* If TYPE's known alignment is less than the alignment of MODE that
5378 would contain the structure, then return in memory. We need to
5379 do so to maintain the compatibility between code compiled with
5380 -mstrict-align and that compiled with -mno-strict-align. */
5381 if (AGGREGATE_TYPE_P (type
)
5382 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5389 /* CPU to schedule the program for. */
5390 enum attr_cpu m68k_sched_cpu
;
5392 /* MAC to schedule the program for. */
5393 enum attr_mac m68k_sched_mac
;
5401 /* Integer register. */
5407 /* Implicit mem reference (e.g. stack). */
5410 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5413 /* Memory with offset but without indexing. EA mode 5. */
5416 /* Memory with indexing. EA mode 6. */
5419 /* Memory referenced by absolute address. EA mode 7. */
5422 /* Immediate operand that doesn't require extension word. */
5425 /* Immediate 16 bit operand. */
5428 /* Immediate 32 bit operand. */
5432 /* Return type of memory ADDR_RTX refers to. */
5433 static enum attr_op_type
5434 sched_address_type (machine_mode mode
, rtx addr_rtx
)
5436 struct m68k_address address
;
5438 if (symbolic_operand (addr_rtx
, VOIDmode
))
5439 return OP_TYPE_MEM7
;
5441 if (!m68k_decompose_address (mode
, addr_rtx
,
5442 reload_completed
, &address
))
5444 gcc_assert (!reload_completed
);
5445 /* Reload will likely fix the address to be in the register. */
5446 return OP_TYPE_MEM234
;
5449 if (address
.scale
!= 0)
5450 return OP_TYPE_MEM6
;
5452 if (address
.base
!= NULL_RTX
)
5454 if (address
.offset
== NULL_RTX
)
5455 return OP_TYPE_MEM234
;
5457 return OP_TYPE_MEM5
;
5460 gcc_assert (address
.offset
!= NULL_RTX
);
5462 return OP_TYPE_MEM7
;
5465 /* Return X or Y (depending on OPX_P) operand of INSN. */
5467 sched_get_operand (rtx_insn
*insn
, bool opx_p
)
5471 if (recog_memoized (insn
) < 0)
5474 extract_constrain_insn_cached (insn
);
5477 i
= get_attr_opx (insn
);
5479 i
= get_attr_opy (insn
);
5481 if (i
>= recog_data
.n_operands
)
5484 return recog_data
.operand
[i
];
5487 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5488 If ADDRESS_P is true, return type of memory location operand refers to. */
5489 static enum attr_op_type
5490 sched_attr_op_type (rtx_insn
*insn
, bool opx_p
, bool address_p
)
5494 op
= sched_get_operand (insn
, opx_p
);
5498 gcc_assert (!reload_completed
);
5503 return sched_address_type (QImode
, op
);
5505 if (memory_operand (op
, VOIDmode
))
5506 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5508 if (register_operand (op
, VOIDmode
))
5510 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5511 || (reload_completed
&& FP_REG_P (op
)))
5517 if (GET_CODE (op
) == CONST_INT
)
5523 /* Check for quick constants. */
5524 switch (get_attr_type (insn
))
5527 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5528 return OP_TYPE_IMM_Q
;
5530 gcc_assert (!reload_completed
);
5534 if (USE_MOVQ (ival
))
5535 return OP_TYPE_IMM_Q
;
5537 gcc_assert (!reload_completed
);
5541 if (valid_mov3q_const (ival
))
5542 return OP_TYPE_IMM_Q
;
5544 gcc_assert (!reload_completed
);
5551 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5552 return OP_TYPE_IMM_W
;
5554 return OP_TYPE_IMM_L
;
5557 if (GET_CODE (op
) == CONST_DOUBLE
)
5559 switch (GET_MODE (op
))
5562 return OP_TYPE_IMM_W
;
5566 return OP_TYPE_IMM_L
;
5573 if (GET_CODE (op
) == CONST
5574 || symbolic_operand (op
, VOIDmode
)
5577 switch (GET_MODE (op
))
5580 return OP_TYPE_IMM_Q
;
5583 return OP_TYPE_IMM_W
;
5586 return OP_TYPE_IMM_L
;
5589 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5591 return OP_TYPE_IMM_W
;
5593 return OP_TYPE_IMM_L
;
5597 gcc_assert (!reload_completed
);
5599 if (FLOAT_MODE_P (GET_MODE (op
)))
5605 /* Implement opx_type attribute.
5606 Return type of INSN's operand X.
5607 If ADDRESS_P is true, return type of memory location operand refers to. */
5609 m68k_sched_attr_opx_type (rtx_insn
*insn
, int address_p
)
5611 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5617 return OPX_TYPE_FPN
;
5620 return OPX_TYPE_MEM1
;
5622 case OP_TYPE_MEM234
:
5623 return OPX_TYPE_MEM234
;
5626 return OPX_TYPE_MEM5
;
5629 return OPX_TYPE_MEM6
;
5632 return OPX_TYPE_MEM7
;
5635 return OPX_TYPE_IMM_Q
;
5638 return OPX_TYPE_IMM_W
;
5641 return OPX_TYPE_IMM_L
;
5648 /* Implement opy_type attribute.
5649 Return type of INSN's operand Y.
5650 If ADDRESS_P is true, return type of memory location operand refers to. */
5652 m68k_sched_attr_opy_type (rtx_insn
*insn
, int address_p
)
5654 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5660 return OPY_TYPE_FPN
;
5663 return OPY_TYPE_MEM1
;
5665 case OP_TYPE_MEM234
:
5666 return OPY_TYPE_MEM234
;
5669 return OPY_TYPE_MEM5
;
5672 return OPY_TYPE_MEM6
;
5675 return OPY_TYPE_MEM7
;
5678 return OPY_TYPE_IMM_Q
;
5681 return OPY_TYPE_IMM_W
;
5684 return OPY_TYPE_IMM_L
;
5691 /* Return size of INSN as int. */
5693 sched_get_attr_size_int (rtx_insn
*insn
)
5697 switch (get_attr_type (insn
))
5700 /* There should be no references to m68k_sched_attr_size for 'ignore'
5714 switch (get_attr_opx_type (insn
))
5720 case OPX_TYPE_MEM234
:
5721 case OPY_TYPE_IMM_Q
:
5726 /* Here we assume that most absolute references are short. */
5728 case OPY_TYPE_IMM_W
:
5732 case OPY_TYPE_IMM_L
:
5740 switch (get_attr_opy_type (insn
))
5746 case OPY_TYPE_MEM234
:
5747 case OPY_TYPE_IMM_Q
:
5752 /* Here we assume that most absolute references are short. */
5754 case OPY_TYPE_IMM_W
:
5758 case OPY_TYPE_IMM_L
:
5768 gcc_assert (!reload_completed
);
5776 /* Return size of INSN as attribute enum value. */
5778 m68k_sched_attr_size (rtx_insn
*insn
)
5780 switch (sched_get_attr_size_int (insn
))
5796 /* Return operand X or Y (depending on OPX_P) of INSN,
5797 if it is a MEM, or NULL overwise. */
5798 static enum attr_op_type
5799 sched_get_opxy_mem_type (rtx_insn
*insn
, bool opx_p
)
5803 switch (get_attr_opx_type (insn
))
5808 case OPX_TYPE_IMM_Q
:
5809 case OPX_TYPE_IMM_W
:
5810 case OPX_TYPE_IMM_L
:
5814 case OPX_TYPE_MEM234
:
5817 return OP_TYPE_MEM1
;
5820 return OP_TYPE_MEM6
;
5828 switch (get_attr_opy_type (insn
))
5833 case OPY_TYPE_IMM_Q
:
5834 case OPY_TYPE_IMM_W
:
5835 case OPY_TYPE_IMM_L
:
5839 case OPY_TYPE_MEM234
:
5842 return OP_TYPE_MEM1
;
5845 return OP_TYPE_MEM6
;
5853 /* Implement op_mem attribute. */
5855 m68k_sched_attr_op_mem (rtx_insn
*insn
)
5857 enum attr_op_type opx
;
5858 enum attr_op_type opy
;
5860 opx
= sched_get_opxy_mem_type (insn
, true);
5861 opy
= sched_get_opxy_mem_type (insn
, false);
5863 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5866 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5868 switch (get_attr_opx_access (insn
))
5884 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5886 switch (get_attr_opx_access (insn
))
5902 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5905 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5907 switch (get_attr_opx_access (insn
))
5913 gcc_assert (!reload_completed
);
5918 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5920 switch (get_attr_opx_access (insn
))
5926 gcc_assert (!reload_completed
);
5931 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5934 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5936 switch (get_attr_opx_access (insn
))
5942 gcc_assert (!reload_completed
);
5947 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5948 gcc_assert (!reload_completed
);
5952 /* Data for ColdFire V4 index bypass.
5953 Producer modifies register that is used as index in consumer with
5957 /* Producer instruction. */
5960 /* Consumer instruction. */
5963 /* Scale of indexed memory access within consumer.
5964 Or zero if bypass should not be effective at the moment. */
5966 } sched_cfv4_bypass_data
;
5968 /* An empty state that is used in m68k_sched_adjust_cost. */
5969 static state_t sched_adjust_cost_state
;
5971 /* Implement adjust_cost scheduler hook.
5972 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5974 m68k_sched_adjust_cost (rtx_insn
*insn
, int, rtx_insn
*def_insn
, int cost
,
5979 if (recog_memoized (def_insn
) < 0
5980 || recog_memoized (insn
) < 0)
5983 if (sched_cfv4_bypass_data
.scale
== 1)
5984 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5986 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5987 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5988 that the data in sched_cfv4_bypass_data is up to date. */
5989 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5990 && sched_cfv4_bypass_data
.con
== insn
);
5995 sched_cfv4_bypass_data
.pro
= NULL
;
5996 sched_cfv4_bypass_data
.con
= NULL
;
5997 sched_cfv4_bypass_data
.scale
= 0;
6000 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6001 && sched_cfv4_bypass_data
.con
== NULL
6002 && sched_cfv4_bypass_data
.scale
== 0);
6004 /* Don't try to issue INSN earlier than DFA permits.
6005 This is especially useful for instructions that write to memory,
6006 as their true dependence (default) latency is better to be set to 0
6007 to workaround alias analysis limitations.
6008 This is, in fact, a machine independent tweak, so, probably,
6009 it should be moved to haifa-sched.c: insn_cost (). */
6010 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
6017 /* Return maximal number of insns that can be scheduled on a single cycle. */
6019 m68k_sched_issue_rate (void)
6021 switch (m68k_sched_cpu
)
6037 /* Maximal length of instruction for current CPU.
6038 E.g. it is 3 for any ColdFire core. */
6039 static int max_insn_size
;
6041 /* Data to model instruction buffer of CPU. */
6044 /* True if instruction buffer model is modeled for current CPU. */
6047 /* Size of the instruction buffer in words. */
6050 /* Number of filled words in the instruction buffer. */
6053 /* Additional information about instruction buffer for CPUs that have
6054 a buffer of instruction records, rather then a plain buffer
6055 of instruction words. */
6056 struct _sched_ib_records
6058 /* Size of buffer in records. */
6061 /* Array to hold data on adjustments made to the size of the buffer. */
6064 /* Index of the above array. */
6068 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6072 static struct _sched_ib sched_ib
;
6074 /* ID of memory unit. */
6075 static int sched_mem_unit_code
;
6077 /* Implementation of the targetm.sched.variable_issue () hook.
6078 It is called after INSN was issued. It returns the number of insns
6079 that can possibly get scheduled on the current cycle.
6080 It is used here to determine the effect of INSN on the instruction
6083 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6084 int sched_verbose ATTRIBUTE_UNUSED
,
6085 rtx_insn
*insn
, int can_issue_more
)
6089 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6091 switch (m68k_sched_cpu
)
6095 insn_size
= sched_get_attr_size_int (insn
);
6099 insn_size
= sched_get_attr_size_int (insn
);
6101 /* ColdFire V3 and V4 cores have instruction buffers that can
6102 accumulate up to 8 instructions regardless of instructions'
6103 sizes. So we should take care not to "prefetch" 24 one-word
6104 or 12 two-words instructions.
6105 To model this behavior we temporarily decrease size of the
6106 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6110 adjust
= max_insn_size
- insn_size
;
6111 sched_ib
.size
-= adjust
;
6113 if (sched_ib
.filled
> sched_ib
.size
)
6114 sched_ib
.filled
= sched_ib
.size
;
6116 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6119 ++sched_ib
.records
.adjust_index
;
6120 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6121 sched_ib
.records
.adjust_index
= 0;
6123 /* Undo adjustment we did 7 instructions ago. */
6125 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6130 gcc_assert (!sched_ib
.enabled_p
);
6138 if (insn_size
> sched_ib
.filled
)
6139 /* Scheduling for register pressure does not always take DFA into
6140 account. Workaround instruction buffer not being filled enough. */
6142 gcc_assert (sched_pressure
== SCHED_PRESSURE_WEIGHTED
);
6143 insn_size
= sched_ib
.filled
;
6148 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6149 || asm_noperands (PATTERN (insn
)) >= 0)
6150 insn_size
= sched_ib
.filled
;
6154 sched_ib
.filled
-= insn_size
;
6156 return can_issue_more
;
6159 /* Return how many instructions should scheduler lookahead to choose the
6162 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6164 return m68k_sched_issue_rate () - 1;
6167 /* Implementation of targetm.sched.init_global () hook.
6168 It is invoked once per scheduling pass and is used here
6169 to initialize scheduler constants. */
6171 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6172 int sched_verbose ATTRIBUTE_UNUSED
,
6173 int n_insns ATTRIBUTE_UNUSED
)
6175 /* Check that all instructions have DFA reservations and
6176 that all instructions can be issued from a clean state. */
6182 state
= alloca (state_size ());
6184 for (insn
= get_insns (); insn
!= NULL
; insn
= NEXT_INSN (insn
))
6186 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6188 gcc_assert (insn_has_dfa_reservation_p (insn
));
6190 state_reset (state
);
6191 if (state_transition (state
, insn
) >= 0)
6197 /* Setup target cpu. */
6199 /* ColdFire V4 has a set of features to keep its instruction buffer full
6200 (e.g., a separate memory bus for instructions) and, hence, we do not model
6201 buffer for this CPU. */
6202 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6204 switch (m68k_sched_cpu
)
6207 sched_ib
.filled
= 0;
6214 sched_ib
.records
.n_insns
= 0;
6215 sched_ib
.records
.adjust
= NULL
;
6220 sched_ib
.records
.n_insns
= 8;
6221 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6228 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6230 sched_adjust_cost_state
= xmalloc (state_size ());
6231 state_reset (sched_adjust_cost_state
);
6234 emit_insn (gen_ib ());
6235 sched_ib
.insn
= get_insns ();
6239 /* Scheduling pass is now finished. Free/reset static variables. */
6241 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6242 int verbose ATTRIBUTE_UNUSED
)
6244 sched_ib
.insn
= NULL
;
6246 free (sched_adjust_cost_state
);
6247 sched_adjust_cost_state
= NULL
;
6249 sched_mem_unit_code
= 0;
6251 free (sched_ib
.records
.adjust
);
6252 sched_ib
.records
.adjust
= NULL
;
6253 sched_ib
.records
.n_insns
= 0;
6257 /* Implementation of targetm.sched.init () hook.
6258 It is invoked each time scheduler starts on the new block (basic block or
6259 extended basic block). */
6261 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6262 int sched_verbose ATTRIBUTE_UNUSED
,
6263 int n_insns ATTRIBUTE_UNUSED
)
6265 switch (m68k_sched_cpu
)
6273 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6275 memset (sched_ib
.records
.adjust
, 0,
6276 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6277 sched_ib
.records
.adjust_index
= 0;
6281 gcc_assert (!sched_ib
.enabled_p
);
6289 if (sched_ib
.enabled_p
)
6290 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6291 the first cycle. Workaround that. */
6292 sched_ib
.filled
= -2;
6295 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6296 It is invoked just before current cycle finishes and is used here
6297 to track if instruction buffer got its two words this cycle. */
6299 m68k_sched_dfa_pre_advance_cycle (void)
6301 if (!sched_ib
.enabled_p
)
6304 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6306 sched_ib
.filled
+= 2;
6308 if (sched_ib
.filled
> sched_ib
.size
)
6309 sched_ib
.filled
= sched_ib
.size
;
6313 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6314 It is invoked just after new cycle begins and is used here
6315 to setup number of filled words in the instruction buffer so that
6316 instructions which won't have all their words prefetched would be
6317 stalled for a cycle. */
6319 m68k_sched_dfa_post_advance_cycle (void)
6323 if (!sched_ib
.enabled_p
)
6326 /* Setup number of prefetched instruction words in the instruction
6328 i
= max_insn_size
- sched_ib
.filled
;
6332 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6333 /* Pick up scheduler state. */
6338 /* Return X or Y (depending on OPX_P) operand of INSN,
6339 if it is an integer register, or NULL overwise. */
6341 sched_get_reg_operand (rtx_insn
*insn
, bool opx_p
)
6347 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6349 op
= sched_get_operand (insn
, true);
6350 gcc_assert (op
!= NULL
);
6352 if (!reload_completed
&& !REG_P (op
))
6358 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6360 op
= sched_get_operand (insn
, false);
6361 gcc_assert (op
!= NULL
);
6363 if (!reload_completed
&& !REG_P (op
))
6371 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6374 sched_mem_operand_p (rtx_insn
*insn
, bool opx_p
)
6376 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6387 /* Return X or Y (depending on OPX_P) operand of INSN,
6388 if it is a MEM, or NULL overwise. */
6390 sched_get_mem_operand (rtx_insn
*insn
, bool must_read_p
, bool must_write_p
)
6410 if (opy_p
&& sched_mem_operand_p (insn
, false))
6411 return sched_get_operand (insn
, false);
6413 if (opx_p
&& sched_mem_operand_p (insn
, true))
6414 return sched_get_operand (insn
, true);
6420 /* Return non-zero if PRO modifies register used as part of
6423 m68k_sched_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6428 pro_x
= sched_get_reg_operand (pro
, true);
6432 con_mem_read
= sched_get_mem_operand (con
, true, false);
6433 gcc_assert (con_mem_read
!= NULL
);
6435 if (reg_mentioned_p (pro_x
, con_mem_read
))
6441 /* Helper function for m68k_sched_indexed_address_bypass_p.
6442 if PRO modifies register used as index in CON,
6443 return scale of indexed memory access in CON. Return zero overwise. */
6445 sched_get_indexed_address_scale (rtx_insn
*pro
, rtx_insn
*con
)
6449 struct m68k_address address
;
6451 reg
= sched_get_reg_operand (pro
, true);
6455 mem
= sched_get_mem_operand (con
, true, false);
6456 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6458 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6462 if (REGNO (reg
) == REGNO (address
.index
))
6464 gcc_assert (address
.scale
!= 0);
6465 return address
.scale
;
6471 /* Return non-zero if PRO modifies register used
6472 as index with scale 2 or 4 in CON. */
6474 m68k_sched_indexed_address_bypass_p (rtx_insn
*pro
, rtx_insn
*con
)
6476 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6477 && sched_cfv4_bypass_data
.con
== NULL
6478 && sched_cfv4_bypass_data
.scale
== 0);
6480 switch (sched_get_indexed_address_scale (pro
, con
))
6483 /* We can't have a variable latency bypass, so
6484 remember to adjust the insn cost in adjust_cost hook. */
6485 sched_cfv4_bypass_data
.pro
= pro
;
6486 sched_cfv4_bypass_data
.con
= con
;
6487 sched_cfv4_bypass_data
.scale
= 1;
6499 /* We generate a two-instructions program at M_TRAMP :
6500 movea.l &CHAIN_VALUE,%a0
6502 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6505 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6507 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6510 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6512 mem
= adjust_address (m_tramp
, HImode
, 0);
6513 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6514 mem
= adjust_address (m_tramp
, SImode
, 2);
6515 emit_move_insn (mem
, chain_value
);
6517 mem
= adjust_address (m_tramp
, HImode
, 6);
6518 emit_move_insn (mem
, GEN_INT(0x4EF9));
6519 mem
= adjust_address (m_tramp
, SImode
, 8);
6520 emit_move_insn (mem
, fnaddr
);
6522 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6525 /* On the 68000, the RTS insn cannot pop anything.
6526 On the 68010, the RTD insn may be used to pop them if the number
6527 of args is fixed, but if the number is variable then the caller
6528 must pop them all. RTD can't be used for library calls now
6529 because the library is compiled with the Unix compiler.
6530 Use of RTD is a selectable option, since it is incompatible with
6531 standard Unix calling sequences. If the option is not selected,
6532 the caller must always pop the args. */
6535 m68k_return_pops_args (tree fundecl
, tree funtype
, poly_int64 size
)
6539 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6540 && (!stdarg_p (funtype
)))
6541 ? (HOST_WIDE_INT
) size
: 0);
6544 /* Make sure everything's fine if we *don't* have a given processor.
6545 This assumes that putting a register in fixed_regs will keep the
6546 compiler's mitts completely off it. We don't bother to zero it out
6547 of register classes. */
6550 m68k_conditional_register_usage (void)
6554 if (!TARGET_HARD_FLOAT
)
6556 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6557 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6558 if (TEST_HARD_REG_BIT (x
, i
))
6559 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6562 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6566 m68k_init_sync_libfuncs (void)
6568 init_sync_libfuncs (UNITS_PER_WORD
);
6571 /* Implements EPILOGUE_USES. All registers are live on exit from an
6572 interrupt routine. */
6574 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED
)
6576 return (reload_completed
6577 && (m68k_get_function_kind (current_function_decl
)
6578 == m68k_fk_interrupt_handler
));
6582 /* Implement TARGET_C_EXCESS_PRECISION.
6584 Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
6585 instructions, we get proper intermediate rounding, otherwise we
6586 get extended precision results. */
6588 static enum flt_eval_method
6589 m68k_excess_precision (enum excess_precision_type type
)
6593 case EXCESS_PRECISION_TYPE_FAST
:
6594 /* The fastest type to promote to will always be the native type,
6595 whether that occurs with implicit excess precision or
6597 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6598 case EXCESS_PRECISION_TYPE_STANDARD
:
6599 case EXCESS_PRECISION_TYPE_IMPLICIT
:
6600 /* Otherwise, the excess precision we want when we are
6601 in a standards compliant mode, and the implicit precision we
6602 provide can be identical. */
6603 if (TARGET_68040
|| ! TARGET_68881
)
6604 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT
;
6606 return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE
;
6610 return FLT_EVAL_METHOD_UNPREDICTABLE
;
6613 #include "gt-m68k.h"