1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 93, 94, 95, 96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* Some output-actions in m68k.md need these. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-flags.h"
34 #include "insn-attr.h"
37 /* Needed for use_return_insn. */
40 #ifdef SUPPORT_SUN_FPA
42 /* Index into this array by (register number >> 3) to find the
43 smallest class which contains that register. */
44 enum reg_class regno_reg_class
[]
45 = { DATA_REGS
, ADDR_REGS
, FP_REGS
,
46 LO_FPA_REGS
, LO_FPA_REGS
, FPA_REGS
, FPA_REGS
};
48 #endif /* defined SUPPORT_SUN_FPA */
50 /* This flag is used to communicate between movhi and ASM_OUTPUT_CASE_END,
51 if SGS_SWITCH_TABLE. */
52 int switch_table_difference_label_flag
;
54 static rtx
find_addr_reg ();
55 rtx
legitimize_pic_address ();
58 /* Alignment to use for loops and jumps */
59 /* Specify power of two alignment used for loops. */
60 char *m68k_align_loops_string
;
61 /* Specify power of two alignment used for non-loop jumps. */
62 char *m68k_align_jumps_string
;
63 /* Specify power of two alignment used for functions. */
64 char *m68k_align_funcs_string
;
66 /* Specify power of two alignment used for loops. */
68 /* Specify power of two alignment used for non-loop jumps. */
70 /* Specify power of two alignment used for functions. */
73 /* Nonzero if the last compare/test insn had FP operands. The
74 sCC expanders peek at this to determine what to do for the
75 68060, which has no fsCC instructions. */
76 int m68k_last_compare_had_fp_operands
;
78 /* Sometimes certain combinations of command options do not make
79 sense on a particular target machine. You can define a macro
80 `OVERRIDE_OPTIONS' to take account of this. This macro, if
81 defined, is executed once just after all the command options have
84 Don't use this macro to turn on various extra optimizations for
85 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */
94 /* Validate -malign-loops= value, or provide default */
95 if (m68k_align_loops_string
)
97 m68k_align_loops
= atoi (m68k_align_loops_string
);
98 if (m68k_align_loops
< 1 || m68k_align_loops
> MAX_CODE_ALIGN
)
99 fatal ("-malign-loops=%d is not between 1 and %d",
100 m68k_align_loops
, MAX_CODE_ALIGN
);
103 m68k_align_loops
= def_align
;
105 /* Validate -malign-jumps= value, or provide default */
106 if (m68k_align_jumps_string
)
108 m68k_align_jumps
= atoi (m68k_align_jumps_string
);
109 if (m68k_align_jumps
< 1 || m68k_align_jumps
> MAX_CODE_ALIGN
)
110 fatal ("-malign-jumps=%d is not between 1 and %d",
111 m68k_align_jumps
, MAX_CODE_ALIGN
);
114 m68k_align_jumps
= def_align
;
116 /* Validate -malign-functions= value, or provide default */
117 if (m68k_align_funcs_string
)
119 m68k_align_funcs
= atoi (m68k_align_funcs_string
);
120 if (m68k_align_funcs
< 1 || m68k_align_funcs
> MAX_CODE_ALIGN
)
121 fatal ("-malign-functions=%d is not between 1 and %d",
122 m68k_align_funcs
, MAX_CODE_ALIGN
);
125 m68k_align_funcs
= def_align
;
128 /* Emit a (use pic_offset_table_rtx) if we used PIC relocation in the
129 function at any time during the compilation process. In the future
130 we should try and eliminate the USE if we can easily determine that
131 all PIC references were deleted from the current function. That would
132 save an address register */
137 if (flag_pic
&& current_function_uses_pic_offset_table
)
139 rtx insn
= gen_rtx (USE
, VOIDmode
, pic_offset_table_rtx
);
140 emit_insn_after (insn
, get_insns ());
146 /* This function generates the assembly code for function entry.
147 STREAM is a stdio stream to output the code to.
148 SIZE is an int: how many units of temporary storage to allocate.
149 Refer to the array `regs_ever_live' to determine which registers
150 to save; `regs_ever_live[I]' is nonzero if register number I
151 is ever used in the function. This function is responsible for
152 knowing which registers should not be saved even if used. */
155 /* Note that the order of the bit mask for fmovem is the opposite
156 of the order for movem! */
160 output_function_prologue (stream
, size
)
165 register int mask
= 0;
166 int num_saved_regs
= 0;
167 extern char call_used_regs
[];
168 int fsize
= (size
+ 3) & -4;
169 int cfa_offset
= INCOMING_FRAME_SP_OFFSET
, cfa_store_offset
= cfa_offset
;
172 if (frame_pointer_needed
)
174 if (fsize
== 0 && TARGET_68040
)
176 /* on the 68040, pea + move is faster than link.w 0 */
178 asm_fprintf (stream
, "\tpea (%s)\n\tmove.l %s,%s\n",
179 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
180 reg_names
[FRAME_POINTER_REGNUM
]);
182 asm_fprintf (stream
, "\tpea %s@\n\tmovel %s,%s\n",
183 reg_names
[FRAME_POINTER_REGNUM
], reg_names
[STACK_POINTER_REGNUM
],
184 reg_names
[FRAME_POINTER_REGNUM
]);
187 else if (fsize
< 0x8000)
190 asm_fprintf (stream
, "\tlink.w %s,%0I%d\n",
191 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
193 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
194 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
197 else if (TARGET_68020
)
200 asm_fprintf (stream
, "\tlink.l %s,%0I%d\n",
201 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
203 asm_fprintf (stream
, "\tlink %s,%0I%d\n",
204 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
209 /* Adding negative number is faster on the 68040. */
211 asm_fprintf (stream
, "\tlink.w %s,%0I0\n\tadd.l %0I%d,%Rsp\n",
212 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
214 asm_fprintf (stream
, "\tlink %s,%0I0\n\taddl %0I%d,%Rsp\n",
215 reg_names
[FRAME_POINTER_REGNUM
], -fsize
);
218 if (dwarf2out_do_frame ())
220 char *l
= dwarf2out_cfi_label ();
222 cfa_store_offset
+= 4;
223 cfa_offset
= cfa_store_offset
;
224 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, cfa_offset
);
225 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
, -cfa_store_offset
);
226 cfa_store_offset
+= fsize
;
231 if (fsize
+ 4 < 0x8000)
238 /* asm_fprintf() cannot handle %. */
240 asm_fprintf (stream
, "\tsubq.w %OI%d,%Rsp\n", fsize
+ 4);
242 asm_fprintf (stream
, "\tsubqw %OI%d,%Rsp\n", fsize
+ 4);
247 /* asm_fprintf() cannot handle %. */
249 asm_fprintf (stream
, "\tsubq.l %OI%d,%Rsp\n", fsize
+ 4);
251 asm_fprintf (stream
, "\tsubql %OI%d,%Rsp\n", fsize
+ 4);
255 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
257 /* On the CPU32 it is faster to use two subqw instructions to
258 subtract a small integer (8 < N <= 16) to a register. */
259 /* asm_fprintf() cannot handle %. */
261 asm_fprintf (stream
, "\tsubq.w %OI8,%Rsp\n\tsubq.w %OI%d,%Rsp\n",
264 asm_fprintf (stream
, "\tsubqw %OI8,%Rsp\n\tsubqw %OI%d,%Rsp\n",
269 #endif /* NO_ADDSUB_Q */
272 /* Adding negative number is faster on the 68040. */
273 /* asm_fprintf() cannot handle %. */
275 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", - (fsize
+ 4));
277 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", - (fsize
+ 4));
283 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", - (fsize
+ 4));
285 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", - (fsize
+ 4));
291 /* asm_fprintf() cannot handle %. */
293 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", - (fsize
+ 4));
295 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", - (fsize
+ 4));
298 if (dwarf2out_do_frame ())
300 cfa_store_offset
+= fsize
;
301 cfa_offset
= cfa_store_offset
;
302 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, cfa_offset
);
305 #ifdef SUPPORT_SUN_FPA
306 for (regno
= 24; regno
< 56; regno
++)
307 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
310 asm_fprintf (stream
, "\tfpmovd %s,-(%Rsp)\n",
313 asm_fprintf (stream
, "\tfpmoved %s,%Rsp@-\n",
316 if (dwarf2out_do_frame ())
318 char *l
= dwarf2out_cfi_label ();
320 cfa_store_offset
+= 8;
321 if (! frame_pointer_needed
)
323 cfa_offset
= cfa_store_offset
;
324 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
326 dwarf2out_reg_save (l
, regno
, -cfa_store_offset
);
332 for (regno
= 16; regno
< 24; regno
++)
333 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
335 mask
|= 1 << (regno
- 16);
338 if ((mask
& 0xff) != 0)
341 asm_fprintf (stream
, "\tfmovm %0I0x%x,-(%Rsp)\n", mask
& 0xff);
343 asm_fprintf (stream
, "\tfmovem %0I0x%x,%Rsp@-\n", mask
& 0xff);
345 if (dwarf2out_do_frame ())
347 char *l
= dwarf2out_cfi_label ();
350 cfa_store_offset
+= num_saved_regs
* 12;
351 if (! frame_pointer_needed
)
353 cfa_offset
= cfa_store_offset
;
354 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
356 for (regno
= 16, n_regs
= 0; regno
< 24; regno
++)
357 if (mask
& (1 << (regno
- 16)))
358 dwarf2out_reg_save (l
, regno
,
359 -cfa_store_offset
+ n_regs
++ * 12);
365 for (regno
= 0; regno
< 16; regno
++)
366 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
368 mask
|= 1 << (15 - regno
);
371 if (frame_pointer_needed
)
373 mask
&= ~ (1 << (15 - FRAME_POINTER_REGNUM
));
380 asm_fprintf (stream
, "\ttstl %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
382 asm_fprintf (stream
, "\ttst.l %d(%Rsp)\n", NEED_PROBE
- num_saved_regs
* 4);
385 asm_fprintf (stream
, "\ttstl %Rsp@(%d)\n", NEED_PROBE
- num_saved_regs
* 4);
389 if (num_saved_regs
<= 2)
391 /* Store each separately in the same order moveml uses.
392 Using two movel instructions instead of a single moveml
393 is about 15% faster for the 68020 and 68030 at no expense
398 /* Undo the work from above. */
399 for (i
= 0; i
< 16; i
++)
404 "\t%Omove.l %s,-(%Rsp)\n",
406 "\tmovel %s,%Rsp@-\n",
409 if (dwarf2out_do_frame ())
411 char *l
= dwarf2out_cfi_label ();
413 cfa_store_offset
+= 4;
414 if (! frame_pointer_needed
)
416 cfa_offset
= cfa_store_offset
;
417 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
419 dwarf2out_reg_save (l
, 15 - i
, -cfa_store_offset
);
427 /* The coldfire does not support the predecrement form of the
428 movml instruction, so we must adjust the stack pointer and
429 then use the plain address register indirect mode. We also
430 have to invert the register save mask to use the new mode.
432 FIXME: if num_saved_regs was calculated earlier, we could
433 combine the stack pointer adjustment with any adjustment
434 done when the initial stack frame is created. This would
435 save an instruction */
440 for (i
= 0; i
< 16; i
++)
442 newmask
|= (1 << (15-i
));
445 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", -num_saved_regs
*4);
446 asm_fprintf (stream
, "\tmovm.l %0I0x%x,(%Rsp)\n", newmask
);
448 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", -num_saved_regs
*4);
449 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@\n", newmask
);
455 asm_fprintf (stream
, "\tmovm.l %0I0x%x,-(%Rsp)\n", mask
);
457 asm_fprintf (stream
, "\tmoveml %0I0x%x,%Rsp@-\n", mask
);
460 if (dwarf2out_do_frame ())
462 char *l
= dwarf2out_cfi_label ();
465 cfa_store_offset
+= num_saved_regs
* 4;
466 if (! frame_pointer_needed
)
468 cfa_offset
= cfa_store_offset
;
469 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, cfa_offset
);
471 for (regno
= 0, n_regs
= 0; regno
< 16; regno
++)
472 if (mask
& (1 << (15 - regno
)))
473 dwarf2out_reg_save (l
, regno
,
474 -cfa_store_offset
+ n_regs
++ * 4);
477 if (flag_pic
&& current_function_uses_pic_offset_table
)
480 asm_fprintf (stream
, "\t%Olea (%Rpc, %U_GLOBAL_OFFSET_TABLE_@GOTPC), %s\n",
481 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
483 asm_fprintf (stream
, "\tmovel %0I__GLOBAL_OFFSET_TABLE_, %s\n",
484 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
485 asm_fprintf (stream
, "\tlea %Rpc@(0,%s:l),%s\n",
486 reg_names
[PIC_OFFSET_TABLE_REGNUM
],
487 reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
492 /* Return true if this function's epilogue can be output as RTL. */
499 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
502 /* Copied from output_function_epilogue (). We should probably create a
503 separate layout routine to perform the common work. */
505 for (regno
= 0 ; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
506 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
512 /* This function generates the assembly code for function exit,
513 on machines that need it. Args are same as for FUNCTION_PROLOGUE.
515 The function epilogue should not depend on the current stack pointer!
516 It should use the frame pointer only, if there is a frame pointer.
517 This is mandatory because of alloca; we also take advantage of it to
518 omit stack adjustments before returning. */
521 output_function_epilogue (stream
, size
)
526 register int mask
, fmask
;
528 int offset
, foffset
, fpoffset
;
529 extern char call_used_regs
[];
530 int fsize
= (size
+ 3) & -4;
532 rtx insn
= get_last_insn ();
533 int restore_from_sp
= 0;
535 /* If the last insn was a BARRIER, we don't have to write any code. */
536 if (GET_CODE (insn
) == NOTE
)
537 insn
= prev_nonnote_insn (insn
);
538 if (insn
&& GET_CODE (insn
) == BARRIER
)
540 /* Output just a no-op so that debuggers don't get confused
541 about which function the pc is in at this address. */
542 asm_fprintf (stream
, "\tnop\n");
546 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
547 if (profile_block_flag
== 2)
549 FUNCTION_BLOCK_PROFILER_EXIT (stream
);
553 #ifdef FUNCTION_EXTRA_EPILOGUE
554 FUNCTION_EXTRA_EPILOGUE (stream
, size
);
556 nregs
= 0; fmask
= 0; fpoffset
= 0;
557 #ifdef SUPPORT_SUN_FPA
558 for (regno
= 24 ; regno
< 56 ; regno
++)
559 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
561 fpoffset
= nregs
* 8;
566 for (regno
= 16; regno
< 24; regno
++)
567 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
570 fmask
|= 1 << (23 - regno
);
573 foffset
= fpoffset
+ nregs
* 12;
575 if (frame_pointer_needed
)
576 regs_ever_live
[FRAME_POINTER_REGNUM
] = 0;
577 for (regno
= 0; regno
< 16; regno
++)
578 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
583 offset
= foffset
+ nregs
* 4;
584 /* FIXME : leaf_function_p below is too strong.
585 What we really need to know there is if there could be pending
586 stack adjustment needed at that point. */
587 restore_from_sp
= ! frame_pointer_needed
588 || (! current_function_calls_alloca
&& leaf_function_p ());
589 if (offset
+ fsize
>= 0x8000
591 && (mask
|| fmask
|| fpoffset
))
594 asm_fprintf (stream
, "\t%Omove.l %0I%d,%Ra1\n", -fsize
);
596 asm_fprintf (stream
, "\tmovel %0I%d,%Ra1\n", -fsize
);
600 if (TARGET_5200
|| nregs
<= 2)
602 /* Restore each separately in the same order moveml does.
603 Using two movel instructions instead of a single moveml
604 is about 15% faster for the 68020 and 68030 at no expense
609 /* Undo the work from above. */
610 for (i
= 0; i
< 16; i
++)
616 asm_fprintf (stream
, "\t%Omove.l -%d(%s,%Ra1.l),%s\n",
618 reg_names
[FRAME_POINTER_REGNUM
],
621 asm_fprintf (stream
, "\tmovel %s@(-%d,%Ra1:l),%s\n",
622 reg_names
[FRAME_POINTER_REGNUM
],
623 offset
+ fsize
, reg_names
[i
]);
626 else if (restore_from_sp
)
629 asm_fprintf (stream
, "\t%Omove.l (%Rsp)+,%s\n",
632 asm_fprintf (stream
, "\tmovel %Rsp@+,%s\n",
639 asm_fprintf (stream
, "\t%Omove.l -%d(%s),%s\n",
641 reg_names
[FRAME_POINTER_REGNUM
],
644 asm_fprintf (stream
, "\tmovel %s@(-%d),%s\n",
645 reg_names
[FRAME_POINTER_REGNUM
],
646 offset
+ fsize
, reg_names
[i
]);
657 asm_fprintf (stream
, "\tmovm.l -%d(%s,%Ra1.l),%0I0x%x\n",
659 reg_names
[FRAME_POINTER_REGNUM
],
662 asm_fprintf (stream
, "\tmoveml %s@(-%d,%Ra1:l),%0I0x%x\n",
663 reg_names
[FRAME_POINTER_REGNUM
],
664 offset
+ fsize
, mask
);
667 else if (restore_from_sp
)
670 asm_fprintf (stream
, "\tmovm.l (%Rsp)+,%0I0x%x\n", mask
);
672 asm_fprintf (stream
, "\tmoveml %Rsp@+,%0I0x%x\n", mask
);
678 asm_fprintf (stream
, "\tmovm.l -%d(%s),%0I0x%x\n",
680 reg_names
[FRAME_POINTER_REGNUM
],
683 asm_fprintf (stream
, "\tmoveml %s@(-%d),%0I0x%x\n",
684 reg_names
[FRAME_POINTER_REGNUM
],
685 offset
+ fsize
, mask
);
694 asm_fprintf (stream
, "\tfmovm -%d(%s,%Ra1.l),%0I0x%x\n",
696 reg_names
[FRAME_POINTER_REGNUM
],
699 asm_fprintf (stream
, "\tfmovem %s@(-%d,%Ra1:l),%0I0x%x\n",
700 reg_names
[FRAME_POINTER_REGNUM
],
701 foffset
+ fsize
, fmask
);
704 else if (restore_from_sp
)
707 asm_fprintf (stream
, "\tfmovm (%Rsp)+,%0I0x%x\n", fmask
);
709 asm_fprintf (stream
, "\tfmovem %Rsp@+,%0I0x%x\n", fmask
);
715 asm_fprintf (stream
, "\tfmovm -%d(%s),%0I0x%x\n",
717 reg_names
[FRAME_POINTER_REGNUM
],
720 asm_fprintf (stream
, "\tfmovem %s@(-%d),%0I0x%x\n",
721 reg_names
[FRAME_POINTER_REGNUM
],
722 foffset
+ fsize
, fmask
);
727 for (regno
= 55; regno
>= 24; regno
--)
728 if (regs_ever_live
[regno
] && ! call_used_regs
[regno
])
733 asm_fprintf (stream
, "\tfpmovd -%d(%s,%Ra1.l), %s\n",
735 reg_names
[FRAME_POINTER_REGNUM
],
738 asm_fprintf (stream
, "\tfpmoved %s@(-%d,%Ra1:l), %s\n",
739 reg_names
[FRAME_POINTER_REGNUM
],
740 fpoffset
+ fsize
, reg_names
[regno
]);
743 else if (restore_from_sp
)
746 asm_fprintf (stream
, "\tfpmovd (%Rsp)+,%s\n",
749 asm_fprintf (stream
, "\tfpmoved %Rsp@+, %s\n",
756 asm_fprintf (stream
, "\tfpmovd -%d(%s), %s\n",
758 reg_names
[FRAME_POINTER_REGNUM
],
761 asm_fprintf (stream
, "\tfpmoved %s@(-%d), %s\n",
762 reg_names
[FRAME_POINTER_REGNUM
],
763 fpoffset
+ fsize
, reg_names
[regno
]);
768 if (frame_pointer_needed
)
769 fprintf (stream
, "\tunlk %s\n",
770 reg_names
[FRAME_POINTER_REGNUM
]);
779 asm_fprintf (stream
, "\taddq.w %OI%d,%Rsp\n", fsize
+ 4);
781 asm_fprintf (stream
, "\taddqw %OI%d,%Rsp\n", fsize
+ 4);
787 asm_fprintf (stream
, "\taddq.l %OI%d,%Rsp\n", fsize
+ 4);
789 asm_fprintf (stream
, "\taddql %OI%d,%Rsp\n", fsize
+ 4);
793 else if (fsize
+ 4 <= 16 && TARGET_CPU32
)
795 /* On the CPU32 it is faster to use two addqw instructions to
796 add a small integer (8 < N <= 16) to a register. */
797 /* asm_fprintf() cannot handle %. */
799 asm_fprintf (stream
, "\taddq.w %OI8,%Rsp\n\taddq.w %OI%d,%Rsp\n",
802 asm_fprintf (stream
, "\taddqw %OI8,%Rsp\n\taddqw %OI%d,%Rsp\n",
807 #endif /* NO_ADDSUB_Q */
808 if (fsize
+ 4 < 0x8000)
812 /* asm_fprintf() cannot handle %. */
814 asm_fprintf (stream
, "\tadd.w %0I%d,%Rsp\n", fsize
+ 4);
816 asm_fprintf (stream
, "\taddw %0I%d,%Rsp\n", fsize
+ 4);
822 asm_fprintf (stream
, "\tlea (%d,%Rsp),%Rsp\n", fsize
+ 4);
824 asm_fprintf (stream
, "\tlea %Rsp@(%d),%Rsp\n", fsize
+ 4);
830 /* asm_fprintf() cannot handle %. */
832 asm_fprintf (stream
, "\tadd.l %0I%d,%Rsp\n", fsize
+ 4);
834 asm_fprintf (stream
, "\taddl %0I%d,%Rsp\n", fsize
+ 4);
838 if (current_function_pops_args
)
839 asm_fprintf (stream
, "\trtd %0I%d\n", current_function_pops_args
);
841 fprintf (stream
, "\trts\n");
844 /* Similar to general_operand, but exclude stack_pointer_rtx. */
847 not_sp_operand (op
, mode
)
849 enum machine_mode mode
;
851 return op
!= stack_pointer_rtx
&& general_operand (op
, mode
);
854 /* Return TRUE if X is a valid comparison operator for the dbcc
857 Note it rejects floating point comparison operators.
858 (In the future we could use Fdbcc).
860 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
863 valid_dbcc_comparison_p (x
, mode
)
865 enum machine_mode mode
;
867 switch (GET_CODE (x
))
869 case EQ
: case NE
: case GTU
: case LTU
:
873 /* Reject some when CC_NO_OVERFLOW is set. This may be over
875 case GT
: case LT
: case GE
: case LE
:
876 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
882 /* Return non-zero if flags are currently in the 68881 flag register. */
886 /* We could add support for these in the future */
887 return cc_status
.flags
& CC_IN_68881
;
890 /* Output a dbCC; jCC sequence. Note we do not handle the
891 floating point version of this sequence (Fdbcc). We also
892 do not handle alternative conditions when CC_NO_OVERFLOW is
893 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
894 kick those out before we get here. */
896 output_dbcc_and_branch (operands
)
899 switch (GET_CODE (operands
[3]))
903 output_asm_insn ("dbeq %0,%l1\n\tjbeq %l2", operands
);
905 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
911 output_asm_insn ("dbne %0,%l1\n\tjbne %l2", operands
);
913 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
919 output_asm_insn ("dbgt %0,%l1\n\tjbgt %l2", operands
);
921 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
927 output_asm_insn ("dbhi %0,%l1\n\tjbhi %l2", operands
);
929 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
935 output_asm_insn ("dblt %0,%l1\n\tjblt %l2", operands
);
937 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
943 output_asm_insn ("dbcs %0,%l1\n\tjbcs %l2", operands
);
945 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
951 output_asm_insn ("dbge %0,%l1\n\tjbge %l2", operands
);
953 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
959 output_asm_insn ("dbcc %0,%l1\n\tjbcc %l2", operands
);
961 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
967 output_asm_insn ("dble %0,%l1\n\tjble %l2", operands
);
969 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
975 output_asm_insn ("dbls %0,%l1\n\tjbls %l2", operands
);
977 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
985 /* If the decrement is to be done in SImode, then we have
986 to compensate for the fact that dbcc decrements in HImode. */
987 switch (GET_MODE (operands
[0]))
991 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjbpl %l1", operands
);
993 output_asm_insn ("clr%.w %0\n\tsubq%.l %#1,%0\n\tjpl %l1", operands
);
1006 output_scc_di(op
, operand1
, operand2
, dest
)
1013 enum rtx_code op_code
= GET_CODE (op
);
1015 /* This does not produce a usefull cc. */
1018 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1019 below. Swap the operands and change the op if these requirements
1020 are not fulfilled. */
1021 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1025 operand1
= operand2
;
1027 op_code
= swap_condition (op_code
);
1029 loperands
[0] = operand1
;
1030 if (GET_CODE (operand1
) == REG
)
1031 loperands
[1] = gen_rtx (REG
, SImode
, REGNO (operand1
) + 1);
1033 loperands
[1] = adj_offsettable_operand (operand1
, 4);
1034 if (operand2
!= const0_rtx
)
1036 loperands
[2] = operand2
;
1037 if (GET_CODE (operand2
) == REG
)
1038 loperands
[3] = gen_rtx (REG
, SImode
, REGNO (operand2
) + 1);
1040 loperands
[3] = adj_offsettable_operand (operand2
, 4);
1042 loperands
[4] = gen_label_rtx();
1043 if (operand2
!= const0_rtx
)
1045 #ifdef SGS_CMP_ORDER
1046 output_asm_insn ("cmp%.l %0,%2\n\tjbne %l4\n\tcmp%.l %1,%3", loperands
);
1048 output_asm_insn ("cmp%.l %2,%0\n\tjbne %l4\n\tcmp%.l %3,%1", loperands
);
1051 #ifdef SGS_CMP_ORDER
1052 output_asm_insn ("cmp%.l %0,%2\n\tjne %l4\n\tcmp%.l %1,%3", loperands
);
1054 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1059 output_asm_insn ("tst%.l %0\n\tjbne %l4\n\ttst%.l %1", loperands
);
1061 output_asm_insn ("tst%.l %0\n\tjne %l4\n\ttst%.l %1", loperands
);
1063 loperands
[5] = dest
;
1068 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1069 CODE_LABEL_NUMBER (loperands
[4]));
1070 output_asm_insn ("seq %5", loperands
);
1074 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1075 CODE_LABEL_NUMBER (loperands
[4]));
1076 output_asm_insn ("sne %5", loperands
);
1080 loperands
[6] = gen_label_rtx();
1082 output_asm_insn ("shi %5\n\tjbra %l6", loperands
);
1084 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1086 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1087 CODE_LABEL_NUMBER (loperands
[4]));
1088 output_asm_insn ("sgt %5", loperands
);
1089 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1090 CODE_LABEL_NUMBER (loperands
[6]));
1094 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1095 CODE_LABEL_NUMBER (loperands
[4]));
1096 output_asm_insn ("shi %5", loperands
);
1100 loperands
[6] = gen_label_rtx();
1102 output_asm_insn ("scs %5\n\tjbra %l6", loperands
);
1104 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1106 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1107 CODE_LABEL_NUMBER (loperands
[4]));
1108 output_asm_insn ("slt %5", loperands
);
1109 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1110 CODE_LABEL_NUMBER (loperands
[6]));
1114 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1115 CODE_LABEL_NUMBER (loperands
[4]));
1116 output_asm_insn ("scs %5", loperands
);
1120 loperands
[6] = gen_label_rtx();
1122 output_asm_insn ("scc %5\n\tjbra %l6", loperands
);
1124 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1126 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1127 CODE_LABEL_NUMBER (loperands
[4]));
1128 output_asm_insn ("sge %5", loperands
);
1129 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1130 CODE_LABEL_NUMBER (loperands
[6]));
1134 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1135 CODE_LABEL_NUMBER (loperands
[4]));
1136 output_asm_insn ("scc %5", loperands
);
1140 loperands
[6] = gen_label_rtx();
1142 output_asm_insn ("sls %5\n\tjbra %l6", loperands
);
1144 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1146 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1147 CODE_LABEL_NUMBER (loperands
[4]));
1148 output_asm_insn ("sle %5", loperands
);
1149 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1150 CODE_LABEL_NUMBER (loperands
[6]));
1154 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1155 CODE_LABEL_NUMBER (loperands
[4]));
1156 output_asm_insn ("sls %5", loperands
);
1166 output_btst (operands
, countop
, dataop
, insn
, signpos
)
1168 rtx countop
, dataop
;
1172 operands
[0] = countop
;
1173 operands
[1] = dataop
;
1175 if (GET_CODE (countop
) == CONST_INT
)
1177 register int count
= INTVAL (countop
);
1178 /* If COUNT is bigger than size of storage unit in use,
1179 advance to the containing unit of same size. */
1180 if (count
> signpos
)
1182 int offset
= (count
& ~signpos
) / 8;
1183 count
= count
& signpos
;
1184 operands
[1] = dataop
= adj_offsettable_operand (dataop
, offset
);
1186 if (count
== signpos
)
1187 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1189 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1191 /* These three statements used to use next_insns_test_no...
1192 but it appears that this should do the same job. */
1194 && next_insn_tests_no_inequality (insn
))
1197 && next_insn_tests_no_inequality (insn
))
1200 && next_insn_tests_no_inequality (insn
))
1203 cc_status
.flags
= CC_NOT_NEGATIVE
;
1205 return "btst %0,%1";
1208 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
1209 reference and a constant. */
1212 symbolic_operand (op
, mode
)
1214 enum machine_mode mode
;
1216 switch (GET_CODE (op
))
1224 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1225 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1226 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1228 #if 0 /* Deleted, with corresponding change in m68k.h,
1229 so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
1231 return GET_MODE (op
) == mode
;
1239 /* Check for sign_extend or zero_extend. Used for bit-count operands. */
1242 extend_operator(x
, mode
)
1244 enum machine_mode mode
;
1246 if (mode
!= VOIDmode
&& GET_MODE(x
) != mode
)
1248 switch (GET_CODE(x
))
1259 /* Legitimize PIC addresses. If the address is already
1260 position-independent, we return ORIG. Newly generated
1261 position-independent addresses go to REG. If we need more
1262 than one register, we lose.
1264 An address is legitimized by making an indirect reference
1265 through the Global Offset Table with the name of the symbol
1268 The assembler and linker are responsible for placing the
1269 address of the symbol in the GOT. The function prologue
1270 is responsible for initializing a5 to the starting address
1273 The assembler is also responsible for translating a symbol name
1274 into a constant displacement from the start of the GOT.
1276 A quick example may make things a little clearer:
1278 When not generating PIC code to store the value 12345 into _foo
1279 we would generate the following code:
1283 When generating PIC two transformations are made. First, the compiler
1284 loads the address of foo into a register. So the first transformation makes:
1289 The code in movsi will intercept the lea instruction and call this
1290 routine which will transform the instructions into:
1292 movel a5@(_foo:w), a0
1296 That (in a nutshell) is how *all* symbol and label references are
1300 legitimize_pic_address (orig
, mode
, reg
)
1302 enum machine_mode mode
;
1306 /* First handle a simple SYMBOL_REF or LABEL_REF */
1307 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
1312 pic_ref
= gen_rtx (MEM
, Pmode
,
1313 gen_rtx (PLUS
, Pmode
,
1314 pic_offset_table_rtx
, orig
));
1315 current_function_uses_pic_offset_table
= 1;
1316 if (reload_in_progress
)
1317 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
1318 RTX_UNCHANGING_P (pic_ref
) = 1;
1319 emit_move_insn (reg
, pic_ref
);
1322 else if (GET_CODE (orig
) == CONST
)
1326 /* Make sure this is CONST has not already been legitimized */
1327 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1328 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1334 /* legitimize both operands of the PLUS */
1335 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1337 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1338 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1339 base
== reg
? 0 : reg
);
1343 if (GET_CODE (orig
) == CONST_INT
)
1344 return plus_constant_for_output (base
, INTVAL (orig
));
1345 pic_ref
= gen_rtx (PLUS
, Pmode
, base
, orig
);
1346 /* Likewise, should we set special REG_NOTEs here? */
1352 typedef enum { MOVL
, SWAP
, NEGW
, NOTW
, NOTB
, MOVQ
} CONST_METHOD
;
1354 #define USE_MOVQ(i) ((unsigned)((i) + 128) <= 255)
1357 const_method (constant
)
1363 i
= INTVAL (constant
);
1367 /* The Coldfire doesn't have byte or word operations. */
1368 /* FIXME: This may not be useful for the m68060 either */
1371 /* if -256 < N < 256 but N is not in range for a moveq
1372 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
1373 if (USE_MOVQ (i
^ 0xff))
1375 /* Likewise, try with not.w */
1376 if (USE_MOVQ (i
^ 0xffff))
1378 /* This is the only value where neg.w is useful */
1381 /* Try also with swap */
1383 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
1386 /* Otherwise, use move.l */
1390 const_int_cost (constant
)
1393 switch (const_method (constant
))
1396 /* Constants between -128 and 127 are cheap due to moveq */
1402 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap */
1412 output_move_const_into_data_reg (operands
)
1417 i
= INTVAL (operands
[1]);
1418 switch (const_method (operands
[1]))
1421 #if defined (MOTOROLA) && !defined (CRDS)
1422 return "moveq%.l %1,%0";
1424 return "moveq %1,%0";
1427 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xff);
1428 #if defined (MOTOROLA) && !defined (CRDS)
1429 return "moveq%.l %1,%0\n\tnot%.b %0";
1431 return "moveq %1,%0\n\tnot%.b %0";
1434 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, i
^ 0xffff);
1435 #if defined (MOTOROLA) && !defined (CRDS)
1436 return "moveq%.l %1,%0\n\tnot%.w %0";
1438 return "moveq %1,%0\n\tnot%.w %0";
1441 #if defined (MOTOROLA) && !defined (CRDS)
1442 return "moveq%.l %#-128,%0\n\tneg%.w %0";
1444 return "moveq %#-128,%0\n\tneg%.w %0";
1450 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, (u
<< 16) | (u
>> 16));
1451 #if defined (MOTOROLA) && !defined (CRDS)
1452 return "moveq%.l %1,%0\n\tswap %0";
1454 return "moveq %1,%0\n\tswap %0";
1458 return "move%.l %1,%0";
1465 output_move_simode_const (operands
)
1468 if (operands
[1] == const0_rtx
1469 && (DATA_REG_P (operands
[0])
1470 || GET_CODE (operands
[0]) == MEM
)
1471 /* clr insns on 68000 read before writing.
1472 This isn't so on the 68010, but we have no TARGET_68010. */
1473 && ((TARGET_68020
|| TARGET_5200
)
1474 || !(GET_CODE (operands
[0]) == MEM
1475 && MEM_VOLATILE_P (operands
[0]))))
1477 else if (DATA_REG_P (operands
[0]))
1478 return output_move_const_into_data_reg (operands
);
1479 else if (ADDRESS_REG_P (operands
[0])
1480 && INTVAL (operands
[1]) < 0x8000
1481 && INTVAL (operands
[1]) >= -0x8000)
1482 return "move%.w %1,%0";
1483 else if (GET_CODE (operands
[0]) == MEM
1484 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1485 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1486 && INTVAL (operands
[1]) < 0x8000
1487 && INTVAL (operands
[1]) >= -0x8000)
1489 return "move%.l %1,%0";
1493 output_move_simode (operands
)
1496 if (GET_CODE (operands
[1]) == CONST_INT
)
1497 return output_move_simode_const (operands
);
1498 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1499 || GET_CODE (operands
[1]) == CONST
)
1500 && push_operand (operands
[0], SImode
))
1502 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
1503 || GET_CODE (operands
[1]) == CONST
)
1504 && ADDRESS_REG_P (operands
[0]))
1505 return "lea %a1,%0";
1506 return "move%.l %1,%0";
1510 output_move_himode (operands
)
1513 if (GET_CODE (operands
[1]) == CONST_INT
)
1515 if (operands
[1] == const0_rtx
1516 && (DATA_REG_P (operands
[0])
1517 || GET_CODE (operands
[0]) == MEM
)
1518 /* clr insns on 68000 read before writing.
1519 This isn't so on the 68010, but we have no TARGET_68010. */
1520 && ((TARGET_68020
|| TARGET_5200
)
1521 || !(GET_CODE (operands
[0]) == MEM
1522 && MEM_VOLATILE_P (operands
[0]))))
1524 else if (DATA_REG_P (operands
[0])
1525 && INTVAL (operands
[1]) < 128
1526 && INTVAL (operands
[1]) >= -128)
1528 #if defined(MOTOROLA) && !defined(CRDS)
1529 return "moveq%.l %1,%0";
1531 return "moveq %1,%0";
1534 else if (INTVAL (operands
[1]) < 0x8000
1535 && INTVAL (operands
[1]) >= -0x8000)
1536 return "move%.w %1,%0";
1538 else if (CONSTANT_P (operands
[1]))
1539 return "move%.l %1,%0";
1541 /* Recognize the insn before a tablejump, one that refers
1542 to a table of offsets. Such an insn will need to refer
1543 to a label on the insn. So output one. Use the label-number
1544 of the table of offsets to generate this label. This code,
1545 and similar code below, assumes that there will be at most one
1546 reference to each table. */
1547 if (GET_CODE (operands
[1]) == MEM
1548 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
1549 && GET_CODE (XEXP (XEXP (operands
[1], 0), 1)) == LABEL_REF
1550 && GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) != PLUS
)
1552 rtx labelref
= XEXP (XEXP (operands
[1], 0), 1);
1553 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
1555 asm_fprintf (asm_out_file
, "\tset %LLI%d,.+2\n",
1556 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1558 asm_fprintf (asm_out_file
, "\t.set %LLI%d,.+2\n",
1559 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1560 #endif /* not SGS */
1561 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
1562 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LI",
1563 CODE_LABEL_NUMBER (XEXP (labelref
, 0)));
1564 #ifdef SGS_SWITCH_TABLES
1565 /* Set flag saying we need to define the symbol
1566 LD%n (with value L%n-LI%n) at the end of the switch table. */
1567 switch_table_difference_label_flag
= 1;
1568 #endif /* SGS_SWITCH_TABLES */
1569 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
1571 #endif /* SGS_NO_LI */
1572 return "move%.w %1,%0";
1576 output_move_qimode (operands
)
1581 /* This is probably useless, since it loses for pushing a struct
1582 of several bytes a byte at a time. */
1583 /* 68k family always modifies the stack pointer by at least 2, even for
1584 byte pushes. The 5200 (coldfire) does not do this. */
1585 if (GET_CODE (operands
[0]) == MEM
1586 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1587 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
1588 && ! ADDRESS_REG_P (operands
[1])
1591 xoperands
[1] = operands
[1];
1593 = gen_rtx (MEM
, QImode
,
1594 gen_rtx (PLUS
, VOIDmode
, stack_pointer_rtx
, const1_rtx
));
1595 /* Just pushing a byte puts it in the high byte of the halfword. */
1596 /* We must put it in the low-order, high-numbered byte. */
1597 if (!reg_mentioned_p (stack_pointer_rtx
, operands
[1]))
1599 xoperands
[3] = stack_pointer_rtx
;
1601 output_asm_insn ("subq%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1603 output_asm_insn ("sub%.l %#2,%3\n\tmove%.b %1,%2", xoperands
);
1607 output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands
);
1611 /* clr and st insns on 68000 read before writing.
1612 This isn't so on the 68010, but we have no TARGET_68010. */
1613 if (!ADDRESS_REG_P (operands
[0])
1614 && ((TARGET_68020
|| TARGET_5200
)
1615 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1617 if (operands
[1] == const0_rtx
)
1619 if ((!TARGET_5200
|| DATA_REG_P (operands
[0]))
1620 && GET_CODE (operands
[1]) == CONST_INT
1621 && (INTVAL (operands
[1]) & 255) == 255)
1627 if (GET_CODE (operands
[1]) == CONST_INT
1628 && DATA_REG_P (operands
[0])
1629 && INTVAL (operands
[1]) < 128
1630 && INTVAL (operands
[1]) >= -128)
1632 #if defined(MOTOROLA) && !defined(CRDS)
1633 return "moveq%.l %1,%0";
1635 return "moveq %1,%0";
1638 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
1639 return "move%.l %1,%0";
1640 /* 68k family doesn't support byte moves to from address registers. The
1641 5200 (coldfire) does not have this restriction. */
1642 if ((ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
1644 return "move%.w %1,%0";
1645 return "move%.b %1,%0";
1649 output_move_stricthi (operands
)
1652 if (operands
[1] == const0_rtx
1653 /* clr insns on 68000 read before writing.
1654 This isn't so on the 68010, but we have no TARGET_68010. */
1655 && ((TARGET_68020
|| TARGET_5200
)
1656 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1658 return "move%.w %1,%0";
1662 output_move_strictqi (operands
)
1665 if (operands
[1] == const0_rtx
1666 /* clr insns on 68000 read before writing.
1667 This isn't so on the 68010, but we have no TARGET_68010. */
1668 && ((TARGET_68020
|| TARGET_5200
)
1669 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
1671 return "move%.b %1,%0";
1674 /* Return the best assembler insn template
1675 for moving operands[1] into operands[0] as a fullword. */
1678 singlemove_string (operands
)
1681 #ifdef SUPPORT_SUN_FPA
1682 if (FPA_REG_P (operands
[0]) || FPA_REG_P (operands
[1]))
1683 return "fpmoves %1,%0";
1685 if (GET_CODE (operands
[1]) == CONST_INT
)
1686 return output_move_simode_const (operands
);
1687 return "move%.l %1,%0";
1691 /* Output assembler code to perform a doubleword move insn
1692 with operands OPERANDS. */
1695 output_move_double (operands
)
1700 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
1705 rtx addreg0
= 0, addreg1
= 0;
1706 int dest_overlapped_low
= 0;
1707 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
1712 /* First classify both operands. */
1714 if (REG_P (operands
[0]))
1716 else if (offsettable_memref_p (operands
[0]))
1718 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
1720 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1722 else if (GET_CODE (operands
[0]) == MEM
)
1727 if (REG_P (operands
[1]))
1729 else if (CONSTANT_P (operands
[1]))
1731 else if (offsettable_memref_p (operands
[1]))
1733 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
1735 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
1737 else if (GET_CODE (operands
[1]) == MEM
)
1742 /* Check for the cases that the operand constraints are not
1743 supposed to allow to happen. Abort if we get one,
1744 because generating code for these cases is painful. */
1746 if (optype0
== RNDOP
|| optype1
== RNDOP
)
1749 /* If one operand is decrementing and one is incrementing
1750 decrement the former register explicitly
1751 and change that operand into ordinary indexing. */
1753 if (optype0
== PUSHOP
&& optype1
== POPOP
)
1755 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
1757 output_asm_insn ("sub%.l %#12,%0", operands
);
1759 output_asm_insn ("subq%.l %#8,%0", operands
);
1760 if (GET_MODE (operands
[1]) == XFmode
)
1761 operands
[0] = gen_rtx (MEM
, XFmode
, operands
[0]);
1762 else if (GET_MODE (operands
[0]) == DFmode
)
1763 operands
[0] = gen_rtx (MEM
, DFmode
, operands
[0]);
1765 operands
[0] = gen_rtx (MEM
, DImode
, operands
[0]);
1768 if (optype0
== POPOP
&& optype1
== PUSHOP
)
1770 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
1772 output_asm_insn ("sub%.l %#12,%1", operands
);
1774 output_asm_insn ("subq%.l %#8,%1", operands
);
1775 if (GET_MODE (operands
[1]) == XFmode
)
1776 operands
[1] = gen_rtx (MEM
, XFmode
, operands
[1]);
1777 else if (GET_MODE (operands
[1]) == DFmode
)
1778 operands
[1] = gen_rtx (MEM
, DFmode
, operands
[1]);
1780 operands
[1] = gen_rtx (MEM
, DImode
, operands
[1]);
1784 /* If an operand is an unoffsettable memory ref, find a register
1785 we can increment temporarily to make it refer to the second word. */
1787 if (optype0
== MEMOP
)
1788 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
1790 if (optype1
== MEMOP
)
1791 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
1793 /* Ok, we can do one word at a time.
1794 Normally we do the low-numbered word first,
1795 but if either operand is autodecrementing then we
1796 do the high-numbered word first.
1798 In either case, set up in LATEHALF the operands to use
1799 for the high-numbered word and in some cases alter the
1800 operands in OPERANDS to be suitable for the low-numbered word. */
1804 if (optype0
== REGOP
)
1806 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 2);
1807 middlehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1809 else if (optype0
== OFFSOP
)
1811 middlehalf
[0] = adj_offsettable_operand (operands
[0], 4);
1812 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1816 middlehalf
[0] = operands
[0];
1817 latehalf
[0] = operands
[0];
1820 if (optype1
== REGOP
)
1822 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 2);
1823 middlehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1825 else if (optype1
== OFFSOP
)
1827 middlehalf
[1] = adj_offsettable_operand (operands
[1], 4);
1828 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1830 else if (optype1
== CNSTOP
)
1832 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1837 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1838 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
1839 operands
[1] = GEN_INT (l
[0]);
1840 middlehalf
[1] = GEN_INT (l
[1]);
1841 latehalf
[1] = GEN_INT (l
[2]);
1843 else if (CONSTANT_P (operands
[1]))
1845 /* actually, no non-CONST_DOUBLE constant should ever
1848 if (GET_CODE (operands
[1]) == CONST_INT
&& INTVAL (operands
[1]) < 0)
1849 latehalf
[1] = constm1_rtx
;
1851 latehalf
[1] = const0_rtx
;
1856 middlehalf
[1] = operands
[1];
1857 latehalf
[1] = operands
[1];
1861 /* size is not 12: */
1863 if (optype0
== REGOP
)
1864 latehalf
[0] = gen_rtx (REG
, SImode
, REGNO (operands
[0]) + 1);
1865 else if (optype0
== OFFSOP
)
1866 latehalf
[0] = adj_offsettable_operand (operands
[0], size
- 4);
1868 latehalf
[0] = operands
[0];
1870 if (optype1
== REGOP
)
1871 latehalf
[1] = gen_rtx (REG
, SImode
, REGNO (operands
[1]) + 1);
1872 else if (optype1
== OFFSOP
)
1873 latehalf
[1] = adj_offsettable_operand (operands
[1], size
- 4);
1874 else if (optype1
== CNSTOP
)
1875 split_double (operands
[1], &operands
[1], &latehalf
[1]);
1877 latehalf
[1] = operands
[1];
1880 /* If insn is effectively movd N(sp),-(sp) then we will do the
1881 high word first. We should use the adjusted operand 1 (which is N+4(sp))
1882 for the low word as well, to compensate for the first decrement of sp. */
1883 if (optype0
== PUSHOP
1884 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
1885 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
1886 operands
[1] = middlehalf
[1] = latehalf
[1];
1888 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
1889 if the upper part of reg N does not appear in the MEM, arrange to
1890 emit the move late-half first. Otherwise, compute the MEM address
1891 into the upper part of N and use that as a pointer to the memory
1893 if (optype0
== REGOP
1894 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
1896 rtx testlow
= gen_rtx (REG
, SImode
, REGNO (operands
[0]));
1898 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1899 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1901 /* If both halves of dest are used in the src memory address,
1902 compute the address into latehalf of dest.
1903 Note that this can't happen if the dest is two data regs. */
1905 xops
[0] = latehalf
[0];
1906 xops
[1] = XEXP (operands
[1], 0);
1907 output_asm_insn ("lea %a1,%0", xops
);
1908 if( GET_MODE (operands
[1]) == XFmode
)
1910 operands
[1] = gen_rtx (MEM
, XFmode
, latehalf
[0]);
1911 middlehalf
[1] = adj_offsettable_operand (operands
[1], size
-8);
1912 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1916 operands
[1] = gen_rtx (MEM
, DImode
, latehalf
[0]);
1917 latehalf
[1] = adj_offsettable_operand (operands
[1], size
-4);
1921 && reg_overlap_mentioned_p (middlehalf
[0],
1922 XEXP (operands
[1], 0)))
1924 /* Check for two regs used by both source and dest.
1925 Note that this can't happen if the dest is all data regs.
1926 It can happen if the dest is d6, d7, a0.
1927 But in that case, latehalf is an addr reg, so
1928 the code at compadr does ok. */
1930 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
1931 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
1934 /* JRV says this can't happen: */
1935 if (addreg0
|| addreg1
)
1938 /* Only the middle reg conflicts; simply put it last. */
1939 output_asm_insn (singlemove_string (operands
), operands
);
1940 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1941 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1944 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
1945 /* If the low half of dest is mentioned in the source memory
1946 address, the arrange to emit the move late half first. */
1947 dest_overlapped_low
= 1;
1950 /* If one or both operands autodecrementing,
1951 do the two words, high-numbered first. */
1953 /* Likewise, the first move would clobber the source of the second one,
1954 do them in the other order. This happens only for registers;
1955 such overlap can't happen in memory unless the user explicitly
1956 sets it up, and that is an undefined circumstance. */
1958 if (optype0
== PUSHOP
|| optype1
== PUSHOP
1959 || (optype0
== REGOP
&& optype1
== REGOP
1960 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
1961 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
1962 || dest_overlapped_low
)
1964 /* Make any unoffsettable addresses point at high-numbered word. */
1968 output_asm_insn ("addq%.l %#8,%0", &addreg0
);
1970 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
1975 output_asm_insn ("addq%.l %#8,%0", &addreg1
);
1977 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
1981 output_asm_insn (singlemove_string (latehalf
), latehalf
);
1983 /* Undo the adds we just did. */
1985 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1987 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1991 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
1993 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
1995 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
1998 /* Do low-numbered word. */
1999 return singlemove_string (operands
);
2002 /* Normal case: do the two words, low-numbered first. */
2004 output_asm_insn (singlemove_string (operands
), operands
);
2006 /* Do the middle one of the three words for long double */
2010 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2012 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2014 output_asm_insn (singlemove_string (middlehalf
), middlehalf
);
2017 /* Make any unoffsettable addresses point at high-numbered word. */
2019 output_asm_insn ("addq%.l %#4,%0", &addreg0
);
2021 output_asm_insn ("addq%.l %#4,%0", &addreg1
);
2024 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2026 /* Undo the adds we just did. */
2030 output_asm_insn ("subq%.l %#8,%0", &addreg0
);
2032 output_asm_insn ("subq%.l %#4,%0", &addreg0
);
2037 output_asm_insn ("subq%.l %#8,%0", &addreg1
);
2039 output_asm_insn ("subq%.l %#4,%0", &addreg1
);
2045 /* Return a REG that occurs in ADDR with coefficient 1.
2046 ADDR can be effectively incremented by incrementing REG. */
2049 find_addr_reg (addr
)
2052 while (GET_CODE (addr
) == PLUS
)
2054 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2055 addr
= XEXP (addr
, 0);
2056 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2057 addr
= XEXP (addr
, 1);
2058 else if (CONSTANT_P (XEXP (addr
, 0)))
2059 addr
= XEXP (addr
, 1);
2060 else if (CONSTANT_P (XEXP (addr
, 1)))
2061 addr
= XEXP (addr
, 0);
2065 if (GET_CODE (addr
) == REG
)
2070 /* Output assembler code to perform a 32 bit 3 operand add. */
2073 output_addsi3 (operands
)
2076 if (! operands_match_p (operands
[0], operands
[1]))
2078 if (!ADDRESS_REG_P (operands
[1]))
2080 rtx tmp
= operands
[1];
2082 operands
[1] = operands
[2];
2086 /* These insns can result from reloads to access
2087 stack slots over 64k from the frame pointer. */
2088 if (GET_CODE (operands
[2]) == CONST_INT
2089 && INTVAL (operands
[2]) + 0x8000 >= (unsigned) 0x10000)
2090 return "move%.l %2,%0\n\tadd%.l %1,%0";
2092 if (GET_CODE (operands
[2]) == REG
)
2093 return "lea 0(%1,%2.l),%0";
2095 return "lea %c2(%1),%0";
2098 if (GET_CODE (operands
[2]) == REG
)
2099 return "lea (%1,%2.l),%0";
2101 return "lea (%c2,%1),%0";
2102 #else /* not MOTOROLA (MIT syntax) */
2103 if (GET_CODE (operands
[2]) == REG
)
2104 return "lea %1@(0,%2:l),%0";
2106 return "lea %1@(%c2),%0";
2107 #endif /* not MOTOROLA */
2108 #endif /* not SGS */
2110 if (GET_CODE (operands
[2]) == CONST_INT
)
2113 if (INTVAL (operands
[2]) > 0
2114 && INTVAL (operands
[2]) <= 8)
2115 return "addq%.l %2,%0";
2116 if (INTVAL (operands
[2]) < 0
2117 && INTVAL (operands
[2]) >= -8)
2119 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
,
2120 - INTVAL (operands
[2]));
2121 return "subq%.l %2,%0";
2123 /* On the CPU32 it is faster to use two addql instructions to
2124 add a small integer (8 < N <= 16) to a register.
2125 Likewise for subql. */
2126 if (TARGET_CPU32
&& REG_P (operands
[0]))
2128 if (INTVAL (operands
[2]) > 8
2129 && INTVAL (operands
[2]) <= 16)
2131 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
,
2132 INTVAL (operands
[2]) - 8);
2133 return "addq%.l %#8,%0\n\taddq%.l %2,%0";
2135 if (INTVAL (operands
[2]) < -8
2136 && INTVAL (operands
[2]) >= -16)
2138 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
,
2139 - INTVAL (operands
[2]) - 8);
2140 return "subq%.l %#8,%0\n\tsubq%.l %2,%0";
2144 if (ADDRESS_REG_P (operands
[0])
2145 && INTVAL (operands
[2]) >= -0x8000
2146 && INTVAL (operands
[2]) < 0x8000)
2149 return "add%.w %2,%0";
2152 return "lea (%c2,%0),%0";
2154 return "lea %0@(%c2),%0";
2158 return "add%.l %2,%0";
2161 /* Store in cc_status the expressions that the condition codes will
2162 describe after execution of an instruction whose pattern is EXP.
2163 Do not alter them if the instruction would not alter the cc's. */
2165 /* On the 68000, all the insns to store in an address register fail to
2166 set the cc's. However, in some cases these instructions can make it
2167 possibly invalid to use the saved cc's. In those cases we clear out
2168 some or all of the saved cc's so they won't be used. */
2170 notice_update_cc (exp
, insn
)
2174 /* If the cc is being set from the fpa and the expression is not an
2175 explicit floating point test instruction (which has code to deal with
2176 this), reinit the CC. */
2177 if (((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2178 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
)))
2179 && !(GET_CODE (exp
) == PARALLEL
2180 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
2181 && XEXP (XVECEXP (exp
, 0, 0), 0) == cc0_rtx
))
2185 else if (GET_CODE (exp
) == SET
)
2187 if (GET_CODE (SET_SRC (exp
)) == CALL
)
2191 else if (ADDRESS_REG_P (SET_DEST (exp
)))
2193 if (cc_status
.value1
2194 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value1
))
2195 cc_status
.value1
= 0;
2196 if (cc_status
.value2
2197 && reg_overlap_mentioned_p (SET_DEST (exp
), cc_status
.value2
))
2198 cc_status
.value2
= 0;
2200 else if (!FP_REG_P (SET_DEST (exp
))
2201 && SET_DEST (exp
) != cc0_rtx
2202 && (FP_REG_P (SET_SRC (exp
))
2203 || GET_CODE (SET_SRC (exp
)) == FIX
2204 || GET_CODE (SET_SRC (exp
)) == FLOAT_TRUNCATE
2205 || GET_CODE (SET_SRC (exp
)) == FLOAT_EXTEND
))
2209 /* A pair of move insns doesn't produce a useful overall cc. */
2210 else if (!FP_REG_P (SET_DEST (exp
))
2211 && !FP_REG_P (SET_SRC (exp
))
2212 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
2213 && (GET_CODE (SET_SRC (exp
)) == REG
2214 || GET_CODE (SET_SRC (exp
)) == MEM
2215 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
2219 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
2223 else if (XEXP (exp
, 0) != pc_rtx
)
2225 cc_status
.flags
= 0;
2226 cc_status
.value1
= XEXP (exp
, 0);
2227 cc_status
.value2
= XEXP (exp
, 1);
2230 else if (GET_CODE (exp
) == PARALLEL
2231 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
2233 if (ADDRESS_REG_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
2235 else if (XEXP (XVECEXP (exp
, 0, 0), 0) != pc_rtx
)
2237 cc_status
.flags
= 0;
2238 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
2239 cc_status
.value2
= XEXP (XVECEXP (exp
, 0, 0), 1);
2244 if (cc_status
.value2
!= 0
2245 && ADDRESS_REG_P (cc_status
.value2
)
2246 && GET_MODE (cc_status
.value2
) == QImode
)
2248 if (cc_status
.value2
!= 0
2249 && !(cc_status
.value1
&& FPA_REG_P (cc_status
.value1
)))
2250 switch (GET_CODE (cc_status
.value2
))
2252 case PLUS
: case MINUS
: case MULT
:
2253 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
2254 #if 0 /* These instructions always clear the overflow bit */
2255 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
2256 case ROTATE
: case ROTATERT
:
2258 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
2259 cc_status
.flags
|= CC_NO_OVERFLOW
;
2262 /* (SET r1 (ZERO_EXTEND r2)) on this machine
2263 ends with a move insn moving r2 in r2's mode.
2264 Thus, the cc's are set for r2.
2265 This can set N bit spuriously. */
2266 cc_status
.flags
|= CC_NOT_NEGATIVE
;
2268 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
2270 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
2271 cc_status
.value2
= 0;
2272 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
2273 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
)))
2274 && !((cc_status
.value1
&& FPA_REG_P (cc_status
.value1
))
2275 || (cc_status
.value2
&& FPA_REG_P (cc_status
.value2
))))
2276 cc_status
.flags
= CC_IN_68881
;
2280 output_move_const_double (operands
)
2283 #ifdef SUPPORT_SUN_FPA
2284 if (TARGET_FPA
&& FPA_REG_P (operands
[0]))
2286 int code
= standard_sun_fpa_constant_p (operands
[1]);
2290 static char buf
[40];
2292 sprintf (buf
, "fpmove%%.d %%%%%d,%%0", code
& 0x1ff);
2295 return "fpmove%.d %1,%0";
2300 int code
= standard_68881_constant_p (operands
[1]);
2304 static char buf
[40];
2306 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2309 return "fmove%.d %1,%0";
2314 output_move_const_single (operands
)
2317 #ifdef SUPPORT_SUN_FPA
2320 int code
= standard_sun_fpa_constant_p (operands
[1]);
2324 static char buf
[40];
2326 sprintf (buf
, "fpmove%%.s %%%%%d,%%0", code
& 0x1ff);
2329 return "fpmove%.s %1,%0";
2332 #endif /* defined SUPPORT_SUN_FPA */
2334 int code
= standard_68881_constant_p (operands
[1]);
2338 static char buf
[40];
2340 sprintf (buf
, "fmovecr %%#0x%x,%%0", code
& 0xff);
2343 return "fmove%.s %f1,%0";
2347 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2348 from the "fmovecr" instruction.
2349 The value, anded with 0xff, gives the code to use in fmovecr
2350 to get the desired constant. */
2352 /* This code has been fixed for cross-compilation. */
2354 static int inited_68881_table
= 0;
2356 char *strings_68881
[7] = {
2366 int codes_68881
[7] = {
2376 REAL_VALUE_TYPE values_68881
[7];
2378 /* Set up values_68881 array by converting the decimal values
2379 strings_68881 to binary. */
2386 enum machine_mode mode
;
2389 for (i
= 0; i
< 7; i
++)
2393 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
2394 values_68881
[i
] = r
;
2396 inited_68881_table
= 1;
2400 standard_68881_constant_p (x
)
2405 enum machine_mode mode
;
2407 #ifdef NO_ASM_FMOVECR
2411 /* fmovecr must be emulated on the 68040, so it shouldn't be used at all. */
2415 #ifndef REAL_ARITHMETIC
2416 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2417 if (! flag_pretend_float
)
2422 if (! inited_68881_table
)
2423 init_68881_table ();
2425 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2427 for (i
= 0; i
< 6; i
++)
2429 if (REAL_VALUES_EQUAL (r
, values_68881
[i
]))
2430 return (codes_68881
[i
]);
2433 if (GET_MODE (x
) == SFmode
)
2436 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
2437 return (codes_68881
[6]);
2439 /* larger powers of ten in the constants ram are not used
2440 because they are not equal to a `double' C constant. */
2444 /* If X is a floating-point constant, return the logarithm of X base 2,
2445 or 0 if X is not a power of 2. */
2448 floating_exact_log2 (x
)
2451 REAL_VALUE_TYPE r
, r1
;
2454 #ifndef REAL_ARITHMETIC
2455 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2456 if (! flag_pretend_float
)
2461 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2463 if (REAL_VALUES_LESS (r
, dconst0
))
2468 while (REAL_VALUES_LESS (r1
, r
))
2470 r1
= REAL_VALUE_LDEXP (dconst1
, i
);
2471 if (REAL_VALUES_EQUAL (r1
, r
))
2478 #ifdef SUPPORT_SUN_FPA
2479 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
2480 from the Sun FPA's constant RAM.
2481 The value returned, anded with 0x1ff, gives the code to use in fpmove
2482 to get the desired constant. */
2484 static int inited_FPA_table
= 0;
2486 char *strings_FPA
[38] = {
2487 /* small rationals */
2500 /* Decimal equivalents of double precision values */
2501 "2.718281828459045091", /* D_E */
2502 "6.283185307179586477", /* 2 pi */
2503 "3.141592653589793116", /* D_PI */
2504 "1.570796326794896619", /* pi/2 */
2505 "1.414213562373095145", /* D_SQRT2 */
2506 "0.7071067811865475244", /* 1/sqrt(2) */
2507 "-1.570796326794896619", /* -pi/2 */
2508 "1.442695040888963387", /* D_LOG2ofE */
2509 "3.321928024887362182", /* D_LOG2of10 */
2510 "0.6931471805599452862", /* D_LOGEof2 */
2511 "2.302585092994045901", /* D_LOGEof10 */
2512 "0.3010299956639811980", /* D_LOG10of2 */
2513 "0.4342944819032518167", /* D_LOG10ofE */
2514 /* Decimal equivalents of single precision values */
2515 "2.718281745910644531", /* S_E */
2516 "6.283185307179586477", /* 2 pi */
2517 "3.141592741012573242", /* S_PI */
2518 "1.570796326794896619", /* pi/2 */
2519 "1.414213538169860840", /* S_SQRT2 */
2520 "0.7071067811865475244", /* 1/sqrt(2) */
2521 "-1.570796326794896619", /* -pi/2 */
2522 "1.442695021629333496", /* S_LOG2ofE */
2523 "3.321928024291992188", /* S_LOG2of10 */
2524 "0.6931471824645996094", /* S_LOGEof2 */
2525 "2.302585124969482442", /* S_LOGEof10 */
2526 "0.3010300099849700928", /* S_LOG10of2 */
2527 "0.4342944920063018799", /* S_LOG10ofE */
2531 int codes_FPA
[38] = {
2532 /* small rationals */
2545 /* double precision */
2559 /* single precision */
2575 REAL_VALUE_TYPE values_FPA
[38];
2577 /* This code has been fixed for cross-compilation. */
2582 enum machine_mode mode
;
2587 for (i
= 0; i
< 38; i
++)
2591 r
= REAL_VALUE_ATOF (strings_FPA
[i
], mode
);
2594 inited_FPA_table
= 1;
2599 standard_sun_fpa_constant_p (x
)
2605 #ifndef REAL_ARITHMETIC
2606 #if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
2607 if (! flag_pretend_float
)
2612 if (! inited_FPA_table
)
2615 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2617 for (i
=0; i
<12; i
++)
2619 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2620 return (codes_FPA
[i
]);
2623 if (GET_MODE (x
) == SFmode
)
2625 for (i
=25; i
<38; i
++)
2627 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2628 return (codes_FPA
[i
]);
2633 for (i
=12; i
<25; i
++)
2635 if (REAL_VALUES_EQUAL (r
, values_FPA
[i
]))
2636 return (codes_FPA
[i
]);
2641 #endif /* define SUPPORT_SUN_FPA */
2643 /* A C compound statement to output to stdio stream STREAM the
2644 assembler syntax for an instruction operand X. X is an RTL
2647 CODE is a value that can be used to specify one of several ways
2648 of printing the operand. It is used when identical operands
2649 must be printed differently depending on the context. CODE
2650 comes from the `%' specification that was used to request
2651 printing of the operand. If the specification was just `%DIGIT'
2652 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2653 is the ASCII code for LTR.
2655 If X is a register, this macro should print the register's name.
2656 The names can be found in an array `reg_names' whose type is
2657 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2659 When the machine description has a specification `%PUNCT' (a `%'
2660 followed by a punctuation character), this macro is called with
2661 a null pointer for X and the punctuation character for CODE.
2663 The m68k specific codes are:
2665 '.' for dot needed in Motorola-style opcode names.
2666 '-' for an operand pushing on the stack:
2667 sp@-, -(sp) or -(%sp) depending on the style of syntax.
2668 '+' for an operand pushing on the stack:
2669 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
2670 '@' for a reference to the top word on the stack:
2671 sp@, (sp) or (%sp) depending on the style of syntax.
2672 '#' for an immediate operand prefix (# in MIT and Motorola syntax
2673 but & in SGS syntax, $ in CRDS/UNOS syntax).
2674 '!' for the cc register (used in an `and to cc' insn).
2675 '$' for the letter `s' in an op code, but only on the 68040.
2676 '&' for the letter `d' in an op code, but only on the 68040.
2677 '/' for register prefix needed by longlong.h.
2679 'b' for byte insn (no effect, on the Sun; this is for the ISI).
2680 'd' to force memory addressing to be absolute, not relative.
2681 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
2682 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
2683 than directly). Second part of 'y' below.
2684 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
2685 or print pair of registers as rx:ry.
2686 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
2687 CONST_DOUBLE's as SunFPA constant RAM registers if
2688 possible, so it should not be used except for the SunFPA.
2693 print_operand (file
, op
, letter
)
2694 FILE *file
; /* file to write to */
2695 rtx op
; /* operand to print */
2696 int letter
; /* %<letter> or 0 */
2702 #if defined (MOTOROLA) && !defined (CRDS)
2703 asm_fprintf (file
, ".");
2706 else if (letter
== '#')
2708 asm_fprintf (file
, "%0I");
2710 else if (letter
== '-')
2713 asm_fprintf (file
, "-(%Rsp)");
2715 asm_fprintf (file
, "%Rsp@-");
2718 else if (letter
== '+')
2721 asm_fprintf (file
, "(%Rsp)+");
2723 asm_fprintf (file
, "%Rsp@+");
2726 else if (letter
== '@')
2729 asm_fprintf (file
, "(%Rsp)");
2731 asm_fprintf (file
, "%Rsp@");
2734 else if (letter
== '!')
2736 asm_fprintf (file
, "%Rfpcr");
2738 else if (letter
== '$')
2740 if (TARGET_68040_ONLY
)
2742 fprintf (file
, "s");
2745 else if (letter
== '&')
2747 if (TARGET_68040_ONLY
)
2749 fprintf (file
, "d");
2752 else if (letter
== '/')
2754 asm_fprintf (file
, "%R");
2756 else if (GET_CODE (op
) == REG
)
2758 #ifdef SUPPORT_SUN_FPA
2760 && (letter
== 'y' || letter
== 'x')
2761 && GET_MODE (op
) == DFmode
)
2763 fprintf (file
, "%s:%s", reg_names
[REGNO (op
)],
2764 reg_names
[REGNO (op
)+1]);
2770 /* Print out the second register name of a register pair.
2771 I.e., R (6) => 7. */
2772 fputs (reg_names
[REGNO (op
) + 1], file
);
2774 fputs (reg_names
[REGNO (op
)], file
);
2777 else if (GET_CODE (op
) == MEM
)
2779 output_address (XEXP (op
, 0));
2780 if (letter
== 'd' && ! TARGET_68020
2781 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
2782 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
2783 && INTVAL (XEXP (op
, 0)) < 0x8000
2784 && INTVAL (XEXP (op
, 0)) >= -0x8000))
2787 fprintf (file
, ".l");
2789 fprintf (file
, ":l");
2793 #ifdef SUPPORT_SUN_FPA
2794 else if ((letter
== 'y' || letter
== 'w')
2795 && GET_CODE (op
) == CONST_DOUBLE
2796 && (i
= standard_sun_fpa_constant_p (op
)))
2798 fprintf (file
, "%%%d", i
& 0x1ff);
2801 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
2804 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2805 ASM_OUTPUT_FLOAT_OPERAND (letter
, file
, r
);
2807 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
2810 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2811 ASM_OUTPUT_LONG_DOUBLE_OPERAND (file
, r
);
2813 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
2816 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
2817 ASM_OUTPUT_DOUBLE_OPERAND (file
, r
);
2821 asm_fprintf (file
, "%0I"); output_addr_const (file
, op
);
2826 /* A C compound statement to output to stdio stream STREAM the
2827 assembler syntax for an instruction operand that is a memory
2828 reference whose address is ADDR. ADDR is an RTL expression.
2830 Note that this contains a kludge that knows that the only reason
2831 we have an address (plus (label_ref...) (reg...)) when not generating
2832 PIC code is in the insn before a tablejump, and we know that m68k.md
2833 generates a label LInnn: on such an insn.
2835 It is possible for PIC to generate a (plus (label_ref...) (reg...))
2836 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
2838 Some SGS assemblers have a bug such that "Lnnn-LInnn-2.b(pc,d0.l*2)"
2839 fails to assemble. Luckily "Lnnn(pc,d0.l*2)" produces the results
2840 we want. This difference can be accommodated by using an assembler
2841 define such "LDnnn" to be either "Lnnn-LInnn-2.b", "Lnnn", or any other
2842 string, as necessary. This is accomplished via the ASM_OUTPUT_CASE_END
2843 macro. See m68k/sgs.h for an example; for versions without the bug.
2844 Some assemblers refuse all the above solutions. The workaround is to
2845 emit "K(pc,d0.l*2)" with K being a small constant known to give the
2848 They also do not like things like "pea 1.w", so we simple leave off
2849 the .w on small constants.
2851 This routine is responsible for distinguishing between -fpic and -fPIC
2852 style relocations in an address. When generating -fpic code the
2853 offset is output in word mode (eg movel a5@(_foo:w), a0). When generating
2854 -fPIC code the offset is output in long mode (eg movel a5@(_foo:l), a0) */
2856 #ifndef ASM_OUTPUT_CASE_FETCH
2859 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2860 asm_fprintf (file, "%LLD%d(%Rpc,%s.", labelno, regname)
2862 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2863 asm_fprintf (file, "%LL%d-%LLI%d.b(%Rpc,%s.", labelno, labelno, regname)
2866 #define ASM_OUTPUT_CASE_FETCH(file, labelno, regname)\
2867 asm_fprintf (file, "%Rpc@(%LL%d-%LLI%d-2:b,%s:", labelno, labelno, regname)
2869 #endif /* ASM_OUTPUT_CASE_FETCH */
2872 print_operand_address (file
, addr
)
2876 register rtx reg1
, reg2
, breg
, ireg
;
2879 switch (GET_CODE (addr
))
2883 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
2885 fprintf (file
, "%s@", reg_names
[REGNO (addr
)]);
2890 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
2892 fprintf (file
, "%s@-", reg_names
[REGNO (XEXP (addr
, 0))]);
2897 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
2899 fprintf (file
, "%s@+", reg_names
[REGNO (XEXP (addr
, 0))]);
2903 reg1
= reg2
= ireg
= breg
= offset
= 0;
2904 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0)))
2906 offset
= XEXP (addr
, 0);
2907 addr
= XEXP (addr
, 1);
2909 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1)))
2911 offset
= XEXP (addr
, 1);
2912 addr
= XEXP (addr
, 0);
2914 if (GET_CODE (addr
) != PLUS
)
2918 else if (GET_CODE (XEXP (addr
, 0)) == SIGN_EXTEND
)
2920 reg1
= XEXP (addr
, 0);
2921 addr
= XEXP (addr
, 1);
2923 else if (GET_CODE (XEXP (addr
, 1)) == SIGN_EXTEND
)
2925 reg1
= XEXP (addr
, 1);
2926 addr
= XEXP (addr
, 0);
2928 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
2930 reg1
= XEXP (addr
, 0);
2931 addr
= XEXP (addr
, 1);
2933 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
2935 reg1
= XEXP (addr
, 1);
2936 addr
= XEXP (addr
, 0);
2938 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
2940 reg1
= XEXP (addr
, 0);
2941 addr
= XEXP (addr
, 1);
2943 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2945 reg1
= XEXP (addr
, 1);
2946 addr
= XEXP (addr
, 0);
2948 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == MULT
2949 || GET_CODE (addr
) == SIGN_EXTEND
)
2961 #if 0 /* for OLD_INDEXING */
2962 else if (GET_CODE (addr
) == PLUS
)
2964 if (GET_CODE (XEXP (addr
, 0)) == REG
)
2966 reg2
= XEXP (addr
, 0);
2967 addr
= XEXP (addr
, 1);
2969 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
2971 reg2
= XEXP (addr
, 1);
2972 addr
= XEXP (addr
, 0);
2984 if ((reg1
&& (GET_CODE (reg1
) == SIGN_EXTEND
2985 || GET_CODE (reg1
) == MULT
))
2986 || (reg2
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2
))))
2991 else if (reg1
!= 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1
)))
2996 if (ireg
!= 0 && breg
== 0 && GET_CODE (addr
) == LABEL_REF
2997 && ! (flag_pic
&& ireg
== pic_offset_table_rtx
))
3000 if (GET_CODE (ireg
) == MULT
)
3002 scale
= INTVAL (XEXP (ireg
, 1));
3003 ireg
= XEXP (ireg
, 0);
3005 if (GET_CODE (ireg
) == SIGN_EXTEND
)
3007 ASM_OUTPUT_CASE_FETCH (file
,
3008 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3009 reg_names
[REGNO (XEXP (ireg
, 0))]);
3010 fprintf (file
, "w");
3014 ASM_OUTPUT_CASE_FETCH (file
,
3015 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3016 reg_names
[REGNO (ireg
)]);
3017 fprintf (file
, "l");
3022 fprintf (file
, "*%d", scale
);
3024 fprintf (file
, ":%d", scale
);
3030 if (breg
!= 0 && ireg
== 0 && GET_CODE (addr
) == LABEL_REF
3031 && ! (flag_pic
&& breg
== pic_offset_table_rtx
))
3033 ASM_OUTPUT_CASE_FETCH (file
,
3034 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3035 reg_names
[REGNO (breg
)]);
3036 fprintf (file
, "l)");
3039 if (ireg
!= 0 || breg
!= 0)
3046 if (! flag_pic
&& addr
&& GET_CODE (addr
) == LABEL_REF
)
3053 output_addr_const (file
, addr
);
3054 if (flag_pic
&& (breg
== pic_offset_table_rtx
))
3056 fprintf (file
, "@GOT");
3058 fprintf (file
, ".w");
3061 fprintf (file
, "(%s", reg_names
[REGNO (breg
)]);
3067 fprintf (file
, "%s@(", reg_names
[REGNO (breg
)]);
3070 output_addr_const (file
, addr
);
3071 if ((flag_pic
== 1) && (breg
== pic_offset_table_rtx
))
3072 fprintf (file
, ":w");
3073 if ((flag_pic
== 2) && (breg
== pic_offset_table_rtx
))
3074 fprintf (file
, ":l");
3076 if (addr
!= 0 && ireg
!= 0)
3081 if (ireg
!= 0 && GET_CODE (ireg
) == MULT
)
3083 scale
= INTVAL (XEXP (ireg
, 1));
3084 ireg
= XEXP (ireg
, 0);
3086 if (ireg
!= 0 && GET_CODE (ireg
) == SIGN_EXTEND
)
3089 fprintf (file
, "%s.w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3091 fprintf (file
, "%s:w", reg_names
[REGNO (XEXP (ireg
, 0))]);
3097 fprintf (file
, "%s.l", reg_names
[REGNO (ireg
)]);
3099 fprintf (file
, "%s:l", reg_names
[REGNO (ireg
)]);
3105 fprintf (file
, "*%d", scale
);
3107 fprintf (file
, ":%d", scale
);
3113 else if (reg1
!= 0 && GET_CODE (addr
) == LABEL_REF
3114 && ! (flag_pic
&& reg1
== pic_offset_table_rtx
))
3116 ASM_OUTPUT_CASE_FETCH (file
,
3117 CODE_LABEL_NUMBER (XEXP (addr
, 0)),
3118 reg_names
[REGNO (reg1
)]);
3119 fprintf (file
, "l)");
3122 /* FALL-THROUGH (is this really what we want? */
3124 if (GET_CODE (addr
) == CONST_INT
3125 && INTVAL (addr
) < 0x8000
3126 && INTVAL (addr
) >= -0x8000)
3130 /* Many SGS assemblers croak on size specifiers for constants. */
3131 fprintf (file
, "%d", INTVAL (addr
));
3133 fprintf (file
, "%d.w", INTVAL (addr
));
3136 fprintf (file
, "%d:w", INTVAL (addr
));
3141 output_addr_const (file
, addr
);
3147 /* Check for cases where a clr insns can be omitted from code using
3148 strict_low_part sets. For example, the second clrl here is not needed:
3149 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
3151 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
3152 insn we are checking for redundancy. TARGET is the register set by the
3156 strict_low_part_peephole_ok (mode
, first_insn
, target
)
3157 enum machine_mode mode
;
3163 p
= prev_nonnote_insn (first_insn
);
3167 /* If it isn't an insn, then give up. */
3168 if (GET_CODE (p
) != INSN
)
3171 if (reg_set_p (target
, p
))
3173 rtx set
= single_set (p
);
3176 /* If it isn't an easy to recognize insn, then give up. */
3180 dest
= SET_DEST (set
);
3182 /* If this sets the entire target register to zero, then our
3183 first_insn is redundant. */
3184 if (rtx_equal_p (dest
, target
)
3185 && SET_SRC (set
) == const0_rtx
)
3187 else if (GET_CODE (dest
) == STRICT_LOW_PART
3188 && GET_CODE (XEXP (dest
, 0)) == REG
3189 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
3190 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
3191 <= GET_MODE_SIZE (mode
)))
3192 /* This is a strict low part set which modifies less than
3193 we are using, so it is safe. */
3199 p
= prev_nonnote_insn (p
);
3206 /* Accept integer operands in the range 0..0xffffffff. We have to check the
3207 range carefully since this predicate is used in DImode contexts. Also, we
3208 need some extra crud to make it work when hosted on 64-bit machines. */
3211 const_uint32_operand (op
, mode
)
3213 enum machine_mode mode
;
3215 #if HOST_BITS_PER_WIDE_INT > 32
3216 /* All allowed constants will fit a CONST_INT. */
3217 return (GET_CODE (op
) == CONST_INT
3218 && (INTVAL (op
) >= 0 && INTVAL (op
) <= 0xffffffffL
));
3220 return ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) >= 0)
3221 || (GET_CODE (op
) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op
) == 0));
3225 /* Accept integer operands in the range -0x80000000..0x7fffffff. We have
3226 to check the range carefully since this predicate is used in DImode
3230 const_sint32_operand (op
, mode
)
3232 enum machine_mode mode
;
3234 /* All allowed constants will fit a CONST_INT. */
3235 return (GET_CODE (op
) == CONST_INT
3236 && (INTVAL (op
) >= (-0x7fffffff - 1) && INTVAL (op
) <= 0x7fffffff));
3240 output_andsi3 (operands
)
3244 if (GET_CODE (operands
[2]) == CONST_INT
3245 && (INTVAL (operands
[2]) | 0xffff) == 0xffffffff
3246 && (DATA_REG_P (operands
[0])
3247 || offsettable_memref_p (operands
[0]))
3250 if (GET_CODE (operands
[0]) != REG
)
3251 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3252 operands
[2] = gen_rtx (CONST_INT
, VOIDmode
,
3253 INTVAL (operands
[2]) & 0xffff);
3254 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3256 if (operands
[2] == const0_rtx
)
3258 return "and%.w %2,%0";
3260 if (GET_CODE (operands
[2]) == CONST_INT
3261 && (logval
= exact_log2 (~ INTVAL (operands
[2]))) >= 0
3262 && (DATA_REG_P (operands
[0])
3263 || offsettable_memref_p (operands
[0])))
3265 if (DATA_REG_P (operands
[0]))
3267 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, logval
);
3271 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3272 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, logval
% 8);
3274 /* This does not set condition codes in a standard way. */
3276 return "bclr %1,%0";
3278 return "and%.l %2,%0";
3282 output_iorsi3 (operands
)
3285 register int logval
;
3286 if (GET_CODE (operands
[2]) == CONST_INT
3287 && INTVAL (operands
[2]) >> 16 == 0
3288 && (DATA_REG_P (operands
[0])
3289 || offsettable_memref_p (operands
[0]))
3292 if (GET_CODE (operands
[0]) != REG
)
3293 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3294 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3296 if (INTVAL (operands
[2]) == 0xffff)
3297 return "mov%.w %2,%0";
3298 return "or%.w %2,%0";
3300 if (GET_CODE (operands
[2]) == CONST_INT
3301 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3302 && (DATA_REG_P (operands
[0])
3303 || offsettable_memref_p (operands
[0])))
3305 if (DATA_REG_P (operands
[0]))
3307 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, logval
);
3311 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3312 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, logval
% 8);
3315 return "bset %1,%0";
3317 return "or%.l %2,%0";
3321 output_xorsi3 (operands
)
3324 register int logval
;
3325 if (GET_CODE (operands
[2]) == CONST_INT
3326 && INTVAL (operands
[2]) >> 16 == 0
3327 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
3330 if (! DATA_REG_P (operands
[0]))
3331 operands
[0] = adj_offsettable_operand (operands
[0], 2);
3332 /* Do not delete a following tstl %0 insn; that would be incorrect. */
3334 if (INTVAL (operands
[2]) == 0xffff)
3336 return "eor%.w %2,%0";
3338 if (GET_CODE (operands
[2]) == CONST_INT
3339 && (logval
= exact_log2 (INTVAL (operands
[2]))) >= 0
3340 && (DATA_REG_P (operands
[0])
3341 || offsettable_memref_p (operands
[0])))
3343 if (DATA_REG_P (operands
[0]))
3345 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, logval
);
3349 operands
[0] = adj_offsettable_operand (operands
[0], 3 - (logval
/ 8));
3350 operands
[1] = gen_rtx (CONST_INT
, VOIDmode
, logval
% 8);
3353 return "bchg %1,%0";
3355 return "eor%.l %2,%0";