1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
36 #include "diagnostic-core.h"
41 #include "target-def.h"
45 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
46 #include "sched-int.h"
47 #include "insn-codes.h"
51 enum reg_class regno_reg_class
[] =
53 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
54 DATA_REGS
, DATA_REGS
, DATA_REGS
, DATA_REGS
,
55 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
56 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
57 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
58 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
63 /* The minimum number of integer registers that we want to save with the
64 movem instruction. Using two movel instructions instead of a single
65 moveml is about 15% faster for the 68020 and 68030 at no expense in
67 #define MIN_MOVEM_REGS 3
69 /* The minimum number of floating point registers that we want to save
70 with the fmovem instruction. */
71 #define MIN_FMOVEM_REGS 1
73 /* Structure describing stack frame layout. */
76 /* Stack pointer to frame pointer offset. */
79 /* Offset of FPU registers. */
80 HOST_WIDE_INT foffset
;
82 /* Frame size in bytes (rounded up). */
85 /* Data and address register. */
87 unsigned int reg_mask
;
91 unsigned int fpu_mask
;
93 /* Offsets relative to ARG_POINTER. */
94 HOST_WIDE_INT frame_pointer_offset
;
95 HOST_WIDE_INT stack_pointer_offset
;
97 /* Function which the above information refers to. */
101 /* Current frame information calculated by m68k_compute_frame_layout(). */
102 static struct m68k_frame current_frame
;
104 /* Structure describing an m68k address.
106 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
107 with null fields evaluating to 0. Here:
109 - BASE satisfies m68k_legitimate_base_reg_p
110 - INDEX satisfies m68k_legitimate_index_reg_p
111 - OFFSET satisfies m68k_legitimate_constant_address_p
113 INDEX is either HImode or SImode. The other fields are SImode.
115 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
116 the address is (BASE)+. */
117 struct m68k_address
{
125 static int m68k_sched_adjust_cost (rtx
, rtx
, rtx
, int);
126 static int m68k_sched_issue_rate (void);
127 static int m68k_sched_variable_issue (FILE *, int, rtx
, int);
128 static void m68k_sched_md_init_global (FILE *, int, int);
129 static void m68k_sched_md_finish_global (FILE *, int);
130 static void m68k_sched_md_init (FILE *, int, int);
131 static void m68k_sched_dfa_pre_advance_cycle (void);
132 static void m68k_sched_dfa_post_advance_cycle (void);
133 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
135 static bool m68k_can_eliminate (const int, const int);
136 static void m68k_conditional_register_usage (void);
137 static bool m68k_legitimate_address_p (enum machine_mode
, rtx
, bool);
138 static bool m68k_handle_option (struct gcc_options
*, struct gcc_options
*,
139 const struct cl_decoded_option
*, location_t
);
140 static void m68k_option_override (void);
141 static rtx
find_addr_reg (rtx
);
142 static const char *singlemove_string (rtx
*);
143 static void m68k_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
144 HOST_WIDE_INT
, tree
);
145 static rtx
m68k_struct_value_rtx (tree
, int);
146 static tree
m68k_handle_fndecl_attribute (tree
*node
, tree name
,
147 tree args
, int flags
,
149 static void m68k_compute_frame_layout (void);
150 static bool m68k_save_reg (unsigned int regno
, bool interrupt_handler
);
151 static bool m68k_ok_for_sibcall_p (tree
, tree
);
152 static bool m68k_tls_symbol_p (rtx
);
153 static rtx
m68k_legitimize_address (rtx
, rtx
, enum machine_mode
);
154 static bool m68k_rtx_costs (rtx
, int, int, int *, bool);
155 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
156 static bool m68k_return_in_memory (const_tree
, const_tree
);
158 static void m68k_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
159 static void m68k_trampoline_init (rtx
, tree
, rtx
);
160 static int m68k_return_pops_args (tree
, tree
, int);
161 static rtx
m68k_delegitimize_address (rtx
);
162 static void m68k_function_arg_advance (CUMULATIVE_ARGS
*, enum machine_mode
,
164 static rtx
m68k_function_arg (CUMULATIVE_ARGS
*, enum machine_mode
,
166 static bool m68k_cannot_force_const_mem (enum machine_mode mode
, rtx x
);
169 /* Specify the identification number of the library being built */
170 const char *m68k_library_id_string
= "_current_shared_library_a5_offset_";
172 /* Initialize the GCC target structure. */
174 #if INT_OP_GROUP == INT_OP_DOT_WORD
175 #undef TARGET_ASM_ALIGNED_HI_OP
176 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
179 #if INT_OP_GROUP == INT_OP_NO_DOT
180 #undef TARGET_ASM_BYTE_OP
181 #define TARGET_ASM_BYTE_OP "\tbyte\t"
182 #undef TARGET_ASM_ALIGNED_HI_OP
183 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
184 #undef TARGET_ASM_ALIGNED_SI_OP
185 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
188 #if INT_OP_GROUP == INT_OP_DC
189 #undef TARGET_ASM_BYTE_OP
190 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
191 #undef TARGET_ASM_ALIGNED_HI_OP
192 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
193 #undef TARGET_ASM_ALIGNED_SI_OP
194 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
197 #undef TARGET_ASM_UNALIGNED_HI_OP
198 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
199 #undef TARGET_ASM_UNALIGNED_SI_OP
200 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
202 #undef TARGET_ASM_OUTPUT_MI_THUNK
203 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
204 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
205 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
207 #undef TARGET_ASM_FILE_START_APP_OFF
208 #define TARGET_ASM_FILE_START_APP_OFF true
210 #undef TARGET_LEGITIMIZE_ADDRESS
211 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
213 #undef TARGET_SCHED_ADJUST_COST
214 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
216 #undef TARGET_SCHED_ISSUE_RATE
217 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
219 #undef TARGET_SCHED_VARIABLE_ISSUE
220 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
222 #undef TARGET_SCHED_INIT_GLOBAL
223 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
225 #undef TARGET_SCHED_FINISH_GLOBAL
226 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
228 #undef TARGET_SCHED_INIT
229 #define TARGET_SCHED_INIT m68k_sched_md_init
231 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
232 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
234 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
235 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
237 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
238 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
239 m68k_sched_first_cycle_multipass_dfa_lookahead
241 #undef TARGET_HANDLE_OPTION
242 #define TARGET_HANDLE_OPTION m68k_handle_option
244 #undef TARGET_OPTION_OVERRIDE
245 #define TARGET_OPTION_OVERRIDE m68k_option_override
247 #undef TARGET_RTX_COSTS
248 #define TARGET_RTX_COSTS m68k_rtx_costs
250 #undef TARGET_ATTRIBUTE_TABLE
251 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
253 #undef TARGET_PROMOTE_PROTOTYPES
254 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
256 #undef TARGET_STRUCT_VALUE_RTX
257 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
259 #undef TARGET_CANNOT_FORCE_CONST_MEM
260 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
262 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
263 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
265 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
266 #undef TARGET_RETURN_IN_MEMORY
267 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
271 #undef TARGET_HAVE_TLS
272 #define TARGET_HAVE_TLS (true)
274 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
275 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
278 #undef TARGET_LEGITIMATE_ADDRESS_P
279 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
281 #undef TARGET_CAN_ELIMINATE
282 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
284 #undef TARGET_CONDITIONAL_REGISTER_USAGE
285 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
287 #undef TARGET_TRAMPOLINE_INIT
288 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
290 #undef TARGET_RETURN_POPS_ARGS
291 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
293 #undef TARGET_DELEGITIMIZE_ADDRESS
294 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
296 #undef TARGET_FUNCTION_ARG
297 #define TARGET_FUNCTION_ARG m68k_function_arg
299 #undef TARGET_FUNCTION_ARG_ADVANCE
300 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
302 static const struct attribute_spec m68k_attribute_table
[] =
304 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
305 affects_type_identity } */
306 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute
,
308 { "interrupt_handler", 0, 0, true, false, false,
309 m68k_handle_fndecl_attribute
, false },
310 { "interrupt_thread", 0, 0, true, false, false,
311 m68k_handle_fndecl_attribute
, false },
312 { NULL
, 0, 0, false, false, false, NULL
, false }
315 struct gcc_target targetm
= TARGET_INITIALIZER
;
317 /* Base flags for 68k ISAs. */
318 #define FL_FOR_isa_00 FL_ISA_68000
319 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
320 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
321 generated 68881 code for 68020 and 68030 targets unless explicitly told
323 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
324 | FL_BITFIELD | FL_68881)
325 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
326 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
328 /* Base flags for ColdFire ISAs. */
329 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
330 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
331 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
332 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
333 /* ISA_C is not upwardly compatible with ISA_B. */
334 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
338 /* Traditional 68000 instruction sets. */
344 /* ColdFire instruction set variants. */
352 /* Information about one of the -march, -mcpu or -mtune arguments. */
353 struct m68k_target_selection
355 /* The argument being described. */
358 /* For -mcpu, this is the device selected by the option.
359 For -mtune and -march, it is a representative device
360 for the microarchitecture or ISA respectively. */
361 enum target_device device
;
363 /* The M68K_DEVICE fields associated with DEVICE. See the comment
364 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
366 enum uarch_type microarch
;
371 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
372 static const struct m68k_target_selection all_devices
[] =
374 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
375 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
376 #include "m68k-devices.def"
378 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
381 /* A list of all ISAs, mapping each one to a representative device.
382 Used for -march selection. */
383 static const struct m68k_target_selection all_isas
[] =
385 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
386 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
387 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
388 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
389 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
390 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
391 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
392 { "isaa", mcf5206e
, NULL
, ucfv2
, isa_a
, (FL_FOR_isa_a
394 { "isaaplus", mcf5271
, NULL
, ucfv2
, isa_aplus
, (FL_FOR_isa_aplus
396 { "isab", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
397 { "isac", unk_device
, NULL
, ucfv4
, isa_c
, (FL_FOR_isa_c
399 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
402 /* A list of all microarchitectures, mapping each one to a representative
403 device. Used for -mtune selection. */
404 static const struct m68k_target_selection all_microarchs
[] =
406 { "68000", m68000
, NULL
, u68000
, isa_00
, FL_FOR_isa_00
},
407 { "68010", m68010
, NULL
, u68010
, isa_10
, FL_FOR_isa_10
},
408 { "68020", m68020
, NULL
, u68020
, isa_20
, FL_FOR_isa_20
},
409 { "68020-40", m68020
, NULL
, u68020_40
, isa_20
, FL_FOR_isa_20
},
410 { "68020-60", m68020
, NULL
, u68020_60
, isa_20
, FL_FOR_isa_20
},
411 { "68030", m68030
, NULL
, u68030
, isa_20
, FL_FOR_isa_20
},
412 { "68040", m68040
, NULL
, u68040
, isa_40
, FL_FOR_isa_40
},
413 { "68060", m68060
, NULL
, u68060
, isa_40
, FL_FOR_isa_40
},
414 { "cpu32", cpu32
, NULL
, ucpu32
, isa_20
, FL_FOR_isa_cpu32
},
415 { "cfv1", mcf51qe
, NULL
, ucfv1
, isa_c
, FL_FOR_isa_c
},
416 { "cfv2", mcf5206
, NULL
, ucfv2
, isa_a
, FL_FOR_isa_a
},
417 { "cfv3", mcf5307
, NULL
, ucfv3
, isa_a
, (FL_FOR_isa_a
419 { "cfv4", mcf5407
, NULL
, ucfv4
, isa_b
, FL_FOR_isa_b
},
420 { "cfv4e", mcf547x
, NULL
, ucfv4e
, isa_b
, (FL_FOR_isa_b
424 { NULL
, unk_device
, NULL
, unk_arch
, isa_max
, 0 }
427 /* The entries associated with the -mcpu, -march and -mtune settings,
428 or null for options that have not been used. */
429 const struct m68k_target_selection
*m68k_cpu_entry
;
430 const struct m68k_target_selection
*m68k_arch_entry
;
431 const struct m68k_target_selection
*m68k_tune_entry
;
433 /* Which CPU we are generating code for. */
434 enum target_device m68k_cpu
;
436 /* Which microarchitecture to tune for. */
437 enum uarch_type m68k_tune
;
439 /* Which FPU to use. */
440 enum fpu_type m68k_fpu
;
442 /* The set of FL_* flags that apply to the target processor. */
443 unsigned int m68k_cpu_flags
;
445 /* The set of FL_* flags that apply to the processor to be tuned for. */
446 unsigned int m68k_tune_flags
;
448 /* Asm templates for calling or jumping to an arbitrary symbolic address,
449 or NULL if such calls or jumps are not supported. The address is held
451 const char *m68k_symbolic_call
;
452 const char *m68k_symbolic_jump
;
454 /* Enum variable that corresponds to m68k_symbolic_call values. */
455 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var
;
458 /* See whether TABLE has an entry with name NAME. Return true and
459 store the entry in *ENTRY if so, otherwise return false and
460 leave *ENTRY alone. */
463 m68k_find_selection (const struct m68k_target_selection
**entry
,
464 const struct m68k_target_selection
*table
,
469 for (i
= 0; table
[i
].name
; i
++)
470 if (strcmp (table
[i
].name
, name
) == 0)
478 /* Implement TARGET_HANDLE_OPTION. */
481 m68k_handle_option (struct gcc_options
*opts
, struct gcc_options
*opts_set
,
482 const struct cl_decoded_option
*decoded
,
483 location_t loc ATTRIBUTE_UNUSED
)
485 size_t code
= decoded
->opt_index
;
486 const char *arg
= decoded
->arg
;
487 int value
= decoded
->value
;
489 gcc_assert (opts
== &global_options
);
490 gcc_assert (opts_set
== &global_options_set
);
495 return m68k_find_selection (&m68k_arch_entry
, all_isas
, arg
);
498 return m68k_find_selection (&m68k_cpu_entry
, all_devices
, arg
);
501 return m68k_find_selection (&m68k_tune_entry
, all_microarchs
, arg
);
504 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
506 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
509 return (m68k_find_selection (&m68k_tune_entry
, all_microarchs
,
511 && m68k_find_selection (&m68k_cpu_entry
, all_devices
, "68020"));
513 case OPT_mshared_library_id_
:
514 if (value
> MAX_LIBRARY_ID
)
515 error ("-mshared-library-id=%s is not between 0 and %d",
516 arg
, MAX_LIBRARY_ID
);
520 asprintf (&tmp
, "%d", (value
* -4) - 4);
521 m68k_library_id_string
= tmp
;
530 /* Implement TARGET_OPTION_OVERRIDE. */
533 m68k_option_override (void)
535 const struct m68k_target_selection
*entry
;
536 unsigned long target_mask
;
544 -march=ARCH should generate code that runs any processor
545 implementing architecture ARCH. -mcpu=CPU should override -march
546 and should generate code that runs on processor CPU, making free
547 use of any instructions that CPU understands. -mtune=UARCH applies
548 on top of -mcpu or -march and optimizes the code for UARCH. It does
549 not change the target architecture. */
552 /* Complain if the -march setting is for a different microarchitecture,
553 or includes flags that the -mcpu setting doesn't. */
555 && (m68k_arch_entry
->microarch
!= m68k_cpu_entry
->microarch
556 || (m68k_arch_entry
->flags
& ~m68k_cpu_entry
->flags
) != 0))
557 warning (0, "-mcpu=%s conflicts with -march=%s",
558 m68k_cpu_entry
->name
, m68k_arch_entry
->name
);
560 entry
= m68k_cpu_entry
;
563 entry
= m68k_arch_entry
;
566 entry
= all_devices
+ TARGET_CPU_DEFAULT
;
568 m68k_cpu_flags
= entry
->flags
;
570 /* Use the architecture setting to derive default values for
574 /* ColdFire is lenient about alignment. */
575 if (!TARGET_COLDFIRE
)
576 target_mask
|= MASK_STRICT_ALIGNMENT
;
578 if ((m68k_cpu_flags
& FL_BITFIELD
) != 0)
579 target_mask
|= MASK_BITFIELD
;
580 if ((m68k_cpu_flags
& FL_CF_HWDIV
) != 0)
581 target_mask
|= MASK_CF_HWDIV
;
582 if ((m68k_cpu_flags
& (FL_68881
| FL_CF_FPU
)) != 0)
583 target_mask
|= MASK_HARD_FLOAT
;
584 target_flags
|= target_mask
& ~target_flags_explicit
;
586 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
587 m68k_cpu
= entry
->device
;
590 m68k_tune
= m68k_tune_entry
->microarch
;
591 m68k_tune_flags
= m68k_tune_entry
->flags
;
593 #ifdef M68K_DEFAULT_TUNE
594 else if (!m68k_cpu_entry
&& !m68k_arch_entry
)
596 enum target_device dev
;
597 dev
= all_microarchs
[M68K_DEFAULT_TUNE
].device
;
598 m68k_tune_flags
= all_devices
[dev
]->flags
;
603 m68k_tune
= entry
->microarch
;
604 m68k_tune_flags
= entry
->flags
;
607 /* Set the type of FPU. */
608 m68k_fpu
= (!TARGET_HARD_FLOAT
? FPUTYPE_NONE
609 : (m68k_cpu_flags
& FL_COLDFIRE
) != 0 ? FPUTYPE_COLDFIRE
612 /* Sanity check to ensure that msep-data and mid-sahred-library are not
613 * both specified together. Doing so simply doesn't make sense.
615 if (TARGET_SEP_DATA
&& TARGET_ID_SHARED_LIBRARY
)
616 error ("cannot specify both -msep-data and -mid-shared-library");
618 /* If we're generating code for a separate A5 relative data segment,
619 * we've got to enable -fPIC as well. This might be relaxable to
620 * -fpic but it hasn't been tested properly.
622 if (TARGET_SEP_DATA
|| TARGET_ID_SHARED_LIBRARY
)
625 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
626 error if the target does not support them. */
627 if (TARGET_PCREL
&& !TARGET_68020
&& flag_pic
== 2)
628 error ("-mpcrel -fPIC is not currently supported on selected cpu");
630 /* ??? A historic way of turning on pic, or is this intended to
631 be an embedded thing that doesn't have the same name binding
632 significance that it does on hosted ELF systems? */
633 if (TARGET_PCREL
&& flag_pic
== 0)
638 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_JSR
;
640 m68k_symbolic_jump
= "jra %a0";
642 else if (TARGET_ID_SHARED_LIBRARY
)
643 /* All addresses must be loaded from the GOT. */
645 else if (TARGET_68020
|| TARGET_ISAB
|| TARGET_ISAC
)
648 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_C
;
650 m68k_symbolic_call_var
= M68K_SYMBOLIC_CALL_BSR_P
;
653 /* No unconditional long branch */;
654 else if (TARGET_PCREL
)
655 m68k_symbolic_jump
= "bra%.l %c0";
657 m68k_symbolic_jump
= "bra%.l %p0";
658 /* Turn off function cse if we are doing PIC. We always want
659 function call to be done as `bsr foo@PLTPC'. */
660 /* ??? It's traditional to do this for -mpcrel too, but it isn't
661 clear how intentional that is. */
662 flag_no_function_cse
= 1;
665 switch (m68k_symbolic_call_var
)
667 case M68K_SYMBOLIC_CALL_JSR
:
668 m68k_symbolic_call
= "jsr %a0";
671 case M68K_SYMBOLIC_CALL_BSR_C
:
672 m68k_symbolic_call
= "bsr%.l %c0";
675 case M68K_SYMBOLIC_CALL_BSR_P
:
676 m68k_symbolic_call
= "bsr%.l %p0";
679 case M68K_SYMBOLIC_CALL_NONE
:
680 gcc_assert (m68k_symbolic_call
== NULL
);
687 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
688 if (align_labels
> 2)
690 warning (0, "-falign-labels=%d is not supported", align_labels
);
695 warning (0, "-falign-loops=%d is not supported", align_loops
);
700 SUBTARGET_OVERRIDE_OPTIONS
;
702 /* Setup scheduling options. */
704 m68k_sched_cpu
= CPU_CFV1
;
706 m68k_sched_cpu
= CPU_CFV2
;
708 m68k_sched_cpu
= CPU_CFV3
;
710 m68k_sched_cpu
= CPU_CFV4
;
713 m68k_sched_cpu
= CPU_UNKNOWN
;
714 flag_schedule_insns
= 0;
715 flag_schedule_insns_after_reload
= 0;
716 flag_modulo_sched
= 0;
719 if (m68k_sched_cpu
!= CPU_UNKNOWN
)
721 if ((m68k_cpu_flags
& (FL_CF_EMAC
| FL_CF_EMAC_B
)) != 0)
722 m68k_sched_mac
= MAC_CF_EMAC
;
723 else if ((m68k_cpu_flags
& FL_CF_MAC
) != 0)
724 m68k_sched_mac
= MAC_CF_MAC
;
726 m68k_sched_mac
= MAC_NO
;
730 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
731 given argument and NAME is the argument passed to -mcpu. Return NULL
732 if -mcpu was not passed. */
735 m68k_cpp_cpu_ident (const char *prefix
)
739 return concat ("__m", prefix
, "_cpu_", m68k_cpu_entry
->name
, NULL
);
742 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
743 given argument and NAME is the name of the representative device for
744 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
747 m68k_cpp_cpu_family (const char *prefix
)
751 return concat ("__m", prefix
, "_family_", m68k_cpu_entry
->family
, NULL
);
754 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
755 "interrupt_handler" attribute and interrupt_thread if FUNC has an
756 "interrupt_thread" attribute. Otherwise, return
757 m68k_fk_normal_function. */
759 enum m68k_function_kind
760 m68k_get_function_kind (tree func
)
764 gcc_assert (TREE_CODE (func
) == FUNCTION_DECL
);
766 a
= lookup_attribute ("interrupt", DECL_ATTRIBUTES (func
));
768 return m68k_fk_interrupt_handler
;
770 a
= lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func
));
772 return m68k_fk_interrupt_handler
;
774 a
= lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func
));
776 return m68k_fk_interrupt_thread
;
778 return m68k_fk_normal_function
;
781 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
782 struct attribute_spec.handler. */
784 m68k_handle_fndecl_attribute (tree
*node
, tree name
,
785 tree args ATTRIBUTE_UNUSED
,
786 int flags ATTRIBUTE_UNUSED
,
789 if (TREE_CODE (*node
) != FUNCTION_DECL
)
791 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
793 *no_add_attrs
= true;
796 if (m68k_get_function_kind (*node
) != m68k_fk_normal_function
)
798 error ("multiple interrupt attributes not allowed");
799 *no_add_attrs
= true;
803 && !strcmp (IDENTIFIER_POINTER (name
), "interrupt_thread"))
805 error ("interrupt_thread is available only on fido");
806 *no_add_attrs
= true;
813 m68k_compute_frame_layout (void)
817 enum m68k_function_kind func_kind
=
818 m68k_get_function_kind (current_function_decl
);
819 bool interrupt_handler
= func_kind
== m68k_fk_interrupt_handler
;
820 bool interrupt_thread
= func_kind
== m68k_fk_interrupt_thread
;
822 /* Only compute the frame once per function.
823 Don't cache information until reload has been completed. */
824 if (current_frame
.funcdef_no
== current_function_funcdef_no
828 current_frame
.size
= (get_frame_size () + 3) & -4;
832 /* Interrupt thread does not need to save any register. */
833 if (!interrupt_thread
)
834 for (regno
= 0; regno
< 16; regno
++)
835 if (m68k_save_reg (regno
, interrupt_handler
))
837 mask
|= 1 << (regno
- D0_REG
);
840 current_frame
.offset
= saved
* 4;
841 current_frame
.reg_no
= saved
;
842 current_frame
.reg_mask
= mask
;
844 current_frame
.foffset
= 0;
846 if (TARGET_HARD_FLOAT
)
848 /* Interrupt thread does not need to save any register. */
849 if (!interrupt_thread
)
850 for (regno
= 16; regno
< 24; regno
++)
851 if (m68k_save_reg (regno
, interrupt_handler
))
853 mask
|= 1 << (regno
- FP0_REG
);
856 current_frame
.foffset
= saved
* TARGET_FP_REG_SIZE
;
857 current_frame
.offset
+= current_frame
.foffset
;
859 current_frame
.fpu_no
= saved
;
860 current_frame
.fpu_mask
= mask
;
862 /* Remember what function this frame refers to. */
863 current_frame
.funcdef_no
= current_function_funcdef_no
;
866 /* Worker function for TARGET_CAN_ELIMINATE. */
869 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
871 return (to
== STACK_POINTER_REGNUM
? ! frame_pointer_needed
: true);
875 m68k_initial_elimination_offset (int from
, int to
)
878 /* The arg pointer points 8 bytes before the start of the arguments,
879 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
880 frame pointer in most frames. */
881 argptr_offset
= frame_pointer_needed
? 0 : UNITS_PER_WORD
;
882 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
883 return argptr_offset
;
885 m68k_compute_frame_layout ();
887 gcc_assert (to
== STACK_POINTER_REGNUM
);
890 case ARG_POINTER_REGNUM
:
891 return current_frame
.offset
+ current_frame
.size
- argptr_offset
;
892 case FRAME_POINTER_REGNUM
:
893 return current_frame
.offset
+ current_frame
.size
;
899 /* Refer to the array `regs_ever_live' to determine which registers
900 to save; `regs_ever_live[I]' is nonzero if register number I
901 is ever used in the function. This function is responsible for
902 knowing which registers should not be saved even if used.
903 Return true if we need to save REGNO. */
906 m68k_save_reg (unsigned int regno
, bool interrupt_handler
)
908 if (flag_pic
&& regno
== PIC_REG
)
910 if (crtl
->saves_all_registers
)
912 if (crtl
->uses_pic_offset_table
)
914 /* Reload may introduce constant pool references into a function
915 that thitherto didn't need a PIC register. Note that the test
916 above will not catch that case because we will only set
917 crtl->uses_pic_offset_table when emitting
918 the address reloads. */
919 if (crtl
->uses_const_pool
)
923 if (crtl
->calls_eh_return
)
928 unsigned int test
= EH_RETURN_DATA_REGNO (i
);
929 if (test
== INVALID_REGNUM
)
936 /* Fixed regs we never touch. */
937 if (fixed_regs
[regno
])
940 /* The frame pointer (if it is such) is handled specially. */
941 if (regno
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
944 /* Interrupt handlers must also save call_used_regs
945 if they are live or when calling nested functions. */
946 if (interrupt_handler
)
948 if (df_regs_ever_live_p (regno
))
951 if (!current_function_is_leaf
&& call_used_regs
[regno
])
955 /* Never need to save registers that aren't touched. */
956 if (!df_regs_ever_live_p (regno
))
959 /* Otherwise save everything that isn't call-clobbered. */
960 return !call_used_regs
[regno
];
963 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
964 the lowest memory address. COUNT is the number of registers to be
965 moved, with register REGNO + I being moved if bit I of MASK is set.
966 STORE_P specifies the direction of the move and ADJUST_STACK_P says
967 whether or not this is pre-decrement (if STORE_P) or post-increment
968 (if !STORE_P) operation. */
971 m68k_emit_movem (rtx base
, HOST_WIDE_INT offset
,
972 unsigned int count
, unsigned int regno
,
973 unsigned int mask
, bool store_p
, bool adjust_stack_p
)
976 rtx body
, addr
, src
, operands
[2];
977 enum machine_mode mode
;
979 body
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (adjust_stack_p
+ count
));
980 mode
= reg_raw_mode
[regno
];
985 src
= plus_constant (base
, (count
986 * GET_MODE_SIZE (mode
)
987 * (HOST_WIDE_INT
) (store_p
? -1 : 1)));
988 XVECEXP (body
, 0, i
++) = gen_rtx_SET (VOIDmode
, base
, src
);
991 for (; mask
!= 0; mask
>>= 1, regno
++)
994 addr
= plus_constant (base
, offset
);
995 operands
[!store_p
] = gen_frame_mem (mode
, addr
);
996 operands
[store_p
] = gen_rtx_REG (mode
, regno
);
997 XVECEXP (body
, 0, i
++)
998 = gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]);
999 offset
+= GET_MODE_SIZE (mode
);
1001 gcc_assert (i
== XVECLEN (body
, 0));
1003 return emit_insn (body
);
1006 /* Make INSN a frame-related instruction. */
1009 m68k_set_frame_related (rtx insn
)
1014 RTX_FRAME_RELATED_P (insn
) = 1;
1015 body
= PATTERN (insn
);
1016 if (GET_CODE (body
) == PARALLEL
)
1017 for (i
= 0; i
< XVECLEN (body
, 0); i
++)
1018 RTX_FRAME_RELATED_P (XVECEXP (body
, 0, i
)) = 1;
1021 /* Emit RTL for the "prologue" define_expand. */
1024 m68k_expand_prologue (void)
1026 HOST_WIDE_INT fsize_with_regs
;
1027 rtx limit
, src
, dest
;
1029 m68k_compute_frame_layout ();
1031 /* If the stack limit is a symbol, we can check it here,
1032 before actually allocating the space. */
1033 if (crtl
->limit_stack
1034 && GET_CODE (stack_limit_rtx
) == SYMBOL_REF
)
1036 limit
= plus_constant (stack_limit_rtx
, current_frame
.size
+ 4);
1037 if (!LEGITIMATE_CONSTANT_P (limit
))
1039 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), limit
);
1040 limit
= gen_rtx_REG (Pmode
, D0_REG
);
1042 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
,
1043 stack_pointer_rtx
, limit
),
1044 stack_pointer_rtx
, limit
,
1048 fsize_with_regs
= current_frame
.size
;
1049 if (TARGET_COLDFIRE
)
1051 /* ColdFire's move multiple instructions do not allow pre-decrement
1052 addressing. Add the size of movem saves to the initial stack
1053 allocation instead. */
1054 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1055 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1056 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1057 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1060 if (frame_pointer_needed
)
1062 if (fsize_with_regs
== 0 && TUNE_68040
)
1064 /* On the 68040, two separate moves are faster than link.w 0. */
1065 dest
= gen_frame_mem (Pmode
,
1066 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1067 m68k_set_frame_related (emit_move_insn (dest
, frame_pointer_rtx
));
1068 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx
,
1069 stack_pointer_rtx
));
1071 else if (fsize_with_regs
< 0x8000 || TARGET_68020
)
1072 m68k_set_frame_related
1073 (emit_insn (gen_link (frame_pointer_rtx
,
1074 GEN_INT (-4 - fsize_with_regs
))));
1077 m68k_set_frame_related
1078 (emit_insn (gen_link (frame_pointer_rtx
, GEN_INT (-4))));
1079 m68k_set_frame_related
1080 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1082 GEN_INT (-fsize_with_regs
))));
1085 /* If the frame pointer is needed, emit a special barrier that
1086 will prevent the scheduler from moving stores to the frame
1087 before the stack adjustment. */
1088 emit_insn (gen_stack_tie (stack_pointer_rtx
, frame_pointer_rtx
));
1090 else if (fsize_with_regs
!= 0)
1091 m68k_set_frame_related
1092 (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1094 GEN_INT (-fsize_with_regs
))));
1096 if (current_frame
.fpu_mask
)
1098 gcc_assert (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
);
1100 m68k_set_frame_related
1101 (m68k_emit_movem (stack_pointer_rtx
,
1102 current_frame
.fpu_no
* -GET_MODE_SIZE (XFmode
),
1103 current_frame
.fpu_no
, FP0_REG
,
1104 current_frame
.fpu_mask
, true, true));
1109 /* If we're using moveml to save the integer registers,
1110 the stack pointer will point to the bottom of the moveml
1111 save area. Find the stack offset of the first FP register. */
1112 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1115 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1116 m68k_set_frame_related
1117 (m68k_emit_movem (stack_pointer_rtx
, offset
,
1118 current_frame
.fpu_no
, FP0_REG
,
1119 current_frame
.fpu_mask
, true, false));
1123 /* If the stack limit is not a symbol, check it here.
1124 This has the disadvantage that it may be too late... */
1125 if (crtl
->limit_stack
)
1127 if (REG_P (stack_limit_rtx
))
1128 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode
, stack_pointer_rtx
,
1130 stack_pointer_rtx
, stack_limit_rtx
,
1133 else if (GET_CODE (stack_limit_rtx
) != SYMBOL_REF
)
1134 warning (0, "stack limit expression is not supported");
1137 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1139 /* Store each register separately in the same order moveml does. */
1142 for (i
= 16; i
-- > 0; )
1143 if (current_frame
.reg_mask
& (1 << i
))
1145 src
= gen_rtx_REG (SImode
, D0_REG
+ i
);
1146 dest
= gen_frame_mem (SImode
,
1147 gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
));
1148 m68k_set_frame_related (emit_insn (gen_movsi (dest
, src
)));
1153 if (TARGET_COLDFIRE
)
1154 /* The required register save space has already been allocated.
1155 The first register should be stored at (%sp). */
1156 m68k_set_frame_related
1157 (m68k_emit_movem (stack_pointer_rtx
, 0,
1158 current_frame
.reg_no
, D0_REG
,
1159 current_frame
.reg_mask
, true, false));
1161 m68k_set_frame_related
1162 (m68k_emit_movem (stack_pointer_rtx
,
1163 current_frame
.reg_no
* -GET_MODE_SIZE (SImode
),
1164 current_frame
.reg_no
, D0_REG
,
1165 current_frame
.reg_mask
, true, true));
1168 if (!TARGET_SEP_DATA
1169 && crtl
->uses_pic_offset_table
)
1170 emit_insn (gen_load_got (pic_offset_table_rtx
));
1173 /* Return true if a simple (return) instruction is sufficient for this
1174 instruction (i.e. if no epilogue is needed). */
1177 m68k_use_return_insn (void)
1179 if (!reload_completed
|| frame_pointer_needed
|| get_frame_size () != 0)
1182 m68k_compute_frame_layout ();
1183 return current_frame
.offset
== 0;
1186 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1187 SIBCALL_P says which.
1189 The function epilogue should not depend on the current stack pointer!
1190 It should use the frame pointer only, if there is a frame pointer.
1191 This is mandatory because of alloca; we also take advantage of it to
1192 omit stack adjustments before returning. */
1195 m68k_expand_epilogue (bool sibcall_p
)
1197 HOST_WIDE_INT fsize
, fsize_with_regs
;
1198 bool big
, restore_from_sp
;
1200 m68k_compute_frame_layout ();
1202 fsize
= current_frame
.size
;
1204 restore_from_sp
= false;
1206 /* FIXME : current_function_is_leaf below is too strong.
1207 What we really need to know there is if there could be pending
1208 stack adjustment needed at that point. */
1209 restore_from_sp
= (!frame_pointer_needed
1210 || (!cfun
->calls_alloca
1211 && current_function_is_leaf
));
1213 /* fsize_with_regs is the size we need to adjust the sp when
1214 popping the frame. */
1215 fsize_with_regs
= fsize
;
1216 if (TARGET_COLDFIRE
&& restore_from_sp
)
1218 /* ColdFire's move multiple instructions do not allow post-increment
1219 addressing. Add the size of movem loads to the final deallocation
1221 if (current_frame
.reg_no
>= MIN_MOVEM_REGS
)
1222 fsize_with_regs
+= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1223 if (current_frame
.fpu_no
>= MIN_FMOVEM_REGS
)
1224 fsize_with_regs
+= current_frame
.fpu_no
* GET_MODE_SIZE (DFmode
);
1227 if (current_frame
.offset
+ fsize
>= 0x8000
1229 && (current_frame
.reg_mask
|| current_frame
.fpu_mask
))
1232 && (current_frame
.reg_no
>= MIN_MOVEM_REGS
1233 || current_frame
.fpu_no
>= MIN_FMOVEM_REGS
))
1235 /* ColdFire's move multiple instructions do not support the
1236 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1237 stack-based restore. */
1238 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
),
1239 GEN_INT (-(current_frame
.offset
+ fsize
)));
1240 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1241 gen_rtx_REG (Pmode
, A1_REG
),
1242 frame_pointer_rtx
));
1243 restore_from_sp
= true;
1247 emit_move_insn (gen_rtx_REG (Pmode
, A1_REG
), GEN_INT (-fsize
));
1253 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1255 /* Restore each register separately in the same order moveml does. */
1257 HOST_WIDE_INT offset
;
1259 offset
= current_frame
.offset
+ fsize
;
1260 for (i
= 0; i
< 16; i
++)
1261 if (current_frame
.reg_mask
& (1 << i
))
1267 /* Generate the address -OFFSET(%fp,%a1.l). */
1268 addr
= gen_rtx_REG (Pmode
, A1_REG
);
1269 addr
= gen_rtx_PLUS (Pmode
, addr
, frame_pointer_rtx
);
1270 addr
= plus_constant (addr
, -offset
);
1272 else if (restore_from_sp
)
1273 addr
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
1275 addr
= plus_constant (frame_pointer_rtx
, -offset
);
1276 emit_move_insn (gen_rtx_REG (SImode
, D0_REG
+ i
),
1277 gen_frame_mem (SImode
, addr
));
1278 offset
-= GET_MODE_SIZE (SImode
);
1281 else if (current_frame
.reg_mask
)
1284 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1285 gen_rtx_REG (Pmode
, A1_REG
),
1287 -(current_frame
.offset
+ fsize
),
1288 current_frame
.reg_no
, D0_REG
,
1289 current_frame
.reg_mask
, false, false);
1290 else if (restore_from_sp
)
1291 m68k_emit_movem (stack_pointer_rtx
, 0,
1292 current_frame
.reg_no
, D0_REG
,
1293 current_frame
.reg_mask
, false,
1296 m68k_emit_movem (frame_pointer_rtx
,
1297 -(current_frame
.offset
+ fsize
),
1298 current_frame
.reg_no
, D0_REG
,
1299 current_frame
.reg_mask
, false, false);
1302 if (current_frame
.fpu_no
> 0)
1305 m68k_emit_movem (gen_rtx_PLUS (Pmode
,
1306 gen_rtx_REG (Pmode
, A1_REG
),
1308 -(current_frame
.foffset
+ fsize
),
1309 current_frame
.fpu_no
, FP0_REG
,
1310 current_frame
.fpu_mask
, false, false);
1311 else if (restore_from_sp
)
1313 if (TARGET_COLDFIRE
)
1317 /* If we used moveml to restore the integer registers, the
1318 stack pointer will still point to the bottom of the moveml
1319 save area. Find the stack offset of the first FP
1321 if (current_frame
.reg_no
< MIN_MOVEM_REGS
)
1324 offset
= current_frame
.reg_no
* GET_MODE_SIZE (SImode
);
1325 m68k_emit_movem (stack_pointer_rtx
, offset
,
1326 current_frame
.fpu_no
, FP0_REG
,
1327 current_frame
.fpu_mask
, false, false);
1330 m68k_emit_movem (stack_pointer_rtx
, 0,
1331 current_frame
.fpu_no
, FP0_REG
,
1332 current_frame
.fpu_mask
, false, true);
1335 m68k_emit_movem (frame_pointer_rtx
,
1336 -(current_frame
.foffset
+ fsize
),
1337 current_frame
.fpu_no
, FP0_REG
,
1338 current_frame
.fpu_mask
, false, false);
1341 if (frame_pointer_needed
)
1342 emit_insn (gen_unlink (frame_pointer_rtx
));
1343 else if (fsize_with_regs
)
1344 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1346 GEN_INT (fsize_with_regs
)));
1348 if (crtl
->calls_eh_return
)
1349 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1351 EH_RETURN_STACKADJ_RTX
));
1354 emit_jump_insn (gen_rtx_RETURN (VOIDmode
));
1357 /* Return true if X is a valid comparison operator for the dbcc
1360 Note it rejects floating point comparison operators.
1361 (In the future we could use Fdbcc).
1363 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1366 valid_dbcc_comparison_p_2 (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1368 switch (GET_CODE (x
))
1370 case EQ
: case NE
: case GTU
: case LTU
:
1374 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1376 case GT
: case LT
: case GE
: case LE
:
1377 return ! (cc_prev_status
.flags
& CC_NO_OVERFLOW
);
1383 /* Return nonzero if flags are currently in the 68881 flag register. */
1385 flags_in_68881 (void)
1387 /* We could add support for these in the future */
1388 return cc_status
.flags
& CC_IN_68881
;
1391 /* Return true if PARALLEL contains register REGNO. */
1393 m68k_reg_present_p (const_rtx parallel
, unsigned int regno
)
1397 if (REG_P (parallel
) && REGNO (parallel
) == regno
)
1400 if (GET_CODE (parallel
) != PARALLEL
)
1403 for (i
= 0; i
< XVECLEN (parallel
, 0); ++i
)
1407 x
= XEXP (XVECEXP (parallel
, 0, i
), 0);
1408 if (REG_P (x
) && REGNO (x
) == regno
)
1415 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1418 m68k_ok_for_sibcall_p (tree decl
, tree exp
)
1420 enum m68k_function_kind kind
;
1422 /* We cannot use sibcalls for nested functions because we use the
1423 static chain register for indirect calls. */
1424 if (CALL_EXPR_STATIC_CHAIN (exp
))
1427 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun
->decl
))))
1429 /* Check that the return value locations are the same. For
1430 example that we aren't returning a value from the sibling in
1431 a D0 register but then need to transfer it to a A0 register. */
1435 cfun_value
= FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun
->decl
)),
1437 call_value
= FUNCTION_VALUE (TREE_TYPE (exp
), decl
);
1439 /* Check that the values are equal or that the result the callee
1440 function returns is superset of what the current function returns. */
1441 if (!(rtx_equal_p (cfun_value
, call_value
)
1442 || (REG_P (cfun_value
)
1443 && m68k_reg_present_p (call_value
, REGNO (cfun_value
)))))
1447 kind
= m68k_get_function_kind (current_function_decl
);
1448 if (kind
== m68k_fk_normal_function
)
1449 /* We can always sibcall from a normal function, because it's
1450 undefined if it is calling an interrupt function. */
1453 /* Otherwise we can only sibcall if the function kind is known to be
1455 if (decl
&& m68k_get_function_kind (decl
) == kind
)
1461 /* On the m68k all args are always pushed. */
1464 m68k_function_arg (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
1465 enum machine_mode mode ATTRIBUTE_UNUSED
,
1466 const_tree type ATTRIBUTE_UNUSED
,
1467 bool named ATTRIBUTE_UNUSED
)
1473 m68k_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1474 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1476 *cum
+= (mode
!= BLKmode
1477 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1478 : (int_size_in_bytes (type
) + 3) & ~3);
1481 /* Convert X to a legitimate function call memory reference and return the
1485 m68k_legitimize_call_address (rtx x
)
1487 gcc_assert (MEM_P (x
));
1488 if (call_operand (XEXP (x
, 0), VOIDmode
))
1490 return replace_equiv_address (x
, force_reg (Pmode
, XEXP (x
, 0)));
1493 /* Likewise for sibling calls. */
1496 m68k_legitimize_sibcall_address (rtx x
)
1498 gcc_assert (MEM_P (x
));
1499 if (sibcall_operand (XEXP (x
, 0), VOIDmode
))
1502 emit_move_insn (gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
), XEXP (x
, 0));
1503 return replace_equiv_address (x
, gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
));
1506 /* Convert X to a legitimate address and return it if successful. Otherwise
1509 For the 68000, we handle X+REG by loading X into a register R and
1510 using R+REG. R will go in an address reg and indexing will be used.
1511 However, if REG is a broken-out memory address or multiplication,
1512 nothing needs to be done because REG can certainly go in an address reg. */
1515 m68k_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
1517 if (m68k_tls_symbol_p (x
))
1518 return m68k_legitimize_tls_address (x
);
1520 if (GET_CODE (x
) == PLUS
)
1522 int ch
= (x
) != (oldx
);
1525 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1527 if (GET_CODE (XEXP (x
, 0)) == MULT
)
1530 XEXP (x
, 0) = force_operand (XEXP (x
, 0), 0);
1532 if (GET_CODE (XEXP (x
, 1)) == MULT
)
1535 XEXP (x
, 1) = force_operand (XEXP (x
, 1), 0);
1539 if (GET_CODE (XEXP (x
, 1)) == REG
1540 && GET_CODE (XEXP (x
, 0)) == REG
)
1542 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
1545 x
= force_operand (x
, 0);
1549 if (memory_address_p (mode
, x
))
1552 if (GET_CODE (XEXP (x
, 0)) == REG
1553 || (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
1554 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
1555 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
))
1557 rtx temp
= gen_reg_rtx (Pmode
);
1558 rtx val
= force_operand (XEXP (x
, 1), 0);
1559 emit_move_insn (temp
, val
);
1562 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1563 && GET_CODE (XEXP (x
, 0)) == REG
)
1564 x
= force_operand (x
, 0);
1566 else if (GET_CODE (XEXP (x
, 1)) == REG
1567 || (GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
1568 && GET_CODE (XEXP (XEXP (x
, 1), 0)) == REG
1569 && GET_MODE (XEXP (XEXP (x
, 1), 0)) == HImode
))
1571 rtx temp
= gen_reg_rtx (Pmode
);
1572 rtx val
= force_operand (XEXP (x
, 0), 0);
1573 emit_move_insn (temp
, val
);
1576 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
1577 && GET_CODE (XEXP (x
, 1)) == REG
)
1578 x
= force_operand (x
, 0);
1586 /* Output a dbCC; jCC sequence. Note we do not handle the
1587 floating point version of this sequence (Fdbcc). We also
1588 do not handle alternative conditions when CC_NO_OVERFLOW is
1589 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1590 kick those out before we get here. */
1593 output_dbcc_and_branch (rtx
*operands
)
1595 switch (GET_CODE (operands
[3]))
1598 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands
);
1602 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands
);
1606 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands
);
1610 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands
);
1614 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands
);
1618 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands
);
1622 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands
);
1626 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands
);
1630 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands
);
1634 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands
);
1641 /* If the decrement is to be done in SImode, then we have
1642 to compensate for the fact that dbcc decrements in HImode. */
1643 switch (GET_MODE (operands
[0]))
1646 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands
);
1658 output_scc_di (rtx op
, rtx operand1
, rtx operand2
, rtx dest
)
1661 enum rtx_code op_code
= GET_CODE (op
);
1663 /* This does not produce a useful cc. */
1666 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1667 below. Swap the operands and change the op if these requirements
1668 are not fulfilled. */
1669 if (GET_CODE (operand2
) == REG
&& GET_CODE (operand1
) != REG
)
1673 operand1
= operand2
;
1675 op_code
= swap_condition (op_code
);
1677 loperands
[0] = operand1
;
1678 if (GET_CODE (operand1
) == REG
)
1679 loperands
[1] = gen_rtx_REG (SImode
, REGNO (operand1
) + 1);
1681 loperands
[1] = adjust_address (operand1
, SImode
, 4);
1682 if (operand2
!= const0_rtx
)
1684 loperands
[2] = operand2
;
1685 if (GET_CODE (operand2
) == REG
)
1686 loperands
[3] = gen_rtx_REG (SImode
, REGNO (operand2
) + 1);
1688 loperands
[3] = adjust_address (operand2
, SImode
, 4);
1690 loperands
[4] = gen_label_rtx ();
1691 if (operand2
!= const0_rtx
)
1692 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands
);
1695 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[0]))
1696 output_asm_insn ("tst%.l %0", loperands
);
1698 output_asm_insn ("cmp%.w #0,%0", loperands
);
1700 output_asm_insn ("jne %l4", loperands
);
1702 if (TARGET_68020
|| TARGET_COLDFIRE
|| ! ADDRESS_REG_P (loperands
[1]))
1703 output_asm_insn ("tst%.l %1", loperands
);
1705 output_asm_insn ("cmp%.w #0,%1", loperands
);
1708 loperands
[5] = dest
;
1713 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1714 CODE_LABEL_NUMBER (loperands
[4]));
1715 output_asm_insn ("seq %5", loperands
);
1719 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1720 CODE_LABEL_NUMBER (loperands
[4]));
1721 output_asm_insn ("sne %5", loperands
);
1725 loperands
[6] = gen_label_rtx ();
1726 output_asm_insn ("shi %5\n\tjra %l6", loperands
);
1727 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1728 CODE_LABEL_NUMBER (loperands
[4]));
1729 output_asm_insn ("sgt %5", loperands
);
1730 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1731 CODE_LABEL_NUMBER (loperands
[6]));
1735 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1736 CODE_LABEL_NUMBER (loperands
[4]));
1737 output_asm_insn ("shi %5", loperands
);
1741 loperands
[6] = gen_label_rtx ();
1742 output_asm_insn ("scs %5\n\tjra %l6", loperands
);
1743 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1744 CODE_LABEL_NUMBER (loperands
[4]));
1745 output_asm_insn ("slt %5", loperands
);
1746 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1747 CODE_LABEL_NUMBER (loperands
[6]));
1751 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1752 CODE_LABEL_NUMBER (loperands
[4]));
1753 output_asm_insn ("scs %5", loperands
);
1757 loperands
[6] = gen_label_rtx ();
1758 output_asm_insn ("scc %5\n\tjra %l6", loperands
);
1759 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1760 CODE_LABEL_NUMBER (loperands
[4]));
1761 output_asm_insn ("sge %5", loperands
);
1762 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1763 CODE_LABEL_NUMBER (loperands
[6]));
1767 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1768 CODE_LABEL_NUMBER (loperands
[4]));
1769 output_asm_insn ("scc %5", loperands
);
1773 loperands
[6] = gen_label_rtx ();
1774 output_asm_insn ("sls %5\n\tjra %l6", loperands
);
1775 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1776 CODE_LABEL_NUMBER (loperands
[4]));
1777 output_asm_insn ("sle %5", loperands
);
1778 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1779 CODE_LABEL_NUMBER (loperands
[6]));
1783 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L",
1784 CODE_LABEL_NUMBER (loperands
[4]));
1785 output_asm_insn ("sls %5", loperands
);
1795 output_btst (rtx
*operands
, rtx countop
, rtx dataop
, rtx insn
, int signpos
)
1797 operands
[0] = countop
;
1798 operands
[1] = dataop
;
1800 if (GET_CODE (countop
) == CONST_INT
)
1802 register int count
= INTVAL (countop
);
1803 /* If COUNT is bigger than size of storage unit in use,
1804 advance to the containing unit of same size. */
1805 if (count
> signpos
)
1807 int offset
= (count
& ~signpos
) / 8;
1808 count
= count
& signpos
;
1809 operands
[1] = dataop
= adjust_address (dataop
, QImode
, offset
);
1811 if (count
== signpos
)
1812 cc_status
.flags
= CC_NOT_POSITIVE
| CC_Z_IN_NOT_N
;
1814 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
;
1816 /* These three statements used to use next_insns_test_no...
1817 but it appears that this should do the same job. */
1819 && next_insn_tests_no_inequality (insn
))
1822 && next_insn_tests_no_inequality (insn
))
1825 && next_insn_tests_no_inequality (insn
))
1827 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1828 On some m68k variants unfortunately that's slower than btst.
1829 On 68000 and higher, that should also work for all HImode operands. */
1830 if (TUNE_CPU32
|| TARGET_COLDFIRE
|| optimize_size
)
1832 if (count
== 3 && DATA_REG_P (operands
[1])
1833 && next_insn_tests_no_inequality (insn
))
1835 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_Z_IN_NOT_N
| CC_NO_OVERFLOW
;
1836 return "move%.w %1,%%ccr";
1838 if (count
== 2 && DATA_REG_P (operands
[1])
1839 && next_insn_tests_no_inequality (insn
))
1841 cc_status
.flags
= CC_NOT_NEGATIVE
| CC_INVERTED
| CC_NO_OVERFLOW
;
1842 return "move%.w %1,%%ccr";
1844 /* count == 1 followed by bvc/bvs and
1845 count == 0 followed by bcc/bcs are also possible, but need
1846 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1849 cc_status
.flags
= CC_NOT_NEGATIVE
;
1851 return "btst %0,%1";
1854 /* Return true if X is a legitimate base register. STRICT_P says
1855 whether we need strict checking. */
1858 m68k_legitimate_base_reg_p (rtx x
, bool strict_p
)
1860 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1861 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1866 ? REGNO_OK_FOR_BASE_P (REGNO (x
))
1867 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x
))));
1870 /* Return true if X is a legitimate index register. STRICT_P says
1871 whether we need strict checking. */
1874 m68k_legitimate_index_reg_p (rtx x
, bool strict_p
)
1876 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
1881 ? REGNO_OK_FOR_INDEX_P (REGNO (x
))
1882 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x
))));
1885 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1886 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1887 ADDRESS if so. STRICT_P says whether we need strict checking. */
1890 m68k_decompose_index (rtx x
, bool strict_p
, struct m68k_address
*address
)
1894 /* Check for a scale factor. */
1896 if ((TARGET_68020
|| TARGET_COLDFIRE
)
1897 && GET_CODE (x
) == MULT
1898 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1899 && (INTVAL (XEXP (x
, 1)) == 2
1900 || INTVAL (XEXP (x
, 1)) == 4
1901 || (INTVAL (XEXP (x
, 1)) == 8
1902 && (TARGET_COLDFIRE_FPU
|| !TARGET_COLDFIRE
))))
1904 scale
= INTVAL (XEXP (x
, 1));
1908 /* Check for a word extension. */
1909 if (!TARGET_COLDFIRE
1910 && GET_CODE (x
) == SIGN_EXTEND
1911 && GET_MODE (XEXP (x
, 0)) == HImode
)
1914 if (m68k_legitimate_index_reg_p (x
, strict_p
))
1916 address
->scale
= scale
;
1924 /* Return true if X is an illegitimate symbolic constant. */
1927 m68k_illegitimate_symbolic_constant_p (rtx x
)
1931 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
)
1933 split_const (x
, &base
, &offset
);
1934 if (GET_CODE (base
) == SYMBOL_REF
1935 && !offset_within_block_p (base
, INTVAL (offset
)))
1938 return m68k_tls_reference_p (x
, false);
1941 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1944 m68k_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1946 return m68k_illegitimate_symbolic_constant_p (x
);
1949 /* Return true if X is a legitimate constant address that can reach
1950 bytes in the range [X, X + REACH). STRICT_P says whether we need
1954 m68k_legitimate_constant_address_p (rtx x
, unsigned int reach
, bool strict_p
)
1958 if (!CONSTANT_ADDRESS_P (x
))
1962 && !(strict_p
&& TARGET_PCREL
)
1963 && symbolic_operand (x
, VOIDmode
))
1966 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P
&& reach
> 1)
1968 split_const (x
, &base
, &offset
);
1969 if (GET_CODE (base
) == SYMBOL_REF
1970 && !offset_within_block_p (base
, INTVAL (offset
) + reach
- 1))
1974 return !m68k_tls_reference_p (x
, false);
1977 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1978 labels will become jump tables. */
1981 m68k_jump_table_ref_p (rtx x
)
1983 if (GET_CODE (x
) != LABEL_REF
)
1987 if (!NEXT_INSN (x
) && !PREV_INSN (x
))
1990 x
= next_nonnote_insn (x
);
1991 return x
&& JUMP_TABLE_DATA_P (x
);
1994 /* Return true if X is a legitimate address for values of mode MODE.
1995 STRICT_P says whether strict checking is needed. If the address
1996 is valid, describe its components in *ADDRESS. */
1999 m68k_decompose_address (enum machine_mode mode
, rtx x
,
2000 bool strict_p
, struct m68k_address
*address
)
2004 memset (address
, 0, sizeof (*address
));
2006 if (mode
== BLKmode
)
2009 reach
= GET_MODE_SIZE (mode
);
2011 /* Check for (An) (mode 2). */
2012 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2018 /* Check for -(An) and (An)+ (modes 3 and 4). */
2019 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
2020 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2022 address
->code
= GET_CODE (x
);
2023 address
->base
= XEXP (x
, 0);
2027 /* Check for (d16,An) (mode 5). */
2028 if (GET_CODE (x
) == PLUS
2029 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2030 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x8000, 0x8000 - reach
)
2031 && m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
))
2033 address
->base
= XEXP (x
, 0);
2034 address
->offset
= XEXP (x
, 1);
2038 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2039 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2041 if (GET_CODE (x
) == PLUS
2042 && XEXP (x
, 0) == pic_offset_table_rtx
)
2044 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2045 they are invalid in this context. */
2046 if (m68k_unwrap_symbol (XEXP (x
, 1), false) != XEXP (x
, 1))
2048 address
->base
= XEXP (x
, 0);
2049 address
->offset
= XEXP (x
, 1);
2054 /* The ColdFire FPU only accepts addressing modes 2-5. */
2055 if (TARGET_COLDFIRE_FPU
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2058 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2059 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2060 All these modes are variations of mode 7. */
2061 if (m68k_legitimate_constant_address_p (x
, reach
, strict_p
))
2063 address
->offset
= x
;
2067 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2070 ??? do_tablejump creates these addresses before placing the target
2071 label, so we have to assume that unplaced labels are jump table
2072 references. It seems unlikely that we would ever generate indexed
2073 accesses to unplaced labels in other cases. */
2074 if (GET_CODE (x
) == PLUS
2075 && m68k_jump_table_ref_p (XEXP (x
, 1))
2076 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2078 address
->offset
= XEXP (x
, 1);
2082 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2083 (bd,An,Xn.SIZE*SCALE) addresses. */
2087 /* Check for a nonzero base displacement. */
2088 if (GET_CODE (x
) == PLUS
2089 && m68k_legitimate_constant_address_p (XEXP (x
, 1), reach
, strict_p
))
2091 address
->offset
= XEXP (x
, 1);
2095 /* Check for a suppressed index register. */
2096 if (m68k_legitimate_base_reg_p (x
, strict_p
))
2102 /* Check for a suppressed base register. Do not allow this case
2103 for non-symbolic offsets as it effectively gives gcc freedom
2104 to treat data registers as base registers, which can generate
2107 && symbolic_operand (address
->offset
, VOIDmode
)
2108 && m68k_decompose_index (x
, strict_p
, address
))
2113 /* Check for a nonzero base displacement. */
2114 if (GET_CODE (x
) == PLUS
2115 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2116 && IN_RANGE (INTVAL (XEXP (x
, 1)), -0x80, 0x80 - reach
))
2118 address
->offset
= XEXP (x
, 1);
2123 /* We now expect the sum of a base and an index. */
2124 if (GET_CODE (x
) == PLUS
)
2126 if (m68k_legitimate_base_reg_p (XEXP (x
, 0), strict_p
)
2127 && m68k_decompose_index (XEXP (x
, 1), strict_p
, address
))
2129 address
->base
= XEXP (x
, 0);
2133 if (m68k_legitimate_base_reg_p (XEXP (x
, 1), strict_p
)
2134 && m68k_decompose_index (XEXP (x
, 0), strict_p
, address
))
2136 address
->base
= XEXP (x
, 1);
2143 /* Return true if X is a legitimate address for values of mode MODE.
2144 STRICT_P says whether strict checking is needed. */
2147 m68k_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2149 struct m68k_address address
;
2151 return m68k_decompose_address (mode
, x
, strict_p
, &address
);
2154 /* Return true if X is a memory, describing its address in ADDRESS if so.
2155 Apply strict checking if called during or after reload. */
2158 m68k_legitimate_mem_p (rtx x
, struct m68k_address
*address
)
2161 && m68k_decompose_address (GET_MODE (x
), XEXP (x
, 0),
2162 reload_in_progress
|| reload_completed
,
2166 /* Return true if X matches the 'Q' constraint. It must be a memory
2167 with a base address and no constant offset or index. */
2170 m68k_matches_q_p (rtx x
)
2172 struct m68k_address address
;
2174 return (m68k_legitimate_mem_p (x
, &address
)
2175 && address
.code
== UNKNOWN
2181 /* Return true if X matches the 'U' constraint. It must be a base address
2182 with a constant offset and no index. */
2185 m68k_matches_u_p (rtx x
)
2187 struct m68k_address address
;
2189 return (m68k_legitimate_mem_p (x
, &address
)
2190 && address
.code
== UNKNOWN
2196 /* Return GOT pointer. */
2201 if (pic_offset_table_rtx
== NULL_RTX
)
2202 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, PIC_REG
);
2204 crtl
->uses_pic_offset_table
= 1;
2206 return pic_offset_table_rtx
;
2209 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2211 enum m68k_reloc
{ RELOC_GOT
, RELOC_TLSGD
, RELOC_TLSLDM
, RELOC_TLSLDO
,
2212 RELOC_TLSIE
, RELOC_TLSLE
};
2214 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2216 /* Wrap symbol X into unspec representing relocation RELOC.
2217 BASE_REG - register that should be added to the result.
2218 TEMP_REG - if non-null, temporary register. */
2221 m68k_wrap_symbol (rtx x
, enum m68k_reloc reloc
, rtx base_reg
, rtx temp_reg
)
2225 use_x_p
= (base_reg
== pic_offset_table_rtx
) ? TARGET_XGOT
: TARGET_XTLS
;
2227 if (TARGET_COLDFIRE
&& use_x_p
)
2228 /* When compiling with -mx{got, tls} switch the code will look like this:
2230 move.l <X>@<RELOC>,<TEMP_REG>
2231 add.l <BASE_REG>,<TEMP_REG> */
2233 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2234 to put @RELOC after reference. */
2235 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2237 x
= gen_rtx_CONST (Pmode
, x
);
2239 if (temp_reg
== NULL
)
2241 gcc_assert (can_create_pseudo_p ());
2242 temp_reg
= gen_reg_rtx (Pmode
);
2245 emit_move_insn (temp_reg
, x
);
2246 emit_insn (gen_addsi3 (temp_reg
, temp_reg
, base_reg
));
2251 x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, x
, GEN_INT (reloc
)),
2253 x
= gen_rtx_CONST (Pmode
, x
);
2255 x
= gen_rtx_PLUS (Pmode
, base_reg
, x
);
2261 /* Helper for m68k_unwrap_symbol.
2262 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2263 sets *RELOC_PTR to relocation type for the symbol. */
2266 m68k_unwrap_symbol_1 (rtx orig
, bool unwrap_reloc32_p
,
2267 enum m68k_reloc
*reloc_ptr
)
2269 if (GET_CODE (orig
) == CONST
)
2272 enum m68k_reloc dummy
;
2276 if (reloc_ptr
== NULL
)
2279 /* Handle an addend. */
2280 if ((GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
)
2281 && CONST_INT_P (XEXP (x
, 1)))
2284 if (GET_CODE (x
) == UNSPEC
)
2286 switch (XINT (x
, 1))
2288 case UNSPEC_RELOC16
:
2289 orig
= XVECEXP (x
, 0, 0);
2290 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2293 case UNSPEC_RELOC32
:
2294 if (unwrap_reloc32_p
)
2296 orig
= XVECEXP (x
, 0, 0);
2297 *reloc_ptr
= (enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1));
2310 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2311 UNSPEC_RELOC32 wrappers. */
2314 m68k_unwrap_symbol (rtx orig
, bool unwrap_reloc32_p
)
2316 return m68k_unwrap_symbol_1 (orig
, unwrap_reloc32_p
, NULL
);
2319 /* Helper for m68k_final_prescan_insn. */
2322 m68k_final_prescan_insn_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2326 if (m68k_unwrap_symbol (x
, true) != x
)
2327 /* For rationale of the below, see comment in m68k_final_prescan_insn. */
2331 gcc_assert (GET_CODE (x
) == CONST
);
2334 if (GET_CODE (plus
) == PLUS
|| GET_CODE (plus
) == MINUS
)
2339 unspec
= XEXP (plus
, 0);
2340 gcc_assert (GET_CODE (unspec
) == UNSPEC
);
2341 addend
= XEXP (plus
, 1);
2342 gcc_assert (CONST_INT_P (addend
));
2344 /* We now have all the pieces, rearrange them. */
2346 /* Move symbol to plus. */
2347 XEXP (plus
, 0) = XVECEXP (unspec
, 0, 0);
2349 /* Move plus inside unspec. */
2350 XVECEXP (unspec
, 0, 0) = plus
;
2352 /* Move unspec to top level of const. */
2353 XEXP (x
, 0) = unspec
;
2362 /* Prescan insn before outputing assembler for it. */
2365 m68k_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED
,
2366 rtx
*operands
, int n_operands
)
2370 /* Combine and, possibly, other optimizations may do good job
2372 (const (unspec [(symbol)]))
2374 (const (plus (unspec [(symbol)])
2376 The problem with this is emitting @TLS or @GOT decorations.
2377 The decoration is emitted when processing (unspec), so the
2378 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2380 It seems that the easiest solution to this is to convert such
2382 (const (unspec [(plus (symbol)
2384 Note, that the top level of operand remains intact, so we don't have
2385 to patch up anything outside of the operand. */
2387 for (i
= 0; i
< n_operands
; ++i
)
2393 for_each_rtx (&op
, m68k_final_prescan_insn_1
, NULL
);
2397 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2398 If REG is non-null, use it; generate new pseudo otherwise. */
2401 m68k_move_to_reg (rtx x
, rtx orig
, rtx reg
)
2405 if (reg
== NULL_RTX
)
2407 gcc_assert (can_create_pseudo_p ());
2408 reg
= gen_reg_rtx (Pmode
);
2411 insn
= emit_move_insn (reg
, x
);
2412 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2414 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
2419 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2423 m68k_wrap_symbol_into_got_ref (rtx x
, enum m68k_reloc reloc
, rtx temp_reg
)
2425 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), temp_reg
);
2427 x
= gen_rtx_MEM (Pmode
, x
);
2428 MEM_READONLY_P (x
) = 1;
2433 /* Legitimize PIC addresses. If the address is already
2434 position-independent, we return ORIG. Newly generated
2435 position-independent addresses go to REG. If we need more
2436 than one register, we lose.
2438 An address is legitimized by making an indirect reference
2439 through the Global Offset Table with the name of the symbol
2442 The assembler and linker are responsible for placing the
2443 address of the symbol in the GOT. The function prologue
2444 is responsible for initializing a5 to the starting address
2447 The assembler is also responsible for translating a symbol name
2448 into a constant displacement from the start of the GOT.
2450 A quick example may make things a little clearer:
2452 When not generating PIC code to store the value 12345 into _foo
2453 we would generate the following code:
2457 When generating PIC two transformations are made. First, the compiler
2458 loads the address of foo into a register. So the first transformation makes:
2463 The code in movsi will intercept the lea instruction and call this
2464 routine which will transform the instructions into:
2466 movel a5@(_foo:w), a0
2470 That (in a nutshell) is how *all* symbol and label references are
2474 legitimize_pic_address (rtx orig
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2479 /* First handle a simple SYMBOL_REF or LABEL_REF */
2480 if (GET_CODE (orig
) == SYMBOL_REF
|| GET_CODE (orig
) == LABEL_REF
)
2484 pic_ref
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_GOT
, reg
);
2485 pic_ref
= m68k_move_to_reg (pic_ref
, orig
, reg
);
2487 else if (GET_CODE (orig
) == CONST
)
2491 /* Make sure this has not already been legitimized. */
2492 if (m68k_unwrap_symbol (orig
, true) != orig
)
2497 /* legitimize both operands of the PLUS */
2498 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
2500 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2501 orig
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2502 base
== reg
? 0 : reg
);
2504 if (GET_CODE (orig
) == CONST_INT
)
2505 pic_ref
= plus_constant (base
, INTVAL (orig
));
2507 pic_ref
= gen_rtx_PLUS (Pmode
, base
, orig
);
2513 /* The __tls_get_addr symbol. */
2514 static GTY(()) rtx m68k_tls_get_addr
;
2516 /* Return SYMBOL_REF for __tls_get_addr. */
2519 m68k_get_tls_get_addr (void)
2521 if (m68k_tls_get_addr
== NULL_RTX
)
2522 m68k_tls_get_addr
= init_one_libfunc ("__tls_get_addr");
2524 return m68k_tls_get_addr
;
2527 /* Return libcall result in A0 instead of usual D0. */
2528 static bool m68k_libcall_value_in_a0_p
= false;
2530 /* Emit instruction sequence that calls __tls_get_addr. X is
2531 the TLS symbol we are referencing and RELOC is the symbol type to use
2532 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2533 emitted. A pseudo register with result of __tls_get_addr call is
2537 m68k_call_tls_get_addr (rtx x
, rtx eqv
, enum m68k_reloc reloc
)
2543 /* Emit the call sequence. */
2546 /* FIXME: Unfortunately, emit_library_call_value does not
2547 consider (plus (%a5) (const (unspec))) to be a good enough
2548 operand for push, so it forces it into a register. The bad
2549 thing about this is that combiner, due to copy propagation and other
2550 optimizations, sometimes can not later fix this. As a consequence,
2551 additional register may be allocated resulting in a spill.
2552 For reference, see args processing loops in
2553 calls.c:emit_library_call_value_1.
2554 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2555 x
= m68k_wrap_symbol (x
, reloc
, m68k_get_gp (), NULL_RTX
);
2557 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2558 is the simpliest way of generating a call. The difference between
2559 __tls_get_addr() and libcall is that the result is returned in D0
2560 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2561 which temporarily switches returning the result to A0. */
2563 m68k_libcall_value_in_a0_p
= true;
2564 a0
= emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX
, LCT_PURE
,
2565 Pmode
, 1, x
, Pmode
);
2566 m68k_libcall_value_in_a0_p
= false;
2568 insns
= get_insns ();
2571 gcc_assert (can_create_pseudo_p ());
2572 dest
= gen_reg_rtx (Pmode
);
2573 emit_libcall_block (insns
, dest
, a0
, eqv
);
2578 /* The __tls_get_addr symbol. */
2579 static GTY(()) rtx m68k_read_tp
;
2581 /* Return SYMBOL_REF for __m68k_read_tp. */
2584 m68k_get_m68k_read_tp (void)
2586 if (m68k_read_tp
== NULL_RTX
)
2587 m68k_read_tp
= init_one_libfunc ("__m68k_read_tp");
2589 return m68k_read_tp
;
2592 /* Emit instruction sequence that calls __m68k_read_tp.
2593 A pseudo register with result of __m68k_read_tp call is returned. */
2596 m68k_call_m68k_read_tp (void)
2605 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2606 is the simpliest way of generating a call. The difference between
2607 __m68k_read_tp() and libcall is that the result is returned in D0
2608 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2609 which temporarily switches returning the result to A0. */
2611 /* Emit the call sequence. */
2612 m68k_libcall_value_in_a0_p
= true;
2613 a0
= emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX
, LCT_PURE
,
2615 m68k_libcall_value_in_a0_p
= false;
2616 insns
= get_insns ();
2619 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2620 share the m68k_read_tp result with other IE/LE model accesses. */
2621 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const1_rtx
), UNSPEC_RELOC32
);
2623 gcc_assert (can_create_pseudo_p ());
2624 dest
= gen_reg_rtx (Pmode
);
2625 emit_libcall_block (insns
, dest
, a0
, eqv
);
2630 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2631 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2635 m68k_legitimize_tls_address (rtx orig
)
2637 switch (SYMBOL_REF_TLS_MODEL (orig
))
2639 case TLS_MODEL_GLOBAL_DYNAMIC
:
2640 orig
= m68k_call_tls_get_addr (orig
, orig
, RELOC_TLSGD
);
2643 case TLS_MODEL_LOCAL_DYNAMIC
:
2649 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2650 share the LDM result with other LD model accesses. */
2651 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2654 a0
= m68k_call_tls_get_addr (orig
, eqv
, RELOC_TLSLDM
);
2656 x
= m68k_wrap_symbol (orig
, RELOC_TLSLDO
, a0
, NULL_RTX
);
2658 if (can_create_pseudo_p ())
2659 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2665 case TLS_MODEL_INITIAL_EXEC
:
2670 a0
= m68k_call_m68k_read_tp ();
2672 x
= m68k_wrap_symbol_into_got_ref (orig
, RELOC_TLSIE
, NULL_RTX
);
2673 x
= gen_rtx_PLUS (Pmode
, x
, a0
);
2675 if (can_create_pseudo_p ())
2676 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2682 case TLS_MODEL_LOCAL_EXEC
:
2687 a0
= m68k_call_m68k_read_tp ();
2689 x
= m68k_wrap_symbol (orig
, RELOC_TLSLE
, a0
, NULL_RTX
);
2691 if (can_create_pseudo_p ())
2692 x
= m68k_move_to_reg (x
, orig
, NULL_RTX
);
2705 /* Return true if X is a TLS symbol. */
2708 m68k_tls_symbol_p (rtx x
)
2710 if (!TARGET_HAVE_TLS
)
2713 if (GET_CODE (x
) != SYMBOL_REF
)
2716 return SYMBOL_REF_TLS_MODEL (x
) != 0;
2719 /* Helper for m68k_tls_referenced_p. */
2722 m68k_tls_reference_p_1 (rtx
*x_ptr
, void *data ATTRIBUTE_UNUSED
)
2724 /* Note: this is not the same as m68k_tls_symbol_p. */
2725 if (GET_CODE (*x_ptr
) == SYMBOL_REF
)
2726 return SYMBOL_REF_TLS_MODEL (*x_ptr
) != 0 ? 1 : 0;
2728 /* Don't recurse into legitimate TLS references. */
2729 if (m68k_tls_reference_p (*x_ptr
, true))
2735 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2736 though illegitimate one.
2737 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2740 m68k_tls_reference_p (rtx x
, bool legitimate_p
)
2742 if (!TARGET_HAVE_TLS
)
2746 return for_each_rtx (&x
, m68k_tls_reference_p_1
, NULL
) == 1 ? true : false;
2749 enum m68k_reloc reloc
= RELOC_GOT
;
2751 return (m68k_unwrap_symbol_1 (x
, true, &reloc
) != x
2752 && TLS_RELOC_P (reloc
));
2758 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2760 /* Return the type of move that should be used for integer I. */
2763 m68k_const_method (HOST_WIDE_INT i
)
2770 /* The ColdFire doesn't have byte or word operations. */
2771 /* FIXME: This may not be useful for the m68060 either. */
2772 if (!TARGET_COLDFIRE
)
2774 /* if -256 < N < 256 but N is not in range for a moveq
2775 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2776 if (USE_MOVQ (i
^ 0xff))
2778 /* Likewise, try with not.w */
2779 if (USE_MOVQ (i
^ 0xffff))
2781 /* This is the only value where neg.w is useful */
2786 /* Try also with swap. */
2788 if (USE_MOVQ ((u
>> 16) | (u
<< 16)))
2793 /* Try using MVZ/MVS with an immediate value to load constants. */
2794 if (i
>= 0 && i
<= 65535)
2796 if (i
>= -32768 && i
<= 32767)
2800 /* Otherwise, use move.l */
2804 /* Return the cost of moving constant I into a data register. */
2807 const_int_cost (HOST_WIDE_INT i
)
2809 switch (m68k_const_method (i
))
2812 /* Constants between -128 and 127 are cheap due to moveq. */
2820 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2830 m68k_rtx_costs (rtx x
, int code
, int outer_code
, int *total
,
2831 bool speed ATTRIBUTE_UNUSED
)
2836 /* Constant zero is super cheap due to clr instruction. */
2837 if (x
== const0_rtx
)
2840 *total
= const_int_cost (INTVAL (x
));
2850 /* Make 0.0 cheaper than other floating constants to
2851 encourage creating tstsf and tstdf insns. */
2852 if (outer_code
== COMPARE
2853 && (x
== CONST0_RTX (SFmode
) || x
== CONST0_RTX (DFmode
)))
2859 /* These are vaguely right for a 68020. */
2860 /* The costs for long multiply have been adjusted to work properly
2861 in synth_mult on the 68020, relative to an average of the time
2862 for add and the time for shift, taking away a little more because
2863 sometimes move insns are needed. */
2864 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2869 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2870 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2872 : TARGET_COLDFIRE ? 3 : 13)
2877 : TUNE_68000_10 ? 5 \
2878 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2879 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2881 : TARGET_COLDFIRE ? 2 : 8)
2884 (TARGET_CF_HWDIV ? 11 \
2885 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2888 /* An lea costs about three times as much as a simple add. */
2889 if (GET_MODE (x
) == SImode
2890 && GET_CODE (XEXP (x
, 1)) == REG
2891 && GET_CODE (XEXP (x
, 0)) == MULT
2892 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
2893 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2894 && (INTVAL (XEXP (XEXP (x
, 0), 1)) == 2
2895 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 4
2896 || INTVAL (XEXP (XEXP (x
, 0), 1)) == 8))
2898 /* lea an@(dx:l:i),am */
2899 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 2 : 3);
2909 *total
= COSTS_N_INSNS(1);
2914 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2916 if (INTVAL (XEXP (x
, 1)) < 16)
2917 *total
= COSTS_N_INSNS (2) + INTVAL (XEXP (x
, 1)) / 2;
2919 /* We're using clrw + swap for these cases. */
2920 *total
= COSTS_N_INSNS (4) + (INTVAL (XEXP (x
, 1)) - 16) / 2;
2923 *total
= COSTS_N_INSNS (10); /* Worst case. */
2926 /* A shift by a big integer takes an extra instruction. */
2927 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2928 && (INTVAL (XEXP (x
, 1)) == 16))
2930 *total
= COSTS_N_INSNS (2); /* clrw;swap */
2933 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
2934 && !(INTVAL (XEXP (x
, 1)) > 0
2935 && INTVAL (XEXP (x
, 1)) <= 8))
2937 *total
= COSTS_N_INSNS (TARGET_COLDFIRE
? 1 : 3); /* lsr #i,dn */
2943 if ((GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2944 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
2945 && GET_MODE (x
) == SImode
)
2946 *total
= COSTS_N_INSNS (MULW_COST
);
2947 else if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2948 *total
= COSTS_N_INSNS (MULW_COST
);
2950 *total
= COSTS_N_INSNS (MULL_COST
);
2957 if (GET_MODE (x
) == QImode
|| GET_MODE (x
) == HImode
)
2958 *total
= COSTS_N_INSNS (DIVW_COST
); /* div.w */
2959 else if (TARGET_CF_HWDIV
)
2960 *total
= COSTS_N_INSNS (18);
2962 *total
= COSTS_N_INSNS (43); /* div.l */
2966 if (outer_code
== COMPARE
)
2975 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2979 output_move_const_into_data_reg (rtx
*operands
)
2983 i
= INTVAL (operands
[1]);
2984 switch (m68k_const_method (i
))
2987 return "mvzw %1,%0";
2989 return "mvsw %1,%0";
2991 return "moveq %1,%0";
2994 operands
[1] = GEN_INT (i
^ 0xff);
2995 return "moveq %1,%0\n\tnot%.b %0";
2998 operands
[1] = GEN_INT (i
^ 0xffff);
2999 return "moveq %1,%0\n\tnot%.w %0";
3002 return "moveq #-128,%0\n\tneg%.w %0";
3007 operands
[1] = GEN_INT ((u
<< 16) | (u
>> 16));
3008 return "moveq %1,%0\n\tswap %0";
3011 return "move%.l %1,%0";
3017 /* Return true if I can be handled by ISA B's mov3q instruction. */
3020 valid_mov3q_const (HOST_WIDE_INT i
)
3022 return TARGET_ISAB
&& (i
== -1 || IN_RANGE (i
, 1, 7));
3025 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3026 I is the value of OPERANDS[1]. */
3029 output_move_simode_const (rtx
*operands
)
3035 src
= INTVAL (operands
[1]);
3037 && (DATA_REG_P (dest
) || MEM_P (dest
))
3038 /* clr insns on 68000 read before writing. */
3039 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3040 || !(MEM_P (dest
) && MEM_VOLATILE_P (dest
))))
3042 else if (GET_MODE (dest
) == SImode
&& valid_mov3q_const (src
))
3043 return "mov3q%.l %1,%0";
3044 else if (src
== 0 && ADDRESS_REG_P (dest
))
3045 return "sub%.l %0,%0";
3046 else if (DATA_REG_P (dest
))
3047 return output_move_const_into_data_reg (operands
);
3048 else if (ADDRESS_REG_P (dest
) && IN_RANGE (src
, -0x8000, 0x7fff))
3050 if (valid_mov3q_const (src
))
3051 return "mov3q%.l %1,%0";
3052 return "move%.w %1,%0";
3054 else if (MEM_P (dest
)
3055 && GET_CODE (XEXP (dest
, 0)) == PRE_DEC
3056 && REGNO (XEXP (XEXP (dest
, 0), 0)) == STACK_POINTER_REGNUM
3057 && IN_RANGE (src
, -0x8000, 0x7fff))
3059 if (valid_mov3q_const (src
))
3060 return "mov3q%.l %1,%-";
3063 return "move%.l %1,%0";
3067 output_move_simode (rtx
*operands
)
3069 if (GET_CODE (operands
[1]) == CONST_INT
)
3070 return output_move_simode_const (operands
);
3071 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3072 || GET_CODE (operands
[1]) == CONST
)
3073 && push_operand (operands
[0], SImode
))
3075 else if ((GET_CODE (operands
[1]) == SYMBOL_REF
3076 || GET_CODE (operands
[1]) == CONST
)
3077 && ADDRESS_REG_P (operands
[0]))
3078 return "lea %a1,%0";
3079 return "move%.l %1,%0";
3083 output_move_himode (rtx
*operands
)
3085 if (GET_CODE (operands
[1]) == CONST_INT
)
3087 if (operands
[1] == const0_rtx
3088 && (DATA_REG_P (operands
[0])
3089 || GET_CODE (operands
[0]) == MEM
)
3090 /* clr insns on 68000 read before writing. */
3091 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3092 || !(GET_CODE (operands
[0]) == MEM
3093 && MEM_VOLATILE_P (operands
[0]))))
3095 else if (operands
[1] == const0_rtx
3096 && ADDRESS_REG_P (operands
[0]))
3097 return "sub%.l %0,%0";
3098 else if (DATA_REG_P (operands
[0])
3099 && INTVAL (operands
[1]) < 128
3100 && INTVAL (operands
[1]) >= -128)
3101 return "moveq %1,%0";
3102 else if (INTVAL (operands
[1]) < 0x8000
3103 && INTVAL (operands
[1]) >= -0x8000)
3104 return "move%.w %1,%0";
3106 else if (CONSTANT_P (operands
[1]))
3107 return "move%.l %1,%0";
3108 return "move%.w %1,%0";
3112 output_move_qimode (rtx
*operands
)
3114 /* 68k family always modifies the stack pointer by at least 2, even for
3115 byte pushes. The 5200 (ColdFire) does not do this. */
3117 /* This case is generated by pushqi1 pattern now. */
3118 gcc_assert (!(GET_CODE (operands
[0]) == MEM
3119 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
3120 && XEXP (XEXP (operands
[0], 0), 0) == stack_pointer_rtx
3121 && ! ADDRESS_REG_P (operands
[1])
3122 && ! TARGET_COLDFIRE
));
3124 /* clr and st insns on 68000 read before writing. */
3125 if (!ADDRESS_REG_P (operands
[0])
3126 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3127 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3129 if (operands
[1] == const0_rtx
)
3131 if ((!TARGET_COLDFIRE
|| DATA_REG_P (operands
[0]))
3132 && GET_CODE (operands
[1]) == CONST_INT
3133 && (INTVAL (operands
[1]) & 255) == 255)
3139 if (GET_CODE (operands
[1]) == CONST_INT
3140 && DATA_REG_P (operands
[0])
3141 && INTVAL (operands
[1]) < 128
3142 && INTVAL (operands
[1]) >= -128)
3143 return "moveq %1,%0";
3144 if (operands
[1] == const0_rtx
&& ADDRESS_REG_P (operands
[0]))
3145 return "sub%.l %0,%0";
3146 if (GET_CODE (operands
[1]) != CONST_INT
&& CONSTANT_P (operands
[1]))
3147 return "move%.l %1,%0";
3148 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3149 from address registers. */
3150 if (ADDRESS_REG_P (operands
[0]) || ADDRESS_REG_P (operands
[1]))
3151 return "move%.w %1,%0";
3152 return "move%.b %1,%0";
3156 output_move_stricthi (rtx
*operands
)
3158 if (operands
[1] == const0_rtx
3159 /* clr insns on 68000 read before writing. */
3160 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3161 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3163 return "move%.w %1,%0";
3167 output_move_strictqi (rtx
*operands
)
3169 if (operands
[1] == const0_rtx
3170 /* clr insns on 68000 read before writing. */
3171 && ((TARGET_68010
|| TARGET_COLDFIRE
)
3172 || !(GET_CODE (operands
[0]) == MEM
&& MEM_VOLATILE_P (operands
[0]))))
3174 return "move%.b %1,%0";
3177 /* Return the best assembler insn template
3178 for moving operands[1] into operands[0] as a fullword. */
3181 singlemove_string (rtx
*operands
)
3183 if (GET_CODE (operands
[1]) == CONST_INT
)
3184 return output_move_simode_const (operands
);
3185 return "move%.l %1,%0";
3189 /* Output assembler or rtl code to perform a doubleword move insn
3190 with operands OPERANDS.
3191 Pointers to 3 helper functions should be specified:
3192 HANDLE_REG_ADJUST to adjust a register by a small value,
3193 HANDLE_COMPADR to compute an address and
3194 HANDLE_MOVSI to move 4 bytes. */
3197 handle_move_double (rtx operands
[2],
3198 void (*handle_reg_adjust
) (rtx
, int),
3199 void (*handle_compadr
) (rtx
[2]),
3200 void (*handle_movsi
) (rtx
[2]))
3204 REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
3209 rtx addreg0
= 0, addreg1
= 0;
3210 int dest_overlapped_low
= 0;
3211 int size
= GET_MODE_SIZE (GET_MODE (operands
[0]));
3216 /* First classify both operands. */
3218 if (REG_P (operands
[0]))
3220 else if (offsettable_memref_p (operands
[0]))
3222 else if (GET_CODE (XEXP (operands
[0], 0)) == POST_INC
)
3224 else if (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
3226 else if (GET_CODE (operands
[0]) == MEM
)
3231 if (REG_P (operands
[1]))
3233 else if (CONSTANT_P (operands
[1]))
3235 else if (offsettable_memref_p (operands
[1]))
3237 else if (GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)
3239 else if (GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
)
3241 else if (GET_CODE (operands
[1]) == MEM
)
3246 /* Check for the cases that the operand constraints are not supposed
3247 to allow to happen. Generating code for these cases is
3249 gcc_assert (optype0
!= RNDOP
&& optype1
!= RNDOP
);
3251 /* If one operand is decrementing and one is incrementing
3252 decrement the former register explicitly
3253 and change that operand into ordinary indexing. */
3255 if (optype0
== PUSHOP
&& optype1
== POPOP
)
3257 operands
[0] = XEXP (XEXP (operands
[0], 0), 0);
3259 handle_reg_adjust (operands
[0], -size
);
3261 if (GET_MODE (operands
[1]) == XFmode
)
3262 operands
[0] = gen_rtx_MEM (XFmode
, operands
[0]);
3263 else if (GET_MODE (operands
[0]) == DFmode
)
3264 operands
[0] = gen_rtx_MEM (DFmode
, operands
[0]);
3266 operands
[0] = gen_rtx_MEM (DImode
, operands
[0]);
3269 if (optype0
== POPOP
&& optype1
== PUSHOP
)
3271 operands
[1] = XEXP (XEXP (operands
[1], 0), 0);
3273 handle_reg_adjust (operands
[1], -size
);
3275 if (GET_MODE (operands
[1]) == XFmode
)
3276 operands
[1] = gen_rtx_MEM (XFmode
, operands
[1]);
3277 else if (GET_MODE (operands
[1]) == DFmode
)
3278 operands
[1] = gen_rtx_MEM (DFmode
, operands
[1]);
3280 operands
[1] = gen_rtx_MEM (DImode
, operands
[1]);
3284 /* If an operand is an unoffsettable memory ref, find a register
3285 we can increment temporarily to make it refer to the second word. */
3287 if (optype0
== MEMOP
)
3288 addreg0
= find_addr_reg (XEXP (operands
[0], 0));
3290 if (optype1
== MEMOP
)
3291 addreg1
= find_addr_reg (XEXP (operands
[1], 0));
3293 /* Ok, we can do one word at a time.
3294 Normally we do the low-numbered word first,
3295 but if either operand is autodecrementing then we
3296 do the high-numbered word first.
3298 In either case, set up in LATEHALF the operands to use
3299 for the high-numbered word and in some cases alter the
3300 operands in OPERANDS to be suitable for the low-numbered word. */
3304 if (optype0
== REGOP
)
3306 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 2);
3307 middlehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3309 else if (optype0
== OFFSOP
)
3311 middlehalf
[0] = adjust_address (operands
[0], SImode
, 4);
3312 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3316 middlehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3317 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3320 if (optype1
== REGOP
)
3322 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 2);
3323 middlehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3325 else if (optype1
== OFFSOP
)
3327 middlehalf
[1] = adjust_address (operands
[1], SImode
, 4);
3328 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3330 else if (optype1
== CNSTOP
)
3332 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
3337 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
3338 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
3339 operands
[1] = GEN_INT (l
[0]);
3340 middlehalf
[1] = GEN_INT (l
[1]);
3341 latehalf
[1] = GEN_INT (l
[2]);
3345 /* No non-CONST_DOUBLE constant should ever appear
3347 gcc_assert (!CONSTANT_P (operands
[1]));
3352 middlehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3353 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3357 /* size is not 12: */
3359 if (optype0
== REGOP
)
3360 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (operands
[0]) + 1);
3361 else if (optype0
== OFFSOP
)
3362 latehalf
[0] = adjust_address (operands
[0], SImode
, size
- 4);
3364 latehalf
[0] = adjust_address (operands
[0], SImode
, 0);
3366 if (optype1
== REGOP
)
3367 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (operands
[1]) + 1);
3368 else if (optype1
== OFFSOP
)
3369 latehalf
[1] = adjust_address (operands
[1], SImode
, size
- 4);
3370 else if (optype1
== CNSTOP
)
3371 split_double (operands
[1], &operands
[1], &latehalf
[1]);
3373 latehalf
[1] = adjust_address (operands
[1], SImode
, 0);
3376 /* If insn is effectively movd N(sp),-(sp) then we will do the
3377 high word first. We should use the adjusted operand 1 (which is N+4(sp))
3378 for the low word as well, to compensate for the first decrement of sp. */
3379 if (optype0
== PUSHOP
3380 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
3381 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
3382 operands
[1] = middlehalf
[1] = latehalf
[1];
3384 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3385 if the upper part of reg N does not appear in the MEM, arrange to
3386 emit the move late-half first. Otherwise, compute the MEM address
3387 into the upper part of N and use that as a pointer to the memory
3389 if (optype0
== REGOP
3390 && (optype1
== OFFSOP
|| optype1
== MEMOP
))
3392 rtx testlow
= gen_rtx_REG (SImode
, REGNO (operands
[0]));
3394 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3395 && reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3397 /* If both halves of dest are used in the src memory address,
3398 compute the address into latehalf of dest.
3399 Note that this can't happen if the dest is two data regs. */
3401 xops
[0] = latehalf
[0];
3402 xops
[1] = XEXP (operands
[1], 0);
3404 handle_compadr (xops
);
3405 if (GET_MODE (operands
[1]) == XFmode
)
3407 operands
[1] = gen_rtx_MEM (XFmode
, latehalf
[0]);
3408 middlehalf
[1] = adjust_address (operands
[1], DImode
, size
- 8);
3409 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3413 operands
[1] = gen_rtx_MEM (DImode
, latehalf
[0]);
3414 latehalf
[1] = adjust_address (operands
[1], DImode
, size
- 4);
3418 && reg_overlap_mentioned_p (middlehalf
[0],
3419 XEXP (operands
[1], 0)))
3421 /* Check for two regs used by both source and dest.
3422 Note that this can't happen if the dest is all data regs.
3423 It can happen if the dest is d6, d7, a0.
3424 But in that case, latehalf is an addr reg, so
3425 the code at compadr does ok. */
3427 if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0))
3428 || reg_overlap_mentioned_p (latehalf
[0], XEXP (operands
[1], 0)))
3431 /* JRV says this can't happen: */
3432 gcc_assert (!addreg0
&& !addreg1
);
3434 /* Only the middle reg conflicts; simply put it last. */
3435 handle_movsi (operands
);
3436 handle_movsi (latehalf
);
3437 handle_movsi (middlehalf
);
3441 else if (reg_overlap_mentioned_p (testlow
, XEXP (operands
[1], 0)))
3442 /* If the low half of dest is mentioned in the source memory
3443 address, the arrange to emit the move late half first. */
3444 dest_overlapped_low
= 1;
3447 /* If one or both operands autodecrementing,
3448 do the two words, high-numbered first. */
3450 /* Likewise, the first move would clobber the source of the second one,
3451 do them in the other order. This happens only for registers;
3452 such overlap can't happen in memory unless the user explicitly
3453 sets it up, and that is an undefined circumstance. */
3455 if (optype0
== PUSHOP
|| optype1
== PUSHOP
3456 || (optype0
== REGOP
&& optype1
== REGOP
3457 && ((middlehalf
[1] && REGNO (operands
[0]) == REGNO (middlehalf
[1]))
3458 || REGNO (operands
[0]) == REGNO (latehalf
[1])))
3459 || dest_overlapped_low
)
3461 /* Make any unoffsettable addresses point at high-numbered word. */
3463 handle_reg_adjust (addreg0
, size
- 4);
3465 handle_reg_adjust (addreg1
, size
- 4);
3468 handle_movsi (latehalf
);
3470 /* Undo the adds we just did. */
3472 handle_reg_adjust (addreg0
, -4);
3474 handle_reg_adjust (addreg1
, -4);
3478 handle_movsi (middlehalf
);
3481 handle_reg_adjust (addreg0
, -4);
3483 handle_reg_adjust (addreg1
, -4);
3486 /* Do low-numbered word. */
3488 handle_movsi (operands
);
3492 /* Normal case: do the two words, low-numbered first. */
3494 m68k_final_prescan_insn (NULL
, operands
, 2);
3495 handle_movsi (operands
);
3497 /* Do the middle one of the three words for long double */
3501 handle_reg_adjust (addreg0
, 4);
3503 handle_reg_adjust (addreg1
, 4);
3505 m68k_final_prescan_insn (NULL
, middlehalf
, 2);
3506 handle_movsi (middlehalf
);
3509 /* Make any unoffsettable addresses point at high-numbered word. */
3511 handle_reg_adjust (addreg0
, 4);
3513 handle_reg_adjust (addreg1
, 4);
3516 m68k_final_prescan_insn (NULL
, latehalf
, 2);
3517 handle_movsi (latehalf
);
3519 /* Undo the adds we just did. */
3521 handle_reg_adjust (addreg0
, -(size
- 4));
3523 handle_reg_adjust (addreg1
, -(size
- 4));
3528 /* Output assembler code to adjust REG by N. */
3530 output_reg_adjust (rtx reg
, int n
)
3534 gcc_assert (GET_MODE (reg
) == SImode
3535 && -12 <= n
&& n
!= 0 && n
<= 12);
3540 s
= "add%.l #12,%0";
3544 s
= "addq%.l #8,%0";
3548 s
= "addq%.l #4,%0";
3552 s
= "sub%.l #12,%0";
3556 s
= "subq%.l #8,%0";
3560 s
= "subq%.l #4,%0";
3568 output_asm_insn (s
, ®
);
3571 /* Emit rtl code to adjust REG by N. */
3573 emit_reg_adjust (rtx reg1
, int n
)
3577 gcc_assert (GET_MODE (reg1
) == SImode
3578 && -12 <= n
&& n
!= 0 && n
<= 12);
3580 reg1
= copy_rtx (reg1
);
3581 reg2
= copy_rtx (reg1
);
3584 emit_insn (gen_subsi3 (reg1
, reg2
, GEN_INT (-n
)));
3586 emit_insn (gen_addsi3 (reg1
, reg2
, GEN_INT (n
)));
3591 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3593 output_compadr (rtx operands
[2])
3595 output_asm_insn ("lea %a1,%0", operands
);
3598 /* Output the best assembler insn for moving operands[1] into operands[0]
3601 output_movsi (rtx operands
[2])
3603 output_asm_insn (singlemove_string (operands
), operands
);
3606 /* Copy OP and change its mode to MODE. */
3608 copy_operand (rtx op
, enum machine_mode mode
)
3610 /* ??? This looks really ugly. There must be a better way
3611 to change a mode on the operand. */
3612 if (GET_MODE (op
) != VOIDmode
)
3615 op
= gen_rtx_REG (mode
, REGNO (op
));
3619 PUT_MODE (op
, mode
);
3626 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3628 emit_movsi (rtx operands
[2])
3630 operands
[0] = copy_operand (operands
[0], SImode
);
3631 operands
[1] = copy_operand (operands
[1], SImode
);
3633 emit_insn (gen_movsi (operands
[0], operands
[1]));
3636 /* Output assembler code to perform a doubleword move insn
3637 with operands OPERANDS. */
3639 output_move_double (rtx
*operands
)
3641 handle_move_double (operands
,
3642 output_reg_adjust
, output_compadr
, output_movsi
);
3647 /* Output rtl code to perform a doubleword move insn
3648 with operands OPERANDS. */
3650 m68k_emit_move_double (rtx operands
[2])
3652 handle_move_double (operands
, emit_reg_adjust
, emit_movsi
, emit_movsi
);
3655 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3656 new rtx with the correct mode. */
3659 force_mode (enum machine_mode mode
, rtx orig
)
3661 if (mode
== GET_MODE (orig
))
3664 if (REGNO (orig
) >= FIRST_PSEUDO_REGISTER
)
3667 return gen_rtx_REG (mode
, REGNO (orig
));
3671 fp_reg_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3673 return reg_renumber
&& FP_REG_P (op
);
3676 /* Emit insns to move operands[1] into operands[0].
3678 Return 1 if we have written out everything that needs to be done to
3679 do the move. Otherwise, return 0 and the caller will emit the move
3682 Note SCRATCH_REG may not be in the proper mode depending on how it
3683 will be used. This routine is responsible for creating a new copy
3684 of SCRATCH_REG in the proper mode. */
3687 emit_move_sequence (rtx
*operands
, enum machine_mode mode
, rtx scratch_reg
)
3689 register rtx operand0
= operands
[0];
3690 register rtx operand1
= operands
[1];
3694 && reload_in_progress
&& GET_CODE (operand0
) == REG
3695 && REGNO (operand0
) >= FIRST_PSEUDO_REGISTER
)
3696 operand0
= reg_equiv_mem (REGNO (operand0
));
3697 else if (scratch_reg
3698 && reload_in_progress
&& GET_CODE (operand0
) == SUBREG
3699 && GET_CODE (SUBREG_REG (operand0
)) == REG
3700 && REGNO (SUBREG_REG (operand0
)) >= FIRST_PSEUDO_REGISTER
)
3702 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3703 the code which tracks sets/uses for delete_output_reload. */
3704 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand0
),
3705 reg_equiv_mem (REGNO (SUBREG_REG (operand0
))),
3706 SUBREG_BYTE (operand0
));
3707 operand0
= alter_subreg (&temp
);
3711 && reload_in_progress
&& GET_CODE (operand1
) == REG
3712 && REGNO (operand1
) >= FIRST_PSEUDO_REGISTER
)
3713 operand1
= reg_equiv_mem (REGNO (operand1
));
3714 else if (scratch_reg
3715 && reload_in_progress
&& GET_CODE (operand1
) == SUBREG
3716 && GET_CODE (SUBREG_REG (operand1
)) == REG
3717 && REGNO (SUBREG_REG (operand1
)) >= FIRST_PSEUDO_REGISTER
)
3719 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3720 the code which tracks sets/uses for delete_output_reload. */
3721 rtx temp
= gen_rtx_SUBREG (GET_MODE (operand1
),
3722 reg_equiv_mem (REGNO (SUBREG_REG (operand1
))),
3723 SUBREG_BYTE (operand1
));
3724 operand1
= alter_subreg (&temp
);
3727 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand0
) == MEM
3728 && ((tem
= find_replacement (&XEXP (operand0
, 0)))
3729 != XEXP (operand0
, 0)))
3730 operand0
= gen_rtx_MEM (GET_MODE (operand0
), tem
);
3731 if (scratch_reg
&& reload_in_progress
&& GET_CODE (operand1
) == MEM
3732 && ((tem
= find_replacement (&XEXP (operand1
, 0)))
3733 != XEXP (operand1
, 0)))
3734 operand1
= gen_rtx_MEM (GET_MODE (operand1
), tem
);
3736 /* Handle secondary reloads for loads/stores of FP registers where
3737 the address is symbolic by using the scratch register */
3738 if (fp_reg_operand (operand0
, mode
)
3739 && ((GET_CODE (operand1
) == MEM
3740 && ! memory_address_p (DFmode
, XEXP (operand1
, 0)))
3741 || ((GET_CODE (operand1
) == SUBREG
3742 && GET_CODE (XEXP (operand1
, 0)) == MEM
3743 && !memory_address_p (DFmode
, XEXP (XEXP (operand1
, 0), 0)))))
3746 if (GET_CODE (operand1
) == SUBREG
)
3747 operand1
= XEXP (operand1
, 0);
3749 /* SCRATCH_REG will hold an address. We want
3750 it in SImode regardless of what mode it was originally given
3752 scratch_reg
= force_mode (SImode
, scratch_reg
);
3754 /* D might not fit in 14 bits either; for such cases load D into
3756 if (!memory_address_p (Pmode
, XEXP (operand1
, 0)))
3758 emit_move_insn (scratch_reg
, XEXP (XEXP (operand1
, 0), 1));
3759 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1
, 0)),
3761 XEXP (XEXP (operand1
, 0), 0),
3765 emit_move_insn (scratch_reg
, XEXP (operand1
, 0));
3766 emit_insn (gen_rtx_SET (VOIDmode
, operand0
,
3767 gen_rtx_MEM (mode
, scratch_reg
)));
3770 else if (fp_reg_operand (operand1
, mode
)
3771 && ((GET_CODE (operand0
) == MEM
3772 && ! memory_address_p (DFmode
, XEXP (operand0
, 0)))
3773 || ((GET_CODE (operand0
) == SUBREG
)
3774 && GET_CODE (XEXP (operand0
, 0)) == MEM
3775 && !memory_address_p (DFmode
, XEXP (XEXP (operand0
, 0), 0))))
3778 if (GET_CODE (operand0
) == SUBREG
)
3779 operand0
= XEXP (operand0
, 0);
3781 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3782 it in SIMODE regardless of what mode it was originally given
3784 scratch_reg
= force_mode (SImode
, scratch_reg
);
3786 /* D might not fit in 14 bits either; for such cases load D into
3788 if (!memory_address_p (Pmode
, XEXP (operand0
, 0)))
3790 emit_move_insn (scratch_reg
, XEXP (XEXP (operand0
, 0), 1));
3791 emit_move_insn (scratch_reg
, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0
,
3794 XEXP (XEXP (operand0
, 0),
3799 emit_move_insn (scratch_reg
, XEXP (operand0
, 0));
3800 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_MEM (mode
, scratch_reg
),
3804 /* Handle secondary reloads for loads of FP registers from constant
3805 expressions by forcing the constant into memory.
3807 use scratch_reg to hold the address of the memory location.
3809 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3810 NO_REGS when presented with a const_int and an register class
3811 containing only FP registers. Doing so unfortunately creates
3812 more problems than it solves. Fix this for 2.5. */
3813 else if (fp_reg_operand (operand0
, mode
)
3814 && CONSTANT_P (operand1
)
3819 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3820 it in SIMODE regardless of what mode it was originally given
3822 scratch_reg
= force_mode (SImode
, scratch_reg
);
3824 /* Force the constant into memory and put the address of the
3825 memory location into scratch_reg. */
3826 xoperands
[0] = scratch_reg
;
3827 xoperands
[1] = XEXP (force_const_mem (mode
, operand1
), 0);
3828 emit_insn (gen_rtx_SET (mode
, scratch_reg
, xoperands
[1]));
3830 /* Now load the destination register. */
3831 emit_insn (gen_rtx_SET (mode
, operand0
,
3832 gen_rtx_MEM (mode
, scratch_reg
)));
3836 /* Now have insn-emit do whatever it normally does. */
3840 /* Split one or more DImode RTL references into pairs of SImode
3841 references. The RTL can be REG, offsettable MEM, integer constant, or
3842 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3843 split and "num" is its length. lo_half and hi_half are output arrays
3844 that parallel "operands". */
3847 split_di (rtx operands
[], int num
, rtx lo_half
[], rtx hi_half
[])
3851 rtx op
= operands
[num
];
3853 /* simplify_subreg refuses to split volatile memory addresses,
3854 but we still have to handle it. */
3855 if (GET_CODE (op
) == MEM
)
3857 lo_half
[num
] = adjust_address (op
, SImode
, 4);
3858 hi_half
[num
] = adjust_address (op
, SImode
, 0);
3862 lo_half
[num
] = simplify_gen_subreg (SImode
, op
,
3863 GET_MODE (op
) == VOIDmode
3864 ? DImode
: GET_MODE (op
), 4);
3865 hi_half
[num
] = simplify_gen_subreg (SImode
, op
,
3866 GET_MODE (op
) == VOIDmode
3867 ? DImode
: GET_MODE (op
), 0);
3872 /* Split X into a base and a constant offset, storing them in *BASE
3873 and *OFFSET respectively. */
3876 m68k_split_offset (rtx x
, rtx
*base
, HOST_WIDE_INT
*offset
)
3879 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
3881 *offset
+= INTVAL (XEXP (x
, 1));
3887 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3888 instruction. STORE_P says whether the move is a load or store.
3890 If the instruction uses post-increment or pre-decrement addressing,
3891 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3892 adjustment. This adjustment will be made by the first element of
3893 PARALLEL, with the loads or stores starting at element 1. If the
3894 instruction does not use post-increment or pre-decrement addressing,
3895 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3896 start at element 0. */
3899 m68k_movem_pattern_p (rtx pattern
, rtx automod_base
,
3900 HOST_WIDE_INT automod_offset
, bool store_p
)
3902 rtx base
, mem_base
, set
, mem
, reg
, last_reg
;
3903 HOST_WIDE_INT offset
, mem_offset
;
3905 enum reg_class rclass
;
3907 len
= XVECLEN (pattern
, 0);
3908 first
= (automod_base
!= NULL
);
3912 /* Stores must be pre-decrement and loads must be post-increment. */
3913 if (store_p
!= (automod_offset
< 0))
3916 /* Work out the base and offset for lowest memory location. */
3917 base
= automod_base
;
3918 offset
= (automod_offset
< 0 ? automod_offset
: 0);
3922 /* Allow any valid base and offset in the first access. */
3929 for (i
= first
; i
< len
; i
++)
3931 /* We need a plain SET. */
3932 set
= XVECEXP (pattern
, 0, i
);
3933 if (GET_CODE (set
) != SET
)
3936 /* Check that we have a memory location... */
3937 mem
= XEXP (set
, !store_p
);
3938 if (!MEM_P (mem
) || !memory_operand (mem
, VOIDmode
))
3941 /* ...with the right address. */
3944 m68k_split_offset (XEXP (mem
, 0), &base
, &offset
);
3945 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3946 There are no mode restrictions for 680x0 besides the
3947 automodification rules enforced above. */
3949 && !m68k_legitimate_base_reg_p (base
, reload_completed
))
3954 m68k_split_offset (XEXP (mem
, 0), &mem_base
, &mem_offset
);
3955 if (!rtx_equal_p (base
, mem_base
) || offset
!= mem_offset
)
3959 /* Check that we have a register of the required mode and class. */
3960 reg
= XEXP (set
, store_p
);
3962 || !HARD_REGISTER_P (reg
)
3963 || GET_MODE (reg
) != reg_raw_mode
[REGNO (reg
)])
3968 /* The register must belong to RCLASS and have a higher number
3969 than the register in the previous SET. */
3970 if (!TEST_HARD_REG_BIT (reg_class_contents
[rclass
], REGNO (reg
))
3971 || REGNO (last_reg
) >= REGNO (reg
))
3976 /* Work out which register class we need. */
3977 if (INT_REGNO_P (REGNO (reg
)))
3978 rclass
= GENERAL_REGS
;
3979 else if (FP_REGNO_P (REGNO (reg
)))
3986 offset
+= GET_MODE_SIZE (GET_MODE (reg
));
3989 /* If we have an automodification, check whether the final offset is OK. */
3990 if (automod_base
&& offset
!= (automod_offset
< 0 ? 0 : automod_offset
))
3993 /* Reject unprofitable cases. */
3994 if (len
< first
+ (rclass
== FP_REGS
? MIN_FMOVEM_REGS
: MIN_MOVEM_REGS
))
4000 /* Return the assembly code template for a movem or fmovem instruction
4001 whose pattern is given by PATTERN. Store the template's operands
4004 If the instruction uses post-increment or pre-decrement addressing,
4005 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
4006 is true if this is a store instruction. */
4009 m68k_output_movem (rtx
*operands
, rtx pattern
,
4010 HOST_WIDE_INT automod_offset
, bool store_p
)
4015 gcc_assert (GET_CODE (pattern
) == PARALLEL
);
4017 first
= (automod_offset
!= 0);
4018 for (i
= first
; i
< XVECLEN (pattern
, 0); i
++)
4020 /* When using movem with pre-decrement addressing, register X + D0_REG
4021 is controlled by bit 15 - X. For all other addressing modes,
4022 register X + D0_REG is controlled by bit X. Confusingly, the
4023 register mask for fmovem is in the opposite order to that for
4027 gcc_assert (MEM_P (XEXP (XVECEXP (pattern
, 0, i
), !store_p
)));
4028 gcc_assert (REG_P (XEXP (XVECEXP (pattern
, 0, i
), store_p
)));
4029 regno
= REGNO (XEXP (XVECEXP (pattern
, 0, i
), store_p
));
4030 if (automod_offset
< 0)
4032 if (FP_REGNO_P (regno
))
4033 mask
|= 1 << (regno
- FP0_REG
);
4035 mask
|= 1 << (15 - (regno
- D0_REG
));
4039 if (FP_REGNO_P (regno
))
4040 mask
|= 1 << (7 - (regno
- FP0_REG
));
4042 mask
|= 1 << (regno
- D0_REG
);
4047 if (automod_offset
== 0)
4048 operands
[0] = XEXP (XEXP (XVECEXP (pattern
, 0, first
), !store_p
), 0);
4049 else if (automod_offset
< 0)
4050 operands
[0] = gen_rtx_PRE_DEC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4052 operands
[0] = gen_rtx_POST_INC (Pmode
, SET_DEST (XVECEXP (pattern
, 0, 0)));
4053 operands
[1] = GEN_INT (mask
);
4054 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern
, 0, first
), store_p
))))
4057 return "fmovem %1,%a0";
4059 return "fmovem %a0,%1";
4064 return "movem%.l %1,%a0";
4066 return "movem%.l %a0,%1";
4070 /* Return a REG that occurs in ADDR with coefficient 1.
4071 ADDR can be effectively incremented by incrementing REG. */
4074 find_addr_reg (rtx addr
)
4076 while (GET_CODE (addr
) == PLUS
)
4078 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4079 addr
= XEXP (addr
, 0);
4080 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
4081 addr
= XEXP (addr
, 1);
4082 else if (CONSTANT_P (XEXP (addr
, 0)))
4083 addr
= XEXP (addr
, 1);
4084 else if (CONSTANT_P (XEXP (addr
, 1)))
4085 addr
= XEXP (addr
, 0);
4089 gcc_assert (GET_CODE (addr
) == REG
);
4093 /* Output assembler code to perform a 32-bit 3-operand add. */
4096 output_addsi3 (rtx
*operands
)
4098 if (! operands_match_p (operands
[0], operands
[1]))
4100 if (!ADDRESS_REG_P (operands
[1]))
4102 rtx tmp
= operands
[1];
4104 operands
[1] = operands
[2];
4108 /* These insns can result from reloads to access
4109 stack slots over 64k from the frame pointer. */
4110 if (GET_CODE (operands
[2]) == CONST_INT
4111 && (INTVAL (operands
[2]) < -32768 || INTVAL (operands
[2]) > 32767))
4112 return "move%.l %2,%0\n\tadd%.l %1,%0";
4113 if (GET_CODE (operands
[2]) == REG
)
4114 return MOTOROLA
? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4115 return MOTOROLA
? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4117 if (GET_CODE (operands
[2]) == CONST_INT
)
4119 if (INTVAL (operands
[2]) > 0
4120 && INTVAL (operands
[2]) <= 8)
4121 return "addq%.l %2,%0";
4122 if (INTVAL (operands
[2]) < 0
4123 && INTVAL (operands
[2]) >= -8)
4125 operands
[2] = GEN_INT (- INTVAL (operands
[2]));
4126 return "subq%.l %2,%0";
4128 /* On the CPU32 it is faster to use two addql instructions to
4129 add a small integer (8 < N <= 16) to a register.
4130 Likewise for subql. */
4131 if (TUNE_CPU32
&& REG_P (operands
[0]))
4133 if (INTVAL (operands
[2]) > 8
4134 && INTVAL (operands
[2]) <= 16)
4136 operands
[2] = GEN_INT (INTVAL (operands
[2]) - 8);
4137 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4139 if (INTVAL (operands
[2]) < -8
4140 && INTVAL (operands
[2]) >= -16)
4142 operands
[2] = GEN_INT (- INTVAL (operands
[2]) - 8);
4143 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4146 if (ADDRESS_REG_P (operands
[0])
4147 && INTVAL (operands
[2]) >= -0x8000
4148 && INTVAL (operands
[2]) < 0x8000)
4151 return "add%.w %2,%0";
4153 return MOTOROLA
? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4156 return "add%.l %2,%0";
4159 /* Store in cc_status the expressions that the condition codes will
4160 describe after execution of an instruction whose pattern is EXP.
4161 Do not alter them if the instruction would not alter the cc's. */
4163 /* On the 68000, all the insns to store in an address register fail to
4164 set the cc's. However, in some cases these instructions can make it
4165 possibly invalid to use the saved cc's. In those cases we clear out
4166 some or all of the saved cc's so they won't be used. */
4169 notice_update_cc (rtx exp
, rtx insn
)
4171 if (GET_CODE (exp
) == SET
)
4173 if (GET_CODE (SET_SRC (exp
)) == CALL
)
4175 else if (ADDRESS_REG_P (SET_DEST (exp
)))
4177 if (cc_status
.value1
&& modified_in_p (cc_status
.value1
, insn
))
4178 cc_status
.value1
= 0;
4179 if (cc_status
.value2
&& modified_in_p (cc_status
.value2
, insn
))
4180 cc_status
.value2
= 0;
4182 /* fmoves to memory or data registers do not set the condition
4183 codes. Normal moves _do_ set the condition codes, but not in
4184 a way that is appropriate for comparison with 0, because -0.0
4185 would be treated as a negative nonzero number. Note that it
4186 isn't appropriate to conditionalize this restriction on
4187 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4188 we care about the difference between -0.0 and +0.0. */
4189 else if (!FP_REG_P (SET_DEST (exp
))
4190 && SET_DEST (exp
) != cc0_rtx
4191 && (FP_REG_P (SET_SRC (exp
))
4192 || GET_CODE (SET_SRC (exp
)) == FIX
4193 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp
)))))
4195 /* A pair of move insns doesn't produce a useful overall cc. */
4196 else if (!FP_REG_P (SET_DEST (exp
))
4197 && !FP_REG_P (SET_SRC (exp
))
4198 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp
))) > 4
4199 && (GET_CODE (SET_SRC (exp
)) == REG
4200 || GET_CODE (SET_SRC (exp
)) == MEM
4201 || GET_CODE (SET_SRC (exp
)) == CONST_DOUBLE
))
4203 else if (SET_DEST (exp
) != pc_rtx
)
4205 cc_status
.flags
= 0;
4206 cc_status
.value1
= SET_DEST (exp
);
4207 cc_status
.value2
= SET_SRC (exp
);
4210 else if (GET_CODE (exp
) == PARALLEL
4211 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
4213 rtx dest
= SET_DEST (XVECEXP (exp
, 0, 0));
4214 rtx src
= SET_SRC (XVECEXP (exp
, 0, 0));
4216 if (ADDRESS_REG_P (dest
))
4218 else if (dest
!= pc_rtx
)
4220 cc_status
.flags
= 0;
4221 cc_status
.value1
= dest
;
4222 cc_status
.value2
= src
;
4227 if (cc_status
.value2
!= 0
4228 && ADDRESS_REG_P (cc_status
.value2
)
4229 && GET_MODE (cc_status
.value2
) == QImode
)
4231 if (cc_status
.value2
!= 0)
4232 switch (GET_CODE (cc_status
.value2
))
4234 case ASHIFT
: case ASHIFTRT
: case LSHIFTRT
:
4235 case ROTATE
: case ROTATERT
:
4236 /* These instructions always clear the overflow bit, and set
4237 the carry to the bit shifted out. */
4238 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
4241 case PLUS
: case MINUS
: case MULT
:
4242 case DIV
: case UDIV
: case MOD
: case UMOD
: case NEG
:
4243 if (GET_MODE (cc_status
.value2
) != VOIDmode
)
4244 cc_status
.flags
|= CC_NO_OVERFLOW
;
4247 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4248 ends with a move insn moving r2 in r2's mode.
4249 Thus, the cc's are set for r2.
4250 This can set N bit spuriously. */
4251 cc_status
.flags
|= CC_NOT_NEGATIVE
;
4256 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
4258 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
4259 cc_status
.value2
= 0;
4260 if (((cc_status
.value1
&& FP_REG_P (cc_status
.value1
))
4261 || (cc_status
.value2
&& FP_REG_P (cc_status
.value2
))))
4262 cc_status
.flags
= CC_IN_68881
;
4263 if (cc_status
.value2
&& GET_CODE (cc_status
.value2
) == COMPARE
4264 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status
.value2
, 0))) == MODE_FLOAT
)
4266 cc_status
.flags
= CC_IN_68881
;
4267 if (!FP_REG_P (XEXP (cc_status
.value2
, 0)))
4268 cc_status
.flags
|= CC_REVERSED
;
4273 output_move_const_double (rtx
*operands
)
4275 int code
= standard_68881_constant_p (operands
[1]);
4279 static char buf
[40];
4281 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4284 return "fmove%.d %1,%0";
4288 output_move_const_single (rtx
*operands
)
4290 int code
= standard_68881_constant_p (operands
[1]);
4294 static char buf
[40];
4296 sprintf (buf
, "fmovecr #0x%x,%%0", code
& 0xff);
4299 return "fmove%.s %f1,%0";
4302 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4303 from the "fmovecr" instruction.
4304 The value, anded with 0xff, gives the code to use in fmovecr
4305 to get the desired constant. */
4307 /* This code has been fixed for cross-compilation. */
4309 static int inited_68881_table
= 0;
4311 static const char *const strings_68881
[7] = {
4321 static const int codes_68881
[7] = {
4331 REAL_VALUE_TYPE values_68881
[7];
4333 /* Set up values_68881 array by converting the decimal values
4334 strings_68881 to binary. */
4337 init_68881_table (void)
4341 enum machine_mode mode
;
4344 for (i
= 0; i
< 7; i
++)
4348 r
= REAL_VALUE_ATOF (strings_68881
[i
], mode
);
4349 values_68881
[i
] = r
;
4351 inited_68881_table
= 1;
4355 standard_68881_constant_p (rtx x
)
4360 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4361 used at all on those chips. */
4365 if (! inited_68881_table
)
4366 init_68881_table ();
4368 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4370 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0
4372 for (i
= 0; i
< 6; i
++)
4374 if (REAL_VALUES_IDENTICAL (r
, values_68881
[i
]))
4375 return (codes_68881
[i
]);
4378 if (GET_MODE (x
) == SFmode
)
4381 if (REAL_VALUES_EQUAL (r
, values_68881
[6]))
4382 return (codes_68881
[6]);
4384 /* larger powers of ten in the constants ram are not used
4385 because they are not equal to a `double' C constant. */
4389 /* If X is a floating-point constant, return the logarithm of X base 2,
4390 or 0 if X is not a power of 2. */
4393 floating_exact_log2 (rtx x
)
4395 REAL_VALUE_TYPE r
, r1
;
4398 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
4400 if (REAL_VALUES_LESS (r
, dconst1
))
4403 exp
= real_exponent (&r
);
4404 real_2expN (&r1
, exp
, DFmode
);
4405 if (REAL_VALUES_EQUAL (r1
, r
))
4411 /* A C compound statement to output to stdio stream STREAM the
4412 assembler syntax for an instruction operand X. X is an RTL
4415 CODE is a value that can be used to specify one of several ways
4416 of printing the operand. It is used when identical operands
4417 must be printed differently depending on the context. CODE
4418 comes from the `%' specification that was used to request
4419 printing of the operand. If the specification was just `%DIGIT'
4420 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4421 is the ASCII code for LTR.
4423 If X is a register, this macro should print the register's name.
4424 The names can be found in an array `reg_names' whose type is
4425 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4427 When the machine description has a specification `%PUNCT' (a `%'
4428 followed by a punctuation character), this macro is called with
4429 a null pointer for X and the punctuation character for CODE.
4431 The m68k specific codes are:
4433 '.' for dot needed in Motorola-style opcode names.
4434 '-' for an operand pushing on the stack:
4435 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4436 '+' for an operand pushing on the stack:
4437 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4438 '@' for a reference to the top word on the stack:
4439 sp@, (sp) or (%sp) depending on the style of syntax.
4440 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4441 but & in SGS syntax).
4442 '!' for the cc register (used in an `and to cc' insn).
4443 '$' for the letter `s' in an op code, but only on the 68040.
4444 '&' for the letter `d' in an op code, but only on the 68040.
4445 '/' for register prefix needed by longlong.h.
4446 '?' for m68k_library_id_string
4448 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4449 'd' to force memory addressing to be absolute, not relative.
4450 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4451 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4452 or print pair of registers as rx:ry.
4453 'p' print an address with @PLTPC attached, but only if the operand
4454 is not locally-bound. */
4457 print_operand (FILE *file
, rtx op
, int letter
)
4462 fprintf (file
, ".");
4464 else if (letter
== '#')
4465 asm_fprintf (file
, "%I");
4466 else if (letter
== '-')
4467 asm_fprintf (file
, MOTOROLA
? "-(%Rsp)" : "%Rsp@-");
4468 else if (letter
== '+')
4469 asm_fprintf (file
, MOTOROLA
? "(%Rsp)+" : "%Rsp@+");
4470 else if (letter
== '@')
4471 asm_fprintf (file
, MOTOROLA
? "(%Rsp)" : "%Rsp@");
4472 else if (letter
== '!')
4473 asm_fprintf (file
, "%Rfpcr");
4474 else if (letter
== '$')
4477 fprintf (file
, "s");
4479 else if (letter
== '&')
4482 fprintf (file
, "d");
4484 else if (letter
== '/')
4485 asm_fprintf (file
, "%R");
4486 else if (letter
== '?')
4487 asm_fprintf (file
, m68k_library_id_string
);
4488 else if (letter
== 'p')
4490 output_addr_const (file
, op
);
4491 if (!(GET_CODE (op
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op
)))
4492 fprintf (file
, "@PLTPC");
4494 else if (GET_CODE (op
) == REG
)
4497 /* Print out the second register name of a register pair.
4498 I.e., R (6) => 7. */
4499 fputs (M68K_REGNAME(REGNO (op
) + 1), file
);
4501 fputs (M68K_REGNAME(REGNO (op
)), file
);
4503 else if (GET_CODE (op
) == MEM
)
4505 output_address (XEXP (op
, 0));
4506 if (letter
== 'd' && ! TARGET_68020
4507 && CONSTANT_ADDRESS_P (XEXP (op
, 0))
4508 && !(GET_CODE (XEXP (op
, 0)) == CONST_INT
4509 && INTVAL (XEXP (op
, 0)) < 0x8000
4510 && INTVAL (XEXP (op
, 0)) >= -0x8000))
4511 fprintf (file
, MOTOROLA
? ".l" : ":l");
4513 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == SFmode
)
4517 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4518 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
4519 asm_fprintf (file
, "%I0x%lx", l
& 0xFFFFFFFF);
4521 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == XFmode
)
4525 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4526 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
4527 asm_fprintf (file
, "%I0x%lx%08lx%08lx", l
[0] & 0xFFFFFFFF,
4528 l
[1] & 0xFFFFFFFF, l
[2] & 0xFFFFFFFF);
4530 else if (GET_CODE (op
) == CONST_DOUBLE
&& GET_MODE (op
) == DFmode
)
4534 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
4535 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
4536 asm_fprintf (file
, "%I0x%lx%08lx", l
[0] & 0xFFFFFFFF, l
[1] & 0xFFFFFFFF);
4540 /* Use `print_operand_address' instead of `output_addr_const'
4541 to ensure that we print relevant PIC stuff. */
4542 asm_fprintf (file
, "%I");
4544 && (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
))
4545 print_operand_address (file
, op
);
4547 output_addr_const (file
, op
);
4551 /* Return string for TLS relocation RELOC. */
4554 m68k_get_reloc_decoration (enum m68k_reloc reloc
)
4556 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4557 gcc_assert (MOTOROLA
|| reloc
== RELOC_GOT
);
4564 if (flag_pic
== 1 && TARGET_68020
)
4605 /* m68k implementation of OUTPUT_ADDR_CONST_EXTRA. */
4608 m68k_output_addr_const_extra (FILE *file
, rtx x
)
4610 if (GET_CODE (x
) == UNSPEC
)
4612 switch (XINT (x
, 1))
4614 case UNSPEC_RELOC16
:
4615 case UNSPEC_RELOC32
:
4616 output_addr_const (file
, XVECEXP (x
, 0, 0));
4617 fputs (m68k_get_reloc_decoration
4618 ((enum m68k_reloc
) INTVAL (XVECEXP (x
, 0, 1))), file
);
4629 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4632 m68k_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4634 gcc_assert (size
== 4);
4635 fputs ("\t.long\t", file
);
4636 output_addr_const (file
, x
);
4637 fputs ("@TLSLDO+0x8000", file
);
4640 /* In the name of slightly smaller debug output, and to cater to
4641 general assembler lossage, recognize various UNSPEC sequences
4642 and turn them back into a direct symbol reference. */
4645 m68k_delegitimize_address (rtx orig_x
)
4648 struct m68k_address addr
;
4651 orig_x
= delegitimize_mem_from_attrs (orig_x
);
4656 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
4659 if (!m68k_decompose_address (GET_MODE (x
), x
, false, &addr
)
4660 || addr
.offset
== NULL_RTX
4661 || GET_CODE (addr
.offset
) != CONST
)
4664 unspec
= XEXP (addr
.offset
, 0);
4665 if (GET_CODE (unspec
) == PLUS
&& CONST_INT_P (XEXP (unspec
, 1)))
4666 unspec
= XEXP (unspec
, 0);
4667 if (GET_CODE (unspec
) != UNSPEC
4668 || (XINT (unspec
, 1) != UNSPEC_RELOC16
4669 && XINT (unspec
, 1) != UNSPEC_RELOC32
))
4671 x
= XVECEXP (unspec
, 0, 0);
4672 gcc_assert (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
);
4673 if (unspec
!= XEXP (addr
.offset
, 0))
4674 x
= gen_rtx_PLUS (Pmode
, x
, XEXP (XEXP (addr
.offset
, 0), 1));
4677 rtx idx
= addr
.index
;
4678 if (addr
.scale
!= 1)
4679 idx
= gen_rtx_MULT (Pmode
, idx
, GEN_INT (addr
.scale
));
4680 x
= gen_rtx_PLUS (Pmode
, idx
, x
);
4683 x
= gen_rtx_PLUS (Pmode
, addr
.base
, x
);
4685 x
= replace_equiv_address_nv (orig_x
, x
);
4690 /* A C compound statement to output to stdio stream STREAM the
4691 assembler syntax for an instruction operand that is a memory
4692 reference whose address is ADDR. ADDR is an RTL expression.
4694 Note that this contains a kludge that knows that the only reason
4695 we have an address (plus (label_ref...) (reg...)) when not generating
4696 PIC code is in the insn before a tablejump, and we know that m68k.md
4697 generates a label LInnn: on such an insn.
4699 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4700 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4702 This routine is responsible for distinguishing between -fpic and -fPIC
4703 style relocations in an address. When generating -fpic code the
4704 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4705 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4708 print_operand_address (FILE *file
, rtx addr
)
4710 struct m68k_address address
;
4712 if (!m68k_decompose_address (QImode
, addr
, true, &address
))
4715 if (address
.code
== PRE_DEC
)
4716 fprintf (file
, MOTOROLA
? "-(%s)" : "%s@-",
4717 M68K_REGNAME (REGNO (address
.base
)));
4718 else if (address
.code
== POST_INC
)
4719 fprintf (file
, MOTOROLA
? "(%s)+" : "%s@+",
4720 M68K_REGNAME (REGNO (address
.base
)));
4721 else if (!address
.base
&& !address
.index
)
4723 /* A constant address. */
4724 gcc_assert (address
.offset
== addr
);
4725 if (GET_CODE (addr
) == CONST_INT
)
4727 /* (xxx).w or (xxx).l. */
4728 if (IN_RANGE (INTVAL (addr
), -0x8000, 0x7fff))
4729 fprintf (file
, MOTOROLA
? "%d.w" : "%d:w", (int) INTVAL (addr
));
4731 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (addr
));
4733 else if (TARGET_PCREL
)
4735 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4737 output_addr_const (file
, addr
);
4738 asm_fprintf (file
, flag_pic
== 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4742 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4743 name ends in `.<letter>', as the last 2 characters can be
4744 mistaken as a size suffix. Put the name in parentheses. */
4745 if (GET_CODE (addr
) == SYMBOL_REF
4746 && strlen (XSTR (addr
, 0)) > 2
4747 && XSTR (addr
, 0)[strlen (XSTR (addr
, 0)) - 2] == '.')
4750 output_addr_const (file
, addr
);
4754 output_addr_const (file
, addr
);
4761 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4762 label being accessed, otherwise it is -1. */
4763 labelno
= (address
.offset
4765 && GET_CODE (address
.offset
) == LABEL_REF
4766 ? CODE_LABEL_NUMBER (XEXP (address
.offset
, 0))
4770 /* Print the "offset(base" component. */
4772 asm_fprintf (file
, "%LL%d(%Rpc,", labelno
);
4776 output_addr_const (file
, address
.offset
);
4780 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4782 /* Print the ",index" component, if any. */
4787 fprintf (file
, "%s.%c",
4788 M68K_REGNAME (REGNO (address
.index
)),
4789 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4790 if (address
.scale
!= 1)
4791 fprintf (file
, "*%d", address
.scale
);
4795 else /* !MOTOROLA */
4797 if (!address
.offset
&& !address
.index
)
4798 fprintf (file
, "%s@", M68K_REGNAME (REGNO (address
.base
)));
4801 /* Print the "base@(offset" component. */
4803 asm_fprintf (file
, "%Rpc@(%LL%d", labelno
);
4807 fputs (M68K_REGNAME (REGNO (address
.base
)), file
);
4808 fprintf (file
, "@(");
4810 output_addr_const (file
, address
.offset
);
4812 /* Print the ",index" component, if any. */
4815 fprintf (file
, ",%s:%c",
4816 M68K_REGNAME (REGNO (address
.index
)),
4817 GET_MODE (address
.index
) == HImode
? 'w' : 'l');
4818 if (address
.scale
!= 1)
4819 fprintf (file
, ":%d", address
.scale
);
4827 /* Check for cases where a clr insns can be omitted from code using
4828 strict_low_part sets. For example, the second clrl here is not needed:
4829 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4831 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4832 insn we are checking for redundancy. TARGET is the register set by the
4836 strict_low_part_peephole_ok (enum machine_mode mode
, rtx first_insn
,
4841 while ((p
= PREV_INSN (p
)))
4843 if (NOTE_INSN_BASIC_BLOCK_P (p
))
4849 /* If it isn't an insn, then give up. */
4853 if (reg_set_p (target
, p
))
4855 rtx set
= single_set (p
);
4858 /* If it isn't an easy to recognize insn, then give up. */
4862 dest
= SET_DEST (set
);
4864 /* If this sets the entire target register to zero, then our
4865 first_insn is redundant. */
4866 if (rtx_equal_p (dest
, target
)
4867 && SET_SRC (set
) == const0_rtx
)
4869 else if (GET_CODE (dest
) == STRICT_LOW_PART
4870 && GET_CODE (XEXP (dest
, 0)) == REG
4871 && REGNO (XEXP (dest
, 0)) == REGNO (target
)
4872 && (GET_MODE_SIZE (GET_MODE (XEXP (dest
, 0)))
4873 <= GET_MODE_SIZE (mode
)))
4874 /* This is a strict low part set which modifies less than
4875 we are using, so it is safe. */
4885 /* Operand predicates for implementing asymmetric pc-relative addressing
4886 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4887 when used as a source operand, but not as a destination operand.
4889 We model this by restricting the meaning of the basic predicates
4890 (general_operand, memory_operand, etc) to forbid the use of this
4891 addressing mode, and then define the following predicates that permit
4892 this addressing mode. These predicates can then be used for the
4893 source operands of the appropriate instructions.
4895 n.b. While it is theoretically possible to change all machine patterns
4896 to use this addressing more where permitted by the architecture,
4897 it has only been implemented for "common" cases: SImode, HImode, and
4898 QImode operands, and only for the principle operations that would
4899 require this addressing mode: data movement and simple integer operations.
4901 In parallel with these new predicates, two new constraint letters
4902 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4903 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4904 In the pcrel case 's' is only valid in combination with 'a' registers.
4905 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4906 of how these constraints are used.
4908 The use of these predicates is strictly optional, though patterns that
4909 don't will cause an extra reload register to be allocated where one
4912 lea (abc:w,%pc),%a0 ; need to reload address
4913 moveq &1,%d1 ; since write to pc-relative space
4914 movel %d1,%a0@ ; is not allowed
4916 lea (abc:w,%pc),%a1 ; no need to reload address here
4917 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4919 For more info, consult tiemann@cygnus.com.
4922 All of the ugliness with predicates and constraints is due to the
4923 simple fact that the m68k does not allow a pc-relative addressing
4924 mode as a destination. gcc does not distinguish between source and
4925 destination addresses. Hence, if we claim that pc-relative address
4926 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4927 end up with invalid code. To get around this problem, we left
4928 pc-relative modes as invalid addresses, and then added special
4929 predicates and constraints to accept them.
4931 A cleaner way to handle this is to modify gcc to distinguish
4932 between source and destination addresses. We can then say that
4933 pc-relative is a valid source address but not a valid destination
4934 address, and hopefully avoid a lot of the predicate and constraint
4935 hackery. Unfortunately, this would be a pretty big change. It would
4936 be a useful change for a number of ports, but there aren't any current
4937 plans to undertake this.
4939 ***************************************************************************/
4943 output_andsi3 (rtx
*operands
)
4946 if (GET_CODE (operands
[2]) == CONST_INT
4947 && (INTVAL (operands
[2]) | 0xffff) == -1
4948 && (DATA_REG_P (operands
[0])
4949 || offsettable_memref_p (operands
[0]))
4950 && !TARGET_COLDFIRE
)
4952 if (GET_CODE (operands
[0]) != REG
)
4953 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4954 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0xffff);
4955 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4957 if (operands
[2] == const0_rtx
)
4959 return "and%.w %2,%0";
4961 if (GET_CODE (operands
[2]) == CONST_INT
4962 && (logval
= exact_log2 (~ INTVAL (operands
[2]) & 0xffffffff)) >= 0
4963 && (DATA_REG_P (operands
[0])
4964 || offsettable_memref_p (operands
[0])))
4966 if (DATA_REG_P (operands
[0]))
4967 operands
[1] = GEN_INT (logval
);
4970 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
4971 operands
[1] = GEN_INT (logval
% 8);
4973 /* This does not set condition codes in a standard way. */
4975 return "bclr %1,%0";
4977 return "and%.l %2,%0";
4981 output_iorsi3 (rtx
*operands
)
4983 register int logval
;
4984 if (GET_CODE (operands
[2]) == CONST_INT
4985 && INTVAL (operands
[2]) >> 16 == 0
4986 && (DATA_REG_P (operands
[0])
4987 || offsettable_memref_p (operands
[0]))
4988 && !TARGET_COLDFIRE
)
4990 if (GET_CODE (operands
[0]) != REG
)
4991 operands
[0] = adjust_address (operands
[0], HImode
, 2);
4992 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4994 if (INTVAL (operands
[2]) == 0xffff)
4995 return "mov%.w %2,%0";
4996 return "or%.w %2,%0";
4998 if (GET_CODE (operands
[2]) == CONST_INT
4999 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5000 && (DATA_REG_P (operands
[0])
5001 || offsettable_memref_p (operands
[0])))
5003 if (DATA_REG_P (operands
[0]))
5004 operands
[1] = GEN_INT (logval
);
5007 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5008 operands
[1] = GEN_INT (logval
% 8);
5011 return "bset %1,%0";
5013 return "or%.l %2,%0";
5017 output_xorsi3 (rtx
*operands
)
5019 register int logval
;
5020 if (GET_CODE (operands
[2]) == CONST_INT
5021 && INTVAL (operands
[2]) >> 16 == 0
5022 && (offsettable_memref_p (operands
[0]) || DATA_REG_P (operands
[0]))
5023 && !TARGET_COLDFIRE
)
5025 if (! DATA_REG_P (operands
[0]))
5026 operands
[0] = adjust_address (operands
[0], HImode
, 2);
5027 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5029 if (INTVAL (operands
[2]) == 0xffff)
5031 return "eor%.w %2,%0";
5033 if (GET_CODE (operands
[2]) == CONST_INT
5034 && (logval
= exact_log2 (INTVAL (operands
[2]) & 0xffffffff)) >= 0
5035 && (DATA_REG_P (operands
[0])
5036 || offsettable_memref_p (operands
[0])))
5038 if (DATA_REG_P (operands
[0]))
5039 operands
[1] = GEN_INT (logval
);
5042 operands
[0] = adjust_address (operands
[0], SImode
, 3 - (logval
/ 8));
5043 operands
[1] = GEN_INT (logval
% 8);
5046 return "bchg %1,%0";
5048 return "eor%.l %2,%0";
5051 /* Return the instruction that should be used for a call to address X,
5052 which is known to be in operand 0. */
5057 if (symbolic_operand (x
, VOIDmode
))
5058 return m68k_symbolic_call
;
5063 /* Likewise sibling calls. */
5066 output_sibcall (rtx x
)
5068 if (symbolic_operand (x
, VOIDmode
))
5069 return m68k_symbolic_jump
;
5075 m68k_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
5076 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
5079 rtx this_slot
, offset
, addr
, mem
, insn
, tmp
;
5081 /* Avoid clobbering the struct value reg by using the
5082 static chain reg as a temporary. */
5083 tmp
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
5085 /* Pretend to be a post-reload pass while generating rtl. */
5086 reload_completed
= 1;
5088 /* The "this" pointer is stored at 4(%sp). */
5089 this_slot
= gen_rtx_MEM (Pmode
, plus_constant (stack_pointer_rtx
, 4));
5091 /* Add DELTA to THIS. */
5094 /* Make the offset a legitimate operand for memory addition. */
5095 offset
= GEN_INT (delta
);
5096 if ((delta
< -8 || delta
> 8)
5097 && (TARGET_COLDFIRE
|| USE_MOVQ (delta
)))
5099 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
), offset
);
5100 offset
= gen_rtx_REG (Pmode
, D0_REG
);
5102 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5103 copy_rtx (this_slot
), offset
));
5106 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5107 if (vcall_offset
!= 0)
5109 /* Set the static chain register to *THIS. */
5110 emit_move_insn (tmp
, this_slot
);
5111 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
5113 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5114 addr
= plus_constant (tmp
, vcall_offset
);
5115 if (!m68k_legitimate_address_p (Pmode
, addr
, true))
5117 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, addr
));
5121 /* Load the offset into %d0 and add it to THIS. */
5122 emit_move_insn (gen_rtx_REG (Pmode
, D0_REG
),
5123 gen_rtx_MEM (Pmode
, addr
));
5124 emit_insn (gen_add3_insn (copy_rtx (this_slot
),
5125 copy_rtx (this_slot
),
5126 gen_rtx_REG (Pmode
, D0_REG
)));
5129 /* Jump to the target function. Use a sibcall if direct jumps are
5130 allowed, otherwise load the address into a register first. */
5131 mem
= DECL_RTL (function
);
5132 if (!sibcall_operand (XEXP (mem
, 0), VOIDmode
))
5134 gcc_assert (flag_pic
);
5136 if (!TARGET_SEP_DATA
)
5138 /* Use the static chain register as a temporary (call-clobbered)
5139 GOT pointer for this function. We can use the static chain
5140 register because it isn't live on entry to the thunk. */
5141 SET_REGNO (pic_offset_table_rtx
, STATIC_CHAIN_REGNUM
);
5142 emit_insn (gen_load_got (pic_offset_table_rtx
));
5144 legitimize_pic_address (XEXP (mem
, 0), Pmode
, tmp
);
5145 mem
= replace_equiv_address (mem
, tmp
);
5147 insn
= emit_call_insn (gen_sibcall (mem
, const0_rtx
));
5148 SIBLING_CALL_P (insn
) = 1;
5150 /* Run just enough of rest_of_compilation. */
5151 insn
= get_insns ();
5152 split_all_insns_noflow ();
5153 final_start_function (insn
, file
, 1);
5154 final (insn
, file
, 1);
5155 final_end_function ();
5157 /* Clean up the vars set above. */
5158 reload_completed
= 0;
5160 /* Restore the original PIC register. */
5162 SET_REGNO (pic_offset_table_rtx
, PIC_REG
);
5165 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5168 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
5169 int incoming ATTRIBUTE_UNUSED
)
5171 return gen_rtx_REG (Pmode
, M68K_STRUCT_VALUE_REGNUM
);
5174 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5176 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED
,
5177 unsigned int new_reg
)
5180 /* Interrupt functions can only use registers that have already been
5181 saved by the prologue, even if they would normally be
5184 if ((m68k_get_function_kind (current_function_decl
)
5185 == m68k_fk_interrupt_handler
)
5186 && !df_regs_ever_live_p (new_reg
))
5192 /* Value is true if hard register REGNO can hold a value of machine-mode
5193 MODE. On the 68000, we let the cpu registers can hold any mode, but
5194 restrict the 68881 registers to floating-point modes. */
5197 m68k_regno_mode_ok (int regno
, enum machine_mode mode
)
5199 if (DATA_REGNO_P (regno
))
5201 /* Data Registers, can hold aggregate if fits in. */
5202 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 8)
5205 else if (ADDRESS_REGNO_P (regno
))
5207 if (regno
+ GET_MODE_SIZE (mode
) / 4 <= 16)
5210 else if (FP_REGNO_P (regno
))
5212 /* FPU registers, hold float or complex float of long double or
5214 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5215 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5216 && GET_MODE_UNIT_SIZE (mode
) <= TARGET_FP_REG_SIZE
)
5222 /* Implement SECONDARY_RELOAD_CLASS. */
5225 m68k_secondary_reload_class (enum reg_class rclass
,
5226 enum machine_mode mode
, rtx x
)
5230 regno
= true_regnum (x
);
5232 /* If one operand of a movqi is an address register, the other
5233 operand must be a general register or constant. Other types
5234 of operand must be reloaded through a data register. */
5235 if (GET_MODE_SIZE (mode
) == 1
5236 && reg_classes_intersect_p (rclass
, ADDR_REGS
)
5237 && !(INT_REGNO_P (regno
) || CONSTANT_P (x
)))
5240 /* PC-relative addresses must be loaded into an address register first. */
5242 && !reg_class_subset_p (rclass
, ADDR_REGS
)
5243 && symbolic_operand (x
, VOIDmode
))
5249 /* Implement PREFERRED_RELOAD_CLASS. */
5252 m68k_preferred_reload_class (rtx x
, enum reg_class rclass
)
5254 enum reg_class secondary_class
;
5256 /* If RCLASS might need a secondary reload, try restricting it to
5257 a class that doesn't. */
5258 secondary_class
= m68k_secondary_reload_class (rclass
, GET_MODE (x
), x
);
5259 if (secondary_class
!= NO_REGS
5260 && reg_class_subset_p (secondary_class
, rclass
))
5261 return secondary_class
;
5263 /* Prefer to use moveq for in-range constants. */
5264 if (GET_CODE (x
) == CONST_INT
5265 && reg_class_subset_p (DATA_REGS
, rclass
)
5266 && IN_RANGE (INTVAL (x
), -0x80, 0x7f))
5269 /* ??? Do we really need this now? */
5270 if (GET_CODE (x
) == CONST_DOUBLE
5271 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
5273 if (TARGET_HARD_FLOAT
&& reg_class_subset_p (FP_REGS
, rclass
))
5282 /* Return floating point values in a 68881 register. This makes 68881 code
5283 a little bit faster. It also makes -msoft-float code incompatible with
5284 hard-float code, so people have to be careful not to mix the two.
5285 For ColdFire it was decided the ABI incompatibility is undesirable.
5286 If there is need for a hard-float ABI it is probably worth doing it
5287 properly and also passing function arguments in FP registers. */
5289 m68k_libcall_value (enum machine_mode mode
)
5296 return gen_rtx_REG (mode
, FP0_REG
);
5302 return gen_rtx_REG (mode
, m68k_libcall_value_in_a0_p
? A0_REG
: D0_REG
);
5305 /* Location in which function value is returned.
5306 NOTE: Due to differences in ABIs, don't call this function directly,
5307 use FUNCTION_VALUE instead. */
5309 m68k_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
)
5311 enum machine_mode mode
;
5313 mode
= TYPE_MODE (valtype
);
5319 return gen_rtx_REG (mode
, FP0_REG
);
5325 /* If the function returns a pointer, push that into %a0. */
5326 if (func
&& POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func
))))
5327 /* For compatibility with the large body of existing code which
5328 does not always properly declare external functions returning
5329 pointer types, the m68k/SVR4 convention is to copy the value
5330 returned for pointer functions from a0 to d0 in the function
5331 epilogue, so that callers that have neglected to properly
5332 declare the callee can still find the correct return value in
5334 return gen_rtx_PARALLEL
5337 gen_rtx_EXPR_LIST (VOIDmode
,
5338 gen_rtx_REG (mode
, A0_REG
),
5340 gen_rtx_EXPR_LIST (VOIDmode
,
5341 gen_rtx_REG (mode
, D0_REG
),
5343 else if (POINTER_TYPE_P (valtype
))
5344 return gen_rtx_REG (mode
, A0_REG
);
5346 return gen_rtx_REG (mode
, D0_REG
);
5349 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5350 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5352 m68k_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
5354 enum machine_mode mode
= TYPE_MODE (type
);
5356 if (mode
== BLKmode
)
5359 /* If TYPE's known alignment is less than the alignment of MODE that
5360 would contain the structure, then return in memory. We need to
5361 do so to maintain the compatibility between code compiled with
5362 -mstrict-align and that compiled with -mno-strict-align. */
5363 if (AGGREGATE_TYPE_P (type
)
5364 && TYPE_ALIGN (type
) < GET_MODE_ALIGNMENT (mode
))
5371 /* CPU to schedule the program for. */
5372 enum attr_cpu m68k_sched_cpu
;
5374 /* MAC to schedule the program for. */
5375 enum attr_mac m68k_sched_mac
;
5383 /* Integer register. */
5389 /* Implicit mem reference (e.g. stack). */
5392 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5395 /* Memory with offset but without indexing. EA mode 5. */
5398 /* Memory with indexing. EA mode 6. */
5401 /* Memory referenced by absolute address. EA mode 7. */
5404 /* Immediate operand that doesn't require extension word. */
5407 /* Immediate 16 bit operand. */
5410 /* Immediate 32 bit operand. */
5414 /* Return type of memory ADDR_RTX refers to. */
5415 static enum attr_op_type
5416 sched_address_type (enum machine_mode mode
, rtx addr_rtx
)
5418 struct m68k_address address
;
5420 if (symbolic_operand (addr_rtx
, VOIDmode
))
5421 return OP_TYPE_MEM7
;
5423 if (!m68k_decompose_address (mode
, addr_rtx
,
5424 reload_completed
, &address
))
5426 gcc_assert (!reload_completed
);
5427 /* Reload will likely fix the address to be in the register. */
5428 return OP_TYPE_MEM234
;
5431 if (address
.scale
!= 0)
5432 return OP_TYPE_MEM6
;
5434 if (address
.base
!= NULL_RTX
)
5436 if (address
.offset
== NULL_RTX
)
5437 return OP_TYPE_MEM234
;
5439 return OP_TYPE_MEM5
;
5442 gcc_assert (address
.offset
!= NULL_RTX
);
5444 return OP_TYPE_MEM7
;
5447 /* Return X or Y (depending on OPX_P) operand of INSN. */
5449 sched_get_operand (rtx insn
, bool opx_p
)
5453 if (recog_memoized (insn
) < 0)
5456 extract_constrain_insn_cached (insn
);
5459 i
= get_attr_opx (insn
);
5461 i
= get_attr_opy (insn
);
5463 if (i
>= recog_data
.n_operands
)
5466 return recog_data
.operand
[i
];
5469 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5470 If ADDRESS_P is true, return type of memory location operand refers to. */
5471 static enum attr_op_type
5472 sched_attr_op_type (rtx insn
, bool opx_p
, bool address_p
)
5476 op
= sched_get_operand (insn
, opx_p
);
5480 gcc_assert (!reload_completed
);
5485 return sched_address_type (QImode
, op
);
5487 if (memory_operand (op
, VOIDmode
))
5488 return sched_address_type (GET_MODE (op
), XEXP (op
, 0));
5490 if (register_operand (op
, VOIDmode
))
5492 if ((!reload_completed
&& FLOAT_MODE_P (GET_MODE (op
)))
5493 || (reload_completed
&& FP_REG_P (op
)))
5499 if (GET_CODE (op
) == CONST_INT
)
5505 /* Check for quick constants. */
5506 switch (get_attr_type (insn
))
5509 if (IN_RANGE (ival
, 1, 8) || IN_RANGE (ival
, -8, -1))
5510 return OP_TYPE_IMM_Q
;
5512 gcc_assert (!reload_completed
);
5516 if (USE_MOVQ (ival
))
5517 return OP_TYPE_IMM_Q
;
5519 gcc_assert (!reload_completed
);
5523 if (valid_mov3q_const (ival
))
5524 return OP_TYPE_IMM_Q
;
5526 gcc_assert (!reload_completed
);
5533 if (IN_RANGE (ival
, -0x8000, 0x7fff))
5534 return OP_TYPE_IMM_W
;
5536 return OP_TYPE_IMM_L
;
5539 if (GET_CODE (op
) == CONST_DOUBLE
)
5541 switch (GET_MODE (op
))
5544 return OP_TYPE_IMM_W
;
5548 return OP_TYPE_IMM_L
;
5555 if (GET_CODE (op
) == CONST
5556 || symbolic_operand (op
, VOIDmode
)
5559 switch (GET_MODE (op
))
5562 return OP_TYPE_IMM_Q
;
5565 return OP_TYPE_IMM_W
;
5568 return OP_TYPE_IMM_L
;
5571 if (symbolic_operand (m68k_unwrap_symbol (op
, false), VOIDmode
))
5573 return OP_TYPE_IMM_W
;
5575 return OP_TYPE_IMM_L
;
5579 gcc_assert (!reload_completed
);
5581 if (FLOAT_MODE_P (GET_MODE (op
)))
5587 /* Implement opx_type attribute.
5588 Return type of INSN's operand X.
5589 If ADDRESS_P is true, return type of memory location operand refers to. */
5591 m68k_sched_attr_opx_type (rtx insn
, int address_p
)
5593 switch (sched_attr_op_type (insn
, true, address_p
!= 0))
5599 return OPX_TYPE_FPN
;
5602 return OPX_TYPE_MEM1
;
5604 case OP_TYPE_MEM234
:
5605 return OPX_TYPE_MEM234
;
5608 return OPX_TYPE_MEM5
;
5611 return OPX_TYPE_MEM6
;
5614 return OPX_TYPE_MEM7
;
5617 return OPX_TYPE_IMM_Q
;
5620 return OPX_TYPE_IMM_W
;
5623 return OPX_TYPE_IMM_L
;
5630 /* Implement opy_type attribute.
5631 Return type of INSN's operand Y.
5632 If ADDRESS_P is true, return type of memory location operand refers to. */
5634 m68k_sched_attr_opy_type (rtx insn
, int address_p
)
5636 switch (sched_attr_op_type (insn
, false, address_p
!= 0))
5642 return OPY_TYPE_FPN
;
5645 return OPY_TYPE_MEM1
;
5647 case OP_TYPE_MEM234
:
5648 return OPY_TYPE_MEM234
;
5651 return OPY_TYPE_MEM5
;
5654 return OPY_TYPE_MEM6
;
5657 return OPY_TYPE_MEM7
;
5660 return OPY_TYPE_IMM_Q
;
5663 return OPY_TYPE_IMM_W
;
5666 return OPY_TYPE_IMM_L
;
5673 /* Return size of INSN as int. */
5675 sched_get_attr_size_int (rtx insn
)
5679 switch (get_attr_type (insn
))
5682 /* There should be no references to m68k_sched_attr_size for 'ignore'
5696 switch (get_attr_opx_type (insn
))
5702 case OPX_TYPE_MEM234
:
5703 case OPY_TYPE_IMM_Q
:
5708 /* Here we assume that most absolute references are short. */
5710 case OPY_TYPE_IMM_W
:
5714 case OPY_TYPE_IMM_L
:
5722 switch (get_attr_opy_type (insn
))
5728 case OPY_TYPE_MEM234
:
5729 case OPY_TYPE_IMM_Q
:
5734 /* Here we assume that most absolute references are short. */
5736 case OPY_TYPE_IMM_W
:
5740 case OPY_TYPE_IMM_L
:
5750 gcc_assert (!reload_completed
);
5758 /* Return size of INSN as attribute enum value. */
5760 m68k_sched_attr_size (rtx insn
)
5762 switch (sched_get_attr_size_int (insn
))
5778 /* Return operand X or Y (depending on OPX_P) of INSN,
5779 if it is a MEM, or NULL overwise. */
5780 static enum attr_op_type
5781 sched_get_opxy_mem_type (rtx insn
, bool opx_p
)
5785 switch (get_attr_opx_type (insn
))
5790 case OPX_TYPE_IMM_Q
:
5791 case OPX_TYPE_IMM_W
:
5792 case OPX_TYPE_IMM_L
:
5796 case OPX_TYPE_MEM234
:
5799 return OP_TYPE_MEM1
;
5802 return OP_TYPE_MEM6
;
5810 switch (get_attr_opy_type (insn
))
5815 case OPY_TYPE_IMM_Q
:
5816 case OPY_TYPE_IMM_W
:
5817 case OPY_TYPE_IMM_L
:
5821 case OPY_TYPE_MEM234
:
5824 return OP_TYPE_MEM1
;
5827 return OP_TYPE_MEM6
;
5835 /* Implement op_mem attribute. */
5837 m68k_sched_attr_op_mem (rtx insn
)
5839 enum attr_op_type opx
;
5840 enum attr_op_type opy
;
5842 opx
= sched_get_opxy_mem_type (insn
, true);
5843 opy
= sched_get_opxy_mem_type (insn
, false);
5845 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_RN
)
5848 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM1
)
5850 switch (get_attr_opx_access (insn
))
5866 if (opy
== OP_TYPE_RN
&& opx
== OP_TYPE_MEM6
)
5868 switch (get_attr_opx_access (insn
))
5884 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_RN
)
5887 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM1
)
5889 switch (get_attr_opx_access (insn
))
5895 gcc_assert (!reload_completed
);
5900 if (opy
== OP_TYPE_MEM1
&& opx
== OP_TYPE_MEM6
)
5902 switch (get_attr_opx_access (insn
))
5908 gcc_assert (!reload_completed
);
5913 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_RN
)
5916 if (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM1
)
5918 switch (get_attr_opx_access (insn
))
5924 gcc_assert (!reload_completed
);
5929 gcc_assert (opy
== OP_TYPE_MEM6
&& opx
== OP_TYPE_MEM6
);
5930 gcc_assert (!reload_completed
);
5934 /* Jump instructions types. Indexed by INSN_UID.
5935 The same rtl insn can be expanded into different asm instructions
5936 depending on the cc0_status. To properly determine type of jump
5937 instructions we scan instruction stream and map jumps types to this
5939 static enum attr_type
*sched_branch_type
;
5941 /* Return the type of the jump insn. */
5943 m68k_sched_branch_type (rtx insn
)
5945 enum attr_type type
;
5947 type
= sched_branch_type
[INSN_UID (insn
)];
5949 gcc_assert (type
!= 0);
5954 /* Data for ColdFire V4 index bypass.
5955 Producer modifies register that is used as index in consumer with
5959 /* Producer instruction. */
5962 /* Consumer instruction. */
5965 /* Scale of indexed memory access within consumer.
5966 Or zero if bypass should not be effective at the moment. */
5968 } sched_cfv4_bypass_data
;
5970 /* An empty state that is used in m68k_sched_adjust_cost. */
5971 static state_t sched_adjust_cost_state
;
5973 /* Implement adjust_cost scheduler hook.
5974 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5976 m68k_sched_adjust_cost (rtx insn
, rtx link ATTRIBUTE_UNUSED
, rtx def_insn
,
5981 if (recog_memoized (def_insn
) < 0
5982 || recog_memoized (insn
) < 0)
5985 if (sched_cfv4_bypass_data
.scale
== 1)
5986 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5988 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5989 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5990 that the data in sched_cfv4_bypass_data is up to date. */
5991 gcc_assert (sched_cfv4_bypass_data
.pro
== def_insn
5992 && sched_cfv4_bypass_data
.con
== insn
);
5997 sched_cfv4_bypass_data
.pro
= NULL
;
5998 sched_cfv4_bypass_data
.con
= NULL
;
5999 sched_cfv4_bypass_data
.scale
= 0;
6002 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6003 && sched_cfv4_bypass_data
.con
== NULL
6004 && sched_cfv4_bypass_data
.scale
== 0);
6006 /* Don't try to issue INSN earlier than DFA permits.
6007 This is especially useful for instructions that write to memory,
6008 as their true dependence (default) latency is better to be set to 0
6009 to workaround alias analysis limitations.
6010 This is, in fact, a machine independent tweak, so, probably,
6011 it should be moved to haifa-sched.c: insn_cost (). */
6012 delay
= min_insn_conflict_delay (sched_adjust_cost_state
, def_insn
, insn
);
6019 /* Return maximal number of insns that can be scheduled on a single cycle. */
6021 m68k_sched_issue_rate (void)
6023 switch (m68k_sched_cpu
)
6039 /* Maximal length of instruction for current CPU.
6040 E.g. it is 3 for any ColdFire core. */
6041 static int max_insn_size
;
6043 /* Data to model instruction buffer of CPU. */
6046 /* True if instruction buffer model is modeled for current CPU. */
6049 /* Size of the instruction buffer in words. */
6052 /* Number of filled words in the instruction buffer. */
6055 /* Additional information about instruction buffer for CPUs that have
6056 a buffer of instruction records, rather then a plain buffer
6057 of instruction words. */
6058 struct _sched_ib_records
6060 /* Size of buffer in records. */
6063 /* Array to hold data on adjustements made to the size of the buffer. */
6066 /* Index of the above array. */
6070 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6074 static struct _sched_ib sched_ib
;
6076 /* ID of memory unit. */
6077 static int sched_mem_unit_code
;
6079 /* Implementation of the targetm.sched.variable_issue () hook.
6080 It is called after INSN was issued. It returns the number of insns
6081 that can possibly get scheduled on the current cycle.
6082 It is used here to determine the effect of INSN on the instruction
6085 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED
,
6086 int sched_verbose ATTRIBUTE_UNUSED
,
6087 rtx insn
, int can_issue_more
)
6091 if (recog_memoized (insn
) >= 0 && get_attr_type (insn
) != TYPE_IGNORE
)
6093 switch (m68k_sched_cpu
)
6097 insn_size
= sched_get_attr_size_int (insn
);
6101 insn_size
= sched_get_attr_size_int (insn
);
6103 /* ColdFire V3 and V4 cores have instruction buffers that can
6104 accumulate up to 8 instructions regardless of instructions'
6105 sizes. So we should take care not to "prefetch" 24 one-word
6106 or 12 two-words instructions.
6107 To model this behavior we temporarily decrease size of the
6108 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6112 adjust
= max_insn_size
- insn_size
;
6113 sched_ib
.size
-= adjust
;
6115 if (sched_ib
.filled
> sched_ib
.size
)
6116 sched_ib
.filled
= sched_ib
.size
;
6118 sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
] = adjust
;
6121 ++sched_ib
.records
.adjust_index
;
6122 if (sched_ib
.records
.adjust_index
== sched_ib
.records
.n_insns
)
6123 sched_ib
.records
.adjust_index
= 0;
6125 /* Undo adjustement we did 7 instructions ago. */
6127 += sched_ib
.records
.adjust
[sched_ib
.records
.adjust_index
];
6132 gcc_assert (!sched_ib
.enabled_p
);
6140 if (insn_size
> sched_ib
.filled
)
6141 /* Scheduling for register pressure does not always take DFA into
6142 account. Workaround instruction buffer not being filled enough. */
6144 gcc_assert (sched_pressure_p
);
6145 insn_size
= sched_ib
.filled
;
6150 else if (GET_CODE (PATTERN (insn
)) == ASM_INPUT
6151 || asm_noperands (PATTERN (insn
)) >= 0)
6152 insn_size
= sched_ib
.filled
;
6156 sched_ib
.filled
-= insn_size
;
6158 return can_issue_more
;
6161 /* Return how many instructions should scheduler lookahead to choose the
6164 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6166 return m68k_sched_issue_rate () - 1;
6169 /* Implementation of targetm.sched.init_global () hook.
6170 It is invoked once per scheduling pass and is used here
6171 to initialize scheduler constants. */
6173 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED
,
6174 int sched_verbose ATTRIBUTE_UNUSED
,
6175 int n_insns ATTRIBUTE_UNUSED
)
6177 /* Init branch types. */
6181 sched_branch_type
= XCNEWVEC (enum attr_type
, get_max_uid () + 1);
6183 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6186 /* !!! FIXME: Implement real scan here. */
6187 sched_branch_type
[INSN_UID (insn
)] = TYPE_BCC
;
6191 #ifdef ENABLE_CHECKING
6192 /* Check that all instructions have DFA reservations and
6193 that all instructions can be issued from a clean state. */
6198 state
= alloca (state_size ());
6200 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
6202 if (INSN_P (insn
) && recog_memoized (insn
) >= 0)
6204 gcc_assert (insn_has_dfa_reservation_p (insn
));
6206 state_reset (state
);
6207 if (state_transition (state
, insn
) >= 0)
6214 /* Setup target cpu. */
6216 /* ColdFire V4 has a set of features to keep its instruction buffer full
6217 (e.g., a separate memory bus for instructions) and, hence, we do not model
6218 buffer for this CPU. */
6219 sched_ib
.enabled_p
= (m68k_sched_cpu
!= CPU_CFV4
);
6221 switch (m68k_sched_cpu
)
6224 sched_ib
.filled
= 0;
6231 sched_ib
.records
.n_insns
= 0;
6232 sched_ib
.records
.adjust
= NULL
;
6237 sched_ib
.records
.n_insns
= 8;
6238 sched_ib
.records
.adjust
= XNEWVEC (int, sched_ib
.records
.n_insns
);
6245 sched_mem_unit_code
= get_cpu_unit_code ("cf_mem1");
6247 sched_adjust_cost_state
= xmalloc (state_size ());
6248 state_reset (sched_adjust_cost_state
);
6251 emit_insn (gen_ib ());
6252 sched_ib
.insn
= get_insns ();
6256 /* Scheduling pass is now finished. Free/reset static variables. */
6258 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED
,
6259 int verbose ATTRIBUTE_UNUSED
)
6261 sched_ib
.insn
= NULL
;
6263 free (sched_adjust_cost_state
);
6264 sched_adjust_cost_state
= NULL
;
6266 sched_mem_unit_code
= 0;
6268 free (sched_ib
.records
.adjust
);
6269 sched_ib
.records
.adjust
= NULL
;
6270 sched_ib
.records
.n_insns
= 0;
6273 free (sched_branch_type
);
6274 sched_branch_type
= NULL
;
6277 /* Implementation of targetm.sched.init () hook.
6278 It is invoked each time scheduler starts on the new block (basic block or
6279 extended basic block). */
6281 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED
,
6282 int sched_verbose ATTRIBUTE_UNUSED
,
6283 int n_insns ATTRIBUTE_UNUSED
)
6285 switch (m68k_sched_cpu
)
6293 sched_ib
.size
= sched_ib
.records
.n_insns
* max_insn_size
;
6295 memset (sched_ib
.records
.adjust
, 0,
6296 sched_ib
.records
.n_insns
* sizeof (*sched_ib
.records
.adjust
));
6297 sched_ib
.records
.adjust_index
= 0;
6301 gcc_assert (!sched_ib
.enabled_p
);
6309 if (sched_ib
.enabled_p
)
6310 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6311 the first cycle. Workaround that. */
6312 sched_ib
.filled
= -2;
6315 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6316 It is invoked just before current cycle finishes and is used here
6317 to track if instruction buffer got its two words this cycle. */
6319 m68k_sched_dfa_pre_advance_cycle (void)
6321 if (!sched_ib
.enabled_p
)
6324 if (!cpu_unit_reservation_p (curr_state
, sched_mem_unit_code
))
6326 sched_ib
.filled
+= 2;
6328 if (sched_ib
.filled
> sched_ib
.size
)
6329 sched_ib
.filled
= sched_ib
.size
;
6333 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6334 It is invoked just after new cycle begins and is used here
6335 to setup number of filled words in the instruction buffer so that
6336 instructions which won't have all their words prefetched would be
6337 stalled for a cycle. */
6339 m68k_sched_dfa_post_advance_cycle (void)
6343 if (!sched_ib
.enabled_p
)
6346 /* Setup number of prefetched instruction words in the instruction
6348 i
= max_insn_size
- sched_ib
.filled
;
6352 if (state_transition (curr_state
, sched_ib
.insn
) >= 0)
6357 /* Return X or Y (depending on OPX_P) operand of INSN,
6358 if it is an integer register, or NULL overwise. */
6360 sched_get_reg_operand (rtx insn
, bool opx_p
)
6366 if (get_attr_opx_type (insn
) == OPX_TYPE_RN
)
6368 op
= sched_get_operand (insn
, true);
6369 gcc_assert (op
!= NULL
);
6371 if (!reload_completed
&& !REG_P (op
))
6377 if (get_attr_opy_type (insn
) == OPY_TYPE_RN
)
6379 op
= sched_get_operand (insn
, false);
6380 gcc_assert (op
!= NULL
);
6382 if (!reload_completed
&& !REG_P (op
))
6390 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6393 sched_mem_operand_p (rtx insn
, bool opx_p
)
6395 switch (sched_get_opxy_mem_type (insn
, opx_p
))
6406 /* Return X or Y (depending on OPX_P) operand of INSN,
6407 if it is a MEM, or NULL overwise. */
6409 sched_get_mem_operand (rtx insn
, bool must_read_p
, bool must_write_p
)
6429 if (opy_p
&& sched_mem_operand_p (insn
, false))
6430 return sched_get_operand (insn
, false);
6432 if (opx_p
&& sched_mem_operand_p (insn
, true))
6433 return sched_get_operand (insn
, true);
6439 /* Return non-zero if PRO modifies register used as part of
6442 m68k_sched_address_bypass_p (rtx pro
, rtx con
)
6447 pro_x
= sched_get_reg_operand (pro
, true);
6451 con_mem_read
= sched_get_mem_operand (con
, true, false);
6452 gcc_assert (con_mem_read
!= NULL
);
6454 if (reg_mentioned_p (pro_x
, con_mem_read
))
6460 /* Helper function for m68k_sched_indexed_address_bypass_p.
6461 if PRO modifies register used as index in CON,
6462 return scale of indexed memory access in CON. Return zero overwise. */
6464 sched_get_indexed_address_scale (rtx pro
, rtx con
)
6468 struct m68k_address address
;
6470 reg
= sched_get_reg_operand (pro
, true);
6474 mem
= sched_get_mem_operand (con
, true, false);
6475 gcc_assert (mem
!= NULL
&& MEM_P (mem
));
6477 if (!m68k_decompose_address (GET_MODE (mem
), XEXP (mem
, 0), reload_completed
,
6481 if (REGNO (reg
) == REGNO (address
.index
))
6483 gcc_assert (address
.scale
!= 0);
6484 return address
.scale
;
6490 /* Return non-zero if PRO modifies register used
6491 as index with scale 2 or 4 in CON. */
6493 m68k_sched_indexed_address_bypass_p (rtx pro
, rtx con
)
6495 gcc_assert (sched_cfv4_bypass_data
.pro
== NULL
6496 && sched_cfv4_bypass_data
.con
== NULL
6497 && sched_cfv4_bypass_data
.scale
== 0);
6499 switch (sched_get_indexed_address_scale (pro
, con
))
6502 /* We can't have a variable latency bypass, so
6503 remember to adjust the insn cost in adjust_cost hook. */
6504 sched_cfv4_bypass_data
.pro
= pro
;
6505 sched_cfv4_bypass_data
.con
= con
;
6506 sched_cfv4_bypass_data
.scale
= 1;
6518 /* We generate a two-instructions program at M_TRAMP :
6519 movea.l &CHAIN_VALUE,%a0
6521 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6524 m68k_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
6526 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6529 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM
));
6531 mem
= adjust_address (m_tramp
, HImode
, 0);
6532 emit_move_insn (mem
, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM
-8) << 9)));
6533 mem
= adjust_address (m_tramp
, SImode
, 2);
6534 emit_move_insn (mem
, chain_value
);
6536 mem
= adjust_address (m_tramp
, HImode
, 6);
6537 emit_move_insn (mem
, GEN_INT(0x4EF9));
6538 mem
= adjust_address (m_tramp
, SImode
, 8);
6539 emit_move_insn (mem
, fnaddr
);
6541 FINALIZE_TRAMPOLINE (XEXP (m_tramp
, 0));
6544 /* On the 68000, the RTS insn cannot pop anything.
6545 On the 68010, the RTD insn may be used to pop them if the number
6546 of args is fixed, but if the number is variable then the caller
6547 must pop them all. RTD can't be used for library calls now
6548 because the library is compiled with the Unix compiler.
6549 Use of RTD is a selectable option, since it is incompatible with
6550 standard Unix calling sequences. If the option is not selected,
6551 the caller must always pop the args. */
6554 m68k_return_pops_args (tree fundecl
, tree funtype
, int size
)
6558 || TREE_CODE (fundecl
) != IDENTIFIER_NODE
)
6559 && (!stdarg_p (funtype
)))
6563 /* Make sure everything's fine if we *don't* have a given processor.
6564 This assumes that putting a register in fixed_regs will keep the
6565 compiler's mitts completely off it. We don't bother to zero it out
6566 of register classes. */
6569 m68k_conditional_register_usage (void)
6573 if (!TARGET_HARD_FLOAT
)
6575 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FP_REGS
]);
6576 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6577 if (TEST_HARD_REG_BIT (x
, i
))
6578 fixed_regs
[i
] = call_used_regs
[i
] = 1;
6581 fixed_regs
[PIC_REG
] = call_used_regs
[PIC_REG
] = 1;
6584 #include "gt-m68k.h"