1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2012
4 ;; Free Software Foundation, Inc.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- Information about MCF5200 port.
24 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
25 ;;- 68k ISA. Differences include reduced support for byte and word
26 ;;- operands and the removal of BCD, bitfield, rotate, and integer
27 ;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the
28 ;;- removed opcodes and addressing modes off.
32 ;;- instruction definitions
34 ;;- @@The original PO technology requires these to be ordered by speed,
35 ;;- @@ so that assigner will pick the fastest.
37 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
39 ;;- When naming insn's (operand 0 of define_insn) be careful about using
40 ;;- names from other targets machine descriptions.
42 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
43 ;;- updates for most instructions.
45 ;;- Operand classes for the register allocator:
46 ;;- 'a' one of the address registers can be used.
47 ;;- 'd' one of the data registers can be used.
48 ;;- 'f' one of the m68881/fpu registers can be used
49 ;;- 'r' either a data or an address register can be used.
51 ;;- Immediate Floating point operator constraints
52 ;;- 'G' a floating point constant that is *NOT* one of the standard
53 ;; 68881 constant values (to force calling output_move_const_double
54 ;; to get it from rom if it is a 68881 constant).
56 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
59 ;;- Immediate integer operand constraints:
61 ;;- 'J' -32768 .. 32767
62 ;;- 'K' all integers EXCEPT -128 .. 127
64 ;;- 'M' all integers EXCEPT -256 .. 255
70 ;;- "%." size separator ("." or "") move%.l d0,d1
71 ;;- "%-" push operand "sp@-" move%.l d0,%-
72 ;;- "%+" pop operand "sp@+" move%.l d0,%+
73 ;;- "%@" top of stack "sp@" move%.l d0,%@
74 ;;- "%!" fpcr register
75 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
76 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
78 ;;- Information about 68040 port.
80 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
81 ;;- be emulated in software by the OS. It is faster to avoid these
82 ;;- instructions and issue a library call rather than trapping into
83 ;;- the kernel. The affected instructions are fintrz and fscale. The
84 ;;- TUNE_68040 flag turns the use of the opcodes off.
86 ;;- The '040 also implements a set of new floating-point instructions
87 ;;- which specify the rounding precision in the opcode. This finally
88 ;;- permit the 68k series to be truly IEEE compliant, and solves all
89 ;;- issues of excess precision accumulating in the extended registers.
90 ;;- By default, GCC does not use these instructions, since such code will
91 ;;- not run on an '030. To use these instructions, use the -m68040-only
94 ;;- These new instructions aren't directly in the md. They are brought
95 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
98 ;;- Information about 68060 port.
100 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
101 ;;- be emulated in software by the OS. It is faster to avoid these
102 ;;- instructions and issue a library call rather than trapping into
103 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
104 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
105 ;;- fscale. The TUNE_68060 flag turns the use of the opcodes off.
107 ;;- Some of these insn's are composites of several m68000 op codes.
108 ;;- The assembler (or final @@??) insures that the appropriate one is
123 ;; UNSPEC_VOLATILE usage:
126 [(UNSPECV_BLOCKAGE 0)
133 ;; Registers by name.
144 (include "predicates.md")
145 (include "constraints.md")
147 ;; ::::::::::::::::::::
151 ;; ::::::::::::::::::::
154 (define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown"
155 (const (symbol_ref "m68k_sched_cpu")))
158 (define_attr "mac" "no, cf_mac, cf_emac"
159 (const (symbol_ref "m68k_sched_mac")))
161 ;; Instruction type for use in scheduling description.
162 ;; _l and _w suffixes indicate size of the operands of instruction.
163 ;; alu - usual arithmetic or logic instruction.
164 ;; aluq - arithmetic or logic instruction which has a quick immediate (the one
165 ;; that is encoded in the instruction word) for its Y operand.
166 ;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx).
167 ;; bcc - conditional branch.
168 ;; bitr - bit operation that only updates flags.
169 ;; bitrw - bit operation that updates flags and output operand.
170 ;; bra, bsr, clr, cmp, div, ext - corresponding instruction.
171 ;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding
173 ;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction
175 ;; ignore - fake instruction.
176 ;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction.
177 ;; mvsz - mvs or mvz instruction.
178 ;; neg, nop, pea, rts, scc - corresponding instruction.
179 ;; shift - arithmetic or logical shift instruction.
180 ;; trap, tst, unlk - corresponding instruction.
182 "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l,
184 falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst,
186 jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop,
190 (const_string "unknown"))
192 ;; Index of the X or Y operand in recog_data.operand[].
193 ;; Should be used only within opx_type and opy_type.
194 (define_attr "opx" "" (const_int 0))
195 (define_attr "opy" "" (const_int 1))
197 ;; Type of the Y operand.
198 ;; See m68k.c: enum attr_op_type.
199 (define_attr "opy_type"
200 "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
201 (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore,
202 jmp,jsr,nop,rts,scc,trap,tst,tst_l,
203 unlk,unknown") (const_string "none")
204 (eq_attr "type" "lea,pea")
205 (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")]
206 (symbol_ref "m68k_sched_attr_opy_type (insn, 0)")))
208 ;; Type of the X operand.
209 ;; See m68k.c: enum attr_op_type.
210 (define_attr "opx_type"
211 "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l"
212 (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
213 unknown") (const_string "none")
214 (eq_attr "type" "pea") (const_string "mem1")
215 (eq_attr "type" "jmp,jsr")
216 (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")]
217 (symbol_ref "m68k_sched_attr_opx_type (insn, 0)")))
219 ;; Access to the X operand: none, read, write, read/write, unknown.
220 ;; Access to the Y operand is either none (if opy_type is none)
221 ;; or read otherwise.
222 (define_attr "opx_access" "none, r, w, rw"
223 (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk,
224 unknown") (const_string "none")
225 (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst,
226 jmp,jsr,tst,tst_l") (const_string "r")
227 (eq_attr "type" "clr,clr_l,fneg,fmove,lea,
228 mov3q_l,move,move_l,moveq_l,mvsz,
229 pea,scc") (const_string "w")
230 (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext,
231 falu,fdiv,fmul,fsqrt,link,mul_w,mul_l,
232 neg_l,shift") (const_string "rw")]
233 ;; Should never be used.
234 (symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)")))
236 ;; Memory accesses of the insn.
237 ;; 00 - no memory references
238 ;; 10 - memory is read
239 ;; i0 - indexed memory is read
240 ;; 01 - memory is written
241 ;; 0i - indexed memory is written
242 ;; 11 - memory is read, memory is written
243 ;; i1 - indexed memory is read, memory is written
244 ;; 1i - memory is read, indexed memory is written
245 (define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i"
246 (symbol_ref "m68k_sched_attr_op_mem (insn)"))
248 ;; Instruction size in words.
249 (define_attr "size" "1,2,3"
250 (symbol_ref "m68k_sched_attr_size (insn)"))
252 ;; Alternative is OK for ColdFire.
253 (define_attr "ok_for_coldfire" "yes,no" (const_string "yes"))
255 ;; Define 'enabled' attribute.
256 (define_attr "enabled" ""
257 (cond [(and (match_test "TARGET_COLDFIRE")
258 (eq_attr "ok_for_coldfire" "no"))
262 ;; Mode macros for integer operations.
263 (define_mode_iterator I [QI HI SI])
264 (define_mode_attr sz [(QI "%.b") (HI "%.w") (SI "%.l")])
266 ;; Mode macros for floating point operations.
267 ;; Valid floating point modes
268 (define_mode_iterator FP [SF DF (XF "TARGET_68881")])
269 ;; Mnemonic infix to round result
270 (define_mode_attr round [(SF "%$") (DF "%&") (XF "")])
271 ;; Mnemonic infix to round result for mul or div instruction
272 (define_mode_attr round_mul [(SF "sgl") (DF "%&") (XF "")])
273 ;; Suffix specifying source operand format
274 (define_mode_attr prec [(SF "s") (DF "d") (XF "x")])
275 ;; Allowable D registers
276 (define_mode_attr dreg [(SF "d") (DF "") (XF "")])
277 ;; Allowable 68881 constant constraints
278 (define_mode_attr const [(SF "F") (DF "G") (XF "")])
281 (define_insn_and_split "*movdf_internal"
282 [(set (match_operand:DF 0 "push_operand" "=m, m")
283 (match_operand:DF 1 "general_operand" "f, ro<>E"))]
288 "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 1)"
291 m68k_emit_move_double (operands);
294 [(set_attr "type" "fmove,*")])
296 (define_insn_and_split "pushdi"
297 [(set (match_operand:DI 0 "push_operand" "=m")
298 (match_operand:DI 1 "general_operand" "ro<>Fi"))]
301 "&& reload_completed"
304 m68k_emit_move_double (operands);
308 ;; We don't want to allow a constant operand for test insns because
309 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
310 ;; be folded while optimizing anyway.
314 (compare (match_operand:DI 0 "nonimmediate_operand" "am,d")
316 (clobber (match_scratch:SI 1 "=X,d"))
317 (clobber (match_scratch:DI 2 "=d,X"))]
320 if (which_alternative == 0)
324 xoperands[0] = operands[2];
325 xoperands[1] = operands[0];
326 output_move_double (xoperands);
327 cc_status.flags |= CC_REVERSED; /*|*/
328 return "neg%.l %R2\;negx%.l %2";
330 if (find_reg_note (insn, REG_DEAD, operands[0]))
332 cc_status.flags |= CC_REVERSED; /*|*/
333 return "neg%.l %R0\;negx%.l %0";
337 'sub' clears %1, and also clears the X cc bit
338 'tst' sets the Z cc bit according to the low part of the DImode operand
339 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part.
341 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0";
344 ;; If you think that the 68020 does not support tstl a0,
345 ;; reread page B-167 of the 68020 manual more carefully.
346 (define_insn "*tstsi_internal_68020_cf"
348 (compare (match_operand:SI 0 "nonimmediate_operand" "rm")
350 "TARGET_68020 || TARGET_COLDFIRE"
352 [(set_attr "type" "tst_l")])
354 ;; On an address reg, cmpw may replace cmpl.
355 (define_insn "*tstsi_internal"
357 (compare (match_operand:SI 0 "nonimmediate_operand" "dm,r")
359 "!(TARGET_68020 || TARGET_COLDFIRE)"
363 [(set_attr "type" "tst_l,cmp")])
365 ;; This can't use an address register, because comparisons
366 ;; with address registers as second operand always test the whole word.
367 (define_insn "*tsthi_internal"
369 (compare (match_operand:HI 0 "nonimmediate_operand" "dm")
373 [(set_attr "type" "tst")])
375 (define_insn "*tstqi_internal"
377 (compare (match_operand:QI 0 "nonimmediate_operand" "dm")
381 [(set_attr "type" "tst")])
383 (define_insn "tst<mode>_68881"
385 (compare (match_operand:FP 0 "general_operand" "f<FP:dreg>m")
386 (match_operand:FP 1 "const0_operand" "H")))]
389 cc_status.flags = CC_IN_68881;
390 if (FP_REG_P (operands[0]))
392 return "ftst%.<FP:prec> %0";
394 [(set_attr "type" "ftst")])
396 (define_insn "tst<mode>_cf"
398 (compare (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U")
399 (match_operand:FP 1 "const0_operand" "H")))]
400 "TARGET_COLDFIRE_FPU"
402 cc_status.flags = CC_IN_68881;
403 if (FP_REG_P (operands[0]))
405 return "ftst%.<FP:prec> %0";
407 [(set_attr "type" "ftst")])
410 ;; compare instructions.
412 (define_insn "*cmpdi_internal"
414 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
415 (match_operand:DI 2 "general_operand" "d,0")))
416 (clobber (match_scratch:DI 0 "=d,d"))]
419 if (rtx_equal_p (operands[0], operands[1]))
420 return "sub%.l %R2,%R0\;subx%.l %2,%0";
423 cc_status.flags |= CC_REVERSED; /*|*/
424 return "sub%.l %R1,%R0\;subx%.l %1,%0";
430 (compare (match_operand:DI 0 "nonimmediate_operand")
431 (match_operand:DI 1 "general_operand")))
432 (clobber (match_scratch:DI 2))]
437 (define_expand "cbranchdi4"
439 (if_then_else (match_operator 0 "ordered_comparison_operator"
440 [(match_operand:DI 1 "nonimmediate_operand")
441 (match_operand:DI 2 "general_operand")])
442 (label_ref (match_operand 3 ""))
446 if (operands[2] == const0_rtx)
447 emit_insn (gen_tstdi (operands[1]));
449 emit_insn (gen_cmpdi (operands[1], operands[2]));
450 operands[1] = cc0_rtx;
451 operands[2] = const0_rtx;
454 (define_expand "cstoredi4"
455 [(set (match_operand:QI 0 "register_operand")
456 (match_operator:QI 1 "ordered_comparison_operator"
457 [(match_operand:DI 2 "nonimmediate_operand")
458 (match_operand:DI 3 "general_operand")]))]
461 if (operands[3] == const0_rtx)
462 emit_insn (gen_tstdi (operands[2]));
464 emit_insn (gen_cmpdi (operands[2], operands[3]));
465 operands[2] = cc0_rtx;
466 operands[3] = const0_rtx;
470 (define_expand "cbranchsi4"
472 (compare (match_operand:SI 1 "nonimmediate_operand" "")
473 (match_operand:SI 2 "general_operand" "")))
475 (if_then_else (match_operator 0 "ordered_comparison_operator"
476 [(cc0) (const_int 0)])
477 (label_ref (match_operand 3 ""))
482 (define_expand "cstoresi4"
484 (compare (match_operand:SI 2 "nonimmediate_operand" "")
485 (match_operand:SI 3 "general_operand" "")))
486 (set (match_operand:QI 0 "register_operand")
487 (match_operator:QI 1 "ordered_comparison_operator"
488 [(cc0) (const_int 0)]))]
493 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
496 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>")
497 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))]
500 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
501 return "cmpm%.l %1,%0";
502 if (REG_P (operands[1])
503 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
505 cc_status.flags |= CC_REVERSED; /*|*/
506 return "cmp%.l %d0,%d1";
508 if (ADDRESS_REG_P (operands[0])
509 && GET_CODE (operands[1]) == CONST_INT
510 && INTVAL (operands[1]) < 0x8000
511 && INTVAL (operands[1]) >= -0x8000)
512 return "cmp%.w %1,%0";
513 return "cmp%.l %d1,%d0";
516 (define_insn "*cmpsi_cf"
518 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
519 (match_operand:SI 1 "general_operand" "r,mrKs")))]
522 if (REG_P (operands[1])
523 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
525 cc_status.flags |= CC_REVERSED; /*|*/
526 return "cmp%.l %d0,%d1";
528 return "cmp%.l %d1,%d0";
530 [(set_attr "type" "cmp_l")])
532 (define_expand "cbranchhi4"
534 (compare (match_operand:HI 1 "nonimmediate_src_operand" "")
535 (match_operand:HI 2 "m68k_subword_comparison_operand" "")))
537 (if_then_else (match_operator 0 "ordered_comparison_operator"
538 [(cc0) (const_int 0)])
539 (label_ref (match_operand 3 ""))
544 (define_expand "cstorehi4"
546 (compare (match_operand:HI 2 "nonimmediate_operand" "")
547 (match_operand:HI 3 "m68k_subword_comparison_operand" "")))
548 (set (match_operand:QI 0 "register_operand")
549 (match_operator:QI 1 "ordered_comparison_operator"
550 [(cc0) (const_int 0)]))]
556 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>")
557 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))]
560 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
561 return "cmpm%.w %1,%0";
562 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
563 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
565 cc_status.flags |= CC_REVERSED; /*|*/
566 return "cmp%.w %d0,%d1";
568 return "cmp%.w %d1,%d0";
571 (define_expand "cbranchqi4"
573 (compare (match_operand:QI 1 "nonimmediate_src_operand" "")
574 (match_operand:QI 2 "m68k_subword_comparison_operand" "")))
576 (if_then_else (match_operator 0 "ordered_comparison_operator"
577 [(cc0) (const_int 0)])
578 (label_ref (match_operand 3 ""))
583 (define_expand "cstoreqi4"
585 (compare (match_operand:QI 2 "nonimmediate_src_operand" "")
586 (match_operand:QI 3 "m68k_subword_comparison_operand" "")))
587 (set (match_operand:QI 0 "register_operand")
588 (match_operator:QI 1 "ordered_comparison_operator"
589 [(cc0) (const_int 0)]))]
595 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>")
596 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))]
599 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
600 return "cmpm%.b %1,%0";
601 if (REG_P (operands[1])
602 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
604 cc_status.flags |= CC_REVERSED; /*|*/
605 return "cmp%.b %d0,%d1";
607 return "cmp%.b %d1,%d0";
610 (define_expand "cbranch<mode>4"
612 (compare (match_operand:FP 1 "register_operand" "")
613 (match_operand:FP 2 "fp_src_operand" "")))
615 (if_then_else (match_operator 0 "comparison_operator"
616 [(cc0) (const_int 0)])
617 (label_ref (match_operand 3 ""))
622 (define_expand "cstore<mode>4"
624 (compare (match_operand:FP 2 "register_operand" "")
625 (match_operand:FP 3 "fp_src_operand" "")))
626 (set (match_operand:QI 0 "register_operand")
627 (match_operator:QI 1 "m68k_cstore_comparison_operator"
628 [(cc0) (const_int 0)]))]
629 "TARGET_HARD_FLOAT && !(TUNE_68060 || TARGET_COLDFIRE_FPU)"
630 "if (TARGET_COLDFIRE && operands[2] != const0_rtx)
633 (define_insn "*cmp<mode>_68881"
635 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF")
636 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF,f")))]
638 && (register_operand (operands[0], <MODE>mode)
639 || register_operand (operands[1], <MODE>mode))"
642 fcmp%.<FP:prec> %f1,%0
643 fcmp%.<FP:prec> %0,%f1"
644 [(set_attr "type" "fcmp")])
646 (define_insn "*cmp<mode>_cf"
648 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg><Q>U")
649 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg><Q>U,f")))]
651 && (register_operand (operands[0], <MODE>mode)
652 || register_operand (operands[1], <MODE>mode))"
655 fcmp%.<FP:prec> %f1,%0
656 fcmp%.<FP:prec> %0,%f1"
657 [(set_attr "type" "fcmp")])
659 ;; Recognizers for btst instructions.
661 ;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
662 ;; specified as a constant, so we must disable all patterns that may extract
663 ;; from a MEM at a constant bit position if we can't use this as a constraint.
668 (compare (zero_extract:SI (match_operand:QI 0 "memory_src_operand" "oS")
670 (minus:SI (const_int 7)
671 (match_operand:SI 1 "general_operand" "di")))
675 return output_btst (operands, operands[1], operands[0], insn, 7);
678 ;; This is the same as the above pattern except for the constraints. The 'i'
684 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
686 (minus:SI (const_int 7)
687 (match_operand:SI 1 "general_operand" "d")))
691 return output_btst (operands, operands[1], operands[0], insn, 7);
697 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
699 (minus:SI (const_int 31)
700 (match_operand:SI 1 "general_operand" "di")))
704 return output_btst (operands, operands[1], operands[0], insn, 31);
707 ;; The following two patterns are like the previous two
708 ;; except that they use the fact that bit-number operands
709 ;; are automatically masked to 3 or 5 bits.
714 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
716 (minus:SI (const_int 7)
718 (match_operand:SI 1 "register_operand" "d")
723 return output_btst (operands, operands[1], operands[0], insn, 7);
729 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
731 (minus:SI (const_int 31)
733 (match_operand:SI 1 "register_operand" "d")
738 return output_btst (operands, operands[1], operands[0], insn, 31);
741 ;; Nonoffsettable mem refs are ok in this one pattern
742 ;; since we don't try to adjust them.
746 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
748 (match_operand:SI 1 "const_int_operand" "n"))
750 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE"
752 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
753 return output_btst (operands, operands[1], operands[0], insn, 7);
759 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do")
761 (match_operand:SI 1 "const_int_operand" "n"))
765 if (GET_CODE (operands[0]) == MEM)
767 operands[0] = adjust_address (operands[0], QImode,
768 INTVAL (operands[1]) / 8);
769 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
770 return output_btst (operands, operands[1], operands[0], insn, 7);
772 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
773 return output_btst (operands, operands[1], operands[0], insn, 31);
776 ;; This is the same as the above pattern except for the constraints.
777 ;; The 'o' has been replaced with 'Q'.
782 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dQ")
784 (match_operand:SI 1 "const_int_operand" "n"))
788 if (GET_CODE (operands[0]) == MEM)
790 operands[0] = adjust_address (operands[0], QImode,
791 INTVAL (operands[1]) / 8);
792 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
793 return output_btst (operands, operands[1], operands[0], insn, 7);
795 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
796 return output_btst (operands, operands[1], operands[0], insn, 31);
802 ;; A special case in which it is not desirable
803 ;; to reload the constant into a data register.
804 (define_insn "pushexthisi_const"
805 [(set (match_operand:SI 0 "push_operand" "=m,m,m")
806 (match_operand:SI 1 "const_int_operand" "C0,R,J"))]
807 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
812 [(set_attr "type" "clr_l,mov3q_l,pea")])
815 ;(define_insn "swapsi"
816 ; [(set (match_operand:SI 0 "nonimmediate_operand" "+r")
817 ; (match_operand:SI 1 "general_operand" "+r"))
818 ; (set (match_dup 1) (match_dup 0))]
822 ;; Special case of fullword move when source is zero for 68000_10.
823 ;; moveq is faster on the 68000.
824 (define_insn "*movsi_const0_68000_10"
825 [(set (match_operand:SI 0 "movsi_const0_operand" "=d,a,g")
832 [(set_attr "type" "moveq_l,alu_l,clr_l")
833 (set_attr "opy" "*,0,*")])
835 ;; Special case of fullword move when source is zero for 68040_60.
836 ;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1
837 (define_insn "*movsi_const0_68040_60"
838 [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
842 if (which_alternative == 0)
843 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
844 else if (which_alternative == 1)
852 [(set_attr "type" "lea,clr_l")])
854 ;; Special case of fullword move when source is zero.
855 (define_insn "*movsi_const0"
856 [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g")
858 "!(TUNE_68000_10 || TUNE_68040_60)"
862 [(set_attr "type" "alu_l,clr_l")
863 (set_attr "opy" "0,*")])
865 ;; General case of fullword move.
867 ;; This is the main "hook" for PIC code. When generating
868 ;; PIC, movsi is responsible for determining when the source address
869 ;; needs PIC relocation and appropriately calling legitimize_pic_address
870 ;; to perform the actual relocation.
872 ;; In both the PIC and non-PIC cases the patterns generated will
873 ;; matched by the next define_insn.
874 (define_expand "movsi"
875 [(set (match_operand:SI 0 "" "")
876 (match_operand:SI 1 "" ""))]
879 rtx tmp, base, offset;
881 /* Recognize the case where operand[1] is a reference to thread-local
882 data and load its address to a register. */
883 if (!TARGET_PCREL && m68k_tls_reference_p (operands[1], false))
885 rtx tmp = operands[1];
888 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
890 addend = XEXP (XEXP (tmp, 0), 1);
891 tmp = XEXP (XEXP (tmp, 0), 0);
894 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
895 gcc_assert (SYMBOL_REF_TLS_MODEL (tmp) != 0);
897 tmp = m68k_legitimize_tls_address (tmp);
905 reg = gen_reg_rtx (Pmode);
906 emit_move_insn (reg, tmp);
910 tmp = gen_rtx_PLUS (SImode, tmp, addend);
915 else if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode))
917 /* The source is an address which requires PIC relocation.
918 Call legitimize_pic_address with the source, mode, and a relocation
919 register (a new pseudo, or the final destination if reload_in_progress
920 is set). Then fall through normally */
921 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
922 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
924 else if (flag_pic && TARGET_PCREL && ! reload_in_progress)
926 /* Don't allow writes to memory except via a register;
927 the m68k doesn't consider PC-relative addresses to be writable. */
928 if (symbolic_operand (operands[0], SImode))
929 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
930 else if (GET_CODE (operands[0]) == MEM
931 && symbolic_operand (XEXP (operands[0], 0), SImode))
932 operands[0] = gen_rtx_MEM (SImode,
933 force_reg (SImode, XEXP (operands[0], 0)));
935 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
937 split_const (operands[1], &base, &offset);
938 if (GET_CODE (base) == SYMBOL_REF
939 && !offset_within_block_p (base, INTVAL (offset)))
941 tmp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (SImode);
942 emit_move_insn (tmp, base);
943 emit_insn (gen_addsi3 (operands[0], tmp, offset));
949 ;; General case of fullword move.
950 (define_insn "*movsi_m68k"
951 ;; Notes: make sure no alternative allows g vs g.
952 ;; We don't allow f-regs since fixed point cannot go in them.
953 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
954 (match_operand:SI 1 "general_src_operand" "damSnT,n,i"))]
955 "!TARGET_COLDFIRE && reload_completed"
957 return output_move_simode (operands);
960 ;; Before reload is completed the register constraints
961 ;; force integer constants in range for a moveq to be reloaded
962 ;; if they are headed for memory.
963 (define_insn "*movsi_m68k2"
964 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<")
965 (match_operand:SI 1 "general_src_operand" "damSKT,n,i"))]
969 return output_move_simode (operands);
972 ;; ColdFire move instructions can have at most one operand of mode >= 6.
973 (define_insn "*movsi_cf"
974 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d, d, d, d, d, a,Ap, a, r<Q>,g, U")
975 (match_operand:SI 1 "general_operand" " R,CQ,CW,CZ,CS,Ci,J,J Cs,Cs, g, Rr<Q>,U"))]
978 switch (which_alternative)
981 return "mov3q%.l %1,%0";
984 return "moveq %1,%0";
988 unsigned u = INTVAL (operands[1]);
990 operands[1] = GEN_INT ((u << 16) | (u >> 16)); /*|*/
991 return "moveq %1,%0\n\tswap %0";
995 return "mvz%.w %1,%0";
998 return "mvs%.w %1,%0";
1001 return "move%.l %1,%0";
1004 return "move%.w %1,%0";
1010 return "lea %a1,%0";
1015 return "move%.l %1,%0";
1022 [(set_attr "type" "mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")])
1024 ;; Special case of fullword move, where we need to get a non-GOT PIC
1025 ;; reference into an address register.
1027 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<")
1028 (match_operand:SI 1 "pcrel_address" ""))]
1031 if (push_operand (operands[0], SImode))
1033 return "lea %a1,%0";
1036 (define_expand "movhi"
1037 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1038 (match_operand:HI 1 "general_operand" ""))]
1043 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1044 (match_operand:HI 1 "general_src_operand" "gS"))]
1046 "* return output_move_himode (operands);")
1049 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
1050 (match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
1052 "* return output_move_himode (operands);")
1054 (define_expand "movstricthi"
1055 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
1056 (match_operand:HI 1 "general_src_operand" ""))]
1061 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
1062 (match_operand:HI 1 "general_src_operand" "rmSn"))]
1064 "* return output_move_stricthi (operands);")
1067 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m"))
1068 (match_operand:HI 1 "general_src_operand" "rmn,r"))]
1070 "* return output_move_stricthi (operands);")
1072 (define_expand "movqi"
1073 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1074 (match_operand:QI 1 "general_src_operand" ""))]
1079 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m")
1080 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))]
1082 "* return output_move_qimode (operands);")
1085 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
1086 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
1088 "* return output_move_qimode (operands);")
1090 (define_expand "movstrictqi"
1091 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
1092 (match_operand:QI 1 "general_src_operand" ""))]
1097 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
1098 (match_operand:QI 1 "general_src_operand" "dmSn"))]
1100 "* return output_move_strictqi (operands);")
1102 (define_insn "*movstrictqi_cf"
1103 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d, Ac, d,m"))
1104 (match_operand:QI 1 "general_src_operand" "C0,C0, dmn,d"))]
1111 [(set_attr "type" "clr,clr,move,move")])
1113 (define_expand "pushqi1"
1114 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))
1115 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1)))
1116 (match_operand:QI 0 "general_operand" ""))]
1120 (define_expand "reload_insf"
1121 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
1122 (match_operand:SF 1 "general_operand" "mf"))
1123 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1124 "TARGET_COLDFIRE_FPU"
1126 if (emit_move_sequence (operands, SFmode, operands[2]))
1129 /* We don't want the clobber emitted, so handle this ourselves. */
1130 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1134 (define_expand "reload_outsf"
1135 [(set (match_operand:SF 0 "general_operand" "")
1136 (match_operand:SF 1 "register_operand" "f"))
1137 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1138 "TARGET_COLDFIRE_FPU"
1140 if (emit_move_sequence (operands, SFmode, operands[2]))
1143 /* We don't want the clobber emitted, so handle this ourselves. */
1144 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1148 (define_expand "movsf"
1149 [(set (match_operand:SF 0 "nonimmediate_operand" "")
1150 (match_operand:SF 1 "general_operand" ""))]
1155 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf")
1156 (match_operand:SF 1 "general_operand" "rmfF"))]
1159 if (FP_REG_P (operands[0]))
1161 if (FP_REG_P (operands[1]))
1162 return "f%$move%.x %1,%0";
1163 else if (ADDRESS_REG_P (operands[1]))
1164 return "move%.l %1,%-\;f%$move%.s %+,%0";
1165 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1166 return output_move_const_single (operands);
1167 return "f%$move%.s %f1,%0";
1169 if (FP_REG_P (operands[1]))
1171 if (ADDRESS_REG_P (operands[0]))
1172 return "fmove%.s %1,%-\;move%.l %+,%0";
1173 return "fmove%.s %f1,%0";
1175 if (operands[1] == CONST0_RTX (SFmode)
1176 /* clr insns on 68000 read before writing. */
1177 && ((TARGET_68010 || TARGET_COLDFIRE)
1178 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1180 if (ADDRESS_REG_P (operands[0]))
1182 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1184 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0";
1186 return "sub%.l %0,%0";
1188 /* moveq is faster on the 68000. */
1189 if (DATA_REG_P (operands[0]) && TUNE_68000_10)
1190 return "moveq #0,%0";
1193 return "move%.l %1,%0";
1196 (define_insn "movsf_cf_soft"
1197 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>,g,U")
1198 (match_operand:SF 1 "general_operand" "g,r<Q>,U"))]
1199 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
1201 [(set_attr "type" "move_l")])
1203 ;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU.
1204 ;; The move instructions can handle all combinations.
1205 (define_insn "movsf_cf_hard"
1206 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f
1208 (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m
1210 "TARGET_COLDFIRE_FPU"
1212 if (which_alternative == 4 || which_alternative == 5) {
1216 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1217 REAL_VALUE_TO_TARGET_SINGLE (r, l);
1218 xoperands[0] = operands[0];
1219 xoperands[1] = GEN_INT (l);
1220 if (which_alternative == 5) {
1222 if (ADDRESS_REG_P (xoperands[0]))
1223 output_asm_insn ("sub%.l %0,%0", xoperands);
1225 output_asm_insn ("clr%.l %0", xoperands);
1227 if (GET_CODE (operands[0]) == MEM
1228 && symbolic_operand (XEXP (operands[0], 0), SImode))
1229 output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands);
1231 output_asm_insn ("move%.l %1,%0", xoperands);
1235 output_asm_insn ("move%.l %1,%-;fsmove%.s %+,%0", xoperands);
1237 output_asm_insn ("clr%.l %-;fsmove%.s %+,%0", xoperands);
1240 if (FP_REG_P (operands[0]))
1242 if (ADDRESS_REG_P (operands[1]))
1243 return "move%.l %1,%-;fsmove%.s %+,%0";
1244 if (FP_REG_P (operands[1]))
1245 return "fsmove%.d %1,%0";
1246 return "fsmove%.s %f1,%0";
1248 if (FP_REG_P (operands[1]))
1250 if (ADDRESS_REG_P (operands[0]))
1251 return "fmove%.s %1,%-;move%.l %+,%0";
1252 return "fmove%.s %f1,%0";
1254 if (operands[1] == CONST0_RTX (SFmode))
1256 if (ADDRESS_REG_P (operands[0]))
1257 return "sub%.l %0,%0";
1260 return "move%.l %1,%0";
1263 (define_expand "reload_indf"
1264 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
1265 (match_operand:DF 1 "general_operand" "mf"))
1266 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1267 "TARGET_COLDFIRE_FPU"
1269 if (emit_move_sequence (operands, DFmode, operands[2]))
1272 /* We don't want the clobber emitted, so handle this ourselves. */
1273 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1277 (define_expand "reload_outdf"
1278 [(set (match_operand:DF 0 "general_operand" "")
1279 (match_operand:DF 1 "register_operand" "f"))
1280 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
1281 "TARGET_COLDFIRE_FPU"
1283 if (emit_move_sequence (operands, DFmode, operands[2]))
1286 /* We don't want the clobber emitted, so handle this ourselves. */
1287 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
1291 (define_expand "movdf"
1292 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1293 (match_operand:DF 1 "general_operand" ""))]
1296 if (TARGET_COLDFIRE_FPU)
1297 if (emit_move_sequence (operands, DFmode, 0))
1302 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>")
1303 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))]
1304 ; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
1305 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1308 if (FP_REG_P (operands[0]))
1310 if (FP_REG_P (operands[1]))
1311 return "f%&move%.x %1,%0";
1312 if (REG_P (operands[1]))
1315 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1316 output_asm_insn ("move%.l %1,%-", xoperands);
1317 output_asm_insn ("move%.l %1,%-", operands);
1318 return "f%&move%.d %+,%0";
1320 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1321 return output_move_const_double (operands);
1322 return "f%&move%.d %f1,%0";
1324 else if (FP_REG_P (operands[1]))
1326 if (REG_P (operands[0]))
1328 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1329 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1330 return "move%.l %+,%0";
1333 return "fmove%.d %f1,%0";
1335 return output_move_double (operands);
1338 (define_insn_and_split "movdf_cf_soft"
1339 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g")
1340 (match_operand:DF 1 "general_operand" "g,r"))]
1341 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU"
1343 "&& reload_completed"
1346 m68k_emit_move_double (operands);
1350 (define_insn "movdf_cf_hard"
1351 [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f")
1352 (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))]
1353 "TARGET_COLDFIRE_FPU"
1359 switch (which_alternative)
1362 return "fdmove%.d %1,%0";
1364 return "fmove%.d %1,%0";
1366 return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0";
1368 return "move%.l %R1,%-;move%.l %1,%-;fdmove%.d %+,%0";
1369 case 4: case 5: case 6:
1370 return output_move_double (operands);
1372 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
1373 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
1374 xoperands[0] = operands[0];
1375 xoperands[1] = GEN_INT (l[0]);
1376 xoperands[2] = GEN_INT (l[1]);
1377 if (operands[1] == CONST0_RTX (DFmode))
1378 output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0",
1382 output_asm_insn ("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0",
1385 output_asm_insn ("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0",
1391 ;; ??? The XFmode patterns are schizophrenic about whether constants are
1392 ;; allowed. Most but not all have predicates and constraint that disallow
1393 ;; constants. Most but not all have output templates that handle constants.
1394 ;; See also TARGET_LEGITIMATE_CONSTANT_P.
1396 (define_expand "movxf"
1397 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1398 (match_operand:XF 1 "general_operand" ""))]
1401 /* We can't rewrite operands during reload. */
1402 if (! reload_in_progress)
1404 if (CONSTANT_P (operands[1]))
1406 operands[1] = force_const_mem (XFmode, operands[1]);
1407 if (! memory_address_p (XFmode, XEXP (operands[1], 0)))
1408 operands[1] = adjust_address (operands[1], XFmode, 0);
1410 if (flag_pic && TARGET_PCREL)
1412 /* Don't allow writes to memory except via a register; the
1413 m68k doesn't consider PC-relative addresses to be writable. */
1414 if (GET_CODE (operands[0]) == MEM
1415 && symbolic_operand (XEXP (operands[0], 0), SImode))
1416 operands[0] = gen_rtx_MEM (XFmode,
1417 force_reg (SImode, XEXP (operands[0], 0)));
1423 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r,m,!r")
1424 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r,!r,m"))]
1427 if (FP_REG_P (operands[0]))
1429 if (FP_REG_P (operands[1]))
1430 return "fmove%.x %1,%0";
1431 if (REG_P (operands[1]))
1434 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1435 output_asm_insn ("move%.l %1,%-", xoperands);
1436 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1437 output_asm_insn ("move%.l %1,%-", xoperands);
1438 output_asm_insn ("move%.l %1,%-", operands);
1439 return "fmove%.x %+,%0";
1441 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1442 return "fmove%.x %1,%0";
1443 return "fmove%.x %f1,%0";
1445 if (FP_REG_P (operands[1]))
1447 if (REG_P (operands[0]))
1449 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1450 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1451 output_asm_insn ("move%.l %+,%0", operands);
1452 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1453 return "move%.l %+,%0";
1455 /* Must be memory destination. */
1456 return "fmove%.x %f1,%0";
1458 return output_move_double (operands);
1462 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1463 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1464 "! TARGET_68881 && ! TARGET_COLDFIRE"
1466 if (FP_REG_P (operands[0]))
1468 if (FP_REG_P (operands[1]))
1469 return "fmove%.x %1,%0";
1470 if (REG_P (operands[1]))
1473 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1474 output_asm_insn ("move%.l %1,%-", xoperands);
1475 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1476 output_asm_insn ("move%.l %1,%-", xoperands);
1477 output_asm_insn ("move%.l %1,%-", operands);
1478 return "fmove%.x %+,%0";
1480 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1481 return "fmove%.x %1,%0";
1482 return "fmove%.x %f1,%0";
1484 if (FP_REG_P (operands[1]))
1486 if (REG_P (operands[0]))
1488 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands);
1489 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1490 output_asm_insn ("move%.l %+,%0", operands);
1491 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1492 return "move%.l %+,%0";
1495 return "fmove%.x %f1,%0";
1497 return output_move_double (operands);
1501 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1502 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1503 "! TARGET_68881 && TARGET_COLDFIRE"
1504 "* return output_move_double (operands);")
1506 (define_expand "movdi"
1507 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1508 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1509 (match_operand:DI 1 "general_operand" ""))]
1513 ;; movdi can apply to fp regs in some cases
1515 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1516 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>")
1517 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))]
1518 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f")
1519 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))]
1520 ; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1521 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1524 if (FP_REG_P (operands[0]))
1526 if (FP_REG_P (operands[1]))
1527 return "fmove%.x %1,%0";
1528 if (REG_P (operands[1]))
1531 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1532 output_asm_insn ("move%.l %1,%-", xoperands);
1533 output_asm_insn ("move%.l %1,%-", operands);
1534 return "fmove%.d %+,%0";
1536 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1537 return output_move_const_double (operands);
1538 return "fmove%.d %f1,%0";
1540 else if (FP_REG_P (operands[1]))
1542 if (REG_P (operands[0]))
1544 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1545 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1546 return "move%.l %+,%0";
1549 return "fmove%.d %f1,%0";
1551 return output_move_double (operands);
1555 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g")
1556 (match_operand:DI 1 "general_operand" "g,r"))]
1558 "* return output_move_double (operands);")
1560 ;; Thus goes after the move instructions
1561 ;; because the move instructions are better (require no spilling)
1562 ;; when they can apply. It goes before the add/sub insns
1563 ;; so we will prefer it to them.
1565 (define_insn "pushasi"
1566 [(set (match_operand:SI 0 "push_operand" "=m")
1567 (match_operand:SI 1 "address_operand" "p"))]
1570 [(set_attr "type" "pea")])
1572 ;; truncation instructions
1573 (define_insn "truncsiqi2"
1574 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1576 (match_operand:SI 1 "general_src_operand" "doJS,i")))]
1579 if (GET_CODE (operands[0]) == REG)
1581 /* Must clear condition codes, since the move.l bases them on
1582 the entire 32 bits, not just the desired 8 bits. */
1584 return "move%.l %1,%0";
1586 if (GET_CODE (operands[1]) == MEM)
1587 operands[1] = adjust_address (operands[1], QImode, 3);
1588 return "move%.b %1,%0";
1591 (define_insn "trunchiqi2"
1592 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d")
1594 (match_operand:HI 1 "general_src_operand" "doJS,i")))]
1597 if (GET_CODE (operands[0]) == REG
1598 && (GET_CODE (operands[1]) == MEM
1599 || GET_CODE (operands[1]) == CONST_INT))
1601 /* Must clear condition codes, since the move.w bases them on
1602 the entire 16 bits, not just the desired 8 bits. */
1604 return "move%.w %1,%0";
1606 if (GET_CODE (operands[0]) == REG)
1608 /* Must clear condition codes, since the move.l bases them on
1609 the entire 32 bits, not just the desired 8 bits. */
1611 return "move%.l %1,%0";
1613 if (GET_CODE (operands[1]) == MEM)
1614 operands[1] = adjust_address (operands[1], QImode, 1);
1615 return "move%.b %1,%0";
1618 (define_insn "truncsihi2"
1619 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d")
1621 (match_operand:SI 1 "general_src_operand" "roJS,i")))]
1624 if (GET_CODE (operands[0]) == REG)
1626 /* Must clear condition codes, since the move.l bases them on
1627 the entire 32 bits, not just the desired 8 bits. */
1629 return "move%.l %1,%0";
1631 if (GET_CODE (operands[1]) == MEM)
1632 operands[1] = adjust_address (operands[1], QImode, 2);
1633 return "move%.w %1,%0";
1636 ;; zero extension instructions
1638 ;; two special patterns to match various post_inc/pre_dec patterns
1639 (define_insn_and_split "*zero_extend_inc"
1640 [(set (match_operand 0 "post_inc_operand" "")
1641 (zero_extend (match_operand 1 "register_operand" "")))]
1642 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1643 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1644 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1652 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1655 (define_insn_and_split "*zero_extend_dec"
1656 [(set (match_operand 0 "pre_dec_operand" "")
1657 (zero_extend (match_operand 1 "register_operand" "")))]
1658 "(GET_MODE (operands[0]) != HImode || XEXP (XEXP (operands[0], 0), 0) != stack_pointer_rtx) &&
1659 GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT &&
1660 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT &&
1661 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2"
1669 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0);
1672 (define_insn_and_split "zero_extendqidi2"
1673 [(set (match_operand:DI 0 "register_operand" "")
1674 (zero_extend:DI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1679 (zero_extend:SI (match_dup 1)))
1683 operands[2] = gen_lowpart (SImode, operands[0]);
1684 operands[3] = gen_highpart (SImode, operands[0]);
1687 (define_insn_and_split "zero_extendhidi2"
1688 [(set (match_operand:DI 0 "register_operand" "")
1689 (zero_extend:DI (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1694 (zero_extend:SI (match_dup 1)))
1698 operands[2] = gen_lowpart (SImode, operands[0]);
1699 operands[3] = gen_highpart (SImode, operands[0]);
1702 (define_expand "zero_extendsidi2"
1703 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1704 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1707 if (GET_CODE (operands[0]) == MEM
1708 && GET_CODE (operands[1]) == MEM)
1709 operands[1] = force_reg (SImode, operands[1]);
1712 (define_insn_and_split "*zero_extendsidi2"
1713 [(set (match_operand:DI 0 "nonimmediate_operand" "")
1714 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
1715 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1723 operands[2] = gen_lowpart (SImode, operands[0]);
1724 operands[3] = gen_highpart (SImode, operands[0]);
1727 (define_insn "*zero_extendhisi2_cf"
1728 [(set (match_operand:SI 0 "register_operand" "=d")
1729 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1732 [(set_attr "type" "mvsz")])
1734 (define_insn "zero_extendhisi2"
1735 [(set (match_operand:SI 0 "register_operand" "=d")
1736 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1740 (define_expand "zero_extendqihi2"
1741 [(set (match_operand:HI 0 "register_operand" "")
1742 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))]
1746 (define_insn "*zero_extendqihi2"
1747 [(set (match_operand:HI 0 "register_operand" "=d")
1748 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1752 (define_insn "*zero_extendqisi2_cfv4"
1753 [(set (match_operand:SI 0 "register_operand" "=d")
1754 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1757 [(set_attr "type" "mvsz")])
1759 (define_insn "zero_extendqisi2"
1760 [(set (match_operand:SI 0 "register_operand" "=d")
1761 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))]
1765 ;; these two pattern split everything else which isn't matched by
1766 ;; something else above
1768 [(set (match_operand 0 "register_operand" "")
1769 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1772 && reg_mentioned_p (operands[0], operands[1])"
1773 [(set (strict_low_part (match_dup 2))
1776 (match_op_dup 4 [(match_dup 0) (match_dup 3)]))]
1778 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1779 operands[3] = GEN_INT (GET_MODE_MASK (GET_MODE (operands[1])));
1780 operands[4] = gen_rtx_AND (GET_MODE (operands[0]), operands[0], operands[3]);
1784 [(set (match_operand 0 "register_operand" "")
1785 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))]
1786 "!ISA_HAS_MVS_MVZ && reload_completed"
1789 (set (strict_low_part (match_dup 2))
1792 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]);
1795 ;; sign extension instructions
1797 (define_insn "extendqidi2"
1798 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1799 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))]
1803 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1804 if (ISA_HAS_MVS_MVZ)
1805 return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
1806 if (TARGET_68020 || TARGET_COLDFIRE)
1808 if (ADDRESS_REG_P (operands[1]))
1809 return "move%.w %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1811 return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
1815 if (ADDRESS_REG_P (operands[1]))
1816 return "move%.w %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1818 return "move%.b %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0";
1822 (define_insn "extendhidi2"
1823 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
1825 (match_operand:HI 1 "general_src_operand" "rmS")))]
1829 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1830 if (ISA_HAS_MVS_MVZ)
1831 return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
1832 if (TARGET_68020 || TARGET_COLDFIRE)
1833 return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
1835 return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0";
1838 (define_insn "extendsidi2"
1839 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,o,<")
1841 (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm,r<Q>,rm")))
1842 (clobber (match_scratch:SI 2 "=X,d,d,d"))]
1847 if (which_alternative == 0)
1848 /* Handle alternative 0. */
1850 if (TARGET_68020 || TARGET_COLDFIRE)
1851 return "move%.l %1,%R0\;smi %0\;extb%.l %0";
1853 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
1856 /* Handle alternatives 1, 2 and 3. We don't need to adjust address by 4
1857 in alternative 3 because autodecrement will do that for us. */
1858 operands[3] = adjust_address (operands[0], SImode,
1859 which_alternative == 3 ? 0 : 4);
1860 operands[0] = adjust_address (operands[0], SImode, 0);
1862 if (TARGET_68020 || TARGET_COLDFIRE)
1863 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
1865 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
1867 [(set_attr "ok_for_coldfire" "yes,no,yes,yes")])
1869 ;; Special case when one can avoid register clobbering, copy and test
1870 ;; Maybe there is a way to make that the general case, by forcing the
1871 ;; result of the SI tree to be in the lower register of the DI target
1873 (define_insn "extendplussidi"
1874 [(set (match_operand:DI 0 "register_operand" "=d")
1875 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1876 (match_operand:SI 2 "general_operand" "rmn"))))]
1880 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1881 if (GET_CODE (operands[1]) == CONST_INT
1882 && (unsigned) INTVAL (operands[1]) > 8)
1884 rtx tmp = operands[1];
1886 operands[1] = operands[2];
1889 if (GET_CODE (operands[1]) == REG
1890 && REGNO (operands[1]) == REGNO (operands[3]))
1891 output_asm_insn ("add%.l %2,%3", operands);
1893 output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands);
1894 if (TARGET_68020 || TARGET_COLDFIRE)
1895 return "smi %0\;extb%.l %0";
1897 return "smi %0\;ext%.w %0\;ext%.l %0";
1900 (define_expand "extendhisi2"
1901 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1903 (match_operand:HI 1 "nonimmediate_src_operand" "")))]
1907 (define_insn "*cfv4_extendhisi2"
1908 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1910 (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
1913 [(set_attr "type" "mvsz")])
1915 (define_insn "*68k_extendhisi2"
1916 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
1918 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
1923 [(set_attr "type" "ext,move")])
1925 (define_insn "extendqihi2"
1926 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
1927 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1930 [(set_attr "type" "ext")])
1932 (define_expand "extendqisi2"
1933 [(set (match_operand:SI 0 "nonimmediate_operand" "")
1934 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1935 "TARGET_68020 || TARGET_COLDFIRE"
1938 (define_insn "*cfv4_extendqisi2"
1939 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1940 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
1943 [(set_attr "type" "mvsz")])
1945 (define_insn "*68k_extendqisi2"
1946 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
1947 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1948 "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)"
1950 [(set_attr "type" "ext")])
1952 ;; Conversions between float and double.
1954 (define_expand "extendsfdf2"
1955 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1957 (match_operand:SF 1 "general_operand" "")))]
1962 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f")
1964 (match_operand:SF 1 "general_operand" "f,dmF")))]
1967 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1969 if (REGNO (operands[0]) == REGNO (operands[1]))
1971 /* Extending float to double in an fp-reg is a no-op.
1972 NOTICE_UPDATE_CC has already assumed that the
1973 cc will be set. So cancel what it did. */
1974 cc_status = cc_prev_status;
1977 return "f%&move%.x %1,%0";
1979 if (FP_REG_P (operands[0]))
1980 return "f%&move%.s %f1,%0";
1981 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1983 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
1984 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1985 return "move%.l %+,%0";
1987 return "fmove%.d %f1,%0";
1990 (define_insn "extendsfdf2_cf"
1991 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f")
1993 (match_operand:SF 1 "general_operand" "f,<Q>U")))]
1994 "TARGET_COLDFIRE_FPU"
1996 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1998 if (REGNO (operands[0]) == REGNO (operands[1]))
2000 /* Extending float to double in an fp-reg is a no-op.
2001 NOTICE_UPDATE_CC has already assumed that the
2002 cc will be set. So cancel what it did. */
2003 cc_status = cc_prev_status;
2006 return "fdmove%.d %1,%0";
2008 return "fdmove%.s %f1,%0";
2011 ;; This cannot output into an f-reg because there is no way to be
2012 ;; sure of truncating in that case.
2013 (define_expand "truncdfsf2"
2014 [(set (match_operand:SF 0 "nonimmediate_operand" "")
2016 (match_operand:DF 1 "general_operand" "")))]
2020 ;; On the '040 we can truncate in a register accurately and easily.
2022 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
2024 (match_operand:DF 1 "general_operand" "fmG")))]
2025 "TARGET_68881 && TARGET_68040"
2027 if (FP_REG_P (operands[1]))
2028 return "f%$move%.x %1,%0";
2029 return "f%$move%.d %f1,%0";
2032 (define_insn "truncdfsf2_cf"
2033 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U")
2035 (match_operand:DF 1 "general_operand" "<Q>U,f")))]
2036 "TARGET_COLDFIRE_FPU"
2040 [(set_attr "type" "fmove")])
2042 (define_insn "*truncdfsf2_68881"
2043 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
2045 (match_operand:DF 1 "general_operand" "f")))]
2048 [(set_attr "type" "fmove")])
2050 ;; Conversion between fixed point and floating point.
2051 ;; Note that among the fix-to-float insns
2052 ;; the ones that start with SImode come first.
2053 ;; That is so that an operand that is a CONST_INT
2054 ;; (and therefore lacks a specific machine mode).
2055 ;; will be recognized as SImode (which is always valid)
2056 ;; rather than as QImode or HImode.
2058 (define_expand "floatsi<mode>2"
2059 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2060 (float:FP (match_operand:SI 1 "general_operand" "")))]
2064 (define_insn "floatsi<mode>2_68881"
2065 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2066 (float:FP (match_operand:SI 1 "general_operand" "dmi")))]
2068 "f<FP:round>move%.l %1,%0"
2069 [(set_attr "type" "fmove")])
2071 (define_insn "floatsi<mode>2_cf"
2072 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2073 (float:FP (match_operand:SI 1 "general_operand" "d<Q>U")))]
2074 "TARGET_COLDFIRE_FPU"
2075 "f<FP:prec>move%.l %1,%0"
2076 [(set_attr "type" "fmove")])
2079 (define_expand "floathi<mode>2"
2080 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2081 (float:FP (match_operand:HI 1 "general_operand" "")))]
2085 (define_insn "floathi<mode>2_68881"
2086 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2087 (float:FP (match_operand:HI 1 "general_operand" "dmn")))]
2090 [(set_attr "type" "fmove")])
2092 (define_insn "floathi<mode>2_cf"
2093 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2094 (float:FP (match_operand:HI 1 "general_operand" "d<Q>U")))]
2095 "TARGET_COLDFIRE_FPU"
2097 [(set_attr "type" "fmove")])
2100 (define_expand "floatqi<mode>2"
2101 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2102 (float:FP (match_operand:QI 1 "general_operand" "")))]
2106 (define_insn "floatqi<mode>2_68881"
2107 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2108 (float:FP (match_operand:QI 1 "general_operand" "dmn")))]
2111 [(set_attr "type" "fmove")])
2113 (define_insn "floatqi<mode>2_cf"
2114 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2115 (float:FP (match_operand:QI 1 "general_operand" "d<Q>U")))]
2116 "TARGET_COLDFIRE_FPU"
2118 [(set_attr "type" "fmove")])
2121 ;; New routines to convert floating-point values to integers
2122 ;; to be used on the '040. These should be faster than trapping
2123 ;; into the kernel to emulate fintrz. They should also be faster
2124 ;; than calling the subroutines fixsfsi or fixdfsi.
2126 (define_insn "fix_truncdfsi2"
2127 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2128 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2129 (clobber (match_scratch:SI 2 "=d"))
2130 (clobber (match_scratch:SI 3 "=d"))]
2131 "TARGET_68881 && TUNE_68040"
2134 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!";
2137 (define_insn "fix_truncdfhi2"
2138 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2139 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2140 (clobber (match_scratch:SI 2 "=d"))
2141 (clobber (match_scratch:SI 3 "=d"))]
2142 "TARGET_68881 && TUNE_68040"
2145 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!";
2148 (define_insn "fix_truncdfqi2"
2149 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2150 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
2151 (clobber (match_scratch:SI 2 "=d"))
2152 (clobber (match_scratch:SI 3 "=d"))]
2153 "TARGET_68881 && TUNE_68040"
2156 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!";
2159 ;; Convert a float to a float whose value is an integer.
2160 ;; This is the first stage of converting it to an integer type.
2162 (define_expand "ftrunc<mode>2"
2163 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2164 (fix:FP (match_operand:FP 1 "general_operand" "")))]
2165 "TARGET_HARD_FLOAT && !TUNE_68040"
2168 (define_insn "ftrunc<mode>2_68881"
2169 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2170 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
2171 "TARGET_68881 && !TUNE_68040"
2173 if (FP_REG_P (operands[1]))
2174 return "fintrz%.x %f1,%0";
2175 return "fintrz%.<FP:prec> %f1,%0";
2177 [(set_attr "type" "falu")])
2179 (define_insn "ftrunc<mode>2_cf"
2180 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2181 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
2182 "TARGET_COLDFIRE_FPU"
2184 if (FP_REG_P (operands[1]))
2185 return "fintrz%.d %f1,%0";
2186 return "fintrz%.<FP:prec> %f1,%0";
2188 [(set_attr "type" "falu")])
2190 ;; Convert a float whose value is an integer
2191 ;; to an actual integer. Second stage of converting float to integer type.
2192 (define_expand "fix<mode>qi2"
2193 [(set (match_operand:QI 0 "nonimmediate_operand" "")
2194 (fix:QI (match_operand:FP 1 "general_operand" "")))]
2198 (define_insn "fix<mode>qi2_68881"
2199 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
2200 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
2203 [(set_attr "type" "fmove")])
2205 (define_insn "fix<mode>qi2_cf"
2206 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U")
2207 (fix:QI (match_operand:FP 1 "general_operand" "f")))]
2208 "TARGET_COLDFIRE_FPU"
2210 [(set_attr "type" "fmove")])
2212 (define_expand "fix<mode>hi2"
2213 [(set (match_operand:HI 0 "nonimmediate_operand" "")
2214 (fix:HI (match_operand:FP 1 "general_operand" "")))]
2218 (define_insn "fix<mode>hi2_68881"
2219 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
2220 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
2223 [(set_attr "type" "fmove")])
2225 (define_insn "fix<mode>hi2_cf"
2226 [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U")
2227 (fix:HI (match_operand:FP 1 "general_operand" "f")))]
2228 "TARGET_COLDFIRE_FPU"
2230 [(set_attr "type" "fmove")])
2232 (define_expand "fix<mode>si2"
2233 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2234 (fix:SI (match_operand:FP 1 "general_operand" "")))]
2238 (define_insn "fix<mode>si2_68881"
2239 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
2240 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
2243 [(set_attr "type" "fmove")])
2245 (define_insn "fix<mode>si2_cf"
2246 [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U")
2247 (fix:SI (match_operand:FP 1 "general_operand" "f")))]
2248 "TARGET_COLDFIRE_FPU"
2250 [(set_attr "type" "fmove")])
2255 (define_insn "adddi_lshrdi_63"
2256 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
2257 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2260 (clobber (match_scratch:SI 2 "=d"))]
2263 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2264 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2266 "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
2267 if (GET_CODE (operands[1]) == REG)
2268 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2269 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2270 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2271 operands[4] = operands[1];
2273 operands[4] = adjust_address (operands[1], SImode, 4);
2274 if (GET_CODE (operands[1]) == MEM
2275 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2276 output_asm_insn ("move%.l %4,%3", operands);
2277 output_asm_insn ("move%.l %1,%0\;smi %2", operands);
2278 if (TARGET_68020 || TARGET_COLDFIRE)
2279 output_asm_insn ("extb%.l %2", operands);
2281 output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
2282 if (GET_CODE (operands[1]) != MEM
2283 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2284 output_asm_insn ("move%.l %4,%3", operands);
2285 return "sub%.l %2,%3\;subx%.l %2,%0";
2288 (define_insn "adddi_sexthishl32"
2289 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2290 (plus:DI (ashift:DI (sign_extend:DI
2291 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2293 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2294 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2298 if (ADDRESS_REG_P (operands[0]))
2299 return "add%.w %1,%0";
2300 else if (ADDRESS_REG_P (operands[3]))
2301 return "move%.w %1,%3\;add%.l %3,%0";
2303 return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0";
2306 (define_insn "*adddi_dilshr32"
2307 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o")
2308 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d")
2310 (match_operand:DI 2 "general_operand" "0,0")))]
2314 if (GET_CODE (operands[0]) == REG)
2315 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2317 operands[2] = adjust_address (operands[0], SImode, 4);
2318 return "add%.l %1,%2\;negx%.l %0\;neg%.l %0";
2321 (define_insn "*adddi_dilshr32_cf"
2322 [(set (match_operand:DI 0 "register_operand" "=d")
2323 (plus:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
2325 (match_operand:DI 2 "register_operand" "0")))]
2329 return "add%.l %1,%R0\;negx%.l %0\;neg%.l %0";
2332 (define_insn "adddi_dishl32"
2333 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o")
2334 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2335 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2336 ;; (const_int 32))))]
2337 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d")
2339 (match_operand:DI 2 "general_operand" "0,0")))]
2343 if (GET_CODE (operands[1]) == REG)
2344 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2346 operands[1] = adjust_address (operands[1], SImode, 4);
2347 return "add%.l %1,%0";
2349 [(set_attr "type" "alu_l")])
2351 (define_insn "adddi3"
2352 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
2353 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
2354 (match_operand:DI 2 "general_operand" "d,no>,d,a")))
2355 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
2358 if (DATA_REG_P (operands[0]))
2360 if (DATA_REG_P (operands[2]))
2361 return "add%.l %R2,%R0\;addx%.l %2,%0";
2362 else if (GET_CODE (operands[2]) == MEM
2363 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2364 return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
2370 if (GET_CODE (operands[2]) == REG)
2372 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2375 else if (CONSTANT_P (operands[2]))
2376 split_double (operands[2], &high, &low);
2379 low = adjust_address (operands[2], SImode, 4);
2383 operands[1] = low, operands[2] = high;
2384 xoperands[0] = operands[3];
2385 if (GET_CODE (operands[1]) == CONST_INT
2386 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2387 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2389 xoperands[1] = operands[2];
2391 output_asm_insn (output_move_simode (xoperands), xoperands);
2392 if (GET_CODE (operands[1]) == CONST_INT)
2394 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2395 return "addq%.l %1,%R0\;addx%.l %3,%0";
2396 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2398 operands[1] = GEN_INT (-INTVAL (operands[1]));
2399 return "subq%.l %1,%R0\;subx%.l %3,%0";
2402 return "add%.l %1,%R0\;addx%.l %3,%0";
2407 gcc_assert (GET_CODE (operands[0]) == MEM);
2409 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2411 operands[1] = gen_rtx_MEM (SImode,
2412 plus_constant (Pmode,
2413 XEXP(operands[0], 0), -8));
2414 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1";
2416 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2418 operands[1] = XEXP(operands[0], 0);
2419 return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1";
2423 operands[1] = adjust_address (operands[0], SImode, 4);
2424 return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0";
2429 (define_insn "addsi_lshrsi_31"
2430 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,dm,d<Q>")
2431 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm,r<Q>,rm")
2436 operands[2] = operands[0];
2437 operands[3] = gen_label_rtx();
2438 if (GET_CODE (operands[0]) == MEM)
2440 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2441 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2442 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2443 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2445 output_asm_insn ("move%.l %1,%0", operands);
2446 output_asm_insn ("jpl %l3", operands);
2447 output_asm_insn ("addq%.l #1,%2", operands);
2448 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2449 CODE_LABEL_NUMBER (operands[3]));
2452 [(set_attr "ok_for_coldfire" "no,yes,yes")])
2454 (define_expand "addsi3"
2455 [(set (match_operand:SI 0 "nonimmediate_operand" "")
2456 (plus:SI (match_operand:SI 1 "general_operand" "")
2457 (match_operand:SI 2 "general_src_operand" "")))]
2461 ;; Note that the middle two alternatives are near-duplicates
2462 ;; in order to handle insns generated by reload.
2463 ;; This is needed since they are not themselves reloaded,
2464 ;; so commutativity won't apply to them.
2465 (define_insn "*addsi3_internal"
2466 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
2467 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
2468 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
2472 "* return output_addsi3 (operands);")
2474 (define_insn_and_split "*addsi3_5200"
2475 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a, m,r, ?a, ?a,?a,?a")
2476 (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0, 0,0, a, a, r, a")
2477 (match_operand:SI 2 "general_src_operand" " I, L, JCu,d,mrKi,Cj, r, a, JCu")))]
2480 switch (which_alternative)
2483 return "addq%.l %2,%0";
2486 operands[2] = GEN_INT (- INTVAL (operands[2]));
2487 return "subq%.l %2,%0";
2491 return "add%.l %2,%0";
2494 /* move%.l %2,%0\n\tadd%.l %1,%0 */
2498 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
2501 return MOTOROLA ? "lea (%2,%1.l),%0" : "lea %2@(0,%1:l),%0";
2505 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
2512 "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 5) && !operands_match_p (operands[0], operands[1])"
2516 (plus:SI (match_dup 0)
2519 [(set_attr "type" "aluq_l,aluq_l,lea, alu_l,alu_l,*,lea, lea, lea")
2520 (set_attr "opy" "2, 2, *, 2, 2, *,*, *, *")
2521 (set_attr "opy_type" "*, *, mem5,*, *, *,mem6,mem6,mem5")])
2524 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2525 (plus:SI (match_operand:SI 1 "general_operand" "0")
2527 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2531 (define_insn "addhi3"
2532 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2533 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2534 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2537 if (GET_CODE (operands[2]) == CONST_INT)
2539 /* If the constant would be a negative number when interpreted as
2540 HImode, make it negative. This is usually, but not always, done
2541 elsewhere in the compiler. First check for constants out of range,
2542 which could confuse us. */
2544 if (INTVAL (operands[2]) >= 32768)
2545 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2547 if (INTVAL (operands[2]) > 0
2548 && INTVAL (operands[2]) <= 8)
2549 return "addq%.w %2,%0";
2550 if (INTVAL (operands[2]) < 0
2551 && INTVAL (operands[2]) >= -8)
2553 operands[2] = GEN_INT (- INTVAL (operands[2]));
2554 return "subq%.w %2,%0";
2556 /* On the CPU32 it is faster to use two addqw instructions to
2557 add a small integer (8 < N <= 16) to a register.
2558 Likewise for subqw. */
2559 if (TUNE_CPU32 && REG_P (operands[0]))
2561 if (INTVAL (operands[2]) > 8
2562 && INTVAL (operands[2]) <= 16)
2564 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2565 return "addq%.w #8,%0\;addq%.w %2,%0";
2567 if (INTVAL (operands[2]) < -8
2568 && INTVAL (operands[2]) >= -16)
2570 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
2571 return "subq%.w #8,%0\;subq%.w %2,%0";
2574 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2575 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
2577 return "add%.w %2,%0";
2580 ;; These insns must use MATCH_DUP instead of the more expected
2581 ;; use of a matching constraint because the "output" here is also
2582 ;; an input, so you can't use the matching constraint. That also means
2583 ;; that you can't use the "%", so you need patterns with the matched
2584 ;; operand in both positions.
2587 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2588 (plus:HI (match_dup 0)
2589 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2592 if (GET_CODE (operands[1]) == CONST_INT)
2594 /* If the constant would be a negative number when interpreted as
2595 HImode, make it negative. This is usually, but not always, done
2596 elsewhere in the compiler. First check for constants out of range,
2597 which could confuse us. */
2599 if (INTVAL (operands[1]) >= 32768)
2600 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2602 if (INTVAL (operands[1]) > 0
2603 && INTVAL (operands[1]) <= 8)
2604 return "addq%.w %1,%0";
2605 if (INTVAL (operands[1]) < 0
2606 && INTVAL (operands[1]) >= -8)
2608 operands[1] = GEN_INT (- INTVAL (operands[1]));
2609 return "subq%.w %1,%0";
2611 /* On the CPU32 it is faster to use two addqw instructions to
2612 add a small integer (8 < N <= 16) to a register.
2613 Likewise for subqw. */
2614 if (TUNE_CPU32 && REG_P (operands[0]))
2616 if (INTVAL (operands[1]) > 8
2617 && INTVAL (operands[1]) <= 16)
2619 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2620 return "addq%.w #8,%0\;addq%.w %1,%0";
2622 if (INTVAL (operands[1]) < -8
2623 && INTVAL (operands[1]) >= -16)
2625 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2626 return "subq%.w #8,%0\;subq%.w %1,%0";
2629 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2630 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2632 return "add%.w %1,%0";
2636 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2637 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn")
2641 if (GET_CODE (operands[1]) == CONST_INT)
2643 /* If the constant would be a negative number when interpreted as
2644 HImode, make it negative. This is usually, but not always, done
2645 elsewhere in the compiler. First check for constants out of range,
2646 which could confuse us. */
2648 if (INTVAL (operands[1]) >= 32768)
2649 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2651 if (INTVAL (operands[1]) > 0
2652 && INTVAL (operands[1]) <= 8)
2653 return "addq%.w %1,%0";
2654 if (INTVAL (operands[1]) < 0
2655 && INTVAL (operands[1]) >= -8)
2657 operands[1] = GEN_INT (- INTVAL (operands[1]));
2658 return "subq%.w %1,%0";
2660 /* On the CPU32 it is faster to use two addqw instructions to
2661 add a small integer (8 < N <= 16) to a register.
2662 Likewise for subqw. */
2663 if (TUNE_CPU32 && REG_P (operands[0]))
2665 if (INTVAL (operands[1]) > 8
2666 && INTVAL (operands[1]) <= 16)
2668 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2669 return "addq%.w #8,%0\;addq%.w %1,%0";
2671 if (INTVAL (operands[1]) < -8
2672 && INTVAL (operands[1]) >= -16)
2674 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8);
2675 return "subq%.w #8,%0\;subq%.w %1,%0";
2678 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040)
2679 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0";
2681 return "add%.w %1,%0";
2684 (define_insn "addqi3"
2685 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2686 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2687 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2690 if (GET_CODE (operands[2]) == CONST_INT)
2692 if (INTVAL (operands[2]) >= 128)
2693 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2695 if (INTVAL (operands[2]) > 0
2696 && INTVAL (operands[2]) <= 8)
2697 return "addq%.b %2,%0";
2698 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2700 operands[2] = GEN_INT (- INTVAL (operands[2]));
2701 return "subq%.b %2,%0";
2704 return "add%.b %2,%0";
2708 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2709 (plus:QI (match_dup 0)
2710 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2713 if (GET_CODE (operands[1]) == CONST_INT)
2715 if (INTVAL (operands[1]) >= 128)
2716 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2718 if (INTVAL (operands[1]) > 0
2719 && INTVAL (operands[1]) <= 8)
2720 return "addq%.b %1,%0";
2721 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2723 operands[1] = GEN_INT (- INTVAL (operands[1]));
2724 return "subq%.b %1,%0";
2727 return "add%.b %1,%0";
2731 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2732 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
2736 if (GET_CODE (operands[1]) == CONST_INT)
2738 if (INTVAL (operands[1]) >= 128)
2739 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2741 if (INTVAL (operands[1]) > 0
2742 && INTVAL (operands[1]) <= 8)
2743 return "addq%.b %1,%0";
2744 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2746 operands[1] = GEN_INT (- INTVAL (operands[1]));
2747 return "subq%.b %1,%0";
2750 return "add%.b %1,%0";
2753 (define_expand "add<mode>3"
2754 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2755 (plus:FP (match_operand:FP 1 "general_operand" "")
2756 (match_operand:FP 2 "general_operand" "")))]
2760 (define_insn "add<mode>3_floatsi_68881"
2761 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2762 (plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
2763 (match_operand:FP 1 "general_operand" "0")))]
2765 "f<FP:round>add%.l %2,%0"
2766 [(set_attr "type" "falu")
2767 (set_attr "opy" "2")])
2769 (define_insn "add<mode>3_floathi_68881"
2770 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2771 (plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
2772 (match_operand:FP 1 "general_operand" "0")))]
2774 "f<FP:round>add%.w %2,%0"
2775 [(set_attr "type" "falu")
2776 (set_attr "opy" "2")])
2778 (define_insn "add<mode>3_floatqi_68881"
2779 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2780 (plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
2781 (match_operand:FP 1 "general_operand" "0")))]
2783 "f<FP:round>add%.b %2,%0"
2784 [(set_attr "type" "falu")
2785 (set_attr "opy" "2")])
2787 (define_insn "add<mode>3_68881"
2788 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2789 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2790 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
2793 if (FP_REG_P (operands[2]))
2794 return "f<FP:round>add%.x %2,%0";
2795 return "f<FP:round>add%.<FP:prec> %f2,%0";
2797 [(set_attr "type" "falu")
2798 (set_attr "opy" "2")])
2800 (define_insn "add<mode>3_cf"
2801 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2802 (plus:FP (match_operand:FP 1 "general_operand" "%0")
2803 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
2804 "TARGET_COLDFIRE_FPU"
2806 if (FP_REG_P (operands[2]))
2807 return "f<FP:prec>add%.d %2,%0";
2808 return "f<FP:prec>add%.<FP:prec> %2,%0";
2810 [(set_attr "type" "falu")
2811 (set_attr "opy" "2")])
2813 ;; subtract instructions
2815 (define_insn "subdi_sexthishl32"
2816 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d")
2817 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2818 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2820 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2824 if (ADDRESS_REG_P (operands[0]))
2825 return "sub%.w %2,%0";
2826 else if (ADDRESS_REG_P (operands[3]))
2827 return "move%.w %2,%3\;sub%.l %3,%0";
2829 return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0";
2832 (define_insn "subdi_dishl32"
2833 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro")
2834 (minus:DI (match_dup 0)
2835 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2840 if (GET_CODE (operands[1]) == REG)
2841 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2843 operands[1] = adjust_address (operands[1], SImode, 4);
2844 return "sub%.l %1,%0";
2846 [(set_attr "type" "alu_l")])
2848 (define_insn "subdi3"
2849 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d")
2850 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2851 (match_operand:DI 2 "general_operand" "d,no>,d,a")))
2852 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))]
2855 if (DATA_REG_P (operands[0]))
2857 if (DATA_REG_P (operands[2]))
2858 return "sub%.l %R2,%R0\;subx%.l %2,%0";
2859 else if (GET_CODE (operands[2]) == MEM
2860 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2862 return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
2869 if (GET_CODE (operands[2]) == REG)
2871 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2874 else if (CONSTANT_P (operands[2]))
2875 split_double (operands[2], &high, &low);
2878 low = adjust_address (operands[2], SImode, 4);
2882 operands[1] = low, operands[2] = high;
2883 xoperands[0] = operands[3];
2884 if (GET_CODE (operands[1]) == CONST_INT
2885 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2886 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
2888 xoperands[1] = operands[2];
2890 output_asm_insn (output_move_simode (xoperands), xoperands);
2891 if (GET_CODE (operands[1]) == CONST_INT)
2893 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2894 return "subq%.l %1,%R0\;subx%.l %3,%0";
2895 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2897 operands[1] = GEN_INT (-INTVAL (operands[1]));
2898 return "addq%.l %1,%R0\;addx%.l %3,%0";
2901 return "sub%.l %1,%R0\;subx%.l %3,%0";
2906 gcc_assert (GET_CODE (operands[0]) == MEM);
2908 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2911 = gen_rtx_MEM (SImode, plus_constant (Pmode,
2912 XEXP (operands[0], 0), -8));
2913 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1";
2915 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2917 operands[1] = XEXP(operands[0], 0);
2918 return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1";
2922 operands[1] = adjust_address (operands[0], SImode, 4);
2923 return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0";
2928 (define_insn "subsi3"
2929 [(set (match_operand:SI 0 "nonimmediate_operand" "=mda,m,d,a")
2930 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
2931 (match_operand:SI 2 "general_src_operand" "I,dT,mSrT,mSrs")))]
2938 [(set_attr "type" "aluq_l,alu_l,alu_l,alu_l")
2939 (set_attr "opy" "2")])
2942 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
2943 (minus:SI (match_operand:SI 1 "general_operand" "0")
2945 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))]
2949 (define_insn "subhi3"
2950 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r")
2951 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2952 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
2957 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
2958 (minus:HI (match_dup 0)
2959 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
2963 (define_insn "subqi3"
2964 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
2965 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2966 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
2971 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
2972 (minus:QI (match_dup 0)
2973 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
2977 (define_expand "sub<mode>3"
2978 [(set (match_operand:FP 0 "nonimmediate_operand" "")
2979 (minus:FP (match_operand:FP 1 "general_operand" "")
2980 (match_operand:FP 2 "general_operand" "")))]
2984 (define_insn "sub<mode>3_floatsi_68881"
2985 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2986 (minus:FP (match_operand:FP 1 "general_operand" "0")
2987 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
2989 "f<FP:round>sub%.l %2,%0"
2990 [(set_attr "type" "falu")
2991 (set_attr "opy" "2")])
2993 (define_insn "sub<mode>3_floathi_68881"
2994 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
2995 (minus:FP (match_operand:FP 1 "general_operand" "0")
2996 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
2998 "f<FP:round>sub%.w %2,%0"
2999 [(set_attr "type" "falu")
3000 (set_attr "opy" "2")])
3002 (define_insn "sub<mode>3_floatqi_68881"
3003 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3004 (minus:FP (match_operand:FP 1 "general_operand" "0")
3005 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
3007 "f<FP:round>sub%.b %2,%0"
3008 [(set_attr "type" "falu")
3009 (set_attr "opy" "2")])
3011 (define_insn "sub<mode>3_68881"
3012 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3013 (minus:FP (match_operand:FP 1 "general_operand" "0")
3014 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
3017 if (FP_REG_P (operands[2]))
3018 return "f<FP:round>sub%.x %2,%0";
3019 return "f<FP:round>sub%.<FP:prec> %f2,%0";
3021 [(set_attr "type" "falu")
3022 (set_attr "opy" "2")])
3024 (define_insn "sub<mode>3_cf"
3025 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3026 (minus:FP (match_operand:FP 1 "general_operand" "0")
3027 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))]
3028 "TARGET_COLDFIRE_FPU"
3030 if (FP_REG_P (operands[2]))
3031 return "f<FP:prec>sub%.d %2,%0";
3032 return "f<FP:prec>sub%.<FP:prec> %2,%0";
3034 [(set_attr "type" "falu")
3035 (set_attr "opy" "2")])
3037 ;; multiply instructions
3039 (define_insn "mulhi3"
3040 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3041 (mult:HI (match_operand:HI 1 "general_operand" "%0")
3042 (match_operand:HI 2 "general_src_operand" "dmSn")))]
3045 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
3047 [(set_attr "type" "mul_w")
3048 (set_attr "opy" "2")])
3050 (define_insn "mulhisi3"
3051 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3052 (mult:SI (sign_extend:SI
3053 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3055 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3058 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
3060 [(set_attr "type" "mul_w")
3061 (set_attr "opy" "2")])
3063 (define_insn "*mulhisisi3_s"
3064 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3065 (mult:SI (sign_extend:SI
3066 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3067 (match_operand:SI 2 "const_int_operand" "n")))]
3068 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
3070 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0";
3072 [(set_attr "type" "mul_w")
3073 (set_attr "opy" "2")])
3075 (define_expand "mulsi3"
3076 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3077 (mult:SI (match_operand:SI 1 "general_operand" "")
3078 (match_operand:SI 2 "general_operand" "")))]
3079 "TARGET_68020 || TARGET_COLDFIRE"
3082 (define_insn "*mulsi3_68020"
3083 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3084 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3085 (match_operand:SI 2 "general_src_operand" "dmSTK")))]
3089 [(set_attr "type" "mul_l")
3090 (set_attr "opy" "2")])
3092 (define_insn "*mulsi3_cf"
3093 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3094 (mult:SI (match_operand:SI 1 "general_operand" "%0")
3095 (match_operand:SI 2 "general_operand" "d<Q>")))]
3098 [(set_attr "type" "mul_l")
3099 (set_attr "opy" "2")])
3101 (define_insn "umulhisi3"
3102 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3103 (mult:SI (zero_extend:SI
3104 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3106 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))]
3109 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
3111 [(set_attr "type" "mul_w")
3112 (set_attr "opy" "2")])
3114 (define_insn "*mulhisisi3_z"
3115 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3116 (mult:SI (zero_extend:SI
3117 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3118 (match_operand:SI 2 "const_int_operand" "n")))]
3119 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3121 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0";
3123 [(set_attr "type" "mul_w")
3124 (set_attr "opy" "2")])
3126 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3127 ;; proper matching constraint. This is because the matching is between
3128 ;; the high-numbered word of the DImode operand[0] and operand[1].
3129 (define_expand "umulsidi3"
3131 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3132 (mult:SI (match_operand:SI 1 "register_operand" "")
3133 (match_operand:SI 2 "register_operand" "")))
3134 (set (subreg:SI (match_dup 0) 0)
3135 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3136 (zero_extend:DI (match_dup 2)))
3137 (const_int 32))))])]
3138 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3142 [(set (match_operand:SI 0 "register_operand" "=d")
3143 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3144 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3145 (set (match_operand:SI 3 "register_operand" "=d")
3146 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3147 (zero_extend:DI (match_dup 2)))
3149 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3152 ; Match immediate case. For 2.4 only match things < 2^31.
3153 ; It's tricky with larger values in these patterns since we need to match
3154 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3157 [(set (match_operand:SI 0 "register_operand" "=d")
3158 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3159 (match_operand:SI 2 "const_int_operand" "n")))
3160 (set (match_operand:SI 3 "register_operand" "=d")
3161 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3164 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE
3165 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3168 (define_expand "mulsidi3"
3170 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 4)
3171 (mult:SI (match_operand:SI 1 "register_operand" "")
3172 (match_operand:SI 2 "register_operand" "")))
3173 (set (subreg:SI (match_dup 0) 0)
3174 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3175 (sign_extend:DI (match_dup 2)))
3176 (const_int 32))))])]
3177 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3181 [(set (match_operand:SI 0 "register_operand" "=d")
3182 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3183 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3184 (set (match_operand:SI 3 "register_operand" "=d")
3185 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3186 (sign_extend:DI (match_dup 2)))
3188 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3192 [(set (match_operand:SI 0 "register_operand" "=d")
3193 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3194 (match_operand:SI 2 "const_int_operand" "n")))
3195 (set (match_operand:SI 3 "register_operand" "=d")
3196 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3199 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3202 (define_expand "umulsi3_highpart"
3204 [(set (match_operand:SI 0 "register_operand" "")
3207 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3208 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3210 (clobber (match_dup 3))])]
3211 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3213 operands[3] = gen_reg_rtx (SImode);
3215 if (GET_CODE (operands[2]) == CONST_INT)
3217 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
3220 /* We have to adjust the operand order for the matching constraints. */
3221 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3222 operands[1], operands[2]));
3228 [(set (match_operand:SI 0 "register_operand" "=d")
3231 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3232 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3234 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3235 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3238 (define_insn "const_umulsi3_highpart"
3239 [(set (match_operand:SI 0 "register_operand" "=d")
3242 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3243 (match_operand:DI 3 "const_uint32_operand" "n"))
3245 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3246 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3249 (define_expand "smulsi3_highpart"
3251 [(set (match_operand:SI 0 "register_operand" "")
3254 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3255 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3257 (clobber (match_dup 3))])]
3258 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3260 operands[3] = gen_reg_rtx (SImode);
3261 if (GET_CODE (operands[2]) == CONST_INT)
3263 /* We have to adjust the operand order for the matching constraints. */
3264 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3265 operands[1], operands[2]));
3271 [(set (match_operand:SI 0 "register_operand" "=d")
3274 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3275 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3277 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3278 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3281 (define_insn "const_smulsi3_highpart"
3282 [(set (match_operand:SI 0 "register_operand" "=d")
3285 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3286 (match_operand:DI 3 "const_sint32_operand" "n"))
3288 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3289 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
3292 (define_expand "mul<mode>3"
3293 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3294 (mult:FP (match_operand:FP 1 "general_operand" "")
3295 (match_operand:FP 2 "general_operand" "")))]
3299 (define_insn "mul<mode>3_floatsi_68881"
3300 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3301 (mult:FP (float:FP (match_operand:SI 2 "general_operand" "dmi"))
3302 (match_operand:FP 1 "general_operand" "0")))]
3306 ? "f<FP:round>mul%.l %2,%0"
3307 : "f<FP:round_mul>mul%.l %2,%0";
3309 [(set_attr "type" "fmul")
3310 (set_attr "opy" "2")])
3312 (define_insn "mul<mode>3_floathi_68881"
3313 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3314 (mult:FP (float:FP (match_operand:HI 2 "general_operand" "dmn"))
3315 (match_operand:FP 1 "general_operand" "0")))]
3319 ? "f<FP:round>mul%.w %2,%0"
3320 : "f<FP:round_mul>mul%.w %2,%0";
3322 [(set_attr "type" "fmul")
3323 (set_attr "opy" "2")])
3325 (define_insn "mul<mode>3_floatqi_68881"
3326 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3327 (mult:FP (float:FP (match_operand:QI 2 "general_operand" "dmn"))
3328 (match_operand:FP 1 "general_operand" "0")))]
3332 ? "f<FP:round>mul%.b %2,%0"
3333 : "f<FP:round_mul>mul%.b %2,%0";
3335 [(set_attr "type" "fmul")
3336 (set_attr "opy" "2")])
3338 (define_insn "muldf_68881"
3339 [(set (match_operand:DF 0 "nonimmediate_operand" "=f")
3340 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3341 (match_operand:DF 2 "general_operand" "fmG")))]
3344 if (GET_CODE (operands[2]) == CONST_DOUBLE
3345 && floating_exact_log2 (operands[2]) && !TUNE_68040_60)
3347 int i = floating_exact_log2 (operands[2]);
3348 operands[2] = GEN_INT (i);
3349 return "fscale%.l %2,%0";
3351 if (REG_P (operands[2]))
3352 return "f%&mul%.x %2,%0";
3353 return "f%&mul%.d %f2,%0";
3356 (define_insn "mulsf_68881"
3357 [(set (match_operand:SF 0 "nonimmediate_operand" "=f")
3358 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3359 (match_operand:SF 2 "general_operand" "fdmF")))]
3362 if (FP_REG_P (operands[2]))
3363 return (TARGET_68040
3365 : "fsglmul%.x %2,%0");
3366 return (TARGET_68040
3368 : "fsglmul%.s %f2,%0");
3371 (define_insn "mulxf3_68881"
3372 [(set (match_operand:XF 0 "nonimmediate_operand" "=f")
3373 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
3374 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
3377 return "fmul%.x %f2,%0";
3380 (define_insn "fmul<mode>3_cf"
3381 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3382 (mult:FP (match_operand:FP 1 "general_operand" "%0")
3383 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
3384 "TARGET_COLDFIRE_FPU"
3386 if (FP_REG_P (operands[2]))
3387 return "f<FP:prec>mul%.d %2,%0";
3388 return "f<FP:prec>mul%.<FP:prec> %2,%0";
3390 [(set_attr "type" "fmul")
3391 (set_attr "opy" "2")])
3393 ;; divide instructions
3395 (define_expand "div<mode>3"
3396 [(set (match_operand:FP 0 "nonimmediate_operand" "")
3397 (div:FP (match_operand:FP 1 "general_operand" "")
3398 (match_operand:FP 2 "general_operand" "")))]
3402 (define_insn "div<mode>3_floatsi_68881"
3403 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3404 (div:FP (match_operand:FP 1 "general_operand" "0")
3405 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))]
3409 ? "f<FP:round>div%.l %2,%0"
3410 : "f<FP:round_mul>div%.l %2,%0";
3413 (define_insn "div<mode>3_floathi_68881"
3414 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3415 (div:FP (match_operand:FP 1 "general_operand" "0")
3416 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))]
3420 ? "f<FP:round>div%.w %2,%0"
3421 : "f<FP:round_mul>div%.w %2,%0";
3424 (define_insn "div<mode>3_floatqi_68881"
3425 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3426 (div:FP (match_operand:FP 1 "general_operand" "0")
3427 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))]
3431 ? "f<FP:round>div%.b %2,%0"
3432 : "f<FP:round_mul>div%.b %2,%0";
3435 (define_insn "div<mode>3_68881"
3436 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3437 (div:FP (match_operand:FP 1 "general_operand" "0")
3438 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))]
3441 if (FP_REG_P (operands[2]))
3442 return (TARGET_68040
3443 ? "f<FP:round>div%.x %2,%0"
3444 : "f<FP:round_mul>div%.x %2,%0");
3445 return (TARGET_68040
3446 ? "f<FP:round>div%.<FP:prec> %f2,%0"
3447 : "f<FP:round_mul>div%.<FP:prec> %f2,%0");
3450 (define_insn "div<mode>3_cf"
3451 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
3452 (div:FP (match_operand:FP 1 "general_operand" "0")
3453 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))]
3454 "TARGET_COLDFIRE_FPU"
3456 if (FP_REG_P (operands[2]))
3457 return "f<FP:prec>div%.d %2,%0";
3458 return "f<FP:prec>div%.<FP:prec> %2,%0";
3460 [(set_attr "type" "fdiv")
3461 (set_attr "opy" "2")])
3463 ;; Remainder instructions.
3465 (define_expand "divmodsi4"
3467 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3468 (div:SI (match_operand:SI 1 "general_operand" "")
3469 (match_operand:SI 2 "general_src_operand" "")))
3470 (set (match_operand:SI 3 "nonimmediate_operand" "")
3471 (mod:SI (match_dup 1) (match_dup 2)))])]
3472 "TARGET_68020 || TARGET_CF_HWDIV"
3476 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3477 (div:SI (match_operand:SI 1 "general_operand" "0")
3478 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3479 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3480 (mod:SI (match_dup 1) (match_dup 2)))]
3483 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3484 return "divs%.l %2,%0";
3485 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3486 return "rems%.l %2,%3:%0";
3488 return "rems%.l %2,%3:%0\;divs%.l %2,%0";
3490 [(set_attr "type" "div_l")
3491 (set_attr "opy" "2")])
3494 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3495 (div:SI (match_operand:SI 1 "general_operand" "0")
3496 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3497 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3498 (mod:SI (match_dup 1) (match_dup 2)))]
3501 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3502 return "divs%.l %2,%0";
3504 return "divsl%.l %2,%3:%0";
3507 (define_expand "udivmodsi4"
3509 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3510 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3511 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3512 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3513 (umod:SI (match_dup 1) (match_dup 2)))])]
3514 "TARGET_68020 || TARGET_CF_HWDIV"
3518 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3519 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3520 (match_operand:SI 2 "general_src_operand" "d<Q>U")))
3521 (set (match_operand:SI 3 "nonimmediate_operand" "=&d")
3522 (umod:SI (match_dup 1) (match_dup 2)))]
3525 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3526 return "divu%.l %2,%0";
3527 else if (find_reg_note (insn, REG_UNUSED, operands[0]))
3528 return "remu%.l %2,%3:%0";
3530 return "remu%.l %2,%3:%0\;divu%.l %2,%0";
3532 [(set_attr "type" "div_l")
3533 (set_attr "opy" "2")])
3536 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
3537 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3538 (match_operand:SI 2 "general_src_operand" "dmSTK")))
3539 (set (match_operand:SI 3 "nonimmediate_operand" "=d")
3540 (umod:SI (match_dup 1) (match_dup 2)))]
3541 "TARGET_68020 && !TARGET_COLDFIRE"
3543 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3544 return "divu%.l %2,%0";
3546 return "divul%.l %2,%3:%0";
3549 (define_insn "divmodhi4"
3550 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3551 (div:HI (match_operand:HI 1 "general_operand" "0")
3552 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3553 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3554 (mod:HI (match_dup 1) (match_dup 2)))]
3555 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3557 output_asm_insn (MOTOROLA ?
3558 "ext%.l %0\;divs%.w %2,%0" :
3559 "extl %0\;divs %2,%0",
3561 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3564 return "move%.l %0,%3\;swap %3";
3570 (define_insn "udivmodhi4"
3571 [(set (match_operand:HI 0 "nonimmediate_operand" "=d")
3572 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3573 (match_operand:HI 2 "general_src_operand" "dmSKT")))
3574 (set (match_operand:HI 3 "nonimmediate_operand" "=d")
3575 (umod:HI (match_dup 1) (match_dup 2)))]
3576 "!TARGET_COLDFIRE || TARGET_CF_HWDIV"
3578 if (ISA_HAS_MVS_MVZ)
3579 output_asm_insn (MOTOROLA ?
3580 "mvz%.w %0,%0\;divu%.w %2,%0" :
3581 "mvz%.w %0,%0\;divu %2,%0",
3584 output_asm_insn (MOTOROLA ?
3585 "and%.l #0xFFFF,%0\;divu%.w %2,%0" :
3586 "and%.l #0xFFFF,%0\;divu %2,%0",
3589 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3592 return "move%.l %0,%3\;swap %3";
3598 ;; logical-and instructions
3600 ;; "anddi3" is mainly here to help combine().
3601 (define_insn "anddi3"
3602 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3603 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3604 (match_operand:DI 2 "general_operand" "dn,don")))]
3608 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3609 if (CONSTANT_P (operands[2]))
3613 split_double (operands[2], &hi, &lo);
3615 switch (INTVAL (hi))
3618 output_asm_insn ("clr%.l %0", operands);
3626 xoperands[0] = operands[0];
3628 output_asm_insn (output_andsi3 (xoperands), xoperands);
3631 if (GET_CODE (operands[0]) == REG)
3632 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3634 operands[0] = adjust_address (operands[0], SImode, 4);
3635 switch (INTVAL (lo))
3638 output_asm_insn ("clr%.l %0", operands);
3646 xoperands[0] = operands[0];
3648 output_asm_insn (output_andsi3 (xoperands), xoperands);
3653 if (GET_CODE (operands[0]) != REG)
3655 operands[1] = adjust_address (operands[0], SImode, 4);
3656 return "and%.l %2,%0\;and%.l %R2,%1";
3658 if (GET_CODE (operands[2]) != REG)
3660 operands[1] = adjust_address (operands[2], SImode, 4);
3661 return "and%.l %2,%0\;and%.l %1,%R0";
3663 return "and%.l %2,%0\;and%.l %R2,%R0";
3666 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3667 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3668 ;; can't allocate pseudos into it.
3670 (define_expand "andsi3"
3671 [(set (match_operand:SI 0 "not_sp_operand" "")
3672 (and:SI (match_operand:SI 1 "general_operand" "")
3673 (match_operand:SI 2 "general_src_operand" "")))]
3677 ;; produced by split operations after reload finished
3678 (define_insn "*andsi3_split"
3679 [(set (match_operand:SI 0 "register_operand" "=d")
3680 (and:SI (match_operand:SI 1 "register_operand" "0")
3681 (match_operand:SI 2 "const_int_operand" "i")))]
3682 "reload_completed && !TARGET_COLDFIRE"
3684 return output_andsi3 (operands);
3687 (define_insn "andsi3_internal"
3688 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3689 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3690 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))]
3693 return output_andsi3 (operands);
3696 (define_insn "andsi3_5200"
3697 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3698 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3699 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3703 && DATA_REG_P (operands[0])
3704 && GET_CODE (operands[2]) == CONST_INT)
3706 if (INTVAL (operands[2]) == 0x000000ff)
3707 return "mvz%.b %0,%0";
3708 else if (INTVAL (operands[2]) == 0x0000ffff)
3709 return "mvz%.w %0,%0";
3711 return output_andsi3 (operands);
3714 (define_insn "andhi3"
3715 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3716 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3717 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3722 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3723 (and:HI (match_dup 0)
3724 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3729 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3730 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3735 (define_insn "andqi3"
3736 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3737 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3738 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3743 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3744 (and:QI (match_dup 0)
3745 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3750 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3751 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3756 ;; inclusive-or instructions
3758 (define_insn "iordi_zext"
3759 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3760 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3761 (match_operand:DI 2 "general_operand" "0,0")))]
3767 if (GET_CODE (operands[0]) == REG)
3768 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3770 operands[0] = adjust_address (operands[0], SImode, 4);
3771 if (GET_MODE (operands[1]) == SImode)
3772 return "or%.l %1,%0";
3773 byte_mode = (GET_MODE (operands[1]) == QImode);
3774 if (GET_CODE (operands[0]) == MEM)
3775 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3778 return "or%.b %1,%0";
3780 return "or%.w %1,%0";
3783 ;; "iordi3" is mainly here to help combine().
3784 (define_insn "iordi3"
3785 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d")
3786 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3787 (match_operand:DI 2 "general_operand" "dn,don")))]
3791 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3792 if (CONSTANT_P (operands[2]))
3796 split_double (operands[2], &hi, &lo);
3798 switch (INTVAL (hi))
3803 /* FIXME : a scratch register would be welcome here if operand[0]
3804 is not a register */
3805 output_asm_insn ("move%.l #-1,%0", operands);
3811 xoperands[0] = operands[0];
3813 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3816 if (GET_CODE (operands[0]) == REG)
3817 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3819 operands[0] = adjust_address (operands[0], SImode, 4);
3820 switch (INTVAL (lo))
3825 /* FIXME : a scratch register would be welcome here if operand[0]
3826 is not a register */
3827 output_asm_insn ("move%.l #-1,%0", operands);
3833 xoperands[0] = operands[0];
3835 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3840 if (GET_CODE (operands[0]) != REG)
3842 operands[1] = adjust_address (operands[0], SImode, 4);
3843 return "or%.l %2,%0\;or%.l %R2,%1";
3845 if (GET_CODE (operands[2]) != REG)
3847 operands[1] = adjust_address (operands[2], SImode, 4);
3848 return "or%.l %2,%0\;or%.l %1,%R0";
3850 return "or%.l %2,%0\;or%.l %R2,%R0";
3853 (define_expand "iorsi3"
3854 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3855 (ior:SI (match_operand:SI 1 "general_operand" "")
3856 (match_operand:SI 2 "general_src_operand" "")))]
3860 (define_insn "iorsi3_internal"
3861 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3862 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3863 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))]
3866 return output_iorsi3 (operands);
3869 (define_insn "iorsi3_5200"
3870 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d")
3871 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3872 (match_operand:SI 2 "general_src_operand" "d,dmsK")))]
3875 return output_iorsi3 (operands);
3878 (define_insn "iorhi3"
3879 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
3880 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3881 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))]
3886 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3887 (ior:HI (match_dup 0)
3888 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))]
3893 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d"))
3894 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn")
3899 (define_insn "iorqi3"
3900 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d")
3901 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3902 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
3907 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3908 (ior:QI (match_dup 0)
3909 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
3914 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d"))
3915 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn")
3920 ;; On all 68k models, this makes faster code in a special case.
3921 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3923 (define_insn "iorsi_zexthi_ashl16"
3924 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
3925 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3926 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3931 if (GET_CODE (operands[2]) != REG)
3932 operands[2] = adjust_address (operands[2], HImode, 2);
3933 if (GET_CODE (operands[2]) != REG
3934 || REGNO (operands[2]) != REGNO (operands[0]))
3935 output_asm_insn ("move%.w %2,%0", operands);
3936 return "swap %0\;mov%.w %1,%0";
3939 (define_insn "iorsi_zext"
3940 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d")
3941 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3942 (match_operand:SI 2 "general_operand" "0,0")))]
3948 byte_mode = (GET_MODE (operands[1]) == QImode);
3949 if (GET_CODE (operands[0]) == MEM)
3950 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
3953 return "or%.b %1,%0";
3955 return "or%.w %1,%0";
3960 ;; "xordi3" is mainly here to help combine().
3961 (define_insn "xordi3"
3962 [(set (match_operand:DI 0 "nonimmediate_operand" "=od")
3963 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3964 (match_operand:DI 2 "general_operand" "dn")))]
3968 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3970 if (CONSTANT_P (operands[2]))
3974 split_double (operands[2], &hi, &lo);
3976 switch (INTVAL (hi))
3981 output_asm_insn ("not%.l %0", operands);
3984 /* FIXME : a scratch register would be welcome here if
3985 -128 <= INTVAL (hi) < -1 */
3989 xoperands[0] = operands[0];
3991 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3994 if (GET_CODE (operands[0]) == REG)
3995 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3997 operands[0] = adjust_address (operands[0], SImode, 4);
3998 switch (INTVAL (lo))
4003 output_asm_insn ("not%.l %0", operands);
4006 /* FIXME : a scratch register would be welcome here if
4007 -128 <= INTVAL (lo) < -1 */
4009 /* FIXME : this should be merged with xorsi3 */
4013 xoperands[0] = operands[0];
4015 output_asm_insn (output_xorsi3 (xoperands), xoperands);
4020 if (GET_CODE (operands[0]) != REG)
4022 operands[1] = adjust_address (operands[0], SImode, 4);
4023 return "eor%.l %2,%0\;eor%.l %R2,%1";
4025 if (GET_CODE (operands[2]) != REG)
4027 operands[1] = adjust_address (operands[2], SImode, 4);
4028 return "eor%.l %2,%0\;eor%.l %1,%R0";
4030 return "eor%.l %2,%0\;eor%.l %R2,%R0";
4033 (define_expand "xorsi3"
4034 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4035 (xor:SI (match_operand:SI 1 "general_operand" "")
4036 (match_operand:SI 2 "general_operand" "")))]
4040 (define_insn "xorsi3_internal"
4041 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m")
4042 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4043 (match_operand:SI 2 "general_operand" "di,dKT")))]
4047 return output_xorsi3 (operands);
4050 (define_insn "xorsi3_5200"
4051 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d")
4052 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4053 (match_operand:SI 2 "general_operand" "d,Ks")))]
4056 return output_xorsi3 (operands);
4059 (define_insn "xorhi3"
4060 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4061 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4062 (match_operand:HI 2 "general_operand" "dn")))]
4067 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4068 (xor:HI (match_dup 0)
4069 (match_operand:HI 1 "general_operand" "dn")))]
4074 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4075 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4080 (define_insn "xorqi3"
4081 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4082 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4083 (match_operand:QI 2 "general_operand" "dn")))]
4088 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4089 (xor:QI (match_dup 0)
4090 (match_operand:QI 1 "general_operand" "dn")))]
4095 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4096 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4101 ;; negation instructions
4103 (define_expand "negdi2"
4104 [(set (match_operand:DI 0 "nonimmediate_operand" "")
4105 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4108 if (TARGET_COLDFIRE)
4109 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4111 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4115 (define_insn "negdi2_internal"
4116 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a")
4117 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4120 if (which_alternative == 0)
4121 return "neg%.l %0\;negx%.l %0";
4122 if (GET_CODE (operands[0]) == REG)
4123 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4125 operands[1] = adjust_address (operands[0], SImode, 4);
4126 if (ADDRESS_REG_P (operands[0]))
4127 return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0";
4129 return "neg%.l %1\;negx%.l %0";
4132 (define_insn "negdi2_5200"
4133 [(set (match_operand:DI 0 "nonimmediate_operand" "=d")
4134 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4137 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4138 return "neg%.l %1\;negx%.l %0";
4141 (define_expand "negsi2"
4142 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4143 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4146 if (TARGET_COLDFIRE)
4147 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4149 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4153 (define_insn "negsi2_internal"
4154 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4155 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4158 [(set_attr "type" "neg_l")])
4160 (define_insn "negsi2_5200"
4161 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4162 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4165 [(set_attr "type" "neg_l")])
4167 (define_insn "neghi2"
4168 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4169 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4174 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4175 (neg:HI (match_dup 0)))]
4179 (define_insn "negqi2"
4180 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4181 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4186 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4187 (neg:QI (match_dup 0)))]
4191 ;; If using software floating point, just flip the sign bit.
4193 (define_expand "negsf2"
4194 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4195 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4198 if (!TARGET_HARD_FLOAT)
4203 target = operand_subword_force (operands[0], 0, SFmode);
4204 result = expand_binop (SImode, xor_optab,
4205 operand_subword_force (operands[1], 0, SFmode),
4206 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4207 gcc_assert (result);
4209 if (result != target)
4210 emit_move_insn (result, target);
4212 /* Make a place for REG_EQUAL. */
4213 emit_move_insn (operands[0], operands[0]);
4218 (define_expand "negdf2"
4219 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4220 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4223 if (!TARGET_HARD_FLOAT)
4230 target = operand_subword (operands[0], 0, 1, DFmode);
4231 result = expand_binop (SImode, xor_optab,
4232 operand_subword_force (operands[1], 0, DFmode),
4233 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4234 gcc_assert (result);
4236 if (result != target)
4237 emit_move_insn (result, target);
4239 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4240 operand_subword_force (operands[1], 1, DFmode));
4242 insns = get_insns ();
4250 (define_expand "negxf2"
4251 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4252 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
4262 target = operand_subword (operands[0], 0, 1, XFmode);
4263 result = expand_binop (SImode, xor_optab,
4264 operand_subword_force (operands[1], 0, XFmode),
4265 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN);
4266 gcc_assert (result);
4268 if (result != target)
4269 emit_move_insn (result, target);
4271 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
4272 operand_subword_force (operands[1], 1, XFmode));
4273 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
4274 operand_subword_force (operands[1], 2, XFmode));
4276 insns = get_insns ();
4284 (define_insn "neg<mode>2_68881"
4285 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4286 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
4289 if (DATA_REG_P (operands[0]))
4291 operands[1] = GEN_INT (31);
4292 return "bchg %1,%0";
4294 if (FP_REG_P (operands[1]))
4295 return "f<FP:round>neg%.x %1,%0";
4296 return "f<FP:round>neg%.<FP:prec> %f1,%0";
4299 (define_insn "neg<mode>2_cf"
4300 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4301 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
4302 "TARGET_COLDFIRE_FPU"
4304 if (DATA_REG_P (operands[0]))
4306 operands[1] = GEN_INT (31);
4307 return "bchg %1,%0";
4309 if (FP_REG_P (operands[1]))
4310 return "f<FP:prec>neg%.d %1,%0";
4311 return "f<FP:prec>neg%.<FP:prec> %1,%0";
4314 ;; Sqrt instruction for the 68881
4316 (define_expand "sqrt<mode>2"
4317 [(set (match_operand:FP 0 "nonimmediate_operand" "")
4318 (sqrt:FP (match_operand:FP 1 "general_operand" "")))]
4322 (define_insn "sqrt<mode>2_68881"
4323 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
4324 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
4327 if (FP_REG_P (operands[1]))
4328 return "f<FP:round>sqrt%.x %1,%0";
4329 return "f<FP:round>sqrt%.<FP:prec> %1,%0";
4331 [(set_attr "type" "fsqrt")])
4333 (define_insn "sqrt<mode>2_cf"
4334 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
4335 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))]
4336 "TARGET_COLDFIRE_FPU"
4338 if (FP_REG_P (operands[1]))
4339 return "f<FP:prec>sqrt%.d %1,%0";
4340 return "f<FP:prec>sqrt%.<FP:prec> %1,%0";
4342 [(set_attr "type" "fsqrt")])
4343 ;; Absolute value instructions
4344 ;; If using software floating point, just zero the sign bit.
4346 (define_expand "abssf2"
4347 [(set (match_operand:SF 0 "nonimmediate_operand" "")
4348 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4351 if (!TARGET_HARD_FLOAT)
4356 target = operand_subword_force (operands[0], 0, SFmode);
4357 result = expand_binop (SImode, and_optab,
4358 operand_subword_force (operands[1], 0, SFmode),
4359 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4360 gcc_assert (result);
4362 if (result != target)
4363 emit_move_insn (result, target);
4365 /* Make a place for REG_EQUAL. */
4366 emit_move_insn (operands[0], operands[0]);
4371 (define_expand "absdf2"
4372 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4373 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4376 if (!TARGET_HARD_FLOAT)
4383 target = operand_subword (operands[0], 0, 1, DFmode);
4384 result = expand_binop (SImode, and_optab,
4385 operand_subword_force (operands[1], 0, DFmode),
4386 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4387 gcc_assert (result);
4389 if (result != target)
4390 emit_move_insn (result, target);
4392 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4393 operand_subword_force (operands[1], 1, DFmode));
4395 insns = get_insns ();
4403 (define_expand "absxf2"
4404 [(set (match_operand:XF 0 "nonimmediate_operand" "")
4405 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
4415 target = operand_subword (operands[0], 0, 1, XFmode);
4416 result = expand_binop (SImode, and_optab,
4417 operand_subword_force (operands[1], 0, XFmode),
4418 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN);
4419 gcc_assert (result);
4421 if (result != target)
4422 emit_move_insn (result, target);
4424 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
4425 operand_subword_force (operands[1], 1, XFmode));
4426 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
4427 operand_subword_force (operands[1], 2, XFmode));
4429 insns = get_insns ();
4437 (define_insn "abs<mode>2_68881"
4438 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4439 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))]
4442 if (DATA_REG_P (operands[0]))
4444 operands[1] = GEN_INT (31);
4445 return "bclr %1,%0";
4447 if (FP_REG_P (operands[1]))
4448 return "f<FP:round>abs%.x %1,%0";
4449 return "f<FP:round>abs%.<FP:prec> %f1,%0";
4452 (define_insn "abs<mode>2_cf"
4453 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d")
4454 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))]
4455 "TARGET_COLDFIRE_FPU"
4457 if (DATA_REG_P (operands[0]))
4459 operands[1] = GEN_INT (31);
4460 return "bclr %1,%0";
4462 if (FP_REG_P (operands[1]))
4463 return "f<FP:prec>abs%.d %1,%0";
4464 return "f<FP:prec>abs%.<FP:prec> %1,%0";
4466 [(set_attr "type" "bitrw,fneg")])
4468 ;; bit indexing instructions
4470 ;; ColdFire ff1 instruction implements clz.
4471 (define_insn "clzsi2"
4472 [(set (match_operand:SI 0 "register_operand" "=d")
4473 (clz:SI (match_operand:SI 1 "register_operand" "0")))]
4476 [(set_attr "type" "ext")])
4478 ;; one complement instructions
4480 ;; "one_cmpldi2" is mainly here to help combine().
4481 (define_insn "one_cmpldi2"
4482 [(set (match_operand:DI 0 "nonimmediate_operand" "=dm")
4483 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4487 if (GET_CODE (operands[0]) == REG)
4488 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4489 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4490 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4491 operands[1] = operands[0];
4493 operands[1] = adjust_address (operands[0], SImode, 4);
4494 return "not%.l %1\;not%.l %0";
4497 (define_expand "one_cmplsi2"
4498 [(set (match_operand:SI 0 "nonimmediate_operand" "")
4499 (not:SI (match_operand:SI 1 "general_operand" "")))]
4502 if (TARGET_COLDFIRE)
4503 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4505 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4509 (define_insn "one_cmplsi2_internal"
4510 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm")
4511 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4515 (define_insn "one_cmplsi2_5200"
4516 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
4517 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4520 [(set_attr "type" "neg_l")])
4522 (define_insn "one_cmplhi2"
4523 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
4524 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4529 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm"))
4530 (not:HI (match_dup 0)))]
4534 (define_insn "one_cmplqi2"
4535 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
4536 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4541 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm"))
4542 (not:QI (match_dup 0)))]
4546 ;; arithmetic shift instructions
4547 ;; We don't need the shift memory by 1 bit instruction
4549 (define_insn "ashldi_extsi"
4550 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro")
4552 (match_operator:DI 2 "extend_operator"
4553 [(match_operand:SI 1 "general_operand" "rm")])
4558 if (GET_CODE (operands[0]) == REG)
4559 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4561 operands[2] = adjust_address (operands[0], SImode, 4);
4562 if (ADDRESS_REG_P (operands[0]))
4563 return "move%.l %1,%0\;sub%.l %2,%2";
4565 return "move%.l %1,%0\;clr%.l %2";
4568 (define_insn "ashldi_sexthi"
4569 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d")
4570 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4572 (clobber (match_scratch:SI 2 "=a,X"))]
4576 if (GET_CODE (operands[0]) == MEM)
4578 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4579 return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
4580 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4581 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0";
4584 operands[3] = adjust_address (operands[0], SImode, 4);
4585 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3";
4588 else if (DATA_REG_P (operands[0]))
4589 return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0";
4591 return "move%.w %1,%0\;sub%.l %R0,%R0";
4594 (define_insn "*ashldi3_const1"
4595 [(set (match_operand:DI 0 "register_operand" "=d")
4596 (ashift:DI (match_operand:DI 1 "register_operand" "0")
4599 "add%.l %R0,%R0\;addx%.l %0,%0")
4602 [(set (match_operand:DI 0 "register_operand" "")
4603 (ashift:DI (match_operand:DI 1 "register_operand" "")
4605 "reload_completed && !TARGET_COLDFIRE"
4607 (ashift:DI (match_dup 1) (const_int 1)))
4609 (ashift:DI (match_dup 0) (const_int 1)))]
4613 [(set (match_operand:DI 0 "register_operand" "")
4614 (ashift:DI (match_operand:DI 1 "register_operand" "")
4616 "reload_completed && !TARGET_COLDFIRE"
4618 (ashift:DI (match_dup 1) (const_int 2)))
4620 (ashift:DI (match_dup 0) (const_int 1)))]
4624 [(set (match_operand:DI 0 "register_operand" "")
4625 (ashift:DI (match_operand:DI 1 "register_operand" "")
4627 "reload_completed && !TARGET_COLDFIRE"
4629 (rotate:SI (match_dup 2) (const_int 8)))
4631 (rotate:SI (match_dup 3) (const_int 8)))
4632 (set (strict_low_part (subreg:QI (match_dup 0) 3))
4633 (subreg:QI (match_dup 0) 7))
4634 (set (strict_low_part (subreg:QI (match_dup 0) 7))
4637 operands[2] = gen_highpart (SImode, operands[0]);
4638 operands[3] = gen_lowpart (SImode, operands[0]);
4642 [(set (match_operand:DI 0 "register_operand" "")
4643 (ashift:DI (match_operand:DI 1 "register_operand" "")
4645 "reload_completed && !TARGET_COLDFIRE"
4647 (rotate:SI (match_dup 2) (const_int 16)))
4649 (rotate:SI (match_dup 3) (const_int 16)))
4650 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4651 (subreg:HI (match_dup 0) 6))
4652 (set (strict_low_part (subreg:HI (match_dup 0) 6))
4655 operands[2] = gen_highpart (SImode, operands[0]);
4656 operands[3] = gen_lowpart (SImode, operands[0]);
4660 [(set (match_operand:DI 0 "pre_dec_operand" "")
4661 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
4664 [(set (match_dup 0) (const_int 0))
4665 (set (match_dup 0) (match_dup 1))]
4667 operands[0] = adjust_address(operands[0], SImode, 0);
4668 operands[1] = gen_lowpart(SImode, operands[1]);
4672 [(set (match_operand:DI 0 "post_inc_operand" "")
4673 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "")
4676 [(set (match_dup 0) (match_dup 1))
4677 (set (match_dup 0) (const_int 0))]
4679 operands[0] = adjust_address(operands[0], SImode, 0);
4680 operands[1] = gen_lowpart(SImode, operands[1]);
4683 (define_insn_and_split "*ashldi3_const32"
4684 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
4685 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro")
4689 "&& reload_completed"
4690 [(set (match_dup 4) (match_dup 3))
4691 (set (match_dup 2) (const_int 0))]
4692 "split_di(operands, 2, operands + 2, operands + 4);")
4695 [(set (match_operand:DI 0 "register_operand" "")
4696 (ashift:DI (match_operand:DI 1 "register_operand" "")
4697 (match_operand 2 "const_int_operand" "")))]
4698 "reload_completed && !TARGET_COLDFIRE
4699 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
4700 [(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2)))
4701 (set (match_dup 3) (match_dup 4))
4702 (set (match_dup 4) (const_int 0))]
4704 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4705 operands[3] = gen_highpart (SImode, operands[0]);
4706 operands[4] = gen_lowpart (SImode, operands[0]);
4710 [(set (match_operand:DI 0 "register_operand" "")
4711 (ashift:DI (match_operand:DI 1 "register_operand" "")
4713 "reload_completed && !TARGET_COLDFIRE"
4714 [(set (match_dup 2) (match_dup 3))
4716 (rotate:SI (match_dup 2) (const_int 16)))
4717 (set (match_dup 3) (const_int 0))
4718 (set (strict_low_part (subreg:HI (match_dup 0) 2))
4721 operands[2] = gen_highpart (SImode, operands[0]);
4722 operands[3] = gen_lowpart (SImode, operands[0]);
4726 [(set (match_operand:DI 0 "register_operand" "")
4727 (ashift:DI (match_operand:DI 1 "register_operand" "")
4728 (match_operand 2 "const_int_operand" "")))]
4729 "reload_completed && !TARGET_COLDFIRE
4730 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63"
4731 [(set (match_dup 3) (match_dup 2))
4732 (set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 3)))
4733 (set (match_dup 3) (match_dup 4))
4734 (set (match_dup 4) (const_int 0))]
4736 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4737 operands[3] = gen_highpart (SImode, operands[0]);
4738 operands[4] = gen_lowpart (SImode, operands[0]);
4741 (define_insn "*ashldi3"
4742 [(set (match_operand:DI 0 "register_operand" "=d")
4743 (ashift:DI (match_operand:DI 1 "register_operand" "0")
4744 (match_operand 2 "const_int_operand" "n")))]
4746 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4747 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4748 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4751 (define_expand "ashldi3"
4752 [(set (match_operand:DI 0 "register_operand" "")
4753 (ashift:DI (match_operand:DI 1 "register_operand" "")
4754 (match_operand 2 "const_int_operand" "")))]
4757 /* ??? This is a named pattern like this is not allowed to FAIL based
4759 if (GET_CODE (operands[2]) != CONST_INT
4760 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4761 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4762 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4766 ;; On most 68k models, this makes faster code in a special case.
4768 (define_insn "ashlsi_16"
4769 [(set (match_operand:SI 0 "register_operand" "=d")
4770 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4775 return "swap %0\;clr%.w %0";
4778 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4779 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4781 ;; On the 68000, this makes faster code in a special case.
4783 (define_insn "ashlsi_17_24"
4784 [(set (match_operand:SI 0 "register_operand" "=d")
4785 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4786 (match_operand:SI 2 "const_int_operand" "n")))]
4788 && INTVAL (operands[2]) > 16
4789 && INTVAL (operands[2]) <= 24"
4793 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4794 return "lsl%.w %2,%0\;swap %0\;clr%.w %0";
4797 (define_insn "ashlsi3"
4798 [(set (match_operand:SI 0 "register_operand" "=d")
4799 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4800 (match_operand:SI 2 "general_operand" "dI")))]
4803 if (operands[2] == const1_rtx)
4805 cc_status.flags = CC_NO_OVERFLOW;
4806 return "add%.l %0,%0";
4808 return "lsl%.l %2,%0";
4811 (define_insn "ashlhi3"
4812 [(set (match_operand:HI 0 "register_operand" "=d")
4813 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4814 (match_operand:HI 2 "general_operand" "dI")))]
4819 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4820 (ashift:HI (match_dup 0)
4821 (match_operand:HI 1 "general_operand" "dI")))]
4825 (define_insn "ashlqi3"
4826 [(set (match_operand:QI 0 "register_operand" "=d")
4827 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4828 (match_operand:QI 2 "general_operand" "dI")))]
4833 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4834 (ashift:QI (match_dup 0)
4835 (match_operand:QI 1 "general_operand" "dI")))]
4839 ;; On most 68k models, this makes faster code in a special case.
4841 (define_insn "ashrsi_16"
4842 [(set (match_operand:SI 0 "register_operand" "=d")
4843 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4846 "swap %0\;ext%.l %0")
4848 ;; On the 68000, this makes faster code in a special case.
4851 [(set (match_operand:SI 0 "register_operand" "=d")
4852 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4853 (match_operand:SI 2 "const_int_operand" "n")))]
4855 && INTVAL (operands[2]) > 16
4856 && INTVAL (operands[2]) <= 24"
4858 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4859 return "swap %0\;asr%.w %2,%0\;ext%.l %0";
4862 (define_insn "subreghi1ashrdi_const32"
4863 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
4864 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4865 (const_int 32)) 6))]
4868 if (GET_CODE (operands[1]) != REG)
4869 operands[1] = adjust_address (operands[1], HImode, 2);
4870 return "move%.w %1,%0";
4872 [(set_attr "type" "move")])
4874 (define_insn "subregsi1ashrdi_const32"
4875 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
4876 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4877 (const_int 32)) 4))]
4880 return "move%.l %1,%0";
4882 [(set_attr "type" "move_l")])
4884 (define_insn "*ashrdi3_const1"
4885 [(set (match_operand:DI 0 "register_operand" "=d")
4886 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4890 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4891 return "asr%.l #1,%0\;roxr%.l #1,%1";
4895 [(set (match_operand:DI 0 "register_operand" "")
4896 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4898 "reload_completed && !TARGET_COLDFIRE"
4900 (ashiftrt:DI (match_dup 1) (const_int 1)))
4902 (ashiftrt:DI (match_dup 0) (const_int 1)))]
4906 [(set (match_operand:DI 0 "register_operand" "")
4907 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4909 "reload_completed && !TARGET_COLDFIRE"
4911 (ashiftrt:DI (match_dup 1) (const_int 2)))
4913 (ashiftrt:DI (match_dup 0) (const_int 1)))]
4917 [(set (match_operand:DI 0 "register_operand" "")
4918 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4920 "reload_completed && !TARGET_COLDFIRE"
4921 [(set (strict_low_part (subreg:QI (match_dup 0) 7))
4922 (subreg:QI (match_dup 0) 3))
4924 (ashiftrt:SI (match_dup 2) (const_int 8)))
4926 (rotatert:SI (match_dup 3) (const_int 8)))]
4928 operands[2] = gen_highpart (SImode, operands[0]);
4929 operands[3] = gen_lowpart (SImode, operands[0]);
4933 [(set (match_operand:DI 0 "register_operand" "")
4934 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4936 "reload_completed && !TARGET_COLDFIRE"
4937 [(set (strict_low_part (subreg:HI (match_dup 0) 6))
4938 (subreg:HI (match_dup 0) 2))
4940 (rotate:SI (match_dup 2) (const_int 16)))
4942 (rotate:SI (match_dup 3) (const_int 16)))
4944 (sign_extend:SI (subreg:HI (match_dup 2) 2)))]
4946 operands[2] = gen_highpart (SImode, operands[0]);
4947 operands[3] = gen_lowpart (SImode, operands[0]);
4950 (define_insn "*ashrdi_const32"
4951 [(set (match_operand:DI 0 "register_operand" "=d")
4952 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro")
4958 return "move%.l %1,%R0\;smi %0\;extb%.l %0";
4960 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0";
4963 (define_insn "*ashrdi_const32_mem"
4964 [(set (match_operand:DI 0 "memory_operand" "=o,<")
4965 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro,ro")
4967 (clobber (match_scratch:SI 2 "=d,d"))]
4971 operands[3] = adjust_address (operands[0], SImode,
4972 which_alternative == 0 ? 4 : 0);
4973 operands[0] = adjust_address (operands[0], SImode, 0);
4974 if (TARGET_68020 || TARGET_COLDFIRE)
4975 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0";
4977 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0";
4981 [(set (match_operand:DI 0 "register_operand" "")
4982 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4984 "reload_completed && !TARGET_COLDFIRE"
4986 (ashiftrt:SI (match_dup 3) (const_int 31)))
4989 "split_di(operands, 1, operands + 2, operands + 3);")
4991 ;; The predicate below must be general_operand, because ashrdi3 allows that
4992 (define_insn "ashrdi_const"
4993 [(set (match_operand:DI 0 "register_operand" "=d")
4994 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
4995 (match_operand 2 "const_int_operand" "n")))]
4997 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4998 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4999 || INTVAL (operands[2]) == 31
5000 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
5002 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5004 if (INTVAL (operands[2]) == 48)
5005 return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0";
5006 if (INTVAL (operands[2]) == 31)
5007 return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0";
5008 if (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)
5010 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5011 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" :
5012 "moveq %2,%1\;asr%.l %1,%0", operands);
5013 output_asm_insn ("mov%.l %0,%1\;smi %0", operands);
5014 return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" :
5015 TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0";
5020 (define_expand "ashrdi3"
5021 [(set (match_operand:DI 0 "register_operand" "")
5022 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5023 (match_operand 2 "const_int_operand" "")))]
5026 /* ??? This is a named pattern like this is not allowed to FAIL based
5028 if (GET_CODE (operands[2]) != CONST_INT
5029 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5030 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5031 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
5035 ;; On all 68k models, this makes faster code in a special case.
5037 (define_insn "ashrsi_31"
5038 [(set (match_operand:SI 0 "register_operand" "=d")
5039 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5043 return "add%.l %0,%0\;subx%.l %0,%0";
5046 (define_insn "ashrsi3"
5047 [(set (match_operand:SI 0 "register_operand" "=d")
5048 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
5049 (match_operand:SI 2 "general_operand" "dI")))]
5052 [(set_attr "type" "shift")
5053 (set_attr "opy" "2")])
5055 (define_insn "ashrhi3"
5056 [(set (match_operand:HI 0 "register_operand" "=d")
5057 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
5058 (match_operand:HI 2 "general_operand" "dI")))]
5063 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5064 (ashiftrt:HI (match_dup 0)
5065 (match_operand:HI 1 "general_operand" "dI")))]
5069 (define_insn "ashrqi3"
5070 [(set (match_operand:QI 0 "register_operand" "=d")
5071 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
5072 (match_operand:QI 2 "general_operand" "dI")))]
5077 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5078 (ashiftrt:QI (match_dup 0)
5079 (match_operand:QI 1 "general_operand" "dI")))]
5083 ;; logical shift instructions
5085 ;; commented out because of reload problems in 950612-1.c
5088 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
5089 ;; (const_int 32)) 4))
5090 ;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm")
5091 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
5092 ;; (const_int 32)) 4))]
5095 ;; return "move%.l %0,%1";
5100 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
5101 ;; (const_int 32)) 0))
5102 ;; (set (match_operand:DI 1 "nonimmediate_operand" "=do")
5103 ;; (lshiftrt:DI (match_dup 0)
5104 ;; (const_int 32)))]
5107 ;; if (GET_CODE (operands[1]) == REG)
5108 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
5110 ;; operands[2] = adjust_address (operands[1], SImode, 4);
5111 ;; return "move%.l %0,%2\;clr%.l %1";
5114 (define_insn "subreg1lshrdi_const32"
5115 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5116 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
5117 (const_int 32)) 4))]
5120 [(set_attr "type" "move_l")])
5122 (define_insn "*lshrdi3_const1"
5123 [(set (match_operand:DI 0 "register_operand" "=d")
5124 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
5127 "lsr%.l #1,%0\;roxr%.l #1,%R0")
5130 [(set (match_operand:DI 0 "register_operand" "")
5131 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5133 "reload_completed && !TARGET_COLDFIRE"
5135 (lshiftrt:DI (match_dup 1) (const_int 1)))
5137 (lshiftrt:DI (match_dup 0) (const_int 1)))]
5141 [(set (match_operand:DI 0 "register_operand" "")
5142 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5144 "reload_completed && !TARGET_COLDFIRE"
5146 (lshiftrt:DI (match_dup 1) (const_int 2)))
5148 (lshiftrt:DI (match_dup 0) (const_int 1)))]
5152 [(set (match_operand:DI 0 "register_operand" "")
5153 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5155 "reload_completed && !TARGET_COLDFIRE"
5156 [(set (strict_low_part (subreg:QI (match_dup 0) 7))
5157 (subreg:QI (match_dup 0) 3))
5159 (lshiftrt:SI (match_dup 2) (const_int 8)))
5161 (rotatert:SI (match_dup 3) (const_int 8)))]
5163 operands[2] = gen_highpart (SImode, operands[0]);
5164 operands[3] = gen_lowpart (SImode, operands[0]);
5168 [(set (match_operand:DI 0 "register_operand" "")
5169 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5171 "reload_completed && !TARGET_COLDFIRE"
5172 [(set (strict_low_part (subreg:HI (match_dup 0) 6))
5173 (subreg:HI (match_dup 0) 2))
5174 (set (strict_low_part (subreg:HI (match_dup 0) 2))
5177 (rotate:SI (match_dup 3) (const_int 16)))
5179 (rotate:SI (match_dup 2) (const_int 16)))]
5181 operands[2] = gen_highpart (SImode, operands[0]);
5182 operands[3] = gen_lowpart (SImode, operands[0]);
5186 [(set (match_operand:DI 0 "pre_dec_operand" "")
5187 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5190 [(set (match_dup 0) (match_dup 1))
5191 (set (match_dup 0) (const_int 0))]
5193 operands[0] = adjust_address(operands[0], SImode, 0);
5194 operands[1] = gen_highpart(SImode, operands[1]);
5198 [(set (match_operand:DI 0 "post_inc_operand" "")
5199 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5202 [(set (match_dup 0) (const_int 0))
5203 (set (match_dup 0) (match_dup 1))]
5205 operands[0] = adjust_address(operands[0], SImode, 0);
5206 operands[1] = gen_highpart(SImode, operands[1]);
5210 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5211 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "")
5214 [(set (match_dup 2) (match_dup 5))
5215 (set (match_dup 4) (const_int 0))]
5216 "split_di(operands, 2, operands + 2, operands + 4);")
5218 (define_insn "*lshrdi_const32"
5219 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>")
5220 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
5226 [(set (match_operand:DI 0 "register_operand" "")
5227 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5228 (match_operand 2 "const_int_operand" "")))]
5229 "reload_completed && !TARGET_COLDFIRE
5230 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40"
5231 [(set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 2)))
5232 (set (match_dup 4) (match_dup 3))
5233 (set (match_dup 3) (const_int 0))]
5235 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5236 operands[3] = gen_highpart (SImode, operands[0]);
5237 operands[4] = gen_lowpart (SImode, operands[0]);
5241 [(set (match_operand:DI 0 "register_operand" "")
5242 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5245 [(set (match_dup 3) (match_dup 2))
5246 (set (strict_low_part (subreg:HI (match_dup 0) 6))
5248 (set (match_dup 2) (const_int 0))
5250 (rotate:SI (match_dup 3) (const_int 16)))]
5252 operands[2] = gen_highpart (SImode, operands[0]);
5253 operands[3] = gen_lowpart (SImode, operands[0]);
5257 [(set (match_operand:DI 0 "register_operand" "")
5258 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5259 (match_operand 2 "const_int_operand" "")))]
5260 "reload_completed && !TARGET_COLDFIRE
5261 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 62"
5262 [(set (match_dup 4) (match_dup 2))
5263 (set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 4)))
5264 (set (match_dup 4) (match_dup 3))
5265 (set (match_dup 3) (const_int 0))]
5267 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
5268 operands[3] = gen_highpart (SImode, operands[0]);
5269 operands[4] = gen_lowpart (SImode, operands[0]);
5272 (define_insn "*lshrdi_const63"
5273 [(set (match_operand:DI 0 "register_operand" "=d")
5274 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
5277 "add%.l %0,%0\;clr%.l %0\;clr%.l %R1\;addx%.l %R1,%R1")
5279 (define_insn "*lshrdi3_const"
5280 [(set (match_operand:DI 0 "register_operand" "=d")
5281 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
5282 (match_operand 2 "const_int_operand" "n")))]
5284 && ((INTVAL (operands[2]) >= 2 && INTVAL (operands[2]) <= 3)
5285 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
5286 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))"
5289 (define_expand "lshrdi3"
5290 [(set (match_operand:DI 0 "register_operand" "")
5291 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
5292 (match_operand 2 "const_int_operand" "")))]
5295 /* ??? This is a named pattern like this is not allowed to FAIL based
5297 if (GET_CODE (operands[2]) != CONST_INT
5298 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
5299 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
5300 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
5304 ;; On all 68k models, this makes faster code in a special case.
5306 (define_insn "lshrsi_31"
5307 [(set (match_operand:SI 0 "register_operand" "=d")
5308 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5312 return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0";
5315 ;; On most 68k models, this makes faster code in a special case.
5317 (define_insn "lshrsi_16"
5318 [(set (match_operand:SI 0 "register_operand" "=d")
5319 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5324 return "clr%.w %0\;swap %0";
5327 ;; On the 68000, this makes faster code in a special case.
5329 (define_insn "lshrsi_17_24"
5330 [(set (match_operand:SI 0 "register_operand" "=d")
5331 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5332 (match_operand:SI 2 "const_int_operand" "n")))]
5334 && INTVAL (operands[2]) > 16
5335 && INTVAL (operands[2]) <= 24"
5337 /* I think lsr%.w sets the CC properly. */
5338 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5339 return "clr%.w %0\;swap %0\;lsr%.w %2,%0";
5342 (define_insn "lshrsi3"
5343 [(set (match_operand:SI 0 "register_operand" "=d")
5344 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5345 (match_operand:SI 2 "general_operand" "dI")))]
5348 [(set_attr "type" "shift")
5349 (set_attr "opy" "2")])
5351 (define_insn "lshrhi3"
5352 [(set (match_operand:HI 0 "register_operand" "=d")
5353 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5354 (match_operand:HI 2 "general_operand" "dI")))]
5359 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5360 (lshiftrt:HI (match_dup 0)
5361 (match_operand:HI 1 "general_operand" "dI")))]
5365 (define_insn "lshrqi3"
5366 [(set (match_operand:QI 0 "register_operand" "=d")
5367 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5368 (match_operand:QI 2 "general_operand" "dI")))]
5373 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5374 (lshiftrt:QI (match_dup 0)
5375 (match_operand:QI 1 "general_operand" "dI")))]
5379 ;; rotate instructions
5381 (define_insn "rotlsi_16"
5382 [(set (match_operand:SI 0 "register_operand" "=d")
5383 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5387 [(set_attr "type" "shift")])
5389 (define_insn "rotlsi3"
5390 [(set (match_operand:SI 0 "register_operand" "=d")
5391 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5392 (match_operand:SI 2 "general_operand" "dINO")))]
5395 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5397 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5399 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5400 return "ror%.l %2,%0";
5403 return "rol%.l %2,%0";
5406 (define_insn "rotlhi3"
5407 [(set (match_operand:HI 0 "register_operand" "=d")
5408 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5409 (match_operand:HI 2 "general_operand" "dIP")))]
5412 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5414 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5415 return "ror%.w %2,%0";
5418 return "rol%.w %2,%0";
5422 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5423 (rotate:HI (match_dup 0)
5424 (match_operand:HI 1 "general_operand" "dIP")))]
5427 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5429 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5430 return "ror%.w %2,%0";
5433 return "rol%.w %2,%0";
5436 (define_insn "rotlqi3"
5437 [(set (match_operand:QI 0 "register_operand" "=d")
5438 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5439 (match_operand:QI 2 "general_operand" "dI")))]
5442 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5444 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5445 return "ror%.b %2,%0";
5448 return "rol%.b %2,%0";
5452 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5453 (rotate:QI (match_dup 0)
5454 (match_operand:QI 1 "general_operand" "dI")))]
5457 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5459 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5460 return "ror%.b %2,%0";
5463 return "rol%.b %2,%0";
5466 (define_insn "rotrsi3"
5467 [(set (match_operand:SI 0 "register_operand" "=d")
5468 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5469 (match_operand:SI 2 "general_operand" "dI")))]
5473 (define_insn "rotrhi3"
5474 [(set (match_operand:HI 0 "register_operand" "=d")
5475 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5476 (match_operand:HI 2 "general_operand" "dI")))]
5480 (define_insn "rotrhi_lowpart"
5481 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5482 (rotatert:HI (match_dup 0)
5483 (match_operand:HI 1 "general_operand" "dI")))]
5487 (define_insn "rotrqi3"
5488 [(set (match_operand:QI 0 "register_operand" "=d")
5489 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5490 (match_operand:QI 2 "general_operand" "dI")))]
5495 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5496 (rotatert:QI (match_dup 0)
5497 (match_operand:QI 1 "general_operand" "dI")))]
5501 (define_expand "bswapsi2"
5502 [(set (match_operand:SI 0 "register_operand")
5503 (bswap:SI (match_operand:SI 1 "register_operand")))]
5506 rtx x = operands[0];
5507 emit_move_insn (x, operands[1]);
5508 emit_insn (gen_rotrhi_lowpart (gen_lowpart (HImode, x), GEN_INT (8)));
5509 emit_insn (gen_rotlsi3 (x, x, GEN_INT (16)));
5510 emit_insn (gen_rotrhi_lowpart (gen_lowpart (HImode, x), GEN_INT (8)));
5515 ;; Bit set/clear in memory byte.
5517 ;; set bit, bit number is int
5518 (define_insn "bsetmemqi"
5519 [(set (match_operand:QI 0 "memory_operand" "+m")
5520 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5521 (match_operand:SI 1 "general_operand" "d")) 3)
5526 return "bset %1,%0";
5528 [(set_attr "type" "bitrw")])
5530 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5531 (define_insn "*bsetmemqi_ext"
5532 [(set (match_operand:QI 0 "memory_operand" "+m")
5533 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5534 (match_operator:SI 2 "extend_operator"
5535 [(match_operand 1 "general_operand" "d")])) 3)
5540 return "bset %1,%0";
5542 [(set_attr "type" "bitrw")])
5544 ;; clear bit, bit number is int
5545 (define_insn "bclrmemqi"
5546 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5548 (minus:SI (const_int 7)
5549 (match_operand:SI 1 "general_operand" "d")))
5554 return "bclr %1,%0";
5556 [(set_attr "type" "bitrw")])
5558 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5559 (define_insn "*bclrmemqi_ext"
5560 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5562 (minus:SI (const_int 7)
5563 (match_operator:SI 2 "extend_operator"
5564 [(match_operand 1 "general_operand" "d")])))
5569 return "bclr %1,%0";
5571 [(set_attr "type" "bitrw")])
5573 ;; Special cases of bit-field insns which we should
5574 ;; recognize in preference to the general case.
5575 ;; These handle aligned 8-bit and 16-bit fields,
5576 ;; which can usually be done with move instructions.
5579 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5580 ; alignment of structure members is specified.
5582 ; The move is allowed to be odd byte aligned, because that's still faster
5583 ; than an odd byte aligned bit-field instruction.
5586 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5588 (match_operand:SI 1 "const_int_operand" "n"))
5589 (match_operand:SI 2 "general_src_operand" "rmSi"))]
5590 "TARGET_68020 && TARGET_BITFIELD
5591 && (INTVAL (operands[1]) % 8) == 0
5592 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5595 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8);
5597 return "move%.l %2,%0";
5601 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5602 (match_operand:SI 1 "const_int_operand" "n")
5603 (match_operand:SI 2 "const_int_operand" "n"))
5604 (match_operand:SI 3 "register_operand" "d"))]
5605 "TARGET_68020 && TARGET_BITFIELD
5606 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5607 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5608 && (GET_CODE (operands[0]) == REG
5609 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5611 if (REG_P (operands[0]))
5613 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5614 return "bfins %3,%0{%b2:%b1}";
5617 operands[0] = adjust_address (operands[0],
5618 INTVAL (operands[1]) == 8 ? QImode : HImode,
5619 INTVAL (operands[2]) / 8);
5621 if (GET_CODE (operands[3]) == MEM)
5622 operands[3] = adjust_address (operands[3],
5623 INTVAL (operands[1]) == 8 ? QImode : HImode,
5624 (32 - INTVAL (operands[1])) / 8);
5626 if (INTVAL (operands[1]) == 8)
5627 return "move%.b %3,%0";
5628 return "move%.w %3,%0";
5633 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5634 ; alignment of structure members is specified.
5636 ; The move is allowed to be odd byte aligned, because that's still faster
5637 ; than an odd byte aligned bit-field instruction.
5640 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5641 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5643 (match_operand:SI 2 "const_int_operand" "n")))]
5644 "TARGET_68020 && TARGET_BITFIELD
5645 && (INTVAL (operands[2]) % 8) == 0
5646 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5649 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5651 return "move%.l %1,%0";
5655 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d")
5656 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5657 (match_operand:SI 2 "const_int_operand" "n")
5658 (match_operand:SI 3 "const_int_operand" "n")))]
5659 "TARGET_68020 && TARGET_BITFIELD
5660 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5661 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5662 && (GET_CODE (operands[1]) == REG
5663 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5665 cc_status.flags |= CC_NOT_NEGATIVE;
5666 if (REG_P (operands[1]))
5668 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5669 return "bfextu %1{%b3:%b2},%0";
5673 = adjust_address (operands[1], SImode, INTVAL (operands[3]) / 8);
5675 output_asm_insn ("clr%.l %0", operands);
5676 if (GET_CODE (operands[0]) == MEM)
5677 operands[0] = adjust_address (operands[0],
5678 INTVAL (operands[2]) == 8 ? QImode : HImode,
5679 (32 - INTVAL (operands[1])) / 8);
5681 if (INTVAL (operands[2]) == 8)
5682 return "move%.b %1,%0";
5683 return "move%.w %1,%0";
5687 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5688 ; alignment of structure members is specified.
5690 ; The move is allowed to be odd byte aligned, because that's still faster
5691 ; than an odd byte aligned bit-field instruction.
5694 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5695 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS")
5697 (match_operand:SI 2 "const_int_operand" "n")))]
5698 "TARGET_68020 && TARGET_BITFIELD
5699 && (INTVAL (operands[2]) % 8) == 0
5700 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5703 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8);
5705 return "move%.l %1,%0";
5709 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5710 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5711 (match_operand:SI 2 "const_int_operand" "n")
5712 (match_operand:SI 3 "const_int_operand" "n")))]
5713 "TARGET_68020 && TARGET_BITFIELD
5714 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5715 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5716 && (GET_CODE (operands[1]) == REG
5717 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5719 if (REG_P (operands[1]))
5721 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5722 return "bfexts %1{%b3:%b2},%0";
5726 = adjust_address (operands[1],
5727 INTVAL (operands[2]) == 8 ? QImode : HImode,
5728 INTVAL (operands[3]) / 8);
5730 if (INTVAL (operands[2]) == 8)
5731 return "move%.b %1,%0\;extb%.l %0";
5732 return "move%.w %1,%0\;ext%.l %0";
5735 ;; Bit-field instructions, general cases.
5736 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5737 ;; so that its address is reloaded.
5739 (define_expand "extv"
5740 [(set (match_operand:SI 0 "register_operand" "")
5741 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5742 (match_operand:SI 2 "const_int_operand" "")
5743 (match_operand:SI 3 "const_int_operand" "")))]
5744 "TARGET_68020 && TARGET_BITFIELD"
5748 [(set (match_operand:SI 0 "register_operand" "=d")
5749 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5750 (match_operand:SI 2 "nonmemory_operand" "dn")
5751 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5752 "TARGET_68020 && TARGET_BITFIELD"
5753 "bfexts %1{%b3:%b2},%0")
5755 (define_expand "extzv"
5756 [(set (match_operand:SI 0 "register_operand" "")
5757 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5758 (match_operand:SI 2 "const_int_operand" "")
5759 (match_operand:SI 3 "const_int_operand" "")))]
5760 "TARGET_68020 && TARGET_BITFIELD"
5764 [(set (match_operand:SI 0 "register_operand" "=d")
5765 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5766 (match_operand:SI 2 "nonmemory_operand" "dn")
5767 (match_operand:SI 3 "nonmemory_operand" "dn")))]
5768 "TARGET_68020 && TARGET_BITFIELD"
5770 if (GET_CODE (operands[2]) == CONST_INT)
5772 if (INTVAL (operands[2]) != 32)
5773 cc_status.flags |= CC_NOT_NEGATIVE;
5779 return "bfextu %1{%b3:%b2},%0";
5783 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5784 (match_operand:SI 1 "nonmemory_operand" "dn")
5785 (match_operand:SI 2 "nonmemory_operand" "dn"))
5786 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5787 (match_operand 3 "const_int_operand" "n")))]
5788 "TARGET_68020 && TARGET_BITFIELD
5789 && (INTVAL (operands[3]) == -1
5790 || (GET_CODE (operands[1]) == CONST_INT
5791 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5794 return "bfchg %0{%b2:%b1}";
5798 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5799 (match_operand:SI 1 "nonmemory_operand" "dn")
5800 (match_operand:SI 2 "nonmemory_operand" "dn"))
5802 "TARGET_68020 && TARGET_BITFIELD"
5805 return "bfclr %0{%b2:%b1}";
5809 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5810 (match_operand:SI 1 "general_operand" "dn")
5811 (match_operand:SI 2 "general_operand" "dn"))
5813 "TARGET_68020 && TARGET_BITFIELD"
5816 return "bfset %0{%b2:%b1}";
5819 (define_expand "insv"
5820 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "")
5821 (match_operand:SI 1 "const_int_operand" "")
5822 (match_operand:SI 2 "const_int_operand" ""))
5823 (match_operand:SI 3 "register_operand" ""))]
5824 "TARGET_68020 && TARGET_BITFIELD"
5828 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5829 (match_operand:SI 1 "nonmemory_operand" "dn")
5830 (match_operand:SI 2 "nonmemory_operand" "dn"))
5831 (match_operand:SI 3 "register_operand" "d"))]
5832 "TARGET_68020 && TARGET_BITFIELD"
5833 "bfins %3,%0{%b2:%b1}")
5835 ;; Now recognize bit-field insns that operate on registers
5836 ;; (or at least were intended to do so).
5839 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5840 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5841 (match_operand:SI 2 "const_int_operand" "n")
5842 (match_operand:SI 3 "const_int_operand" "n")))]
5843 "TARGET_68020 && TARGET_BITFIELD"
5844 "bfexts %1{%b3:%b2},%0")
5847 [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
5848 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5849 (match_operand:SI 2 "const_int_operand" "n")
5850 (match_operand:SI 3 "const_int_operand" "n")))]
5851 "TARGET_68020 && TARGET_BITFIELD"
5853 if (GET_CODE (operands[2]) == CONST_INT)
5855 if (INTVAL (operands[2]) != 32)
5856 cc_status.flags |= CC_NOT_NEGATIVE;
5862 return "bfextu %1{%b3:%b2},%0";
5866 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5867 (match_operand:SI 1 "const_int_operand" "n")
5868 (match_operand:SI 2 "const_int_operand" "n"))
5870 "TARGET_68020 && TARGET_BITFIELD"
5873 return "bfclr %0{%b2:%b1}";
5877 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5878 (match_operand:SI 1 "const_int_operand" "n")
5879 (match_operand:SI 2 "const_int_operand" "n"))
5881 "TARGET_68020 && TARGET_BITFIELD"
5884 return "bfset %0{%b2:%b1}";
5888 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5889 (match_operand:SI 1 "const_int_operand" "n")
5890 (match_operand:SI 2 "const_int_operand" "n"))
5891 (match_operand:SI 3 "register_operand" "d"))]
5892 "TARGET_68020 && TARGET_BITFIELD"
5895 /* These special cases are now recognized by a specific pattern. */
5896 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5897 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5898 return "move%.w %3,%0";
5899 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5900 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5901 return "move%.b %3,%0";
5903 return "bfins %3,%0{%b2:%b1}";
5906 ;; Special patterns for optimizing bit-field instructions.
5910 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5911 (match_operand:SI 1 "const_int_operand" "n")
5912 (match_operand:SI 2 "general_operand" "dn"))
5914 "TARGET_68020 && TARGET_BITFIELD"
5916 if (operands[1] == const1_rtx
5917 && GET_CODE (operands[2]) == CONST_INT)
5919 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5920 return output_btst (operands,
5921 GEN_INT (width - INTVAL (operands[2])),
5922 operands[0], insn, 1000);
5923 /* Pass 1000 as SIGNPOS argument so that btst will
5924 not think we are testing the sign bit for an `and'
5925 and assume that nonzero implies a negative result. */
5927 if (INTVAL (operands[1]) != 32)
5928 cc_status.flags = CC_NOT_NEGATIVE;
5929 return "bftst %0{%b2:%b1}";
5933 ;;; now handle the register cases
5936 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5937 (match_operand:SI 1 "const_int_operand" "n")
5938 (match_operand:SI 2 "general_operand" "dn"))
5940 "TARGET_68020 && TARGET_BITFIELD"
5942 if (operands[1] == const1_rtx
5943 && GET_CODE (operands[2]) == CONST_INT)
5945 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5946 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
5947 operands[0], insn, 1000);
5948 /* Pass 1000 as SIGNPOS argument so that btst will
5949 not think we are testing the sign bit for an `and'
5950 and assume that nonzero implies a negative result. */
5952 if (INTVAL (operands[1]) != 32)
5953 cc_status.flags = CC_NOT_NEGATIVE;
5954 return "bftst %0{%b2:%b1}";
5957 (define_insn "scc0_di"
5958 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm")
5959 (match_operator 1 "ordered_comparison_operator"
5960 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5963 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5966 (define_insn "scc0_di_5200"
5967 [(set (match_operand:QI 0 "nonimmediate_operand" "=d")
5968 (match_operator 1 "ordered_comparison_operator"
5969 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5972 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5975 (define_insn "scc_di"
5976 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm")
5977 (match_operator 1 "ordered_comparison_operator"
5978 [(match_operand:DI 2 "general_operand" "ro,r")
5979 (match_operand:DI 3 "general_operand" "r,ro")]))]
5982 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5985 (define_insn "scc_di_5200"
5986 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d")
5987 (match_operator 1 "ordered_comparison_operator"
5988 [(match_operand:DI 2 "general_operand" "ro,r")
5989 (match_operand:DI 3 "general_operand" "r,ro")]))]
5992 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5995 ;; Note that operand 0 of an SCC insn is supported in the hardware as
5996 ;; memory, but we cannot allow it to be in memory in case the address
5997 ;; needs to be reloaded.
6000 [(set (match_operand:QI 0 "register_operand" "=d")
6001 (eq:QI (cc0) (const_int 0)))]
6004 cc_status = cc_prev_status;
6005 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");
6009 [(set (match_operand:QI 0 "register_operand" "=d")
6010 (ne:QI (cc0) (const_int 0)))]
6013 cc_status = cc_prev_status;
6014 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");
6018 [(set (match_operand:QI 0 "register_operand" "=d")
6019 (gt:QI (cc0) (const_int 0)))]
6022 cc_status = cc_prev_status;
6023 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);
6027 [(set (match_operand:QI 0 "register_operand" "=d")
6028 (gtu:QI (cc0) (const_int 0)))]
6031 cc_status = cc_prev_status;
6036 [(set (match_operand:QI 0 "register_operand" "=d")
6037 (lt:QI (cc0) (const_int 0)))]
6040 cc_status = cc_prev_status;
6041 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
6045 [(set (match_operand:QI 0 "register_operand" "=d")
6046 (ltu:QI (cc0) (const_int 0)))]
6049 cc_status = cc_prev_status;
6054 [(set (match_operand:QI 0 "register_operand" "=d")
6055 (ge:QI (cc0) (const_int 0)))]
6058 cc_status = cc_prev_status;
6059 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
6063 [(set (match_operand:QI 0 "register_operand" "=d")
6064 (geu:QI (cc0) (const_int 0)))]
6067 cc_status = cc_prev_status;
6070 [(set_attr "type" "scc")])
6073 [(set (match_operand:QI 0 "register_operand" "=d")
6074 (le:QI (cc0) (const_int 0)))]
6077 cc_status = cc_prev_status;
6078 OUTPUT_JUMP ("sle %0", "fsle %0", 0);
6082 [(set (match_operand:QI 0 "register_operand" "=d")
6083 (leu:QI (cc0) (const_int 0)))]
6086 cc_status = cc_prev_status;
6089 [(set_attr "type" "scc")])
6091 (define_insn "*sordered_1"
6092 [(set (match_operand:QI 0 "register_operand" "=d")
6093 (ordered:QI (cc0) (const_int 0)))]
6094 "TARGET_68881 && !TUNE_68060"
6096 cc_status = cc_prev_status;
6100 (define_insn "*sunordered_1"
6101 [(set (match_operand:QI 0 "register_operand" "=d")
6102 (unordered:QI (cc0) (const_int 0)))]
6103 "TARGET_68881 && !TUNE_68060"
6105 cc_status = cc_prev_status;
6109 (define_insn "*suneq_1"
6110 [(set (match_operand:QI 0 "register_operand" "=d")
6111 (uneq:QI (cc0) (const_int 0)))]
6112 "TARGET_68881 && !TUNE_68060"
6114 cc_status = cc_prev_status;
6118 (define_insn "*sunge_1"
6119 [(set (match_operand:QI 0 "register_operand" "=d")
6120 (unge:QI (cc0) (const_int 0)))]
6121 "TARGET_68881 && !TUNE_68060"
6123 cc_status = cc_prev_status;
6127 (define_insn "*sungt_1"
6128 [(set (match_operand:QI 0 "register_operand" "=d")
6129 (ungt:QI (cc0) (const_int 0)))]
6130 "TARGET_68881 && !TUNE_68060"
6132 cc_status = cc_prev_status;
6136 (define_insn "*sunle_1"
6137 [(set (match_operand:QI 0 "register_operand" "=d")
6138 (unle:QI (cc0) (const_int 0)))]
6139 "TARGET_68881 && !TUNE_68060"
6141 cc_status = cc_prev_status;
6145 (define_insn "*sunlt_1"
6146 [(set (match_operand:QI 0 "register_operand" "=d")
6147 (unlt:QI (cc0) (const_int 0)))]
6148 "TARGET_68881 && !TUNE_68060"
6150 cc_status = cc_prev_status;
6154 (define_insn "*sltgt_1"
6155 [(set (match_operand:QI 0 "register_operand" "=d")
6156 (ltgt:QI (cc0) (const_int 0)))]
6157 "TARGET_68881 && !TUNE_68060"
6159 cc_status = cc_prev_status;
6163 (define_insn "*fsogt_1"
6164 [(set (match_operand:QI 0 "register_operand" "=d")
6165 (not:QI (unle:QI (cc0) (const_int 0))))]
6166 "TARGET_68881 && !TUNE_68060"
6168 cc_status = cc_prev_status;
6172 (define_insn "*fsoge_1"
6173 [(set (match_operand:QI 0 "register_operand" "=d")
6174 (not:QI (unlt:QI (cc0) (const_int 0))))]
6175 "TARGET_68881 && !TUNE_68060"
6177 cc_status = cc_prev_status;
6181 (define_insn "*fsolt_1"
6182 [(set (match_operand:QI 0 "register_operand" "=d")
6183 (not:QI (unge:QI (cc0) (const_int 0))))]
6184 "TARGET_68881 && !TUNE_68060"
6186 cc_status = cc_prev_status;
6190 (define_insn "*fsole_1"
6191 [(set (match_operand:QI 0 "register_operand" "=d")
6192 (not:QI (ungt:QI (cc0) (const_int 0))))]
6193 "TARGET_68881 && !TUNE_68060"
6195 cc_status = cc_prev_status;
6199 ;; Basic conditional jump instructions.
6201 (define_insn "beq0_di"
6203 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
6205 (label_ref (match_operand 1 "" ","))
6207 (clobber (match_scratch:SI 2 "=d,d"))]
6211 if (which_alternative == 1)
6212 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1";
6213 if ((cc_prev_status.value1
6214 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6215 || (cc_prev_status.value2
6216 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6218 cc_status = cc_prev_status;
6221 if (GET_CODE (operands[0]) == REG)
6222 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6224 operands[3] = adjust_address (operands[0], SImode, 4);
6225 if (! ADDRESS_REG_P (operands[0]))
6227 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6229 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6230 return "or%.l %0,%2\;jeq %l1";
6232 return "or%.l %3,%2\;jeq %l1";
6234 return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1";
6236 operands[4] = gen_label_rtx();
6237 if (TARGET_68020 || TARGET_COLDFIRE)
6238 output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands);
6240 output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands);
6241 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6242 CODE_LABEL_NUMBER (operands[4]));
6246 (define_insn "bne0_di"
6248 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
6250 (label_ref (match_operand 1 "" ","))
6252 (clobber (match_scratch:SI 2 "=d,X"))]
6255 if ((cc_prev_status.value1
6256 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6257 || (cc_prev_status.value2
6258 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6260 cc_status = cc_prev_status;
6264 if (GET_CODE (operands[0]) == REG)
6265 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6267 operands[3] = adjust_address (operands[0], SImode, 4);
6268 if (!ADDRESS_REG_P (operands[0]))
6270 if (reg_overlap_mentioned_p (operands[2], operands[0]))
6272 if (reg_overlap_mentioned_p (operands[2], operands[3]))
6273 return "or%.l %0,%2\;jne %l1";
6275 return "or%.l %3,%2\;jne %l1";
6277 return "move%.l %0,%2\;or%.l %3,%2\;jne %l1";
6279 if (TARGET_68020 || TARGET_COLDFIRE)
6280 return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1";
6282 return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1";
6285 (define_insn "bge0_di"
6287 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6289 (label_ref (match_operand 1 "" ""))
6293 if ((cc_prev_status.value1
6294 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6295 || (cc_prev_status.value2
6296 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6298 cc_status = cc_prev_status;
6299 return cc_status.flags & CC_REVERSED ? "jle %l1" : "jpl %l1";
6302 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
6303 output_asm_insn("tst%.l %0", operands);
6306 /* On an address reg, cmpw may replace cmpl. */
6307 output_asm_insn("cmp%.w #0,%0", operands);
6312 (define_insn "blt0_di"
6314 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6316 (label_ref (match_operand 1 "" ""))
6320 if ((cc_prev_status.value1
6321 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6322 || (cc_prev_status.value2
6323 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6325 cc_status = cc_prev_status;
6326 return cc_status.flags & CC_REVERSED ? "jgt %l1" : "jmi %l1";
6329 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0]))
6330 output_asm_insn("tst%.l %0", operands);
6333 /* On an address reg, cmpw may replace cmpl. */
6334 output_asm_insn("cmp%.w #0,%0", operands);
6341 (if_then_else (eq (cc0)
6343 (label_ref (match_operand 0 "" ""))
6347 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6349 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
6353 (if_then_else (ne (cc0)
6355 (label_ref (match_operand 0 "" ""))
6359 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6361 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
6365 (if_then_else (gt (cc0)
6367 (label_ref (match_operand 0 "" ""))
6371 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6373 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6377 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0);
6379 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
6383 (if_then_else (gtu (cc0)
6385 (label_ref (match_operand 0 "" ""))
6389 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6391 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6397 [(set_attr "type" "bcc")])
6401 (if_then_else (lt (cc0)
6403 (label_ref (match_operand 0 "" ""))
6407 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6409 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6413 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0");
6415 [(set (attr "type") (symbol_ref "m68k_sched_branch_type (insn)"))])
6419 (if_then_else (ltu (cc0)
6421 (label_ref (match_operand 0 "" ""))
6425 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6427 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6433 [(set_attr "type" "bcc")])
6437 (if_then_else (ge (cc0)
6439 (label_ref (match_operand 0 "" ""))
6443 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6445 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6449 OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0");
6454 (if_then_else (geu (cc0)
6456 (label_ref (match_operand 0 "" ""))
6460 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6462 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6468 [(set_attr "type" "bcc")])
6472 (if_then_else (le (cc0)
6474 (label_ref (match_operand 0 "" ""))
6478 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6480 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6484 OUTPUT_JUMP ("jle %l0", "fjle %l0", 0);
6486 [(set_attr "type" "bcc")])
6490 (if_then_else (leu (cc0)
6492 (label_ref (match_operand 0 "" ""))
6496 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6498 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6504 [(set_attr "type" "bcc")])
6506 (define_insn "bordered"
6508 (if_then_else (ordered (cc0) (const_int 0))
6509 (label_ref (match_operand 0 "" ""))
6513 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6516 [(set_attr "type" "fbcc")])
6518 (define_insn "bunordered"
6520 (if_then_else (unordered (cc0) (const_int 0))
6521 (label_ref (match_operand 0 "" ""))
6525 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6528 [(set_attr "type" "fbcc")])
6530 (define_insn "buneq"
6532 (if_then_else (uneq (cc0) (const_int 0))
6533 (label_ref (match_operand 0 "" ""))
6537 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6540 [(set_attr "type" "fbcc")])
6542 (define_insn "bunge"
6544 (if_then_else (unge (cc0) (const_int 0))
6545 (label_ref (match_operand 0 "" ""))
6549 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6552 [(set_attr "type" "fbcc")])
6554 (define_insn "bungt"
6556 (if_then_else (ungt (cc0) (const_int 0))
6557 (label_ref (match_operand 0 "" ""))
6561 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6564 [(set_attr "type" "fbcc")])
6566 (define_insn "bunle"
6568 (if_then_else (unle (cc0) (const_int 0))
6569 (label_ref (match_operand 0 "" ""))
6573 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6576 [(set_attr "type" "fbcc")])
6578 (define_insn "bunlt"
6580 (if_then_else (unlt (cc0) (const_int 0))
6581 (label_ref (match_operand 0 "" ""))
6585 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6588 [(set_attr "type" "fbcc")])
6590 (define_insn "bltgt"
6592 (if_then_else (ltgt (cc0) (const_int 0))
6593 (label_ref (match_operand 0 "" ""))
6597 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6600 [(set_attr "type" "fbcc")])
6602 ;; Negated conditional jump instructions.
6604 (define_insn "*beq_rev"
6606 (if_then_else (eq (cc0)
6609 (label_ref (match_operand 0 "" ""))))]
6612 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0");
6614 [(set_attr "type" "bcc")])
6616 (define_insn "*bne_rev"
6618 (if_then_else (ne (cc0)
6621 (label_ref (match_operand 0 "" ""))))]
6624 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0");
6626 [(set_attr "type" "bcc")])
6628 (define_insn "*bgt_rev"
6630 (if_then_else (gt (cc0)
6633 (label_ref (match_operand 0 "" ""))))]
6636 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6638 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6642 OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0);
6644 [(set_attr "type" "bcc")])
6646 (define_insn "*bgtu_rev"
6648 (if_then_else (gtu (cc0)
6651 (label_ref (match_operand 0 "" ""))))]
6654 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6656 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6662 [(set_attr "type" "bcc")])
6664 (define_insn "*blt_rev"
6666 (if_then_else (lt (cc0)
6669 (label_ref (match_operand 0 "" ""))))]
6672 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6674 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6678 OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0");
6680 [(set_attr "type" "bcc")])
6682 (define_insn "*bltu_rev"
6684 (if_then_else (ltu (cc0)
6687 (label_ref (match_operand 0 "" ""))))]
6690 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6692 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6698 [(set_attr "type" "bcc")])
6700 (define_insn "*bge_rev"
6702 (if_then_else (ge (cc0)
6705 (label_ref (match_operand 0 "" ""))))]
6708 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6710 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6714 OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0");
6716 [(set_attr "type" "bcc")])
6718 (define_insn "*bgeu_rev"
6720 (if_then_else (geu (cc0)
6723 (label_ref (match_operand 0 "" ""))))]
6726 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6728 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6734 [(set_attr "type" "bcc")])
6736 (define_insn "*ble_rev"
6738 (if_then_else (le (cc0)
6741 (label_ref (match_operand 0 "" ""))))]
6744 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6746 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6750 OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0);
6752 [(set_attr "type" "bcc")])
6754 (define_insn "*bleu_rev"
6756 (if_then_else (leu (cc0)
6759 (label_ref (match_operand 0 "" ""))))]
6762 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
6764 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
6770 [(set_attr "type" "bcc")])
6772 (define_insn "*bordered_rev"
6774 (if_then_else (ordered (cc0) (const_int 0))
6776 (label_ref (match_operand 0 "" ""))))]
6779 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6782 [(set_attr "type" "fbcc")])
6784 (define_insn "*bunordered_rev"
6786 (if_then_else (unordered (cc0) (const_int 0))
6788 (label_ref (match_operand 0 "" ""))))]
6791 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6794 [(set_attr "type" "fbcc")])
6796 (define_insn "*buneq_rev"
6798 (if_then_else (uneq (cc0) (const_int 0))
6800 (label_ref (match_operand 0 "" ""))))]
6803 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6806 [(set_attr "type" "fbcc")])
6808 (define_insn "*bunge_rev"
6810 (if_then_else (unge (cc0) (const_int 0))
6812 (label_ref (match_operand 0 "" ""))))]
6815 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6818 [(set_attr "type" "fbcc")])
6820 (define_insn "*bungt_rev"
6822 (if_then_else (ungt (cc0) (const_int 0))
6824 (label_ref (match_operand 0 "" ""))))]
6827 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6830 [(set_attr "type" "fbcc")])
6832 (define_insn "*bunle_rev"
6834 (if_then_else (unle (cc0) (const_int 0))
6836 (label_ref (match_operand 0 "" ""))))]
6839 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6842 [(set_attr "type" "fbcc")])
6844 (define_insn "*bunlt_rev"
6846 (if_then_else (unlt (cc0) (const_int 0))
6848 (label_ref (match_operand 0 "" ""))))]
6851 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6854 [(set_attr "type" "fbcc")])
6856 (define_insn "*bltgt_rev"
6858 (if_then_else (ltgt (cc0) (const_int 0))
6860 (label_ref (match_operand 0 "" ""))))]
6863 gcc_assert (cc_prev_status.flags & CC_IN_68881);
6866 [(set_attr "type" "fbcc")])
6868 ;; Unconditional and other jump instructions
6871 (label_ref (match_operand 0 "" "")))]
6874 [(set_attr "type" "bra")])
6876 (define_expand "tablejump"
6877 [(parallel [(set (pc) (match_operand 0 "" ""))
6878 (use (label_ref (match_operand 1 "" "")))])]
6881 #ifdef CASE_VECTOR_PC_RELATIVE
6882 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6883 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6887 ;; Jump to variable address from dispatch table of absolute addresses.
6888 (define_insn "*tablejump_internal"
6889 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6890 (use (label_ref (match_operand 1 "" "")))]
6893 return MOTOROLA ? "jmp (%0)" : "jmp %0@";
6895 [(set_attr "type" "jmp")])
6897 ;; Jump to variable address from dispatch table of relative addresses.
6901 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6902 (use (label_ref (match_operand 1 "" "")))]
6905 #ifdef ASM_RETURN_CASE_JUMP
6906 ASM_RETURN_CASE_JUMP;
6908 if (TARGET_COLDFIRE)
6910 if (ADDRESS_REG_P (operands[0]))
6911 return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)";
6913 return "ext%.l %0\;jmp (2,pc,%0.l)";
6915 return "extl %0\;jmp pc@(2,%0:l)";
6918 return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)";
6922 ;; Decrement-and-branch insns.
6923 (define_insn "*dbne_hi"
6926 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g")
6928 (label_ref (match_operand 1 "" ""))
6931 (plus:HI (match_dup 0)
6936 if (DATA_REG_P (operands[0]))
6937 return "dbra %0,%l1";
6938 if (GET_CODE (operands[0]) == MEM)
6939 return "subq%.w #1,%0\;jcc %l1";
6940 return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
6943 (define_insn "*dbne_si"
6946 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g")
6948 (label_ref (match_operand 1 "" ""))
6951 (plus:SI (match_dup 0)
6956 if (DATA_REG_P (operands[0]))
6957 return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
6958 if (GET_CODE (operands[0]) == MEM)
6959 return "subq%.l #1,%0\;jcc %l1";
6960 return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
6963 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6965 (define_insn "*dbge_hi"
6968 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am")
6971 (label_ref (match_operand 1 "" ""))
6974 (plus:HI (match_dup 0)
6976 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
6979 if (DATA_REG_P (operands[0]))
6980 return "dbra %0,%l1";
6981 if (GET_CODE (operands[0]) == MEM)
6982 return "subq%.w #1,%0\;jcc %l1";
6983 return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
6986 (define_expand "decrement_and_branch_until_zero"
6987 [(parallel [(set (pc)
6989 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "")
6992 (label_ref (match_operand 1 "" ""))
6995 (plus:SI (match_dup 0)
7000 (define_insn "*dbge_si"
7003 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am")
7006 (label_ref (match_operand 1 "" ""))
7009 (plus:SI (match_dup 0)
7011 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)"
7014 if (DATA_REG_P (operands[0]))
7015 return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
7016 if (GET_CODE (operands[0]) == MEM)
7017 return "subq%.l #1,%0\;jcc %l1";
7018 return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
7021 (define_expand "sibcall"
7022 [(call (match_operand:QI 0 "memory_operand" "")
7023 (match_operand:SI 1 "general_operand" ""))]
7026 operands[0] = m68k_legitimize_sibcall_address (operands[0]);
7029 (define_insn "*sibcall"
7030 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" ""))
7031 (match_operand:SI 1 "general_operand" ""))]
7032 "SIBLING_CALL_P (insn)"
7034 return output_sibcall (operands[0]);
7037 (define_expand "sibcall_value"
7038 [(set (match_operand 0 "" "")
7039 (call (match_operand:QI 1 "memory_operand" "")
7040 (match_operand:SI 2 "general_operand" "")))]
7043 operands[1] = m68k_legitimize_sibcall_address (operands[1]);
7046 (define_insn "*sibcall_value"
7047 [(set (match_operand 0 "" "=rf,rf")
7048 (call (mem:QI (match_operand:SI 1 "sibcall_operand" ""))
7049 (match_operand:SI 2 "general_operand" "")))]
7050 "SIBLING_CALL_P (insn)"
7052 operands[0] = operands[1];
7053 return output_sibcall (operands[0]);
7056 ;; Call subroutine with no return value.
7057 (define_expand "call"
7058 [(call (match_operand:QI 0 "memory_operand" "")
7059 (match_operand:SI 1 "general_operand" ""))]
7060 ;; Operand 1 not really used on the m68000.
7063 operands[0] = m68k_legitimize_call_address (operands[0]);
7066 (define_insn "*call"
7067 [(call (mem:QI (match_operand:SI 0 "call_operand" "a,W"))
7068 (match_operand:SI 1 "general_operand" "g,g"))]
7069 ;; Operand 1 not really used on the m68000.
7070 "!SIBLING_CALL_P (insn)"
7072 return output_call (operands[0]);
7074 [(set_attr "type" "jsr")])
7076 ;; Call subroutine, returning value in operand 0
7077 ;; (which must be a hard register).
7078 (define_expand "call_value"
7079 [(set (match_operand 0 "" "")
7080 (call (match_operand:QI 1 "memory_operand" "")
7081 (match_operand:SI 2 "general_operand" "")))]
7082 ;; Operand 2 not really used on the m68000.
7085 operands[1] = m68k_legitimize_call_address (operands[1]);
7088 (define_insn "*non_symbolic_call_value"
7089 [(set (match_operand 0 "" "=rf,rf")
7090 (call (mem:QI (match_operand:SI 1 "non_symbolic_call_operand" "a,W"))
7091 (match_operand:SI 2 "general_operand" "g,g")))]
7092 ;; Operand 2 not really used on the m68000.
7093 "!SIBLING_CALL_P (insn)"
7095 [(set_attr "type" "jsr")
7096 (set_attr "opx" "1")])
7098 (define_insn "*symbolic_call_value_jsr"
7099 [(set (match_operand 0 "" "=rf,rf")
7100 (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W"))
7101 (match_operand:SI 2 "general_operand" "g,g")))]
7102 ;; Operand 2 not really used on the m68000.
7103 "!SIBLING_CALL_P (insn) && m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_JSR"
7105 operands[0] = operands[1];
7106 return m68k_symbolic_call;
7108 [(set_attr "type" "jsr")
7109 (set_attr "opx" "1")])
7111 (define_insn "*symbolic_call_value_bsr"
7112 [(set (match_operand 0 "" "=rf,rf")
7113 (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W"))
7114 (match_operand:SI 2 "general_operand" "g,g")))]
7115 ;; Operand 2 not really used on the m68000.
7116 "!SIBLING_CALL_P (insn)
7117 && (m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_C
7118 || m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_P)"
7120 operands[0] = operands[1];
7121 return m68k_symbolic_call;
7123 [(set_attr "type" "bsr")
7124 (set_attr "opx" "1")])
7126 ;; Call subroutine returning any type.
7128 (define_expand "untyped_call"
7129 [(parallel [(call (match_operand 0 "" "")
7131 (match_operand 1 "" "")
7132 (match_operand 2 "" "")])]
7133 "NEEDS_UNTYPED_CALL"
7137 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7139 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7141 rtx set = XVECEXP (operands[2], 0, i);
7142 emit_move_insn (SET_DEST (set), SET_SRC (set));
7145 /* The optimizer does not know that the call sets the function value
7146 registers we stored in the result block. We avoid problems by
7147 claiming that all hard registers are used and clobbered at this
7149 emit_insn (gen_blockage ());
7154 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7155 ;; all of memory. This blocks insns from being moved across this point.
7157 (define_insn "blockage"
7158 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7166 [(set_attr "type" "nop")])
7168 (define_expand "prologue"
7172 m68k_expand_prologue ();
7176 (define_expand "epilogue"
7180 m68k_expand_epilogue (false);
7184 (define_expand "sibcall_epilogue"
7188 m68k_expand_epilogue (true);
7192 ;; Used for frameless functions which save no regs and allocate no locals.
7193 (define_expand "return"
7195 "m68k_use_return_insn ()"
7198 (define_insn "*return"
7202 switch (m68k_get_function_kind (current_function_decl))
7204 case m68k_fk_interrupt_handler:
7207 case m68k_fk_interrupt_thread:
7211 if (crtl->args.pops_args)
7213 operands[0] = GEN_INT (crtl->args.pops_args);
7220 [(set_attr "type" "rts")])
7222 (define_insn "*m68k_store_multiple"
7223 [(match_parallel 0 "" [(match_operand 1 "")])]
7224 "m68k_movem_pattern_p (operands[0], NULL, 0, true)"
7226 return m68k_output_movem (operands, operands[0], 0, true);
7229 (define_insn "*m68k_store_multiple_automod"
7230 [(match_parallel 0 ""
7231 [(set (match_operand:SI 1 "register_operand" "=a")
7232 (plus:SI (match_operand:SI 2 "register_operand" "1")
7233 (match_operand:SI 3 "const_int_operand")))])]
7234 "m68k_movem_pattern_p (operands[0], operands[1], INTVAL (operands[3]), true)"
7236 return m68k_output_movem (operands, operands[0], INTVAL (operands[3]), true);
7239 (define_insn "*m68k_load_multiple"
7240 [(match_parallel 0 "" [(match_operand 1 "")])]
7241 "m68k_movem_pattern_p (operands[0], NULL, 0, false)"
7243 return m68k_output_movem (operands, operands[0], 0, false);
7246 (define_insn "*m68k_load_multiple_automod"
7247 [(match_parallel 0 ""
7248 [(set (match_operand:SI 1 "register_operand" "=a")
7249 (plus:SI (match_operand:SI 2 "register_operand" "1")
7250 (match_operand:SI 3 "const_int_operand")))])]
7251 "m68k_movem_pattern_p (operands[0], operands[1],
7252 INTVAL (operands[3]), false)"
7254 return m68k_output_movem (operands, operands[0],
7255 INTVAL (operands[3]), false);
7258 (define_expand "link"
7260 [(set (match_operand:SI 0 "register_operand")
7261 (plus:SI (reg:SI SP_REG) (const_int -4)))
7264 (set (reg:SI SP_REG)
7265 (plus:SI (reg:SI SP_REG)
7266 (match_operand:SI 1 "const_int_operand")))])]
7267 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
7269 operands[2] = gen_frame_mem (SImode,
7270 plus_constant (Pmode, stack_pointer_rtx, -4));
7273 (define_insn "*link"
7274 [(set (match_operand:SI 0 "register_operand" "+r")
7275 (plus:SI (reg:SI SP_REG) (const_int -4)))
7276 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4)))
7278 (set (reg:SI SP_REG)
7279 (plus:SI (reg:SI SP_REG)
7280 (match_operand:SI 1 "const_int_operand")))]
7281 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004"
7283 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
7285 return "link %0,%1";
7286 else if (INTVAL (operands[1]) >= -0x8000)
7287 return "link.w %0,%1";
7289 return "link.l %0,%1";
7291 [(set_attr "type" "link")])
7293 (define_expand "unlink"
7295 [(set (match_operand:SI 0 "register_operand")
7297 (set (reg:SI SP_REG)
7298 (plus:SI (match_dup 0)
7302 operands[1] = gen_frame_mem (SImode, copy_rtx (operands[0]));
7305 (define_insn "*unlink"
7306 [(set (match_operand:SI 0 "register_operand" "+r")
7307 (mem:SI (match_dup 0)))
7308 (set (reg:SI SP_REG)
7309 (plus:SI (match_dup 0)
7313 [(set_attr "type" "unlk")])
7315 (define_insn "load_got"
7316 [(set (match_operand:SI 0 "register_operand" "=a")
7317 (unspec:SI [(const_int 0)] UNSPEC_GOT))]
7320 if (TARGET_ID_SHARED_LIBRARY)
7322 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
7323 return MOTOROLA ? "move.l %?(%1),%0" : "movel %1@(%?), %0";
7327 if (TARGET_COLDFIRE)
7328 /* Load the full 32-bit PC-relative offset of
7329 _GLOBAL_OFFSET_TABLE_ into the PIC register, then use it to
7330 calculate the absolute value. The offset and "lea"
7331 operation word together occupy 6 bytes. */
7332 return ("move.l #_GLOBAL_OFFSET_TABLE_@GOTPC, %0\n\t"
7333 "lea (-6, %%pc, %0), %0");
7335 return "lea (%%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %0";
7338 return ("movel #_GLOBAL_OFFSET_TABLE_, %0\n\t"
7339 "lea %%pc@(0,%0:l),%0");
7342 (define_insn "indirect_jump"
7343 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
7346 [(set_attr "type" "jmp")])
7348 ;; This should not be used unless the add/sub insns can't be.
7351 [(set (match_operand:SI 0 "nonimmediate_operand" "=a")
7352 (match_operand:QI 1 "address_operand" "p"))]
7356 ;; This is the first machine-dependent peephole optimization.
7357 ;; It is useful when a floating value is returned from a function call
7358 ;; and then is moved into an FP register.
7359 ;; But it is mainly intended to test the support for these optimizations.
7362 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7363 (set (match_operand:DF 0 "register_operand" "")
7364 (match_operand:DF 1 "register_operand" ""))]
7365 "FP_REG_P (operands[0]) && !FP_REG_P (operands[1])"
7366 [(set (mem:SI (reg:SI SP_REG)) (match_dup 1))
7367 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 2))
7368 (set (match_dup 0) (mem:DF (post_inc:SI (reg:SI SP_REG))))]
7369 "split_di(operands + 1, 1, operands + 1, operands + 2);")
7371 ;; Optimize a stack-adjust followed by a push of an argument.
7372 ;; This is said to happen frequently with -msoft-float
7373 ;; when there are consecutive library calls.
7376 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7377 (set (match_operand:SF 0 "push_operand" "")
7378 (match_operand:SF 1 "general_operand" ""))]
7379 "!reg_mentioned_p (stack_pointer_rtx, operands[0])"
7380 [(set (match_dup 0) (match_dup 1))]
7381 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7384 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7385 (match_operand:SI 0 "const_int_operand" "")))
7386 (set (match_operand:SF 1 "push_operand" "")
7387 (match_operand:SF 2 "general_operand" ""))]
7388 "INTVAL (operands[0]) > 4
7389 && !reg_mentioned_p (stack_pointer_rtx, operands[2])"
7390 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0)))
7391 (set (match_dup 1) (match_dup 2))]
7393 operands[0] = GEN_INT (INTVAL (operands[0]) - 4);
7394 operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
7397 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7398 ;; Constant operands need special care, as replacing a "pea X.w" with
7399 ;; "move.l #X,(%sp)" is often not a win.
7401 ;; Already done by the previous csa pass, left as reference.
7403 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4)))
7404 (set (match_operand:SI 0 "push_operand" "")
7405 (match_operand:SI 1 "general_operand" ""))]
7406 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7407 [(set (match_dup 0) (match_dup 1))]
7408 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7410 ;; Try to use moveq, after stack push has been changed into a simple move.
7412 [(match_scratch:SI 2 "d")
7413 (set (match_operand:SI 0 "memory_operand" "")
7414 (match_operand:SI 1 "const_int_operand" ""))]
7415 "GET_CODE (XEXP (operands[0], 0)) != PRE_DEC
7416 && INTVAL (operands[1]) != 0
7417 && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f)
7418 && !valid_mov3q_const (INTVAL (operands[1]))"
7419 [(set (match_dup 2) (match_dup 1))
7420 (set (match_dup 0) (match_dup 2))])
7422 ;; This sequence adds an instruction, but is two bytes shorter.
7424 [(match_scratch:SI 2 "d")
7425 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 12)))
7426 (set (match_operand:SI 0 "push_operand" "")
7427 (match_operand:SI 1 "const_int_operand" ""))]
7428 "INTVAL (operands[1]) != 0
7429 && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f)
7430 && !valid_mov3q_const (INTVAL (operands[1]))"
7431 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8)))
7432 (set (match_dup 2) (match_dup 1))
7433 (set (match_dup 0) (match_dup 2))]
7434 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);")
7436 ;; Changing pea X.w into a move.l is no real win here.
7438 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG)
7439 (match_operand:SI 0 "const_int_operand" "")))
7440 (set (match_operand:SI 1 "push_operand" "")
7441 (match_operand:SI 2 "general_operand" ""))]
7442 "INTVAL (operands[0]) > 4
7443 && !reg_mentioned_p (stack_pointer_rtx, operands[2])
7444 && !(CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0
7445 && IN_RANGE (INTVAL (operands[2]), -0x8000, 0x7fff)
7446 && !valid_mov3q_const (INTVAL (operands[2])))"
7447 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0)))
7448 (set (match_dup 1) (match_dup 2))]
7450 operands[0] = GEN_INT (INTVAL (operands[0]) - 4);
7451 operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx);
7454 ;; Speed up pushing a single byte/two bytes but leaving four bytes of space
7455 ;; (which differs slightly between m680x0 and ColdFire).
7458 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4)))
7459 (set (match_operand:QI 0 "memory_operand" "")
7460 (match_operand:QI 1 "register_operand" ""))]
7461 "!reg_mentioned_p (stack_pointer_rtx, operands[1])
7462 && GET_CODE (XEXP (operands[0], 0)) == PLUS
7463 && rtx_equal_p (XEXP (XEXP (operands[0], 0), 0), stack_pointer_rtx)
7464 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
7465 && INTVAL (XEXP (XEXP (operands[0], 0), 1)) == 3"
7466 [(set (match_dup 0) (match_dup 1))]
7468 rtx addr = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx);
7469 operands[0] = adjust_automodify_address (operands[0], SImode, addr, -3);
7470 operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
7474 [(set (match_operand:QI 0 "push_operand" "")
7475 (match_operand:QI 1 "register_operand" ""))
7476 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -3)))]
7477 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7478 [(set (match_dup 0) (match_dup 1))]
7480 operands[0] = adjust_automodify_address (operands[0], SImode,
7481 XEXP (operands[0], 0), -3);
7482 operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0);
7486 [(set (match_operand:HI 0 "push_operand" "")
7487 (match_operand:HI 1 "register_operand" ""))
7488 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))]
7489 "!reg_mentioned_p (stack_pointer_rtx, operands[1])"
7490 [(set (match_dup 0) (match_dup 1))]
7492 operands[0] = adjust_automodify_address (operands[0], SImode,
7493 XEXP (operands[0], 0), -2);
7494 operands[1] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
7497 ;; Optimize a series of strict_low_part assignments
7500 [(set (match_operand:SI 0 "register_operand" "")
7502 (set (strict_low_part (match_operand:HI 1 "register_operand" ""))
7503 (match_operand:HI 2 "general_operand" ""))]
7504 "REGNO (operands[0]) == REGNO (operands[1])
7505 && strict_low_part_peephole_ok (HImode, insn, operands[0])"
7506 [(set (strict_low_part (match_dup 1)) (match_dup 2))]
7510 [(set (match_operand:SI 0 "register_operand" "")
7512 (set (strict_low_part (match_operand:QI 1 "register_operand" ""))
7513 (match_operand:QI 2 "general_operand" ""))]
7514 "REGNO (operands[0]) == REGNO (operands[1])
7515 && strict_low_part_peephole_ok (QImode, insn, operands[0])"
7516 [(set (strict_low_part (match_dup 1)) (match_dup 2))]
7524 ;; jCC label ; abnormal loop termination
7525 ;; dbra dN, loop ; normal loop termination
7533 ;; Which moves the jCC condition outside the inner loop for free.
7537 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7538 [(cc0) (const_int 0)])
7539 (label_ref (match_operand 2 "" ""))
7544 (ne (match_operand:HI 0 "register_operand" "")
7546 (label_ref (match_operand 1 "" ""))
7549 (plus:HI (match_dup 0)
7551 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7554 output_dbcc_and_branch (operands);
7559 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7560 [(cc0) (const_int 0)])
7561 (label_ref (match_operand 2 "" ""))
7566 (ne (match_operand:SI 0 "register_operand" "")
7568 (label_ref (match_operand 1 "" ""))
7571 (plus:SI (match_dup 0)
7573 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7576 output_dbcc_and_branch (operands);
7581 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7582 [(cc0) (const_int 0)])
7583 (label_ref (match_operand 2 "" ""))
7588 (ge (plus:HI (match_operand:HI 0 "register_operand" "")
7591 (label_ref (match_operand 1 "" ""))
7594 (plus:HI (match_dup 0)
7596 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7599 output_dbcc_and_branch (operands);
7604 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7605 [(cc0) (const_int 0)])
7606 (label_ref (match_operand 2 "" ""))
7611 (ge (plus:SI (match_operand:SI 0 "register_operand" "")
7614 (label_ref (match_operand 1 "" ""))
7617 (plus:SI (match_dup 0)
7619 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7622 output_dbcc_and_branch (operands);
7627 (define_insn "extendsfxf2"
7628 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7629 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))]
7632 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7634 if (REGNO (operands[0]) == REGNO (operands[1]))
7636 /* Extending float to double in an fp-reg is a no-op.
7637 NOTICE_UPDATE_CC has already assumed that the
7638 cc will be set. So cancel what it did. */
7639 cc_status = cc_prev_status;
7642 return "f%$move%.x %1,%0";
7644 if (FP_REG_P (operands[0]))
7646 if (FP_REG_P (operands[1]))
7647 return "f%$move%.x %1,%0";
7648 else if (ADDRESS_REG_P (operands[1]))
7649 return "move%.l %1,%-\;f%$move%.s %+,%0";
7650 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
7651 return output_move_const_single (operands);
7652 return "f%$move%.s %f1,%0";
7654 return "fmove%.x %f1,%0";
7658 (define_insn "extenddfxf2"
7659 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f")
7661 (match_operand:DF 1 "general_operand" "f,rmE")))]
7664 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7666 if (REGNO (operands[0]) == REGNO (operands[1]))
7668 /* Extending float to double in an fp-reg is a no-op.
7669 NOTICE_UPDATE_CC has already assumed that the
7670 cc will be set. So cancel what it did. */
7671 cc_status = cc_prev_status;
7674 return "fmove%.x %1,%0";
7676 if (FP_REG_P (operands[0]))
7678 if (REG_P (operands[1]))
7681 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7682 output_asm_insn ("move%.l %1,%-", xoperands);
7683 output_asm_insn ("move%.l %1,%-", operands);
7684 return "f%&move%.d %+,%0";
7686 if (GET_CODE (operands[1]) == CONST_DOUBLE)
7687 return output_move_const_double (operands);
7688 return "f%&move%.d %f1,%0";
7690 return "fmove%.x %f1,%0";
7693 (define_insn "truncxfdf2"
7694 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r")
7696 (match_operand:XF 1 "general_operand" "f,f")))]
7699 if (REG_P (operands[0]))
7701 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands);
7702 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7703 return "move%.l %+,%0";
7705 return "fmove%.d %f1,%0";
7708 (define_insn "truncxfsf2"
7709 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm")
7711 (match_operand:XF 1 "general_operand" "f")))]
7715 (define_insn "sin<mode>2"
7716 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
7718 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_SIN))]
7719 "TARGET_68881 && flag_unsafe_math_optimizations"
7721 if (FP_REG_P (operands[1]))
7722 return "fsin%.x %1,%0";
7724 return "fsin%.<FP:prec> %1,%0";
7727 (define_insn "cos<mode>2"
7728 [(set (match_operand:FP 0 "nonimmediate_operand" "=f")
7730 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_COS))]
7731 "TARGET_68881 && flag_unsafe_math_optimizations"
7733 if (FP_REG_P (operands[1]))
7734 return "fcos%.x %1,%0";
7736 return "fcos%.<FP:prec> %1,%0";
7739 ;; Unconditional traps are assumed to have (const_int 1) for the condition.
7741 [(trap_if (const_int 1) (const_int 7))]
7744 [(set_attr "type" "trap")])
7746 (define_expand "ctrapdi4"
7747 [(trap_if (match_operator 0 "ordered_comparison_operator"
7748 [(cc0) (const_int 0)])
7749 (match_operand:SI 3 "const1_operand" ""))]
7752 if (operands[2] == const0_rtx)
7753 emit_insn (gen_tstdi (operands[1]));
7755 emit_insn (gen_cmpdi (operands[1], operands[2]));
7756 operands[1] = cc0_rtx;
7757 operands[2] = const0_rtx;
7760 (define_expand "ctrapsi4"
7762 (compare (match_operand:SI 1 "nonimmediate_operand" "")
7763 (match_operand:SI 2 "general_operand" "")))
7764 (trap_if (match_operator 0 "ordered_comparison_operator"
7765 [(cc0) (const_int 0)])
7766 (match_operand:SI 3 "const1_operand" ""))]
7770 (define_expand "ctraphi4"
7772 (compare (match_operand:HI 1 "nonimmediate_src_operand" "")
7773 (match_operand:HI 2 "general_src_operand" "")))
7774 (trap_if (match_operator 0 "ordered_comparison_operator"
7775 [(cc0) (const_int 0)])
7776 (match_operand:SI 3 "const1_operand" ""))]
7780 (define_expand "ctrapqi4"
7782 (compare (match_operand:QI 1 "nonimmediate_src_operand" "")
7783 (match_operand:QI 2 "general_src_operand" "")))
7784 (trap_if (match_operator 0 "ordered_comparison_operator"
7785 [(cc0) (const_int 0)])
7786 (match_operand:SI 3 "const1_operand" ""))]
7790 (define_insn "*conditional_trap"
7791 [(trap_if (match_operator 0 "ordered_comparison_operator"
7792 [(cc0) (const_int 0)])
7793 (match_operand:SI 1 "const1_operand" "I"))]
7794 "TARGET_68020 && ! flags_in_68881 ()"
7796 switch (GET_CODE (operands[0]))
7798 case EQ: return "trapeq";
7799 case NE: return "trapne";
7800 case GT: return "trapgt";
7801 case GTU: return "traphi";
7802 case LT: return "traplt";
7803 case LTU: return "trapcs";
7804 case GE: return "trapge";
7805 case GEU: return "trapcc";
7806 case LE: return "traple";
7807 case LEU: return "trapls";
7808 default: gcc_unreachable ();
7812 ;; These are to prevent the scheduler from moving stores to the frame
7813 ;; before the stack adjustment.
7814 (define_insn "stack_tie"
7815 [(set (mem:BLK (scratch))
7816 (unspec:BLK [(match_operand:SI 0 "register_operand" "r")
7817 (match_operand:SI 1 "register_operand" "r")]
7821 [(set_attr "type" "ignore")])
7823 ;; Instruction that subscribes one word in ColdFire instruction buffer.
7824 ;; This instruction is used within scheduler only and should not appear
7825 ;; in the instruction stream.
7827 [(unspec [(const_int 0)] UNSPEC_IB)]
7830 [(set_attr "type" "ib")])