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[thirdparty/gcc.git] / gcc / config / microblaze / microblaze.h
1 /* Definitions of target machine for GNU compiler for Xilinx MicroBlaze.
2 Copyright (C) 2009-2017 Free Software Foundation, Inc.
3
4 Contributed by Michael Eager <eager@eagercon.com>.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* Standard GCC variables that we reference. */
23
24 /* MicroBlaze external variables defined in microblaze.c. */
25
26 /* Which pipeline to schedule for. */
27 enum pipeline_type
28 {
29 MICROBLAZE_PIPE_3 = 0,
30 MICROBLAZE_PIPE_5 = 1
31 };
32
33 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
34
35 /* print_operand punctuation chars */
36 extern char microblaze_print_operand_punct[];
37
38 /* # bytes of data/sdata cutoff */
39 extern int microblaze_section_threshold;
40
41 /* Map register # to debug register # */
42 extern int microblaze_dbx_regno[];
43
44 extern int microblaze_no_unsafe_delay;
45 extern int microblaze_has_clz;
46 extern enum pipeline_type microblaze_pipe;
47
48 #define OBJECT_FORMAT_ELF
49
50 #if TARGET_BIG_ENDIAN_DEFAULT
51 #define TARGET_ENDIAN_DEFAULT 0
52 #define TARGET_ENDIAN_OPTION "mbig-endian"
53 #else
54 #define TARGET_ENDIAN_DEFAULT MASK_LITTLE_ENDIAN
55 #define TARGET_ENDIAN_OPTION "mlittle-endian"
56 #endif
57
58 /* Default target_flags if no switches are specified */
59 #define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT \
60 | TARGET_ENDIAN_DEFAULT)
61
62 /* Do we have CLZ? */
63 #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
64
65 /* The default is to support PIC. */
66 #define TARGET_SUPPORTS_PIC 1
67
68 /* The default is to not need GOT for TLS. */
69 #define TLS_NEEDS_GOT 0
70
71 /* What is the default setting for -mcpu= . We set it to v4.00.a even though
72 we are actually ahead. This is safest version that has generate code
73 compatible for the original ISA */
74 #define MICROBLAZE_DEFAULT_CPU "v4.00.a"
75
76 /* Macros to decide whether certain features are available or not,
77 depending on the instruction set architecture level. */
78
79 #define DRIVER_SELF_SPECS \
80 "%{mxl-soft-mul:%<mno-xl-soft-mul}", \
81 "%{mno-xl-barrel-shift:%<mxl-barrel-shift}", \
82 "%{mno-xl-pattern-compare:%<mxl-pattern-compare}", \
83 "%{mxl-soft-div:%<mno-xl-soft-div}", \
84 "%{mxl-reorder:%<mno-xl-reorder}", \
85 "%{msoft-float:%<mhard-float}"
86
87 /* Tell collect what flags to pass to nm. */
88 #ifndef NM_FLAGS
89 #define NM_FLAGS "-Bn"
90 #endif
91
92 /* Names to predefine in the preprocessor for this target machine. */
93 #define TARGET_CPU_CPP_BUILTINS() microblaze_cpp_define (pfile)
94
95 /* Assembler specs. */
96
97 #define TARGET_ASM_SPEC ""
98
99 #define ASM_SPEC "\
100 %(target_asm_spec) \
101 %{mbig-endian:-EB} \
102 %{mlittle-endian:-EL}"
103
104 /* Extra switches sometimes passed to the linker. */
105 /* -xl-mode-xmdstub translated to -Zxl-mode-xmdstub -- deprecated. */
106
107 #define LINK_SPEC "%{shared:-shared} -N -relax \
108 %{mbig-endian:-EB --oformat=elf32-microblaze} \
109 %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
110 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
111 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
112 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
113 %{!T*: -dT xilinx.ld%s}"
114
115 /* Specs for the compiler proper */
116
117 #ifndef CC1_SPEC
118 #define CC1_SPEC " \
119 %{G*} \
120 %(subtarget_cc1_spec) \
121 %{mxl-multiply-high:-mcpu=v6.00.a} \
122 "
123 #endif
124
125 #define EXTRA_SPECS \
126 { "target_asm_spec", TARGET_ASM_SPEC }, \
127 SUBTARGET_EXTRA_SPECS
128
129 /* Local compiler-generated symbols must have a prefix that the assembler
130 understands. */
131
132 #ifndef LOCAL_LABEL_PREFIX
133 #define LOCAL_LABEL_PREFIX "$"
134 #endif
135
136 /* fixed registers. */
137 #define MB_ABI_BASE_REGNUM 0
138 #define MB_ABI_STACK_POINTER_REGNUM 1
139 #define MB_ABI_GPRO_REGNUM 2
140 #define MB_ABI_GPRW_REGNUM 13
141 #define MB_ABI_INTR_RETURN_ADDR_REGNUM 14
142 #define MB_ABI_SUB_RETURN_ADDR_REGNUM 15
143 #define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16
144 #define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17
145 #define MB_ABI_ASM_TEMP_REGNUM 18
146 /* This is our temp register. */
147 #define MB_ABI_FRAME_POINTER_REGNUM 19
148 #define MB_ABI_PIC_ADDR_REGNUM 20
149 #define MB_ABI_PIC_FUNC_REGNUM 21
150 /* Volatile registers. */
151 #define MB_ABI_INT_RETURN_VAL_REGNUM 3
152 #define MB_ABI_INT_RETURN_VAL2_REGNUM 4
153 #define MB_ABI_FIRST_ARG_REGNUM 5
154 #define MB_ABI_LAST_ARG_REGNUM 10
155 #define MB_ABI_MAX_ARG_REGS (MB_ABI_LAST_ARG_REGNUM \
156 - MB_ABI_FIRST_ARG_REGNUM + 1)
157 #define MB_ABI_STATIC_CHAIN_REGNUM 3
158 #define MB_ABI_TEMP1_REGNUM 11
159 #define MB_ABI_TEMP2_REGNUM 12
160 #define MB_ABI_MSR_SAVE_REG 11
161 /* Volatile register used to save MSR in interrupt handlers. */
162
163
164 /* Debug stuff. */
165
166 /* How to renumber registers for dbx and gdb. */
167 #define DBX_REGISTER_NUMBER(REGNO) microblaze_dbx_regno[(REGNO)]
168
169 /* Generate DWARF exception handling info. */
170 #define DWARF2_UNWIND_INFO 1
171
172 /* Don't generate .loc operations. */
173 #define DWARF2_ASM_LINE_DEBUG_INFO 0
174
175 /* The DWARF 2 CFA column which tracks the return address. */
176 #define DWARF_FRAME_RETURN_COLUMN \
177 (GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
178
179 /* Initial state of return address on entry to func = R15.
180 Actually, the RA is at R15+8, but gcc doesn't know how
181 to generate this.
182 NOTE: GDB has a workaround and expects this incorrect value.
183 If this is fixed, a corresponding fix to GDB is needed. */
184 #define INCOMING_RETURN_ADDR_RTX \
185 gen_rtx_REG (Pmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
186
187 /* Specifies the offset from INCOMING_RETURN_ADDR_RTX and the actual return PC. */
188 #define RETURN_ADDR_OFFSET (8)
189
190 /* Describe how we implement __builtin_eh_return. */
191 #define EH_RETURN_DATA_REGNO(N) \
192 (((N) < 2) ? MB_ABI_FIRST_ARG_REGNUM + (N) : INVALID_REGNUM)
193
194 #define MB_EH_STACKADJ_REGNUM MB_ABI_INT_RETURN_VAL2_REGNUM
195 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, MB_EH_STACKADJ_REGNUM)
196
197 /* Select a format to encode pointers in exception handling data. CODE
198 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
199 true if the symbol may be affected by dynamic relocations. */
200 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
201 ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
202
203 /* Use DWARF 2 debugging information by default. */
204 #define DWARF2_DEBUGGING_INFO
205 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
206
207 /* Target machine storage layout */
208
209 #define BITS_BIG_ENDIAN 0
210 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
211 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
212 #define BITS_PER_WORD 32
213 #define UNITS_PER_WORD 4
214 #define MIN_UNITS_PER_WORD 4
215 #define INT_TYPE_SIZE 32
216 #define SHORT_TYPE_SIZE 16
217 #define LONG_TYPE_SIZE 32
218 #define LONG_LONG_TYPE_SIZE 64
219 #define FLOAT_TYPE_SIZE 32
220 #define DOUBLE_TYPE_SIZE 64
221 #define LONG_DOUBLE_TYPE_SIZE 64
222 #define POINTER_SIZE 32
223 #define PARM_BOUNDARY 32
224 #define FUNCTION_BOUNDARY 32
225 #define EMPTY_FIELD_BOUNDARY 32
226 #define STRUCTURE_SIZE_BOUNDARY 8
227 #define BIGGEST_ALIGNMENT 32
228 #define STRICT_ALIGNMENT 1
229 #define PCC_BITFIELD_TYPE_MATTERS 1
230
231 #undef SIZE_TYPE
232 #define SIZE_TYPE "unsigned int"
233
234 #undef PTRDIFF_TYPE
235 #define PTRDIFF_TYPE "int"
236
237 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
238 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
239 && (ALIGN) < BITS_PER_WORD \
240 ? BITS_PER_WORD \
241 : (ALIGN))
242
243 #define DATA_ALIGNMENT(TYPE, ALIGN) \
244 ((((ALIGN) < BITS_PER_WORD) \
245 && (TREE_CODE (TYPE) == ARRAY_TYPE \
246 || TREE_CODE (TYPE) == UNION_TYPE \
247 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
248
249 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
250 (((TREE_CODE (TYPE) == ARRAY_TYPE \
251 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
252 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
253
254 #define WORD_REGISTER_OPERATIONS 1
255
256 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
257
258 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
259 if (GET_MODE_CLASS (MODE) == MODE_INT \
260 && GET_MODE_SIZE (MODE) < 4) \
261 (MODE) = SImode;
262
263 /* Standard register usage. */
264
265 /* On the MicroBlaze, we have 32 integer registers */
266
267 #define FIRST_PSEUDO_REGISTER 36
268
269 #define FIXED_REGISTERS \
270 { \
271 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
272 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
273 1, 1, 1, 1 \
274 }
275
276 #define CALL_USED_REGISTERS \
277 { \
278 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
279 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
280 1, 1, 1, 1 \
281 }
282 #define GP_REG_FIRST 0
283 #define GP_REG_LAST 31
284 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
285 #define GP_DBX_FIRST 0
286
287 #define ST_REG 32
288 #define AP_REG_NUM 33
289 #define RAP_REG_NUM 34
290 #define FRP_REG_NUM 35
291
292 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
293 #define ST_REG_P(REGNO) ((REGNO) == ST_REG)
294
295 #define STACK_POINTER_REGNUM (GP_REG_FIRST + MB_ABI_STACK_POINTER_REGNUM)
296
297 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(FNDECL)
298
299 /* Base register for access to local variables of the function. We
300 pretend that the frame pointer is
301 MB_ABI_INTR_RETURN_ADDR_REGNUM, and then eliminate it
302 to HARD_FRAME_POINTER_REGNUM. We can get away with this because
303 rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed
304 register(return address for interrupt), and will not be used for
305 anything else. */
306
307 #define FRAME_POINTER_REGNUM FRP_REG_NUM
308 #define HARD_FRAME_POINTER_REGNUM \
309 (GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM)
310 #define ARG_POINTER_REGNUM AP_REG_NUM
311 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
312 #define STATIC_CHAIN_REGNUM \
313 (GP_REG_FIRST + MB_ABI_STATIC_CHAIN_REGNUM)
314
315 /* registers used in prologue/epilogue code when the stack frame
316 is larger than 32K bytes. These registers must come from the
317 scratch register set, and not used for passing and returning
318 arguments and any other information used in the calling sequence
319 (such as pic). */
320
321 #define MICROBLAZE_TEMP1_REGNUM \
322 (GP_REG_FIRST + MB_ABI_TEMP1_REGNUM)
323
324 #define MICROBLAZE_TEMP2_REGNUM \
325 (GP_REG_FIRST + MB_ABI_TEMP2_REGNUM)
326
327 #define NO_FUNCTION_CSE 1
328
329 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + MB_ABI_PIC_ADDR_REGNUM)
330
331 enum reg_class
332 {
333 NO_REGS, /* no registers in set. */
334 GR_REGS, /* integer registers. */
335 ST_REGS, /* status register. */
336 ALL_REGS, /* all registers. */
337 LIM_REG_CLASSES /* max value + 1. */
338 };
339
340 #define N_REG_CLASSES (int) LIM_REG_CLASSES
341
342 #define GENERAL_REGS GR_REGS
343
344 #define REG_CLASS_NAMES \
345 { \
346 "NO_REGS", \
347 "GR_REGS", \
348 "ST_REGS", \
349 "ALL_REGS" \
350 }
351
352 #define REG_CLASS_CONTENTS \
353 { \
354 { 0x00000000, 0x00000000 }, /* no registers. */ \
355 { 0xffffffff, 0x00000000 }, /* integer registers. */ \
356 { 0x00000000, 0x00000001 }, /* status registers. */ \
357 { 0xffffffff, 0x0000000f } /* all registers. */ \
358 }
359
360 extern enum reg_class microblaze_regno_to_class[];
361
362 #define REGNO_REG_CLASS(REGNO) microblaze_regno_to_class[ (REGNO) ]
363
364 #define BASE_REG_CLASS GR_REGS
365
366 #define INDEX_REG_CLASS GR_REGS
367
368 #define GR_REG_CLASS_P(CLASS) ((CLASS) == GR_REGS)
369
370 /* REGISTER AND CONSTANT CLASSES */
371
372 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
373 #define LARGE_INT(X) \
374 (INTVAL (X) > 0 && UINTVAL (X) >= 0x80000000 && UINTVAL (X) <= 0xffffffff)
375 #define PLT_ADDR_P(X) (GET_CODE (X) == UNSPEC && XINT (X,1) == UNSPEC_PLT)
376 /* Test for a valid operand for a call instruction.
377 Don't allow the arg pointer register or virtual regs
378 since they may change into reg + const, which the patterns
379 can't handle yet. */
380 #define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \
381 || (GET_CODE (X) == REG && X != arg_pointer_rtx\
382 && ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \
383 && REGNO (X) <= LAST_VIRTUAL_REGISTER)))
384
385 /* True if VALUE is a signed 16-bit number. */
386 #define SMALL_OPERAND(VALUE) \
387 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
388
389 /* Constant which cannot be loaded in one instruction. */
390 #define LARGE_OPERAND(VALUE) \
391 ((((VALUE) & ~0x0000ffff) != 0) \
392 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
393 && (((VALUE) & 0x0000ffff) != 0 \
394 || (((VALUE) & ~2147483647) != 0 \
395 && ((VALUE) & ~2147483647) != ~2147483647)))
396
397 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
398 ((CLASS) != ALL_REGS \
399 ? (CLASS) \
400 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
401 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
402 ? (GR_REGS) \
403 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
404 || GET_MODE (X) == VOIDmode) \
405 ? (GR_REGS) : (CLASS))))
406
407 /* Stack layout; function entry, exit and calling. */
408
409 #define STACK_GROWS_DOWNWARD 1
410
411 /* Changed the starting frame offset to including the new link stuff */
412 #define STARTING_FRAME_OFFSET \
413 (crtl->outgoing_args_size + FIRST_PARM_OFFSET(FNDECL))
414
415 /* The return address for the current frame is in r31 if this is a leaf
416 function. Otherwise, it is on the stack. It is at a variable offset
417 from sp/fp/ap, so we define a fake hard register rap which is a
418 poiner to the return address on the stack. This always gets eliminated
419 during reload to be either the frame pointer or the stack pointer plus
420 an offset. */
421
422 #define RETURN_ADDR_RTX(count, frame) \
423 microblaze_return_addr(count,frame)
424
425 extern struct microblaze_frame_info current_frame_info;
426
427 #define ELIMINABLE_REGS \
428 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
429 { ARG_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
430 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
431 { RETURN_ADDRESS_POINTER_REGNUM, \
432 GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
433 { RETURN_ADDRESS_POINTER_REGNUM, \
434 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM}, \
435 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
436 { FRAME_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}}
437
438 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
439 (OFFSET) = microblaze_initial_elimination_offset ((FROM), (TO))
440
441 #define ACCUMULATE_OUTGOING_ARGS 1
442
443 #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
444
445 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
446
447 #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
448
449 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
450
451 #define STACK_BOUNDARY 32
452
453 #define NUM_OF_ARGS 6
454
455 #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
456
457 #define GP_ARG_FIRST (GP_REG_FIRST + MB_ABI_FIRST_ARG_REGNUM)
458 #define GP_ARG_LAST (GP_REG_FIRST + MB_ABI_LAST_ARG_REGNUM)
459
460 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
461
462 #define LIBCALL_VALUE(MODE) \
463 gen_rtx_REG ( \
464 ((GET_MODE_CLASS (MODE) != MODE_INT \
465 || GET_MODE_SIZE (MODE) >= 4) \
466 ? (MODE) \
467 : SImode), GP_RETURN)
468
469 /* 1 if N is a possible register number for a function value.
470 On the MicroBlaze, R2 R3 are the only register thus used.
471 Currently, R2 are only implemented here (C has no complex type) */
472
473 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
474
475 #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
476
477 typedef struct microblaze_args
478 {
479 int gp_reg_found; /* whether a gp register was found yet */
480 int arg_number; /* argument number */
481 int arg_words; /* # total words the arguments take */
482 int fp_arg_words; /* # words for FP args */
483 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
484 int fp_code; /* Mode of FP arguments */
485 int num_adjusts; /* number of adjustments made */
486 /* Adjustments made to args pass in regs. */
487 /* ??? The size is doubled to work around a bug in the code that sets the
488 adjustments in function_arg. */
489 rtx adjust[MAX_ARGS_IN_REGISTERS * 2];
490 } CUMULATIVE_ARGS;
491
492 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
493 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
494
495 #define NO_PROFILE_COUNTERS 1
496
497 #define FUNCTION_PROFILER(FILE, LABELNO) { \
498 { \
499 fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
500 } \
501 }
502
503 #define EXIT_IGNORE_STACK 1
504
505 /* 4 insns + 2 words of data. */
506 #define TRAMPOLINE_SIZE (6 * 4)
507
508 #define TRAMPOLINE_ALIGNMENT 32
509
510 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
511
512 #define REGNO_OK_FOR_INDEX_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
513
514 #ifndef REG_OK_STRICT
515 #define REG_STRICT_FLAG 0
516 #else
517 #define REG_STRICT_FLAG 1
518 #endif
519
520 #define REG_OK_FOR_BASE_P(X) \
521 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
522
523 #define REG_OK_FOR_INDEX_P(X) \
524 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
525
526 #define MAX_REGS_PER_ADDRESS 2
527
528
529 /* Identify valid constant addresses. Exclude if PIC addr which
530 needs scratch register. */
531 #define CONSTANT_ADDRESS_P(X) \
532 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
533 || GET_CODE (X) == CONST_INT \
534 || (GET_CODE (X) == CONST \
535 && ! (flag_pic && pic_address_needs_scratch (X))))
536
537 /* Define this, so that when PIC, reload won't try to reload invalid
538 addresses which require two reload registers. */
539 #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X)
540
541 #define CASE_VECTOR_MODE (SImode)
542
543 #ifndef DEFAULT_SIGNED_CHAR
544 #define DEFAULT_SIGNED_CHAR 1
545 #endif
546
547 #define MOVE_MAX 4
548 #define MAX_MOVE_MAX 8
549
550 #define SLOW_BYTE_ACCESS 1
551
552 /* sCOND operations return 1. */
553 #define STORE_FLAG_VALUE 1
554
555 #define SHIFT_COUNT_TRUNCATED 1
556
557 /* This results in inefficient code for 64 bit to 32 conversions.
558 Something needs to be done about this. Perhaps not use any 32 bit
559 instructions? Perhaps use PROMOTE_MODE? */
560 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
561
562 #define Pmode SImode
563
564 #define FUNCTION_MODE SImode
565
566 /* Mode should always be SImode */
567 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
568 ( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \
569 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
570 : 12)
571
572 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
573 (4 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
574
575 #define BRANCH_COST(speed_p, predictable_p) 2
576
577 /* Control the assembler format that we output. */
578 #define ASM_APP_ON " #APP\n"
579 #define ASM_APP_OFF " #NO_APP\n"
580
581 #define REGISTER_NAMES { \
582 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
583 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
584 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
585 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
586 "rmsr", "$ap", "$rap", "$frp" }
587
588 #define ADDITIONAL_REGISTER_NAMES \
589 { \
590 { "r0", 0 + GP_REG_FIRST }, \
591 { "r1", 1 + GP_REG_FIRST }, \
592 { "r2", 2 + GP_REG_FIRST }, \
593 { "r3", 3 + GP_REG_FIRST }, \
594 { "r4", 4 + GP_REG_FIRST }, \
595 { "r5", 5 + GP_REG_FIRST }, \
596 { "r6", 6 + GP_REG_FIRST }, \
597 { "r7", 7 + GP_REG_FIRST }, \
598 { "r8", 8 + GP_REG_FIRST }, \
599 { "r9", 9 + GP_REG_FIRST }, \
600 { "r10", 10 + GP_REG_FIRST }, \
601 { "r11", 11 + GP_REG_FIRST }, \
602 { "r12", 12 + GP_REG_FIRST }, \
603 { "r13", 13 + GP_REG_FIRST }, \
604 { "r14", 14 + GP_REG_FIRST }, \
605 { "r15", 15 + GP_REG_FIRST }, \
606 { "r16", 16 + GP_REG_FIRST }, \
607 { "r17", 17 + GP_REG_FIRST }, \
608 { "r18", 18 + GP_REG_FIRST }, \
609 { "r19", 19 + GP_REG_FIRST }, \
610 { "r20", 20 + GP_REG_FIRST }, \
611 { "r21", 21 + GP_REG_FIRST }, \
612 { "r22", 22 + GP_REG_FIRST }, \
613 { "r23", 23 + GP_REG_FIRST }, \
614 { "r24", 24 + GP_REG_FIRST }, \
615 { "r25", 25 + GP_REG_FIRST }, \
616 { "r26", 26 + GP_REG_FIRST }, \
617 { "r27", 27 + GP_REG_FIRST }, \
618 { "r28", 28 + GP_REG_FIRST }, \
619 { "r29", 29 + GP_REG_FIRST }, \
620 { "r30", 30 + GP_REG_FIRST }, \
621 { "r31", 31 + GP_REG_FIRST }, \
622 { "rmsr", ST_REG} \
623 }
624
625 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
626
627 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) microblaze_print_operand_punct[CODE]
628
629 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
630
631 /* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL
632
633 Unfortunately, we still need to set the section explicitly. Somehow,
634 our binutils assign .comm and .lcomm variables to the "current" section
635 in the assembly file, rather than where they implicitly belong. We need to
636 remove this explicit setting in GCC when binutils can understand sections
637 better. */
638 #undef ASM_OUTPUT_ALIGNED_COMMON
639 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
640 do { \
641 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
642 && (int) (SIZE) <= microblaze_section_threshold \
643 && TARGET_XLGPOPT) \
644 { \
645 switch_to_section (sbss_section); \
646 } \
647 else \
648 { \
649 switch_to_section (bss_section); \
650 } \
651 fprintf (FILE, "%s", COMMON_ASM_OP); \
652 assemble_name ((FILE), (NAME)); \
653 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
654 (SIZE), (ALIGN) / BITS_PER_UNIT); \
655 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
656 } while (0)
657
658 #undef ASM_OUTPUT_ALIGNED_LOCAL
659 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
660 do { \
661 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
662 && (int) (SIZE) <= microblaze_section_threshold \
663 && TARGET_XLGPOPT) \
664 { \
665 switch_to_section (sbss_section); \
666 } \
667 else \
668 { \
669 switch_to_section (bss_section); \
670 } \
671 fprintf (FILE, "%s", LCOMMON_ASM_OP); \
672 assemble_name ((FILE), (NAME)); \
673 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
674 (SIZE), (ALIGN) / BITS_PER_UNIT); \
675 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
676 } while (0)
677
678 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
679 do { \
680 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
681 } while (0)
682
683 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
684 { \
685 }
686
687 #undef TARGET_ASM_CONSTRUCTOR
688 #define TARGET_ASM_CONSTRUCTOR microblaze_elf_asm_constructor
689
690 #undef TARGET_ASM_DESTRUCTOR
691 #define TARGET_ASM_DESTRUCTOR microblaze_elf_asm_destructor
692
693 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
694 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
695
696 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
697 fprintf (STREAM, "\t%s\t%sL%d\n", \
698 ".gpword", \
699 LOCAL_LABEL_PREFIX, VALUE)
700
701 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
702 do { \
703 if (flag_pic == 2) \
704 fprintf (STREAM, "\t%s\t%sL%d@GOTOFF\n", \
705 ".gpword", \
706 LOCAL_LABEL_PREFIX, VALUE); \
707 else \
708 fprintf (STREAM, "\t%s\t%sL%d\n", \
709 ".gpword", \
710 LOCAL_LABEL_PREFIX, VALUE); \
711 } while (0)
712
713 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
714 fprintf (STREAM, "\t.align\t%d\n", (LOG))
715
716 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
717 fprintf (STREAM, "\t.space\t%lu\n", (SIZE))
718
719 #define ASCII_DATA_ASM_OP "\t.ascii\t"
720 #define STRING_ASM_OP "\t.asciz\t"
721
722 #undef TARGET_ASM_OUTPUT_IDENT
723 #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
724
725 /* Default to -G 8 */
726 #ifndef MICROBLAZE_DEFAULT_GVALUE
727 #define MICROBLAZE_DEFAULT_GVALUE 8
728 #endif
729
730 /* Given a decl node or constant node, choose the section to output it in
731 and select that section. */
732
733 /* Store in OUTPUT a string (made with alloca) containing
734 an assembler-name for a local static variable named NAME.
735 LABELNO is an integer which is different for each call. */
736 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
737 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 13), \
738 sprintf ((OUTPUT), "%s.%lu", (NAME), (unsigned long)(LABELNO)))
739
740 /* How to start an assembler comment.
741 The leading space is important (the microblaze assembler requires it). */
742 #ifndef ASM_COMMENT_START
743 #define ASM_COMMENT_START " #"
744 #endif
745
746 #define BSS_VAR 1
747 #define SBSS_VAR 2
748 #define DATA_VAR 4
749 #define SDATA_VAR 5
750 #define RODATA_VAR 6
751 #define SDATA2_VAR 7
752
753 /* These definitions are used in with the shift_type flag in the rtl. */
754 #define SHIFT_CONST 1
755 #define SHIFT_REG 2
756 #define USE_ADDK 3
757
758 /* Handle interrupt attribute. */
759 extern int interrupt_handler;
760 extern int fast_interrupt;
761 extern int save_volatiles;
762
763 #define INTERRUPT_HANDLER_NAME "_interrupt_handler"
764 /* The function name for the function tagged with attribute break_handler
765 has been set in the RTL as _break_handler. This function name is used
766 in the generation of directives .ent .end and .global. */
767 #define BREAK_HANDLER_NAME "_break_handler"
768 #define FAST_INTERRUPT_NAME "_fast_interrupt"
769
770 /* The following #defines are used in the headers files. Always retain these. */
771
772 /* Added for declaring size at the end of the function. */
773 #undef ASM_DECLARE_FUNCTION_SIZE
774 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
775 do { \
776 if (!flag_inhibit_size_directive) \
777 { \
778 char label[256]; \
779 static int labelno; \
780 labelno++; \
781 ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \
782 (*targetm.asm_out.internal_label) (FILE, "Lfe", labelno); \
783 fprintf (FILE, "%s", SIZE_ASM_OP); \
784 assemble_name (FILE, (FNAME)); \
785 fprintf (FILE, ","); \
786 assemble_name (FILE, label); \
787 fprintf (FILE, "-"); \
788 assemble_name (FILE, (FNAME)); \
789 putc ('\n', FILE); \
790 } \
791 } while (0)
792
793 #define GLOBAL_ASM_OP "\t.globl\t"
794 #define TYPE_ASM_OP "\t.type\t"
795 #define SIZE_ASM_OP "\t.size\t"
796 #define COMMON_ASM_OP "\t.comm\t"
797 #define LCOMMON_ASM_OP "\t.lcomm\t"
798
799 #define MAX_OFILE_ALIGNMENT (32768*8)
800
801 #define TYPE_OPERAND_FMT "@%s"
802
803 /* Write the extra assembler code needed to declare an object properly. */
804 #undef ASM_DECLARE_OBJECT_NAME
805 #define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \
806 do { \
807 fprintf (FILE, "%s", TYPE_ASM_OP); \
808 assemble_name (FILE, NAME); \
809 putc (',', FILE); \
810 fprintf (FILE, TYPE_OPERAND_FMT, "object"); \
811 putc ('\n', FILE); \
812 size_directive_output = 0; \
813 if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \
814 { \
815 size_directive_output = 1; \
816 fprintf (FILE, "%s", SIZE_ASM_OP); \
817 assemble_name (FILE, NAME); \
818 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
819 int_size_in_bytes (TREE_TYPE (DECL))); \
820 } \
821 microblaze_declare_object (FILE, NAME, "", ":\n", 0); \
822 } while (0)
823
824 #undef ASM_FINISH_DECLARE_OBJECT
825 #define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \
826 do { \
827 const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
828 if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \
829 && ! AT_END && TOP_LEVEL \
830 && DECL_INITIAL (DECL) == error_mark_node \
831 && !size_directive_output) \
832 { \
833 size_directive_output = 1; \
834 fprintf (FILE, "%s", SIZE_ASM_OP); \
835 assemble_name (FILE, name); \
836 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
837 int_size_in_bytes (TREE_TYPE (DECL))); \
838 } \
839 } while (0)
840
841 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \
842 do { fputc ( '\t', FILE); \
843 assemble_name (FILE, LABEL1); \
844 fputs ( " = ", FILE); \
845 assemble_name (FILE, LABEL2); \
846 fputc ( '\n', FILE); \
847 } while (0)
848
849 #define ASM_WEAKEN_LABEL(FILE,NAME) \
850 do { fputs ("\t.weakext\t", FILE); \
851 assemble_name (FILE, NAME); \
852 fputc ('\n', FILE); \
853 } while (0)
854
855 #define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
856 #undef UNIQUE_SECTION_P
857 #define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
858
859 #undef TARGET_ASM_NAMED_SECTION
860 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
861
862 /* Define the strings to put out for each section in the object file.
863
864 Note: For ctors/dtors, we want to give these sections the SHF_WRITE
865 attribute to allow shared libraries to patch/resolve addresses into
866 these locations. On Microblaze, there is no concept of shared libraries
867 yet, so this is for future use. */
868 #define TEXT_SECTION_ASM_OP "\t.text"
869 #define DATA_SECTION_ASM_OP "\t.data"
870 #define READONLY_DATA_SECTION_ASM_OP \
871 "\t.rodata"
872 #define BSS_SECTION_ASM_OP "\t.bss"
873 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
874 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
875 #define INIT_SECTION_ASM_OP "\t.section\t.init,\"ax\""
876 #define FINI_SECTION_ASM_OP "\t.section\t.fini,\"ax\""
877
878 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small RW initialized data */
879 #define SDATA2_SECTION_ASM_OP "\t.sdata2" /* Small RO initialized data */
880 #define SBSS_SECTION_ASM_OP "\t.sbss" /* Small RW uninitialized data */
881 #define SBSS2_SECTION_ASM_OP "\t.sbss2" /* Small RO uninitialized data */
882
883 /* We do this to save a few 10s of code space that would be taken up
884 by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
885 definition in crtstuff.c. */
886 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
887 asm ( SECTION_OP "\n" \
888 "\tbrlid r15, " #FUNC "\n\t nop\n" \
889 TEXT_SECTION_ASM_OP);
890
891 /* We need to group -lm as well, since some Newlib math functions
892 reference __errno! */
893 #undef LIB_SPEC
894 #define LIB_SPEC \
895 "%{!nostdlib: \
896 %{pg:-start-group -lxilprofile -lgloss -lxil -lc -lm -end-group } \
897 %{!pg:-start-group -lgloss -lxil -lc -lm -end-group }} "
898
899 /* microblaze-unknown-elf target has no support of C99 runtime */
900 #undef TARGET_LIBC_HAS_FUNCTION
901 #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
902
903 #undef ENDFILE_SPEC
904 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
905
906 #define STARTFILE_EXECUTABLE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
907 #define STARTFILE_XMDSTUB_SPEC "crt1.o%s crti.o%s crtbegin.o%s"
908 #define STARTFILE_BOOTSTRAP_SPEC "crt2.o%s crti.o%s crtbegin.o%s"
909 #define STARTFILE_NOVECTORS_SPEC "crt3.o%s crti.o%s crtbegin.o%s"
910 #define STARTFILE_CRTINIT_SPEC "%{!pg: %{!mno-clearbss: crtinit.o%s} \
911 %{mno-clearbss: sim-crtinit.o%s}} \
912 %{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}"
913
914 #define STARTFILE_DEFAULT_SPEC STARTFILE_EXECUTABLE_SPEC
915
916 #undef SUBTARGET_EXTRA_SPECS
917 #define SUBTARGET_EXTRA_SPECS \
918 { "startfile_executable", STARTFILE_EXECUTABLE_SPEC }, \
919 { "startfile_xmdstub", STARTFILE_XMDSTUB_SPEC }, \
920 { "startfile_bootstrap", STARTFILE_BOOTSTRAP_SPEC }, \
921 { "startfile_novectors", STARTFILE_NOVECTORS_SPEC }, \
922 { "startfile_crtinit", STARTFILE_CRTINIT_SPEC }, \
923 { "startfile_default", STARTFILE_DEFAULT_SPEC },
924
925 #undef STARTFILE_SPEC
926 #define STARTFILE_SPEC "\
927 %{Zxl-mode-executable : %(startfile_executable) ; \
928 mxl-mode-executable : %(startfile_executable) ; \
929 Zxl-mode-xmdstub : %(startfile_xmdstub) ; \
930 mxl-mode-xmdstub : %(startfile_xmdstub) ; \
931 Zxl-mode-bootstrap : %(startfile_bootstrap) ; \
932 mxl-mode-bootstrap : %(startfile_bootstrap) ; \
933 Zxl-mode-novectors : %(startfile_novectors) ; \
934 mxl-mode-novectors : %(startfile_novectors) ; \
935 Zxl-mode-xilkernel : %(startfile_xilkernel) ; \
936 mxl-mode-xilkernel : %(startfile_xilkernel) ; \
937 : %(startfile_default) \
938 } \
939 %(startfile_crtinit)"
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