1 /* Subroutines used for MIPS code generation.
2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
5 Free Software Foundation, Inc.
6 Contributed by A. Lichnewsky, lich@inria.inria.fr.
7 Changes by Michael Meissner, meissner@osf.org.
8 64-bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
9 Brendan Eich, brendan@microunity.com.
11 This file is part of GCC.
13 GCC is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GCC is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GCC; see the file COPYING3. If not see
25 <http://www.gnu.org/licenses/>. */
29 #include "coretypes.h"
33 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-attr.h"
52 #include "target-def.h"
53 #include "integrate.h"
54 #include "langhooks.h"
55 #include "cfglayout.h"
56 #include "sched-int.h"
59 #include "diagnostic.h"
60 #include "target-globals.h"
62 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
63 #define UNSPEC_ADDRESS_P(X) \
64 (GET_CODE (X) == UNSPEC \
65 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
66 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
68 /* Extract the symbol or label from UNSPEC wrapper X. */
69 #define UNSPEC_ADDRESS(X) \
72 /* Extract the symbol type from UNSPEC wrapper X. */
73 #define UNSPEC_ADDRESS_TYPE(X) \
74 ((enum mips_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
76 /* The maximum distance between the top of the stack frame and the
77 value $sp has when we save and restore registers.
79 The value for normal-mode code must be a SMALL_OPERAND and must
80 preserve the maximum stack alignment. We therefore use a value
81 of 0x7ff0 in this case.
83 MIPS16e SAVE and RESTORE instructions can adjust the stack pointer by
84 up to 0x7f8 bytes and can usually save or restore all the registers
85 that we need to save or restore. (Note that we can only use these
86 instructions for o32, for which the stack alignment is 8 bytes.)
88 We use a maximum gap of 0x100 or 0x400 for MIPS16 code when SAVE and
89 RESTORE are not available. We can then use unextended instructions
90 to save and restore registers, and to allocate and deallocate the top
92 #define MIPS_MAX_FIRST_STACK_STEP \
93 (!TARGET_MIPS16 ? 0x7ff0 \
94 : GENERATE_MIPS16E_SAVE_RESTORE ? 0x7f8 \
95 : TARGET_64BIT ? 0x100 : 0x400)
97 /* True if INSN is a mips.md pattern or asm statement. */
98 #define USEFUL_INSN_P(INSN) \
99 (NONDEBUG_INSN_P (INSN) \
100 && GET_CODE (PATTERN (INSN)) != USE \
101 && GET_CODE (PATTERN (INSN)) != CLOBBER \
102 && GET_CODE (PATTERN (INSN)) != ADDR_VEC \
103 && GET_CODE (PATTERN (INSN)) != ADDR_DIFF_VEC)
105 /* If INSN is a delayed branch sequence, return the first instruction
106 in the sequence, otherwise return INSN itself. */
107 #define SEQ_BEGIN(INSN) \
108 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
109 ? XVECEXP (PATTERN (INSN), 0, 0) \
112 /* Likewise for the last instruction in a delayed branch sequence. */
113 #define SEQ_END(INSN) \
114 (INSN_P (INSN) && GET_CODE (PATTERN (INSN)) == SEQUENCE \
115 ? XVECEXP (PATTERN (INSN), 0, XVECLEN (PATTERN (INSN), 0) - 1) \
118 /* Execute the following loop body with SUBINSN set to each instruction
119 between SEQ_BEGIN (INSN) and SEQ_END (INSN) inclusive. */
120 #define FOR_EACH_SUBINSN(SUBINSN, INSN) \
121 for ((SUBINSN) = SEQ_BEGIN (INSN); \
122 (SUBINSN) != NEXT_INSN (SEQ_END (INSN)); \
123 (SUBINSN) = NEXT_INSN (SUBINSN))
125 /* True if bit BIT is set in VALUE. */
126 #define BITSET_P(VALUE, BIT) (((VALUE) & (1 << (BIT))) != 0)
128 /* Return the opcode for a ptr_mode load of the form:
130 l[wd] DEST, OFFSET(BASE). */
131 #define MIPS_LOAD_PTR(DEST, OFFSET, BASE) \
132 (((ptr_mode == DImode ? 0x37 : 0x23) << 26) \
137 /* Return the opcode to move register SRC into register DEST. */
138 #define MIPS_MOVE(DEST, SRC) \
139 ((TARGET_64BIT ? 0x2d : 0x21) \
143 /* Return the opcode for:
146 #define MIPS_LUI(DEST, VALUE) \
147 ((0xf << 26) | ((DEST) << 16) | (VALUE))
149 /* Return the opcode to jump to register DEST. */
150 #define MIPS_JR(DEST) \
151 (((DEST) << 21) | 0x8)
153 /* Return the opcode for:
155 bal . + (1 + OFFSET) * 4. */
156 #define MIPS_BAL(OFFSET) \
157 ((0x1 << 26) | (0x11 << 16) | (OFFSET))
159 /* Return the usual opcode for a nop. */
162 /* Classifies an address.
165 A natural register + offset address. The register satisfies
166 mips_valid_base_register_p and the offset is a const_arith_operand.
169 A LO_SUM rtx. The first operand is a valid base register and
170 the second operand is a symbolic address.
173 A signed 16-bit constant address.
176 A constant symbolic address. */
177 enum mips_address_type
{
184 /* Enumerates the setting of the -mr10k-cache-barrier option. */
185 enum mips_r10k_cache_barrier_setting
{
186 R10K_CACHE_BARRIER_NONE
,
187 R10K_CACHE_BARRIER_STORE
,
188 R10K_CACHE_BARRIER_LOAD_STORE
191 /* Macros to create an enumeration identifier for a function prototype. */
192 #define MIPS_FTYPE_NAME1(A, B) MIPS_##A##_FTYPE_##B
193 #define MIPS_FTYPE_NAME2(A, B, C) MIPS_##A##_FTYPE_##B##_##C
194 #define MIPS_FTYPE_NAME3(A, B, C, D) MIPS_##A##_FTYPE_##B##_##C##_##D
195 #define MIPS_FTYPE_NAME4(A, B, C, D, E) MIPS_##A##_FTYPE_##B##_##C##_##D##_##E
197 /* Classifies the prototype of a built-in function. */
198 enum mips_function_type
{
199 #define DEF_MIPS_FTYPE(NARGS, LIST) MIPS_FTYPE_NAME##NARGS LIST,
200 #include "config/mips/mips-ftypes.def"
201 #undef DEF_MIPS_FTYPE
205 /* Specifies how a built-in function should be converted into rtl. */
206 enum mips_builtin_type
{
207 /* The function corresponds directly to an .md pattern. The return
208 value is mapped to operand 0 and the arguments are mapped to
209 operands 1 and above. */
212 /* The function corresponds directly to an .md pattern. There is no return
213 value and the arguments are mapped to operands 0 and above. */
214 MIPS_BUILTIN_DIRECT_NO_TARGET
,
216 /* The function corresponds to a comparison instruction followed by
217 a mips_cond_move_tf_ps pattern. The first two arguments are the
218 values to compare and the second two arguments are the vector
219 operands for the movt.ps or movf.ps instruction (in assembly order). */
223 /* The function corresponds to a V2SF comparison instruction. Operand 0
224 of this instruction is the result of the comparison, which has mode
225 CCV2 or CCV4. The function arguments are mapped to operands 1 and
226 above. The function's return value is an SImode boolean that is
227 true under the following conditions:
229 MIPS_BUILTIN_CMP_ANY: one of the registers is true
230 MIPS_BUILTIN_CMP_ALL: all of the registers are true
231 MIPS_BUILTIN_CMP_LOWER: the first register is true
232 MIPS_BUILTIN_CMP_UPPER: the second register is true. */
233 MIPS_BUILTIN_CMP_ANY
,
234 MIPS_BUILTIN_CMP_ALL
,
235 MIPS_BUILTIN_CMP_UPPER
,
236 MIPS_BUILTIN_CMP_LOWER
,
238 /* As above, but the instruction only sets a single $fcc register. */
239 MIPS_BUILTIN_CMP_SINGLE
,
241 /* For generating bposge32 branch instructions in MIPS32 DSP ASE. */
242 MIPS_BUILTIN_BPOSGE32
245 /* Invoke MACRO (COND) for each C.cond.fmt condition. */
246 #define MIPS_FP_CONDITIONS(MACRO) \
264 /* Enumerates the codes above as MIPS_FP_COND_<X>. */
265 #define DECLARE_MIPS_COND(X) MIPS_FP_COND_ ## X
266 enum mips_fp_condition
{
267 MIPS_FP_CONDITIONS (DECLARE_MIPS_COND
)
270 /* Index X provides the string representation of MIPS_FP_COND_<X>. */
271 #define STRINGIFY(X) #X
272 static const char *const mips_fp_conditions
[] = {
273 MIPS_FP_CONDITIONS (STRINGIFY
)
276 /* Information about a function's frame layout. */
277 struct GTY(()) mips_frame_info
{
278 /* The size of the frame in bytes. */
279 HOST_WIDE_INT total_size
;
281 /* The number of bytes allocated to variables. */
282 HOST_WIDE_INT var_size
;
284 /* The number of bytes allocated to outgoing function arguments. */
285 HOST_WIDE_INT args_size
;
287 /* The number of bytes allocated to the .cprestore slot, or 0 if there
289 HOST_WIDE_INT cprestore_size
;
291 /* Bit X is set if the function saves or restores GPR X. */
294 /* Likewise FPR X. */
297 /* Likewise doubleword accumulator X ($acX). */
298 unsigned int acc_mask
;
300 /* The number of GPRs, FPRs, doubleword accumulators and COP0
304 unsigned int num_acc
;
305 unsigned int num_cop0_regs
;
307 /* The offset of the topmost GPR, FPR, accumulator and COP0-register
308 save slots from the top of the frame, or zero if no such slots are
310 HOST_WIDE_INT gp_save_offset
;
311 HOST_WIDE_INT fp_save_offset
;
312 HOST_WIDE_INT acc_save_offset
;
313 HOST_WIDE_INT cop0_save_offset
;
315 /* Likewise, but giving offsets from the bottom of the frame. */
316 HOST_WIDE_INT gp_sp_offset
;
317 HOST_WIDE_INT fp_sp_offset
;
318 HOST_WIDE_INT acc_sp_offset
;
319 HOST_WIDE_INT cop0_sp_offset
;
321 /* Similar, but the value passed to _mcount. */
322 HOST_WIDE_INT ra_fp_offset
;
324 /* The offset of arg_pointer_rtx from the bottom of the frame. */
325 HOST_WIDE_INT arg_pointer_offset
;
327 /* The offset of hard_frame_pointer_rtx from the bottom of the frame. */
328 HOST_WIDE_INT hard_frame_pointer_offset
;
331 struct GTY(()) machine_function
{
332 /* The register returned by mips16_gp_pseudo_reg; see there for details. */
333 rtx mips16_gp_pseudo_rtx
;
335 /* The number of extra stack bytes taken up by register varargs.
336 This area is allocated by the callee at the very top of the frame. */
339 /* The current frame information, calculated by mips_compute_frame_info. */
340 struct mips_frame_info frame
;
342 /* The register to use as the function's global pointer, or INVALID_REGNUM
343 if the function doesn't need one. */
344 unsigned int global_pointer
;
346 /* How many instructions it takes to load a label into $AT, or 0 if
347 this property hasn't yet been calculated. */
348 unsigned int load_label_num_insns
;
350 /* True if mips_adjust_insn_length should ignore an instruction's
352 bool ignore_hazard_length_p
;
354 /* True if the whole function is suitable for .set noreorder and
356 bool all_noreorder_p
;
358 /* True if the function has "inflexible" and "flexible" references
359 to the global pointer. See mips_cfun_has_inflexible_gp_ref_p
360 and mips_cfun_has_flexible_gp_ref_p for details. */
361 bool has_inflexible_gp_insn_p
;
362 bool has_flexible_gp_insn_p
;
364 /* True if the function's prologue must load the global pointer
365 value into pic_offset_table_rtx and store the same value in
366 the function's cprestore slot (if any). Even if this value
367 is currently false, we may decide to set it to true later;
368 see mips_must_initialize_gp_p () for details. */
369 bool must_initialize_gp_p
;
371 /* True if the current function must restore $gp after any potential
372 clobber. This value is only meaningful during the first post-epilogue
373 split_insns pass; see mips_must_initialize_gp_p () for details. */
374 bool must_restore_gp_when_clobbered_p
;
376 /* True if this is an interrupt handler. */
377 bool interrupt_handler_p
;
379 /* True if this is an interrupt handler that uses shadow registers. */
380 bool use_shadow_register_set_p
;
382 /* True if this is an interrupt handler that should keep interrupts
384 bool keep_interrupts_masked_p
;
386 /* True if this is an interrupt handler that should use DERET
388 bool use_debug_exception_return_p
;
391 /* Information about a single argument. */
392 struct mips_arg_info
{
393 /* True if the argument is passed in a floating-point register, or
394 would have been if we hadn't run out of registers. */
397 /* The number of words passed in registers, rounded up. */
398 unsigned int reg_words
;
400 /* For EABI, the offset of the first register from GP_ARG_FIRST or
401 FP_ARG_FIRST. For other ABIs, the offset of the first register from
402 the start of the ABI's argument structure (see the CUMULATIVE_ARGS
403 comment for details).
405 The value is MAX_ARGS_IN_REGISTERS if the argument is passed entirely
407 unsigned int reg_offset
;
409 /* The number of words that must be passed on the stack, rounded up. */
410 unsigned int stack_words
;
412 /* The offset from the start of the stack overflow area of the argument's
413 first stack word. Only meaningful when STACK_WORDS is nonzero. */
414 unsigned int stack_offset
;
417 /* Information about an address described by mips_address_type.
423 REG is the base register and OFFSET is the constant offset.
426 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE
427 is the type of symbol it references.
430 SYMBOL_TYPE is the type of symbol that the address references. */
431 struct mips_address_info
{
432 enum mips_address_type type
;
435 enum mips_symbol_type symbol_type
;
438 /* One stage in a constant building sequence. These sequences have
442 A = A CODE[1] VALUE[1]
443 A = A CODE[2] VALUE[2]
446 where A is an accumulator, each CODE[i] is a binary rtl operation
447 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
448 struct mips_integer_op
{
450 unsigned HOST_WIDE_INT value
;
453 /* The largest number of operations needed to load an integer constant.
454 The worst accepted case for 64-bit constants is LUI,ORI,SLL,ORI,SLL,ORI.
455 When the lowest bit is clear, we can try, but reject a sequence with
456 an extra SLL at the end. */
457 #define MIPS_MAX_INTEGER_OPS 7
459 /* Information about a MIPS16e SAVE or RESTORE instruction. */
460 struct mips16e_save_restore_info
{
461 /* The number of argument registers saved by a SAVE instruction.
462 0 for RESTORE instructions. */
465 /* Bit X is set if the instruction saves or restores GPR X. */
468 /* The total number of bytes to allocate. */
472 /* Costs of various operations on the different architectures. */
474 struct mips_rtx_cost_data
476 unsigned short fp_add
;
477 unsigned short fp_mult_sf
;
478 unsigned short fp_mult_df
;
479 unsigned short fp_div_sf
;
480 unsigned short fp_div_df
;
481 unsigned short int_mult_si
;
482 unsigned short int_mult_di
;
483 unsigned short int_div_si
;
484 unsigned short int_div_di
;
485 unsigned short branch_cost
;
486 unsigned short memory_latency
;
489 /* Global variables for machine-dependent things. */
491 /* The -G setting, or the configuration's default small-data limit if
492 no -G option is given. */
493 static unsigned int mips_small_data_threshold
;
495 /* The number of file directives written by mips_output_filename. */
496 int num_source_filenames
;
498 /* The name that appeared in the last .file directive written by
499 mips_output_filename, or "" if mips_output_filename hasn't
500 written anything yet. */
501 const char *current_function_file
= "";
503 /* A label counter used by PUT_SDB_BLOCK_START and PUT_SDB_BLOCK_END. */
506 /* Arrays that map GCC register numbers to debugger register numbers. */
507 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
508 int mips_dwarf_regno
[FIRST_PSEUDO_REGISTER
];
510 /* The nesting depth of the PRINT_OPERAND '%(', '%<' and '%[' constructs. */
511 struct mips_asm_switch mips_noreorder
= { "reorder", 0 };
512 struct mips_asm_switch mips_nomacro
= { "macro", 0 };
513 struct mips_asm_switch mips_noat
= { "at", 0 };
515 /* True if we're writing out a branch-likely instruction rather than a
517 static bool mips_branch_likely
;
519 /* The current instruction-set architecture. */
520 enum processor mips_arch
;
521 const struct mips_cpu_info
*mips_arch_info
;
523 /* The processor that we should tune the code for. */
524 enum processor mips_tune
;
525 const struct mips_cpu_info
*mips_tune_info
;
527 /* The ISA level associated with mips_arch. */
530 /* The architecture selected by -mipsN, or null if -mipsN wasn't used. */
531 static const struct mips_cpu_info
*mips_isa_option_info
;
533 /* Which ABI to use. */
534 int mips_abi
= MIPS_ABI_DEFAULT
;
536 /* Which cost information to use. */
537 static const struct mips_rtx_cost_data
*mips_cost
;
539 /* The ambient target flags, excluding MASK_MIPS16. */
540 static int mips_base_target_flags
;
542 /* True if MIPS16 is the default mode. */
543 bool mips_base_mips16
;
545 /* The ambient values of other global variables. */
546 static int mips_base_schedule_insns
; /* flag_schedule_insns */
547 static int mips_base_reorder_blocks_and_partition
; /* flag_reorder... */
548 static int mips_base_move_loop_invariants
; /* flag_move_loop_invariants */
549 static int mips_base_align_loops
; /* align_loops */
550 static int mips_base_align_jumps
; /* align_jumps */
551 static int mips_base_align_functions
; /* align_functions */
553 /* The -mcode-readable setting. */
554 enum mips_code_readable_setting mips_code_readable
= CODE_READABLE_YES
;
556 /* The -mr10k-cache-barrier setting. */
557 static enum mips_r10k_cache_barrier_setting mips_r10k_cache_barrier
;
559 /* Index [M][R] is true if register R is allowed to hold a value of mode M. */
560 bool mips_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
562 /* Index C is true if character C is a valid PRINT_OPERAND punctation
564 static bool mips_print_operand_punct
[256];
566 static GTY (()) int mips_output_filename_first_time
= 1;
568 /* mips_split_p[X] is true if symbols of type X can be split by
569 mips_split_symbol. */
570 bool mips_split_p
[NUM_SYMBOL_TYPES
];
572 /* mips_split_hi_p[X] is true if the high parts of symbols of type X
573 can be split by mips_split_symbol. */
574 bool mips_split_hi_p
[NUM_SYMBOL_TYPES
];
576 /* mips_lo_relocs[X] is the relocation to use when a symbol of type X
577 appears in a LO_SUM. It can be null if such LO_SUMs aren't valid or
578 if they are matched by a special .md file pattern. */
579 static const char *mips_lo_relocs
[NUM_SYMBOL_TYPES
];
581 /* Likewise for HIGHs. */
582 static const char *mips_hi_relocs
[NUM_SYMBOL_TYPES
];
584 /* Target state for MIPS16. */
585 struct target_globals
*mips16_globals
;
587 /* Cached value of can_issue_more. This is cached in mips_variable_issue hook
588 and returned from mips_sched_reorder2. */
589 static int cached_can_issue_more
;
591 /* Index R is the smallest register class that contains register R. */
592 const enum reg_class mips_regno_to_class
[FIRST_PSEUDO_REGISTER
] = {
593 LEA_REGS
, LEA_REGS
, M16_REGS
, V1_REG
,
594 M16_REGS
, M16_REGS
, M16_REGS
, M16_REGS
,
595 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
596 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
597 M16_REGS
, M16_REGS
, LEA_REGS
, LEA_REGS
,
598 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
599 T_REG
, PIC_FN_ADDR_REG
, LEA_REGS
, LEA_REGS
,
600 LEA_REGS
, LEA_REGS
, LEA_REGS
, LEA_REGS
,
601 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
602 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
603 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
604 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
605 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
606 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
607 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
608 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
609 MD0_REG
, MD1_REG
, NO_REGS
, ST_REGS
,
610 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
611 ST_REGS
, ST_REGS
, ST_REGS
, NO_REGS
,
612 NO_REGS
, FRAME_REGS
, FRAME_REGS
, NO_REGS
,
613 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
614 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
615 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
616 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
617 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
618 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
619 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
620 COP0_REGS
, COP0_REGS
, COP0_REGS
, COP0_REGS
,
621 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
622 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
623 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
624 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
625 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
626 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
627 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
628 COP2_REGS
, COP2_REGS
, COP2_REGS
, COP2_REGS
,
629 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
630 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
631 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
632 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
633 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
634 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
635 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
636 COP3_REGS
, COP3_REGS
, COP3_REGS
, COP3_REGS
,
637 DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
, DSP_ACC_REGS
,
638 DSP_ACC_REGS
, DSP_ACC_REGS
, ALL_REGS
, ALL_REGS
,
639 ALL_REGS
, ALL_REGS
, ALL_REGS
, ALL_REGS
642 /* The value of TARGET_ATTRIBUTE_TABLE. */
643 static const struct attribute_spec mips_attribute_table
[] = {
644 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
646 { "long_call", 0, 0, false, true, true, NULL
, false },
647 { "far", 0, 0, false, true, true, NULL
, false },
648 { "near", 0, 0, false, true, true, NULL
, false },
649 /* We would really like to treat "mips16" and "nomips16" as type
650 attributes, but GCC doesn't provide the hooks we need to support
651 the right conversion rules. As declaration attributes, they affect
652 code generation but don't carry other semantics. */
653 { "mips16", 0, 0, true, false, false, NULL
, false },
654 { "nomips16", 0, 0, true, false, false, NULL
, false },
655 /* Allow functions to be specified as interrupt handlers */
656 { "interrupt", 0, 0, false, true, true, NULL
, false },
657 { "use_shadow_register_set", 0, 0, false, true, true, NULL
, false },
658 { "keep_interrupts_masked", 0, 0, false, true, true, NULL
, false },
659 { "use_debug_exception_return", 0, 0, false, true, true, NULL
, false },
660 { NULL
, 0, 0, false, false, false, NULL
, false }
663 /* A table describing all the processors GCC knows about. Names are
664 matched in the order listed. The first mention of an ISA level is
665 taken as the canonical name for that ISA.
667 To ease comparison, please keep this table in the same order
668 as GAS's mips_cpu_info_table. Please also make sure that
669 MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
670 options correctly. */
671 static const struct mips_cpu_info mips_cpu_info_table
[] = {
672 /* Entries for generic ISAs. */
673 { "mips1", PROCESSOR_R3000
, 1, 0 },
674 { "mips2", PROCESSOR_R6000
, 2, 0 },
675 { "mips3", PROCESSOR_R4000
, 3, 0 },
676 { "mips4", PROCESSOR_R8000
, 4, 0 },
677 /* Prefer not to use branch-likely instructions for generic MIPS32rX
678 and MIPS64rX code. The instructions were officially deprecated
679 in revisions 2 and earlier, but revision 3 is likely to downgrade
680 that to a recommendation to avoid the instructions in code that
681 isn't tuned to a specific processor. */
682 { "mips32", PROCESSOR_4KC
, 32, PTF_AVOID_BRANCHLIKELY
},
683 { "mips32r2", PROCESSOR_M4K
, 33, PTF_AVOID_BRANCHLIKELY
},
684 { "mips64", PROCESSOR_5KC
, 64, PTF_AVOID_BRANCHLIKELY
},
685 /* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
686 { "mips64r2", PROCESSOR_5KC
, 65, PTF_AVOID_BRANCHLIKELY
},
688 /* MIPS I processors. */
689 { "r3000", PROCESSOR_R3000
, 1, 0 },
690 { "r2000", PROCESSOR_R3000
, 1, 0 },
691 { "r3900", PROCESSOR_R3900
, 1, 0 },
693 /* MIPS II processors. */
694 { "r6000", PROCESSOR_R6000
, 2, 0 },
696 /* MIPS III processors. */
697 { "r4000", PROCESSOR_R4000
, 3, 0 },
698 { "vr4100", PROCESSOR_R4100
, 3, 0 },
699 { "vr4111", PROCESSOR_R4111
, 3, 0 },
700 { "vr4120", PROCESSOR_R4120
, 3, 0 },
701 { "vr4130", PROCESSOR_R4130
, 3, 0 },
702 { "vr4300", PROCESSOR_R4300
, 3, 0 },
703 { "r4400", PROCESSOR_R4000
, 3, 0 },
704 { "r4600", PROCESSOR_R4600
, 3, 0 },
705 { "orion", PROCESSOR_R4600
, 3, 0 },
706 { "r4650", PROCESSOR_R4650
, 3, 0 },
707 /* ST Loongson 2E/2F processors. */
708 { "loongson2e", PROCESSOR_LOONGSON_2E
, 3, PTF_AVOID_BRANCHLIKELY
},
709 { "loongson2f", PROCESSOR_LOONGSON_2F
, 3, PTF_AVOID_BRANCHLIKELY
},
711 /* MIPS IV processors. */
712 { "r8000", PROCESSOR_R8000
, 4, 0 },
713 { "r10000", PROCESSOR_R10000
, 4, 0 },
714 { "r12000", PROCESSOR_R10000
, 4, 0 },
715 { "r14000", PROCESSOR_R10000
, 4, 0 },
716 { "r16000", PROCESSOR_R10000
, 4, 0 },
717 { "vr5000", PROCESSOR_R5000
, 4, 0 },
718 { "vr5400", PROCESSOR_R5400
, 4, 0 },
719 { "vr5500", PROCESSOR_R5500
, 4, PTF_AVOID_BRANCHLIKELY
},
720 { "rm7000", PROCESSOR_R7000
, 4, 0 },
721 { "rm9000", PROCESSOR_R9000
, 4, 0 },
723 /* MIPS32 processors. */
724 { "4kc", PROCESSOR_4KC
, 32, 0 },
725 { "4km", PROCESSOR_4KC
, 32, 0 },
726 { "4kp", PROCESSOR_4KP
, 32, 0 },
727 { "4ksc", PROCESSOR_4KC
, 32, 0 },
729 /* MIPS32 Release 2 processors. */
730 { "m4k", PROCESSOR_M4K
, 33, 0 },
731 { "4kec", PROCESSOR_4KC
, 33, 0 },
732 { "4kem", PROCESSOR_4KC
, 33, 0 },
733 { "4kep", PROCESSOR_4KP
, 33, 0 },
734 { "4ksd", PROCESSOR_4KC
, 33, 0 },
736 { "24kc", PROCESSOR_24KC
, 33, 0 },
737 { "24kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
738 { "24kf", PROCESSOR_24KF2_1
, 33, 0 },
739 { "24kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
740 { "24kfx", PROCESSOR_24KF1_1
, 33, 0 },
741 { "24kx", PROCESSOR_24KF1_1
, 33, 0 },
743 { "24kec", PROCESSOR_24KC
, 33, 0 }, /* 24K with DSP. */
744 { "24kef2_1", PROCESSOR_24KF2_1
, 33, 0 },
745 { "24kef", PROCESSOR_24KF2_1
, 33, 0 },
746 { "24kef1_1", PROCESSOR_24KF1_1
, 33, 0 },
747 { "24kefx", PROCESSOR_24KF1_1
, 33, 0 },
748 { "24kex", PROCESSOR_24KF1_1
, 33, 0 },
750 { "34kc", PROCESSOR_24KC
, 33, 0 }, /* 34K with MT/DSP. */
751 { "34kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
752 { "34kf", PROCESSOR_24KF2_1
, 33, 0 },
753 { "34kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
754 { "34kfx", PROCESSOR_24KF1_1
, 33, 0 },
755 { "34kx", PROCESSOR_24KF1_1
, 33, 0 },
757 { "74kc", PROCESSOR_74KC
, 33, 0 }, /* 74K with DSPr2. */
758 { "74kf2_1", PROCESSOR_74KF2_1
, 33, 0 },
759 { "74kf", PROCESSOR_74KF2_1
, 33, 0 },
760 { "74kf1_1", PROCESSOR_74KF1_1
, 33, 0 },
761 { "74kfx", PROCESSOR_74KF1_1
, 33, 0 },
762 { "74kx", PROCESSOR_74KF1_1
, 33, 0 },
763 { "74kf3_2", PROCESSOR_74KF3_2
, 33, 0 },
765 { "1004kc", PROCESSOR_24KC
, 33, 0 }, /* 1004K with MT/DSP. */
766 { "1004kf2_1", PROCESSOR_24KF2_1
, 33, 0 },
767 { "1004kf", PROCESSOR_24KF2_1
, 33, 0 },
768 { "1004kf1_1", PROCESSOR_24KF1_1
, 33, 0 },
770 /* MIPS64 processors. */
771 { "5kc", PROCESSOR_5KC
, 64, 0 },
772 { "5kf", PROCESSOR_5KF
, 64, 0 },
773 { "20kc", PROCESSOR_20KC
, 64, PTF_AVOID_BRANCHLIKELY
},
774 { "sb1", PROCESSOR_SB1
, 64, PTF_AVOID_BRANCHLIKELY
},
775 { "sb1a", PROCESSOR_SB1A
, 64, PTF_AVOID_BRANCHLIKELY
},
776 { "sr71000", PROCESSOR_SR71000
, 64, PTF_AVOID_BRANCHLIKELY
},
777 { "xlr", PROCESSOR_XLR
, 64, 0 },
778 { "loongson3a", PROCESSOR_LOONGSON_3A
, 64, PTF_AVOID_BRANCHLIKELY
},
780 /* MIPS64 Release 2 processors. */
781 { "octeon", PROCESSOR_OCTEON
, 65, PTF_AVOID_BRANCHLIKELY
}
784 /* Default costs. If these are used for a processor we should look
785 up the actual costs. */
786 #define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \
787 COSTS_N_INSNS (7), /* fp_mult_sf */ \
788 COSTS_N_INSNS (8), /* fp_mult_df */ \
789 COSTS_N_INSNS (23), /* fp_div_sf */ \
790 COSTS_N_INSNS (36), /* fp_div_df */ \
791 COSTS_N_INSNS (10), /* int_mult_si */ \
792 COSTS_N_INSNS (10), /* int_mult_di */ \
793 COSTS_N_INSNS (69), /* int_div_si */ \
794 COSTS_N_INSNS (69), /* int_div_di */ \
795 2, /* branch_cost */ \
796 4 /* memory_latency */
798 /* Floating-point costs for processors without an FPU. Just assume that
799 all floating-point libcalls are very expensive. */
800 #define SOFT_FP_COSTS COSTS_N_INSNS (256), /* fp_add */ \
801 COSTS_N_INSNS (256), /* fp_mult_sf */ \
802 COSTS_N_INSNS (256), /* fp_mult_df */ \
803 COSTS_N_INSNS (256), /* fp_div_sf */ \
804 COSTS_N_INSNS (256) /* fp_div_df */
806 /* Costs to use when optimizing for size. */
807 static const struct mips_rtx_cost_data mips_rtx_cost_optimize_size
= {
808 COSTS_N_INSNS (1), /* fp_add */
809 COSTS_N_INSNS (1), /* fp_mult_sf */
810 COSTS_N_INSNS (1), /* fp_mult_df */
811 COSTS_N_INSNS (1), /* fp_div_sf */
812 COSTS_N_INSNS (1), /* fp_div_df */
813 COSTS_N_INSNS (1), /* int_mult_si */
814 COSTS_N_INSNS (1), /* int_mult_di */
815 COSTS_N_INSNS (1), /* int_div_si */
816 COSTS_N_INSNS (1), /* int_div_di */
818 4 /* memory_latency */
821 /* Costs to use when optimizing for speed, indexed by processor. */
822 static const struct mips_rtx_cost_data
823 mips_rtx_cost_data
[NUM_PROCESSOR_VALUES
] = {
825 COSTS_N_INSNS (2), /* fp_add */
826 COSTS_N_INSNS (4), /* fp_mult_sf */
827 COSTS_N_INSNS (5), /* fp_mult_df */
828 COSTS_N_INSNS (12), /* fp_div_sf */
829 COSTS_N_INSNS (19), /* fp_div_df */
830 COSTS_N_INSNS (12), /* int_mult_si */
831 COSTS_N_INSNS (12), /* int_mult_di */
832 COSTS_N_INSNS (35), /* int_div_si */
833 COSTS_N_INSNS (35), /* int_div_di */
835 4 /* memory_latency */
839 COSTS_N_INSNS (6), /* int_mult_si */
840 COSTS_N_INSNS (6), /* int_mult_di */
841 COSTS_N_INSNS (36), /* int_div_si */
842 COSTS_N_INSNS (36), /* int_div_di */
844 4 /* memory_latency */
848 COSTS_N_INSNS (36), /* int_mult_si */
849 COSTS_N_INSNS (36), /* int_mult_di */
850 COSTS_N_INSNS (37), /* int_div_si */
851 COSTS_N_INSNS (37), /* int_div_di */
853 4 /* memory_latency */
857 COSTS_N_INSNS (4), /* int_mult_si */
858 COSTS_N_INSNS (11), /* int_mult_di */
859 COSTS_N_INSNS (36), /* int_div_si */
860 COSTS_N_INSNS (68), /* int_div_di */
862 4 /* memory_latency */
865 COSTS_N_INSNS (4), /* fp_add */
866 COSTS_N_INSNS (4), /* fp_mult_sf */
867 COSTS_N_INSNS (5), /* fp_mult_df */
868 COSTS_N_INSNS (17), /* fp_div_sf */
869 COSTS_N_INSNS (32), /* fp_div_df */
870 COSTS_N_INSNS (4), /* int_mult_si */
871 COSTS_N_INSNS (11), /* int_mult_di */
872 COSTS_N_INSNS (36), /* int_div_si */
873 COSTS_N_INSNS (68), /* int_div_di */
875 4 /* memory_latency */
878 COSTS_N_INSNS (4), /* fp_add */
879 COSTS_N_INSNS (4), /* fp_mult_sf */
880 COSTS_N_INSNS (5), /* fp_mult_df */
881 COSTS_N_INSNS (17), /* fp_div_sf */
882 COSTS_N_INSNS (32), /* fp_div_df */
883 COSTS_N_INSNS (4), /* int_mult_si */
884 COSTS_N_INSNS (7), /* int_mult_di */
885 COSTS_N_INSNS (42), /* int_div_si */
886 COSTS_N_INSNS (72), /* int_div_di */
888 4 /* memory_latency */
892 COSTS_N_INSNS (5), /* int_mult_si */
893 COSTS_N_INSNS (5), /* int_mult_di */
894 COSTS_N_INSNS (41), /* int_div_si */
895 COSTS_N_INSNS (41), /* int_div_di */
897 4 /* memory_latency */
900 COSTS_N_INSNS (8), /* fp_add */
901 COSTS_N_INSNS (8), /* fp_mult_sf */
902 COSTS_N_INSNS (10), /* fp_mult_df */
903 COSTS_N_INSNS (34), /* fp_div_sf */
904 COSTS_N_INSNS (64), /* fp_div_df */
905 COSTS_N_INSNS (5), /* int_mult_si */
906 COSTS_N_INSNS (5), /* int_mult_di */
907 COSTS_N_INSNS (41), /* int_div_si */
908 COSTS_N_INSNS (41), /* int_div_di */
910 4 /* memory_latency */
913 COSTS_N_INSNS (4), /* fp_add */
914 COSTS_N_INSNS (4), /* fp_mult_sf */
915 COSTS_N_INSNS (5), /* fp_mult_df */
916 COSTS_N_INSNS (17), /* fp_div_sf */
917 COSTS_N_INSNS (32), /* fp_div_df */
918 COSTS_N_INSNS (5), /* int_mult_si */
919 COSTS_N_INSNS (5), /* int_mult_di */
920 COSTS_N_INSNS (41), /* int_div_si */
921 COSTS_N_INSNS (41), /* int_div_di */
923 4 /* memory_latency */
927 COSTS_N_INSNS (5), /* int_mult_si */
928 COSTS_N_INSNS (5), /* int_mult_di */
929 COSTS_N_INSNS (41), /* int_div_si */
930 COSTS_N_INSNS (41), /* int_div_di */
932 4 /* memory_latency */
935 COSTS_N_INSNS (8), /* fp_add */
936 COSTS_N_INSNS (8), /* fp_mult_sf */
937 COSTS_N_INSNS (10), /* fp_mult_df */
938 COSTS_N_INSNS (34), /* fp_div_sf */
939 COSTS_N_INSNS (64), /* fp_div_df */
940 COSTS_N_INSNS (5), /* int_mult_si */
941 COSTS_N_INSNS (5), /* int_mult_di */
942 COSTS_N_INSNS (41), /* int_div_si */
943 COSTS_N_INSNS (41), /* int_div_di */
945 4 /* memory_latency */
948 COSTS_N_INSNS (4), /* fp_add */
949 COSTS_N_INSNS (4), /* fp_mult_sf */
950 COSTS_N_INSNS (5), /* fp_mult_df */
951 COSTS_N_INSNS (17), /* fp_div_sf */
952 COSTS_N_INSNS (32), /* fp_div_df */
953 COSTS_N_INSNS (5), /* int_mult_si */
954 COSTS_N_INSNS (5), /* int_mult_di */
955 COSTS_N_INSNS (41), /* int_div_si */
956 COSTS_N_INSNS (41), /* int_div_di */
958 4 /* memory_latency */
961 COSTS_N_INSNS (6), /* fp_add */
962 COSTS_N_INSNS (6), /* fp_mult_sf */
963 COSTS_N_INSNS (7), /* fp_mult_df */
964 COSTS_N_INSNS (25), /* fp_div_sf */
965 COSTS_N_INSNS (48), /* fp_div_df */
966 COSTS_N_INSNS (5), /* int_mult_si */
967 COSTS_N_INSNS (5), /* int_mult_di */
968 COSTS_N_INSNS (41), /* int_div_si */
969 COSTS_N_INSNS (41), /* int_div_di */
971 4 /* memory_latency */
988 COSTS_N_INSNS (5), /* int_mult_si */
989 COSTS_N_INSNS (5), /* int_mult_di */
990 COSTS_N_INSNS (72), /* int_div_si */
991 COSTS_N_INSNS (72), /* int_div_di */
993 4 /* memory_latency */
996 COSTS_N_INSNS (2), /* fp_add */
997 COSTS_N_INSNS (4), /* fp_mult_sf */
998 COSTS_N_INSNS (5), /* fp_mult_df */
999 COSTS_N_INSNS (12), /* fp_div_sf */
1000 COSTS_N_INSNS (19), /* fp_div_df */
1001 COSTS_N_INSNS (2), /* int_mult_si */
1002 COSTS_N_INSNS (2), /* int_mult_di */
1003 COSTS_N_INSNS (35), /* int_div_si */
1004 COSTS_N_INSNS (35), /* int_div_di */
1005 1, /* branch_cost */
1006 4 /* memory_latency */
1009 COSTS_N_INSNS (3), /* fp_add */
1010 COSTS_N_INSNS (5), /* fp_mult_sf */
1011 COSTS_N_INSNS (6), /* fp_mult_df */
1012 COSTS_N_INSNS (15), /* fp_div_sf */
1013 COSTS_N_INSNS (16), /* fp_div_df */
1014 COSTS_N_INSNS (17), /* int_mult_si */
1015 COSTS_N_INSNS (17), /* int_mult_di */
1016 COSTS_N_INSNS (38), /* int_div_si */
1017 COSTS_N_INSNS (38), /* int_div_di */
1018 2, /* branch_cost */
1019 6 /* memory_latency */
1022 COSTS_N_INSNS (6), /* fp_add */
1023 COSTS_N_INSNS (7), /* fp_mult_sf */
1024 COSTS_N_INSNS (8), /* fp_mult_df */
1025 COSTS_N_INSNS (23), /* fp_div_sf */
1026 COSTS_N_INSNS (36), /* fp_div_df */
1027 COSTS_N_INSNS (10), /* int_mult_si */
1028 COSTS_N_INSNS (10), /* int_mult_di */
1029 COSTS_N_INSNS (69), /* int_div_si */
1030 COSTS_N_INSNS (69), /* int_div_di */
1031 2, /* branch_cost */
1032 6 /* memory_latency */
1044 /* The only costs that appear to be updated here are
1045 integer multiplication. */
1047 COSTS_N_INSNS (4), /* int_mult_si */
1048 COSTS_N_INSNS (6), /* int_mult_di */
1049 COSTS_N_INSNS (69), /* int_div_si */
1050 COSTS_N_INSNS (69), /* int_div_di */
1051 1, /* branch_cost */
1052 4 /* memory_latency */
1064 COSTS_N_INSNS (6), /* fp_add */
1065 COSTS_N_INSNS (4), /* fp_mult_sf */
1066 COSTS_N_INSNS (5), /* fp_mult_df */
1067 COSTS_N_INSNS (23), /* fp_div_sf */
1068 COSTS_N_INSNS (36), /* fp_div_df */
1069 COSTS_N_INSNS (5), /* int_mult_si */
1070 COSTS_N_INSNS (5), /* int_mult_di */
1071 COSTS_N_INSNS (36), /* int_div_si */
1072 COSTS_N_INSNS (36), /* int_div_di */
1073 1, /* branch_cost */
1074 4 /* memory_latency */
1077 COSTS_N_INSNS (6), /* fp_add */
1078 COSTS_N_INSNS (5), /* fp_mult_sf */
1079 COSTS_N_INSNS (6), /* fp_mult_df */
1080 COSTS_N_INSNS (30), /* fp_div_sf */
1081 COSTS_N_INSNS (59), /* fp_div_df */
1082 COSTS_N_INSNS (3), /* int_mult_si */
1083 COSTS_N_INSNS (4), /* int_mult_di */
1084 COSTS_N_INSNS (42), /* int_div_si */
1085 COSTS_N_INSNS (74), /* int_div_di */
1086 1, /* branch_cost */
1087 4 /* memory_latency */
1090 COSTS_N_INSNS (6), /* fp_add */
1091 COSTS_N_INSNS (5), /* fp_mult_sf */
1092 COSTS_N_INSNS (6), /* fp_mult_df */
1093 COSTS_N_INSNS (30), /* fp_div_sf */
1094 COSTS_N_INSNS (59), /* fp_div_df */
1095 COSTS_N_INSNS (5), /* int_mult_si */
1096 COSTS_N_INSNS (9), /* int_mult_di */
1097 COSTS_N_INSNS (42), /* int_div_si */
1098 COSTS_N_INSNS (74), /* int_div_di */
1099 1, /* branch_cost */
1100 4 /* memory_latency */
1103 /* The only costs that are changed here are
1104 integer multiplication. */
1105 COSTS_N_INSNS (6), /* fp_add */
1106 COSTS_N_INSNS (7), /* fp_mult_sf */
1107 COSTS_N_INSNS (8), /* fp_mult_df */
1108 COSTS_N_INSNS (23), /* fp_div_sf */
1109 COSTS_N_INSNS (36), /* fp_div_df */
1110 COSTS_N_INSNS (5), /* int_mult_si */
1111 COSTS_N_INSNS (9), /* int_mult_di */
1112 COSTS_N_INSNS (69), /* int_div_si */
1113 COSTS_N_INSNS (69), /* int_div_di */
1114 1, /* branch_cost */
1115 4 /* memory_latency */
1121 /* The only costs that are changed here are
1122 integer multiplication. */
1123 COSTS_N_INSNS (6), /* fp_add */
1124 COSTS_N_INSNS (7), /* fp_mult_sf */
1125 COSTS_N_INSNS (8), /* fp_mult_df */
1126 COSTS_N_INSNS (23), /* fp_div_sf */
1127 COSTS_N_INSNS (36), /* fp_div_df */
1128 COSTS_N_INSNS (3), /* int_mult_si */
1129 COSTS_N_INSNS (8), /* int_mult_di */
1130 COSTS_N_INSNS (69), /* int_div_si */
1131 COSTS_N_INSNS (69), /* int_div_di */
1132 1, /* branch_cost */
1133 4 /* memory_latency */
1136 COSTS_N_INSNS (2), /* fp_add */
1137 COSTS_N_INSNS (2), /* fp_mult_sf */
1138 COSTS_N_INSNS (2), /* fp_mult_df */
1139 COSTS_N_INSNS (12), /* fp_div_sf */
1140 COSTS_N_INSNS (19), /* fp_div_df */
1141 COSTS_N_INSNS (5), /* int_mult_si */
1142 COSTS_N_INSNS (9), /* int_mult_di */
1143 COSTS_N_INSNS (34), /* int_div_si */
1144 COSTS_N_INSNS (66), /* int_div_di */
1145 1, /* branch_cost */
1146 4 /* memory_latency */
1149 /* These costs are the same as the SB-1A below. */
1150 COSTS_N_INSNS (4), /* fp_add */
1151 COSTS_N_INSNS (4), /* fp_mult_sf */
1152 COSTS_N_INSNS (4), /* fp_mult_df */
1153 COSTS_N_INSNS (24), /* fp_div_sf */
1154 COSTS_N_INSNS (32), /* fp_div_df */
1155 COSTS_N_INSNS (3), /* int_mult_si */
1156 COSTS_N_INSNS (4), /* int_mult_di */
1157 COSTS_N_INSNS (36), /* int_div_si */
1158 COSTS_N_INSNS (68), /* int_div_di */
1159 1, /* branch_cost */
1160 4 /* memory_latency */
1163 /* These costs are the same as the SB-1 above. */
1164 COSTS_N_INSNS (4), /* fp_add */
1165 COSTS_N_INSNS (4), /* fp_mult_sf */
1166 COSTS_N_INSNS (4), /* fp_mult_df */
1167 COSTS_N_INSNS (24), /* fp_div_sf */
1168 COSTS_N_INSNS (32), /* fp_div_df */
1169 COSTS_N_INSNS (3), /* int_mult_si */
1170 COSTS_N_INSNS (4), /* int_mult_di */
1171 COSTS_N_INSNS (36), /* int_div_si */
1172 COSTS_N_INSNS (68), /* int_div_di */
1173 1, /* branch_cost */
1174 4 /* memory_latency */
1181 COSTS_N_INSNS (8), /* int_mult_si */
1182 COSTS_N_INSNS (8), /* int_mult_di */
1183 COSTS_N_INSNS (72), /* int_div_si */
1184 COSTS_N_INSNS (72), /* int_div_di */
1185 1, /* branch_cost */
1186 4 /* memory_latency */
1190 static rtx
mips_find_pic_call_symbol (rtx
, rtx
);
1191 static int mips_register_move_cost (enum machine_mode
, reg_class_t
,
1193 static unsigned int mips_function_arg_boundary (enum machine_mode
, const_tree
);
1195 /* This hash table keeps track of implicit "mips16" and "nomips16" attributes
1196 for -mflip_mips16. It maps decl names onto a boolean mode setting. */
1197 struct GTY (()) mflip_mips16_entry
{
1201 static GTY ((param_is (struct mflip_mips16_entry
))) htab_t mflip_mips16_htab
;
1203 /* Hash table callbacks for mflip_mips16_htab. */
1206 mflip_mips16_htab_hash (const void *entry
)
1208 return htab_hash_string (((const struct mflip_mips16_entry
*) entry
)->name
);
1212 mflip_mips16_htab_eq (const void *entry
, const void *name
)
1214 return strcmp (((const struct mflip_mips16_entry
*) entry
)->name
,
1215 (const char *) name
) == 0;
1218 /* True if -mflip-mips16 should next add an attribute for the default MIPS16
1219 mode, false if it should next add an attribute for the opposite mode. */
1220 static GTY(()) bool mips16_flipper
;
1222 /* DECL is a function that needs a default "mips16" or "nomips16" attribute
1223 for -mflip-mips16. Return true if it should use "mips16" and false if
1224 it should use "nomips16". */
1227 mflip_mips16_use_mips16_p (tree decl
)
1229 struct mflip_mips16_entry
*entry
;
1234 /* Use the opposite of the command-line setting for anonymous decls. */
1235 if (!DECL_NAME (decl
))
1236 return !mips_base_mips16
;
1238 if (!mflip_mips16_htab
)
1239 mflip_mips16_htab
= htab_create_ggc (37, mflip_mips16_htab_hash
,
1240 mflip_mips16_htab_eq
, NULL
);
1242 name
= IDENTIFIER_POINTER (DECL_NAME (decl
));
1243 hash
= htab_hash_string (name
);
1244 slot
= htab_find_slot_with_hash (mflip_mips16_htab
, name
, hash
, INSERT
);
1245 entry
= (struct mflip_mips16_entry
*) *slot
;
1248 mips16_flipper
= !mips16_flipper
;
1249 entry
= ggc_alloc_mflip_mips16_entry ();
1251 entry
->mips16_p
= mips16_flipper
? !mips_base_mips16
: mips_base_mips16
;
1254 return entry
->mips16_p
;
1257 /* Predicates to test for presence of "near" and "far"/"long_call"
1258 attributes on the given TYPE. */
1261 mips_near_type_p (const_tree type
)
1263 return lookup_attribute ("near", TYPE_ATTRIBUTES (type
)) != NULL
;
1267 mips_far_type_p (const_tree type
)
1269 return (lookup_attribute ("long_call", TYPE_ATTRIBUTES (type
)) != NULL
1270 || lookup_attribute ("far", TYPE_ATTRIBUTES (type
)) != NULL
);
1273 /* Similar predicates for "mips16"/"nomips16" function attributes. */
1276 mips_mips16_decl_p (const_tree decl
)
1278 return lookup_attribute ("mips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1282 mips_nomips16_decl_p (const_tree decl
)
1284 return lookup_attribute ("nomips16", DECL_ATTRIBUTES (decl
)) != NULL
;
1287 /* Check if the interrupt attribute is set for a function. */
1290 mips_interrupt_type_p (tree type
)
1292 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type
)) != NULL
;
1295 /* Check if the attribute to use shadow register set is set for a function. */
1298 mips_use_shadow_register_set_p (tree type
)
1300 return lookup_attribute ("use_shadow_register_set",
1301 TYPE_ATTRIBUTES (type
)) != NULL
;
1304 /* Check if the attribute to keep interrupts masked is set for a function. */
1307 mips_keep_interrupts_masked_p (tree type
)
1309 return lookup_attribute ("keep_interrupts_masked",
1310 TYPE_ATTRIBUTES (type
)) != NULL
;
1313 /* Check if the attribute to use debug exception return is set for
1317 mips_use_debug_exception_return_p (tree type
)
1319 return lookup_attribute ("use_debug_exception_return",
1320 TYPE_ATTRIBUTES (type
)) != NULL
;
1323 /* Return true if function DECL is a MIPS16 function. Return the ambient
1324 setting if DECL is null. */
1327 mips_use_mips16_mode_p (tree decl
)
1331 /* Nested functions must use the same frame pointer as their
1332 parent and must therefore use the same ISA mode. */
1333 tree parent
= decl_function_context (decl
);
1336 if (mips_mips16_decl_p (decl
))
1338 if (mips_nomips16_decl_p (decl
))
1341 return mips_base_mips16
;
1344 /* Implement TARGET_COMP_TYPE_ATTRIBUTES. */
1347 mips_comp_type_attributes (const_tree type1
, const_tree type2
)
1349 /* Disallow mixed near/far attributes. */
1350 if (mips_far_type_p (type1
) && mips_near_type_p (type2
))
1352 if (mips_near_type_p (type1
) && mips_far_type_p (type2
))
1357 /* Implement TARGET_INSERT_ATTRIBUTES. */
1360 mips_insert_attributes (tree decl
, tree
*attributes
)
1363 bool mips16_p
, nomips16_p
;
1365 /* Check for "mips16" and "nomips16" attributes. */
1366 mips16_p
= lookup_attribute ("mips16", *attributes
) != NULL
;
1367 nomips16_p
= lookup_attribute ("nomips16", *attributes
) != NULL
;
1368 if (TREE_CODE (decl
) != FUNCTION_DECL
)
1371 error ("%qs attribute only applies to functions", "mips16");
1373 error ("%qs attribute only applies to functions", "nomips16");
1377 mips16_p
|= mips_mips16_decl_p (decl
);
1378 nomips16_p
|= mips_nomips16_decl_p (decl
);
1379 if (mips16_p
|| nomips16_p
)
1381 /* DECL cannot be simultaneously "mips16" and "nomips16". */
1382 if (mips16_p
&& nomips16_p
)
1383 error ("%qE cannot have both %<mips16%> and "
1384 "%<nomips16%> attributes",
1387 else if (TARGET_FLIP_MIPS16
&& !DECL_ARTIFICIAL (decl
))
1389 /* Implement -mflip-mips16. If DECL has neither a "nomips16" nor a
1390 "mips16" attribute, arbitrarily pick one. We must pick the same
1391 setting for duplicate declarations of a function. */
1392 name
= mflip_mips16_use_mips16_p (decl
) ? "mips16" : "nomips16";
1393 *attributes
= tree_cons (get_identifier (name
), NULL
, *attributes
);
1398 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
1401 mips_merge_decl_attributes (tree olddecl
, tree newdecl
)
1403 /* The decls' "mips16" and "nomips16" attributes must match exactly. */
1404 if (mips_mips16_decl_p (olddecl
) != mips_mips16_decl_p (newdecl
))
1405 error ("%qE redeclared with conflicting %qs attributes",
1406 DECL_NAME (newdecl
), "mips16");
1407 if (mips_nomips16_decl_p (olddecl
) != mips_nomips16_decl_p (newdecl
))
1408 error ("%qE redeclared with conflicting %qs attributes",
1409 DECL_NAME (newdecl
), "nomips16");
1411 return merge_attributes (DECL_ATTRIBUTES (olddecl
),
1412 DECL_ATTRIBUTES (newdecl
));
1415 /* If X is a PLUS of a CONST_INT, return the two terms in *BASE_PTR
1416 and *OFFSET_PTR. Return X in *BASE_PTR and 0 in *OFFSET_PTR otherwise. */
1419 mips_split_plus (rtx x
, rtx
*base_ptr
, HOST_WIDE_INT
*offset_ptr
)
1421 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
1423 *base_ptr
= XEXP (x
, 0);
1424 *offset_ptr
= INTVAL (XEXP (x
, 1));
1433 static unsigned int mips_build_integer (struct mips_integer_op
*,
1434 unsigned HOST_WIDE_INT
);
1436 /* A subroutine of mips_build_integer, with the same interface.
1437 Assume that the final action in the sequence should be a left shift. */
1440 mips_build_shift (struct mips_integer_op
*codes
, HOST_WIDE_INT value
)
1442 unsigned int i
, shift
;
1444 /* Shift VALUE right until its lowest bit is set. Shift arithmetically
1445 since signed numbers are easier to load than unsigned ones. */
1447 while ((value
& 1) == 0)
1448 value
/= 2, shift
++;
1450 i
= mips_build_integer (codes
, value
);
1451 codes
[i
].code
= ASHIFT
;
1452 codes
[i
].value
= shift
;
1456 /* As for mips_build_shift, but assume that the final action will be
1457 an IOR or PLUS operation. */
1460 mips_build_lower (struct mips_integer_op
*codes
, unsigned HOST_WIDE_INT value
)
1462 unsigned HOST_WIDE_INT high
;
1465 high
= value
& ~(unsigned HOST_WIDE_INT
) 0xffff;
1466 if (!LUI_OPERAND (high
) && (value
& 0x18000) == 0x18000)
1468 /* The constant is too complex to load with a simple LUI/ORI pair,
1469 so we want to give the recursive call as many trailing zeros as
1470 possible. In this case, we know bit 16 is set and that the
1471 low 16 bits form a negative number. If we subtract that number
1472 from VALUE, we will clear at least the lowest 17 bits, maybe more. */
1473 i
= mips_build_integer (codes
, CONST_HIGH_PART (value
));
1474 codes
[i
].code
= PLUS
;
1475 codes
[i
].value
= CONST_LOW_PART (value
);
1479 /* Either this is a simple LUI/ORI pair, or clearing the lowest 16
1480 bits gives a value with at least 17 trailing zeros. */
1481 i
= mips_build_integer (codes
, high
);
1482 codes
[i
].code
= IOR
;
1483 codes
[i
].value
= value
& 0xffff;
1488 /* Fill CODES with a sequence of rtl operations to load VALUE.
1489 Return the number of operations needed. */
1492 mips_build_integer (struct mips_integer_op
*codes
,
1493 unsigned HOST_WIDE_INT value
)
1495 if (SMALL_OPERAND (value
)
1496 || SMALL_OPERAND_UNSIGNED (value
)
1497 || LUI_OPERAND (value
))
1499 /* The value can be loaded with a single instruction. */
1500 codes
[0].code
= UNKNOWN
;
1501 codes
[0].value
= value
;
1504 else if ((value
& 1) != 0 || LUI_OPERAND (CONST_HIGH_PART (value
)))
1506 /* Either the constant is a simple LUI/ORI combination or its
1507 lowest bit is set. We don't want to shift in this case. */
1508 return mips_build_lower (codes
, value
);
1510 else if ((value
& 0xffff) == 0)
1512 /* The constant will need at least three actions. The lowest
1513 16 bits are clear, so the final action will be a shift. */
1514 return mips_build_shift (codes
, value
);
1518 /* The final action could be a shift, add or inclusive OR.
1519 Rather than use a complex condition to select the best
1520 approach, try both mips_build_shift and mips_build_lower
1521 and pick the one that gives the shortest sequence.
1522 Note that this case is only used once per constant. */
1523 struct mips_integer_op alt_codes
[MIPS_MAX_INTEGER_OPS
];
1524 unsigned int cost
, alt_cost
;
1526 cost
= mips_build_shift (codes
, value
);
1527 alt_cost
= mips_build_lower (alt_codes
, value
);
1528 if (alt_cost
< cost
)
1530 memcpy (codes
, alt_codes
, alt_cost
* sizeof (codes
[0]));
1537 /* Return true if symbols of type TYPE require a GOT access. */
1540 mips_got_symbol_type_p (enum mips_symbol_type type
)
1544 case SYMBOL_GOT_PAGE_OFST
:
1545 case SYMBOL_GOT_DISP
:
1553 /* Return true if X is a thread-local symbol. */
1556 mips_tls_symbol_p (rtx x
)
1558 return GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
) != 0;
1561 /* Return true if SYMBOL_REF X is associated with a global symbol
1562 (in the STB_GLOBAL sense). */
1565 mips_global_symbol_p (const_rtx x
)
1567 const_tree decl
= SYMBOL_REF_DECL (x
);
1570 return !SYMBOL_REF_LOCAL_P (x
) || SYMBOL_REF_EXTERNAL_P (x
);
1572 /* Weakref symbols are not TREE_PUBLIC, but their targets are global
1573 or weak symbols. Relocations in the object file will be against
1574 the target symbol, so it's that symbol's binding that matters here. */
1575 return DECL_P (decl
) && (TREE_PUBLIC (decl
) || DECL_WEAK (decl
));
1578 /* Return true if function X is a libgcc MIPS16 stub function. */
1581 mips16_stub_function_p (const_rtx x
)
1583 return (GET_CODE (x
) == SYMBOL_REF
1584 && strncmp (XSTR (x
, 0), "__mips16_", 9) == 0);
1587 /* Return true if function X is a locally-defined and locally-binding
1591 mips16_local_function_p (const_rtx x
)
1593 return (GET_CODE (x
) == SYMBOL_REF
1594 && SYMBOL_REF_LOCAL_P (x
)
1595 && !SYMBOL_REF_EXTERNAL_P (x
)
1596 && mips_use_mips16_mode_p (SYMBOL_REF_DECL (x
)));
1599 /* Return true if SYMBOL_REF X binds locally. */
1602 mips_symbol_binds_local_p (const_rtx x
)
1604 return (SYMBOL_REF_DECL (x
)
1605 ? targetm
.binds_local_p (SYMBOL_REF_DECL (x
))
1606 : SYMBOL_REF_LOCAL_P (x
));
1609 /* Return true if rtx constants of mode MODE should be put into a small
1613 mips_rtx_constant_in_small_data_p (enum machine_mode mode
)
1615 return (!TARGET_EMBEDDED_DATA
1616 && TARGET_LOCAL_SDATA
1617 && GET_MODE_SIZE (mode
) <= mips_small_data_threshold
);
1620 /* Return true if X should not be moved directly into register $25.
1621 We need this because many versions of GAS will treat "la $25,foo" as
1622 part of a call sequence and so allow a global "foo" to be lazily bound. */
1625 mips_dangerous_for_la25_p (rtx x
)
1627 return (!TARGET_EXPLICIT_RELOCS
1629 && GET_CODE (x
) == SYMBOL_REF
1630 && mips_global_symbol_p (x
));
1633 /* Return true if calls to X might need $25 to be valid on entry. */
1636 mips_use_pic_fn_addr_reg_p (const_rtx x
)
1638 if (!TARGET_USE_PIC_FN_ADDR_REG
)
1641 /* MIPS16 stub functions are guaranteed not to use $25. */
1642 if (mips16_stub_function_p (x
))
1645 if (GET_CODE (x
) == SYMBOL_REF
)
1647 /* If PLTs and copy relocations are available, the static linker
1648 will make sure that $25 is valid on entry to the target function. */
1649 if (TARGET_ABICALLS_PIC0
)
1652 /* Locally-defined functions use absolute accesses to set up
1653 the global pointer. */
1654 if (TARGET_ABSOLUTE_ABICALLS
1655 && mips_symbol_binds_local_p (x
)
1656 && !SYMBOL_REF_EXTERNAL_P (x
))
1663 /* Return the method that should be used to access SYMBOL_REF or
1664 LABEL_REF X in context CONTEXT. */
1666 static enum mips_symbol_type
1667 mips_classify_symbol (const_rtx x
, enum mips_symbol_context context
)
1670 return SYMBOL_GOT_DISP
;
1672 if (GET_CODE (x
) == LABEL_REF
)
1674 /* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
1675 code and if we know that the label is in the current function's
1676 text section. LABEL_REFs are used for jump tables as well as
1677 text labels, so we must check whether jump tables live in the
1679 if (TARGET_MIPS16_SHORT_JUMP_TABLES
1680 && !LABEL_REF_NONLOCAL_P (x
))
1681 return SYMBOL_PC_RELATIVE
;
1683 if (TARGET_ABICALLS
&& !TARGET_ABSOLUTE_ABICALLS
)
1684 return SYMBOL_GOT_PAGE_OFST
;
1686 return SYMBOL_ABSOLUTE
;
1689 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1691 if (SYMBOL_REF_TLS_MODEL (x
))
1694 if (CONSTANT_POOL_ADDRESS_P (x
))
1696 if (TARGET_MIPS16_TEXT_LOADS
)
1697 return SYMBOL_PC_RELATIVE
;
1699 if (TARGET_MIPS16_PCREL_LOADS
&& context
== SYMBOL_CONTEXT_MEM
)
1700 return SYMBOL_PC_RELATIVE
;
1702 if (mips_rtx_constant_in_small_data_p (get_pool_mode (x
)))
1703 return SYMBOL_GP_RELATIVE
;
1706 /* Do not use small-data accesses for weak symbols; they may end up
1708 if (TARGET_GPOPT
&& SYMBOL_REF_SMALL_P (x
) && !SYMBOL_REF_WEAK (x
))
1709 return SYMBOL_GP_RELATIVE
;
1711 /* Don't use GOT accesses for locally-binding symbols when -mno-shared
1713 if (TARGET_ABICALLS_PIC2
1714 && !(TARGET_ABSOLUTE_ABICALLS
&& mips_symbol_binds_local_p (x
)))
1716 /* There are three cases to consider:
1718 - o32 PIC (either with or without explicit relocs)
1719 - n32/n64 PIC without explicit relocs
1720 - n32/n64 PIC with explicit relocs
1722 In the first case, both local and global accesses will use an
1723 R_MIPS_GOT16 relocation. We must correctly predict which of
1724 the two semantics (local or global) the assembler and linker
1725 will apply. The choice depends on the symbol's binding rather
1726 than its visibility.
1728 In the second case, the assembler will not use R_MIPS_GOT16
1729 relocations, but it chooses between local and global accesses
1730 in the same way as for o32 PIC.
1732 In the third case we have more freedom since both forms of
1733 access will work for any kind of symbol. However, there seems
1734 little point in doing things differently. */
1735 if (mips_global_symbol_p (x
))
1736 return SYMBOL_GOT_DISP
;
1738 return SYMBOL_GOT_PAGE_OFST
;
1741 if (TARGET_MIPS16_PCREL_LOADS
&& context
!= SYMBOL_CONTEXT_CALL
)
1742 return SYMBOL_FORCE_TO_MEM
;
1744 return SYMBOL_ABSOLUTE
;
1747 /* Classify the base of symbolic expression X, given that X appears in
1750 static enum mips_symbol_type
1751 mips_classify_symbolic_expression (rtx x
, enum mips_symbol_context context
)
1755 split_const (x
, &x
, &offset
);
1756 if (UNSPEC_ADDRESS_P (x
))
1757 return UNSPEC_ADDRESS_TYPE (x
);
1759 return mips_classify_symbol (x
, context
);
1762 /* Return true if OFFSET is within the range [0, ALIGN), where ALIGN
1763 is the alignment in bytes of SYMBOL_REF X. */
1766 mips_offset_within_alignment_p (rtx x
, HOST_WIDE_INT offset
)
1768 HOST_WIDE_INT align
;
1770 align
= SYMBOL_REF_DECL (x
) ? DECL_ALIGN_UNIT (SYMBOL_REF_DECL (x
)) : 1;
1771 return IN_RANGE (offset
, 0, align
- 1);
1774 /* Return true if X is a symbolic constant that can be used in context
1775 CONTEXT. If it is, store the type of the symbol in *SYMBOL_TYPE. */
1778 mips_symbolic_constant_p (rtx x
, enum mips_symbol_context context
,
1779 enum mips_symbol_type
*symbol_type
)
1783 split_const (x
, &x
, &offset
);
1784 if (UNSPEC_ADDRESS_P (x
))
1786 *symbol_type
= UNSPEC_ADDRESS_TYPE (x
);
1787 x
= UNSPEC_ADDRESS (x
);
1789 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1791 *symbol_type
= mips_classify_symbol (x
, context
);
1792 if (*symbol_type
== SYMBOL_TLS
)
1798 if (offset
== const0_rtx
)
1801 /* Check whether a nonzero offset is valid for the underlying
1803 switch (*symbol_type
)
1805 case SYMBOL_ABSOLUTE
:
1806 case SYMBOL_FORCE_TO_MEM
:
1807 case SYMBOL_32_HIGH
:
1808 case SYMBOL_64_HIGH
:
1811 /* If the target has 64-bit pointers and the object file only
1812 supports 32-bit symbols, the values of those symbols will be
1813 sign-extended. In this case we can't allow an arbitrary offset
1814 in case the 32-bit value X + OFFSET has a different sign from X. */
1815 if (Pmode
== DImode
&& !ABI_HAS_64BIT_SYMBOLS
)
1816 return offset_within_block_p (x
, INTVAL (offset
));
1818 /* In other cases the relocations can handle any offset. */
1821 case SYMBOL_PC_RELATIVE
:
1822 /* Allow constant pool references to be converted to LABEL+CONSTANT.
1823 In this case, we no longer have access to the underlying constant,
1824 but the original symbol-based access was known to be valid. */
1825 if (GET_CODE (x
) == LABEL_REF
)
1830 case SYMBOL_GP_RELATIVE
:
1831 /* Make sure that the offset refers to something within the
1832 same object block. This should guarantee that the final
1833 PC- or GP-relative offset is within the 16-bit limit. */
1834 return offset_within_block_p (x
, INTVAL (offset
));
1836 case SYMBOL_GOT_PAGE_OFST
:
1837 case SYMBOL_GOTOFF_PAGE
:
1838 /* If the symbol is global, the GOT entry will contain the symbol's
1839 address, and we will apply a 16-bit offset after loading it.
1840 If the symbol is local, the linker should provide enough local
1841 GOT entries for a 16-bit offset, but larger offsets may lead
1843 return SMALL_INT (offset
);
1847 /* There is no carry between the HI and LO REL relocations, so the
1848 offset is only valid if we know it won't lead to such a carry. */
1849 return mips_offset_within_alignment_p (x
, INTVAL (offset
));
1851 case SYMBOL_GOT_DISP
:
1852 case SYMBOL_GOTOFF_DISP
:
1853 case SYMBOL_GOTOFF_CALL
:
1854 case SYMBOL_GOTOFF_LOADGP
:
1857 case SYMBOL_GOTTPREL
:
1865 /* Like mips_symbol_insns, but treat extended MIPS16 instructions as a
1866 single instruction. We rely on the fact that, in the worst case,
1867 all instructions involved in a MIPS16 address calculation are usually
1871 mips_symbol_insns_1 (enum mips_symbol_type type
, enum machine_mode mode
)
1875 case SYMBOL_ABSOLUTE
:
1876 /* When using 64-bit symbols, we need 5 preparatory instructions,
1879 lui $at,%highest(symbol)
1880 daddiu $at,$at,%higher(symbol)
1882 daddiu $at,$at,%hi(symbol)
1885 The final address is then $at + %lo(symbol). With 32-bit
1886 symbols we just need a preparatory LUI for normal mode and
1887 a preparatory LI and SLL for MIPS16. */
1888 return ABI_HAS_64BIT_SYMBOLS
? 6 : TARGET_MIPS16
? 3 : 2;
1890 case SYMBOL_GP_RELATIVE
:
1891 /* Treat GP-relative accesses as taking a single instruction on
1892 MIPS16 too; the copy of $gp can often be shared. */
1895 case SYMBOL_PC_RELATIVE
:
1896 /* PC-relative constants can be only be used with ADDIUPC,
1897 DADDIUPC, LWPC and LDPC. */
1898 if (mode
== MAX_MACHINE_MODE
1899 || GET_MODE_SIZE (mode
) == 4
1900 || GET_MODE_SIZE (mode
) == 8)
1903 /* The constant must be loaded using ADDIUPC or DADDIUPC first. */
1906 case SYMBOL_FORCE_TO_MEM
:
1907 /* LEAs will be converted into constant-pool references by
1909 if (mode
== MAX_MACHINE_MODE
)
1912 /* The constant must be loaded and then dereferenced. */
1915 case SYMBOL_GOT_DISP
:
1916 /* The constant will have to be loaded from the GOT before it
1917 is used in an address. */
1918 if (mode
!= MAX_MACHINE_MODE
)
1923 case SYMBOL_GOT_PAGE_OFST
:
1924 /* Unless -funit-at-a-time is in effect, we can't be sure whether the
1925 local/global classification is accurate. The worst cases are:
1927 (1) For local symbols when generating o32 or o64 code. The assembler
1933 ...and the final address will be $at + %lo(symbol).
1935 (2) For global symbols when -mxgot. The assembler will use:
1937 lui $at,%got_hi(symbol)
1940 ...and the final address will be $at + %got_lo(symbol). */
1943 case SYMBOL_GOTOFF_PAGE
:
1944 case SYMBOL_GOTOFF_DISP
:
1945 case SYMBOL_GOTOFF_CALL
:
1946 case SYMBOL_GOTOFF_LOADGP
:
1947 case SYMBOL_32_HIGH
:
1948 case SYMBOL_64_HIGH
:
1954 case SYMBOL_GOTTPREL
:
1957 /* A 16-bit constant formed by a single relocation, or a 32-bit
1958 constant formed from a high 16-bit relocation and a low 16-bit
1959 relocation. Use mips_split_p to determine which. 32-bit
1960 constants need an "lui; addiu" sequence for normal mode and
1961 an "li; sll; addiu" sequence for MIPS16 mode. */
1962 return !mips_split_p
[type
] ? 1 : TARGET_MIPS16
? 3 : 2;
1965 /* We don't treat a bare TLS symbol as a constant. */
1971 /* If MODE is MAX_MACHINE_MODE, return the number of instructions needed
1972 to load symbols of type TYPE into a register. Return 0 if the given
1973 type of symbol cannot be used as an immediate operand.
1975 Otherwise, return the number of instructions needed to load or store
1976 values of mode MODE to or from addresses of type TYPE. Return 0 if
1977 the given type of symbol is not valid in addresses.
1979 In both cases, treat extended MIPS16 instructions as two instructions. */
1982 mips_symbol_insns (enum mips_symbol_type type
, enum machine_mode mode
)
1984 return mips_symbol_insns_1 (type
, mode
) * (TARGET_MIPS16
? 2 : 1);
1987 /* A for_each_rtx callback. Stop the search if *X references a
1988 thread-local symbol. */
1991 mips_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
1993 return mips_tls_symbol_p (*x
);
1996 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1999 mips_cannot_force_const_mem (rtx x
)
2001 enum mips_symbol_type type
;
2004 /* There is no assembler syntax for expressing an address-sized
2006 if (GET_CODE (x
) == HIGH
)
2009 /* As an optimization, reject constants that mips_legitimize_move
2012 Suppose we have a multi-instruction sequence that loads constant C
2013 into register R. If R does not get allocated a hard register, and
2014 R is used in an operand that allows both registers and memory
2015 references, reload will consider forcing C into memory and using
2016 one of the instruction's memory alternatives. Returning false
2017 here will force it to use an input reload instead. */
2018 if (CONST_INT_P (x
) && LEGITIMATE_CONSTANT_P (x
))
2021 split_const (x
, &base
, &offset
);
2022 if (mips_symbolic_constant_p (base
, SYMBOL_CONTEXT_LEA
, &type
)
2023 && type
!= SYMBOL_FORCE_TO_MEM
)
2025 /* The same optimization as for CONST_INT. */
2026 if (SMALL_INT (offset
) && mips_symbol_insns (type
, MAX_MACHINE_MODE
) > 0)
2029 /* If MIPS16 constant pools live in the text section, they should
2030 not refer to anything that might need run-time relocation. */
2031 if (TARGET_MIPS16_PCREL_LOADS
&& mips_got_symbol_type_p (type
))
2035 /* TLS symbols must be computed by mips_legitimize_move. */
2036 if (for_each_rtx (&x
, &mips_tls_symbol_ref_1
, NULL
))
2042 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. We can't use blocks for
2043 constants when we're using a per-function constant pool. */
2046 mips_use_blocks_for_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2047 const_rtx x ATTRIBUTE_UNUSED
)
2049 return !TARGET_MIPS16_PCREL_LOADS
;
2052 /* Return true if register REGNO is a valid base register for mode MODE.
2053 STRICT_P is true if REG_OK_STRICT is in effect. */
2056 mips_regno_mode_ok_for_base_p (int regno
, enum machine_mode mode
,
2059 if (!HARD_REGISTER_NUM_P (regno
))
2063 regno
= reg_renumber
[regno
];
2066 /* These fake registers will be eliminated to either the stack or
2067 hard frame pointer, both of which are usually valid base registers.
2068 Reload deals with the cases where the eliminated form isn't valid. */
2069 if (regno
== ARG_POINTER_REGNUM
|| regno
== FRAME_POINTER_REGNUM
)
2072 /* In MIPS16 mode, the stack pointer can only address word and doubleword
2073 values, nothing smaller. There are two problems here:
2075 (a) Instantiating virtual registers can introduce new uses of the
2076 stack pointer. If these virtual registers are valid addresses,
2077 the stack pointer should be too.
2079 (b) Most uses of the stack pointer are not made explicit until
2080 FRAME_POINTER_REGNUM and ARG_POINTER_REGNUM have been eliminated.
2081 We don't know until that stage whether we'll be eliminating to the
2082 stack pointer (which needs the restriction) or the hard frame
2083 pointer (which doesn't).
2085 All in all, it seems more consistent to only enforce this restriction
2086 during and after reload. */
2087 if (TARGET_MIPS16
&& regno
== STACK_POINTER_REGNUM
)
2088 return !strict_p
|| GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8;
2090 return TARGET_MIPS16
? M16_REG_P (regno
) : GP_REG_P (regno
);
2093 /* Return true if X is a valid base register for mode MODE.
2094 STRICT_P is true if REG_OK_STRICT is in effect. */
2097 mips_valid_base_register_p (rtx x
, enum machine_mode mode
, bool strict_p
)
2099 if (!strict_p
&& GET_CODE (x
) == SUBREG
)
2103 && mips_regno_mode_ok_for_base_p (REGNO (x
), mode
, strict_p
));
2106 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
2107 can address a value of mode MODE. */
2110 mips_valid_offset_p (rtx x
, enum machine_mode mode
)
2112 /* Check that X is a signed 16-bit number. */
2113 if (!const_arith_operand (x
, Pmode
))
2116 /* We may need to split multiword moves, so make sure that every word
2118 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2119 && !SMALL_OPERAND (INTVAL (x
) + GET_MODE_SIZE (mode
) - UNITS_PER_WORD
))
2125 /* Return true if a LO_SUM can address a value of mode MODE when the
2126 LO_SUM symbol has type SYMBOL_TYPE. */
2129 mips_valid_lo_sum_p (enum mips_symbol_type symbol_type
, enum machine_mode mode
)
2131 /* Check that symbols of type SYMBOL_TYPE can be used to access values
2133 if (mips_symbol_insns (symbol_type
, mode
) == 0)
2136 /* Check that there is a known low-part relocation. */
2137 if (mips_lo_relocs
[symbol_type
] == NULL
)
2140 /* We may need to split multiword moves, so make sure that each word
2141 can be accessed without inducing a carry. This is mainly needed
2142 for o64, which has historically only guaranteed 64-bit alignment
2143 for 128-bit types. */
2144 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
2145 && GET_MODE_BITSIZE (mode
) > GET_MODE_ALIGNMENT (mode
))
2151 /* Return true if X is a valid address for machine mode MODE. If it is,
2152 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
2156 mips_classify_address (struct mips_address_info
*info
, rtx x
,
2157 enum machine_mode mode
, bool strict_p
)
2159 switch (GET_CODE (x
))
2163 info
->type
= ADDRESS_REG
;
2165 info
->offset
= const0_rtx
;
2166 return mips_valid_base_register_p (info
->reg
, mode
, strict_p
);
2169 info
->type
= ADDRESS_REG
;
2170 info
->reg
= XEXP (x
, 0);
2171 info
->offset
= XEXP (x
, 1);
2172 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2173 && mips_valid_offset_p (info
->offset
, mode
));
2176 info
->type
= ADDRESS_LO_SUM
;
2177 info
->reg
= XEXP (x
, 0);
2178 info
->offset
= XEXP (x
, 1);
2179 /* We have to trust the creator of the LO_SUM to do something vaguely
2180 sane. Target-independent code that creates a LO_SUM should also
2181 create and verify the matching HIGH. Target-independent code that
2182 adds an offset to a LO_SUM must prove that the offset will not
2183 induce a carry. Failure to do either of these things would be
2184 a bug, and we are not required to check for it here. The MIPS
2185 backend itself should only create LO_SUMs for valid symbolic
2186 constants, with the high part being either a HIGH or a copy
2189 = mips_classify_symbolic_expression (info
->offset
, SYMBOL_CONTEXT_MEM
);
2190 return (mips_valid_base_register_p (info
->reg
, mode
, strict_p
)
2191 && mips_valid_lo_sum_p (info
->symbol_type
, mode
));
2194 /* Small-integer addresses don't occur very often, but they
2195 are legitimate if $0 is a valid base register. */
2196 info
->type
= ADDRESS_CONST_INT
;
2197 return !TARGET_MIPS16
&& SMALL_INT (x
);
2202 info
->type
= ADDRESS_SYMBOLIC
;
2203 return (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_MEM
,
2205 && mips_symbol_insns (info
->symbol_type
, mode
) > 0
2206 && !mips_split_p
[info
->symbol_type
]);
2213 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
2216 mips_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict_p
)
2218 struct mips_address_info addr
;
2220 return mips_classify_address (&addr
, x
, mode
, strict_p
);
2223 /* Return true if X is a legitimate $sp-based address for mode MDOE. */
2226 mips_stack_address_p (rtx x
, enum machine_mode mode
)
2228 struct mips_address_info addr
;
2230 return (mips_classify_address (&addr
, x
, mode
, false)
2231 && addr
.type
== ADDRESS_REG
2232 && addr
.reg
== stack_pointer_rtx
);
2235 /* Return true if ADDR matches the pattern for the LWXS load scaled indexed
2236 address instruction. Note that such addresses are not considered
2237 legitimate in the TARGET_LEGITIMATE_ADDRESS_P sense, because their use
2238 is so restricted. */
2241 mips_lwxs_address_p (rtx addr
)
2244 && GET_CODE (addr
) == PLUS
2245 && REG_P (XEXP (addr
, 1)))
2247 rtx offset
= XEXP (addr
, 0);
2248 if (GET_CODE (offset
) == MULT
2249 && REG_P (XEXP (offset
, 0))
2250 && CONST_INT_P (XEXP (offset
, 1))
2251 && INTVAL (XEXP (offset
, 1)) == 4)
2257 /* Return true if a value at OFFSET bytes from base register BASE can be
2258 accessed using an unextended MIPS16 instruction. MODE is the mode of
2261 Usually the offset in an unextended instruction is a 5-bit field.
2262 The offset is unsigned and shifted left once for LH and SH, twice
2263 for LW and SW, and so on. An exception is LWSP and SWSP, which have
2264 an 8-bit immediate field that's shifted left twice. */
2267 mips16_unextended_reference_p (enum machine_mode mode
, rtx base
,
2268 unsigned HOST_WIDE_INT offset
)
2270 if (offset
% GET_MODE_SIZE (mode
) == 0)
2272 if (GET_MODE_SIZE (mode
) == 4 && base
== stack_pointer_rtx
)
2273 return offset
< 256U * GET_MODE_SIZE (mode
);
2274 return offset
< 32U * GET_MODE_SIZE (mode
);
2279 /* Return the number of instructions needed to load or store a value
2280 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2281 Assume that multiword moves may need to be split into word moves
2282 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2285 For MIPS16 code, count extended instructions as two instructions. */
2288 mips_address_insns (rtx x
, enum machine_mode mode
, bool might_split_p
)
2290 struct mips_address_info addr
;
2293 /* BLKmode is used for single unaligned loads and stores and should
2294 not count as a multiword mode. (GET_MODE_SIZE (BLKmode) is pretty
2295 meaningless, so we have to single it out as a special case one way
2297 if (mode
!= BLKmode
&& might_split_p
)
2298 factor
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2302 if (mips_classify_address (&addr
, x
, mode
, false))
2307 && !mips16_unextended_reference_p (mode
, addr
.reg
,
2308 UINTVAL (addr
.offset
)))
2312 case ADDRESS_LO_SUM
:
2313 return TARGET_MIPS16
? factor
* 2 : factor
;
2315 case ADDRESS_CONST_INT
:
2318 case ADDRESS_SYMBOLIC
:
2319 return factor
* mips_symbol_insns (addr
.symbol_type
, mode
);
2324 /* Return the number of instructions needed to load constant X.
2325 Return 0 if X isn't a valid constant. */
2328 mips_const_insns (rtx x
)
2330 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
2331 enum mips_symbol_type symbol_type
;
2334 switch (GET_CODE (x
))
2337 if (!mips_symbolic_constant_p (XEXP (x
, 0), SYMBOL_CONTEXT_LEA
,
2339 || !mips_split_p
[symbol_type
])
2342 /* This is simply an LUI for normal mode. It is an extended
2343 LI followed by an extended SLL for MIPS16. */
2344 return TARGET_MIPS16
? 4 : 1;
2348 /* Unsigned 8-bit constants can be loaded using an unextended
2349 LI instruction. Unsigned 16-bit constants can be loaded
2350 using an extended LI. Negative constants must be loaded
2351 using LI and then negated. */
2352 return (IN_RANGE (INTVAL (x
), 0, 255) ? 1
2353 : SMALL_OPERAND_UNSIGNED (INTVAL (x
)) ? 2
2354 : IN_RANGE (-INTVAL (x
), 0, 255) ? 2
2355 : SMALL_OPERAND_UNSIGNED (-INTVAL (x
)) ? 3
2358 return mips_build_integer (codes
, INTVAL (x
));
2362 /* Allow zeros for normal mode, where we can use $0. */
2363 return !TARGET_MIPS16
&& x
== CONST0_RTX (GET_MODE (x
)) ? 1 : 0;
2369 /* See if we can refer to X directly. */
2370 if (mips_symbolic_constant_p (x
, SYMBOL_CONTEXT_LEA
, &symbol_type
))
2371 return mips_symbol_insns (symbol_type
, MAX_MACHINE_MODE
);
2373 /* Otherwise try splitting the constant into a base and offset.
2374 If the offset is a 16-bit value, we can load the base address
2375 into a register and then use (D)ADDIU to add in the offset.
2376 If the offset is larger, we can load the base and offset
2377 into separate registers and add them together with (D)ADDU.
2378 However, the latter is only possible before reload; during
2379 and after reload, we must have the option of forcing the
2380 constant into the pool instead. */
2381 split_const (x
, &x
, &offset
);
2384 int n
= mips_const_insns (x
);
2387 if (SMALL_INT (offset
))
2389 else if (!targetm
.cannot_force_const_mem (x
))
2390 return n
+ 1 + mips_build_integer (codes
, INTVAL (offset
));
2397 return mips_symbol_insns (mips_classify_symbol (x
, SYMBOL_CONTEXT_LEA
),
2405 /* X is a doubleword constant that can be handled by splitting it into
2406 two words and loading each word separately. Return the number of
2407 instructions required to do this. */
2410 mips_split_const_insns (rtx x
)
2412 unsigned int low
, high
;
2414 low
= mips_const_insns (mips_subword (x
, false));
2415 high
= mips_const_insns (mips_subword (x
, true));
2416 gcc_assert (low
> 0 && high
> 0);
2420 /* Return the number of instructions needed to implement INSN,
2421 given that it loads from or stores to MEM. Count extended
2422 MIPS16 instructions as two instructions. */
2425 mips_load_store_insns (rtx mem
, rtx insn
)
2427 enum machine_mode mode
;
2431 gcc_assert (MEM_P (mem
));
2432 mode
= GET_MODE (mem
);
2434 /* Try to prove that INSN does not need to be split. */
2435 might_split_p
= true;
2436 if (GET_MODE_BITSIZE (mode
) == 64)
2438 set
= single_set (insn
);
2439 if (set
&& !mips_split_64bit_move_p (SET_DEST (set
), SET_SRC (set
)))
2440 might_split_p
= false;
2443 return mips_address_insns (XEXP (mem
, 0), mode
, might_split_p
);
2446 /* Return the number of instructions needed for an integer division. */
2449 mips_idiv_insns (void)
2454 if (TARGET_CHECK_ZERO_DIV
)
2456 if (GENERATE_DIVIDE_TRAPS
)
2462 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
2467 /* Emit a move from SRC to DEST. Assume that the move expanders can
2468 handle all moves if !can_create_pseudo_p (). The distinction is
2469 important because, unlike emit_move_insn, the move expanders know
2470 how to force Pmode objects into the constant pool even when the
2471 constant pool address is not itself legitimate. */
2474 mips_emit_move (rtx dest
, rtx src
)
2476 return (can_create_pseudo_p ()
2477 ? emit_move_insn (dest
, src
)
2478 : emit_move_insn_1 (dest
, src
));
2481 /* Emit an instruction of the form (set TARGET (CODE OP0)). */
2484 mips_emit_unary (enum rtx_code code
, rtx target
, rtx op0
)
2486 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2487 gen_rtx_fmt_e (code
, GET_MODE (op0
), op0
)));
2490 /* Compute (CODE OP0) and store the result in a new register of mode MODE.
2491 Return that new register. */
2494 mips_force_unary (enum machine_mode mode
, enum rtx_code code
, rtx op0
)
2498 reg
= gen_reg_rtx (mode
);
2499 mips_emit_unary (code
, reg
, op0
);
2503 /* Emit an instruction of the form (set TARGET (CODE OP0 OP1)). */
2506 mips_emit_binary (enum rtx_code code
, rtx target
, rtx op0
, rtx op1
)
2508 emit_insn (gen_rtx_SET (VOIDmode
, target
,
2509 gen_rtx_fmt_ee (code
, GET_MODE (target
), op0
, op1
)));
2512 /* Compute (CODE OP0 OP1) and store the result in a new register
2513 of mode MODE. Return that new register. */
2516 mips_force_binary (enum machine_mode mode
, enum rtx_code code
, rtx op0
, rtx op1
)
2520 reg
= gen_reg_rtx (mode
);
2521 mips_emit_binary (code
, reg
, op0
, op1
);
2525 /* Copy VALUE to a register and return that register. If new pseudos
2526 are allowed, copy it into a new register, otherwise use DEST. */
2529 mips_force_temporary (rtx dest
, rtx value
)
2531 if (can_create_pseudo_p ())
2532 return force_reg (Pmode
, value
);
2535 mips_emit_move (dest
, value
);
2540 /* Emit a call sequence with call pattern PATTERN and return the call
2541 instruction itself (which is not necessarily the last instruction
2542 emitted). ORIG_ADDR is the original, unlegitimized address,
2543 ADDR is the legitimized form, and LAZY_P is true if the call
2544 address is lazily-bound. */
2547 mips_emit_call_insn (rtx pattern
, rtx orig_addr
, rtx addr
, bool lazy_p
)
2551 insn
= emit_call_insn (pattern
);
2553 if (TARGET_MIPS16
&& mips_use_pic_fn_addr_reg_p (orig_addr
))
2555 /* MIPS16 JALRs only take MIPS16 registers. If the target
2556 function requires $25 to be valid on entry, we must copy it
2557 there separately. The move instruction can be put in the
2558 call's delay slot. */
2559 reg
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
2560 emit_insn_before (gen_move_insn (reg
, addr
), insn
);
2561 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
2565 /* Lazy-binding stubs require $gp to be valid on entry. */
2566 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
2570 /* See the comment above load_call<mode> for details. */
2571 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
),
2572 gen_rtx_REG (Pmode
, GOT_VERSION_REGNUM
));
2573 emit_insn (gen_update_got_version ());
2578 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2579 then add CONST_INT OFFSET to the result. */
2582 mips_unspec_address_offset (rtx base
, rtx offset
,
2583 enum mips_symbol_type symbol_type
)
2585 base
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, base
),
2586 UNSPEC_ADDRESS_FIRST
+ symbol_type
);
2587 if (offset
!= const0_rtx
)
2588 base
= gen_rtx_PLUS (Pmode
, base
, offset
);
2589 return gen_rtx_CONST (Pmode
, base
);
2592 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2593 type SYMBOL_TYPE. */
2596 mips_unspec_address (rtx address
, enum mips_symbol_type symbol_type
)
2600 split_const (address
, &base
, &offset
);
2601 return mips_unspec_address_offset (base
, offset
, symbol_type
);
2604 /* If OP is an UNSPEC address, return the address to which it refers,
2605 otherwise return OP itself. */
2608 mips_strip_unspec_address (rtx op
)
2612 split_const (op
, &base
, &offset
);
2613 if (UNSPEC_ADDRESS_P (base
))
2614 op
= plus_constant (UNSPEC_ADDRESS (base
), INTVAL (offset
));
2618 /* If mips_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2619 high part to BASE and return the result. Just return BASE otherwise.
2620 TEMP is as for mips_force_temporary.
2622 The returned expression can be used as the first operand to a LO_SUM. */
2625 mips_unspec_offset_high (rtx temp
, rtx base
, rtx addr
,
2626 enum mips_symbol_type symbol_type
)
2628 if (mips_split_p
[symbol_type
])
2630 addr
= gen_rtx_HIGH (Pmode
, mips_unspec_address (addr
, symbol_type
));
2631 addr
= mips_force_temporary (temp
, addr
);
2632 base
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, addr
, base
));
2637 /* Return an instruction that copies $gp into register REG. We want
2638 GCC to treat the register's value as constant, so that its value
2639 can be rematerialized on demand. */
2642 gen_load_const_gp (rtx reg
)
2644 return (Pmode
== SImode
2645 ? gen_load_const_gp_si (reg
)
2646 : gen_load_const_gp_di (reg
));
2649 /* Return a pseudo register that contains the value of $gp throughout
2650 the current function. Such registers are needed by MIPS16 functions,
2651 for which $gp itself is not a valid base register or addition operand. */
2654 mips16_gp_pseudo_reg (void)
2656 if (cfun
->machine
->mips16_gp_pseudo_rtx
== NULL_RTX
)
2660 cfun
->machine
->mips16_gp_pseudo_rtx
= gen_reg_rtx (Pmode
);
2662 push_topmost_sequence ();
2664 scan
= get_insns ();
2665 while (NEXT_INSN (scan
) && !INSN_P (NEXT_INSN (scan
)))
2666 scan
= NEXT_INSN (scan
);
2668 insn
= gen_load_const_gp (cfun
->machine
->mips16_gp_pseudo_rtx
);
2669 emit_insn_after (insn
, scan
);
2671 pop_topmost_sequence ();
2674 return cfun
->machine
->mips16_gp_pseudo_rtx
;
2677 /* Return a base register that holds pic_offset_table_rtx.
2678 TEMP, if nonnull, is a scratch Pmode base register. */
2681 mips_pic_base_register (rtx temp
)
2684 return pic_offset_table_rtx
;
2686 if (currently_expanding_to_rtl
)
2687 return mips16_gp_pseudo_reg ();
2689 if (can_create_pseudo_p ())
2690 temp
= gen_reg_rtx (Pmode
);
2693 /* The first post-reload split exposes all references to $gp
2694 (both uses and definitions). All references must remain
2695 explicit after that point.
2697 It is safe to introduce uses of $gp at any time, so for
2698 simplicity, we do that before the split too. */
2699 mips_emit_move (temp
, pic_offset_table_rtx
);
2701 emit_insn (gen_load_const_gp (temp
));
2705 /* Return the RHS of a load_call<mode> insn. */
2708 mips_unspec_call (rtx reg
, rtx symbol
)
2712 vec
= gen_rtvec (3, reg
, symbol
, gen_rtx_REG (SImode
, GOT_VERSION_REGNUM
));
2713 return gen_rtx_UNSPEC (Pmode
, vec
, UNSPEC_LOAD_CALL
);
2716 /* If SRC is the RHS of a load_call<mode> insn, return the underlying symbol
2717 reference. Return NULL_RTX otherwise. */
2720 mips_strip_unspec_call (rtx src
)
2722 if (GET_CODE (src
) == UNSPEC
&& XINT (src
, 1) == UNSPEC_LOAD_CALL
)
2723 return mips_strip_unspec_address (XVECEXP (src
, 0, 1));
2727 /* Create and return a GOT reference of type TYPE for address ADDR.
2728 TEMP, if nonnull, is a scratch Pmode base register. */
2731 mips_got_load (rtx temp
, rtx addr
, enum mips_symbol_type type
)
2733 rtx base
, high
, lo_sum_symbol
;
2735 base
= mips_pic_base_register (temp
);
2737 /* If we used the temporary register to load $gp, we can't use
2738 it for the high part as well. */
2739 if (temp
!= NULL
&& reg_overlap_mentioned_p (base
, temp
))
2742 high
= mips_unspec_offset_high (temp
, base
, addr
, type
);
2743 lo_sum_symbol
= mips_unspec_address (addr
, type
);
2745 if (type
== SYMBOL_GOTOFF_CALL
)
2746 return mips_unspec_call (high
, lo_sum_symbol
);
2748 return (Pmode
== SImode
2749 ? gen_unspec_gotsi (high
, lo_sum_symbol
)
2750 : gen_unspec_gotdi (high
, lo_sum_symbol
));
2753 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2754 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2755 constant in that context and can be split into high and low parts.
2756 If so, and if LOW_OUT is nonnull, emit the high part and store the
2757 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2759 TEMP is as for mips_force_temporary and is used to load the high
2760 part into a register.
2762 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2763 a legitimize SET_SRC for an .md pattern, otherwise the low part
2764 is guaranteed to be a legitimate address for mode MODE. */
2767 mips_split_symbol (rtx temp
, rtx addr
, enum machine_mode mode
, rtx
*low_out
)
2769 enum mips_symbol_context context
;
2770 enum mips_symbol_type symbol_type
;
2773 context
= (mode
== MAX_MACHINE_MODE
2774 ? SYMBOL_CONTEXT_LEA
2775 : SYMBOL_CONTEXT_MEM
);
2776 if (GET_CODE (addr
) == HIGH
&& context
== SYMBOL_CONTEXT_LEA
)
2778 addr
= XEXP (addr
, 0);
2779 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2780 && mips_symbol_insns (symbol_type
, mode
) > 0
2781 && mips_split_hi_p
[symbol_type
])
2784 switch (symbol_type
)
2786 case SYMBOL_GOT_PAGE_OFST
:
2787 /* The high part of a page/ofst pair is loaded from the GOT. */
2788 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_PAGE
);
2799 if (mips_symbolic_constant_p (addr
, context
, &symbol_type
)
2800 && mips_symbol_insns (symbol_type
, mode
) > 0
2801 && mips_split_p
[symbol_type
])
2804 switch (symbol_type
)
2806 case SYMBOL_GOT_DISP
:
2807 /* SYMBOL_GOT_DISP symbols are loaded from the GOT. */
2808 *low_out
= mips_got_load (temp
, addr
, SYMBOL_GOTOFF_DISP
);
2811 case SYMBOL_GP_RELATIVE
:
2812 high
= mips_pic_base_register (temp
);
2813 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2817 high
= gen_rtx_HIGH (Pmode
, copy_rtx (addr
));
2818 high
= mips_force_temporary (temp
, high
);
2819 *low_out
= gen_rtx_LO_SUM (Pmode
, high
, addr
);
2828 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2829 mips_force_temporary; it is only needed when OFFSET is not a
2833 mips_add_offset (rtx temp
, rtx reg
, HOST_WIDE_INT offset
)
2835 if (!SMALL_OPERAND (offset
))
2841 /* Load the full offset into a register so that we can use
2842 an unextended instruction for the address itself. */
2843 high
= GEN_INT (offset
);
2848 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2849 The addition inside the macro CONST_HIGH_PART may cause an
2850 overflow, so we need to force a sign-extension check. */
2851 high
= gen_int_mode (CONST_HIGH_PART (offset
), Pmode
);
2852 offset
= CONST_LOW_PART (offset
);
2854 high
= mips_force_temporary (temp
, high
);
2855 reg
= mips_force_temporary (temp
, gen_rtx_PLUS (Pmode
, high
, reg
));
2857 return plus_constant (reg
, offset
);
2860 /* The __tls_get_attr symbol. */
2861 static GTY(()) rtx mips_tls_symbol
;
2863 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2864 the TLS symbol we are referencing and TYPE is the symbol type to use
2865 (either global dynamic or local dynamic). V0 is an RTX for the
2866 return value location. */
2869 mips_call_tls_get_addr (rtx sym
, enum mips_symbol_type type
, rtx v0
)
2873 a0
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
2875 if (!mips_tls_symbol
)
2876 mips_tls_symbol
= init_one_libfunc ("__tls_get_addr");
2878 loc
= mips_unspec_address (sym
, type
);
2882 emit_insn (gen_rtx_SET (Pmode
, a0
,
2883 gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, loc
)));
2884 insn
= mips_expand_call (MIPS_CALL_NORMAL
, v0
, mips_tls_symbol
,
2885 const0_rtx
, NULL_RTX
, false);
2886 RTL_CONST_CALL_P (insn
) = 1;
2887 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), a0
);
2888 insn
= get_insns ();
2895 /* Return a pseudo register that contains the current thread pointer. */
2902 tp
= gen_reg_rtx (Pmode
);
2903 if (Pmode
== DImode
)
2904 emit_insn (gen_tls_get_tp_di (tp
));
2906 emit_insn (gen_tls_get_tp_si (tp
));
2910 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2911 its address. The return value will be both a valid address and a valid
2912 SET_SRC (either a REG or a LO_SUM). */
2915 mips_legitimize_tls_address (rtx loc
)
2917 rtx dest
, insn
, v0
, tp
, tmp1
, tmp2
, eqv
;
2918 enum tls_model model
;
2922 sorry ("MIPS16 TLS");
2923 return gen_reg_rtx (Pmode
);
2926 model
= SYMBOL_REF_TLS_MODEL (loc
);
2927 /* Only TARGET_ABICALLS code can have more than one module; other
2928 code must be be static and should not use a GOT. All TLS models
2929 reduce to local exec in this situation. */
2930 if (!TARGET_ABICALLS
)
2931 model
= TLS_MODEL_LOCAL_EXEC
;
2935 case TLS_MODEL_GLOBAL_DYNAMIC
:
2936 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2937 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSGD
, v0
);
2938 dest
= gen_reg_rtx (Pmode
);
2939 emit_libcall_block (insn
, dest
, v0
, loc
);
2942 case TLS_MODEL_LOCAL_DYNAMIC
:
2943 v0
= gen_rtx_REG (Pmode
, GP_RETURN
);
2944 insn
= mips_call_tls_get_addr (loc
, SYMBOL_TLSLDM
, v0
);
2945 tmp1
= gen_reg_rtx (Pmode
);
2947 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2948 share the LDM result with other LD model accesses. */
2949 eqv
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
2951 emit_libcall_block (insn
, tmp1
, v0
, eqv
);
2953 tmp2
= mips_unspec_offset_high (NULL
, tmp1
, loc
, SYMBOL_DTPREL
);
2954 dest
= gen_rtx_LO_SUM (Pmode
, tmp2
,
2955 mips_unspec_address (loc
, SYMBOL_DTPREL
));
2958 case TLS_MODEL_INITIAL_EXEC
:
2959 tp
= mips_get_tp ();
2960 tmp1
= gen_reg_rtx (Pmode
);
2961 tmp2
= mips_unspec_address (loc
, SYMBOL_GOTTPREL
);
2962 if (Pmode
== DImode
)
2963 emit_insn (gen_load_gotdi (tmp1
, pic_offset_table_rtx
, tmp2
));
2965 emit_insn (gen_load_gotsi (tmp1
, pic_offset_table_rtx
, tmp2
));
2966 dest
= gen_reg_rtx (Pmode
);
2967 emit_insn (gen_add3_insn (dest
, tmp1
, tp
));
2970 case TLS_MODEL_LOCAL_EXEC
:
2971 tp
= mips_get_tp ();
2972 tmp1
= mips_unspec_offset_high (NULL
, tp
, loc
, SYMBOL_TPREL
);
2973 dest
= gen_rtx_LO_SUM (Pmode
, tmp1
,
2974 mips_unspec_address (loc
, SYMBOL_TPREL
));
2983 /* If X is not a valid address for mode MODE, force it into a register. */
2986 mips_force_address (rtx x
, enum machine_mode mode
)
2988 if (!mips_legitimate_address_p (mode
, x
, false))
2989 x
= force_reg (Pmode
, x
);
2993 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2994 be legitimized in a way that the generic machinery might not expect,
2995 return a new address, otherwise return NULL. MODE is the mode of
2996 the memory being accessed. */
2999 mips_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3000 enum machine_mode mode
)
3003 HOST_WIDE_INT offset
;
3005 if (mips_tls_symbol_p (x
))
3006 return mips_legitimize_tls_address (x
);
3008 /* See if the address can split into a high part and a LO_SUM. */
3009 if (mips_split_symbol (NULL
, x
, mode
, &addr
))
3010 return mips_force_address (addr
, mode
);
3012 /* Handle BASE + OFFSET using mips_add_offset. */
3013 mips_split_plus (x
, &base
, &offset
);
3016 if (!mips_valid_base_register_p (base
, mode
, false))
3017 base
= copy_to_mode_reg (Pmode
, base
);
3018 addr
= mips_add_offset (NULL
, base
, offset
);
3019 return mips_force_address (addr
, mode
);
3025 /* Load VALUE into DEST. TEMP is as for mips_force_temporary. */
3028 mips_move_integer (rtx temp
, rtx dest
, unsigned HOST_WIDE_INT value
)
3030 struct mips_integer_op codes
[MIPS_MAX_INTEGER_OPS
];
3031 enum machine_mode mode
;
3032 unsigned int i
, num_ops
;
3035 mode
= GET_MODE (dest
);
3036 num_ops
= mips_build_integer (codes
, value
);
3038 /* Apply each binary operation to X. Invariant: X is a legitimate
3039 source operand for a SET pattern. */
3040 x
= GEN_INT (codes
[0].value
);
3041 for (i
= 1; i
< num_ops
; i
++)
3043 if (!can_create_pseudo_p ())
3045 emit_insn (gen_rtx_SET (VOIDmode
, temp
, x
));
3049 x
= force_reg (mode
, x
);
3050 x
= gen_rtx_fmt_ee (codes
[i
].code
, mode
, x
, GEN_INT (codes
[i
].value
));
3053 emit_insn (gen_rtx_SET (VOIDmode
, dest
, x
));
3056 /* Subroutine of mips_legitimize_move. Move constant SRC into register
3057 DEST given that SRC satisfies immediate_operand but doesn't satisfy
3061 mips_legitimize_const_move (enum machine_mode mode
, rtx dest
, rtx src
)
3065 /* Split moves of big integers into smaller pieces. */
3066 if (splittable_const_int_operand (src
, mode
))
3068 mips_move_integer (dest
, dest
, INTVAL (src
));
3072 /* Split moves of symbolic constants into high/low pairs. */
3073 if (mips_split_symbol (dest
, src
, MAX_MACHINE_MODE
, &src
))
3075 emit_insn (gen_rtx_SET (VOIDmode
, dest
, src
));
3079 /* Generate the appropriate access sequences for TLS symbols. */
3080 if (mips_tls_symbol_p (src
))
3082 mips_emit_move (dest
, mips_legitimize_tls_address (src
));
3086 /* If we have (const (plus symbol offset)), and that expression cannot
3087 be forced into memory, load the symbol first and add in the offset.
3088 In non-MIPS16 mode, prefer to do this even if the constant _can_ be
3089 forced into memory, as it usually produces better code. */
3090 split_const (src
, &base
, &offset
);
3091 if (offset
!= const0_rtx
3092 && (targetm
.cannot_force_const_mem (src
)
3093 || (!TARGET_MIPS16
&& can_create_pseudo_p ())))
3095 base
= mips_force_temporary (dest
, base
);
3096 mips_emit_move (dest
, mips_add_offset (NULL
, base
, INTVAL (offset
)));
3100 src
= force_const_mem (mode
, src
);
3102 /* When using explicit relocs, constant pool references are sometimes
3103 not legitimate addresses. */
3104 mips_split_symbol (dest
, XEXP (src
, 0), mode
, &XEXP (src
, 0));
3105 mips_emit_move (dest
, src
);
3108 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3109 sequence that is valid. */
3112 mips_legitimize_move (enum machine_mode mode
, rtx dest
, rtx src
)
3114 if (!register_operand (dest
, mode
) && !reg_or_0_operand (src
, mode
))
3116 mips_emit_move (dest
, force_reg (mode
, src
));
3120 /* We need to deal with constants that would be legitimate
3121 immediate_operands but aren't legitimate move_operands. */
3122 if (CONSTANT_P (src
) && !move_operand (src
, mode
))
3124 mips_legitimize_const_move (mode
, dest
, src
);
3125 set_unique_reg_note (get_last_insn (), REG_EQUAL
, copy_rtx (src
));
3131 /* Return true if value X in context CONTEXT is a small-data address
3132 that can be rewritten as a LO_SUM. */
3135 mips_rewrite_small_data_p (rtx x
, enum mips_symbol_context context
)
3137 enum mips_symbol_type symbol_type
;
3139 return (mips_lo_relocs
[SYMBOL_GP_RELATIVE
]
3140 && !mips_split_p
[SYMBOL_GP_RELATIVE
]
3141 && mips_symbolic_constant_p (x
, context
, &symbol_type
)
3142 && symbol_type
== SYMBOL_GP_RELATIVE
);
3145 /* A for_each_rtx callback for mips_small_data_pattern_p. DATA is the
3146 containing MEM, or null if none. */
3149 mips_small_data_pattern_1 (rtx
*loc
, void *data
)
3151 enum mips_symbol_context context
;
3153 if (GET_CODE (*loc
) == LO_SUM
)
3158 if (for_each_rtx (&XEXP (*loc
, 0), mips_small_data_pattern_1
, *loc
))
3163 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3164 return mips_rewrite_small_data_p (*loc
, context
);
3167 /* Return true if OP refers to small data symbols directly, not through
3171 mips_small_data_pattern_p (rtx op
)
3173 return for_each_rtx (&op
, mips_small_data_pattern_1
, NULL
);
3176 /* A for_each_rtx callback, used by mips_rewrite_small_data.
3177 DATA is the containing MEM, or null if none. */
3180 mips_rewrite_small_data_1 (rtx
*loc
, void *data
)
3182 enum mips_symbol_context context
;
3186 for_each_rtx (&XEXP (*loc
, 0), mips_rewrite_small_data_1
, *loc
);
3190 context
= data
? SYMBOL_CONTEXT_MEM
: SYMBOL_CONTEXT_LEA
;
3191 if (mips_rewrite_small_data_p (*loc
, context
))
3192 *loc
= gen_rtx_LO_SUM (Pmode
, pic_offset_table_rtx
, *loc
);
3194 if (GET_CODE (*loc
) == LO_SUM
)
3200 /* Rewrite instruction pattern PATTERN so that it refers to small data
3201 using explicit relocations. */
3204 mips_rewrite_small_data (rtx pattern
)
3206 pattern
= copy_insn (pattern
);
3207 for_each_rtx (&pattern
, mips_rewrite_small_data_1
, NULL
);
3211 /* We need a lot of little routines to check the range of MIPS16 immediate
3215 m16_check_op (rtx op
, int low
, int high
, int mask
)
3217 return (CONST_INT_P (op
)
3218 && IN_RANGE (INTVAL (op
), low
, high
)
3219 && (INTVAL (op
) & mask
) == 0);
3223 m16_uimm3_b (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3225 return m16_check_op (op
, 0x1, 0x8, 0);
3229 m16_simm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3231 return m16_check_op (op
, -0x8, 0x7, 0);
3235 m16_nsimm4_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3237 return m16_check_op (op
, -0x7, 0x8, 0);
3241 m16_simm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3243 return m16_check_op (op
, -0x10, 0xf, 0);
3247 m16_nsimm5_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3249 return m16_check_op (op
, -0xf, 0x10, 0);
3253 m16_uimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3255 return m16_check_op (op
, -0x10 << 2, 0xf << 2, 3);
3259 m16_nuimm5_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3261 return m16_check_op (op
, -0xf << 2, 0x10 << 2, 3);
3265 m16_simm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3267 return m16_check_op (op
, -0x80, 0x7f, 0);
3271 m16_nsimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3273 return m16_check_op (op
, -0x7f, 0x80, 0);
3277 m16_uimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3279 return m16_check_op (op
, 0x0, 0xff, 0);
3283 m16_nuimm8_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3285 return m16_check_op (op
, -0xff, 0x0, 0);
3289 m16_uimm8_m1_1 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3291 return m16_check_op (op
, -0x1, 0xfe, 0);
3295 m16_uimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3297 return m16_check_op (op
, 0x0, 0xff << 2, 3);
3301 m16_nuimm8_4 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3303 return m16_check_op (op
, -0xff << 2, 0x0, 3);
3307 m16_simm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3309 return m16_check_op (op
, -0x80 << 3, 0x7f << 3, 7);
3313 m16_nsimm8_8 (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
3315 return m16_check_op (op
, -0x7f << 3, 0x80 << 3, 7);
3318 /* The cost of loading values from the constant pool. It should be
3319 larger than the cost of any constant we want to synthesize inline. */
3320 #define CONSTANT_POOL_COST COSTS_N_INSNS (TARGET_MIPS16 ? 4 : 8)
3322 /* Return the cost of X when used as an operand to the MIPS16 instruction
3323 that implements CODE. Return -1 if there is no such instruction, or if
3324 X is not a valid immediate operand for it. */
3327 mips16_constant_cost (int code
, HOST_WIDE_INT x
)
3334 /* Shifts by between 1 and 8 bits (inclusive) are unextended,
3335 other shifts are extended. The shift patterns truncate the shift
3336 count to the right size, so there are no out-of-range values. */
3337 if (IN_RANGE (x
, 1, 8))
3339 return COSTS_N_INSNS (1);
3342 if (IN_RANGE (x
, -128, 127))
3344 if (SMALL_OPERAND (x
))
3345 return COSTS_N_INSNS (1);
3349 /* Like LE, but reject the always-true case. */
3353 /* We add 1 to the immediate and use SLT. */
3356 /* We can use CMPI for an xor with an unsigned 16-bit X. */
3359 if (IN_RANGE (x
, 0, 255))
3361 if (SMALL_OPERAND_UNSIGNED (x
))
3362 return COSTS_N_INSNS (1);
3367 /* Equality comparisons with 0 are cheap. */
3377 /* Return true if there is a non-MIPS16 instruction that implements CODE
3378 and if that instruction accepts X as an immediate operand. */
3381 mips_immediate_operand_p (int code
, HOST_WIDE_INT x
)
3388 /* All shift counts are truncated to a valid constant. */
3393 /* Likewise rotates, if the target supports rotates at all. */
3399 /* These instructions take 16-bit unsigned immediates. */
3400 return SMALL_OPERAND_UNSIGNED (x
);
3405 /* These instructions take 16-bit signed immediates. */
3406 return SMALL_OPERAND (x
);
3412 /* The "immediate" forms of these instructions are really
3413 implemented as comparisons with register 0. */
3418 /* Likewise, meaning that the only valid immediate operand is 1. */
3422 /* We add 1 to the immediate and use SLT. */
3423 return SMALL_OPERAND (x
+ 1);
3426 /* Likewise SLTU, but reject the always-true case. */
3427 return SMALL_OPERAND (x
+ 1) && x
+ 1 != 0;
3431 /* The bit position and size are immediate operands. */
3432 return ISA_HAS_EXT_INS
;
3435 /* By default assume that $0 can be used for 0. */
3440 /* Return the cost of binary operation X, given that the instruction
3441 sequence for a word-sized or smaller operation has cost SINGLE_COST
3442 and that the sequence of a double-word operation has cost DOUBLE_COST.
3443 If SPEED is true, optimize for speed otherwise optimize for size. */
3446 mips_binary_cost (rtx x
, int single_cost
, int double_cost
, bool speed
)
3450 if (GET_MODE_SIZE (GET_MODE (x
)) == UNITS_PER_WORD
* 2)
3455 + rtx_cost (XEXP (x
, 0), SET
, speed
)
3456 + rtx_cost (XEXP (x
, 1), GET_CODE (x
), speed
));
3459 /* Return the cost of floating-point multiplications of mode MODE. */
3462 mips_fp_mult_cost (enum machine_mode mode
)
3464 return mode
== DFmode
? mips_cost
->fp_mult_df
: mips_cost
->fp_mult_sf
;
3467 /* Return the cost of floating-point divisions of mode MODE. */
3470 mips_fp_div_cost (enum machine_mode mode
)
3472 return mode
== DFmode
? mips_cost
->fp_div_df
: mips_cost
->fp_div_sf
;
3475 /* Return the cost of sign-extending OP to mode MODE, not including the
3476 cost of OP itself. */
3479 mips_sign_extend_cost (enum machine_mode mode
, rtx op
)
3482 /* Extended loads are as cheap as unextended ones. */
3485 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3486 /* A sign extension from SImode to DImode in 64-bit mode is free. */
3489 if (ISA_HAS_SEB_SEH
|| GENERATE_MIPS16E
)
3490 /* We can use SEB or SEH. */
3491 return COSTS_N_INSNS (1);
3493 /* We need to use a shift left and a shift right. */
3494 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3497 /* Return the cost of zero-extending OP to mode MODE, not including the
3498 cost of OP itself. */
3501 mips_zero_extend_cost (enum machine_mode mode
, rtx op
)
3504 /* Extended loads are as cheap as unextended ones. */
3507 if (TARGET_64BIT
&& mode
== DImode
&& GET_MODE (op
) == SImode
)
3508 /* We need a shift left by 32 bits and a shift right by 32 bits. */
3509 return COSTS_N_INSNS (TARGET_MIPS16
? 4 : 2);
3511 if (GENERATE_MIPS16E
)
3512 /* We can use ZEB or ZEH. */
3513 return COSTS_N_INSNS (1);
3516 /* We need to load 0xff or 0xffff into a register and use AND. */
3517 return COSTS_N_INSNS (GET_MODE (op
) == QImode
? 2 : 3);
3519 /* We can use ANDI. */
3520 return COSTS_N_INSNS (1);
3523 /* Implement TARGET_RTX_COSTS. */
3526 mips_rtx_costs (rtx x
, int code
, int outer_code
, int *total
, bool speed
)
3528 enum machine_mode mode
= GET_MODE (x
);
3529 bool float_mode_p
= FLOAT_MODE_P (mode
);
3533 /* The cost of a COMPARE is hard to define for MIPS. COMPAREs don't
3534 appear in the instruction stream, and the cost of a comparison is
3535 really the cost of the branch or scc condition. At the time of
3536 writing, GCC only uses an explicit outer COMPARE code when optabs
3537 is testing whether a constant is expensive enough to force into a
3538 register. We want optabs to pass such constants through the MIPS
3539 expanders instead, so make all constants very cheap here. */
3540 if (outer_code
== COMPARE
)
3542 gcc_assert (CONSTANT_P (x
));
3550 /* Treat *clear_upper32-style ANDs as having zero cost in the
3551 second operand. The cost is entirely in the first operand.
3553 ??? This is needed because we would otherwise try to CSE
3554 the constant operand. Although that's the right thing for
3555 instructions that continue to be a register operation throughout
3556 compilation, it is disastrous for instructions that could
3557 later be converted into a memory operation. */
3559 && outer_code
== AND
3560 && UINTVAL (x
) == 0xffffffff)
3568 cost
= mips16_constant_cost (outer_code
, INTVAL (x
));
3577 /* When not optimizing for size, we care more about the cost
3578 of hot code, and hot code is often in a loop. If a constant
3579 operand needs to be forced into a register, we will often be
3580 able to hoist the constant load out of the loop, so the load
3581 should not contribute to the cost. */
3582 if (speed
|| mips_immediate_operand_p (outer_code
, INTVAL (x
)))
3594 if (force_to_mem_operand (x
, VOIDmode
))
3596 *total
= COSTS_N_INSNS (1);
3599 cost
= mips_const_insns (x
);
3602 /* If the constant is likely to be stored in a GPR, SETs of
3603 single-insn constants are as cheap as register sets; we
3604 never want to CSE them.
3606 Don't reduce the cost of storing a floating-point zero in
3607 FPRs. If we have a zero in an FPR for other reasons, we
3608 can get better cfg-cleanup and delayed-branch results by
3609 using it consistently, rather than using $0 sometimes and
3610 an FPR at other times. Also, moves between floating-point
3611 registers are sometimes cheaper than (D)MTC1 $0. */
3613 && outer_code
== SET
3614 && !(float_mode_p
&& TARGET_HARD_FLOAT
))
3616 /* When non-MIPS16 code loads a constant N>1 times, we rarely
3617 want to CSE the constant itself. It is usually better to
3618 have N copies of the last operation in the sequence and one
3619 shared copy of the other operations. (Note that this is
3620 not true for MIPS16 code, where the final operation in the
3621 sequence is often an extended instruction.)
3623 Also, if we have a CONST_INT, we don't know whether it is
3624 for a word or doubleword operation, so we cannot rely on
3625 the result of mips_build_integer. */
3626 else if (!TARGET_MIPS16
3627 && (outer_code
== SET
|| mode
== VOIDmode
))
3629 *total
= COSTS_N_INSNS (cost
);
3632 /* The value will need to be fetched from the constant pool. */
3633 *total
= CONSTANT_POOL_COST
;
3637 /* If the address is legitimate, return the number of
3638 instructions it needs. */
3640 cost
= mips_address_insns (addr
, mode
, true);
3643 *total
= COSTS_N_INSNS (cost
+ 1);
3646 /* Check for a scaled indexed address. */
3647 if (mips_lwxs_address_p (addr
))
3649 *total
= COSTS_N_INSNS (2);
3652 /* Otherwise use the default handling. */
3656 *total
= COSTS_N_INSNS (6);
3660 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 2 : 1);
3664 /* Check for a *clear_upper32 pattern and treat it like a zero
3665 extension. See the pattern's comment for details. */
3668 && CONST_INT_P (XEXP (x
, 1))
3669 && UINTVAL (XEXP (x
, 1)) == 0xffffffff)
3671 *total
= (mips_zero_extend_cost (mode
, XEXP (x
, 0))
3672 + rtx_cost (XEXP (x
, 0), SET
, speed
));
3679 /* Double-word operations use two single-word operations. */
3680 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (2),
3689 if (CONSTANT_P (XEXP (x
, 1)))
3690 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3693 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (12),
3699 *total
= mips_cost
->fp_add
;
3701 *total
= COSTS_N_INSNS (4);
3705 /* Low-part immediates need an extended MIPS16 instruction. */
3706 *total
= (COSTS_N_INSNS (TARGET_MIPS16
? 2 : 1)
3707 + rtx_cost (XEXP (x
, 0), SET
, speed
));
3722 /* Branch comparisons have VOIDmode, so use the first operand's
3724 mode
= GET_MODE (XEXP (x
, 0));
3725 if (FLOAT_MODE_P (mode
))
3727 *total
= mips_cost
->fp_add
;
3730 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1), COSTS_N_INSNS (4),
3736 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3737 && TARGET_FUSED_MADD
3738 && !HONOR_NANS (mode
)
3739 && !HONOR_SIGNED_ZEROS (mode
))
3741 /* See if we can use NMADD or NMSUB. See mips.md for the
3742 associated patterns. */
3743 rtx op0
= XEXP (x
, 0);
3744 rtx op1
= XEXP (x
, 1);
3745 if (GET_CODE (op0
) == MULT
&& GET_CODE (XEXP (op0
, 0)) == NEG
)
3747 *total
= (mips_fp_mult_cost (mode
)
3748 + rtx_cost (XEXP (XEXP (op0
, 0), 0), SET
, speed
)
3749 + rtx_cost (XEXP (op0
, 1), SET
, speed
)
3750 + rtx_cost (op1
, SET
, speed
));
3753 if (GET_CODE (op1
) == MULT
)
3755 *total
= (mips_fp_mult_cost (mode
)
3756 + rtx_cost (op0
, SET
, speed
)
3757 + rtx_cost (XEXP (op1
, 0), SET
, speed
)
3758 + rtx_cost (XEXP (op1
, 1), SET
, speed
));
3767 /* If this is part of a MADD or MSUB, treat the PLUS as
3770 && TARGET_FUSED_MADD
3771 && GET_CODE (XEXP (x
, 0)) == MULT
)
3774 *total
= mips_cost
->fp_add
;
3778 /* Double-word operations require three single-word operations and
3779 an SLTU. The MIPS16 version then needs to move the result of
3780 the SLTU from $24 to a MIPS16 register. */
3781 *total
= mips_binary_cost (x
, COSTS_N_INSNS (1),
3782 COSTS_N_INSNS (TARGET_MIPS16
? 5 : 4),
3788 && (ISA_HAS_NMADD4_NMSUB4 (mode
) || ISA_HAS_NMADD3_NMSUB3 (mode
))
3789 && TARGET_FUSED_MADD
3790 && !HONOR_NANS (mode
)
3791 && HONOR_SIGNED_ZEROS (mode
))
3793 /* See if we can use NMADD or NMSUB. See mips.md for the
3794 associated patterns. */
3795 rtx op
= XEXP (x
, 0);
3796 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3797 && GET_CODE (XEXP (op
, 0)) == MULT
)
3799 *total
= (mips_fp_mult_cost (mode
)
3800 + rtx_cost (XEXP (XEXP (op
, 0), 0), SET
, speed
)
3801 + rtx_cost (XEXP (XEXP (op
, 0), 1), SET
, speed
)
3802 + rtx_cost (XEXP (op
, 1), SET
, speed
));
3808 *total
= mips_cost
->fp_add
;
3810 *total
= COSTS_N_INSNS (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
? 4 : 1);
3815 *total
= mips_fp_mult_cost (mode
);
3816 else if (mode
== DImode
&& !TARGET_64BIT
)
3817 /* Synthesized from 2 mulsi3s, 1 mulsidi3 and two additions,
3818 where the mulsidi3 always includes an MFHI and an MFLO. */
3820 ? mips_cost
->int_mult_si
* 3 + 6
3821 : COSTS_N_INSNS (ISA_HAS_MUL3
? 7 : 9));
3823 *total
= (ISA_HAS_MUL3
? 1 : 2);
3824 else if (mode
== DImode
)
3825 *total
= mips_cost
->int_mult_di
;
3827 *total
= mips_cost
->int_mult_si
;
3831 /* Check for a reciprocal. */
3834 && flag_unsafe_math_optimizations
3835 && XEXP (x
, 0) == CONST1_RTX (mode
))
3837 if (outer_code
== SQRT
|| GET_CODE (XEXP (x
, 1)) == SQRT
)
3838 /* An rsqrt<mode>a or rsqrt<mode>b pattern. Count the
3839 division as being free. */
3840 *total
= rtx_cost (XEXP (x
, 1), SET
, speed
);
3842 *total
= (mips_fp_div_cost (mode
)
3843 + rtx_cost (XEXP (x
, 1), SET
, speed
));
3852 *total
= mips_fp_div_cost (mode
);
3861 /* It is our responsibility to make division by a power of 2
3862 as cheap as 2 register additions if we want the division
3863 expanders to be used for such operations; see the setting
3864 of sdiv_pow2_cheap in optabs.c. Using (D)DIV for MIPS16
3865 should always produce shorter code than using
3866 expand_sdiv2_pow2. */
3868 && CONST_INT_P (XEXP (x
, 1))
3869 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
3871 *total
= COSTS_N_INSNS (2) + rtx_cost (XEXP (x
, 0), SET
, speed
);
3874 *total
= COSTS_N_INSNS (mips_idiv_insns ());
3876 else if (mode
== DImode
)
3877 *total
= mips_cost
->int_div_di
;
3879 *total
= mips_cost
->int_div_si
;
3883 *total
= mips_sign_extend_cost (mode
, XEXP (x
, 0));
3887 *total
= mips_zero_extend_cost (mode
, XEXP (x
, 0));
3891 case UNSIGNED_FLOAT
:
3894 case FLOAT_TRUNCATE
:
3895 *total
= mips_cost
->fp_add
;
3903 /* Implement TARGET_ADDRESS_COST. */
3906 mips_address_cost (rtx addr
, bool speed ATTRIBUTE_UNUSED
)
3908 return mips_address_insns (addr
, SImode
, false);
3911 /* Information about a single instruction in a multi-instruction
3913 struct mips_multi_member
{
3914 /* True if this is a label, false if it is code. */
3917 /* The output_asm_insn format of the instruction. */
3920 /* The operands to the instruction. */
3921 rtx operands
[MAX_RECOG_OPERANDS
];
3923 typedef struct mips_multi_member mips_multi_member
;
3925 /* Vector definitions for the above. */
3926 DEF_VEC_O(mips_multi_member
);
3927 DEF_VEC_ALLOC_O(mips_multi_member
, heap
);
3929 /* The instructions that make up the current multi-insn sequence. */
3930 static VEC (mips_multi_member
, heap
) *mips_multi_members
;
3932 /* How many instructions (as opposed to labels) are in the current
3933 multi-insn sequence. */
3934 static unsigned int mips_multi_num_insns
;
3936 /* Start a new multi-insn sequence. */
3939 mips_multi_start (void)
3941 VEC_truncate (mips_multi_member
, mips_multi_members
, 0);
3942 mips_multi_num_insns
= 0;
3945 /* Add a new, uninitialized member to the current multi-insn sequence. */
3947 static struct mips_multi_member
*
3948 mips_multi_add (void)
3950 return VEC_safe_push (mips_multi_member
, heap
, mips_multi_members
, 0);
3953 /* Add a normal insn with the given asm format to the current multi-insn
3954 sequence. The other arguments are a null-terminated list of operands. */
3957 mips_multi_add_insn (const char *format
, ...)
3959 struct mips_multi_member
*member
;
3964 member
= mips_multi_add ();
3965 member
->is_label_p
= false;
3966 member
->format
= format
;
3967 va_start (ap
, format
);
3969 while ((op
= va_arg (ap
, rtx
)))
3970 member
->operands
[i
++] = op
;
3972 mips_multi_num_insns
++;
3975 /* Add the given label definition to the current multi-insn sequence.
3976 The definition should include the colon. */
3979 mips_multi_add_label (const char *label
)
3981 struct mips_multi_member
*member
;
3983 member
= mips_multi_add ();
3984 member
->is_label_p
= true;
3985 member
->format
= label
;
3988 /* Return the index of the last member of the current multi-insn sequence. */
3991 mips_multi_last_index (void)
3993 return VEC_length (mips_multi_member
, mips_multi_members
) - 1;
3996 /* Add a copy of an existing instruction to the current multi-insn
3997 sequence. I is the index of the instruction that should be copied. */
4000 mips_multi_copy_insn (unsigned int i
)
4002 struct mips_multi_member
*member
;
4004 member
= mips_multi_add ();
4005 memcpy (member
, VEC_index (mips_multi_member
, mips_multi_members
, i
),
4007 gcc_assert (!member
->is_label_p
);
4010 /* Change the operand of an existing instruction in the current
4011 multi-insn sequence. I is the index of the instruction,
4012 OP is the index of the operand, and X is the new value. */
4015 mips_multi_set_operand (unsigned int i
, unsigned int op
, rtx x
)
4017 VEC_index (mips_multi_member
, mips_multi_members
, i
)->operands
[op
] = x
;
4020 /* Write out the asm code for the current multi-insn sequence. */
4023 mips_multi_write (void)
4025 struct mips_multi_member
*member
;
4028 FOR_EACH_VEC_ELT (mips_multi_member
, mips_multi_members
, i
, member
)
4029 if (member
->is_label_p
)
4030 fprintf (asm_out_file
, "%s\n", member
->format
);
4032 output_asm_insn (member
->format
, member
->operands
);
4035 /* Return one word of double-word value OP, taking into account the fixed
4036 endianness of certain registers. HIGH_P is true to select the high part,
4037 false to select the low part. */
4040 mips_subword (rtx op
, bool high_p
)
4042 unsigned int byte
, offset
;
4043 enum machine_mode mode
;
4045 mode
= GET_MODE (op
);
4046 if (mode
== VOIDmode
)
4047 mode
= TARGET_64BIT
? TImode
: DImode
;
4049 if (TARGET_BIG_ENDIAN
? !high_p
: high_p
)
4050 byte
= UNITS_PER_WORD
;
4054 if (FP_REG_RTX_P (op
))
4056 /* Paired FPRs are always ordered little-endian. */
4057 offset
= (UNITS_PER_WORD
< UNITS_PER_HWFPVALUE
? high_p
: byte
!= 0);
4058 return gen_rtx_REG (word_mode
, REGNO (op
) + offset
);
4062 return mips_rewrite_small_data (adjust_address (op
, word_mode
, byte
));
4064 return simplify_gen_subreg (word_mode
, op
, mode
, byte
);
4067 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4070 mips_split_64bit_move_p (rtx dest
, rtx src
)
4075 /* FPR-to-FPR moves can be done in a single instruction, if they're
4077 if (FP_REG_RTX_P (src
) && FP_REG_RTX_P (dest
))
4080 /* Check for floating-point loads and stores. */
4081 if (ISA_HAS_LDC1_SDC1
)
4083 if (FP_REG_RTX_P (dest
) && MEM_P (src
))
4085 if (FP_REG_RTX_P (src
) && MEM_P (dest
))
4091 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4092 this function handles 64-bit moves for which mips_split_64bit_move_p
4093 holds. For 64-bit targets, this function handles 128-bit moves. */
4096 mips_split_doubleword_move (rtx dest
, rtx src
)
4100 if (FP_REG_RTX_P (dest
) || FP_REG_RTX_P (src
))
4102 if (!TARGET_64BIT
&& GET_MODE (dest
) == DImode
)
4103 emit_insn (gen_move_doubleword_fprdi (dest
, src
));
4104 else if (!TARGET_64BIT
&& GET_MODE (dest
) == DFmode
)
4105 emit_insn (gen_move_doubleword_fprdf (dest
, src
));
4106 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SFmode
)
4107 emit_insn (gen_move_doubleword_fprv2sf (dest
, src
));
4108 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V2SImode
)
4109 emit_insn (gen_move_doubleword_fprv2si (dest
, src
));
4110 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V4HImode
)
4111 emit_insn (gen_move_doubleword_fprv4hi (dest
, src
));
4112 else if (!TARGET_64BIT
&& GET_MODE (dest
) == V8QImode
)
4113 emit_insn (gen_move_doubleword_fprv8qi (dest
, src
));
4114 else if (TARGET_64BIT
&& GET_MODE (dest
) == TFmode
)
4115 emit_insn (gen_move_doubleword_fprtf (dest
, src
));
4119 else if (REG_P (dest
) && REGNO (dest
) == MD_REG_FIRST
)
4121 low_dest
= mips_subword (dest
, false);
4122 mips_emit_move (low_dest
, mips_subword (src
, false));
4124 emit_insn (gen_mthidi_ti (dest
, mips_subword (src
, true), low_dest
));
4126 emit_insn (gen_mthisi_di (dest
, mips_subword (src
, true), low_dest
));
4128 else if (REG_P (src
) && REGNO (src
) == MD_REG_FIRST
)
4130 mips_emit_move (mips_subword (dest
, false), mips_subword (src
, false));
4132 emit_insn (gen_mfhidi_ti (mips_subword (dest
, true), src
));
4134 emit_insn (gen_mfhisi_di (mips_subword (dest
, true), src
));
4138 /* The operation can be split into two normal moves. Decide in
4139 which order to do them. */
4140 low_dest
= mips_subword (dest
, false);
4141 if (REG_P (low_dest
)
4142 && reg_overlap_mentioned_p (low_dest
, src
))
4144 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4145 mips_emit_move (low_dest
, mips_subword (src
, false));
4149 mips_emit_move (low_dest
, mips_subword (src
, false));
4150 mips_emit_move (mips_subword (dest
, true), mips_subword (src
, true));
4155 /* Return the appropriate instructions to move SRC into DEST. Assume
4156 that SRC is operand 1 and DEST is operand 0. */
4159 mips_output_move (rtx dest
, rtx src
)
4161 enum rtx_code dest_code
, src_code
;
4162 enum machine_mode mode
;
4163 enum mips_symbol_type symbol_type
;
4166 dest_code
= GET_CODE (dest
);
4167 src_code
= GET_CODE (src
);
4168 mode
= GET_MODE (dest
);
4169 dbl_p
= (GET_MODE_SIZE (mode
) == 8);
4171 if (dbl_p
&& mips_split_64bit_move_p (dest
, src
))
4174 if ((src_code
== REG
&& GP_REG_P (REGNO (src
)))
4175 || (!TARGET_MIPS16
&& src
== CONST0_RTX (mode
)))
4177 if (dest_code
== REG
)
4179 if (GP_REG_P (REGNO (dest
)))
4180 return "move\t%0,%z1";
4182 /* Moves to HI are handled by special .md insns. */
4183 if (REGNO (dest
) == LO_REGNUM
)
4186 if (DSP_ACC_REG_P (REGNO (dest
)))
4188 static char retval
[] = "mt__\t%z1,%q0";
4190 retval
[2] = reg_names
[REGNO (dest
)][4];
4191 retval
[3] = reg_names
[REGNO (dest
)][5];
4195 if (FP_REG_P (REGNO (dest
)))
4196 return dbl_p
? "dmtc1\t%z1,%0" : "mtc1\t%z1,%0";
4198 if (ALL_COP_REG_P (REGNO (dest
)))
4200 static char retval
[] = "dmtc_\t%z1,%0";
4202 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4203 return dbl_p
? retval
: retval
+ 1;
4206 if (dest_code
== MEM
)
4207 switch (GET_MODE_SIZE (mode
))
4209 case 1: return "sb\t%z1,%0";
4210 case 2: return "sh\t%z1,%0";
4211 case 4: return "sw\t%z1,%0";
4212 case 8: return "sd\t%z1,%0";
4215 if (dest_code
== REG
&& GP_REG_P (REGNO (dest
)))
4217 if (src_code
== REG
)
4219 /* Moves from HI are handled by special .md insns. */
4220 if (REGNO (src
) == LO_REGNUM
)
4222 /* When generating VR4120 or VR4130 code, we use MACC and
4223 DMACC instead of MFLO. This avoids both the normal
4224 MIPS III HI/LO hazards and the errata related to
4227 return dbl_p
? "dmacc\t%0,%.,%." : "macc\t%0,%.,%.";
4231 if (DSP_ACC_REG_P (REGNO (src
)))
4233 static char retval
[] = "mf__\t%0,%q1";
4235 retval
[2] = reg_names
[REGNO (src
)][4];
4236 retval
[3] = reg_names
[REGNO (src
)][5];
4240 if (FP_REG_P (REGNO (src
)))
4241 return dbl_p
? "dmfc1\t%0,%1" : "mfc1\t%0,%1";
4243 if (ALL_COP_REG_P (REGNO (src
)))
4245 static char retval
[] = "dmfc_\t%0,%1";
4247 retval
[4] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4248 return dbl_p
? retval
: retval
+ 1;
4251 if (ST_REG_P (REGNO (src
)) && ISA_HAS_8CC
)
4252 return "lui\t%0,0x3f80\n\tmovf\t%0,%.,%1";
4255 if (src_code
== MEM
)
4256 switch (GET_MODE_SIZE (mode
))
4258 case 1: return "lbu\t%0,%1";
4259 case 2: return "lhu\t%0,%1";
4260 case 4: return "lw\t%0,%1";
4261 case 8: return "ld\t%0,%1";
4264 if (src_code
== CONST_INT
)
4266 /* Don't use the X format for the operand itself, because that
4267 will give out-of-range numbers for 64-bit hosts and 32-bit
4270 return "li\t%0,%1\t\t\t# %X1";
4272 if (SMALL_OPERAND_UNSIGNED (INTVAL (src
)))
4275 if (SMALL_OPERAND_UNSIGNED (-INTVAL (src
)))
4279 if (src_code
== HIGH
)
4280 return TARGET_MIPS16
? "#" : "lui\t%0,%h1";
4282 if (CONST_GP_P (src
))
4283 return "move\t%0,%1";
4285 if (mips_symbolic_constant_p (src
, SYMBOL_CONTEXT_LEA
, &symbol_type
)
4286 && mips_lo_relocs
[symbol_type
] != 0)
4288 /* A signed 16-bit constant formed by applying a relocation
4289 operator to a symbolic address. */
4290 gcc_assert (!mips_split_p
[symbol_type
]);
4291 return "li\t%0,%R1";
4294 if (symbolic_operand (src
, VOIDmode
))
4296 gcc_assert (TARGET_MIPS16
4297 ? TARGET_MIPS16_TEXT_LOADS
4298 : !TARGET_EXPLICIT_RELOCS
);
4299 return dbl_p
? "dla\t%0,%1" : "la\t%0,%1";
4302 if (src_code
== REG
&& FP_REG_P (REGNO (src
)))
4304 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4306 if (GET_MODE (dest
) == V2SFmode
)
4307 return "mov.ps\t%0,%1";
4309 return dbl_p
? "mov.d\t%0,%1" : "mov.s\t%0,%1";
4312 if (dest_code
== MEM
)
4313 return dbl_p
? "sdc1\t%1,%0" : "swc1\t%1,%0";
4315 if (dest_code
== REG
&& FP_REG_P (REGNO (dest
)))
4317 if (src_code
== MEM
)
4318 return dbl_p
? "ldc1\t%0,%1" : "lwc1\t%0,%1";
4320 if (dest_code
== REG
&& ALL_COP_REG_P (REGNO (dest
)) && src_code
== MEM
)
4322 static char retval
[] = "l_c_\t%0,%1";
4324 retval
[1] = (dbl_p
? 'd' : 'w');
4325 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (dest
));
4328 if (dest_code
== MEM
&& src_code
== REG
&& ALL_COP_REG_P (REGNO (src
)))
4330 static char retval
[] = "s_c_\t%1,%0";
4332 retval
[1] = (dbl_p
? 'd' : 'w');
4333 retval
[3] = COPNUM_AS_CHAR_FROM_REGNUM (REGNO (src
));
4339 /* Return true if CMP1 is a suitable second operand for integer ordering
4340 test CODE. See also the *sCC patterns in mips.md. */
4343 mips_int_order_operand_ok_p (enum rtx_code code
, rtx cmp1
)
4349 return reg_or_0_operand (cmp1
, VOIDmode
);
4353 return !TARGET_MIPS16
&& cmp1
== const1_rtx
;
4357 return arith_operand (cmp1
, VOIDmode
);
4360 return sle_operand (cmp1
, VOIDmode
);
4363 return sleu_operand (cmp1
, VOIDmode
);
4370 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4371 integer ordering test *CODE, or if an equivalent combination can
4372 be formed by adjusting *CODE and *CMP1. When returning true, update
4373 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4377 mips_canonicalize_int_order_test (enum rtx_code
*code
, rtx
*cmp1
,
4378 enum machine_mode mode
)
4380 HOST_WIDE_INT plus_one
;
4382 if (mips_int_order_operand_ok_p (*code
, *cmp1
))
4385 if (CONST_INT_P (*cmp1
))
4389 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4390 if (INTVAL (*cmp1
) < plus_one
)
4393 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4399 plus_one
= trunc_int_for_mode (UINTVAL (*cmp1
) + 1, mode
);
4403 *cmp1
= force_reg (mode
, GEN_INT (plus_one
));
4414 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4415 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4416 is nonnull, it's OK to set TARGET to the inverse of the result and
4417 flip *INVERT_PTR instead. */
4420 mips_emit_int_order_test (enum rtx_code code
, bool *invert_ptr
,
4421 rtx target
, rtx cmp0
, rtx cmp1
)
4423 enum machine_mode mode
;
4425 /* First see if there is a MIPS instruction that can do this operation.
4426 If not, try doing the same for the inverse operation. If that also
4427 fails, force CMP1 into a register and try again. */
4428 mode
= GET_MODE (cmp0
);
4429 if (mips_canonicalize_int_order_test (&code
, &cmp1
, mode
))
4430 mips_emit_binary (code
, target
, cmp0
, cmp1
);
4433 enum rtx_code inv_code
= reverse_condition (code
);
4434 if (!mips_canonicalize_int_order_test (&inv_code
, &cmp1
, mode
))
4436 cmp1
= force_reg (mode
, cmp1
);
4437 mips_emit_int_order_test (code
, invert_ptr
, target
, cmp0
, cmp1
);
4439 else if (invert_ptr
== 0)
4443 inv_target
= mips_force_binary (GET_MODE (target
),
4444 inv_code
, cmp0
, cmp1
);
4445 mips_emit_binary (XOR
, target
, inv_target
, const1_rtx
);
4449 *invert_ptr
= !*invert_ptr
;
4450 mips_emit_binary (inv_code
, target
, cmp0
, cmp1
);
4455 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4456 The register will have the same mode as CMP0. */
4459 mips_zero_if_equal (rtx cmp0
, rtx cmp1
)
4461 if (cmp1
== const0_rtx
)
4464 if (uns_arith_operand (cmp1
, VOIDmode
))
4465 return expand_binop (GET_MODE (cmp0
), xor_optab
,
4466 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4468 return expand_binop (GET_MODE (cmp0
), sub_optab
,
4469 cmp0
, cmp1
, 0, 0, OPTAB_DIRECT
);
4472 /* Convert *CODE into a code that can be used in a floating-point
4473 scc instruction (C.cond.fmt). Return true if the values of
4474 the condition code registers will be inverted, with 0 indicating
4475 that the condition holds. */
4478 mips_reversed_fp_cond (enum rtx_code
*code
)
4485 *code
= reverse_condition_maybe_unordered (*code
);
4493 /* Convert a comparison into something that can be used in a branch or
4494 conditional move. On entry, *OP0 and *OP1 are the values being
4495 compared and *CODE is the code used to compare them.
4497 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4498 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are possible,
4499 otherwise any standard branch condition can be used. The standard branch
4502 - EQ or NE between two registers.
4503 - any comparison between a register and zero. */
4506 mips_emit_compare (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
, bool need_eq_ne_p
)
4511 if (GET_MODE_CLASS (GET_MODE (*op0
)) == MODE_INT
)
4513 if (!need_eq_ne_p
&& *op1
== const0_rtx
)
4515 else if (*code
== EQ
|| *code
== NE
)
4519 *op0
= mips_zero_if_equal (cmp_op0
, cmp_op1
);
4523 *op1
= force_reg (GET_MODE (cmp_op0
), cmp_op1
);
4527 /* The comparison needs a separate scc instruction. Store the
4528 result of the scc in *OP0 and compare it against zero. */
4529 bool invert
= false;
4530 *op0
= gen_reg_rtx (GET_MODE (cmp_op0
));
4531 mips_emit_int_order_test (*code
, &invert
, *op0
, cmp_op0
, cmp_op1
);
4532 *code
= (invert
? EQ
: NE
);
4536 else if (ALL_FIXED_POINT_MODE_P (GET_MODE (cmp_op0
)))
4538 *op0
= gen_rtx_REG (CCDSPmode
, CCDSP_CC_REGNUM
);
4539 mips_emit_binary (*code
, *op0
, cmp_op0
, cmp_op1
);
4545 enum rtx_code cmp_code
;
4547 /* Floating-point tests use a separate C.cond.fmt comparison to
4548 set a condition code register. The branch or conditional move
4549 will then compare that register against zero.
4551 Set CMP_CODE to the code of the comparison instruction and
4552 *CODE to the code that the branch or move should use. */
4554 *code
= mips_reversed_fp_cond (&cmp_code
) ? EQ
: NE
;
4556 ? gen_reg_rtx (CCmode
)
4557 : gen_rtx_REG (CCmode
, FPSW_REGNUM
));
4559 mips_emit_binary (cmp_code
, *op0
, cmp_op0
, cmp_op1
);
4563 /* Try performing the comparison in OPERANDS[1], whose arms are OPERANDS[2]
4564 and OPERAND[3]. Store the result in OPERANDS[0].
4566 On 64-bit targets, the mode of the comparison and target will always be
4567 SImode, thus possibly narrower than that of the comparison's operands. */
4570 mips_expand_scc (rtx operands
[])
4572 rtx target
= operands
[0];
4573 enum rtx_code code
= GET_CODE (operands
[1]);
4574 rtx op0
= operands
[2];
4575 rtx op1
= operands
[3];
4577 gcc_assert (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
);
4579 if (code
== EQ
|| code
== NE
)
4582 && reg_imm10_operand (op1
, GET_MODE (op1
)))
4583 mips_emit_binary (code
, target
, op0
, op1
);
4586 rtx zie
= mips_zero_if_equal (op0
, op1
);
4587 mips_emit_binary (code
, target
, zie
, const0_rtx
);
4591 mips_emit_int_order_test (code
, 0, target
, op0
, op1
);
4594 /* Compare OPERANDS[1] with OPERANDS[2] using comparison code
4595 CODE and jump to OPERANDS[3] if the condition holds. */
4598 mips_expand_conditional_branch (rtx
*operands
)
4600 enum rtx_code code
= GET_CODE (operands
[0]);
4601 rtx op0
= operands
[1];
4602 rtx op1
= operands
[2];
4605 mips_emit_compare (&code
, &op0
, &op1
, TARGET_MIPS16
);
4606 condition
= gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
4607 emit_jump_insn (gen_condjump (condition
, operands
[3]));
4612 (set temp (COND:CCV2 CMP_OP0 CMP_OP1))
4613 (set DEST (unspec [TRUE_SRC FALSE_SRC temp] UNSPEC_MOVE_TF_PS)) */
4616 mips_expand_vcondv2sf (rtx dest
, rtx true_src
, rtx false_src
,
4617 enum rtx_code cond
, rtx cmp_op0
, rtx cmp_op1
)
4622 reversed_p
= mips_reversed_fp_cond (&cond
);
4623 cmp_result
= gen_reg_rtx (CCV2mode
);
4624 emit_insn (gen_scc_ps (cmp_result
,
4625 gen_rtx_fmt_ee (cond
, VOIDmode
, cmp_op0
, cmp_op1
)));
4627 emit_insn (gen_mips_cond_move_tf_ps (dest
, false_src
, true_src
,
4630 emit_insn (gen_mips_cond_move_tf_ps (dest
, true_src
, false_src
,
4634 /* Perform the comparison in OPERANDS[1]. Move OPERANDS[2] into OPERANDS[0]
4635 if the condition holds, otherwise move OPERANDS[3] into OPERANDS[0]. */
4638 mips_expand_conditional_move (rtx
*operands
)
4641 enum rtx_code code
= GET_CODE (operands
[1]);
4642 rtx op0
= XEXP (operands
[1], 0);
4643 rtx op1
= XEXP (operands
[1], 1);
4645 mips_emit_compare (&code
, &op0
, &op1
, true);
4646 cond
= gen_rtx_fmt_ee (code
, GET_MODE (op0
), op0
, op1
);
4647 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
4648 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]), cond
,
4649 operands
[2], operands
[3])));
4652 /* Perform the comparison in COMPARISON, then trap if the condition holds. */
4655 mips_expand_conditional_trap (rtx comparison
)
4658 enum machine_mode mode
;
4661 /* MIPS conditional trap instructions don't have GT or LE flavors,
4662 so we must swap the operands and convert to LT and GE respectively. */
4663 code
= GET_CODE (comparison
);
4670 code
= swap_condition (code
);
4671 op0
= XEXP (comparison
, 1);
4672 op1
= XEXP (comparison
, 0);
4676 op0
= XEXP (comparison
, 0);
4677 op1
= XEXP (comparison
, 1);
4681 mode
= GET_MODE (XEXP (comparison
, 0));
4682 op0
= force_reg (mode
, op0
);
4683 if (!arith_operand (op1
, mode
))
4684 op1
= force_reg (mode
, op1
);
4686 emit_insn (gen_rtx_TRAP_IF (VOIDmode
,
4687 gen_rtx_fmt_ee (code
, mode
, op0
, op1
),
4691 /* Initialize *CUM for a call to a function of type FNTYPE. */
4694 mips_init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
)
4696 memset (cum
, 0, sizeof (*cum
));
4697 cum
->prototype
= (fntype
&& prototype_p (fntype
));
4698 cum
->gp_reg_found
= (cum
->prototype
&& stdarg_p (fntype
));
4701 /* Fill INFO with information about a single argument. CUM is the
4702 cumulative state for earlier arguments. MODE is the mode of this
4703 argument and TYPE is its type (if known). NAMED is true if this
4704 is a named (fixed) argument rather than a variable one. */
4707 mips_get_arg_info (struct mips_arg_info
*info
, const CUMULATIVE_ARGS
*cum
,
4708 enum machine_mode mode
, const_tree type
, bool named
)
4710 bool doubleword_aligned_p
;
4711 unsigned int num_bytes
, num_words
, max_regs
;
4713 /* Work out the size of the argument. */
4714 num_bytes
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
4715 num_words
= (num_bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4717 /* Decide whether it should go in a floating-point register, assuming
4718 one is free. Later code checks for availability.
4720 The checks against UNITS_PER_FPVALUE handle the soft-float and
4721 single-float cases. */
4725 /* The EABI conventions have traditionally been defined in terms
4726 of TYPE_MODE, regardless of the actual type. */
4727 info
->fpr_p
= ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4728 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4729 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4734 /* Only leading floating-point scalars are passed in
4735 floating-point registers. We also handle vector floats the same
4736 say, which is OK because they are not covered by the standard ABI. */
4737 info
->fpr_p
= (!cum
->gp_reg_found
4738 && cum
->arg_number
< 2
4740 || SCALAR_FLOAT_TYPE_P (type
)
4741 || VECTOR_FLOAT_TYPE_P (type
))
4742 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4743 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4744 && GET_MODE_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4749 /* Scalar, complex and vector floating-point types are passed in
4750 floating-point registers, as long as this is a named rather
4751 than a variable argument. */
4752 info
->fpr_p
= (named
4753 && (type
== 0 || FLOAT_TYPE_P (type
))
4754 && (GET_MODE_CLASS (mode
) == MODE_FLOAT
4755 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4756 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)
4757 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_FPVALUE
);
4759 /* ??? According to the ABI documentation, the real and imaginary
4760 parts of complex floats should be passed in individual registers.
4761 The real and imaginary parts of stack arguments are supposed
4762 to be contiguous and there should be an extra word of padding
4765 This has two problems. First, it makes it impossible to use a
4766 single "void *" va_list type, since register and stack arguments
4767 are passed differently. (At the time of writing, MIPSpro cannot
4768 handle complex float varargs correctly.) Second, it's unclear
4769 what should happen when there is only one register free.
4771 For now, we assume that named complex floats should go into FPRs
4772 if there are two FPRs free, otherwise they should be passed in the
4773 same way as a struct containing two floats. */
4775 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4776 && GET_MODE_UNIT_SIZE (mode
) < UNITS_PER_FPVALUE
)
4778 if (cum
->num_gprs
>= MAX_ARGS_IN_REGISTERS
- 1)
4779 info
->fpr_p
= false;
4789 /* See whether the argument has doubleword alignment. */
4790 doubleword_aligned_p
= (mips_function_arg_boundary (mode
, type
)
4793 /* Set REG_OFFSET to the register count we're interested in.
4794 The EABI allocates the floating-point registers separately,
4795 but the other ABIs allocate them like integer registers. */
4796 info
->reg_offset
= (mips_abi
== ABI_EABI
&& info
->fpr_p
4800 /* Advance to an even register if the argument is doubleword-aligned. */
4801 if (doubleword_aligned_p
)
4802 info
->reg_offset
+= info
->reg_offset
& 1;
4804 /* Work out the offset of a stack argument. */
4805 info
->stack_offset
= cum
->stack_words
;
4806 if (doubleword_aligned_p
)
4807 info
->stack_offset
+= info
->stack_offset
& 1;
4809 max_regs
= MAX_ARGS_IN_REGISTERS
- info
->reg_offset
;
4811 /* Partition the argument between registers and stack. */
4812 info
->reg_words
= MIN (num_words
, max_regs
);
4813 info
->stack_words
= num_words
- info
->reg_words
;
4816 /* INFO describes a register argument that has the normal format for the
4817 argument's mode. Return the register it uses, assuming that FPRs are
4818 available if HARD_FLOAT_P. */
4821 mips_arg_regno (const struct mips_arg_info
*info
, bool hard_float_p
)
4823 if (!info
->fpr_p
|| !hard_float_p
)
4824 return GP_ARG_FIRST
+ info
->reg_offset
;
4825 else if (mips_abi
== ABI_32
&& TARGET_DOUBLE_FLOAT
&& info
->reg_offset
> 0)
4826 /* In o32, the second argument is always passed in $f14
4827 for TARGET_DOUBLE_FLOAT, regardless of whether the
4828 first argument was a word or doubleword. */
4829 return FP_ARG_FIRST
+ 2;
4831 return FP_ARG_FIRST
+ info
->reg_offset
;
4834 /* Implement TARGET_STRICT_ARGUMENT_NAMING. */
4837 mips_strict_argument_naming (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
)
4839 return !TARGET_OLDABI
;
4842 /* Implement TARGET_FUNCTION_ARG. */
4845 mips_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4846 const_tree type
, bool named
)
4848 struct mips_arg_info info
;
4850 /* We will be called with a mode of VOIDmode after the last argument
4851 has been seen. Whatever we return will be passed to the call expander.
4852 If we need a MIPS16 fp_code, return a REG with the code stored as
4854 if (mode
== VOIDmode
)
4856 if (TARGET_MIPS16
&& cum
->fp_code
!= 0)
4857 return gen_rtx_REG ((enum machine_mode
) cum
->fp_code
, 0);
4862 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4864 /* Return straight away if the whole argument is passed on the stack. */
4865 if (info
.reg_offset
== MAX_ARGS_IN_REGISTERS
)
4868 /* The n32 and n64 ABIs say that if any 64-bit chunk of the structure
4869 contains a double in its entirety, then that 64-bit chunk is passed
4870 in a floating-point register. */
4872 && TARGET_HARD_FLOAT
4875 && TREE_CODE (type
) == RECORD_TYPE
4876 && TYPE_SIZE_UNIT (type
)
4877 && host_integerp (TYPE_SIZE_UNIT (type
), 1))
4881 /* First check to see if there is any such field. */
4882 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
4883 if (TREE_CODE (field
) == FIELD_DECL
4884 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4885 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
4886 && host_integerp (bit_position (field
), 0)
4887 && int_bit_position (field
) % BITS_PER_WORD
== 0)
4892 /* Now handle the special case by returning a PARALLEL
4893 indicating where each 64-bit chunk goes. INFO.REG_WORDS
4894 chunks are passed in registers. */
4896 HOST_WIDE_INT bitpos
;
4899 /* assign_parms checks the mode of ENTRY_PARM, so we must
4900 use the actual mode here. */
4901 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (info
.reg_words
));
4904 field
= TYPE_FIELDS (type
);
4905 for (i
= 0; i
< info
.reg_words
; i
++)
4909 for (; field
; field
= DECL_CHAIN (field
))
4910 if (TREE_CODE (field
) == FIELD_DECL
4911 && int_bit_position (field
) >= bitpos
)
4915 && int_bit_position (field
) == bitpos
4916 && SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
))
4917 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
4918 reg
= gen_rtx_REG (DFmode
, FP_ARG_FIRST
+ info
.reg_offset
+ i
);
4920 reg
= gen_rtx_REG (DImode
, GP_ARG_FIRST
+ info
.reg_offset
+ i
);
4923 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4924 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4926 bitpos
+= BITS_PER_WORD
;
4932 /* Handle the n32/n64 conventions for passing complex floating-point
4933 arguments in FPR pairs. The real part goes in the lower register
4934 and the imaginary part goes in the upper register. */
4937 && GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4940 enum machine_mode inner
;
4943 inner
= GET_MODE_INNER (mode
);
4944 regno
= FP_ARG_FIRST
+ info
.reg_offset
;
4945 if (info
.reg_words
* UNITS_PER_WORD
== GET_MODE_SIZE (inner
))
4947 /* Real part in registers, imaginary part on stack. */
4948 gcc_assert (info
.stack_words
== info
.reg_words
);
4949 return gen_rtx_REG (inner
, regno
);
4953 gcc_assert (info
.stack_words
== 0);
4954 real
= gen_rtx_EXPR_LIST (VOIDmode
,
4955 gen_rtx_REG (inner
, regno
),
4957 imag
= gen_rtx_EXPR_LIST (VOIDmode
,
4959 regno
+ info
.reg_words
/ 2),
4960 GEN_INT (GET_MODE_SIZE (inner
)));
4961 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, real
, imag
));
4965 return gen_rtx_REG (mode
, mips_arg_regno (&info
, TARGET_HARD_FLOAT
));
4968 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
4971 mips_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
4972 const_tree type
, bool named
)
4974 struct mips_arg_info info
;
4976 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
4979 cum
->gp_reg_found
= true;
4981 /* See the comment above the CUMULATIVE_ARGS structure in mips.h for
4982 an explanation of what this code does. It assumes that we're using
4983 either the o32 or the o64 ABI, both of which pass at most 2 arguments
4985 if (cum
->arg_number
< 2 && info
.fpr_p
)
4986 cum
->fp_code
+= (mode
== SFmode
? 1 : 2) << (cum
->arg_number
* 2);
4988 /* Advance the register count. This has the effect of setting
4989 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
4990 argument required us to skip the final GPR and pass the whole
4991 argument on the stack. */
4992 if (mips_abi
!= ABI_EABI
|| !info
.fpr_p
)
4993 cum
->num_gprs
= info
.reg_offset
+ info
.reg_words
;
4994 else if (info
.reg_words
> 0)
4995 cum
->num_fprs
+= MAX_FPRS_PER_FMT
;
4997 /* Advance the stack word count. */
4998 if (info
.stack_words
> 0)
4999 cum
->stack_words
= info
.stack_offset
+ info
.stack_words
;
5004 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5007 mips_arg_partial_bytes (CUMULATIVE_ARGS
*cum
,
5008 enum machine_mode mode
, tree type
, bool named
)
5010 struct mips_arg_info info
;
5012 mips_get_arg_info (&info
, cum
, mode
, type
, named
);
5013 return info
.stack_words
> 0 ? info
.reg_words
* UNITS_PER_WORD
: 0;
5016 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5017 least PARM_BOUNDARY bits of alignment, but will be given anything up
5018 to STACK_BOUNDARY bits if the type requires it. */
5021 mips_function_arg_boundary (enum machine_mode mode
, const_tree type
)
5023 unsigned int alignment
;
5025 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
5026 if (alignment
< PARM_BOUNDARY
)
5027 alignment
= PARM_BOUNDARY
;
5028 if (alignment
> STACK_BOUNDARY
)
5029 alignment
= STACK_BOUNDARY
;
5033 /* Return true if FUNCTION_ARG_PADDING (MODE, TYPE) should return
5034 upward rather than downward. In other words, return true if the
5035 first byte of the stack slot has useful data, false if the last
5039 mips_pad_arg_upward (enum machine_mode mode
, const_tree type
)
5041 /* On little-endian targets, the first byte of every stack argument
5042 is passed in the first byte of the stack slot. */
5043 if (!BYTES_BIG_ENDIAN
)
5046 /* Otherwise, integral types are padded downward: the last byte of a
5047 stack argument is passed in the last byte of the stack slot. */
5049 ? (INTEGRAL_TYPE_P (type
)
5050 || POINTER_TYPE_P (type
)
5051 || FIXED_POINT_TYPE_P (type
))
5052 : (SCALAR_INT_MODE_P (mode
)
5053 || ALL_SCALAR_FIXED_POINT_MODE_P (mode
)))
5056 /* Big-endian o64 pads floating-point arguments downward. */
5057 if (mips_abi
== ABI_O64
)
5058 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5061 /* Other types are padded upward for o32, o64, n32 and n64. */
5062 if (mips_abi
!= ABI_EABI
)
5065 /* Arguments smaller than a stack slot are padded downward. */
5066 if (mode
!= BLKmode
)
5067 return GET_MODE_BITSIZE (mode
) >= PARM_BOUNDARY
;
5069 return int_size_in_bytes (type
) >= (PARM_BOUNDARY
/ BITS_PER_UNIT
);
5072 /* Likewise BLOCK_REG_PADDING (MODE, TYPE, ...). Return !BYTES_BIG_ENDIAN
5073 if the least significant byte of the register has useful data. Return
5074 the opposite if the most significant byte does. */
5077 mips_pad_reg_upward (enum machine_mode mode
, tree type
)
5079 /* No shifting is required for floating-point arguments. */
5080 if (type
!= 0 ? FLOAT_TYPE_P (type
) : GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5081 return !BYTES_BIG_ENDIAN
;
5083 /* Otherwise, apply the same padding to register arguments as we do
5084 to stack arguments. */
5085 return mips_pad_arg_upward (mode
, type
);
5088 /* Return nonzero when an argument must be passed by reference. */
5091 mips_pass_by_reference (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5092 enum machine_mode mode
, const_tree type
,
5093 bool named ATTRIBUTE_UNUSED
)
5095 if (mips_abi
== ABI_EABI
)
5099 /* ??? How should SCmode be handled? */
5100 if (mode
== DImode
|| mode
== DFmode
5101 || mode
== DQmode
|| mode
== UDQmode
5102 || mode
== DAmode
|| mode
== UDAmode
)
5105 size
= type
? int_size_in_bytes (type
) : GET_MODE_SIZE (mode
);
5106 return size
== -1 || size
> UNITS_PER_WORD
;
5110 /* If we have a variable-sized parameter, we have no choice. */
5111 return targetm
.calls
.must_pass_in_stack (mode
, type
);
5115 /* Implement TARGET_CALLEE_COPIES. */
5118 mips_callee_copies (CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
,
5119 enum machine_mode mode ATTRIBUTE_UNUSED
,
5120 const_tree type ATTRIBUTE_UNUSED
, bool named
)
5122 return mips_abi
== ABI_EABI
&& named
;
5125 /* See whether VALTYPE is a record whose fields should be returned in
5126 floating-point registers. If so, return the number of fields and
5127 list them in FIELDS (which should have two elements). Return 0
5130 For n32 & n64, a structure with one or two fields is returned in
5131 floating-point registers as long as every field has a floating-point
5135 mips_fpr_return_fields (const_tree valtype
, tree
*fields
)
5143 if (TREE_CODE (valtype
) != RECORD_TYPE
)
5147 for (field
= TYPE_FIELDS (valtype
); field
!= 0; field
= DECL_CHAIN (field
))
5149 if (TREE_CODE (field
) != FIELD_DECL
)
5152 if (!SCALAR_FLOAT_TYPE_P (TREE_TYPE (field
)))
5158 fields
[i
++] = field
;
5163 /* Implement TARGET_RETURN_IN_MSB. For n32 & n64, we should return
5164 a value in the most significant part of $2/$3 if:
5166 - the target is big-endian;
5168 - the value has a structure or union type (we generalize this to
5169 cover aggregates from other languages too); and
5171 - the structure is not returned in floating-point registers. */
5174 mips_return_in_msb (const_tree valtype
)
5178 return (TARGET_NEWABI
5179 && TARGET_BIG_ENDIAN
5180 && AGGREGATE_TYPE_P (valtype
)
5181 && mips_fpr_return_fields (valtype
, fields
) == 0);
5184 /* Return true if the function return value MODE will get returned in a
5185 floating-point register. */
5188 mips_return_mode_in_fpr_p (enum machine_mode mode
)
5190 return ((GET_MODE_CLASS (mode
) == MODE_FLOAT
5191 || GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
5192 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5193 && GET_MODE_UNIT_SIZE (mode
) <= UNITS_PER_HWFPVALUE
);
5196 /* Return the representation of an FPR return register when the
5197 value being returned in FP_RETURN has mode VALUE_MODE and the
5198 return type itself has mode TYPE_MODE. On NewABI targets,
5199 the two modes may be different for structures like:
5201 struct __attribute__((packed)) foo { float f; }
5203 where we return the SFmode value of "f" in FP_RETURN, but where
5204 the structure itself has mode BLKmode. */
5207 mips_return_fpr_single (enum machine_mode type_mode
,
5208 enum machine_mode value_mode
)
5212 x
= gen_rtx_REG (value_mode
, FP_RETURN
);
5213 if (type_mode
!= value_mode
)
5215 x
= gen_rtx_EXPR_LIST (VOIDmode
, x
, const0_rtx
);
5216 x
= gen_rtx_PARALLEL (type_mode
, gen_rtvec (1, x
));
5221 /* Return a composite value in a pair of floating-point registers.
5222 MODE1 and OFFSET1 are the mode and byte offset for the first value,
5223 likewise MODE2 and OFFSET2 for the second. MODE is the mode of the
5226 For n32 & n64, $f0 always holds the first value and $f2 the second.
5227 Otherwise the values are packed together as closely as possible. */
5230 mips_return_fpr_pair (enum machine_mode mode
,
5231 enum machine_mode mode1
, HOST_WIDE_INT offset1
,
5232 enum machine_mode mode2
, HOST_WIDE_INT offset2
)
5236 inc
= (TARGET_NEWABI
? 2 : MAX_FPRS_PER_FMT
);
5237 return gen_rtx_PARALLEL
5240 gen_rtx_EXPR_LIST (VOIDmode
,
5241 gen_rtx_REG (mode1
, FP_RETURN
),
5243 gen_rtx_EXPR_LIST (VOIDmode
,
5244 gen_rtx_REG (mode2
, FP_RETURN
+ inc
),
5245 GEN_INT (offset2
))));
5249 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5250 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5251 VALTYPE is null and MODE is the mode of the return value. */
5254 mips_function_value (const_tree valtype
, const_tree func
, enum machine_mode mode
)
5261 mode
= TYPE_MODE (valtype
);
5262 unsigned_p
= TYPE_UNSIGNED (valtype
);
5264 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5265 return values, promote the mode here too. */
5266 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
5268 /* Handle structures whose fields are returned in $f0/$f2. */
5269 switch (mips_fpr_return_fields (valtype
, fields
))
5272 return mips_return_fpr_single (mode
,
5273 TYPE_MODE (TREE_TYPE (fields
[0])));
5276 return mips_return_fpr_pair (mode
,
5277 TYPE_MODE (TREE_TYPE (fields
[0])),
5278 int_byte_position (fields
[0]),
5279 TYPE_MODE (TREE_TYPE (fields
[1])),
5280 int_byte_position (fields
[1]));
5283 /* If a value is passed in the most significant part of a register, see
5284 whether we have to round the mode up to a whole number of words. */
5285 if (mips_return_in_msb (valtype
))
5287 HOST_WIDE_INT size
= int_size_in_bytes (valtype
);
5288 if (size
% UNITS_PER_WORD
!= 0)
5290 size
+= UNITS_PER_WORD
- size
% UNITS_PER_WORD
;
5291 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
5295 /* For EABI, the class of return register depends entirely on MODE.
5296 For example, "struct { some_type x; }" and "union { some_type x; }"
5297 are returned in the same way as a bare "some_type" would be.
5298 Other ABIs only use FPRs for scalar, complex or vector types. */
5299 if (mips_abi
!= ABI_EABI
&& !FLOAT_TYPE_P (valtype
))
5300 return gen_rtx_REG (mode
, GP_RETURN
);
5305 /* Handle long doubles for n32 & n64. */
5307 return mips_return_fpr_pair (mode
,
5309 DImode
, GET_MODE_SIZE (mode
) / 2);
5311 if (mips_return_mode_in_fpr_p (mode
))
5313 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5314 return mips_return_fpr_pair (mode
,
5315 GET_MODE_INNER (mode
), 0,
5316 GET_MODE_INNER (mode
),
5317 GET_MODE_SIZE (mode
) / 2);
5319 return gen_rtx_REG (mode
, FP_RETURN
);
5323 return gen_rtx_REG (mode
, GP_RETURN
);
5326 /* Implement TARGET_RETURN_IN_MEMORY. Under the o32 and o64 ABIs,
5327 all BLKmode objects are returned in memory. Under the n32, n64
5328 and embedded ABIs, small structures are returned in a register.
5329 Objects with varying size must still be returned in memory, of
5333 mips_return_in_memory (const_tree type
, const_tree fndecl ATTRIBUTE_UNUSED
)
5335 return (TARGET_OLDABI
5336 ? TYPE_MODE (type
) == BLKmode
5337 : !IN_RANGE (int_size_in_bytes (type
), 0, 2 * UNITS_PER_WORD
));
5340 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5343 mips_setup_incoming_varargs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
5344 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
5347 CUMULATIVE_ARGS local_cum
;
5348 int gp_saved
, fp_saved
;
5350 /* The caller has advanced CUM up to, but not beyond, the last named
5351 argument. Advance a local copy of CUM past the last "real" named
5352 argument, to find out how many registers are left over. */
5354 mips_function_arg_advance (&local_cum
, mode
, type
, true);
5356 /* Found out how many registers we need to save. */
5357 gp_saved
= MAX_ARGS_IN_REGISTERS
- local_cum
.num_gprs
;
5358 fp_saved
= (EABI_FLOAT_VARARGS_P
5359 ? MAX_ARGS_IN_REGISTERS
- local_cum
.num_fprs
5368 ptr
= plus_constant (virtual_incoming_args_rtx
,
5369 REG_PARM_STACK_SPACE (cfun
->decl
)
5370 - gp_saved
* UNITS_PER_WORD
);
5371 mem
= gen_frame_mem (BLKmode
, ptr
);
5372 set_mem_alias_set (mem
, get_varargs_alias_set ());
5374 move_block_from_reg (local_cum
.num_gprs
+ GP_ARG_FIRST
,
5379 /* We can't use move_block_from_reg, because it will use
5381 enum machine_mode mode
;
5384 /* Set OFF to the offset from virtual_incoming_args_rtx of
5385 the first float register. The FP save area lies below
5386 the integer one, and is aligned to UNITS_PER_FPVALUE bytes. */
5387 off
= (-gp_saved
* UNITS_PER_WORD
) & -UNITS_PER_FPVALUE
;
5388 off
-= fp_saved
* UNITS_PER_FPREG
;
5390 mode
= TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5392 for (i
= local_cum
.num_fprs
; i
< MAX_ARGS_IN_REGISTERS
;
5393 i
+= MAX_FPRS_PER_FMT
)
5397 ptr
= plus_constant (virtual_incoming_args_rtx
, off
);
5398 mem
= gen_frame_mem (mode
, ptr
);
5399 set_mem_alias_set (mem
, get_varargs_alias_set ());
5400 mips_emit_move (mem
, gen_rtx_REG (mode
, FP_ARG_FIRST
+ i
));
5401 off
+= UNITS_PER_HWFPVALUE
;
5405 if (REG_PARM_STACK_SPACE (cfun
->decl
) == 0)
5406 cfun
->machine
->varargs_size
= (gp_saved
* UNITS_PER_WORD
5407 + fp_saved
* UNITS_PER_FPREG
);
5410 /* Implement TARGET_BUILTIN_VA_LIST. */
5413 mips_build_builtin_va_list (void)
5415 if (EABI_FLOAT_VARARGS_P
)
5417 /* We keep 3 pointers, and two offsets.
5419 Two pointers are to the overflow area, which starts at the CFA.
5420 One of these is constant, for addressing into the GPR save area
5421 below it. The other is advanced up the stack through the
5424 The third pointer is to the bottom of the GPR save area.
5425 Since the FPR save area is just below it, we can address
5426 FPR slots off this pointer.
5428 We also keep two one-byte offsets, which are to be subtracted
5429 from the constant pointers to yield addresses in the GPR and
5430 FPR save areas. These are downcounted as float or non-float
5431 arguments are used, and when they get to zero, the argument
5432 must be obtained from the overflow region. */
5433 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
, f_res
, record
;
5436 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
5438 f_ovfl
= build_decl (BUILTINS_LOCATION
,
5439 FIELD_DECL
, get_identifier ("__overflow_argptr"),
5441 f_gtop
= build_decl (BUILTINS_LOCATION
,
5442 FIELD_DECL
, get_identifier ("__gpr_top"),
5444 f_ftop
= build_decl (BUILTINS_LOCATION
,
5445 FIELD_DECL
, get_identifier ("__fpr_top"),
5447 f_goff
= build_decl (BUILTINS_LOCATION
,
5448 FIELD_DECL
, get_identifier ("__gpr_offset"),
5449 unsigned_char_type_node
);
5450 f_foff
= build_decl (BUILTINS_LOCATION
,
5451 FIELD_DECL
, get_identifier ("__fpr_offset"),
5452 unsigned_char_type_node
);
5453 /* Explicitly pad to the size of a pointer, so that -Wpadded won't
5454 warn on every user file. */
5455 index
= build_int_cst (NULL_TREE
, GET_MODE_SIZE (ptr_mode
) - 2 - 1);
5456 array
= build_array_type (unsigned_char_type_node
,
5457 build_index_type (index
));
5458 f_res
= build_decl (BUILTINS_LOCATION
,
5459 FIELD_DECL
, get_identifier ("__reserved"), array
);
5461 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
5462 DECL_FIELD_CONTEXT (f_gtop
) = record
;
5463 DECL_FIELD_CONTEXT (f_ftop
) = record
;
5464 DECL_FIELD_CONTEXT (f_goff
) = record
;
5465 DECL_FIELD_CONTEXT (f_foff
) = record
;
5466 DECL_FIELD_CONTEXT (f_res
) = record
;
5468 TYPE_FIELDS (record
) = f_ovfl
;
5469 DECL_CHAIN (f_ovfl
) = f_gtop
;
5470 DECL_CHAIN (f_gtop
) = f_ftop
;
5471 DECL_CHAIN (f_ftop
) = f_goff
;
5472 DECL_CHAIN (f_goff
) = f_foff
;
5473 DECL_CHAIN (f_foff
) = f_res
;
5475 layout_type (record
);
5478 else if (TARGET_IRIX6
)
5479 /* On IRIX 6, this type is 'char *'. */
5480 return build_pointer_type (char_type_node
);
5482 /* Otherwise, we use 'void *'. */
5483 return ptr_type_node
;
5486 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
5489 mips_va_start (tree valist
, rtx nextarg
)
5491 if (EABI_FLOAT_VARARGS_P
)
5493 const CUMULATIVE_ARGS
*cum
;
5494 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5495 tree ovfl
, gtop
, ftop
, goff
, foff
;
5497 int gpr_save_area_size
;
5498 int fpr_save_area_size
;
5501 cum
= &crtl
->args
.info
;
5503 = (MAX_ARGS_IN_REGISTERS
- cum
->num_gprs
) * UNITS_PER_WORD
;
5505 = (MAX_ARGS_IN_REGISTERS
- cum
->num_fprs
) * UNITS_PER_FPREG
;
5507 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5508 f_gtop
= DECL_CHAIN (f_ovfl
);
5509 f_ftop
= DECL_CHAIN (f_gtop
);
5510 f_goff
= DECL_CHAIN (f_ftop
);
5511 f_foff
= DECL_CHAIN (f_goff
);
5513 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5515 gtop
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
), valist
, f_gtop
,
5517 ftop
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
), valist
, f_ftop
,
5519 goff
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
), valist
, f_goff
,
5521 foff
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
), valist
, f_foff
,
5524 /* Emit code to initialize OVFL, which points to the next varargs
5525 stack argument. CUM->STACK_WORDS gives the number of stack
5526 words used by named arguments. */
5527 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
5528 if (cum
->stack_words
> 0)
5529 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), t
,
5530 size_int (cum
->stack_words
* UNITS_PER_WORD
));
5531 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
5532 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5534 /* Emit code to initialize GTOP, the top of the GPR save area. */
5535 t
= make_tree (TREE_TYPE (gtop
), virtual_incoming_args_rtx
);
5536 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gtop
), gtop
, t
);
5537 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5539 /* Emit code to initialize FTOP, the top of the FPR save area.
5540 This address is gpr_save_area_bytes below GTOP, rounded
5541 down to the next fp-aligned boundary. */
5542 t
= make_tree (TREE_TYPE (ftop
), virtual_incoming_args_rtx
);
5543 fpr_offset
= gpr_save_area_size
+ UNITS_PER_FPVALUE
- 1;
5544 fpr_offset
&= -UNITS_PER_FPVALUE
;
5546 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ftop
), t
,
5547 size_int (-fpr_offset
));
5548 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ftop
), ftop
, t
);
5549 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5551 /* Emit code to initialize GOFF, the offset from GTOP of the
5552 next GPR argument. */
5553 t
= build2 (MODIFY_EXPR
, TREE_TYPE (goff
), goff
,
5554 build_int_cst (TREE_TYPE (goff
), gpr_save_area_size
));
5555 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5557 /* Likewise emit code to initialize FOFF, the offset from FTOP
5558 of the next FPR argument. */
5559 t
= build2 (MODIFY_EXPR
, TREE_TYPE (foff
), foff
,
5560 build_int_cst (TREE_TYPE (foff
), fpr_save_area_size
));
5561 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5565 nextarg
= plus_constant (nextarg
, -cfun
->machine
->varargs_size
);
5566 std_expand_builtin_va_start (valist
, nextarg
);
5570 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
5573 mips_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
5579 indirect_p
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, 0);
5581 type
= build_pointer_type (type
);
5583 if (!EABI_FLOAT_VARARGS_P
)
5584 addr
= std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
5587 tree f_ovfl
, f_gtop
, f_ftop
, f_goff
, f_foff
;
5588 tree ovfl
, top
, off
, align
;
5589 HOST_WIDE_INT size
, rsize
, osize
;
5592 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
5593 f_gtop
= DECL_CHAIN (f_ovfl
);
5594 f_ftop
= DECL_CHAIN (f_gtop
);
5595 f_goff
= DECL_CHAIN (f_ftop
);
5596 f_foff
= DECL_CHAIN (f_goff
);
5600 TOP be the top of the GPR or FPR save area;
5601 OFF be the offset from TOP of the next register;
5602 ADDR_RTX be the address of the argument;
5603 SIZE be the number of bytes in the argument type;
5604 RSIZE be the number of bytes used to store the argument
5605 when it's in the register save area; and
5606 OSIZE be the number of bytes used to store it when it's
5607 in the stack overflow area.
5609 The code we want is:
5611 1: off &= -rsize; // round down
5614 4: addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0);
5619 9: ovfl = ((intptr_t) ovfl + osize - 1) & -osize;
5620 10: addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0);
5624 [1] and [9] can sometimes be optimized away. */
5626 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
,
5628 size
= int_size_in_bytes (type
);
5630 if (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
5631 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_FPVALUE
)
5633 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_ftop
),
5634 unshare_expr (valist
), f_ftop
, NULL_TREE
);
5635 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_foff
),
5636 unshare_expr (valist
), f_foff
, NULL_TREE
);
5638 /* When va_start saves FPR arguments to the stack, each slot
5639 takes up UNITS_PER_HWFPVALUE bytes, regardless of the
5640 argument's precision. */
5641 rsize
= UNITS_PER_HWFPVALUE
;
5643 /* Overflow arguments are padded to UNITS_PER_WORD bytes
5644 (= PARM_BOUNDARY bits). This can be different from RSIZE
5647 (1) On 32-bit targets when TYPE is a structure such as:
5649 struct s { float f; };
5651 Such structures are passed in paired FPRs, so RSIZE
5652 will be 8 bytes. However, the structure only takes
5653 up 4 bytes of memory, so OSIZE will only be 4.
5655 (2) In combinations such as -mgp64 -msingle-float
5656 -fshort-double. Doubles passed in registers will then take
5657 up 4 (UNITS_PER_HWFPVALUE) bytes, but those passed on the
5658 stack take up UNITS_PER_WORD bytes. */
5659 osize
= MAX (GET_MODE_SIZE (TYPE_MODE (type
)), UNITS_PER_WORD
);
5663 top
= build3 (COMPONENT_REF
, TREE_TYPE (f_gtop
),
5664 unshare_expr (valist
), f_gtop
, NULL_TREE
);
5665 off
= build3 (COMPONENT_REF
, TREE_TYPE (f_goff
),
5666 unshare_expr (valist
), f_goff
, NULL_TREE
);
5667 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5668 if (rsize
> UNITS_PER_WORD
)
5670 /* [1] Emit code for: off &= -rsize. */
5671 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (off
), unshare_expr (off
),
5672 build_int_cst (TREE_TYPE (off
), -rsize
));
5673 gimplify_assign (unshare_expr (off
), t
, pre_p
);
5678 /* [2] Emit code to branch if off == 0. */
5679 t
= build2 (NE_EXPR
, boolean_type_node
, off
,
5680 build_int_cst (TREE_TYPE (off
), 0));
5681 addr
= build3 (COND_EXPR
, ptr_type_node
, t
, NULL_TREE
, NULL_TREE
);
5683 /* [5] Emit code for: off -= rsize. We do this as a form of
5684 post-decrement not available to C. */
5685 t
= fold_convert (TREE_TYPE (off
), build_int_cst (NULL_TREE
, rsize
));
5686 t
= build2 (POSTDECREMENT_EXPR
, TREE_TYPE (off
), off
, t
);
5688 /* [4] Emit code for:
5689 addr_rtx = top - off + (BYTES_BIG_ENDIAN ? RSIZE - SIZE : 0). */
5690 t
= fold_convert (sizetype
, t
);
5691 t
= fold_build1 (NEGATE_EXPR
, sizetype
, t
);
5692 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (top
), top
, t
);
5693 if (BYTES_BIG_ENDIAN
&& rsize
> size
)
5695 u
= size_int (rsize
- size
);
5696 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5698 COND_EXPR_THEN (addr
) = t
;
5700 if (osize
> UNITS_PER_WORD
)
5702 /* [9] Emit: ovfl = ((intptr_t) ovfl + osize - 1) & -osize. */
5703 u
= size_int (osize
- 1);
5704 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
),
5705 unshare_expr (ovfl
), u
);
5706 t
= fold_convert (sizetype
, t
);
5707 u
= size_int (-osize
);
5708 t
= build2 (BIT_AND_EXPR
, sizetype
, t
, u
);
5709 t
= fold_convert (TREE_TYPE (ovfl
), t
);
5710 align
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
),
5711 unshare_expr (ovfl
), t
);
5716 /* [10, 11] Emit code for:
5717 addr_rtx = ovfl + (BYTES_BIG_ENDIAN ? OSIZE - SIZE : 0)
5719 u
= fold_convert (TREE_TYPE (ovfl
), build_int_cst (NULL_TREE
, osize
));
5720 t
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (ovfl
), ovfl
, u
);
5721 if (BYTES_BIG_ENDIAN
&& osize
> size
)
5723 u
= size_int (osize
- size
);
5724 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (t
), t
, u
);
5727 /* String [9] and [10, 11] together. */
5729 t
= build2 (COMPOUND_EXPR
, TREE_TYPE (t
), align
, t
);
5730 COND_EXPR_ELSE (addr
) = t
;
5732 addr
= fold_convert (build_pointer_type (type
), addr
);
5733 addr
= build_va_arg_indirect_ref (addr
);
5737 addr
= build_va_arg_indirect_ref (addr
);
5742 /* Start a definition of function NAME. MIPS16_P indicates whether the
5743 function contains MIPS16 code. */
5746 mips_start_function_definition (const char *name
, bool mips16_p
)
5749 fprintf (asm_out_file
, "\t.set\tmips16\n");
5751 fprintf (asm_out_file
, "\t.set\tnomips16\n");
5753 if (!flag_inhibit_size_directive
)
5755 fputs ("\t.ent\t", asm_out_file
);
5756 assemble_name (asm_out_file
, name
);
5757 fputs ("\n", asm_out_file
);
5760 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file
, name
, "function");
5762 /* Start the definition proper. */
5763 assemble_name (asm_out_file
, name
);
5764 fputs (":\n", asm_out_file
);
5767 /* End a function definition started by mips_start_function_definition. */
5770 mips_end_function_definition (const char *name
)
5772 if (!flag_inhibit_size_directive
)
5774 fputs ("\t.end\t", asm_out_file
);
5775 assemble_name (asm_out_file
, name
);
5776 fputs ("\n", asm_out_file
);
5780 /* Return true if calls to X can use R_MIPS_CALL* relocations. */
5783 mips_ok_for_lazy_binding_p (rtx x
)
5785 return (TARGET_USE_GOT
5786 && GET_CODE (x
) == SYMBOL_REF
5787 && !SYMBOL_REF_BIND_NOW_P (x
)
5788 && !mips_symbol_binds_local_p (x
));
5791 /* Load function address ADDR into register DEST. TYPE is as for
5792 mips_expand_call. Return true if we used an explicit lazy-binding
5796 mips_load_call_address (enum mips_call_type type
, rtx dest
, rtx addr
)
5798 /* If we're generating PIC, and this call is to a global function,
5799 try to allow its address to be resolved lazily. This isn't
5800 possible for sibcalls when $gp is call-saved because the value
5801 of $gp on entry to the stub would be our caller's gp, not ours. */
5802 if (TARGET_EXPLICIT_RELOCS
5803 && !(type
== MIPS_CALL_SIBCALL
&& TARGET_CALL_SAVED_GP
)
5804 && mips_ok_for_lazy_binding_p (addr
))
5806 addr
= mips_got_load (dest
, addr
, SYMBOL_GOTOFF_CALL
);
5807 emit_insn (gen_rtx_SET (VOIDmode
, dest
, addr
));
5812 mips_emit_move (dest
, addr
);
5817 /* Each locally-defined hard-float MIPS16 function has a local symbol
5818 associated with it. This hash table maps the function symbol (FUNC)
5819 to the local symbol (LOCAL). */
5820 struct GTY(()) mips16_local_alias
{
5824 static GTY ((param_is (struct mips16_local_alias
))) htab_t mips16_local_aliases
;
5826 /* Hash table callbacks for mips16_local_aliases. */
5829 mips16_local_aliases_hash (const void *entry
)
5831 const struct mips16_local_alias
*alias
;
5833 alias
= (const struct mips16_local_alias
*) entry
;
5834 return htab_hash_string (XSTR (alias
->func
, 0));
5838 mips16_local_aliases_eq (const void *entry1
, const void *entry2
)
5840 const struct mips16_local_alias
*alias1
, *alias2
;
5842 alias1
= (const struct mips16_local_alias
*) entry1
;
5843 alias2
= (const struct mips16_local_alias
*) entry2
;
5844 return rtx_equal_p (alias1
->func
, alias2
->func
);
5847 /* FUNC is the symbol for a locally-defined hard-float MIPS16 function.
5848 Return a local alias for it, creating a new one if necessary. */
5851 mips16_local_alias (rtx func
)
5853 struct mips16_local_alias
*alias
, tmp_alias
;
5856 /* Create the hash table if this is the first call. */
5857 if (mips16_local_aliases
== NULL
)
5858 mips16_local_aliases
= htab_create_ggc (37, mips16_local_aliases_hash
,
5859 mips16_local_aliases_eq
, NULL
);
5861 /* Look up the function symbol, creating a new entry if need be. */
5862 tmp_alias
.func
= func
;
5863 slot
= htab_find_slot (mips16_local_aliases
, &tmp_alias
, INSERT
);
5864 gcc_assert (slot
!= NULL
);
5866 alias
= (struct mips16_local_alias
*) *slot
;
5869 const char *func_name
, *local_name
;
5872 /* Create a new SYMBOL_REF for the local symbol. The choice of
5873 __fn_local_* is based on the __fn_stub_* names that we've
5874 traditionally used for the non-MIPS16 stub. */
5875 func_name
= targetm
.strip_name_encoding (XSTR (func
, 0));
5876 local_name
= ACONCAT (("__fn_local_", func_name
, NULL
));
5877 local
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (local_name
));
5878 SYMBOL_REF_FLAGS (local
) = SYMBOL_REF_FLAGS (func
) | SYMBOL_FLAG_LOCAL
;
5880 /* Create a new structure to represent the mapping. */
5881 alias
= ggc_alloc_mips16_local_alias ();
5883 alias
->local
= local
;
5886 return alias
->local
;
5889 /* A chained list of functions for which mips16_build_call_stub has already
5890 generated a stub. NAME is the name of the function and FP_RET_P is true
5891 if the function returns a value in floating-point registers. */
5892 struct mips16_stub
{
5893 struct mips16_stub
*next
;
5897 static struct mips16_stub
*mips16_stubs
;
5899 /* Return a SYMBOL_REF for a MIPS16 function called NAME. */
5902 mips16_stub_function (const char *name
)
5906 x
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
5907 SYMBOL_REF_FLAGS (x
) |= (SYMBOL_FLAG_EXTERNAL
| SYMBOL_FLAG_FUNCTION
);
5911 /* Return the two-character string that identifies floating-point
5912 return mode MODE in the name of a MIPS16 function stub. */
5915 mips16_call_stub_mode_suffix (enum machine_mode mode
)
5919 else if (mode
== DFmode
)
5921 else if (mode
== SCmode
)
5923 else if (mode
== DCmode
)
5925 else if (mode
== V2SFmode
)
5931 /* Write instructions to move a 32-bit value between general register
5932 GPREG and floating-point register FPREG. DIRECTION is 't' to move
5933 from GPREG to FPREG and 'f' to move in the opposite direction. */
5936 mips_output_32bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5938 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5939 reg_names
[gpreg
], reg_names
[fpreg
]);
5942 /* Likewise for 64-bit values. */
5945 mips_output_64bit_xfer (char direction
, unsigned int gpreg
, unsigned int fpreg
)
5948 fprintf (asm_out_file
, "\tdm%cc1\t%s,%s\n", direction
,
5949 reg_names
[gpreg
], reg_names
[fpreg
]);
5950 else if (TARGET_FLOAT64
)
5952 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5953 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5954 fprintf (asm_out_file
, "\tm%chc1\t%s,%s\n", direction
,
5955 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
]);
5959 /* Move the least-significant word. */
5960 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5961 reg_names
[gpreg
+ TARGET_BIG_ENDIAN
], reg_names
[fpreg
]);
5962 /* ...then the most significant word. */
5963 fprintf (asm_out_file
, "\tm%cc1\t%s,%s\n", direction
,
5964 reg_names
[gpreg
+ TARGET_LITTLE_ENDIAN
], reg_names
[fpreg
+ 1]);
5968 /* Write out code to move floating-point arguments into or out of
5969 general registers. FP_CODE is the code describing which arguments
5970 are present (see the comment above the definition of CUMULATIVE_ARGS
5971 in mips.h). DIRECTION is as for mips_output_32bit_xfer. */
5974 mips_output_args_xfer (int fp_code
, char direction
)
5976 unsigned int gparg
, fparg
, f
;
5977 CUMULATIVE_ARGS cum
;
5979 /* This code only works for o32 and o64. */
5980 gcc_assert (TARGET_OLDABI
);
5982 mips_init_cumulative_args (&cum
, NULL
);
5984 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
5986 enum machine_mode mode
;
5987 struct mips_arg_info info
;
5991 else if ((f
& 3) == 2)
5996 mips_get_arg_info (&info
, &cum
, mode
, NULL
, true);
5997 gparg
= mips_arg_regno (&info
, false);
5998 fparg
= mips_arg_regno (&info
, true);
6001 mips_output_32bit_xfer (direction
, gparg
, fparg
);
6003 mips_output_64bit_xfer (direction
, gparg
, fparg
);
6005 mips_function_arg_advance (&cum
, mode
, NULL
, true);
6009 /* Write a MIPS16 stub for the current function. This stub is used
6010 for functions which take arguments in the floating-point registers.
6011 It is normal-mode code that moves the floating-point arguments
6012 into the general registers and then jumps to the MIPS16 code. */
6015 mips16_build_function_stub (void)
6017 const char *fnname
, *alias_name
, *separator
;
6018 char *secname
, *stubname
;
6023 /* Create the name of the stub, and its unique section. */
6024 symbol
= XEXP (DECL_RTL (current_function_decl
), 0);
6025 alias
= mips16_local_alias (symbol
);
6027 fnname
= targetm
.strip_name_encoding (XSTR (symbol
, 0));
6028 alias_name
= targetm
.strip_name_encoding (XSTR (alias
, 0));
6029 secname
= ACONCAT ((".mips16.fn.", fnname
, NULL
));
6030 stubname
= ACONCAT (("__fn_stub_", fnname
, NULL
));
6032 /* Build a decl for the stub. */
6033 stubdecl
= build_decl (BUILTINS_LOCATION
,
6034 FUNCTION_DECL
, get_identifier (stubname
),
6035 build_function_type (void_type_node
, NULL_TREE
));
6036 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6037 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6038 RESULT_DECL
, NULL_TREE
, void_type_node
);
6040 /* Output a comment. */
6041 fprintf (asm_out_file
, "\t# Stub function for %s (",
6042 current_function_name ());
6044 for (f
= (unsigned int) crtl
->args
.info
.fp_code
; f
!= 0; f
>>= 2)
6046 fprintf (asm_out_file
, "%s%s", separator
,
6047 (f
& 3) == 1 ? "float" : "double");
6050 fprintf (asm_out_file
, ")\n");
6052 /* Start the function definition. */
6053 assemble_start_function (stubdecl
, stubname
);
6054 mips_start_function_definition (stubname
, false);
6056 /* If generating pic2 code, either set up the global pointer or
6058 if (TARGET_ABICALLS_PIC2
)
6060 if (TARGET_ABSOLUTE_ABICALLS
)
6061 fprintf (asm_out_file
, "\t.option\tpic0\n");
6064 output_asm_insn ("%(.cpload\t%^%)", NULL
);
6065 /* Emit an R_MIPS_NONE relocation to tell the linker what the
6066 target function is. Use a local GOT access when loading the
6067 symbol, to cut down on the number of unnecessary GOT entries
6068 for stubs that aren't needed. */
6069 output_asm_insn (".reloc\t0,R_MIPS_NONE,%0", &symbol
);
6074 /* Load the address of the MIPS16 function into $25. Do this first so
6075 that targets with coprocessor interlocks can use an MFC1 to fill the
6077 output_asm_insn ("la\t%^,%0", &symbol
);
6079 /* Move the arguments from floating-point registers to general registers. */
6080 mips_output_args_xfer (crtl
->args
.info
.fp_code
, 'f');
6082 /* Jump to the MIPS16 function. */
6083 output_asm_insn ("jr\t%^", NULL
);
6085 if (TARGET_ABICALLS_PIC2
&& TARGET_ABSOLUTE_ABICALLS
)
6086 fprintf (asm_out_file
, "\t.option\tpic2\n");
6088 mips_end_function_definition (stubname
);
6090 /* If the linker needs to create a dynamic symbol for the target
6091 function, it will associate the symbol with the stub (which,
6092 unlike the target function, follows the proper calling conventions).
6093 It is therefore useful to have a local alias for the target function,
6094 so that it can still be identified as MIPS16 code. As an optimization,
6095 this symbol can also be used for indirect MIPS16 references from
6096 within this file. */
6097 ASM_OUTPUT_DEF (asm_out_file
, alias_name
, fnname
);
6099 switch_to_section (function_section (current_function_decl
));
6102 /* The current function is a MIPS16 function that returns a value in an FPR.
6103 Copy the return value from its soft-float to its hard-float location.
6104 libgcc2 has special non-MIPS16 helper functions for each case. */
6107 mips16_copy_fpr_return_value (void)
6109 rtx fn
, insn
, retval
;
6111 enum machine_mode return_mode
;
6114 return_type
= DECL_RESULT (current_function_decl
);
6115 return_mode
= DECL_MODE (return_type
);
6117 name
= ACONCAT (("__mips16_ret_",
6118 mips16_call_stub_mode_suffix (return_mode
),
6120 fn
= mips16_stub_function (name
);
6122 /* The function takes arguments in $2 (and possibly $3), so calls
6123 to it cannot be lazily bound. */
6124 SYMBOL_REF_FLAGS (fn
) |= SYMBOL_FLAG_BIND_NOW
;
6126 /* Model the call as something that takes the GPR return value as
6127 argument and returns an "updated" value. */
6128 retval
= gen_rtx_REG (return_mode
, GP_RETURN
);
6129 insn
= mips_expand_call (MIPS_CALL_EPILOGUE
, retval
, fn
,
6130 const0_rtx
, NULL_RTX
, false);
6131 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), retval
);
6134 /* Consider building a stub for a MIPS16 call to function *FN_PTR.
6135 RETVAL is the location of the return value, or null if this is
6136 a "call" rather than a "call_value". ARGS_SIZE is the size of the
6137 arguments and FP_CODE is the code built by mips_function_arg;
6138 see the comment before the fp_code field in CUMULATIVE_ARGS for details.
6140 There are three alternatives:
6142 - If a stub was needed, emit the call and return the call insn itself.
6144 - If we can avoid using a stub by redirecting the call, set *FN_PTR
6145 to the new target and return null.
6147 - If *FN_PTR doesn't need a stub, return null and leave *FN_PTR
6150 A stub is needed for calls to functions that, in normal mode,
6151 receive arguments in FPRs or return values in FPRs. The stub
6152 copies the arguments from their soft-float positions to their
6153 hard-float positions, calls the real function, then copies the
6154 return value from its hard-float position to its soft-float
6157 We can emit a JAL to *FN_PTR even when *FN_PTR might need a stub.
6158 If *FN_PTR turns out to be to a non-MIPS16 function, the linker
6159 automatically redirects the JAL to the stub, otherwise the JAL
6160 continues to call FN directly. */
6163 mips16_build_call_stub (rtx retval
, rtx
*fn_ptr
, rtx args_size
, int fp_code
)
6167 struct mips16_stub
*l
;
6170 /* We don't need to do anything if we aren't in MIPS16 mode, or if
6171 we were invoked with the -msoft-float option. */
6172 if (!TARGET_MIPS16
|| TARGET_SOFT_FLOAT_ABI
)
6175 /* Figure out whether the value might come back in a floating-point
6177 fp_ret_p
= retval
&& mips_return_mode_in_fpr_p (GET_MODE (retval
));
6179 /* We don't need to do anything if there were no floating-point
6180 arguments and the value will not be returned in a floating-point
6182 if (fp_code
== 0 && !fp_ret_p
)
6185 /* We don't need to do anything if this is a call to a special
6186 MIPS16 support function. */
6188 if (mips16_stub_function_p (fn
))
6191 /* This code will only work for o32 and o64 abis. The other ABI's
6192 require more sophisticated support. */
6193 gcc_assert (TARGET_OLDABI
);
6195 /* If we're calling via a function pointer, use one of the magic
6196 libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
6197 Each stub expects the function address to arrive in register $2. */
6198 if (GET_CODE (fn
) != SYMBOL_REF
6199 || !call_insn_operand (fn
, VOIDmode
))
6202 rtx stub_fn
, insn
, addr
;
6205 /* If this is a locally-defined and locally-binding function,
6206 avoid the stub by calling the local alias directly. */
6207 if (mips16_local_function_p (fn
))
6209 *fn_ptr
= mips16_local_alias (fn
);
6213 /* Create a SYMBOL_REF for the libgcc.a function. */
6215 sprintf (buf
, "__mips16_call_stub_%s_%d",
6216 mips16_call_stub_mode_suffix (GET_MODE (retval
)),
6219 sprintf (buf
, "__mips16_call_stub_%d", fp_code
);
6220 stub_fn
= mips16_stub_function (buf
);
6222 /* The function uses $2 as an argument, so calls to it
6223 cannot be lazily bound. */
6224 SYMBOL_REF_FLAGS (stub_fn
) |= SYMBOL_FLAG_BIND_NOW
;
6226 /* Load the target function into $2. */
6227 addr
= gen_rtx_REG (Pmode
, GP_REG_FIRST
+ 2);
6228 lazy_p
= mips_load_call_address (MIPS_CALL_NORMAL
, addr
, fn
);
6230 /* Emit the call. */
6231 insn
= mips_expand_call (MIPS_CALL_NORMAL
, retval
, stub_fn
,
6232 args_size
, NULL_RTX
, lazy_p
);
6234 /* Tell GCC that this call does indeed use the value of $2. */
6235 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), addr
);
6237 /* If we are handling a floating-point return value, we need to
6238 save $18 in the function prologue. Putting a note on the
6239 call will mean that df_regs_ever_live_p ($18) will be true if the
6240 call is not eliminated, and we can check that in the prologue
6243 CALL_INSN_FUNCTION_USAGE (insn
) =
6244 gen_rtx_EXPR_LIST (VOIDmode
,
6245 gen_rtx_CLOBBER (VOIDmode
,
6246 gen_rtx_REG (word_mode
, 18)),
6247 CALL_INSN_FUNCTION_USAGE (insn
));
6252 /* We know the function we are going to call. If we have already
6253 built a stub, we don't need to do anything further. */
6254 fnname
= targetm
.strip_name_encoding (XSTR (fn
, 0));
6255 for (l
= mips16_stubs
; l
!= NULL
; l
= l
->next
)
6256 if (strcmp (l
->name
, fnname
) == 0)
6261 const char *separator
;
6262 char *secname
, *stubname
;
6263 tree stubid
, stubdecl
;
6266 /* If the function does not return in FPRs, the special stub
6270 If the function does return in FPRs, the stub section is named
6271 .mips16.call.fp.FNNAME
6273 Build a decl for the stub. */
6274 secname
= ACONCAT ((".mips16.call.", fp_ret_p
? "fp." : "",
6276 stubname
= ACONCAT (("__call_stub_", fp_ret_p
? "fp_" : "",
6278 stubid
= get_identifier (stubname
);
6279 stubdecl
= build_decl (BUILTINS_LOCATION
,
6280 FUNCTION_DECL
, stubid
,
6281 build_function_type (void_type_node
, NULL_TREE
));
6282 DECL_SECTION_NAME (stubdecl
) = build_string (strlen (secname
), secname
);
6283 DECL_RESULT (stubdecl
) = build_decl (BUILTINS_LOCATION
,
6284 RESULT_DECL
, NULL_TREE
,
6287 /* Output a comment. */
6288 fprintf (asm_out_file
, "\t# Stub function to call %s%s (",
6290 ? (GET_MODE (retval
) == SFmode
? "float " : "double ")
6294 for (f
= (unsigned int) fp_code
; f
!= 0; f
>>= 2)
6296 fprintf (asm_out_file
, "%s%s", separator
,
6297 (f
& 3) == 1 ? "float" : "double");
6300 fprintf (asm_out_file
, ")\n");
6302 /* Start the function definition. */
6303 assemble_start_function (stubdecl
, stubname
);
6304 mips_start_function_definition (stubname
, false);
6308 /* Load the address of the MIPS16 function into $25. Do this
6309 first so that targets with coprocessor interlocks can use
6310 an MFC1 to fill the delay slot. */
6311 if (TARGET_EXPLICIT_RELOCS
)
6313 output_asm_insn ("lui\t%^,%%hi(%0)", &fn
);
6314 output_asm_insn ("addiu\t%^,%^,%%lo(%0)", &fn
);
6317 output_asm_insn ("la\t%^,%0", &fn
);
6320 /* Move the arguments from general registers to floating-point
6322 mips_output_args_xfer (fp_code
, 't');
6326 /* Jump to the previously-loaded address. */
6327 output_asm_insn ("jr\t%^", NULL
);
6331 /* Save the return address in $18 and call the non-MIPS16 function.
6332 The stub's caller knows that $18 might be clobbered, even though
6333 $18 is usually a call-saved register. */
6334 fprintf (asm_out_file
, "\tmove\t%s,%s\n",
6335 reg_names
[GP_REG_FIRST
+ 18], reg_names
[RETURN_ADDR_REGNUM
]);
6336 output_asm_insn (MIPS_CALL ("jal", &fn
, 0, -1), &fn
);
6338 /* Move the result from floating-point registers to
6339 general registers. */
6340 switch (GET_MODE (retval
))
6343 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_BIG_ENDIAN
,
6345 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6347 mips_output_32bit_xfer ('f', GP_RETURN
+ TARGET_LITTLE_ENDIAN
,
6348 TARGET_LITTLE_ENDIAN
6349 ? FP_REG_FIRST
+ MAX_FPRS_PER_FMT
6351 if (GET_MODE (retval
) == SCmode
&& TARGET_64BIT
)
6353 /* On 64-bit targets, complex floats are returned in
6354 a single GPR, such that "sd" on a suitably-aligned
6355 target would store the value correctly. */
6356 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6357 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6358 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6359 fprintf (asm_out_file
, "\tdsll\t%s,%s,32\n",
6360 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
],
6361 reg_names
[GP_RETURN
+ TARGET_LITTLE_ENDIAN
]);
6362 fprintf (asm_out_file
, "\tdsrl\t%s,%s,32\n",
6363 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
],
6364 reg_names
[GP_RETURN
+ TARGET_BIG_ENDIAN
]);
6365 fprintf (asm_out_file
, "\tor\t%s,%s,%s\n",
6366 reg_names
[GP_RETURN
],
6367 reg_names
[GP_RETURN
],
6368 reg_names
[GP_RETURN
+ 1]);
6373 mips_output_32bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6377 mips_output_64bit_xfer ('f', GP_RETURN
+ (8 / UNITS_PER_WORD
),
6378 FP_REG_FIRST
+ MAX_FPRS_PER_FMT
);
6382 mips_output_64bit_xfer ('f', GP_RETURN
, FP_REG_FIRST
);
6388 fprintf (asm_out_file
, "\tjr\t%s\n", reg_names
[GP_REG_FIRST
+ 18]);
6391 #ifdef ASM_DECLARE_FUNCTION_SIZE
6392 ASM_DECLARE_FUNCTION_SIZE (asm_out_file
, stubname
, stubdecl
);
6395 mips_end_function_definition (stubname
);
6397 /* Record this stub. */
6398 l
= XNEW (struct mips16_stub
);
6399 l
->name
= xstrdup (fnname
);
6400 l
->fp_ret_p
= fp_ret_p
;
6401 l
->next
= mips16_stubs
;
6405 /* If we expect a floating-point return value, but we've built a
6406 stub which does not expect one, then we're in trouble. We can't
6407 use the existing stub, because it won't handle the floating-point
6408 value. We can't build a new stub, because the linker won't know
6409 which stub to use for the various calls in this object file.
6410 Fortunately, this case is illegal, since it means that a function
6411 was declared in two different ways in a single compilation. */
6412 if (fp_ret_p
&& !l
->fp_ret_p
)
6413 error ("cannot handle inconsistent calls to %qs", fnname
);
6415 if (retval
== NULL_RTX
)
6416 insn
= gen_call_internal_direct (fn
, args_size
);
6418 insn
= gen_call_value_internal_direct (retval
, fn
, args_size
);
6419 insn
= mips_emit_call_insn (insn
, fn
, fn
, false);
6421 /* If we are calling a stub which handles a floating-point return
6422 value, we need to arrange to save $18 in the prologue. We do this
6423 by marking the function call as using the register. The prologue
6424 will later see that it is used, and emit code to save it. */
6426 CALL_INSN_FUNCTION_USAGE (insn
) =
6427 gen_rtx_EXPR_LIST (VOIDmode
,
6428 gen_rtx_CLOBBER (VOIDmode
,
6429 gen_rtx_REG (word_mode
, 18)),
6430 CALL_INSN_FUNCTION_USAGE (insn
));
6435 /* Expand a call of type TYPE. RESULT is where the result will go (null
6436 for "call"s and "sibcall"s), ADDR is the address of the function,
6437 ARGS_SIZE is the size of the arguments and AUX is the value passed
6438 to us by mips_function_arg. LAZY_P is true if this call already
6439 involves a lazily-bound function address (such as when calling
6440 functions through a MIPS16 hard-float stub).
6442 Return the call itself. */
6445 mips_expand_call (enum mips_call_type type
, rtx result
, rtx addr
,
6446 rtx args_size
, rtx aux
, bool lazy_p
)
6448 rtx orig_addr
, pattern
, insn
;
6451 fp_code
= aux
== 0 ? 0 : (int) GET_MODE (aux
);
6452 insn
= mips16_build_call_stub (result
, &addr
, args_size
, fp_code
);
6455 gcc_assert (!lazy_p
&& type
== MIPS_CALL_NORMAL
);
6460 if (!call_insn_operand (addr
, VOIDmode
))
6462 if (type
== MIPS_CALL_EPILOGUE
)
6463 addr
= MIPS_EPILOGUE_TEMP (Pmode
);
6465 addr
= gen_reg_rtx (Pmode
);
6466 lazy_p
|= mips_load_call_address (type
, addr
, orig_addr
);
6471 rtx (*fn
) (rtx
, rtx
);
6473 if (type
== MIPS_CALL_SIBCALL
)
6474 fn
= gen_sibcall_internal
;
6476 fn
= gen_call_internal
;
6478 pattern
= fn (addr
, args_size
);
6480 else if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 2)
6482 /* Handle return values created by mips_return_fpr_pair. */
6483 rtx (*fn
) (rtx
, rtx
, rtx
, rtx
);
6486 if (type
== MIPS_CALL_SIBCALL
)
6487 fn
= gen_sibcall_value_multiple_internal
;
6489 fn
= gen_call_value_multiple_internal
;
6491 reg1
= XEXP (XVECEXP (result
, 0, 0), 0);
6492 reg2
= XEXP (XVECEXP (result
, 0, 1), 0);
6493 pattern
= fn (reg1
, addr
, args_size
, reg2
);
6497 rtx (*fn
) (rtx
, rtx
, rtx
);
6499 if (type
== MIPS_CALL_SIBCALL
)
6500 fn
= gen_sibcall_value_internal
;
6502 fn
= gen_call_value_internal
;
6504 /* Handle return values created by mips_return_fpr_single. */
6505 if (GET_CODE (result
) == PARALLEL
&& XVECLEN (result
, 0) == 1)
6506 result
= XEXP (XVECEXP (result
, 0, 0), 0);
6507 pattern
= fn (result
, addr
, args_size
);
6510 return mips_emit_call_insn (pattern
, orig_addr
, addr
, lazy_p
);
6513 /* Split call instruction INSN into a $gp-clobbering call and
6514 (where necessary) an instruction to restore $gp from its save slot.
6515 CALL_PATTERN is the pattern of the new call. */
6518 mips_split_call (rtx insn
, rtx call_pattern
)
6520 emit_call_insn (call_pattern
);
6521 if (!find_reg_note (insn
, REG_NORETURN
, 0))
6522 /* Pick a temporary register that is suitable for both MIPS16 and
6523 non-MIPS16 code. $4 and $5 are used for returning complex double
6524 values in soft-float code, so $6 is the first suitable candidate. */
6525 mips_restore_gp_from_cprestore_slot (gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 2));
6528 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
6531 mips_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
6533 if (!TARGET_SIBCALLS
)
6536 /* Interrupt handlers need special epilogue code and therefore can't
6538 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
6541 /* We can't do a sibcall if the called function is a MIPS16 function
6542 because there is no direct "jx" instruction equivalent to "jalx" to
6543 switch the ISA mode. We only care about cases where the sibling
6544 and normal calls would both be direct. */
6546 && mips_use_mips16_mode_p (decl
)
6547 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6550 /* When -minterlink-mips16 is in effect, assume that non-locally-binding
6551 functions could be MIPS16 ones unless an attribute explicitly tells
6553 if (TARGET_INTERLINK_MIPS16
6555 && (DECL_EXTERNAL (decl
) || !targetm
.binds_local_p (decl
))
6556 && !mips_nomips16_decl_p (decl
)
6557 && const_call_insn_operand (XEXP (DECL_RTL (decl
), 0), VOIDmode
))
6564 /* Emit code to move general operand SRC into condition-code
6565 register DEST given that SCRATCH is a scratch TFmode FPR.
6572 where FP1 and FP2 are single-precision FPRs taken from SCRATCH. */
6575 mips_expand_fcc_reload (rtx dest
, rtx src
, rtx scratch
)
6579 /* Change the source to SFmode. */
6581 src
= adjust_address (src
, SFmode
, 0);
6582 else if (REG_P (src
) || GET_CODE (src
) == SUBREG
)
6583 src
= gen_rtx_REG (SFmode
, true_regnum (src
));
6585 fp1
= gen_rtx_REG (SFmode
, REGNO (scratch
));
6586 fp2
= gen_rtx_REG (SFmode
, REGNO (scratch
) + MAX_FPRS_PER_FMT
);
6588 mips_emit_move (copy_rtx (fp1
), src
);
6589 mips_emit_move (copy_rtx (fp2
), CONST0_RTX (SFmode
));
6590 emit_insn (gen_slt_sf (dest
, fp2
, fp1
));
6593 /* Emit straight-line code to move LENGTH bytes from SRC to DEST.
6594 Assume that the areas do not overlap. */
6597 mips_block_move_straight (rtx dest
, rtx src
, HOST_WIDE_INT length
)
6599 HOST_WIDE_INT offset
, delta
;
6600 unsigned HOST_WIDE_INT bits
;
6602 enum machine_mode mode
;
6605 /* Work out how many bits to move at a time. If both operands have
6606 half-word alignment, it is usually better to move in half words.
6607 For instance, lh/lh/sh/sh is usually better than lwl/lwr/swl/swr
6608 and lw/lw/sw/sw is usually better than ldl/ldr/sdl/sdr.
6609 Otherwise move word-sized chunks. */
6610 if (MEM_ALIGN (src
) == BITS_PER_WORD
/ 2
6611 && MEM_ALIGN (dest
) == BITS_PER_WORD
/ 2)
6612 bits
= BITS_PER_WORD
/ 2;
6614 bits
= BITS_PER_WORD
;
6616 mode
= mode_for_size (bits
, MODE_INT
, 0);
6617 delta
= bits
/ BITS_PER_UNIT
;
6619 /* Allocate a buffer for the temporary registers. */
6620 regs
= XALLOCAVEC (rtx
, length
/ delta
);
6622 /* Load as many BITS-sized chunks as possible. Use a normal load if
6623 the source has enough alignment, otherwise use left/right pairs. */
6624 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6626 regs
[i
] = gen_reg_rtx (mode
);
6627 if (MEM_ALIGN (src
) >= bits
)
6628 mips_emit_move (regs
[i
], adjust_address (src
, mode
, offset
));
6631 rtx part
= adjust_address (src
, BLKmode
, offset
);
6632 if (!mips_expand_ext_as_unaligned_load (regs
[i
], part
, bits
, 0))
6637 /* Copy the chunks to the destination. */
6638 for (offset
= 0, i
= 0; offset
+ delta
<= length
; offset
+= delta
, i
++)
6639 if (MEM_ALIGN (dest
) >= bits
)
6640 mips_emit_move (adjust_address (dest
, mode
, offset
), regs
[i
]);
6643 rtx part
= adjust_address (dest
, BLKmode
, offset
);
6644 if (!mips_expand_ins_as_unaligned_store (part
, regs
[i
], bits
, 0))
6648 /* Mop up any left-over bytes. */
6649 if (offset
< length
)
6651 src
= adjust_address (src
, BLKmode
, offset
);
6652 dest
= adjust_address (dest
, BLKmode
, offset
);
6653 move_by_pieces (dest
, src
, length
- offset
,
6654 MIN (MEM_ALIGN (src
), MEM_ALIGN (dest
)), 0);
6658 /* Helper function for doing a loop-based block operation on memory
6659 reference MEM. Each iteration of the loop will operate on LENGTH
6662 Create a new base register for use within the loop and point it to
6663 the start of MEM. Create a new memory reference that uses this
6664 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */
6667 mips_adjust_block_mem (rtx mem
, HOST_WIDE_INT length
,
6668 rtx
*loop_reg
, rtx
*loop_mem
)
6670 *loop_reg
= copy_addr_to_reg (XEXP (mem
, 0));
6672 /* Although the new mem does not refer to a known location,
6673 it does keep up to LENGTH bytes of alignment. */
6674 *loop_mem
= change_address (mem
, BLKmode
, *loop_reg
);
6675 set_mem_align (*loop_mem
, MIN (MEM_ALIGN (mem
), length
* BITS_PER_UNIT
));
6678 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER
6679 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that
6680 the memory regions do not overlap. */
6683 mips_block_move_loop (rtx dest
, rtx src
, HOST_WIDE_INT length
,
6684 HOST_WIDE_INT bytes_per_iter
)
6686 rtx label
, src_reg
, dest_reg
, final_src
, test
;
6687 HOST_WIDE_INT leftover
;
6689 leftover
= length
% bytes_per_iter
;
6692 /* Create registers and memory references for use within the loop. */
6693 mips_adjust_block_mem (src
, bytes_per_iter
, &src_reg
, &src
);
6694 mips_adjust_block_mem (dest
, bytes_per_iter
, &dest_reg
, &dest
);
6696 /* Calculate the value that SRC_REG should have after the last iteration
6698 final_src
= expand_simple_binop (Pmode
, PLUS
, src_reg
, GEN_INT (length
),
6701 /* Emit the start of the loop. */
6702 label
= gen_label_rtx ();
6705 /* Emit the loop body. */
6706 mips_block_move_straight (dest
, src
, bytes_per_iter
);
6708 /* Move on to the next block. */
6709 mips_emit_move (src_reg
, plus_constant (src_reg
, bytes_per_iter
));
6710 mips_emit_move (dest_reg
, plus_constant (dest_reg
, bytes_per_iter
));
6712 /* Emit the loop condition. */
6713 test
= gen_rtx_NE (VOIDmode
, src_reg
, final_src
);
6714 if (Pmode
== DImode
)
6715 emit_jump_insn (gen_cbranchdi4 (test
, src_reg
, final_src
, label
));
6717 emit_jump_insn (gen_cbranchsi4 (test
, src_reg
, final_src
, label
));
6719 /* Mop up any left-over bytes. */
6721 mips_block_move_straight (dest
, src
, leftover
);
6724 /* Expand a movmemsi instruction, which copies LENGTH bytes from
6725 memory reference SRC to memory reference DEST. */
6728 mips_expand_block_move (rtx dest
, rtx src
, rtx length
)
6730 if (CONST_INT_P (length
))
6732 if (INTVAL (length
) <= MIPS_MAX_MOVE_BYTES_STRAIGHT
)
6734 mips_block_move_straight (dest
, src
, INTVAL (length
));
6739 mips_block_move_loop (dest
, src
, INTVAL (length
),
6740 MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER
);
6747 /* Expand a loop of synci insns for the address range [BEGIN, END). */
6750 mips_expand_synci_loop (rtx begin
, rtx end
)
6752 rtx inc
, label
, end_label
, cmp_result
, mask
, length
;
6754 /* Create end_label. */
6755 end_label
= gen_label_rtx ();
6757 /* Check if begin equals end. */
6758 cmp_result
= gen_rtx_EQ (VOIDmode
, begin
, end
);
6759 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
6761 /* Load INC with the cache line size (rdhwr INC,$1). */
6762 inc
= gen_reg_rtx (Pmode
);
6763 emit_insn (Pmode
== SImode
6764 ? gen_rdhwr_synci_step_si (inc
)
6765 : gen_rdhwr_synci_step_di (inc
));
6767 /* Check if inc is 0. */
6768 cmp_result
= gen_rtx_EQ (VOIDmode
, inc
, const0_rtx
);
6769 emit_jump_insn (gen_condjump (cmp_result
, end_label
));
6771 /* Calculate mask. */
6772 mask
= mips_force_unary (Pmode
, NEG
, inc
);
6774 /* Mask out begin by mask. */
6775 begin
= mips_force_binary (Pmode
, AND
, begin
, mask
);
6777 /* Calculate length. */
6778 length
= mips_force_binary (Pmode
, MINUS
, end
, begin
);
6780 /* Loop back to here. */
6781 label
= gen_label_rtx ();
6784 emit_insn (gen_synci (begin
));
6786 /* Update length. */
6787 mips_emit_binary (MINUS
, length
, length
, inc
);
6790 mips_emit_binary (PLUS
, begin
, begin
, inc
);
6792 /* Check if length is greater than 0. */
6793 cmp_result
= gen_rtx_GT (VOIDmode
, length
, const0_rtx
);
6794 emit_jump_insn (gen_condjump (cmp_result
, label
));
6796 emit_label (end_label
);
6799 /* Expand a QI or HI mode atomic memory operation.
6801 GENERATOR contains a pointer to the gen_* function that generates
6802 the SI mode underlying atomic operation using masks that we
6805 RESULT is the return register for the operation. Its value is NULL
6808 MEM is the location of the atomic access.
6810 OLDVAL is the first operand for the operation.
6812 NEWVAL is the optional second operand for the operation. Its value
6813 is NULL if unused. */
6816 mips_expand_atomic_qihi (union mips_gen_fn_ptrs generator
,
6817 rtx result
, rtx mem
, rtx oldval
, rtx newval
)
6819 rtx orig_addr
, memsi_addr
, memsi
, shift
, shiftsi
, unshifted_mask
;
6820 rtx unshifted_mask_reg
, mask
, inverted_mask
, si_op
;
6822 enum machine_mode mode
;
6824 mode
= GET_MODE (mem
);
6826 /* Compute the address of the containing SImode value. */
6827 orig_addr
= force_reg (Pmode
, XEXP (mem
, 0));
6828 memsi_addr
= mips_force_binary (Pmode
, AND
, orig_addr
,
6829 force_reg (Pmode
, GEN_INT (-4)));
6831 /* Create a memory reference for it. */
6832 memsi
= gen_rtx_MEM (SImode
, memsi_addr
);
6833 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
6834 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
6836 /* Work out the byte offset of the QImode or HImode value,
6837 counting from the least significant byte. */
6838 shift
= mips_force_binary (Pmode
, AND
, orig_addr
, GEN_INT (3));
6839 if (TARGET_BIG_ENDIAN
)
6840 mips_emit_binary (XOR
, shift
, shift
, GEN_INT (mode
== QImode
? 3 : 2));
6842 /* Multiply by eight to convert the shift value from bytes to bits. */
6843 mips_emit_binary (ASHIFT
, shift
, shift
, GEN_INT (3));
6845 /* Make the final shift an SImode value, so that it can be used in
6846 SImode operations. */
6847 shiftsi
= force_reg (SImode
, gen_lowpart (SImode
, shift
));
6849 /* Set MASK to an inclusive mask of the QImode or HImode value. */
6850 unshifted_mask
= GEN_INT (GET_MODE_MASK (mode
));
6851 unshifted_mask_reg
= force_reg (SImode
, unshifted_mask
);
6852 mask
= mips_force_binary (SImode
, ASHIFT
, unshifted_mask_reg
, shiftsi
);
6854 /* Compute the equivalent exclusive mask. */
6855 inverted_mask
= gen_reg_rtx (SImode
);
6856 emit_insn (gen_rtx_SET (VOIDmode
, inverted_mask
,
6857 gen_rtx_NOT (SImode
, mask
)));
6859 /* Shift the old value into place. */
6860 if (oldval
!= const0_rtx
)
6862 oldval
= convert_modes (SImode
, mode
, oldval
, true);
6863 oldval
= force_reg (SImode
, oldval
);
6864 oldval
= mips_force_binary (SImode
, ASHIFT
, oldval
, shiftsi
);
6867 /* Do the same for the new value. */
6868 if (newval
&& newval
!= const0_rtx
)
6870 newval
= convert_modes (SImode
, mode
, newval
, true);
6871 newval
= force_reg (SImode
, newval
);
6872 newval
= mips_force_binary (SImode
, ASHIFT
, newval
, shiftsi
);
6875 /* Do the SImode atomic access. */
6877 res
= gen_reg_rtx (SImode
);
6879 si_op
= generator
.fn_6 (res
, memsi
, mask
, inverted_mask
, oldval
, newval
);
6881 si_op
= generator
.fn_5 (res
, memsi
, mask
, inverted_mask
, oldval
);
6883 si_op
= generator
.fn_4 (memsi
, mask
, inverted_mask
, oldval
);
6889 /* Shift and convert the result. */
6890 mips_emit_binary (AND
, res
, res
, mask
);
6891 mips_emit_binary (LSHIFTRT
, res
, res
, shiftsi
);
6892 mips_emit_move (result
, gen_lowpart (GET_MODE (result
), res
));
6896 /* Return true if it is possible to use left/right accesses for a
6897 bitfield of WIDTH bits starting BITPOS bits into *OP. When
6898 returning true, update *OP, *LEFT and *RIGHT as follows:
6900 *OP is a BLKmode reference to the whole field.
6902 *LEFT is a QImode reference to the first byte if big endian or
6903 the last byte if little endian. This address can be used in the
6904 left-side instructions (LWL, SWL, LDL, SDL).
6906 *RIGHT is a QImode reference to the opposite end of the field and
6907 can be used in the patterning right-side instruction. */
6910 mips_get_unaligned_mem (rtx
*op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
,
6911 rtx
*left
, rtx
*right
)
6915 /* Check that the operand really is a MEM. Not all the extv and
6916 extzv predicates are checked. */
6920 /* Check that the size is valid. */
6921 if (width
!= 32 && (!TARGET_64BIT
|| width
!= 64))
6924 /* We can only access byte-aligned values. Since we are always passed
6925 a reference to the first byte of the field, it is not necessary to
6926 do anything with BITPOS after this check. */
6927 if (bitpos
% BITS_PER_UNIT
!= 0)
6930 /* Reject aligned bitfields: we want to use a normal load or store
6931 instead of a left/right pair. */
6932 if (MEM_ALIGN (*op
) >= width
)
6935 /* Adjust *OP to refer to the whole field. This also has the effect
6936 of legitimizing *OP's address for BLKmode, possibly simplifying it. */
6937 *op
= adjust_address (*op
, BLKmode
, 0);
6938 set_mem_size (*op
, GEN_INT (width
/ BITS_PER_UNIT
));
6940 /* Get references to both ends of the field. We deliberately don't
6941 use the original QImode *OP for FIRST since the new BLKmode one
6942 might have a simpler address. */
6943 first
= adjust_address (*op
, QImode
, 0);
6944 last
= adjust_address (*op
, QImode
, width
/ BITS_PER_UNIT
- 1);
6946 /* Allocate to LEFT and RIGHT according to endianness. LEFT should
6947 correspond to the MSB and RIGHT to the LSB. */
6948 if (TARGET_BIG_ENDIAN
)
6949 *left
= first
, *right
= last
;
6951 *left
= last
, *right
= first
;
6956 /* Try to use left/right loads to expand an "extv" or "extzv" pattern.
6957 DEST, SRC, WIDTH and BITPOS are the operands passed to the expander;
6958 the operation is the equivalent of:
6960 (set DEST (*_extract SRC WIDTH BITPOS))
6962 Return true on success. */
6965 mips_expand_ext_as_unaligned_load (rtx dest
, rtx src
, HOST_WIDE_INT width
,
6966 HOST_WIDE_INT bitpos
)
6968 rtx left
, right
, temp
;
6970 /* If TARGET_64BIT, the destination of a 32-bit "extz" or "extzv" will
6971 be a paradoxical word_mode subreg. This is the only case in which
6972 we allow the destination to be larger than the source. */
6973 if (GET_CODE (dest
) == SUBREG
6974 && GET_MODE (dest
) == DImode
6975 && GET_MODE (SUBREG_REG (dest
)) == SImode
)
6976 dest
= SUBREG_REG (dest
);
6978 /* After the above adjustment, the destination must be the same
6979 width as the source. */
6980 if (GET_MODE_BITSIZE (GET_MODE (dest
)) != width
)
6983 if (!mips_get_unaligned_mem (&src
, width
, bitpos
, &left
, &right
))
6986 temp
= gen_reg_rtx (GET_MODE (dest
));
6987 if (GET_MODE (dest
) == DImode
)
6989 emit_insn (gen_mov_ldl (temp
, src
, left
));
6990 emit_insn (gen_mov_ldr (dest
, copy_rtx (src
), right
, temp
));
6994 emit_insn (gen_mov_lwl (temp
, src
, left
));
6995 emit_insn (gen_mov_lwr (dest
, copy_rtx (src
), right
, temp
));
7000 /* Try to use left/right stores to expand an "ins" pattern. DEST, WIDTH,
7001 BITPOS and SRC are the operands passed to the expander; the operation
7002 is the equivalent of:
7004 (set (zero_extract DEST WIDTH BITPOS) SRC)
7006 Return true on success. */
7009 mips_expand_ins_as_unaligned_store (rtx dest
, rtx src
, HOST_WIDE_INT width
,
7010 HOST_WIDE_INT bitpos
)
7013 enum machine_mode mode
;
7015 if (!mips_get_unaligned_mem (&dest
, width
, bitpos
, &left
, &right
))
7018 mode
= mode_for_size (width
, MODE_INT
, 0);
7019 src
= gen_lowpart (mode
, src
);
7022 emit_insn (gen_mov_sdl (dest
, src
, left
));
7023 emit_insn (gen_mov_sdr (copy_rtx (dest
), copy_rtx (src
), right
));
7027 emit_insn (gen_mov_swl (dest
, src
, left
));
7028 emit_insn (gen_mov_swr (copy_rtx (dest
), copy_rtx (src
), right
));
7033 /* Return true if X is a MEM with the same size as MODE. */
7036 mips_mem_fits_mode_p (enum machine_mode mode
, rtx x
)
7043 size
= MEM_SIZE (x
);
7044 return size
&& INTVAL (size
) == GET_MODE_SIZE (mode
);
7047 /* Return true if (zero_extract OP WIDTH BITPOS) can be used as the
7048 source of an "ext" instruction or the destination of an "ins"
7049 instruction. OP must be a register operand and the following
7050 conditions must hold:
7052 0 <= BITPOS < GET_MODE_BITSIZE (GET_MODE (op))
7053 0 < WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7054 0 < BITPOS + WIDTH <= GET_MODE_BITSIZE (GET_MODE (op))
7056 Also reject lengths equal to a word as they are better handled
7057 by the move patterns. */
7060 mips_use_ins_ext_p (rtx op
, HOST_WIDE_INT width
, HOST_WIDE_INT bitpos
)
7062 if (!ISA_HAS_EXT_INS
7063 || !register_operand (op
, VOIDmode
)
7064 || GET_MODE_BITSIZE (GET_MODE (op
)) > BITS_PER_WORD
)
7067 if (!IN_RANGE (width
, 1, GET_MODE_BITSIZE (GET_MODE (op
)) - 1))
7070 if (bitpos
< 0 || bitpos
+ width
> GET_MODE_BITSIZE (GET_MODE (op
)))
7076 /* Check if MASK and SHIFT are valid in mask-low-and-shift-left
7077 operation if MAXLEN is the maxium length of consecutive bits that
7078 can make up MASK. MODE is the mode of the operation. See
7079 mask_low_and_shift_len for the actual definition. */
7082 mask_low_and_shift_p (enum machine_mode mode
, rtx mask
, rtx shift
, int maxlen
)
7084 return IN_RANGE (mask_low_and_shift_len (mode
, mask
, shift
), 1, maxlen
);
7087 /* Return true iff OP1 and OP2 are valid operands together for the
7088 *and<MODE>3 and *and<MODE>3_mips16 patterns. For the cases to consider,
7089 see the table in the comment before the pattern. */
7092 and_operands_ok (enum machine_mode mode
, rtx op1
, rtx op2
)
7094 return (memory_operand (op1
, mode
)
7095 ? and_load_operand (op2
, mode
)
7096 : and_reg_operand (op2
, mode
));
7099 /* The canonical form of a mask-low-and-shift-left operation is
7100 (and (ashift X SHIFT) MASK) where MASK has the lower SHIFT number of bits
7101 cleared. Thus we need to shift MASK to the right before checking if it
7102 is a valid mask value. MODE is the mode of the operation. If true
7103 return the length of the mask, otherwise return -1. */
7106 mask_low_and_shift_len (enum machine_mode mode
, rtx mask
, rtx shift
)
7108 HOST_WIDE_INT shval
;
7110 shval
= INTVAL (shift
) & (GET_MODE_BITSIZE (mode
) - 1);
7111 return exact_log2 ((UINTVAL (mask
) >> shval
) + 1);
7114 /* Return true if -msplit-addresses is selected and should be honored.
7116 -msplit-addresses is a half-way house between explicit relocations
7117 and the traditional assembler macros. It can split absolute 32-bit
7118 symbolic constants into a high/lo_sum pair but uses macros for other
7121 Like explicit relocation support for REL targets, it relies
7122 on GNU extensions in the assembler and the linker.
7124 Although this code should work for -O0, it has traditionally
7125 been treated as an optimization. */
7128 mips_split_addresses_p (void)
7130 return (TARGET_SPLIT_ADDRESSES
7134 && !ABI_HAS_64BIT_SYMBOLS
);
7137 /* (Re-)Initialize mips_split_p, mips_lo_relocs and mips_hi_relocs. */
7140 mips_init_relocs (void)
7142 memset (mips_split_p
, '\0', sizeof (mips_split_p
));
7143 memset (mips_split_hi_p
, '\0', sizeof (mips_split_hi_p
));
7144 memset (mips_hi_relocs
, '\0', sizeof (mips_hi_relocs
));
7145 memset (mips_lo_relocs
, '\0', sizeof (mips_lo_relocs
));
7147 if (ABI_HAS_64BIT_SYMBOLS
)
7149 if (TARGET_EXPLICIT_RELOCS
)
7151 mips_split_p
[SYMBOL_64_HIGH
] = true;
7152 mips_hi_relocs
[SYMBOL_64_HIGH
] = "%highest(";
7153 mips_lo_relocs
[SYMBOL_64_HIGH
] = "%higher(";
7155 mips_split_p
[SYMBOL_64_MID
] = true;
7156 mips_hi_relocs
[SYMBOL_64_MID
] = "%higher(";
7157 mips_lo_relocs
[SYMBOL_64_MID
] = "%hi(";
7159 mips_split_p
[SYMBOL_64_LOW
] = true;
7160 mips_hi_relocs
[SYMBOL_64_LOW
] = "%hi(";
7161 mips_lo_relocs
[SYMBOL_64_LOW
] = "%lo(";
7163 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7164 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7169 if (TARGET_EXPLICIT_RELOCS
|| mips_split_addresses_p () || TARGET_MIPS16
)
7171 mips_split_p
[SYMBOL_ABSOLUTE
] = true;
7172 mips_hi_relocs
[SYMBOL_ABSOLUTE
] = "%hi(";
7173 mips_lo_relocs
[SYMBOL_ABSOLUTE
] = "%lo(";
7175 mips_lo_relocs
[SYMBOL_32_HIGH
] = "%hi(";
7181 /* The high part is provided by a pseudo copy of $gp. */
7182 mips_split_p
[SYMBOL_GP_RELATIVE
] = true;
7183 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gprel(";
7185 else if (TARGET_EXPLICIT_RELOCS
)
7186 /* Small data constants are kept whole until after reload,
7187 then lowered by mips_rewrite_small_data. */
7188 mips_lo_relocs
[SYMBOL_GP_RELATIVE
] = "%gp_rel(";
7190 if (TARGET_EXPLICIT_RELOCS
)
7192 mips_split_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7195 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got_page(";
7196 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%got_ofst(";
7200 mips_lo_relocs
[SYMBOL_GOTOFF_PAGE
] = "%got(";
7201 mips_lo_relocs
[SYMBOL_GOT_PAGE_OFST
] = "%lo(";
7204 /* Expose the use of $28 as soon as possible. */
7205 mips_split_hi_p
[SYMBOL_GOT_PAGE_OFST
] = true;
7209 /* The HIGH and LO_SUM are matched by special .md patterns. */
7210 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7212 mips_split_p
[SYMBOL_GOTOFF_DISP
] = true;
7213 mips_hi_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_hi(";
7214 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_lo(";
7216 mips_split_p
[SYMBOL_GOTOFF_CALL
] = true;
7217 mips_hi_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_hi(";
7218 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call_lo(";
7223 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got_disp(";
7225 mips_lo_relocs
[SYMBOL_GOTOFF_DISP
] = "%got(";
7226 mips_lo_relocs
[SYMBOL_GOTOFF_CALL
] = "%call16(";
7228 /* Expose the use of $28 as soon as possible. */
7229 mips_split_p
[SYMBOL_GOT_DISP
] = true;
7235 mips_split_p
[SYMBOL_GOTOFF_LOADGP
] = true;
7236 mips_hi_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%hi(%neg(%gp_rel(";
7237 mips_lo_relocs
[SYMBOL_GOTOFF_LOADGP
] = "%lo(%neg(%gp_rel(";
7240 mips_lo_relocs
[SYMBOL_TLSGD
] = "%tlsgd(";
7241 mips_lo_relocs
[SYMBOL_TLSLDM
] = "%tlsldm(";
7243 mips_split_p
[SYMBOL_DTPREL
] = true;
7244 mips_hi_relocs
[SYMBOL_DTPREL
] = "%dtprel_hi(";
7245 mips_lo_relocs
[SYMBOL_DTPREL
] = "%dtprel_lo(";
7247 mips_lo_relocs
[SYMBOL_GOTTPREL
] = "%gottprel(";
7249 mips_split_p
[SYMBOL_TPREL
] = true;
7250 mips_hi_relocs
[SYMBOL_TPREL
] = "%tprel_hi(";
7251 mips_lo_relocs
[SYMBOL_TPREL
] = "%tprel_lo(";
7253 mips_lo_relocs
[SYMBOL_HALF
] = "%half(";
7256 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
7257 in context CONTEXT. RELOCS is the array of relocations to use. */
7260 mips_print_operand_reloc (FILE *file
, rtx op
, enum mips_symbol_context context
,
7261 const char **relocs
)
7263 enum mips_symbol_type symbol_type
;
7266 symbol_type
= mips_classify_symbolic_expression (op
, context
);
7267 gcc_assert (relocs
[symbol_type
]);
7269 fputs (relocs
[symbol_type
], file
);
7270 output_addr_const (file
, mips_strip_unspec_address (op
));
7271 for (p
= relocs
[symbol_type
]; *p
!= 0; p
++)
7276 /* Start a new block with the given asm switch enabled. If we need
7277 to print a directive, emit PREFIX before it and SUFFIX after it. */
7280 mips_push_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7281 const char *prefix
, const char *suffix
)
7283 if (asm_switch
->nesting_level
== 0)
7284 fprintf (asm_out_file
, "%s.set\tno%s%s", prefix
, asm_switch
->name
, suffix
);
7285 asm_switch
->nesting_level
++;
7288 /* Likewise, but end a block. */
7291 mips_pop_asm_switch_1 (struct mips_asm_switch
*asm_switch
,
7292 const char *prefix
, const char *suffix
)
7294 gcc_assert (asm_switch
->nesting_level
);
7295 asm_switch
->nesting_level
--;
7296 if (asm_switch
->nesting_level
== 0)
7297 fprintf (asm_out_file
, "%s.set\t%s%s", prefix
, asm_switch
->name
, suffix
);
7300 /* Wrappers around mips_push_asm_switch_1 and mips_pop_asm_switch_1
7301 that either print a complete line or print nothing. */
7304 mips_push_asm_switch (struct mips_asm_switch
*asm_switch
)
7306 mips_push_asm_switch_1 (asm_switch
, "\t", "\n");
7310 mips_pop_asm_switch (struct mips_asm_switch
*asm_switch
)
7312 mips_pop_asm_switch_1 (asm_switch
, "\t", "\n");
7315 /* Print the text for PRINT_OPERAND punctation character CH to FILE.
7316 The punctuation characters are:
7318 '(' Start a nested ".set noreorder" block.
7319 ')' End a nested ".set noreorder" block.
7320 '[' Start a nested ".set noat" block.
7321 ']' End a nested ".set noat" block.
7322 '<' Start a nested ".set nomacro" block.
7323 '>' End a nested ".set nomacro" block.
7324 '*' Behave like %(%< if generating a delayed-branch sequence.
7325 '#' Print a nop if in a ".set noreorder" block.
7326 '/' Like '#', but do nothing within a delayed-branch sequence.
7327 '?' Print "l" if mips_branch_likely is true
7328 '~' Print a nop if mips_branch_likely is true
7329 '.' Print the name of the register with a hard-wired zero (zero or $0).
7330 '@' Print the name of the assembler temporary register (at or $1).
7331 '^' Print the name of the pic call-through register (t9 or $25).
7332 '+' Print the name of the gp register (usually gp or $28).
7333 '$' Print the name of the stack pointer register (sp or $29).
7335 See also mips_init_print_operand_pucnt. */
7338 mips_print_operand_punctuation (FILE *file
, int ch
)
7343 mips_push_asm_switch_1 (&mips_noreorder
, "", "\n\t");
7347 mips_pop_asm_switch_1 (&mips_noreorder
, "\n\t", "");
7351 mips_push_asm_switch_1 (&mips_noat
, "", "\n\t");
7355 mips_pop_asm_switch_1 (&mips_noat
, "\n\t", "");
7359 mips_push_asm_switch_1 (&mips_nomacro
, "", "\n\t");
7363 mips_pop_asm_switch_1 (&mips_nomacro
, "\n\t", "");
7367 if (final_sequence
!= 0)
7369 mips_print_operand_punctuation (file
, '(');
7370 mips_print_operand_punctuation (file
, '<');
7375 if (mips_noreorder
.nesting_level
> 0)
7376 fputs ("\n\tnop", file
);
7380 /* Print an extra newline so that the delayed insn is separated
7381 from the following ones. This looks neater and is consistent
7382 with non-nop delayed sequences. */
7383 if (mips_noreorder
.nesting_level
> 0 && final_sequence
== 0)
7384 fputs ("\n\tnop\n", file
);
7388 if (mips_branch_likely
)
7393 if (mips_branch_likely
)
7394 fputs ("\n\tnop", file
);
7398 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
7402 fputs (reg_names
[AT_REGNUM
], file
);
7406 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
7410 fputs (reg_names
[PIC_OFFSET_TABLE_REGNUM
], file
);
7414 fputs (reg_names
[STACK_POINTER_REGNUM
], file
);
7423 /* Initialize mips_print_operand_punct. */
7426 mips_init_print_operand_punct (void)
7430 for (p
= "()[]<>*#/?~.@^+$"; *p
; p
++)
7431 mips_print_operand_punct
[(unsigned char) *p
] = true;
7434 /* PRINT_OPERAND prefix LETTER refers to the integer branch instruction
7435 associated with condition CODE. Print the condition part of the
7439 mips_print_int_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7453 /* Conveniently, the MIPS names for these conditions are the same
7454 as their RTL equivalents. */
7455 fputs (GET_RTX_NAME (code
), file
);
7459 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7464 /* Likewise floating-point branches. */
7467 mips_print_float_branch_condition (FILE *file
, enum rtx_code code
, int letter
)
7472 fputs ("c1f", file
);
7476 fputs ("c1t", file
);
7480 output_operand_lossage ("'%%%c' is not a valid operand prefix", letter
);
7485 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
7488 mips_print_operand_punct_valid_p (unsigned char code
)
7490 return mips_print_operand_punct
[code
];
7493 /* Implement TARGET_PRINT_OPERAND. The MIPS-specific operand codes are:
7495 'X' Print CONST_INT OP in hexadecimal format.
7496 'x' Print the low 16 bits of CONST_INT OP in hexadecimal format.
7497 'd' Print CONST_INT OP in decimal.
7498 'm' Print one less than CONST_INT OP in decimal.
7499 'h' Print the high-part relocation associated with OP, after stripping
7501 'R' Print the low-part relocation associated with OP.
7502 'C' Print the integer branch condition for comparison OP.
7503 'N' Print the inverse of the integer branch condition for comparison OP.
7504 'F' Print the FPU branch condition for comparison OP.
7505 'W' Print the inverse of the FPU branch condition for comparison OP.
7506 'T' Print 'f' for (eq:CC ...), 't' for (ne:CC ...),
7507 'z' for (eq:?I ...), 'n' for (ne:?I ...).
7508 't' Like 'T', but with the EQ/NE cases reversed
7509 'Y' Print mips_fp_conditions[INTVAL (OP)]
7510 'Z' Print OP and a comma for ISA_HAS_8CC, otherwise print nothing.
7511 'q' Print a DSP accumulator register.
7512 'D' Print the second part of a double-word register or memory operand.
7513 'L' Print the low-order register in a double-word register operand.
7514 'M' Print high-order register in a double-word register operand.
7515 'z' Print $0 if OP is zero, otherwise print OP normally. */
7518 mips_print_operand (FILE *file
, rtx op
, int letter
)
7522 if (mips_print_operand_punct_valid_p (letter
))
7524 mips_print_operand_punctuation (file
, letter
);
7529 code
= GET_CODE (op
);
7534 if (CONST_INT_P (op
))
7535 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
7537 output_operand_lossage ("invalid use of '%%%c'", letter
);
7541 if (CONST_INT_P (op
))
7542 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
) & 0xffff);
7544 output_operand_lossage ("invalid use of '%%%c'", letter
);
7548 if (CONST_INT_P (op
))
7549 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
7551 output_operand_lossage ("invalid use of '%%%c'", letter
);
7555 if (CONST_INT_P (op
))
7556 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
) - 1);
7558 output_operand_lossage ("invalid use of '%%%c'", letter
);
7564 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_hi_relocs
);
7568 mips_print_operand_reloc (file
, op
, SYMBOL_CONTEXT_LEA
, mips_lo_relocs
);
7572 mips_print_int_branch_condition (file
, code
, letter
);
7576 mips_print_int_branch_condition (file
, reverse_condition (code
), letter
);
7580 mips_print_float_branch_condition (file
, code
, letter
);
7584 mips_print_float_branch_condition (file
, reverse_condition (code
),
7591 int truth
= (code
== NE
) == (letter
== 'T');
7592 fputc ("zfnt"[truth
* 2 + (GET_MODE (op
) == CCmode
)], file
);
7597 if (code
== CONST_INT
&& UINTVAL (op
) < ARRAY_SIZE (mips_fp_conditions
))
7598 fputs (mips_fp_conditions
[UINTVAL (op
)], file
);
7600 output_operand_lossage ("'%%%c' is not a valid operand prefix",
7607 mips_print_operand (file
, op
, 0);
7613 if (code
== REG
&& MD_REG_P (REGNO (op
)))
7614 fprintf (file
, "$ac0");
7615 else if (code
== REG
&& DSP_ACC_REG_P (REGNO (op
)))
7616 fprintf (file
, "$ac%c", reg_names
[REGNO (op
)][3]);
7618 output_operand_lossage ("invalid use of '%%%c'", letter
);
7626 unsigned int regno
= REGNO (op
);
7627 if ((letter
== 'M' && TARGET_LITTLE_ENDIAN
)
7628 || (letter
== 'L' && TARGET_BIG_ENDIAN
)
7631 else if (letter
&& letter
!= 'z' && letter
!= 'M' && letter
!= 'L')
7632 output_operand_lossage ("invalid use of '%%%c'", letter
);
7633 /* We need to print $0 .. $31 for COP0 registers. */
7634 if (COP0_REG_P (regno
))
7635 fprintf (file
, "$%s", ®_names
[regno
][4]);
7637 fprintf (file
, "%s", reg_names
[regno
]);
7643 output_address (plus_constant (XEXP (op
, 0), 4));
7644 else if (letter
&& letter
!= 'z')
7645 output_operand_lossage ("invalid use of '%%%c'", letter
);
7647 output_address (XEXP (op
, 0));
7651 if (letter
== 'z' && op
== CONST0_RTX (GET_MODE (op
)))
7652 fputs (reg_names
[GP_REG_FIRST
], file
);
7653 else if (letter
&& letter
!= 'z')
7654 output_operand_lossage ("invalid use of '%%%c'", letter
);
7655 else if (CONST_GP_P (op
))
7656 fputs (reg_names
[GLOBAL_POINTER_REGNUM
], file
);
7658 output_addr_const (file
, mips_strip_unspec_address (op
));
7664 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
7667 mips_print_operand_address (FILE *file
, rtx x
)
7669 struct mips_address_info addr
;
7671 if (mips_classify_address (&addr
, x
, word_mode
, true))
7675 mips_print_operand (file
, addr
.offset
, 0);
7676 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
7679 case ADDRESS_LO_SUM
:
7680 mips_print_operand_reloc (file
, addr
.offset
, SYMBOL_CONTEXT_MEM
,
7682 fprintf (file
, "(%s)", reg_names
[REGNO (addr
.reg
)]);
7685 case ADDRESS_CONST_INT
:
7686 output_addr_const (file
, x
);
7687 fprintf (file
, "(%s)", reg_names
[GP_REG_FIRST
]);
7690 case ADDRESS_SYMBOLIC
:
7691 output_addr_const (file
, mips_strip_unspec_address (x
));
7697 /* Implement TARGET_ENCODE_SECTION_INFO. */
7700 mips_encode_section_info (tree decl
, rtx rtl
, int first
)
7702 default_encode_section_info (decl
, rtl
, first
);
7704 if (TREE_CODE (decl
) == FUNCTION_DECL
)
7706 rtx symbol
= XEXP (rtl
, 0);
7707 tree type
= TREE_TYPE (decl
);
7709 /* Encode whether the symbol is short or long. */
7710 if ((TARGET_LONG_CALLS
&& !mips_near_type_p (type
))
7711 || mips_far_type_p (type
))
7712 SYMBOL_REF_FLAGS (symbol
) |= SYMBOL_FLAG_LONG_CALL
;
7716 /* Implement TARGET_SELECT_RTX_SECTION. */
7719 mips_select_rtx_section (enum machine_mode mode
, rtx x
,
7720 unsigned HOST_WIDE_INT align
)
7722 /* ??? Consider using mergeable small data sections. */
7723 if (mips_rtx_constant_in_small_data_p (mode
))
7724 return get_named_section (NULL
, ".sdata", 0);
7726 return default_elf_select_rtx_section (mode
, x
, align
);
7729 /* Implement TARGET_ASM_FUNCTION_RODATA_SECTION.
7731 The complication here is that, with the combination TARGET_ABICALLS
7732 && !TARGET_ABSOLUTE_ABICALLS && !TARGET_GPWORD, jump tables will use
7733 absolute addresses, and should therefore not be included in the
7734 read-only part of a DSO. Handle such cases by selecting a normal
7735 data section instead of a read-only one. The logic apes that in
7736 default_function_rodata_section. */
7739 mips_function_rodata_section (tree decl
)
7741 if (!TARGET_ABICALLS
|| TARGET_ABSOLUTE_ABICALLS
|| TARGET_GPWORD
)
7742 return default_function_rodata_section (decl
);
7744 if (decl
&& DECL_SECTION_NAME (decl
))
7746 const char *name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7747 if (DECL_ONE_ONLY (decl
) && strncmp (name
, ".gnu.linkonce.t.", 16) == 0)
7749 char *rname
= ASTRDUP (name
);
7751 return get_section (rname
, SECTION_LINKONCE
| SECTION_WRITE
, decl
);
7753 else if (flag_function_sections
7754 && flag_data_sections
7755 && strncmp (name
, ".text.", 6) == 0)
7757 char *rname
= ASTRDUP (name
);
7758 memcpy (rname
+ 1, "data", 4);
7759 return get_section (rname
, SECTION_WRITE
, decl
);
7762 return data_section
;
7765 /* Implement TARGET_IN_SMALL_DATA_P. */
7768 mips_in_small_data_p (const_tree decl
)
7770 unsigned HOST_WIDE_INT size
;
7772 if (TREE_CODE (decl
) == STRING_CST
|| TREE_CODE (decl
) == FUNCTION_DECL
)
7775 /* We don't yet generate small-data references for -mabicalls
7776 or VxWorks RTP code. See the related -G handling in
7777 mips_option_override. */
7778 if (TARGET_ABICALLS
|| TARGET_VXWORKS_RTP
)
7781 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
) != 0)
7785 /* Reject anything that isn't in a known small-data section. */
7786 name
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
7787 if (strcmp (name
, ".sdata") != 0 && strcmp (name
, ".sbss") != 0)
7790 /* If a symbol is defined externally, the assembler will use the
7791 usual -G rules when deciding how to implement macros. */
7792 if (mips_lo_relocs
[SYMBOL_GP_RELATIVE
] || !DECL_EXTERNAL (decl
))
7795 else if (TARGET_EMBEDDED_DATA
)
7797 /* Don't put constants into the small data section: we want them
7798 to be in ROM rather than RAM. */
7799 if (TREE_CODE (decl
) != VAR_DECL
)
7802 if (TREE_READONLY (decl
)
7803 && !TREE_SIDE_EFFECTS (decl
)
7804 && (!DECL_INITIAL (decl
) || TREE_CONSTANT (DECL_INITIAL (decl
))))
7808 /* Enforce -mlocal-sdata. */
7809 if (!TARGET_LOCAL_SDATA
&& !TREE_PUBLIC (decl
))
7812 /* Enforce -mextern-sdata. */
7813 if (!TARGET_EXTERN_SDATA
&& DECL_P (decl
))
7815 if (DECL_EXTERNAL (decl
))
7817 if (DECL_COMMON (decl
) && DECL_INITIAL (decl
) == NULL
)
7821 /* We have traditionally not treated zero-sized objects as small data,
7822 so this is now effectively part of the ABI. */
7823 size
= int_size_in_bytes (TREE_TYPE (decl
));
7824 return size
> 0 && size
<= mips_small_data_threshold
;
7827 /* Implement TARGET_USE_ANCHORS_FOR_SYMBOL_P. We don't want to use
7828 anchors for small data: the GP register acts as an anchor in that
7829 case. We also don't want to use them for PC-relative accesses,
7830 where the PC acts as an anchor. */
7833 mips_use_anchors_for_symbol_p (const_rtx symbol
)
7835 switch (mips_classify_symbol (symbol
, SYMBOL_CONTEXT_MEM
))
7837 case SYMBOL_PC_RELATIVE
:
7838 case SYMBOL_GP_RELATIVE
:
7842 return default_use_anchors_for_symbol_p (symbol
);
7846 /* The MIPS debug format wants all automatic variables and arguments
7847 to be in terms of the virtual frame pointer (stack pointer before
7848 any adjustment in the function), while the MIPS 3.0 linker wants
7849 the frame pointer to be the stack pointer after the initial
7850 adjustment. So, we do the adjustment here. The arg pointer (which
7851 is eliminated) points to the virtual frame pointer, while the frame
7852 pointer (which may be eliminated) points to the stack pointer after
7853 the initial adjustments. */
7856 mips_debugger_offset (rtx addr
, HOST_WIDE_INT offset
)
7858 rtx offset2
= const0_rtx
;
7859 rtx reg
= eliminate_constant_term (addr
, &offset2
);
7862 offset
= INTVAL (offset2
);
7864 if (reg
== stack_pointer_rtx
7865 || reg
== frame_pointer_rtx
7866 || reg
== hard_frame_pointer_rtx
)
7868 offset
-= cfun
->machine
->frame
.total_size
;
7869 if (reg
== hard_frame_pointer_rtx
)
7870 offset
+= cfun
->machine
->frame
.hard_frame_pointer_offset
;
7873 /* sdbout_parms does not want this to crash for unrecognized cases. */
7875 else if (reg
!= arg_pointer_rtx
)
7876 fatal_insn ("mips_debugger_offset called with non stack/frame/arg pointer",
7883 /* Implement ASM_OUTPUT_EXTERNAL. */
7886 mips_output_external (FILE *file
, tree decl
, const char *name
)
7888 default_elf_asm_output_external (file
, decl
, name
);
7890 /* We output the name if and only if TREE_SYMBOL_REFERENCED is
7891 set in order to avoid putting out names that are never really
7893 if (TREE_SYMBOL_REFERENCED (DECL_ASSEMBLER_NAME (decl
)))
7895 if (!TARGET_EXPLICIT_RELOCS
&& mips_in_small_data_p (decl
))
7897 /* When using assembler macros, emit .extern directives for
7898 all small-data externs so that the assembler knows how
7901 In most cases it would be safe (though pointless) to emit
7902 .externs for other symbols too. One exception is when an
7903 object is within the -G limit but declared by the user to
7904 be in a section other than .sbss or .sdata. */
7905 fputs ("\t.extern\t", file
);
7906 assemble_name (file
, name
);
7907 fprintf (file
, ", " HOST_WIDE_INT_PRINT_DEC
"\n",
7908 int_size_in_bytes (TREE_TYPE (decl
)));
7913 /* Implement TARGET_ASM_OUTPUT_SOURCE_FILENAME. */
7916 mips_output_filename (FILE *stream
, const char *name
)
7918 /* If we are emitting DWARF-2, let dwarf2out handle the ".file"
7920 if (write_symbols
== DWARF2_DEBUG
)
7922 else if (mips_output_filename_first_time
)
7924 mips_output_filename_first_time
= 0;
7925 num_source_filenames
+= 1;
7926 current_function_file
= name
;
7927 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7928 output_quoted_string (stream
, name
);
7929 putc ('\n', stream
);
7931 /* If we are emitting stabs, let dbxout.c handle this (except for
7932 the mips_output_filename_first_time case). */
7933 else if (write_symbols
== DBX_DEBUG
)
7935 else if (name
!= current_function_file
7936 && strcmp (name
, current_function_file
) != 0)
7938 num_source_filenames
+= 1;
7939 current_function_file
= name
;
7940 fprintf (stream
, "\t.file\t%d ", num_source_filenames
);
7941 output_quoted_string (stream
, name
);
7942 putc ('\n', stream
);
7946 /* Implement TARGET_ASM_OUTPUT_DWARF_DTPREL. */
7948 static void ATTRIBUTE_UNUSED
7949 mips_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
7954 fputs ("\t.dtprelword\t", file
);
7958 fputs ("\t.dtpreldword\t", file
);
7964 output_addr_const (file
, x
);
7965 fputs ("+0x8000", file
);
7968 /* Implement TARGET_DWARF_REGISTER_SPAN. */
7971 mips_dwarf_register_span (rtx reg
)
7974 enum machine_mode mode
;
7976 /* By default, GCC maps increasing register numbers to increasing
7977 memory locations, but paired FPRs are always little-endian,
7978 regardless of the prevailing endianness. */
7979 mode
= GET_MODE (reg
);
7980 if (FP_REG_P (REGNO (reg
))
7981 && TARGET_BIG_ENDIAN
7982 && MAX_FPRS_PER_FMT
> 1
7983 && GET_MODE_SIZE (mode
) > UNITS_PER_FPREG
)
7985 gcc_assert (GET_MODE_SIZE (mode
) == UNITS_PER_HWFPVALUE
);
7986 high
= mips_subword (reg
, true);
7987 low
= mips_subword (reg
, false);
7988 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, high
, low
));
7994 /* Implement ASM_OUTPUT_ASCII. */
7997 mips_output_ascii (FILE *stream
, const char *string
, size_t len
)
8003 fprintf (stream
, "\t.ascii\t\"");
8004 for (i
= 0; i
< len
; i
++)
8008 c
= (unsigned char) string
[i
];
8011 if (c
== '\\' || c
== '\"')
8013 putc ('\\', stream
);
8021 fprintf (stream
, "\\%03o", c
);
8025 if (cur_pos
> 72 && i
+1 < len
)
8028 fprintf (stream
, "\"\n\t.ascii\t\"");
8031 fprintf (stream
, "\"\n");
8034 /* Emit either a label, .comm, or .lcomm directive. When using assembler
8035 macros, mark the symbol as written so that mips_asm_output_external
8036 won't emit an .extern for it. STREAM is the output file, NAME is the
8037 name of the symbol, INIT_STRING is the string that should be written
8038 before the symbol and FINAL_STRING is the string that should be
8039 written after it. FINAL_STRING is a printf format that consumes the
8040 remaining arguments. */
8043 mips_declare_object (FILE *stream
, const char *name
, const char *init_string
,
8044 const char *final_string
, ...)
8048 fputs (init_string
, stream
);
8049 assemble_name (stream
, name
);
8050 va_start (ap
, final_string
);
8051 vfprintf (stream
, final_string
, ap
);
8054 if (!TARGET_EXPLICIT_RELOCS
)
8056 tree name_tree
= get_identifier (name
);
8057 TREE_ASM_WRITTEN (name_tree
) = 1;
8061 /* Declare a common object of SIZE bytes using asm directive INIT_STRING.
8062 NAME is the name of the object and ALIGN is the required alignment
8063 in bytes. TAKES_ALIGNMENT_P is true if the directive takes a third
8064 alignment argument. */
8067 mips_declare_common_object (FILE *stream
, const char *name
,
8068 const char *init_string
,
8069 unsigned HOST_WIDE_INT size
,
8070 unsigned int align
, bool takes_alignment_p
)
8072 if (!takes_alignment_p
)
8074 size
+= (align
/ BITS_PER_UNIT
) - 1;
8075 size
-= size
% (align
/ BITS_PER_UNIT
);
8076 mips_declare_object (stream
, name
, init_string
,
8077 "," HOST_WIDE_INT_PRINT_UNSIGNED
"\n", size
);
8080 mips_declare_object (stream
, name
, init_string
,
8081 "," HOST_WIDE_INT_PRINT_UNSIGNED
",%u\n",
8082 size
, align
/ BITS_PER_UNIT
);
8085 /* Implement ASM_OUTPUT_ALIGNED_DECL_COMMON. This is usually the same as the
8086 elfos.h version, but we also need to handle -muninit-const-in-rodata. */
8089 mips_output_aligned_decl_common (FILE *stream
, tree decl
, const char *name
,
8090 unsigned HOST_WIDE_INT size
,
8093 /* If the target wants uninitialized const declarations in
8094 .rdata then don't put them in .comm. */
8095 if (TARGET_EMBEDDED_DATA
8096 && TARGET_UNINIT_CONST_IN_RODATA
8097 && TREE_CODE (decl
) == VAR_DECL
8098 && TREE_READONLY (decl
)
8099 && (DECL_INITIAL (decl
) == 0 || DECL_INITIAL (decl
) == error_mark_node
))
8101 if (TREE_PUBLIC (decl
) && DECL_NAME (decl
))
8102 targetm
.asm_out
.globalize_label (stream
, name
);
8104 switch_to_section (readonly_data_section
);
8105 ASM_OUTPUT_ALIGN (stream
, floor_log2 (align
/ BITS_PER_UNIT
));
8106 mips_declare_object (stream
, name
, "",
8107 ":\n\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED
"\n",
8111 mips_declare_common_object (stream
, name
, "\n\t.comm\t",
8115 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8116 extern int size_directive_output
;
8118 /* Implement ASM_DECLARE_OBJECT_NAME. This is like most of the standard ELF
8119 definitions except that it uses mips_declare_object to emit the label. */
8122 mips_declare_object_name (FILE *stream
, const char *name
,
8123 tree decl ATTRIBUTE_UNUSED
)
8125 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8126 ASM_OUTPUT_TYPE_DIRECTIVE (stream
, name
, "object");
8129 size_directive_output
= 0;
8130 if (!flag_inhibit_size_directive
&& DECL_SIZE (decl
))
8134 size_directive_output
= 1;
8135 size
= int_size_in_bytes (TREE_TYPE (decl
));
8136 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8139 mips_declare_object (stream
, name
, "", ":\n");
8142 /* Implement ASM_FINISH_DECLARE_OBJECT. This is generic ELF stuff. */
8145 mips_finish_declare_object (FILE *stream
, tree decl
, int top_level
, int at_end
)
8149 name
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
8150 if (!flag_inhibit_size_directive
8151 && DECL_SIZE (decl
) != 0
8154 && DECL_INITIAL (decl
) == error_mark_node
8155 && !size_directive_output
)
8159 size_directive_output
= 1;
8160 size
= int_size_in_bytes (TREE_TYPE (decl
));
8161 ASM_OUTPUT_SIZE_DIRECTIVE (stream
, name
, size
);
8166 /* Return the FOO in the name of the ".mdebug.FOO" section associated
8167 with the current ABI. */
8170 mips_mdebug_abi_name (void)
8183 return TARGET_64BIT
? "eabi64" : "eabi32";
8189 /* Implement TARGET_ASM_FILE_START. */
8192 mips_file_start (void)
8194 default_file_start ();
8196 /* Generate a special section to describe the ABI switches used to
8197 produce the resultant binary. This is unnecessary on IRIX and
8198 causes unwanted warnings from the native linker. */
8201 /* Record the ABI itself. Modern versions of binutils encode
8202 this information in the ELF header flags, but GDB needs the
8203 information in order to correctly debug binaries produced by
8204 older binutils. See the function mips_gdbarch_init in
8206 fprintf (asm_out_file
, "\t.section .mdebug.%s\n\t.previous\n",
8207 mips_mdebug_abi_name ());
8209 /* There is no ELF header flag to distinguish long32 forms of the
8210 EABI from long64 forms. Emit a special section to help tools
8211 such as GDB. Do the same for o64, which is sometimes used with
8213 if (mips_abi
== ABI_EABI
|| mips_abi
== ABI_O64
)
8214 fprintf (asm_out_file
, "\t.section .gcc_compiled_long%d\n"
8215 "\t.previous\n", TARGET_LONG64
? 64 : 32);
8217 #ifdef HAVE_AS_GNU_ATTRIBUTE
8221 /* No floating-point operations, -mno-float. */
8222 if (TARGET_NO_FLOAT
)
8224 /* Soft-float code, -msoft-float. */
8225 else if (!TARGET_HARD_FLOAT_ABI
)
8227 /* Single-float code, -msingle-float. */
8228 else if (!TARGET_DOUBLE_FLOAT
)
8230 /* 64-bit FP registers on a 32-bit target, -mips32r2 -mfp64. */
8231 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
8233 /* Regular FP code, FP regs same size as GP regs, -mdouble-float. */
8237 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", attr
);
8242 /* If TARGET_ABICALLS, tell GAS to generate -KPIC code. */
8243 if (TARGET_ABICALLS
)
8245 fprintf (asm_out_file
, "\t.abicalls\n");
8246 if (TARGET_ABICALLS_PIC0
)
8247 fprintf (asm_out_file
, "\t.option\tpic0\n");
8250 if (flag_verbose_asm
)
8251 fprintf (asm_out_file
, "\n%s -G value = %d, Arch = %s, ISA = %d\n",
8253 mips_small_data_threshold
, mips_arch_info
->name
, mips_isa
);
8256 /* Make the last instruction frame-related and note that it performs
8257 the operation described by FRAME_PATTERN. */
8260 mips_set_frame_expr (rtx frame_pattern
)
8264 insn
= get_last_insn ();
8265 RTX_FRAME_RELATED_P (insn
) = 1;
8266 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8271 /* Return a frame-related rtx that stores REG at MEM.
8272 REG must be a single register. */
8275 mips_frame_set (rtx mem
, rtx reg
)
8279 /* If we're saving the return address register and the DWARF return
8280 address column differs from the hard register number, adjust the
8281 note reg to refer to the former. */
8282 if (REGNO (reg
) == RETURN_ADDR_REGNUM
8283 && DWARF_FRAME_RETURN_COLUMN
!= RETURN_ADDR_REGNUM
)
8284 reg
= gen_rtx_REG (GET_MODE (reg
), DWARF_FRAME_RETURN_COLUMN
);
8286 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
8287 RTX_FRAME_RELATED_P (set
) = 1;
8292 /* If a MIPS16e SAVE or RESTORE instruction saves or restores register
8293 mips16e_s2_s8_regs[X], it must also save the registers in indexes
8294 X + 1 onwards. Likewise mips16e_a0_a3_regs. */
8295 static const unsigned char mips16e_s2_s8_regs
[] = {
8296 30, 23, 22, 21, 20, 19, 18
8298 static const unsigned char mips16e_a0_a3_regs
[] = {
8302 /* A list of the registers that can be saved by the MIPS16e SAVE instruction,
8303 ordered from the uppermost in memory to the lowest in memory. */
8304 static const unsigned char mips16e_save_restore_regs
[] = {
8305 31, 30, 23, 22, 21, 20, 19, 18, 17, 16, 7, 6, 5, 4
8308 /* Return the index of the lowest X in the range [0, SIZE) for which
8309 bit REGS[X] is set in MASK. Return SIZE if there is no such X. */
8312 mips16e_find_first_register (unsigned int mask
, const unsigned char *regs
,
8317 for (i
= 0; i
< size
; i
++)
8318 if (BITSET_P (mask
, regs
[i
]))
8324 /* *MASK_PTR is a mask of general-purpose registers and *NUM_REGS_PTR
8325 is the number of set bits. If *MASK_PTR contains REGS[X] for some X
8326 in [0, SIZE), adjust *MASK_PTR and *NUM_REGS_PTR so that the same
8327 is true for all indexes (X, SIZE). */
8330 mips16e_mask_registers (unsigned int *mask_ptr
, const unsigned char *regs
,
8331 unsigned int size
, unsigned int *num_regs_ptr
)
8335 i
= mips16e_find_first_register (*mask_ptr
, regs
, size
);
8336 for (i
++; i
< size
; i
++)
8337 if (!BITSET_P (*mask_ptr
, regs
[i
]))
8340 *mask_ptr
|= 1 << regs
[i
];
8344 /* Return a simplified form of X using the register values in REG_VALUES.
8345 REG_VALUES[R] is the last value assigned to hard register R, or null
8346 if R has not been modified.
8348 This function is rather limited, but is good enough for our purposes. */
8351 mips16e_collect_propagate_value (rtx x
, rtx
*reg_values
)
8353 x
= avoid_constant_pool_reference (x
);
8357 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8358 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
8359 x0
, GET_MODE (XEXP (x
, 0)));
8362 if (ARITHMETIC_P (x
))
8364 rtx x0
= mips16e_collect_propagate_value (XEXP (x
, 0), reg_values
);
8365 rtx x1
= mips16e_collect_propagate_value (XEXP (x
, 1), reg_values
);
8366 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), x0
, x1
);
8370 && reg_values
[REGNO (x
)]
8371 && !rtx_unstable_p (reg_values
[REGNO (x
)]))
8372 return reg_values
[REGNO (x
)];
8377 /* Return true if (set DEST SRC) stores an argument register into its
8378 caller-allocated save slot, storing the number of that argument
8379 register in *REGNO_PTR if so. REG_VALUES is as for
8380 mips16e_collect_propagate_value. */
8383 mips16e_collect_argument_save_p (rtx dest
, rtx src
, rtx
*reg_values
,
8384 unsigned int *regno_ptr
)
8386 unsigned int argno
, regno
;
8387 HOST_WIDE_INT offset
, required_offset
;
8390 /* Check that this is a word-mode store. */
8391 if (!MEM_P (dest
) || !REG_P (src
) || GET_MODE (dest
) != word_mode
)
8394 /* Check that the register being saved is an unmodified argument
8396 regno
= REGNO (src
);
8397 if (!IN_RANGE (regno
, GP_ARG_FIRST
, GP_ARG_LAST
) || reg_values
[regno
])
8399 argno
= regno
- GP_ARG_FIRST
;
8401 /* Check whether the address is an appropriate stack-pointer or
8402 frame-pointer access. */
8403 addr
= mips16e_collect_propagate_value (XEXP (dest
, 0), reg_values
);
8404 mips_split_plus (addr
, &base
, &offset
);
8405 required_offset
= cfun
->machine
->frame
.total_size
+ argno
* UNITS_PER_WORD
;
8406 if (base
== hard_frame_pointer_rtx
)
8407 required_offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
8408 else if (base
!= stack_pointer_rtx
)
8410 if (offset
!= required_offset
)
8417 /* A subroutine of mips_expand_prologue, called only when generating
8418 MIPS16e SAVE instructions. Search the start of the function for any
8419 instructions that save argument registers into their caller-allocated
8420 save slots. Delete such instructions and return a value N such that
8421 saving [GP_ARG_FIRST, GP_ARG_FIRST + N) would make all the deleted
8422 instructions redundant. */
8425 mips16e_collect_argument_saves (void)
8427 rtx reg_values
[FIRST_PSEUDO_REGISTER
];
8428 rtx insn
, next
, set
, dest
, src
;
8429 unsigned int nargs
, regno
;
8431 push_topmost_sequence ();
8433 memset (reg_values
, 0, sizeof (reg_values
));
8434 for (insn
= get_insns (); insn
; insn
= next
)
8436 next
= NEXT_INSN (insn
);
8437 if (NOTE_P (insn
) || DEBUG_INSN_P (insn
))
8443 set
= PATTERN (insn
);
8444 if (GET_CODE (set
) != SET
)
8447 dest
= SET_DEST (set
);
8448 src
= SET_SRC (set
);
8449 if (mips16e_collect_argument_save_p (dest
, src
, reg_values
, ®no
))
8451 if (!BITSET_P (cfun
->machine
->frame
.mask
, regno
))
8454 nargs
= MAX (nargs
, (regno
- GP_ARG_FIRST
) + 1);
8457 else if (REG_P (dest
) && GET_MODE (dest
) == word_mode
)
8458 reg_values
[REGNO (dest
)]
8459 = mips16e_collect_propagate_value (src
, reg_values
);
8463 pop_topmost_sequence ();
8468 /* Return a move between register REGNO and memory location SP + OFFSET.
8469 Make the move a load if RESTORE_P, otherwise make it a frame-related
8473 mips16e_save_restore_reg (bool restore_p
, HOST_WIDE_INT offset
,
8478 mem
= gen_frame_mem (SImode
, plus_constant (stack_pointer_rtx
, offset
));
8479 reg
= gen_rtx_REG (SImode
, regno
);
8481 ? gen_rtx_SET (VOIDmode
, reg
, mem
)
8482 : mips_frame_set (mem
, reg
));
8485 /* Return RTL for a MIPS16e SAVE or RESTORE instruction; RESTORE_P says which.
8486 The instruction must:
8488 - Allocate or deallocate SIZE bytes in total; SIZE is known
8491 - Save or restore as many registers in *MASK_PTR as possible.
8492 The instruction saves the first registers at the top of the
8493 allocated area, with the other registers below it.
8495 - Save NARGS argument registers above the allocated area.
8497 (NARGS is always zero if RESTORE_P.)
8499 The SAVE and RESTORE instructions cannot save and restore all general
8500 registers, so there may be some registers left over for the caller to
8501 handle. Destructively modify *MASK_PTR so that it contains the registers
8502 that still need to be saved or restored. The caller can save these
8503 registers in the memory immediately below *OFFSET_PTR, which is a
8504 byte offset from the bottom of the allocated stack area. */
8507 mips16e_build_save_restore (bool restore_p
, unsigned int *mask_ptr
,
8508 HOST_WIDE_INT
*offset_ptr
, unsigned int nargs
,
8512 HOST_WIDE_INT offset
, top_offset
;
8513 unsigned int i
, regno
;
8516 gcc_assert (cfun
->machine
->frame
.num_fp
== 0);
8518 /* Calculate the number of elements in the PARALLEL. We need one element
8519 for the stack adjustment, one for each argument register save, and one
8520 for each additional register move. */
8522 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8523 if (BITSET_P (*mask_ptr
, mips16e_save_restore_regs
[i
]))
8526 /* Create the final PARALLEL. */
8527 pattern
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (n
));
8530 /* Add the stack pointer adjustment. */
8531 set
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8532 plus_constant (stack_pointer_rtx
,
8533 restore_p
? size
: -size
));
8534 RTX_FRAME_RELATED_P (set
) = 1;
8535 XVECEXP (pattern
, 0, n
++) = set
;
8537 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8538 top_offset
= restore_p
? size
: 0;
8540 /* Save the arguments. */
8541 for (i
= 0; i
< nargs
; i
++)
8543 offset
= top_offset
+ i
* UNITS_PER_WORD
;
8544 set
= mips16e_save_restore_reg (restore_p
, offset
, GP_ARG_FIRST
+ i
);
8545 XVECEXP (pattern
, 0, n
++) = set
;
8548 /* Then fill in the other register moves. */
8549 offset
= top_offset
;
8550 for (i
= 0; i
< ARRAY_SIZE (mips16e_save_restore_regs
); i
++)
8552 regno
= mips16e_save_restore_regs
[i
];
8553 if (BITSET_P (*mask_ptr
, regno
))
8555 offset
-= UNITS_PER_WORD
;
8556 set
= mips16e_save_restore_reg (restore_p
, offset
, regno
);
8557 XVECEXP (pattern
, 0, n
++) = set
;
8558 *mask_ptr
&= ~(1 << regno
);
8562 /* Tell the caller what offset it should use for the remaining registers. */
8563 *offset_ptr
= size
+ (offset
- top_offset
);
8565 gcc_assert (n
== XVECLEN (pattern
, 0));
8570 /* PATTERN is a PARALLEL whose first element adds ADJUST to the stack
8571 pointer. Return true if PATTERN matches the kind of instruction
8572 generated by mips16e_build_save_restore. If INFO is nonnull,
8573 initialize it when returning true. */
8576 mips16e_save_restore_pattern_p (rtx pattern
, HOST_WIDE_INT adjust
,
8577 struct mips16e_save_restore_info
*info
)
8579 unsigned int i
, nargs
, mask
, extra
;
8580 HOST_WIDE_INT top_offset
, save_offset
, offset
;
8581 rtx set
, reg
, mem
, base
;
8584 if (!GENERATE_MIPS16E_SAVE_RESTORE
)
8587 /* Stack offsets in the PARALLEL are relative to the old stack pointer. */
8588 top_offset
= adjust
> 0 ? adjust
: 0;
8590 /* Interpret all other members of the PARALLEL. */
8591 save_offset
= top_offset
- UNITS_PER_WORD
;
8595 for (n
= 1; n
< XVECLEN (pattern
, 0); n
++)
8597 /* Check that we have a SET. */
8598 set
= XVECEXP (pattern
, 0, n
);
8599 if (GET_CODE (set
) != SET
)
8602 /* Check that the SET is a load (if restoring) or a store
8604 mem
= adjust
> 0 ? SET_SRC (set
) : SET_DEST (set
);
8608 /* Check that the address is the sum of the stack pointer and a
8609 possibly-zero constant offset. */
8610 mips_split_plus (XEXP (mem
, 0), &base
, &offset
);
8611 if (base
!= stack_pointer_rtx
)
8614 /* Check that SET's other operand is a register. */
8615 reg
= adjust
> 0 ? SET_DEST (set
) : SET_SRC (set
);
8619 /* Check for argument saves. */
8620 if (offset
== top_offset
+ nargs
* UNITS_PER_WORD
8621 && REGNO (reg
) == GP_ARG_FIRST
+ nargs
)
8623 else if (offset
== save_offset
)
8625 while (mips16e_save_restore_regs
[i
++] != REGNO (reg
))
8626 if (i
== ARRAY_SIZE (mips16e_save_restore_regs
))
8629 mask
|= 1 << REGNO (reg
);
8630 save_offset
-= UNITS_PER_WORD
;
8636 /* Check that the restrictions on register ranges are met. */
8638 mips16e_mask_registers (&mask
, mips16e_s2_s8_regs
,
8639 ARRAY_SIZE (mips16e_s2_s8_regs
), &extra
);
8640 mips16e_mask_registers (&mask
, mips16e_a0_a3_regs
,
8641 ARRAY_SIZE (mips16e_a0_a3_regs
), &extra
);
8645 /* Make sure that the topmost argument register is not saved twice.
8646 The checks above ensure that the same is then true for the other
8647 argument registers. */
8648 if (nargs
> 0 && BITSET_P (mask
, GP_ARG_FIRST
+ nargs
- 1))
8651 /* Pass back information, if requested. */
8654 info
->nargs
= nargs
;
8656 info
->size
= (adjust
> 0 ? adjust
: -adjust
);
8662 /* Add a MIPS16e SAVE or RESTORE register-range argument to string S
8663 for the register range [MIN_REG, MAX_REG]. Return a pointer to
8664 the null terminator. */
8667 mips16e_add_register_range (char *s
, unsigned int min_reg
,
8668 unsigned int max_reg
)
8670 if (min_reg
!= max_reg
)
8671 s
+= sprintf (s
, ",%s-%s", reg_names
[min_reg
], reg_names
[max_reg
]);
8673 s
+= sprintf (s
, ",%s", reg_names
[min_reg
]);
8677 /* Return the assembly instruction for a MIPS16e SAVE or RESTORE instruction.
8678 PATTERN and ADJUST are as for mips16e_save_restore_pattern_p. */
8681 mips16e_output_save_restore (rtx pattern
, HOST_WIDE_INT adjust
)
8683 static char buffer
[300];
8685 struct mips16e_save_restore_info info
;
8686 unsigned int i
, end
;
8689 /* Parse the pattern. */
8690 if (!mips16e_save_restore_pattern_p (pattern
, adjust
, &info
))
8693 /* Add the mnemonic. */
8694 s
= strcpy (buffer
, adjust
> 0 ? "restore\t" : "save\t");
8697 /* Save the arguments. */
8699 s
+= sprintf (s
, "%s-%s,", reg_names
[GP_ARG_FIRST
],
8700 reg_names
[GP_ARG_FIRST
+ info
.nargs
- 1]);
8701 else if (info
.nargs
== 1)
8702 s
+= sprintf (s
, "%s,", reg_names
[GP_ARG_FIRST
]);
8704 /* Emit the amount of stack space to allocate or deallocate. */
8705 s
+= sprintf (s
, "%d", (int) info
.size
);
8707 /* Save or restore $16. */
8708 if (BITSET_P (info
.mask
, 16))
8709 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 16]);
8711 /* Save or restore $17. */
8712 if (BITSET_P (info
.mask
, 17))
8713 s
+= sprintf (s
, ",%s", reg_names
[GP_REG_FIRST
+ 17]);
8715 /* Save or restore registers in the range $s2...$s8, which
8716 mips16e_s2_s8_regs lists in decreasing order. Note that this
8717 is a software register range; the hardware registers are not
8718 numbered consecutively. */
8719 end
= ARRAY_SIZE (mips16e_s2_s8_regs
);
8720 i
= mips16e_find_first_register (info
.mask
, mips16e_s2_s8_regs
, end
);
8722 s
= mips16e_add_register_range (s
, mips16e_s2_s8_regs
[end
- 1],
8723 mips16e_s2_s8_regs
[i
]);
8725 /* Save or restore registers in the range $a0...$a3. */
8726 end
= ARRAY_SIZE (mips16e_a0_a3_regs
);
8727 i
= mips16e_find_first_register (info
.mask
, mips16e_a0_a3_regs
, end
);
8729 s
= mips16e_add_register_range (s
, mips16e_a0_a3_regs
[i
],
8730 mips16e_a0_a3_regs
[end
- 1]);
8732 /* Save or restore $31. */
8733 if (BITSET_P (info
.mask
, RETURN_ADDR_REGNUM
))
8734 s
+= sprintf (s
, ",%s", reg_names
[RETURN_ADDR_REGNUM
]);
8739 /* Return true if the current function returns its value in a floating-point
8740 register in MIPS16 mode. */
8743 mips16_cfun_returns_in_fpr_p (void)
8745 tree return_type
= DECL_RESULT (current_function_decl
);
8746 return (TARGET_MIPS16
8747 && TARGET_HARD_FLOAT_ABI
8748 && !aggregate_value_p (return_type
, current_function_decl
)
8749 && mips_return_mode_in_fpr_p (DECL_MODE (return_type
)));
8752 /* Return true if predicate PRED is true for at least one instruction.
8753 Cache the result in *CACHE, and assume that the result is true
8754 if *CACHE is already true. */
8757 mips_find_gp_ref (bool *cache
, bool (*pred
) (rtx
))
8763 push_topmost_sequence ();
8764 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
8765 if (USEFUL_INSN_P (insn
) && pred (insn
))
8770 pop_topmost_sequence ();
8775 /* Return true if INSN refers to the global pointer in an "inflexible" way.
8776 See mips_cfun_has_inflexible_gp_ref_p for details. */
8779 mips_insn_has_inflexible_gp_ref_p (rtx insn
)
8781 /* Uses of pic_offset_table_rtx in CALL_INSN_FUNCTION_USAGE
8782 indicate that the target could be a traditional MIPS
8783 lazily-binding stub. */
8784 return find_reg_fusage (insn
, USE
, pic_offset_table_rtx
);
8787 /* Return true if the current function refers to the global pointer
8788 in a way that forces $28 to be valid. This means that we can't
8789 change the choice of global pointer, even for NewABI code.
8791 One example of this (and one which needs several checks) is that
8792 $28 must be valid when calling traditional MIPS lazy-binding stubs.
8793 (This restriction does not apply to PLTs.) */
8796 mips_cfun_has_inflexible_gp_ref_p (void)
8798 /* If the function has a nonlocal goto, $28 must hold the correct
8799 global pointer for the target function. That is, the target
8800 of the goto implicitly uses $28. */
8801 if (crtl
->has_nonlocal_goto
)
8804 if (TARGET_ABICALLS_PIC2
)
8806 /* Symbolic accesses implicitly use the global pointer unless
8807 -mexplicit-relocs is in effect. JAL macros to symbolic addresses
8808 might go to traditional MIPS lazy-binding stubs. */
8809 if (!TARGET_EXPLICIT_RELOCS
)
8812 /* FUNCTION_PROFILER includes a JAL to _mcount, which again
8813 can be lazily-bound. */
8817 /* MIPS16 functions that return in FPRs need to call an
8818 external libgcc routine. This call is only made explict
8819 during mips_expand_epilogue, and it too might be lazily bound. */
8820 if (mips16_cfun_returns_in_fpr_p ())
8824 return mips_find_gp_ref (&cfun
->machine
->has_inflexible_gp_insn_p
,
8825 mips_insn_has_inflexible_gp_ref_p
);
8828 /* Return true if INSN refers to the global pointer in a "flexible" way.
8829 See mips_cfun_has_flexible_gp_ref_p for details. */
8832 mips_insn_has_flexible_gp_ref_p (rtx insn
)
8834 return (get_attr_got (insn
) != GOT_UNSET
8835 || mips_small_data_pattern_p (PATTERN (insn
))
8836 || reg_overlap_mentioned_p (pic_offset_table_rtx
, PATTERN (insn
)));
8839 /* Return true if the current function references the global pointer,
8840 but if those references do not inherently require the global pointer
8841 to be $28. Assume !mips_cfun_has_inflexible_gp_ref_p (). */
8844 mips_cfun_has_flexible_gp_ref_p (void)
8846 /* Reload can sometimes introduce constant pool references
8847 into a function that otherwise didn't need them. For example,
8848 suppose we have an instruction like:
8850 (set (reg:DF R1) (float:DF (reg:SI R2)))
8852 If R2 turns out to be a constant such as 1, the instruction may
8853 have a REG_EQUAL note saying that R1 == 1.0. Reload then has
8854 the option of using this constant if R2 doesn't get allocated
8857 In cases like these, reload will have added the constant to the
8858 pool but no instruction will yet refer to it. */
8859 if (TARGET_ABICALLS_PIC2
&& !reload_completed
&& crtl
->uses_const_pool
)
8862 return mips_find_gp_ref (&cfun
->machine
->has_flexible_gp_insn_p
,
8863 mips_insn_has_flexible_gp_ref_p
);
8866 /* Return the register that should be used as the global pointer
8867 within this function. Return INVALID_REGNUM if the function
8868 doesn't need a global pointer. */
8871 mips_global_pointer (void)
8875 /* $gp is always available unless we're using a GOT. */
8876 if (!TARGET_USE_GOT
)
8877 return GLOBAL_POINTER_REGNUM
;
8879 /* If there are inflexible references to $gp, we must use the
8880 standard register. */
8881 if (mips_cfun_has_inflexible_gp_ref_p ())
8882 return GLOBAL_POINTER_REGNUM
;
8884 /* If there are no current references to $gp, then the only uses
8885 we can introduce later are those involved in long branches. */
8886 if (TARGET_ABSOLUTE_JUMPS
&& !mips_cfun_has_flexible_gp_ref_p ())
8887 return INVALID_REGNUM
;
8889 /* If the global pointer is call-saved, try to use a call-clobbered
8891 if (TARGET_CALL_SAVED_GP
&& current_function_is_leaf
)
8892 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
8893 if (!df_regs_ever_live_p (regno
)
8894 && call_really_used_regs
[regno
]
8895 && !fixed_regs
[regno
]
8896 && regno
!= PIC_FUNCTION_ADDR_REGNUM
)
8899 return GLOBAL_POINTER_REGNUM
;
8902 /* Return true if the current function's prologue must load the global
8903 pointer value into pic_offset_table_rtx and store the same value in
8904 the function's cprestore slot (if any).
8906 One problem we have to deal with is that, when emitting GOT-based
8907 position independent code, long-branch sequences will need to load
8908 the address of the branch target from the GOT. We don't know until
8909 the very end of compilation whether (and where) the function needs
8910 long branches, so we must ensure that _any_ branch can access the
8911 global pointer in some form. However, we do not want to pessimize
8912 the usual case in which all branches are short.
8914 We handle this as follows:
8916 (1) During reload, we set cfun->machine->global_pointer to
8917 INVALID_REGNUM if we _know_ that the current function
8918 doesn't need a global pointer. This is only valid if
8919 long branches don't need the GOT.
8921 Otherwise, we assume that we might need a global pointer
8922 and pick an appropriate register.
8924 (2) If cfun->machine->global_pointer != INVALID_REGNUM,
8925 we ensure that the global pointer is available at every
8926 block boundary bar entry and exit. We do this in one of two ways:
8928 - If the function has a cprestore slot, we ensure that this
8929 slot is valid at every branch. However, as explained in
8930 point (6) below, there is no guarantee that pic_offset_table_rtx
8931 itself is valid if new uses of the global pointer are introduced
8932 after the first post-epilogue split.
8934 We guarantee that the cprestore slot is valid by loading it
8935 into a fake register, CPRESTORE_SLOT_REGNUM. We then make
8936 this register live at every block boundary bar function entry
8937 and exit. It is then invalid to move the load (and thus the
8938 preceding store) across a block boundary.
8940 - If the function has no cprestore slot, we guarantee that
8941 pic_offset_table_rtx itself is valid at every branch.
8943 See mips_eh_uses for the handling of the register liveness.
8945 (3) During prologue and epilogue generation, we emit "ghost"
8946 placeholder instructions to manipulate the global pointer.
8948 (4) During prologue generation, we set cfun->machine->must_initialize_gp_p
8949 and cfun->machine->must_restore_gp_when_clobbered_p if we already know
8950 that the function needs a global pointer. (There is no need to set
8951 them earlier than this, and doing it as late as possible leads to
8952 fewer false positives.)
8954 (5) If cfun->machine->must_initialize_gp_p is true during a
8955 split_insns pass, we split the ghost instructions into real
8956 instructions. These split instructions can then be optimized in
8957 the usual way. Otherwise, we keep the ghost instructions intact,
8958 and optimize for the case where they aren't needed. We still
8959 have the option of splitting them later, if we need to introduce
8960 new uses of the global pointer.
8962 For example, the scheduler ignores a ghost instruction that
8963 stores $28 to the stack, but it handles the split form of
8964 the ghost instruction as an ordinary store.
8966 (6) [OldABI only.] If cfun->machine->must_restore_gp_when_clobbered_p
8967 is true during the first post-epilogue split_insns pass, we split
8968 calls and restore_gp patterns into instructions that explicitly
8969 load pic_offset_table_rtx from the cprestore slot. Otherwise,
8970 we split these patterns into instructions that _don't_ load from
8973 If cfun->machine->must_restore_gp_when_clobbered_p is true at the
8974 time of the split, then any instructions that exist at that time
8975 can make free use of pic_offset_table_rtx. However, if we want
8976 to introduce new uses of the global pointer after the split,
8977 we must explicitly load the value from the cprestore slot, since
8978 pic_offset_table_rtx itself might not be valid at a given point
8981 The idea is that we want to be able to delete redundant
8982 loads from the cprestore slot in the usual case where no
8983 long branches are needed.
8985 (7) If cfun->machine->must_initialize_gp_p is still false at the end
8986 of md_reorg, we decide whether the global pointer is needed for
8987 long branches. If so, we set cfun->machine->must_initialize_gp_p
8988 to true and split the ghost instructions into real instructions
8991 Note that the ghost instructions must have a zero length for three reasons:
8993 - Giving the length of the underlying $gp sequence might cause
8994 us to use long branches in cases where they aren't really needed.
8996 - They would perturb things like alignment calculations.
8998 - More importantly, the hazard detection in md_reorg relies on
8999 empty instructions having a zero length.
9001 If we find a long branch and split the ghost instructions at the
9002 end of md_reorg, the split could introduce more long branches.
9003 That isn't a problem though, because we still do the split before
9004 the final shorten_branches pass.
9006 This is extremely ugly, but it seems like the best compromise between
9007 correctness and efficiency. */
9010 mips_must_initialize_gp_p (void)
9012 return cfun
->machine
->must_initialize_gp_p
;
9015 /* Return true if REGNO is a register that is ordinarily call-clobbered
9016 but must nevertheless be preserved by an interrupt handler. */
9019 mips_interrupt_extra_call_saved_reg_p (unsigned int regno
)
9021 if (MD_REG_P (regno
))
9024 if (TARGET_DSP
&& DSP_ACC_REG_P (regno
))
9027 if (GP_REG_P (regno
) && !cfun
->machine
->use_shadow_register_set_p
)
9029 /* $0 is hard-wired. */
9030 if (regno
== GP_REG_FIRST
)
9033 /* The interrupt handler can treat kernel registers as
9034 scratch registers. */
9035 if (KERNEL_REG_P (regno
))
9038 /* The function will return the stack pointer to its original value
9040 if (regno
== STACK_POINTER_REGNUM
)
9043 /* Otherwise, return true for registers that aren't ordinarily
9045 return call_really_used_regs
[regno
];
9051 /* Return true if the current function should treat register REGNO
9055 mips_cfun_call_saved_reg_p (unsigned int regno
)
9057 /* Interrupt handlers need to save extra registers. */
9058 if (cfun
->machine
->interrupt_handler_p
9059 && mips_interrupt_extra_call_saved_reg_p (regno
))
9062 /* call_insns preserve $28 unless they explicitly say otherwise,
9063 so call_really_used_regs[] treats $28 as call-saved. However,
9064 we want the ABI property rather than the default call_insn
9066 return (regno
== GLOBAL_POINTER_REGNUM
9067 ? TARGET_CALL_SAVED_GP
9068 : !call_really_used_regs
[regno
]);
9071 /* Return true if the function body might clobber register REGNO.
9072 We know that REGNO is call-saved. */
9075 mips_cfun_might_clobber_call_saved_reg_p (unsigned int regno
)
9077 /* Some functions should be treated as clobbering all call-saved
9079 if (crtl
->saves_all_registers
)
9082 /* DF handles cases where a register is explicitly referenced in
9083 the rtl. Incoming values are passed in call-clobbered registers,
9084 so we can assume that any live call-saved register is set within
9086 if (df_regs_ever_live_p (regno
))
9089 /* Check for registers that are clobbered by FUNCTION_PROFILER.
9090 These clobbers are not explicit in the rtl. */
9091 if (crtl
->profile
&& MIPS_SAVE_REG_FOR_PROFILING_P (regno
))
9094 /* If we're using a call-saved global pointer, the function's
9095 prologue will need to set it up. */
9096 if (cfun
->machine
->global_pointer
== regno
)
9099 /* The function's prologue will need to set the frame pointer if
9100 frame_pointer_needed. */
9101 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
9104 /* If a MIPS16 function returns a value in FPRs, its epilogue
9105 will need to call an external libgcc routine. This yet-to-be
9106 generated call_insn will clobber $31. */
9107 if (regno
== RETURN_ADDR_REGNUM
&& mips16_cfun_returns_in_fpr_p ())
9110 /* If REGNO is ordinarily call-clobbered, we must assume that any
9111 called function could modify it. */
9112 if (cfun
->machine
->interrupt_handler_p
9113 && !current_function_is_leaf
9114 && mips_interrupt_extra_call_saved_reg_p (regno
))
9120 /* Return true if the current function must save register REGNO. */
9123 mips_save_reg_p (unsigned int regno
)
9125 if (mips_cfun_call_saved_reg_p (regno
))
9127 if (mips_cfun_might_clobber_call_saved_reg_p (regno
))
9130 /* Save both registers in an FPR pair if either one is used. This is
9131 needed for the case when MIN_FPRS_PER_FMT == 1, which allows the odd
9132 register to be used without the even register. */
9133 if (FP_REG_P (regno
)
9134 && MAX_FPRS_PER_FMT
== 2
9135 && mips_cfun_might_clobber_call_saved_reg_p (regno
+ 1))
9139 /* We need to save the incoming return address if __builtin_eh_return
9140 is being used to set a different return address. */
9141 if (regno
== RETURN_ADDR_REGNUM
&& crtl
->calls_eh_return
)
9147 /* Populate the current function's mips_frame_info structure.
9149 MIPS stack frames look like:
9151 +-------------------------------+
9153 | incoming stack arguments |
9155 +-------------------------------+
9157 | caller-allocated save area |
9158 A | for register arguments |
9160 +-------------------------------+ <-- incoming stack pointer
9162 | callee-allocated save area |
9163 B | for arguments that are |
9164 | split between registers and |
9167 +-------------------------------+ <-- arg_pointer_rtx
9169 C | callee-allocated save area |
9170 | for register varargs |
9172 +-------------------------------+ <-- frame_pointer_rtx
9173 | | + cop0_sp_offset
9174 | COP0 reg save area | + UNITS_PER_WORD
9176 +-------------------------------+ <-- frame_pointer_rtx + acc_sp_offset
9177 | | + UNITS_PER_WORD
9178 | accumulator save area |
9180 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
9181 | | + UNITS_PER_HWFPVALUE
9184 +-------------------------------+ <-- stack_pointer_rtx + gp_sp_offset
9185 | | + UNITS_PER_WORD
9188 +-------------------------------+ <-- frame_pointer_rtx with
9189 | | \ -fstack-protector
9190 | local variables | | var_size
9192 +-------------------------------+
9194 | $gp save area | | cprestore_size
9196 P +-------------------------------+ <-- hard_frame_pointer_rtx for
9198 | outgoing stack arguments | |
9200 +-------------------------------+ | args_size
9202 | caller-allocated save area | |
9203 | for register arguments | |
9205 +-------------------------------+ <-- stack_pointer_rtx
9206 frame_pointer_rtx without
9208 hard_frame_pointer_rtx for
9211 At least two of A, B and C will be empty.
9213 Dynamic stack allocations such as alloca insert data at point P.
9214 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
9215 hard_frame_pointer_rtx unchanged. */
9218 mips_compute_frame_info (void)
9220 struct mips_frame_info
*frame
;
9221 HOST_WIDE_INT offset
, size
;
9222 unsigned int regno
, i
;
9224 /* Set this function's interrupt properties. */
9225 if (mips_interrupt_type_p (TREE_TYPE (current_function_decl
)))
9228 error ("the %<interrupt%> attribute requires a MIPS32r2 processor");
9229 else if (TARGET_HARD_FLOAT
)
9230 error ("the %<interrupt%> attribute requires %<-msoft-float%>");
9231 else if (TARGET_MIPS16
)
9232 error ("interrupt handlers cannot be MIPS16 functions");
9235 cfun
->machine
->interrupt_handler_p
= true;
9236 cfun
->machine
->use_shadow_register_set_p
=
9237 mips_use_shadow_register_set_p (TREE_TYPE (current_function_decl
));
9238 cfun
->machine
->keep_interrupts_masked_p
=
9239 mips_keep_interrupts_masked_p (TREE_TYPE (current_function_decl
));
9240 cfun
->machine
->use_debug_exception_return_p
=
9241 mips_use_debug_exception_return_p (TREE_TYPE
9242 (current_function_decl
));
9246 frame
= &cfun
->machine
->frame
;
9247 memset (frame
, 0, sizeof (*frame
));
9248 size
= get_frame_size ();
9250 cfun
->machine
->global_pointer
= mips_global_pointer ();
9252 /* The first two blocks contain the outgoing argument area and the $gp save
9253 slot. This area isn't needed in leaf functions, but if the
9254 target-independent frame size is nonzero, we have already committed to
9255 allocating these in STARTING_FRAME_OFFSET for !FRAME_GROWS_DOWNWARD. */
9256 if ((size
== 0 || FRAME_GROWS_DOWNWARD
) && current_function_is_leaf
)
9258 /* The MIPS 3.0 linker does not like functions that dynamically
9259 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
9260 looks like we are trying to create a second frame pointer to the
9261 function, so allocate some stack space to make it happy. */
9262 if (cfun
->calls_alloca
)
9263 frame
->args_size
= REG_PARM_STACK_SPACE (cfun
->decl
);
9265 frame
->args_size
= 0;
9266 frame
->cprestore_size
= 0;
9270 frame
->args_size
= crtl
->outgoing_args_size
;
9271 frame
->cprestore_size
= MIPS_GP_SAVE_AREA_SIZE
;
9273 offset
= frame
->args_size
+ frame
->cprestore_size
;
9275 /* Move above the local variables. */
9276 frame
->var_size
= MIPS_STACK_ALIGN (size
);
9277 offset
+= frame
->var_size
;
9279 /* Find out which GPRs we need to save. */
9280 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
9281 if (mips_save_reg_p (regno
))
9284 frame
->mask
|= 1 << (regno
- GP_REG_FIRST
);
9287 /* If this function calls eh_return, we must also save and restore the
9288 EH data registers. */
9289 if (crtl
->calls_eh_return
)
9290 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
9293 frame
->mask
|= 1 << (EH_RETURN_DATA_REGNO (i
) - GP_REG_FIRST
);
9296 /* The MIPS16e SAVE and RESTORE instructions have two ranges of registers:
9297 $a3-$a0 and $s2-$s8. If we save one register in the range, we must
9298 save all later registers too. */
9299 if (GENERATE_MIPS16E_SAVE_RESTORE
)
9301 mips16e_mask_registers (&frame
->mask
, mips16e_s2_s8_regs
,
9302 ARRAY_SIZE (mips16e_s2_s8_regs
), &frame
->num_gp
);
9303 mips16e_mask_registers (&frame
->mask
, mips16e_a0_a3_regs
,
9304 ARRAY_SIZE (mips16e_a0_a3_regs
), &frame
->num_gp
);
9307 /* Move above the GPR save area. */
9308 if (frame
->num_gp
> 0)
9310 offset
+= MIPS_STACK_ALIGN (frame
->num_gp
* UNITS_PER_WORD
);
9311 frame
->gp_sp_offset
= offset
- UNITS_PER_WORD
;
9314 /* Find out which FPRs we need to save. This loop must iterate over
9315 the same space as its companion in mips_for_each_saved_gpr_and_fpr. */
9316 if (TARGET_HARD_FLOAT
)
9317 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= MAX_FPRS_PER_FMT
)
9318 if (mips_save_reg_p (regno
))
9320 frame
->num_fp
+= MAX_FPRS_PER_FMT
;
9321 frame
->fmask
|= ~(~0 << MAX_FPRS_PER_FMT
) << (regno
- FP_REG_FIRST
);
9324 /* Move above the FPR save area. */
9325 if (frame
->num_fp
> 0)
9327 offset
+= MIPS_STACK_ALIGN (frame
->num_fp
* UNITS_PER_FPREG
);
9328 frame
->fp_sp_offset
= offset
- UNITS_PER_HWFPVALUE
;
9331 /* Add in space for the interrupt context information. */
9332 if (cfun
->machine
->interrupt_handler_p
)
9335 if (mips_save_reg_p (LO_REGNUM
) || mips_save_reg_p (HI_REGNUM
))
9338 frame
->acc_mask
|= (1 << 0);
9341 /* Check accumulators 1, 2, 3. */
9342 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
9343 if (mips_save_reg_p (i
) || mips_save_reg_p (i
+ 1))
9346 frame
->acc_mask
|= 1 << (((i
- DSP_ACC_REG_FIRST
) / 2) + 1);
9349 /* All interrupt context functions need space to preserve STATUS. */
9350 frame
->num_cop0_regs
++;
9352 /* If we don't keep interrupts masked, we need to save EPC. */
9353 if (!cfun
->machine
->keep_interrupts_masked_p
)
9354 frame
->num_cop0_regs
++;
9357 /* Move above the accumulator save area. */
9358 if (frame
->num_acc
> 0)
9360 /* Each accumulator needs 2 words. */
9361 offset
+= frame
->num_acc
* 2 * UNITS_PER_WORD
;
9362 frame
->acc_sp_offset
= offset
- UNITS_PER_WORD
;
9365 /* Move above the COP0 register save area. */
9366 if (frame
->num_cop0_regs
> 0)
9368 offset
+= frame
->num_cop0_regs
* UNITS_PER_WORD
;
9369 frame
->cop0_sp_offset
= offset
- UNITS_PER_WORD
;
9372 /* Move above the callee-allocated varargs save area. */
9373 offset
+= MIPS_STACK_ALIGN (cfun
->machine
->varargs_size
);
9374 frame
->arg_pointer_offset
= offset
;
9376 /* Move above the callee-allocated area for pretend stack arguments. */
9377 offset
+= crtl
->args
.pretend_args_size
;
9378 frame
->total_size
= offset
;
9380 /* Work out the offsets of the save areas from the top of the frame. */
9381 if (frame
->gp_sp_offset
> 0)
9382 frame
->gp_save_offset
= frame
->gp_sp_offset
- offset
;
9383 if (frame
->fp_sp_offset
> 0)
9384 frame
->fp_save_offset
= frame
->fp_sp_offset
- offset
;
9385 if (frame
->acc_sp_offset
> 0)
9386 frame
->acc_save_offset
= frame
->acc_sp_offset
- offset
;
9387 if (frame
->num_cop0_regs
> 0)
9388 frame
->cop0_save_offset
= frame
->cop0_sp_offset
- offset
;
9390 /* MIPS16 code offsets the frame pointer by the size of the outgoing
9391 arguments. This tends to increase the chances of using unextended
9392 instructions for local variables and incoming arguments. */
9394 frame
->hard_frame_pointer_offset
= frame
->args_size
;
9397 /* Return the style of GP load sequence that is being used for the
9398 current function. */
9400 enum mips_loadgp_style
9401 mips_current_loadgp_style (void)
9403 if (!TARGET_USE_GOT
|| cfun
->machine
->global_pointer
== INVALID_REGNUM
)
9409 if (TARGET_ABSOLUTE_ABICALLS
)
9410 return LOADGP_ABSOLUTE
;
9412 return TARGET_NEWABI
? LOADGP_NEWABI
: LOADGP_OLDABI
;
9415 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
9418 mips_frame_pointer_required (void)
9420 /* If the function contains dynamic stack allocations, we need to
9421 use the frame pointer to access the static parts of the frame. */
9422 if (cfun
->calls_alloca
)
9425 /* In MIPS16 mode, we need a frame pointer for a large frame; otherwise,
9426 reload may be unable to compute the address of a local variable,
9427 since there is no way to add a large constant to the stack pointer
9428 without using a second temporary register. */
9431 mips_compute_frame_info ();
9432 if (!SMALL_OPERAND (cfun
->machine
->frame
.total_size
))
9439 /* Make sure that we're not trying to eliminate to the wrong hard frame
9443 mips_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
9445 return (to
== HARD_FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
9448 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
9449 or argument pointer. TO is either the stack pointer or hard frame
9453 mips_initial_elimination_offset (int from
, int to
)
9455 HOST_WIDE_INT offset
;
9457 mips_compute_frame_info ();
9459 /* Set OFFSET to the offset from the end-of-prologue stack pointer. */
9462 case FRAME_POINTER_REGNUM
:
9463 if (FRAME_GROWS_DOWNWARD
)
9464 offset
= (cfun
->machine
->frame
.args_size
9465 + cfun
->machine
->frame
.cprestore_size
9466 + cfun
->machine
->frame
.var_size
);
9471 case ARG_POINTER_REGNUM
:
9472 offset
= cfun
->machine
->frame
.arg_pointer_offset
;
9479 if (to
== HARD_FRAME_POINTER_REGNUM
)
9480 offset
-= cfun
->machine
->frame
.hard_frame_pointer_offset
;
9485 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. */
9488 mips_extra_live_on_entry (bitmap regs
)
9492 /* PIC_FUNCTION_ADDR_REGNUM is live if we need it to set up
9493 the global pointer. */
9494 if (!TARGET_ABSOLUTE_ABICALLS
)
9495 bitmap_set_bit (regs
, PIC_FUNCTION_ADDR_REGNUM
);
9497 /* The prologue may set MIPS16_PIC_TEMP_REGNUM to the value of
9498 the global pointer. */
9500 bitmap_set_bit (regs
, MIPS16_PIC_TEMP_REGNUM
);
9502 /* See the comment above load_call<mode> for details. */
9503 bitmap_set_bit (regs
, GOT_VERSION_REGNUM
);
9507 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
9511 mips_return_addr (int count
, rtx frame ATTRIBUTE_UNUSED
)
9516 return get_hard_reg_initial_val (Pmode
, RETURN_ADDR_REGNUM
);
9519 /* Emit code to change the current function's return address to
9520 ADDRESS. SCRATCH is available as a scratch register, if needed.
9521 ADDRESS and SCRATCH are both word-mode GPRs. */
9524 mips_set_return_address (rtx address
, rtx scratch
)
9528 gcc_assert (BITSET_P (cfun
->machine
->frame
.mask
, RETURN_ADDR_REGNUM
));
9529 slot_address
= mips_add_offset (scratch
, stack_pointer_rtx
,
9530 cfun
->machine
->frame
.gp_sp_offset
);
9531 mips_emit_move (gen_frame_mem (GET_MODE (address
), slot_address
), address
);
9534 /* Return true if the current function has a cprestore slot. */
9537 mips_cfun_has_cprestore_slot_p (void)
9539 return (cfun
->machine
->global_pointer
!= INVALID_REGNUM
9540 && cfun
->machine
->frame
.cprestore_size
> 0);
9543 /* Fill *BASE and *OFFSET such that *BASE + *OFFSET refers to the
9544 cprestore slot. LOAD_P is true if the caller wants to load from
9545 the cprestore slot; it is false if the caller wants to store to
9549 mips_get_cprestore_base_and_offset (rtx
*base
, HOST_WIDE_INT
*offset
,
9552 const struct mips_frame_info
*frame
;
9554 frame
= &cfun
->machine
->frame
;
9555 /* .cprestore always uses the stack pointer instead of the frame pointer.
9556 We have a free choice for direct stores for non-MIPS16 functions,
9557 and for MIPS16 functions whose cprestore slot is in range of the
9558 stack pointer. Using the stack pointer would sometimes give more
9559 (early) scheduling freedom, but using the frame pointer would
9560 sometimes give more (late) scheduling freedom. It's hard to
9561 predict which applies to a given function, so let's keep things
9564 Loads must always use the frame pointer in functions that call
9565 alloca, and there's little benefit to using the stack pointer
9567 if (frame_pointer_needed
&& !(TARGET_CPRESTORE_DIRECTIVE
&& !load_p
))
9569 *base
= hard_frame_pointer_rtx
;
9570 *offset
= frame
->args_size
- frame
->hard_frame_pointer_offset
;
9574 *base
= stack_pointer_rtx
;
9575 *offset
= frame
->args_size
;
9579 /* Return true if X is the load or store address of the cprestore slot;
9580 LOAD_P says which. */
9583 mips_cprestore_address_p (rtx x
, bool load_p
)
9585 rtx given_base
, required_base
;
9586 HOST_WIDE_INT given_offset
, required_offset
;
9588 mips_split_plus (x
, &given_base
, &given_offset
);
9589 mips_get_cprestore_base_and_offset (&required_base
, &required_offset
, load_p
);
9590 return given_base
== required_base
&& given_offset
== required_offset
;
9593 /* Return a MEM rtx for the cprestore slot. LOAD_P is true if we are
9594 going to load from it, false if we are going to store to it.
9595 Use TEMP as a temporary register if need be. */
9598 mips_cprestore_slot (rtx temp
, bool load_p
)
9601 HOST_WIDE_INT offset
;
9603 mips_get_cprestore_base_and_offset (&base
, &offset
, load_p
);
9604 return gen_frame_mem (Pmode
, mips_add_offset (temp
, base
, offset
));
9607 /* Emit instructions to save global pointer value GP into cprestore
9608 slot MEM. OFFSET is the offset that MEM applies to the base register.
9610 MEM may not be a legitimate address. If it isn't, TEMP is a
9611 temporary register that can be used, otherwise it is a SCRATCH. */
9614 mips_save_gp_to_cprestore_slot (rtx mem
, rtx offset
, rtx gp
, rtx temp
)
9616 if (TARGET_CPRESTORE_DIRECTIVE
)
9618 gcc_assert (gp
== pic_offset_table_rtx
);
9619 emit_insn (gen_cprestore (mem
, offset
));
9622 mips_emit_move (mips_cprestore_slot (temp
, false), gp
);
9625 /* Restore $gp from its save slot, using TEMP as a temporary base register
9626 if need be. This function is for o32 and o64 abicalls only.
9628 See mips_must_initialize_gp_p for details about how we manage the
9632 mips_restore_gp_from_cprestore_slot (rtx temp
)
9634 gcc_assert (TARGET_ABICALLS
&& TARGET_OLDABI
&& epilogue_completed
);
9636 if (!cfun
->machine
->must_restore_gp_when_clobbered_p
)
9638 emit_note (NOTE_INSN_DELETED
);
9644 mips_emit_move (temp
, mips_cprestore_slot (temp
, true));
9645 mips_emit_move (pic_offset_table_rtx
, temp
);
9648 mips_emit_move (pic_offset_table_rtx
, mips_cprestore_slot (temp
, true));
9649 if (!TARGET_EXPLICIT_RELOCS
)
9650 emit_insn (gen_blockage ());
9653 /* A function to save or store a register. The first argument is the
9654 register and the second is the stack slot. */
9655 typedef void (*mips_save_restore_fn
) (rtx
, rtx
);
9657 /* Use FN to save or restore register REGNO. MODE is the register's
9658 mode and OFFSET is the offset of its save slot from the current
9662 mips_save_restore_reg (enum machine_mode mode
, int regno
,
9663 HOST_WIDE_INT offset
, mips_save_restore_fn fn
)
9667 mem
= gen_frame_mem (mode
, plus_constant (stack_pointer_rtx
, offset
));
9668 fn (gen_rtx_REG (mode
, regno
), mem
);
9671 /* Call FN for each accumlator that is saved by the current function.
9672 SP_OFFSET is the offset of the current stack pointer from the start
9676 mips_for_each_saved_acc (HOST_WIDE_INT sp_offset
, mips_save_restore_fn fn
)
9678 HOST_WIDE_INT offset
;
9681 offset
= cfun
->machine
->frame
.acc_sp_offset
- sp_offset
;
9682 if (BITSET_P (cfun
->machine
->frame
.acc_mask
, 0))
9684 mips_save_restore_reg (word_mode
, LO_REGNUM
, offset
, fn
);
9685 offset
-= UNITS_PER_WORD
;
9686 mips_save_restore_reg (word_mode
, HI_REGNUM
, offset
, fn
);
9687 offset
-= UNITS_PER_WORD
;
9690 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
9691 if (BITSET_P (cfun
->machine
->frame
.acc_mask
,
9692 ((regno
- DSP_ACC_REG_FIRST
) / 2) + 1))
9694 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
9695 offset
-= UNITS_PER_WORD
;
9699 /* Call FN for each register that is saved by the current function.
9700 SP_OFFSET is the offset of the current stack pointer from the start
9704 mips_for_each_saved_gpr_and_fpr (HOST_WIDE_INT sp_offset
,
9705 mips_save_restore_fn fn
)
9707 enum machine_mode fpr_mode
;
9708 HOST_WIDE_INT offset
;
9711 /* Save registers starting from high to low. The debuggers prefer at least
9712 the return register be stored at func+4, and also it allows us not to
9713 need a nop in the epilogue if at least one register is reloaded in
9714 addition to return address. */
9715 offset
= cfun
->machine
->frame
.gp_sp_offset
- sp_offset
;
9716 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
9717 if (BITSET_P (cfun
->machine
->frame
.mask
, regno
- GP_REG_FIRST
))
9719 /* Record the ra offset for use by mips_function_profiler. */
9720 if (regno
== RETURN_ADDR_REGNUM
)
9721 cfun
->machine
->frame
.ra_fp_offset
= offset
+ sp_offset
;
9722 mips_save_restore_reg (word_mode
, regno
, offset
, fn
);
9723 offset
-= UNITS_PER_WORD
;
9726 /* This loop must iterate over the same space as its companion in
9727 mips_compute_frame_info. */
9728 offset
= cfun
->machine
->frame
.fp_sp_offset
- sp_offset
;
9729 fpr_mode
= (TARGET_SINGLE_FLOAT
? SFmode
: DFmode
);
9730 for (regno
= FP_REG_LAST
- MAX_FPRS_PER_FMT
+ 1;
9731 regno
>= FP_REG_FIRST
;
9732 regno
-= MAX_FPRS_PER_FMT
)
9733 if (BITSET_P (cfun
->machine
->frame
.fmask
, regno
- FP_REG_FIRST
))
9735 mips_save_restore_reg (fpr_mode
, regno
, offset
, fn
);
9736 offset
-= GET_MODE_SIZE (fpr_mode
);
9740 /* Return true if a move between register REGNO and its save slot (MEM)
9741 can be done in a single move. LOAD_P is true if we are loading
9742 from the slot, false if we are storing to it. */
9745 mips_direct_save_slot_move_p (unsigned int regno
, rtx mem
, bool load_p
)
9747 /* There is a specific MIPS16 instruction for saving $31 to the stack. */
9748 if (TARGET_MIPS16
&& !load_p
&& regno
== RETURN_ADDR_REGNUM
)
9751 return mips_secondary_reload_class (REGNO_REG_CLASS (regno
),
9752 GET_MODE (mem
), mem
, load_p
) == NO_REGS
;
9755 /* Emit a move from SRC to DEST, given that one of them is a register
9756 save slot and that the other is a register. TEMP is a temporary
9757 GPR of the same mode that is available if need be. */
9760 mips_emit_save_slot_move (rtx dest
, rtx src
, rtx temp
)
9767 regno
= REGNO (src
);
9772 regno
= REGNO (dest
);
9776 if (regno
== cfun
->machine
->global_pointer
&& !mips_must_initialize_gp_p ())
9778 /* We don't yet know whether we'll need this instruction or not.
9779 Postpone the decision by emitting a ghost move. This move
9780 is specifically not frame-related; only the split version is. */
9782 emit_insn (gen_move_gpdi (dest
, src
));
9784 emit_insn (gen_move_gpsi (dest
, src
));
9788 if (regno
== HI_REGNUM
)
9792 mips_emit_move (temp
, src
);
9794 emit_insn (gen_mthisi_di (gen_rtx_REG (TImode
, MD_REG_FIRST
),
9795 temp
, gen_rtx_REG (DImode
, LO_REGNUM
)));
9797 emit_insn (gen_mthisi_di (gen_rtx_REG (DImode
, MD_REG_FIRST
),
9798 temp
, gen_rtx_REG (SImode
, LO_REGNUM
)));
9803 emit_insn (gen_mfhidi_ti (temp
,
9804 gen_rtx_REG (TImode
, MD_REG_FIRST
)));
9806 emit_insn (gen_mfhisi_di (temp
,
9807 gen_rtx_REG (DImode
, MD_REG_FIRST
)));
9808 mips_emit_move (dest
, temp
);
9811 else if (mips_direct_save_slot_move_p (regno
, mem
, mem
== src
))
9812 mips_emit_move (dest
, src
);
9815 gcc_assert (!reg_overlap_mentioned_p (dest
, temp
));
9816 mips_emit_move (temp
, src
);
9817 mips_emit_move (dest
, temp
);
9820 mips_set_frame_expr (mips_frame_set (dest
, src
));
9823 /* If we're generating n32 or n64 abicalls, and the current function
9824 does not use $28 as its global pointer, emit a cplocal directive.
9825 Use pic_offset_table_rtx as the argument to the directive. */
9828 mips_output_cplocal (void)
9830 if (!TARGET_EXPLICIT_RELOCS
9831 && mips_must_initialize_gp_p ()
9832 && cfun
->machine
->global_pointer
!= GLOBAL_POINTER_REGNUM
)
9833 output_asm_insn (".cplocal %+", 0);
9836 /* Implement TARGET_OUTPUT_FUNCTION_PROLOGUE. */
9839 mips_output_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
9843 #ifdef SDB_DEBUGGING_INFO
9844 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
9845 SDB_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
9848 /* In MIPS16 mode, we may need to generate a non-MIPS16 stub to handle
9849 floating-point arguments. */
9851 && TARGET_HARD_FLOAT_ABI
9852 && crtl
->args
.info
.fp_code
!= 0)
9853 mips16_build_function_stub ();
9855 /* Get the function name the same way that toplev.c does before calling
9856 assemble_start_function. This is needed so that the name used here
9857 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9858 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9859 mips_start_function_definition (fnname
, TARGET_MIPS16
);
9861 /* Output MIPS-specific frame information. */
9862 if (!flag_inhibit_size_directive
)
9864 const struct mips_frame_info
*frame
;
9866 frame
= &cfun
->machine
->frame
;
9868 /* .frame FRAMEREG, FRAMESIZE, RETREG. */
9870 "\t.frame\t%s," HOST_WIDE_INT_PRINT_DEC
",%s\t\t"
9871 "# vars= " HOST_WIDE_INT_PRINT_DEC
9873 ", args= " HOST_WIDE_INT_PRINT_DEC
9874 ", gp= " HOST_WIDE_INT_PRINT_DEC
"\n",
9875 reg_names
[frame_pointer_needed
9876 ? HARD_FRAME_POINTER_REGNUM
9877 : STACK_POINTER_REGNUM
],
9878 (frame_pointer_needed
9879 ? frame
->total_size
- frame
->hard_frame_pointer_offset
9880 : frame
->total_size
),
9881 reg_names
[RETURN_ADDR_REGNUM
],
9883 frame
->num_gp
, frame
->num_fp
,
9885 frame
->cprestore_size
);
9887 /* .mask MASK, OFFSET. */
9888 fprintf (file
, "\t.mask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
9889 frame
->mask
, frame
->gp_save_offset
);
9891 /* .fmask MASK, OFFSET. */
9892 fprintf (file
, "\t.fmask\t0x%08x," HOST_WIDE_INT_PRINT_DEC
"\n",
9893 frame
->fmask
, frame
->fp_save_offset
);
9896 /* Handle the initialization of $gp for SVR4 PIC, if applicable.
9897 Also emit the ".set noreorder; .set nomacro" sequence for functions
9899 if (mips_must_initialize_gp_p ()
9900 && mips_current_loadgp_style () == LOADGP_OLDABI
)
9904 /* This is a fixed-form sequence. The position of the
9905 first two instructions is important because of the
9906 way _gp_disp is defined. */
9907 output_asm_insn ("li\t$2,%%hi(_gp_disp)", 0);
9908 output_asm_insn ("addiu\t$3,$pc,%%lo(_gp_disp)", 0);
9909 output_asm_insn ("sll\t$2,16", 0);
9910 output_asm_insn ("addu\t$2,$3", 0);
9914 /* .cpload must be in a .set noreorder but not a
9915 .set nomacro block. */
9916 mips_push_asm_switch (&mips_noreorder
);
9917 output_asm_insn (".cpload\t%^", 0);
9918 if (!cfun
->machine
->all_noreorder_p
)
9919 mips_pop_asm_switch (&mips_noreorder
);
9921 mips_push_asm_switch (&mips_nomacro
);
9924 else if (cfun
->machine
->all_noreorder_p
)
9926 mips_push_asm_switch (&mips_noreorder
);
9927 mips_push_asm_switch (&mips_nomacro
);
9930 /* Tell the assembler which register we're using as the global
9931 pointer. This is needed for thunks, since they can use either
9932 explicit relocs or assembler macros. */
9933 mips_output_cplocal ();
9936 /* Implement TARGET_OUTPUT_FUNCTION_EPILOGUE. */
9939 mips_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
9940 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
9944 /* Reinstate the normal $gp. */
9945 SET_REGNO (pic_offset_table_rtx
, GLOBAL_POINTER_REGNUM
);
9946 mips_output_cplocal ();
9948 if (cfun
->machine
->all_noreorder_p
)
9950 mips_pop_asm_switch (&mips_nomacro
);
9951 mips_pop_asm_switch (&mips_noreorder
);
9954 /* Get the function name the same way that toplev.c does before calling
9955 assemble_start_function. This is needed so that the name used here
9956 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
9957 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
9958 mips_end_function_definition (fnname
);
9961 /* Save register REG to MEM. Make the instruction frame-related. */
9964 mips_save_reg (rtx reg
, rtx mem
)
9966 if (GET_MODE (reg
) == DFmode
&& !TARGET_FLOAT64
)
9970 if (mips_split_64bit_move_p (mem
, reg
))
9971 mips_split_doubleword_move (mem
, reg
);
9973 mips_emit_move (mem
, reg
);
9975 x1
= mips_frame_set (mips_subword (mem
, false),
9976 mips_subword (reg
, false));
9977 x2
= mips_frame_set (mips_subword (mem
, true),
9978 mips_subword (reg
, true));
9979 mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, x1
, x2
)));
9982 mips_emit_save_slot_move (mem
, reg
, MIPS_PROLOGUE_TEMP (GET_MODE (reg
)));
9985 /* The __gnu_local_gp symbol. */
9987 static GTY(()) rtx mips_gnu_local_gp
;
9989 /* If we're generating n32 or n64 abicalls, emit instructions
9990 to set up the global pointer. */
9993 mips_emit_loadgp (void)
9995 rtx addr
, offset
, incoming_address
, base
, index
, pic_reg
;
9997 pic_reg
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
9998 switch (mips_current_loadgp_style ())
10000 case LOADGP_ABSOLUTE
:
10001 if (mips_gnu_local_gp
== NULL
)
10003 mips_gnu_local_gp
= gen_rtx_SYMBOL_REF (Pmode
, "__gnu_local_gp");
10004 SYMBOL_REF_FLAGS (mips_gnu_local_gp
) |= SYMBOL_FLAG_LOCAL
;
10006 emit_insn (Pmode
== SImode
10007 ? gen_loadgp_absolute_si (pic_reg
, mips_gnu_local_gp
)
10008 : gen_loadgp_absolute_di (pic_reg
, mips_gnu_local_gp
));
10011 case LOADGP_OLDABI
:
10012 /* Added by mips_output_function_prologue. */
10015 case LOADGP_NEWABI
:
10016 addr
= XEXP (DECL_RTL (current_function_decl
), 0);
10017 offset
= mips_unspec_address (addr
, SYMBOL_GOTOFF_LOADGP
);
10018 incoming_address
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
10019 emit_insn (Pmode
== SImode
10020 ? gen_loadgp_newabi_si (pic_reg
, offset
, incoming_address
)
10021 : gen_loadgp_newabi_di (pic_reg
, offset
, incoming_address
));
10025 base
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_BASE
));
10026 index
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (VXWORKS_GOTT_INDEX
));
10027 emit_insn (Pmode
== SImode
10028 ? gen_loadgp_rtp_si (pic_reg
, base
, index
)
10029 : gen_loadgp_rtp_di (pic_reg
, base
, index
));
10037 emit_insn (gen_copygp_mips16 (pic_offset_table_rtx
, pic_reg
));
10039 /* Emit a blockage if there are implicit uses of the GP register.
10040 This includes profiled functions, because FUNCTION_PROFILE uses
10042 if (!TARGET_EXPLICIT_RELOCS
|| crtl
->profile
)
10043 emit_insn (gen_loadgp_blockage ());
10046 /* A for_each_rtx callback. Stop the search if *X is a kernel register. */
10049 mips_kernel_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
10051 return REG_P (*x
) && KERNEL_REG_P (REGNO (*x
));
10054 /* Expand the "prologue" pattern. */
10057 mips_expand_prologue (void)
10059 const struct mips_frame_info
*frame
;
10060 HOST_WIDE_INT size
;
10061 unsigned int nargs
;
10064 if (cfun
->machine
->global_pointer
!= INVALID_REGNUM
)
10066 /* Check whether an insn uses pic_offset_table_rtx, either explicitly
10067 or implicitly. If so, we can commit to using a global pointer
10068 straight away, otherwise we need to defer the decision. */
10069 if (mips_cfun_has_inflexible_gp_ref_p ()
10070 || mips_cfun_has_flexible_gp_ref_p ())
10072 cfun
->machine
->must_initialize_gp_p
= true;
10073 cfun
->machine
->must_restore_gp_when_clobbered_p
= true;
10076 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
10079 frame
= &cfun
->machine
->frame
;
10080 size
= frame
->total_size
;
10082 if (flag_stack_usage
)
10083 current_function_static_stack_size
= size
;
10085 /* Save the registers. Allocate up to MIPS_MAX_FIRST_STACK_STEP
10086 bytes beforehand; this is enough to cover the register save area
10087 without going out of range. */
10088 if (((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0)
10089 || frame
->num_cop0_regs
> 0)
10091 HOST_WIDE_INT step1
;
10093 step1
= MIN (size
, MIPS_MAX_FIRST_STACK_STEP
);
10094 if (GENERATE_MIPS16E_SAVE_RESTORE
)
10096 HOST_WIDE_INT offset
;
10097 unsigned int mask
, regno
;
10099 /* Try to merge argument stores into the save instruction. */
10100 nargs
= mips16e_collect_argument_saves ();
10102 /* Build the save instruction. */
10103 mask
= frame
->mask
;
10104 insn
= mips16e_build_save_restore (false, &mask
, &offset
,
10106 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10109 /* Check if we need to save other registers. */
10110 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10111 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10113 offset
-= UNITS_PER_WORD
;
10114 mips_save_restore_reg (word_mode
, regno
,
10115 offset
, mips_save_reg
);
10120 if (cfun
->machine
->interrupt_handler_p
)
10122 HOST_WIDE_INT offset
;
10125 /* If this interrupt is using a shadow register set, we need to
10126 get the stack pointer from the previous register set. */
10127 if (cfun
->machine
->use_shadow_register_set_p
)
10128 emit_insn (gen_mips_rdpgpr (stack_pointer_rtx
,
10129 stack_pointer_rtx
));
10131 if (!cfun
->machine
->keep_interrupts_masked_p
)
10133 /* Move from COP0 Cause to K0. */
10134 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K0_REG_NUM
),
10135 gen_rtx_REG (SImode
,
10136 COP0_CAUSE_REG_NUM
)));
10137 /* Move from COP0 EPC to K1. */
10138 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10139 gen_rtx_REG (SImode
,
10140 COP0_EPC_REG_NUM
)));
10143 /* Allocate the first part of the frame. */
10144 insn
= gen_add3_insn (stack_pointer_rtx
, stack_pointer_rtx
,
10146 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10149 /* Start at the uppermost location for saving. */
10150 offset
= frame
->cop0_sp_offset
- size
;
10151 if (!cfun
->machine
->keep_interrupts_masked_p
)
10153 /* Push EPC into its stack slot. */
10154 mem
= gen_frame_mem (word_mode
,
10155 plus_constant (stack_pointer_rtx
,
10157 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10158 offset
-= UNITS_PER_WORD
;
10161 /* Move from COP0 Status to K1. */
10162 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, K1_REG_NUM
),
10163 gen_rtx_REG (SImode
,
10164 COP0_STATUS_REG_NUM
)));
10166 /* Right justify the RIPL in k0. */
10167 if (!cfun
->machine
->keep_interrupts_masked_p
)
10168 emit_insn (gen_lshrsi3 (gen_rtx_REG (SImode
, K0_REG_NUM
),
10169 gen_rtx_REG (SImode
, K0_REG_NUM
),
10170 GEN_INT (CAUSE_IPL
)));
10172 /* Push Status into its stack slot. */
10173 mem
= gen_frame_mem (word_mode
,
10174 plus_constant (stack_pointer_rtx
, offset
));
10175 mips_emit_move (mem
, gen_rtx_REG (word_mode
, K1_REG_NUM
));
10176 offset
-= UNITS_PER_WORD
;
10178 /* Insert the RIPL into our copy of SR (k1) as the new IPL. */
10179 if (!cfun
->machine
->keep_interrupts_masked_p
)
10180 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10183 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10185 if (!cfun
->machine
->keep_interrupts_masked_p
)
10186 /* Enable interrupts by clearing the KSU ERL and EXL bits.
10187 IE is already the correct value, so we don't have to do
10188 anything explicit. */
10189 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10192 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10194 /* Disable interrupts by clearing the KSU, ERL, EXL,
10196 emit_insn (gen_insvsi (gen_rtx_REG (SImode
, K1_REG_NUM
),
10199 gen_rtx_REG (SImode
, GP_REG_FIRST
)));
10203 insn
= gen_add3_insn (stack_pointer_rtx
,
10206 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10209 mips_for_each_saved_acc (size
, mips_save_reg
);
10210 mips_for_each_saved_gpr_and_fpr (size
, mips_save_reg
);
10214 /* Allocate the rest of the frame. */
10217 if (SMALL_OPERAND (-size
))
10218 RTX_FRAME_RELATED_P (emit_insn (gen_add3_insn (stack_pointer_rtx
,
10220 GEN_INT (-size
)))) = 1;
10223 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (size
));
10226 /* There are no instructions to add or subtract registers
10227 from the stack pointer, so use the frame pointer as a
10228 temporary. We should always be using a frame pointer
10229 in this case anyway. */
10230 gcc_assert (frame_pointer_needed
);
10231 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10232 emit_insn (gen_sub3_insn (hard_frame_pointer_rtx
,
10233 hard_frame_pointer_rtx
,
10234 MIPS_PROLOGUE_TEMP (Pmode
)));
10235 mips_emit_move (stack_pointer_rtx
, hard_frame_pointer_rtx
);
10238 emit_insn (gen_sub3_insn (stack_pointer_rtx
,
10240 MIPS_PROLOGUE_TEMP (Pmode
)));
10242 /* Describe the combined effect of the previous instructions. */
10243 mips_set_frame_expr
10244 (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
10245 plus_constant (stack_pointer_rtx
, -size
)));
10249 /* Set up the frame pointer, if we're using one. */
10250 if (frame_pointer_needed
)
10252 HOST_WIDE_INT offset
;
10254 offset
= frame
->hard_frame_pointer_offset
;
10257 insn
= mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10258 RTX_FRAME_RELATED_P (insn
) = 1;
10260 else if (SMALL_OPERAND (offset
))
10262 insn
= gen_add3_insn (hard_frame_pointer_rtx
,
10263 stack_pointer_rtx
, GEN_INT (offset
));
10264 RTX_FRAME_RELATED_P (emit_insn (insn
)) = 1;
10268 mips_emit_move (MIPS_PROLOGUE_TEMP (Pmode
), GEN_INT (offset
));
10269 mips_emit_move (hard_frame_pointer_rtx
, stack_pointer_rtx
);
10270 emit_insn (gen_add3_insn (hard_frame_pointer_rtx
,
10271 hard_frame_pointer_rtx
,
10272 MIPS_PROLOGUE_TEMP (Pmode
)));
10273 mips_set_frame_expr
10274 (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
10275 plus_constant (stack_pointer_rtx
, offset
)));
10279 mips_emit_loadgp ();
10281 /* Initialize the $gp save slot. */
10282 if (mips_cfun_has_cprestore_slot_p ())
10284 rtx base
, mem
, gp
, temp
;
10285 HOST_WIDE_INT offset
;
10287 mips_get_cprestore_base_and_offset (&base
, &offset
, false);
10288 mem
= gen_frame_mem (Pmode
, plus_constant (base
, offset
));
10289 gp
= TARGET_MIPS16
? MIPS16_PIC_TEMP
: pic_offset_table_rtx
;
10290 temp
= (SMALL_OPERAND (offset
)
10291 ? gen_rtx_SCRATCH (Pmode
)
10292 : MIPS_PROLOGUE_TEMP (Pmode
));
10293 emit_insn (gen_potential_cprestore (mem
, GEN_INT (offset
), gp
, temp
));
10295 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
10296 mem
= gen_frame_mem (Pmode
, plus_constant (base
, offset
));
10297 emit_insn (gen_use_cprestore (mem
));
10300 /* We need to search back to the last use of K0 or K1. */
10301 if (cfun
->machine
->interrupt_handler_p
)
10303 for (insn
= get_last_insn (); insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
10305 && for_each_rtx (&PATTERN (insn
), mips_kernel_reg_p
, NULL
))
10307 /* Emit a move from K1 to COP0 Status after insn. */
10308 gcc_assert (insn
!= NULL_RTX
);
10309 emit_insn_after (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10310 gen_rtx_REG (SImode
, K1_REG_NUM
)),
10314 /* If we are profiling, make sure no instructions are scheduled before
10315 the call to mcount. */
10317 emit_insn (gen_blockage ());
10320 /* Emit instructions to restore register REG from slot MEM. */
10323 mips_restore_reg (rtx reg
, rtx mem
)
10325 /* There's no MIPS16 instruction to load $31 directly. Load into
10326 $7 instead and adjust the return insn appropriately. */
10327 if (TARGET_MIPS16
&& REGNO (reg
) == RETURN_ADDR_REGNUM
)
10328 reg
= gen_rtx_REG (GET_MODE (reg
), GP_REG_FIRST
+ 7);
10330 mips_emit_save_slot_move (reg
, mem
, MIPS_EPILOGUE_TEMP (GET_MODE (reg
)));
10333 /* Emit any instructions needed before a return. */
10336 mips_expand_before_return (void)
10338 /* When using a call-clobbered gp, we start out with unified call
10339 insns that include instructions to restore the gp. We then split
10340 these unified calls after reload. These split calls explicitly
10341 clobber gp, so there is no need to define
10342 PIC_OFFSET_TABLE_REG_CALL_CLOBBERED.
10344 For consistency, we should also insert an explicit clobber of $28
10345 before return insns, so that the post-reload optimizers know that
10346 the register is not live on exit. */
10347 if (TARGET_CALL_CLOBBERED_GP
)
10348 emit_clobber (pic_offset_table_rtx
);
10351 /* Expand an "epilogue" or "sibcall_epilogue" pattern; SIBCALL_P
10355 mips_expand_epilogue (bool sibcall_p
)
10357 const struct mips_frame_info
*frame
;
10358 HOST_WIDE_INT step1
, step2
;
10359 rtx base
, target
, insn
;
10361 if (!sibcall_p
&& mips_can_use_return_insn ())
10363 emit_jump_insn (gen_return ());
10367 /* In MIPS16 mode, if the return value should go into a floating-point
10368 register, we need to call a helper routine to copy it over. */
10369 if (mips16_cfun_returns_in_fpr_p ())
10370 mips16_copy_fpr_return_value ();
10372 /* Split the frame into two. STEP1 is the amount of stack we should
10373 deallocate before restoring the registers. STEP2 is the amount we
10374 should deallocate afterwards.
10376 Start off by assuming that no registers need to be restored. */
10377 frame
= &cfun
->machine
->frame
;
10378 step1
= frame
->total_size
;
10381 /* Work out which register holds the frame address. */
10382 if (!frame_pointer_needed
)
10383 base
= stack_pointer_rtx
;
10386 base
= hard_frame_pointer_rtx
;
10387 step1
-= frame
->hard_frame_pointer_offset
;
10390 /* If we need to restore registers, deallocate as much stack as
10391 possible in the second step without going out of range. */
10392 if ((frame
->mask
| frame
->fmask
| frame
->acc_mask
) != 0
10393 || frame
->num_cop0_regs
> 0)
10395 step2
= MIN (step1
, MIPS_MAX_FIRST_STACK_STEP
);
10399 /* Set TARGET to BASE + STEP1. */
10405 /* Get an rtx for STEP1 that we can add to BASE. */
10406 adjust
= GEN_INT (step1
);
10407 if (!SMALL_OPERAND (step1
))
10409 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), adjust
);
10410 adjust
= MIPS_EPILOGUE_TEMP (Pmode
);
10413 /* Normal mode code can copy the result straight into $sp. */
10414 if (!TARGET_MIPS16
)
10415 target
= stack_pointer_rtx
;
10417 emit_insn (gen_add3_insn (target
, base
, adjust
));
10420 /* Copy TARGET into the stack pointer. */
10421 if (target
!= stack_pointer_rtx
)
10422 mips_emit_move (stack_pointer_rtx
, target
);
10424 /* If we're using addressing macros, $gp is implicitly used by all
10425 SYMBOL_REFs. We must emit a blockage insn before restoring $gp
10427 if (TARGET_CALL_SAVED_GP
&& !TARGET_EXPLICIT_RELOCS
)
10428 emit_insn (gen_blockage ());
10430 if (GENERATE_MIPS16E_SAVE_RESTORE
&& frame
->mask
!= 0)
10432 unsigned int regno
, mask
;
10433 HOST_WIDE_INT offset
;
10436 /* Generate the restore instruction. */
10437 mask
= frame
->mask
;
10438 restore
= mips16e_build_save_restore (true, &mask
, &offset
, 0, step2
);
10440 /* Restore any other registers manually. */
10441 for (regno
= GP_REG_FIRST
; regno
< GP_REG_LAST
; regno
++)
10442 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
10444 offset
-= UNITS_PER_WORD
;
10445 mips_save_restore_reg (word_mode
, regno
, offset
, mips_restore_reg
);
10448 /* Restore the remaining registers and deallocate the final bit
10450 emit_insn (restore
);
10454 /* Restore the registers. */
10455 mips_for_each_saved_acc (frame
->total_size
- step2
, mips_restore_reg
);
10456 mips_for_each_saved_gpr_and_fpr (frame
->total_size
- step2
,
10459 if (cfun
->machine
->interrupt_handler_p
)
10461 HOST_WIDE_INT offset
;
10464 offset
= frame
->cop0_sp_offset
- (frame
->total_size
- step2
);
10465 if (!cfun
->machine
->keep_interrupts_masked_p
)
10467 /* Restore the original EPC. */
10468 mem
= gen_frame_mem (word_mode
,
10469 plus_constant (stack_pointer_rtx
, offset
));
10470 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10471 offset
-= UNITS_PER_WORD
;
10473 /* Move to COP0 EPC. */
10474 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_EPC_REG_NUM
),
10475 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10478 /* Restore the original Status. */
10479 mem
= gen_frame_mem (word_mode
,
10480 plus_constant (stack_pointer_rtx
, offset
));
10481 mips_emit_move (gen_rtx_REG (word_mode
, K0_REG_NUM
), mem
);
10482 offset
-= UNITS_PER_WORD
;
10484 /* If we don't use shoadow register set, we need to update SP. */
10485 if (!cfun
->machine
->use_shadow_register_set_p
&& step2
> 0)
10486 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10490 /* Move to COP0 Status. */
10491 emit_insn (gen_cop0_move (gen_rtx_REG (SImode
, COP0_STATUS_REG_NUM
),
10492 gen_rtx_REG (SImode
, K0_REG_NUM
)));
10496 /* Deallocate the final bit of the frame. */
10498 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10504 /* Add in the __builtin_eh_return stack adjustment. We need to
10505 use a temporary in MIPS16 code. */
10506 if (crtl
->calls_eh_return
)
10510 mips_emit_move (MIPS_EPILOGUE_TEMP (Pmode
), stack_pointer_rtx
);
10511 emit_insn (gen_add3_insn (MIPS_EPILOGUE_TEMP (Pmode
),
10512 MIPS_EPILOGUE_TEMP (Pmode
),
10513 EH_RETURN_STACKADJ_RTX
));
10514 mips_emit_move (stack_pointer_rtx
, MIPS_EPILOGUE_TEMP (Pmode
));
10517 emit_insn (gen_add3_insn (stack_pointer_rtx
,
10519 EH_RETURN_STACKADJ_RTX
));
10524 mips_expand_before_return ();
10525 if (cfun
->machine
->interrupt_handler_p
)
10527 /* Interrupt handlers generate eret or deret. */
10528 if (cfun
->machine
->use_debug_exception_return_p
)
10529 emit_jump_insn (gen_mips_deret ());
10531 emit_jump_insn (gen_mips_eret ());
10535 unsigned int regno
;
10537 /* When generating MIPS16 code, the normal
10538 mips_for_each_saved_gpr_and_fpr path will restore the return
10539 address into $7 rather than $31. */
10541 && !GENERATE_MIPS16E_SAVE_RESTORE
10542 && BITSET_P (frame
->mask
, RETURN_ADDR_REGNUM
))
10543 regno
= GP_REG_FIRST
+ 7;
10545 regno
= RETURN_ADDR_REGNUM
;
10546 emit_jump_insn (gen_return_internal (gen_rtx_REG (Pmode
, regno
)));
10550 /* Search from the beginning to the first use of K0 or K1. */
10551 if (cfun
->machine
->interrupt_handler_p
10552 && !cfun
->machine
->keep_interrupts_masked_p
)
10554 for (insn
= get_insns (); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
10556 && for_each_rtx (&PATTERN(insn
), mips_kernel_reg_p
, NULL
))
10558 gcc_assert (insn
!= NULL_RTX
);
10559 /* Insert disable interrupts before the first use of K0 or K1. */
10560 emit_insn_before (gen_mips_di (), insn
);
10561 emit_insn_before (gen_mips_ehb (), insn
);
10565 /* Return nonzero if this function is known to have a null epilogue.
10566 This allows the optimizer to omit jumps to jumps if no stack
10570 mips_can_use_return_insn (void)
10572 /* Interrupt handlers need to go through the epilogue. */
10573 if (cfun
->machine
->interrupt_handler_p
)
10576 if (!reload_completed
)
10582 /* In MIPS16 mode, a function that returns a floating-point value
10583 needs to arrange to copy the return value into the floating-point
10585 if (mips16_cfun_returns_in_fpr_p ())
10588 return cfun
->machine
->frame
.total_size
== 0;
10591 /* Return true if register REGNO can store a value of mode MODE.
10592 The result of this function is cached in mips_hard_regno_mode_ok. */
10595 mips_hard_regno_mode_ok_p (unsigned int regno
, enum machine_mode mode
)
10598 enum mode_class mclass
;
10600 if (mode
== CCV2mode
)
10601 return (ISA_HAS_8CC
10602 && ST_REG_P (regno
)
10603 && (regno
- ST_REG_FIRST
) % 2 == 0);
10605 if (mode
== CCV4mode
)
10606 return (ISA_HAS_8CC
10607 && ST_REG_P (regno
)
10608 && (regno
- ST_REG_FIRST
) % 4 == 0);
10610 if (mode
== CCmode
)
10613 return regno
== FPSW_REGNUM
;
10615 return (ST_REG_P (regno
)
10616 || GP_REG_P (regno
)
10617 || FP_REG_P (regno
));
10620 size
= GET_MODE_SIZE (mode
);
10621 mclass
= GET_MODE_CLASS (mode
);
10623 if (GP_REG_P (regno
))
10624 return ((regno
- GP_REG_FIRST
) & 1) == 0 || size
<= UNITS_PER_WORD
;
10626 if (FP_REG_P (regno
)
10627 && (((regno
- FP_REG_FIRST
) % MAX_FPRS_PER_FMT
) == 0
10628 || (MIN_FPRS_PER_FMT
== 1 && size
<= UNITS_PER_FPREG
)))
10630 /* Allow TFmode for CCmode reloads. */
10631 if (mode
== TFmode
&& ISA_HAS_8CC
)
10634 /* Allow 64-bit vector modes for Loongson-2E/2F. */
10635 if (TARGET_LOONGSON_VECTORS
10636 && (mode
== V2SImode
10637 || mode
== V4HImode
10638 || mode
== V8QImode
10639 || mode
== DImode
))
10642 if (mclass
== MODE_FLOAT
10643 || mclass
== MODE_COMPLEX_FLOAT
10644 || mclass
== MODE_VECTOR_FLOAT
)
10645 return size
<= UNITS_PER_FPVALUE
;
10647 /* Allow integer modes that fit into a single register. We need
10648 to put integers into FPRs when using instructions like CVT
10649 and TRUNC. There's no point allowing sizes smaller than a word,
10650 because the FPU has no appropriate load/store instructions. */
10651 if (mclass
== MODE_INT
)
10652 return size
>= MIN_UNITS_PER_WORD
&& size
<= UNITS_PER_FPREG
;
10655 if (ACC_REG_P (regno
)
10656 && (INTEGRAL_MODE_P (mode
) || ALL_FIXED_POINT_MODE_P (mode
)))
10658 if (MD_REG_P (regno
))
10660 /* After a multiplication or division, clobbering HI makes
10661 the value of LO unpredictable, and vice versa. This means
10662 that, for all interesting cases, HI and LO are effectively
10665 We model this by requiring that any value that uses HI
10667 if (size
<= UNITS_PER_WORD
* 2)
10668 return regno
== (size
<= UNITS_PER_WORD
? LO_REGNUM
: MD_REG_FIRST
);
10672 /* DSP accumulators do not have the same restrictions as
10673 HI and LO, so we can treat them as normal doubleword
10675 if (size
<= UNITS_PER_WORD
)
10678 if (size
<= UNITS_PER_WORD
* 2
10679 && ((regno
- DSP_ACC_REG_FIRST
) & 1) == 0)
10684 if (ALL_COP_REG_P (regno
))
10685 return mclass
== MODE_INT
&& size
<= UNITS_PER_WORD
;
10687 if (regno
== GOT_VERSION_REGNUM
)
10688 return mode
== SImode
;
10693 /* Implement HARD_REGNO_NREGS. */
10696 mips_hard_regno_nregs (int regno
, enum machine_mode mode
)
10698 if (ST_REG_P (regno
))
10699 /* The size of FP status registers is always 4, because they only hold
10700 CCmode values, and CCmode is always considered to be 4 bytes wide. */
10701 return (GET_MODE_SIZE (mode
) + 3) / 4;
10703 if (FP_REG_P (regno
))
10704 return (GET_MODE_SIZE (mode
) + UNITS_PER_FPREG
- 1) / UNITS_PER_FPREG
;
10706 /* All other registers are word-sized. */
10707 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
10710 /* Implement CLASS_MAX_NREGS, taking the maximum of the cases
10711 in mips_hard_regno_nregs. */
10714 mips_class_max_nregs (enum reg_class rclass
, enum machine_mode mode
)
10720 COPY_HARD_REG_SET (left
, reg_class_contents
[(int) rclass
]);
10721 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) ST_REGS
]))
10723 size
= MIN (size
, 4);
10724 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) ST_REGS
]);
10726 if (hard_reg_set_intersect_p (left
, reg_class_contents
[(int) FP_REGS
]))
10728 size
= MIN (size
, UNITS_PER_FPREG
);
10729 AND_COMPL_HARD_REG_SET (left
, reg_class_contents
[(int) FP_REGS
]);
10731 if (!hard_reg_set_empty_p (left
))
10732 size
= MIN (size
, UNITS_PER_WORD
);
10733 return (GET_MODE_SIZE (mode
) + size
- 1) / size
;
10736 /* Implement CANNOT_CHANGE_MODE_CLASS. */
10739 mips_cannot_change_mode_class (enum machine_mode from ATTRIBUTE_UNUSED
,
10740 enum machine_mode to ATTRIBUTE_UNUSED
,
10741 enum reg_class rclass
)
10743 /* There are several problems with changing the modes of values
10744 in floating-point registers:
10746 - When a multi-word value is stored in paired floating-point
10747 registers, the first register always holds the low word.
10748 We therefore can't allow FPRs to change between single-word
10749 and multi-word modes on big-endian targets.
10751 - GCC assumes that each word of a multiword register can be accessed
10752 individually using SUBREGs. This is not true for floating-point
10753 registers if they are bigger than a word.
10755 - Loading a 32-bit value into a 64-bit floating-point register
10756 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
10757 We can't allow FPRs to change from SImode to to a wider mode on
10760 - If the FPU has already interpreted a value in one format, we must
10761 not ask it to treat the value as having a different format.
10763 We therefore disallow all mode changes involving FPRs. */
10764 return reg_classes_intersect_p (FP_REGS
, rclass
);
10767 /* Implement target hook small_register_classes_for_mode_p. */
10770 mips_small_register_classes_for_mode_p (enum machine_mode mode
10773 return TARGET_MIPS16
;
10776 /* Return true if moves in mode MODE can use the FPU's mov.fmt instruction. */
10779 mips_mode_ok_for_mov_fmt_p (enum machine_mode mode
)
10784 return TARGET_HARD_FLOAT
;
10787 return TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
;
10790 return TARGET_HARD_FLOAT
&& TARGET_PAIRED_SINGLE_FLOAT
;
10797 /* Implement MODES_TIEABLE_P. */
10800 mips_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
10802 /* FPRs allow no mode punning, so it's not worth tying modes if we'd
10803 prefer to put one of them in FPRs. */
10804 return (mode1
== mode2
10805 || (!mips_mode_ok_for_mov_fmt_p (mode1
)
10806 && !mips_mode_ok_for_mov_fmt_p (mode2
)));
10809 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
10812 mips_preferred_reload_class (rtx x
, reg_class_t rclass
)
10814 if (mips_dangerous_for_la25_p (x
) && reg_class_subset_p (LEA_REGS
, rclass
))
10817 if (reg_class_subset_p (FP_REGS
, rclass
)
10818 && mips_mode_ok_for_mov_fmt_p (GET_MODE (x
)))
10821 if (reg_class_subset_p (GR_REGS
, rclass
))
10824 if (TARGET_MIPS16
&& reg_class_subset_p (M16_REGS
, rclass
))
10830 /* RCLASS is a class involved in a REGISTER_MOVE_COST calculation.
10831 Return a "canonical" class to represent it in later calculations. */
10834 mips_canonicalize_move_class (reg_class_t rclass
)
10836 /* All moves involving accumulator registers have the same cost. */
10837 if (reg_class_subset_p (rclass
, ACC_REGS
))
10840 /* Likewise promote subclasses of general registers to the most
10841 interesting containing class. */
10842 if (TARGET_MIPS16
&& reg_class_subset_p (rclass
, M16_REGS
))
10844 else if (reg_class_subset_p (rclass
, GENERAL_REGS
))
10845 rclass
= GENERAL_REGS
;
10850 /* Return the cost of moving a value of mode MODE from a register of
10851 class FROM to a GPR. Return 0 for classes that are unions of other
10852 classes handled by this function. */
10855 mips_move_to_gpr_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
10861 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10865 /* MFLO and MFHI. */
10873 /* LUI followed by MOVF. */
10879 /* This choice of value is historical. */
10887 /* Return the cost of moving a value of mode MODE from a GPR to a
10888 register of class TO. Return 0 for classes that are unions of
10889 other classes handled by this function. */
10892 mips_move_from_gpr_cost (enum machine_mode mode
, reg_class_t to
)
10897 /* A MIPS16 MOVE instruction, or a non-MIPS16 MOVE macro. */
10901 /* MTLO and MTHI. */
10909 /* A secondary reload through an FPR scratch. */
10910 return (mips_register_move_cost (mode
, GENERAL_REGS
, FP_REGS
)
10911 + mips_register_move_cost (mode
, FP_REGS
, ST_REGS
));
10916 /* This choice of value is historical. */
10924 /* Implement TARGET_REGISTER_MOVE_COST. Return 0 for classes that are the
10925 maximum of the move costs for subclasses; regclass will work out
10926 the maximum for us. */
10929 mips_register_move_cost (enum machine_mode mode
,
10930 reg_class_t from
, reg_class_t to
)
10935 from
= mips_canonicalize_move_class (from
);
10936 to
= mips_canonicalize_move_class (to
);
10938 /* Handle moves that can be done without using general-purpose registers. */
10939 if (from
== FP_REGS
)
10941 if (to
== FP_REGS
&& mips_mode_ok_for_mov_fmt_p (mode
))
10945 /* The sequence generated by mips_expand_fcc_reload. */
10949 /* Handle cases in which only one class deviates from the ideal. */
10950 dregs
= TARGET_MIPS16
? M16_REGS
: GENERAL_REGS
;
10952 return mips_move_from_gpr_cost (mode
, to
);
10954 return mips_move_to_gpr_cost (mode
, from
);
10956 /* Handles cases that require a GPR temporary. */
10957 cost1
= mips_move_to_gpr_cost (mode
, from
);
10960 cost2
= mips_move_from_gpr_cost (mode
, to
);
10962 return cost1
+ cost2
;
10968 /* Implement TARGET_MEMORY_MOVE_COST. */
10971 mips_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
, bool in
)
10973 return (mips_cost
->memory_latency
10974 + memory_move_secondary_cost (mode
, rclass
, in
));
10977 /* Implement TARGET_IRA_COVER_CLASSES. */
10979 static const reg_class_t
*
10980 mips_ira_cover_classes (void)
10982 static const reg_class_t acc_classes
[] = {
10983 GR_AND_ACC_REGS
, FP_REGS
, COP0_REGS
, COP2_REGS
, COP3_REGS
,
10984 ST_REGS
, LIM_REG_CLASSES
10986 static const reg_class_t no_acc_classes
[] = {
10987 GR_REGS
, FP_REGS
, COP0_REGS
, COP2_REGS
, COP3_REGS
,
10988 ST_REGS
, LIM_REG_CLASSES
10991 /* Don't allow the register allocators to use LO and HI in MIPS16 mode,
10992 which has no MTLO or MTHI instructions. Also, using GR_AND_ACC_REGS
10993 as a cover class only works well when we keep per-register costs.
10994 Using it when not optimizing can cause us to think accumulators
10995 have the same cost as GPRs in cases where GPRs are actually much
10997 return TARGET_MIPS16
|| !optimize
? no_acc_classes
: acc_classes
;
11000 /* Return the register class required for a secondary register when
11001 copying between one of the registers in RCLASS and value X, which
11002 has mode MODE. X is the source of the move if IN_P, otherwise it
11003 is the destination. Return NO_REGS if no secondary register is
11007 mips_secondary_reload_class (enum reg_class rclass
,
11008 enum machine_mode mode
, rtx x
, bool in_p
)
11012 /* If X is a constant that cannot be loaded into $25, it must be loaded
11013 into some other GPR. No other register class allows a direct move. */
11014 if (mips_dangerous_for_la25_p (x
))
11015 return reg_class_subset_p (rclass
, LEA_REGS
) ? NO_REGS
: LEA_REGS
;
11017 regno
= true_regnum (x
);
11020 /* In MIPS16 mode, every move must involve a member of M16_REGS. */
11021 if (!reg_class_subset_p (rclass
, M16_REGS
) && !M16_REG_P (regno
))
11027 /* Copying from accumulator registers to anywhere other than a general
11028 register requires a temporary general register. */
11029 if (reg_class_subset_p (rclass
, ACC_REGS
))
11030 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11031 if (ACC_REG_P (regno
))
11032 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11034 /* We can only copy a value to a condition code register from a
11035 floating-point register, and even then we require a scratch
11036 floating-point register. We can only copy a value out of a
11037 condition-code register into a general register. */
11038 if (reg_class_subset_p (rclass
, ST_REGS
))
11042 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
11044 if (ST_REG_P (regno
))
11048 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11051 if (reg_class_subset_p (rclass
, FP_REGS
))
11054 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8))
11055 /* In this case we can use lwc1, swc1, ldc1 or sdc1. We'll use
11056 pairs of lwc1s and swc1s if ldc1 and sdc1 are not supported. */
11059 if (GP_REG_P (regno
) || x
== CONST0_RTX (mode
))
11060 /* In this case we can use mtc1, mfc1, dmtc1 or dmfc1. */
11063 if (CONSTANT_P (x
) && !targetm
.cannot_force_const_mem (x
))
11064 /* We can force the constant to memory and use lwc1
11065 and ldc1. As above, we will use pairs of lwc1s if
11066 ldc1 is not supported. */
11069 if (FP_REG_P (regno
) && mips_mode_ok_for_mov_fmt_p (mode
))
11070 /* In this case we can use mov.fmt. */
11073 /* Otherwise, we need to reload through an integer register. */
11076 if (FP_REG_P (regno
))
11077 return reg_class_subset_p (rclass
, GR_REGS
) ? NO_REGS
: GR_REGS
;
11082 /* Implement TARGET_MODE_REP_EXTENDED. */
11085 mips_mode_rep_extended (enum machine_mode mode
, enum machine_mode mode_rep
)
11087 /* On 64-bit targets, SImode register values are sign-extended to DImode. */
11088 if (TARGET_64BIT
&& mode
== SImode
&& mode_rep
== DImode
)
11089 return SIGN_EXTEND
;
11094 /* Implement TARGET_VALID_POINTER_MODE. */
11097 mips_valid_pointer_mode (enum machine_mode mode
)
11099 return mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
);
11102 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
11105 mips_vector_mode_supported_p (enum machine_mode mode
)
11110 return TARGET_PAIRED_SINGLE_FLOAT
;
11125 return TARGET_LOONGSON_VECTORS
;
11132 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
11135 mips_scalar_mode_supported_p (enum machine_mode mode
)
11137 if (ALL_FIXED_POINT_MODE_P (mode
)
11138 && GET_MODE_PRECISION (mode
) <= 2 * BITS_PER_WORD
)
11141 return default_scalar_mode_supported_p (mode
);
11144 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
11146 static enum machine_mode
11147 mips_preferred_simd_mode (enum machine_mode mode ATTRIBUTE_UNUSED
)
11149 if (TARGET_PAIRED_SINGLE_FLOAT
11155 /* Implement TARGET_INIT_LIBFUNCS. */
11158 mips_init_libfuncs (void)
11160 if (TARGET_FIX_VR4120
)
11162 /* Register the special divsi3 and modsi3 functions needed to work
11163 around VR4120 division errata. */
11164 set_optab_libfunc (sdiv_optab
, SImode
, "__vr4120_divsi3");
11165 set_optab_libfunc (smod_optab
, SImode
, "__vr4120_modsi3");
11168 if (TARGET_MIPS16
&& TARGET_HARD_FLOAT_ABI
)
11170 /* Register the MIPS16 -mhard-float stubs. */
11171 set_optab_libfunc (add_optab
, SFmode
, "__mips16_addsf3");
11172 set_optab_libfunc (sub_optab
, SFmode
, "__mips16_subsf3");
11173 set_optab_libfunc (smul_optab
, SFmode
, "__mips16_mulsf3");
11174 set_optab_libfunc (sdiv_optab
, SFmode
, "__mips16_divsf3");
11176 set_optab_libfunc (eq_optab
, SFmode
, "__mips16_eqsf2");
11177 set_optab_libfunc (ne_optab
, SFmode
, "__mips16_nesf2");
11178 set_optab_libfunc (gt_optab
, SFmode
, "__mips16_gtsf2");
11179 set_optab_libfunc (ge_optab
, SFmode
, "__mips16_gesf2");
11180 set_optab_libfunc (lt_optab
, SFmode
, "__mips16_ltsf2");
11181 set_optab_libfunc (le_optab
, SFmode
, "__mips16_lesf2");
11182 set_optab_libfunc (unord_optab
, SFmode
, "__mips16_unordsf2");
11184 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__mips16_fix_truncsfsi");
11185 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__mips16_floatsisf");
11186 set_conv_libfunc (ufloat_optab
, SFmode
, SImode
, "__mips16_floatunsisf");
11188 if (TARGET_DOUBLE_FLOAT
)
11190 set_optab_libfunc (add_optab
, DFmode
, "__mips16_adddf3");
11191 set_optab_libfunc (sub_optab
, DFmode
, "__mips16_subdf3");
11192 set_optab_libfunc (smul_optab
, DFmode
, "__mips16_muldf3");
11193 set_optab_libfunc (sdiv_optab
, DFmode
, "__mips16_divdf3");
11195 set_optab_libfunc (eq_optab
, DFmode
, "__mips16_eqdf2");
11196 set_optab_libfunc (ne_optab
, DFmode
, "__mips16_nedf2");
11197 set_optab_libfunc (gt_optab
, DFmode
, "__mips16_gtdf2");
11198 set_optab_libfunc (ge_optab
, DFmode
, "__mips16_gedf2");
11199 set_optab_libfunc (lt_optab
, DFmode
, "__mips16_ltdf2");
11200 set_optab_libfunc (le_optab
, DFmode
, "__mips16_ledf2");
11201 set_optab_libfunc (unord_optab
, DFmode
, "__mips16_unorddf2");
11203 set_conv_libfunc (sext_optab
, DFmode
, SFmode
,
11204 "__mips16_extendsfdf2");
11205 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
,
11206 "__mips16_truncdfsf2");
11207 set_conv_libfunc (sfix_optab
, SImode
, DFmode
,
11208 "__mips16_fix_truncdfsi");
11209 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
,
11210 "__mips16_floatsidf");
11211 set_conv_libfunc (ufloat_optab
, DFmode
, SImode
,
11212 "__mips16_floatunsidf");
11216 /* The MIPS16 ISA does not have an encoding for "sync", so we rely
11217 on an external non-MIPS16 routine to implement __sync_synchronize. */
11219 synchronize_libfunc
= init_one_libfunc ("__sync_synchronize");
11222 /* Build up a multi-insn sequence that loads label TARGET into $AT. */
11225 mips_process_load_label (rtx target
)
11227 rtx base
, gp
, intop
;
11228 HOST_WIDE_INT offset
;
11230 mips_multi_start ();
11234 mips_multi_add_insn ("lw\t%@,%%got_page(%0)(%+)", target
, 0);
11235 mips_multi_add_insn ("addiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11239 mips_multi_add_insn ("ld\t%@,%%got_page(%0)(%+)", target
, 0);
11240 mips_multi_add_insn ("daddiu\t%@,%@,%%got_ofst(%0)", target
, 0);
11244 gp
= pic_offset_table_rtx
;
11245 if (mips_cfun_has_cprestore_slot_p ())
11247 gp
= gen_rtx_REG (Pmode
, AT_REGNUM
);
11248 mips_get_cprestore_base_and_offset (&base
, &offset
, true);
11249 if (!SMALL_OPERAND (offset
))
11251 intop
= GEN_INT (CONST_HIGH_PART (offset
));
11252 mips_multi_add_insn ("lui\t%0,%1", gp
, intop
, 0);
11253 mips_multi_add_insn ("addu\t%0,%0,%1", gp
, base
, 0);
11256 offset
= CONST_LOW_PART (offset
);
11258 intop
= GEN_INT (offset
);
11259 if (ISA_HAS_LOAD_DELAY
)
11260 mips_multi_add_insn ("lw\t%0,%1(%2)%#", gp
, intop
, base
, 0);
11262 mips_multi_add_insn ("lw\t%0,%1(%2)", gp
, intop
, base
, 0);
11264 if (ISA_HAS_LOAD_DELAY
)
11265 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)%#", target
, gp
, 0);
11267 mips_multi_add_insn ("lw\t%@,%%got(%0)(%1)", target
, gp
, 0);
11268 mips_multi_add_insn ("addiu\t%@,%@,%%lo(%0)", target
, 0);
11273 /* Return the number of instructions needed to load a label into $AT. */
11275 static unsigned int
11276 mips_load_label_num_insns (void)
11278 if (cfun
->machine
->load_label_num_insns
== 0)
11280 mips_process_load_label (pc_rtx
);
11281 cfun
->machine
->load_label_num_insns
= mips_multi_num_insns
;
11283 return cfun
->machine
->load_label_num_insns
;
11286 /* Emit an asm sequence to start a noat block and load the address
11287 of a label into $1. */
11290 mips_output_load_label (rtx target
)
11292 mips_push_asm_switch (&mips_noat
);
11293 if (TARGET_EXPLICIT_RELOCS
)
11295 mips_process_load_label (target
);
11296 mips_multi_write ();
11300 if (Pmode
== DImode
)
11301 output_asm_insn ("dla\t%@,%0", &target
);
11303 output_asm_insn ("la\t%@,%0", &target
);
11307 /* Return the length of INSN. LENGTH is the initial length computed by
11308 attributes in the machine-description file. */
11311 mips_adjust_insn_length (rtx insn
, int length
)
11313 /* mips.md uses MAX_PIC_BRANCH_LENGTH as a placeholder for the length
11314 of a PIC long-branch sequence. Substitute the correct value. */
11315 if (length
== MAX_PIC_BRANCH_LENGTH
11316 && INSN_CODE (insn
) >= 0
11317 && get_attr_type (insn
) == TYPE_BRANCH
)
11319 /* Add the branch-over instruction and its delay slot, if this
11320 is a conditional branch. */
11321 length
= simplejump_p (insn
) ? 0 : 8;
11323 /* Load the label into $AT and jump to it. Ignore the delay
11324 slot of the jump. */
11325 length
+= 4 * mips_load_label_num_insns() + 4;
11328 /* A unconditional jump has an unfilled delay slot if it is not part
11329 of a sequence. A conditional jump normally has a delay slot, but
11330 does not on MIPS16. */
11331 if (CALL_P (insn
) || (TARGET_MIPS16
? simplejump_p (insn
) : JUMP_P (insn
)))
11334 /* See how many nops might be needed to avoid hardware hazards. */
11335 if (!cfun
->machine
->ignore_hazard_length_p
&& INSN_CODE (insn
) >= 0)
11336 switch (get_attr_hazard (insn
))
11350 /* In order to make it easier to share MIPS16 and non-MIPS16 patterns,
11351 the .md file length attributes are 4-based for both modes.
11352 Adjust the MIPS16 ones here. */
11359 /* Return the assembly code for INSN, which has the operands given by
11360 OPERANDS, and which branches to OPERANDS[0] if some condition is true.
11361 BRANCH_IF_TRUE is the asm template that should be used if OPERANDS[0]
11362 is in range of a direct branch. BRANCH_IF_FALSE is an inverted
11363 version of BRANCH_IF_TRUE. */
11366 mips_output_conditional_branch (rtx insn
, rtx
*operands
,
11367 const char *branch_if_true
,
11368 const char *branch_if_false
)
11370 unsigned int length
;
11371 rtx taken
, not_taken
;
11373 gcc_assert (LABEL_P (operands
[0]));
11375 length
= get_attr_length (insn
);
11378 /* Just a simple conditional branch. */
11379 mips_branch_likely
= (final_sequence
&& INSN_ANNULLED_BRANCH_P (insn
));
11380 return branch_if_true
;
11383 /* Generate a reversed branch around a direct jump. This fallback does
11384 not use branch-likely instructions. */
11385 mips_branch_likely
= false;
11386 not_taken
= gen_label_rtx ();
11387 taken
= operands
[0];
11389 /* Generate the reversed branch to NOT_TAKEN. */
11390 operands
[0] = not_taken
;
11391 output_asm_insn (branch_if_false
, operands
);
11393 /* If INSN has a delay slot, we must provide delay slots for both the
11394 branch to NOT_TAKEN and the conditional jump. We must also ensure
11395 that INSN's delay slot is executed in the appropriate cases. */
11396 if (final_sequence
)
11398 /* This first delay slot will always be executed, so use INSN's
11399 delay slot if is not annulled. */
11400 if (!INSN_ANNULLED_BRANCH_P (insn
))
11402 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11403 asm_out_file
, optimize
, 1, NULL
);
11404 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11407 output_asm_insn ("nop", 0);
11408 fprintf (asm_out_file
, "\n");
11411 /* Output the unconditional branch to TAKEN. */
11412 if (TARGET_ABSOLUTE_JUMPS
)
11413 output_asm_insn (MIPS_ABSOLUTE_JUMP ("j\t%0%/"), &taken
);
11416 mips_output_load_label (taken
);
11417 output_asm_insn ("jr\t%@%]%/", 0);
11420 /* Now deal with its delay slot; see above. */
11421 if (final_sequence
)
11423 /* This delay slot will only be executed if the branch is taken.
11424 Use INSN's delay slot if is annulled. */
11425 if (INSN_ANNULLED_BRANCH_P (insn
))
11427 final_scan_insn (XVECEXP (final_sequence
, 0, 1),
11428 asm_out_file
, optimize
, 1, NULL
);
11429 INSN_DELETED_P (XVECEXP (final_sequence
, 0, 1)) = 1;
11432 output_asm_insn ("nop", 0);
11433 fprintf (asm_out_file
, "\n");
11436 /* Output NOT_TAKEN. */
11437 targetm
.asm_out
.internal_label (asm_out_file
, "L",
11438 CODE_LABEL_NUMBER (not_taken
));
11442 /* Return the assembly code for INSN, which branches to OPERANDS[0]
11443 if some ordering condition is true. The condition is given by
11444 OPERANDS[1] if !INVERTED_P, otherwise it is the inverse of
11445 OPERANDS[1]. OPERANDS[2] is the comparison's first operand;
11446 its second is always zero. */
11449 mips_output_order_conditional_branch (rtx insn
, rtx
*operands
, bool inverted_p
)
11451 const char *branch
[2];
11453 /* Make BRANCH[1] branch to OPERANDS[0] when the condition is true.
11454 Make BRANCH[0] branch on the inverse condition. */
11455 switch (GET_CODE (operands
[1]))
11457 /* These cases are equivalent to comparisons against zero. */
11459 inverted_p
= !inverted_p
;
11460 /* Fall through. */
11462 branch
[!inverted_p
] = MIPS_BRANCH ("bne", "%2,%.,%0");
11463 branch
[inverted_p
] = MIPS_BRANCH ("beq", "%2,%.,%0");
11466 /* These cases are always true or always false. */
11468 inverted_p
= !inverted_p
;
11469 /* Fall through. */
11471 branch
[!inverted_p
] = MIPS_BRANCH ("beq", "%.,%.,%0");
11472 branch
[inverted_p
] = MIPS_BRANCH ("bne", "%.,%.,%0");
11476 branch
[!inverted_p
] = MIPS_BRANCH ("b%C1z", "%2,%0");
11477 branch
[inverted_p
] = MIPS_BRANCH ("b%N1z", "%2,%0");
11480 return mips_output_conditional_branch (insn
, operands
, branch
[1], branch
[0]);
11483 /* Start a block of code that needs access to the LL, SC and SYNC
11487 mips_start_ll_sc_sync_block (void)
11489 if (!ISA_HAS_LL_SC
)
11491 output_asm_insn (".set\tpush", 0);
11492 output_asm_insn (".set\tmips2", 0);
11496 /* End a block started by mips_start_ll_sc_sync_block. */
11499 mips_end_ll_sc_sync_block (void)
11501 if (!ISA_HAS_LL_SC
)
11502 output_asm_insn (".set\tpop", 0);
11505 /* Output and/or return the asm template for a sync instruction. */
11508 mips_output_sync (void)
11510 mips_start_ll_sc_sync_block ();
11511 output_asm_insn ("sync", 0);
11512 mips_end_ll_sc_sync_block ();
11516 /* Return the asm template associated with sync_insn1 value TYPE.
11517 IS_64BIT_P is true if we want a 64-bit rather than 32-bit operation. */
11519 static const char *
11520 mips_sync_insn1_template (enum attr_sync_insn1 type
, bool is_64bit_p
)
11524 case SYNC_INSN1_MOVE
:
11525 return "move\t%0,%z2";
11526 case SYNC_INSN1_LI
:
11527 return "li\t%0,%2";
11528 case SYNC_INSN1_ADDU
:
11529 return is_64bit_p
? "daddu\t%0,%1,%z2" : "addu\t%0,%1,%z2";
11530 case SYNC_INSN1_ADDIU
:
11531 return is_64bit_p
? "daddiu\t%0,%1,%2" : "addiu\t%0,%1,%2";
11532 case SYNC_INSN1_SUBU
:
11533 return is_64bit_p
? "dsubu\t%0,%1,%z2" : "subu\t%0,%1,%z2";
11534 case SYNC_INSN1_AND
:
11535 return "and\t%0,%1,%z2";
11536 case SYNC_INSN1_ANDI
:
11537 return "andi\t%0,%1,%2";
11538 case SYNC_INSN1_OR
:
11539 return "or\t%0,%1,%z2";
11540 case SYNC_INSN1_ORI
:
11541 return "ori\t%0,%1,%2";
11542 case SYNC_INSN1_XOR
:
11543 return "xor\t%0,%1,%z2";
11544 case SYNC_INSN1_XORI
:
11545 return "xori\t%0,%1,%2";
11547 gcc_unreachable ();
11550 /* Return the asm template associated with sync_insn2 value TYPE. */
11552 static const char *
11553 mips_sync_insn2_template (enum attr_sync_insn2 type
)
11557 case SYNC_INSN2_NOP
:
11558 gcc_unreachable ();
11559 case SYNC_INSN2_AND
:
11560 return "and\t%0,%1,%z2";
11561 case SYNC_INSN2_XOR
:
11562 return "xor\t%0,%1,%z2";
11563 case SYNC_INSN2_NOT
:
11564 return "nor\t%0,%1,%.";
11566 gcc_unreachable ();
11569 /* OPERANDS are the operands to a sync loop instruction and INDEX is
11570 the value of the one of the sync_* attributes. Return the operand
11571 referred to by the attribute, or DEFAULT_VALUE if the insn doesn't
11572 have the associated attribute. */
11575 mips_get_sync_operand (rtx
*operands
, int index
, rtx default_value
)
11578 default_value
= operands
[index
- 1];
11579 return default_value
;
11582 /* INSN is a sync loop with operands OPERANDS. Build up a multi-insn
11583 sequence for it. */
11586 mips_process_sync_loop (rtx insn
, rtx
*operands
)
11588 rtx at
, mem
, oldval
, newval
, inclusive_mask
, exclusive_mask
;
11589 rtx required_oldval
, insn1_op2
, tmp1
, tmp2
, tmp3
;
11590 unsigned int tmp3_insn
;
11591 enum attr_sync_insn1 insn1
;
11592 enum attr_sync_insn2 insn2
;
11595 /* Read an operand from the sync_WHAT attribute and store it in
11596 variable WHAT. DEFAULT is the default value if no attribute
11598 #define READ_OPERAND(WHAT, DEFAULT) \
11599 WHAT = mips_get_sync_operand (operands, (int) get_attr_sync_##WHAT (insn), \
11602 /* Read the memory. */
11603 READ_OPERAND (mem
, 0);
11605 is_64bit_p
= (GET_MODE_BITSIZE (GET_MODE (mem
)) == 64);
11607 /* Read the other attributes. */
11608 at
= gen_rtx_REG (GET_MODE (mem
), AT_REGNUM
);
11609 READ_OPERAND (oldval
, at
);
11610 READ_OPERAND (newval
, at
);
11611 READ_OPERAND (inclusive_mask
, 0);
11612 READ_OPERAND (exclusive_mask
, 0);
11613 READ_OPERAND (required_oldval
, 0);
11614 READ_OPERAND (insn1_op2
, 0);
11615 insn1
= get_attr_sync_insn1 (insn
);
11616 insn2
= get_attr_sync_insn2 (insn
);
11618 mips_multi_start ();
11620 /* Output the release side of the memory barrier. */
11621 if (get_attr_sync_release_barrier (insn
) == SYNC_RELEASE_BARRIER_YES
)
11623 if (required_oldval
== 0 && TARGET_OCTEON
)
11625 /* Octeon doesn't reorder reads, so a full barrier can be
11626 created by using SYNCW to order writes combined with the
11627 write from the following SC. When the SC successfully
11628 completes, we know that all preceding writes are also
11629 committed to the coherent memory system. It is possible
11630 for a single SYNCW to fail, but a pair of them will never
11631 fail, so we use two. */
11632 mips_multi_add_insn ("syncw", NULL
);
11633 mips_multi_add_insn ("syncw", NULL
);
11636 mips_multi_add_insn ("sync", NULL
);
11639 /* Output the branch-back label. */
11640 mips_multi_add_label ("1:");
11642 /* OLDVAL = *MEM. */
11643 mips_multi_add_insn (is_64bit_p
? "lld\t%0,%1" : "ll\t%0,%1",
11644 oldval
, mem
, NULL
);
11646 /* if ((OLDVAL & INCLUSIVE_MASK) != REQUIRED_OLDVAL) goto 2. */
11647 if (required_oldval
)
11649 if (inclusive_mask
== 0)
11653 gcc_assert (oldval
!= at
);
11654 mips_multi_add_insn ("and\t%0,%1,%2",
11655 at
, oldval
, inclusive_mask
, NULL
);
11658 mips_multi_add_insn ("bne\t%0,%z1,2f", tmp1
, required_oldval
, NULL
);
11661 /* $TMP1 = OLDVAL & EXCLUSIVE_MASK. */
11662 if (exclusive_mask
== 0)
11666 gcc_assert (oldval
!= at
);
11667 mips_multi_add_insn ("and\t%0,%1,%z2",
11668 at
, oldval
, exclusive_mask
, NULL
);
11672 /* $TMP2 = INSN1 (OLDVAL, INSN1_OP2).
11674 We can ignore moves if $TMP4 != INSN1_OP2, since we'll still emit
11675 at least one instruction in that case. */
11676 if (insn1
== SYNC_INSN1_MOVE
11677 && (tmp1
!= const0_rtx
|| insn2
!= SYNC_INSN2_NOP
))
11681 mips_multi_add_insn (mips_sync_insn1_template (insn1
, is_64bit_p
),
11682 newval
, oldval
, insn1_op2
, NULL
);
11686 /* $TMP3 = INSN2 ($TMP2, INCLUSIVE_MASK). */
11687 if (insn2
== SYNC_INSN2_NOP
)
11691 mips_multi_add_insn (mips_sync_insn2_template (insn2
),
11692 newval
, tmp2
, inclusive_mask
, NULL
);
11695 tmp3_insn
= mips_multi_last_index ();
11697 /* $AT = $TMP1 | $TMP3. */
11698 if (tmp1
== const0_rtx
|| tmp3
== const0_rtx
)
11700 mips_multi_set_operand (tmp3_insn
, 0, at
);
11705 gcc_assert (tmp1
!= tmp3
);
11706 mips_multi_add_insn ("or\t%0,%1,%2", at
, tmp1
, tmp3
, NULL
);
11709 /* if (!commit (*MEM = $AT)) goto 1.
11711 This will sometimes be a delayed branch; see the write code below
11713 mips_multi_add_insn (is_64bit_p
? "scd\t%0,%1" : "sc\t%0,%1", at
, mem
, NULL
);
11714 mips_multi_add_insn ("beq%?\t%0,%.,1b", at
, NULL
);
11716 /* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */
11717 if (insn1
!= SYNC_INSN1_MOVE
&& insn1
!= SYNC_INSN1_LI
&& tmp3
!= newval
)
11719 mips_multi_copy_insn (tmp3_insn
);
11720 mips_multi_set_operand (mips_multi_last_index (), 0, newval
);
11723 mips_multi_add_insn ("nop", NULL
);
11725 /* Output the acquire side of the memory barrier. */
11726 if (TARGET_SYNC_AFTER_SC
)
11727 mips_multi_add_insn ("sync", NULL
);
11729 /* Output the exit label, if needed. */
11730 if (required_oldval
)
11731 mips_multi_add_label ("2:");
11733 #undef READ_OPERAND
11736 /* Output and/or return the asm template for sync loop INSN, which has
11737 the operands given by OPERANDS. */
11740 mips_output_sync_loop (rtx insn
, rtx
*operands
)
11742 mips_process_sync_loop (insn
, operands
);
11744 /* Use branch-likely instructions to work around the LL/SC R10000
11746 mips_branch_likely
= TARGET_FIX_R10000
;
11748 mips_push_asm_switch (&mips_noreorder
);
11749 mips_push_asm_switch (&mips_nomacro
);
11750 mips_push_asm_switch (&mips_noat
);
11751 mips_start_ll_sc_sync_block ();
11753 mips_multi_write ();
11755 mips_end_ll_sc_sync_block ();
11756 mips_pop_asm_switch (&mips_noat
);
11757 mips_pop_asm_switch (&mips_nomacro
);
11758 mips_pop_asm_switch (&mips_noreorder
);
11763 /* Return the number of individual instructions in sync loop INSN,
11764 which has the operands given by OPERANDS. */
11767 mips_sync_loop_insns (rtx insn
, rtx
*operands
)
11769 mips_process_sync_loop (insn
, operands
);
11770 return mips_multi_num_insns
;
11773 /* Return the assembly code for DIV or DDIV instruction DIVISION, which has
11774 the operands given by OPERANDS. Add in a divide-by-zero check if needed.
11776 When working around R4000 and R4400 errata, we need to make sure that
11777 the division is not immediately followed by a shift[1][2]. We also
11778 need to stop the division from being put into a branch delay slot[3].
11779 The easiest way to avoid both problems is to add a nop after the
11780 division. When a divide-by-zero check is needed, this nop can be
11781 used to fill the branch delay slot.
11783 [1] If a double-word or a variable shift executes immediately
11784 after starting an integer division, the shift may give an
11785 incorrect result. See quotations of errata #16 and #28 from
11786 "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11787 in mips.md for details.
11789 [2] A similar bug to [1] exists for all revisions of the
11790 R4000 and the R4400 when run in an MC configuration.
11791 From "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0":
11793 "19. In this following sequence:
11795 ddiv (or ddivu or div or divu)
11796 dsll32 (or dsrl32, dsra32)
11798 if an MPT stall occurs, while the divide is slipping the cpu
11799 pipeline, then the following double shift would end up with an
11802 Workaround: The compiler needs to avoid generating any
11803 sequence with divide followed by extended double shift."
11805 This erratum is also present in "MIPS R4400MC Errata, Processor
11806 Revision 1.0" and "MIPS R4400MC Errata, Processor Revision 2.0
11807 & 3.0" as errata #10 and #4, respectively.
11809 [3] From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
11810 (also valid for MIPS R4000MC processors):
11812 "52. R4000SC: This bug does not apply for the R4000PC.
11814 There are two flavors of this bug:
11816 1) If the instruction just after divide takes an RF exception
11817 (tlb-refill, tlb-invalid) and gets an instruction cache
11818 miss (both primary and secondary) and the line which is
11819 currently in secondary cache at this index had the first
11820 data word, where the bits 5..2 are set, then R4000 would
11821 get a wrong result for the div.
11826 ------------------- # end-of page. -tlb-refill
11831 ------------------- # end-of page. -tlb-invalid
11834 2) If the divide is in the taken branch delay slot, where the
11835 target takes RF exception and gets an I-cache miss for the
11836 exception vector or where I-cache miss occurs for the
11837 target address, under the above mentioned scenarios, the
11838 div would get wrong results.
11841 j r2 # to next page mapped or unmapped
11842 div r8,r9 # this bug would be there as long
11843 # as there is an ICache miss and
11844 nop # the "data pattern" is present
11847 beq r0, r0, NextPage # to Next page
11851 This bug is present for div, divu, ddiv, and ddivu
11854 Workaround: For item 1), OS could make sure that the next page
11855 after the divide instruction is also mapped. For item 2), the
11856 compiler could make sure that the divide instruction is not in
11857 the branch delay slot."
11859 These processors have PRId values of 0x00004220 and 0x00004300 for
11860 the R4000 and 0x00004400, 0x00004500 and 0x00004600 for the R4400. */
11863 mips_output_division (const char *division
, rtx
*operands
)
11868 if (TARGET_FIX_R4000
|| TARGET_FIX_R4400
)
11870 output_asm_insn (s
, operands
);
11873 if (TARGET_CHECK_ZERO_DIV
)
11877 output_asm_insn (s
, operands
);
11878 s
= "bnez\t%2,1f\n\tbreak\t7\n1:";
11880 else if (GENERATE_DIVIDE_TRAPS
)
11882 /* Avoid long replay penalty on load miss by putting the trap before
11885 output_asm_insn ("teq\t%2,%.,7", operands
);
11888 output_asm_insn (s
, operands
);
11889 s
= "teq\t%2,%.,7";
11894 output_asm_insn ("%(bne\t%2,%.,1f", operands
);
11895 output_asm_insn (s
, operands
);
11896 s
= "break\t7%)\n1:";
11902 /* Return true if IN_INSN is a multiply-add or multiply-subtract
11903 instruction and if OUT_INSN assigns to the accumulator operand. */
11906 mips_linked_madd_p (rtx out_insn
, rtx in_insn
)
11910 x
= single_set (in_insn
);
11916 if (GET_CODE (x
) == PLUS
11917 && GET_CODE (XEXP (x
, 0)) == MULT
11918 && reg_set_p (XEXP (x
, 1), out_insn
))
11921 if (GET_CODE (x
) == MINUS
11922 && GET_CODE (XEXP (x
, 1)) == MULT
11923 && reg_set_p (XEXP (x
, 0), out_insn
))
11929 /* True if the dependency between OUT_INSN and IN_INSN is on the store
11930 data rather than the address. We need this because the cprestore
11931 pattern is type "store", but is defined using an UNSPEC_VOLATILE,
11932 which causes the default routine to abort. We just return false
11936 mips_store_data_bypass_p (rtx out_insn
, rtx in_insn
)
11938 if (GET_CODE (PATTERN (in_insn
)) == UNSPEC_VOLATILE
)
11941 return !store_data_bypass_p (out_insn
, in_insn
);
11945 /* Variables and flags used in scheduler hooks when tuning for
11949 /* Variables to support Loongson 2E/2F round-robin [F]ALU1/2 dispatch
11952 /* If true, then next ALU1/2 instruction will go to ALU1. */
11955 /* If true, then next FALU1/2 unstruction will go to FALU1. */
11958 /* Codes to query if [f]alu{1,2}_core units are subscribed or not. */
11959 int alu1_core_unit_code
;
11960 int alu2_core_unit_code
;
11961 int falu1_core_unit_code
;
11962 int falu2_core_unit_code
;
11964 /* True if current cycle has a multi instruction.
11965 This flag is used in mips_ls2_dfa_post_advance_cycle. */
11966 bool cycle_has_multi_p
;
11968 /* Instructions to subscribe ls2_[f]alu{1,2}_turn_enabled units.
11969 These are used in mips_ls2_dfa_post_advance_cycle to initialize
11971 E.g., when alu1_turn_enabled_insn is issued it makes next ALU1/2
11972 instruction to go ALU1. */
11973 rtx alu1_turn_enabled_insn
;
11974 rtx alu2_turn_enabled_insn
;
11975 rtx falu1_turn_enabled_insn
;
11976 rtx falu2_turn_enabled_insn
;
11979 /* Implement TARGET_SCHED_ADJUST_COST. We assume that anti and output
11980 dependencies have no cost, except on the 20Kc where output-dependence
11981 is treated like input-dependence. */
11984 mips_adjust_cost (rtx insn ATTRIBUTE_UNUSED
, rtx link
,
11985 rtx dep ATTRIBUTE_UNUSED
, int cost
)
11987 if (REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
11990 if (REG_NOTE_KIND (link
) != 0)
11995 /* Return the number of instructions that can be issued per cycle. */
11998 mips_issue_rate (void)
12002 case PROCESSOR_74KC
:
12003 case PROCESSOR_74KF2_1
:
12004 case PROCESSOR_74KF1_1
:
12005 case PROCESSOR_74KF3_2
:
12006 /* The 74k is not strictly quad-issue cpu, but can be seen as one
12007 by the scheduler. It can issue 1 ALU, 1 AGEN and 2 FPU insns,
12008 but in reality only a maximum of 3 insns can be issued as
12009 floating-point loads and stores also require a slot in the
12011 case PROCESSOR_R10000
:
12012 /* All R10K Processors are quad-issue (being the first MIPS
12013 processors to support this feature). */
12016 case PROCESSOR_20KC
:
12017 case PROCESSOR_R4130
:
12018 case PROCESSOR_R5400
:
12019 case PROCESSOR_R5500
:
12020 case PROCESSOR_R7000
:
12021 case PROCESSOR_R9000
:
12022 case PROCESSOR_OCTEON
:
12025 case PROCESSOR_SB1
:
12026 case PROCESSOR_SB1A
:
12027 /* This is actually 4, but we get better performance if we claim 3.
12028 This is partly because of unwanted speculative code motion with the
12029 larger number, and partly because in most common cases we can't
12030 reach the theoretical max of 4. */
12033 case PROCESSOR_LOONGSON_2E
:
12034 case PROCESSOR_LOONGSON_2F
:
12035 case PROCESSOR_LOONGSON_3A
:
12043 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook for Loongson2. */
12046 mips_ls2_init_dfa_post_cycle_insn (void)
12049 emit_insn (gen_ls2_alu1_turn_enabled_insn ());
12050 mips_ls2
.alu1_turn_enabled_insn
= get_insns ();
12054 emit_insn (gen_ls2_alu2_turn_enabled_insn ());
12055 mips_ls2
.alu2_turn_enabled_insn
= get_insns ();
12059 emit_insn (gen_ls2_falu1_turn_enabled_insn ());
12060 mips_ls2
.falu1_turn_enabled_insn
= get_insns ();
12064 emit_insn (gen_ls2_falu2_turn_enabled_insn ());
12065 mips_ls2
.falu2_turn_enabled_insn
= get_insns ();
12068 mips_ls2
.alu1_core_unit_code
= get_cpu_unit_code ("ls2_alu1_core");
12069 mips_ls2
.alu2_core_unit_code
= get_cpu_unit_code ("ls2_alu2_core");
12070 mips_ls2
.falu1_core_unit_code
= get_cpu_unit_code ("ls2_falu1_core");
12071 mips_ls2
.falu2_core_unit_code
= get_cpu_unit_code ("ls2_falu2_core");
12074 /* Implement TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN hook.
12075 Init data used in mips_dfa_post_advance_cycle. */
12078 mips_init_dfa_post_cycle_insn (void)
12080 if (TUNE_LOONGSON_2EF
)
12081 mips_ls2_init_dfa_post_cycle_insn ();
12084 /* Initialize STATE when scheduling for Loongson 2E/2F.
12085 Support round-robin dispatch scheme by enabling only one of
12086 ALU1/ALU2 and one of FALU1/FALU2 units for ALU1/2 and FALU1/2 instructions
12090 mips_ls2_dfa_post_advance_cycle (state_t state
)
12092 if (cpu_unit_reservation_p (state
, mips_ls2
.alu1_core_unit_code
))
12094 /* Though there are no non-pipelined ALU1 insns,
12095 we can get an instruction of type 'multi' before reload. */
12096 gcc_assert (mips_ls2
.cycle_has_multi_p
);
12097 mips_ls2
.alu1_turn_p
= false;
12100 mips_ls2
.cycle_has_multi_p
= false;
12102 if (cpu_unit_reservation_p (state
, mips_ls2
.alu2_core_unit_code
))
12103 /* We have a non-pipelined alu instruction in the core,
12104 adjust round-robin counter. */
12105 mips_ls2
.alu1_turn_p
= true;
12107 if (mips_ls2
.alu1_turn_p
)
12109 if (state_transition (state
, mips_ls2
.alu1_turn_enabled_insn
) >= 0)
12110 gcc_unreachable ();
12114 if (state_transition (state
, mips_ls2
.alu2_turn_enabled_insn
) >= 0)
12115 gcc_unreachable ();
12118 if (cpu_unit_reservation_p (state
, mips_ls2
.falu1_core_unit_code
))
12120 /* There are no non-pipelined FALU1 insns. */
12121 gcc_unreachable ();
12122 mips_ls2
.falu1_turn_p
= false;
12125 if (cpu_unit_reservation_p (state
, mips_ls2
.falu2_core_unit_code
))
12126 /* We have a non-pipelined falu instruction in the core,
12127 adjust round-robin counter. */
12128 mips_ls2
.falu1_turn_p
= true;
12130 if (mips_ls2
.falu1_turn_p
)
12132 if (state_transition (state
, mips_ls2
.falu1_turn_enabled_insn
) >= 0)
12133 gcc_unreachable ();
12137 if (state_transition (state
, mips_ls2
.falu2_turn_enabled_insn
) >= 0)
12138 gcc_unreachable ();
12142 /* Implement TARGET_SCHED_DFA_POST_ADVANCE_CYCLE.
12143 This hook is being called at the start of each cycle. */
12146 mips_dfa_post_advance_cycle (void)
12148 if (TUNE_LOONGSON_2EF
)
12149 mips_ls2_dfa_post_advance_cycle (curr_state
);
12152 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
12153 be as wide as the scheduling freedom in the DFA. */
12156 mips_multipass_dfa_lookahead (void)
12158 /* Can schedule up to 4 of the 6 function units in any one cycle. */
12162 if (TUNE_LOONGSON_2EF
|| TUNE_LOONGSON_3A
)
12171 /* Remove the instruction at index LOWER from ready queue READY and
12172 reinsert it in front of the instruction at index HIGHER. LOWER must
12176 mips_promote_ready (rtx
*ready
, int lower
, int higher
)
12181 new_head
= ready
[lower
];
12182 for (i
= lower
; i
< higher
; i
++)
12183 ready
[i
] = ready
[i
+ 1];
12184 ready
[i
] = new_head
;
12187 /* If the priority of the instruction at POS2 in the ready queue READY
12188 is within LIMIT units of that of the instruction at POS1, swap the
12189 instructions if POS2 is not already less than POS1. */
12192 mips_maybe_swap_ready (rtx
*ready
, int pos1
, int pos2
, int limit
)
12195 && INSN_PRIORITY (ready
[pos1
]) + limit
>= INSN_PRIORITY (ready
[pos2
]))
12199 temp
= ready
[pos1
];
12200 ready
[pos1
] = ready
[pos2
];
12201 ready
[pos2
] = temp
;
12205 /* Used by TUNE_MACC_CHAINS to record the last scheduled instruction
12206 that may clobber hi or lo. */
12207 static rtx mips_macc_chains_last_hilo
;
12209 /* A TUNE_MACC_CHAINS helper function. Record that instruction INSN has
12210 been scheduled, updating mips_macc_chains_last_hilo appropriately. */
12213 mips_macc_chains_record (rtx insn
)
12215 if (get_attr_may_clobber_hilo (insn
))
12216 mips_macc_chains_last_hilo
= insn
;
12219 /* A TUNE_MACC_CHAINS helper function. Search ready queue READY, which
12220 has NREADY elements, looking for a multiply-add or multiply-subtract
12221 instruction that is cumulative with mips_macc_chains_last_hilo.
12222 If there is one, promote it ahead of anything else that might
12223 clobber hi or lo. */
12226 mips_macc_chains_reorder (rtx
*ready
, int nready
)
12230 if (mips_macc_chains_last_hilo
!= 0)
12231 for (i
= nready
- 1; i
>= 0; i
--)
12232 if (mips_linked_madd_p (mips_macc_chains_last_hilo
, ready
[i
]))
12234 for (j
= nready
- 1; j
> i
; j
--)
12235 if (recog_memoized (ready
[j
]) >= 0
12236 && get_attr_may_clobber_hilo (ready
[j
]))
12238 mips_promote_ready (ready
, i
, j
);
12245 /* The last instruction to be scheduled. */
12246 static rtx vr4130_last_insn
;
12248 /* A note_stores callback used by vr4130_true_reg_dependence_p. DATA
12249 points to an rtx that is initially an instruction. Nullify the rtx
12250 if the instruction uses the value of register X. */
12253 vr4130_true_reg_dependence_p_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
12258 insn_ptr
= (rtx
*) data
;
12261 && reg_referenced_p (x
, PATTERN (*insn_ptr
)))
12265 /* Return true if there is true register dependence between vr4130_last_insn
12269 vr4130_true_reg_dependence_p (rtx insn
)
12271 note_stores (PATTERN (vr4130_last_insn
),
12272 vr4130_true_reg_dependence_p_1
, &insn
);
12276 /* A TUNE_MIPS4130 helper function. Given that INSN1 is at the head of
12277 the ready queue and that INSN2 is the instruction after it, return
12278 true if it is worth promoting INSN2 ahead of INSN1. Look for cases
12279 in which INSN1 and INSN2 can probably issue in parallel, but for
12280 which (INSN2, INSN1) should be less sensitive to instruction
12281 alignment than (INSN1, INSN2). See 4130.md for more details. */
12284 vr4130_swap_insns_p (rtx insn1
, rtx insn2
)
12286 sd_iterator_def sd_it
;
12289 /* Check for the following case:
12291 1) there is some other instruction X with an anti dependence on INSN1;
12292 2) X has a higher priority than INSN2; and
12293 3) X is an arithmetic instruction (and thus has no unit restrictions).
12295 If INSN1 is the last instruction blocking X, it would better to
12296 choose (INSN1, X) over (INSN2, INSN1). */
12297 FOR_EACH_DEP (insn1
, SD_LIST_FORW
, sd_it
, dep
)
12298 if (DEP_TYPE (dep
) == REG_DEP_ANTI
12299 && INSN_PRIORITY (DEP_CON (dep
)) > INSN_PRIORITY (insn2
)
12300 && recog_memoized (DEP_CON (dep
)) >= 0
12301 && get_attr_vr4130_class (DEP_CON (dep
)) == VR4130_CLASS_ALU
)
12304 if (vr4130_last_insn
!= 0
12305 && recog_memoized (insn1
) >= 0
12306 && recog_memoized (insn2
) >= 0)
12308 /* See whether INSN1 and INSN2 use different execution units,
12309 or if they are both ALU-type instructions. If so, they can
12310 probably execute in parallel. */
12311 enum attr_vr4130_class class1
= get_attr_vr4130_class (insn1
);
12312 enum attr_vr4130_class class2
= get_attr_vr4130_class (insn2
);
12313 if (class1
!= class2
|| class1
== VR4130_CLASS_ALU
)
12315 /* If only one of the instructions has a dependence on
12316 vr4130_last_insn, prefer to schedule the other one first. */
12317 bool dep1_p
= vr4130_true_reg_dependence_p (insn1
);
12318 bool dep2_p
= vr4130_true_reg_dependence_p (insn2
);
12319 if (dep1_p
!= dep2_p
)
12322 /* Prefer to schedule INSN2 ahead of INSN1 if vr4130_last_insn
12323 is not an ALU-type instruction and if INSN1 uses the same
12324 execution unit. (Note that if this condition holds, we already
12325 know that INSN2 uses a different execution unit.) */
12326 if (class1
!= VR4130_CLASS_ALU
12327 && recog_memoized (vr4130_last_insn
) >= 0
12328 && class1
== get_attr_vr4130_class (vr4130_last_insn
))
12335 /* A TUNE_MIPS4130 helper function. (READY, NREADY) describes a ready
12336 queue with at least two instructions. Swap the first two if
12337 vr4130_swap_insns_p says that it could be worthwhile. */
12340 vr4130_reorder (rtx
*ready
, int nready
)
12342 if (vr4130_swap_insns_p (ready
[nready
- 1], ready
[nready
- 2]))
12343 mips_promote_ready (ready
, nready
- 2, nready
- 1);
12346 /* Record whether last 74k AGEN instruction was a load or store. */
12347 static enum attr_type mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12349 /* Initialize mips_last_74k_agen_insn from INSN. A null argument
12350 resets to TYPE_UNKNOWN state. */
12353 mips_74k_agen_init (rtx insn
)
12355 if (!insn
|| CALL_P (insn
) || JUMP_P (insn
))
12356 mips_last_74k_agen_insn
= TYPE_UNKNOWN
;
12359 enum attr_type type
= get_attr_type (insn
);
12360 if (type
== TYPE_LOAD
|| type
== TYPE_STORE
)
12361 mips_last_74k_agen_insn
= type
;
12365 /* A TUNE_74K helper function. The 74K AGEN pipeline likes multiple
12366 loads to be grouped together, and multiple stores to be grouped
12367 together. Swap things around in the ready queue to make this happen. */
12370 mips_74k_agen_reorder (rtx
*ready
, int nready
)
12373 int store_pos
, load_pos
;
12378 for (i
= nready
- 1; i
>= 0; i
--)
12380 rtx insn
= ready
[i
];
12381 if (USEFUL_INSN_P (insn
))
12382 switch (get_attr_type (insn
))
12385 if (store_pos
== -1)
12390 if (load_pos
== -1)
12399 if (load_pos
== -1 || store_pos
== -1)
12402 switch (mips_last_74k_agen_insn
)
12405 /* Prefer to schedule loads since they have a higher latency. */
12407 /* Swap loads to the front of the queue. */
12408 mips_maybe_swap_ready (ready
, load_pos
, store_pos
, 4);
12411 /* Swap stores to the front of the queue. */
12412 mips_maybe_swap_ready (ready
, store_pos
, load_pos
, 4);
12419 /* Implement TARGET_SCHED_INIT. */
12422 mips_sched_init (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12423 int max_ready ATTRIBUTE_UNUSED
)
12425 mips_macc_chains_last_hilo
= 0;
12426 vr4130_last_insn
= 0;
12427 mips_74k_agen_init (NULL_RTX
);
12429 /* When scheduling for Loongson2, branch instructions go to ALU1,
12430 therefore basic block is most likely to start with round-robin counter
12431 pointed to ALU2. */
12432 mips_ls2
.alu1_turn_p
= false;
12433 mips_ls2
.falu1_turn_p
= true;
12436 /* Subroutine used by TARGET_SCHED_REORDER and TARGET_SCHED_REORDER2. */
12439 mips_sched_reorder_1 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12440 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12442 if (!reload_completed
12443 && TUNE_MACC_CHAINS
12445 mips_macc_chains_reorder (ready
, *nreadyp
);
12447 if (reload_completed
12449 && !TARGET_VR4130_ALIGN
12451 vr4130_reorder (ready
, *nreadyp
);
12454 mips_74k_agen_reorder (ready
, *nreadyp
);
12457 /* Implement TARGET_SCHED_REORDER. */
12460 mips_sched_reorder (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12461 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12463 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
12464 return mips_issue_rate ();
12467 /* Implement TARGET_SCHED_REORDER2. */
12470 mips_sched_reorder2 (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12471 rtx
*ready
, int *nreadyp
, int cycle ATTRIBUTE_UNUSED
)
12473 mips_sched_reorder_1 (file
, verbose
, ready
, nreadyp
, cycle
);
12474 return cached_can_issue_more
;
12477 /* Update round-robin counters for ALU1/2 and FALU1/2. */
12480 mips_ls2_variable_issue (rtx insn
)
12482 if (mips_ls2
.alu1_turn_p
)
12484 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu1_core_unit_code
))
12485 mips_ls2
.alu1_turn_p
= false;
12489 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.alu2_core_unit_code
))
12490 mips_ls2
.alu1_turn_p
= true;
12493 if (mips_ls2
.falu1_turn_p
)
12495 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu1_core_unit_code
))
12496 mips_ls2
.falu1_turn_p
= false;
12500 if (cpu_unit_reservation_p (curr_state
, mips_ls2
.falu2_core_unit_code
))
12501 mips_ls2
.falu1_turn_p
= true;
12504 if (recog_memoized (insn
) >= 0)
12505 mips_ls2
.cycle_has_multi_p
|= (get_attr_type (insn
) == TYPE_MULTI
);
12508 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
12511 mips_variable_issue (FILE *file ATTRIBUTE_UNUSED
, int verbose ATTRIBUTE_UNUSED
,
12512 rtx insn
, int more
)
12514 /* Ignore USEs and CLOBBERs; don't count them against the issue rate. */
12515 if (USEFUL_INSN_P (insn
))
12517 if (get_attr_type (insn
) != TYPE_GHOST
)
12519 if (!reload_completed
&& TUNE_MACC_CHAINS
)
12520 mips_macc_chains_record (insn
);
12521 vr4130_last_insn
= insn
;
12523 mips_74k_agen_init (insn
);
12524 else if (TUNE_LOONGSON_2EF
)
12525 mips_ls2_variable_issue (insn
);
12528 /* Instructions of type 'multi' should all be split before
12529 the second scheduling pass. */
12530 gcc_assert (!reload_completed
12531 || recog_memoized (insn
) < 0
12532 || get_attr_type (insn
) != TYPE_MULTI
);
12534 cached_can_issue_more
= more
;
12538 /* Given that we have an rtx of the form (prefetch ... WRITE LOCALITY),
12539 return the first operand of the associated PREF or PREFX insn. */
12542 mips_prefetch_cookie (rtx write
, rtx locality
)
12544 /* store_streamed / load_streamed. */
12545 if (INTVAL (locality
) <= 0)
12546 return GEN_INT (INTVAL (write
) + 4);
12548 /* store / load. */
12549 if (INTVAL (locality
) <= 2)
12552 /* store_retained / load_retained. */
12553 return GEN_INT (INTVAL (write
) + 6);
12556 /* Flags that indicate when a built-in function is available.
12558 BUILTIN_AVAIL_NON_MIPS16
12559 The function is available on the current target, but only
12560 in non-MIPS16 mode. */
12561 #define BUILTIN_AVAIL_NON_MIPS16 1
12563 /* Declare an availability predicate for built-in functions that
12564 require non-MIPS16 mode and also require COND to be true.
12565 NAME is the main part of the predicate's name. */
12566 #define AVAIL_NON_MIPS16(NAME, COND) \
12567 static unsigned int \
12568 mips_builtin_avail_##NAME (void) \
12570 return (COND) ? BUILTIN_AVAIL_NON_MIPS16 : 0; \
12573 /* This structure describes a single built-in function. */
12574 struct mips_builtin_description
{
12575 /* The code of the main .md file instruction. See mips_builtin_type
12576 for more information. */
12577 enum insn_code icode
;
12579 /* The floating-point comparison code to use with ICODE, if any. */
12580 enum mips_fp_condition cond
;
12582 /* The name of the built-in function. */
12585 /* Specifies how the function should be expanded. */
12586 enum mips_builtin_type builtin_type
;
12588 /* The function's prototype. */
12589 enum mips_function_type function_type
;
12591 /* Whether the function is available. */
12592 unsigned int (*avail
) (void);
12595 AVAIL_NON_MIPS16 (paired_single
, TARGET_PAIRED_SINGLE_FLOAT
)
12596 AVAIL_NON_MIPS16 (sb1_paired_single
, TARGET_SB1
&& TARGET_PAIRED_SINGLE_FLOAT
)
12597 AVAIL_NON_MIPS16 (mips3d
, TARGET_MIPS3D
)
12598 AVAIL_NON_MIPS16 (dsp
, TARGET_DSP
)
12599 AVAIL_NON_MIPS16 (dspr2
, TARGET_DSPR2
)
12600 AVAIL_NON_MIPS16 (dsp_32
, !TARGET_64BIT
&& TARGET_DSP
)
12601 AVAIL_NON_MIPS16 (dspr2_32
, !TARGET_64BIT
&& TARGET_DSPR2
)
12602 AVAIL_NON_MIPS16 (loongson
, TARGET_LOONGSON_VECTORS
)
12603 AVAIL_NON_MIPS16 (cache
, TARGET_CACHE_BUILTIN
)
12605 /* Construct a mips_builtin_description from the given arguments.
12607 INSN is the name of the associated instruction pattern, without the
12608 leading CODE_FOR_mips_.
12610 CODE is the floating-point condition code associated with the
12611 function. It can be 'f' if the field is not applicable.
12613 NAME is the name of the function itself, without the leading
12616 BUILTIN_TYPE and FUNCTION_TYPE are mips_builtin_description fields.
12618 AVAIL is the name of the availability predicate, without the leading
12619 mips_builtin_avail_. */
12620 #define MIPS_BUILTIN(INSN, COND, NAME, BUILTIN_TYPE, \
12621 FUNCTION_TYPE, AVAIL) \
12622 { CODE_FOR_mips_ ## INSN, MIPS_FP_COND_ ## COND, \
12623 "__builtin_mips_" NAME, BUILTIN_TYPE, FUNCTION_TYPE, \
12624 mips_builtin_avail_ ## AVAIL }
12626 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT function
12627 mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE and AVAIL
12628 are as for MIPS_BUILTIN. */
12629 #define DIRECT_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12630 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT, FUNCTION_TYPE, AVAIL)
12632 /* Define __builtin_mips_<INSN>_<COND>_{s,d} functions, both of which
12633 are subject to mips_builtin_avail_<AVAIL>. */
12634 #define CMP_SCALAR_BUILTINS(INSN, COND, AVAIL) \
12635 MIPS_BUILTIN (INSN ## _cond_s, COND, #INSN "_" #COND "_s", \
12636 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_SF_SF, AVAIL), \
12637 MIPS_BUILTIN (INSN ## _cond_d, COND, #INSN "_" #COND "_d", \
12638 MIPS_BUILTIN_CMP_SINGLE, MIPS_INT_FTYPE_DF_DF, AVAIL)
12640 /* Define __builtin_mips_{any,all,upper,lower}_<INSN>_<COND>_ps.
12641 The lower and upper forms are subject to mips_builtin_avail_<AVAIL>
12642 while the any and all forms are subject to mips_builtin_avail_mips3d. */
12643 #define CMP_PS_BUILTINS(INSN, COND, AVAIL) \
12644 MIPS_BUILTIN (INSN ## _cond_ps, COND, "any_" #INSN "_" #COND "_ps", \
12645 MIPS_BUILTIN_CMP_ANY, MIPS_INT_FTYPE_V2SF_V2SF, \
12647 MIPS_BUILTIN (INSN ## _cond_ps, COND, "all_" #INSN "_" #COND "_ps", \
12648 MIPS_BUILTIN_CMP_ALL, MIPS_INT_FTYPE_V2SF_V2SF, \
12650 MIPS_BUILTIN (INSN ## _cond_ps, COND, "lower_" #INSN "_" #COND "_ps", \
12651 MIPS_BUILTIN_CMP_LOWER, MIPS_INT_FTYPE_V2SF_V2SF, \
12653 MIPS_BUILTIN (INSN ## _cond_ps, COND, "upper_" #INSN "_" #COND "_ps", \
12654 MIPS_BUILTIN_CMP_UPPER, MIPS_INT_FTYPE_V2SF_V2SF, \
12657 /* Define __builtin_mips_{any,all}_<INSN>_<COND>_4s. The functions
12658 are subject to mips_builtin_avail_mips3d. */
12659 #define CMP_4S_BUILTINS(INSN, COND) \
12660 MIPS_BUILTIN (INSN ## _cond_4s, COND, "any_" #INSN "_" #COND "_4s", \
12661 MIPS_BUILTIN_CMP_ANY, \
12662 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d), \
12663 MIPS_BUILTIN (INSN ## _cond_4s, COND, "all_" #INSN "_" #COND "_4s", \
12664 MIPS_BUILTIN_CMP_ALL, \
12665 MIPS_INT_FTYPE_V2SF_V2SF_V2SF_V2SF, mips3d)
12667 /* Define __builtin_mips_mov{t,f}_<INSN>_<COND>_ps. The comparison
12668 instruction requires mips_builtin_avail_<AVAIL>. */
12669 #define MOVTF_BUILTINS(INSN, COND, AVAIL) \
12670 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movt_" #INSN "_" #COND "_ps", \
12671 MIPS_BUILTIN_MOVT, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12673 MIPS_BUILTIN (INSN ## _cond_ps, COND, "movf_" #INSN "_" #COND "_ps", \
12674 MIPS_BUILTIN_MOVF, MIPS_V2SF_FTYPE_V2SF_V2SF_V2SF_V2SF, \
12677 /* Define all the built-in functions related to C.cond.fmt condition COND. */
12678 #define CMP_BUILTINS(COND) \
12679 MOVTF_BUILTINS (c, COND, paired_single), \
12680 MOVTF_BUILTINS (cabs, COND, mips3d), \
12681 CMP_SCALAR_BUILTINS (cabs, COND, mips3d), \
12682 CMP_PS_BUILTINS (c, COND, paired_single), \
12683 CMP_PS_BUILTINS (cabs, COND, mips3d), \
12684 CMP_4S_BUILTINS (c, COND), \
12685 CMP_4S_BUILTINS (cabs, COND)
12687 /* Define __builtin_mips_<INSN>, which is a MIPS_BUILTIN_DIRECT_NO_TARGET
12688 function mapped to instruction CODE_FOR_mips_<INSN>, FUNCTION_TYPE
12689 and AVAIL are as for MIPS_BUILTIN. */
12690 #define DIRECT_NO_TARGET_BUILTIN(INSN, FUNCTION_TYPE, AVAIL) \
12691 MIPS_BUILTIN (INSN, f, #INSN, MIPS_BUILTIN_DIRECT_NO_TARGET, \
12692 FUNCTION_TYPE, AVAIL)
12694 /* Define __builtin_mips_bposge<VALUE>. <VALUE> is 32 for the MIPS32 DSP
12695 branch instruction. AVAIL is as for MIPS_BUILTIN. */
12696 #define BPOSGE_BUILTIN(VALUE, AVAIL) \
12697 MIPS_BUILTIN (bposge, f, "bposge" #VALUE, \
12698 MIPS_BUILTIN_BPOSGE ## VALUE, MIPS_SI_FTYPE_VOID, AVAIL)
12700 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<FN_NAME>
12701 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12702 builtin_description field. */
12703 #define LOONGSON_BUILTIN_ALIAS(INSN, FN_NAME, FUNCTION_TYPE) \
12704 { CODE_FOR_loongson_ ## INSN, MIPS_FP_COND_f, \
12705 "__builtin_loongson_" #FN_NAME, MIPS_BUILTIN_DIRECT, \
12706 FUNCTION_TYPE, mips_builtin_avail_loongson }
12708 /* Define a Loongson MIPS_BUILTIN_DIRECT function __builtin_loongson_<INSN>
12709 for instruction CODE_FOR_loongson_<INSN>. FUNCTION_TYPE is a
12710 builtin_description field. */
12711 #define LOONGSON_BUILTIN(INSN, FUNCTION_TYPE) \
12712 LOONGSON_BUILTIN_ALIAS (INSN, INSN, FUNCTION_TYPE)
12714 /* Like LOONGSON_BUILTIN, but add _<SUFFIX> to the end of the function name.
12715 We use functions of this form when the same insn can be usefully applied
12716 to more than one datatype. */
12717 #define LOONGSON_BUILTIN_SUFFIX(INSN, SUFFIX, FUNCTION_TYPE) \
12718 LOONGSON_BUILTIN_ALIAS (INSN, INSN ## _ ## SUFFIX, FUNCTION_TYPE)
12720 #define CODE_FOR_mips_sqrt_ps CODE_FOR_sqrtv2sf2
12721 #define CODE_FOR_mips_addq_ph CODE_FOR_addv2hi3
12722 #define CODE_FOR_mips_addu_qb CODE_FOR_addv4qi3
12723 #define CODE_FOR_mips_subq_ph CODE_FOR_subv2hi3
12724 #define CODE_FOR_mips_subu_qb CODE_FOR_subv4qi3
12725 #define CODE_FOR_mips_mul_ph CODE_FOR_mulv2hi3
12726 #define CODE_FOR_mips_mult CODE_FOR_mulsidi3_32bit
12727 #define CODE_FOR_mips_multu CODE_FOR_umulsidi3_32bit
12729 #define CODE_FOR_loongson_packsswh CODE_FOR_vec_pack_ssat_v2si
12730 #define CODE_FOR_loongson_packsshb CODE_FOR_vec_pack_ssat_v4hi
12731 #define CODE_FOR_loongson_packushb CODE_FOR_vec_pack_usat_v4hi
12732 #define CODE_FOR_loongson_paddw CODE_FOR_addv2si3
12733 #define CODE_FOR_loongson_paddh CODE_FOR_addv4hi3
12734 #define CODE_FOR_loongson_paddb CODE_FOR_addv8qi3
12735 #define CODE_FOR_loongson_paddsh CODE_FOR_ssaddv4hi3
12736 #define CODE_FOR_loongson_paddsb CODE_FOR_ssaddv8qi3
12737 #define CODE_FOR_loongson_paddush CODE_FOR_usaddv4hi3
12738 #define CODE_FOR_loongson_paddusb CODE_FOR_usaddv8qi3
12739 #define CODE_FOR_loongson_pmaxsh CODE_FOR_smaxv4hi3
12740 #define CODE_FOR_loongson_pmaxub CODE_FOR_umaxv8qi3
12741 #define CODE_FOR_loongson_pminsh CODE_FOR_sminv4hi3
12742 #define CODE_FOR_loongson_pminub CODE_FOR_uminv8qi3
12743 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
12744 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
12745 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
12746 #define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
12747 #define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
12748 #define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
12749 #define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
12750 #define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
12751 #define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
12752 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
12753 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
12754 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3
12755 #define CODE_FOR_loongson_psubsh CODE_FOR_sssubv4hi3
12756 #define CODE_FOR_loongson_psubsb CODE_FOR_sssubv8qi3
12757 #define CODE_FOR_loongson_psubush CODE_FOR_ussubv4hi3
12758 #define CODE_FOR_loongson_psubusb CODE_FOR_ussubv8qi3
12759 #define CODE_FOR_loongson_punpckhbh CODE_FOR_vec_interleave_highv8qi
12760 #define CODE_FOR_loongson_punpckhhw CODE_FOR_vec_interleave_highv4hi
12761 #define CODE_FOR_loongson_punpckhwd CODE_FOR_vec_interleave_highv2si
12762 #define CODE_FOR_loongson_punpcklbh CODE_FOR_vec_interleave_lowv8qi
12763 #define CODE_FOR_loongson_punpcklhw CODE_FOR_vec_interleave_lowv4hi
12764 #define CODE_FOR_loongson_punpcklwd CODE_FOR_vec_interleave_lowv2si
12766 static const struct mips_builtin_description mips_builtins
[] = {
12767 DIRECT_BUILTIN (pll_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12768 DIRECT_BUILTIN (pul_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12769 DIRECT_BUILTIN (plu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12770 DIRECT_BUILTIN (puu_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, paired_single
),
12771 DIRECT_BUILTIN (cvt_ps_s
, MIPS_V2SF_FTYPE_SF_SF
, paired_single
),
12772 DIRECT_BUILTIN (cvt_s_pl
, MIPS_SF_FTYPE_V2SF
, paired_single
),
12773 DIRECT_BUILTIN (cvt_s_pu
, MIPS_SF_FTYPE_V2SF
, paired_single
),
12774 DIRECT_BUILTIN (abs_ps
, MIPS_V2SF_FTYPE_V2SF
, paired_single
),
12776 DIRECT_BUILTIN (alnv_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF_INT
, paired_single
),
12777 DIRECT_BUILTIN (addr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12778 DIRECT_BUILTIN (mulr_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12779 DIRECT_BUILTIN (cvt_pw_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12780 DIRECT_BUILTIN (cvt_ps_pw
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12782 DIRECT_BUILTIN (recip1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
12783 DIRECT_BUILTIN (recip1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
12784 DIRECT_BUILTIN (recip1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12785 DIRECT_BUILTIN (recip2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
12786 DIRECT_BUILTIN (recip2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
12787 DIRECT_BUILTIN (recip2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12789 DIRECT_BUILTIN (rsqrt1_s
, MIPS_SF_FTYPE_SF
, mips3d
),
12790 DIRECT_BUILTIN (rsqrt1_d
, MIPS_DF_FTYPE_DF
, mips3d
),
12791 DIRECT_BUILTIN (rsqrt1_ps
, MIPS_V2SF_FTYPE_V2SF
, mips3d
),
12792 DIRECT_BUILTIN (rsqrt2_s
, MIPS_SF_FTYPE_SF_SF
, mips3d
),
12793 DIRECT_BUILTIN (rsqrt2_d
, MIPS_DF_FTYPE_DF_DF
, mips3d
),
12794 DIRECT_BUILTIN (rsqrt2_ps
, MIPS_V2SF_FTYPE_V2SF_V2SF
, mips3d
),
12796 MIPS_FP_CONDITIONS (CMP_BUILTINS
),
12798 /* Built-in functions for the SB-1 processor. */
12799 DIRECT_BUILTIN (sqrt_ps
, MIPS_V2SF_FTYPE_V2SF
, sb1_paired_single
),
12801 /* Built-in functions for the DSP ASE (32-bit and 64-bit). */
12802 DIRECT_BUILTIN (addq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12803 DIRECT_BUILTIN (addq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12804 DIRECT_BUILTIN (addq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12805 DIRECT_BUILTIN (addu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12806 DIRECT_BUILTIN (addu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12807 DIRECT_BUILTIN (subq_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12808 DIRECT_BUILTIN (subq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12809 DIRECT_BUILTIN (subq_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12810 DIRECT_BUILTIN (subu_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12811 DIRECT_BUILTIN (subu_s_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12812 DIRECT_BUILTIN (addsc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12813 DIRECT_BUILTIN (addwc
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12814 DIRECT_BUILTIN (modsub
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12815 DIRECT_BUILTIN (raddu_w_qb
, MIPS_SI_FTYPE_V4QI
, dsp
),
12816 DIRECT_BUILTIN (absq_s_ph
, MIPS_V2HI_FTYPE_V2HI
, dsp
),
12817 DIRECT_BUILTIN (absq_s_w
, MIPS_SI_FTYPE_SI
, dsp
),
12818 DIRECT_BUILTIN (precrq_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
12819 DIRECT_BUILTIN (precrq_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
12820 DIRECT_BUILTIN (precrq_rs_ph_w
, MIPS_V2HI_FTYPE_SI_SI
, dsp
),
12821 DIRECT_BUILTIN (precrqu_s_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dsp
),
12822 DIRECT_BUILTIN (preceq_w_phl
, MIPS_SI_FTYPE_V2HI
, dsp
),
12823 DIRECT_BUILTIN (preceq_w_phr
, MIPS_SI_FTYPE_V2HI
, dsp
),
12824 DIRECT_BUILTIN (precequ_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12825 DIRECT_BUILTIN (precequ_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12826 DIRECT_BUILTIN (precequ_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12827 DIRECT_BUILTIN (precequ_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12828 DIRECT_BUILTIN (preceu_ph_qbl
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12829 DIRECT_BUILTIN (preceu_ph_qbr
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12830 DIRECT_BUILTIN (preceu_ph_qbla
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12831 DIRECT_BUILTIN (preceu_ph_qbra
, MIPS_V2HI_FTYPE_V4QI
, dsp
),
12832 DIRECT_BUILTIN (shll_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
12833 DIRECT_BUILTIN (shll_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12834 DIRECT_BUILTIN (shll_s_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12835 DIRECT_BUILTIN (shll_s_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12836 DIRECT_BUILTIN (shrl_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dsp
),
12837 DIRECT_BUILTIN (shra_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12838 DIRECT_BUILTIN (shra_r_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dsp
),
12839 DIRECT_BUILTIN (shra_r_w
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12840 DIRECT_BUILTIN (muleu_s_ph_qbl
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
12841 DIRECT_BUILTIN (muleu_s_ph_qbr
, MIPS_V2HI_FTYPE_V4QI_V2HI
, dsp
),
12842 DIRECT_BUILTIN (mulq_rs_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12843 DIRECT_BUILTIN (muleq_s_w_phl
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
12844 DIRECT_BUILTIN (muleq_s_w_phr
, MIPS_SI_FTYPE_V2HI_V2HI
, dsp
),
12845 DIRECT_BUILTIN (bitrev
, MIPS_SI_FTYPE_SI
, dsp
),
12846 DIRECT_BUILTIN (insv
, MIPS_SI_FTYPE_SI_SI
, dsp
),
12847 DIRECT_BUILTIN (repl_qb
, MIPS_V4QI_FTYPE_SI
, dsp
),
12848 DIRECT_BUILTIN (repl_ph
, MIPS_V2HI_FTYPE_SI
, dsp
),
12849 DIRECT_NO_TARGET_BUILTIN (cmpu_eq_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12850 DIRECT_NO_TARGET_BUILTIN (cmpu_lt_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12851 DIRECT_NO_TARGET_BUILTIN (cmpu_le_qb
, MIPS_VOID_FTYPE_V4QI_V4QI
, dsp
),
12852 DIRECT_BUILTIN (cmpgu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12853 DIRECT_BUILTIN (cmpgu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12854 DIRECT_BUILTIN (cmpgu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dsp
),
12855 DIRECT_NO_TARGET_BUILTIN (cmp_eq_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12856 DIRECT_NO_TARGET_BUILTIN (cmp_lt_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12857 DIRECT_NO_TARGET_BUILTIN (cmp_le_ph
, MIPS_VOID_FTYPE_V2HI_V2HI
, dsp
),
12858 DIRECT_BUILTIN (pick_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dsp
),
12859 DIRECT_BUILTIN (pick_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12860 DIRECT_BUILTIN (packrl_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dsp
),
12861 DIRECT_NO_TARGET_BUILTIN (wrdsp
, MIPS_VOID_FTYPE_SI_SI
, dsp
),
12862 DIRECT_BUILTIN (rddsp
, MIPS_SI_FTYPE_SI
, dsp
),
12863 DIRECT_BUILTIN (lbux
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12864 DIRECT_BUILTIN (lhx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12865 DIRECT_BUILTIN (lwx
, MIPS_SI_FTYPE_POINTER_SI
, dsp
),
12866 BPOSGE_BUILTIN (32, dsp
),
12868 /* The following are for the MIPS DSP ASE REV 2 (32-bit and 64-bit). */
12869 DIRECT_BUILTIN (absq_s_qb
, MIPS_V4QI_FTYPE_V4QI
, dspr2
),
12870 DIRECT_BUILTIN (addu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12871 DIRECT_BUILTIN (addu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12872 DIRECT_BUILTIN (adduh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12873 DIRECT_BUILTIN (adduh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12874 DIRECT_BUILTIN (append
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12875 DIRECT_BUILTIN (balign
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12876 DIRECT_BUILTIN (cmpgdu_eq_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12877 DIRECT_BUILTIN (cmpgdu_lt_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12878 DIRECT_BUILTIN (cmpgdu_le_qb
, MIPS_SI_FTYPE_V4QI_V4QI
, dspr2
),
12879 DIRECT_BUILTIN (mul_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12880 DIRECT_BUILTIN (mul_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12881 DIRECT_BUILTIN (mulq_rs_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12882 DIRECT_BUILTIN (mulq_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12883 DIRECT_BUILTIN (mulq_s_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12884 DIRECT_BUILTIN (precr_qb_ph
, MIPS_V4QI_FTYPE_V2HI_V2HI
, dspr2
),
12885 DIRECT_BUILTIN (precr_sra_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
12886 DIRECT_BUILTIN (precr_sra_r_ph_w
, MIPS_V2HI_FTYPE_SI_SI_SI
, dspr2
),
12887 DIRECT_BUILTIN (prepend
, MIPS_SI_FTYPE_SI_SI_SI
, dspr2
),
12888 DIRECT_BUILTIN (shra_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
12889 DIRECT_BUILTIN (shra_r_qb
, MIPS_V4QI_FTYPE_V4QI_SI
, dspr2
),
12890 DIRECT_BUILTIN (shrl_ph
, MIPS_V2HI_FTYPE_V2HI_SI
, dspr2
),
12891 DIRECT_BUILTIN (subu_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12892 DIRECT_BUILTIN (subu_s_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12893 DIRECT_BUILTIN (subuh_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12894 DIRECT_BUILTIN (subuh_r_qb
, MIPS_V4QI_FTYPE_V4QI_V4QI
, dspr2
),
12895 DIRECT_BUILTIN (addqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12896 DIRECT_BUILTIN (addqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12897 DIRECT_BUILTIN (addqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12898 DIRECT_BUILTIN (addqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12899 DIRECT_BUILTIN (subqh_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12900 DIRECT_BUILTIN (subqh_r_ph
, MIPS_V2HI_FTYPE_V2HI_V2HI
, dspr2
),
12901 DIRECT_BUILTIN (subqh_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12902 DIRECT_BUILTIN (subqh_r_w
, MIPS_SI_FTYPE_SI_SI
, dspr2
),
12904 /* Built-in functions for the DSP ASE (32-bit only). */
12905 DIRECT_BUILTIN (dpau_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12906 DIRECT_BUILTIN (dpau_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12907 DIRECT_BUILTIN (dpsu_h_qbl
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12908 DIRECT_BUILTIN (dpsu_h_qbr
, MIPS_DI_FTYPE_DI_V4QI_V4QI
, dsp_32
),
12909 DIRECT_BUILTIN (dpaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12910 DIRECT_BUILTIN (dpsq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12911 DIRECT_BUILTIN (mulsaq_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12912 DIRECT_BUILTIN (dpaq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12913 DIRECT_BUILTIN (dpsq_sa_l_w
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12914 DIRECT_BUILTIN (maq_s_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12915 DIRECT_BUILTIN (maq_s_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12916 DIRECT_BUILTIN (maq_sa_w_phl
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12917 DIRECT_BUILTIN (maq_sa_w_phr
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dsp_32
),
12918 DIRECT_BUILTIN (extr_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12919 DIRECT_BUILTIN (extr_r_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12920 DIRECT_BUILTIN (extr_rs_w
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12921 DIRECT_BUILTIN (extr_s_h
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12922 DIRECT_BUILTIN (extp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12923 DIRECT_BUILTIN (extpdp
, MIPS_SI_FTYPE_DI_SI
, dsp_32
),
12924 DIRECT_BUILTIN (shilo
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
12925 DIRECT_BUILTIN (mthlip
, MIPS_DI_FTYPE_DI_SI
, dsp_32
),
12926 DIRECT_BUILTIN (madd
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12927 DIRECT_BUILTIN (maddu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
12928 DIRECT_BUILTIN (msub
, MIPS_DI_FTYPE_DI_SI_SI
, dsp_32
),
12929 DIRECT_BUILTIN (msubu
, MIPS_DI_FTYPE_DI_USI_USI
, dsp_32
),
12930 DIRECT_BUILTIN (mult
, MIPS_DI_FTYPE_SI_SI
, dsp_32
),
12931 DIRECT_BUILTIN (multu
, MIPS_DI_FTYPE_USI_USI
, dsp_32
),
12933 /* The following are for the MIPS DSP ASE REV 2 (32-bit only). */
12934 DIRECT_BUILTIN (dpa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12935 DIRECT_BUILTIN (dps_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12936 DIRECT_BUILTIN (mulsa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12937 DIRECT_BUILTIN (dpax_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12938 DIRECT_BUILTIN (dpsx_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12939 DIRECT_BUILTIN (dpaqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12940 DIRECT_BUILTIN (dpaqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12941 DIRECT_BUILTIN (dpsqx_s_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12942 DIRECT_BUILTIN (dpsqx_sa_w_ph
, MIPS_DI_FTYPE_DI_V2HI_V2HI
, dspr2_32
),
12944 /* Builtin functions for ST Microelectronics Loongson-2E/2F cores. */
12945 LOONGSON_BUILTIN (packsswh
, MIPS_V4HI_FTYPE_V2SI_V2SI
),
12946 LOONGSON_BUILTIN (packsshb
, MIPS_V8QI_FTYPE_V4HI_V4HI
),
12947 LOONGSON_BUILTIN (packushb
, MIPS_UV8QI_FTYPE_UV4HI_UV4HI
),
12948 LOONGSON_BUILTIN_SUFFIX (paddw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12949 LOONGSON_BUILTIN_SUFFIX (paddh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12950 LOONGSON_BUILTIN_SUFFIX (paddb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12951 LOONGSON_BUILTIN_SUFFIX (paddw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12952 LOONGSON_BUILTIN_SUFFIX (paddh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12953 LOONGSON_BUILTIN_SUFFIX (paddb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12954 LOONGSON_BUILTIN_SUFFIX (paddd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
12955 LOONGSON_BUILTIN_SUFFIX (paddd
, s
, MIPS_DI_FTYPE_DI_DI
),
12956 LOONGSON_BUILTIN (paddsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12957 LOONGSON_BUILTIN (paddsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12958 LOONGSON_BUILTIN (paddush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12959 LOONGSON_BUILTIN (paddusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12960 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_ud
, MIPS_UDI_FTYPE_UDI_UDI
),
12961 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_uw
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12962 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_uh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12963 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_ub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12964 LOONGSON_BUILTIN_ALIAS (pandn_d
, pandn_sd
, MIPS_DI_FTYPE_DI_DI
),
12965 LOONGSON_BUILTIN_ALIAS (pandn_w
, pandn_sw
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12966 LOONGSON_BUILTIN_ALIAS (pandn_h
, pandn_sh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12967 LOONGSON_BUILTIN_ALIAS (pandn_b
, pandn_sb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12968 LOONGSON_BUILTIN (pavgh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12969 LOONGSON_BUILTIN (pavgb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12970 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12971 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12972 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12973 LOONGSON_BUILTIN_SUFFIX (pcmpeqw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12974 LOONGSON_BUILTIN_SUFFIX (pcmpeqh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12975 LOONGSON_BUILTIN_SUFFIX (pcmpeqb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12976 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
12977 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12978 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12979 LOONGSON_BUILTIN_SUFFIX (pcmpgtw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
12980 LOONGSON_BUILTIN_SUFFIX (pcmpgth
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12981 LOONGSON_BUILTIN_SUFFIX (pcmpgtb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
12982 LOONGSON_BUILTIN_SUFFIX (pextrh
, u
, MIPS_UV4HI_FTYPE_UV4HI_USI
),
12983 LOONGSON_BUILTIN_SUFFIX (pextrh
, s
, MIPS_V4HI_FTYPE_V4HI_USI
),
12984 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12985 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12986 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12987 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
12988 LOONGSON_BUILTIN_SUFFIX (pinsrh_0
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12989 LOONGSON_BUILTIN_SUFFIX (pinsrh_1
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12990 LOONGSON_BUILTIN_SUFFIX (pinsrh_2
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12991 LOONGSON_BUILTIN_SUFFIX (pinsrh_3
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12992 LOONGSON_BUILTIN (pmaddhw
, MIPS_V2SI_FTYPE_V4HI_V4HI
),
12993 LOONGSON_BUILTIN (pmaxsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12994 LOONGSON_BUILTIN (pmaxub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12995 LOONGSON_BUILTIN (pminsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
12996 LOONGSON_BUILTIN (pminub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
12997 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, u
, MIPS_UV8QI_FTYPE_UV8QI
),
12998 LOONGSON_BUILTIN_SUFFIX (pmovmskb
, s
, MIPS_V8QI_FTYPE_V8QI
),
12999 LOONGSON_BUILTIN (pmulhuh
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13000 LOONGSON_BUILTIN (pmulhh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13001 LOONGSON_BUILTIN (pmullh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13002 LOONGSON_BUILTIN (pmuluw
, MIPS_UDI_FTYPE_UV2SI_UV2SI
),
13003 LOONGSON_BUILTIN (pasubub
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13004 LOONGSON_BUILTIN (biadd
, MIPS_UV4HI_FTYPE_UV8QI
),
13005 LOONGSON_BUILTIN (psadbh
, MIPS_UV4HI_FTYPE_UV8QI_UV8QI
),
13006 LOONGSON_BUILTIN_SUFFIX (pshufh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI_UQI
),
13007 LOONGSON_BUILTIN_SUFFIX (pshufh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI_UQI
),
13008 LOONGSON_BUILTIN_SUFFIX (psllh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13009 LOONGSON_BUILTIN_SUFFIX (psllh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13010 LOONGSON_BUILTIN_SUFFIX (psllw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13011 LOONGSON_BUILTIN_SUFFIX (psllw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13012 LOONGSON_BUILTIN_SUFFIX (psrah
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13013 LOONGSON_BUILTIN_SUFFIX (psrah
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13014 LOONGSON_BUILTIN_SUFFIX (psraw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13015 LOONGSON_BUILTIN_SUFFIX (psraw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13016 LOONGSON_BUILTIN_SUFFIX (psrlh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UQI
),
13017 LOONGSON_BUILTIN_SUFFIX (psrlh
, s
, MIPS_V4HI_FTYPE_V4HI_UQI
),
13018 LOONGSON_BUILTIN_SUFFIX (psrlw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UQI
),
13019 LOONGSON_BUILTIN_SUFFIX (psrlw
, s
, MIPS_V2SI_FTYPE_V2SI_UQI
),
13020 LOONGSON_BUILTIN_SUFFIX (psubw
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13021 LOONGSON_BUILTIN_SUFFIX (psubh
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13022 LOONGSON_BUILTIN_SUFFIX (psubb
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13023 LOONGSON_BUILTIN_SUFFIX (psubw
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13024 LOONGSON_BUILTIN_SUFFIX (psubh
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13025 LOONGSON_BUILTIN_SUFFIX (psubb
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13026 LOONGSON_BUILTIN_SUFFIX (psubd
, u
, MIPS_UDI_FTYPE_UDI_UDI
),
13027 LOONGSON_BUILTIN_SUFFIX (psubd
, s
, MIPS_DI_FTYPE_DI_DI
),
13028 LOONGSON_BUILTIN (psubsh
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13029 LOONGSON_BUILTIN (psubsb
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13030 LOONGSON_BUILTIN (psubush
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13031 LOONGSON_BUILTIN (psubusb
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13032 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13033 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13034 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13035 LOONGSON_BUILTIN_SUFFIX (punpckhbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13036 LOONGSON_BUILTIN_SUFFIX (punpckhhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13037 LOONGSON_BUILTIN_SUFFIX (punpckhwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13038 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, u
, MIPS_UV8QI_FTYPE_UV8QI_UV8QI
),
13039 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, u
, MIPS_UV4HI_FTYPE_UV4HI_UV4HI
),
13040 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, u
, MIPS_UV2SI_FTYPE_UV2SI_UV2SI
),
13041 LOONGSON_BUILTIN_SUFFIX (punpcklbh
, s
, MIPS_V8QI_FTYPE_V8QI_V8QI
),
13042 LOONGSON_BUILTIN_SUFFIX (punpcklhw
, s
, MIPS_V4HI_FTYPE_V4HI_V4HI
),
13043 LOONGSON_BUILTIN_SUFFIX (punpcklwd
, s
, MIPS_V2SI_FTYPE_V2SI_V2SI
),
13045 /* Sundry other built-in functions. */
13046 DIRECT_NO_TARGET_BUILTIN (cache
, MIPS_VOID_FTYPE_SI_CVPOINTER
, cache
)
13049 /* Index I is the function declaration for mips_builtins[I], or null if the
13050 function isn't defined on this target. */
13051 static GTY(()) tree mips_builtin_decls
[ARRAY_SIZE (mips_builtins
)];
13053 /* MODE is a vector mode whose elements have type TYPE. Return the type
13054 of the vector itself. */
13057 mips_builtin_vector_type (tree type
, enum machine_mode mode
)
13059 static tree types
[2 * (int) MAX_MACHINE_MODE
];
13062 mode_index
= (int) mode
;
13064 if (TREE_CODE (type
) == INTEGER_TYPE
&& TYPE_UNSIGNED (type
))
13065 mode_index
+= MAX_MACHINE_MODE
;
13067 if (types
[mode_index
] == NULL_TREE
)
13068 types
[mode_index
] = build_vector_type_for_mode (type
, mode
);
13069 return types
[mode_index
];
13072 /* Return a type for 'const volatile void *'. */
13075 mips_build_cvpointer_type (void)
13079 if (cache
== NULL_TREE
)
13080 cache
= build_pointer_type (build_qualified_type
13082 TYPE_QUAL_CONST
| TYPE_QUAL_VOLATILE
));
13086 /* Source-level argument types. */
13087 #define MIPS_ATYPE_VOID void_type_node
13088 #define MIPS_ATYPE_INT integer_type_node
13089 #define MIPS_ATYPE_POINTER ptr_type_node
13090 #define MIPS_ATYPE_CVPOINTER mips_build_cvpointer_type ()
13092 /* Standard mode-based argument types. */
13093 #define MIPS_ATYPE_UQI unsigned_intQI_type_node
13094 #define MIPS_ATYPE_SI intSI_type_node
13095 #define MIPS_ATYPE_USI unsigned_intSI_type_node
13096 #define MIPS_ATYPE_DI intDI_type_node
13097 #define MIPS_ATYPE_UDI unsigned_intDI_type_node
13098 #define MIPS_ATYPE_SF float_type_node
13099 #define MIPS_ATYPE_DF double_type_node
13101 /* Vector argument types. */
13102 #define MIPS_ATYPE_V2SF mips_builtin_vector_type (float_type_node, V2SFmode)
13103 #define MIPS_ATYPE_V2HI mips_builtin_vector_type (intHI_type_node, V2HImode)
13104 #define MIPS_ATYPE_V2SI mips_builtin_vector_type (intSI_type_node, V2SImode)
13105 #define MIPS_ATYPE_V4QI mips_builtin_vector_type (intQI_type_node, V4QImode)
13106 #define MIPS_ATYPE_V4HI mips_builtin_vector_type (intHI_type_node, V4HImode)
13107 #define MIPS_ATYPE_V8QI mips_builtin_vector_type (intQI_type_node, V8QImode)
13108 #define MIPS_ATYPE_UV2SI \
13109 mips_builtin_vector_type (unsigned_intSI_type_node, V2SImode)
13110 #define MIPS_ATYPE_UV4HI \
13111 mips_builtin_vector_type (unsigned_intHI_type_node, V4HImode)
13112 #define MIPS_ATYPE_UV8QI \
13113 mips_builtin_vector_type (unsigned_intQI_type_node, V8QImode)
13115 /* MIPS_FTYPE_ATYPESN takes N MIPS_FTYPES-like type codes and lists
13116 their associated MIPS_ATYPEs. */
13117 #define MIPS_FTYPE_ATYPES1(A, B) \
13118 MIPS_ATYPE_##A, MIPS_ATYPE_##B
13120 #define MIPS_FTYPE_ATYPES2(A, B, C) \
13121 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C
13123 #define MIPS_FTYPE_ATYPES3(A, B, C, D) \
13124 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D
13126 #define MIPS_FTYPE_ATYPES4(A, B, C, D, E) \
13127 MIPS_ATYPE_##A, MIPS_ATYPE_##B, MIPS_ATYPE_##C, MIPS_ATYPE_##D, \
13130 /* Return the function type associated with function prototype TYPE. */
13133 mips_build_function_type (enum mips_function_type type
)
13135 static tree types
[(int) MIPS_MAX_FTYPE_MAX
];
13137 if (types
[(int) type
] == NULL_TREE
)
13140 #define DEF_MIPS_FTYPE(NUM, ARGS) \
13141 case MIPS_FTYPE_NAME##NUM ARGS: \
13142 types[(int) type] \
13143 = build_function_type_list (MIPS_FTYPE_ATYPES##NUM ARGS, \
13146 #include "config/mips/mips-ftypes.def"
13147 #undef DEF_MIPS_FTYPE
13149 gcc_unreachable ();
13152 return types
[(int) type
];
13155 /* Implement TARGET_INIT_BUILTINS. */
13158 mips_init_builtins (void)
13160 const struct mips_builtin_description
*d
;
13163 /* Iterate through all of the bdesc arrays, initializing all of the
13164 builtin functions. */
13165 for (i
= 0; i
< ARRAY_SIZE (mips_builtins
); i
++)
13167 d
= &mips_builtins
[i
];
13169 mips_builtin_decls
[i
]
13170 = add_builtin_function (d
->name
,
13171 mips_build_function_type (d
->function_type
),
13172 i
, BUILT_IN_MD
, NULL
, NULL
);
13176 /* Implement TARGET_BUILTIN_DECL. */
13179 mips_builtin_decl (unsigned int code
, bool initialize_p ATTRIBUTE_UNUSED
)
13181 if (code
>= ARRAY_SIZE (mips_builtins
))
13182 return error_mark_node
;
13183 return mips_builtin_decls
[code
];
13186 /* Take argument ARGNO from EXP's argument list and convert it into a
13187 form suitable for input operand OPNO of instruction ICODE. Return the
13191 mips_prepare_builtin_arg (enum insn_code icode
,
13192 unsigned int opno
, tree exp
, unsigned int argno
)
13196 enum machine_mode mode
;
13198 arg
= CALL_EXPR_ARG (exp
, argno
);
13199 value
= expand_normal (arg
);
13200 mode
= insn_data
[icode
].operand
[opno
].mode
;
13201 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
13203 /* We need to get the mode from ARG for two reasons:
13205 - to cope with address operands, where MODE is the mode of the
13206 memory, rather than of VALUE itself.
13208 - to cope with special predicates like pmode_register_operand,
13209 where MODE is VOIDmode. */
13210 value
= copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg
)), value
);
13212 /* Check the predicate again. */
13213 if (!insn_data
[icode
].operand
[opno
].predicate (value
, mode
))
13215 error ("invalid argument to built-in function");
13223 /* Return an rtx suitable for output operand OP of instruction ICODE.
13224 If TARGET is non-null, try to use it where possible. */
13227 mips_prepare_builtin_target (enum insn_code icode
, unsigned int op
, rtx target
)
13229 enum machine_mode mode
;
13231 mode
= insn_data
[icode
].operand
[op
].mode
;
13232 if (target
== 0 || !insn_data
[icode
].operand
[op
].predicate (target
, mode
))
13233 target
= gen_reg_rtx (mode
);
13238 /* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
13239 HAS_TARGET_P says which. EXP is the CALL_EXPR that calls the function
13240 and ICODE is the code of the associated .md pattern. TARGET, if nonnull,
13241 suggests a good place to put the result. */
13244 mips_expand_builtin_direct (enum insn_code icode
, rtx target
, tree exp
,
13247 rtx ops
[MAX_RECOG_OPERANDS
];
13250 /* Map any target to operand 0. */
13254 target
= mips_prepare_builtin_target (icode
, opno
, target
);
13255 ops
[opno
] = target
;
13259 /* Map the arguments to the other operands. The n_operands value
13260 for an expander includes match_dups and match_scratches as well as
13261 match_operands, so n_operands is only an upper bound on the number
13262 of arguments to the expander function. */
13263 gcc_assert (opno
+ call_expr_nargs (exp
) <= insn_data
[icode
].n_operands
);
13264 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++, opno
++)
13265 ops
[opno
] = mips_prepare_builtin_arg (icode
, opno
, exp
, argno
);
13270 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1]));
13274 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2]));
13278 emit_insn (GEN_FCN (icode
) (ops
[0], ops
[1], ops
[2], ops
[3]));
13282 gcc_unreachable ();
13287 /* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
13288 function; TYPE says which. EXP is the CALL_EXPR that calls the
13289 function, ICODE is the instruction that should be used to compare
13290 the first two arguments, and COND is the condition it should test.
13291 TARGET, if nonnull, suggests a good place to put the result. */
13294 mips_expand_builtin_movtf (enum mips_builtin_type type
,
13295 enum insn_code icode
, enum mips_fp_condition cond
,
13296 rtx target
, tree exp
)
13298 rtx cmp_result
, op0
, op1
;
13300 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
13301 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 0);
13302 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 1);
13303 emit_insn (GEN_FCN (icode
) (cmp_result
, op0
, op1
, GEN_INT (cond
)));
13305 icode
= CODE_FOR_mips_cond_move_tf_ps
;
13306 target
= mips_prepare_builtin_target (icode
, 0, target
);
13307 if (type
== MIPS_BUILTIN_MOVT
)
13309 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 2);
13310 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 3);
13314 op0
= mips_prepare_builtin_arg (icode
, 1, exp
, 2);
13315 op1
= mips_prepare_builtin_arg (icode
, 2, exp
, 3);
13317 emit_insn (gen_mips_cond_move_tf_ps (target
, op0
, op1
, cmp_result
));
13321 /* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
13322 into TARGET otherwise. Return TARGET. */
13325 mips_builtin_branch_and_move (rtx condition
, rtx target
,
13326 rtx value_if_true
, rtx value_if_false
)
13328 rtx true_label
, done_label
;
13330 true_label
= gen_label_rtx ();
13331 done_label
= gen_label_rtx ();
13333 /* First assume that CONDITION is false. */
13334 mips_emit_move (target
, value_if_false
);
13336 /* Branch to TRUE_LABEL if CONDITION is true and DONE_LABEL otherwise. */
13337 emit_jump_insn (gen_condjump (condition
, true_label
));
13338 emit_jump_insn (gen_jump (done_label
));
13341 /* Fix TARGET if CONDITION is true. */
13342 emit_label (true_label
);
13343 mips_emit_move (target
, value_if_true
);
13345 emit_label (done_label
);
13349 /* Expand a comparison built-in function of type BUILTIN_TYPE. EXP is
13350 the CALL_EXPR that calls the function, ICODE is the code of the
13351 comparison instruction, and COND is the condition it should test.
13352 TARGET, if nonnull, suggests a good place to put the boolean result. */
13355 mips_expand_builtin_compare (enum mips_builtin_type builtin_type
,
13356 enum insn_code icode
, enum mips_fp_condition cond
,
13357 rtx target
, tree exp
)
13359 rtx offset
, condition
, cmp_result
, args
[MAX_RECOG_OPERANDS
];
13362 if (target
== 0 || GET_MODE (target
) != SImode
)
13363 target
= gen_reg_rtx (SImode
);
13365 /* The instruction should have a target operand, an operand for each
13366 argument, and an operand for COND. */
13367 gcc_assert (call_expr_nargs (exp
) + 2 == insn_data
[icode
].n_operands
);
13369 /* Prepare the operands to the comparison. */
13370 cmp_result
= mips_prepare_builtin_target (icode
, 0, 0);
13371 for (argno
= 0; argno
< call_expr_nargs (exp
); argno
++)
13372 args
[argno
] = mips_prepare_builtin_arg (icode
, argno
+ 1, exp
, argno
);
13374 switch (insn_data
[icode
].n_operands
)
13377 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
13382 emit_insn (GEN_FCN (icode
) (cmp_result
, args
[0], args
[1],
13383 args
[2], args
[3], GEN_INT (cond
)));
13387 gcc_unreachable ();
13390 /* If the comparison sets more than one register, we define the result
13391 to be 0 if all registers are false and -1 if all registers are true.
13392 The value of the complete result is indeterminate otherwise. */
13393 switch (builtin_type
)
13395 case MIPS_BUILTIN_CMP_ALL
:
13396 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, constm1_rtx
);
13397 return mips_builtin_branch_and_move (condition
, target
,
13398 const0_rtx
, const1_rtx
);
13400 case MIPS_BUILTIN_CMP_UPPER
:
13401 case MIPS_BUILTIN_CMP_LOWER
:
13402 offset
= GEN_INT (builtin_type
== MIPS_BUILTIN_CMP_UPPER
);
13403 condition
= gen_single_cc (cmp_result
, offset
);
13404 return mips_builtin_branch_and_move (condition
, target
,
13405 const1_rtx
, const0_rtx
);
13408 condition
= gen_rtx_NE (VOIDmode
, cmp_result
, const0_rtx
);
13409 return mips_builtin_branch_and_move (condition
, target
,
13410 const1_rtx
, const0_rtx
);
13414 /* Expand a bposge built-in function of type BUILTIN_TYPE. TARGET,
13415 if nonnull, suggests a good place to put the boolean result. */
13418 mips_expand_builtin_bposge (enum mips_builtin_type builtin_type
, rtx target
)
13420 rtx condition
, cmp_result
;
13423 if (target
== 0 || GET_MODE (target
) != SImode
)
13424 target
= gen_reg_rtx (SImode
);
13426 cmp_result
= gen_rtx_REG (CCDSPmode
, CCDSP_PO_REGNUM
);
13428 if (builtin_type
== MIPS_BUILTIN_BPOSGE32
)
13433 condition
= gen_rtx_GE (VOIDmode
, cmp_result
, GEN_INT (cmp_value
));
13434 return mips_builtin_branch_and_move (condition
, target
,
13435 const1_rtx
, const0_rtx
);
13438 /* Implement TARGET_EXPAND_BUILTIN. */
13441 mips_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13442 enum machine_mode mode
, int ignore
)
13445 unsigned int fcode
, avail
;
13446 const struct mips_builtin_description
*d
;
13448 fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13449 fcode
= DECL_FUNCTION_CODE (fndecl
);
13450 gcc_assert (fcode
< ARRAY_SIZE (mips_builtins
));
13451 d
= &mips_builtins
[fcode
];
13452 avail
= d
->avail ();
13453 gcc_assert (avail
!= 0);
13456 error ("built-in function %qE not supported for MIPS16",
13457 DECL_NAME (fndecl
));
13458 return ignore
? const0_rtx
: CONST0_RTX (mode
);
13460 switch (d
->builtin_type
)
13462 case MIPS_BUILTIN_DIRECT
:
13463 return mips_expand_builtin_direct (d
->icode
, target
, exp
, true);
13465 case MIPS_BUILTIN_DIRECT_NO_TARGET
:
13466 return mips_expand_builtin_direct (d
->icode
, target
, exp
, false);
13468 case MIPS_BUILTIN_MOVT
:
13469 case MIPS_BUILTIN_MOVF
:
13470 return mips_expand_builtin_movtf (d
->builtin_type
, d
->icode
,
13471 d
->cond
, target
, exp
);
13473 case MIPS_BUILTIN_CMP_ANY
:
13474 case MIPS_BUILTIN_CMP_ALL
:
13475 case MIPS_BUILTIN_CMP_UPPER
:
13476 case MIPS_BUILTIN_CMP_LOWER
:
13477 case MIPS_BUILTIN_CMP_SINGLE
:
13478 return mips_expand_builtin_compare (d
->builtin_type
, d
->icode
,
13479 d
->cond
, target
, exp
);
13481 case MIPS_BUILTIN_BPOSGE32
:
13482 return mips_expand_builtin_bposge (d
->builtin_type
, target
);
13484 gcc_unreachable ();
13487 /* An entry in the MIPS16 constant pool. VALUE is the pool constant,
13488 MODE is its mode, and LABEL is the CODE_LABEL associated with it. */
13489 struct mips16_constant
{
13490 struct mips16_constant
*next
;
13493 enum machine_mode mode
;
13496 /* Information about an incomplete MIPS16 constant pool. FIRST is the
13497 first constant, HIGHEST_ADDRESS is the highest address that the first
13498 byte of the pool can have, and INSN_ADDRESS is the current instruction
13500 struct mips16_constant_pool
{
13501 struct mips16_constant
*first
;
13502 int highest_address
;
13506 /* Add constant VALUE to POOL and return its label. MODE is the
13507 value's mode (used for CONST_INTs, etc.). */
13510 mips16_add_constant (struct mips16_constant_pool
*pool
,
13511 rtx value
, enum machine_mode mode
)
13513 struct mips16_constant
**p
, *c
;
13514 bool first_of_size_p
;
13516 /* See whether the constant is already in the pool. If so, return the
13517 existing label, otherwise leave P pointing to the place where the
13518 constant should be added.
13520 Keep the pool sorted in increasing order of mode size so that we can
13521 reduce the number of alignments needed. */
13522 first_of_size_p
= true;
13523 for (p
= &pool
->first
; *p
!= 0; p
= &(*p
)->next
)
13525 if (mode
== (*p
)->mode
&& rtx_equal_p (value
, (*p
)->value
))
13526 return (*p
)->label
;
13527 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE ((*p
)->mode
))
13529 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE ((*p
)->mode
))
13530 first_of_size_p
= false;
13533 /* In the worst case, the constant needed by the earliest instruction
13534 will end up at the end of the pool. The entire pool must then be
13535 accessible from that instruction.
13537 When adding the first constant, set the pool's highest address to
13538 the address of the first out-of-range byte. Adjust this address
13539 downwards each time a new constant is added. */
13540 if (pool
->first
== 0)
13541 /* For LWPC, ADDIUPC and DADDIUPC, the base PC value is the address
13542 of the instruction with the lowest two bits clear. The base PC
13543 value for LDPC has the lowest three bits clear. Assume the worst
13544 case here; namely that the PC-relative instruction occupies the
13545 last 2 bytes in an aligned word. */
13546 pool
->highest_address
= pool
->insn_address
- (UNITS_PER_WORD
- 2) + 0x8000;
13547 pool
->highest_address
-= GET_MODE_SIZE (mode
);
13548 if (first_of_size_p
)
13549 /* Take into account the worst possible padding due to alignment. */
13550 pool
->highest_address
-= GET_MODE_SIZE (mode
) - 1;
13552 /* Create a new entry. */
13553 c
= XNEW (struct mips16_constant
);
13556 c
->label
= gen_label_rtx ();
13563 /* Output constant VALUE after instruction INSN and return the last
13564 instruction emitted. MODE is the mode of the constant. */
13567 mips16_emit_constants_1 (enum machine_mode mode
, rtx value
, rtx insn
)
13569 if (SCALAR_INT_MODE_P (mode
) || ALL_SCALAR_FIXED_POINT_MODE_P (mode
))
13571 rtx size
= GEN_INT (GET_MODE_SIZE (mode
));
13572 return emit_insn_after (gen_consttable_int (value
, size
), insn
);
13575 if (SCALAR_FLOAT_MODE_P (mode
))
13576 return emit_insn_after (gen_consttable_float (value
), insn
);
13578 if (VECTOR_MODE_P (mode
))
13582 for (i
= 0; i
< CONST_VECTOR_NUNITS (value
); i
++)
13583 insn
= mips16_emit_constants_1 (GET_MODE_INNER (mode
),
13584 CONST_VECTOR_ELT (value
, i
), insn
);
13588 gcc_unreachable ();
13591 /* Dump out the constants in CONSTANTS after INSN. */
13594 mips16_emit_constants (struct mips16_constant
*constants
, rtx insn
)
13596 struct mips16_constant
*c
, *next
;
13600 for (c
= constants
; c
!= NULL
; c
= next
)
13602 /* If necessary, increase the alignment of PC. */
13603 if (align
< GET_MODE_SIZE (c
->mode
))
13605 int align_log
= floor_log2 (GET_MODE_SIZE (c
->mode
));
13606 insn
= emit_insn_after (gen_align (GEN_INT (align_log
)), insn
);
13608 align
= GET_MODE_SIZE (c
->mode
);
13610 insn
= emit_label_after (c
->label
, insn
);
13611 insn
= mips16_emit_constants_1 (c
->mode
, c
->value
, insn
);
13617 emit_barrier_after (insn
);
13620 /* Return the length of instruction INSN. */
13623 mips16_insn_length (rtx insn
)
13627 rtx body
= PATTERN (insn
);
13628 if (GET_CODE (body
) == ADDR_VEC
)
13629 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 0);
13630 if (GET_CODE (body
) == ADDR_DIFF_VEC
)
13631 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, 1);
13633 return get_attr_length (insn
);
13636 /* If *X is a symbolic constant that refers to the constant pool, add
13637 the constant to POOL and rewrite *X to use the constant's label. */
13640 mips16_rewrite_pool_constant (struct mips16_constant_pool
*pool
, rtx
*x
)
13642 rtx base
, offset
, label
;
13644 split_const (*x
, &base
, &offset
);
13645 if (GET_CODE (base
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base
))
13647 label
= mips16_add_constant (pool
, get_pool_constant (base
),
13648 get_pool_mode (base
));
13649 base
= gen_rtx_LABEL_REF (Pmode
, label
);
13650 *x
= mips_unspec_address_offset (base
, offset
, SYMBOL_PC_RELATIVE
);
13654 /* This structure is used to communicate with mips16_rewrite_pool_refs.
13655 INSN is the instruction we're rewriting and POOL points to the current
13657 struct mips16_rewrite_pool_refs_info
{
13659 struct mips16_constant_pool
*pool
;
13662 /* Rewrite *X so that constant pool references refer to the constant's
13663 label instead. DATA points to a mips16_rewrite_pool_refs_info
13667 mips16_rewrite_pool_refs (rtx
*x
, void *data
)
13669 struct mips16_rewrite_pool_refs_info
*info
=
13670 (struct mips16_rewrite_pool_refs_info
*) data
;
13672 if (force_to_mem_operand (*x
, Pmode
))
13674 rtx mem
= force_const_mem (GET_MODE (*x
), *x
);
13675 validate_change (info
->insn
, x
, mem
, false);
13680 mips16_rewrite_pool_constant (info
->pool
, &XEXP (*x
, 0));
13684 if (TARGET_MIPS16_TEXT_LOADS
)
13685 mips16_rewrite_pool_constant (info
->pool
, x
);
13687 return GET_CODE (*x
) == CONST
? -1 : 0;
13690 /* Return whether CFG is used in mips_reorg. */
13693 mips_cfg_in_reorg (void)
13695 return (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
13696 || TARGET_RELAX_PIC_CALLS
);
13699 /* Build MIPS16 constant pools. */
13702 mips16_lay_out_constants (void)
13704 struct mips16_constant_pool pool
;
13705 struct mips16_rewrite_pool_refs_info info
;
13708 if (!TARGET_MIPS16_PCREL_LOADS
)
13711 if (mips_cfg_in_reorg ())
13712 split_all_insns ();
13714 split_all_insns_noflow ();
13716 memset (&pool
, 0, sizeof (pool
));
13717 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
13719 /* Rewrite constant pool references in INSN. */
13720 if (USEFUL_INSN_P (insn
))
13724 for_each_rtx (&PATTERN (insn
), mips16_rewrite_pool_refs
, &info
);
13727 pool
.insn_address
+= mips16_insn_length (insn
);
13729 if (pool
.first
!= NULL
)
13731 /* If there are no natural barriers between the first user of
13732 the pool and the highest acceptable address, we'll need to
13733 create a new instruction to jump around the constant pool.
13734 In the worst case, this instruction will be 4 bytes long.
13736 If it's too late to do this transformation after INSN,
13737 do it immediately before INSN. */
13738 if (barrier
== 0 && pool
.insn_address
+ 4 > pool
.highest_address
)
13742 label
= gen_label_rtx ();
13744 jump
= emit_jump_insn_before (gen_jump (label
), insn
);
13745 JUMP_LABEL (jump
) = label
;
13746 LABEL_NUSES (label
) = 1;
13747 barrier
= emit_barrier_after (jump
);
13749 emit_label_after (label
, barrier
);
13750 pool
.insn_address
+= 4;
13753 /* See whether the constant pool is now out of range of the first
13754 user. If so, output the constants after the previous barrier.
13755 Note that any instructions between BARRIER and INSN (inclusive)
13756 will use negative offsets to refer to the pool. */
13757 if (pool
.insn_address
> pool
.highest_address
)
13759 mips16_emit_constants (pool
.first
, barrier
);
13763 else if (BARRIER_P (insn
))
13767 mips16_emit_constants (pool
.first
, get_last_insn ());
13770 /* Return true if it is worth r10k_simplify_address's while replacing
13771 an address with X. We are looking for constants, and for addresses
13772 at a known offset from the incoming stack pointer. */
13775 r10k_simplified_address_p (rtx x
)
13777 if (GET_CODE (x
) == PLUS
&& CONST_INT_P (XEXP (x
, 1)))
13779 return x
== virtual_incoming_args_rtx
|| CONSTANT_P (x
);
13782 /* X is an expression that appears in INSN. Try to use the UD chains
13783 to simplify it, returning the simplified form on success and the
13784 original form otherwise. Replace the incoming value of $sp with
13785 virtual_incoming_args_rtx (which should never occur in X otherwise). */
13788 r10k_simplify_address (rtx x
, rtx insn
)
13790 rtx newx
, op0
, op1
, set
, def_insn
, note
;
13792 struct df_link
*defs
;
13797 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13798 if (op0
!= XEXP (x
, 0))
13799 newx
= simplify_gen_unary (GET_CODE (x
), GET_MODE (x
),
13800 op0
, GET_MODE (XEXP (x
, 0)));
13802 else if (BINARY_P (x
))
13804 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13805 op1
= r10k_simplify_address (XEXP (x
, 1), insn
);
13806 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
13807 newx
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
13809 else if (GET_CODE (x
) == LO_SUM
)
13811 /* LO_SUMs can be offset from HIGHs, if we know they won't
13812 overflow. See mips_classify_address for the rationale behind
13814 op0
= r10k_simplify_address (XEXP (x
, 0), insn
);
13815 if (GET_CODE (op0
) == HIGH
)
13816 newx
= XEXP (x
, 1);
13818 else if (REG_P (x
))
13820 /* Uses are recorded by regno_reg_rtx, not X itself. */
13821 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (x
)]);
13823 defs
= DF_REF_CHAIN (use
);
13825 /* Require a single definition. */
13826 if (defs
&& defs
->next
== NULL
)
13829 if (DF_REF_IS_ARTIFICIAL (def
))
13831 /* Replace the incoming value of $sp with
13832 virtual_incoming_args_rtx. */
13833 if (x
== stack_pointer_rtx
13834 && DF_REF_BB (def
) == ENTRY_BLOCK_PTR
)
13835 newx
= virtual_incoming_args_rtx
;
13837 else if (dominated_by_p (CDI_DOMINATORS
, DF_REF_BB (use
),
13840 /* Make sure that DEF_INSN is a single set of REG. */
13841 def_insn
= DF_REF_INSN (def
);
13842 if (NONJUMP_INSN_P (def_insn
))
13844 set
= single_set (def_insn
);
13845 if (set
&& rtx_equal_p (SET_DEST (set
), x
))
13847 /* Prefer to use notes, since the def-use chains
13848 are often shorter. */
13849 note
= find_reg_equal_equiv_note (def_insn
);
13851 newx
= XEXP (note
, 0);
13853 newx
= SET_SRC (set
);
13854 newx
= r10k_simplify_address (newx
, def_insn
);
13860 if (newx
&& r10k_simplified_address_p (newx
))
13865 /* Return true if ADDRESS is known to be an uncached address
13866 on R10K systems. */
13869 r10k_uncached_address_p (unsigned HOST_WIDE_INT address
)
13871 unsigned HOST_WIDE_INT upper
;
13873 /* Check for KSEG1. */
13874 if (address
+ 0x60000000 < 0x20000000)
13877 /* Check for uncached XKPHYS addresses. */
13878 if (Pmode
== DImode
)
13880 upper
= (address
>> 40) & 0xf9ffff;
13881 if (upper
== 0x900000 || upper
== 0xb80000)
13887 /* Return true if we can prove that an access to address X in instruction
13888 INSN would be safe from R10K speculation. This X is a general
13889 expression; it might not be a legitimate address. */
13892 r10k_safe_address_p (rtx x
, rtx insn
)
13895 HOST_WIDE_INT offset_val
;
13897 x
= r10k_simplify_address (x
, insn
);
13899 /* Check for references to the stack frame. It doesn't really matter
13900 how much of the frame has been allocated at INSN; -mr10k-cache-barrier
13901 allows us to assume that accesses to any part of the eventual frame
13902 is safe from speculation at any point in the function. */
13903 mips_split_plus (x
, &base
, &offset_val
);
13904 if (base
== virtual_incoming_args_rtx
13905 && offset_val
>= -cfun
->machine
->frame
.total_size
13906 && offset_val
< cfun
->machine
->frame
.args_size
)
13909 /* Check for uncached addresses. */
13910 if (CONST_INT_P (x
))
13911 return r10k_uncached_address_p (INTVAL (x
));
13913 /* Check for accesses to a static object. */
13914 split_const (x
, &base
, &offset
);
13915 return offset_within_block_p (base
, INTVAL (offset
));
13918 /* Return true if a MEM with MEM_EXPR EXPR and MEM_OFFSET OFFSET is
13919 an in-range access to an automatic variable, or to an object with
13920 a link-time-constant address. */
13923 r10k_safe_mem_expr_p (tree expr
, rtx offset
)
13925 if (expr
== NULL_TREE
13926 || offset
== NULL_RTX
13927 || !CONST_INT_P (offset
)
13928 || INTVAL (offset
) < 0
13929 || INTVAL (offset
) >= int_size_in_bytes (TREE_TYPE (expr
)))
13932 while (TREE_CODE (expr
) == COMPONENT_REF
)
13934 expr
= TREE_OPERAND (expr
, 0);
13935 if (expr
== NULL_TREE
)
13939 return DECL_P (expr
);
13942 /* A for_each_rtx callback for which DATA points to the instruction
13943 containing *X. Stop the search if we find a MEM that is not safe
13944 from R10K speculation. */
13947 r10k_needs_protection_p_1 (rtx
*loc
, void *data
)
13955 if (r10k_safe_mem_expr_p (MEM_EXPR (mem
), MEM_OFFSET (mem
)))
13958 if (r10k_safe_address_p (XEXP (mem
, 0), (rtx
) data
))
13964 /* A note_stores callback for which DATA points to an instruction pointer.
13965 If *DATA is nonnull, make it null if it X contains a MEM that is not
13966 safe from R10K speculation. */
13969 r10k_needs_protection_p_store (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
,
13974 insn_ptr
= (rtx
*) data
;
13975 if (*insn_ptr
&& for_each_rtx (&x
, r10k_needs_protection_p_1
, *insn_ptr
))
13976 *insn_ptr
= NULL_RTX
;
13979 /* A for_each_rtx callback that iterates over the pattern of a CALL_INSN.
13980 Return nonzero if the call is not to a declared function. */
13983 r10k_needs_protection_p_call (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13992 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_DECL (x
))
13998 /* Return true if instruction INSN needs to be protected by an R10K
14002 r10k_needs_protection_p (rtx insn
)
14005 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_call
, NULL
);
14007 if (mips_r10k_cache_barrier
== R10K_CACHE_BARRIER_STORE
)
14009 note_stores (PATTERN (insn
), r10k_needs_protection_p_store
, &insn
);
14010 return insn
== NULL_RTX
;
14013 return for_each_rtx (&PATTERN (insn
), r10k_needs_protection_p_1
, insn
);
14016 /* Return true if BB is only reached by blocks in PROTECTED_BBS and if every
14017 edge is unconditional. */
14020 r10k_protected_bb_p (basic_block bb
, sbitmap protected_bbs
)
14025 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
14026 if (!single_succ_p (e
->src
)
14027 || !TEST_BIT (protected_bbs
, e
->src
->index
)
14028 || (e
->flags
& EDGE_COMPLEX
) != 0)
14033 /* Implement -mr10k-cache-barrier= for the current function. */
14036 r10k_insert_cache_barriers (void)
14038 int *rev_post_order
;
14041 sbitmap protected_bbs
;
14042 rtx insn
, end
, unprotected_region
;
14046 sorry ("%qs does not support MIPS16 code", "-mr10k-cache-barrier");
14050 /* Calculate dominators. */
14051 calculate_dominance_info (CDI_DOMINATORS
);
14053 /* Bit X of PROTECTED_BBS is set if the last operation in basic block
14054 X is protected by a cache barrier. */
14055 protected_bbs
= sbitmap_alloc (last_basic_block
);
14056 sbitmap_zero (protected_bbs
);
14058 /* Iterate over the basic blocks in reverse post-order. */
14059 rev_post_order
= XNEWVEC (int, last_basic_block
);
14060 n
= pre_and_rev_post_order_compute (NULL
, rev_post_order
, false);
14061 for (i
= 0; i
< n
; i
++)
14063 bb
= BASIC_BLOCK (rev_post_order
[i
]);
14065 /* If this block is only reached by unconditional edges, and if the
14066 source of every edge is protected, the beginning of the block is
14068 if (r10k_protected_bb_p (bb
, protected_bbs
))
14069 unprotected_region
= NULL_RTX
;
14071 unprotected_region
= pc_rtx
;
14072 end
= NEXT_INSN (BB_END (bb
));
14074 /* UNPROTECTED_REGION is:
14076 - null if we are processing a protected region,
14077 - pc_rtx if we are processing an unprotected region but have
14078 not yet found the first instruction in it
14079 - the first instruction in an unprotected region otherwise. */
14080 for (insn
= BB_HEAD (bb
); insn
!= end
; insn
= NEXT_INSN (insn
))
14082 if (unprotected_region
&& USEFUL_INSN_P (insn
))
14084 if (recog_memoized (insn
) == CODE_FOR_mips_cache
)
14085 /* This CACHE instruction protects the following code. */
14086 unprotected_region
= NULL_RTX
;
14089 /* See if INSN is the first instruction in this
14090 unprotected region. */
14091 if (unprotected_region
== pc_rtx
)
14092 unprotected_region
= insn
;
14094 /* See if INSN needs to be protected. If so,
14095 we must insert a cache barrier somewhere between
14096 PREV_INSN (UNPROTECTED_REGION) and INSN. It isn't
14097 clear which position is better performance-wise,
14098 but as a tie-breaker, we assume that it is better
14099 to allow delay slots to be back-filled where
14100 possible, and that it is better not to insert
14101 barriers in the middle of already-scheduled code.
14102 We therefore insert the barrier at the beginning
14104 if (r10k_needs_protection_p (insn
))
14106 emit_insn_before (gen_r10k_cache_barrier (),
14107 unprotected_region
);
14108 unprotected_region
= NULL_RTX
;
14114 /* The called function is not required to protect the exit path.
14115 The code that follows a call is therefore unprotected. */
14116 unprotected_region
= pc_rtx
;
14119 /* Record whether the end of this block is protected. */
14120 if (unprotected_region
== NULL_RTX
)
14121 SET_BIT (protected_bbs
, bb
->index
);
14123 XDELETEVEC (rev_post_order
);
14125 sbitmap_free (protected_bbs
);
14127 free_dominance_info (CDI_DOMINATORS
);
14130 /* If INSN is a call, return the underlying CALL expr. Return NULL_RTX
14131 otherwise. If INSN has two call rtx, then store the second one in
14135 mips_call_expr_from_insn (rtx insn
, rtx
*second_call
)
14140 if (!CALL_P (insn
))
14143 x
= PATTERN (insn
);
14144 if (GET_CODE (x
) == PARALLEL
)
14146 /* Calls returning complex values have two CALL rtx. Look for the second
14147 one here, and return it via the SECOND_CALL arg. */
14148 x2
= XVECEXP (x
, 0, 1);
14149 if (GET_CODE (x2
) == SET
)
14151 if (GET_CODE (x2
) == CALL
)
14154 x
= XVECEXP (x
, 0, 0);
14156 if (GET_CODE (x
) == SET
)
14158 gcc_assert (GET_CODE (x
) == CALL
);
14163 /* REG is set in DEF. See if the definition is one of the ways we load a
14164 register with a symbol address for a mips_use_pic_fn_addr_reg_p call. If
14165 it is return the symbol reference of the function, otherwise return
14169 mips_pic_call_symbol_from_set (df_ref def
, rtx reg
)
14173 if (DF_REF_IS_ARTIFICIAL (def
))
14176 def_insn
= DF_REF_INSN (def
);
14177 set
= single_set (def_insn
);
14178 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
14180 rtx note
, src
, symbol
;
14182 /* First, look at REG_EQUAL/EQUIV notes. */
14183 note
= find_reg_equal_equiv_note (def_insn
);
14184 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
14185 return XEXP (note
, 0);
14187 /* For %call16 references we don't have REG_EQUAL. */
14188 src
= SET_SRC (set
);
14189 symbol
= mips_strip_unspec_call (src
);
14192 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14196 /* Follow simple register copies. */
14198 return mips_find_pic_call_symbol (def_insn
, src
);
14204 /* Find the definition of the use of REG in INSN. See if the definition is
14205 one of the ways we load a register with a symbol address for a
14206 mips_use_pic_fn_addr_reg_p call. If it is return the symbol reference of
14207 the function, otherwise return NULL_RTX. */
14210 mips_find_pic_call_symbol (rtx insn
, rtx reg
)
14213 struct df_link
*defs
;
14216 use
= df_find_use (insn
, regno_reg_rtx
[REGNO (reg
)]);
14219 defs
= DF_REF_CHAIN (use
);
14222 symbol
= mips_pic_call_symbol_from_set (defs
->ref
, reg
);
14226 /* If we have more than one definition, they need to be identical. */
14227 for (defs
= defs
->next
; defs
; defs
= defs
->next
)
14231 other
= mips_pic_call_symbol_from_set (defs
->ref
, reg
);
14232 if (!rtx_equal_p (symbol
, other
))
14239 /* Replace the args_size operand of the call expression CALL with the
14240 call-attribute UNSPEC and fill in SYMBOL as the function symbol. */
14243 mips_annotate_pic_call_expr (rtx call
, rtx symbol
)
14247 args_size
= XEXP (call
, 1);
14248 XEXP (call
, 1) = gen_rtx_UNSPEC (GET_MODE (args_size
),
14249 gen_rtvec (2, args_size
, symbol
),
14253 /* OPERANDS[ARGS_SIZE_OPNO] is the arg_size operand of a CALL expression. See
14254 if instead of the arg_size argument it contains the call attributes. If
14255 yes return true along with setting OPERANDS[ARGS_SIZE_OPNO] to the function
14256 symbol from the call attributes. Also return false if ARGS_SIZE_OPNO is
14260 mips_get_pic_call_symbol (rtx
*operands
, int args_size_opno
)
14262 rtx args_size
, symbol
;
14264 if (!TARGET_RELAX_PIC_CALLS
|| args_size_opno
== -1)
14267 args_size
= operands
[args_size_opno
];
14268 if (GET_CODE (args_size
) != UNSPEC
)
14270 gcc_assert (XINT (args_size
, 1) == UNSPEC_CALL_ATTR
);
14272 symbol
= XVECEXP (args_size
, 0, 1);
14273 gcc_assert (GET_CODE (symbol
) == SYMBOL_REF
);
14275 operands
[args_size_opno
] = symbol
;
14279 /* Use DF to annotate PIC indirect calls with the function symbol they
14283 mips_annotate_pic_calls (void)
14289 FOR_BB_INSNS (bb
, insn
)
14291 rtx call
, reg
, symbol
, second_call
;
14294 call
= mips_call_expr_from_insn (insn
, &second_call
);
14297 gcc_assert (MEM_P (XEXP (call
, 0)));
14298 reg
= XEXP (XEXP (call
, 0), 0);
14302 symbol
= mips_find_pic_call_symbol (insn
, reg
);
14305 mips_annotate_pic_call_expr (call
, symbol
);
14307 mips_annotate_pic_call_expr (second_call
, symbol
);
14312 /* A temporary variable used by for_each_rtx callbacks, etc. */
14313 static rtx mips_sim_insn
;
14315 /* A structure representing the state of the processor pipeline.
14316 Used by the mips_sim_* family of functions. */
14318 /* The maximum number of instructions that can be issued in a cycle.
14319 (Caches mips_issue_rate.) */
14320 unsigned int issue_rate
;
14322 /* The current simulation time. */
14325 /* How many more instructions can be issued in the current cycle. */
14326 unsigned int insns_left
;
14328 /* LAST_SET[X].INSN is the last instruction to set register X.
14329 LAST_SET[X].TIME is the time at which that instruction was issued.
14330 INSN is null if no instruction has yet set register X. */
14334 } last_set
[FIRST_PSEUDO_REGISTER
];
14336 /* The pipeline's current DFA state. */
14340 /* Reset STATE to the initial simulation state. */
14343 mips_sim_reset (struct mips_sim
*state
)
14346 state
->insns_left
= state
->issue_rate
;
14347 memset (&state
->last_set
, 0, sizeof (state
->last_set
));
14348 state_reset (state
->dfa_state
);
14351 /* Initialize STATE before its first use. DFA_STATE points to an
14352 allocated but uninitialized DFA state. */
14355 mips_sim_init (struct mips_sim
*state
, state_t dfa_state
)
14357 state
->issue_rate
= mips_issue_rate ();
14358 state
->dfa_state
= dfa_state
;
14359 mips_sim_reset (state
);
14362 /* Advance STATE by one clock cycle. */
14365 mips_sim_next_cycle (struct mips_sim
*state
)
14368 state
->insns_left
= state
->issue_rate
;
14369 state_transition (state
->dfa_state
, 0);
14372 /* Advance simulation state STATE until instruction INSN can read
14376 mips_sim_wait_reg (struct mips_sim
*state
, rtx insn
, rtx reg
)
14378 unsigned int regno
, end_regno
;
14380 end_regno
= END_REGNO (reg
);
14381 for (regno
= REGNO (reg
); regno
< end_regno
; regno
++)
14382 if (state
->last_set
[regno
].insn
!= 0)
14386 t
= (state
->last_set
[regno
].time
14387 + insn_latency (state
->last_set
[regno
].insn
, insn
));
14388 while (state
->time
< t
)
14389 mips_sim_next_cycle (state
);
14393 /* A for_each_rtx callback. If *X is a register, advance simulation state
14394 DATA until mips_sim_insn can read the register's value. */
14397 mips_sim_wait_regs_2 (rtx
*x
, void *data
)
14400 mips_sim_wait_reg ((struct mips_sim
*) data
, mips_sim_insn
, *x
);
14404 /* Call mips_sim_wait_regs_2 (R, DATA) for each register R mentioned in *X. */
14407 mips_sim_wait_regs_1 (rtx
*x
, void *data
)
14409 for_each_rtx (x
, mips_sim_wait_regs_2
, data
);
14412 /* Advance simulation state STATE until all of INSN's register
14413 dependencies are satisfied. */
14416 mips_sim_wait_regs (struct mips_sim
*state
, rtx insn
)
14418 mips_sim_insn
= insn
;
14419 note_uses (&PATTERN (insn
), mips_sim_wait_regs_1
, state
);
14422 /* Advance simulation state STATE until the units required by
14423 instruction INSN are available. */
14426 mips_sim_wait_units (struct mips_sim
*state
, rtx insn
)
14430 tmp_state
= alloca (state_size ());
14431 while (state
->insns_left
== 0
14432 || (memcpy (tmp_state
, state
->dfa_state
, state_size ()),
14433 state_transition (tmp_state
, insn
) >= 0))
14434 mips_sim_next_cycle (state
);
14437 /* Advance simulation state STATE until INSN is ready to issue. */
14440 mips_sim_wait_insn (struct mips_sim
*state
, rtx insn
)
14442 mips_sim_wait_regs (state
, insn
);
14443 mips_sim_wait_units (state
, insn
);
14446 /* mips_sim_insn has just set X. Update the LAST_SET array
14447 in simulation state DATA. */
14450 mips_sim_record_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
14452 struct mips_sim
*state
;
14454 state
= (struct mips_sim
*) data
;
14457 unsigned int regno
, end_regno
;
14459 end_regno
= END_REGNO (x
);
14460 for (regno
= REGNO (x
); regno
< end_regno
; regno
++)
14462 state
->last_set
[regno
].insn
= mips_sim_insn
;
14463 state
->last_set
[regno
].time
= state
->time
;
14468 /* Issue instruction INSN in scheduler state STATE. Assume that INSN
14469 can issue immediately (i.e., that mips_sim_wait_insn has already
14473 mips_sim_issue_insn (struct mips_sim
*state
, rtx insn
)
14475 state_transition (state
->dfa_state
, insn
);
14476 state
->insns_left
--;
14478 mips_sim_insn
= insn
;
14479 note_stores (PATTERN (insn
), mips_sim_record_set
, state
);
14482 /* Simulate issuing a NOP in state STATE. */
14485 mips_sim_issue_nop (struct mips_sim
*state
)
14487 if (state
->insns_left
== 0)
14488 mips_sim_next_cycle (state
);
14489 state
->insns_left
--;
14492 /* Update simulation state STATE so that it's ready to accept the instruction
14493 after INSN. INSN should be part of the main rtl chain, not a member of a
14497 mips_sim_finish_insn (struct mips_sim
*state
, rtx insn
)
14499 /* If INSN is a jump with an implicit delay slot, simulate a nop. */
14501 mips_sim_issue_nop (state
);
14503 switch (GET_CODE (SEQ_BEGIN (insn
)))
14507 /* We can't predict the processor state after a call or label. */
14508 mips_sim_reset (state
);
14512 /* The delay slots of branch likely instructions are only executed
14513 when the branch is taken. Therefore, if the caller has simulated
14514 the delay slot instruction, STATE does not really reflect the state
14515 of the pipeline for the instruction after the delay slot. Also,
14516 branch likely instructions tend to incur a penalty when not taken,
14517 so there will probably be an extra delay between the branch and
14518 the instruction after the delay slot. */
14519 if (INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (insn
)))
14520 mips_sim_reset (state
);
14528 /* The VR4130 pipeline issues aligned pairs of instructions together,
14529 but it stalls the second instruction if it depends on the first.
14530 In order to cut down the amount of logic required, this dependence
14531 check is not based on a full instruction decode. Instead, any non-SPECIAL
14532 instruction is assumed to modify the register specified by bits 20-16
14533 (which is usually the "rt" field).
14535 In BEQ, BEQL, BNE and BNEL instructions, the rt field is actually an
14536 input, so we can end up with a false dependence between the branch
14537 and its delay slot. If this situation occurs in instruction INSN,
14538 try to avoid it by swapping rs and rt. */
14541 vr4130_avoid_branch_rt_conflict (rtx insn
)
14545 first
= SEQ_BEGIN (insn
);
14546 second
= SEQ_END (insn
);
14548 && NONJUMP_INSN_P (second
)
14549 && GET_CODE (PATTERN (first
)) == SET
14550 && GET_CODE (SET_DEST (PATTERN (first
))) == PC
14551 && GET_CODE (SET_SRC (PATTERN (first
))) == IF_THEN_ELSE
)
14553 /* Check for the right kind of condition. */
14554 rtx cond
= XEXP (SET_SRC (PATTERN (first
)), 0);
14555 if ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
14556 && REG_P (XEXP (cond
, 0))
14557 && REG_P (XEXP (cond
, 1))
14558 && reg_referenced_p (XEXP (cond
, 1), PATTERN (second
))
14559 && !reg_referenced_p (XEXP (cond
, 0), PATTERN (second
)))
14561 /* SECOND mentions the rt register but not the rs register. */
14562 rtx tmp
= XEXP (cond
, 0);
14563 XEXP (cond
, 0) = XEXP (cond
, 1);
14564 XEXP (cond
, 1) = tmp
;
14569 /* Implement -mvr4130-align. Go through each basic block and simulate the
14570 processor pipeline. If we find that a pair of instructions could execute
14571 in parallel, and the first of those instructions is not 8-byte aligned,
14572 insert a nop to make it aligned. */
14575 vr4130_align_insns (void)
14577 struct mips_sim state
;
14578 rtx insn
, subinsn
, last
, last2
, next
;
14583 /* LAST is the last instruction before INSN to have a nonzero length.
14584 LAST2 is the last such instruction before LAST. */
14588 /* ALIGNED_P is true if INSN is known to be at an aligned address. */
14591 mips_sim_init (&state
, alloca (state_size ()));
14592 for (insn
= get_insns (); insn
!= 0; insn
= next
)
14594 unsigned int length
;
14596 next
= NEXT_INSN (insn
);
14598 /* See the comment above vr4130_avoid_branch_rt_conflict for details.
14599 This isn't really related to the alignment pass, but we do it on
14600 the fly to avoid a separate instruction walk. */
14601 vr4130_avoid_branch_rt_conflict (insn
);
14603 if (USEFUL_INSN_P (insn
))
14604 FOR_EACH_SUBINSN (subinsn
, insn
)
14606 mips_sim_wait_insn (&state
, subinsn
);
14608 /* If we want this instruction to issue in parallel with the
14609 previous one, make sure that the previous instruction is
14610 aligned. There are several reasons why this isn't worthwhile
14611 when the second instruction is a call:
14613 - Calls are less likely to be performance critical,
14614 - There's a good chance that the delay slot can execute
14615 in parallel with the call.
14616 - The return address would then be unaligned.
14618 In general, if we're going to insert a nop between instructions
14619 X and Y, it's better to insert it immediately after X. That
14620 way, if the nop makes Y aligned, it will also align any labels
14621 between X and Y. */
14622 if (state
.insns_left
!= state
.issue_rate
14623 && !CALL_P (subinsn
))
14625 if (subinsn
== SEQ_BEGIN (insn
) && aligned_p
)
14627 /* SUBINSN is the first instruction in INSN and INSN is
14628 aligned. We want to align the previous instruction
14629 instead, so insert a nop between LAST2 and LAST.
14631 Note that LAST could be either a single instruction
14632 or a branch with a delay slot. In the latter case,
14633 LAST, like INSN, is already aligned, but the delay
14634 slot must have some extra delay that stops it from
14635 issuing at the same time as the branch. We therefore
14636 insert a nop before the branch in order to align its
14638 emit_insn_after (gen_nop (), last2
);
14641 else if (subinsn
!= SEQ_BEGIN (insn
) && !aligned_p
)
14643 /* SUBINSN is the delay slot of INSN, but INSN is
14644 currently unaligned. Insert a nop between
14645 LAST and INSN to align it. */
14646 emit_insn_after (gen_nop (), last
);
14650 mips_sim_issue_insn (&state
, subinsn
);
14652 mips_sim_finish_insn (&state
, insn
);
14654 /* Update LAST, LAST2 and ALIGNED_P for the next instruction. */
14655 length
= get_attr_length (insn
);
14658 /* If the instruction is an asm statement or multi-instruction
14659 mips.md patern, the length is only an estimate. Insert an
14660 8 byte alignment after it so that the following instructions
14661 can be handled correctly. */
14662 if (NONJUMP_INSN_P (SEQ_BEGIN (insn
))
14663 && (recog_memoized (insn
) < 0 || length
>= 8))
14665 next
= emit_insn_after (gen_align (GEN_INT (3)), insn
);
14666 next
= NEXT_INSN (next
);
14667 mips_sim_next_cycle (&state
);
14670 else if (length
& 4)
14671 aligned_p
= !aligned_p
;
14676 /* See whether INSN is an aligned label. */
14677 if (LABEL_P (insn
) && label_to_alignment (insn
) >= 3)
14683 /* This structure records that the current function has a LO_SUM
14684 involving SYMBOL_REF or LABEL_REF BASE and that MAX_OFFSET is
14685 the largest offset applied to BASE by all such LO_SUMs. */
14686 struct mips_lo_sum_offset
{
14688 HOST_WIDE_INT offset
;
14691 /* Return a hash value for SYMBOL_REF or LABEL_REF BASE. */
14694 mips_hash_base (rtx base
)
14696 int do_not_record_p
;
14698 return hash_rtx (base
, GET_MODE (base
), &do_not_record_p
, NULL
, false);
14701 /* Hash-table callbacks for mips_lo_sum_offsets. */
14704 mips_lo_sum_offset_hash (const void *entry
)
14706 return mips_hash_base (((const struct mips_lo_sum_offset
*) entry
)->base
);
14710 mips_lo_sum_offset_eq (const void *entry
, const void *value
)
14712 return rtx_equal_p (((const struct mips_lo_sum_offset
*) entry
)->base
,
14713 (const_rtx
) value
);
14716 /* Look up symbolic constant X in HTAB, which is a hash table of
14717 mips_lo_sum_offsets. If OPTION is NO_INSERT, return true if X can be
14718 paired with a recorded LO_SUM, otherwise record X in the table. */
14721 mips_lo_sum_offset_lookup (htab_t htab
, rtx x
, enum insert_option option
)
14725 struct mips_lo_sum_offset
*entry
;
14727 /* Split X into a base and offset. */
14728 split_const (x
, &base
, &offset
);
14729 if (UNSPEC_ADDRESS_P (base
))
14730 base
= UNSPEC_ADDRESS (base
);
14732 /* Look up the base in the hash table. */
14733 slot
= htab_find_slot_with_hash (htab
, base
, mips_hash_base (base
), option
);
14737 entry
= (struct mips_lo_sum_offset
*) *slot
;
14738 if (option
== INSERT
)
14742 entry
= XNEW (struct mips_lo_sum_offset
);
14743 entry
->base
= base
;
14744 entry
->offset
= INTVAL (offset
);
14749 if (INTVAL (offset
) > entry
->offset
)
14750 entry
->offset
= INTVAL (offset
);
14753 return INTVAL (offset
) <= entry
->offset
;
14756 /* A for_each_rtx callback for which DATA is a mips_lo_sum_offset hash table.
14757 Record every LO_SUM in *LOC. */
14760 mips_record_lo_sum (rtx
*loc
, void *data
)
14762 if (GET_CODE (*loc
) == LO_SUM
)
14763 mips_lo_sum_offset_lookup ((htab_t
) data
, XEXP (*loc
, 1), INSERT
);
14767 /* Return true if INSN is a SET of an orphaned high-part relocation.
14768 HTAB is a hash table of mips_lo_sum_offsets that describes all the
14769 LO_SUMs in the current function. */
14772 mips_orphaned_high_part_p (htab_t htab
, rtx insn
)
14774 enum mips_symbol_type type
;
14777 set
= single_set (insn
);
14780 /* Check for %his. */
14782 if (GET_CODE (x
) == HIGH
14783 && absolute_symbolic_operand (XEXP (x
, 0), VOIDmode
))
14784 return !mips_lo_sum_offset_lookup (htab
, XEXP (x
, 0), NO_INSERT
);
14786 /* Check for local %gots (and %got_pages, which is redundant but OK). */
14787 if (GET_CODE (x
) == UNSPEC
14788 && XINT (x
, 1) == UNSPEC_LOAD_GOT
14789 && mips_symbolic_constant_p (XVECEXP (x
, 0, 1),
14790 SYMBOL_CONTEXT_LEA
, &type
)
14791 && type
== SYMBOL_GOTOFF_PAGE
)
14792 return !mips_lo_sum_offset_lookup (htab
, XVECEXP (x
, 0, 1), NO_INSERT
);
14797 /* Subroutine of mips_reorg_process_insns. If there is a hazard between
14798 INSN and a previous instruction, avoid it by inserting nops after
14801 *DELAYED_REG and *HILO_DELAY describe the hazards that apply at
14802 this point. If *DELAYED_REG is non-null, INSN must wait a cycle
14803 before using the value of that register. *HILO_DELAY counts the
14804 number of instructions since the last hilo hazard (that is,
14805 the number of instructions since the last MFLO or MFHI).
14807 After inserting nops for INSN, update *DELAYED_REG and *HILO_DELAY
14808 for the next instruction.
14810 LO_REG is an rtx for the LO register, used in dependence checking. */
14813 mips_avoid_hazard (rtx after
, rtx insn
, int *hilo_delay
,
14814 rtx
*delayed_reg
, rtx lo_reg
)
14819 pattern
= PATTERN (insn
);
14821 /* Do not put the whole function in .set noreorder if it contains
14822 an asm statement. We don't know whether there will be hazards
14823 between the asm statement and the gcc-generated code. */
14824 if (GET_CODE (pattern
) == ASM_INPUT
|| asm_noperands (pattern
) >= 0)
14825 cfun
->machine
->all_noreorder_p
= false;
14827 /* Ignore zero-length instructions (barriers and the like). */
14828 ninsns
= get_attr_length (insn
) / 4;
14832 /* Work out how many nops are needed. Note that we only care about
14833 registers that are explicitly mentioned in the instruction's pattern.
14834 It doesn't matter that calls use the argument registers or that they
14835 clobber hi and lo. */
14836 if (*hilo_delay
< 2 && reg_set_p (lo_reg
, pattern
))
14837 nops
= 2 - *hilo_delay
;
14838 else if (*delayed_reg
!= 0 && reg_referenced_p (*delayed_reg
, pattern
))
14843 /* Insert the nops between this instruction and the previous one.
14844 Each new nop takes us further from the last hilo hazard. */
14845 *hilo_delay
+= nops
;
14847 emit_insn_after (gen_hazard_nop (), after
);
14849 /* Set up the state for the next instruction. */
14850 *hilo_delay
+= ninsns
;
14852 if (INSN_CODE (insn
) >= 0)
14853 switch (get_attr_hazard (insn
))
14863 set
= single_set (insn
);
14865 *delayed_reg
= SET_DEST (set
);
14870 /* Go through the instruction stream and insert nops where necessary.
14871 Also delete any high-part relocations whose partnering low parts
14872 are now all dead. See if the whole function can then be put into
14873 .set noreorder and .set nomacro. */
14876 mips_reorg_process_insns (void)
14878 rtx insn
, last_insn
, subinsn
, next_insn
, lo_reg
, delayed_reg
;
14882 /* Force all instructions to be split into their final form. */
14883 split_all_insns_noflow ();
14885 /* Recalculate instruction lengths without taking nops into account. */
14886 cfun
->machine
->ignore_hazard_length_p
= true;
14887 shorten_branches (get_insns ());
14889 cfun
->machine
->all_noreorder_p
= true;
14891 /* We don't track MIPS16 PC-relative offsets closely enough to make
14892 a good job of "set .noreorder" code in MIPS16 mode. */
14894 cfun
->machine
->all_noreorder_p
= false;
14896 /* Code that doesn't use explicit relocs can't be ".set nomacro". */
14897 if (!TARGET_EXPLICIT_RELOCS
)
14898 cfun
->machine
->all_noreorder_p
= false;
14900 /* Profiled functions can't be all noreorder because the profiler
14901 support uses assembler macros. */
14903 cfun
->machine
->all_noreorder_p
= false;
14905 /* Code compiled with -mfix-vr4120 can't be all noreorder because
14906 we rely on the assembler to work around some errata. */
14907 if (TARGET_FIX_VR4120
)
14908 cfun
->machine
->all_noreorder_p
= false;
14910 /* The same is true for -mfix-vr4130 if we might generate MFLO or
14911 MFHI instructions. Note that we avoid using MFLO and MFHI if
14912 the VR4130 MACC and DMACC instructions are available instead;
14913 see the *mfhilo_{si,di}_macc patterns. */
14914 if (TARGET_FIX_VR4130
&& !ISA_HAS_MACCHI
)
14915 cfun
->machine
->all_noreorder_p
= false;
14917 htab
= htab_create (37, mips_lo_sum_offset_hash
,
14918 mips_lo_sum_offset_eq
, free
);
14920 /* Make a first pass over the instructions, recording all the LO_SUMs. */
14921 for (insn
= get_insns (); insn
!= 0; insn
= NEXT_INSN (insn
))
14922 FOR_EACH_SUBINSN (subinsn
, insn
)
14923 if (USEFUL_INSN_P (subinsn
))
14924 for_each_rtx (&PATTERN (subinsn
), mips_record_lo_sum
, htab
);
14929 lo_reg
= gen_rtx_REG (SImode
, LO_REGNUM
);
14931 /* Make a second pass over the instructions. Delete orphaned
14932 high-part relocations or turn them into NOPs. Avoid hazards
14933 by inserting NOPs. */
14934 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
14936 next_insn
= NEXT_INSN (insn
);
14937 if (USEFUL_INSN_P (insn
))
14939 if (GET_CODE (PATTERN (insn
)) == SEQUENCE
)
14941 /* If we find an orphaned high-part relocation in a delay
14942 slot, it's easier to turn that instruction into a NOP than
14943 to delete it. The delay slot will be a NOP either way. */
14944 FOR_EACH_SUBINSN (subinsn
, insn
)
14945 if (INSN_P (subinsn
))
14947 if (mips_orphaned_high_part_p (htab
, subinsn
))
14949 PATTERN (subinsn
) = gen_nop ();
14950 INSN_CODE (subinsn
) = CODE_FOR_nop
;
14952 mips_avoid_hazard (last_insn
, subinsn
, &hilo_delay
,
14953 &delayed_reg
, lo_reg
);
14959 /* INSN is a single instruction. Delete it if it's an
14960 orphaned high-part relocation. */
14961 if (mips_orphaned_high_part_p (htab
, insn
))
14962 delete_insn (insn
);
14963 /* Also delete cache barriers if the last instruction
14964 was an annulled branch. INSN will not be speculatively
14966 else if (recog_memoized (insn
) == CODE_FOR_r10k_cache_barrier
14968 && INSN_ANNULLED_BRANCH_P (SEQ_BEGIN (last_insn
)))
14969 delete_insn (insn
);
14972 mips_avoid_hazard (last_insn
, insn
, &hilo_delay
,
14973 &delayed_reg
, lo_reg
);
14980 htab_delete (htab
);
14983 /* If we are using a GOT, but have not decided to use a global pointer yet,
14984 see whether we need one to implement long branches. Convert the ghost
14985 global-pointer instructions into real ones if so. */
14988 mips_expand_ghost_gp_insns (void)
14993 /* Quick exit if we already know that we will or won't need a
14995 if (!TARGET_USE_GOT
14996 || cfun
->machine
->global_pointer
== INVALID_REGNUM
14997 || mips_must_initialize_gp_p ())
15000 shorten_branches (get_insns ());
15002 /* Look for a branch that is longer than normal. The normal length for
15003 non-MIPS16 branches is 8, because the length includes the delay slot.
15004 It is 4 for MIPS16, because MIPS16 branches are extended instructions,
15005 but they have no delay slot. */
15006 normal_length
= (TARGET_MIPS16
? 4 : 8);
15007 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
15009 && USEFUL_INSN_P (insn
)
15010 && get_attr_length (insn
) > normal_length
)
15013 if (insn
== NULL_RTX
)
15016 /* We've now established that we need $gp. */
15017 cfun
->machine
->must_initialize_gp_p
= true;
15018 split_all_insns_noflow ();
15023 /* Subroutine of mips_reorg to manage passes that require DF. */
15026 mips_df_reorg (void)
15028 /* Create def-use chains. */
15029 df_set_flags (DF_EQ_NOTES
);
15030 df_chain_add_problem (DF_UD_CHAIN
);
15033 if (TARGET_RELAX_PIC_CALLS
)
15034 mips_annotate_pic_calls ();
15036 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
)
15037 r10k_insert_cache_barriers ();
15039 df_finish_pass (false);
15042 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
15047 /* Restore the BLOCK_FOR_INSN pointers, which are needed by DF. Also during
15048 insn splitting in mips16_lay_out_constants, DF insn info is only kept up
15049 to date if the CFG is available. */
15050 if (mips_cfg_in_reorg ())
15051 compute_bb_for_insn ();
15052 mips16_lay_out_constants ();
15053 if (mips_cfg_in_reorg ())
15056 free_bb_for_insn ();
15059 if (optimize
> 0 && flag_delayed_branch
)
15060 dbr_schedule (get_insns ());
15061 mips_reorg_process_insns ();
15063 && TARGET_EXPLICIT_RELOCS
15065 && TARGET_VR4130_ALIGN
)
15066 vr4130_align_insns ();
15067 if (mips_expand_ghost_gp_insns ())
15068 /* The expansion could invalidate some of the VR4130 alignment
15069 optimizations, but this should be an extremely rare case anyhow. */
15070 mips_reorg_process_insns ();
15073 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
15074 in order to avoid duplicating too much logic from elsewhere. */
15077 mips_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
15078 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
15081 rtx this_rtx
, temp1
, temp2
, insn
, fnaddr
;
15082 bool use_sibcall_p
;
15084 /* Pretend to be a post-reload pass while generating rtl. */
15085 reload_completed
= 1;
15087 /* Mark the end of the (empty) prologue. */
15088 emit_note (NOTE_INSN_PROLOGUE_END
);
15090 /* Determine if we can use a sibcall to call FUNCTION directly. */
15091 fnaddr
= XEXP (DECL_RTL (function
), 0);
15092 use_sibcall_p
= (mips_function_ok_for_sibcall (function
, NULL
)
15093 && const_call_insn_operand (fnaddr
, Pmode
));
15095 /* Determine if we need to load FNADDR from the GOT. */
15097 && (mips_got_symbol_type_p
15098 (mips_classify_symbol (fnaddr
, SYMBOL_CONTEXT_LEA
))))
15100 /* Pick a global pointer. Use a call-clobbered register if
15101 TARGET_CALL_SAVED_GP. */
15102 cfun
->machine
->global_pointer
15103 = TARGET_CALL_SAVED_GP
? 15 : GLOBAL_POINTER_REGNUM
;
15104 cfun
->machine
->must_initialize_gp_p
= true;
15105 SET_REGNO (pic_offset_table_rtx
, cfun
->machine
->global_pointer
);
15107 /* Set up the global pointer for n32 or n64 abicalls. */
15108 mips_emit_loadgp ();
15111 /* We need two temporary registers in some cases. */
15112 temp1
= gen_rtx_REG (Pmode
, 2);
15113 temp2
= gen_rtx_REG (Pmode
, 3);
15115 /* Find out which register contains the "this" pointer. */
15116 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
15117 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
+ 1);
15119 this_rtx
= gen_rtx_REG (Pmode
, GP_ARG_FIRST
);
15121 /* Add DELTA to THIS_RTX. */
15124 rtx offset
= GEN_INT (delta
);
15125 if (!SMALL_OPERAND (delta
))
15127 mips_emit_move (temp1
, offset
);
15130 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, offset
));
15133 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
15134 if (vcall_offset
!= 0)
15138 /* Set TEMP1 to *THIS_RTX. */
15139 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, this_rtx
));
15141 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
15142 addr
= mips_add_offset (temp2
, temp1
, vcall_offset
);
15144 /* Load the offset and add it to THIS_RTX. */
15145 mips_emit_move (temp1
, gen_rtx_MEM (Pmode
, addr
));
15146 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, temp1
));
15149 /* Jump to the target function. Use a sibcall if direct jumps are
15150 allowed, otherwise load the address into a register first. */
15153 insn
= emit_call_insn (gen_sibcall_internal (fnaddr
, const0_rtx
));
15154 SIBLING_CALL_P (insn
) = 1;
15158 /* This is messy. GAS treats "la $25,foo" as part of a call
15159 sequence and may allow a global "foo" to be lazily bound.
15160 The general move patterns therefore reject this combination.
15162 In this context, lazy binding would actually be OK
15163 for TARGET_CALL_CLOBBERED_GP, but it's still wrong for
15164 TARGET_CALL_SAVED_GP; see mips_load_call_address.
15165 We must therefore load the address via a temporary
15166 register if mips_dangerous_for_la25_p.
15168 If we jump to the temporary register rather than $25,
15169 the assembler can use the move insn to fill the jump's
15172 We can use the same technique for MIPS16 code, where $25
15173 is not a valid JR register. */
15174 if (TARGET_USE_PIC_FN_ADDR_REG
15176 && !mips_dangerous_for_la25_p (fnaddr
))
15177 temp1
= gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
);
15178 mips_load_call_address (MIPS_CALL_SIBCALL
, temp1
, fnaddr
);
15180 if (TARGET_USE_PIC_FN_ADDR_REG
15181 && REGNO (temp1
) != PIC_FUNCTION_ADDR_REGNUM
)
15182 mips_emit_move (gen_rtx_REG (Pmode
, PIC_FUNCTION_ADDR_REGNUM
), temp1
);
15183 emit_jump_insn (gen_indirect_jump (temp1
));
15186 /* Run just enough of rest_of_compilation. This sequence was
15187 "borrowed" from alpha.c. */
15188 insn
= get_insns ();
15189 insn_locators_alloc ();
15190 split_all_insns_noflow ();
15191 mips16_lay_out_constants ();
15192 shorten_branches (insn
);
15193 final_start_function (insn
, file
, 1);
15194 final (insn
, file
, 1);
15195 final_end_function ();
15197 /* Clean up the vars set above. Note that final_end_function resets
15198 the global pointer for us. */
15199 reload_completed
= 0;
15202 /* The last argument passed to mips_set_mips16_mode, or negative if the
15203 function hasn't been called yet.
15205 There are two copies of this information. One is saved and restored
15206 by the PCH process while the other is specific to this compiler
15207 invocation. The information calculated by mips_set_mips16_mode
15208 is invalid unless the two variables are the same. */
15209 static int was_mips16_p
= -1;
15210 static GTY(()) int was_mips16_pch_p
= -1;
15212 /* Set up the target-dependent global state so that it matches the
15213 current function's ISA mode. */
15216 mips_set_mips16_mode (int mips16_p
)
15218 if (mips16_p
== was_mips16_p
15219 && mips16_p
== was_mips16_pch_p
)
15222 /* Restore base settings of various flags. */
15223 target_flags
= mips_base_target_flags
;
15224 flag_schedule_insns
= mips_base_schedule_insns
;
15225 flag_reorder_blocks_and_partition
= mips_base_reorder_blocks_and_partition
;
15226 flag_move_loop_invariants
= mips_base_move_loop_invariants
;
15227 align_loops
= mips_base_align_loops
;
15228 align_jumps
= mips_base_align_jumps
;
15229 align_functions
= mips_base_align_functions
;
15233 /* Switch to MIPS16 mode. */
15234 target_flags
|= MASK_MIPS16
;
15236 /* Don't run the scheduler before reload, since it tends to
15237 increase register pressure. */
15238 flag_schedule_insns
= 0;
15240 /* Don't do hot/cold partitioning. mips16_lay_out_constants expects
15241 the whole function to be in a single section. */
15242 flag_reorder_blocks_and_partition
= 0;
15244 /* Don't move loop invariants, because it tends to increase
15245 register pressure. It also introduces an extra move in cases
15246 where the constant is the first operand in a two-operand binary
15247 instruction, or when it forms a register argument to a functon
15249 flag_move_loop_invariants
= 0;
15251 target_flags
|= MASK_EXPLICIT_RELOCS
;
15253 /* Experiments suggest we get the best overall section-anchor
15254 results from using the range of an unextended LW or SW. Code
15255 that makes heavy use of byte or short accesses can do better
15256 with ranges of 0...31 and 0...63 respectively, but most code is
15257 sensitive to the range of LW and SW instead. */
15258 targetm
.min_anchor_offset
= 0;
15259 targetm
.max_anchor_offset
= 127;
15261 targetm
.const_anchor
= 0;
15263 /* MIPS16 has no BAL instruction. */
15264 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
15266 if (flag_pic
&& !TARGET_OLDABI
)
15267 sorry ("MIPS16 PIC for ABIs other than o32 and o64");
15270 sorry ("MIPS16 -mxgot code");
15272 if (TARGET_HARD_FLOAT_ABI
&& !TARGET_OLDABI
)
15273 sorry ("hard-float MIPS16 code for ABIs other than o32 and o64");
15277 /* Switch to normal (non-MIPS16) mode. */
15278 target_flags
&= ~MASK_MIPS16
;
15280 /* Provide default values for align_* for 64-bit targets. */
15283 if (align_loops
== 0)
15285 if (align_jumps
== 0)
15287 if (align_functions
== 0)
15288 align_functions
= 8;
15291 targetm
.min_anchor_offset
= -32768;
15292 targetm
.max_anchor_offset
= 32767;
15294 targetm
.const_anchor
= 0x8000;
15297 /* (Re)initialize MIPS target internals for new ISA. */
15298 mips_init_relocs ();
15302 if (!mips16_globals
)
15303 mips16_globals
= save_target_globals ();
15305 restore_target_globals (mips16_globals
);
15308 restore_target_globals (&default_target_globals
);
15310 was_mips16_p
= mips16_p
;
15311 was_mips16_pch_p
= mips16_p
;
15314 /* Implement TARGET_SET_CURRENT_FUNCTION. Decide whether the current
15315 function should use the MIPS16 ISA and switch modes accordingly. */
15318 mips_set_current_function (tree fndecl
)
15320 mips_set_mips16_mode (mips_use_mips16_mode_p (fndecl
));
15323 /* Allocate a chunk of memory for per-function machine-dependent data. */
15325 static struct machine_function
*
15326 mips_init_machine_status (void)
15328 return ggc_alloc_cleared_machine_function ();
15331 /* Return the processor associated with the given ISA level, or null
15332 if the ISA isn't valid. */
15334 static const struct mips_cpu_info
*
15335 mips_cpu_info_from_isa (int isa
)
15339 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15340 if (mips_cpu_info_table
[i
].isa
== isa
)
15341 return mips_cpu_info_table
+ i
;
15346 /* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
15347 with a final "000" replaced by "k". Ignore case.
15349 Note: this function is shared between GCC and GAS. */
15352 mips_strict_matching_cpu_name_p (const char *canonical
, const char *given
)
15354 while (*given
!= 0 && TOLOWER (*given
) == TOLOWER (*canonical
))
15355 given
++, canonical
++;
15357 return ((*given
== 0 && *canonical
== 0)
15358 || (strcmp (canonical
, "000") == 0 && strcasecmp (given
, "k") == 0));
15361 /* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
15362 CPU name. We've traditionally allowed a lot of variation here.
15364 Note: this function is shared between GCC and GAS. */
15367 mips_matching_cpu_name_p (const char *canonical
, const char *given
)
15369 /* First see if the name matches exactly, or with a final "000"
15370 turned into "k". */
15371 if (mips_strict_matching_cpu_name_p (canonical
, given
))
15374 /* If not, try comparing based on numerical designation alone.
15375 See if GIVEN is an unadorned number, or 'r' followed by a number. */
15376 if (TOLOWER (*given
) == 'r')
15378 if (!ISDIGIT (*given
))
15381 /* Skip over some well-known prefixes in the canonical name,
15382 hoping to find a number there too. */
15383 if (TOLOWER (canonical
[0]) == 'v' && TOLOWER (canonical
[1]) == 'r')
15385 else if (TOLOWER (canonical
[0]) == 'r' && TOLOWER (canonical
[1]) == 'm')
15387 else if (TOLOWER (canonical
[0]) == 'r')
15390 return mips_strict_matching_cpu_name_p (canonical
, given
);
15393 /* Return the mips_cpu_info entry for the processor or ISA given
15394 by CPU_STRING. Return null if the string isn't recognized.
15396 A similar function exists in GAS. */
15398 static const struct mips_cpu_info
*
15399 mips_parse_cpu (const char *cpu_string
)
15404 /* In the past, we allowed upper-case CPU names, but it doesn't
15405 work well with the multilib machinery. */
15406 for (s
= cpu_string
; *s
!= 0; s
++)
15409 warning (0, "CPU names must be lower case");
15413 /* 'from-abi' selects the most compatible architecture for the given
15414 ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
15415 EABIs, we have to decide whether we're using the 32-bit or 64-bit
15417 if (strcasecmp (cpu_string
, "from-abi") == 0)
15418 return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS
? 1
15419 : ABI_NEEDS_64BIT_REGS
? 3
15420 : (TARGET_64BIT
? 3 : 1));
15422 /* 'default' has traditionally been a no-op. Probably not very useful. */
15423 if (strcasecmp (cpu_string
, "default") == 0)
15426 for (i
= 0; i
< ARRAY_SIZE (mips_cpu_info_table
); i
++)
15427 if (mips_matching_cpu_name_p (mips_cpu_info_table
[i
].name
, cpu_string
))
15428 return mips_cpu_info_table
+ i
;
15433 /* Set up globals to generate code for the ISA or processor
15434 described by INFO. */
15437 mips_set_architecture (const struct mips_cpu_info
*info
)
15441 mips_arch_info
= info
;
15442 mips_arch
= info
->cpu
;
15443 mips_isa
= info
->isa
;
15447 /* Likewise for tuning. */
15450 mips_set_tune (const struct mips_cpu_info
*info
)
15454 mips_tune_info
= info
;
15455 mips_tune
= info
->cpu
;
15459 /* Implement TARGET_HANDLE_OPTION. */
15462 mips_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
15467 if (strcmp (arg
, "32") == 0)
15469 else if (strcmp (arg
, "o64") == 0)
15470 mips_abi
= ABI_O64
;
15471 else if (strcmp (arg
, "n32") == 0)
15472 mips_abi
= ABI_N32
;
15473 else if (strcmp (arg
, "64") == 0)
15475 else if (strcmp (arg
, "eabi") == 0)
15476 mips_abi
= ABI_EABI
;
15483 return mips_parse_cpu (arg
) != 0;
15486 mips_isa_option_info
= mips_parse_cpu (ACONCAT (("mips", arg
, NULL
)));
15487 return mips_isa_option_info
!= 0;
15489 case OPT_mno_flush_func
:
15490 mips_cache_flush_func
= NULL
;
15493 case OPT_mcode_readable_
:
15494 if (strcmp (arg
, "yes") == 0)
15495 mips_code_readable
= CODE_READABLE_YES
;
15496 else if (strcmp (arg
, "pcrel") == 0)
15497 mips_code_readable
= CODE_READABLE_PCREL
;
15498 else if (strcmp (arg
, "no") == 0)
15499 mips_code_readable
= CODE_READABLE_NO
;
15504 case OPT_mr10k_cache_barrier_
:
15505 if (strcmp (arg
, "load-store") == 0)
15506 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_LOAD_STORE
;
15507 else if (strcmp (arg
, "store") == 0)
15508 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_STORE
;
15509 else if (strcmp (arg
, "none") == 0)
15510 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
15520 /* Implement TARGET_OPTION_OVERRIDE. */
15523 mips_option_override (void)
15525 int i
, start
, regno
, mode
;
15527 /* Process flags as though we were generating non-MIPS16 code. */
15528 mips_base_mips16
= TARGET_MIPS16
;
15529 target_flags
&= ~MASK_MIPS16
;
15531 #ifdef SUBTARGET_OVERRIDE_OPTIONS
15532 SUBTARGET_OVERRIDE_OPTIONS
;
15535 /* -mno-float overrides -mhard-float and -msoft-float. */
15536 if (TARGET_NO_FLOAT
)
15538 target_flags
|= MASK_SOFT_FLOAT_ABI
;
15539 target_flags_explicit
|= MASK_SOFT_FLOAT_ABI
;
15542 if (TARGET_FLIP_MIPS16
)
15543 TARGET_INTERLINK_MIPS16
= 1;
15545 /* Set the small data limit. */
15546 mips_small_data_threshold
= (global_options_set
.x_g_switch_value
15548 : MIPS_DEFAULT_GVALUE
);
15550 /* The following code determines the architecture and register size.
15551 Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
15552 The GAS and GCC code should be kept in sync as much as possible. */
15554 if (mips_arch_string
!= 0)
15555 mips_set_architecture (mips_parse_cpu (mips_arch_string
));
15557 if (mips_isa_option_info
!= 0)
15559 if (mips_arch_info
== 0)
15560 mips_set_architecture (mips_isa_option_info
);
15561 else if (mips_arch_info
->isa
!= mips_isa_option_info
->isa
)
15562 error ("%<-%s%> conflicts with the other architecture options, "
15563 "which specify a %s processor",
15564 mips_isa_option_info
->name
,
15565 mips_cpu_info_from_isa (mips_arch_info
->isa
)->name
);
15568 if (mips_arch_info
== 0)
15570 #ifdef MIPS_CPU_STRING_DEFAULT
15571 mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT
));
15573 mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT
));
15577 if (ABI_NEEDS_64BIT_REGS
&& !ISA_HAS_64BIT_REGS
)
15578 error ("%<-march=%s%> is not compatible with the selected ABI",
15579 mips_arch_info
->name
);
15581 /* Optimize for mips_arch, unless -mtune selects a different processor. */
15582 if (mips_tune_string
!= 0)
15583 mips_set_tune (mips_parse_cpu (mips_tune_string
));
15585 if (mips_tune_info
== 0)
15586 mips_set_tune (mips_arch_info
);
15588 if ((target_flags_explicit
& MASK_64BIT
) != 0)
15590 /* The user specified the size of the integer registers. Make sure
15591 it agrees with the ABI and ISA. */
15592 if (TARGET_64BIT
&& !ISA_HAS_64BIT_REGS
)
15593 error ("%<-mgp64%> used with a 32-bit processor");
15594 else if (!TARGET_64BIT
&& ABI_NEEDS_64BIT_REGS
)
15595 error ("%<-mgp32%> used with a 64-bit ABI");
15596 else if (TARGET_64BIT
&& ABI_NEEDS_32BIT_REGS
)
15597 error ("%<-mgp64%> used with a 32-bit ABI");
15601 /* Infer the integer register size from the ABI and processor.
15602 Restrict ourselves to 32-bit registers if that's all the
15603 processor has, or if the ABI cannot handle 64-bit registers. */
15604 if (ABI_NEEDS_32BIT_REGS
|| !ISA_HAS_64BIT_REGS
)
15605 target_flags
&= ~MASK_64BIT
;
15607 target_flags
|= MASK_64BIT
;
15610 if ((target_flags_explicit
& MASK_FLOAT64
) != 0)
15612 if (TARGET_SINGLE_FLOAT
&& TARGET_FLOAT64
)
15613 error ("unsupported combination: %s", "-mfp64 -msingle-float");
15614 else if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
&& !TARGET_FLOAT64
)
15615 error ("unsupported combination: %s", "-mgp64 -mfp32 -mdouble-float");
15616 else if (!TARGET_64BIT
&& TARGET_FLOAT64
)
15618 if (!ISA_HAS_MXHC1
)
15619 error ("%<-mgp32%> and %<-mfp64%> can only be combined if"
15620 " the target supports the mfhc1 and mthc1 instructions");
15621 else if (mips_abi
!= ABI_32
)
15622 error ("%<-mgp32%> and %<-mfp64%> can only be combined when using"
15628 /* -msingle-float selects 32-bit float registers. Otherwise the
15629 float registers should be the same size as the integer ones. */
15630 if (TARGET_64BIT
&& TARGET_DOUBLE_FLOAT
)
15631 target_flags
|= MASK_FLOAT64
;
15633 target_flags
&= ~MASK_FLOAT64
;
15636 /* End of code shared with GAS. */
15638 /* If no -mlong* option was given, infer it from the other options. */
15639 if ((target_flags_explicit
& MASK_LONG64
) == 0)
15641 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
) || mips_abi
== ABI_64
)
15642 target_flags
|= MASK_LONG64
;
15644 target_flags
&= ~MASK_LONG64
;
15647 if (!TARGET_OLDABI
)
15648 flag_pcc_struct_return
= 0;
15650 /* Decide which rtx_costs structure to use. */
15652 mips_cost
= &mips_rtx_cost_optimize_size
;
15654 mips_cost
= &mips_rtx_cost_data
[mips_tune
];
15656 /* If the user hasn't specified a branch cost, use the processor's
15658 if (mips_branch_cost
== 0)
15659 mips_branch_cost
= mips_cost
->branch_cost
;
15661 /* If neither -mbranch-likely nor -mno-branch-likely was given
15662 on the command line, set MASK_BRANCHLIKELY based on the target
15663 architecture and tuning flags. Annulled delay slots are a
15664 size win, so we only consider the processor-specific tuning
15665 for !optimize_size. */
15666 if ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0)
15668 if (ISA_HAS_BRANCHLIKELY
15670 || (mips_tune_info
->tune_flags
& PTF_AVOID_BRANCHLIKELY
) == 0))
15671 target_flags
|= MASK_BRANCHLIKELY
;
15673 target_flags
&= ~MASK_BRANCHLIKELY
;
15675 else if (TARGET_BRANCHLIKELY
&& !ISA_HAS_BRANCHLIKELY
)
15676 warning (0, "the %qs architecture does not support branch-likely"
15677 " instructions", mips_arch_info
->name
);
15679 /* The effect of -mabicalls isn't defined for the EABI. */
15680 if (mips_abi
== ABI_EABI
&& TARGET_ABICALLS
)
15682 error ("unsupported combination: %s", "-mabicalls -mabi=eabi");
15683 target_flags
&= ~MASK_ABICALLS
;
15686 if (TARGET_ABICALLS_PIC2
)
15687 /* We need to set flag_pic for executables as well as DSOs
15688 because we may reference symbols that are not defined in
15689 the final executable. (MIPS does not use things like
15690 copy relocs, for example.)
15692 There is a body of code that uses __PIC__ to distinguish
15693 between -mabicalls and -mno-abicalls code. The non-__PIC__
15694 variant is usually appropriate for TARGET_ABICALLS_PIC0, as
15695 long as any indirect jumps use $25. */
15698 /* -mvr4130-align is a "speed over size" optimization: it usually produces
15699 faster code, but at the expense of more nops. Enable it at -O3 and
15701 if (optimize
> 2 && (target_flags_explicit
& MASK_VR4130_ALIGN
) == 0)
15702 target_flags
|= MASK_VR4130_ALIGN
;
15704 /* Prefer a call to memcpy over inline code when optimizing for size,
15705 though see MOVE_RATIO in mips.h. */
15706 if (optimize_size
&& (target_flags_explicit
& MASK_MEMCPY
) == 0)
15707 target_flags
|= MASK_MEMCPY
;
15709 /* If we have a nonzero small-data limit, check that the -mgpopt
15710 setting is consistent with the other target flags. */
15711 if (mips_small_data_threshold
> 0)
15715 if (!TARGET_EXPLICIT_RELOCS
)
15716 error ("%<-mno-gpopt%> needs %<-mexplicit-relocs%>");
15718 TARGET_LOCAL_SDATA
= false;
15719 TARGET_EXTERN_SDATA
= false;
15723 if (TARGET_VXWORKS_RTP
)
15724 warning (0, "cannot use small-data accesses for %qs", "-mrtp");
15726 if (TARGET_ABICALLS
)
15727 warning (0, "cannot use small-data accesses for %qs",
15732 #ifdef MIPS_TFMODE_FORMAT
15733 REAL_MODE_FORMAT (TFmode
) = &MIPS_TFMODE_FORMAT
;
15736 /* Make sure that the user didn't turn off paired single support when
15737 MIPS-3D support is requested. */
15739 && (target_flags_explicit
& MASK_PAIRED_SINGLE_FLOAT
)
15740 && !TARGET_PAIRED_SINGLE_FLOAT
)
15741 error ("%<-mips3d%> requires %<-mpaired-single%>");
15743 /* If TARGET_MIPS3D, enable MASK_PAIRED_SINGLE_FLOAT. */
15745 target_flags
|= MASK_PAIRED_SINGLE_FLOAT
;
15747 /* Make sure that when TARGET_PAIRED_SINGLE_FLOAT is true, TARGET_FLOAT64
15748 and TARGET_HARD_FLOAT_ABI are both true. */
15749 if (TARGET_PAIRED_SINGLE_FLOAT
&& !(TARGET_FLOAT64
&& TARGET_HARD_FLOAT_ABI
))
15750 error ("%qs must be used with %qs",
15751 TARGET_MIPS3D
? "-mips3d" : "-mpaired-single",
15752 TARGET_HARD_FLOAT_ABI
? "-mfp64" : "-mhard-float");
15754 /* Make sure that the ISA supports TARGET_PAIRED_SINGLE_FLOAT when it is
15756 if (TARGET_PAIRED_SINGLE_FLOAT
&& !ISA_HAS_PAIRED_SINGLE
)
15757 warning (0, "the %qs architecture does not support paired-single"
15758 " instructions", mips_arch_info
->name
);
15760 if (mips_r10k_cache_barrier
!= R10K_CACHE_BARRIER_NONE
15761 && !TARGET_CACHE_BUILTIN
)
15763 error ("%qs requires a target that provides the %qs instruction",
15764 "-mr10k-cache-barrier", "cache");
15765 mips_r10k_cache_barrier
= R10K_CACHE_BARRIER_NONE
;
15768 /* If TARGET_DSPR2, enable MASK_DSP. */
15770 target_flags
|= MASK_DSP
;
15772 /* .eh_frame addresses should be the same width as a C pointer.
15773 Most MIPS ABIs support only one pointer size, so the assembler
15774 will usually know exactly how big an .eh_frame address is.
15776 Unfortunately, this is not true of the 64-bit EABI. The ABI was
15777 originally defined to use 64-bit pointers (i.e. it is LP64), and
15778 this is still the default mode. However, we also support an n32-like
15779 ILP32 mode, which is selected by -mlong32. The problem is that the
15780 assembler has traditionally not had an -mlong option, so it has
15781 traditionally not known whether we're using the ILP32 or LP64 form.
15783 As it happens, gas versions up to and including 2.19 use _32-bit_
15784 addresses for EABI64 .cfi_* directives. This is wrong for the
15785 default LP64 mode, so we can't use the directives by default.
15786 Moreover, since gas's current behavior is at odds with gcc's
15787 default behavior, it seems unwise to rely on future versions
15788 of gas behaving the same way. We therefore avoid using .cfi
15789 directives for -mlong32 as well. */
15790 if (mips_abi
== ABI_EABI
&& TARGET_64BIT
)
15791 flag_dwarf2_cfi_asm
= 0;
15793 /* .cfi_* directives generate a read-only section, so fall back on
15794 manual .eh_frame creation if we need the section to be writable. */
15795 if (TARGET_WRITABLE_EH_FRAME
)
15796 flag_dwarf2_cfi_asm
= 0;
15798 mips_init_print_operand_punct ();
15800 /* Set up array to map GCC register number to debug register number.
15801 Ignore the special purpose register numbers. */
15803 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
15805 mips_dbx_regno
[i
] = INVALID_REGNUM
;
15806 if (GP_REG_P (i
) || FP_REG_P (i
) || ALL_COP_REG_P (i
))
15807 mips_dwarf_regno
[i
] = i
;
15809 mips_dwarf_regno
[i
] = INVALID_REGNUM
;
15812 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
15813 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
15814 mips_dbx_regno
[i
] = i
+ start
;
15816 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
15817 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
15818 mips_dbx_regno
[i
] = i
+ start
;
15820 /* Accumulator debug registers use big-endian ordering. */
15821 mips_dbx_regno
[HI_REGNUM
] = MD_DBX_FIRST
+ 0;
15822 mips_dbx_regno
[LO_REGNUM
] = MD_DBX_FIRST
+ 1;
15823 mips_dwarf_regno
[HI_REGNUM
] = MD_REG_FIRST
+ 0;
15824 mips_dwarf_regno
[LO_REGNUM
] = MD_REG_FIRST
+ 1;
15825 for (i
= DSP_ACC_REG_FIRST
; i
<= DSP_ACC_REG_LAST
; i
+= 2)
15827 mips_dwarf_regno
[i
+ TARGET_LITTLE_ENDIAN
] = i
;
15828 mips_dwarf_regno
[i
+ TARGET_BIG_ENDIAN
] = i
+ 1;
15831 /* Set up mips_hard_regno_mode_ok. */
15832 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
15833 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
15834 mips_hard_regno_mode_ok
[mode
][regno
]
15835 = mips_hard_regno_mode_ok_p (regno
, (enum machine_mode
) mode
);
15837 /* Function to allocate machine-dependent function status. */
15838 init_machine_status
= &mips_init_machine_status
;
15840 /* Default to working around R4000 errata only if the processor
15841 was selected explicitly. */
15842 if ((target_flags_explicit
& MASK_FIX_R4000
) == 0
15843 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4000"))
15844 target_flags
|= MASK_FIX_R4000
;
15846 /* Default to working around R4400 errata only if the processor
15847 was selected explicitly. */
15848 if ((target_flags_explicit
& MASK_FIX_R4400
) == 0
15849 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r4400"))
15850 target_flags
|= MASK_FIX_R4400
;
15852 /* Default to working around R10000 errata only if the processor
15853 was selected explicitly. */
15854 if ((target_flags_explicit
& MASK_FIX_R10000
) == 0
15855 && mips_matching_cpu_name_p (mips_arch_info
->name
, "r10000"))
15856 target_flags
|= MASK_FIX_R10000
;
15858 /* Make sure that branch-likely instructions available when using
15859 -mfix-r10000. The instructions are not available if either:
15861 1. -mno-branch-likely was passed.
15862 2. The selected ISA does not support branch-likely and
15863 the command line does not include -mbranch-likely. */
15864 if (TARGET_FIX_R10000
15865 && ((target_flags_explicit
& MASK_BRANCHLIKELY
) == 0
15866 ? !ISA_HAS_BRANCHLIKELY
15867 : !TARGET_BRANCHLIKELY
))
15868 sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
15870 if (TARGET_SYNCI
&& !ISA_HAS_SYNCI
)
15872 warning (0, "the %qs architecture does not support the synci "
15873 "instruction", mips_arch_info
->name
);
15874 target_flags
&= ~MASK_SYNCI
;
15877 /* Only optimize PIC indirect calls if they are actually required. */
15878 if (!TARGET_USE_GOT
|| !TARGET_EXPLICIT_RELOCS
)
15879 target_flags
&= ~MASK_RELAX_PIC_CALLS
;
15881 /* Save base state of options. */
15882 mips_base_target_flags
= target_flags
;
15883 mips_base_schedule_insns
= flag_schedule_insns
;
15884 mips_base_reorder_blocks_and_partition
= flag_reorder_blocks_and_partition
;
15885 mips_base_move_loop_invariants
= flag_move_loop_invariants
;
15886 mips_base_align_loops
= align_loops
;
15887 mips_base_align_jumps
= align_jumps
;
15888 mips_base_align_functions
= align_functions
;
15890 /* Now select the ISA mode.
15892 Do all CPP-sensitive stuff in non-MIPS16 mode; we'll switch to
15893 MIPS16 mode afterwards if need be. */
15894 mips_set_mips16_mode (false);
15897 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
15898 static const struct default_options mips_option_optimization_table
[] =
15900 { OPT_LEVELS_1_PLUS
, OPT_fomit_frame_pointer
, NULL
, 1 },
15901 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
15904 /* Swap the register information for registers I and I + 1, which
15905 currently have the wrong endianness. Note that the registers'
15906 fixedness and call-clobberedness might have been set on the
15910 mips_swap_registers (unsigned int i
)
15915 #define SWAP_INT(X, Y) (tmpi = (X), (X) = (Y), (Y) = tmpi)
15916 #define SWAP_STRING(X, Y) (tmps = (X), (X) = (Y), (Y) = tmps)
15918 SWAP_INT (fixed_regs
[i
], fixed_regs
[i
+ 1]);
15919 SWAP_INT (call_used_regs
[i
], call_used_regs
[i
+ 1]);
15920 SWAP_INT (call_really_used_regs
[i
], call_really_used_regs
[i
+ 1]);
15921 SWAP_STRING (reg_names
[i
], reg_names
[i
+ 1]);
15927 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
15930 mips_conditional_register_usage (void)
15935 /* These DSP control register fields are global. */
15936 global_regs
[CCDSP_PO_REGNUM
] = 1;
15937 global_regs
[CCDSP_SC_REGNUM
] = 1;
15943 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
++)
15944 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15946 if (!TARGET_HARD_FLOAT
)
15950 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
++)
15951 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15952 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
15953 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15955 else if (! ISA_HAS_8CC
)
15959 /* We only have a single condition-code register. We implement
15960 this by fixing all the condition-code registers and generating
15961 RTL that refers directly to ST_REG_FIRST. */
15962 for (regno
= ST_REG_FIRST
; regno
<= ST_REG_LAST
; regno
++)
15963 fixed_regs
[regno
] = call_used_regs
[regno
] = 1;
15965 /* In MIPS16 mode, we permit the $t temporary registers to be used
15966 for reload. We prohibit the unused $s registers, since they
15967 are call-saved, and saving them via a MIPS16 register would
15968 probably waste more time than just reloading the value. */
15971 fixed_regs
[18] = call_used_regs
[18] = 1;
15972 fixed_regs
[19] = call_used_regs
[19] = 1;
15973 fixed_regs
[20] = call_used_regs
[20] = 1;
15974 fixed_regs
[21] = call_used_regs
[21] = 1;
15975 fixed_regs
[22] = call_used_regs
[22] = 1;
15976 fixed_regs
[23] = call_used_regs
[23] = 1;
15977 fixed_regs
[26] = call_used_regs
[26] = 1;
15978 fixed_regs
[27] = call_used_regs
[27] = 1;
15979 fixed_regs
[30] = call_used_regs
[30] = 1;
15981 /* $f20-$f23 are call-clobbered for n64. */
15982 if (mips_abi
== ABI_64
)
15985 for (regno
= FP_REG_FIRST
+ 20; regno
< FP_REG_FIRST
+ 24; regno
++)
15986 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
15988 /* Odd registers in the range $f21-$f31 (inclusive) are call-clobbered
15990 if (mips_abi
== ABI_N32
)
15993 for (regno
= FP_REG_FIRST
+ 21; regno
<= FP_REG_FIRST
+ 31; regno
+=2)
15994 call_really_used_regs
[regno
] = call_used_regs
[regno
] = 1;
15996 /* Make sure that double-register accumulator values are correctly
15997 ordered for the current endianness. */
15998 if (TARGET_LITTLE_ENDIAN
)
16000 unsigned int regno
;
16002 mips_swap_registers (MD_REG_FIRST
);
16003 for (regno
= DSP_ACC_REG_FIRST
; regno
<= DSP_ACC_REG_LAST
; regno
+= 2)
16004 mips_swap_registers (regno
);
16008 /* Initialize vector TARGET to VALS. */
16011 mips_expand_vector_init (rtx target
, rtx vals
)
16013 enum machine_mode mode
;
16014 enum machine_mode inner
;
16015 unsigned int i
, n_elts
;
16018 mode
= GET_MODE (target
);
16019 inner
= GET_MODE_INNER (mode
);
16020 n_elts
= GET_MODE_NUNITS (mode
);
16022 gcc_assert (VECTOR_MODE_P (mode
));
16024 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
), 0);
16025 for (i
= 0; i
< n_elts
; i
++)
16026 emit_move_insn (adjust_address_nv (mem
, inner
, i
* GET_MODE_SIZE (inner
)),
16027 XVECEXP (vals
, 0, i
));
16029 emit_move_insn (target
, mem
);
16032 /* When generating MIPS16 code, we want to allocate $24 (T_REG) before
16033 other registers for instructions for which it is possible. This
16034 encourages the compiler to use CMP in cases where an XOR would
16035 require some register shuffling. */
16038 mips_order_regs_for_local_alloc (void)
16042 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
16043 reg_alloc_order
[i
] = i
;
16047 /* It really doesn't matter where we put register 0, since it is
16048 a fixed register anyhow. */
16049 reg_alloc_order
[0] = 24;
16050 reg_alloc_order
[24] = 0;
16054 /* Implement EH_USES. */
16057 mips_eh_uses (unsigned int regno
)
16059 if (reload_completed
&& !TARGET_ABSOLUTE_JUMPS
)
16061 /* We need to force certain registers to be live in order to handle
16062 PIC long branches correctly. See mips_must_initialize_gp_p for
16064 if (mips_cfun_has_cprestore_slot_p ())
16066 if (regno
== CPRESTORE_SLOT_REGNUM
)
16071 if (cfun
->machine
->global_pointer
== regno
)
16079 /* Implement EPILOGUE_USES. */
16082 mips_epilogue_uses (unsigned int regno
)
16084 /* Say that the epilogue uses the return address register. Note that
16085 in the case of sibcalls, the values "used by the epilogue" are
16086 considered live at the start of the called function. */
16087 if (regno
== RETURN_ADDR_REGNUM
)
16090 /* If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
16091 See the comment above load_call<mode> for details. */
16092 if (TARGET_USE_GOT
&& (regno
) == GOT_VERSION_REGNUM
)
16095 /* An interrupt handler must preserve some registers that are
16096 ordinarily call-clobbered. */
16097 if (cfun
->machine
->interrupt_handler_p
16098 && mips_interrupt_extra_call_saved_reg_p (regno
))
16104 /* A for_each_rtx callback. Stop the search if *X is an AT register. */
16107 mips_at_reg_p (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
16109 return REG_P (*x
) && REGNO (*x
) == AT_REGNUM
;
16112 /* Return true if INSN needs to be wrapped in ".set noat".
16113 INSN has NOPERANDS operands, stored in OPVEC. */
16116 mips_need_noat_wrapper_p (rtx insn
, rtx
*opvec
, int noperands
)
16120 if (recog_memoized (insn
) >= 0)
16121 for (i
= 0; i
< noperands
; i
++)
16122 if (for_each_rtx (&opvec
[i
], mips_at_reg_p
, NULL
))
16127 /* Implement FINAL_PRESCAN_INSN. */
16130 mips_final_prescan_insn (rtx insn
, rtx
*opvec
, int noperands
)
16132 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
16133 mips_push_asm_switch (&mips_noat
);
16136 /* Implement TARGET_ASM_FINAL_POSTSCAN_INSN. */
16139 mips_final_postscan_insn (FILE *file ATTRIBUTE_UNUSED
, rtx insn
,
16140 rtx
*opvec
, int noperands
)
16142 if (mips_need_noat_wrapper_p (insn
, opvec
, noperands
))
16143 mips_pop_asm_switch (&mips_noat
);
16146 /* Return the function that is used to expand the <u>mulsidi3 pattern.
16147 EXT_CODE is the code of the extension used. Return NULL if widening
16148 multiplication shouldn't be used. */
16151 mips_mulsidi3_gen_fn (enum rtx_code ext_code
)
16155 signed_p
= ext_code
== SIGN_EXTEND
;
16158 /* Don't use widening multiplication with MULT when we have DMUL. Even
16159 with the extension of its input operands DMUL is faster. Note that
16160 the extension is not needed for signed multiplication. In order to
16161 ensure that we always remove the redundant sign-extension in this
16162 case we still expand mulsidi3 for DMUL. */
16164 return signed_p
? gen_mulsidi3_64bit_dmul
: NULL
;
16165 if (TARGET_FIX_R4000
)
16167 return signed_p
? gen_mulsidi3_64bit
: gen_umulsidi3_64bit
;
16171 if (TARGET_FIX_R4000
&& !ISA_HAS_DSP
)
16172 return signed_p
? gen_mulsidi3_32bit_r4000
: gen_umulsidi3_32bit_r4000
;
16173 return signed_p
? gen_mulsidi3_32bit
: gen_umulsidi3_32bit
;
16177 /* Return the size in bytes of the trampoline code, padded to
16178 TRAMPOLINE_ALIGNMENT bits. The static chain pointer and target
16179 function address immediately follow. */
16182 mips_trampoline_code_size (void)
16184 if (TARGET_USE_PIC_FN_ADDR_REG
)
16186 else if (ptr_mode
== DImode
)
16188 else if (ISA_HAS_LOAD_DELAY
)
16194 /* Implement TARGET_TRAMPOLINE_INIT. */
16197 mips_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
16199 rtx addr
, end_addr
, high
, low
, opcode
, mem
;
16202 HOST_WIDE_INT end_addr_offset
, static_chain_offset
, target_function_offset
;
16204 /* Work out the offsets of the pointers from the start of the
16205 trampoline code. */
16206 end_addr_offset
= mips_trampoline_code_size ();
16207 static_chain_offset
= end_addr_offset
;
16208 target_function_offset
= static_chain_offset
+ GET_MODE_SIZE (ptr_mode
);
16210 /* Get pointers to the beginning and end of the code block. */
16211 addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
16212 end_addr
= mips_force_binary (Pmode
, PLUS
, addr
, GEN_INT (end_addr_offset
));
16214 #define OP(X) gen_int_mode (X, SImode)
16216 /* Build up the code in TRAMPOLINE. */
16218 if (TARGET_USE_PIC_FN_ADDR_REG
)
16220 /* $25 contains the address of the trampoline. Emit code of the form:
16222 l[wd] $1, target_function_offset($25)
16223 l[wd] $static_chain, static_chain_offset($25)
16226 trampoline
[i
++] = OP (MIPS_LOAD_PTR (AT_REGNUM
,
16227 target_function_offset
,
16228 PIC_FUNCTION_ADDR_REGNUM
));
16229 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16230 static_chain_offset
,
16231 PIC_FUNCTION_ADDR_REGNUM
));
16232 trampoline
[i
++] = OP (MIPS_JR (AT_REGNUM
));
16233 trampoline
[i
++] = OP (MIPS_MOVE (PIC_FUNCTION_ADDR_REGNUM
, AT_REGNUM
));
16235 else if (ptr_mode
== DImode
)
16237 /* It's too cumbersome to create the full 64-bit address, so let's
16243 1: l[wd] $25, target_function_offset - 12($31)
16244 l[wd] $static_chain, static_chain_offset - 12($31)
16248 where 12 is the offset of "1:" from the start of the code block. */
16249 trampoline
[i
++] = OP (MIPS_MOVE (AT_REGNUM
, RETURN_ADDR_REGNUM
));
16250 trampoline
[i
++] = OP (MIPS_BAL (1));
16251 trampoline
[i
++] = OP (MIPS_NOP
);
16252 trampoline
[i
++] = OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16253 target_function_offset
- 12,
16254 RETURN_ADDR_REGNUM
));
16255 trampoline
[i
++] = OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16256 static_chain_offset
- 12,
16257 RETURN_ADDR_REGNUM
));
16258 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16259 trampoline
[i
++] = OP (MIPS_MOVE (RETURN_ADDR_REGNUM
, AT_REGNUM
));
16263 /* If the target has load delays, emit:
16265 lui $1, %hi(end_addr)
16266 lw $25, %lo(end_addr + ...)($1)
16267 lw $static_chain, %lo(end_addr + ...)($1)
16273 lui $1, %hi(end_addr)
16274 lw $25, %lo(end_addr + ...)($1)
16276 lw $static_chain, %lo(end_addr + ...)($1). */
16278 /* Split END_ADDR into %hi and %lo values. Trampolines are aligned
16279 to 64 bits, so the %lo value will have the bottom 3 bits clear. */
16280 high
= expand_simple_binop (SImode
, PLUS
, end_addr
, GEN_INT (0x8000),
16281 NULL
, false, OPTAB_WIDEN
);
16282 high
= expand_simple_binop (SImode
, LSHIFTRT
, high
, GEN_INT (16),
16283 NULL
, false, OPTAB_WIDEN
);
16284 low
= convert_to_mode (SImode
, gen_lowpart (HImode
, end_addr
), true);
16286 /* Emit the LUI. */
16287 opcode
= OP (MIPS_LUI (AT_REGNUM
, 0));
16288 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, high
,
16289 NULL
, false, OPTAB_WIDEN
);
16291 /* Emit the load of the target function. */
16292 opcode
= OP (MIPS_LOAD_PTR (PIC_FUNCTION_ADDR_REGNUM
,
16293 target_function_offset
- end_addr_offset
,
16295 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16296 NULL
, false, OPTAB_WIDEN
);
16298 /* Emit the JR here, if we can. */
16299 if (!ISA_HAS_LOAD_DELAY
)
16300 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16302 /* Emit the load of the static chain register. */
16303 opcode
= OP (MIPS_LOAD_PTR (STATIC_CHAIN_REGNUM
,
16304 static_chain_offset
- end_addr_offset
,
16306 trampoline
[i
++] = expand_simple_binop (SImode
, IOR
, opcode
, low
,
16307 NULL
, false, OPTAB_WIDEN
);
16309 /* Emit the JR, if we couldn't above. */
16310 if (ISA_HAS_LOAD_DELAY
)
16312 trampoline
[i
++] = OP (MIPS_JR (PIC_FUNCTION_ADDR_REGNUM
));
16313 trampoline
[i
++] = OP (MIPS_NOP
);
16319 /* Copy the trampoline code. Leave any padding uninitialized. */
16320 for (j
= 0; j
< i
; j
++)
16322 mem
= adjust_address (m_tramp
, SImode
, j
* GET_MODE_SIZE (SImode
));
16323 mips_emit_move (mem
, trampoline
[j
]);
16326 /* Set up the static chain pointer field. */
16327 mem
= adjust_address (m_tramp
, ptr_mode
, static_chain_offset
);
16328 mips_emit_move (mem
, chain_value
);
16330 /* Set up the target function field. */
16331 mem
= adjust_address (m_tramp
, ptr_mode
, target_function_offset
);
16332 mips_emit_move (mem
, XEXP (DECL_RTL (fndecl
), 0));
16334 /* Flush the code part of the trampoline. */
16335 emit_insn (gen_add3_insn (end_addr
, addr
, GEN_INT (TRAMPOLINE_SIZE
)));
16336 emit_insn (gen_clear_cache (addr
, end_addr
));
16339 /* Implement FUNCTION_PROFILER. */
16341 void mips_function_profiler (FILE *file
)
16344 sorry ("mips16 function profiling");
16345 if (TARGET_LONG_CALLS
)
16347 /* For TARGET_LONG_CALLS use $3 for the address of _mcount. */
16348 if (Pmode
== DImode
)
16349 fprintf (file
, "\tdla\t%s,_mcount\n", reg_names
[3]);
16351 fprintf (file
, "\tla\t%s,_mcount\n", reg_names
[3]);
16353 mips_push_asm_switch (&mips_noat
);
16354 fprintf (file
, "\tmove\t%s,%s\t\t# save current return address\n",
16355 reg_names
[AT_REGNUM
], reg_names
[RETURN_ADDR_REGNUM
]);
16356 /* _mcount treats $2 as the static chain register. */
16357 if (cfun
->static_chain_decl
!= NULL
)
16358 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[2],
16359 reg_names
[STATIC_CHAIN_REGNUM
]);
16360 if (TARGET_MCOUNT_RA_ADDRESS
)
16362 /* If TARGET_MCOUNT_RA_ADDRESS load $12 with the address of the
16363 ra save location. */
16364 if (cfun
->machine
->frame
.ra_fp_offset
== 0)
16365 /* ra not saved, pass zero. */
16366 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[12], reg_names
[0]);
16368 fprintf (file
, "\t%s\t%s," HOST_WIDE_INT_PRINT_DEC
"(%s)\n",
16369 Pmode
== DImode
? "dla" : "la", reg_names
[12],
16370 cfun
->machine
->frame
.ra_fp_offset
,
16371 reg_names
[STACK_POINTER_REGNUM
]);
16373 if (!TARGET_NEWABI
)
16375 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n",
16376 TARGET_64BIT
? "dsubu" : "subu",
16377 reg_names
[STACK_POINTER_REGNUM
],
16378 reg_names
[STACK_POINTER_REGNUM
],
16379 Pmode
== DImode
? 16 : 8);
16381 if (TARGET_LONG_CALLS
)
16382 fprintf (file
, "\tjalr\t%s\n", reg_names
[3]);
16384 fprintf (file
, "\tjal\t_mcount\n");
16385 mips_pop_asm_switch (&mips_noat
);
16386 /* _mcount treats $2 as the static chain register. */
16387 if (cfun
->static_chain_decl
!= NULL
)
16388 fprintf (file
, "\tmove\t%s,%s\n", reg_names
[STATIC_CHAIN_REGNUM
],
16392 /* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
16393 behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
16394 when TARGET_LOONGSON_VECTORS is true. */
16396 static unsigned HOST_WIDE_INT
16397 mips_shift_truncation_mask (enum machine_mode mode
)
16399 if (TARGET_LOONGSON_VECTORS
&& VECTOR_MODE_P (mode
))
16402 return GET_MODE_BITSIZE (mode
) - 1;
16406 /* Initialize the GCC target structure. */
16407 #undef TARGET_ASM_ALIGNED_HI_OP
16408 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
16409 #undef TARGET_ASM_ALIGNED_SI_OP
16410 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
16411 #undef TARGET_ASM_ALIGNED_DI_OP
16412 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
16414 #undef TARGET_OPTION_OVERRIDE
16415 #define TARGET_OPTION_OVERRIDE mips_option_override
16416 #undef TARGET_OPTION_OPTIMIZATION_TABLE
16417 #define TARGET_OPTION_OPTIMIZATION_TABLE mips_option_optimization_table
16419 #undef TARGET_LEGITIMIZE_ADDRESS
16420 #define TARGET_LEGITIMIZE_ADDRESS mips_legitimize_address
16422 #undef TARGET_ASM_FUNCTION_PROLOGUE
16423 #define TARGET_ASM_FUNCTION_PROLOGUE mips_output_function_prologue
16424 #undef TARGET_ASM_FUNCTION_EPILOGUE
16425 #define TARGET_ASM_FUNCTION_EPILOGUE mips_output_function_epilogue
16426 #undef TARGET_ASM_SELECT_RTX_SECTION
16427 #define TARGET_ASM_SELECT_RTX_SECTION mips_select_rtx_section
16428 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
16429 #define TARGET_ASM_FUNCTION_RODATA_SECTION mips_function_rodata_section
16431 #undef TARGET_SCHED_INIT
16432 #define TARGET_SCHED_INIT mips_sched_init
16433 #undef TARGET_SCHED_REORDER
16434 #define TARGET_SCHED_REORDER mips_sched_reorder
16435 #undef TARGET_SCHED_REORDER2
16436 #define TARGET_SCHED_REORDER2 mips_sched_reorder2
16437 #undef TARGET_SCHED_VARIABLE_ISSUE
16438 #define TARGET_SCHED_VARIABLE_ISSUE mips_variable_issue
16439 #undef TARGET_SCHED_ADJUST_COST
16440 #define TARGET_SCHED_ADJUST_COST mips_adjust_cost
16441 #undef TARGET_SCHED_ISSUE_RATE
16442 #define TARGET_SCHED_ISSUE_RATE mips_issue_rate
16443 #undef TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN
16444 #define TARGET_SCHED_INIT_DFA_POST_CYCLE_INSN mips_init_dfa_post_cycle_insn
16445 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
16446 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE mips_dfa_post_advance_cycle
16447 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
16448 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
16449 mips_multipass_dfa_lookahead
16450 #undef TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P
16451 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \
16452 mips_small_register_classes_for_mode_p
16454 #undef TARGET_DEFAULT_TARGET_FLAGS
16455 #define TARGET_DEFAULT_TARGET_FLAGS \
16457 | TARGET_CPU_DEFAULT \
16458 | TARGET_ENDIAN_DEFAULT \
16459 | TARGET_FP_EXCEPTIONS_DEFAULT \
16460 | MASK_CHECK_ZERO_DIV \
16462 #undef TARGET_HANDLE_OPTION
16463 #define TARGET_HANDLE_OPTION mips_handle_option
16465 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
16466 #define TARGET_FUNCTION_OK_FOR_SIBCALL mips_function_ok_for_sibcall
16468 #undef TARGET_INSERT_ATTRIBUTES
16469 #define TARGET_INSERT_ATTRIBUTES mips_insert_attributes
16470 #undef TARGET_MERGE_DECL_ATTRIBUTES
16471 #define TARGET_MERGE_DECL_ATTRIBUTES mips_merge_decl_attributes
16472 #undef TARGET_SET_CURRENT_FUNCTION
16473 #define TARGET_SET_CURRENT_FUNCTION mips_set_current_function
16475 #undef TARGET_VALID_POINTER_MODE
16476 #define TARGET_VALID_POINTER_MODE mips_valid_pointer_mode
16477 #undef TARGET_REGISTER_MOVE_COST
16478 #define TARGET_REGISTER_MOVE_COST mips_register_move_cost
16479 #undef TARGET_MEMORY_MOVE_COST
16480 #define TARGET_MEMORY_MOVE_COST mips_memory_move_cost
16481 #undef TARGET_RTX_COSTS
16482 #define TARGET_RTX_COSTS mips_rtx_costs
16483 #undef TARGET_ADDRESS_COST
16484 #define TARGET_ADDRESS_COST mips_address_cost
16486 #undef TARGET_IN_SMALL_DATA_P
16487 #define TARGET_IN_SMALL_DATA_P mips_in_small_data_p
16489 #undef TARGET_MACHINE_DEPENDENT_REORG
16490 #define TARGET_MACHINE_DEPENDENT_REORG mips_reorg
16492 #undef TARGET_PREFERRED_RELOAD_CLASS
16493 #define TARGET_PREFERRED_RELOAD_CLASS mips_preferred_reload_class
16495 #undef TARGET_ASM_FILE_START
16496 #define TARGET_ASM_FILE_START mips_file_start
16497 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
16498 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
16500 #undef TARGET_INIT_LIBFUNCS
16501 #define TARGET_INIT_LIBFUNCS mips_init_libfuncs
16503 #undef TARGET_BUILD_BUILTIN_VA_LIST
16504 #define TARGET_BUILD_BUILTIN_VA_LIST mips_build_builtin_va_list
16505 #undef TARGET_EXPAND_BUILTIN_VA_START
16506 #define TARGET_EXPAND_BUILTIN_VA_START mips_va_start
16507 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
16508 #define TARGET_GIMPLIFY_VA_ARG_EXPR mips_gimplify_va_arg_expr
16510 #undef TARGET_PROMOTE_FUNCTION_MODE
16511 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
16512 #undef TARGET_PROMOTE_PROTOTYPES
16513 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
16515 #undef TARGET_RETURN_IN_MEMORY
16516 #define TARGET_RETURN_IN_MEMORY mips_return_in_memory
16517 #undef TARGET_RETURN_IN_MSB
16518 #define TARGET_RETURN_IN_MSB mips_return_in_msb
16520 #undef TARGET_ASM_OUTPUT_MI_THUNK
16521 #define TARGET_ASM_OUTPUT_MI_THUNK mips_output_mi_thunk
16522 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
16523 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
16525 #undef TARGET_PRINT_OPERAND
16526 #define TARGET_PRINT_OPERAND mips_print_operand
16527 #undef TARGET_PRINT_OPERAND_ADDRESS
16528 #define TARGET_PRINT_OPERAND_ADDRESS mips_print_operand_address
16529 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
16530 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mips_print_operand_punct_valid_p
16532 #undef TARGET_SETUP_INCOMING_VARARGS
16533 #define TARGET_SETUP_INCOMING_VARARGS mips_setup_incoming_varargs
16534 #undef TARGET_STRICT_ARGUMENT_NAMING
16535 #define TARGET_STRICT_ARGUMENT_NAMING mips_strict_argument_naming
16536 #undef TARGET_MUST_PASS_IN_STACK
16537 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
16538 #undef TARGET_PASS_BY_REFERENCE
16539 #define TARGET_PASS_BY_REFERENCE mips_pass_by_reference
16540 #undef TARGET_CALLEE_COPIES
16541 #define TARGET_CALLEE_COPIES mips_callee_copies
16542 #undef TARGET_ARG_PARTIAL_BYTES
16543 #define TARGET_ARG_PARTIAL_BYTES mips_arg_partial_bytes
16544 #undef TARGET_FUNCTION_ARG
16545 #define TARGET_FUNCTION_ARG mips_function_arg
16546 #undef TARGET_FUNCTION_ARG_ADVANCE
16547 #define TARGET_FUNCTION_ARG_ADVANCE mips_function_arg_advance
16548 #undef TARGET_FUNCTION_ARG_BOUNDARY
16549 #define TARGET_FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
16551 #undef TARGET_MODE_REP_EXTENDED
16552 #define TARGET_MODE_REP_EXTENDED mips_mode_rep_extended
16554 #undef TARGET_VECTOR_MODE_SUPPORTED_P
16555 #define TARGET_VECTOR_MODE_SUPPORTED_P mips_vector_mode_supported_p
16557 #undef TARGET_SCALAR_MODE_SUPPORTED_P
16558 #define TARGET_SCALAR_MODE_SUPPORTED_P mips_scalar_mode_supported_p
16560 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
16561 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE mips_preferred_simd_mode
16563 #undef TARGET_INIT_BUILTINS
16564 #define TARGET_INIT_BUILTINS mips_init_builtins
16565 #undef TARGET_BUILTIN_DECL
16566 #define TARGET_BUILTIN_DECL mips_builtin_decl
16567 #undef TARGET_EXPAND_BUILTIN
16568 #define TARGET_EXPAND_BUILTIN mips_expand_builtin
16570 #undef TARGET_HAVE_TLS
16571 #define TARGET_HAVE_TLS HAVE_AS_TLS
16573 #undef TARGET_CANNOT_FORCE_CONST_MEM
16574 #define TARGET_CANNOT_FORCE_CONST_MEM mips_cannot_force_const_mem
16576 #undef TARGET_ENCODE_SECTION_INFO
16577 #define TARGET_ENCODE_SECTION_INFO mips_encode_section_info
16579 #undef TARGET_ATTRIBUTE_TABLE
16580 #define TARGET_ATTRIBUTE_TABLE mips_attribute_table
16581 /* All our function attributes are related to how out-of-line copies should
16582 be compiled or called. They don't in themselves prevent inlining. */
16583 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
16584 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
16586 #undef TARGET_EXTRA_LIVE_ON_ENTRY
16587 #define TARGET_EXTRA_LIVE_ON_ENTRY mips_extra_live_on_entry
16589 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
16590 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P mips_use_blocks_for_constant_p
16591 #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P
16592 #define TARGET_USE_ANCHORS_FOR_SYMBOL_P mips_use_anchors_for_symbol_p
16594 #undef TARGET_COMP_TYPE_ATTRIBUTES
16595 #define TARGET_COMP_TYPE_ATTRIBUTES mips_comp_type_attributes
16597 #ifdef HAVE_AS_DTPRELWORD
16598 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
16599 #define TARGET_ASM_OUTPUT_DWARF_DTPREL mips_output_dwarf_dtprel
16601 #undef TARGET_DWARF_REGISTER_SPAN
16602 #define TARGET_DWARF_REGISTER_SPAN mips_dwarf_register_span
16604 #undef TARGET_IRA_COVER_CLASSES
16605 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes
16607 #undef TARGET_ASM_FINAL_POSTSCAN_INSN
16608 #define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
16610 #undef TARGET_LEGITIMATE_ADDRESS_P
16611 #define TARGET_LEGITIMATE_ADDRESS_P mips_legitimate_address_p
16613 #undef TARGET_FRAME_POINTER_REQUIRED
16614 #define TARGET_FRAME_POINTER_REQUIRED mips_frame_pointer_required
16616 #undef TARGET_CAN_ELIMINATE
16617 #define TARGET_CAN_ELIMINATE mips_can_eliminate
16619 #undef TARGET_CONDITIONAL_REGISTER_USAGE
16620 #define TARGET_CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage
16622 #undef TARGET_TRAMPOLINE_INIT
16623 #define TARGET_TRAMPOLINE_INIT mips_trampoline_init
16625 #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME
16626 #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
16628 #undef TARGET_SHIFT_TRUNCATION_MASK
16629 #define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask
16631 struct gcc_target targetm
= TARGET_INITIALIZER
;
16633 #include "gt-mips.h"