1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
3 ;; Changes by Michael Meissner, meissner@osf.org
4 ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
5 ;; Brendan Eich, brendan@microunity.com.
6 ;; Copyright (C) 1989, 90-96, 1997 Free Software Foundation, Inc.
8 ;; This file is part of GNU CC.
10 ;; GNU CC is free software; you can redistribute it and/or modify
11 ;; it under the terms of the GNU General Public License as published by
12 ;; the Free Software Foundation; either version 2, or (at your option)
15 ;; GNU CC is distributed in the hope that it will be useful,
16 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ;; GNU General Public License for more details.
20 ;; You should have received a copy of the GNU General Public License
21 ;; along with GNU CC; see the file COPYING. If not, write to
22 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
23 ;; Boston, MA 02111-1307, USA.
25 ;; ??? Currently does not have define_function_unit support for the R8000.
26 ;; Must include new entries for fmadd in addition to existing entries.
30 ;; ....................
34 ;; ....................
36 ;; Classification of each insn.
37 ;; branch conditional branch
38 ;; jump unconditional jump
39 ;; call unconditional call
40 ;; load load instruction(s)
41 ;; store store instruction(s)
42 ;; move data movement within same register set
43 ;; xfer transfer to/from coprocessor
44 ;; hilo transfer of hi/lo registers
45 ;; arith integer arithmetic instruction
46 ;; darith double precision integer arithmetic instructions
47 ;; imul integer multiply
48 ;; idiv integer divide
49 ;; icmp integer compare
50 ;; fadd floating point add/subtract
51 ;; fmul floating point multiply
52 ;; fmadd floating point multiply-add
53 ;; fdiv floating point divide
54 ;; fabs floating point absolute value
55 ;; fneg floating point negation
56 ;; fcmp floating point compare
57 ;; fcvt floating point convert
58 ;; fsqrt floating point square root
59 ;; multi multiword sequence (or user asm statements)
63 "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fmadd,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
64 (const_string "unknown"))
66 ;; Main data type used by the insn
67 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
69 ;; # instructions (4 bytes each)
70 (define_attr "length" "" (const_int 1))
72 ;; whether or not an instruction has a mandatory delay slot
73 (define_attr "dslot" "no,yes"
74 (if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp")
78 ;; Attribute describing the processor. This attribute must match exactly
79 ;; with the processor_type enumeration in mips.h.
81 ;; Attribute describing the processor
82 ;; (define_attr "cpu" "default,r3000,r6000,r4000"
84 ;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
85 ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
86 ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
87 ;; (const_string "default"))))
89 ;; ??? Fix everything that tests this attribute.
91 "default,r3000,r3900,r6000,r4000,r4100,r4300,r4600,r4650,r5000,r8000"
92 (const (symbol_ref "mips_cpu_attr")))
94 ;; Attribute defining whether or not we can use the branch-likely instructions
96 (define_attr "branch_likely" "no,yes"
98 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
100 (const_string "no"))))
103 ;; Describe a user's asm statement.
104 (define_asm_attributes
105 [(set_attr "type" "multi")])
107 ;; whether or not generating calls to position independent functions
108 (define_attr "abicalls" "no,yes"
109 (const (symbol_ref "mips_abicalls_attr")))
113 ;; .........................
115 ;; Delay slots, can't describe load/fcmp/xfer delay slots here
117 ;; .........................
119 (define_delay (eq_attr "type" "branch")
120 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
122 (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))])
124 (define_delay (eq_attr "type" "jump")
125 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
129 (define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
130 [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
136 ;; .........................
140 ;; .........................
142 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
143 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
145 ;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
147 (define_function_unit "memory" 1 0
148 (and (eq_attr "type" "load")
149 (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
152 (define_function_unit "memory" 1 0
153 (and (eq_attr "type" "load")
154 (eq_attr "cpu" "r3000,r3900,r4600,r4650,r4100,r4300,r5000"))
157 (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
159 (define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
161 (define_function_unit "imuldiv" 1 0
162 (eq_attr "type" "hilo")
165 (define_function_unit "imuldiv" 1 0
166 (and (eq_attr "type" "imul")
167 (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
170 (define_function_unit "imuldiv" 1 0
171 (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000,r3900"))
174 (define_function_unit "imuldiv" 1 0
175 (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600"))
178 (define_function_unit "imuldiv" 1 0
179 (and (eq_attr "type" "imul") (eq_attr "cpu" "r4650"))
182 (define_function_unit "imuldiv" 1 0
183 (and (eq_attr "type" "imul")
184 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
187 (define_function_unit "imuldiv" 1 0
188 (and (eq_attr "type" "imul")
189 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
192 (define_function_unit "imuldiv" 1 0
193 (and (eq_attr "type" "imul")
194 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
197 (define_function_unit "imuldiv" 1 0
198 (and (eq_attr "type" "imul")
199 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
202 (define_function_unit "imuldiv" 1 0
203 (and (eq_attr "type" "imul")
204 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
207 (define_function_unit "imuldiv" 1 0
208 (and (eq_attr "type" "idiv")
209 (eq_attr "cpu" "!r3000,r3900,r4000,r4600,r4650,r4100,r4300,r5000"))
212 (define_function_unit "imuldiv" 1 0
213 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000,r3900"))
216 (define_function_unit "imuldiv" 1 0
217 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
220 (define_function_unit "imuldiv" 1 0
221 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
224 (define_function_unit "imuldiv" 1 0
225 (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
228 (define_function_unit "imuldiv" 1 0
229 (and (eq_attr "type" "idiv")
230 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100")))
233 (define_function_unit "imuldiv" 1 0
234 (and (eq_attr "type" "idiv")
235 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100")))
238 (define_function_unit "imuldiv" 1 0
239 (and (eq_attr "type" "idiv")
240 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
243 (define_function_unit "imuldiv" 1 0
244 (and (eq_attr "type" "idiv")
245 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
248 (define_function_unit "imuldiv" 1 0
249 (and (eq_attr "type" "idiv")
250 (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
253 (define_function_unit "imuldiv" 1 0
254 (and (eq_attr "type" "idiv")
255 (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
258 ;; The R4300 does *NOT* have a separate Floating Point Unit, instead
259 ;; the FP hardware is part of the normal ALU circuitry. This means FP
260 ;; instructions affect the pipe-line, and no functional unit
261 ;; parallelism can occur on R4300 processors. To force GCC into coding
262 ;; for only a single functional unit, we force the R4300 FP
263 ;; instructions to be processed in the "imuldiv" unit.
265 (define_function_unit "adder" 1 1
266 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000"))
269 (define_function_unit "adder" 1 1
270 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r3900,r6000"))
273 (define_function_unit "adder" 1 1
274 (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
277 (define_function_unit "adder" 1 1
278 (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r3900,r6000,r4300"))
281 (define_function_unit "adder" 1 1
282 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000,r3900"))
285 (define_function_unit "adder" 1 1
286 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
289 (define_function_unit "adder" 1 1
290 (and (eq_attr "type" "fabs,fneg")
291 (eq_attr "cpu" "!r3000,r3900,r4600,r4650,r4300,r5000"))
294 (define_function_unit "adder" 1 1
295 (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r3900,r4600,r4650,r5000"))
298 (define_function_unit "mult" 1 1
299 (and (eq_attr "type" "fmul")
300 (and (eq_attr "mode" "SF")
301 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
304 (define_function_unit "mult" 1 1
305 (and (eq_attr "type" "fmul")
306 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900,r5000")))
309 (define_function_unit "mult" 1 1
310 (and (eq_attr "type" "fmul")
311 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
314 (define_function_unit "mult" 1 1
315 (and (eq_attr "type" "fmul")
316 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
319 (define_function_unit "mult" 1 1
320 (and (eq_attr "type" "fmul")
321 (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r3900,r6000,r4300,r5000")))
324 (define_function_unit "mult" 1 1
325 (and (eq_attr "type" "fmul")
326 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900,r5000")))
329 (define_function_unit "mult" 1 1
330 (and (eq_attr "type" "fmul")
331 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
334 (define_function_unit "divide" 1 1
335 (and (eq_attr "type" "fdiv")
336 (and (eq_attr "mode" "SF")
337 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300,r5000")))
340 (define_function_unit "divide" 1 1
341 (and (eq_attr "type" "fdiv")
342 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000,r3900")))
345 (define_function_unit "divide" 1 1
346 (and (eq_attr "type" "fdiv")
347 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
350 (define_function_unit "divide" 1 1
351 (and (eq_attr "type" "fdiv")
352 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
355 (define_function_unit "divide" 1 1
356 (and (eq_attr "type" "fdiv")
357 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
360 (define_function_unit "divide" 1 1
361 (and (eq_attr "type" "fdiv")
362 (and (eq_attr "mode" "DF")
363 (eq_attr "cpu" "!r3000,r3900,r6000,r4600,r4650,r4300")))
366 (define_function_unit "divide" 1 1
367 (and (eq_attr "type" "fdiv")
368 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000,r3900")))
371 (define_function_unit "divide" 1 1
372 (and (eq_attr "type" "fdiv")
373 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
376 (define_function_unit "divide" 1 1
377 (and (eq_attr "type" "fdiv")
378 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
381 ;;; ??? Is this number right?
382 (define_function_unit "divide" 1 1
383 (and (eq_attr "type" "fsqrt")
384 (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
387 (define_function_unit "divide" 1 1
388 (and (eq_attr "type" "fsqrt")
389 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
392 (define_function_unit "divide" 1 1
393 (and (eq_attr "type" "fsqrt")
394 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
397 ;;; ??? Is this number right?
398 (define_function_unit "divide" 1 1
399 (and (eq_attr "type" "fsqrt")
400 (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
403 (define_function_unit "divide" 1 1
404 (and (eq_attr "type" "fsqrt")
405 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
408 (define_function_unit "divide" 1 1
409 (and (eq_attr "type" "fsqrt")
410 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
413 ;; R4300 FP instruction classes treated as part of the "imuldiv"
416 (define_function_unit "imuldiv" 1 0
417 (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
420 (define_function_unit "imuldiv" 1 0
421 (and (eq_attr "type" "fcmp,fabs,fneg") (eq_attr "cpu" "r4300"))
424 (define_function_unit "imuldiv" 1 0
425 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
427 (define_function_unit "imuldiv" 1 0
428 (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
431 (define_function_unit "imuldiv" 1 0
432 (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
433 (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
435 (define_function_unit "imuldiv" 1 0
436 (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt"))
437 (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
440 ;; The following functional units do not use the cpu type, and use
441 ;; much less memory in genattrtab.c.
443 ;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
444 ;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
446 ;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
448 ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
449 ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
451 ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
452 ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
454 ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
455 ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
457 ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
458 ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
460 ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
461 ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
463 ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
464 ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
468 ;; ....................
472 ;; ....................
475 (define_insn "adddf3"
476 [(set (match_operand:DF 0 "register_operand" "=f")
477 (plus:DF (match_operand:DF 1 "register_operand" "f")
478 (match_operand:DF 2 "register_operand" "f")))]
479 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
481 [(set_attr "type" "fadd")
482 (set_attr "mode" "DF")
483 (set_attr "length" "1")])
485 (define_insn "addsf3"
486 [(set (match_operand:SF 0 "register_operand" "=f")
487 (plus:SF (match_operand:SF 1 "register_operand" "f")
488 (match_operand:SF 2 "register_operand" "f")))]
491 [(set_attr "type" "fadd")
492 (set_attr "mode" "SF")
493 (set_attr "length" "1")])
495 (define_expand "addsi3"
496 [(set (match_operand:SI 0 "register_operand" "=d")
497 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
498 (match_operand:SI 2 "arith_operand" "dI")))]
502 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
503 operands[2] = force_reg (SImode, operands[2]);
506 (define_insn "addsi3_internal"
507 [(set (match_operand:SI 0 "register_operand" "=d")
508 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
509 (match_operand:SI 2 "arith_operand" "dI")))]
510 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768"
512 [(set_attr "type" "arith")
513 (set_attr "mode" "SI")
514 (set_attr "length" "1")])
516 (define_expand "adddi3"
517 [(parallel [(set (match_operand:DI 0 "register_operand" "")
518 (plus:DI (match_operand:DI 1 "se_register_operand" "")
519 (match_operand:DI 2 "se_arith_operand" "")))
520 (clobber (match_dup 3))])]
521 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
524 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
525 operands[2] = force_reg (DImode, operands[2]);
529 emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
534 operands[3] = gen_reg_rtx (SImode);
537 (define_insn "adddi3_internal_1"
538 [(set (match_operand:DI 0 "register_operand" "=d,&d")
539 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
540 (match_operand:DI 2 "register_operand" "d,d")))
541 (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
542 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
545 return (REGNO (operands[0]) == REGNO (operands[1])
546 && REGNO (operands[0]) == REGNO (operands[2]))
547 ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
548 : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
550 [(set_attr "type" "darith")
551 (set_attr "mode" "DI")
552 (set_attr "length" "4")])
555 [(set (match_operand:DI 0 "register_operand" "")
556 (plus:DI (match_operand:DI 1 "register_operand" "")
557 (match_operand:DI 2 "register_operand" "")))
558 (clobber (match_operand:SI 3 "register_operand" ""))]
559 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
560 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
561 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
562 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
563 && (REGNO (operands[0]) != REGNO (operands[1])
564 || REGNO (operands[0]) != REGNO (operands[2]))"
566 [(set (subreg:SI (match_dup 0) 0)
567 (plus:SI (subreg:SI (match_dup 1) 0)
568 (subreg:SI (match_dup 2) 0)))
571 (ltu:SI (subreg:SI (match_dup 0) 0)
572 (subreg:SI (match_dup 2) 0)))
574 (set (subreg:SI (match_dup 0) 1)
575 (plus:SI (subreg:SI (match_dup 1) 1)
576 (subreg:SI (match_dup 2) 1)))
578 (set (subreg:SI (match_dup 0) 1)
579 (plus:SI (subreg:SI (match_dup 0) 1)
584 [(set (match_operand:DI 0 "register_operand" "")
585 (plus:DI (match_operand:DI 1 "register_operand" "")
586 (match_operand:DI 2 "register_operand" "")))
587 (clobber (match_operand:SI 3 "register_operand" ""))]
588 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
589 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
590 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
591 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
592 && (REGNO (operands[0]) != REGNO (operands[1])
593 || REGNO (operands[0]) != REGNO (operands[2]))"
595 [(set (subreg:SI (match_dup 0) 1)
596 (plus:SI (subreg:SI (match_dup 1) 1)
597 (subreg:SI (match_dup 2) 1)))
600 (ltu:SI (subreg:SI (match_dup 0) 1)
601 (subreg:SI (match_dup 2) 1)))
603 (set (subreg:SI (match_dup 0) 0)
604 (plus:SI (subreg:SI (match_dup 1) 0)
605 (subreg:SI (match_dup 2) 0)))
607 (set (subreg:SI (match_dup 0) 0)
608 (plus:SI (subreg:SI (match_dup 0) 0)
612 (define_insn "adddi3_internal_2"
613 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
614 (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
615 (match_operand:DI 2 "small_int" "P,J,N")))
616 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
617 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
619 addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
620 move\\t%L0,%L1\;move\\t%M0,%M1
621 subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
622 [(set_attr "type" "darith")
623 (set_attr "mode" "DI")
624 (set_attr "length" "3,2,4")])
627 [(set (match_operand:DI 0 "register_operand" "")
628 (plus:DI (match_operand:DI 1 "register_operand" "")
629 (match_operand:DI 2 "small_int" "")))
630 (clobber (match_operand:SI 3 "register_operand" "=d"))]
631 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
632 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
633 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
634 && INTVAL (operands[2]) > 0"
636 [(set (subreg:SI (match_dup 0) 0)
637 (plus:SI (subreg:SI (match_dup 1) 0)
641 (ltu:SI (subreg:SI (match_dup 0) 0)
644 (set (subreg:SI (match_dup 0) 1)
645 (plus:SI (subreg:SI (match_dup 1) 1)
650 [(set (match_operand:DI 0 "register_operand" "")
651 (plus:DI (match_operand:DI 1 "register_operand" "")
652 (match_operand:DI 2 "small_int" "")))
653 (clobber (match_operand:SI 3 "register_operand" "=d"))]
654 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
655 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
656 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
657 && INTVAL (operands[2]) > 0"
659 [(set (subreg:SI (match_dup 0) 1)
660 (plus:SI (subreg:SI (match_dup 1) 1)
664 (ltu:SI (subreg:SI (match_dup 0) 1)
667 (set (subreg:SI (match_dup 0) 0)
668 (plus:SI (subreg:SI (match_dup 1) 0)
672 (define_insn "adddi3_internal_3"
673 [(set (match_operand:DI 0 "register_operand" "=d")
674 (plus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
675 (match_operand:DI 2 "se_arith_operand" "dI")))]
676 "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
679 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
680 ? \"dsubu\\t%0,%z1,%n2\"
681 : \"daddu\\t%0,%z1,%2\";
683 [(set_attr "type" "darith")
684 (set_attr "mode" "DI")
685 (set_attr "length" "1")])
688 (define_insn "addsi3_internal_2"
689 [(set (match_operand:DI 0 "register_operand" "=d")
690 (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
691 (match_operand:SI 2 "arith_operand" "dI"))))]
692 "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
695 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
696 ? \"subu\\t%0,%z1,%n2\"
697 : \"addu\\t%0,%z1,%2\";
699 [(set_attr "type" "arith")
700 (set_attr "mode" "SI")
701 (set_attr "length" "1")])
705 ;; ....................
709 ;; ....................
712 (define_insn "subdf3"
713 [(set (match_operand:DF 0 "register_operand" "=f")
714 (minus:DF (match_operand:DF 1 "register_operand" "f")
715 (match_operand:DF 2 "register_operand" "f")))]
716 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
718 [(set_attr "type" "fadd")
719 (set_attr "mode" "DF")
720 (set_attr "length" "1")])
722 (define_insn "subsf3"
723 [(set (match_operand:SF 0 "register_operand" "=f")
724 (minus:SF (match_operand:SF 1 "register_operand" "f")
725 (match_operand:SF 2 "register_operand" "f")))]
728 [(set_attr "type" "fadd")
729 (set_attr "mode" "SF")
730 (set_attr "length" "1")])
732 (define_expand "subsi3"
733 [(set (match_operand:SI 0 "register_operand" "=d")
734 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
735 (match_operand:SI 2 "arith_operand" "dI")))]
739 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
740 operands[2] = force_reg (SImode, operands[2]);
743 (define_insn "subsi3_internal"
744 [(set (match_operand:SI 0 "register_operand" "=d")
745 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
746 (match_operand:SI 2 "arith_operand" "dI")))]
747 "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768"
749 [(set_attr "type" "arith")
750 (set_attr "mode" "SI")
751 (set_attr "length" "1")])
753 (define_expand "subdi3"
754 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
755 (minus:DI (match_operand:DI 1 "se_register_operand" "d")
756 (match_operand:DI 2 "se_register_operand" "d")))
757 (clobber (match_dup 3))])]
758 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
763 emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
768 operands[3] = gen_reg_rtx (SImode);
771 (define_insn "subdi3_internal"
772 [(set (match_operand:DI 0 "register_operand" "=d")
773 (minus:DI (match_operand:DI 1 "register_operand" "d")
774 (match_operand:DI 2 "register_operand" "d")))
775 (clobber (match_operand:SI 3 "register_operand" "=d"))]
776 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
777 "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
778 [(set_attr "type" "darith")
779 (set_attr "mode" "DI")
780 (set_attr "length" "4")])
783 [(set (match_operand:DI 0 "register_operand" "")
784 (minus:DI (match_operand:DI 1 "register_operand" "")
785 (match_operand:DI 2 "register_operand" "")))
786 (clobber (match_operand:SI 3 "register_operand" ""))]
787 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
788 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
789 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
790 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
793 (ltu:SI (subreg:SI (match_dup 1) 0)
794 (subreg:SI (match_dup 2) 0)))
796 (set (subreg:SI (match_dup 0) 0)
797 (minus:SI (subreg:SI (match_dup 1) 0)
798 (subreg:SI (match_dup 2) 0)))
800 (set (subreg:SI (match_dup 0) 1)
801 (minus:SI (subreg:SI (match_dup 1) 1)
802 (subreg:SI (match_dup 2) 1)))
804 (set (subreg:SI (match_dup 0) 1)
805 (minus:SI (subreg:SI (match_dup 0) 1)
810 [(set (match_operand:DI 0 "register_operand" "")
811 (minus:DI (match_operand:DI 1 "register_operand" "")
812 (match_operand:DI 2 "register_operand" "")))
813 (clobber (match_operand:SI 3 "register_operand" ""))]
814 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
815 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
816 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
817 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
820 (ltu:SI (subreg:SI (match_dup 1) 1)
821 (subreg:SI (match_dup 2) 1)))
823 (set (subreg:SI (match_dup 0) 1)
824 (minus:SI (subreg:SI (match_dup 1) 1)
825 (subreg:SI (match_dup 2) 1)))
827 (set (subreg:SI (match_dup 0) 0)
828 (minus:SI (subreg:SI (match_dup 1) 0)
829 (subreg:SI (match_dup 2) 0)))
831 (set (subreg:SI (match_dup 0) 0)
832 (minus:SI (subreg:SI (match_dup 0) 0)
836 (define_insn "subdi3_internal_2"
837 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
838 (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
839 (match_operand:DI 2 "small_int" "P,J,N")))
840 (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
841 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
843 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
844 move\\t%L0,%L1\;move\\t%M0,%M1
845 sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
846 [(set_attr "type" "darith")
847 (set_attr "mode" "DI")
848 (set_attr "length" "3,2,4")])
851 [(set (match_operand:DI 0 "register_operand" "")
852 (minus:DI (match_operand:DI 1 "register_operand" "")
853 (match_operand:DI 2 "small_int" "")))
854 (clobber (match_operand:SI 3 "register_operand" ""))]
855 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
856 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
857 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
858 && INTVAL (operands[2]) > 0"
861 (ltu:SI (subreg:SI (match_dup 1) 0)
864 (set (subreg:SI (match_dup 0) 0)
865 (minus:SI (subreg:SI (match_dup 1) 0)
868 (set (subreg:SI (match_dup 0) 1)
869 (minus:SI (subreg:SI (match_dup 1) 1)
874 [(set (match_operand:DI 0 "register_operand" "")
875 (minus:DI (match_operand:DI 1 "register_operand" "")
876 (match_operand:DI 2 "small_int" "")))
877 (clobber (match_operand:SI 3 "register_operand" ""))]
878 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
879 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
880 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
881 && INTVAL (operands[2]) > 0"
884 (ltu:SI (subreg:SI (match_dup 1) 1)
887 (set (subreg:SI (match_dup 0) 1)
888 (minus:SI (subreg:SI (match_dup 1) 1)
891 (set (subreg:SI (match_dup 0) 0)
892 (minus:SI (subreg:SI (match_dup 1) 0)
896 (define_insn "subdi3_internal_3"
897 [(set (match_operand:DI 0 "register_operand" "=d")
898 (minus:DI (match_operand:DI 1 "se_reg_or_0_operand" "dJ")
899 (match_operand:DI 2 "se_arith_operand" "dI")))]
900 "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
903 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
904 ? \"daddu\\t%0,%z1,%n2\"
905 : \"dsubu\\t%0,%z1,%2\";
907 [(set_attr "type" "darith")
908 (set_attr "mode" "DI")
909 (set_attr "length" "1")])
912 (define_insn "subsi3_internal_2"
913 [(set (match_operand:DI 0 "register_operand" "=d")
914 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
915 (match_operand:SI 2 "arith_operand" "dI"))))]
916 "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
919 return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
920 ? \"addu\\t%0,%z1,%n2\"
921 : \"subu\\t%0,%z1,%2\";
923 [(set_attr "type" "arith")
924 (set_attr "mode" "DI")
925 (set_attr "length" "1")])
929 ;; ....................
933 ;; ....................
936 ;; Early Vr4300 silicon has a CPU bug where multiplies with certain
937 ;; operands may corrupt immediately following multiplies. This is a
938 ;; simple fix to insert NOPs.
940 (define_expand "muldf3"
941 [(set (match_operand:DF 0 "register_operand" "=f")
942 (mult:DF (match_operand:DF 1 "register_operand" "f")
943 (match_operand:DF 2 "register_operand" "f")))]
944 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
947 if (mips_cpu != PROCESSOR_R4300)
948 emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
950 emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
954 (define_insn "muldf3_internal"
955 [(set (match_operand:DF 0 "register_operand" "=f")
956 (mult:DF (match_operand:DF 1 "register_operand" "f")
957 (match_operand:DF 2 "register_operand" "f")))]
958 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu != PROCESSOR_R4300"
960 [(set_attr "type" "fmul")
961 (set_attr "mode" "DF")
962 (set_attr "length" "1")])
964 (define_insn "muldf3_r4300"
965 [(set (match_operand:DF 0 "register_operand" "=f")
966 (mult:DF (match_operand:DF 1 "register_operand" "f")
967 (match_operand:DF 2 "register_operand" "f")))]
968 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && mips_cpu == PROCESSOR_R4300"
971 output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
972 if (TARGET_4300_MUL_FIX)
973 output_asm_insn (\"nop\", operands);
976 [(set_attr "type" "fmul")
977 (set_attr "mode" "DF")
978 (set_attr "length" "2")]) ;; mul.d + nop
980 (define_expand "mulsf3"
981 [(set (match_operand:SF 0 "register_operand" "=f")
982 (mult:SF (match_operand:SF 1 "register_operand" "f")
983 (match_operand:SF 2 "register_operand" "f")))]
987 if (mips_cpu != PROCESSOR_R4300)
988 emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
990 emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
994 (define_insn "mulsf3_internal"
995 [(set (match_operand:SF 0 "register_operand" "=f")
996 (mult:SF (match_operand:SF 1 "register_operand" "f")
997 (match_operand:SF 2 "register_operand" "f")))]
998 "TARGET_HARD_FLOAT && mips_cpu != PROCESSOR_R4300"
1000 [(set_attr "type" "fmul")
1001 (set_attr "mode" "SF")
1002 (set_attr "length" "1")])
1004 (define_insn "mulsf3_r4300"
1005 [(set (match_operand:SF 0 "register_operand" "=f")
1006 (mult:SF (match_operand:SF 1 "register_operand" "f")
1007 (match_operand:SF 2 "register_operand" "f")))]
1008 "TARGET_HARD_FLOAT && mips_cpu == PROCESSOR_R4300"
1011 output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
1012 if (TARGET_4300_MUL_FIX)
1013 output_asm_insn (\"nop\", operands);
1016 [(set_attr "type" "fmul")
1017 (set_attr "mode" "SF")
1018 (set_attr "length" "2")]) ;; mul.s + nop
1020 ;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
1021 ;; a multiply is in progress, it may give an incorrect result. Avoid
1022 ;; this by keeping the mflo with the mult on the R4000.
1024 (define_expand "mulsi3"
1025 [(set (match_operand:SI 0 "register_operand" "=l")
1026 (mult:SI (match_operand:SI 1 "register_operand" "d")
1027 (match_operand:SI 2 "register_operand" "d")))
1028 (clobber (match_scratch:SI 3 "=h"))
1029 (clobber (match_scratch:SI 4 "=a"))]
1034 emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
1035 else if (TARGET_MAD)
1036 emit_insn (gen_mulsi3_r4650 (operands[0], operands[1], operands[2]));
1037 else if (mips_cpu != PROCESSOR_R4000)
1038 emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
1040 emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
1044 (define_insn "mulsi3_mult3"
1045 [(set (match_operand:SI 0 "register_operand" "=d")
1046 (mult:SI (match_operand:SI 1 "register_operand" "d")
1047 (match_operand:SI 2 "register_operand" "d")))
1048 (clobber (match_scratch:SI 3 "=h"))
1049 (clobber (match_scratch:SI 4 "=l"))
1050 (clobber (match_scratch:SI 5 "=a"))]
1053 [(set_attr "type" "imul")
1054 (set_attr "mode" "SI")
1055 (set_attr "length" "1")])
1057 (define_insn "mulsi3_internal"
1058 [(set (match_operand:SI 0 "register_operand" "=l")
1059 (mult:SI (match_operand:SI 1 "register_operand" "d")
1060 (match_operand:SI 2 "register_operand" "d")))
1061 (clobber (match_scratch:SI 3 "=h"))
1062 (clobber (match_scratch:SI 4 "=a"))]
1063 "mips_cpu != PROCESSOR_R4000"
1065 [(set_attr "type" "imul")
1066 (set_attr "mode" "SI")
1067 (set_attr "length" "1")])
1069 (define_insn "mulsi3_r4000"
1070 [(set (match_operand:SI 0 "register_operand" "=d")
1071 (mult:SI (match_operand:SI 1 "register_operand" "d")
1072 (match_operand:SI 2 "register_operand" "d")))
1073 (clobber (match_scratch:SI 3 "=h"))
1074 (clobber (match_scratch:SI 4 "=l"))
1075 (clobber (match_scratch:SI 5 "=a"))]
1076 "mips_cpu == PROCESSOR_R4000"
1081 xoperands[0] = operands[0];
1082 xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM);
1084 output_asm_insn (\"mult\\t%1,%2\", operands);
1085 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1088 [(set_attr "type" "imul")
1089 (set_attr "mode" "SI")
1090 (set_attr "length" "3")]) ;; mult + mflo + delay
1092 (define_insn "mulsi3_r4650"
1093 [(set (match_operand:SI 0 "register_operand" "=d")
1094 (mult:SI (match_operand:SI 1 "register_operand" "d")
1095 (match_operand:SI 2 "register_operand" "d")))
1096 (clobber (match_scratch:SI 3 "=h"))
1097 (clobber (match_scratch:SI 4 "=l"))
1098 (clobber (match_scratch:SI 5 "=a"))]
1101 [(set_attr "type" "imul")
1102 (set_attr "mode" "SI")
1103 (set_attr "length" "1")])
1105 (define_expand "muldi3"
1106 [(set (match_operand:DI 0 "register_operand" "=l")
1107 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
1108 (match_operand:DI 2 "register_operand" "d")))
1109 (clobber (match_scratch:DI 3 "=h"))
1110 (clobber (match_scratch:DI 4 "=a"))]
1114 if (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000)
1115 emit_insn (gen_muldi3_internal2 (operands[0], operands[1], operands[2]));
1117 emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
1121 ;; Don't accept both operands using se_register_operand, because if
1122 ;; both operands are sign extended we would prefer to use mult in the
1123 ;; mulsidi3 pattern. Commutativity should permit either operand to be
1126 (define_insn "muldi3_internal"
1127 [(set (match_operand:DI 0 "register_operand" "=l")
1128 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
1129 (match_operand:DI 2 "register_operand" "d")))
1130 (clobber (match_scratch:DI 3 "=h"))
1131 (clobber (match_scratch:DI 4 "=a"))]
1132 "TARGET_64BIT && mips_cpu != PROCESSOR_R4000"
1134 [(set_attr "type" "imul")
1135 (set_attr "mode" "DI")
1136 (set_attr "length" "1")])
1138 (define_insn "muldi3_internal2"
1139 [(set (match_operand:DI 0 "register_operand" "=d")
1140 (mult:DI (match_operand:DI 1 "se_register_operand" "d")
1141 (match_operand:DI 2 "register_operand" "d")))
1142 (clobber (match_scratch:DI 3 "=h"))
1143 (clobber (match_scratch:DI 4 "=l"))
1144 (clobber (match_scratch:DI 5 "=a"))]
1145 "TARGET_64BIT && (GENERATE_MULT3 || mips_cpu == PROCESSOR_R4000)"
1149 output_asm_insn (\"dmult\\t%0,%1,%2\", operands);
1154 xoperands[0] = operands[0];
1155 xoperands[1] = gen_rtx (REG, DImode, LO_REGNUM);
1157 output_asm_insn (\"dmult\\t%1,%2\", operands);
1158 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1162 [(set_attr "type" "imul")
1163 (set_attr "mode" "DI")
1164 (set (attr "length")
1165 (if_then_else (ne (symbol_ref "GENERATE_MULT3") (const_int 0))
1167 (const_int 3)))]) ;; mult + mflo + delay
1169 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1171 (define_expand "mulsidi3"
1172 [(set (match_operand:DI 0 "register_operand" "=x")
1173 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1174 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1179 emit_insn (gen_mulsidi3_64bit (operands[0], operands[1], operands[2]));
1181 emit_insn (gen_mulsidi3_internal (operands[0], operands[1], operands[2]));
1185 (define_insn "mulsidi3_internal"
1186 [(set (match_operand:DI 0 "register_operand" "=x")
1187 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1188 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1189 (clobber (match_scratch:SI 3 "=a"))]
1192 [(set_attr "type" "imul")
1193 (set_attr "mode" "SI")
1194 (set_attr "length" "1")])
1196 (define_insn "mulsidi3_64bit"
1197 [(set (match_operand:DI 0 "register_operand" "=a")
1198 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1199 (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1200 (clobber (match_scratch:DI 3 "=l"))
1201 (clobber (match_scratch:DI 4 "=h"))]
1204 [(set_attr "type" "imul")
1205 (set_attr "mode" "SI")
1206 (set_attr "length" "1")])
1208 (define_insn "smulsi3_highpart"
1209 [(set (match_operand:SI 0 "register_operand" "=h")
1211 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
1212 (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
1214 (clobber (match_scratch:SI 3 "=l"))
1215 (clobber (match_scratch:SI 4 "=a"))]
1218 [(set_attr "type" "imul")
1219 (set_attr "mode" "SI")
1220 (set_attr "length" "1")])
1222 (define_expand "umulsidi3"
1223 [(set (match_operand:DI 0 "register_operand" "=x")
1224 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1225 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1230 emit_insn (gen_umulsidi3_64bit (operands[0], operands[1], operands[2]));
1232 emit_insn (gen_umulsidi3_internal (operands[0], operands[1], operands[2]));
1236 (define_insn "umulsidi3_internal"
1237 [(set (match_operand:DI 0 "register_operand" "=x")
1238 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1239 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1240 (clobber (match_scratch:SI 3 "=a"))]
1243 [(set_attr "type" "imul")
1244 (set_attr "mode" "SI")
1245 (set_attr "length" "1")])
1247 (define_insn "umulsidi3_64bit"
1248 [(set (match_operand:DI 0 "register_operand" "=a")
1249 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1250 (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1251 (clobber (match_scratch:DI 3 "=l"))
1252 (clobber (match_scratch:DI 4 "=h"))]
1255 [(set_attr "type" "imul")
1256 (set_attr "mode" "SI")
1257 (set_attr "length" "1")])
1259 (define_insn "umulsi3_highpart"
1260 [(set (match_operand:SI 0 "register_operand" "=h")
1262 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
1263 (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
1265 (clobber (match_scratch:SI 3 "=l"))
1266 (clobber (match_scratch:SI 4 "=a"))]
1269 [(set_attr "type" "imul")
1270 (set_attr "mode" "SI")
1271 (set_attr "length" "1")])
1273 (define_insn "smuldi3_highpart"
1274 [(set (match_operand:DI 0 "register_operand" "=h")
1276 (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
1277 (sign_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
1279 (clobber (match_scratch:DI 3 "=l"))
1280 (clobber (match_scratch:DI 4 "=a"))]
1283 [(set_attr "type" "imul")
1284 (set_attr "mode" "DI")
1285 (set_attr "length" "1")])
1287 (define_insn "umuldi3_highpart"
1288 [(set (match_operand:DI 0 "register_operand" "=h")
1290 (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "se_register_operand" "d"))
1291 (zero_extend:TI (match_operand:DI 2 "se_register_operand" "d")))
1293 (clobber (match_scratch:DI 3 "=l"))
1294 (clobber (match_scratch:DI 4 "=a"))]
1297 [(set_attr "type" "imul")
1298 (set_attr "mode" "DI")
1299 (set_attr "length" "1")])
1301 ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
1302 ;; instruction. The HI/LO registers are used as a 64 bit accumulator.
1304 (define_insn "madsi"
1305 [(set (match_operand:SI 0 "register_operand" "+l")
1306 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1307 (match_operand:SI 2 "register_operand" "d"))
1309 (clobber (match_scratch:SI 3 "=h"))
1310 (clobber (match_scratch:SI 4 "=a"))]
1311 "TARGET_MAD || GENERATE_MADD"
1315 return \"mad\\t%1,%2\";
1317 return \"madd\\t%1,%2\";
1319 [(set_attr "type" "imul")
1320 (set_attr "mode" "SI")
1321 (set_attr "length" "1")])
1323 (define_insn "maddi"
1324 [(set (match_operand:DI 0 "register_operand" "+x")
1325 (plus:DI (mult:DI (sign_extend:DI
1326 (match_operand:SI 1 "register_operand" "d"))
1328 (match_operand:SI 2 "register_operand" "d")))
1330 (clobber (match_scratch:SI 3 "=a"))]
1331 "TARGET_MAD && ! TARGET_64BIT"
1333 [(set_attr "type" "imul")
1334 (set_attr "mode" "SI")
1335 (set_attr "length" "1")])
1337 (define_insn "maddi_64bit"
1338 [(set (match_operand:DI 0 "register_operand" "+a")
1339 (plus:DI (mult:DI (sign_extend:DI
1340 (match_operand:SI 1 "register_operand" "d"))
1342 (match_operand:SI 2 "register_operand" "d")))
1344 (clobber (match_scratch:DI 3 "=l"))
1345 (clobber (match_scratch:DI 4 "=h"))]
1346 "TARGET_MAD && TARGET_64BIT"
1348 [(set_attr "type" "imul")
1349 (set_attr "mode" "SI")
1350 (set_attr "length" "1")])
1352 (define_insn "umaddi"
1353 [(set (match_operand:DI 0 "register_operand" "+x")
1354 (plus:DI (mult:DI (zero_extend:DI
1355 (match_operand:SI 1 "register_operand" "d"))
1357 (match_operand:SI 2 "register_operand" "d")))
1359 (clobber (match_scratch:SI 3 "=a"))]
1360 "TARGET_MAD && ! TARGET_64BIT"
1362 [(set_attr "type" "imul")
1363 (set_attr "mode" "SI")
1364 (set_attr "length" "1")])
1366 (define_insn "umaddi_64bit"
1367 [(set (match_operand:DI 0 "register_operand" "+a")
1368 (plus:DI (mult:DI (zero_extend:DI
1369 (match_operand:SI 1 "register_operand" "d"))
1371 (match_operand:SI 2 "register_operand" "d")))
1373 (clobber (match_scratch:DI 3 "=l"))
1374 (clobber (match_scratch:DI 4 "=h"))]
1375 "TARGET_MAD && TARGET_64BIT"
1377 [(set_attr "type" "imul")
1378 (set_attr "mode" "SI")
1379 (set_attr "length" "1")])
1381 (define_insn "madd3"
1382 [(set (match_operand:SI 0 "register_operand" "=d")
1383 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1384 (match_operand:SI 2 "register_operand" "d"))
1385 (match_operand:SI 3 "register_operand" "l")))
1386 (clobber (match_scratch:SI 4 "=l"))
1387 (clobber (match_scratch:SI 5 "=h"))
1388 (clobber (match_scratch:SI 6 "=a"))]
1391 [(set_attr "type" "imul")
1392 (set_attr "mode" "SI")
1393 (set_attr "length" "1")])
1395 ;; Floating point multiply accumulate instructions.
1398 [(set (match_operand:DF 0 "register_operand" "=f")
1399 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
1400 (match_operand:DF 2 "register_operand" "f"))
1401 (match_operand:DF 3 "register_operand" "f")))]
1402 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1403 "madd.d\\t%0,%3,%1,%2"
1404 [(set_attr "type" "fmadd")
1405 (set_attr "mode" "DF")
1406 (set_attr "length" "1")])
1409 [(set (match_operand:SF 0 "register_operand" "=f")
1410 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
1411 (match_operand:SF 2 "register_operand" "f"))
1412 (match_operand:SF 3 "register_operand" "f")))]
1413 "mips_isa >= 4 && TARGET_HARD_FLOAT"
1414 "madd.s\\t%0,%3,%1,%2"
1415 [(set_attr "type" "fmadd")
1416 (set_attr "mode" "SF")
1417 (set_attr "length" "1")])
1420 [(set (match_operand:DF 0 "register_operand" "=f")
1421 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
1422 (match_operand:DF 2 "register_operand" "f"))
1423 (match_operand:DF 3 "register_operand" "f")))]
1424 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1425 "msub.d\\t%0,%3,%1,%2"
1426 [(set_attr "type" "fmadd")
1427 (set_attr "mode" "DF")
1428 (set_attr "length" "1")])
1431 [(set (match_operand:SF 0 "register_operand" "=f")
1432 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
1433 (match_operand:SF 2 "register_operand" "f"))
1434 (match_operand:SF 3 "register_operand" "f")))]
1436 "mips_isa >= 4 && TARGET_HARD_FLOAT"
1437 "msub.s\\t%0,%3,%1,%2"
1438 [(set_attr "type" "fmadd")
1439 (set_attr "mode" "SF")
1440 (set_attr "length" "1")])
1443 [(set (match_operand:DF 0 "register_operand" "=f")
1444 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
1445 (match_operand:DF 2 "register_operand" "f"))
1446 (match_operand:DF 3 "register_operand" "f"))))]
1447 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1448 "nmadd.d\\t%0,%3,%1,%2"
1449 [(set_attr "type" "fmadd")
1450 (set_attr "mode" "DF")
1451 (set_attr "length" "1")])
1454 [(set (match_operand:SF 0 "register_operand" "=f")
1455 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
1456 (match_operand:SF 2 "register_operand" "f"))
1457 (match_operand:SF 3 "register_operand" "f"))))]
1458 "mips_isa >= 4 && TARGET_HARD_FLOAT"
1459 "nmadd.s\\t%0,%3,%1,%2"
1460 [(set_attr "type" "fmadd")
1461 (set_attr "mode" "SF")
1462 (set_attr "length" "1")])
1465 [(set (match_operand:DF 0 "register_operand" "=f")
1466 (minus:DF (match_operand:DF 1 "register_operand" "f")
1467 (mult:DF (match_operand:DF 2 "register_operand" "f")
1468 (match_operand:DF 3 "register_operand" "f"))))]
1469 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1470 "nmsub.d\\t%0,%1,%2,%3"
1471 [(set_attr "type" "fmadd")
1472 (set_attr "mode" "DF")
1473 (set_attr "length" "1")])
1476 [(set (match_operand:SF 0 "register_operand" "=f")
1477 (minus:SF (match_operand:SF 1 "register_operand" "f")
1478 (mult:SF (match_operand:SF 2 "register_operand" "f")
1479 (match_operand:SF 3 "register_operand" "f"))))]
1480 "mips_isa >= 4 && TARGET_HARD_FLOAT"
1481 "nmsub.s\\t%0,%1,%2,%3"
1482 [(set_attr "type" "fmadd")
1483 (set_attr "mode" "SF")
1484 (set_attr "length" "1")])
1487 ;; ....................
1489 ;; DIVISION and REMAINDER
1491 ;; ....................
1494 (define_insn "divdf3"
1495 [(set (match_operand:DF 0 "register_operand" "=f")
1496 (div:DF (match_operand:DF 1 "register_operand" "f")
1497 (match_operand:DF 2 "register_operand" "f")))]
1498 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1500 [(set_attr "type" "fdiv")
1501 (set_attr "mode" "DF")
1502 (set_attr "length" "1")])
1504 (define_insn "divsf3"
1505 [(set (match_operand:SF 0 "register_operand" "=f")
1506 (div:SF (match_operand:SF 1 "register_operand" "f")
1507 (match_operand:SF 2 "register_operand" "f")))]
1510 [(set_attr "type" "fdiv")
1511 (set_attr "mode" "SF")
1512 (set_attr "length" "1")])
1515 [(set (match_operand:DF 0 "register_operand" "=f")
1516 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
1517 (match_operand:DF 2 "register_operand" "f")))]
1518 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
1520 [(set_attr "type" "fdiv")
1521 (set_attr "mode" "DF")
1522 (set_attr "length" "1")])
1525 [(set (match_operand:SF 0 "register_operand" "=f")
1526 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
1527 (match_operand:SF 2 "register_operand" "f")))]
1528 "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
1530 [(set_attr "type" "fdiv")
1531 (set_attr "mode" "SF")
1532 (set_attr "length" "1")])
1534 ;; If optimizing, prefer the divmod functions over separate div and
1535 ;; mod functions, since this will allow using one instruction for both
1536 ;; the quotient and remainder. At present, the divmod is not moved out
1537 ;; of loops if it is constant within the loop, so allow -mdebugc to
1538 ;; use the old method of doing things.
1540 ;; 64 is the multiply/divide hi register
1541 ;; 65 is the multiply/divide lo register
1543 ;; ??? We can't accept constants here, because the MIPS assembler will replace
1544 ;; a divide by power of 2 with a shift, and then the remainder is no longer
1547 (define_insn "divmodsi4"
1548 [(set (match_operand:SI 0 "register_operand" "=d")
1549 (div:SI (match_operand:SI 1 "register_operand" "d")
1550 (match_operand:SI 2 "register_operand" "d")))
1551 (set (match_operand:SI 3 "register_operand" "=d")
1552 (mod:SI (match_dup 1)
1554 (clobber (match_scratch:SI 4 "=l"))
1555 (clobber (match_scratch:SI 5 "=h"))
1556 (clobber (match_scratch:SI 6 "=a"))]
1560 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1561 return \"div\\t%0,%1,%2\";
1563 if (find_reg_note (insn, REG_UNUSED, operands[0]))
1564 return \"rem\\t%3,%1,%2\";
1566 return \"div\\t%0,%1,%2\;mfhi\\t%3\";
1568 [(set_attr "type" "idiv")
1569 (set_attr "mode" "SI")
1570 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
1572 (define_insn "divmoddi4"
1573 [(set (match_operand:DI 0 "register_operand" "=d")
1574 (div:DI (match_operand:DI 1 "se_register_operand" "d")
1575 (match_operand:DI 2 "se_register_operand" "d")))
1576 (set (match_operand:DI 3 "register_operand" "=d")
1577 (mod:DI (match_dup 1)
1579 (clobber (match_scratch:DI 4 "=l"))
1580 (clobber (match_scratch:DI 5 "=h"))
1581 (clobber (match_scratch:DI 6 "=a"))]
1582 "TARGET_64BIT && optimize"
1585 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1586 return \"ddiv\\t%0,%1,%2\";
1588 if (find_reg_note (insn, REG_UNUSED, operands[0]))
1589 return \"drem\\t%3,%1,%2\";
1591 return \"ddiv\\t%0,%1,%2\;mfhi\\t%3\";
1593 [(set_attr "type" "idiv")
1594 (set_attr "mode" "DI")
1595 (set_attr "length" "15")]) ;; various tests for dividing by 0 and such
1597 (define_insn "udivmodsi4"
1598 [(set (match_operand:SI 0 "register_operand" "=d")
1599 (udiv:SI (match_operand:SI 1 "register_operand" "d")
1600 (match_operand:SI 2 "register_operand" "d")))
1601 (set (match_operand:SI 3 "register_operand" "=d")
1602 (umod:SI (match_dup 1)
1604 (clobber (match_scratch:SI 4 "=l"))
1605 (clobber (match_scratch:SI 5 "=h"))
1606 (clobber (match_scratch:SI 6 "=a"))]
1610 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1611 return \"divu\\t%0,%1,%2\";
1613 if (find_reg_note (insn, REG_UNUSED, operands[0]))
1614 return \"remu\\t%3,%1,%2\";
1616 return \"divu\\t%0,%1,%2\;mfhi\\t%3\";
1618 [(set_attr "type" "idiv")
1619 (set_attr "mode" "SI")
1620 (set_attr "length" "8")]) ;; various tests for dividing by 0 and such
1622 (define_insn "udivmoddi4"
1623 [(set (match_operand:DI 0 "register_operand" "=d")
1624 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
1625 (match_operand:DI 2 "se_register_operand" "d")))
1626 (set (match_operand:DI 3 "register_operand" "=d")
1627 (umod:DI (match_dup 1)
1629 (clobber (match_scratch:DI 4 "=l"))
1630 (clobber (match_scratch:DI 5 "=h"))
1631 (clobber (match_scratch:DI 6 "=a"))]
1632 "TARGET_64BIT && optimize"
1635 if (find_reg_note (insn, REG_UNUSED, operands[3]))
1636 return \"ddivu\\t%0,%1,%2\";
1638 if (find_reg_note (insn, REG_UNUSED, operands[0]))
1639 return \"dremu\\t%3,%1,%2\";
1641 return \"ddivu\\t%0,%1,%2\;mfhi\\t%3\";
1643 [(set_attr "type" "idiv")
1644 (set_attr "mode" "DI")
1645 (set_attr "length" "8")]) ;; various tests for dividing by 0 and such
1647 (define_insn "divsi3"
1648 [(set (match_operand:SI 0 "register_operand" "=d")
1649 (div:SI (match_operand:SI 1 "register_operand" "d")
1650 (match_operand:SI 2 "nonmemory_operand" "di")))
1651 (clobber (match_scratch:SI 3 "=l"))
1652 (clobber (match_scratch:SI 4 "=h"))
1653 (clobber (match_scratch:SI 6 "=a"))]
1656 [(set_attr "type" "idiv")
1657 (set_attr "mode" "SI")
1658 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
1660 (define_insn "divdi3"
1661 [(set (match_operand:DI 0 "register_operand" "=d")
1662 (div:DI (match_operand:DI 1 "se_register_operand" "d")
1663 (match_operand:DI 2 "se_nonmemory_operand" "di")))
1664 (clobber (match_scratch:DI 3 "=l"))
1665 (clobber (match_scratch:DI 4 "=h"))
1666 (clobber (match_scratch:DI 6 "=a"))]
1667 "TARGET_64BIT && !optimize"
1669 [(set_attr "type" "idiv")
1670 (set_attr "mode" "DI")
1671 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
1673 (define_insn "modsi3"
1674 [(set (match_operand:SI 0 "register_operand" "=d")
1675 (mod:SI (match_operand:SI 1 "register_operand" "d")
1676 (match_operand:SI 2 "nonmemory_operand" "di")))
1677 (clobber (match_scratch:SI 3 "=l"))
1678 (clobber (match_scratch:SI 4 "=h"))
1679 (clobber (match_scratch:SI 6 "=a"))]
1682 [(set_attr "type" "idiv")
1683 (set_attr "mode" "SI")
1684 (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
1686 (define_insn "moddi3"
1687 [(set (match_operand:DI 0 "register_operand" "=d")
1688 (mod:DI (match_operand:DI 1 "se_register_operand" "d")
1689 (match_operand:DI 2 "se_nonmemory_operand" "di")))
1690 (clobber (match_scratch:DI 3 "=l"))
1691 (clobber (match_scratch:DI 4 "=h"))
1692 (clobber (match_scratch:DI 6 "=a"))]
1693 "TARGET_64BIT && !optimize"
1695 [(set_attr "type" "idiv")
1696 (set_attr "mode" "DI")
1697 (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
1699 (define_insn "udivsi3"
1700 [(set (match_operand:SI 0 "register_operand" "=d")
1701 (udiv:SI (match_operand:SI 1 "register_operand" "d")
1702 (match_operand:SI 2 "nonmemory_operand" "di")))
1703 (clobber (match_scratch:SI 3 "=l"))
1704 (clobber (match_scratch:SI 4 "=h"))
1705 (clobber (match_scratch:SI 6 "=a"))]
1708 [(set_attr "type" "idiv")
1709 (set_attr "mode" "SI")
1710 (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
1712 (define_insn "udivdi3"
1713 [(set (match_operand:DI 0 "register_operand" "=d")
1714 (udiv:DI (match_operand:DI 1 "se_register_operand" "d")
1715 (match_operand:DI 2 "se_nonmemory_operand" "di")))
1716 (clobber (match_scratch:DI 3 "=l"))
1717 (clobber (match_scratch:DI 4 "=h"))
1718 (clobber (match_scratch:DI 6 "=a"))]
1719 "TARGET_64BIT && !optimize"
1721 [(set_attr "type" "idiv")
1722 (set_attr "mode" "DI")
1723 (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
1725 (define_insn "umodsi3"
1726 [(set (match_operand:SI 0 "register_operand" "=d")
1727 (umod:SI (match_operand:SI 1 "register_operand" "d")
1728 (match_operand:SI 2 "nonmemory_operand" "di")))
1729 (clobber (match_scratch:SI 3 "=l"))
1730 (clobber (match_scratch:SI 4 "=h"))
1731 (clobber (match_scratch:SI 6 "=a"))]
1734 [(set_attr "type" "idiv")
1735 (set_attr "mode" "SI")
1736 (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
1738 (define_insn "umoddi3"
1739 [(set (match_operand:DI 0 "register_operand" "=d")
1740 (umod:DI (match_operand:DI 1 "se_register_operand" "d")
1741 (match_operand:DI 2 "se_nonmemory_operand" "di")))
1742 (clobber (match_scratch:DI 3 "=l"))
1743 (clobber (match_scratch:DI 4 "=h"))
1744 (clobber (match_scratch:DI 6 "=a"))]
1745 "TARGET_64BIT && !optimize"
1747 [(set_attr "type" "idiv")
1748 (set_attr "mode" "DI")
1749 (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
1753 ;; ....................
1757 ;; ....................
1759 (define_insn "sqrtdf2"
1760 [(set (match_operand:DF 0 "register_operand" "=f")
1761 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
1762 "TARGET_HARD_FLOAT && HAVE_SQRT_P() && TARGET_DOUBLE_FLOAT"
1764 [(set_attr "type" "fsqrt")
1765 (set_attr "mode" "DF")
1766 (set_attr "length" "1")])
1768 (define_insn "sqrtsf2"
1769 [(set (match_operand:SF 0 "register_operand" "=f")
1770 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
1771 "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
1773 [(set_attr "type" "fsqrt")
1774 (set_attr "mode" "SF")
1775 (set_attr "length" "1")])
1778 [(set (match_operand:DF 0 "register_operand" "=f")
1779 (div:DF (match_operand:DF 1 "const_float_1_operand" "")
1780 (sqrt:DF (match_operand:DF 2 "register_operand" "f"))))]
1781 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && flag_fast_math"
1783 [(set_attr "type" "fsqrt")
1784 (set_attr "mode" "DF")
1785 (set_attr "length" "1")])
1788 [(set (match_operand:SF 0 "register_operand" "=f")
1789 (div:SF (match_operand:SF 1 "const_float_1_operand" "")
1790 (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
1791 "mips_isa >= 4 && TARGET_HARD_FLOAT && flag_fast_math"
1793 [(set_attr "type" "fsqrt")
1794 (set_attr "mode" "SF")
1795 (set_attr "length" "1")])
1799 ;; ....................
1803 ;; ....................
1805 ;; Do not use the integer abs macro instruction, since that signals an
1806 ;; exception on -2147483648 (sigh).
1808 (define_insn "abssi2"
1809 [(set (match_operand:SI 0 "register_operand" "=d")
1810 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1814 dslots_jump_total++;
1815 dslots_jump_filled++;
1816 operands[2] = const0_rtx;
1818 if (REGNO (operands[0]) == REGNO (operands[1]))
1820 if (GENERATE_BRANCHLIKELY)
1821 return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
1823 return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\";
1826 return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
1828 [(set_attr "type" "multi")
1829 (set_attr "mode" "SI")
1830 (set_attr "length" "3")])
1832 (define_insn "absdi2"
1833 [(set (match_operand:DI 0 "register_operand" "=d")
1834 (abs:DI (match_operand:DI 1 "se_register_operand" "d")))]
1838 dslots_jump_total++;
1839 dslots_jump_filled++;
1840 operands[2] = const0_rtx;
1842 if (REGNO (operands[0]) == REGNO (operands[1]))
1843 return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
1845 return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
1847 [(set_attr "type" "multi")
1848 (set_attr "mode" "DI")
1849 (set_attr "length" "3")])
1851 (define_insn "absdf2"
1852 [(set (match_operand:DF 0 "register_operand" "=f")
1853 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
1854 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
1856 [(set_attr "type" "fabs")
1857 (set_attr "mode" "DF")
1858 (set_attr "length" "1")])
1860 (define_insn "abssf2"
1861 [(set (match_operand:SF 0 "register_operand" "=f")
1862 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
1865 [(set_attr "type" "fabs")
1866 (set_attr "mode" "SF")
1867 (set_attr "length" "1")])
1871 ;; ....................
1873 ;; FIND FIRST BIT INSTRUCTION
1875 ;; ....................
1878 (define_insn "ffssi2"
1879 [(set (match_operand:SI 0 "register_operand" "=&d")
1880 (ffs:SI (match_operand:SI 1 "register_operand" "d")))
1881 (clobber (match_scratch:SI 2 "=&d"))
1882 (clobber (match_scratch:SI 3 "=&d"))]
1886 dslots_jump_total += 2;
1887 dslots_jump_filled += 2;
1888 operands[4] = const0_rtx;
1890 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
1893 \\tbeq\\t%1,%z4,2f\\n\\
1894 1:\\tand\\t%2,%1,0x0001\\n\\
1895 \\taddu\\t%0,%0,1\\n\\
1896 \\tbeq\\t%2,%z4,1b\\n\\
1897 \\tsrl\\t%1,%1,1\\n\\
1902 \\tmove\\t%3,%1\\n\\
1903 \\tbeq\\t%3,%z4,2f\\n\\
1904 1:\\tand\\t%2,%3,0x0001\\n\\
1905 \\taddu\\t%0,%0,1\\n\\
1906 \\tbeq\\t%2,%z4,1b\\n\\
1907 \\tsrl\\t%3,%3,1\\n\\
1910 [(set_attr "type" "multi")
1911 (set_attr "mode" "SI")
1912 (set_attr "length" "6")])
1914 (define_insn "ffsdi2"
1915 [(set (match_operand:DI 0 "register_operand" "=&d")
1916 (ffs:DI (match_operand:DI 1 "se_register_operand" "d")))
1917 (clobber (match_scratch:DI 2 "=&d"))
1918 (clobber (match_scratch:DI 3 "=&d"))]
1922 dslots_jump_total += 2;
1923 dslots_jump_filled += 2;
1924 operands[4] = const0_rtx;
1926 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
1929 \\tbeq\\t%1,%z4,2f\\n\\
1930 1:\\tand\\t%2,%1,0x0001\\n\\
1931 \\tdaddu\\t%0,%0,1\\n\\
1932 \\tbeq\\t%2,%z4,1b\\n\\
1933 \\tdsrl\\t%1,%1,1\\n\\
1938 \\tmove\\t%3,%1\\n\\
1939 \\tbeq\\t%3,%z4,2f\\n\\
1940 1:\\tand\\t%2,%3,0x0001\\n\\
1941 \\tdaddu\\t%0,%0,1\\n\\
1942 \\tbeq\\t%2,%z4,1b\\n\\
1943 \\tdsrl\\t%3,%3,1\\n\\
1946 [(set_attr "type" "multi")
1947 (set_attr "mode" "DI")
1948 (set_attr "length" "6")])
1952 ;; ....................
1954 ;; NEGATION and ONE'S COMPLEMENT
1956 ;; ....................
1958 (define_insn "negsi2"
1959 [(set (match_operand:SI 0 "register_operand" "=d")
1960 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1964 operands[2] = const0_rtx;
1965 return \"subu\\t%0,%z2,%1\";
1967 [(set_attr "type" "arith")
1968 (set_attr "mode" "SI")
1969 (set_attr "length" "1")])
1971 (define_expand "negdi2"
1972 [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
1973 (neg:DI (match_operand:DI 1 "se_register_operand" "d")))
1974 (clobber (match_dup 2))])]
1975 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
1980 emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
1984 operands[2] = gen_reg_rtx (SImode);
1987 (define_insn "negdi2_internal"
1988 [(set (match_operand:DI 0 "register_operand" "=d")
1989 (neg:DI (match_operand:DI 1 "register_operand" "d")))
1990 (clobber (match_operand:SI 2 "register_operand" "=d"))]
1991 "! TARGET_64BIT && !TARGET_DEBUG_G_MODE"
1994 operands[3] = const0_rtx;
1995 return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
1997 [(set_attr "type" "darith")
1998 (set_attr "mode" "DI")
1999 (set_attr "length" "4")])
2001 (define_insn "negdi2_internal_2"
2002 [(set (match_operand:DI 0 "register_operand" "=d")
2003 (neg:DI (match_operand:DI 1 "se_register_operand" "d")))]
2007 operands[2] = const0_rtx;
2008 return \"dsubu\\t%0,%z2,%1\";
2010 [(set_attr "type" "arith")
2011 (set_attr "mode" "DI")
2012 (set_attr "length" "1")])
2014 (define_insn "negdf2"
2015 [(set (match_operand:DF 0 "register_operand" "=f")
2016 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
2017 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2019 [(set_attr "type" "fneg")
2020 (set_attr "mode" "DF")
2021 (set_attr "length" "1")])
2023 (define_insn "negsf2"
2024 [(set (match_operand:SF 0 "register_operand" "=f")
2025 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
2028 [(set_attr "type" "fneg")
2029 (set_attr "mode" "SF")
2030 (set_attr "length" "1")])
2032 (define_insn "one_cmplsi2"
2033 [(set (match_operand:SI 0 "register_operand" "=d")
2034 (not:SI (match_operand:SI 1 "register_operand" "d")))]
2038 operands[2] = const0_rtx;
2039 return \"nor\\t%0,%z2,%1\";
2041 [(set_attr "type" "arith")
2042 (set_attr "mode" "SI")
2043 (set_attr "length" "1")])
2045 (define_insn "one_cmpldi2"
2046 [(set (match_operand:DI 0 "register_operand" "=d")
2047 (not:DI (match_operand:DI 1 "se_register_operand" "d")))]
2051 operands[2] = const0_rtx;
2053 return \"nor\\t%0,%z2,%1\";
2054 return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
2056 [(set_attr "type" "darith")
2057 (set_attr "mode" "DI")
2058 (set (attr "length")
2059 (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
2064 [(set (match_operand:DI 0 "register_operand" "")
2065 (not:DI (match_operand:DI 1 "register_operand" "")))]
2066 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
2067 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2068 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
2070 [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
2071 (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))]
2076 ;; ....................
2080 ;; ....................
2083 (define_insn "andsi3"
2084 [(set (match_operand:SI 0 "register_operand" "=d,d")
2085 (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
2086 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
2091 [(set_attr "type" "arith")
2092 (set_attr "mode" "SI")
2093 (set_attr "length" "1")])
2095 (define_insn "anddi3"
2096 [(set (match_operand:DI 0 "register_operand" "=d")
2097 (and:DI (match_operand:DI 1 "se_register_operand" "d")
2098 (match_operand:DI 2 "se_register_operand" "d")))]
2099 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
2103 return \"and\\t%0,%1,%2\";
2104 return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\";
2106 [(set_attr "type" "darith")
2107 (set_attr "mode" "DI")
2108 (set (attr "length")
2109 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
2114 [(set (match_operand:DI 0 "register_operand" "")
2115 (and:DI (match_operand:DI 1 "register_operand" "")
2116 (match_operand:DI 2 "register_operand" "")))]
2117 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
2118 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2119 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
2120 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
2122 [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
2123 (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
2126 (define_insn "anddi3_internal1"
2127 [(set (match_operand:DI 0 "register_operand" "=d,d")
2128 (and:DI (match_operand:DI 1 "se_register_operand" "%d,d")
2129 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
2134 [(set_attr "type" "arith")
2135 (set_attr "mode" "DI")
2136 (set_attr "length" "1")])
2138 (define_insn "iorsi3"
2139 [(set (match_operand:SI 0 "register_operand" "=d,d")
2140 (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
2141 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
2146 [(set_attr "type" "arith")
2147 (set_attr "mode" "SI")
2148 (set_attr "length" "1")])
2150 ;;; ??? There is no iordi3 pattern which accepts 'K' constants when
2153 (define_insn "iordi3"
2154 [(set (match_operand:DI 0 "register_operand" "=d")
2155 (ior:DI (match_operand:DI 1 "se_register_operand" "d")
2156 (match_operand:DI 2 "se_register_operand" "d")))]
2157 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
2161 return \"or\\t%0,%1,%2\";
2162 return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\";
2164 [(set_attr "type" "darith")
2165 (set_attr "mode" "DI")
2166 (set (attr "length")
2167 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
2172 [(set (match_operand:DI 0 "register_operand" "")
2173 (ior:DI (match_operand:DI 1 "register_operand" "")
2174 (match_operand:DI 2 "register_operand" "")))]
2175 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
2176 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2177 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
2178 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
2180 [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
2181 (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
2184 (define_insn "xorsi3"
2185 [(set (match_operand:SI 0 "register_operand" "=d,d")
2186 (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
2187 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
2192 [(set_attr "type" "arith")
2193 (set_attr "mode" "SI")
2194 (set_attr "length" "1")])
2196 ;; ??? If delete the 32-bit long long patterns, then could merge this with
2197 ;; the following xordi3_internal pattern.
2198 (define_insn "xordi3"
2199 [(set (match_operand:DI 0 "register_operand" "=d")
2200 (xor:DI (match_operand:DI 1 "se_register_operand" "d")
2201 (match_operand:DI 2 "se_register_operand" "d")))]
2202 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
2206 return \"xor\\t%0,%1,%2\";
2207 return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\";
2209 [(set_attr "type" "darith")
2210 (set_attr "mode" "DI")
2211 (set (attr "length")
2212 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
2217 [(set (match_operand:DI 0 "register_operand" "")
2218 (xor:DI (match_operand:DI 1 "register_operand" "")
2219 (match_operand:DI 2 "register_operand" "")))]
2220 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
2221 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2222 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
2223 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
2225 [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
2226 (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
2229 (define_insn "xordi3_immed"
2230 [(set (match_operand:DI 0 "register_operand" "d")
2231 (xor:DI (match_operand:DI 1 "se_register_operand" "d")
2232 (match_operand:DI 2 "se_uns_arith_operand" "K")))]
2235 [(set_attr "type" "arith")
2236 (set_attr "mode" "DI")
2237 (set_attr "length" "1")])
2239 (define_insn "*norsi3"
2240 [(set (match_operand:SI 0 "register_operand" "=d")
2241 (and:SI (not:SI (match_operand:SI 1 "register_operand" "d"))
2242 (not:SI (match_operand:SI 2 "register_operand" "d"))))]
2245 [(set_attr "type" "arith")
2246 (set_attr "mode" "SI")
2247 (set_attr "length" "1")])
2249 (define_insn "*nordi3"
2250 [(set (match_operand:DI 0 "register_operand" "=d")
2251 (and:DI (not:DI (match_operand:DI 1 "se_register_operand" "d"))
2252 (not:DI (match_operand:DI 2 "se_register_operand" "d"))))]
2257 return \"nor\\t%0,%z1,%z2\";
2258 return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\";
2260 [(set_attr "type" "darith")
2261 (set_attr "mode" "DI")
2262 (set (attr "length")
2263 (if_then_else (ne (symbol_ref "TARGET_64BIT") (const_int 0))
2268 [(set (match_operand:DI 0 "register_operand" "")
2269 (and:DI (not:DI (match_operand:DI 1 "register_operand" ""))
2270 (not:DI (match_operand:DI 2 "register_operand" ""))))]
2271 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
2272 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2273 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
2274 && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
2276 [(set (subreg:SI (match_dup 0) 0) (and:SI (not:SI (subreg:SI (match_dup 1) 0)) (not:SI (subreg:SI (match_dup 2) 0))))
2277 (set (subreg:SI (match_dup 0) 1) (and:SI (not:SI (subreg:SI (match_dup 1) 1)) (not:SI (subreg:SI (match_dup 2) 1))))]
2281 ;; ....................
2285 ;; ....................
2287 (define_insn "truncdfsf2"
2288 [(set (match_operand:SF 0 "register_operand" "=f")
2289 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2290 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2292 [(set_attr "type" "fcvt")
2293 (set_attr "mode" "SF")
2294 (set_attr "length" "1")])
2296 (define_insn "truncdisi2"
2297 [(set (match_operand:SI 0 "register_operand" "=d")
2298 (truncate:SI (match_operand:DI 1 "se_register_operand" "d")))]
2300 "dsll\\t%0,%1,32\;dsra\\t%0,%0,32"
2301 [(set_attr "type" "darith")
2302 (set_attr "mode" "SI")
2303 (set_attr "length" "2")])
2305 (define_insn "truncdihi2"
2306 [(set (match_operand:HI 0 "register_operand" "=d")
2307 (truncate:HI (match_operand:DI 1 "se_register_operand" "d")))]
2309 "andi\\t%0,%1,0xffff"
2310 [(set_attr "type" "darith")
2311 (set_attr "mode" "HI")
2312 (set_attr "length" "1")])
2314 (define_insn "truncdiqi2"
2315 [(set (match_operand:QI 0 "register_operand" "=d")
2316 (truncate:QI (match_operand:DI 1 "se_register_operand" "d")))]
2318 "andi\\t%0,%1,0x00ff"
2319 [(set_attr "type" "darith")
2320 (set_attr "mode" "QI")
2321 (set_attr "length" "1")])
2323 ;; Combiner patterns to optimize shift/truncate combinations.
2325 [(set (match_operand:SI 0 "register_operand" "=d")
2326 (truncate:SI (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
2327 (match_operand:DI 2 "small_int" "I"))))]
2331 int shift_amt = INTVAL (operands[2]) & 0x3f;
2335 operands[2] = GEN_INT (32 - shift_amt);
2336 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
2340 operands[2] = GEN_INT (shift_amt);
2341 return \"dsra\\t%0,%1,%2\";
2344 [(set_attr "type" "darith")
2345 (set_attr "mode" "SI")
2346 (set_attr "length" "2")])
2349 [(set (match_operand:SI 0 "register_operand" "=d")
2350 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
2351 (match_operand:DI 2 "small_int" "I"))))]
2355 int shift_amt = INTVAL (operands[2]) & 0x3f;
2359 operands[2] = GEN_INT (32 - shift_amt);
2360 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
2362 else if (shift_amt == 32)
2363 return \"dsra\\t%0,%1,32\";
2366 operands[2] = GEN_INT (shift_amt);
2367 return \"dsrl\\t%0,%1,%2\";
2370 [(set_attr "type" "darith")
2371 (set_attr "mode" "SI")
2372 (set_attr "length" "2")])
2375 [(set (match_operand:SI 0 "register_operand" "=d")
2376 (truncate:SI (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
2377 (match_operand:DI 2 "small_int" "I"))))]
2381 int shift_amt = INTVAL (operands[2]) & 0x3f;
2385 operands[2] = GEN_INT (32 + shift_amt);
2386 return \"dsll\\t%0,%1,%2\;dsra\\t%0,%0,32\";
2389 return \"move\\t%0,%.\";
2391 [(set_attr "type" "darith")
2392 (set_attr "mode" "SI")
2393 (set_attr "length" "2")])
2395 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2398 [(set (match_operand:SI 0 "register_operand" "=d")
2399 (zero_extend:SI (truncate:HI
2400 (match_operand:DI 1 "se_register_operand" "d"))))]
2402 "andi\\t%0,%1,0xffff"
2403 [(set_attr "type" "darith")
2404 (set_attr "mode" "SI")
2405 (set_attr "length" "1")])
2408 [(set (match_operand:SI 0 "register_operand" "=d")
2409 (zero_extend:SI (truncate:QI
2410 (match_operand:DI 1 "se_register_operand" "d"))))]
2413 [(set_attr "type" "darith")
2414 (set_attr "mode" "SI")
2415 (set_attr "length" "1")])
2418 [(set (match_operand:HI 0 "register_operand" "=d")
2419 (zero_extend:HI (truncate:QI
2420 (match_operand:DI 1 "se_register_operand" "d"))))]
2423 [(set_attr "type" "darith")
2424 (set_attr "mode" "HI")
2425 (set_attr "length" "1")])
2428 ;; ....................
2432 ;; ....................
2435 ;; Those for integer source operand are ordered widest source type first.
2437 (define_expand "zero_extendsidi2"
2438 [(set (match_operand:DI 0 "register_operand" "")
2439 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2443 if (optimize && GET_CODE (operands[1]) == MEM)
2444 operands[1] = force_not_mem (operands[1]);
2446 if (GET_CODE (operands[1]) != MEM)
2448 rtx op1 = gen_lowpart (DImode, operands[1]);
2449 rtx temp = gen_reg_rtx (DImode);
2450 rtx shift = gen_rtx (CONST_INT, VOIDmode, 32);
2452 emit_insn (gen_ashldi3 (temp, op1, shift));
2453 emit_insn (gen_lshrdi3 (operands[0], temp, shift));
2458 (define_insn "zero_extendsidi2_internal"
2459 [(set (match_operand:DI 0 "register_operand" "=d,d")
2460 (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
2462 "* return mips_move_1word (operands, insn, TRUE);"
2463 [(set_attr "type" "load")
2464 (set_attr "mode" "DI")
2465 (set_attr "length" "1,2")])
2467 (define_insn "zero_extendhisi2"
2468 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2469 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
2473 if (which_alternative == 0)
2474 return \"andi\\t%0,%1,0xffff\";
2476 return mips_move_1word (operands, insn, TRUE);
2478 [(set_attr "type" "arith,load,load")
2479 (set_attr "mode" "SI")
2480 (set_attr "length" "1,1,2")])
2482 (define_insn "zero_extendhidi2"
2483 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2484 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
2488 if (which_alternative == 0)
2489 return \"andi\\t%0,%1,0xffff\";
2491 return mips_move_1word (operands, insn, TRUE);
2493 [(set_attr "type" "arith,load,load")
2494 (set_attr "mode" "DI")
2495 (set_attr "length" "1,1,2")])
2497 (define_insn "zero_extendqihi2"
2498 [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2499 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
2503 if (which_alternative == 0)
2504 return \"andi\\t%0,%1,0x00ff\";
2506 return mips_move_1word (operands, insn, TRUE);
2508 [(set_attr "type" "arith,load,load")
2509 (set_attr "mode" "HI")
2510 (set_attr "length" "1,1,2")])
2512 (define_insn "zero_extendqisi2"
2513 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2514 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
2518 if (which_alternative == 0)
2519 return \"andi\\t%0,%1,0x00ff\";
2521 return mips_move_1word (operands, insn, TRUE);
2523 [(set_attr "type" "arith,load,load")
2524 (set_attr "mode" "SI")
2525 (set_attr "length" "1,1,2")])
2527 (define_insn "zero_extendqidi2"
2528 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
2529 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
2533 if (which_alternative == 0)
2534 return \"andi\\t%0,%1,0x00ff\";
2536 return mips_move_1word (operands, insn, TRUE);
2538 [(set_attr "type" "arith,load,load")
2539 (set_attr "mode" "DI")
2540 (set_attr "length" "1,1,2")])
2542 ;; These can be created when a paradoxical subreg operand with an implicit
2543 ;; sign_extend operator is reloaded. Because of the subreg, this is really
2545 ;; ??? It might be possible to eliminate the need for these patterns by adding
2546 ;; more support to reload for implicit sign_extend operators.
2547 (define_insn "*paradoxical_extendhidi2"
2548 [(set (match_operand:DI 0 "register_operand" "=d,d")
2550 (subreg:SI (match_operand:HI 1 "memory_operand" "R,m") 0)))]
2554 return mips_move_1word (operands, insn, TRUE);
2556 [(set_attr "type" "load,load")
2557 (set_attr "mode" "DI")
2558 (set_attr "length" "1,2")])
2560 (define_insn "*paradoxical_extendqidi2"
2561 [(set (match_operand:DI 0 "register_operand" "=d,d")
2563 (subreg:SI (match_operand:QI 1 "memory_operand" "R,m") 0)))]
2567 return mips_move_1word (operands, insn, TRUE);
2569 [(set_attr "type" "load,load")
2570 (set_attr "mode" "DI")
2571 (set_attr "length" "1,2")])
2574 ;; ....................
2578 ;; ....................
2581 ;; Those for integer source operand are ordered widest source type first.
2583 ;; In 64 bit mode, 32 bit values in general registers are always
2584 ;; correctly sign extended. That means that if the target is a
2585 ;; general register, we can sign extend from SImode to DImode just by
2588 (define_insn "extendsidi2"
2589 [(set (match_operand:DI 0 "register_operand" "=d,*d,d,d")
2590 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,*x,R,m")))]
2592 "* return mips_move_1word (operands, insn, FALSE);"
2593 [(set_attr "type" "move,hilo,load,load")
2594 (set_attr "mode" "DI")
2595 (set_attr "length" "1,1,1,2")])
2597 ;; These patterns originally accepted general_operands, however, slightly
2598 ;; better code is generated by only accepting register_operands, and then
2599 ;; letting combine generate the lh and lb insns.
2601 (define_expand "extendhidi2"
2602 [(set (match_operand:DI 0 "register_operand" "")
2603 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
2607 if (optimize && GET_CODE (operands[1]) == MEM)
2608 operands[1] = force_not_mem (operands[1]);
2610 if (GET_CODE (operands[1]) != MEM)
2612 rtx op1 = gen_lowpart (DImode, operands[1]);
2613 rtx temp = gen_reg_rtx (DImode);
2614 rtx shift = gen_rtx (CONST_INT, VOIDmode, 48);
2616 emit_insn (gen_ashldi3 (temp, op1, shift));
2617 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
2622 (define_insn "extendhidi2_internal"
2623 [(set (match_operand:DI 0 "register_operand" "=d,d")
2624 (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
2626 "* return mips_move_1word (operands, insn, FALSE);"
2627 [(set_attr "type" "load")
2628 (set_attr "mode" "DI")
2629 (set_attr "length" "1,2")])
2631 (define_expand "extendhisi2"
2632 [(set (match_operand:SI 0 "register_operand" "")
2633 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2637 if (optimize && GET_CODE (operands[1]) == MEM)
2638 operands[1] = force_not_mem (operands[1]);
2640 if (GET_CODE (operands[1]) != MEM)
2642 rtx op1 = gen_lowpart (SImode, operands[1]);
2643 rtx temp = gen_reg_rtx (SImode);
2644 rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);
2646 emit_insn (gen_ashlsi3 (temp, op1, shift));
2647 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
2652 (define_insn "extendhisi2_internal"
2653 [(set (match_operand:SI 0 "register_operand" "=d,d")
2654 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
2656 "* return mips_move_1word (operands, insn, FALSE);"
2657 [(set_attr "type" "load")
2658 (set_attr "mode" "SI")
2659 (set_attr "length" "1,2")])
2661 (define_expand "extendqihi2"
2662 [(set (match_operand:HI 0 "register_operand" "")
2663 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
2667 if (optimize && GET_CODE (operands[1]) == MEM)
2668 operands[1] = force_not_mem (operands[1]);
2670 if (GET_CODE (operands[1]) != MEM)
2672 rtx op0 = gen_lowpart (SImode, operands[0]);
2673 rtx op1 = gen_lowpart (SImode, operands[1]);
2674 rtx temp = gen_reg_rtx (SImode);
2675 rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
2677 emit_insn (gen_ashlsi3 (temp, op1, shift));
2678 emit_insn (gen_ashrsi3 (op0, temp, shift));
2683 (define_insn "extendqihi2_internal"
2684 [(set (match_operand:HI 0 "register_operand" "=d,d")
2685 (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
2687 "* return mips_move_1word (operands, insn, FALSE);"
2688 [(set_attr "type" "load")
2689 (set_attr "mode" "SI")
2690 (set_attr "length" "1,2")])
2693 (define_expand "extendqisi2"
2694 [(set (match_operand:SI 0 "register_operand" "")
2695 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
2699 if (optimize && GET_CODE (operands[1]) == MEM)
2700 operands[1] = force_not_mem (operands[1]);
2702 if (GET_CODE (operands[1]) != MEM)
2704 rtx op1 = gen_lowpart (SImode, operands[1]);
2705 rtx temp = gen_reg_rtx (SImode);
2706 rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
2708 emit_insn (gen_ashlsi3 (temp, op1, shift));
2709 emit_insn (gen_ashrsi3 (operands[0], temp, shift));
2714 (define_insn "extendqisi2_insn"
2715 [(set (match_operand:SI 0 "register_operand" "=d,d")
2716 (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
2718 "* return mips_move_1word (operands, insn, FALSE);"
2719 [(set_attr "type" "load")
2720 (set_attr "mode" "SI")
2721 (set_attr "length" "1,2")])
2723 (define_expand "extendqidi2"
2724 [(set (match_operand:DI 0 "register_operand" "")
2725 (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
2729 if (optimize && GET_CODE (operands[1]) == MEM)
2730 operands[1] = force_not_mem (operands[1]);
2732 if (GET_CODE (operands[1]) != MEM)
2734 rtx op1 = gen_lowpart (DImode, operands[1]);
2735 rtx temp = gen_reg_rtx (DImode);
2736 rtx shift = gen_rtx (CONST_INT, VOIDmode, 56);
2738 emit_insn (gen_ashldi3 (temp, op1, shift));
2739 emit_insn (gen_ashrdi3 (operands[0], temp, shift));
2744 (define_insn "extendqidi2_insn"
2745 [(set (match_operand:DI 0 "register_operand" "=d,d")
2746 (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
2748 "* return mips_move_1word (operands, insn, FALSE);"
2749 [(set_attr "type" "load")
2750 (set_attr "mode" "DI")
2751 (set_attr "length" "1,2")])
2754 (define_insn "extendsfdf2"
2755 [(set (match_operand:DF 0 "register_operand" "=f")
2756 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2757 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2759 [(set_attr "type" "fcvt")
2760 (set_attr "mode" "DF")
2761 (set_attr "length" "1")])
2766 ;; ....................
2770 ;; ....................
2772 ;; The SImode scratch register can not be shared with address regs used for
2773 ;; operand zero, because then the address in the move instruction will be
2774 ;; clobbered. We mark the scratch register as early clobbered to prevent this.
2776 ;; We need the ?X in alternative 1 so that it will be choosen only if the
2777 ;; destination is a floating point register. Otherwise, alternative 1 can
2778 ;; have lower cost than alternative 0 (because there is one less loser), and
2779 ;; can be choosen when it won't work (because integral reloads into FP
2780 ;; registers are not supported).
2782 (define_insn "fix_truncdfsi2"
2783 [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
2784 (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
2785 (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
2786 (clobber (match_scratch:DF 3 "=f,?*X,f,f"))]
2787 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2792 if (which_alternative == 1)
2793 return \"trunc.w.d %0,%1,%2\";
2795 output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
2797 xoperands[0] = operands[0];
2798 xoperands[1] = operands[3];
2799 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
2802 [(set_attr "type" "fcvt")
2803 (set_attr "mode" "DF")
2804 (set_attr "length" "11,9,10,11")])
2807 (define_insn "fix_truncsfsi2"
2808 [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
2809 (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
2810 (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
2811 (clobber (match_scratch:SF 3 "=f,?*X,f,f"))]
2817 if (which_alternative == 1)
2818 return \"trunc.w.s %0,%1,%2\";
2820 output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
2822 xoperands[0] = operands[0];
2823 xoperands[1] = operands[3];
2824 output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
2827 [(set_attr "type" "fcvt")
2828 (set_attr "mode" "SF")
2829 (set_attr "length" "11,9,10,11")])
2832 ;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
2833 ;;; but not in the chapter that describes the FPU. It is not mentioned at all
2834 ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
2836 ;;; Deleting this means that we now need two libgcc2.a libraries. One for
2837 ;;; the 32 bit calling convention and one for the 64 bit calling convention.
2839 ;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
2841 (define_insn "fix_truncdfdi2"
2842 [(set (match_operand:DI 0 "general_operand" "=d,*f,R,o")
2843 (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
2844 (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
2845 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2850 if (which_alternative == 1)
2851 return \"trunc.l.d %0,%1\";
2853 output_asm_insn (\"trunc.l.d %2,%1\", operands);
2855 xoperands[0] = operands[0];
2856 xoperands[1] = operands[2];
2857 output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
2860 [(set_attr "type" "fcvt")
2861 (set_attr "mode" "DF")
2862 (set_attr "length" "2,1,2,3")])
2865 ;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
2866 ;;; but not in the chapter that describes the FPU. It is not mentioned at all
2867 ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
2868 (define_insn "fix_truncsfdi2"
2869 [(set (match_operand:DI 0 "general_operand" "=d,*f,R,o")
2870 (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
2871 (clobber (match_scratch:DF 2 "=f,?*X,f,f"))]
2872 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2877 if (which_alternative == 1)
2878 return \"trunc.l.s %0,%1\";
2880 output_asm_insn (\"trunc.l.s %2,%1\", operands);
2882 xoperands[0] = operands[0];
2883 xoperands[1] = operands[2];
2884 output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
2887 [(set_attr "type" "fcvt")
2888 (set_attr "mode" "SF")
2889 (set_attr "length" "2,1,2,3")])
2892 (define_insn "floatsidf2"
2893 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
2894 (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
2895 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2898 dslots_load_total++;
2899 if (GET_CODE (operands[1]) == MEM)
2900 return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
2902 return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
2904 [(set_attr "type" "fcvt")
2905 (set_attr "mode" "DF")
2906 (set_attr "length" "3,4,3")])
2909 (define_insn "floatdidf2"
2910 [(set (match_operand:DF 0 "register_operand" "=f,f,f")
2911 (float:DF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
2912 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2915 dslots_load_total++;
2916 if (GET_CODE (operands[1]) == MEM)
2917 return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
2919 return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
2921 [(set_attr "type" "fcvt")
2922 (set_attr "mode" "DF")
2923 (set_attr "length" "3,4,3")])
2926 (define_insn "floatsisf2"
2927 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
2928 (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
2932 dslots_load_total++;
2933 if (GET_CODE (operands[1]) == MEM)
2934 return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
2936 return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
2938 [(set_attr "type" "fcvt")
2939 (set_attr "mode" "SF")
2940 (set_attr "length" "3,4,3")])
2943 (define_insn "floatdisf2"
2944 [(set (match_operand:SF 0 "register_operand" "=f,f,f")
2945 (float:SF (match_operand:DI 1 "se_nonimmediate_operand" "d,R,m")))]
2946 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2949 dslots_load_total++;
2950 if (GET_CODE (operands[1]) == MEM)
2951 return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
2953 return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
2955 [(set_attr "type" "fcvt")
2956 (set_attr "mode" "SF")
2957 (set_attr "length" "3,4,3")])
2960 (define_expand "fixuns_truncdfsi2"
2961 [(set (match_operand:SI 0 "register_operand" "")
2962 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2963 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2966 rtx reg1 = gen_reg_rtx (DFmode);
2967 rtx reg2 = gen_reg_rtx (DFmode);
2968 rtx reg3 = gen_reg_rtx (SImode);
2969 rtx label1 = gen_label_rtx ();
2970 rtx label2 = gen_label_rtx ();
2971 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
2973 if (reg1) /* turn off complaints about unreached code */
2975 emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
2976 do_pending_stack_adjust ();
2978 emit_insn (gen_cmpdf (operands[1], reg1));
2979 emit_jump_insn (gen_bge (label1));
2981 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2982 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2983 gen_rtx (LABEL_REF, VOIDmode, label2)));
2986 emit_label (label1);
2987 emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
2988 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
2990 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2991 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2993 emit_label (label2);
2995 /* allow REG_NOTES to be set on last insn (labels don't have enough
2996 fields, and can't be used for REG_NOTES anyway). */
2997 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
3003 (define_expand "fixuns_truncdfdi2"
3004 [(set (match_operand:DI 0 "register_operand" "")
3005 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
3006 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3009 rtx reg1 = gen_reg_rtx (DFmode);
3010 rtx reg2 = gen_reg_rtx (DFmode);
3011 rtx reg3 = gen_reg_rtx (DImode);
3012 rtx label1 = gen_label_rtx ();
3013 rtx label2 = gen_label_rtx ();
3014 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
3016 if (reg1) /* turn off complaints about unreached code */
3018 emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
3019 do_pending_stack_adjust ();
3021 emit_insn (gen_cmpdf (operands[1], reg1));
3022 emit_jump_insn (gen_bge (label1));
3024 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
3025 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
3026 gen_rtx (LABEL_REF, VOIDmode, label2)));
3029 emit_label (label1);
3030 emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
3031 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
3032 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3034 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
3035 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3037 emit_label (label2);
3039 /* allow REG_NOTES to be set on last insn (labels don't have enough
3040 fields, and can't be used for REG_NOTES anyway). */
3041 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
3047 (define_expand "fixuns_truncsfsi2"
3048 [(set (match_operand:SI 0 "register_operand" "")
3049 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
3053 rtx reg1 = gen_reg_rtx (SFmode);
3054 rtx reg2 = gen_reg_rtx (SFmode);
3055 rtx reg3 = gen_reg_rtx (SImode);
3056 rtx label1 = gen_label_rtx ();
3057 rtx label2 = gen_label_rtx ();
3058 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
3060 if (reg1) /* turn off complaints about unreached code */
3062 emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
3063 do_pending_stack_adjust ();
3065 emit_insn (gen_cmpsf (operands[1], reg1));
3066 emit_jump_insn (gen_bge (label1));
3068 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
3069 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
3070 gen_rtx (LABEL_REF, VOIDmode, label2)));
3073 emit_label (label1);
3074 emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
3075 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
3077 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
3078 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
3080 emit_label (label2);
3082 /* allow REG_NOTES to be set on last insn (labels don't have enough
3083 fields, and can't be used for REG_NOTES anyway). */
3084 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
3090 (define_expand "fixuns_truncsfdi2"
3091 [(set (match_operand:DI 0 "register_operand" "")
3092 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
3093 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
3096 rtx reg1 = gen_reg_rtx (SFmode);
3097 rtx reg2 = gen_reg_rtx (SFmode);
3098 rtx reg3 = gen_reg_rtx (DImode);
3099 rtx label1 = gen_label_rtx ();
3100 rtx label2 = gen_label_rtx ();
3101 REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
3103 if (reg1) /* turn off complaints about unreached code */
3105 emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
3106 do_pending_stack_adjust ();
3108 emit_insn (gen_cmpsf (operands[1], reg1));
3109 emit_jump_insn (gen_bge (label1));
3111 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
3112 emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
3113 gen_rtx (LABEL_REF, VOIDmode, label2)));
3116 emit_label (label1);
3117 emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
3118 emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
3119 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
3121 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
3122 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
3124 emit_label (label2);
3126 /* allow REG_NOTES to be set on last insn (labels don't have enough
3127 fields, and can't be used for REG_NOTES anyway). */
3128 emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
3135 ;; ....................
3139 ;; ....................
3141 ;; Bit field extract patterns which use lwl/lwr.
3143 ;; ??? There should be DImode variants for 64 bit code, but the current
3144 ;; bitfield scheme can't handle that. We would need to add new optabs
3145 ;; in order to make that work.
3147 ;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
3148 ;; It isn't clear whether this will give better code.
3150 (define_expand "extv"
3151 [(set (match_operand:SI 0 "register_operand" "")
3152 (sign_extract:SI (match_operand:QI 1 "memory_operand" "")
3153 (match_operand:SI 2 "immediate_operand" "")
3154 (match_operand:SI 3 "immediate_operand" "")))]
3158 /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
3160 if (INTVAL (operands[2]) != 32 || (INTVAL (operands[3]) % 8) != 0)
3163 /* This can happen for a 64 bit target, when extracting a value from
3164 a 64 bit union member. extract_bit_field doesn't verify that our
3165 source matches the predicate, so we force it to be a MEM here. */
3166 if (GET_CODE (operands[1]) != MEM)
3169 /* Change the mode to BLKmode for aliasing purposes. */
3170 operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
3172 /* Otherwise, emit a lwl/lwr pair to load the value. */
3173 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
3177 (define_expand "extzv"
3178 [(set (match_operand:SI 0 "register_operand" "")
3179 (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
3180 (match_operand:SI 2 "immediate_operand" "")
3181 (match_operand:SI 3 "immediate_operand" "")))]
3185 /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
3187 if (INTVAL (operands[2]) != 32 || (INTVAL (operands[3]) % 8) != 0)
3190 /* This can happen for a 64 bit target, when extracting a value from
3191 a 64 bit union member. extract_bit_field doesn't verify that our
3192 source matches the predicate, so we force it to be a MEM here. */
3193 if (GET_CODE (operands[1]) != MEM)
3196 /* Change the mode to BLKmode for aliasing purposes. */
3197 operands[1] = change_address (operands[1], BLKmode, XEXP (operands[1], 0));
3199 /* Otherwise, emit a lwl/lwr pair to load the value. */
3200 emit_insn (gen_movsi_ulw (operands[0], operands[1]));
3204 (define_expand "insv"
3205 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
3206 (match_operand:SI 1 "immediate_operand" "")
3207 (match_operand:SI 2 "immediate_operand" ""))
3208 (match_operand:SI 3 "register_operand" ""))]
3212 /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
3214 if (INTVAL (operands[1]) != 32 || (INTVAL (operands[2]) % 8) != 0)
3217 /* This can happen for a 64 bit target, when storing into a 32 bit union
3218 member. store_bit_field doesn't verify that our target matches the
3219 predicate, so we force it to be a MEM here. */
3220 if (GET_CODE (operands[0]) != MEM)
3223 /* Change the mode to BLKmode for aliasing purposes. */
3224 operands[0] = change_address (operands[0], BLKmode, XEXP (operands[0], 0));
3226 /* Otherwise, emit a swl/swr pair to load the value. */
3227 emit_insn (gen_movsi_usw (operands[0], operands[3]));
3231 ;; unaligned word moves generated by the bit field patterns
3233 (define_insn "movsi_ulw"
3234 [(set (match_operand:SI 0 "register_operand" "=&d,&d")
3235 (unspec:SI [(match_operand:BLK 1 "general_operand" "R,o")] 0))]
3239 rtx offset = const0_rtx;
3240 rtx addr = XEXP (operands[1], 0);
3241 rtx mem_addr = eliminate_constant_term (addr, &offset);
3245 mips_count_memory_refs (operands[1], 2);
3247 /* The stack/frame pointers are always aligned, so we can convert
3248 to the faster lw if we are referencing an aligned stack location. */
3250 if ((INTVAL (offset) & 3) == 0
3251 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
3252 ret = \"lw\\t%0,%1\";
3254 ret = \"ulw\\t%0,%1\";
3256 return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
3258 [(set_attr "type" "load,load")
3259 (set_attr "mode" "SI")
3260 (set_attr "length" "2,4")])
3262 (define_insn "movsi_usw"
3263 [(set (match_operand:BLK 0 "memory_operand" "=R,o")
3264 (unspec:BLK [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
3268 rtx offset = const0_rtx;
3269 rtx addr = XEXP (operands[0], 0);
3270 rtx mem_addr = eliminate_constant_term (addr, &offset);
3273 mips_count_memory_refs (operands[0], 2);
3275 /* The stack/frame pointers are always aligned, so we can convert
3276 to the faster sw if we are referencing an aligned stack location. */
3278 if ((INTVAL (offset) & 3) == 0
3279 && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
3280 return \"sw\\t%1,%0\";
3282 return \"usw\\t%z1,%0\";
3284 [(set_attr "type" "store")
3285 (set_attr "mode" "SI")
3286 (set_attr "length" "2,4")])
3288 ;; These two patterns support loading addresses with two instructions instead
3289 ;; of using the macro instruction la.
3291 ;; ??? mips_move_1word has support for HIGH, so this pattern may be
3295 [(set (match_operand:SI 0 "register_operand" "=r")
3296 (high:SI (match_operand:SI 1 "immediate_operand" "")))]
3297 "mips_split_addresses"
3298 "lui\\t%0,%%hi(%1) # high"
3299 [(set_attr "type" "move")
3300 (set_attr "length" "1")])
3303 [(set (match_operand:SI 0 "register_operand" "=r")
3304 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3305 (match_operand:SI 2 "immediate_operand" "")))]
3306 "mips_split_addresses"
3307 "addiu\\t%0,%1,%%lo(%2) # low"
3308 [(set_attr "type" "arith")
3309 (set_attr "mode" "SI")
3310 (set_attr "length" "1")])
3312 ;; 64-bit integer moves
3314 ;; Unlike most other insns, the move insns can't be split with
3315 ;; different predicates, because register spilling and other parts of
3316 ;; the compiler, have memoized the insn number already.
3318 (define_expand "movdi"
3319 [(set (match_operand:DI 0 "nonimmediate_operand" "")
3320 (match_operand:DI 1 "general_operand" ""))]
3324 if (mips_split_addresses && mips_check_split (operands[1], DImode))
3326 enum machine_mode mode = GET_MODE (operands[0]);
3327 rtx tem = ((reload_in_progress | reload_completed)
3328 ? operands[0] : gen_reg_rtx (mode));
3330 emit_insn (gen_rtx (SET, VOIDmode, tem,
3331 gen_rtx (HIGH, mode, operands[1])));
3333 operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
3336 /* If we are generating embedded PIC code, and we are referring to a
3337 symbol in the .text section, we must use an offset from the start
3339 if (TARGET_EMBEDDED_PIC
3340 && (GET_CODE (operands[1]) == LABEL_REF
3341 || (GET_CODE (operands[1]) == SYMBOL_REF
3342 && ! SYMBOL_REF_FLAG (operands[1]))))
3346 temp = embedded_pic_offset (operands[1]);
3347 temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
3348 force_reg (DImode, temp));
3349 emit_move_insn (operands[0], force_reg (DImode, temp));
3353 /* If operands[1] is a constant address illegal for pic, then we need to
3354 handle it just like LEGITIMIZE_ADDRESS does. */
3355 if (flag_pic && pic_address_needs_scratch (operands[1]))
3357 rtx temp = force_reg (DImode, XEXP (XEXP (operands[1], 0), 0));
3358 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
3360 if (! SMALL_INT (temp2))
3361 temp2 = force_reg (DImode, temp2);
3363 emit_move_insn (operands[0], gen_rtx (PLUS, DImode, temp, temp2));
3367 if ((reload_in_progress | reload_completed) == 0
3368 && !register_operand (operands[0], DImode)
3369 && !register_operand (operands[1], DImode)
3370 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
3371 && operands[1] != CONST0_RTX (DImode))
3373 rtx temp = force_reg (DImode, operands[1]);
3374 emit_move_insn (operands[0], temp);
3379 (define_insn "movdi_internal"
3380 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*x,*d,*x")
3381 (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,J,*x,*d"))]
3383 && (register_operand (operands[0], DImode)
3384 || register_operand (operands[1], DImode)
3385 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3386 || operands[1] == CONST0_RTX (DImode))"
3387 "* return mips_move_2words (operands, insn); "
3388 [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo,hilo")
3389 (set_attr "mode" "DI")
3390 (set_attr "length" "2,4,2,4,2,4,2,2,2")])
3393 [(set (match_operand:DI 0 "register_operand" "")
3394 (match_operand:DI 1 "register_operand" ""))]
3395 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
3396 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3397 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
3399 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
3400 (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
3403 (define_insn "movdi_internal2"
3404 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*x,*d,*x,*a")
3405 (match_operand:DI 1 "movdi_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,J,*x,*d,*J"))]
3407 && (register_operand (operands[0], DImode)
3408 || se_register_operand (operands[1], DImode)
3409 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3410 || operands[1] == CONST0_RTX (DImode))"
3411 "* return mips_move_2words (operands, insn); "
3412 [(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo,hilo,hilo")
3413 (set_attr "mode" "DI")
3414 (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,2")])
3416 ;; Handle input reloads in DImode.
3417 ;; This is mainly to handle reloading HILO_REGNUM. Note that we may
3418 ;; see it as the source or the destination, depending upon which way
3419 ;; reload handles the instruction.
3420 ;; Making the second operand TImode is a trick. The compiler may
3421 ;; reuse the same register for operand 0 and operand 2. Using TImode
3422 ;; gives us two registers, so we can always use the one which is not
3425 (define_expand "reload_indi"
3426 [(set (match_operand:DI 0 "register_operand" "=b")
3427 (match_operand:DI 1 "movdi_operand" "b"))
3428 (clobber (match_operand:TI 2 "register_operand" "=&d"))]
3432 rtx scratch = gen_rtx (REG, DImode,
3433 (REGNO (operands[0]) == REGNO (operands[2])
3434 ? REGNO (operands[2]) + 1
3435 : REGNO (operands[2])));
3437 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
3439 if (GET_CODE (operands[1]) == MEM)
3441 rtx memword, offword, hiword, loword;
3443 scratch = gen_rtx (REG, SImode, REGNO (scratch));
3444 memword = change_address (operands[1], SImode, NULL_RTX);
3445 offword = change_address (adj_offsettable_operand (operands[1], 4),
3447 if (BYTES_BIG_ENDIAN)
3457 emit_move_insn (scratch, hiword);
3458 emit_move_insn (gen_rtx (REG, SImode, 64), scratch);
3459 emit_move_insn (scratch, loword);
3460 emit_move_insn (gen_rtx (REG, SImode, 65), scratch);
3464 emit_insn (gen_ashrdi3 (scratch, operands[1], GEN_INT (32)));
3465 emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), scratch));
3466 emit_insn (gen_ashldi3 (scratch, operands[1], GEN_INT (32)));
3467 emit_insn (gen_ashrdi3 (scratch, scratch, GEN_INT (32)));
3468 emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), scratch));
3472 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
3474 emit_insn (gen_movdi (scratch, gen_rtx (REG, DImode, 65)));
3475 emit_insn (gen_ashldi3 (scratch, scratch, GEN_INT (32)));
3476 emit_insn (gen_lshrdi3 (scratch, scratch, GEN_INT (32)));
3477 emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
3478 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
3479 emit_insn (gen_iordi3 (operands[0], operands[0], scratch));
3482 /* This handles moves between a float register and HI/LO. */
3483 emit_move_insn (scratch, operands[1]);
3484 emit_move_insn (operands[0], scratch);
3488 ;; Handle output reloads in DImode.
3490 (define_expand "reload_outdi"
3491 [(set (match_operand:DI 0 "general_operand" "=b")
3492 (match_operand:DI 1 "se_register_operand" "b"))
3493 (clobber (match_operand:DI 2 "register_operand" "=&d"))]
3497 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
3499 emit_insn (gen_ashrdi3 (operands[2], operands[1], GEN_INT (32)));
3500 emit_insn (gen_movdi (gen_rtx (REG, DImode, 64), operands[2]));
3501 emit_insn (gen_ashldi3 (operands[2], operands[1], GEN_INT (32)));
3502 emit_insn (gen_ashrdi3 (operands[2], operands[2], GEN_INT (32)));
3503 emit_insn (gen_movdi (gen_rtx (REG, DImode, 65), operands[2]));
3506 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) == HILO_REGNUM)
3508 if (GET_CODE (operands[0]) == MEM)
3510 rtx scratch, memword, offword, hiword, loword;
3512 scratch = gen_rtx (REG, SImode, REGNO (operands[2]));
3513 memword = change_address (operands[0], SImode, NULL_RTX);
3514 offword = change_address (adj_offsettable_operand (operands[0], 4),
3516 if (BYTES_BIG_ENDIAN)
3526 emit_move_insn (scratch, gen_rtx (REG, SImode, 64));
3527 emit_move_insn (hiword, scratch);
3528 emit_move_insn (scratch, gen_rtx (REG, SImode, 65));
3529 emit_move_insn (loword, scratch);
3533 emit_insn (gen_movdi (operands[2], gen_rtx (REG, DImode, 65)));
3534 emit_insn (gen_ashldi3 (operands[2], operands[2], GEN_INT (32)));
3535 emit_insn (gen_lshrdi3 (operands[2], operands[2], GEN_INT (32)));
3536 emit_insn (gen_movdi (operands[0], gen_rtx (REG, DImode, 64)));
3537 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
3538 emit_insn (gen_iordi3 (operands[0], operands[0], operands[2]));
3542 /* This handles moves between a float register and HI/LO. */
3543 emit_move_insn (operands[2], operands[1]);
3544 emit_move_insn (operands[0], operands[2]);
3548 ;; 32-bit Integer moves
3551 [(set (match_operand:SI 0 "register_operand" "")
3552 (match_operand:SI 1 "large_int" ""))]
3553 "!TARGET_DEBUG_D_MODE"
3557 (ior:SI (match_dup 0)
3561 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff0000);
3562 operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0x0000ffff);
3565 ;; Unlike most other insns, the move insns can't be split with
3566 ;; different predicates, because register spilling and other parts of
3567 ;; the compiler, have memoized the insn number already.
3569 (define_expand "movsi"
3570 [(set (match_operand:SI 0 "nonimmediate_operand" "")
3571 (match_operand:SI 1 "general_operand" ""))]
3575 if (mips_split_addresses && mips_check_split (operands[1], SImode))
3577 enum machine_mode mode = GET_MODE (operands[0]);
3578 rtx tem = ((reload_in_progress | reload_completed)
3579 ? operands[0] : gen_reg_rtx (mode));
3581 emit_insn (gen_rtx (SET, VOIDmode, tem,
3582 gen_rtx (HIGH, mode, operands[1])));
3584 operands[1] = gen_rtx (LO_SUM, mode, tem, operands[1]);
3587 /* If we are generating embedded PIC code, and we are referring to a
3588 symbol in the .text section, we must use an offset from the start
3590 if (TARGET_EMBEDDED_PIC
3591 && (GET_CODE (operands[1]) == LABEL_REF
3592 || (GET_CODE (operands[1]) == SYMBOL_REF
3593 && ! SYMBOL_REF_FLAG (operands[1]))))
3597 temp = embedded_pic_offset (operands[1]);
3598 temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
3599 force_reg (SImode, temp));
3600 emit_move_insn (operands[0], force_reg (SImode, temp));
3604 /* If operands[1] is a constant address invalid for pic, then we need to
3605 handle it just like LEGITIMIZE_ADDRESS does. */
3606 if (flag_pic && pic_address_needs_scratch (operands[1]))
3608 rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
3609 rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
3611 if (! SMALL_INT (temp2))
3612 temp2 = force_reg (SImode, temp2);
3614 emit_move_insn (operands[0], gen_rtx (PLUS, SImode, temp, temp2));
3618 if ((reload_in_progress | reload_completed) == 0
3619 && !register_operand (operands[0], SImode)
3620 && !register_operand (operands[1], SImode)
3621 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
3623 rtx temp = force_reg (SImode, operands[1]);
3624 emit_move_insn (operands[0], temp);
3629 ;; The difference between these two is whether or not ints are allowed
3630 ;; in FP registers (off by default, use -mdebugh to enable).
3632 (define_insn "movsi_internal1"
3633 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*x,*d,*d")
3634 (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,J,*d,*x,*a"))]
3635 "TARGET_DEBUG_H_MODE
3636 && (register_operand (operands[0], SImode)
3637 || register_operand (operands[1], SImode)
3638 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3639 "* return mips_move_1word (operands, insn, FALSE);"
3640 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo,hilo,hilo")
3641 (set_attr "mode" "SI")
3642 (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1,1,1")])
3644 (define_insn "movsi_internal2"
3645 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*x,*d,*x,*d")
3646 (match_operand:SI 1 "move_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,J,*x,*d,*a"))]
3647 "!TARGET_DEBUG_H_MODE
3648 && (register_operand (operands[0], SImode)
3649 || register_operand (operands[1], SImode)
3650 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3651 "* return mips_move_1word (operands, insn, FALSE);"
3652 [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo,hilo,hilo")
3653 (set_attr "mode" "SI")
3654 (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,1,1")])
3656 ;; Reload HILO_REGNUM in SI mode. This needs a scratch register in
3657 ;; order to set the sign bit correctly in the HI register.
3659 (define_expand "reload_outsi"
3660 [(set (match_operand:SI 0 "general_operand" "=b")
3661 (match_operand:SI 1 "register_operand" "d"))
3662 (clobber (match_operand:SI 2 "register_operand" "=&d"))]
3666 if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) == HILO_REGNUM)
3668 emit_insn (gen_movsi (gen_rtx (REG, SImode, 65), operands[1]));
3669 emit_insn (gen_ashrsi3 (operands[2], operands[1], GEN_INT (31)));
3670 emit_insn (gen_movsi (gen_rtx (REG, SImode, 64), operands[2]));
3673 /* This handles moves between a float register and HI/LO. */
3674 emit_move_insn (operands[2], operands[1]);
3675 emit_move_insn (operands[0], operands[2]);
3679 ;; This insn handles moving CCmode values. It's really just a
3680 ;; slightly simplified copy of movsi_internal2, with additional cases
3681 ;; to move a condition register to a general register and to move
3682 ;; between the general registers and the floating point registers.
3684 (define_insn "movcc"
3685 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*d,*R,*m,*d,*f,*f,*f,*f,*R,*m")
3686 (match_operand:CC 1 "general_operand" "z,*d,*R,*m,*d,*d,*f,*d,*f,*R,*m,*f,*f"))]
3687 "mips_isa >= 4 && TARGET_HARD_FLOAT"
3688 "* return mips_move_1word (operands, insn, FALSE);"
3689 [(set_attr "type" "move,move,load,load,store,store,xfer,xfer,move,load,load,store,store")
3690 (set_attr "mode" "SI")
3691 (set_attr "length" "2,1,1,2,1,2,1,1,1,1,2,1,2")])
3693 ;; Reload condition code registers. These need scratch registers.
3695 (define_expand "reload_incc"
3696 [(set (match_operand:CC 0 "register_operand" "=z")
3697 (match_operand:CC 1 "general_operand" "z"))
3698 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3699 "mips_isa >= 4 && TARGET_HARD_FLOAT"
3705 /* This is called when are copying some value into a condition code
3706 register. Operand 0 is the condition code register. Operand 1
3707 is the source. Operand 2 is a scratch register; we use TFmode
3708 because we actually need two floating point registers. */
3709 if (! ST_REG_P (true_regnum (operands[0]))
3710 || ! FP_REG_P (true_regnum (operands[2])))
3713 /* We need to get the source in SFmode so that the insn is
3715 if (GET_CODE (operands[1]) == MEM)
3716 source = change_address (operands[1], SFmode, NULL_RTX);
3717 else if (GET_CODE (operands[1]) == REG || GET_CODE (operands[1]) == SUBREG)
3718 source = gen_rtx (REG, SFmode, true_regnum (operands[1]));
3720 source = operands[1];
3722 fp1 = gen_rtx (REG, SFmode, REGNO (operands[2]));
3723 fp2 = gen_rtx (REG, SFmode, REGNO (operands[2]) + 1);
3725 emit_insn (gen_move_insn (fp1, source));
3726 emit_insn (gen_move_insn (fp2, gen_rtx (REG, SFmode, 0)));
3727 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
3728 gen_rtx (LT, CCmode, fp2, fp1)));
3733 (define_expand "reload_outcc"
3734 [(set (match_operand:CC 0 "general_operand" "=z")
3735 (match_operand:CC 1 "register_operand" "z"))
3736 (clobber (match_operand:CC 2 "register_operand" "=&d"))]
3737 "mips_isa >= 4 && TARGET_HARD_FLOAT"
3740 /* This is called when we are copying a condition code register out
3741 to save it somewhere. Operand 0 should be the location we are
3742 going to save it to. Operand 1 should be the condition code
3743 register. Operand 2 should be a scratch general purpose register
3744 created for us by reload. The mips_secondary_reload_class
3745 function should have told reload that we don't need a scratch
3746 register if the destination is a general purpose register anyhow. */
3747 if (ST_REG_P (true_regnum (operands[0]))
3748 || GP_REG_P (true_regnum (operands[0]))
3749 || ! ST_REG_P (true_regnum (operands[1]))
3750 || ! GP_REG_P (true_regnum (operands[2])))
3753 /* All we have to do is copy the value from the condition code to
3754 the data register, which movcc can handle, and then store the
3755 value into the real final destination. */
3756 emit_insn (gen_move_insn (operands[2], operands[1]));
3757 emit_insn (gen_move_insn (operands[0], operands[2]));
3762 ;; MIPS4 supports loading and storing a floating point register from
3763 ;; the sum of two general registers. We use two versions for each of
3764 ;; these four instructions: one where the two general registers are
3765 ;; SImode, and one where they are DImode. This is because general
3766 ;; registers will be in SImode when they hold 32 bit values, but,
3767 ;; since the 32 bit values are always sign extended, the [ls][wd]xc1
3768 ;; instructions will still work correctly.
3770 ;; ??? Perhaps it would be better to support these instructions by
3771 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3772 ;; these instructions can only be used to load and store floating
3773 ;; point registers, that would probably cause trouble in reload.
3776 [(set (match_operand:SF 0 "register_operand" "=f")
3777 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
3778 (match_operand:SI 2 "register_operand" "d"))))]
3779 "mips_isa >= 4 && TARGET_HARD_FLOAT"
3781 [(set_attr "type" "load")
3782 (set_attr "mode" "SF")
3783 (set_attr "length" "1")])
3786 [(set (match_operand:SF 0 "register_operand" "=f")
3787 (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
3788 (match_operand:DI 2 "se_register_operand" "d"))))]
3789 "mips_isa >= 4 && TARGET_HARD_FLOAT"
3791 [(set_attr "type" "load")
3792 (set_attr "mode" "SF")
3793 (set_attr "length" "1")])
3796 [(set (match_operand:DF 0 "register_operand" "=f")
3797 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
3798 (match_operand:SI 2 "register_operand" "d"))))]
3799 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3801 [(set_attr "type" "load")
3802 (set_attr "mode" "DF")
3803 (set_attr "length" "1")])
3806 [(set (match_operand:DF 0 "register_operand" "=f")
3807 (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
3808 (match_operand:DI 2 "se_register_operand" "d"))))]
3809 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3811 [(set_attr "type" "load")
3812 (set_attr "mode" "DF")
3813 (set_attr "length" "1")])
3816 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
3817 (match_operand:SI 2 "register_operand" "d")))
3818 (match_operand:SF 0 "register_operand" "=f"))]
3819 "mips_isa >= 4 && TARGET_HARD_FLOAT"
3821 [(set_attr "type" "store")
3822 (set_attr "mode" "SF")
3823 (set_attr "length" "1")])
3826 [(set (mem:SF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
3827 (match_operand:DI 2 "se_register_operand" "d")))
3828 (match_operand:SF 0 "register_operand" "=f"))]
3829 "mips_isa >= 4 && TARGET_HARD_FLOAT"
3831 [(set_attr "type" "store")
3832 (set_attr "mode" "SF")
3833 (set_attr "length" "1")])
3836 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
3837 (match_operand:SI 2 "register_operand" "d")))
3838 (match_operand:DF 0 "register_operand" "=f"))]
3839 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3841 [(set_attr "type" "store")
3842 (set_attr "mode" "DF")
3843 (set_attr "length" "1")])
3846 [(set (mem:DF (plus:DI (match_operand:DI 1 "se_register_operand" "d")
3847 (match_operand:DI 2 "se_register_operand" "d")))
3848 (match_operand:DF 0 "register_operand" "=f"))]
3849 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
3851 [(set_attr "type" "store")
3852 (set_attr "mode" "DF")
3853 (set_attr "length" "1")])
3855 ;; 16-bit Integer moves
3857 ;; Unlike most other insns, the move insns can't be split with
3858 ;; different predicates, because register spilling and other parts of
3859 ;; the compiler, have memoized the insn number already.
3860 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
3862 (define_expand "movhi"
3863 [(set (match_operand:HI 0 "nonimmediate_operand" "")
3864 (match_operand:HI 1 "general_operand" ""))]
3868 if ((reload_in_progress | reload_completed) == 0
3869 && !register_operand (operands[0], HImode)
3870 && !register_operand (operands[1], HImode)
3871 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
3873 rtx temp = force_reg (HImode, operands[1]);
3874 emit_move_insn (operands[0], temp);
3879 ;; The difference between these two is whether or not ints are allowed
3880 ;; in FP registers (off by default, use -mdebugh to enable).
3882 (define_insn "movhi_internal1"
3883 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
3884 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
3885 "TARGET_DEBUG_H_MODE
3886 && (register_operand (operands[0], HImode)
3887 || register_operand (operands[1], HImode)
3888 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3889 "* return mips_move_1word (operands, insn, TRUE);"
3890 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
3891 (set_attr "mode" "HI")
3892 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
3894 (define_insn "movhi_internal2"
3895 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
3896 (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
3897 "!TARGET_DEBUG_H_MODE
3898 && (register_operand (operands[0], HImode)
3899 || register_operand (operands[1], HImode)
3900 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3901 "* return mips_move_1word (operands, insn, TRUE);"
3902 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
3903 (set_attr "mode" "HI")
3904 (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
3907 ;; 8-bit Integer moves
3909 ;; Unlike most other insns, the move insns can't be split with
3910 ;; different predicates, because register spilling and other parts of
3911 ;; the compiler, have memoized the insn number already.
3912 ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
3914 (define_expand "movqi"
3915 [(set (match_operand:QI 0 "nonimmediate_operand" "")
3916 (match_operand:QI 1 "general_operand" ""))]
3920 if ((reload_in_progress | reload_completed) == 0
3921 && !register_operand (operands[0], QImode)
3922 && !register_operand (operands[1], QImode)
3923 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
3925 rtx temp = force_reg (QImode, operands[1]);
3926 emit_move_insn (operands[0], temp);
3931 ;; The difference between these two is whether or not ints are allowed
3932 ;; in FP registers (off by default, use -mdebugh to enable).
3934 (define_insn "movqi_internal1"
3935 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
3936 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
3937 "TARGET_DEBUG_H_MODE
3938 && (register_operand (operands[0], QImode)
3939 || register_operand (operands[1], QImode)
3940 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3941 "* return mips_move_1word (operands, insn, TRUE);"
3942 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
3943 (set_attr "mode" "QI")
3944 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
3946 (define_insn "movqi_internal2"
3947 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
3948 (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
3949 "!TARGET_DEBUG_H_MODE
3950 && (register_operand (operands[0], QImode)
3951 || register_operand (operands[1], QImode)
3952 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3953 "* return mips_move_1word (operands, insn, TRUE);"
3954 [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
3955 (set_attr "mode" "QI")
3956 (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
3959 ;; 32-bit floating point moves
3961 (define_expand "movsf"
3962 [(set (match_operand:SF 0 "nonimmediate_operand" "")
3963 (match_operand:SF 1 "general_operand" ""))]
3967 if ((reload_in_progress | reload_completed) == 0
3968 && !register_operand (operands[0], SFmode)
3969 && !register_operand (operands[1], SFmode)
3970 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
3971 && operands[1] != CONST0_RTX (SFmode))
3973 rtx temp = force_reg (SFmode, operands[1]);
3974 emit_move_insn (operands[0], temp);
3979 (define_insn "movsf_internal1"
3980 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
3981 (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
3983 && (register_operand (operands[0], SFmode)
3984 || register_operand (operands[1], SFmode)
3985 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3986 || operands[1] == CONST0_RTX (SFmode))"
3987 "* return mips_move_1word (operands, insn, FALSE);"
3988 [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
3989 (set_attr "mode" "SF")
3990 (set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")])
3993 (define_insn "movsf_internal2"
3994 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
3995 (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))]
3997 && (register_operand (operands[0], SFmode)
3998 || register_operand (operands[1], SFmode)
3999 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
4000 || operands[1] == CONST0_RTX (SFmode))"
4001 "* return mips_move_1word (operands, insn, FALSE);"
4002 [(set_attr "type" "move,load,load,store,store")
4003 (set_attr "mode" "SF")
4004 (set_attr "length" "1,1,2,1,2")])
4007 ;; 64-bit floating point moves
4009 (define_expand "movdf"
4010 [(set (match_operand:DF 0 "nonimmediate_operand" "")
4011 (match_operand:DF 1 "general_operand" ""))]
4015 if ((reload_in_progress | reload_completed) == 0
4016 && !register_operand (operands[0], DFmode)
4017 && !register_operand (operands[1], DFmode)
4018 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
4019 && operands[1] != CONST0_RTX (DFmode))
4021 rtx temp = force_reg (DFmode, operands[1]);
4022 emit_move_insn (operands[0], temp);
4027 (define_insn "movdf_internal1"
4028 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,o,f,*f,*d,*d,*d,*d,*R,*o")
4029 (match_operand:DF 1 "general_operand" "f,R,o,fG,fG,F,*d,*f,*d*G,*R,*o*F,*d,*d"))]
4030 "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
4031 && TARGET_DOUBLE_FLOAT
4032 && (register_operand (operands[0], DFmode)
4033 || register_operand (operands[1], DFmode)
4034 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
4035 || operands[1] == CONST0_RTX (DFmode))"
4036 "* return mips_move_2words (operands, insn); "
4037 [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
4038 (set_attr "mode" "DF")
4039 (set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")])
4041 (define_insn "movdf_internal1a"
4042 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,o,o,f,*d,*d,*d,*o,*R")
4043 (match_operand:DF 1 "general_operand" " f,o,f,G,f,G,F,*F,*o,*R,*d,*d"))]
4044 "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
4045 && TARGET_DOUBLE_FLOAT
4046 && (register_operand (operands[0], DFmode)
4047 || register_operand (operands[1], DFmode))
4048 || (GET_CODE (operands [0]) == MEM
4049 && ((GET_CODE (operands[1]) == CONST_INT
4050 && INTVAL (operands[1]) == 0)
4051 || operands[1] == CONST0_RTX (DFmode)))"
4052 "* return mips_move_2words (operands, insn); "
4053 [(set_attr "type" "move,load,store,store,store,store,load,load,load,load,store,store")
4054 (set_attr "mode" "DF")
4055 (set_attr "length" "1,2,1,1,2,2,2,2,2,1,2,1")])
4057 (define_insn "movdf_internal2"
4058 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,o")
4059 (match_operand:DF 1 "general_operand" "dG,R,oF,d,d"))]
4060 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT)
4061 && (register_operand (operands[0], DFmode)
4062 || register_operand (operands[1], DFmode)
4063 || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
4064 || operands[1] == CONST0_RTX (DFmode))"
4065 "* return mips_move_2words (operands, insn); "
4066 [(set_attr "type" "move,load,load,store,store")
4067 (set_attr "mode" "DF")
4068 (set_attr "length" "2,2,4,2,4")])
4071 [(set (match_operand:DF 0 "register_operand" "")
4072 (match_operand:DF 1 "register_operand" ""))]
4073 "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4074 && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
4075 && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
4076 [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
4077 (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
4080 ;; Instructions to load the global pointer register.
4081 ;; This is volatile to make sure that the scheduler won't move any symbol_ref
4082 ;; uses in front of it. All symbol_refs implicitly use the gp reg.
4084 (define_insn "loadgp"
4086 (unspec_volatile:DI [(match_operand:DI 0 "address_operand" "")] 2))
4087 (clobber (reg:DI 1))]
4089 "%[lui\\t$1,%%hi(%%neg(%%gp_rel(%a0)))\\n\\taddiu\\t$1,$1,%%lo(%%neg(%%gp_rel(%a0)))\\n\\tdaddu\\t$gp,$1,$25%]"
4090 [(set_attr "type" "move")
4091 (set_attr "mode" "DI")
4092 (set_attr "length" "3")])
4094 ;; Block moves, see mips.c for more details.
4095 ;; Argument 0 is the destination
4096 ;; Argument 1 is the source
4097 ;; Argument 2 is the length
4098 ;; Argument 3 is the alignment
4100 (define_expand "movstrsi"
4101 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
4102 (match_operand:BLK 1 "general_operand" ""))
4103 (use (match_operand:SI 2 "arith32_operand" ""))
4104 (use (match_operand:SI 3 "immediate_operand" ""))])]
4108 if (operands[0]) /* avoid unused code messages */
4110 expand_block_move (operands);
4115 ;; Insn generated by block moves
4117 (define_insn "movstrsi_internal"
4118 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
4119 (match_operand:BLK 1 "memory_operand" "o")) ;; source
4120 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
4121 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
4122 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
4123 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
4124 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
4125 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
4126 (use (const_int 0))] ;; normal block move
4128 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
4129 [(set_attr "type" "store")
4130 (set_attr "mode" "none")
4131 (set_attr "length" "20")])
4133 ;; Split a block move into 2 parts, the first part is everything
4134 ;; except for the last move, and the second part is just the last
4135 ;; store, which is exactly 1 instruction (ie, not a usw), so it can
4136 ;; fill a delay slot. This also prevents a bug in delayed branches
4137 ;; from showing up, which reuses one of the registers in our clobbers.
4140 [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
4141 (mem:BLK (match_operand:SI 1 "register_operand" "")))
4142 (clobber (match_operand:SI 4 "register_operand" ""))
4143 (clobber (match_operand:SI 5 "register_operand" ""))
4144 (clobber (match_operand:SI 6 "register_operand" ""))
4145 (clobber (match_operand:SI 7 "register_operand" ""))
4146 (use (match_operand:SI 2 "small_int" ""))
4147 (use (match_operand:SI 3 "small_int" ""))
4148 (use (const_int 0))]
4150 "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
4152 ;; All but the last move
4153 [(parallel [(set (mem:BLK (match_dup 0))
4154 (mem:BLK (match_dup 1)))
4155 (clobber (match_dup 4))
4156 (clobber (match_dup 5))
4157 (clobber (match_dup 6))
4158 (clobber (match_dup 7))
4161 (use (const_int 1))])
4163 ;; The last store, so it can fill a delay slot
4164 (parallel [(set (mem:BLK (match_dup 0))
4165 (mem:BLK (match_dup 1)))
4166 (clobber (match_dup 4))
4167 (clobber (match_dup 5))
4168 (clobber (match_dup 6))
4169 (clobber (match_dup 7))
4172 (use (const_int 2))])]
4176 (define_insn "movstrsi_internal2"
4177 [(set (match_operand:BLK 0 "memory_operand" "=o") ;; destination
4178 (match_operand:BLK 1 "memory_operand" "o")) ;; source
4179 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
4180 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
4181 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
4182 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
4183 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
4184 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
4185 (use (const_int 1))] ;; all but last store
4187 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
4188 [(set_attr "type" "store")
4189 (set_attr "mode" "none")
4190 (set_attr "length" "20")])
4192 (define_insn "movstrsi_internal3"
4193 [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
4194 (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
4195 (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
4196 (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
4197 (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
4198 (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
4199 (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
4200 (use (match_operand:SI 3 "small_int" "I")) ;; alignment
4201 (use (const_int 2))] ;; just last store of block move
4203 "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
4204 [(set_attr "type" "store")
4205 (set_attr "mode" "none")
4206 (set_attr "length" "1")])
4210 ;; ....................
4214 ;; ....................
4216 (define_insn "ashlsi3"
4217 [(set (match_operand:SI 0 "register_operand" "=d")
4218 (ashift:SI (match_operand:SI 1 "register_operand" "d")
4219 (match_operand:SI 2 "arith_operand" "dI")))]
4223 if (GET_CODE (operands[2]) == CONST_INT)
4224 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);
4226 return \"sll\\t%0,%1,%2\";
4228 [(set_attr "type" "arith")
4229 (set_attr "mode" "SI")
4230 (set_attr "length" "1")])
4233 (define_expand "ashldi3"
4234 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4235 (ashift:DI (match_operand:DI 1 "se_register_operand" "")
4236 (match_operand:SI 2 "arith_operand" "")))
4237 (clobber (match_dup 3))])]
4238 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
4243 emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
4248 operands[3] = gen_reg_rtx (SImode);
4252 (define_insn "ashldi3_internal"
4253 [(set (match_operand:DI 0 "register_operand" "=&d")
4254 (ashift:DI (match_operand:DI 1 "register_operand" "d")
4255 (match_operand:SI 2 "register_operand" "d")))
4256 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4257 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
4260 operands[4] = const0_rtx;
4261 dslots_jump_total += 3;
4262 dslots_jump_filled += 2;
4264 return \"sll\\t%3,%2,26\\n\\
4265 \\tbgez\\t%3,1f\\n\\
4266 \\tsll\\t%M0,%L1,%2\\n\\
4268 \\tmove\\t%L0,%z4%)\\n\\
4271 \\t%(beq\\t%3,%z4,2f\\n\\
4272 \\tsll\\t%M0,%M1,%2%)\\n\\
4274 \\tsubu\\t%3,%z4,%2\\n\\
4275 \\tsrl\\t%3,%L1,%3\\n\\
4276 \\tor\\t%M0,%M0,%3\\n\\
4278 \\tsll\\t%L0,%L1,%2\\n\\
4281 [(set_attr "type" "darith")
4282 (set_attr "mode" "SI")
4283 (set_attr "length" "12")])
4286 (define_insn "ashldi3_internal2"
4287 [(set (match_operand:DI 0 "register_operand" "=d")
4288 (ashift:DI (match_operand:DI 1 "register_operand" "d")
4289 (match_operand:SI 2 "small_int" "IJK")))
4290 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4291 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
4294 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);
4295 operands[4] = const0_rtx;
4296 return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
4298 [(set_attr "type" "darith")
4299 (set_attr "mode" "DI")
4300 (set_attr "length" "2")])
4304 [(set (match_operand:DI 0 "register_operand" "")
4305 (ashift:DI (match_operand:DI 1 "register_operand" "")
4306 (match_operand:SI 2 "small_int" "")))
4307 (clobber (match_operand:SI 3 "register_operand" ""))]
4308 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4309 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4310 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4311 && (INTVAL (operands[2]) & 32) != 0"
4313 [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
4314 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
4316 "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);")
4320 [(set (match_operand:DI 0 "register_operand" "")
4321 (ashift:DI (match_operand:DI 1 "register_operand" "")
4322 (match_operand:SI 2 "small_int" "")))
4323 (clobber (match_operand:SI 3 "register_operand" ""))]
4324 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4325 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4326 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4327 && (INTVAL (operands[2]) & 32) != 0"
4329 [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
4330 (set (subreg:SI (match_dup 0) 1) (const_int 0))]
4332 "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);")
4335 (define_insn "ashldi3_internal3"
4336 [(set (match_operand:DI 0 "register_operand" "=d")
4337 (ashift:DI (match_operand:DI 1 "register_operand" "d")
4338 (match_operand:SI 2 "small_int" "IJK")))
4339 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4340 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
4341 && (INTVAL (operands[2]) & 63) < 32
4342 && (INTVAL (operands[2]) & 63) != 0"
4345 int amount = INTVAL (operands[2]);
4347 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4348 operands[4] = const0_rtx;
4349 operands[5] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4351 return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
4353 [(set_attr "type" "darith")
4354 (set_attr "mode" "DI")
4355 (set_attr "length" "4")])
4359 [(set (match_operand:DI 0 "register_operand" "")
4360 (ashift:DI (match_operand:DI 1 "register_operand" "")
4361 (match_operand:SI 2 "small_int" "")))
4362 (clobber (match_operand:SI 3 "register_operand" ""))]
4363 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4364 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4365 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4366 && (INTVAL (operands[2]) & 63) < 32
4367 && (INTVAL (operands[2]) & 63) != 0"
4369 [(set (subreg:SI (match_dup 0) 1)
4370 (ashift:SI (subreg:SI (match_dup 1) 1)
4374 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
4377 (set (subreg:SI (match_dup 0) 1)
4378 (ior:SI (subreg:SI (match_dup 0) 1)
4381 (set (subreg:SI (match_dup 0) 0)
4382 (ashift:SI (subreg:SI (match_dup 1) 0)
4386 int amount = INTVAL (operands[2]);
4387 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4388 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4393 [(set (match_operand:DI 0 "register_operand" "")
4394 (ashift:DI (match_operand:DI 1 "register_operand" "")
4395 (match_operand:SI 2 "small_int" "")))
4396 (clobber (match_operand:SI 3 "register_operand" ""))]
4397 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4398 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4399 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4400 && (INTVAL (operands[2]) & 63) < 32
4401 && (INTVAL (operands[2]) & 63) != 0"
4403 [(set (subreg:SI (match_dup 0) 0)
4404 (ashift:SI (subreg:SI (match_dup 1) 0)
4408 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
4411 (set (subreg:SI (match_dup 0) 0)
4412 (ior:SI (subreg:SI (match_dup 0) 0)
4415 (set (subreg:SI (match_dup 0) 1)
4416 (ashift:SI (subreg:SI (match_dup 1) 1)
4420 int amount = INTVAL (operands[2]);
4421 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4422 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4426 (define_insn "ashldi3_internal4"
4427 [(set (match_operand:DI 0 "register_operand" "=d")
4428 (ashift:DI (match_operand:DI 1 "se_register_operand" "d")
4429 (match_operand:SI 2 "arith_operand" "dI")))]
4433 if (GET_CODE (operands[2]) == CONST_INT)
4434 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4436 return \"dsll\\t%0,%1,%2\";
4438 [(set_attr "type" "arith")
4439 (set_attr "mode" "DI")
4440 (set_attr "length" "1")])
4443 (define_insn "ashrsi3"
4444 [(set (match_operand:SI 0 "register_operand" "=d")
4445 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
4446 (match_operand:SI 2 "arith_operand" "dI")))]
4450 if (GET_CODE (operands[2]) == CONST_INT)
4451 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);
4453 return \"sra\\t%0,%1,%2\";
4455 [(set_attr "type" "arith")
4456 (set_attr "mode" "SI")
4457 (set_attr "length" "1")])
4460 (define_expand "ashrdi3"
4461 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4462 (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "")
4463 (match_operand:SI 2 "arith_operand" "")))
4464 (clobber (match_dup 3))])]
4465 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
4470 emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
4475 operands[3] = gen_reg_rtx (SImode);
4479 (define_insn "ashrdi3_internal"
4480 [(set (match_operand:DI 0 "register_operand" "=&d")
4481 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
4482 (match_operand:SI 2 "register_operand" "d")))
4483 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4484 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
4487 operands[4] = const0_rtx;
4488 dslots_jump_total += 3;
4489 dslots_jump_filled += 2;
4491 return \"sll\\t%3,%2,26\\n\\
4492 \\tbgez\\t%3,1f\\n\\
4493 \\tsra\\t%L0,%M1,%2\\n\\
4495 \\tsra\\t%M0,%M1,31%)\\n\\
4498 \\t%(beq\\t%3,%z4,2f\\n\\
4499 \\tsrl\\t%L0,%L1,%2%)\\n\\
4501 \\tsubu\\t%3,%z4,%2\\n\\
4502 \\tsll\\t%3,%M1,%3\\n\\
4503 \\tor\\t%L0,%L0,%3\\n\\
4505 \\tsra\\t%M0,%M1,%2\\n\\
4508 [(set_attr "type" "darith")
4509 (set_attr "mode" "DI")
4510 (set_attr "length" "12")])
4513 (define_insn "ashrdi3_internal2"
4514 [(set (match_operand:DI 0 "register_operand" "=d")
4515 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
4516 (match_operand:SI 2 "small_int" "IJK")))
4517 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4518 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
4521 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);
4522 return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
4524 [(set_attr "type" "darith")
4525 (set_attr "mode" "DI")
4526 (set_attr "length" "2")])
4530 [(set (match_operand:DI 0 "register_operand" "")
4531 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4532 (match_operand:SI 2 "small_int" "")))
4533 (clobber (match_operand:SI 3 "register_operand" ""))]
4534 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4535 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4536 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4537 && (INTVAL (operands[2]) & 32) != 0"
4539 [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
4540 (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))]
4542 "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);")
4546 [(set (match_operand:DI 0 "register_operand" "")
4547 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4548 (match_operand:SI 2 "small_int" "")))
4549 (clobber (match_operand:SI 3 "register_operand" ""))]
4550 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4551 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4552 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4553 && (INTVAL (operands[2]) & 32) != 0"
4555 [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
4556 (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
4558 "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);")
4561 (define_insn "ashrdi3_internal3"
4562 [(set (match_operand:DI 0 "register_operand" "=d")
4563 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
4564 (match_operand:SI 2 "small_int" "IJK")))
4565 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4566 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
4567 && (INTVAL (operands[2]) & 63) < 32
4568 && (INTVAL (operands[2]) & 63) != 0"
4571 int amount = INTVAL (operands[2]);
4573 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4574 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4576 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
4578 [(set_attr "type" "darith")
4579 (set_attr "mode" "DI")
4580 (set_attr "length" "4")])
4584 [(set (match_operand:DI 0 "register_operand" "")
4585 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4586 (match_operand:SI 2 "small_int" "")))
4587 (clobber (match_operand:SI 3 "register_operand" ""))]
4588 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4589 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4590 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4591 && (INTVAL (operands[2]) & 63) < 32
4592 && (INTVAL (operands[2]) & 63) != 0"
4594 [(set (subreg:SI (match_dup 0) 0)
4595 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
4599 (ashift:SI (subreg:SI (match_dup 1) 1)
4602 (set (subreg:SI (match_dup 0) 0)
4603 (ior:SI (subreg:SI (match_dup 0) 0)
4606 (set (subreg:SI (match_dup 0) 1)
4607 (ashiftrt:SI (subreg:SI (match_dup 1) 1)
4611 int amount = INTVAL (operands[2]);
4612 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4613 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4618 [(set (match_operand:DI 0 "register_operand" "")
4619 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
4620 (match_operand:SI 2 "small_int" "")))
4621 (clobber (match_operand:SI 3 "register_operand" ""))]
4622 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4623 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4624 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4625 && (INTVAL (operands[2]) & 63) < 32
4626 && (INTVAL (operands[2]) & 63) != 0"
4628 [(set (subreg:SI (match_dup 0) 1)
4629 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
4633 (ashift:SI (subreg:SI (match_dup 1) 0)
4636 (set (subreg:SI (match_dup 0) 1)
4637 (ior:SI (subreg:SI (match_dup 0) 1)
4640 (set (subreg:SI (match_dup 0) 0)
4641 (ashiftrt:SI (subreg:SI (match_dup 1) 0)
4645 int amount = INTVAL (operands[2]);
4646 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4647 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4651 (define_insn "ashrdi3_internal4"
4652 [(set (match_operand:DI 0 "register_operand" "=d")
4653 (ashiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
4654 (match_operand:SI 2 "arith_operand" "dI")))]
4658 if (GET_CODE (operands[2]) == CONST_INT)
4659 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4661 return \"dsra\\t%0,%1,%2\";
4663 [(set_attr "type" "arith")
4664 (set_attr "mode" "DI")
4665 (set_attr "length" "1")])
4668 (define_insn "lshrsi3"
4669 [(set (match_operand:SI 0 "register_operand" "=d")
4670 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
4671 (match_operand:SI 2 "arith_operand" "dI")))]
4675 if (GET_CODE (operands[2]) == CONST_INT)
4676 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);
4678 return \"srl\\t%0,%1,%2\";
4680 [(set_attr "type" "arith")
4681 (set_attr "mode" "SI")
4682 (set_attr "length" "1")])
4685 (define_expand "lshrdi3"
4686 [(parallel [(set (match_operand:DI 0 "register_operand" "")
4687 (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "")
4688 (match_operand:SI 2 "arith_operand" "")))
4689 (clobber (match_dup 3))])]
4690 "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
4695 emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
4700 operands[3] = gen_reg_rtx (SImode);
4704 (define_insn "lshrdi3_internal"
4705 [(set (match_operand:DI 0 "register_operand" "=&d")
4706 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
4707 (match_operand:SI 2 "register_operand" "d")))
4708 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4709 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
4712 operands[4] = const0_rtx;
4713 dslots_jump_total += 3;
4714 dslots_jump_filled += 2;
4716 return \"sll\\t%3,%2,26\\n\\
4717 \\tbgez\\t%3,1f\\n\\
4718 \\tsrl\\t%L0,%M1,%2\\n\\
4720 \\tmove\\t%M0,%z4%)\\n\\
4723 \\t%(beq\\t%3,%z4,2f\\n\\
4724 \\tsrl\\t%L0,%L1,%2%)\\n\\
4726 \\tsubu\\t%3,%z4,%2\\n\\
4727 \\tsll\\t%3,%M1,%3\\n\\
4728 \\tor\\t%L0,%L0,%3\\n\\
4730 \\tsrl\\t%M0,%M1,%2\\n\\
4733 [(set_attr "type" "darith")
4734 (set_attr "mode" "DI")
4735 (set_attr "length" "12")])
4738 (define_insn "lshrdi3_internal2"
4739 [(set (match_operand:DI 0 "register_operand" "=d")
4740 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
4741 (match_operand:SI 2 "small_int" "IJK")))
4742 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4743 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
4746 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);
4747 operands[4] = const0_rtx;
4748 return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
4750 [(set_attr "type" "darith")
4751 (set_attr "mode" "DI")
4752 (set_attr "length" "2")])
4756 [(set (match_operand:DI 0 "register_operand" "")
4757 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4758 (match_operand:SI 2 "small_int" "")))
4759 (clobber (match_operand:SI 3 "register_operand" ""))]
4760 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4761 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4762 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4763 && (INTVAL (operands[2]) & 32) != 0"
4765 [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
4766 (set (subreg:SI (match_dup 0) 1) (const_int 0))]
4768 "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);")
4772 [(set (match_operand:DI 0 "register_operand" "")
4773 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4774 (match_operand:SI 2 "small_int" "")))
4775 (clobber (match_operand:SI 3 "register_operand" ""))]
4776 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4777 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4778 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4779 && (INTVAL (operands[2]) & 32) != 0"
4781 [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
4782 (set (subreg:SI (match_dup 0) 0) (const_int 0))]
4784 "operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0x1f);")
4787 (define_insn "lshrdi3_internal3"
4788 [(set (match_operand:DI 0 "register_operand" "=d")
4789 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
4790 (match_operand:SI 2 "small_int" "IJK")))
4791 (clobber (match_operand:SI 3 "register_operand" "=d"))]
4792 "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
4793 && (INTVAL (operands[2]) & 63) < 32
4794 && (INTVAL (operands[2]) & 63) != 0"
4797 int amount = INTVAL (operands[2]);
4799 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4800 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4802 return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
4804 [(set_attr "type" "darith")
4805 (set_attr "mode" "DI")
4806 (set_attr "length" "4")])
4810 [(set (match_operand:DI 0 "register_operand" "")
4811 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4812 (match_operand:SI 2 "small_int" "")))
4813 (clobber (match_operand:SI 3 "register_operand" ""))]
4814 "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4815 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4816 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4817 && (INTVAL (operands[2]) & 63) < 32
4818 && (INTVAL (operands[2]) & 63) != 0"
4820 [(set (subreg:SI (match_dup 0) 0)
4821 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
4825 (ashift:SI (subreg:SI (match_dup 1) 1)
4828 (set (subreg:SI (match_dup 0) 0)
4829 (ior:SI (subreg:SI (match_dup 0) 0)
4832 (set (subreg:SI (match_dup 0) 1)
4833 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
4837 int amount = INTVAL (operands[2]);
4838 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4839 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4844 [(set (match_operand:DI 0 "register_operand" "")
4845 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
4846 (match_operand:SI 2 "small_int" "")))
4847 (clobber (match_operand:SI 3 "register_operand" ""))]
4848 "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
4849 && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
4850 && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
4851 && (INTVAL (operands[2]) & 63) < 32
4852 && (INTVAL (operands[2]) & 63) != 0"
4854 [(set (subreg:SI (match_dup 0) 1)
4855 (lshiftrt:SI (subreg:SI (match_dup 1) 1)
4859 (ashift:SI (subreg:SI (match_dup 1) 0)
4862 (set (subreg:SI (match_dup 0) 1)
4863 (ior:SI (subreg:SI (match_dup 0) 1)
4866 (set (subreg:SI (match_dup 0) 0)
4867 (lshiftrt:SI (subreg:SI (match_dup 1) 0)
4871 int amount = INTVAL (operands[2]);
4872 operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
4873 operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
4877 (define_insn "lshrdi3_internal4"
4878 [(set (match_operand:DI 0 "register_operand" "=d")
4879 (lshiftrt:DI (match_operand:DI 1 "se_register_operand" "d")
4880 (match_operand:SI 2 "arith_operand" "dI")))]
4884 if (GET_CODE (operands[2]) == CONST_INT)
4885 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4887 return \"dsrl\\t%0,%1,%2\";
4889 [(set_attr "type" "arith")
4890 (set_attr "mode" "DI")
4891 (set_attr "length" "1")])
4895 ;; ....................
4899 ;; ....................
4901 ;; Flow here is rather complex:
4903 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
4904 ;; arguments into the branch_cmp array, and the type into
4905 ;; branch_type. No RTL is generated.
4907 ;; 2) The appropriate branch define_expand is called, which then
4908 ;; creates the appropriate RTL for the comparison and branch.
4909 ;; Different CC modes are used, based on what type of branch is
4910 ;; done, so that we can constrain things appropriately. There
4911 ;; are assumptions in the rest of GCC that break if we fold the
4912 ;; operands into the branchs for integer operations, and use cc0
4913 ;; for floating point, so we use the fp status register instead.
4914 ;; If needed, an appropriate temporary is created to hold the
4915 ;; of the integer compare.
4917 (define_expand "cmpsi"
4919 (compare:CC (match_operand:SI 0 "register_operand" "")
4920 (match_operand:SI 1 "arith_operand" "")))]
4924 if (operands[0]) /* avoid unused code message */
4926 branch_cmp[0] = operands[0];
4927 branch_cmp[1] = operands[1];
4928 branch_type = CMP_SI;
4933 (define_expand "tstsi"
4935 (match_operand:SI 0 "register_operand" ""))]
4939 if (operands[0]) /* avoid unused code message */
4941 branch_cmp[0] = operands[0];
4942 branch_cmp[1] = const0_rtx;
4943 branch_type = CMP_SI;
4948 (define_expand "cmpdi"
4950 (compare:CC (match_operand:DI 0 "se_register_operand" "")
4951 (match_operand:DI 1 "se_arith_operand" "")))]
4955 if (operands[0]) /* avoid unused code message */
4957 branch_cmp[0] = operands[0];
4958 branch_cmp[1] = operands[1];
4959 branch_type = CMP_DI;
4964 (define_expand "tstdi"
4966 (match_operand:DI 0 "se_register_operand" ""))]
4970 if (operands[0]) /* avoid unused code message */
4972 branch_cmp[0] = operands[0];
4973 branch_cmp[1] = const0_rtx;
4974 branch_type = CMP_DI;
4979 (define_expand "cmpdf"
4981 (compare:CC (match_operand:DF 0 "register_operand" "")
4982 (match_operand:DF 1 "register_operand" "")))]
4983 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
4986 if (operands[0]) /* avoid unused code message */
4988 branch_cmp[0] = operands[0];
4989 branch_cmp[1] = operands[1];
4990 branch_type = CMP_DF;
4995 (define_expand "cmpsf"
4997 (compare:CC (match_operand:SF 0 "register_operand" "")
4998 (match_operand:SF 1 "register_operand" "")))]
5002 if (operands[0]) /* avoid unused code message */
5004 branch_cmp[0] = operands[0];
5005 branch_cmp[1] = operands[1];
5006 branch_type = CMP_SF;
5013 ;; ....................
5015 ;; CONDITIONAL BRANCHES
5017 ;; ....................
5019 (define_insn "branch_fp_ne"
5021 (if_then_else (ne:CC (match_operand:CC 0 "register_operand" "z")
5023 (match_operand 1 "pc_or_label_operand" "")
5024 (match_operand 2 "pc_or_label_operand" "")))]
5028 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
5029 return (operands[1] != pc_rtx) ? \"%*bc1t%?\\t%Z0%1\" : \"%*bc1f%?\\t%Z0%2\";
5031 [(set_attr "type" "branch")
5032 (set_attr "mode" "none")
5033 (set_attr "length" "1")])
5035 (define_insn "branch_fp_eq"
5037 (if_then_else (eq:CC (match_operand:CC 0 "register_operand" "z")
5039 (match_operand 1 "pc_or_label_operand" "")
5040 (match_operand 2 "pc_or_label_operand" "")))]
5044 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
5045 return (operands[1] != pc_rtx) ? \"%*bc1f%?\\t%Z0%1\" : \"%*bc1t%?\\t%Z0%2\";
5047 [(set_attr "type" "branch")
5048 (set_attr "mode" "none")
5049 (set_attr "length" "1")])
5051 (define_insn "branch_zero"
5053 (if_then_else (match_operator:SI 0 "cmp_op"
5054 [(match_operand:SI 1 "register_operand" "d")
5056 (match_operand 2 "pc_or_label_operand" "")
5057 (match_operand 3 "pc_or_label_operand" "")))]
5061 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
5062 if (operands[2] != pc_rtx)
5064 switch (GET_CODE (operands[0]))
5066 case EQ: return \"%*beq%?\\t%z1,%.,%2\";
5067 case NE: return \"%*bne%?\\t%z1,%.,%2\";
5068 case GTU: return \"%*bne%?\\t%z1,%.,%2\";
5069 case LEU: return \"%*beq%?\\t%z1,%.,%2\";
5070 case GEU: return \"%*j\\t%2\";
5071 case LTU: return \"%*bne%?\\t%.,%.,%2\";
5074 return \"%*b%C0z%?\\t%z1,%2\";
5077 { /* inverted jump */
5078 switch (GET_CODE (operands[0]))
5080 case EQ: return \"%*bne%?\\t%z1,%.,%3\";
5081 case NE: return \"%*beq%?\\t%z1,%.,%3\";
5082 case GTU: return \"%*beq%?\\t%z1,%.,%3\";
5083 case LEU: return \"%*bne%?\\t%z1,%.,%3\";
5084 case GEU: return \"%*beq%?\\t%.,%.,%3\";
5085 case LTU: return \"%*j\\t%3\";
5088 return \"%*b%N0z%?\\t%z1,%3\";
5091 [(set_attr "type" "branch")
5092 (set_attr "mode" "none")
5093 (set_attr "length" "1")])
5096 (define_insn "branch_zero_di"
5098 (if_then_else (match_operator:DI 0 "cmp_op"
5099 [(match_operand:DI 1 "se_register_operand" "d")
5101 (match_operand 2 "pc_or_label_operand" "")
5102 (match_operand 3 "pc_or_label_operand" "")))]
5106 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
5107 if (operands[2] != pc_rtx)
5109 switch (GET_CODE (operands[0]))
5111 case EQ: return \"%*beq%?\\t%z1,%.,%2\";
5112 case NE: return \"%*bne%?\\t%z1,%.,%2\";
5113 case GTU: return \"%*bne%?\\t%z1,%.,%2\";
5114 case LEU: return \"%*beq%?\\t%z1,%.,%2\";
5115 case GEU: return \"%*j\\t%2\";
5116 case LTU: return \"%*bne%?\\t%.,%.,%2\";
5119 return \"%*b%C0z%?\\t%z1,%2\";
5122 { /* inverted jump */
5123 switch (GET_CODE (operands[0]))
5125 case EQ: return \"%*bne%?\\t%z1,%.,%3\";
5126 case NE: return \"%*beq%?\\t%z1,%.,%3\";
5127 case GTU: return \"%*beq%?\\t%z1,%.,%3\";
5128 case LEU: return \"%*bne%?\\t%z1,%.,%3\";
5129 case GEU: return \"%*beq%?\\t%.,%.,%3\";
5130 case LTU: return \"%*j\\t%3\";
5133 return \"%*b%N0z%?\\t%z1,%3\";
5136 [(set_attr "type" "branch")
5137 (set_attr "mode" "none")
5138 (set_attr "length" "1")])
5141 (define_insn "branch_equality"
5143 (if_then_else (match_operator:SI 0 "equality_op"
5144 [(match_operand:SI 1 "register_operand" "d")
5145 (match_operand:SI 2 "register_operand" "d")])
5146 (match_operand 3 "pc_or_label_operand" "")
5147 (match_operand 4 "pc_or_label_operand" "")))]
5151 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
5152 return (operands[3] != pc_rtx)
5153 ? \"%*b%C0%?\\t%z1,%z2,%3\"
5154 : \"%*b%N0%?\\t%z1,%z2,%4\";
5156 [(set_attr "type" "branch")
5157 (set_attr "mode" "none")
5158 (set_attr "length" "1")])
5161 (define_insn "branch_equality_di"
5163 (if_then_else (match_operator:DI 0 "equality_op"
5164 [(match_operand:DI 1 "se_register_operand" "d")
5165 (match_operand:DI 2 "se_register_operand" "d")])
5166 (match_operand 3 "pc_or_label_operand" "")
5167 (match_operand 4 "pc_or_label_operand" "")))]
5171 mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
5172 return (operands[3] != pc_rtx)
5173 ? \"%*b%C0%?\\t%z1,%z2,%3\"
5174 : \"%*b%N0%?\\t%z1,%z2,%4\";
5176 [(set_attr "type" "branch")
5177 (set_attr "mode" "none")
5178 (set_attr "length" "1")])
5181 (define_expand "beq"
5183 (if_then_else (eq:CC (cc0)
5185 (label_ref (match_operand 0 "" ""))
5190 if (operands[0]) /* avoid unused code warning */
5192 gen_conditional_branch (operands, EQ);
5197 (define_expand "bne"
5199 (if_then_else (ne:CC (cc0)
5201 (label_ref (match_operand 0 "" ""))
5206 if (operands[0]) /* avoid unused code warning */
5208 gen_conditional_branch (operands, NE);
5213 (define_expand "bgt"
5215 (if_then_else (gt:CC (cc0)
5217 (label_ref (match_operand 0 "" ""))
5222 if (operands[0]) /* avoid unused code warning */
5224 gen_conditional_branch (operands, GT);
5229 (define_expand "bge"
5231 (if_then_else (ge:CC (cc0)
5233 (label_ref (match_operand 0 "" ""))
5238 if (operands[0]) /* avoid unused code warning */
5240 gen_conditional_branch (operands, GE);
5245 (define_expand "blt"
5247 (if_then_else (lt:CC (cc0)
5249 (label_ref (match_operand 0 "" ""))
5254 if (operands[0]) /* avoid unused code warning */
5256 gen_conditional_branch (operands, LT);
5261 (define_expand "ble"
5263 (if_then_else (le:CC (cc0)
5265 (label_ref (match_operand 0 "" ""))
5270 if (operands[0]) /* avoid unused code warning */
5272 gen_conditional_branch (operands, LE);
5277 (define_expand "bgtu"
5279 (if_then_else (gtu:CC (cc0)
5281 (label_ref (match_operand 0 "" ""))
5286 if (operands[0]) /* avoid unused code warning */
5288 gen_conditional_branch (operands, GTU);
5293 (define_expand "bgeu"
5295 (if_then_else (geu:CC (cc0)
5297 (label_ref (match_operand 0 "" ""))
5302 if (operands[0]) /* avoid unused code warning */
5304 gen_conditional_branch (operands, GEU);
5310 (define_expand "bltu"
5312 (if_then_else (ltu:CC (cc0)
5314 (label_ref (match_operand 0 "" ""))
5319 if (operands[0]) /* avoid unused code warning */
5321 gen_conditional_branch (operands, LTU);
5326 (define_expand "bleu"
5328 (if_then_else (leu:CC (cc0)
5330 (label_ref (match_operand 0 "" ""))
5335 if (operands[0]) /* avoid unused code warning */
5337 gen_conditional_branch (operands, LEU);
5344 ;; ....................
5346 ;; SETTING A REGISTER FROM A COMPARISON
5348 ;; ....................
5350 (define_expand "seq"
5351 [(set (match_operand:SI 0 "register_operand" "=d")
5352 (eq:SI (match_dup 1)
5357 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5360 /* set up operands from compare. */
5361 operands[1] = branch_cmp[0];
5362 operands[2] = branch_cmp[1];
5364 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5366 gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
5370 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5371 operands[2] = force_reg (SImode, operands[2]);
5373 /* fall through and generate default code */
5377 (define_insn "seq_si_zero"
5378 [(set (match_operand:SI 0 "register_operand" "=d")
5379 (eq:SI (match_operand:SI 1 "register_operand" "d")
5383 [(set_attr "type" "arith")
5384 (set_attr "mode" "SI")
5385 (set_attr "length" "1")])
5387 (define_insn "seq_di_zero"
5388 [(set (match_operand:DI 0 "register_operand" "=d")
5389 (eq:DI (match_operand:DI 1 "se_register_operand" "d")
5393 [(set_attr "type" "arith")
5394 (set_attr "mode" "DI")
5395 (set_attr "length" "1")])
5397 (define_insn "seq_si"
5398 [(set (match_operand:SI 0 "register_operand" "=d,d")
5399 (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
5400 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
5401 "TARGET_DEBUG_C_MODE"
5403 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
5404 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
5405 [(set_attr "type" "arith")
5406 (set_attr "mode" "SI")
5407 (set_attr "length" "2")])
5410 [(set (match_operand:SI 0 "register_operand" "")
5411 (eq:SI (match_operand:SI 1 "register_operand" "")
5412 (match_operand:SI 2 "uns_arith_operand" "")))]
5413 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
5414 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
5416 (xor:SI (match_dup 1)
5419 (ltu:SI (match_dup 0)
5423 (define_insn "seq_di"
5424 [(set (match_operand:DI 0 "register_operand" "=d,d")
5425 (eq:DI (match_operand:DI 1 "se_register_operand" "%d,d")
5426 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
5427 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
5429 xor\\t%0,%1,%2\;sltu\\t%0,%0,1
5430 xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
5431 [(set_attr "type" "arith")
5432 (set_attr "mode" "DI")
5433 (set_attr "length" "2")])
5436 [(set (match_operand:DI 0 "register_operand" "")
5437 (eq:DI (match_operand:DI 1 "se_register_operand" "")
5438 (match_operand:DI 2 "se_uns_arith_operand" "")))]
5439 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
5440 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
5442 (xor:DI (match_dup 1)
5445 (ltu:DI (match_dup 0)
5449 (define_expand "sne"
5450 [(set (match_operand:SI 0 "register_operand" "=d")
5451 (ne:SI (match_dup 1)
5456 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5459 /* set up operands from compare. */
5460 operands[1] = branch_cmp[0];
5461 operands[2] = branch_cmp[1];
5463 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5465 gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
5469 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
5470 operands[2] = force_reg (SImode, operands[2]);
5472 /* fall through and generate default code */
5475 (define_insn "sne_si_zero"
5476 [(set (match_operand:SI 0 "register_operand" "=d")
5477 (ne:SI (match_operand:SI 1 "register_operand" "d")
5481 [(set_attr "type" "arith")
5482 (set_attr "mode" "SI")
5483 (set_attr "length" "1")])
5485 (define_insn "sne_di_zero"
5486 [(set (match_operand:DI 0 "register_operand" "=d")
5487 (ne:DI (match_operand:DI 1 "se_register_operand" "d")
5491 [(set_attr "type" "arith")
5492 (set_attr "mode" "DI")
5493 (set_attr "length" "1")])
5495 (define_insn "sne_si"
5496 [(set (match_operand:SI 0 "register_operand" "=d,d")
5497 (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
5498 (match_operand:SI 2 "uns_arith_operand" "d,K")))]
5499 "TARGET_DEBUG_C_MODE"
5501 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
5502 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
5503 [(set_attr "type" "arith")
5504 (set_attr "mode" "SI")
5505 (set_attr "length" "2")])
5508 [(set (match_operand:SI 0 "register_operand" "")
5509 (ne:SI (match_operand:SI 1 "register_operand" "")
5510 (match_operand:SI 2 "uns_arith_operand" "")))]
5511 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
5512 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
5514 (xor:SI (match_dup 1)
5517 (gtu:SI (match_dup 0)
5521 (define_insn "sne_di"
5522 [(set (match_operand:DI 0 "register_operand" "=d,d")
5523 (ne:DI (match_operand:DI 1 "se_register_operand" "%d,d")
5524 (match_operand:DI 2 "se_uns_arith_operand" "d,K")))]
5525 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
5527 xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
5528 xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
5529 [(set_attr "type" "arith")
5530 (set_attr "mode" "DI")
5531 (set_attr "length" "2")])
5534 [(set (match_operand:DI 0 "register_operand" "")
5535 (ne:DI (match_operand:DI 1 "se_register_operand" "")
5536 (match_operand:DI 2 "se_uns_arith_operand" "")))]
5537 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
5538 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
5540 (xor:DI (match_dup 1)
5543 (gtu:DI (match_dup 0)
5547 (define_expand "sgt"
5548 [(set (match_operand:SI 0 "register_operand" "=d")
5549 (gt:SI (match_dup 1)
5554 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5557 /* set up operands from compare. */
5558 operands[1] = branch_cmp[0];
5559 operands[2] = branch_cmp[1];
5561 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5563 gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
5567 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
5568 operands[2] = force_reg (SImode, operands[2]);
5570 /* fall through and generate default code */
5573 (define_insn "sgt_si"
5574 [(set (match_operand:SI 0 "register_operand" "=d")
5575 (gt:SI (match_operand:SI 1 "register_operand" "d")
5576 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
5579 [(set_attr "type" "arith")
5580 (set_attr "mode" "SI")
5581 (set_attr "length" "1")])
5583 (define_insn "sgt_di"
5584 [(set (match_operand:DI 0 "register_operand" "=d")
5585 (gt:DI (match_operand:DI 1 "se_register_operand" "d")
5586 (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
5589 [(set_attr "type" "arith")
5590 (set_attr "mode" "DI")
5591 (set_attr "length" "1")])
5593 (define_expand "sge"
5594 [(set (match_operand:SI 0 "register_operand" "=d")
5595 (ge:SI (match_dup 1)
5600 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5603 /* set up operands from compare. */
5604 operands[1] = branch_cmp[0];
5605 operands[2] = branch_cmp[1];
5607 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5609 gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
5613 /* fall through and generate default code */
5616 (define_insn "sge_si"
5617 [(set (match_operand:SI 0 "register_operand" "=d")
5618 (ge:SI (match_operand:SI 1 "register_operand" "d")
5619 (match_operand:SI 2 "arith_operand" "dI")))]
5620 "TARGET_DEBUG_C_MODE"
5621 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
5622 [(set_attr "type" "arith")
5623 (set_attr "mode" "SI")
5624 (set_attr "length" "2")])
5627 [(set (match_operand:SI 0 "register_operand" "")
5628 (ge:SI (match_operand:SI 1 "register_operand" "")
5629 (match_operand:SI 2 "arith_operand" "")))]
5630 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5632 (lt:SI (match_dup 1)
5635 (xor:SI (match_dup 0)
5639 (define_insn "sge_di"
5640 [(set (match_operand:DI 0 "register_operand" "=d")
5641 (ge:DI (match_operand:DI 1 "se_register_operand" "d")
5642 (match_operand:DI 2 "se_arith_operand" "dI")))]
5643 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
5644 "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
5645 [(set_attr "type" "arith")
5646 (set_attr "mode" "DI")
5647 (set_attr "length" "2")])
5650 [(set (match_operand:DI 0 "register_operand" "")
5651 (ge:DI (match_operand:DI 1 "se_register_operand" "")
5652 (match_operand:DI 2 "se_arith_operand" "")))]
5653 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5655 (lt:DI (match_dup 1)
5658 (xor:DI (match_dup 0)
5662 (define_expand "slt"
5663 [(set (match_operand:SI 0 "register_operand" "=d")
5664 (lt:SI (match_dup 1)
5669 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5672 /* set up operands from compare. */
5673 operands[1] = branch_cmp[0];
5674 operands[2] = branch_cmp[1];
5676 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5678 gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
5682 /* fall through and generate default code */
5685 (define_insn "slt_si"
5686 [(set (match_operand:SI 0 "register_operand" "=d")
5687 (lt:SI (match_operand:SI 1 "register_operand" "d")
5688 (match_operand:SI 2 "arith_operand" "dI")))]
5691 [(set_attr "type" "arith")
5692 (set_attr "mode" "SI")
5693 (set_attr "length" "1")])
5695 (define_insn "slt_di"
5696 [(set (match_operand:DI 0 "register_operand" "=d")
5697 (lt:DI (match_operand:DI 1 "se_register_operand" "d")
5698 (match_operand:DI 2 "se_arith_operand" "dI")))]
5701 [(set_attr "type" "arith")
5702 (set_attr "mode" "DI")
5703 (set_attr "length" "1")])
5705 (define_expand "sle"
5706 [(set (match_operand:SI 0 "register_operand" "=d")
5707 (le:SI (match_dup 1)
5712 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5715 /* set up operands from compare. */
5716 operands[1] = branch_cmp[0];
5717 operands[2] = branch_cmp[1];
5719 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5721 gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
5725 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
5726 operands[2] = force_reg (SImode, operands[2]);
5728 /* fall through and generate default code */
5731 (define_insn "sle_si_const"
5732 [(set (match_operand:SI 0 "register_operand" "=d")
5733 (le:SI (match_operand:SI 1 "register_operand" "d")
5734 (match_operand:SI 2 "small_int" "I")))]
5735 "INTVAL (operands[2]) < 32767"
5738 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
5739 return \"slt\\t%0,%1,%2\";
5741 [(set_attr "type" "arith")
5742 (set_attr "mode" "SI")
5743 (set_attr "length" "1")])
5745 (define_insn "sle_di_const"
5746 [(set (match_operand:DI 0 "register_operand" "=d")
5747 (le:DI (match_operand:DI 1 "se_register_operand" "d")
5748 (match_operand:DI 2 "small_int" "I")))]
5749 "TARGET_64BIT && INTVAL (operands[2]) < 32767"
5752 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
5753 return \"slt\\t%0,%1,%2\";
5755 [(set_attr "type" "arith")
5756 (set_attr "mode" "DI")
5757 (set_attr "length" "1")])
5759 (define_insn "sle_si_reg"
5760 [(set (match_operand:SI 0 "register_operand" "=d")
5761 (le:SI (match_operand:SI 1 "register_operand" "d")
5762 (match_operand:SI 2 "register_operand" "d")))]
5763 "TARGET_DEBUG_C_MODE"
5764 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
5765 [(set_attr "type" "arith")
5766 (set_attr "mode" "SI")
5767 (set_attr "length" "2")])
5770 [(set (match_operand:SI 0 "register_operand" "")
5771 (le:SI (match_operand:SI 1 "register_operand" "")
5772 (match_operand:SI 2 "register_operand" "")))]
5773 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5775 (lt:SI (match_dup 2)
5778 (xor:SI (match_dup 0)
5782 (define_insn "sle_di_reg"
5783 [(set (match_operand:DI 0 "register_operand" "=d")
5784 (le:DI (match_operand:DI 1 "se_register_operand" "d")
5785 (match_operand:DI 2 "se_register_operand" "d")))]
5786 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
5787 "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
5788 [(set_attr "type" "arith")
5789 (set_attr "mode" "DI")
5790 (set_attr "length" "2")])
5793 [(set (match_operand:DI 0 "register_operand" "")
5794 (le:DI (match_operand:DI 1 "se_register_operand" "")
5795 (match_operand:DI 2 "se_register_operand" "")))]
5796 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5798 (lt:DI (match_dup 2)
5801 (xor:DI (match_dup 0)
5805 (define_expand "sgtu"
5806 [(set (match_operand:SI 0 "register_operand" "=d")
5807 (gtu:SI (match_dup 1)
5812 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5815 /* set up operands from compare. */
5816 operands[1] = branch_cmp[0];
5817 operands[2] = branch_cmp[1];
5819 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5821 gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
5825 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
5826 operands[2] = force_reg (SImode, operands[2]);
5828 /* fall through and generate default code */
5831 (define_insn "sgtu_si"
5832 [(set (match_operand:SI 0 "register_operand" "=d")
5833 (gtu:SI (match_operand:SI 1 "register_operand" "d")
5834 (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
5837 [(set_attr "type" "arith")
5838 (set_attr "mode" "SI")
5839 (set_attr "length" "1")])
5841 (define_insn "sgtu_di"
5842 [(set (match_operand:DI 0 "register_operand" "=d")
5843 (gtu:DI (match_operand:DI 1 "se_register_operand" "d")
5844 (match_operand:DI 2 "se_reg_or_0_operand" "dJ")))]
5847 [(set_attr "type" "arith")
5848 (set_attr "mode" "DI")
5849 (set_attr "length" "1")])
5851 (define_expand "sgeu"
5852 [(set (match_operand:SI 0 "register_operand" "=d")
5853 (geu:SI (match_dup 1)
5858 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5861 /* set up operands from compare. */
5862 operands[1] = branch_cmp[0];
5863 operands[2] = branch_cmp[1];
5865 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5867 gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
5871 /* fall through and generate default code */
5874 (define_insn "sgeu_si"
5875 [(set (match_operand:SI 0 "register_operand" "=d")
5876 (geu:SI (match_operand:SI 1 "register_operand" "d")
5877 (match_operand:SI 2 "arith_operand" "dI")))]
5878 "TARGET_DEBUG_C_MODE"
5879 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
5880 [(set_attr "type" "arith")
5881 (set_attr "mode" "SI")
5882 (set_attr "length" "2")])
5885 [(set (match_operand:SI 0 "register_operand" "")
5886 (geu:SI (match_operand:SI 1 "register_operand" "")
5887 (match_operand:SI 2 "arith_operand" "")))]
5888 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5890 (ltu:SI (match_dup 1)
5893 (xor:SI (match_dup 0)
5897 (define_insn "sgeu_di"
5898 [(set (match_operand:DI 0 "register_operand" "=d")
5899 (geu:DI (match_operand:DI 1 "se_register_operand" "d")
5900 (match_operand:DI 2 "se_arith_operand" "dI")))]
5901 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
5902 "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
5903 [(set_attr "type" "arith")
5904 (set_attr "mode" "DI")
5905 (set_attr "length" "2")])
5908 [(set (match_operand:DI 0 "register_operand" "")
5909 (geu:DI (match_operand:DI 1 "se_register_operand" "")
5910 (match_operand:DI 2 "se_arith_operand" "")))]
5911 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5913 (ltu:DI (match_dup 1)
5916 (xor:DI (match_dup 0)
5920 (define_expand "sltu"
5921 [(set (match_operand:SI 0 "register_operand" "=d")
5922 (ltu:SI (match_dup 1)
5927 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5930 /* set up operands from compare. */
5931 operands[1] = branch_cmp[0];
5932 operands[2] = branch_cmp[1];
5934 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5936 gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
5940 /* fall through and generate default code */
5943 (define_insn "sltu_si"
5944 [(set (match_operand:SI 0 "register_operand" "=d")
5945 (ltu:SI (match_operand:SI 1 "register_operand" "d")
5946 (match_operand:SI 2 "arith_operand" "dI")))]
5949 [(set_attr "type" "arith")
5950 (set_attr "mode" "SI")
5951 (set_attr "length" "1")])
5953 (define_insn "sltu_di"
5954 [(set (match_operand:DI 0 "register_operand" "=d")
5955 (ltu:DI (match_operand:DI 1 "se_register_operand" "d")
5956 (match_operand:DI 2 "se_arith_operand" "dI")))]
5959 [(set_attr "type" "arith")
5960 (set_attr "mode" "DI")
5961 (set_attr "length" "1")])
5963 (define_expand "sleu"
5964 [(set (match_operand:SI 0 "register_operand" "=d")
5965 (leu:SI (match_dup 1)
5970 if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
5973 /* set up operands from compare. */
5974 operands[1] = branch_cmp[0];
5975 operands[2] = branch_cmp[1];
5977 if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
5979 gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
5983 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
5984 operands[2] = force_reg (SImode, operands[2]);
5986 /* fall through and generate default code */
5989 (define_insn "sleu_si_const"
5990 [(set (match_operand:SI 0 "register_operand" "=d")
5991 (leu:SI (match_operand:SI 1 "register_operand" "d")
5992 (match_operand:SI 2 "small_int" "I")))]
5993 "INTVAL (operands[2]) < 32767"
5996 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
5997 return \"sltu\\t%0,%1,%2\";
5999 [(set_attr "type" "arith")
6000 (set_attr "mode" "SI")
6001 (set_attr "length" "1")])
6003 (define_insn "sleu_di_const"
6004 [(set (match_operand:DI 0 "register_operand" "=d")
6005 (leu:DI (match_operand:DI 1 "se_register_operand" "d")
6006 (match_operand:DI 2 "small_int" "I")))]
6007 "TARGET_64BIT && INTVAL (operands[2]) < 32767"
6010 operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
6011 return \"sltu\\t%0,%1,%2\";
6013 [(set_attr "type" "arith")
6014 (set_attr "mode" "DI")
6015 (set_attr "length" "1")])
6017 (define_insn "sleu_si_reg"
6018 [(set (match_operand:SI 0 "register_operand" "=d")
6019 (leu:SI (match_operand:SI 1 "register_operand" "d")
6020 (match_operand:SI 2 "register_operand" "d")))]
6021 "TARGET_DEBUG_C_MODE"
6022 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
6023 [(set_attr "type" "arith")
6024 (set_attr "mode" "SI")
6025 (set_attr "length" "2")])
6028 [(set (match_operand:SI 0 "register_operand" "")
6029 (leu:SI (match_operand:SI 1 "register_operand" "")
6030 (match_operand:SI 2 "register_operand" "")))]
6031 "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
6033 (ltu:SI (match_dup 2)
6036 (xor:SI (match_dup 0)
6040 (define_insn "sleu_di_reg"
6041 [(set (match_operand:DI 0 "register_operand" "=d")
6042 (leu:DI (match_operand:DI 1 "se_register_operand" "d")
6043 (match_operand:DI 2 "se_register_operand" "d")))]
6044 "TARGET_64BIT && TARGET_DEBUG_C_MODE"
6045 "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
6046 [(set_attr "type" "arith")
6047 (set_attr "mode" "DI")
6048 (set_attr "length" "2")])
6051 [(set (match_operand:DI 0 "register_operand" "")
6052 (leu:DI (match_operand:DI 1 "se_register_operand" "")
6053 (match_operand:DI 2 "se_register_operand" "")))]
6054 "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
6056 (ltu:DI (match_dup 2)
6059 (xor:DI (match_dup 0)
6065 ;; ....................
6067 ;; FLOATING POINT COMPARISONS
6069 ;; ....................
6071 (define_insn "seq_df"
6072 [(set (match_operand:CC 0 "register_operand" "=z")
6073 (eq:CC (match_operand:DF 1 "register_operand" "f")
6074 (match_operand:DF 2 "register_operand" "f")))]
6075 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6078 return mips_fill_delay_slot (\"c.eq.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
6080 [(set_attr "type" "fcmp")
6081 (set_attr "mode" "FPSW")
6082 (set_attr "length" "1")])
6084 (define_insn "slt_df"
6085 [(set (match_operand:CC 0 "register_operand" "=z")
6086 (lt:CC (match_operand:DF 1 "register_operand" "f")
6087 (match_operand:DF 2 "register_operand" "f")))]
6088 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6091 return mips_fill_delay_slot (\"c.lt.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
6093 [(set_attr "type" "fcmp")
6094 (set_attr "mode" "FPSW")
6095 (set_attr "length" "1")])
6097 (define_insn "sle_df"
6098 [(set (match_operand:CC 0 "register_operand" "=z")
6099 (le:CC (match_operand:DF 1 "register_operand" "f")
6100 (match_operand:DF 2 "register_operand" "f")))]
6101 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6104 return mips_fill_delay_slot (\"c.le.d\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
6106 [(set_attr "type" "fcmp")
6107 (set_attr "mode" "FPSW")
6108 (set_attr "length" "1")])
6110 (define_insn "sgt_df"
6111 [(set (match_operand:CC 0 "register_operand" "=z")
6112 (gt:CC (match_operand:DF 1 "register_operand" "f")
6113 (match_operand:DF 2 "register_operand" "f")))]
6114 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6117 return mips_fill_delay_slot (\"c.lt.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
6119 [(set_attr "type" "fcmp")
6120 (set_attr "mode" "FPSW")
6121 (set_attr "length" "1")])
6123 (define_insn "sge_df"
6124 [(set (match_operand:CC 0 "register_operand" "=z")
6125 (ge:CC (match_operand:DF 1 "register_operand" "f")
6126 (match_operand:DF 2 "register_operand" "f")))]
6127 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
6130 return mips_fill_delay_slot (\"c.le.d\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
6132 [(set_attr "type" "fcmp")
6133 (set_attr "mode" "FPSW")
6134 (set_attr "length" "1")])
6136 (define_insn "seq_sf"
6137 [(set (match_operand:CC 0 "register_operand" "=z")
6138 (eq:CC (match_operand:SF 1 "register_operand" "f")
6139 (match_operand:SF 2 "register_operand" "f")))]
6143 return mips_fill_delay_slot (\"c.eq.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
6145 [(set_attr "type" "fcmp")
6146 (set_attr "mode" "FPSW")
6147 (set_attr "length" "1")])
6149 (define_insn "slt_sf"
6150 [(set (match_operand:CC 0 "register_operand" "=z")
6151 (lt:CC (match_operand:SF 1 "register_operand" "f")
6152 (match_operand:SF 2 "register_operand" "f")))]
6156 return mips_fill_delay_slot (\"c.lt.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
6158 [(set_attr "type" "fcmp")
6159 (set_attr "mode" "FPSW")
6160 (set_attr "length" "1")])
6162 (define_insn "sle_sf"
6163 [(set (match_operand:CC 0 "register_operand" "=z")
6164 (le:CC (match_operand:SF 1 "register_operand" "f")
6165 (match_operand:SF 2 "register_operand" "f")))]
6169 return mips_fill_delay_slot (\"c.le.s\\t%Z0%1,%2\", DELAY_FCMP, operands, insn);
6171 [(set_attr "type" "fcmp")
6172 (set_attr "mode" "FPSW")
6173 (set_attr "length" "1")])
6175 (define_insn "sgt_sf"
6176 [(set (match_operand:CC 0 "register_operand" "=z")
6177 (gt:CC (match_operand:SF 1 "register_operand" "f")
6178 (match_operand:SF 2 "register_operand" "f")))]
6182 return mips_fill_delay_slot (\"c.lt.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
6184 [(set_attr "type" "fcmp")
6185 (set_attr "mode" "FPSW")
6186 (set_attr "length" "1")])
6188 (define_insn "sge_sf"
6189 [(set (match_operand:CC 0 "register_operand" "=z")
6190 (ge:CC (match_operand:SF 1 "register_operand" "f")
6191 (match_operand:SF 2 "register_operand" "f")))]
6195 return mips_fill_delay_slot (\"c.le.s\\t%Z0%2,%1\", DELAY_FCMP, operands, insn);
6197 [(set_attr "type" "fcmp")
6198 (set_attr "mode" "FPSW")
6199 (set_attr "length" "1")])
6203 ;; ....................
6205 ;; UNCONDITIONAL BRANCHES
6207 ;; ....................
6209 ;; Unconditional branches.
6213 (label_ref (match_operand 0 "" "")))]
6217 if (GET_CODE (operands[0]) == REG)
6218 return \"%*j\\t%0\";
6219 /* ??? I don't know why this is necessary. This works around an
6220 assembler problem that appears when a label is defined, then referenced
6221 in a switch table, then used in a `j' instruction. */
6222 else if (mips_abi != ABI_32)
6223 return \"%*b\\t%l0\";
6225 return \"%*j\\t%l0\";
6227 [(set_attr "type" "jump")
6228 (set_attr "mode" "none")
6229 (set_attr "length" "1")])
6231 (define_expand "indirect_jump"
6232 [(set (pc) (match_operand 0 "register_operand" "d"))]
6238 if (operands[0]) /* eliminate unused code warnings */
6241 if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
6242 operands[0] = copy_to_mode_reg (Pmode, dest);
6245 emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
6247 emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
6253 (define_insn "indirect_jump_internal1"
6254 [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
6257 [(set_attr "type" "jump")
6258 (set_attr "mode" "none")
6259 (set_attr "length" "1")])
6261 (define_insn "indirect_jump_internal2"
6262 [(set (pc) (match_operand:DI 0 "se_register_operand" "d"))]
6265 [(set_attr "type" "jump")
6266 (set_attr "mode" "none")
6267 (set_attr "length" "1")])
6269 (define_expand "tablejump"
6271 (match_operand 0 "register_operand" "d"))
6272 (use (label_ref (match_operand 1 "" "")))]
6278 if (operands[0]) /* eliminate unused code warnings */
6280 if (GET_MODE (operands[0]) != Pmode)
6286 emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
6288 emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
6293 emit_jump_insn (gen_tablejump_internal3 (operands[0], operands[1]));
6295 emit_jump_insn (gen_tablejump_internal4 (operands[0], operands[1]));
6302 (define_insn "tablejump_internal1"
6304 (match_operand:SI 0 "register_operand" "d"))
6305 (use (label_ref (match_operand 1 "" "")))]
6308 [(set_attr "type" "jump")
6309 (set_attr "mode" "none")
6310 (set_attr "length" "1")])
6312 (define_insn "tablejump_internal2"
6314 (match_operand:DI 0 "se_register_operand" "d"))
6315 (use (label_ref (match_operand 1 "" "")))]
6318 [(set_attr "type" "jump")
6319 (set_attr "mode" "none")
6320 (set_attr "length" "1")])
6322 (define_expand "tablejump_internal3"
6324 (plus:SI (match_operand:SI 0 "register_operand" "d")
6325 (label_ref:SI (match_operand:SI 1 "" ""))))]
6329 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
6330 ;;; it is not valid.
6332 ;;; ??? The length depends on the ABI. It is two for o32, and one for n32.
6333 ;;; We just use the conservative number here.
6337 (plus:SI (match_operand:SI 0 "register_operand" "d")
6338 (label_ref:SI (match_operand:SI 1 "" ""))))]
6339 "!TARGET_LONG64 && next_active_insn (insn) != 0
6340 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
6341 && PREV_INSN (next_active_insn (insn)) == operands[1]"
6344 /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic. */
6345 if (mips_abi == ABI_32)
6346 output_asm_insn (\".cpadd\\t%0\", operands);
6347 return \"%*j\\t%0\";
6349 [(set_attr "type" "jump")
6350 (set_attr "mode" "none")
6351 (set_attr "length" "2")])
6353 (define_expand "tablejump_internal4"
6355 (plus:DI (match_operand:DI 0 "se_register_operand" "d")
6356 (label_ref:DI (match_operand:SI 1 "" ""))))]
6360 ;;; Make sure that this only matches the insn before ADDR_DIFF_VEC. Otherwise
6361 ;;; it is not valid.
6365 (plus:DI (match_operand:DI 0 "se_register_operand" "d")
6366 (label_ref:DI (match_operand:SI 1 "" ""))))]
6367 "TARGET_LONG64 && next_active_insn (insn) != 0
6368 && GET_CODE (PATTERN (next_active_insn (insn))) == ADDR_DIFF_VEC
6369 && PREV_INSN (next_active_insn (insn)) == operands[1]"
6371 [(set_attr "type" "jump")
6372 (set_attr "mode" "none")
6373 (set_attr "length" "1")])
6375 ;; Implement a switch statement when generating embedded PIC code.
6376 ;; Switches are implemented by `tablejump' when not using -membedded-pic.
6378 (define_expand "casesi"
6380 (minus:SI (match_operand:SI 0 "register_operand" "d")
6381 (match_operand:SI 1 "arith_operand" "dI")))
6383 (compare:CC (match_dup 5)
6384 (match_operand:SI 2 "arith_operand" "")))
6386 (if_then_else (gtu (cc0)
6388 (label_ref (match_operand 4 "" ""))
6392 (mem:SI (plus:SI (mult:SI (match_dup 5)
6394 (label_ref (match_operand 3 "" "")))))
6395 (clobber (match_scratch:SI 6 ""))
6396 (clobber (reg:SI 31))])]
6397 "TARGET_EMBEDDED_PIC"
6400 /* We need slightly different code for eight byte table entries. */
6406 rtx reg = gen_reg_rtx (SImode);
6408 /* If the index is too large, go to the default label. */
6409 emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
6410 emit_insn (gen_cmpsi (reg, operands[2]));
6411 emit_insn (gen_bgtu (operands[4]));
6413 /* Do the PIC jump. */
6414 emit_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode)));
6420 ;; An embedded PIC switch statement looks like this:
6422 ;; sll $reg,$index,2
6424 ;; addu $reg,$reg,$31
6425 ;; lw $reg,$L1-$LS1($reg)
6426 ;; addu $reg,$reg,$31
6433 (define_insn "casesi_internal"
6435 (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
6437 (label_ref (match_operand 1 "" "")))))
6438 (clobber (match_operand:SI 2 "register_operand" "d"))
6439 (clobber (reg:SI 31))]
6440 "TARGET_EMBEDDED_PIC"
6443 output_asm_insn (\"%(bal\\t%S1\;sll\\t%0,2\\n%S1:\", operands);
6444 output_asm_insn (\"addu\\t%0,%0,$31%)\", operands);
6445 output_asm_insn (\"lw\\t%0,%1-%S1(%0)\;addu\\t%0,%0,$31\", operands);
6448 [(set_attr "type" "jump")
6449 (set_attr "mode" "none")
6450 (set_attr "length" "6")])
6452 ;; ??? This is a hack to work around a problem with expand_builtin_setjmp.
6453 ;; It restores the frame pointer, and then does a call to restore the global
6454 ;; pointer (gp) register. The call insn implicitly (via the assembler) reloads
6455 ;; gp from the stack. However, call insns do not depend on $fp, so it is
6456 ;; possible for the instruction scheduler to move the fp restore after the
6457 ;; call, which then causes gp to be corrupted. We fix this by emitting a
6458 ;; scheduler barrier. A better fix is to put code here that restores the
6459 ;; $gp, and then the call is unnecessary. This is only a problem when PIC
6460 ;; (TARGET_ABICALLS), and only when the gp register is caller-saved
6461 ;; (irix5/o32, but not irix6/n32/n64).
6463 (define_expand "nonlocal_goto_receiver"
6468 emit_insn (gen_blockage ());
6472 ;; ....................
6474 ;; Function prologue/epilogue
6476 ;; ....................
6479 (define_expand "prologue"
6484 if (mips_isa >= 0) /* avoid unused code warnings */
6486 mips_expand_prologue ();
6491 ;; Block any insns from being moved before this point, since the
6492 ;; profiling call to mcount can use various registers that aren't
6493 ;; saved or used to pass arguments.
6495 (define_insn "blockage"
6496 [(unspec_volatile [(const_int 0)] 0)]
6499 [(set_attr "type" "unknown")
6500 (set_attr "mode" "none")
6501 (set_attr "length" "0")])
6503 (define_expand "epilogue"
6508 if (mips_isa >= 0) /* avoid unused code warnings */
6510 mips_expand_epilogue ();
6515 ;; Trivial return. Make it look like a normal return insn as that
6516 ;; allows jump optimizations to work better .
6517 (define_insn "return"
6519 "mips_can_use_return_insn ()"
6521 [(set_attr "type" "jump")
6522 (set_attr "mode" "none")
6523 (set_attr "length" "1")])
6526 (define_insn "return_internal"
6531 [(set_attr "type" "jump")
6532 (set_attr "mode" "none")
6533 (set_attr "length" "1")])
6535 ;; When generating embedded PIC code we need to get the address of the
6536 ;; current function. This specialized instruction does just that.
6538 (define_insn "get_fnaddr"
6539 [(set (match_operand 0 "register_operand" "=d")
6540 (unspec [(match_operand 1 "" "")] 1))
6541 (clobber (reg:SI 31))]
6542 "TARGET_EMBEDDED_PIC
6543 && GET_CODE (operands[1]) == SYMBOL_REF"
6544 "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
6545 [(set_attr "type" "call")
6546 (set_attr "mode" "none")
6547 (set_attr "length" "4")])
6551 ;; ....................
6555 ;; ....................
6557 ;; calls.c now passes a third argument, make saber happy
6559 (define_expand "call"
6560 [(parallel [(call (match_operand 0 "memory_operand" "m")
6561 (match_operand 1 "" "i"))
6562 (clobber (reg:SI 31))
6563 (use (match_operand 2 "" "")) ;; next_arg_reg
6564 (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
6570 if (operands[0]) /* eliminate unused code warnings */
6572 addr = XEXP (operands[0], 0);
6573 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
6574 || ! call_insn_operand (addr, VOIDmode))
6575 XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
6577 /* In order to pass small structures by value in registers
6578 compatibly with the MIPS compiler, we need to shift the value
6579 into the high part of the register. Function_arg has encoded
6580 a PARALLEL rtx, holding a vector of adjustments to be made
6581 as the next_arg_reg variable, so we split up the insns,
6582 and emit them separately. */
6584 if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
6586 rtvec adjust = XVEC (operands[2], 0);
6587 int num = GET_NUM_ELEM (adjust);
6590 for (i = 0; i < num; i++)
6591 emit_insn (RTVEC_ELT (adjust, i));
6594 emit_call_insn (gen_call_internal0 (operands[0], operands[1],
6595 gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
6600 (define_expand "call_internal0"
6601 [(parallel [(call (match_operand 0 "" "")
6602 (match_operand 1 "" ""))
6603 (clobber (match_operand:SI 2 "" ""))])]
6607 (define_insn "call_internal1"
6608 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
6609 (match_operand 1 "" "i"))
6610 (clobber (match_operand:SI 2 "register_operand" "=d"))]
6611 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
6614 register rtx target = operands[0];
6616 if (GET_CODE (target) == SYMBOL_REF)
6617 return \"%*jal\\t%0\";
6618 else if (GET_CODE (target) == CONST_INT)
6619 return \"%[li\\t%@,%0\\n\\t%*jal\\t%2,%@%]\";
6621 return \"%*jal\\t%2,%0\";
6623 [(set_attr "type" "call")
6624 (set_attr "mode" "none")
6625 (set_attr "length" "1")])
6627 (define_insn "call_internal2"
6628 [(call (mem (match_operand 0 "call_insn_operand" "ri"))
6629 (match_operand 1 "" "i"))
6630 (clobber (match_operand:SI 2 "register_operand" "=d"))]
6631 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
6634 register rtx target = operands[0];
6636 if (GET_CODE (target) == SYMBOL_REF)
6638 if (GET_MODE (target) == SImode)
6639 return \"la\\t%^,%0\\n\\tjal\\t%2,%^\";
6641 return \"dla\\t%^,%0\\n\\tjal\\t%2,%^\";
6643 else if (GET_CODE (target) == CONST_INT)
6644 return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
6645 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
6646 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
6648 return \"jal\\t%2,%0\";
6650 [(set_attr "type" "call")
6651 (set_attr "mode" "none")
6652 (set_attr "length" "2")])
6654 (define_insn "call_internal3a"
6655 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
6656 (match_operand 1 "" "i"))
6657 (clobber (match_operand:SI 2 "register_operand" "=d"))]
6658 "!TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
6660 [(set_attr "type" "call")
6661 (set_attr "mode" "none")
6662 (set_attr "length" "1")])
6664 (define_insn "call_internal3b"
6665 [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
6666 (match_operand 1 "" "i"))
6667 (clobber (match_operand:SI 2 "register_operand" "=d"))]
6668 "TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
6670 [(set_attr "type" "call")
6671 (set_attr "mode" "none")
6672 (set_attr "length" "1")])
6674 (define_insn "call_internal4a"
6675 [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
6676 (match_operand 1 "" "i"))
6677 (clobber (match_operand:SI 2 "register_operand" "=d"))]
6678 "!TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
6681 if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
6682 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
6684 return \"jal\\t%2,%0\";
6686 [(set_attr "type" "call")
6687 (set_attr "mode" "none")
6688 (set_attr "length" "2")])
6690 (define_insn "call_internal4b"
6691 [(call (mem:DI (match_operand:DI 0 "se_register_operand" "r"))
6692 (match_operand 1 "" "i"))
6693 (clobber (match_operand:SI 2 "register_operand" "=d"))]
6694 "TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
6697 if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
6698 return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
6700 return \"jal\\t%2,%0\";
6702 [(set_attr "type" "call")
6703 (set_attr "mode" "none")
6704 (set_attr "length" "2")])
6706 ;; calls.c now passes a fourth argument, make saber happy
6708 (define_expand "call_value"
6709 [(parallel [(set (match_operand 0 "register_operand" "=df")
6710 (call (match_operand 1 "memory_operand" "m")
6711 (match_operand 2 "" "i")))
6712 (clobber (reg:SI 31))
6713 (use (match_operand 3 "" ""))])] ;; next_arg_reg
6719 if (operands[0]) /* eliminate unused code warning */
6721 addr = XEXP (operands[1], 0);
6722 if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
6723 || ! call_insn_operand (addr, VOIDmode))
6724 XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
6726 /* In order to pass small structures by value in registers
6727 compatibly with the MIPS compiler, we need to shift the value
6728 into the high part of the register. Function_arg has encoded
6729 a PARALLEL rtx, holding a vector of adjustments to be made
6730 as the next_arg_reg variable, so we split up the insns,
6731 and emit them separately. */
6733 if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
6735 rtvec adjust = XVEC (operands[3], 0);
6736 int num = GET_NUM_ELEM (adjust);
6739 for (i = 0; i < num; i++)
6740 emit_insn (RTVEC_ELT (adjust, i));
6743 /* Handle Irix6 function calls that have multiple non-contiguous
6745 if (GET_CODE (operands[0]) == PARALLEL && XVECLEN (operands[0], 0) > 1)
6747 emit_call_insn (gen_call_value_multiple_internal0
6748 (XEXP (XVECEXP (operands[0], 0, 0), 0),
6749 operands[1], operands[2],
6750 XEXP (XVECEXP (operands[0], 0, 1), 0),
6751 gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
6755 /* We have a call returning a DImode structure in an FP reg.
6756 Strip off the now unnecessary PARALLEL. */
6757 if (GET_CODE (operands[0]) == PARALLEL)
6758 operands[0] = XEXP (XVECEXP (operands[0], 0, 0), 0);
6760 emit_call_insn (gen_call_value_internal0 (operands[0], operands[1], operands[2],
6761 gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
6767 (define_expand "call_value_internal0"
6768 [(parallel [(set (match_operand 0 "" "")
6769 (call (match_operand 1 "" "")
6770 (match_operand 2 "" "")))
6771 (clobber (match_operand:SI 3 "" ""))])]
6775 (define_insn "call_value_internal1"
6776 [(set (match_operand 0 "register_operand" "=df")
6777 (call (mem (match_operand 1 "call_insn_operand" "ri"))
6778 (match_operand 2 "" "i")))
6779 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6780 "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
6783 register rtx target = operands[1];
6785 if (GET_CODE (target) == SYMBOL_REF)
6786 return \"%*jal\\t%1\";
6787 else if (GET_CODE (target) == CONST_INT)
6788 return \"%[li\\t%@,%1\\n\\t%*jal\\t%3,%@%]\";
6790 return \"%*jal\\t%3,%1\";
6792 [(set_attr "type" "call")
6793 (set_attr "mode" "none")
6794 (set_attr "length" "1")])
6796 (define_insn "call_value_internal2"
6797 [(set (match_operand 0 "register_operand" "=df")
6798 (call (mem (match_operand 1 "call_insn_operand" "ri"))
6799 (match_operand 2 "" "i")))
6800 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6801 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
6804 register rtx target = operands[1];
6806 if (GET_CODE (target) == SYMBOL_REF)
6808 if (GET_MODE (target) == SImode)
6809 return \"la\\t%^,%1\\n\\tjal\\t%3,%^\";
6811 return \"dla\\t%^,%1\\n\\tjal\\t%3,%^\";
6813 else if (GET_CODE (target) == CONST_INT)
6814 return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
6815 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
6816 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
6818 return \"jal\\t%3,%1\";
6820 [(set_attr "type" "call")
6821 (set_attr "mode" "none")
6822 (set_attr "length" "2")])
6824 (define_insn "call_value_internal3a"
6825 [(set (match_operand 0 "register_operand" "=df")
6826 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
6827 (match_operand 2 "" "i")))
6828 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6829 "!TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
6831 [(set_attr "type" "call")
6832 (set_attr "mode" "none")
6833 (set_attr "length" "1")])
6835 (define_insn "call_value_internal3b"
6836 [(set (match_operand 0 "register_operand" "=df")
6837 (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
6838 (match_operand 2 "" "i")))
6839 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6840 "TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
6842 [(set_attr "type" "call")
6843 (set_attr "mode" "none")
6844 (set_attr "length" "1")])
6846 (define_insn "call_value_internal4a"
6847 [(set (match_operand 0 "register_operand" "=df")
6848 (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
6849 (match_operand 2 "" "i")))
6850 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6851 "!TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
6854 if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
6855 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
6857 return \"jal\\t%3,%1\";
6859 [(set_attr "type" "call")
6860 (set_attr "mode" "none")
6861 (set_attr "length" "2")])
6863 (define_insn "call_value_internal4b"
6864 [(set (match_operand 0 "register_operand" "=df")
6865 (call (mem:DI (match_operand:DI 1 "se_register_operand" "r"))
6866 (match_operand 2 "" "i")))
6867 (clobber (match_operand:SI 3 "register_operand" "=d"))]
6868 "TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
6871 if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
6872 return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
6874 return \"jal\\t%3,%1\";
6876 [(set_attr "type" "call")
6877 (set_attr "mode" "none")
6878 (set_attr "length" "2")])
6880 (define_expand "call_value_multiple_internal0"
6881 [(parallel [(set (match_operand 0 "" "")
6882 (call (match_operand 1 "" "")
6883 (match_operand 2 "" "")))
6884 (set (match_operand 3 "" "")
6887 (clobber (match_operand:SI 4 "" ""))])]
6891 ;; ??? May eventually need all 6 versions of the call patterns with multiple
6894 (define_insn "call_value_multiple_internal2"
6895 [(set (match_operand 0 "register_operand" "=df")
6896 (call (mem (match_operand 1 "call_insn_operand" "ri"))
6897 (match_operand 2 "" "i")))
6898 (set (match_operand 3 "register_operand" "=df")
6899 (call (mem (match_dup 1))
6901 (clobber (match_operand:SI 4 "register_operand" "=d"))]
6902 "TARGET_ABICALLS && !TARGET_LONG_CALLS"
6905 register rtx target = operands[1];
6907 if (GET_CODE (target) == SYMBOL_REF)
6909 if (GET_MODE (target) == SImode)
6910 return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
6912 return \"la\\t%^,%1\\n\\tjal\\t%4,%^\";
6914 else if (GET_CODE (target) == CONST_INT)
6915 return \"li\\t%^,%1\\n\\tjal\\t%4,%^\";
6916 else if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
6917 return \"move\\t%^,%1\\n\\tjal\\t%4,%^\";
6919 return \"jal\\t%4,%1\";
6921 [(set_attr "type" "call")
6922 (set_attr "mode" "none")
6923 (set_attr "length" "2")])
6926 ;; Call subroutine returning any type.
6928 (define_expand "untyped_call"
6929 [(parallel [(call (match_operand 0 "" "")
6931 (match_operand 1 "" "")
6932 (match_operand 2 "" "")])]
6936 if (operands[0]) /* silence statement not reached warnings */
6940 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6942 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6944 rtx set = XVECEXP (operands[2], 0, i);
6945 emit_move_insn (SET_DEST (set), SET_SRC (set));
6948 emit_insn (gen_blockage ());
6954 ;; ....................
6958 ;; ....................
6965 [(set_attr "type" "nop")
6966 (set_attr "mode" "none")
6967 (set_attr "length" "1")])
6969 ;; The MIPS chip does not seem to require stack probes.
6971 ;; (define_expand "probe"
6972 ;; [(set (match_dup 0)
6977 ;; operands[0] = gen_reg_rtx (SImode);
6978 ;; operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx);
6979 ;; MEM_VOLATILE_P (operands[1]) = TRUE;
6981 ;; /* fall through and generate default code */
6986 ;; MIPS4 Conditional move instructions.
6989 [(set (match_operand:SI 0 "register_operand" "=d,d")
6991 (match_operator 4 "equality_op"
6992 [(match_operand:SI 1 "register_operand" "d,d")
6994 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
6995 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
7000 [(set_attr "type" "move")
7001 (set_attr "mode" "SI")])
7004 [(set (match_operand:SI 0 "register_operand" "=d,d")
7006 (match_operator 4 "equality_op"
7007 [(match_operand:DI 1 "se_register_operand" "d,d")
7009 (match_operand:SI 2 "reg_or_0_operand" "dJ,0")
7010 (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
7015 [(set_attr "type" "move")
7016 (set_attr "mode" "SI")])
7019 [(set (match_operand:SI 0 "register_operand" "=d,d")
7021 (match_operator 3 "equality_op" [(match_operand:CC 4
7025 (match_operand:SI 1 "reg_or_0_operand" "dJ,0")
7026 (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
7027 "mips_isa >= 4 && TARGET_HARD_FLOAT"
7031 [(set_attr "type" "move")
7032 (set_attr "mode" "SI")])
7035 [(set (match_operand:DI 0 "register_operand" "=d,d")
7037 (match_operator 4 "equality_op"
7038 [(match_operand:SI 1 "register_operand" "d,d")
7040 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
7041 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
7046 [(set_attr "type" "move")
7047 (set_attr "mode" "DI")])
7050 [(set (match_operand:DI 0 "register_operand" "=d,d")
7052 (match_operator 4 "equality_op"
7053 [(match_operand:DI 1 "se_register_operand" "d,d")
7055 (match_operand:DI 2 "se_reg_or_0_operand" "dJ,0")
7056 (match_operand:DI 3 "se_reg_or_0_operand" "0,dJ")))]
7061 [(set_attr "type" "move")
7062 (set_attr "mode" "DI")])
7065 [(set (match_operand:DI 0 "register_operand" "=d,d")
7067 (match_operator 3 "equality_op" [(match_operand:CC 4
7071 (match_operand:DI 1 "se_reg_or_0_operand" "dJ,0")
7072 (match_operand:DI 2 "se_reg_or_0_operand" "0,dJ")))]
7073 "mips_isa >= 4 && TARGET_HARD_FLOAT"
7077 [(set_attr "type" "move")
7078 (set_attr "mode" "DI")])
7081 [(set (match_operand:SF 0 "register_operand" "=f,f")
7083 (match_operator 4 "equality_op"
7084 [(match_operand:SI 1 "register_operand" "d,d")
7086 (match_operand:SF 2 "register_operand" "f,0")
7087 (match_operand:SF 3 "register_operand" "0,f")))]
7088 "mips_isa >= 4 && TARGET_HARD_FLOAT"
7091 mov%b4.s\\t%0,%3,%1"
7092 [(set_attr "type" "move")
7093 (set_attr "mode" "SF")])
7096 [(set (match_operand:SF 0 "register_operand" "=f,f")
7098 (match_operator 3 "equality_op" [(match_operand:CC 4
7102 (match_operand:SF 1 "register_operand" "f,0")
7103 (match_operand:SF 2 "register_operand" "0,f")))]
7104 "mips_isa >= 4 && TARGET_HARD_FLOAT"
7107 mov%t3.s\\t%0,%2,%4"
7108 [(set_attr "type" "move")
7109 (set_attr "mode" "SF")])
7112 [(set (match_operand:DF 0 "register_operand" "=f,f")
7114 (match_operator 4 "equality_op"
7115 [(match_operand:SI 1 "register_operand" "d,d")
7117 (match_operand:DF 2 "register_operand" "f,0")
7118 (match_operand:DF 3 "register_operand" "0,f")))]
7119 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7122 mov%b4.d\\t%0,%3,%1"
7123 [(set_attr "type" "move")
7124 (set_attr "mode" "DF")])
7127 [(set (match_operand:DF 0 "register_operand" "=f,f")
7129 (match_operator 3 "equality_op" [(match_operand:CC 4
7133 (match_operand:DF 1 "register_operand" "f,0")
7134 (match_operand:DF 2 "register_operand" "0,f")))]
7135 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7138 mov%t3.d\\t%0,%2,%4"
7139 [(set_attr "type" "move")
7140 (set_attr "mode" "DF")])
7142 ;; These are the main define_expand's used to make conditional moves.
7144 (define_expand "movsicc"
7145 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
7146 (set (match_operand:SI 0 "register_operand" "")
7147 (if_then_else:SI (match_dup 5)
7148 (match_operand:SI 2 "reg_or_0_operand" "")
7149 (match_operand:SI 3 "reg_or_0_operand" "")))]
7153 gen_conditional_move (operands);
7157 (define_expand "movdicc"
7158 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
7159 (set (match_operand:DI 0 "register_operand" "")
7160 (if_then_else:DI (match_dup 5)
7161 (match_operand:DI 2 "se_reg_or_0_operand" "")
7162 (match_operand:DI 3 "se_reg_or_0_operand" "")))]
7166 gen_conditional_move (operands);
7170 (define_expand "movsfcc"
7171 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
7172 (set (match_operand:SF 0 "register_operand" "")
7173 (if_then_else:SF (match_dup 5)
7174 (match_operand:SF 2 "register_operand" "")
7175 (match_operand:SF 3 "register_operand" "")))]
7176 "mips_isa >= 4 && TARGET_HARD_FLOAT"
7179 gen_conditional_move (operands);
7183 (define_expand "movdfcc"
7184 [(set (match_dup 4) (match_operand 1 "comparison_operator" ""))
7185 (set (match_operand:DF 0 "register_operand" "")
7186 (if_then_else:DF (match_dup 5)
7187 (match_operand:DF 2 "register_operand" "")
7188 (match_operand:DF 3 "register_operand" "")))]
7189 "mips_isa >= 4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
7192 gen_conditional_move (operands);