1 ; Options for the MIPS port of the compiler
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22 config/mips/mips-opts.h
31 Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT)
32 -mabi=ABI Generate code that conforms to the given ABI.
35 Name(mips_abi) Type(int)
36 Known MIPS ABIs (for use with the -mabi= option):
39 Enum(mips_abi) String(32) Value(ABI_32)
42 Enum(mips_abi) String(o64) Value(ABI_O64)
45 Enum(mips_abi) String(n32) Value(ABI_N32)
48 Enum(mips_abi) String(64) Value(ABI_64)
51 Enum(mips_abi) String(eabi) Value(ABI_EABI)
55 Generate code that can be used in SVR4-style dynamic objects.
58 Target Var(TARGET_MAD)
59 Use PMC-style 'mad' instructions.
63 Use integer madd/msub instructions.
66 Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value)
67 -march=ISA Generate code for the given ISA.
70 Target RejectNegative Joined UInteger Var(mips_branch_cost)
71 -mbranch-cost=COST Set the cost of branches to roughly COST instructions.
74 Target Mask(BRANCHLIKELY)
75 Use Branch Likely instructions, overriding the architecture default.
78 Target Var(TARGET_FLIP_MIPS16)
79 Switch on/off MIPS16 ASE on alternating functions for compiler testing.
82 Target Mask(CHECK_ZERO_DIV)
83 Trap on integer divide by zero.
86 Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES)
87 -mcode-readable=SETTING Specify when instructions are allowed to access code.
90 Name(mips_code_readable_setting) Type(enum mips_code_readable_setting)
91 Valid arguments to -mcode-readable=:
94 Enum(mips_code_readable_setting) String(yes) Value(CODE_READABLE_YES)
97 Enum(mips_code_readable_setting) String(pcrel) Value(CODE_READABLE_PCREL)
100 Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO)
103 Target RejectNegative Mask(DIVIDE_BREAKS)
104 Use branch-and-break sequences to check for integer divide by zero.
107 Target RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS)
108 Use trap instructions to check for integer divide by zero.
111 Target RejectNegative Var(TARGET_MDMX)
112 Allow the use of MDMX instructions.
115 Target RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT)
116 Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations.
119 Target Var(TARGET_DSP)
120 Use MIPS-DSP instructions.
123 Target Var(TARGET_DSPR2)
124 Use MIPS-DSP REV 2 instructions.
127 Target Var(TARGET_DEBUG_MODE) Undocumented
130 Target Var(TARGET_DEBUG_D_MODE) Undocumented
133 Target RejectNegative Mask(BIG_ENDIAN)
134 Use big-endian byte order.
137 Target RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
138 Use little-endian byte order.
141 Target Var(TARGET_EMBEDDED_DATA)
142 Use ROM instead of RAM.
145 Target Var(TARGET_EVA)
146 Use Enhanced Virtual Addressing instructions.
149 Target Mask(EXPLICIT_RELOCS)
150 Use NewABI-style %reloc() assembly operators.
153 Target Var(TARGET_EXTERN_SDATA) Init(1)
154 Use -G for data that is not defined by the current object.
157 Target Var(TARGET_FIX_24K)
158 Work around certain 24K errata.
161 Target Mask(FIX_R4000)
162 Work around certain R4000 errata.
165 Target Mask(FIX_R4400)
166 Work around certain R4400 errata.
169 Target Mask(FIX_R5900)
170 Work around the R5900 short loop erratum.
173 Target Var(TARGET_FIX_RM7000)
174 Work around certain RM7000 errata.
177 Target Mask(FIX_R10000)
178 Work around certain R10000 errata.
181 Target Var(TARGET_FIX_SB1)
182 Work around errata for early SB-1 revision 2 cores.
185 Target Var(TARGET_FIX_VR4120)
186 Work around certain VR4120 errata.
189 Target Var(TARGET_FIX_VR4130)
190 Work around VR4130 mflo/mfhi errata.
193 Target Var(TARGET_4300_MUL_FIX)
194 Work around an early 4300 hardware bug.
197 Target Var(TARGET_FP_EXCEPTIONS) Init(1)
198 FP exceptions are enabled.
201 Target RejectNegative InverseMask(FLOAT64)
202 Use 32-bit floating-point registers.
205 Target RejectNegative Mask(FLOATXX)
206 Conform to the o32 FPXX ABI.
209 Target RejectNegative Mask(FLOAT64)
210 Use 64-bit floating-point registers.
213 Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC)
214 -mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines.
217 Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_abs) Init(MIPS_IEEE_754_DEFAULT)
218 -mabs=MODE Select the IEEE 754 ABS/NEG instruction execution mode.
221 Target RejectNegative Joined Enum(mips_ieee_754_value) Var(mips_nan) Init(MIPS_IEEE_754_DEFAULT)
222 -mnan=ENCODING Select the IEEE 754 NaN data encoding.
225 Name(mips_ieee_754_value) Type(int)
226 Known MIPS IEEE 754 settings (for use with the -mabs= and -mnan= options):
229 Enum(mips_ieee_754_value) String(2008) Value(MIPS_IEEE_754_2008)
232 Enum(mips_ieee_754_value) String(legacy) Value(MIPS_IEEE_754_LEGACY)
235 Target RejectNegative InverseMask(64BIT)
236 Use 32-bit general registers.
239 Target RejectNegative Mask(64BIT)
240 Use 64-bit general registers.
243 Target Var(TARGET_GPOPT) Init(1)
244 Use GP-relative addressing to access small data.
247 Target Var(TARGET_PLT)
248 When generating -mabicalls code, allow executables to use PLTs and copy relocations.
251 Target RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI)
252 Allow the use of hardware floating-point ABI and instructions.
254 minterlink-compressed
255 Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
256 Generate code that is link-compatible with MIPS16 and microMIPS code.
259 Target Var(TARGET_INTERLINK_COMPRESSED) Init(0)
260 An alias for minterlink-compressed provided for backward-compatibility.
263 Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option)
264 -mipsN Generate code for ISA level N.
267 Target RejectNegative Mask(MIPS16)
268 Generate MIPS16 code.
271 Target RejectNegative Var(TARGET_MIPS3D)
272 Use MIPS-3D instructions.
276 Use ll, sc and sync instructions.
279 Target Var(TARGET_LOCAL_SDATA) Init(1)
280 Use -G for object-local data.
283 Target Var(TARGET_LONG_CALLS)
287 Target RejectNegative InverseMask(LONG64, LONG32)
288 Use a 32-bit long type.
291 Target RejectNegative Mask(LONG64)
292 Use a 64-bit long type.
295 Target Var(TARGET_MCOUNT_RA_ADDRESS)
296 Pass the address of the ra save location to _mcount in $12.
300 Don't optimize block moves.
303 Target Mask(MICROMIPS)
304 Use microMIPS instructions.
308 Use MIPS MSA Extension instructions.
311 Target Var(TARGET_MT)
312 Allow the use of MT instructions.
315 Target RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT)
316 Prevent the use of all floating-point operations.
319 Target Var(TARGET_MCU)
320 Use MCU instructions.
323 Target RejectNegative
324 Do not use a cache-flushing function before calling stack trampolines.
327 Target RejectNegative Var(TARGET_MDMX, 0)
328 Do not use MDMX instructions.
331 Target RejectNegative InverseMask(MIPS16)
332 Generate normal-mode code.
335 Target RejectNegative Var(TARGET_MIPS3D, 0)
336 Do not use MIPS-3D instructions.
339 Target Mask(PAIRED_SINGLE_FLOAT)
340 Use paired-single floating-point instructions.
343 Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE)
344 -mr10k-cache-barrier=SETTING Specify when r10k cache barriers should be inserted.
347 Name(mips_r10k_cache_barrier_setting) Type(enum mips_r10k_cache_barrier_setting)
348 Valid arguments to -mr10k-cache-barrier=:
351 Enum(mips_r10k_cache_barrier_setting) String(load-store) Value(R10K_CACHE_BARRIER_LOAD_STORE)
354 Enum(mips_r10k_cache_barrier_setting) String(store) Value(R10K_CACHE_BARRIER_STORE)
357 Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE)
360 Target Mask(RELAX_PIC_CALLS)
361 Try to allow the linker to turn PIC calls into direct calls.
364 Target Var(TARGET_SHARED) Init(1)
365 When generating -mabicalls code, make the code suitable for use in shared libraries.
368 Target RejectNegative Mask(SINGLE_FLOAT)
369 Restrict the use of hardware floating-point instructions to 32-bit operations.
372 Target Mask(SMARTMIPS)
373 Use SmartMIPS instructions.
376 Target RejectNegative Mask(SOFT_FLOAT_ABI)
377 Prevent the use of all hardware floating-point instructions.
380 Target Mask(SPLIT_ADDRESSES)
381 Optimize lui/addiu address loads.
384 Target Var(TARGET_MIPS16E2) Init(0)
385 Enable the MIPS16e V2 instructions.
388 Target Var(TARGET_SYM32)
389 Assume all symbols have 32-bit values.
393 Use synci instruction to invalidate i-cache.
396 Target Var(mips_lra_flag) Init(1) Save
397 Use LRA instead of reload.
400 Target Var(mips_lxc1_sxc1) Init(1)
401 Use lwxc1/swxc1/ldxc1/sdxc1 instructions where applicable.
404 Target Var(mips_madd4) Init(1)
405 Use 4-operand madd.s/madd.d and related instructions where applicable.
408 Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
409 -mtune=PROCESSOR Optimize the output for PROCESSOR.
412 Target Var(TARGET_UNALIGNED_ACCESS) Init(1)
413 Generate code with unaligned load store, valid for MIPS R6.
415 muninit-const-in-rodata
416 Target Var(TARGET_UNINIT_CONST_IN_RODATA)
417 Put uninitialized constants in ROM (needs -membedded-data).
420 Target Var(TARGET_VIRT)
421 Use Virtualization (VZ) instructions.
424 Target Var(TARGET_XPA)
425 Use eXtended Physical Address (XPA) instructions.
428 Target Var(TARGET_CRC)
429 Use Cyclic Redundancy Check (CRC) instructions.
432 Target Var(TARGET_GINV)
433 Use Global INValidate (GINV) instructions.
436 Target Mask(VR4130_ALIGN)
437 Perform VR4130-specific alignment optimizations.
440 Target Var(TARGET_XGOT)
441 Lift restrictions on GOT size.
444 Target Mask(ODD_SPREG)
445 Enable use of odd-numbered single-precision registers.
448 Target Var(flag_frame_header_optimization) Optimization
449 Optimize frame header.
455 Target Var(TARGET_LOAD_STORE_PAIRS) Init(1)
456 Enable load/store bonding.
459 Target RejectNegative JoinedOrMissing Var(mips_cb) Enum(mips_cb_setting) Init(MIPS_CB_OPTIMAL)
460 Specify the compact branch usage policy.
463 Name(mips_cb_setting) Type(enum mips_cb_setting)
464 Policies available for use with -mcompact-branches=:
467 Enum(mips_cb_setting) String(never) Value(MIPS_CB_NEVER)
470 Enum(mips_cb_setting) String(optimal) Value(MIPS_CB_OPTIMAL)
473 Enum(mips_cb_setting) String(always) Value(MIPS_CB_ALWAYS)
476 Target Mask(LOONGSON_MMI)
477 Use Loongson MultiMedia extensions Instructions (MMI) instructions.
480 Target Mask(LOONGSON_EXT)
481 Use Loongson EXTension (EXT) instructions.
484 Target Var(TARGET_LOONGSON_EXT2)
485 Use Loongson EXTension R2 (EXT2) instructions.