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1 /* Definitions of target machine for GNU compiler.
2 Matsushita MN10200 series
3 Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002
4 Free Software Foundation, Inc.
5 Contributed by Jeff Law (law@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 /* Get rid of svr4.h stuff we don't want/need. */
33 /* Names to predefine in the preprocessor for this target machine. */
35 #define CPP_PREDEFINES "-D__mn10200__ -D__MN10200__ -D__LONG_MAX__=2147483647L -D__LONG_LONG_MAX__=2147483647L -D__INT_MAX__=32767"
37 /* Run-time compilation parameters selecting different hardware subsets. */
39 /* We don't have any switched on the mn10200. Though there are some things
40 that might be worth a switch:
42 -mspace to optimize even more for space.
44 -mrelax to enable the relaxing linker. */
46 extern int target_flags
;
48 /* Macros used in the machine description to test the flags. */
50 /* Macro to define tables used to set the flags.
51 This is a list in braces of pairs in braces,
52 each pair being { "NAME", VALUE }
53 where VALUE is the bits to set or minus the bits to clear.
54 An empty string NAME is used to identify the default VALUE. */
56 #define TARGET_SWITCHES \
57 {{ "", TARGET_DEFAULT, 0}}
59 #ifndef TARGET_DEFAULT
60 #define TARGET_DEFAULT 0
63 /* Print subsidiary information on the compiler version in use. */
65 #define TARGET_VERSION fprintf (stderr, " (MN10200)");
68 /* Target machine storage layout */
70 /* Define this if most significant bit is lowest numbered
71 in instructions that operate on numbered bit-fields.
72 This is not true on the Matsushita MN10300. */
73 #define BITS_BIG_ENDIAN 0
75 /* Define this if most significant byte of a word is the lowest numbered. */
76 /* This is not true on the Matsushita MN10200. */
77 #define BYTES_BIG_ENDIAN 0
79 /* Define this if most significant word of a multiword number is lowest
81 This is not true on the Matsushita MN10200. */
82 #define WORDS_BIG_ENDIAN 0
84 /* This is a white lie. Registers are really 24bits, but most operations
85 only operate on 16 bits. GCC chokes badly if we set this to a value
86 that is not a power of two. */
87 /* Width of a word, in units (bytes). */
88 #define UNITS_PER_WORD 2
90 /* Width in bits of a pointer.
91 See also the macro `Pmode' defined below.
93 This differs from Pmode because we need to allocate 32bits of space
94 to hold the 24bit pointers on this machine. */
95 #define POINTER_SIZE 32
97 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
98 #define PARM_BOUNDARY 16
100 /* The stack goes in 16 bit lumps. */
101 #define STACK_BOUNDARY 16
103 /* Allocation boundary (in *bits*) for the code of a function.
104 8 is the minimum boundary; it's unclear if bigger alignments
105 would improve performance. */
106 #define FUNCTION_BOUNDARY 8
108 /* No data type wants to be aligned rounder than this. */
109 #define BIGGEST_ALIGNMENT 16
111 /* Alignment of field after `int : 0' in a structure. */
112 #define EMPTY_FIELD_BOUNDARY 16
114 /* Seems to be how the Matsushita compiler does things, and there's
115 no real reason to be different. */
116 #define STRUCTURE_SIZE_BOUNDARY 16
117 #undef PCC_BITFIELD_TYPE_MATTERS
119 /* Define this if move instructions will actually fail to work
120 when given unaligned data. */
121 #define STRICT_ALIGNMENT 1
123 /* Define this as 1 if `char' should by default be signed; else as 0. */
124 #define DEFAULT_SIGNED_CHAR 0
126 /* Standard register usage. */
128 /* Number of actual hardware registers.
129 The hardware registers are assigned numbers for the compiler
130 from 0 to just below FIRST_PSEUDO_REGISTER.
132 All registers that the compiler knows about must be given numbers,
133 even those that are not normally considered general registers.
135 XXX Long term we should probably expose the MDR register, we use
136 it for division, multiplication, and some extension operations. */
138 #define FIRST_PSEUDO_REGISTER 8
140 /* 1 for registers that have pervasive standard uses
141 and are not available for the register allocator. */
143 #define FIXED_REGISTERS \
144 { 0, 0, 0, 0, 0, 0, 0, 1}
146 /* 1 for registers not available across function calls.
147 These must include the FIXED_REGISTERS and also any
148 registers that can be used without being saved.
149 The latter must include the registers where values are returned
150 and the register where structure-value addresses are passed.
151 Aside from that, you can include as many other registers as you
154 #define CALL_USED_REGISTERS \
155 { 1, 1, 0, 0, 1, 0, 0, 1}
157 #define REG_ALLOC_ORDER \
158 { 0, 1, 4, 2, 3, 5, 6, 7}
160 /* Return number of consecutive hard regs needed starting at reg REGNO
161 to hold something of mode MODE.
163 This is ordinarily the length in words of a value of mode MODE
164 but can be less for certain modes in special long registers. */
166 #define HARD_REGNO_NREGS(REGNO, MODE) \
167 ((MODE) == PSImode ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
170 /* Value is 1 if hard register REGNO can hold a value of machine-mode
173 We allow any register to hold a PSImode value. We allow any register
174 to hold values <= 16 bits. For values > 16 bits we require aligned
176 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
177 ((MODE) == PSImode ? 1 : ((REGNO) & 1) == 0 || GET_MODE_SIZE (MODE) <= 2)
179 /* Value is 1 if it is a good idea to tie two pseudo registers
180 when one has mode MODE1 and one has mode MODE2.
181 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
182 for any hard reg, then this must be 0 for correct output. */
183 #define MODES_TIEABLE_P(MODE1, MODE2) \
184 (MODE1 == MODE2 || (GET_MODE_SIZE (MODE1) <= 2 && GET_MODE_SIZE (MODE2) <= 2))
186 /* 4 data, and effectively 2 address registers is small as far as I'm
187 concerned. Especially since we use 2 data registers for argument
188 passing and return values.
190 We used to define CLASS_LIKELY_SPILLED_P as true for DATA_REGS too,
191 but we've made improvements to the port which greatly reduce register
192 pressure. As a result we no longer need to define CLASS_LIKELY_SPILLED_P
193 for DATA_REGS (and by not defining it we get significantly better code). */
194 #define SMALL_REGISTER_CLASSES 1
195 #define CLASS_LIKELY_SPILLED_P(CLASS) (CLASS == ADDRESS_REGS)
197 /* Define the classes of registers for register constraints in the
198 machine description. Also define ranges of constants.
200 One of the classes must always be named ALL_REGS and include all hard regs.
201 If there is more than one class, another class must be named NO_REGS
202 and contain no registers.
204 The name GENERAL_REGS must be the name of a class (or an alias for
205 another name such as ALL_REGS). This is the class of registers
206 that is allowed by "g" or "r" in a register constraint.
207 Also, registers outside this class are allocated only when
208 instructions express preferences for them.
210 The classes must be numbered in nondecreasing order; that is,
211 a larger-numbered class must never be contained completely
212 in a smaller-numbered class.
214 For any two classes, it is very desirable that there be another
215 class that represents their union. */
218 NO_REGS
, DATA_REGS
, ADDRESS_REGS
, GENERAL_REGS
, ALL_REGS
, LIM_REG_CLASSES
221 #define N_REG_CLASSES (int) LIM_REG_CLASSES
223 /* Give names of register classes as strings for dump file. */
225 #define REG_CLASS_NAMES \
226 { "NO_REGS", "DATA_REGS", "ADDRESS_REGS", \
227 "GENERAL_REGS", "ALL_REGS", "LIM_REGS" }
229 /* Define which registers fit in which classes.
230 This is an initializer for a vector of HARD_REG_SET
231 of length N_REG_CLASSES. */
233 #define REG_CLASS_CONTENTS \
234 { {0}, /* No regs */ \
235 {0x0f}, /* DATA_REGS */ \
236 {0xf0}, /* ADDRESS_REGS */ \
237 {0xff}, /* GENERAL_REGS */ \
238 {0xff}, /* ALL_REGS */ \
241 /* The same information, inverted:
242 Return the class number of the smallest class containing
243 reg number REGNO. This could be a conditional expression
244 or could index an array. */
246 #define REGNO_REG_CLASS(REGNO) \
247 ((REGNO) < 4 ? DATA_REGS : ADDRESS_REGS)
249 /* The class value for index registers, and the one for base regs. */
251 #define INDEX_REG_CLASS DATA_REGS
252 #define BASE_REG_CLASS ADDRESS_REGS
254 /* Get reg_class from a letter such as appears in the machine description. */
256 #define REG_CLASS_FROM_LETTER(C) \
257 ((C) == 'd' ? DATA_REGS : \
258 (C) == 'a' ? ADDRESS_REGS : NO_REGS)
260 /* Macros to check register numbers against specific register classes. */
262 /* These assume that REGNO is a hard or pseudo reg number.
263 They give nonzero only if REGNO is a hard reg of the suitable class
264 or a pseudo reg currently allocated to a suitable hard reg.
265 Since they use reg_renumber, they are safe only once reg_renumber
266 has been allocated, which happens in local-alloc.c. */
268 #define REGNO_OK_FOR_BASE_P(regno) \
269 (((regno) > 3 && regno < FIRST_PSEUDO_REGISTER) \
270 || (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER))
272 #define REGNO_OK_FOR_INDEX_P(regno) \
273 (IN_RANGE ((regno), 0, 3) \
274 || (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4))
277 /* Given an rtx X being reloaded into a reg required to be
278 in class CLASS, return the class of reg to actually use.
279 In general this is just CLASS; but on some machines
280 in some cases it is preferable to use a more restrictive class. */
282 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
283 ((GET_MODE (X) != PSImode && GET_MODE (X) != VOIDmode) ? DATA_REGS : CLASS)
285 /* We want to use DATA_REGS for anything that is not PSImode. */
286 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
287 ((MODE != PSImode && MODE != VOIDmode) ? DATA_REGS : CLASS)
289 /* We have/need secondary reloads on the mn10200. Mostly to deal
290 with problems using address registers. */
291 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,IN) \
292 secondary_reload_class(CLASS,MODE,IN, 1)
294 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS,MODE,IN) \
295 secondary_reload_class(CLASS,MODE,IN, 0)
297 /* Return the maximum number of consecutive registers
298 needed to represent mode MODE in a register of class CLASS. */
300 #define CLASS_MAX_NREGS(CLASS, MODE) \
301 ((MODE) == PSImode ? 1 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
303 /* The letters I, J, K, L, M, N, O, P in a register constraint string
304 can be used to stand for particular ranges of immediate operands.
305 This macro defines what the ranges are.
306 C is the letter, and VALUE is a constant value.
307 Return 1 if VALUE is in the range specified by C. */
309 #define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
310 #define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
312 #define CONST_OK_FOR_I(VALUE) ((VALUE) == 0)
313 #define CONST_OK_FOR_J(VALUE) ((VALUE) >= 1 && (VALUE) <= 3)
314 #define CONST_OK_FOR_K(VALUE) ((VALUE) >= 1 && (VALUE) <= 4)
315 #define CONST_OK_FOR_L(VALUE) ((VALUE) == 15)
316 #define CONST_OK_FOR_M(VALUE) ((VALUE) == 255)
318 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
319 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) : \
320 (C) == 'J' ? CONST_OK_FOR_J (VALUE) : \
321 (C) == 'K' ? CONST_OK_FOR_K (VALUE) : \
322 (C) == 'L' ? CONST_OK_FOR_L (VALUE) : \
323 (C) == 'M' ? CONST_OK_FOR_M (VALUE) : 0)
325 /* Similar, but for floating constants, and defining letters G and H.
326 Here VALUE is the CONST_DOUBLE rtx itself.
328 `G' is a floating-point zero. */
330 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
331 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
332 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
337 /* Stack layout; function entry, exit and calling. */
339 /* Define this if pushing a word on the stack
340 makes the stack pointer a smaller address. */
342 #define STACK_GROWS_DOWNWARD
344 /* Define this if the nominal address of the stack frame
345 is at the high-address end of the local variables;
346 that is, each additional local variable allocated
347 goes at a more negative offset in the frame. */
349 #define FRAME_GROWS_DOWNWARD
351 /* Offset within stack frame to start allocating local variables at.
352 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
353 first local allocated. Otherwise, it is the offset to the BEGINNING
354 of the first local allocated. */
356 #define STARTING_FRAME_OFFSET 0
358 /* Offset of first parameter from the argument pointer register value. */
359 /* Is equal to the size of the saved fp + pc, even if an fp isn't
360 saved since the value is used before we know. */
362 #define FIRST_PARM_OFFSET(FNDECL) (current_function_needs_context ? 8 : 4)
364 /* Specify the registers used for certain standard purposes.
365 The values of these macros are register numbers. */
367 /* Register to use for pushing function arguments. */
368 #define STACK_POINTER_REGNUM 7
370 /* Base register for access to local variables of the function. */
371 #define FRAME_POINTER_REGNUM 6
373 /* Base register for access to arguments of the function. */
374 #define ARG_POINTER_REGNUM 6
376 /* Register in which static-chain is passed to a function. */
377 #define STATIC_CHAIN_REGNUM 4
379 /* Value should be nonzero if functions must have frame pointers.
380 Zero means the frame pointer need not be set up (and parms
381 may be accessed via the stack pointer) in functions that seem suitable.
382 This is computed in `reload', in reload1.c.
384 We allow frame pointers to be eliminated when not having one will
385 not interfere with debugging. */
386 #define ACCUMULATE_OUTGOING_ARGS 1
387 #define FRAME_POINTER_REQUIRED 0
388 #define CAN_DEBUG_WITHOUT_FP
390 /* Store in the variable DEPTH the initial difference between the
391 frame pointer reg contents and the stack pointer reg contents,
392 as of the start of the function body. This depends on the layout
393 of the fixed parts of the stack frame and on how registers are saved. */
395 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = total_frame_size()
397 /* Various type size information.
399 The mn10200 has a limited number of small registers. Sizes of basic
400 data types are adjusted accordingly. */
401 #define SHORT_TYPE_SIZE 16
402 #define INT_TYPE_SIZE 16
403 #define LONG_TYPE_SIZE 32
404 #define LONG_LONG_TYPE_SIZE 32
405 #define FLOAT_TYPE_SIZE 32
406 #define DOUBLE_TYPE_SIZE 32
407 #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
409 /* Any size less than 64bits will work; but a smarter definition
410 can make G++ code smaller and faster. Most operations on the
411 mn10200 occur on 16bit hunks, so the best size for a boolean
413 #define BOOL_TYPE_SIZE 16
415 /* The difference of two pointers must be at least 24bits since pointers
416 are 24bits; however, no basic data type is 24bits, so we have to round
417 up to a 32bits for the difference of pointers. */
420 #define SIZE_TYPE "long unsigned int"
421 #define PTRDIFF_TYPE "long int"
423 /* Note sizeof (WCHAR_TYPE) must be equal to the value of WCHAR_TYPE_SIZE! */
425 #define WCHAR_TYPE "int"
427 #undef WCHAR_TYPE_SIZE
428 #define WCHAR_TYPE_SIZE BITS_PER_WORD
430 #define MAX_FIXED_MODE_SIZE 32
432 /* A guess for the MN10200. */
433 #define PROMOTE_PROTOTYPES 1
435 /* Value is the number of bytes of arguments automatically
436 popped when returning from a subroutine call.
437 FUNDECL is the declaration node of the function (as a tree),
438 FUNTYPE is the data type of the function (as a tree),
439 or for a library call it is an identifier node for the subroutine name.
440 SIZE is the number of bytes of arguments passed on the stack. */
442 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
444 /* 1 if N is a possible register number for function argument passing. */
446 #define FUNCTION_ARG_REGNO_P(N) ((N) <= 1)
448 /* Define a data type for recording info about an argument list
449 during the scan of that argument list. This data type should
450 hold all necessary information about the function itself
451 and about the args processed so far, enough to enable macros
452 such as FUNCTION_ARG to determine where the next arg should go. */
454 #define CUMULATIVE_ARGS struct cum_arg
455 struct cum_arg
{ int nbytes
; };
457 /* Initialize a variable CUM of type CUMULATIVE_ARGS
458 for a call to a function whose data type is FNTYPE.
459 For a library call, FNTYPE is 0.
461 On the MN10200, the offset starts at 0. */
463 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
466 /* Update the data in CUM to advance over an argument
467 of mode MODE and data type TYPE.
468 (TYPE is null for libcalls where that information may not be available.) */
470 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
471 ((CUM).nbytes += ((MODE) != BLKmode \
472 ? (MODE) == PSImode ? 2 : \
473 (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD \
474 : (int_size_in_bytes (TYPE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD))
476 /* Define where to put the arguments to a function.
477 Value is zero to push the argument on the stack,
478 or a hard register in which to store the argument.
480 MODE is the argument's machine mode.
481 TYPE is the data type of the argument (as a tree).
482 This is null for libcalls where that information may
484 CUM is a variable of type CUMULATIVE_ARGS which gives info about
485 the preceding args and about the function being called.
486 NAMED is nonzero if this argument is a named parameter
487 (otherwise it is an extra parameter matching an ellipsis). */
489 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
490 function_arg (&CUM, MODE, TYPE, NAMED)
492 /* Implement `va_arg'. */
493 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
494 mn10200_va_arg (valist, type)
496 /* For "large" items, we pass them by invisible reference, and the
497 callee is responsible for copying the data item if it might be
499 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
500 ((TYPE) && int_size_in_bytes (TYPE) > 8)
502 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
503 ((TYPE) && int_size_in_bytes (TYPE) > 8)
505 /* Define how to find the value returned by a function.
506 VALTYPE is the data type of the value (as a tree).
507 If the precise function being called is known, FUNC is its FUNCTION_DECL;
508 otherwise, FUNC is 0. */
510 #define FUNCTION_VALUE(VALTYPE, FUNC) \
511 gen_rtx_REG (TYPE_MODE (VALTYPE), TYPE_MODE (VALTYPE) == PSImode ? 4 : 0)
513 /* Define how to find the value returned by a library function
514 assuming the value has mode MODE. */
516 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, (MODE) == PSImode ? 4 : 0)
518 /* 1 if N is a possible register number for a function value. */
520 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N) == 4)
522 /* Return values > 8 bytes in length in memory. */
523 #define DEFAULT_PCC_STRUCT_RETURN 0
524 #define RETURN_IN_MEMORY(TYPE) \
525 (int_size_in_bytes (TYPE) > 8 || TYPE_MODE (TYPE) == BLKmode)
527 /* Register in which address to store a structure value
528 is passed to a function. On the MN10200 it's passed as
529 the first parameter. */
531 #define STRUCT_VALUE 0
533 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
534 the stack pointer does not matter. The value is tested only in
535 functions that have frame pointers.
536 No definition is equivalent to always zero. */
538 #define EXIT_IGNORE_STACK 1
540 /* Output assembler code to FILE to increment profiler label # LABELNO
541 for profiling a function entry.
543 ?!? Profiling is not currently supported. */
545 #define FUNCTION_PROFILER(FILE, LABELNO) ;
547 /* Yes, we actually support trampolines on this machine, even though
548 nobody is likely to ever use them. */
549 #define TRAMPOLINE_TEMPLATE(FILE) \
551 fprintf (FILE, "\t.byte 0xfd\n"); \
552 fprintf (FILE, "\t.byte 0x00\n"); \
553 fprintf (FILE, "\t.byte 0x00\n"); \
554 fprintf (FILE, "\tmov (a3),a0\n"); \
555 fprintf (FILE, "\tadd -4,a3\n"); \
556 fprintf (FILE, "\tmov a0,(0,a3)\n"); \
557 fprintf (FILE, "\tmov (21,a0),a0\n"); \
558 fprintf (FILE, "\tmov a0,(4,a3)\n"); \
559 fprintf (FILE, "\tmov (0,a3),a0\n"); \
560 fprintf (FILE, "\tmov (17,a0),a0\n"); \
561 fprintf (FILE, "\tadd 4,a3\n"); \
562 fprintf (FILE, "\trts\n"); \
563 fprintf (FILE, "\t.long 0\n"); \
564 fprintf (FILE, "\t.long 0\n"); \
567 /* Length in units of the trampoline for entering a nested function. */
569 #define TRAMPOLINE_SIZE 0x1c
571 /* Emit RTL insns to initialize the variable parts of a trampoline.
572 FNADDR is an RTX for the address of the function's pure code.
573 CXT is an RTX for the static chain value for the function. */
575 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
577 emit_move_insn (gen_rtx_MEM (PSImode, plus_constant ((TRAMP), 20)), \
579 emit_move_insn (gen_rtx_MEM (PSImode, plus_constant ((TRAMP), 24)), \
583 /* A C expression whose value is RTL representing the value of the return
584 address for the frame COUNT steps up from the current frame. */
586 #define RETURN_ADDR_RTX(COUNT, FRAME) \
588 ? gen_rtx_MEM (Pmode, frame_pointer_rtx) \
592 /* Addressing modes, and classification of registers for them. */
595 /* 1 if X is an rtx for a constant that is a valid address. */
597 #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
599 /* Extra constraints. */
600 #define OK_FOR_R(OP) \
601 (GET_CODE (OP) == MEM \
602 && GET_MODE (OP) == QImode \
603 && REG_P (XEXP (OP, 0)))
605 /* Q is used for sp + <something> in the {zero,sign}_extendpsisi2 patterns. */
606 #define EXTRA_CONSTRAINT(OP, C) \
607 ((C) == 'R' ? OK_FOR_R (OP) : \
608 (C) == 'S' ? GET_CODE (OP) == SYMBOL_REF : \
609 (C) == 'Q' ? GET_CODE (OP) == PLUS : 0)
611 /* Maximum number of registers that can appear in a valid memory address. */
613 #define MAX_REGS_PER_ADDRESS 2
615 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
616 and check its validity for a certain class.
617 We have two alternate definitions for each of them.
618 The usual definition accepts all pseudo regs; the other rejects
619 them unless they have been allocated suitable hard regs.
620 The symbol REG_OK_STRICT causes the latter definition to be used.
622 Most source files want to accept pseudo regs in the hope that
623 they will get allocated to the class that the insn wants them to be in.
624 Source files for reload pass need to be strict.
625 After reload, it makes no difference, since pseudo regs have
626 been eliminated by then. */
628 #ifndef REG_OK_STRICT
629 /* Nonzero if X is a hard reg that can be used as an index
630 or if it is a pseudo reg. */
631 #define REG_OK_FOR_INDEX_P(X) \
632 (IN_RANGE (REGNO (X), 0, 3) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
633 /* Nonzero if X is a hard reg that can be used as a base reg
634 or if it is a pseudo reg. */
635 #define REG_OK_FOR_BASE_P(X) \
636 (((REGNO (X) >= 4 && REGNO(X) <= 8) || REGNO (X) >= FIRST_PSEUDO_REGISTER))
638 /* Nonzero if X is a hard reg that can be used as an index. */
639 #define REG_OK_FOR_INDEX_P(X) \
640 REGNO_OK_FOR_INDEX_P (REGNO (X))
641 /* Nonzero if X is a hard reg that can be used as a base reg. */
642 #define REG_OK_FOR_BASE_P(X) \
643 REGNO_OK_FOR_BASE_P (REGNO (X))
647 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
648 that is a valid memory address for an instruction.
649 The MODE argument is the machine mode for the MEM expression
650 that wants to use this address.
652 We used to allow reg+reg addresses for QImode and HImode; however,
653 they tended to cause the register allocator to run out of registers.
654 Basically, an indexed load/store always keeps 2 data and one address
655 register live, which is just too many for this machine.
657 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS,
658 except for CONSTANT_ADDRESS_P which is actually machine-independent. */
660 /* Accept either REG or SUBREG where a register is valid. */
662 #define RTX_OK_FOR_BASE_P(X) \
663 ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
664 || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \
665 && REG_OK_FOR_BASE_P (SUBREG_REG (X))))
667 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
669 if ((MODE != PSImode) && CONSTANT_ADDRESS_P (X)) \
671 if (RTX_OK_FOR_BASE_P (X)) \
673 if (GET_CODE (X) == PLUS) \
675 rtx base = 0, index = 0; \
676 if (RTX_OK_FOR_BASE_P (XEXP (X, 0))) \
677 base = XEXP (X, 0), index = XEXP (X, 1); \
678 if (RTX_OK_FOR_BASE_P (XEXP (X, 1))) \
679 base = XEXP (X, 1), index = XEXP (X, 0); \
680 if (base != 0 && index != 0) \
682 if (GET_CODE (index) == CONST_INT) \
689 /* Try machine-dependent ways of modifying an illegitimate address
690 to be legitimate. If we find one, return the new, valid address.
691 This macro is used in only one place: `memory_address' in explow.c.
693 OLDX is the address as it was before break_out_memory_refs was called.
694 In some cases it is useful to look at this to decide what needs to be done.
696 MODE and WIN are passed so that this macro can use
697 GO_IF_LEGITIMATE_ADDRESS.
699 It is always safe for this macro to do nothing. It exists to recognize
700 opportunities to optimize the output. */
702 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
704 /* Go to LABEL if ADDR (a legitimate address expression)
705 has an effect that depends on the machine mode it is used for. */
707 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
709 /* Nonzero if the constant value X is a legitimate general operand.
710 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
712 #define LEGITIMATE_CONSTANT_P(X) 1
715 /* Tell final.c how to eliminate redundant test instructions. */
717 /* Here we define machine-dependent flags and fields in cc_status
718 (see `conditions.h'). No extra ones are needed for the VAX. */
720 /* Store in cc_status the expressions
721 that the condition codes will describe
722 after execution of an instruction whose pattern is EXP.
723 Do not alter them if the instruction would not alter the cc's. */
725 #define CC_OVERFLOW_UNUSABLE 0x200
726 #define CC_NO_CARRY CC_NO_OVERFLOW
727 #define NOTICE_UPDATE_CC(EXP, INSN) notice_update_cc(EXP, INSN)
729 /* The mn10200 has a limited number of registers, so CSE of function
730 addresses generally makes code worse due to register pressure. */
731 #define NO_FUNCTION_CSE
733 /* Compute the cost of computing a constant rtl expression RTX
734 whose rtx-code is CODE. The body of this macro is a portion
735 of a switch statement. If the code is computed here,
736 return it with a return statement. Otherwise, break from the switch. */
738 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
740 /* Zeros are extremely cheap. */ \
741 if (INTVAL (RTX) == 0) \
743 /* If it fits in 8 bits, then it's still relatively cheap. */ \
744 if (INT_8_BITS (INTVAL (RTX))) \
746 /* This is the "base" cost, includes constants where either the \
747 upper or lower 16bits are all zeros. */ \
748 if (INT_16_BITS (INTVAL (RTX)) \
749 || (INTVAL (RTX) & 0xffff) == 0 \
750 || (INTVAL (RTX) & 0xffff0000) == 0) \
753 /* These are more costly than a CONST_INT, but we can relax them, \
754 so they're less costly than a CONST_DOUBLE. */ \
759 /* We don't optimize CONST_DOUBLEs well nor do we relax them well, \
760 so their cost is very high. */ \
764 /* Make moves between different classes more expensive than moves
765 within the same class. */
766 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) (CLASS1 != CLASS2 ? 4 : 2)
768 /* Provide the costs of a rtl expression. This is in the body of a
771 ?!? This probably needs more work. The definitions below were first
772 taken from the H8 port, then tweaked slightly to improve code density
773 on various sample codes. */
775 #define RTX_COSTS(RTX,CODE,OUTER_CODE) \
780 return (GET_MODE (RTX) == SImode ? 20 : 8);
782 /* Nonzero if access to memory by bytes or half words is no faster
783 than accessing full words. */
784 #define SLOW_BYTE_ACCESS 1
786 /* According expr.c, a value of around 6 should minimize code size, and
787 for the MN10200 series, code size our primary concern. */
790 #define TEXT_SECTION_ASM_OP "\t.section .text"
791 #define DATA_SECTION_ASM_OP "\t.section .data"
792 #define BSS_SECTION_ASM_OP "\t.section .bss"
794 /* Output at beginning/end of assembler file. */
795 #undef ASM_FILE_START
796 #define ASM_FILE_START(FILE) asm_file_start(FILE)
798 #define ASM_COMMENT_START "#"
800 /* Output to assembler file text saying following lines
801 may contain character constants, extra white space, comments, etc. */
803 #define ASM_APP_ON "#APP\n"
805 /* Output to assembler file text saying following lines
806 no longer contain unusual constructs. */
808 #define ASM_APP_OFF "#NO_APP\n"
810 /* This says how to output the assembler to define a global
811 uninitialized but not common symbol.
812 Try to use asm_output_bss to implement this macro. */
814 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
815 asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
817 /* This is how to output the definition of a user-level label named NAME,
818 such as the label on a static function or variable NAME. */
820 #define ASM_OUTPUT_LABEL(FILE, NAME) \
821 do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
823 /* This is how to output a command to make the user-level label named NAME
824 defined for reference from other files. */
826 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
827 do { fputs ("\t.global ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0)
829 /* This is how to output a reference to a user-level label named NAME.
830 `assemble_name' uses this. */
832 #undef ASM_OUTPUT_LABELREF
833 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
834 fprintf (FILE, "_%s", (*targetm.strip_name_encoding) (NAME))
836 /* Store in OUTPUT a string (made with alloca) containing
837 an assembler-name for a local static variable named NAME.
838 LABELNO is an integer which is different for each call. */
840 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
841 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
842 sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
844 /* This is how we tell the assembler that two symbols have the same value. */
846 #define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
847 do { assemble_name(FILE, NAME1); \
848 fputs(" = ", FILE); \
849 assemble_name(FILE, NAME2); \
850 fputc('\n', FILE); } while (0)
853 /* How to refer to registers in assembler output.
854 This sequence is indexed by compiler's hard-register-number (see above). */
856 #define REGISTER_NAMES \
857 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3"}
859 /* Print an instruction operand X on file FILE.
860 look in mn10200.c for details */
862 #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE,X,CODE)
864 /* Print a memory operand whose address is X, on file FILE.
865 This uses a function in output-vax.c. */
867 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
869 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO)
870 #define ASM_OUTPUT_REG_POP(FILE,REGNO)
872 /* This is how to output an element of a case-vector that is absolute. */
874 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
875 asm_fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
877 /* This is how to output an element of a case-vector that is relative. */
879 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
880 fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL)
882 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
884 fprintf (FILE, "\t.align %d\n", (LOG))
886 /* We don't have to worry about dbx compatibility for the mn10200. */
887 #define DEFAULT_GDB_EXTENSIONS 1
889 /* Use stabs debugging info by default. */
890 #undef PREFERRED_DEBUGGING_TYPE
891 #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
893 /* GDB always assumes the current function's frame begins at the value
894 of the stack pointer upon entry to the current function. Accessing
895 local variables and parameters passed on the stack is done using the
896 base of the frame + an offset provided by GCC.
898 For functions which have frame pointers this method works fine;
899 the (frame pointer) == (stack pointer at function entry) and GCC provides
900 an offset relative to the frame pointer.
902 This loses for functions without a frame pointer; GCC provides an offset
903 which is relative to the stack pointer after adjusting for the function's
904 frame size. GDB would prefer the offset to be relative to the value of
905 the stack pointer at the function's entry. Yuk! */
906 #define DEBUGGER_AUTO_OFFSET(X) \
907 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
908 + (frame_pointer_needed ? 0 : -total_frame_size ()))
910 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
911 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
912 + (frame_pointer_needed ? 0 : -total_frame_size ()))
914 /* Specify the machine mode that this machine uses
915 for the index in the tablejump instruction. */
916 #define CASE_VECTOR_MODE Pmode
918 /* Dispatch tables on the mn10200 are extremely expensive in terms of code
919 and readonly data size. So we crank up the case threshold value to
920 encourage a series of if/else comparisons to implement many small switch
921 statements. In theory, this value could be increased much more if we
922 were solely optimizing for space, but we keep it "reasonable" to avoid
923 serious code efficiency lossage. */
924 #define CASE_VALUES_THRESHOLD 8
926 /* Define if operations between registers always perform the operation
927 on the full register even if a narrower mode is specified. */
928 #define WORD_REGISTER_OPERATIONS
930 /* We could define this either way. Using ZERO_EXTEND for QImode makes slightly
931 fast and more compact code. */
932 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
934 /* This flag, if defined, says the same insns that convert to a signed fixnum
935 also convert validly to an unsigned one. */
936 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
938 /* Max number of bytes we can move from memory to memory
939 in one reasonably fast instruction. */
942 /* Define if shifts truncate the shift count
943 which implies one can omit a sign-extension or zero-extension
945 #define SHIFT_COUNT_TRUNCATED 1
947 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
948 is done just by pretending it is already truncated. */
949 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) (OUTPREC != 32)
951 /* Specify the machine mode that pointers have.
952 After generation of rtl, the compiler makes no further distinction
953 between pointers and any other objects of this machine mode. */
954 #define Pmode PSImode
956 /* A function address in a call instruction
957 is a byte address (for indexing purposes)
958 so give the MEM rtx a byte's mode. */
959 #define FUNCTION_MODE QImode
961 /* Perform target dependent optabs initialization. */
962 #define MODHI3_LIBCALL "__modhi3"
963 #define DIVHI3_LIBCALL "__divhi3"
965 #define INIT_TARGET_OPTABS \
967 sdiv_optab->handlers[(int) HImode].libfunc \
968 = init_one_libfunc (DIVHI3_LIBCALL); \
969 smod_optab->handlers[(int) HImode].libfunc \
970 = init_one_libfunc (MODHI3_LIBCALL); \
973 /* The assembler op to get a word. */
975 #define FILE_ASM_OP "\t.file\n"
977 #define PREDICATE_CODES \
978 {"call_address_operand", { SYMBOL_REF, REG }}, \
979 {"constant_memory_operand", { MEM }}, \
980 {"psimode_truncation_operand",{ PLUS, CONST_INT, CONST_DOUBLE, CONST, \
981 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM }},\
982 {"extendpsi_operand", { PLUS, CONST_INT, CONST_DOUBLE, CONST, \
983 SYMBOL_REF, LABEL_REF, SUBREG, REG, MEM }}, \
984 {"nshift_operator", { ASHIFTRT, LSHIFTRT, ASHIFT }},
986 extern struct rtx_def
*zero_dreg
;
987 extern struct rtx_def
*zero_areg
;