1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
45 #include "target-def.h"
47 /* This is used by GOTaddr2picreg to uniquely identify
49 int mn10300_unspec_int_label_counter
;
51 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
52 names are not prefixed by underscores, to tell whether to prefix a
53 label with a plus sign or not, so that the assembler can tell
54 symbol names from register names. */
55 int mn10300_protect_label
;
57 /* The size of the callee register save area. Right now we save everything
58 on entry since it costs us nothing in code size. It does cost us from a
59 speed standpoint, so we want to optimize this sooner or later. */
60 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
61 + 4 * regs_ever_live[3] \
62 + 4 * regs_ever_live[6] \
63 + 4 * regs_ever_live[7] \
64 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
65 || regs_ever_live[16] || regs_ever_live[17]))
68 static int mn10300_address_cost_1 (rtx
, int *);
69 static int mn10300_address_cost (rtx
);
70 static bool mn10300_rtx_costs (rtx
, int, int, int *);
71 static void mn10300_file_start (void);
72 static bool mn10300_return_in_memory (tree
, tree
);
73 static rtx
mn10300_builtin_saveregs (void);
76 /* Initialize the GCC target structure. */
77 #undef TARGET_ASM_ALIGNED_HI_OP
78 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
80 #undef TARGET_RTX_COSTS
81 #define TARGET_RTX_COSTS mn10300_rtx_costs
82 #undef TARGET_ADDRESS_COST
83 #define TARGET_ADDRESS_COST mn10300_address_cost
85 #undef TARGET_ASM_FILE_START
86 #define TARGET_ASM_FILE_START mn10300_file_start
87 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
88 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
90 #undef TARGET_ENCODE_SECTION_INFO
91 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
93 #undef TARGET_PROMOTE_PROTOTYPES
94 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
96 #undef TARGET_RETURN_IN_MEMORY
97 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
99 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
100 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
102 static void mn10300_encode_section_info (tree
, rtx
, int);
103 struct gcc_target targetm
= TARGET_INITIALIZER
;
106 mn10300_file_start (void)
108 default_file_start ();
111 fprintf (asm_out_file
, "\t.am33_2\n");
112 else if (TARGET_AM33
)
113 fprintf (asm_out_file
, "\t.am33\n");
117 /* Print operand X using operand code CODE to assembly language output file
121 print_operand (FILE *file
, rtx x
, int code
)
127 if (cc_status
.mdep
.fpCC
)
129 switch (code
== 'b' ? GET_CODE (x
)
130 : reverse_condition_maybe_unordered (GET_CODE (x
)))
133 fprintf (file
, "ne");
136 fprintf (file
, "eq");
139 fprintf (file
, "ge");
142 fprintf (file
, "gt");
145 fprintf (file
, "le");
148 fprintf (file
, "lt");
151 fprintf (file
, "lge");
154 fprintf (file
, "uo");
157 fprintf (file
, "lg");
160 fprintf (file
, "ue");
163 fprintf (file
, "uge");
166 fprintf (file
, "ug");
169 fprintf (file
, "ule");
172 fprintf (file
, "ul");
179 /* These are normal and reversed branches. */
180 switch (code
== 'b' ? GET_CODE (x
) : reverse_condition (GET_CODE (x
)))
183 fprintf (file
, "ne");
186 fprintf (file
, "eq");
189 fprintf (file
, "ge");
192 fprintf (file
, "gt");
195 fprintf (file
, "le");
198 fprintf (file
, "lt");
201 fprintf (file
, "cc");
204 fprintf (file
, "hi");
207 fprintf (file
, "ls");
210 fprintf (file
, "cs");
217 /* This is used for the operand to a call instruction;
218 if it's a REG, enclose it in parens, else output
219 the operand normally. */
220 if (GET_CODE (x
) == REG
)
223 print_operand (file
, x
, 0);
227 print_operand (file
, x
, 0);
231 switch (GET_CODE (x
))
235 output_address (XEXP (x
, 0));
240 fprintf (file
, "fd%d", REGNO (x
) - 18);
248 /* These are the least significant word in a 64bit value. */
250 switch (GET_CODE (x
))
254 output_address (XEXP (x
, 0));
259 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
263 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
271 switch (GET_MODE (x
))
274 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
275 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
276 fprintf (file
, "0x%lx", val
[0]);
279 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
280 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
[0]);
281 fprintf (file
, "0x%lx", val
[0]);
285 print_operand_address (file
,
286 GEN_INT (CONST_DOUBLE_LOW (x
)));
297 split_double (x
, &low
, &high
);
298 fprintf (file
, "%ld", (long)INTVAL (low
));
307 /* Similarly, but for the most significant word. */
309 switch (GET_CODE (x
))
313 x
= adjust_address (x
, SImode
, 4);
314 output_address (XEXP (x
, 0));
319 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
323 fprintf (file
, "%s", reg_names
[subreg_regno (x
) + 1]);
331 switch (GET_MODE (x
))
334 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
335 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
336 fprintf (file
, "0x%lx", val
[1]);
342 print_operand_address (file
,
343 GEN_INT (CONST_DOUBLE_HIGH (x
)));
354 split_double (x
, &low
, &high
);
355 fprintf (file
, "%ld", (long)INTVAL (high
));
366 if (GET_CODE (XEXP (x
, 0)) == REG
)
367 output_address (gen_rtx_PLUS (SImode
, XEXP (x
, 0), const0_rtx
));
369 output_address (XEXP (x
, 0));
374 if (INTVAL (x
) < -128 || INTVAL (x
) > 255)
376 fprintf (file
, "%d", (int)((~INTVAL (x
)) & 0xff));
380 if (INTVAL (x
) < -128 || INTVAL (x
) > 255)
382 fprintf (file
, "%d", (int)(INTVAL (x
) & 0xff));
385 /* For shift counts. The hardware ignores the upper bits of
386 any immediate, but the assembler will flag an out of range
387 shift count as an error. So we mask off the high bits
388 of the immediate here. */
390 if (GET_CODE (x
) == CONST_INT
)
392 fprintf (file
, "%d", (int)(INTVAL (x
) & 0x1f));
398 switch (GET_CODE (x
))
402 output_address (XEXP (x
, 0));
411 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
415 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
418 /* This will only be single precision.... */
424 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
425 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
426 fprintf (file
, "0x%lx", val
);
436 print_operand_address (file
, x
);
445 /* Output assembly language output for the address ADDR to FILE. */
448 print_operand_address (FILE *file
, rtx addr
)
450 switch (GET_CODE (addr
))
453 print_operand_address (file
, XEXP (addr
, 0));
457 print_operand (file
, addr
, 0);
462 if (REG_P (XEXP (addr
, 0))
463 && REG_OK_FOR_BASE_P (XEXP (addr
, 0)))
464 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
465 else if (REG_P (XEXP (addr
, 1))
466 && REG_OK_FOR_BASE_P (XEXP (addr
, 1)))
467 base
= XEXP (addr
, 1), index
= XEXP (addr
, 0);
470 print_operand (file
, index
, 0);
472 print_operand (file
, base
, 0);;
476 output_addr_const (file
, addr
);
479 output_addr_const (file
, addr
);
484 /* Count the number of FP registers that have to be saved. */
486 fp_regs_to_save (void)
493 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
494 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
500 /* Print a set of registers in the format required by "movm" and "ret".
501 Register K is saved if bit K of MASK is set. The data and address
502 registers can be stored individually, but the extended registers cannot.
503 We assume that the mask alread takes that into account. For instance,
504 bits 14 to 17 must have the same value. */
507 mn10300_print_reg_list (FILE *file
, int mask
)
515 for (i
= 0; i
< FIRST_EXTENDED_REGNUM
; i
++)
516 if ((mask
& (1 << i
)) != 0)
520 fputs (reg_names
[i
], file
);
524 if ((mask
& 0x3c000) != 0)
526 if ((mask
& 0x3c000) != 0x3c000)
530 fputs ("exreg1", file
);
538 can_use_return_insn (void)
540 /* size includes the fixed stack space needed for function calls. */
541 int size
= get_frame_size () + current_function_outgoing_args_size
;
543 /* And space for the return pointer. */
544 size
+= current_function_outgoing_args_size
? 4 : 0;
546 return (reload_completed
548 && !regs_ever_live
[2]
549 && !regs_ever_live
[3]
550 && !regs_ever_live
[6]
551 && !regs_ever_live
[7]
552 && !regs_ever_live
[14]
553 && !regs_ever_live
[15]
554 && !regs_ever_live
[16]
555 && !regs_ever_live
[17]
556 && fp_regs_to_save () == 0
557 && !frame_pointer_needed
);
560 /* Returns the set of live, callee-saved registers as a bitmask. The
561 callee-saved extended registers cannot be stored individually, so
562 all of them will be included in the mask if any one of them is used. */
565 mn10300_get_live_callee_saved_regs (void)
571 for (i
= 0; i
<= LAST_EXTENDED_REGNUM
; i
++)
572 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
574 if ((mask
& 0x3c000) != 0)
580 /* Generate an instruction that pushes several registers onto the stack.
581 Register K will be saved if bit K in MASK is set. The function does
582 nothing if MASK is zero.
584 To be compatible with the "movm" instruction, the lowest-numbered
585 register must be stored in the lowest slot. If MASK is the set
586 { R1,...,RN }, where R1...RN are ordered least first, the generated
587 instruction will have the form:
590 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
591 (set (mem:SI (plus:SI (reg:SI 9)
595 (set (mem:SI (plus:SI (reg:SI 9)
600 mn10300_gen_multiple_store (int mask
)
609 /* Count how many registers need to be saved. */
611 for (i
= 0; i
<= LAST_EXTENDED_REGNUM
; i
++)
612 if ((mask
& (1 << i
)) != 0)
615 /* We need one PARALLEL element to update the stack pointer and
616 an additional element for each register that is stored. */
617 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
+ 1));
619 /* Create the instruction that updates the stack pointer. */
621 = gen_rtx_SET (SImode
,
623 gen_rtx_PLUS (SImode
,
625 GEN_INT (-count
* 4)));
627 /* Create each store. */
629 for (i
= LAST_EXTENDED_REGNUM
; i
>= 0; i
--)
630 if ((mask
& (1 << i
)) != 0)
632 rtx address
= gen_rtx_PLUS (SImode
,
634 GEN_INT (-pari
* 4));
635 XVECEXP(par
, 0, pari
)
636 = gen_rtx_SET (VOIDmode
,
637 gen_rtx_MEM (SImode
, address
),
638 gen_rtx_REG (SImode
, i
));
642 par
= emit_insn (par
);
643 RTX_FRAME_RELATED_P (par
) = 1;
648 expand_prologue (void)
652 /* SIZE includes the fixed stack space needed for function calls. */
653 size
= get_frame_size () + current_function_outgoing_args_size
;
654 size
+= (current_function_outgoing_args_size
? 4 : 0);
656 /* If we use any of the callee-saved registers, save them now. */
657 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
659 if (TARGET_AM33_2
&& fp_regs_to_save ())
661 int num_regs_to_save
= fp_regs_to_save (), i
;
663 enum { save_sp_merge
,
665 save_sp_partial_merge
,
667 save_a0_no_merge
} strategy
;
668 unsigned int strategy_size
= (unsigned)-1, this_strategy_size
;
672 /* We have several different strategies to save FP registers.
673 We can store them using SP offsets, which is beneficial if
674 there are just a few registers to save, or we can use `a0' in
675 post-increment mode (`a0' is the only call-clobbered address
676 register that is never used to pass information to a
677 function). Furthermore, if we don't need a frame pointer, we
678 can merge the two SP adds into a single one, but this isn't
679 always beneficial; sometimes we can just split the two adds
680 so that we don't exceed a 16-bit constant size. The code
681 below will select which strategy to use, so as to generate
682 smallest code. Ties are broken in favor or shorter sequences
683 (in terms of number of instructions). */
685 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
686 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
687 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
688 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
689 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
690 (((S) >= (L)) ? (SIZE1) * (N) \
691 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
692 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
694 #define SIZE_FMOV_SP_(S,N) \
695 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
696 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
697 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
698 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
700 /* Consider alternative save_sp_merge only if we don't need the
701 frame pointer and size is nonzero. */
702 if (! frame_pointer_needed
&& size
)
704 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
705 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
706 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
707 this_strategy_size
+= SIZE_FMOV_SP (size
, num_regs_to_save
);
709 if (this_strategy_size
< strategy_size
)
711 strategy
= save_sp_merge
;
712 strategy_size
= this_strategy_size
;
716 /* Consider alternative save_sp_no_merge unconditionally. */
717 /* Insn: add -4 * num_regs_to_save, sp. */
718 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
719 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
720 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
723 /* Insn: add -size, sp. */
724 this_strategy_size
+= SIZE_ADD_SP (-size
);
727 if (this_strategy_size
< strategy_size
)
729 strategy
= save_sp_no_merge
;
730 strategy_size
= this_strategy_size
;
733 /* Consider alternative save_sp_partial_merge only if we don't
734 need a frame pointer and size is reasonably large. */
735 if (! frame_pointer_needed
&& size
+ 4 * num_regs_to_save
> 128)
737 /* Insn: add -128, sp. */
738 this_strategy_size
= SIZE_ADD_SP (-128);
739 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
740 this_strategy_size
+= SIZE_FMOV_SP (128 - 4 * num_regs_to_save
,
744 /* Insn: add 128-size, sp. */
745 this_strategy_size
+= SIZE_ADD_SP (128 - size
);
748 if (this_strategy_size
< strategy_size
)
750 strategy
= save_sp_partial_merge
;
751 strategy_size
= this_strategy_size
;
755 /* Consider alternative save_a0_merge only if we don't need a
756 frame pointer, size is nonzero and the user hasn't
757 changed the calling conventions of a0. */
758 if (! frame_pointer_needed
&& size
759 && call_used_regs
[FIRST_ADDRESS_REGNUM
]
760 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
762 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
763 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
764 /* Insn: mov sp, a0. */
765 this_strategy_size
++;
768 /* Insn: add size, a0. */
769 this_strategy_size
+= SIZE_ADD_AX (size
);
771 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
772 this_strategy_size
+= 3 * num_regs_to_save
;
774 if (this_strategy_size
< strategy_size
)
776 strategy
= save_a0_merge
;
777 strategy_size
= this_strategy_size
;
781 /* Consider alternative save_a0_no_merge if the user hasn't
782 changed the calling conventions of a0. */
783 if (call_used_regs
[FIRST_ADDRESS_REGNUM
]
784 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
786 /* Insn: add -4 * num_regs_to_save, sp. */
787 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
788 /* Insn: mov sp, a0. */
789 this_strategy_size
++;
790 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
791 this_strategy_size
+= 3 * num_regs_to_save
;
794 /* Insn: add -size, sp. */
795 this_strategy_size
+= SIZE_ADD_SP (-size
);
798 if (this_strategy_size
< strategy_size
)
800 strategy
= save_a0_no_merge
;
801 strategy_size
= this_strategy_size
;
805 /* Emit the initial SP add, common to all strategies. */
808 case save_sp_no_merge
:
809 case save_a0_no_merge
:
810 emit_insn (gen_addsi3 (stack_pointer_rtx
,
812 GEN_INT (-4 * num_regs_to_save
)));
816 case save_sp_partial_merge
:
817 emit_insn (gen_addsi3 (stack_pointer_rtx
,
820 xsize
= 128 - 4 * num_regs_to_save
;
826 emit_insn (gen_addsi3 (stack_pointer_rtx
,
828 GEN_INT (-(size
+ 4 * num_regs_to_save
))));
829 /* We'll have to adjust FP register saves according to the
832 /* Since we've already created the stack frame, don't do it
833 again at the end of the function. */
841 /* Now prepare register a0, if we have decided to use it. */
845 case save_sp_no_merge
:
846 case save_sp_partial_merge
:
851 case save_a0_no_merge
:
852 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
);
853 emit_insn (gen_movsi (reg
, stack_pointer_rtx
));
855 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (xsize
)));
856 reg
= gen_rtx_POST_INC (SImode
, reg
);
863 /* Now actually save the FP registers. */
864 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
865 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
873 /* If we aren't using `a0', use an SP offset. */
876 addr
= gen_rtx_PLUS (SImode
,
881 addr
= stack_pointer_rtx
;
886 insn
= emit_insn (gen_movsi (gen_rtx_MEM (SImode
, addr
),
887 gen_rtx_REG (SImode
, i
)));
889 RTX_FRAME_RELATED_P (insn
) = 1;
893 /* Now put the frame pointer into the frame pointer register. */
894 if (frame_pointer_needed
)
895 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
897 /* Allocate stack for this frame. */
899 emit_insn (gen_addsi3 (stack_pointer_rtx
,
902 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
904 rtx insn
= get_last_insn ();
905 rtx last
= emit_insn (gen_GOTaddr2picreg ());
907 /* Mark these insns as possibly dead. Sometimes, flow2 may
908 delete all uses of the PIC register. In this case, let it
909 delete the initialization too. */
912 insn
= NEXT_INSN (insn
);
914 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
918 while (insn
!= last
);
923 expand_epilogue (void)
927 /* SIZE includes the fixed stack space needed for function calls. */
928 size
= get_frame_size () + current_function_outgoing_args_size
;
929 size
+= (current_function_outgoing_args_size
? 4 : 0);
931 if (TARGET_AM33_2
&& fp_regs_to_save ())
933 int num_regs_to_save
= fp_regs_to_save (), i
;
936 /* We have several options to restore FP registers. We could
937 load them from SP offsets, but, if there are enough FP
938 registers to restore, we win if we use a post-increment
941 /* If we have a frame pointer, it's the best option, because we
942 already know it has the value we want. */
943 if (frame_pointer_needed
)
944 reg
= gen_rtx_REG (SImode
, FRAME_POINTER_REGNUM
);
945 /* Otherwise, we may use `a1', since it's call-clobbered and
946 it's never used for return values. But only do so if it's
947 smaller than using SP offsets. */
950 enum { restore_sp_post_adjust
,
951 restore_sp_pre_adjust
,
952 restore_sp_partial_adjust
,
953 restore_a1
} strategy
;
954 unsigned int this_strategy_size
, strategy_size
= (unsigned)-1;
956 /* Consider using sp offsets before adjusting sp. */
957 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
958 this_strategy_size
= SIZE_FMOV_SP (size
, num_regs_to_save
);
959 /* If size is too large, we'll have to adjust SP with an
961 if (size
+ 4 * num_regs_to_save
+ REG_SAVE_BYTES
> 255)
963 /* Insn: add size + 4 * num_regs_to_save, sp. */
964 this_strategy_size
+= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
);
966 /* If we don't have to restore any non-FP registers,
967 we'll be able to save one byte by using rets. */
968 if (! REG_SAVE_BYTES
)
969 this_strategy_size
--;
971 if (this_strategy_size
< strategy_size
)
973 strategy
= restore_sp_post_adjust
;
974 strategy_size
= this_strategy_size
;
977 /* Consider using sp offsets after adjusting sp. */
978 /* Insn: add size, sp. */
979 this_strategy_size
= SIZE_ADD_SP (size
);
980 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
981 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
982 /* We're going to use ret to release the FP registers
983 save area, so, no savings. */
985 if (this_strategy_size
< strategy_size
)
987 strategy
= restore_sp_pre_adjust
;
988 strategy_size
= this_strategy_size
;
991 /* Consider using sp offsets after partially adjusting sp.
992 When size is close to 32Kb, we may be able to adjust SP
993 with an imm16 add instruction while still using fmov
995 if (size
+ 4 * num_regs_to_save
+ REG_SAVE_BYTES
> 255)
997 /* Insn: add size + 4 * num_regs_to_save
998 + REG_SAVE_BYTES - 252,sp. */
999 this_strategy_size
= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
1000 + REG_SAVE_BYTES
- 252);
1001 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1002 this_strategy_size
+= SIZE_FMOV_SP (252 - REG_SAVE_BYTES
1003 - 4 * num_regs_to_save
,
1005 /* We're going to use ret to release the FP registers
1006 save area, so, no savings. */
1008 if (this_strategy_size
< strategy_size
)
1010 strategy
= restore_sp_partial_adjust
;
1011 strategy_size
= this_strategy_size
;
1015 /* Consider using a1 in post-increment mode, as long as the
1016 user hasn't changed the calling conventions of a1. */
1017 if (call_used_regs
[FIRST_ADDRESS_REGNUM
+1]
1018 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
+1])
1020 /* Insn: mov sp,a1. */
1021 this_strategy_size
= 1;
1024 /* Insn: add size,a1. */
1025 this_strategy_size
+= SIZE_ADD_AX (size
);
1027 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1028 this_strategy_size
+= 3 * num_regs_to_save
;
1029 /* If size is large enough, we may be able to save a
1031 if (size
+ 4 * num_regs_to_save
+ REG_SAVE_BYTES
> 255)
1033 /* Insn: mov a1,sp. */
1034 this_strategy_size
+= 2;
1036 /* If we don't have to restore any non-FP registers,
1037 we'll be able to save one byte by using rets. */
1038 if (! REG_SAVE_BYTES
)
1039 this_strategy_size
--;
1041 if (this_strategy_size
< strategy_size
)
1043 strategy
= restore_a1
;
1044 strategy_size
= this_strategy_size
;
1050 case restore_sp_post_adjust
:
1053 case restore_sp_pre_adjust
:
1054 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1060 case restore_sp_partial_adjust
:
1061 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1063 GEN_INT (size
+ 4 * num_regs_to_save
1064 + REG_SAVE_BYTES
- 252)));
1065 size
= 252 - REG_SAVE_BYTES
- 4 * num_regs_to_save
;
1069 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
+ 1);
1070 emit_insn (gen_movsi (reg
, stack_pointer_rtx
));
1072 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
1080 /* Adjust the selected register, if any, for post-increment. */
1082 reg
= gen_rtx_POST_INC (SImode
, reg
);
1084 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
1085 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
1093 /* If we aren't using a post-increment register, use an
1095 addr
= gen_rtx_PLUS (SImode
,
1100 addr
= stack_pointer_rtx
;
1104 emit_insn (gen_movsi (gen_rtx_REG (SImode
, i
),
1105 gen_rtx_MEM (SImode
, addr
)));
1108 /* If we were using the restore_a1 strategy and the number of
1109 bytes to be released won't fit in the `ret' byte, copy `a1'
1110 to `sp', to avoid having to use `add' to adjust it. */
1111 if (! frame_pointer_needed
&& reg
&& size
+ REG_SAVE_BYTES
> 255)
1113 emit_move_insn (stack_pointer_rtx
, XEXP (reg
, 0));
1118 /* Maybe cut back the stack, except for the register save area.
1120 If the frame pointer exists, then use the frame pointer to
1123 If the stack size + register save area is more than 255 bytes,
1124 then the stack must be cut back here since the size + register
1125 save size is too big for a ret/retf instruction.
1127 Else leave it alone, it will be cut back as part of the
1128 ret/retf instruction, or there wasn't any stack to begin with.
1130 Under no circumstances should the register save area be
1131 deallocated here, that would leave a window where an interrupt
1132 could occur and trash the register save area. */
1133 if (frame_pointer_needed
)
1135 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
1138 else if (size
+ REG_SAVE_BYTES
> 255)
1140 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1146 /* Adjust the stack and restore callee-saved registers, if any. */
1147 if (size
|| regs_ever_live
[2] || regs_ever_live
[3]
1148 || regs_ever_live
[6] || regs_ever_live
[7]
1149 || regs_ever_live
[14] || regs_ever_live
[15]
1150 || regs_ever_live
[16] || regs_ever_live
[17]
1151 || frame_pointer_needed
)
1152 emit_jump_insn (gen_return_internal_regs
1153 (GEN_INT (size
+ REG_SAVE_BYTES
)));
1155 emit_jump_insn (gen_return_internal ());
1158 /* Update the condition code from the insn. */
1161 notice_update_cc (rtx body
, rtx insn
)
1163 switch (get_attr_cc (insn
))
1166 /* Insn does not affect CC at all. */
1170 /* Insn does not change CC, but the 0'th operand has been changed. */
1171 if (cc_status
.value1
!= 0
1172 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
1173 cc_status
.value1
= 0;
1177 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1178 V,C are unusable. */
1180 cc_status
.flags
|= CC_NO_CARRY
| CC_OVERFLOW_UNUSABLE
;
1181 cc_status
.value1
= recog_data
.operand
[0];
1185 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1188 cc_status
.flags
|= CC_NO_CARRY
;
1189 cc_status
.value1
= recog_data
.operand
[0];
1193 /* The insn is a compare instruction. */
1195 cc_status
.value1
= SET_SRC (body
);
1196 if (GET_CODE (cc_status
.value1
) == COMPARE
1197 && GET_MODE (XEXP (cc_status
.value1
, 0)) == SFmode
)
1198 cc_status
.mdep
.fpCC
= 1;
1202 /* Insn doesn't leave CC in a usable state. */
1211 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1212 This function is for MATCH_PARALLEL and so assumes OP is known to be
1213 parallel. If OP is a multiple store, return a mask indicating which
1214 registers it saves. Return 0 otherwise. */
1217 store_multiple_operation (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1225 count
= XVECLEN (op
, 0);
1229 /* Check that first instruction has the form (set (sp) (plus A B)) */
1230 elt
= XVECEXP (op
, 0, 0);
1231 if (GET_CODE (elt
) != SET
1232 || GET_CODE (SET_DEST (elt
)) != REG
1233 || REGNO (SET_DEST (elt
)) != STACK_POINTER_REGNUM
1234 || GET_CODE (SET_SRC (elt
)) != PLUS
)
1237 /* Check that A is the stack pointer and B is the expected stack size.
1238 For OP to match, each subsequent instruction should push a word onto
1239 the stack. We therefore expect the first instruction to create
1240 COUNT-1 stack slots. */
1241 elt
= SET_SRC (elt
);
1242 if (GET_CODE (XEXP (elt
, 0)) != REG
1243 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1244 || GET_CODE (XEXP (elt
, 1)) != CONST_INT
1245 || INTVAL (XEXP (elt
, 1)) != -(count
- 1) * 4)
1248 /* Now go through the rest of the vector elements. They must be
1249 ordered so that the first instruction stores the highest-numbered
1250 register to the highest stack slot and that subsequent instructions
1251 store a lower-numbered register to the slot below.
1253 LAST keeps track of the smallest-numbered register stored so far.
1254 MASK is the set of stored registers. */
1255 last
= LAST_EXTENDED_REGNUM
+ 1;
1257 for (i
= 1; i
< count
; i
++)
1259 /* Check that element i is a (set (mem M) R) and that R is valid. */
1260 elt
= XVECEXP (op
, 0, i
);
1261 if (GET_CODE (elt
) != SET
1262 || GET_CODE (SET_DEST (elt
)) != MEM
1263 || GET_CODE (SET_SRC (elt
)) != REG
1264 || REGNO (SET_SRC (elt
)) >= last
)
1267 /* R was OK, so provisionally add it to MASK. We return 0 in any
1268 case if the rest of the instruction has a flaw. */
1269 last
= REGNO (SET_SRC (elt
));
1270 mask
|= (1 << last
);
1272 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1273 elt
= XEXP (SET_DEST (elt
), 0);
1274 if (GET_CODE (elt
) != PLUS
1275 || GET_CODE (XEXP (elt
, 0)) != REG
1276 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1277 || GET_CODE (XEXP (elt
, 1)) != CONST_INT
1278 || INTVAL (XEXP (elt
, 1)) != -i
* 4)
1282 /* All or none of the callee-saved extended registers must be in the set. */
1283 if ((mask
& 0x3c000) != 0
1284 && (mask
& 0x3c000) != 0x3c000)
1290 /* Return true if OP is a valid call operand. */
1293 call_address_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1296 return (EXTRA_CONSTRAINT (op
, 'S') || GET_CODE (op
) == REG
);
1298 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == REG
);
1301 /* What (if any) secondary registers are needed to move IN with mode
1302 MODE into a register in register class CLASS.
1304 We might be able to simplify this. */
1306 secondary_reload_class (enum reg_class
class, enum machine_mode mode
, rtx in
)
1308 /* Memory loads less than a full word wide can't have an
1309 address or stack pointer destination. They must use
1310 a data register as an intermediate register. */
1311 if ((GET_CODE (in
) == MEM
1312 || (GET_CODE (in
) == REG
1313 && REGNO (in
) >= FIRST_PSEUDO_REGISTER
)
1314 || (GET_CODE (in
) == SUBREG
1315 && GET_CODE (SUBREG_REG (in
)) == REG
1316 && REGNO (SUBREG_REG (in
)) >= FIRST_PSEUDO_REGISTER
))
1317 && (mode
== QImode
|| mode
== HImode
)
1318 && (class == ADDRESS_REGS
|| class == SP_REGS
1319 || class == SP_OR_ADDRESS_REGS
))
1322 return DATA_OR_EXTENDED_REGS
;
1326 /* We can't directly load sp + const_int into a data register;
1327 we must use an address register as an intermediate. */
1328 if (class != SP_REGS
1329 && class != ADDRESS_REGS
1330 && class != SP_OR_ADDRESS_REGS
1331 && class != SP_OR_EXTENDED_REGS
1332 && class != ADDRESS_OR_EXTENDED_REGS
1333 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
1334 && (in
== stack_pointer_rtx
1335 || (GET_CODE (in
) == PLUS
1336 && (XEXP (in
, 0) == stack_pointer_rtx
1337 || XEXP (in
, 1) == stack_pointer_rtx
))))
1338 return ADDRESS_REGS
;
1340 if (GET_CODE (in
) == PLUS
1341 && (XEXP (in
, 0) == stack_pointer_rtx
1342 || XEXP (in
, 1) == stack_pointer_rtx
))
1345 return DATA_OR_EXTENDED_REGS
;
1349 if (TARGET_AM33_2
&& class == FP_REGS
1350 && GET_CODE (in
) == MEM
&& ! OK_FOR_Q (in
))
1353 return DATA_OR_EXTENDED_REGS
;
1357 /* Otherwise assume no secondary reloads are needed. */
1362 initial_offset (int from
, int to
)
1364 /* The difference between the argument pointer and the frame pointer
1365 is the size of the callee register save area. */
1366 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1368 if (regs_ever_live
[2] || regs_ever_live
[3]
1369 || regs_ever_live
[6] || regs_ever_live
[7]
1370 || regs_ever_live
[14] || regs_ever_live
[15]
1371 || regs_ever_live
[16] || regs_ever_live
[17]
1372 || fp_regs_to_save ()
1373 || frame_pointer_needed
)
1374 return REG_SAVE_BYTES
1375 + 4 * fp_regs_to_save ();
1380 /* The difference between the argument pointer and the stack pointer is
1381 the sum of the size of this function's frame, the callee register save
1382 area, and the fixed stack space needed for function calls (if any). */
1383 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1385 if (regs_ever_live
[2] || regs_ever_live
[3]
1386 || regs_ever_live
[6] || regs_ever_live
[7]
1387 || regs_ever_live
[14] || regs_ever_live
[15]
1388 || regs_ever_live
[16] || regs_ever_live
[17]
1389 || fp_regs_to_save ()
1390 || frame_pointer_needed
)
1391 return (get_frame_size () + REG_SAVE_BYTES
1392 + 4 * fp_regs_to_save ()
1393 + (current_function_outgoing_args_size
1394 ? current_function_outgoing_args_size
+ 4 : 0));
1396 return (get_frame_size ()
1397 + (current_function_outgoing_args_size
1398 ? current_function_outgoing_args_size
+ 4 : 0));
1401 /* The difference between the frame pointer and stack pointer is the sum
1402 of the size of this function's frame and the fixed stack space needed
1403 for function calls (if any). */
1404 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1405 return (get_frame_size ()
1406 + (current_function_outgoing_args_size
1407 ? current_function_outgoing_args_size
+ 4 : 0));
1412 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1415 mn10300_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
1417 /* Return values > 8 bytes in length in memory. */
1418 return int_size_in_bytes (type
) > 8 || TYPE_MODE (type
) == BLKmode
;
1421 /* Flush the argument registers to the stack for a stdarg function;
1422 return the new argument pointer. */
1424 mn10300_builtin_saveregs (void)
1427 tree fntype
= TREE_TYPE (current_function_decl
);
1428 int argadj
= ((!(TYPE_ARG_TYPES (fntype
) != 0
1429 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
1430 != void_type_node
)))
1431 ? UNITS_PER_WORD
: 0);
1432 int set
= get_varargs_alias_set ();
1435 offset
= plus_constant (current_function_arg_offset_rtx
, argadj
);
1437 offset
= current_function_arg_offset_rtx
;
1439 mem
= gen_rtx_MEM (SImode
, current_function_internal_arg_pointer
);
1440 set_mem_alias_set (mem
, set
);
1441 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
1443 mem
= gen_rtx_MEM (SImode
,
1444 plus_constant (current_function_internal_arg_pointer
, 4));
1445 set_mem_alias_set (mem
, set
);
1446 emit_move_insn (mem
, gen_rtx_REG (SImode
, 1));
1448 return copy_to_reg (expand_binop (Pmode
, add_optab
,
1449 current_function_internal_arg_pointer
,
1450 offset
, 0, 0, OPTAB_LIB_WIDEN
));
1454 mn10300_va_start (tree valist
, rtx nextarg
)
1456 nextarg
= expand_builtin_saveregs ();
1457 std_expand_builtin_va_start (valist
, nextarg
);
1461 mn10300_va_arg (tree valist
, tree type
)
1463 HOST_WIDE_INT align
, rsize
;
1466 /* Compute the rounded size of the type. */
1467 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
1468 rsize
= (((int_size_in_bytes (type
) + align
- 1) / align
) * align
);
1470 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (valist
), valist
,
1471 build_int_2 ((rsize
> 8 ? 4 : rsize
), 0));
1472 TREE_SIDE_EFFECTS (t
) = 1;
1474 ptr
= build_pointer_type (type
);
1476 /* "Large" types are passed by reference. */
1479 pptr
= build_pointer_type (ptr
);
1480 t
= build1 (NOP_EXPR
, pptr
, t
);
1481 TREE_SIDE_EFFECTS (t
) = 1;
1483 t
= build1 (INDIRECT_REF
, ptr
, t
);
1484 TREE_SIDE_EFFECTS (t
) = 1;
1488 t
= build1 (NOP_EXPR
, ptr
, t
);
1489 TREE_SIDE_EFFECTS (t
) = 1;
1493 return expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
1496 /* Return an RTX to represent where a value with mode MODE will be returned
1497 from a function. If the result is 0, the argument is pushed. */
1500 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1501 tree type
, int named ATTRIBUTE_UNUSED
)
1506 /* We only support using 2 data registers as argument registers. */
1509 /* Figure out the size of the object to be passed. */
1510 if (mode
== BLKmode
)
1511 size
= int_size_in_bytes (type
);
1513 size
= GET_MODE_SIZE (mode
);
1515 /* Figure out the alignment of the object to be passed. */
1518 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1520 /* Don't pass this arg via a register if all the argument registers
1522 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1525 /* Don't pass this arg via a register if it would be split between
1526 registers and memory. */
1527 if (type
== NULL_TREE
1528 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1531 switch (cum
->nbytes
/ UNITS_PER_WORD
)
1534 result
= gen_rtx_REG (mode
, 0);
1537 result
= gen_rtx_REG (mode
, 1);
1546 /* Return the number of registers to use for an argument passed partially
1547 in registers and partially in memory. */
1550 function_arg_partial_nregs (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
1551 tree type
, int named ATTRIBUTE_UNUSED
)
1555 /* We only support using 2 data registers as argument registers. */
1558 /* Figure out the size of the object to be passed. */
1559 if (mode
== BLKmode
)
1560 size
= int_size_in_bytes (type
);
1562 size
= GET_MODE_SIZE (mode
);
1564 /* Figure out the alignment of the object to be passed. */
1567 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1569 /* Don't pass this arg via a register if all the argument registers
1571 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1574 if (cum
->nbytes
+ size
<= nregs
* UNITS_PER_WORD
)
1577 /* Don't pass this arg via a register if it would be split between
1578 registers and memory. */
1579 if (type
== NULL_TREE
1580 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1583 return (nregs
* UNITS_PER_WORD
- cum
->nbytes
) / UNITS_PER_WORD
;
1586 /* Output a tst insn. */
1588 output_tst (rtx operand
, rtx insn
)
1593 /* We can save a byte if we can find a register which has the value
1595 temp
= PREV_INSN (insn
);
1596 while (optimize
&& temp
)
1600 /* We allow the search to go through call insns. We record
1601 the fact that we've past a CALL_INSN and reject matches which
1602 use call clobbered registers. */
1603 if (GET_CODE (temp
) == CODE_LABEL
1604 || GET_CODE (temp
) == JUMP_INSN
1605 || GET_CODE (temp
) == BARRIER
)
1608 if (GET_CODE (temp
) == CALL_INSN
)
1611 if (GET_CODE (temp
) == NOTE
)
1613 temp
= PREV_INSN (temp
);
1617 /* It must be an insn, see if it is a simple set. */
1618 set
= single_set (temp
);
1621 temp
= PREV_INSN (temp
);
1625 /* Are we setting a data register to zero (this does not win for
1628 If it's a call clobbered register, have we past a call?
1630 Make sure the register we find isn't the same as ourself;
1631 the mn10300 can't encode that.
1633 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1634 so the code to detect calls here isn't doing anything useful. */
1635 if (REG_P (SET_DEST (set
))
1636 && SET_SRC (set
) == CONST0_RTX (GET_MODE (SET_DEST (set
)))
1637 && !reg_set_between_p (SET_DEST (set
), temp
, insn
)
1638 && (REGNO_REG_CLASS (REGNO (SET_DEST (set
)))
1639 == REGNO_REG_CLASS (REGNO (operand
)))
1640 && REGNO_REG_CLASS (REGNO (SET_DEST (set
))) != EXTENDED_REGS
1641 && REGNO (SET_DEST (set
)) != REGNO (operand
)
1643 || !call_used_regs
[REGNO (SET_DEST (set
))]))
1646 xoperands
[0] = operand
;
1647 xoperands
[1] = SET_DEST (set
);
1649 output_asm_insn ("cmp %1,%0", xoperands
);
1653 if (REGNO_REG_CLASS (REGNO (operand
)) == EXTENDED_REGS
1654 && REG_P (SET_DEST (set
))
1655 && SET_SRC (set
) == CONST0_RTX (GET_MODE (SET_DEST (set
)))
1656 && !reg_set_between_p (SET_DEST (set
), temp
, insn
)
1657 && (REGNO_REG_CLASS (REGNO (SET_DEST (set
)))
1658 != REGNO_REG_CLASS (REGNO (operand
)))
1659 && REGNO_REG_CLASS (REGNO (SET_DEST (set
))) == EXTENDED_REGS
1660 && REGNO (SET_DEST (set
)) != REGNO (operand
)
1662 || !call_used_regs
[REGNO (SET_DEST (set
))]))
1665 xoperands
[0] = operand
;
1666 xoperands
[1] = SET_DEST (set
);
1668 output_asm_insn ("cmp %1,%0", xoperands
);
1671 temp
= PREV_INSN (temp
);
1677 impossible_plus_operand (rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1679 if (GET_CODE (op
) != PLUS
)
1682 if (XEXP (op
, 0) == stack_pointer_rtx
1683 || XEXP (op
, 1) == stack_pointer_rtx
)
1689 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1690 for the btst insn which may examine memory or a register (the memory
1691 variant only allows an unsigned 8 bit integer). */
1693 const_8bit_operand (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1695 return (GET_CODE (op
) == CONST_INT
1697 && INTVAL (op
) < 256);
1700 /* Return true if the operand is the 1.0f constant. */
1702 const_1f_operand (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1704 return (op
== CONST1_RTX (SFmode
));
1707 /* Similarly, but when using a zero_extract pattern for a btst where
1708 the source operand might end up in memory. */
1710 mask_ok_for_mem_btst (int len
, int bit
)
1712 unsigned int mask
= 0;
1721 /* MASK must bit into an 8bit value. */
1722 return (((mask
& 0xff) == mask
)
1723 || ((mask
& 0xff00) == mask
)
1724 || ((mask
& 0xff0000) == mask
)
1725 || ((mask
& 0xff000000) == mask
));
1728 /* Return 1 if X contains a symbolic expression. We know these
1729 expressions will have one of a few well defined forms, so
1730 we need only check those forms. */
1732 symbolic_operand (register rtx op
, enum machine_mode mode ATTRIBUTE_UNUSED
)
1734 switch (GET_CODE (op
))
1741 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1742 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1743 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
1749 /* Try machine dependent ways of modifying an illegitimate address
1750 to be legitimate. If we find one, return the new valid address.
1751 This macro is used in only one place: `memory_address' in explow.c.
1753 OLDX is the address as it was before break_out_memory_refs was called.
1754 In some cases it is useful to look at this to decide what needs to be done.
1756 MODE and WIN are passed so that this macro can use
1757 GO_IF_LEGITIMATE_ADDRESS.
1759 Normally it is always safe for this macro to do nothing. It exists to
1760 recognize opportunities to optimize the output.
1762 But on a few ports with segmented architectures and indexed addressing
1763 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1765 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1766 enum machine_mode mode ATTRIBUTE_UNUSED
)
1768 if (flag_pic
&& ! legitimate_pic_operand_p (x
))
1769 x
= legitimize_pic_address (oldx
, NULL_RTX
);
1771 /* Uh-oh. We might have an address for x[n-100000]. This needs
1772 special handling to avoid creating an indexed memory address
1773 with x-100000 as the base. */
1774 if (GET_CODE (x
) == PLUS
1775 && symbolic_operand (XEXP (x
, 1), VOIDmode
))
1777 /* Ugly. We modify things here so that the address offset specified
1778 by the index expression is computed first, then added to x to form
1779 the entire address. */
1781 rtx regx1
, regy1
, regy2
, y
;
1783 /* Strip off any CONST. */
1785 if (GET_CODE (y
) == CONST
)
1788 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1790 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1791 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1792 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1793 regx1
= force_reg (Pmode
,
1794 gen_rtx_fmt_ee (GET_CODE (y
), Pmode
, regx1
, regy2
));
1795 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1801 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1802 @GOTOFF in `reg'. */
1804 legitimize_pic_address (rtx orig
, rtx reg
)
1806 if (GET_CODE (orig
) == LABEL_REF
1807 || (GET_CODE (orig
) == SYMBOL_REF
1808 && (CONSTANT_POOL_ADDRESS_P (orig
)
1809 || ! MN10300_GLOBAL_P (orig
))))
1812 reg
= gen_reg_rtx (Pmode
);
1814 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
1817 else if (GET_CODE (orig
) == SYMBOL_REF
)
1820 reg
= gen_reg_rtx (Pmode
);
1822 emit_insn (gen_symGOT2reg (reg
, orig
));
1828 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1829 isn't protected by a PIC unspec; nonzero otherwise. */
1831 legitimate_pic_operand_p (rtx x
)
1833 register const char *fmt
;
1836 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1839 if (GET_CODE (x
) == UNSPEC
1840 && (XINT (x
, 1) == UNSPEC_PIC
1841 || XINT (x
, 1) == UNSPEC_GOT
1842 || XINT (x
, 1) == UNSPEC_GOTOFF
1843 || XINT (x
, 1) == UNSPEC_PLT
))
1846 if (GET_CODE (x
) == QUEUED
)
1847 return legitimate_pic_operand_p (QUEUED_VAR (x
));
1849 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
1850 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
1856 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1857 if (! legitimate_pic_operand_p (XVECEXP (x
, i
, j
)))
1860 else if (fmt
[i
] == 'e' && ! legitimate_pic_operand_p (XEXP (x
, i
)))
1867 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1868 legitimate, and FALSE otherwise. */
1870 legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1872 if (CONSTANT_ADDRESS_P (x
)
1873 && (! flag_pic
|| legitimate_pic_operand_p (x
)))
1876 if (RTX_OK_FOR_BASE_P (x
, strict
))
1880 && GET_CODE (x
) == POST_INC
1881 && RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
)
1882 && (mode
== SImode
|| mode
== SFmode
|| mode
== HImode
))
1885 if (GET_CODE (x
) == PLUS
)
1887 rtx base
= 0, index
= 0;
1889 if (REG_P (XEXP (x
, 0))
1890 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x
, 0)), strict
))
1893 index
= XEXP (x
, 1);
1896 if (REG_P (XEXP (x
, 1))
1897 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x
, 1)), strict
))
1900 index
= XEXP (x
, 0);
1903 if (base
!= 0 && index
!= 0)
1905 if (GET_CODE (index
) == CONST_INT
)
1907 if (GET_CODE (index
) == CONST
1909 || legitimate_pic_operand_p (index
)))
1918 mn10300_address_cost_1 (rtx x
, int *unsig
)
1920 switch (GET_CODE (x
))
1923 switch (REGNO_REG_CLASS (REGNO (x
)))
1949 return (mn10300_address_cost_1 (XEXP (x
, 0), unsig
)
1950 + mn10300_address_cost_1 (XEXP (x
, 1), unsig
));
1955 return mn10300_address_cost (XEXP (x
, 0));
1959 return mn10300_address_cost_1 (XEXP (x
, 0), unsig
);
1962 if (INTVAL (x
) == 0)
1964 if (INTVAL (x
) + (*unsig
? 0 : 0x80) < 0x100)
1966 if (INTVAL (x
) + (*unsig
? 0 : 0x8000) < 0x10000)
1968 if (INTVAL (x
) + (*unsig
? 0 : 0x800000) < 0x1000000)
1978 switch (GET_CODE (XEXP (x
, 0)))
1981 return mn10300_address_cost (XEXP (x
, 0));
1997 mn10300_address_cost (rtx x
)
2000 return mn10300_address_cost_1 (x
, &s
);
2004 mn10300_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2009 /* Zeros are extremely cheap. */
2010 if (INTVAL (x
) == 0 && outer_code
== SET
)
2012 /* If it fits in 8 bits, then it's still relatively cheap. */
2013 else if (INT_8_BITS (INTVAL (x
)))
2015 /* This is the "base" cost, includes constants where either the
2016 upper or lower 16bits are all zeros. */
2017 else if (INT_16_BITS (INTVAL (x
))
2018 || (INTVAL (x
) & 0xffff) == 0
2019 || (INTVAL (x
) & 0xffff0000) == 0)
2028 /* These are more costly than a CONST_INT, but we can relax them,
2029 so they're less costly than a CONST_DOUBLE. */
2034 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
2035 so their cost is very high. */
2039 /* ??? This probably needs more work. */
2051 /* Check whether a constant used to initialize a DImode or DFmode can
2052 use a clr instruction. The code here must be kept in sync with
2056 mn10300_wide_const_load_uses_clr (rtx operands
[2])
2060 if (GET_CODE (operands
[0]) != REG
2061 || REGNO_REG_CLASS (REGNO (operands
[0])) != DATA_REGS
)
2064 switch (GET_CODE (operands
[1]))
2069 split_double (operands
[1], &low
, &high
);
2070 val
[0] = INTVAL (low
);
2071 val
[1] = INTVAL (high
);
2076 if (GET_MODE (operands
[1]) == DFmode
)
2080 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operands
[1]);
2081 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
2083 else if (GET_MODE (operands
[1]) == VOIDmode
2084 || GET_MODE (operands
[1]) == DImode
)
2086 val
[0] = CONST_DOUBLE_LOW (operands
[1]);
2087 val
[1] = CONST_DOUBLE_HIGH (operands
[1]);
2095 return val
[0] == 0 || val
[1] == 0;
2097 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2098 may access it using GOTOFF instead of GOT. */
2101 mn10300_encode_section_info (tree decl
, rtx rtl
, int first ATTRIBUTE_UNUSED
)
2105 if (GET_CODE (rtl
) != MEM
)
2107 symbol
= XEXP (rtl
, 0);
2108 if (GET_CODE (symbol
) != SYMBOL_REF
)
2112 SYMBOL_REF_FLAG (symbol
) = (*targetm
.binds_local_p
) (decl
);