1 /* Definitions of target machine for GNU compiler.
2 Matsushita MN10300 series
3 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
4 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 Contributed by Jeff Law (law@cygnus.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
27 #define LINK_SPEC "%{mrelax:--relax}"
29 #define STARTFILE_SPEC "%{!mno-crt0:%{!shared:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}"
31 /* Names to predefine in the preprocessor for this target machine. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 builtin_define ("__mn10300__"); \
37 builtin_define ("__MN10300__"); \
38 builtin_assert ("cpu=mn10300"); \
39 builtin_assert ("machine=mn10300"); \
43 builtin_define ("__AM33__=4"); \
44 builtin_define ("__AM34__"); \
46 else if (TARGET_AM33_2) \
48 builtin_define ("__AM33__=2"); \
49 builtin_define ("__AM33_2__"); \
51 else if (TARGET_AM33) \
52 builtin_define ("__AM33__=1"); \
54 builtin_define (TARGET_ALLOW_LIW ? \
55 "__LIW__" : "__NO_LIW__");\
60 #ifndef MN10300_OPTS_H
61 #include "config/mn10300/mn10300-opts.h"
64 extern enum processor_type mn10300_tune_cpu
;
66 #define TARGET_AM33 (mn10300_processor >= PROCESSOR_AM33)
67 #define TARGET_AM33_2 (mn10300_processor >= PROCESSOR_AM33_2)
68 #define TARGET_AM34 (mn10300_processor >= PROCESSOR_AM34)
70 #ifndef PROCESSOR_DEFAULT
71 #define PROCESSOR_DEFAULT PROCESSOR_MN10300
75 /* Target machine storage layout */
77 /* Define this if most significant bit is lowest numbered
78 in instructions that operate on numbered bit-fields.
79 This is not true on the Matsushita MN1003. */
80 #define BITS_BIG_ENDIAN 0
82 /* Define this if most significant byte of a word is the lowest numbered. */
83 /* This is not true on the Matsushita MN10300. */
84 #define BYTES_BIG_ENDIAN 0
86 /* Define this if most significant word of a multiword number is lowest
88 This is not true on the Matsushita MN10300. */
89 #define WORDS_BIG_ENDIAN 0
91 /* Width of a word, in units (bytes). */
92 #define UNITS_PER_WORD 4
94 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
95 #define PARM_BOUNDARY 32
97 /* The stack goes in 32-bit lumps. */
98 #define STACK_BOUNDARY 32
100 /* Allocation boundary (in *bits*) for the code of a function.
101 8 is the minimum boundary; it's unclear if bigger alignments
102 would improve performance. */
103 #define FUNCTION_BOUNDARY 8
105 /* No data type wants to be aligned rounder than this. */
106 #define BIGGEST_ALIGNMENT 32
108 /* Alignment of field after `int : 0' in a structure. */
109 #define EMPTY_FIELD_BOUNDARY 32
111 /* Define this if move instructions will actually fail to work
112 when given unaligned data. */
113 #define STRICT_ALIGNMENT 1
115 /* Define this as 1 if `char' should by default be signed; else as 0. */
116 #define DEFAULT_SIGNED_CHAR 0
119 #define SIZE_TYPE "unsigned int"
122 #define PTRDIFF_TYPE "int"
125 #define WCHAR_TYPE "long int"
127 #undef WCHAR_TYPE_SIZE
128 #define WCHAR_TYPE_SIZE BITS_PER_WORD
130 /* Standard register usage. */
132 /* Number of actual hardware registers.
133 The hardware registers are assigned numbers for the compiler
134 from 0 to just below FIRST_PSEUDO_REGISTER.
136 All registers that the compiler knows about must be given numbers,
137 even those that are not normally considered general registers. */
139 #define FIRST_PSEUDO_REGISTER 52
141 /* Specify machine-specific register numbers. The commented out entries
142 are defined in mn10300.md. */
143 #define FIRST_DATA_REGNUM 0
144 #define LAST_DATA_REGNUM 3
145 #define FIRST_ADDRESS_REGNUM 4
146 /* #define PIC_REG 6 */
147 #define LAST_ADDRESS_REGNUM 8
148 /* #define SP_REG 9 */
149 #define FIRST_EXTENDED_REGNUM 10
150 #define LAST_EXTENDED_REGNUM 17
151 #define FIRST_FP_REGNUM 18
152 #define LAST_FP_REGNUM 49
153 /* #define MDR_REG 50 */
154 /* #define CC_REG 51 */
155 #define FIRST_ARGUMENT_REGNUM 0
157 /* Specify the registers used for certain standard purposes.
158 The values of these macros are register numbers. */
160 /* Register to use for pushing function arguments. */
161 #define STACK_POINTER_REGNUM (LAST_ADDRESS_REGNUM + 1)
163 /* Base register for access to local variables of the function. */
164 #define FRAME_POINTER_REGNUM (LAST_ADDRESS_REGNUM - 1)
166 /* Base register for access to arguments of the function. This
167 is a fake register and will be eliminated into either the frame
168 pointer or stack pointer. */
169 #define ARG_POINTER_REGNUM LAST_ADDRESS_REGNUM
171 /* Register in which static-chain is passed to a function. */
172 #define STATIC_CHAIN_REGNUM (FIRST_ADDRESS_REGNUM + 1)
174 /* 1 for registers that have pervasive standard uses
175 and are not available for the register allocator. */
177 #define FIXED_REGISTERS \
178 { 0, 0, 0, 0, /* data regs */ \
179 0, 0, 0, 0, /* addr regs */ \
182 0, 0, 0, 0, 0, 0, 0, 0, /* extended regs */ \
183 0, 0, /* fp regs (18-19) */ \
184 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \
185 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (30-39) */ \
186 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (40-49) */ \
191 /* 1 for registers not available across function calls.
192 These must include the FIXED_REGISTERS and also any
193 registers that can be used without being saved.
194 The latter must include the registers where values are returned
195 and the register where structure-value addresses are passed.
196 Aside from that, you can include as many other registers as you
199 #define CALL_USED_REGISTERS \
200 { 1, 1, 0, 0, /* data regs */ \
201 1, 1, 0, 0, /* addr regs */ \
204 1, 1, 1, 1, 0, 0, 0, 0, /* extended regs */ \
205 1, 1, /* fp regs (18-19) */ \
206 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, /* fp regs (20-29) */ \
207 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, /* fp regs (30-39) */ \
208 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, /* fp regs (40-49) */ \
213 /* Note: The definition of CALL_REALLY_USED_REGISTERS is not
214 redundant. It is needed when compiling in PIC mode because
215 the a2 register becomes fixed (and hence must be marked as
216 call_used) but in order to preserve the ABI it is not marked
217 as call_really_used. */
218 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS
220 #define REG_ALLOC_ORDER \
221 { 0, 1, 4, 5, 2, 3, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 8, 9 \
222 , 42, 43, 44, 45, 46, 47, 48, 49, 34, 35, 36, 37, 38, 39, 40, 41 \
223 , 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 50, 51 \
226 /* Return number of consecutive hard regs needed starting at reg REGNO
227 to hold something of mode MODE.
229 This is ordinarily the length in words of a value of mode MODE
230 but can be less for certain modes in special long registers. */
232 #define HARD_REGNO_NREGS(REGNO, MODE) \
233 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
235 /* Value is 1 if hard register REGNO can hold a value of machine-mode
237 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
238 mn10300_hard_regno_mode_ok ((REGNO), (MODE))
240 /* Value is 1 if it is a good idea to tie two pseudo registers
241 when one has mode MODE1 and one has mode MODE2.
242 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
243 for any hard reg, then this must be 0 for correct output. */
244 #define MODES_TIEABLE_P(MODE1, MODE2) \
245 mn10300_modes_tieable ((MODE1), (MODE2))
247 /* 4 data, and effectively 3 address registers is small as far as I'm
249 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
251 /* Define the classes of registers for register constraints in the
252 machine description. Also define ranges of constants.
254 One of the classes must always be named ALL_REGS and include all hard regs.
255 If there is more than one class, another class must be named NO_REGS
256 and contain no registers.
258 The name GENERAL_REGS must be the name of a class (or an alias for
259 another name such as ALL_REGS). This is the class of registers
260 that is allowed by "g" or "r" in a register constraint.
261 Also, registers outside this class are allocated only when
262 instructions express preferences for them.
264 The classes must be numbered in nondecreasing order; that is,
265 a larger-numbered class must never be contained completely
266 in a smaller-numbered class.
268 For any two classes, it is very desirable that there be another
269 class that represents their union. */
273 NO_REGS
, DATA_REGS
, ADDRESS_REGS
, SP_REGS
, SP_OR_ADDRESS_REGS
,
274 EXTENDED_REGS
, FP_REGS
, FP_ACC_REGS
, CC_REGS
, MDR_REGS
,
275 GENERAL_REGS
, SP_OR_GENERAL_REGS
, ALL_REGS
, LIM_REG_CLASSES
278 #define N_REG_CLASSES (int) LIM_REG_CLASSES
280 /* Give names of register classes as strings for dump file. */
282 #define REG_CLASS_NAMES \
283 { "NO_REGS", "DATA_REGS", "ADDRESS_REGS", "SP_REGS", "SP_OR_ADDRESS_REGS", \
284 "EXTENDED_REGS", "FP_REGS", "FP_ACC_REGS", "CC_REGS", "MDR_REGS", \
285 "GENERAL_REGS", "SP_OR_GENERAL_REGS", "ALL_REGS", "LIM_REGS" \
288 /* Define which registers fit in which classes.
289 This is an initializer for a vector of HARD_REG_SET
290 of length N_REG_CLASSES. */
292 #define REG_CLASS_CONTENTS \
293 { { 0, 0 }, /* No regs */ \
294 { 0x0000000f, 0 }, /* DATA_REGS */ \
295 { 0x000001f0, 0 }, /* ADDRESS_REGS */ \
296 { 0x00000200, 0 }, /* SP_REGS */ \
297 { 0x000003f0, 0 }, /* SP_OR_ADDRESS_REGS */ \
298 { 0x0003fc00, 0 }, /* EXTENDED_REGS */ \
299 { 0xfffc0000, 0x3ffff },/* FP_REGS */ \
300 { 0x03fc0000, 0 }, /* FP_ACC_REGS */ \
301 { 0x00000000, 0x80000 },/* CC_REGS */ \
302 { 0x00000000, 0x40000 },/* MDR_REGS */ \
303 { 0x0003fdff, 0 }, /* GENERAL_REGS */ \
304 { 0x0003ffff, 0 }, /* SP_OR_GENERAL_REGS */ \
305 { 0xffffffff, 0xfffff } /* ALL_REGS */ \
308 /* The same information, inverted:
309 Return the class number of the smallest class containing
310 reg number REGNO. This could be a conditional expression
311 or could index an array. */
313 #define REGNO_REG_CLASS(REGNO) \
314 ((REGNO) <= LAST_DATA_REGNUM ? DATA_REGS : \
315 (REGNO) <= LAST_ADDRESS_REGNUM ? ADDRESS_REGS : \
316 (REGNO) == STACK_POINTER_REGNUM ? SP_REGS : \
317 (REGNO) <= LAST_EXTENDED_REGNUM ? EXTENDED_REGS : \
318 (REGNO) <= LAST_FP_REGNUM ? FP_REGS : \
319 (REGNO) == MDR_REG ? MDR_REGS : \
320 (REGNO) == CC_REG ? CC_REGS : \
323 /* The class value for index registers, and the one for base regs. */
324 #define INDEX_REG_CLASS \
325 (TARGET_AM33 ? GENERAL_REGS : DATA_REGS)
326 #define BASE_REG_CLASS \
327 (TARGET_AM33 ? SP_OR_GENERAL_REGS : SP_OR_ADDRESS_REGS)
329 /* Macros to check register numbers against specific register classes. */
331 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
332 and check its validity for a certain class.
333 We have two alternate definitions for each of them.
334 The usual definition accepts all pseudo regs; the other rejects
335 them unless they have been allocated suitable hard regs.
336 The symbol REG_OK_STRICT causes the latter definition to be used.
338 Most source files want to accept pseudo regs in the hope that
339 they will get allocated to the class that the insn wants them to be in.
340 Source files for reload pass need to be strict.
341 After reload, it makes no difference, since pseudo regs have
342 been eliminated by then. */
344 /* These assume that REGNO is a hard or pseudo reg number.
345 They give nonzero only if REGNO is a hard reg of the suitable class
346 or a pseudo reg currently allocated to a suitable hard reg.
347 Since they use reg_renumber, they are safe only once reg_renumber
348 has been allocated, which happens in local-alloc.c. */
350 #ifndef REG_OK_STRICT
351 # define REG_STRICT 0
353 # define REG_STRICT 1
356 #define REGNO_DATA_P(regno, strict) \
357 mn10300_regno_in_class_p (regno, DATA_REGS, strict)
358 #define REGNO_ADDRESS_P(regno, strict) \
359 mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict)
360 #define REGNO_EXTENDED_P(regno, strict) \
361 mn10300_regno_in_class_p (regno, EXTENDED_REGS, strict)
362 #define REGNO_GENERAL_P(regno, strict) \
363 mn10300_regno_in_class_p (regno, GENERAL_REGS, strict)
365 #define REGNO_STRICT_OK_FOR_BASE_P(regno, strict) \
366 mn10300_regno_in_class_p (regno, BASE_REG_CLASS, strict)
367 #define REGNO_OK_FOR_BASE_P(regno) \
368 (REGNO_STRICT_OK_FOR_BASE_P ((regno), REG_STRICT))
369 #define REG_OK_FOR_BASE_P(X) \
370 (REGNO_OK_FOR_BASE_P (REGNO (X)))
372 #define REGNO_STRICT_OK_FOR_BIT_BASE_P(regno, strict) \
373 mn10300_regno_in_class_p (regno, ADDRESS_REGS, strict)
374 #define REGNO_OK_FOR_BIT_BASE_P(regno) \
375 (REGNO_STRICT_OK_FOR_BIT_BASE_P ((regno), REG_STRICT))
376 #define REG_OK_FOR_BIT_BASE_P(X) \
377 (REGNO_OK_FOR_BIT_BASE_P (REGNO (X)))
379 #define REGNO_STRICT_OK_FOR_INDEX_P(regno, strict) \
380 mn10300_regno_in_class_p (regno, INDEX_REG_CLASS, strict)
381 #define REGNO_OK_FOR_INDEX_P(regno) \
382 (REGNO_STRICT_OK_FOR_INDEX_P ((regno), REG_STRICT))
383 #define REG_OK_FOR_INDEX_P(X) \
384 (REGNO_OK_FOR_INDEX_P (REGNO (X)))
386 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \
387 (!TARGET_AM33 && (MODE == QImode || MODE == HImode) ? DATA_REGS : CLASS)
389 /* Return the maximum number of consecutive registers
390 needed to represent mode MODE in a register of class CLASS. */
392 #define CLASS_MAX_NREGS(CLASS, MODE) \
393 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
395 /* A class that contains registers which the compiler must always
396 access in a mode that is the same size as the mode in which it
397 loaded the register. */
398 #define CLASS_CANNOT_CHANGE_SIZE FP_REGS
400 /* Return 1 if VALUE is in the range specified. */
402 #define INT_8_BITS(VALUE) ((unsigned) (VALUE) + 0x80 < 0x100)
403 #define INT_16_BITS(VALUE) ((unsigned) (VALUE) + 0x8000 < 0x10000)
406 /* Stack layout; function entry, exit and calling. */
408 /* Define this if pushing a word on the stack
409 makes the stack pointer a smaller address. */
411 #define STACK_GROWS_DOWNWARD
413 /* Define this to nonzero if the nominal address of the stack frame
414 is at the high-address end of the local variables;
415 that is, each additional local variable allocated
416 goes at a more negative offset in the frame. */
418 #define FRAME_GROWS_DOWNWARD 1
420 /* Offset within stack frame to start allocating local variables at.
421 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
422 first local allocated. Otherwise, it is the offset to the BEGINNING
423 of the first local allocated. */
425 #define STARTING_FRAME_OFFSET 0
427 /* Offset of first parameter from the argument pointer register value. */
428 /* Is equal to the size of the saved fp + pc, even if an fp isn't
429 saved since the value is used before we know. */
431 #define FIRST_PARM_OFFSET(FNDECL) 4
433 /* But the CFA is at the arg pointer directly, not at the first argument. */
434 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
436 #define ELIMINABLE_REGS \
437 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
438 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
439 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
441 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
442 OFFSET = mn10300_initial_offset (FROM, TO)
444 /* We use d0/d1 for passing parameters, so allocate 8 bytes of space
445 for a register flushback area. */
446 #define REG_PARM_STACK_SPACE(DECL) 8
447 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
448 #define ACCUMULATE_OUTGOING_ARGS 1
450 /* So we can allocate space for return pointers once for the function
451 instead of around every call. */
452 #define STACK_POINTER_OFFSET 4
454 /* 1 if N is a possible register number for function argument passing.
455 On the MN10300, d0 and d1 are used in this way. */
457 #define FUNCTION_ARG_REGNO_P(N) ((N) <= 1)
460 /* Define a data type for recording info about an argument list
461 during the scan of that argument list. This data type should
462 hold all necessary information about the function itself
463 and about the args processed so far, enough to enable macros
464 such as FUNCTION_ARG to determine where the next arg should go.
466 On the MN10300, this is a single integer, which is a number of bytes
467 of arguments scanned so far. */
469 #define CUMULATIVE_ARGS struct cum_arg
476 /* Initialize a variable CUM of type CUMULATIVE_ARGS
477 for a call to a function whose data type is FNTYPE.
478 For a library call, FNTYPE is 0.
480 On the MN10300, the offset starts at 0. */
482 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
485 #define FUNCTION_VALUE_REGNO_P(N) mn10300_function_value_regno_p (N)
487 #define DEFAULT_PCC_STRUCT_RETURN 0
489 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
490 the stack pointer does not matter. The value is tested only in
491 functions that have frame pointers.
492 No definition is equivalent to always zero. */
494 #define EXIT_IGNORE_STACK 1
496 /* Output assembler code to FILE to increment profiler label # LABELNO
497 for profiling a function entry. */
499 #define FUNCTION_PROFILER(FILE, LABELNO) ;
501 /* Length in units of the trampoline for entering a nested function. */
503 #define TRAMPOLINE_SIZE 16
504 #define TRAMPOLINE_ALIGNMENT 32
506 /* A C expression whose value is RTL representing the value of the return
507 address for the frame COUNT steps up from the current frame.
509 On the mn10300, the return address is not at a constant location
510 due to the frame layout. Luckily, it is at a constant offset from
511 the argument pointer, so we define RETURN_ADDR_RTX to return a
512 MEM using arg_pointer_rtx. Reload will replace arg_pointer_rtx
513 with a reference to the stack/frame pointer + an appropriate offset. */
515 #define RETURN_ADDR_RTX(COUNT, FRAME) \
517 ? gen_rtx_MEM (Pmode, arg_pointer_rtx) \
520 /* The return address is saved both in the stack and in MDR. Using
521 the stack location is handiest for what unwinding needs. */
522 #define INCOMING_RETURN_ADDR_RTX \
523 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
525 /* Maximum number of registers that can appear in a valid memory address. */
527 #define MAX_REGS_PER_ADDRESS 2
530 /* We have post-increments. */
531 #define HAVE_POST_INCREMENT TARGET_AM33
532 #define HAVE_POST_MODIFY_DISP TARGET_AM33
534 /* ... But we don't want to use them for block moves. Small offsets are
535 just as effective, at least for inline block move sizes, and appears
536 to produce cleaner code. */
537 #define USE_LOAD_POST_INCREMENT(M) 0
538 #define USE_STORE_POST_INCREMENT(M) 0
540 /* Accept either REG or SUBREG where a register is valid. */
542 #define RTX_OK_FOR_BASE_P(X, strict) \
543 ((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X), \
545 || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \
546 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)), \
549 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_L,WIN) \
551 rtx new_x = mn10300_legitimize_reload_address (X, MODE, OPNUM, TYPE, IND_L); \
560 /* Nonzero if the constant value X is a legitimate general operand.
561 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
562 #define LEGITIMATE_CONSTANT_P(X) mn10300_legitimate_constant_p (X)
564 /* Zero if this needs fixing up to become PIC. */
566 #define LEGITIMATE_PIC_OPERAND_P(X) \
567 mn10300_legitimate_pic_operand_p (X)
569 /* Register to hold the addressing base for
570 position independent code access to data items. */
571 #define PIC_OFFSET_TABLE_REGNUM PIC_REG
573 /* The name of the pseudo-symbol representing the Global Offset Table. */
574 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
576 #define SYMBOLIC_CONST_P(X) \
577 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
578 && ! LEGITIMATE_PIC_OPERAND_P (X))
580 /* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled. */
581 #define MN10300_GLOBAL_P(X) (! SYMBOL_REF_FLAG (X))
583 #define SELECT_CC_MODE(OP, X, Y) mn10300_select_cc_mode (OP, X, Y)
584 #define REVERSIBLE_CC_MODE(MODE) 0
586 /* Nonzero if access to memory by bytes or half words is no faster
587 than accessing full words. */
588 #define SLOW_BYTE_ACCESS 1
590 #define NO_FUNCTION_CSE
592 /* According expr.c, a value of around 6 should minimize code size, and
593 for the MN10300 series, that's our primary concern. */
594 #define MOVE_RATIO(speed) 6
596 #define TEXT_SECTION_ASM_OP "\t.section .text"
597 #define DATA_SECTION_ASM_OP "\t.section .data"
598 #define BSS_SECTION_ASM_OP "\t.section .bss"
600 #define ASM_COMMENT_START "#"
602 /* Output to assembler file text saying following lines
603 may contain character constants, extra white space, comments, etc. */
605 #define ASM_APP_ON "#APP\n"
607 /* Output to assembler file text saying following lines
608 no longer contain unusual constructs. */
610 #define ASM_APP_OFF "#NO_APP\n"
612 #undef USER_LABEL_PREFIX
613 #define USER_LABEL_PREFIX "_"
615 /* This says how to output the assembler to define a global
616 uninitialized but not common symbol.
617 Try to use asm_output_bss to implement this macro. */
619 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
620 asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN))
622 /* Globalizing directive for a label. */
623 #define GLOBAL_ASM_OP "\t.global "
625 /* This is how to output a reference to a user-level label named NAME.
626 `assemble_name' uses this. */
628 #undef ASM_OUTPUT_LABELREF
629 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
630 asm_fprintf (FILE, "%U%s", (*targetm.strip_name_encoding) (NAME))
632 /* This is how we tell the assembler that two symbols have the same value. */
634 #define ASM_OUTPUT_DEF(FILE,NAME1,NAME2) \
637 assemble_name (FILE, NAME1); \
638 fputs (" = ", FILE); \
639 assemble_name (FILE, NAME2); \
640 fputc ('\n', FILE); \
644 /* How to refer to registers in assembler output.
645 This sequence is indexed by compiler's hard-register-number (see above). */
647 #define REGISTER_NAMES \
648 { "d0", "d1", "d2", "d3", "a0", "a1", "a2", "a3", "ap", "sp", \
649 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7" \
650 , "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" \
651 , "fs8", "fs9", "fs10", "fs11", "fs12", "fs13", "fs14", "fs15" \
652 , "fs16", "fs17", "fs18", "fs19", "fs20", "fs21", "fs22", "fs23" \
653 , "fs24", "fs25", "fs26", "fs27", "fs28", "fs29", "fs30", "fs31" \
657 #define ADDITIONAL_REGISTER_NAMES \
658 { {"r8", 4}, {"r9", 5}, {"r10", 6}, {"r11", 7}, \
659 {"r12", 0}, {"r13", 1}, {"r14", 2}, {"r15", 3}, \
660 {"e0", 10}, {"e1", 11}, {"e2", 12}, {"e3", 13}, \
661 {"e4", 14}, {"e5", 15}, {"e6", 16}, {"e7", 17} \
662 , {"fd0", 18}, {"fd2", 20}, {"fd4", 22}, {"fd6", 24} \
663 , {"fd8", 26}, {"fd10", 28}, {"fd12", 30}, {"fd14", 32} \
664 , {"fd16", 34}, {"fd18", 36}, {"fd20", 38}, {"fd22", 40} \
665 , {"fd24", 42}, {"fd26", 44}, {"fd28", 46}, {"fd30", 48} \
669 /* Print an instruction operand X on file FILE.
670 look in mn10300.c for details */
672 #define PRINT_OPERAND(FILE, X, CODE) \
673 mn10300_print_operand (FILE, X, CODE)
675 /* Print a memory operand whose address is X, on file FILE.
676 This uses a function in output-vax.c. */
678 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
679 mn10300_print_operand_address (FILE, ADDR)
681 /* This is how to output an element of a case-vector that is absolute. */
683 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
684 fprintf (FILE, "\t%s .L%d\n", ".long", VALUE)
686 /* This is how to output an element of a case-vector that is relative. */
688 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
689 fprintf (FILE, "\t%s .L%d-.L%d\n", ".long", VALUE, REL)
691 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
693 fprintf (FILE, "\t.align %d\n", (LOG))
695 /* We don't have to worry about dbx compatibility for the mn10300. */
696 #define DEFAULT_GDB_EXTENSIONS 1
698 /* Use dwarf2 debugging info by default. */
699 #undef PREFERRED_DEBUGGING_TYPE
700 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
701 #define DWARF2_DEBUGGING_INFO 1
702 #define DWARF2_ASM_LINE_DEBUG_INFO 1
704 /* Specify the machine mode that this machine uses
705 for the index in the tablejump instruction. */
706 #define CASE_VECTOR_MODE Pmode
708 /* Define if operations between registers always perform the operation
709 on the full register even if a narrower mode is specified. */
710 #define WORD_REGISTER_OPERATIONS
712 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
714 /* This flag, if defined, says the same insns that convert to a signed fixnum
715 also convert validly to an unsigned one. */
716 #define FIXUNS_TRUNC_LIKE_FIX_TRUNC
718 /* Max number of bytes we can move from memory to memory
719 in one reasonably fast instruction. */
722 /* Define if shifts truncate the shift count
723 which implies one can omit a sign-extension or zero-extension
725 #define SHIFT_COUNT_TRUNCATED 1
727 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
728 is done just by pretending it is already truncated. */
729 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
731 /* Specify the machine mode that pointers have.
732 After generation of rtl, the compiler makes no further distinction
733 between pointers and any other objects of this machine mode. */
736 /* A function address in a call instruction
737 is a byte address (for indexing purposes)
738 so give the MEM rtx a byte's mode. */
739 #define FUNCTION_MODE QImode
741 /* The assembler op to get a word. */
743 #define FILE_ASM_OP "\t.file\n"