gcc/config/nds32/nds32-predicates.c

   1 /* Predicate functions of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2014 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* ------------------------------------------------------------------------ */
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "tm.h"
  27 #include "tree.h"
  28 #include "stor-layout.h"
  29 #include "varasm.h"
  30 #include "calls.h"
  31 #include "rtl.h"
  32 #include "regs.h"
  33 #include "hard-reg-set.h"
  34 #include "insn-config.h"        /* Required by recog.h.  */
  35 #include "conditions.h"
  36 #include "output.h"
  37 #include "insn-attr.h"          /* For DFA state_t.  */
  38 #include "insn-codes.h"         /* For CODE_FOR_xxx.  */
  39 #include "reload.h"             /* For push_reload().  */
  40 #include "flags.h"
  41 #include "hashtab.h"
  42 #include "hash-set.h"
  43 #include "vec.h"
  44 #include "machmode.h"
  45 #include "input.h"
  46 #include "function.h"
  47 #include "expr.h"
  48 #include "recog.h"
  49 #include "diagnostic-core.h"
  50 #include "df.h"
  51 #include "tm_p.h"
  52 #include "tm-constrs.h"
  53 #include "optabs.h"             /* For GEN_FCN.  */
  54 #include "target.h"
  55 #include "target-def.h"
  56 #include "langhooks.h"          /* For add_builtin_function().  */
  57 #include "ggc.h"
  58 #include "builtins.h"
  59
  60 /* ------------------------------------------------------------------------ */
  61
  62 /* A subroutine that checks multiple load and store
  63    using consecutive registers.
  64      OP is a parallel rtx we would like to check.
  65      LOAD_P indicates whether we are checking load operation.
  66      PAR_INDEX is starting element of parallel rtx.
  67      FIRST_ELT_REGNO is used to tell starting register number.
  68      COUNT helps us to check consecutive register numbers.  */
  69 static bool
  70 nds32_consecutive_registers_load_store_p (rtx op,
  71                                           bool load_p,
  72                                           int par_index,
  73                                           int first_elt_regno,
  74                                           int count)
  75 {
  76   int i;
  77   int check_regno;
  78   rtx elt;
  79   rtx elt_reg;
  80   rtx elt_mem;
  81
  82   for (i = 0; i < count; i++)
  83     {
  84       /* Pick up each element from parallel rtx.  */
  85       elt = XVECEXP (op, 0, i + par_index);
  86
  87       /* If this element is not a 'set' rtx, return false immediately.  */
  88       if (GET_CODE (elt) != SET)
  89         return false;
  90
  91       /* Pick up reg and mem of this element.  */
  92       elt_reg = load_p ? SET_DEST (elt) : SET_SRC (elt);
  93       elt_mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
  94
  95       /* If elt_reg is not a expected reg rtx, return false.  */
  96       if (GET_CODE (elt_reg) != REG || GET_MODE (elt_reg) != SImode)
  97         return false;
  98       /* If elt_mem is not a expected mem rtx, return false.  */
  99       if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
 100         return false;
 101
 102       /* The consecutive registers should be in (Rb,Rb+1...Re) order.  */
 103       check_regno = first_elt_regno + i;
 104
 105       /* If the register number is not continuous, return false.  */
 106       if (REGNO (elt_reg) != (unsigned int) check_regno)
 107         return false;
 108     }
 109
 110   return true;
 111 }
 112
 113 /* Function to check whether the OP is a valid load/store operation.
 114    This is a helper function for the predicates:
 115    'nds32_load_multiple_operation' and 'nds32_store_multiple_operation'
 116    in predicates.md file.
 117
 118    The OP is supposed to be a parallel rtx.
 119    For each element within this parallel rtx:
 120      (set (reg) (mem addr)) is the form for load operation.
 121      (set (mem addr) (reg)) is the form for store operation.
 122    We have to extract reg and mem of every element and
 123    check if the information is valid for multiple load/store operation.  */
 124 bool
 125 nds32_valid_multiple_load_store (rtx op, bool load_p)
 126 {
 127   int count;
 128   int first_elt_regno;
 129   rtx elt;
 130
 131   /* Get the counts of elements in the parallel rtx.  */
 132   count = XVECLEN (op, 0);
 133   /* Pick up the first element.  */
 134   elt = XVECEXP (op, 0, 0);
 135
 136   /* Perform some quick check for the first element in the parallel rtx.  */
 137   if (GET_CODE (elt) != SET
 138       || count <= 1
 139       || count > 8)
 140     return false;
 141
 142   /* Pick up regno of first element for further detail checking.
 143      Note that the form is different between load and store operation.  */
 144   if (load_p)
 145     {
 146       if (GET_CODE (SET_DEST (elt)) != REG
 147           || GET_CODE (SET_SRC (elt)) != MEM)
 148         return false;
 149
 150       first_elt_regno = REGNO (SET_DEST (elt));
 151     }
 152   else
 153     {
 154       if (GET_CODE (SET_SRC (elt)) != REG
 155           || GET_CODE (SET_DEST (elt)) != MEM)
 156         return false;
 157
 158       first_elt_regno = REGNO (SET_SRC (elt));
 159     }
 160
 161   /* Perform detail check for each element.
 162      Refer to nds32-multiple.md for more information
 163      about following checking.
 164      The starting element of parallel rtx is index 0.  */
 165   if (!nds32_consecutive_registers_load_store_p (op, load_p, 0,
 166                                                  first_elt_regno,
 167                                                  count))
 168     return false;
 169
 170   /* Pass all test, this is a valid rtx.  */
 171   return true;
 172 }
 173
 174 /* Function to check whether the OP is a valid stack push/pop operation.
 175    For a valid stack operation, it must satisfy following conditions:
 176      1. Consecutive registers push/pop operations.
 177      2. Valid $fp/$gp/$lp push/pop operations.
 178      3. The last element must be stack adjustment rtx.
 179    See the prologue/epilogue implementation for details.  */
 180 bool
 181 nds32_valid_stack_push_pop_p (rtx op, bool push_p)
 182 {
 183   int index;
 184   int total_count;
 185   int rest_count;
 186   int first_regno;
 187   int save_fp, save_gp, save_lp;
 188   rtx elt;
 189   rtx elt_reg;
 190   rtx elt_mem;
 191   rtx elt_plus;
 192
 193   /* Get the counts of elements in the parallel rtx.  */
 194   total_count = XVECLEN (op, 0);
 195
 196   /* Perform some quick check for that every element should be 'set'.  */
 197   for (index = 0; index < total_count; index++)
 198     {
 199       elt = XVECEXP (op, 0, index);
 200       if (GET_CODE (elt) != SET)
 201         return false;
 202     }
 203
 204   /* For push operation, the parallel rtx looks like:
 205      (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32)))
 206                      (reg:SI Rb))
 207                 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28)))
 208                      (reg:SI Rb+1))
 209                 ...
 210                 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16)))
 211                      (reg:SI Re))
 212                 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12)))
 213                      (reg:SI FP_REGNUM))
 214                 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8)))
 215                      (reg:SI GP_REGNUM))
 216                 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4)))
 217                      (reg:SI LP_REGNUM))
 218                 (set (reg:SI SP_REGNUM)
 219                      (plus (reg:SI SP_REGNUM) (const_int -32)))])
 220
 221      For pop operation, the parallel rtx looks like:
 222      (parallel [(set (reg:SI Rb)
 223                      (mem (reg:SI SP_REGNUM)))
 224                 (set (reg:SI Rb+1)
 225                      (mem (plus (reg:SI SP_REGNUM) (const_int 4))))
 226                 ...
 227                 (set (reg:SI Re)
 228                      (mem (plus (reg:SI SP_REGNUM) (const_int 16))))
 229                 (set (reg:SI FP_REGNUM)
 230                      (mem (plus (reg:SI SP_REGNUM) (const_int 20))))
 231                 (set (reg:SI GP_REGNUM)
 232                      (mem (plus (reg:SI SP_REGNUM) (const_int 24))))
 233                 (set (reg:SI LP_REGNUM)
 234                      (mem (plus (reg:SI SP_REGNUM) (const_int 28))))
 235                 (set (reg:SI SP_REGNUM)
 236                      (plus (reg:SI SP_REGNUM) (const_int 32)))]) */
 237
 238   /* 1. Consecutive registers push/pop operations.
 239         We need to calculate how many registers should be consecutive.
 240         The $sp adjustment rtx, $fp push rtx, $gp push rtx,
 241         and $lp push rtx are excluded.  */
 242
 243   /* Detect whether we have $fp, $gp, or $lp in the parallel rtx.  */
 244   save_fp = reg_mentioned_p (gen_rtx_REG (SImode, FP_REGNUM), op);
 245   save_gp = reg_mentioned_p (gen_rtx_REG (SImode, GP_REGNUM), op);
 246   save_lp = reg_mentioned_p (gen_rtx_REG (SImode, LP_REGNUM), op);
 247   /* Exclude last $sp adjustment rtx.  */
 248   rest_count = total_count - 1;
 249   /* Exclude $fp, $gp, and $lp if they are in the parallel rtx.  */
 250   if (save_fp)
 251     rest_count--;
 252   if (save_gp)
 253     rest_count--;
 254   if (save_lp)
 255     rest_count--;
 256
 257   if (rest_count > 0)
 258     {
 259       elt = XVECEXP (op, 0, 0);
 260       /* Pick up register element.  */
 261       elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
 262       first_regno = REGNO (elt_reg);
 263
 264       /* The 'push' operation is a kind of store operation.
 265          The 'pop' operation is a kind of load operation.
 266          Pass corresponding false/true as second argument (bool load_p).
 267          The par_index is supposed to start with index 0.  */
 268       if (!nds32_consecutive_registers_load_store_p (op,
 269                                                      !push_p ? true : false,
 270                                                      0,
 271                                                      first_regno,
 272                                                      rest_count))
 273         return false;
 274     }
 275
 276   /* 2. Valid $fp/$gp/$lp push/pop operations.
 277         Remember to set start index for checking them.  */
 278
 279   /* The rest_count is the start index for checking $fp/$gp/$lp.  */
 280   index = rest_count;
 281   /* If index < 0, this parallel rtx is definitely
 282      not a valid stack push/pop operation.  */
 283   if (index < 0)
 284     return false;
 285
 286   /* Check $fp/$gp/$lp one by one.
 287      We use 'push_p' to pick up reg rtx and mem rtx.  */
 288   if (save_fp)
 289     {
 290       elt = XVECEXP (op, 0, index);
 291       elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
 292       elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
 293       index++;
 294
 295       if (GET_CODE (elt_mem) != MEM
 296           || GET_CODE (elt_reg) != REG
 297           || REGNO (elt_reg) != FP_REGNUM)
 298         return false;
 299     }
 300   if (save_gp)
 301     {
 302       elt = XVECEXP (op, 0, index);
 303       elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
 304       elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
 305       index++;
 306
 307       if (GET_CODE (elt_mem) != MEM
 308           || GET_CODE (elt_reg) != REG
 309           || REGNO (elt_reg) != GP_REGNUM)
 310         return false;
 311     }
 312   if (save_lp)
 313     {
 314       elt = XVECEXP (op, 0, index);
 315       elt_mem = push_p ? SET_DEST (elt) : SET_SRC (elt);
 316       elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
 317       index++;
 318
 319       if (GET_CODE (elt_mem) != MEM
 320           || GET_CODE (elt_reg) != REG
 321           || REGNO (elt_reg) != LP_REGNUM)
 322         return false;
 323     }
 324
 325   /* 3. The last element must be stack adjustment rtx.
 326         Its form of rtx should be:
 327           (set (reg:SI SP_REGNUM)
 328                (plus (reg:SI SP_REGNUM) (const_int X)))
 329         The X could be positive or negative value.  */
 330
 331   /* Pick up the last element.  */
 332   elt = XVECEXP (op, 0, total_count - 1);
 333
 334   /* Extract its destination and source rtx.  */
 335   elt_reg  = SET_DEST (elt);
 336   elt_plus = SET_SRC (elt);
 337
 338   /* Check this is (set (stack_reg) (plus stack_reg const)) pattern.  */
 339   if (GET_CODE (elt_reg) != REG
 340       || GET_CODE (elt_plus) != PLUS
 341       || REGNO (elt_reg) != SP_REGNUM)
 342     return false;
 343
 344   /* Pass all test, this is a valid rtx.  */
 345   return true;
 346 }
 347
 348 /* Function to check if 'bclr' instruction can be used with IVAL.  */
 349 int
 350 nds32_can_use_bclr_p (int ival)
 351 {
 352   int one_bit_count;
 353
 354   /* Calculate the number of 1-bit of (~ival), if there is only one 1-bit,
 355      it means the original ival has only one 0-bit,
 356      So it is ok to perform 'bclr' operation.  */
 357
 358   one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (~ival));
 359
 360   /* 'bclr' is a performance extension instruction.  */
 361   return (TARGET_PERF_EXT && (one_bit_count == 1));
 362 }
 363
 364 /* Function to check if 'bset' instruction can be used with IVAL.  */
 365 int
 366 nds32_can_use_bset_p (int ival)
 367 {
 368   int one_bit_count;
 369
 370   /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
 371      it is ok to perform 'bset' operation.  */
 372
 373   one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
 374
 375   /* 'bset' is a performance extension instruction.  */
 376   return (TARGET_PERF_EXT && (one_bit_count == 1));
 377 }
 378
 379 /* Function to check if 'btgl' instruction can be used with IVAL.  */
 380 int
 381 nds32_can_use_btgl_p (int ival)
 382 {
 383   int one_bit_count;
 384
 385   /* Caculate the number of 1-bit of ival, if there is only one 1-bit,
 386      it is ok to perform 'btgl' operation.  */
 387
 388   one_bit_count = popcount_hwi ((unsigned HOST_WIDE_INT) (ival));
 389
 390   /* 'btgl' is a performance extension instruction.  */
 391   return (TARGET_PERF_EXT && (one_bit_count == 1));
 392 }
 393
 394 /* Function to check if 'bitci' instruction can be used with IVAL.  */
 395 int
 396 nds32_can_use_bitci_p (int ival)
 397 {
 398   /* If we are using V3 ISA, we have 'bitci' instruction.
 399      Try to see if we can present 'andi' semantic with
 400      such 'bit-clear-immediate' operation.
 401      For example, 'andi $r0,$r0,0xfffffffc' can be
 402      presented with 'bitci $r0,$r0,3'.  */
 403   return (TARGET_ISA_V3
 404           && (ival < 0)
 405           && satisfies_constraint_Iu15 (gen_int_mode (~ival, SImode)));
 406 }
 407
 408 /* ------------------------------------------------------------------------ */