1 ;;- Machine description for GNU compiler, ns32000 Version
2 ;; Copyright (C) 1988, 1994, 1996, 1999 Free Software Foundation, Inc.
3 ;; Contributed by Michael Tiemann (tiemann@cygnus.com)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
24 ;; Insert no-op between an insn with memory read-write operands
25 ;; following by a scale-indexing operation.
26 ;; The Sequent assembler does not allow addresses to be used
27 ;; except in insns which explicitly compute an effective address.
28 ;; I.e., one cannot say "cmpd _p,@_x"
29 ;; Implement unsigned multiplication??
31 ;;- Instruction patterns. When multiple patterns apply,
32 ;;- the first one in the file is chosen.
34 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37 ;;- updates for most instructions.
39 ;; We don't want to allow a constant operand for test insns because
40 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
41 ;; be folded while optimizing anyway.
43 ;; In order for pic mode to work we cannot generate, for example
47 ;; instead we must force gcc to generate something like
52 ;; This was done through operand constraints (using "rmn" in place of "g"),
53 ;; but with the proper definition of LEGITIMATE_PIC_OPERAND (ns32k.h)
54 ;; this is unnecessary.
58 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
61 { cc_status.flags |= CC_REVERSED;
62 operands[1] = const0_rtx;
63 return \"cmpqd %1,%0\"; }")
67 (match_operand:HI 0 "nonimmediate_operand" "g"))]
70 { cc_status.flags |= CC_REVERSED;
71 operands[1] = const0_rtx;
72 return \"cmpqw %1,%0\"; }")
76 (match_operand:QI 0 "nonimmediate_operand" "g"))]
79 { cc_status.flags |= CC_REVERSED;
80 operands[1] = const0_rtx;
81 return \"cmpqb %1,%0\"; }")
85 (match_operand:DF 0 "general_operand" "lmF"))]
88 { cc_status.flags |= CC_REVERSED;
89 operands[1] = CONST0_RTX (DFmode);
90 return \"cmpl %1,%0\"; }")
94 (match_operand:SF 0 "general_operand" "fmF"))]
97 { cc_status.flags |= CC_REVERSED;
98 operands[1] = CONST0_RTX (SFmode);
99 return \"cmpf %1,%0\"; }")
104 (compare (match_operand:SI 0 "general_operand" "g")
105 (match_operand:SI 1 "general_operand" "g")))]
109 if (GET_CODE (operands[1]) == CONST_INT)
111 int i = INTVAL (operands[1]);
112 if (i <= 7 && i >= -8)
114 cc_status.flags |= CC_REVERSED;
115 return \"cmpqd %1,%0\";
118 cc_status.flags &= ~CC_REVERSED;
119 if (GET_CODE (operands[0]) == CONST_INT)
121 int i = INTVAL (operands[0]);
122 if (i <= 7 && i >= -8)
123 return \"cmpqd %0,%1\";
125 return \"cmpd %0,%1\";
130 (compare (match_operand:HI 0 "general_operand" "g")
131 (match_operand:HI 1 "general_operand" "g")))]
135 if (GET_CODE (operands[1]) == CONST_INT)
137 short i = INTVAL (operands[1]);
138 if (i <= 7 && i >= -8)
140 cc_status.flags |= CC_REVERSED;
141 if (INTVAL (operands[1]) > 7)
142 operands[1] = GEN_INT (i);
143 return \"cmpqw %1,%0\";
146 cc_status.flags &= ~CC_REVERSED;
147 if (GET_CODE (operands[0]) == CONST_INT)
149 short i = INTVAL (operands[0]);
150 if (i <= 7 && i >= -8)
152 if (INTVAL (operands[0]) > 7)
153 operands[0] = GEN_INT (i);
154 return \"cmpqw %0,%1\";
157 return \"cmpw %0,%1\";
162 (compare (match_operand:QI 0 "general_operand" "g")
163 (match_operand:QI 1 "general_operand" "g")))]
167 if (GET_CODE (operands[1]) == CONST_INT)
169 char i = INTVAL (operands[1]);
170 if (i <= 7 && i >= -8)
172 cc_status.flags |= CC_REVERSED;
173 if (INTVAL (operands[1]) > 7)
174 operands[1] = GEN_INT (i);
175 return \"cmpqb %1,%0\";
178 cc_status.flags &= ~CC_REVERSED;
179 if (GET_CODE (operands[0]) == CONST_INT)
181 char i = INTVAL (operands[0]);
182 if (i <= 7 && i >= -8)
184 if (INTVAL (operands[0]) > 7)
185 operands[0] = GEN_INT (i);
186 return \"cmpqb %0,%1\";
189 return \"cmpb %0,%1\";
194 (compare (match_operand:DF 0 "general_operand" "lmF")
195 (match_operand:DF 1 "general_operand" "lmF")))]
201 (compare (match_operand:SF 0 "general_operand" "fmF")
202 (match_operand:SF 1 "general_operand" "fmF")))]
206 ;; movdf and movsf copy between general and floating registers using
207 ;; the stack. In principle, we could get better code not allowing
208 ;; that case in the constraints and defining SECONDARY_MEMORY_NEEDED
209 ;; in practice, though the stack slots used are not available for
212 [(set (match_operand:DF 0 "general_operand" "=lg<")
213 (match_operand:DF 1 "general_operand" "lFg"))]
217 if (FP_REG_P (operands[0]))
219 if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
220 return \"movl %1,%0\";
221 if (REG_P (operands[1]))
224 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
225 output_asm_insn (\"movd %1,tos\", xoperands);
226 output_asm_insn (\"movd %1,tos\", operands);
227 return \"movl tos,%0\";
229 return \"movl %1,%0\";
231 else if (FP_REG_P (operands[1]))
233 if (REG_P (operands[0]))
235 output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
236 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
237 return \"movd tos,%0\";
240 return \"movl %1,%0\";
242 return output_move_double (operands);
246 [(set (match_operand:SF 0 "general_operand" "=fg<")
247 (match_operand:SF 1 "general_operand" "fFg"))]
251 if (FP_REG_P (operands[0]))
253 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
254 return \"movd %1,tos\;movf tos,%0\";
256 return \"movf %1,%0\";
258 else if (FP_REG_P (operands[1]))
260 if (REG_P (operands[0]))
261 return \"movf %1,tos\;movd tos,%0\";
262 return \"movf %1,%0\";
264 #if 0 /* Someone suggested this for the Sequent. Is it needed? */
265 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
266 return \"movf %1,%0\";
268 /* There was a #if 0 around this, but that was erroneous
269 for many machines -- rms. */
270 #ifndef MOVD_FLOAT_OK
271 /* GAS understands floating constants in ordinary movd instructions
272 but other assemblers might object. */
273 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
275 union {int i[2]; float f; double d;} convrt;
276 convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
277 convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
280 /* Is there a better machine-independent way to do this? */
281 operands[1] = GEN_INT (convrt.i[0]);
282 return \"movd %1,%0\";
285 else return \"movd %1,%0\";
289 [(set (match_operand:TI 0 "memory_operand" "=m")
290 (match_operand:TI 1 "memory_operand" "m"))]
295 [(set (match_operand:DI 0 "general_operand" "=g<,*f,g")
296 (match_operand:DI 1 "general_operand" "gF,g,*f"))]
300 if (FP_REG_P (operands[0]))
302 if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
303 return \"movl %1,%0\";
304 if (REG_P (operands[1]))
307 xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
308 output_asm_insn (\"movd %1,tos\", xoperands);
309 output_asm_insn (\"movd %1,tos\", operands);
310 return \"movl tos,%0\";
312 return \"movl %1,%0\";
314 else if (FP_REG_P (operands[1]))
316 if (REG_P (operands[0]))
318 output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
319 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
320 return \"movd tos,%0\";
323 return \"movl %1,%0\";
325 return output_move_double (operands);
328 ;; This special case must precede movsi.
331 (match_operand:SI 0 "general_operand" "g"))]
336 [(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g,x")
337 (match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))]
341 extern int flag_pic; \
343 if (FP_REG_P (operands[0]))
345 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
346 return \"movd %1,tos\;movf tos,%0\";
348 return \"movf %1,%0\";
350 else if (FP_REG_P (operands[1]))
352 if (REG_P (operands[0]))
353 return \"movf %1,tos\;movd tos,%0\";
354 return \"movf %1,%0\";
356 if (GET_CODE (operands[0]) == REG
357 && REGNO (operands[0]) == FRAME_POINTER_REGNUM)
358 return \"lprd fp,%1\";
359 if (GET_CODE (operands[1]) == CONST_DOUBLE)
361 = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
362 if (GET_CODE (operands[1]) == CONST_INT)
364 int i = INTVAL (operands[1]);
367 if (i <= 7 && i >= -8)
368 return \"movqd %1,%0\";
369 if (NS32K_DISPLACEMENT_P (i))
370 #if defined (GNX_V3) || defined (UTEK_ASM)
371 return \"addr %c1,%0\";
373 return \"addr @%c1,%0\";
375 return \"movd %1,%0\";
378 return output_move_dconst(i, \"%1,%0\");
380 else if (GET_CODE (operands[1]) == CONST && ! flag_pic)
382 /* Must contain symbols so we don`t know how big it is. In
383 * that case addr might lead to overflow. For PIC symbolic
384 * address loads always have to be done with addr.
386 return \"movd %1,%0\";
388 else if (GET_CODE (operands[1]) == REG)
390 if (REGNO (operands[1]) < F0_REGNUM)
391 return \"movd %1,%0\";
392 else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
394 if (GET_CODE(operands[0]) == REG)
395 return \"sprd fp,%0\";
397 return \"addr 0(fp),%0\" ;
399 else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
401 if (GET_CODE(operands[0]) == REG)
402 return \"sprd sp,%0\";
404 return \"addr 0(sp),%0\" ;
408 else if (GET_CODE (operands[1]) == MEM)
409 return \"movd %1,%0\";
411 /* Check if this effective address can be
412 calculated faster by pulling it apart. */
413 if (REG_P (operands[0])
414 && GET_CODE (operands[1]) == MULT
415 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
416 && (INTVAL (XEXP (operands[1], 1)) == 2
417 || INTVAL (XEXP (operands[1], 1)) == 4))
420 xoperands[0] = operands[0];
421 xoperands[1] = XEXP (operands[1], 0);
422 xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
423 return output_shift_insn (xoperands);
425 return \"addr %a1,%0\";
429 [(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
430 (match_operand:HI 1 "general_operand" "g,g,*f"))]
434 if (GET_CODE (operands[1]) == CONST_INT)
436 short i = INTVAL (operands[1]);
437 if (i <= 7 && i >= -8)
439 if (INTVAL (operands[1]) > 7)
442 return \"movqw %1,%0\";
444 return \"movw %1,%0\";
446 else if (FP_REG_P (operands[0]))
448 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
449 return \"movwf %1,tos\;movf tos,%0\";
451 return \"movwf %1,%0\";
453 else if (FP_REG_P (operands[1]))
455 if (REG_P (operands[0]))
456 return \"movf %1,tos\;movd tos,%0\";
457 return \"movf %1,%0\";
460 return \"movw %1,%0\";
463 (define_insn "movstricthi"
464 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
465 (match_operand:HI 1 "general_operand" "g"))]
469 if (GET_CODE (operands[1]) == CONST_INT
470 && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
471 return \"movqw %1,%0\";
472 return \"movw %1,%0\";
476 [(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
477 (match_operand:QI 1 "general_operand" "g,g,*f"))]
480 { if (GET_CODE (operands[1]) == CONST_INT)
482 char char_val = (char)INTVAL (operands[1]);
483 if (char_val <= 7 && char_val >= -8)
485 if (INTVAL (operands[1]) > 7)
488 return \"movqb %1,%0\";
490 return \"movb %1,%0\";
492 else if (FP_REG_P (operands[0]))
494 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < F0_REGNUM)
495 return \"movbf %1,tos\;movf tos,%0\";
497 return \"movbf %1,%0\";
499 else if (FP_REG_P (operands[1]))
501 if (REG_P (operands[0]))
502 return \"movf %1,tos\;movd tos,%0\";
503 return \"movf %1,%0\";
506 return \"movb %1,%0\";
509 (define_insn "movstrictqi"
510 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
511 (match_operand:QI 1 "general_operand" "g"))]
515 if (GET_CODE (operands[1]) == CONST_INT
516 && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
517 return \"movqb %1,%0\";
518 return \"movb %1,%0\";
522 ;; Argument 0 is the destination
523 ;; Argument 1 is the source
524 ;; Argument 2 is the length
525 ;; Argument 3 is the alignment
527 ;; Strategy: Use define_expand to
528 ;; either emit insns directly if it can be done simply or
529 ;; emit rtl to match movstrsi1 which has extra scratch registers
530 ;; which can be used to generate more complex code.
532 (define_expand "movstrsi"
533 [(parallel [(set (match_operand:BLK 0 "general_operand" "")
534 (match_operand:BLK 1 "general_operand" ""))
535 (use (match_operand:SI 2 "general_operand" ""))
536 (use (match_operand:SI 3 "const_int_operand" ""))])]
540 if (operands[0]) /* avoid unused code messages */
542 expand_block_move (operands);
547 ;; Special Registers:
554 (define_insn "movstrsi1"
555 [(set (mem:BLK (reg:SI 2))
556 (mem:BLK (reg:SI 1)))
558 (set (reg:SI 2) (plus:SI (reg:SI 2) (mult:SI (reg:SI 0) (match_operand:SI 0 "const_int_operand" ""))))
559 (set (reg:SI 1) (plus:SI (reg:SI 1) (mult:SI (reg:SI 0) (match_dup 0))))
560 (set (reg:SI 0) (const_int 0))]
564 int align = INTVAL(operands[0]);
571 (define_insn "movstrsi2"
572 [(set (mem:BLK (match_operand:SI 0 "address_operand" "g"))
573 (mem:BLK (match_operand:SI 1 "address_operand" "g")))
574 (use (match_operand 2 "immediate_operand" "i"))]
579 ;; Extension and truncation insns.
580 ;; Those for integer source operand
581 ;; are ordered widest source type first.
583 (define_insn "truncsiqi2"
584 [(set (match_operand:QI 0 "general_operand" "=g<")
585 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
589 (define_insn "truncsihi2"
590 [(set (match_operand:HI 0 "general_operand" "=g<")
591 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
595 (define_insn "trunchiqi2"
596 [(set (match_operand:QI 0 "general_operand" "=g<")
597 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
601 (define_insn "extendhisi2"
602 [(set (match_operand:SI 0 "general_operand" "=g<")
603 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
607 (define_insn "extendqihi2"
608 [(set (match_operand:HI 0 "general_operand" "=g<")
609 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
613 (define_insn "extendqisi2"
614 [(set (match_operand:SI 0 "general_operand" "=g<")
615 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
619 (define_insn "extendsfdf2"
620 [(set (match_operand:DF 0 "general_operand" "=lm<")
621 (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
625 (define_insn "truncdfsf2"
626 [(set (match_operand:SF 0 "general_operand" "=fm<")
627 (float_truncate:SF (match_operand:DF 1 "general_operand" "lmF")))]
631 (define_insn "zero_extendhisi2"
632 [(set (match_operand:SI 0 "general_operand" "=g<")
633 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
637 (define_insn "zero_extendqihi2"
638 [(set (match_operand:HI 0 "general_operand" "=g<")
639 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
643 (define_insn "zero_extendqisi2"
644 [(set (match_operand:SI 0 "general_operand" "=g<")
645 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
649 ;; Fix-to-float conversion insns.
650 ;; Note that the ones that start with SImode come first.
651 ;; That is so that an operand that is a CONST_INT
652 ;; (and therefore lacks a specific machine mode).
653 ;; will be recognized as SImode (which is always valid)
654 ;; rather than as QImode or HImode.
656 ;; Rumor has it that the National part does not correctly convert
657 ;; constant ints to floats. This conversion is therefore disabled.
658 ;; A register must be used to perform the conversion.
660 (define_insn "floatsisf2"
661 [(set (match_operand:SF 0 "general_operand" "=fm<")
662 (float:SF (match_operand:SI 1 "general_operand" "rm")))]
666 (define_insn "floatsidf2"
667 [(set (match_operand:DF 0 "general_operand" "=lm<")
668 (float:DF (match_operand:SI 1 "general_operand" "rm")))]
672 (define_insn "floathisf2"
673 [(set (match_operand:SF 0 "general_operand" "=fm<")
674 (float:SF (match_operand:HI 1 "general_operand" "rm")))]
678 (define_insn "floathidf2"
679 [(set (match_operand:DF 0 "general_operand" "=lm<")
680 (float:DF (match_operand:HI 1 "general_operand" "rm")))]
684 (define_insn "floatqisf2"
685 [(set (match_operand:SF 0 "general_operand" "=fm<")
686 (float:SF (match_operand:QI 1 "general_operand" "rm")))]
690 ; Some assemblers warn that this insn doesn't work.
691 ; Maybe they know something we don't.
692 ;(define_insn "floatqidf2"
693 ; [(set (match_operand:DF 0 "general_operand" "=lm<")
694 ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
698 ;; Float-to-fix conversion insns.
699 ;; The sequent compiler always generates "trunc" insns.
701 (define_insn "fixsfqi2"
702 [(set (match_operand:QI 0 "general_operand" "=g<")
703 (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
707 (define_insn "fixsfhi2"
708 [(set (match_operand:HI 0 "general_operand" "=g<")
709 (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
713 (define_insn "fixsfsi2"
714 [(set (match_operand:SI 0 "general_operand" "=g<")
715 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
719 (define_insn "fixdfqi2"
720 [(set (match_operand:QI 0 "general_operand" "=g<")
721 (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
725 (define_insn "fixdfhi2"
726 [(set (match_operand:HI 0 "general_operand" "=g<")
727 (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
731 (define_insn "fixdfsi2"
732 [(set (match_operand:SI 0 "general_operand" "=g<")
733 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
739 (define_insn "fixunssfqi2"
740 [(set (match_operand:QI 0 "general_operand" "=g<")
741 (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
745 (define_insn "fixunssfhi2"
746 [(set (match_operand:HI 0 "general_operand" "=g<")
747 (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
751 (define_insn "fixunssfsi2"
752 [(set (match_operand:SI 0 "general_operand" "=g<")
753 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
757 (define_insn "fixunsdfqi2"
758 [(set (match_operand:QI 0 "general_operand" "=g<")
759 (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
763 (define_insn "fixunsdfhi2"
764 [(set (match_operand:HI 0 "general_operand" "=g<")
765 (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
769 (define_insn "fixunsdfsi2"
770 [(set (match_operand:SI 0 "general_operand" "=g<")
771 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "lm"))))]
775 ;;; These are not yet used by GCC
776 (define_insn "fix_truncsfqi2"
777 [(set (match_operand:QI 0 "general_operand" "=g<")
778 (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
782 (define_insn "fix_truncsfhi2"
783 [(set (match_operand:HI 0 "general_operand" "=g<")
784 (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
788 (define_insn "fix_truncsfsi2"
789 [(set (match_operand:SI 0 "general_operand" "=g<")
790 (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
794 (define_insn "fix_truncdfqi2"
795 [(set (match_operand:QI 0 "general_operand" "=g<")
796 (fix:QI (match_operand:DF 1 "general_operand" "lm")))]
800 (define_insn "fix_truncdfhi2"
801 [(set (match_operand:HI 0 "general_operand" "=g<")
802 (fix:HI (match_operand:DF 1 "general_operand" "lm")))]
806 (define_insn "fix_truncdfsi2"
807 [(set (match_operand:SI 0 "general_operand" "=g<")
808 (fix:SI (match_operand:DF 1 "general_operand" "lm")))]
812 ;; Multiply-add instructions
814 [(set (match_operand:DF 0 "general_operand" "=v,v")
815 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
816 (match_operand:DF 2 "general_operand" "lmF,lmF"))
817 (match_operand:DF 3 "general_operand" "0,lmF")))]
824 [(set (match_operand:SF 0 "general_operand" "=u,u")
825 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
826 (match_operand:SF 2 "general_operand" "fmF,fmF"))
827 (match_operand:SF 3 "general_operand" "0,fmF")))]
834 ;; Multiply-sub instructions
836 [(set (match_operand:DF 0 "general_operand" "=v")
837 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF")
838 (match_operand:DF 2 "general_operand" "lmF"))
839 (match_operand:DF 3 "general_operand" "0")))]
842 negl %0,%0\;dotl %1,%2")
845 [(set (match_operand:SF 0 "general_operand" "=u")
846 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF")
847 (match_operand:SF 2 "general_operand" "fmF"))
848 (match_operand:SF 3 "general_operand" "0")))]
851 negf %0,%0\;dotf %1,%2")
853 ;;- All kinds of add instructions.
855 (define_insn "adddf3"
856 [(set (match_operand:DF 0 "general_operand" "=lm")
857 (plus:DF (match_operand:DF 1 "general_operand" "%0")
858 (match_operand:DF 2 "general_operand" "lmF")))]
863 (define_insn "addsf3"
864 [(set (match_operand:SF 0 "general_operand" "=fm")
865 (plus:SF (match_operand:SF 1 "general_operand" "%0")
866 (match_operand:SF 2 "general_operand" "fmF")))]
873 (match_operand:SI 0 "immediate_operand" "i")))]
874 "GET_CODE (operands[0]) == CONST_INT"
877 #ifndef SEQUENT_ADJUST_STACK
879 if (INTVAL (operands[0]) == 8)
880 return \"cmpd tos,tos\";
881 if (TARGET_32532 || TARGET_32332)
882 if (INTVAL (operands[0]) == 4)
883 return \"cmpqd %$0,tos\";
887 if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
888 return \"adjspb %n0\";
889 else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
890 return \"adjspw %n0\";
892 return \"adjspd %n0\";
896 [(set (match_operand:SI 0 "general_operand" "=g<")
898 (match_operand:SI 1 "immediate_operand" "i")))]
899 "GET_CODE (operands[1]) == CONST_INT"
903 [(set (match_operand:SI 0 "general_operand" "=g<")
905 (match_operand:SI 1 "immediate_operand" "i")))]
906 "GET_CODE (operands[1]) == CONST_INT"
909 (define_insn "adddi3"
910 [(set (match_operand:DI 0 "general_operand" "=ro")
911 (plus:DI (match_operand:DI 1 "general_operand" "%0")
912 (match_operand:DI 2 "general_operand" "ron")))]
916 rtx low[3], high[3], xops[4];
917 split_di (operands, 3, low, high);
923 if (GET_CODE (xops[2]) == CONST_INT)
925 int i = INTVAL (xops[2]);
927 if (i <= 7 && i >= -8)
931 i = INTVAL (xops[3]);
932 if (i <= 7 && i >= -8)
933 output_asm_insn (\"addqd %3,%1\", xops);
935 output_asm_insn (\"addd %3,%1\", xops);
939 output_asm_insn (\"addqd %2,%0\", xops);
940 output_asm_insn (\"addcd %3,%1\", xops);
945 output_asm_insn (\"addd %2,%0\", xops);
946 output_asm_insn (\"addcd %3,%1\", xops);
951 (define_insn "addsi3"
952 [(set (match_operand:SI 0 "general_operand" "=g,=g&<")
953 (plus:SI (match_operand:SI 1 "general_operand" "%0,r")
954 (match_operand:SI 2 "general_operand" "g,i")))]
958 if (which_alternative == 1)
960 if (GET_CODE (operands[2]) == CONST_INT)
962 int i = INTVAL (operands[2]);
963 if (NS32K_DISPLACEMENT_P (i))
964 return \"addr %c2(%1),%0\";
966 return \"movd %1,%0\;addd %2,%0\";
971 return \"addr %a2[%1:b],%0\";
973 return \"addr %c2(%1),%0\";
976 else if (GET_CODE (operands[2]) == CONST_INT)
978 int i = INTVAL (operands[2]);
980 if (i <= 7 && i >= -8)
981 return \"addqd %2,%0\";
982 else if (! TARGET_32532 && GET_CODE (operands[0]) == REG
983 && NS32K_DISPLACEMENT_P (i))
984 return \"addr %c2(%0),%0\";
986 return \"addd %2,%0\";
989 (define_insn "addhi3"
990 [(set (match_operand:HI 0 "general_operand" "=g")
991 (plus:HI (match_operand:HI 1 "general_operand" "%0")
992 (match_operand:HI 2 "general_operand" "g")))]
995 { if (GET_CODE (operands[2]) == CONST_INT)
997 int i = INTVAL (operands[2]);
998 if (i <= 7 && i >= -8)
999 return \"addqw %2,%0\";
1001 return \"addw %2,%0\";
1005 [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
1006 (plus:HI (match_operand:HI 1 "general_operand" "0")
1007 (match_operand:HI 2 "general_operand" "g")))]
1011 if (GET_CODE (operands[1]) == CONST_INT
1012 && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
1013 return \"addqw %2,%0\";
1014 return \"addw %2,%0\";
1017 (define_insn "addqi3"
1018 [(set (match_operand:QI 0 "general_operand" "=g")
1019 (plus:QI (match_operand:QI 1 "general_operand" "%0")
1020 (match_operand:QI 2 "general_operand" "g")))]
1023 { if (GET_CODE (operands[2]) == CONST_INT)
1025 int i = INTVAL (operands[2]);
1026 if (i <= 7 && i >= -8)
1027 return \"addqb %2,%0\";
1029 return \"addb %2,%0\";
1033 [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
1034 (plus:QI (match_operand:QI 1 "general_operand" "0")
1035 (match_operand:QI 2 "general_operand" "g")))]
1039 if (GET_CODE (operands[1]) == CONST_INT
1040 && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
1041 return \"addqb %2,%0\";
1042 return \"addb %2,%0\";
1045 ;;- All kinds of subtract instructions.
1047 (define_insn "subdf3"
1048 [(set (match_operand:DF 0 "general_operand" "=lm")
1049 (minus:DF (match_operand:DF 1 "general_operand" "0")
1050 (match_operand:DF 2 "general_operand" "lmF")))]
1054 (define_insn "subsf3"
1055 [(set (match_operand:SF 0 "general_operand" "=fm")
1056 (minus:SF (match_operand:SF 1 "general_operand" "0")
1057 (match_operand:SF 2 "general_operand" "fmF")))]
1063 (minus:SI (reg:SI 25)
1064 (match_operand:SI 0 "immediate_operand" "i")))]
1065 "GET_CODE (operands[0]) == CONST_INT"
1068 if (! TARGET_32532 && GET_CODE(operands[0]) == CONST_INT
1069 && INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
1070 return \"adjspb %0\";
1071 return \"adjspd %0\";
1074 (define_insn "subdi3"
1075 [(set (match_operand:DI 0 "general_operand" "=ro")
1076 (minus:DI (match_operand:DI 1 "general_operand" "0")
1077 (match_operand:DI 2 "general_operand" "ron")))]
1081 rtx low[3], high[3], xops[4];
1082 split_di (operands, 3, low, high);
1088 if (GET_CODE (xops[2]) == CONST_INT)
1090 int i = INTVAL (xops[2]);
1092 if (i <= 8 && i >= -7)
1096 i = INTVAL (xops[3]);
1097 if (i <= 8 && i >= -7)
1098 output_asm_insn (\"addqd %n3,%1\", xops);
1100 output_asm_insn (\"subd %3,%1\", xops);
1104 output_asm_insn (\"addqd %n2,%0\", xops);
1105 output_asm_insn (\"subcd %3,%1\", xops);
1110 output_asm_insn (\"subd %2,%0\", xops);
1111 output_asm_insn (\"subcd %3,%1\", xops);
1115 (define_insn "subsi3"
1116 [(set (match_operand:SI 0 "general_operand" "=g")
1117 (minus:SI (match_operand:SI 1 "general_operand" "0")
1118 (match_operand:SI 2 "general_operand" "g")))]
1121 { if (GET_CODE (operands[2]) == CONST_INT)
1123 int i = INTVAL (operands[2]);
1125 if (i <= 8 && i >= -7)
1126 return \"addqd %n2,%0\";
1128 return \"subd %2,%0\";
1131 (define_insn "subhi3"
1132 [(set (match_operand:HI 0 "general_operand" "=g")
1133 (minus:HI (match_operand:HI 1 "general_operand" "0")
1134 (match_operand:HI 2 "general_operand" "g")))]
1137 { if (GET_CODE (operands[2]) == CONST_INT)
1139 int i = INTVAL (operands[2]);
1141 if (i <= 8 && i >= -7)
1142 return \"addqw %n2,%0\";
1144 return \"subw %2,%0\";
1148 [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
1149 (minus:HI (match_operand:HI 1 "general_operand" "0")
1150 (match_operand:HI 2 "general_operand" "g")))]
1154 if (GET_CODE (operands[1]) == CONST_INT
1155 && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1156 return \"addqw %n2,%0\";
1157 return \"subw %2,%0\";
1160 (define_insn "subqi3"
1161 [(set (match_operand:QI 0 "general_operand" "=g")
1162 (minus:QI (match_operand:QI 1 "general_operand" "0")
1163 (match_operand:QI 2 "general_operand" "g")))]
1166 { if (GET_CODE (operands[2]) == CONST_INT)
1168 int i = INTVAL (operands[2]);
1170 if (i <= 8 && i >= -7)
1171 return \"addqb %n2,%0\";
1173 return \"subb %2,%0\";
1177 [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
1178 (minus:QI (match_operand:QI 1 "general_operand" "0")
1179 (match_operand:QI 2 "general_operand" "g")))]
1183 if (GET_CODE (operands[1]) == CONST_INT
1184 && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1185 return \"addqb %n2,%0\";
1186 return \"subb %2,%0\";
1189 ;;- Multiply instructions.
1191 (define_insn "muldf3"
1192 [(set (match_operand:DF 0 "general_operand" "=lm")
1193 (mult:DF (match_operand:DF 1 "general_operand" "%0")
1194 (match_operand:DF 2 "general_operand" "lmF")))]
1198 (define_insn "mulsf3"
1199 [(set (match_operand:SF 0 "general_operand" "=fm")
1200 (mult:SF (match_operand:SF 1 "general_operand" "%0")
1201 (match_operand:SF 2 "general_operand" "fmF")))]
1206 (define_insn "mulsi3"
1207 [(set (match_operand:SI 0 "general_operand" "=g")
1208 (mult:SI (match_operand:SI 1 "general_operand" "%0")
1209 (match_operand:SI 2 "general_operand" "g")))]
1213 (define_insn "mulhi3"
1214 [(set (match_operand:HI 0 "general_operand" "=g")
1215 (mult:HI (match_operand:HI 1 "general_operand" "%0")
1216 (match_operand:HI 2 "general_operand" "g")))]
1220 (define_insn "mulqi3"
1221 [(set (match_operand:QI 0 "general_operand" "=g")
1222 (mult:QI (match_operand:QI 1 "general_operand" "%0")
1223 (match_operand:QI 2 "general_operand" "g")))]
1227 (define_insn "umulsidi3"
1228 [(set (match_operand:DI 0 "general_operand" "=g")
1229 (mult:DI (zero_extend:DI
1230 (match_operand:SI 1 "nonimmediate_operand" "0"))
1232 (match_operand:SI 2 "nonimmediate_operand" "g"))))]
1236 ;; divmod insns: We can only do the unsigned case.
1237 (define_expand "udivmodsi4"
1239 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
1240 (udiv:SI (match_operand:SI 1 "general_operand" "")
1241 (match_operand:SI 2 "general_operand" "")))
1242 (set (match_operand:SI 3 "reg_or_mem_operand" "")
1243 (umod:SI (match_dup 1) (match_dup 2)))])]
1247 rtx temp = gen_reg_rtx(DImode);
1248 rtx insn, first, last;
1249 first = emit_move_insn(gen_lowpart(SImode, temp), operands[1]);
1250 emit_move_insn(gen_highpart(SImode, temp), const0_rtx);
1251 emit_insn(gen_udivmoddisi4_internal(temp, temp, operands[2]));
1252 last = emit_move_insn(temp, temp);
1254 rtx divdi, moddi, divsi, modsi;
1255 divsi = gen_rtx (UDIV, SImode, operands[1], operands[2]);
1256 modsi = gen_rtx (UMOD, SImode, operands[1], operands[2]);
1257 divdi = gen_rtx (ZERO_EXTEND, DImode, divsi);
1258 moddi = gen_rtx (ZERO_EXTEND, DImode, modsi);
1259 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1261 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1262 gen_rtx (EXPR_LIST, REG_EQUAL,
1263 gen_rtx (IOR, DImode, moddi,
1264 gen_rtx (ASHIFT, DImode, divdi, GEN_INT(32))),
1268 insn = emit_move_insn(operands[0], gen_highpart(SImode, temp));
1269 insn = emit_move_insn(operands[3], gen_lowpart(SImode, temp));
1273 ;; If we try and describe what this does, we have to zero-expand an
1274 ;; operand, which prevents it being a constant (VOIDmode) (see udivmoddisi4
1275 ;; below. This udivmoddisi4_internal never matches anything and is only
1276 ;; ever used when explicitly emitted by a define_expand.
1277 (define_insn "udivmoddisi4_internal"
1278 [(set (match_operand:DI 0 "reg_or_mem_operand" "=rm")
1279 (unspec:DI [(match_operand:DI 1 "reg_or_mem_operand" "0")
1280 (match_operand:SI 2 "general_operand" "g")] 0))]
1284 ;; Retain this insn which *does* have a pattern indicating what it does,
1285 ;; just in case the compiler is smart enough to recognize a substitution.
1286 (define_insn "udivmoddisi4"
1287 [(set (subreg:SI (match_operand:DI 0 "register_operand" "=rm") 1)
1288 (truncate:SI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
1289 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "g")))))
1290 (set (subreg:SI (match_operand:DI 3 "register_operand" "=0") 0)
1291 (truncate:SI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1295 ;; Part word variants. These seem to never be used at the moment (gcc
1296 ;; 2.7.2.2). The code generation prefers to zero extend hi's and qi's
1297 ;; and use signed div and mod. Keep these insns incase that changes.
1298 ;; divmod should have an advantage when both div and mod are needed. However,
1299 ;; divmod uses two registers, so maybe the compiler knows best.
1301 (define_expand "udivmodhi4"
1303 [(set (match_operand:HI 0 "reg_or_mem_operand" "")
1304 (udiv:HI (match_operand:HI 1 "general_operand" "")
1305 (match_operand:HI 2 "general_operand" "")))
1306 (set (match_operand:HI 3 "reg_or_mem_operand" "")
1307 (umod:HI (match_dup 1) (match_dup 2)))])]
1311 rtx temp = gen_reg_rtx(DImode);
1312 rtx insn, first, last;
1313 first = emit_move_insn(gen_lowpart(HImode, temp), operands[1]);
1314 emit_move_insn(gen_highpart (HImode, temp), const0_rtx);
1315 operands[2] = force_reg(HImode, operands[2]);
1316 emit_insn(gen_udivmoddihi4_internal(temp, temp, operands[2]));
1317 last = emit_move_insn(temp, temp);
1319 rtx divdi, moddi, divhi, modhi;
1320 divhi = gen_rtx (UDIV, HImode, operands[1], operands[2]);
1321 modhi = gen_rtx (UMOD, HImode, operands[1], operands[2]);
1322 divdi = gen_rtx (ZERO_EXTEND, DImode, divhi);
1323 moddi = gen_rtx (ZERO_EXTEND, DImode, modhi);
1324 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1326 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1327 gen_rtx (EXPR_LIST, REG_EQUAL,
1328 gen_rtx(IOR, DImode, moddi,
1329 gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
1333 insn = emit_move_insn(operands[0], gen_highpart(HImode, temp));
1334 insn = emit_move_insn(operands[3], gen_lowpart(HImode, temp));
1338 ;; deiw wants two hi's in separate registers or else they can be adjacent
1339 ;; in memory. DI mode will ensure two registers are available, but if we
1340 ;; want to allow memory as an operand we would need SI mode. There is no
1341 ;; way to do this, so just restrict operand 0 and 1 to be in registers.
1342 (define_insn "udivmoddihi4_internal"
1343 [(set (match_operand:DI 0 "register_operand" "=r")
1344 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
1345 (match_operand:HI 2 "general_operand" "g")] 0))]
1349 (define_insn "udivmoddihi4"
1350 [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 1)
1351 (truncate:HI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
1352 (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "g")))))
1353 (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
1354 (truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1358 (define_expand "udivmodqi4"
1360 [(set (match_operand:QI 0 "reg_or_mem_operand" "")
1361 (udiv:QI (match_operand:QI 1 "general_operand" "")
1362 (match_operand:QI 2 "general_operand" "")))
1363 (set (match_operand:QI 3 "reg_or_mem_operand" "")
1364 (umod:QI (match_dup 1) (match_dup 2)))])]
1368 rtx temp = gen_reg_rtx(DImode);
1369 rtx insn, first, last;
1370 first = emit_move_insn(gen_lowpart(QImode, temp), operands[1]);
1371 emit_move_insn(gen_highpart(QImode, temp), const0_rtx);
1372 operands[2] = force_reg(QImode, operands[2]);
1373 emit_insn(gen_udivmoddiqi4_internal(temp, temp, operands[2]));
1374 last = emit_move_insn(temp, temp);
1376 rtx divdi, moddi, divqi, modqi;
1377 divqi = gen_rtx (UDIV, QImode, operands[1], operands[2]);
1378 modqi = gen_rtx (UMOD, QImode, operands[1], operands[2]);
1379 divdi = gen_rtx (ZERO_EXTEND, DImode, divqi);
1380 moddi = gen_rtx (ZERO_EXTEND, DImode, modqi);
1381 REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1383 REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
1384 gen_rtx (EXPR_LIST, REG_EQUAL,
1385 gen_rtx(IOR, DImode, moddi,
1386 gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
1390 insn = emit_move_insn(operands[0], gen_highpart(QImode, temp));
1391 insn = emit_move_insn(operands[3], gen_lowpart(QImode, temp));
1395 ;; deib wants two qi's in separate registers or else they can be adjacent
1396 ;; in memory. DI mode will ensure two registers are available, but if we
1397 ;; want to allow memory as an operand we would need HI mode. There is no
1398 ;; way to do this, so just restrict operand 0 and 1 to be in registers.
1399 (define_insn "udivmoddiqi4_internal"
1400 [(set (match_operand:DI 0 "register_operand" "=r")
1401 (unspec:DI [(match_operand:DI 1 "reg_or_mem_operand" "0")
1402 (match_operand:QI 2 "general_operand" "g")] 0))]
1406 (define_insn "udivmoddiqi4"
1407 [(set (subreg:QI (match_operand:DI 0 "register_operand" "=r") 1)
1408 (truncate:QI (udiv:DI (match_operand:DI 1 "reg_or_mem_operand" "0")
1409 (zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "g")))))
1410 (set (subreg:QI (match_operand:DI 3 "register_operand" "=0") 0)
1411 (truncate:QI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
1415 ;;- Divide instructions.
1417 (define_insn "divdf3"
1418 [(set (match_operand:DF 0 "general_operand" "=lm")
1419 (div:DF (match_operand:DF 1 "general_operand" "0")
1420 (match_operand:DF 2 "general_operand" "lmF")))]
1424 (define_insn "divsf3"
1425 [(set (match_operand:SF 0 "general_operand" "=fm")
1426 (div:SF (match_operand:SF 1 "general_operand" "0")
1427 (match_operand:SF 2 "general_operand" "fmF")))]
1432 (define_insn "divsi3"
1433 [(set (match_operand:SI 0 "general_operand" "=g")
1434 (div:SI (match_operand:SI 1 "general_operand" "0")
1435 (match_operand:SI 2 "general_operand" "g")))]
1439 (define_insn "divhi3"
1440 [(set (match_operand:HI 0 "general_operand" "=g")
1441 (div:HI (match_operand:HI 1 "general_operand" "0")
1442 (match_operand:HI 2 "general_operand" "g")))]
1446 (define_insn "divqi3"
1447 [(set (match_operand:QI 0 "general_operand" "=g")
1448 (div:QI (match_operand:QI 1 "general_operand" "0")
1449 (match_operand:QI 2 "general_operand" "g")))]
1453 ;; Remainder instructions.
1456 (define_insn "modsi3"
1457 [(set (match_operand:SI 0 "general_operand" "=g")
1458 (mod:SI (match_operand:SI 1 "general_operand" "0")
1459 (match_operand:SI 2 "general_operand" "g")))]
1463 (define_insn "modhi3"
1464 [(set (match_operand:HI 0 "general_operand" "=g")
1465 (mod:HI (match_operand:HI 1 "general_operand" "0")
1466 (match_operand:HI 2 "general_operand" "g")))]
1470 (define_insn "modqi3"
1471 [(set (match_operand:QI 0 "general_operand" "=g")
1472 (mod:QI (match_operand:QI 1 "general_operand" "0")
1473 (match_operand:QI 2 "general_operand" "g")))]
1478 ;;- Logical Instructions: AND
1481 (define_insn "andsi3"
1482 [(set (match_operand:SI 0 "general_operand" "=g")
1483 (and:SI (match_operand:SI 1 "general_operand" "%0")
1484 (match_operand:SI 2 "general_operand" "g")))]
1488 if (GET_CODE (operands[2]) == CONST_INT)
1490 if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1492 if (INTVAL (operands[2]) == 0xffffff00)
1493 return \"movqb %$0,%0\";
1496 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1497 return \"andb %2,%0\";
1500 if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1502 if (INTVAL (operands[2]) == 0xffff0000)
1503 return \"movqw %$0,%0\";
1506 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
1507 return \"andw %2,%0\";
1511 return \"andd %2,%0\";
1514 (define_insn "andhi3"
1515 [(set (match_operand:HI 0 "general_operand" "=g")
1516 (and:HI (match_operand:HI 1 "general_operand" "%0")
1517 (match_operand:HI 2 "general_operand" "g")))]
1521 if (GET_CODE (operands[2]) == CONST_INT
1522 && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1524 if (INTVAL (operands[2]) == 0xffffff00)
1525 return \"movqb %$0,%0\";
1528 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1529 return \"andb %2,%0\";
1532 return \"andw %2,%0\";
1535 (define_insn "andqi3"
1536 [(set (match_operand:QI 0 "general_operand" "=g")
1537 (and:QI (match_operand:QI 1 "general_operand" "%0")
1538 (match_operand:QI 2 "general_operand" "g")))]
1544 [(set (match_operand:SI 0 "general_operand" "=g")
1545 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
1546 (match_operand:SI 2 "general_operand" "0")))]
1551 [(set (match_operand:HI 0 "general_operand" "=g")
1552 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1553 (match_operand:HI 2 "general_operand" "0")))]
1558 [(set (match_operand:QI 0 "general_operand" "=g")
1559 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1560 (match_operand:QI 2 "general_operand" "0")))]
1564 ;;- Bit set instructions.
1567 (define_insn "iorsi3"
1568 [(set (match_operand:SI 0 "general_operand" "=g")
1569 (ior:SI (match_operand:SI 1 "general_operand" "%0")
1570 (match_operand:SI 2 "general_operand" "g")))]
1574 if (GET_CODE (operands[2]) == CONST_INT) {
1575 if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1576 return \"orb %2,%0\";
1577 if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1578 return \"orw %2,%0\";
1580 return \"ord %2,%0\";
1583 (define_insn "iorhi3"
1584 [(set (match_operand:HI 0 "general_operand" "=g")
1585 (ior:HI (match_operand:HI 1 "general_operand" "%0")
1586 (match_operand:HI 2 "general_operand" "g")))]
1590 if (GET_CODE(operands[2]) == CONST_INT &&
1591 (INTVAL(operands[2]) & 0xffffff00) == 0)
1592 return \"orb %2,%0\";
1593 return \"orw %2,%0\";
1596 (define_insn "iorqi3"
1597 [(set (match_operand:QI 0 "general_operand" "=g")
1598 (ior:QI (match_operand:QI 1 "general_operand" "%0")
1599 (match_operand:QI 2 "general_operand" "g")))]
1603 ;;- xor instructions.
1606 (define_insn "xorsi3"
1607 [(set (match_operand:SI 0 "general_operand" "=g")
1608 (xor:SI (match_operand:SI 1 "general_operand" "%0")
1609 (match_operand:SI 2 "general_operand" "g")))]
1613 if (GET_CODE (operands[2]) == CONST_INT) {
1614 if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1615 return \"xorb %2,%0\";
1616 if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1617 return \"xorw %2,%0\";
1619 return \"xord %2,%0\";
1622 (define_insn "xorhi3"
1623 [(set (match_operand:HI 0 "general_operand" "=g")
1624 (xor:HI (match_operand:HI 1 "general_operand" "%0")
1625 (match_operand:HI 2 "general_operand" "g")))]
1629 if (GET_CODE(operands[2]) == CONST_INT &&
1630 (INTVAL(operands[2]) & 0xffffff00) == 0)
1631 return \"xorb %2,%0\";
1632 return \"xorw %2,%0\";
1635 (define_insn "xorqi3"
1636 [(set (match_operand:QI 0 "general_operand" "=g")
1637 (xor:QI (match_operand:QI 1 "general_operand" "%0")
1638 (match_operand:QI 2 "general_operand" "g")))]
1642 (define_insn "negdf2"
1643 [(set (match_operand:DF 0 "general_operand" "=lm<")
1644 (neg:DF (match_operand:DF 1 "general_operand" "lmF")))]
1648 (define_insn "negsf2"
1649 [(set (match_operand:SF 0 "general_operand" "=fm<")
1650 (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1654 (define_insn "negdi2"
1655 [(set (match_operand:DI 0 "general_operand" "=ro")
1656 (neg:DI (match_operand:DI 1 "general_operand" "ro")))]
1660 rtx low[2], high[2], xops[4];
1661 split_di (operands, 2, low, high);
1667 if (rtx_equal_p (operands[0], operands[1]))
1669 output_asm_insn (\"negd %3,%1\", xops);
1670 output_asm_insn (\"negd %2,%0\", xops);
1671 output_asm_insn (\"subcd %$0,%1\", xops);
1675 output_asm_insn (\"negd %2,%0\", xops);
1676 output_asm_insn (\"movqd %$0,%1\", xops);
1677 output_asm_insn (\"subcd %3,%1\", xops);
1683 (define_insn "negsi2"
1684 [(set (match_operand:SI 0 "general_operand" "=g<")
1685 (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1689 (define_insn "neghi2"
1690 [(set (match_operand:HI 0 "general_operand" "=g<")
1691 (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1695 (define_insn "negqi2"
1696 [(set (match_operand:QI 0 "general_operand" "=g<")
1697 (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1702 (define_insn "one_cmplsi2"
1703 [(set (match_operand:SI 0 "general_operand" "=g<")
1704 (not:SI (match_operand:SI 1 "general_operand" "g")))]
1708 (define_insn "one_cmplhi2"
1709 [(set (match_operand:HI 0 "general_operand" "=g<")
1710 (not:HI (match_operand:HI 1 "general_operand" "g")))]
1714 (define_insn "one_cmplqi2"
1715 [(set (match_operand:QI 0 "general_operand" "=g<")
1716 (not:QI (match_operand:QI 1 "general_operand" "g")))]
1720 ;; arithmetic left and right shift operations
1721 ;; on the 32532 we will always use lshd for arithmetic left shifts,
1722 ;; because it is three times faster. Broken programs which
1723 ;; use negative shift counts are probably broken differently
1726 ;; alternative 0 never matches on the 32532
1728 (define_insn "ashlsi3"
1729 [(set (match_operand:SI 0 "general_operand" "=g,g")
1730 (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1731 (match_operand:SI 2 "general_operand" "I,g")))]
1735 return \"lshd %2,%0\";
1737 return output_shift_insn (operands);
1740 (define_insn "ashlhi3"
1741 [(set (match_operand:HI 0 "general_operand" "=g")
1742 (ashift:HI (match_operand:HI 1 "general_operand" "0")
1743 (match_operand:SI 2 "general_operand" "g")))]
1746 { if (GET_CODE (operands[2]) == CONST_INT)
1748 if (INTVAL (operands[2]) == 1)
1749 return \"addw %0,%0\";
1750 else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1751 return \"addw %0,%0\;addw %0,%0\";
1754 return \"lshw %2,%0\";
1756 return \"ashw %2,%0\";
1759 (define_insn "ashlqi3"
1760 [(set (match_operand:QI 0 "general_operand" "=g")
1761 (ashift:QI (match_operand:QI 1 "general_operand" "0")
1762 (match_operand:SI 2 "general_operand" "g")))]
1765 { if (GET_CODE (operands[2]) == CONST_INT)
1767 if (INTVAL (operands[2]) == 1)
1768 return \"addb %0,%0\";
1769 else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1770 return \"addb %0,%0\;addb %0,%0\";
1773 return \"lshb %2,%0\";
1775 return \"ashb %2,%0\";
1778 ;; Arithmetic right shift on the 32k works by negating the shift count.
1779 (define_expand "ashrsi3"
1780 [(set (match_operand:SI 0 "general_operand" "=g")
1781 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1782 (match_operand:SI 2 "general_operand" "g")))]
1786 if (GET_CODE (operands[2]) != CONST_INT)
1787 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1791 [(set (match_operand:SI 0 "general_operand" "=g")
1792 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1793 (match_operand:SI 2 "immediate_operand" "i")))]
1798 [(set (match_operand:SI 0 "general_operand" "=g")
1799 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1800 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1804 (define_expand "ashrhi3"
1805 [(set (match_operand:HI 0 "general_operand" "=g")
1806 (ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1807 (match_operand:SI 2 "general_operand" "g")))]
1811 if (GET_CODE (operands[2]) != CONST_INT)
1812 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1816 [(set (match_operand:HI 0 "general_operand" "=g")
1817 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1818 (match_operand:SI 2 "immediate_operand" "i")))]
1823 [(set (match_operand:HI 0 "general_operand" "=g")
1824 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1825 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1829 (define_expand "ashrqi3"
1830 [(set (match_operand:QI 0 "general_operand" "=g")
1831 (ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1832 (match_operand:SI 2 "general_operand" "g")))]
1836 if (GET_CODE (operands[2]) != CONST_INT)
1837 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1841 [(set (match_operand:QI 0 "general_operand" "=g")
1842 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1843 (match_operand:SI 2 "immediate_operand" "i")))]
1848 [(set (match_operand:QI 0 "general_operand" "=g")
1849 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1850 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1854 ;; logical shift instructions
1856 ;; Logical right shift on the 32k works by negating the shift count.
1857 (define_expand "lshrsi3"
1858 [(set (match_operand:SI 0 "general_operand" "=g")
1859 (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1860 (match_operand:SI 2 "general_operand" "g")))]
1864 if (GET_CODE (operands[2]) != CONST_INT)
1865 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1869 [(set (match_operand:SI 0 "general_operand" "=g")
1870 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1871 (match_operand:SI 2 "immediate_operand" "i")))]
1876 [(set (match_operand:SI 0 "general_operand" "=g")
1877 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1878 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1882 (define_expand "lshrhi3"
1883 [(set (match_operand:HI 0 "general_operand" "=g")
1884 (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1885 (match_operand:SI 2 "general_operand" "g")))]
1889 if (GET_CODE (operands[2]) != CONST_INT)
1890 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1894 [(set (match_operand:HI 0 "general_operand" "=g")
1895 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1896 (match_operand:SI 2 "immediate_operand" "i")))]
1901 [(set (match_operand:HI 0 "general_operand" "=g")
1902 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1903 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1907 (define_expand "lshrqi3"
1908 [(set (match_operand:QI 0 "general_operand" "=g")
1909 (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1910 (match_operand:SI 2 "general_operand" "g")))]
1914 if (GET_CODE (operands[2]) != CONST_INT)
1915 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1919 [(set (match_operand:QI 0 "general_operand" "=g")
1920 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1921 (match_operand:SI 2 "immediate_operand" "i")))]
1926 [(set (match_operand:QI 0 "general_operand" "=g")
1927 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1928 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1932 ;; Rotate instructions
1935 (define_insn "rotlsi3"
1936 [(set (match_operand:SI 0 "general_operand" "=g")
1937 (rotate:SI (match_operand:SI 1 "general_operand" "0")
1938 (match_operand:SI 2 "general_operand" "g")))]
1942 (define_insn "rotlhi3"
1943 [(set (match_operand:HI 0 "general_operand" "=g")
1944 (rotate:HI (match_operand:HI 1 "general_operand" "0")
1945 (match_operand:SI 2 "general_operand" "g")))]
1949 (define_insn "rotlqi3"
1950 [(set (match_operand:QI 0 "general_operand" "=g")
1951 (rotate:QI (match_operand:QI 1 "general_operand" "0")
1952 (match_operand:SI 2 "general_operand" "g")))]
1956 ;; Right rotate on the 32k works by negating the shift count.
1957 (define_expand "rotrsi3"
1958 [(set (match_operand:SI 0 "general_operand" "=g")
1959 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1960 (match_operand:SI 2 "general_operand" "g")))]
1964 if (GET_CODE (operands[2]) != CONST_INT)
1965 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1969 [(set (match_operand:SI 0 "general_operand" "=g")
1970 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1971 (match_operand:SI 2 "immediate_operand" "i")))]
1976 [(set (match_operand:SI 0 "general_operand" "=g")
1977 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1978 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1982 (define_expand "rotrhi3"
1983 [(set (match_operand:HI 0 "general_operand" "=g")
1984 (rotatert:HI (match_operand:HI 1 "general_operand" "g")
1985 (match_operand:SI 2 "general_operand" "g")))]
1989 if (GET_CODE (operands[2]) != CONST_INT)
1990 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1994 [(set (match_operand:HI 0 "general_operand" "=g")
1995 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1996 (match_operand:SI 2 "immediate_operand" "i")))]
2001 [(set (match_operand:HI 0 "general_operand" "=g")
2002 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
2003 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
2007 (define_expand "rotrqi3"
2008 [(set (match_operand:QI 0 "general_operand" "=g")
2009 (rotatert:QI (match_operand:QI 1 "general_operand" "g")
2010 (match_operand:SI 2 "general_operand" "g")))]
2014 if (GET_CODE (operands[2]) != CONST_INT)
2015 operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
2019 [(set (match_operand:QI 0 "general_operand" "=g")
2020 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
2021 (match_operand:SI 2 "immediate_operand" "i")))]
2026 [(set (match_operand:QI 0 "general_operand" "=g")
2027 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
2028 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
2032 ;;- load or push effective address
2033 ;; These come after the move, add, and multiply patterns
2034 ;; because we don't want pushl $1 turned into pushad 1.
2037 [(set (match_operand:SI 0 "general_operand" "=g<")
2038 (match_operand:QI 1 "address_operand" "p"))]
2042 if (REG_P (operands[0])
2043 && GET_CODE (operands[1]) == MULT
2044 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
2045 && (INTVAL (XEXP (operands[1], 1)) == 2
2046 || INTVAL (XEXP (operands[1], 1)) == 4))
2049 xoperands[0] = operands[0];
2050 xoperands[1] = XEXP (operands[1], 0);
2051 xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
2052 return output_shift_insn (xoperands);
2054 return \"addr %a1,%0\";
2057 ;;; Index insns. These are about the same speed as multiply-add counterparts.
2058 ;;; but slower then using power-of-2 shifts if we can use them
2062 ; [(set (match_operand:SI 0 "register_operand" "=r")
2063 ; (plus:SI (match_operand:SI 1 "general_operand" "g")
2064 ; (mult:SI (match_operand:SI 2 "register_operand" "0")
2065 ; (plus:SI (match_operand:SI 3 "general_operand" "g") (const_int 1)))))]
2066 ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
2067 ; "indexd %0,%3,%1")
2070 ; [(set (match_operand:SI 0 "register_operand" "=r")
2071 ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
2072 ; (plus:SI (match_operand:SI 2 "general_operand" "g") (const_int 1)))
2073 ; (match_operand:SI 3 "general_operand" "g")))]
2074 ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
2075 ; "indexd %0,%2,%3")
2077 ;; Set, Clear, and Invert bit
2081 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
2083 (match_operand:SI 1 "general_operand" "g"))
2090 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
2092 (match_operand:SI 1 "general_operand" "g"))
2099 [(set (match_operand:SI 0 "general_operand" "+g")
2100 (xor:SI (ashift:SI (const_int 1)
2101 (match_operand:SI 1 "general_operand" "g"))
2108 [(set (match_operand:QI 0 "general_operand" "=g")
2110 (ashift:SI (const_int 1)
2111 (match_operand:QI 1 "general_operand" "g")) 0)
2116 ;; Recognize jbs and jbc instructions.
2120 (zero_extract (match_operand:SI 0 "general_operand" "rm")
2122 (match_operand:SI 1 "general_operand" "g")))]
2125 { cc_status.flags = CC_Z_IN_F;
2126 return \"tbitd %1,%0\";
2129 ;; extract(base, width, offset)
2130 ;; Signed bitfield extraction is not supported in hardware on the
2131 ;; NS 32032. It is therefore better to let GCC figure out a
2132 ;; good strategy for generating the proper instruction sequence
2133 ;; and represent it as rtl.
2135 ;; Optimize the case of extracting a byte or word from a register.
2136 ;; Otherwise we must load a register with the offset of the
2137 ;; chunk we want, and perform an extract insn (each of which
2138 ;; is very expensive). Since we use the stack to do our bit-twiddling
2139 ;; we cannot use it for a destination. Perhaps things are fast
2140 ;; enough on the 32532 that such hacks are not needed.
2143 [(set (match_operand:SI 0 "general_operand" "=ro")
2144 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2145 (match_operand:SI 2 "const_int_operand" "i")
2146 (match_operand:SI 3 "const_int_operand" "i")))]
2147 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2148 && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
2151 output_asm_insn (\"movd %1,tos\", operands);
2152 if (INTVAL (operands[2]) == 16)
2154 if (INTVAL (operands[3]) == 8)
2155 output_asm_insn (\"movzwd 1(sp),%0\", operands);
2157 output_asm_insn (\"movzwd 2(sp),%0\", operands);
2161 if (INTVAL (operands[3]) == 8)
2162 output_asm_insn (\"movzbd 1(sp),%0\", operands);
2163 else if (INTVAL (operands[3]) == 16)
2164 output_asm_insn (\"movzbd 2(sp),%0\", operands);
2166 output_asm_insn (\"movzbd 3(sp),%0\", operands);
2168 if (TARGET_32532 || TARGET_32332)
2169 return \"cmpqd %$0,tos\";
2171 return \"adjspb %$-4\";
2174 ;; The exts/ext instructions have the problem that they always access
2175 ;; 32 bits even if the bitfield is smaller. For example the instruction
2176 ;; extsd 7(r1),r0,2,5
2177 ;; would read not only at address 7(r1) but also at 8(r1) to 10(r1).
2178 ;; If these addresses are in a different (unmapped) page a memory fault
2181 ;; Timing considerations:
2182 ;; movd 0(r1),r0 3 bytes
2185 ;; takes about 13 cycles on the 532 while
2186 ;; extsd 7(r1),r0,2,5 5 bytes
2187 ;; takes about 21 cycles.
2189 ;; The inss/ins instructions suffer from the same problem.
2191 ;; A machine specific option (-mbitfield/-mnobitfield) is used
2192 ;; to allow/disallow the use of these instructions.
2195 [(set (match_operand:SI 0 "general_operand" "=g<")
2196 (zero_extract:SI (match_operand:SI 1 "register_operand" "g")
2197 (match_operand:SI 2 "const_int_operand" "i")
2198 (match_operand:SI 3 "general_operand" "rK")))]
2201 { if (GET_CODE (operands[3]) == CONST_INT)
2202 return \"extsd %1,%0,%3,%2\";
2203 else return \"extd %3,%1,%0,%2\";
2206 (define_insn "extzv"
2207 [(set (match_operand:SI 0 "general_operand" "=g<")
2208 (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
2209 (match_operand:SI 2 "const_int_operand" "i")
2210 (match_operand:SI 3 "general_operand" "rK")))]
2213 { if (GET_CODE (operands[3]) == CONST_INT)
2214 return \"extsd %1,%0,%3,%2\";
2215 else return \"extd %3,%1,%0,%2\";
2219 [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
2220 (match_operand:SI 1 "const_int_operand" "i")
2221 (match_operand:SI 2 "general_operand" "rn"))
2222 (match_operand:SI 3 "general_operand" "rm"))]
2225 { if (GET_CODE (operands[2]) == CONST_INT)
2227 if (INTVAL (operands[2]) >= 8)
2229 operands[0] = adj_offsettable_operand (operands[0],
2230 INTVAL (operands[2]) / 8);
2231 operands[2] = GEN_INT (INTVAL (operands[2]) % 8);
2233 if (INTVAL (operands[1]) <= 8)
2234 return \"inssb %3,%0,%2,%1\";
2235 else if (INTVAL (operands[1]) <= 16)
2236 return \"inssw %3,%0,%2,%1\";
2238 return \"inssd %3,%0,%2,%1\";
2240 return \"insd %2,%3,%0,%1\";
2244 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2245 (match_operand:SI 1 "const_int_operand" "i")
2246 (match_operand:SI 2 "general_operand" "rK"))
2247 (match_operand:SI 3 "general_operand" "rm"))]
2250 { if (GET_CODE (operands[2]) == CONST_INT)
2251 if (INTVAL (operands[1]) <= 8)
2252 return \"inssb %3,%0,%2,%1\";
2253 else if (INTVAL (operands[1]) <= 16)
2254 return \"inssw %3,%0,%2,%1\";
2256 return \"inssd %3,%0,%2,%1\";
2257 return \"insd %2,%3,%0,%1\";
2261 [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
2262 (match_operand:SI 1 "const_int_operand" "i")
2263 (match_operand:SI 2 "general_operand" "rK"))
2264 (match_operand:SI 3 "general_operand" "rm"))]
2267 { if (GET_CODE (operands[2]) == CONST_INT)
2268 if (INTVAL (operands[1]) <= 8)
2269 return \"inssb %3,%0,%2,%1\";
2270 else if (INTVAL (operands[1]) <= 16)
2271 return \"inssw %3,%0,%2,%1\";
2273 return \"inssd %3,%0,%2,%1\";
2274 return \"insd %2,%3,%0,%1\";
2280 (label_ref (match_operand 0 "" "")))]
2286 (if_then_else (eq (cc0)
2288 (label_ref (match_operand 0 "" ""))
2292 { if (cc_prev_status.flags & CC_Z_IN_F)
2294 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2296 else return \"beq %l0\";
2301 (if_then_else (ne (cc0)
2303 (label_ref (match_operand 0 "" ""))
2307 { if (cc_prev_status.flags & CC_Z_IN_F)
2309 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2311 else return \"bne %l0\";
2316 (if_then_else (gt (cc0)
2318 (label_ref (match_operand 0 "" ""))
2325 (if_then_else (gtu (cc0)
2327 (label_ref (match_operand 0 "" ""))
2334 (if_then_else (lt (cc0)
2336 (label_ref (match_operand 0 "" ""))
2343 (if_then_else (ltu (cc0)
2345 (label_ref (match_operand 0 "" ""))
2352 (if_then_else (ge (cc0)
2354 (label_ref (match_operand 0 "" ""))
2361 (if_then_else (geu (cc0)
2363 (label_ref (match_operand 0 "" ""))
2370 (if_then_else (le (cc0)
2372 (label_ref (match_operand 0 "" ""))
2379 (if_then_else (leu (cc0)
2381 (label_ref (match_operand 0 "" ""))
2388 (if_then_else (eq (cc0)
2391 (label_ref (match_operand 0 "" ""))))]
2394 { if (cc_prev_status.flags & CC_Z_IN_F)
2396 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2398 else return \"bne %l0\";
2403 (if_then_else (ne (cc0)
2406 (label_ref (match_operand 0 "" ""))))]
2409 { if (cc_prev_status.flags & CC_Z_IN_F)
2411 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2413 else return \"beq %l0\";
2418 (if_then_else (gt (cc0)
2421 (label_ref (match_operand 0 "" ""))))]
2427 (if_then_else (gtu (cc0)
2430 (label_ref (match_operand 0 "" ""))))]
2436 (if_then_else (lt (cc0)
2439 (label_ref (match_operand 0 "" ""))))]
2445 (if_then_else (ltu (cc0)
2448 (label_ref (match_operand 0 "" ""))))]
2454 (if_then_else (ge (cc0)
2457 (label_ref (match_operand 0 "" ""))))]
2463 (if_then_else (geu (cc0)
2466 (label_ref (match_operand 0 "" ""))))]
2472 (if_then_else (le (cc0)
2475 (label_ref (match_operand 0 "" ""))))]
2481 (if_then_else (leu (cc0)
2484 (label_ref (match_operand 0 "" ""))))]
2488 ;; Subtract-and-jump and Add-and-jump insns.
2489 ;; These can actually be used for adding numbers in the range -8 to 7
2494 (ne (match_operand:SI 0 "general_operand" "+g")
2495 (match_operand:SI 1 "const_int_operand" "i"))
2496 (label_ref (match_operand 2 "" ""))
2499 (minus:SI (match_dup 0)
2501 "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2507 (ne (match_operand:SI 0 "general_operand" "+g")
2508 (match_operand:SI 1 "const_int_operand" "i"))
2509 (label_ref (match_operand 2 "" ""))
2512 (plus:SI (match_dup 0)
2513 (match_operand:SI 3 "const_int_operand" "i")))]
2514 "INTVAL (operands[1]) == - INTVAL (operands[3])
2515 && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2519 [(call (match_operand:QI 0 "memory_operand" "m")
2520 (match_operand:QI 1 "general_operand" "g"))]
2525 if (GET_CODE (operands[0]) == MEM)
2527 rtx temp = XEXP (operands[0], 0);
2528 if (CONSTANT_ADDRESS_P (temp))
2531 return \"bsr %?%0\";
2533 #ifdef CALL_MEMREF_IMPLICIT
2540 return \"bsr %?%a0\";
2545 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2546 #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2552 #endif /* not JSR_ALWAYS */
2556 (define_insn "call_value"
2557 [(set (match_operand 0 "" "=rf")
2558 (call (match_operand:QI 1 "memory_operand" "m")
2559 (match_operand:QI 2 "general_operand" "g")))]
2564 if (GET_CODE (operands[1]) == MEM)
2566 rtx temp = XEXP (operands[1], 0);
2567 if (CONSTANT_ADDRESS_P (temp))
2570 return \"bsr %?%1\";
2572 #ifdef CALL_MEMREF_IMPLICIT
2579 return \"bsr %?%a1\";
2584 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2585 #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2591 #endif /* not JSR_ALWAYS */
2595 ;; Call subroutine returning any type.
2597 (define_expand "untyped_call"
2598 [(parallel [(call (match_operand 0 "" "")
2600 (match_operand 1 "" "")
2601 (match_operand 2 "" "")])]
2607 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2609 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2611 rtx set = XVECEXP (operands[2], 0, i);
2612 emit_move_insn (SET_DEST (set), SET_SRC (set));
2615 /* The optimizer does not know that the call sets the function value
2616 registers we stored in the result block. We avoid problems by
2617 claiming that all hard registers are used and clobbered at this
2619 emit_insn (gen_blockage ());
2624 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2625 ;; all of memory. This blocks insns from being moved across this point.
2627 (define_insn "blockage"
2628 [(unspec_volatile [(const_int 0)] 0)]
2632 (define_insn "return"
2637 (define_insn "abssf2"
2638 [(set (match_operand:SF 0 "general_operand" "=fm<")
2639 (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2643 (define_insn "absdf2"
2644 [(set (match_operand:DF 0 "general_operand" "=lm<")
2645 (abs:DF (match_operand:DF 1 "general_operand" "lmF")))]
2650 (define_insn "abssi2"
2651 [(set (match_operand:SI 0 "general_operand" "=g<")
2652 (abs:SI (match_operand:SI 1 "general_operand" "g")))]
2656 (define_insn "abshi2"
2657 [(set (match_operand:HI 0 "general_operand" "=g<")
2658 (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2662 (define_insn "absqi2"
2663 [(set (match_operand:QI 0 "general_operand" "=g<")
2664 (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2673 (define_insn "indirect_jump"
2674 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2678 (define_insn "tablejump"
2680 (plus:SI (pc) (match_operand:SI 0 "general_operand" "g")))
2681 (use (label_ref (match_operand 1 "" "")))]
2685 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2686 CODE_LABEL_NUMBER (operands[1]));
2687 return \"cased %0\";
2690 ;; Scondi instructions
2692 [(set (match_operand:SI 0 "general_operand" "=g<")
2693 (eq:SI (cc0) (const_int 0)))]
2696 { if (cc_prev_status.flags & CC_Z_IN_F)
2698 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2700 else return \"seqd %0\";
2704 [(set (match_operand:HI 0 "general_operand" "=g<")
2705 (eq:HI (cc0) (const_int 0)))]
2708 { if (cc_prev_status.flags & CC_Z_IN_F)
2710 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2712 else return \"seqw %0\";
2716 [(set (match_operand:QI 0 "general_operand" "=g<")
2717 (eq:QI (cc0) (const_int 0)))]
2720 { if (cc_prev_status.flags & CC_Z_IN_F)
2722 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2724 else return \"seqb %0\";
2728 [(set (match_operand:SI 0 "general_operand" "=g<")
2729 (ne:SI (cc0) (const_int 0)))]
2732 { if (cc_prev_status.flags & CC_Z_IN_F)
2734 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2736 else return \"sned %0\";
2740 [(set (match_operand:HI 0 "general_operand" "=g<")
2741 (ne:HI (cc0) (const_int 0)))]
2744 { if (cc_prev_status.flags & CC_Z_IN_F)
2746 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2748 else return \"snew %0\";
2752 [(set (match_operand:QI 0 "general_operand" "=g<")
2753 (ne:QI (cc0) (const_int 0)))]
2756 { if (cc_prev_status.flags & CC_Z_IN_F)
2758 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2760 else return \"sneb %0\";
2764 [(set (match_operand:SI 0 "general_operand" "=g<")
2765 (gt:SI (cc0) (const_int 0)))]
2770 [(set (match_operand:HI 0 "general_operand" "=g<")
2771 (gt:HI (cc0) (const_int 0)))]
2776 [(set (match_operand:QI 0 "general_operand" "=g<")
2777 (gt:QI (cc0) (const_int 0)))]
2782 [(set (match_operand:SI 0 "general_operand" "=g<")
2783 (gtu:SI (cc0) (const_int 0)))]
2788 [(set (match_operand:HI 0 "general_operand" "=g<")
2789 (gtu:HI (cc0) (const_int 0)))]
2794 [(set (match_operand:QI 0 "general_operand" "=g<")
2795 (gtu:QI (cc0) (const_int 0)))]
2800 [(set (match_operand:SI 0 "general_operand" "=g<")
2801 (lt:SI (cc0) (const_int 0)))]
2806 [(set (match_operand:HI 0 "general_operand" "=g<")
2807 (lt:HI (cc0) (const_int 0)))]
2812 [(set (match_operand:QI 0 "general_operand" "=g<")
2813 (lt:QI (cc0) (const_int 0)))]
2818 [(set (match_operand:SI 0 "general_operand" "=g<")
2819 (ltu:SI (cc0) (const_int 0)))]
2824 [(set (match_operand:HI 0 "general_operand" "=g<")
2825 (ltu:HI (cc0) (const_int 0)))]
2830 [(set (match_operand:QI 0 "general_operand" "=g<")
2831 (ltu:QI (cc0) (const_int 0)))]
2836 [(set (match_operand:SI 0 "general_operand" "=g<")
2837 (ge:SI (cc0) (const_int 0)))]
2842 [(set (match_operand:HI 0 "general_operand" "=g<")
2843 (ge:HI (cc0) (const_int 0)))]
2848 [(set (match_operand:QI 0 "general_operand" "=g<")
2849 (ge:QI (cc0) (const_int 0)))]
2854 [(set (match_operand:SI 0 "general_operand" "=g<")
2855 (geu:SI (cc0) (const_int 0)))]
2860 [(set (match_operand:HI 0 "general_operand" "=g<")
2861 (geu:HI (cc0) (const_int 0)))]
2866 [(set (match_operand:QI 0 "general_operand" "=g<")
2867 (geu:QI (cc0) (const_int 0)))]
2872 [(set (match_operand:SI 0 "general_operand" "=g<")
2873 (le:SI (cc0) (const_int 0)))]
2878 [(set (match_operand:HI 0 "general_operand" "=g<")
2879 (le:HI (cc0) (const_int 0)))]
2884 [(set (match_operand:QI 0 "general_operand" "=g<")
2885 (le:QI (cc0) (const_int 0)))]
2890 [(set (match_operand:SI 0 "general_operand" "=g<")
2891 (leu:SI (cc0) (const_int 0)))]
2896 [(set (match_operand:HI 0 "general_operand" "=g<")
2897 (leu:HI (cc0) (const_int 0)))]
2902 [(set (match_operand:QI 0 "general_operand" "=g<")
2903 (leu:QI (cc0) (const_int 0)))]
2910 [(set (match_operand:SI 0 "general_operand" "ro")
2912 (plus:SI (ffs:SI (zero_extract:SI
2913 (match_operand:SI 1 "general_operand" "g")
2914 (minus:SI (const_int 32) (match_dup 0))
2919 "ffsd %1,%0; bfc 1f; addqd %$-1,%0; 1:")
2921 (define_expand "ffssi2"
2922 [(set (match_operand:SI 0 "general_operand" "=g") (const_int 0))
2925 (plus:SI (ffs:SI (zero_extract:SI
2926 (match_operand:SI 1 "general_operand" "g")
2927 (minus:SI (const_int 32) (match_dup 0))
2932 (plus:SI (match_dup 0)
2935 "operands[1] = make_safe_from(operands[1], operands[0]);")
2937 ;; Speed up stack adjust followed by a HI fixedpoint push.
2940 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2941 (set (match_operand:HI 0 "push_operand" "=m")
2942 (match_operand:HI 1 "general_operand" "g"))]
2943 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2946 if (GET_CODE (operands[1]) == CONST_INT)
2947 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
2950 output_asm_insn (\"movzwd %1,tos\", operands);
2954 ;; Speed up stack adjust followed by a zero_extend:HI(QI) fixedpoint push.
2957 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2958 (set (match_operand:HI 0 "push_operand" "=m")
2959 (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2960 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2963 if (GET_CODE (operands[1]) == CONST_INT)
2964 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
2967 output_asm_insn (\"movzbd %1,tos\", operands);
2971 ;; Speed up stack adjust followed by a sign_extend:HI(QI) fixedpoint push.
2974 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -2)))
2975 (set (match_operand:HI 0 "push_operand" "=m")
2976 (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2977 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2980 if (GET_CODE (operands[1]) == CONST_INT)
2981 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
2984 output_asm_insn (\"movxbd %1,tos\", operands);
2988 ;; Speed up stack adjust followed by a QI fixedpoint push.
2991 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int -3)))
2992 (set (match_operand:QI 0 "push_operand" "=m")
2993 (match_operand:QI 1 "general_operand" "g"))]
2994 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2997 if (GET_CODE (operands[1]) == CONST_INT)
2998 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,tos\"),
3001 output_asm_insn (\"movzbd %1,tos\", operands);
3005 ;; Speed up stack adjust followed by a SI fixedpoint push.
3008 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int 4)))
3009 (set (match_operand:SI 0 "push_operand" "=m")
3010 (match_operand:SI 1 "general_operand" "g"))]
3011 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
3014 if (GET_CODE (operands[1]) == CONST_INT)
3015 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,0(sp)\"),
3017 else if (GET_CODE (operands[1]) != REG
3018 && GET_CODE (operands[1]) != MEM
3019 && address_operand (operands[1], SImode))
3020 output_asm_insn (\"addr %a1,0(sp)\", operands);
3022 output_asm_insn (\"movd %1,0(sp)\", operands);
3026 ;; Speed up stack adjust followed by two fullword fixedpoint pushes.
3029 [(set (reg:SI 25) (plus:SI (reg:SI 25) (const_int 8)))
3030 (set (match_operand:SI 0 "push_operand" "=m")
3031 (match_operand:SI 1 "general_operand" "g"))
3032 (set (match_operand:SI 2 "push_operand" "=m")
3033 (match_operand:SI 3 "general_operand" "g"))]
3034 "! reg_mentioned_p (stack_pointer_rtx, operands[1])
3035 && ! reg_mentioned_p (stack_pointer_rtx, operands[3])"
3038 if (GET_CODE (operands[1]) == CONST_INT)
3039 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%1,4(sp)\"),
3041 else if (GET_CODE (operands[1]) != REG
3042 && GET_CODE (operands[1]) != MEM
3043 && address_operand (operands[1], SImode))
3044 output_asm_insn (\"addr %a1,4(sp)\", operands);
3046 output_asm_insn (\"movd %1,4(sp)\", operands);
3048 if (GET_CODE (operands[3]) == CONST_INT)
3049 output_asm_insn (output_move_dconst (INTVAL (operands[3]), \"%3,0(sp)\"),
3051 else if (GET_CODE (operands[3]) != REG
3052 && GET_CODE (operands[3]) != MEM
3053 && address_operand (operands[3], SImode))
3054 output_asm_insn (\"addr %a3,0(sp)\", operands);
3056 output_asm_insn (\"movd %3,0(sp)\", operands);