1 ;;- Machine description for the pdp11 for GNU C compiler
2 ;; Copyright (C) 1994, 1995, 1997, 1999 Free Software Foundation, Inc.
3 ;; Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 1, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29 ;;- updates for most instructions.
31 ;;- Operand classes for the register allocator:
33 ;; Compare instructions.
35 ;; currently we only support df floats, which saves us quite some
36 ;; hassle switching the FP mode!
37 ;; we assume that CPU is always in long float mode, and
38 ;; 16 bit integer mode - currently, the prologue for main does this,
39 ;; but maybe we should just set up a NEW crt0 properly,
40 ;; -- and what about signal handling code?
41 ;; (we don't even let sf floats in the register file, so
42 ;; we only should have to worry about truncating and widening
43 ;; when going to memory)
45 ;; abort() call by g++ - must define libfunc for cmp_optab
46 ;; and ucmp_optab for mode SImode, because we don't have that!!!
47 ;; - yet since no libfunc is there, we abort ()
49 ;; The only thing that remains to be done then is output
50 ;; the floats in a way the assembler can handle it (and
51 ;; if you're really into it, use a PDP11 float emulation
52 ;; library to do floating point constant folding - but
53 ;; I guess you'll get reasonable results even when not
55 ;; the last thing to do is fix the UPDATE_CC macro to check
56 ;; for floating point condition codes, and set cc_status
57 ;; properly, also setting the CC_IN_FCCR flag.
60 ;; currently type is only fpu or arith or unknown, maybe branch later ?
62 (define_attr "type" "unknown,arith,fp" (const_string "arith"))
64 ;; length default is 1 word each
65 (define_attr "length" "" (const_int 1))
67 ;; a user's asm statement
68 (define_asm_attributes
69 [(set_attr "type" "unknown")
70 ; all bets are off how long it is - make it 256, forces long jumps
71 ; whenever jumping around it !!!
72 (set_attr "length" "256")])
74 ;; define function units
76 ;; arithmetic - values here immediately when next insn issued
77 ;; or does it mean the number of cycles after this insn was issued?
78 ;; how do I say that fpu insns use cpu also? (pre-interaction phase)
80 ;(define_function_unit "cpu" 1 1 (eq_attr "type" "arith") 0 0)
81 ;(define_function_unit "fpu" 1 1 (eq_attr "type" "fp") 0 0)
86 (compare (match_operand:DF 0 "general_operand" "fR,Q,F")
87 (match_operand:DF 1 "register_operand" "a,a,a")))]
91 cc_status.flags = CC_IN_FPU;
92 return \"{cmpd|cmpf} %0, %1\;cfcc\";
94 [(set_attr "length" "2,3,6")])
96 ;; a bit of brain damage, maybe inline later -
97 ;; problem is - gcc seems to NEED SImode because
98 ;; of the cmp weirdness - maybe change gcc to handle this?
100 (define_expand "cmpsi"
102 (match_operand:SI 0 "general_operand" "g"))
104 (match_operand:SI 1 "general_operand" "g"))
105 (parallel [(set (cc0)
108 (clobber (reg:SI 0))])]
109 "0" ;; disable for test
112 ;; check for next insn for branch code - does this still
119 (clobber (reg:SI 0))]
123 rtx br_insn = NEXT_INSN (insn);
126 if (GET_CODE (br_insn) != JUMP_INSN)
128 br_code = GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
137 return \"jsr pc, ___ucmpsi\;cmp $1,r0\";
146 return \"jsr pc, ___cmpsi\;tst r0\";
153 [(set_attr "length" "4")])
158 (compare (match_operand:HI 0 "general_operand" "rR,rR,Qi,Qi")
159 (match_operand:HI 1 "general_operand" "rR,Qi,rR,Qi")))]
162 [(set_attr "length" "1,2,2,3")])
166 (compare (match_operand:QI 0 "general_operand" "rR,rR,Qi,Qi")
167 (match_operand:QI 1 "general_operand" "rR,Qi,rR,Qi")))]
170 [(set_attr "length" "1,2,2,3")])
173 ;; We have to have this because cse can optimize the previous pattern
178 (match_operand:DF 0 "general_operand" "fR,Q"))]
182 cc_status.flags = CC_IN_FPU;
183 return \"{tstd|tstf} %0\;cfcc\";
185 [(set_attr "length" "2,3")])
188 (define_expand "tstsi"
190 (match_operand:SI 0 "general_operand" "g"))
191 (parallel [(set (cc0)
193 (clobber (reg:SI 0))])]
194 "0" ;; disable for test
200 (clobber (reg:SI 0))]
202 "jsr pc, ___tstsi\;tst r0"
203 [(set_attr "length" "3")])
208 (match_operand:HI 0 "general_operand" "rR,Q"))]
211 [(set_attr "length" "1,2")])
215 (match_operand:QI 0 "general_operand" "rR,Q"))]
218 [(set_attr "length" "1,2")])
220 ;; sob instruction - we need an assembler which can make this instruction
221 ;; valid under _all_ circumstances!
226 (ne (plus:HI (match_operand:HI 0 "register_operand" "r")
229 (label_ref (match_operand 1 "" ""))
232 (plus:HI (match_dup 0)
237 static int labelcount = 0;
238 static char buf[1000];
240 if (get_attr_length (insn) == 1)
241 return \"sob %0, %l1\";
244 output_asm_insn (\"dec %0\", operands);
246 sprintf (buf, \"bge LONG_SOB%d\", labelcount);
247 output_asm_insn (buf, NULL);
249 output_asm_insn (\"jmp %l1\", operands);
251 sprintf (buf, \"LONG_SOB%d:\", labelcount++);
252 output_asm_insn (buf, NULL);
256 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
259 (ge (minus (match_dup 0)
265 ;; These control RTL generation for conditional jump insns
266 ;; and match them for register allocation.
268 ;; problem with too short jump distance! we need an assembler which can
269 ;; make this valid for all jump distances!
272 ;; these must be changed to check for CC_IN_FCCR if float is to be
277 (if_then_else (eq (cc0)
279 (label_ref (match_operand 0 "" ""))
282 "* return output_jump(\"beq\", \"bne\", get_attr_length(insn));"
283 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
286 (ge (minus (match_dup 0)
295 (if_then_else (ne (cc0)
297 (label_ref (match_operand 0 "" ""))
300 "* return output_jump(\"bne\", \"beq\", get_attr_length(insn));"
301 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
304 (ge (minus (match_dup 0)
312 (if_then_else (gt (cc0)
314 (label_ref (match_operand 0 "" ""))
317 "* return output_jump(\"bgt\", \"ble\", get_attr_length(insn));"
318 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
321 (ge (minus (match_dup 0)
329 (if_then_else (gtu (cc0)
331 (label_ref (match_operand 0 "" ""))
334 "* return output_jump(\"bhi\", \"blos\", get_attr_length(insn));"
335 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
338 (ge (minus (match_dup 0)
346 (if_then_else (lt (cc0)
348 (label_ref (match_operand 0 "" ""))
351 "* return output_jump(\"blt\", \"bge\", get_attr_length(insn));"
352 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
355 (ge (minus (match_dup 0)
364 (if_then_else (ltu (cc0)
366 (label_ref (match_operand 0 "" ""))
369 "* return output_jump(\"blo\", \"bhis\", get_attr_length(insn));"
370 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
373 (ge (minus (match_dup 0)
381 (if_then_else (ge (cc0)
383 (label_ref (match_operand 0 "" ""))
386 "* return output_jump(\"bge\", \"blt\", get_attr_length(insn));"
387 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
390 (ge (minus (match_dup 0)
398 (if_then_else (geu (cc0)
400 (label_ref (match_operand 0 "" ""))
403 "* return output_jump(\"bhis\", \"blo\", get_attr_length(insn));"
404 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
407 (ge (minus (match_dup 0)
415 (if_then_else (le (cc0)
417 (label_ref (match_operand 0 "" ""))
420 "* return output_jump(\"ble\", \"bgt\", get_attr_length(insn));"
421 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
424 (ge (minus (match_dup 0)
432 (if_then_else (leu (cc0)
434 (label_ref (match_operand 0 "" ""))
437 "* return output_jump(\"blos\", \"bhi\", get_attr_length(insn));"
438 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
441 (ge (minus (match_dup 0)
448 ;; These match inverted jump insns for register allocation.
452 (if_then_else (eq (cc0)
455 (label_ref (match_operand 0 "" ""))))]
457 "* return output_jump(\"bne\", \"beq\", get_attr_length(insn));"
458 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
461 (ge (minus (match_dup 0)
469 (if_then_else (ne (cc0)
472 (label_ref (match_operand 0 "" ""))))]
474 "* return output_jump(\"beq\", \"bne\", get_attr_length(insn));"
475 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
478 (ge (minus (match_dup 0)
486 (if_then_else (gt (cc0)
489 (label_ref (match_operand 0 "" ""))))]
491 "* return output_jump(\"ble\", \"bgt\", get_attr_length(insn));"
492 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
495 (ge (minus (match_dup 0)
503 (if_then_else (gtu (cc0)
506 (label_ref (match_operand 0 "" ""))))]
508 "* return output_jump(\"blos\", \"bhi\", get_attr_length(insn));"
509 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
512 (ge (minus (match_dup 0)
520 (if_then_else (lt (cc0)
523 (label_ref (match_operand 0 "" ""))))]
525 "* return output_jump(\"bge\", \"blt\", get_attr_length(insn));"
526 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
529 (ge (minus (match_dup 0)
537 (if_then_else (ltu (cc0)
540 (label_ref (match_operand 0 "" ""))))]
542 "* return output_jump(\"bhis\", \"blo\", get_attr_length(insn));"
543 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
546 (ge (minus (match_dup 0)
554 (if_then_else (ge (cc0)
557 (label_ref (match_operand 0 "" ""))))]
559 "* return output_jump(\"blt\", \"bge\", get_attr_length(insn));"
560 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
563 (ge (minus (match_dup 0)
571 (if_then_else (geu (cc0)
574 (label_ref (match_operand 0 "" ""))))]
576 "* return output_jump(\"blo\", \"bhis\", get_attr_length(insn));"
577 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
580 (ge (minus (match_dup 0)
588 (if_then_else (le (cc0)
591 (label_ref (match_operand 0 "" ""))))]
593 "* return output_jump(\"bgt\", \"ble\", get_attr_length(insn));"
594 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
597 (ge (minus (match_dup 0)
605 (if_then_else (leu (cc0)
608 (label_ref (match_operand 0 "" ""))))]
610 "* return output_jump(\"bhi\", \"blos\", get_attr_length(insn));"
611 [(set (attr "length") (if_then_else (ior (le (minus (match_dup 0)
614 (ge (minus (match_dup 0)
623 [(set (match_operand:DI 0 "general_operand" "=g")
624 (match_operand:DI 1 "general_operand" "g"))]
626 "* return output_move_quad (operands);"
627 ;; what's the mose expensive code - say twice movsi = 16
628 [(set_attr "length" "16")])
631 [(set (match_operand:SI 0 "general_operand" "=r,r,r,rm,m")
632 (match_operand:SI 1 "general_operand" "rN,IJ,K,m,r"))]
634 "* return output_move_double (operands);"
635 ;; what's the most expensive code ? - I think 8!
636 ;; we could split it up and make several sub-cases...
637 [(set_attr "length" "2,3,4,8,8")])
640 [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
641 (match_operand:HI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
645 if (operands[1] == const0_rtx)
648 return \"mov %1, %0\";
650 [(set_attr "length" "1,2,2,3")])
653 [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
654 (match_operand:QI 1 "general_operand" "rRN,Qi,rRN,Qi"))]
658 if (operands[1] == const0_rtx)
661 return \"movb %1, %0\";
663 [(set_attr "length" "1,2,2,3")])
665 ;; do we have to supply all these moves? e.g. to
666 ;; NO_LOAD_FPU_REGs ?
668 [(set (match_operand:DF 0 "general_operand" "=f,R,f,Q,f,m")
669 (match_operand:DF 1 "general_operand" "fR,f,Q,f,F,m"))]
671 "* return output_move_quad (operands);"
673 [(set_attr "length" "1,1,2,2,5,16")])
676 [(set (match_operand:SF 0 "general_operand" "=g,r,g")
677 (match_operand:SF 1 "general_operand" "r,rmF,g"))]
679 "* return output_move_double (operands);"
680 [(set_attr "length" "8,8,8")])
682 ;; maybe fiddle a bit with move_ratio, then
683 ;; let constraints only accept a register ...
685 (define_expand "movstrhi"
686 [(parallel [(set (match_operand:BLK 0 "general_operand" "=g,g")
687 (match_operand:BLK 1 "general_operand" "g,g"))
688 (use (match_operand:HI 2 "arith_operand" "n,&mr"))
689 (use (match_operand:HI 3 "immediate_operand" "i,i"))
690 (clobber (match_scratch:HI 4 "=&r,X"))
691 (clobber (match_dup 5))
692 (clobber (match_dup 6))
693 (clobber (match_dup 2))])]
694 "(TARGET_BCOPY_BUILTIN)"
698 = change_address (operands[0], VOIDmode,
699 copy_to_mode_reg (Pmode, XEXP (operands[0], 0)));
701 = change_address (operands[1], VOIDmode,
702 copy_to_mode_reg (Pmode, XEXP (operands[1], 0)));
704 operands[5] = XEXP (operands[0], 0);
705 operands[6] = XEXP (operands[1], 0);
709 (define_insn "" ; "movstrhi"
710 [(set (mem:BLK (match_operand:HI 0 "general_operand" "=r,r"))
711 (mem:BLK (match_operand:HI 1 "general_operand" "r,r")))
712 (use (match_operand:HI 2 "arith_operand" "n,&r"))
713 (use (match_operand:HI 3 "immediate_operand" "i,i"))
714 (clobber (match_scratch:HI 4 "=&r,X"))
715 (clobber (match_dup 0))
716 (clobber (match_dup 1))
717 (clobber (match_dup 2))]
718 "(TARGET_BCOPY_BUILTIN)"
719 "* return output_block_move (operands);"
721 [(set_attr "length" "40")])
725 ;;- truncation instructions
727 (define_insn "truncdfsf2"
728 [(set (match_operand:SF 0 "general_operand" "=r,R,Q")
729 (float_truncate:SF (match_operand:DF 1 "register_operand" "a,a,a")))]
731 "* if (which_alternative ==0)
733 output_asm_insn(\"{stcdf|movfo} %1, -(sp)\", operands);
734 output_asm_insn(\"mov (sp)+, %0\", operands);
735 operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
736 output_asm_insn(\"mov (sp)+, %0\", operands);
739 else if (which_alternative == 1)
740 return \"{stcdf|movfo} %1, %0\";
742 return \"{stcdf|movfo} %1, %0\";
744 [(set_attr "length" "3,1,2")])
747 (define_expand "truncsihi2"
748 [(set (match_operand:HI 0 "general_operand" "=g")
750 (match_operand:SI 1 "general_operand" "or")
756 ;;- zero extension instructions
758 (define_insn "zero_extendqihi2"
759 [(set (match_operand:HI 0 "general_operand" "=r")
760 (zero_extend:HI (match_operand:QI 1 "general_operand" "0")))]
763 [(set_attr "length" "2")])
765 (define_expand "zero_extendhisi2"
769 (match_operand:HI 1 "register_operand" "r"))
771 (match_operand:SI 0 "register_operand" "=r")
775 "/* operands[1] = make_safe_from (operands[1], operands[0]); */")
778 ;;- sign extension instructions
780 (define_insn "extendsfdf2"
781 [(set (match_operand:DF 0 "register_operand" "=a,a,a")
782 (float_extend:DF (match_operand:SF 1 "general_operand" "r,R,Q")))]
785 mov %1, -(sp)\;{ldcfd|movof} (sp)+,%0
787 {ldcfd|movof} %1, %0"
788 [(set_attr "length" "2,1,2")])
790 ;; does movb sign extend in register-to-register move?
791 (define_insn "extendqihi2"
792 [(set (match_operand:HI 0 "register_operand" "=r,r")
793 (sign_extend:HI (match_operand:QI 1 "general_operand" "rR,Q")))]
796 [(set_attr "length" "1,2")])
798 (define_insn "extendqisi2"
799 [(set (match_operand:SI 0 "register_operand" "=r,r")
800 (sign_extend:SI (match_operand:QI 1 "general_operand" "rR,Q")))]
806 /* make register pair available */
807 latehalf[0] = operands[0];
808 operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
810 output_asm_insn(\"movb %1, %0\", operands);
811 output_asm_insn(\"sxt %0\", latehalf);
815 [(set_attr "length" "2,3")])
817 ;; maybe we have to use define_expand to say that we have the instruction,
818 ;; unconditionally, and then match dependent on CPU type:
820 (define_expand "extendhisi2"
821 [(set (match_operand:SI 0 "general_operand" "=g")
822 (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
826 (define_insn "" ; "extendhisi2"
827 [(set (match_operand:SI 0 "general_operand" "=o,<,r")
828 (sign_extend:SI (match_operand:HI 1 "general_operand" "g,g,g")))]
834 /* we don't want to mess with auto increment */
836 switch(which_alternative)
840 latehalf[0] = operands[0];
841 operands[0] = adj_offsettable_operand(operands[0], 2);
843 output_asm_insn(\"mov %1, %0\", operands);
844 output_asm_insn(\"sxt %0\", latehalf);
850 /* - auto-decrement - right direction ;-) */
851 output_asm_insn(\"mov %1, %0\", operands);
852 output_asm_insn(\"sxt %0\", operands);
858 /* make register pair available */
859 latehalf[0] = operands[0];
860 operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
862 output_asm_insn(\"mov %1, %0\", operands);
863 output_asm_insn(\"sxt %0\", latehalf);
872 [(set_attr "length" "5,3,3")])
876 [(set (match_operand:SI 0 "register_operand" "=r")
877 (sign_extend:SI (match_operand:HI 1 "general_operand" "0")))]
881 static int count = 0;
885 lateoperands[0] = operands[0];
886 operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
888 output_asm_insn(\"tst %0\", operands);
889 sprintf(buf, \"bge extendhisi%d\", count);
890 output_asm_insn(buf, NULL);
891 output_asm_insn(\"mov -1, %0\", lateoperands);
892 sprintf(buf, \"bne extendhisi%d\", count+1);
893 output_asm_insn(buf, NULL);
894 sprintf(buf, \"\\nextendhisi%d:\", count);
895 output_asm_insn(buf, NULL);
896 output_asm_insn(\"clr %0\", lateoperands);
897 sprintf(buf, \"\\nextendhisi%d:\", count+1);
898 output_asm_insn(buf, NULL);
904 [(set_attr "length" "6")])
906 ;; make float to int and vice versa
907 ;; using the cc_status.flag field we could probably cut down
909 ;; assume that we are normally in double and integer mode -
910 ;; what do pdp library routines do to fpu mode ?
912 (define_insn "floatsidf2"
913 [(set (match_operand:DF 0 "register_operand" "=a,a,a")
914 (float:DF (match_operand:SI 1 "general_operand" "r,R,Q")))]
916 "* if (which_alternative ==0)
921 latehalf[1] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
922 output_asm_insn(\"mov %1, -(sp)\", latehalf);
923 output_asm_insn(\"mov %1, -(sp)\", operands);
925 output_asm_insn(\"setl\", operands);
926 output_asm_insn(\"{ldcld|movif} (sp)+, %0\", operands);
927 output_asm_insn(\"seti\", operands);
930 else if (which_alternative == 1)
931 return \"setl\;{ldcld|movif} %1, %0\;seti\";
933 return \"setl\;{ldcld|movif} %1, %0\;seti\";
935 [(set_attr "length" "5,3,4")])
937 (define_insn "floathidf2"
938 [(set (match_operand:DF 0 "register_operand" "=a,a")
939 (float:DF (match_operand:HI 1 "general_operand" "rR,Qi")))]
941 "{ldcid|movif} %1, %0"
942 [(set_attr "length" "1,2")])
945 (define_insn "fix_truncdfsi2"
946 [(set (match_operand:SI 0 "general_operand" "=r,R,Q")
947 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a,a,a"))))]
949 "* if (which_alternative ==0)
951 output_asm_insn(\"setl\", operands);
952 output_asm_insn(\"{stcdl|movfi} %1, -(sp)\", operands);
953 output_asm_insn(\"seti\", operands);
954 output_asm_insn(\"mov (sp)+, %0\", operands);
955 operands[0] = gen_rtx(REG, HImode, REGNO (operands[0])+1);
956 output_asm_insn(\"mov (sp)+, %0\", operands);
959 else if (which_alternative == 1)
960 return \"setl\;{stcdl|movfi} %1, %0\;seti\";
962 return \"setl\;{stcdl|movfi} %1, %0\;seti\";
964 [(set_attr "length" "5,3,4")])
966 (define_insn "fix_truncdfhi2"
967 [(set (match_operand:HI 0 "general_operand" "=rR,Q")
968 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "a,a"))))]
970 "{stcdi|movfi} %1, %0"
971 [(set_attr "length" "1,2")])
974 ;;- arithmetic instructions
977 (define_insn "adddf3"
978 [(set (match_operand:DF 0 "register_operand" "=a,a,a")
979 (plus:DF (match_operand:DF 1 "register_operand" "%0,0,0")
980 (match_operand:DF 2 "general_operand" "fR,Q,F")))]
983 [(set_attr "length" "1,2,5")])
985 (define_insn "addsi3"
986 [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
987 (plus:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
988 (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
991 { /* Here we trust that operands don't overlap
993 or is lateoperands the low word?? - looks like it! */
998 lateoperands[0] = operands[0];
1000 if (REG_P (operands[0]))
1001 operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
1003 operands[0] = adj_offsettable_operand (operands[0], 2);
1005 if (! CONSTANT_P(operands[2]))
1007 lateoperands[2] = operands[2];
1009 if (REG_P (operands[2]))
1010 operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
1012 operands[2] = adj_offsettable_operand(operands[2], 2);
1014 output_asm_insn (\"add %2, %0\", operands);
1015 output_asm_insn (\"adc %0\", lateoperands);
1016 output_asm_insn (\"add %2, %0\", lateoperands);
1020 lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
1021 operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
1023 if (INTVAL(operands[2]))
1025 output_asm_insn (\"add %2, %0\", operands);
1026 output_asm_insn (\"adc %0\", lateoperands);
1029 if (INTVAL(lateoperands[2]))
1030 output_asm_insn (\"add %2, %0\", lateoperands);
1034 [(set_attr "length" "3,5,6,8,3,1,5,5,3,8")])
1036 (define_insn "addhi3"
1037 [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
1038 (plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
1039 (match_operand:HI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
1043 if (GET_CODE (operands[2]) == CONST_INT)
1045 if (INTVAL(operands[2]) == 1)
1047 else if (INTVAL(operands[2]) == -1)
1051 return \"add %2, %0\";
1053 [(set_attr "length" "1,2,2,3")])
1055 (define_insn "addqi3"
1056 [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
1057 (plus:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
1058 (match_operand:QI 2 "general_operand" "rRLM,Qi,rRLM,Qi")))]
1062 if (GET_CODE (operands[2]) == CONST_INT)
1064 if (INTVAL(operands[2]) == 1)
1066 else if (INTVAL(operands[2]) == -1)
1070 return \"addb %2, %0\";
1072 [(set_attr "length" "1,2,2,3")])
1075 ;;- subtract instructions
1076 ;; we don't have to care for constant second
1077 ;; args, since they are canonical plus:xx now!
1078 ;; also for minus:DF ??
1080 (define_insn "subdf3"
1081 [(set (match_operand:DF 0 "register_operand" "=a,a")
1082 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
1083 (match_operand:DF 2 "general_operand" "fR,Q")))]
1085 "{subd|subf} %2, %0"
1086 [(set_attr "length" "1,2")])
1088 (define_insn "subsi3"
1089 [(set (match_operand:SI 0 "general_operand" "=r,r,o,o")
1090 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0")
1091 (match_operand:SI 2 "general_operand" "r,o,r,o")))]
1094 { /* Here we trust that operands don't overlap
1096 or is lateoperands the low word?? - looks like it! */
1099 rtx lateoperands[3];
1101 lateoperands[0] = operands[0];
1103 if (REG_P (operands[0]))
1104 operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
1106 operands[0] = adj_offsettable_operand (operands[0], 2);
1108 lateoperands[2] = operands[2];
1110 if (REG_P (operands[2]))
1111 operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
1113 operands[2] = adj_offsettable_operand(operands[2], 2);
1115 output_asm_insn (\"sub %2, %0\", operands);
1116 output_asm_insn (\"sbc %0\", lateoperands);
1117 output_asm_insn (\"sub %2, %0\", lateoperands);
1120 ;; offsettable memory addresses always are expensive!!!
1121 [(set_attr "length" "3,5,6,8")])
1123 (define_insn "subhi3"
1124 [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
1125 (minus:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
1126 (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))]
1130 if (GET_CODE (operands[2]) == CONST_INT)
1133 return \"sub %2, %0\";
1135 [(set_attr "length" "1,2,2,3")])
1137 (define_insn "subqi3"
1138 [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
1139 (minus:QI (match_operand:QI 1 "general_operand" "0,0,0,0")
1140 (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))]
1144 if (GET_CODE (operands[2]) == CONST_INT)
1147 return \"subb %2, %0\";
1149 [(set_attr "length" "1,2,2,3")])
1151 ;;;;- and instructions
1152 ;; Bit-and on the pdp (like on the vax) is done with a clear-bits insn.
1153 (define_expand "andsi3"
1154 [(set (match_operand:SI 0 "general_operand" "=g")
1155 (and:SI (match_operand:SI 1 "general_operand" "0")
1156 (not:SI (match_operand:SI 2 "general_operand" "g"))))]
1160 extern rtx expand_unop ();
1161 if (GET_CODE (operands[2]) == CONST_INT)
1162 operands[2] = GEN_INT (~INTVAL (operands[2]));
1164 operands[2] = expand_unop (SImode, one_cmpl_optab, operands[2], 0, 1);
1167 (define_expand "andhi3"
1168 [(set (match_operand:HI 0 "general_operand" "=g")
1169 (and:HI (match_operand:HI 1 "general_operand" "0")
1170 (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1174 extern rtx expand_unop ();
1175 if (GET_CODE (operands[2]) == CONST_INT)
1176 operands[2] = GEN_INT (~INTVAL (operands[2]));
1178 operands[2] = expand_unop (HImode, one_cmpl_optab, operands[2], 0, 1);
1181 (define_expand "andqi3"
1182 [(set (match_operand:QI 0 "general_operand" "=g")
1183 (and:QI (match_operand:QI 1 "general_operand" "0")
1184 (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1188 extern rtx expand_unop ();
1189 rtx op = operands[2];
1190 if (GET_CODE (op) == CONST_INT)
1191 operands[2] = GEN_INT (((1 << 8) - 1) & ~INTVAL (op));
1193 operands[2] = expand_unop (QImode, one_cmpl_optab, op, 0, 1);
1196 (define_insn "andcbsi3"
1197 [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
1198 (and:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
1199 (not:SI (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K"))))]
1202 { /* Here we trust that operands don't overlap
1204 or is lateoperands the low word?? - looks like it! */
1207 rtx lateoperands[3];
1209 lateoperands[0] = operands[0];
1211 if (REG_P (operands[0]))
1212 operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
1214 operands[0] = adj_offsettable_operand (operands[0], 2);
1216 if (! CONSTANT_P(operands[2]))
1218 lateoperands[2] = operands[2];
1220 if (REG_P (operands[2]))
1221 operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
1223 operands[2] = adj_offsettable_operand(operands[2], 2);
1225 output_asm_insn (\"bic %2, %0\", operands);
1226 output_asm_insn (\"bic %2, %0\", lateoperands);
1230 lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
1231 operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
1233 /* these have different lengths, so we should have
1234 different constraints! */
1235 if (INTVAL(operands[2]))
1236 output_asm_insn (\"bic %2, %0\", operands);
1238 if (INTVAL(lateoperands[2]))
1239 output_asm_insn (\"bic %2, %0\", lateoperands);
1243 [(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
1245 (define_insn "andcbhi3"
1246 [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
1247 (and:HI (match_operand:HI 1 "general_operand" "0,0,0,0")
1248 (not:HI (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi"))))]
1251 [(set_attr "length" "1,2,2,3")])
1253 (define_insn "andcbqi3"
1254 [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
1255 (and:QI (match_operand:QI 1 "general_operand" "0,0,0,0")
1256 (not:QI (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi"))))]
1259 [(set_attr "length" "1,2,2,3")])
1261 ;;- Bit set (inclusive or) instructions
1262 (define_insn "iorsi3"
1263 [(set (match_operand:SI 0 "general_operand" "=r,r,o,o,r,r,r,o,o,o")
1264 (ior:SI (match_operand:SI 1 "general_operand" "%0,0,0,0,0,0,0,0,0,0")
1265 (match_operand:SI 2 "general_operand" "r,o,r,o,I,J,K,I,J,K")))]
1268 { /* Here we trust that operands don't overlap
1270 or is lateoperands the low word?? - looks like it! */
1273 rtx lateoperands[3];
1275 lateoperands[0] = operands[0];
1277 if (REG_P (operands[0]))
1278 operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
1280 operands[0] = adj_offsettable_operand (operands[0], 2);
1282 if (! CONSTANT_P(operands[2]))
1284 lateoperands[2] = operands[2];
1286 if (REG_P (operands[2]))
1287 operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
1289 operands[2] = adj_offsettable_operand(operands[2], 2);
1291 output_asm_insn (\"bis %2, %0\", operands);
1292 output_asm_insn (\"bis %2, %0\", lateoperands);
1296 lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
1297 operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
1299 /* these have different lengths, so we should have
1300 different constraints! */
1301 if (INTVAL(operands[2]))
1302 output_asm_insn (\"bis %2, %0\", operands);
1304 if (INTVAL(lateoperands[2]))
1305 output_asm_insn (\"bis %2, %0\", lateoperands);
1309 [(set_attr "length" "2,4,4,6,2,2,4,3,3,6")])
1311 (define_insn "iorhi3"
1312 [(set (match_operand:HI 0 "general_operand" "=rR,rR,Q,Q")
1313 (ior:HI (match_operand:HI 1 "general_operand" "%0,0,0,0")
1314 (match_operand:HI 2 "general_operand" "rR,Qi,rR,Qi")))]
1317 [(set_attr "length" "1,2,2,3")])
1319 (define_insn "iorqi3"
1320 [(set (match_operand:QI 0 "general_operand" "=rR,rR,Q,Q")
1321 (ior:QI (match_operand:QI 1 "general_operand" "%0,0,0,0")
1322 (match_operand:QI 2 "general_operand" "rR,Qi,rR,Qi")))]
1326 ;;- xor instructions
1327 (define_insn "xorsi3"
1328 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1329 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,0,0")
1330 (match_operand:SI 2 "arith_operand" "r,I,J,K")))]
1333 { /* Here we trust that operands don't overlap */
1336 rtx lateoperands[3];
1338 lateoperands[0] = operands[0];
1339 operands[0] = gen_rtx(REG, HImode, REGNO(operands[0]) + 1);
1341 if (REG_P(operands[2]))
1343 lateoperands[2] = operands[2];
1344 operands[2] = gen_rtx(REG, HImode, REGNO(operands[2]) + 1);
1346 output_asm_insn (\"xor %2, %0\", operands);
1347 output_asm_insn (\"xor %2, %0\", lateoperands);
1352 lateoperands[2] = GEN_INT ((INTVAL(operands[2]) >> 16) & 0xffff);
1353 operands[2] = GEN_INT (INTVAL(operands[2]) & 0xffff);
1355 if (INTVAL(operands[2]))
1356 output_asm_insn (\"xor %2, %0\", operands);
1358 if (INTVAL(lateoperands[2]))
1359 output_asm_insn (\"xor %2, %0\", lateoperands);
1363 [(set_attr "length" "2,1,1,2")])
1365 (define_insn "xorhi3"
1366 [(set (match_operand:HI 0 "general_operand" "=rR,Q")
1367 (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1368 (match_operand:HI 2 "register_operand" "r,r")))]
1371 [(set_attr "length" "1,2")])
1373 ;;- one complement instructions
1375 (define_insn "one_cmplhi2"
1376 [(set (match_operand:HI 0 "general_operand" "=rR,Q")
1377 (not:HI (match_operand:HI 1 "general_operand" "0,0")))]
1380 [(set_attr "length" "1,2")])
1382 (define_insn "one_cmplqi2"
1383 [(set (match_operand:QI 0 "general_operand" "=rR,Q")
1384 (not:QI (match_operand:QI 1 "general_operand" "0,0")))]
1387 [(set_attr "length" "1,2")])
1389 ;;- arithmetic shift instructions
1390 (define_insn "ashlsi3"
1391 [(set (match_operand:SI 0 "register_operand" "=r,r")
1392 (ashift:SI (match_operand:SI 1 "register_operand" "0,0")
1393 (match_operand:HI 2 "general_operand" "rR,Qi")))]
1396 [(set_attr "length" "1,2")])
1398 ;; Arithmetic right shift on the pdp works by negating the shift count.
1399 (define_expand "ashrsi3"
1400 [(set (match_operand:SI 0 "register_operand" "=r")
1401 (ashift:SI (match_operand:SI 1 "register_operand" "0")
1402 (match_operand:HI 2 "general_operand" "g")))]
1406 operands[2] = negate_rtx (HImode, operands[2]);
1409 ;; define asl aslb asr asrb - ashc missing!
1413 [(set (match_operand:HI 0 "general_operand" "=rR,Q")
1414 (ashift:HI (match_operand:HI 1 "general_operand" "0,0")
1418 [(set_attr "length" "1,2")])
1420 ;; and another possibility for asr is << -1
1421 ;; might cause problems since -1 can also be encoded as 65535!
1426 [(set (match_operand:HI 0 "general_operand" "=rR,Q")
1427 (ashift:HI (match_operand:HI 1 "general_operand" "0,0")
1431 [(set_attr "length" "1,2")])
1433 ;; shift is by arbitrary count is expensive,
1434 ;; shift by one cheap - so let's do that, if
1435 ;; space doesn't matter
1437 [(set (match_operand:HI 0 "general_operand" "=r")
1438 (ashift:HI (match_operand:HI 1 "general_operand" "0")
1439 (match_operand:HI 2 "expand_shift_operand" "O")))]
1445 for (i = 1; i <= abs(INTVAL(operands[2])); i++)
1446 if (INTVAL(operands[2]) < 0)
1447 output_asm_insn(\"asr %0\", operands);
1449 output_asm_insn(\"asl %0\", operands);
1454 [(set (attr "length") (const_int 4))])
1458 [(set (match_operand:QI 0 "general_operand" "=r,o")
1459 (ashift:QI (match_operand:QI 1 "general_operand" "0,0")
1460 (match_operand:HI 2 "const_immediate_operand" "n,n")))]
1463 { /* allowing predec or post_inc is possible, but hairy! */
1466 cnt = INTVAL(operands[2]) & 0x0007;
1468 for (i=0 ; i < cnt ; i++)
1469 output_asm_insn(\"aslb %0\", operands);
1473 ;; set attribute length ( match_dup 2 & 7 ) *(1 or 2) !!!
1474 [(set_attr_alternative "length"
1480 ; [(set (match_operand:HI 0 "general_operand" "=rR,Q")
1481 ; (ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0")
1485 ; [(set_attr "length" "1,2")])
1489 [(set (match_operand:QI 0 "general_operand" "=r,o")
1490 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0")
1491 (match_operand:HI 2 "const_immediate_operand" "n,n")))]
1494 { /* allowing predec or post_inc is possible, but hairy! */
1497 cnt = INTVAL(operands[2]) & 0x0007;
1499 for (i=0 ; i < cnt ; i++)
1500 output_asm_insn(\"asrb %0\", operands);
1504 [(set_attr_alternative "length"
1508 ;; the following is invalid - too complex!!! - just say 14 !!!
1509 ; [(set (attr "length") (plus (and (match_dup 2)
1511 ; (and (match_dup 2)
1512 ; (const_int 7))))])
1516 ;; can we get +-1 in the next pattern? should
1517 ;; have been caught by previous patterns!
1519 (define_insn "ashlhi3"
1520 [(set (match_operand:HI 0 "register_operand" "=r,r")
1521 (ashift:HI (match_operand:HI 1 "register_operand" "0,0")
1522 (match_operand:HI 2 "general_operand" "rR,Qi")))]
1526 if (GET_CODE(operands[2]) == CONST_INT)
1528 if (INTVAL(operands[2]) == 1)
1530 else if (INTVAL(operands[2]) == -1)
1534 return \"ash %2,%0\";
1536 [(set_attr "length" "1,2")])
1538 ;; Arithmetic right shift on the pdp works by negating the shift count.
1539 (define_expand "ashrhi3"
1540 [(set (match_operand:HI 0 "register_operand" "=r")
1541 (ashift:HI (match_operand:HI 1 "register_operand" "0")
1542 (match_operand:HI 2 "general_operand" "g")))]
1546 operands[2] = negate_rtx (HImode, operands[2]);
1549 ;;;;- logical shift instructions
1550 ;;(define_insn "lshrsi3"
1551 ;; [(set (match_operand:HI 0 "register_operand" "=r")
1552 ;; (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
1553 ;; (match_operand:HI 2 "arith_operand" "rI")))]
1559 (define_insn "absdf2"
1560 [(set (match_operand:DF 0 "general_operand" "=fR,Q")
1561 (abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
1564 [(set_attr "length" "1,2")])
1566 (define_insn "abshi2"
1567 [(set (match_operand:HI 0 "general_operand" "=r,o")
1568 (abs:HI (match_operand:HI 1 "general_operand" "0,0")))]
1569 "TARGET_ABSHI_BUILTIN"
1572 static int count = 0;
1575 output_asm_insn(\"tst %0\", operands);
1576 sprintf(buf, \"bge abshi%d\", count);
1577 output_asm_insn(buf, NULL);
1578 output_asm_insn(\"neg %0\", operands);
1579 sprintf(buf, \"\\nabshi%d:\", count++);
1580 output_asm_insn(buf, NULL);
1584 [(set_attr "length" "3,5")])
1587 ;; define expand abshi - is much better !!! - but
1588 ;; will it be optimized into an abshi2 ?
1589 ;; it will leave better code, because the tsthi might be
1591 ; -- just a thought - don't have time to check
1593 ;(define_expand "abshi2"
1594 ; [(match_operand:HI 0 "general_operand" "")
1595 ; (match_operand:HI 1 "general_operand" "")]
1599 ; rtx label = gen_label_rtx ();
1601 ; /* do I need this? */
1602 ; do_pending_stack_adjust ();
1604 ; emit_move_insn (operands[0], operands[1]);
1606 ; emit_insn (gen_tsthi (operands[0]));
1607 ; emit_insn (gen_bge (label1));
1609 ; emit_insn (gen_neghi(operands[0], operands[0])
1613 ; emit_label (label);
1615 ; /* allow REG_NOTES to be set on last insn (labels don't have enough
1616 ; fields, and can't be used for REG_NOTES anyway). */
1617 ; emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
1623 (define_insn "negdf2"
1624 [(set (match_operand:DF 0 "general_operand" "=fR,Q")
1625 (neg:DF (match_operand:DF 1 "register_operand" "0,0")))]
1628 [(set_attr "length" "1,2")])
1630 (define_insn "neghi2"
1631 [(set (match_operand:HI 0 "general_operand" "=rR,Q")
1632 (neg:HI (match_operand:HI 1 "general_operand" "0,0")))]
1635 [(set_attr "length" "1,2")])
1637 (define_insn "negqi2"
1638 [(set (match_operand:QI 0 "general_operand" "=rR,Q")
1639 (neg:QI (match_operand:QI 1 "general_operand" "0,0")))]
1642 [(set_attr "length" "1,2")])
1645 ;; Unconditional and other jump instructions
1648 (label_ref (match_operand 0 "" "")))]
1651 [(set_attr "length" "2")])
1655 (label_ref (match_operand 0 "" "")))
1656 (clobber (const_int 1))]
1659 [(set_attr "length" "2")])
1661 (define_insn "tablejump"
1662 [(set (pc) (match_operand:HI 0 "general_operand" "rR,Q"))
1663 (use (label_ref (match_operand 1 "" "")))]
1666 [(set_attr "length" "1,2")])
1668 ;; indirect jump - let's be conservative!
1669 ;; allow only register_operand, even though we could also
1670 ;; allow labels etc.
1672 (define_insn "indirect_jump"
1673 [(set (pc) (match_operand:HI 0 "register_operand" "r"))]
1677 ;;- jump to subroutine
1680 [(call (match_operand:HI 0 "general_operand" "R,Q")
1681 (match_operand:HI 1 "general_operand" "g,g"))
1682 ;; (use (reg:HI 0)) what was that ???
1684 ;;- Don't use operand 1 for most machines.
1687 [(set_attr "length" "1,2")])
1689 ;;- jump to subroutine
1690 (define_insn "call_value"
1691 [(set (match_operand 0 "" "")
1692 (call (match_operand:HI 1 "general_operand" "R,Q")
1693 (match_operand:HI 2 "general_operand" "g,g")))
1694 ;; (use (reg:HI 0)) - what was that ????
1696 ;;- Don't use operand 2 for most machines.
1699 [(set_attr "length" "1,2")])
1710 (define_insn "muldf3"
1711 [(set (match_operand:DF 0 "register_operand" "=a,a,a")
1712 (mult:DF (match_operand:DF 1 "register_operand" "%0,0,0")
1713 (match_operand:DF 2 "general_operand" "fR,Q,F")))]
1715 "{muld|mulf} %2, %0"
1716 [(set_attr "length" "1,2,5")])
1718 ;; 16 bit result multiply:
1719 ;; currently we multiply only into odd registers, so we don't use two
1720 ;; registers - but this is a bit inefficient at times. If we define
1721 ;; a register class for each register, then we can specify properly
1722 ;; which register need which scratch register ....
1724 (define_insn "mulhi3"
1725 [(set (match_operand:HI 0 "register_operand" "=d,d") ; multiply regs
1726 (mult:HI (match_operand:HI 1 "register_operand" "%0,0")
1727 (match_operand:HI 2 "general_operand" "rR,Qi")))]
1730 [(set_attr "length" "1,2")])
1733 (define_expand "mulhisi3"
1735 (match_operand:HI 1 "general_operand" "g,g"))
1736 (set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
1737 (mult:SI (truncate:HI
1739 (match_operand:HI 2 "general_operand" "rR,Qi")))]
1741 "operands[3] = gen_lowpart(HImode, operands[1]);")
1744 [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
1745 (mult:SI (truncate:HI
1746 (match_operand:SI 1 "register_operand" "%0,0"))
1747 (match_operand:HI 2 "general_operand" "rR,Qi")))]
1750 [(set_attr "length" "1,2")])
1752 ;(define_insn "mulhisi3"
1753 ; [(set (match_operand:SI 0 "register_operand" "=r,r") ; even numbered!
1754 ; (mult:SI (truncate:HI
1755 ; (match_operand:SI 1 "register_operand" "%0,0"))
1756 ; (match_operand:HI 2 "general_operand" "rR,Qi")))]
1759 ; [(set_attr "length" "1,2")])
1762 (define_insn "divdf3"
1763 [(set (match_operand:DF 0 "register_operand" "=a,a,a")
1764 (div:DF (match_operand:DF 1 "register_operand" "0,0,0")
1765 (match_operand:DF 2 "general_operand" "fR,Q,F")))]
1767 "{divd|divf} %2, %0"
1768 [(set_attr "length" "1,2,5")])
1771 (define_expand "divhi3"
1772 [(set (subreg:HI (match_dup 1) 0)
1773 (div:HI (match_operand:SI 1 "general_operand" "0")
1774 (match_operand:HI 2 "general_operand" "g")))
1775 (set (match_operand:HI 0 "general_operand" "=r")
1776 (subreg:HI (match_dup 1) 0))]
1781 [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0)
1782 (div:HI (match_operand:SI 1 "general_operand" "0")
1783 (match_operand:HI 2 "general_operand" "g")))]
1786 [(set_attr "length" "2")])
1788 (define_expand "modhi3"
1789 [(set (subreg:HI (match_dup 1) 1)
1790 (mod:HI (match_operand:SI 1 "general_operand" "0")
1791 (match_operand:HI 2 "general_operand" "g")))
1792 (set (match_operand:HI 0 "general_operand" "=r")
1793 (subreg:HI (match_dup 1) 1))]
1798 [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 1)
1799 (mod:HI (match_operand:SI 1 "general_operand" "0")
1800 (match_operand:HI 2 "general_operand" "g")))]
1803 [(set_attr "length" "2")])
1805 ;(define_expand "divmodhi4"
1806 ; [(parallel [(set (subreg:HI (match_dup 1) 0)
1807 ; (div:HI (match_operand:SI 1 "general_operand" "0")
1808 ; (match_operand:HI 2 "general_operand" "g")))
1809 ; (set (subreg:HI (match_dup 1) 1)
1810 ; (mod:HI (match_dup 1)
1812 ; (set (match_operand:HI 3 "general_operand" "=r")
1813 ; (subreg:HI (match_dup 1) 1))
1814 ; (set (match_operand:HI 0 "general_operand" "=r")
1815 ; (subreg:HI (match_dup 1) 0))]
1820 ; [(set (subreg:HI (match_operand:SI 0 "general_operand" "=r") 0)
1821 ; (div:HI (match_operand:SI 1 "general_operand" "0")
1822 ; (match_operand:HI 2 "general_operand" "g")))
1823 ; (set (subreg:HI (match_dup 0) 1)
1824 ; (mod:HI (match_dup 1)
1830 ;; is rotate doing the right thing to be included here ????