1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001-2013 Free Software Foundation, Inc.
3 Contributed by Picochip Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
38 #include "stor-layout.h"
39 #include "stringpool.h"
46 #include "basic-block.h"
47 #include "diagnostic-core.h"
52 #include "target-def.h"
53 #include "langhooks.h"
57 #include "picochip-protos.h"
59 #include "insn-attr.h" /* For DFA state_t. */
60 #include "insn-config.h" /* Required by recog.h */
61 #include "insn-codes.h" /* For CODE_FOR_? */
62 #include "optabs.h" /* For GEN_FCN */
63 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
64 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
65 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
66 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
70 /* Target AE ISA information. */
71 enum picochip_dfa_type picochip_schedule_type
;
73 bool picochip_has_mul_unit
= false;
74 bool picochip_has_mac_unit
= false;
76 /* targetm hook function prototypes. */
78 void picochip_asm_file_start (void);
79 void picochip_asm_file_end (void);
81 void picochip_init_libfuncs (void);
82 void picochip_reorg (void);
84 int picochip_arg_partial_bytes (cumulative_args_t p_cum
,
85 enum machine_mode mode
,
86 tree type
, bool named
);
87 rtx
picochip_function_arg (cumulative_args_t p_cum
,
88 enum machine_mode mode
,
89 const_tree type
, bool named
);
90 rtx
picochip_incoming_function_arg (cumulative_args_t p_cum
,
91 enum machine_mode mode
,
92 const_tree type
, bool named
);
93 void picochip_arg_advance (cumulative_args_t p_cum
, enum machine_mode mode
,
94 const_tree type
, bool named
);
95 unsigned int picochip_function_arg_boundary (enum machine_mode mode
,
98 int picochip_sched_lookahead (void);
99 int picochip_sched_issue_rate (void);
100 int picochip_sched_adjust_cost (rtx insn
, rtx link
,
101 rtx dep_insn
, int cost
);
102 int picochip_sched_reorder (FILE * file
, int verbose
, rtx
* ready
,
103 int *n_readyp
, int clock
);
105 void picochip_init_builtins (void);
106 rtx
picochip_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
108 bool picochip_rtx_costs (rtx x
, int code
, int outer_code
, int opno
,
109 int* total
, bool speed
);
110 bool picochip_return_in_memory(const_tree type
,
111 const_tree fntype ATTRIBUTE_UNUSED
);
112 bool picochip_legitimate_address_p (enum machine_mode
, rtx
, bool);
113 rtx
picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
114 enum machine_mode mode
);
115 int picochip_legitimize_reload_address (rtx
*x
, enum machine_mode mode
,
116 int opnum
, int type
, int ind_levels
);
118 rtx
picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED
, int incoming ATTRIBUTE_UNUSED
);
119 rtx
picochip_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
120 bool outgoing ATTRIBUTE_UNUSED
);
122 picochip_secondary_reload (bool in_p
,
123 rtx x ATTRIBUTE_UNUSED
,
124 reg_class_t cla ATTRIBUTE_UNUSED
,
125 enum machine_mode mode
,
126 secondary_reload_info
*sri
);
128 picochip_asm_named_section (const char *name
,
129 unsigned int flags ATTRIBUTE_UNUSED
,
130 tree decl ATTRIBUTE_UNUSED
);
132 static rtx
picochip_static_chain (const_tree
, bool);
134 static void picochip_option_override (void);
136 /* Lookup table mapping a register number to the earliest containing
137 class. Used by REGNO_REG_CLASS. */
138 const enum reg_class picochip_regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
140 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
141 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
142 TWIN_REGS
, TWIN_REGS
, TWIN_REGS
, TWIN_REGS
,
143 GR_REGS
, FRAME_REGS
, PTR_REGS
, CONST_REGS
,
144 ACC_REGS
, CC_REGS
, GR_REGS
, GR_REGS
147 /* picoChip register names. */
148 const char *picochip_regnames
[] = REGISTER_NAMES
;
150 /* Define the maximum number of registers which may be used to pass
151 * parameters to functions. */
152 #define MAX_CALL_PARAMETER_REGS 6
155 /* Target scheduling information. */
157 /* This flag indicates whether the next instruction to be output is a
158 VLIW continuation instruction. It is used to communicate between
159 final_prescan_insn and asm_output_opcode. */
160 static int picochip_vliw_continuation
= 0;
162 /* This variable is used to communicate the current instruction
163 between final_prescan_insn and functions such as asm_output_opcode,
164 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
165 current instruction. */
166 static rtx picochip_current_prescan_insn
;
168 static bool picochip_is_delay_slot_pending
= 0;
170 /* When final_prescan_insn is called, it computes information about
171 the current VLIW packet, and stores it in this structure. When
172 instructions are output, this state is used to make sure that the
173 instructions are output in the correct way (e.g., which ALU to use,
174 whether a macro branch was ever previously a real branch, etc.). */
177 int contains_pico_alu_insn
;
178 int contains_non_cc_alu_insn
;
179 int num_alu_insns_so_far
;
181 /* Record how many instructions are contained in the packet. */
182 int num_insns_in_packet
;
184 /* There was a case for this to be more than 1 */
185 int num_cfi_labels_deferred
;
186 char cfi_label_name
[2][256]; /* Used to record the name of a CFI label
187 emitted inside a VLIW packet. */
188 char lm_label_name
[256]; /* Used to record the name of an LM label. */
191 struct vliw_state picochip_current_vliw_state
;
193 /* Save/restore recog_data. */
194 static int picochip_saved_which_alternative
;
195 static struct recog_data_d picochip_saved_recog_data
;
197 /* Determine which ALU to use for the instruction in
198 picochip_current_prescan_insn. */
199 static char picochip_get_vliw_alu_id (void);
201 /* Initialize the GCC target structure. */
203 #undef TARGET_ASM_FUNCTION_PROLOGUE
204 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
206 #undef TARGET_ASM_FUNCTION_EPILOGUE
207 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
209 #undef TARGET_ASM_INTERNAL_LABEL
210 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
212 #undef TARGET_ASM_GLOBALIZE_LABEL
213 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
215 #undef TARGET_ASM_BYTE_OP
216 #define TARGET_ASM_BYTE_OP ".initByte "
217 #undef TARGET_ASM_ALIGNED_HI_OP
218 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
219 #undef TARGET_ASM_UNALIGNED_HI_OP
220 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
221 #undef TARGET_ASM_ALIGNED_SI_OP
222 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
223 #undef TARGET_ASM_UNALIGNED_SI_OP
224 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
226 #undef TARGET_INIT_BUILTINS
227 #define TARGET_INIT_BUILTINS picochip_init_builtins
229 #undef TARGET_EXPAND_BUILTIN
230 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
232 #undef TARGET_RTX_COSTS
233 #define TARGET_RTX_COSTS picochip_rtx_costs
235 #undef TARGET_SCHED_ISSUE_RATE
236 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
238 #undef TARGET_SCHED_REORDER
239 #define TARGET_SCHED_REORDER picochip_sched_reorder
241 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
242 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
243 picochip_sched_lookahead
245 #undef TARGET_SCHED_ADJUST_COST
246 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
248 #undef TARGET_ASM_NAMED_SECTION
249 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
251 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
252 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
254 #undef TARGET_INIT_LIBFUNCS
255 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
257 #undef TARGET_ASM_FILE_START
258 #define TARGET_ASM_FILE_START picochip_asm_file_start
260 #undef TARGET_ASM_FILE_END
261 #define TARGET_ASM_FILE_END picochip_asm_file_end
263 #undef TARGET_MACHINE_DEPENDENT_REORG
264 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
266 #undef TARGET_ARG_PARTIAL_BYTES
267 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
269 #undef TARGET_FUNCTION_ARG
270 #define TARGET_FUNCTION_ARG picochip_function_arg
272 #undef TARGET_FUNCTION_INCOMING_ARG
273 #define TARGET_FUNCTION_INCOMING_ARG picochip_incoming_function_arg
275 #undef TARGET_FUNCTION_ARG_ADVANCE
276 #define TARGET_FUNCTION_ARG_ADVANCE picochip_arg_advance
278 #undef TARGET_FUNCTION_ARG_BOUNDARY
279 #define TARGET_FUNCTION_ARG_BOUNDARY picochip_function_arg_boundary
281 #undef TARGET_PROMOTE_FUNCTION_MODE
282 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
283 #undef TARGET_PROMOTE_PROTOTYPES
284 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
286 /* Target support for Anchored Addresses optimization */
287 #undef TARGET_MIN_ANCHOR_OFFSET
288 #define TARGET_MIN_ANCHOR_OFFSET 0
289 #undef TARGET_MAX_ANCHOR_OFFSET
290 #define TARGET_MAX_ANCHOR_OFFSET 7
291 #undef TARGET_ASM_OUTPUT_ANCHOR
292 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
294 #undef TARGET_FUNCTION_VALUE
295 #define TARGET_FUNCTION_VALUE picochip_function_value
297 #undef TARGET_LIBGCC_CMP_RETURN_MODE
298 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
301 #undef TARGET_LEGITIMATE_ADDRESS_P
302 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
304 #undef TARGET_LEGITIMIZE_ADDRESS
305 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
307 /* Loading and storing QImode values to and from memory
308 usually requires a scratch register. */
309 #undef TARGET_SECONDARY_RELOAD
310 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
312 /* How Large Values are Returned */
314 #undef TARGET_RETURN_IN_MEMORY
315 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
317 #undef TARGET_STATIC_CHAIN
318 #define TARGET_STATIC_CHAIN picochip_static_chain
320 #undef TARGET_OPTION_OVERRIDE
321 #define TARGET_OPTION_OVERRIDE picochip_option_override
323 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
324 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE picochip_option_override
326 /* The 2nd scheduling pass option is switched off, and a machine
327 dependent reorganisation ensures that it is run later on, after the
328 second jump optimisation. */
329 #undef TARGET_DELAY_SCHED2
330 #define TARGET_DELAY_SCHED2 true
332 /* Variable tracking should be run after all optimizations which
333 change order of insns. It also needs a valid CFG. */
334 #undef TARGET_DELAY_VARTRACK
335 #define TARGET_DELAY_VARTRACK true
337 struct gcc_target targetm
= TARGET_INITIALIZER
;
340 /* Only return a value in memory if it is greater than 4 bytes.
341 int_size_in_bytes returns -1 for variable size objects, which go in
342 memory always. The cast to unsigned makes -1 > 8. */
345 picochip_return_in_memory(const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
347 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 4);
350 /* Allow some options to be overriden. */
353 picochip_option_override (void)
355 /* If we are optimizing for stack, dont let inliner to inline functions
356 that could potentially increase stack size.*/
357 if (flag_conserve_stack
)
359 maybe_set_param_value (PARAM_LARGE_STACK_FRAME
, 0,
360 global_options
.x_param_values
,
361 global_options_set
.x_param_values
);
362 maybe_set_param_value (PARAM_STACK_FRAME_GROWTH
, 0,
363 global_options
.x_param_values
,
364 global_options_set
.x_param_values
);
367 /* Turn off the elimination of unused types. The elaborator
368 generates various interesting types to represent constants,
369 generics, and so on, and it is useful to retain this information
370 in the debug output. The increased size of the debug information
371 is not really an issue for us. */
372 flag_eliminate_unused_debug_types
= 0;
374 /* Even if the user specifies a -fno-omit-frame-pointer on the
375 command line, we still want to go ahead and omit frame pointer
376 usages, since we dont really have a frame pointer register.
377 So, all accesses to FP need to be converted to accesses off
379 flag_omit_frame_pointer
= 1;
381 /* Turning on anchored addresses by default. This is an optimization
382 that could decrease the code size by placing anchors in data and
383 accessing offsets from the anchor for file local data variables.*/
385 flag_section_anchors
= 1;
387 /* The second scheduling pass runs within picochip_reorg, to avoid
388 having the second jump optimisation trash the instruction modes
389 (e.g., instructions are changed to TImode to mark the beginning
390 of cycles). Two types of DFA scheduling are possible: space and
391 speed. In both cases, instructions are reordered to avoid stalls
392 (e.g., memory loads stall for one cycle). Speed scheduling will
393 also enable VLIW instruction packing. VLIW instructions use more
394 code space, so VLIW scheduling is disabled when scheduling for
396 if (flag_schedule_insns_after_reload
)
399 picochip_schedule_type
= DFA_TYPE_SPACE
;
402 picochip_schedule_type
= DFA_TYPE_SPEED
;
403 flag_delayed_branch
= 0;
407 picochip_schedule_type
= DFA_TYPE_NONE
;
409 /* Ensure that the debug level is always at least -g2. The flow
410 analyser works at its best if it always has debug
411 information. DWARF is non-intrusive, so it makes no difference to
412 code quality if debug is always enabled. */
413 if (debug_info_level
< DINFO_LEVEL_NORMAL
)
415 debug_info_level
= DINFO_LEVEL_NORMAL
;
416 write_symbols
= DWARF2_DEBUG
;
419 /* Options of the form -mae=mac, and so on will be substituted by
420 the compiler driver for the appropriate byte access and multiply
421 unit ISA options. Any unrecognised AE types will end up being
422 passed to the compiler, which should reject them as invalid. */
423 if (picochip_ae_type_string
!= NULL
)
424 error ("invalid AE type specified (%s)", picochip_ae_type_string
);
426 /* Override any specific capabilities of the instruction set. These
427 take precedence over any capabilities inferred from the AE type,
428 regardless of where the options appear on the command line. */
429 if (picochip_mul_type_string
== NULL
)
431 /* Default to MEM-type multiply, for historical compatibility. */
432 picochip_has_mac_unit
= false;
433 picochip_has_mul_unit
= true;
437 picochip_has_mac_unit
= false;
438 picochip_has_mul_unit
= false;
440 if (strcmp (picochip_mul_type_string
, "mul") == 0)
441 picochip_has_mul_unit
= true;
442 else if (strcmp (picochip_mul_type_string
, "mac") == 0)
443 picochip_has_mac_unit
= true;
444 else if (strcmp (picochip_mul_type_string
, "none") == 0)
445 { /* Do nothing. Unit types already set to false. */ }
447 error ("invalid mul type specified (%s) - expected mac, mul or none",
448 picochip_mul_type_string
);
453 /* Initialise the library functions to handle arithmetic on some of
456 picochip_init_libfuncs (void)
459 set_optab_libfunc (ashr_optab
, DImode
, "__ashrdi3");
460 set_optab_libfunc (ashl_optab
, DImode
, "__ashldi3");
461 set_optab_libfunc (lshr_optab
, DImode
, "__lshrdi3");
463 /* 64-bit signed multiplication. */
464 set_optab_libfunc (smul_optab
, DImode
, "__muldi3");
466 /* Signed division */
467 set_optab_libfunc (sdiv_optab
, HImode
, "__divhi3");
468 set_optab_libfunc (sdiv_optab
, DImode
, "__divdi3");
471 set_optab_libfunc (smod_optab
, HImode
, "__modhi3");
472 set_optab_libfunc (smod_optab
, DImode
, "__moddi3");
474 /* 32-bit count leading Zeros*/
475 set_optab_libfunc (clz_optab
, SImode
, "_clzsi2");
477 /* 64-bit comparison */
478 set_optab_libfunc (ucmp_optab
, DImode
, "__ucmpdi2");
479 set_optab_libfunc (cmp_optab
, DImode
, "__cmpdi2");
481 /* 64-bit addition and subtraction*/
482 set_optab_libfunc (add_optab
, DImode
, "_adddi3");
483 set_optab_libfunc (sub_optab
, DImode
, "_subdi3");
486 /* Memcpy function */
488 picochip_expand_movmemhi (rtx
*operands
)
490 rtx src_addr_reg
, dst_addr_reg
, count_reg
, src_mem
, dst_mem
, tmp_reg
;
493 src_addr_reg
= gen_reg_rtx(HImode
);
494 dst_addr_reg
= gen_reg_rtx(HImode
);
495 count_reg
= gen_reg_rtx(HImode
);
496 emit_insn (gen_movhi (count_reg
, operands
[2]));
497 emit_insn (gen_movqi (src_addr_reg
, XEXP(operands
[1], 0)));
498 emit_insn (gen_movqi (dst_addr_reg
, XEXP(operands
[0], 0)));
499 gcc_assert (GET_CODE(count_reg
) == REG
);
500 start_label
= gen_label_rtx ();
501 emit_label (start_label
);
503 /* We can specialise the code for different alignments */
504 align
= INTVAL(operands
[3]);
505 size
= INTVAL(operands
[2]);
506 gcc_assert(align
>= 0 && size
>= 0);
509 if (size
% 4 == 0 && align
% 4 == 0)
511 src_mem
= gen_rtx_MEM(SImode
, src_addr_reg
);
512 dst_mem
= gen_rtx_MEM(SImode
, dst_addr_reg
);
513 tmp_reg
= gen_reg_rtx(SImode
);
514 emit_insn (gen_movsi (tmp_reg
, src_mem
));
515 emit_insn (gen_movsi (dst_mem
, tmp_reg
));
516 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, GEN_INT(4)));
517 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, GEN_INT(4)));
518 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-4)));
519 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
520 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
522 else if (size
% 2 == 0 && align
% 2 == 0)
524 src_mem
= gen_rtx_MEM(HImode
, src_addr_reg
);
525 dst_mem
= gen_rtx_MEM(HImode
, dst_addr_reg
);
526 tmp_reg
= gen_reg_rtx(HImode
);
527 emit_insn (gen_movhi (tmp_reg
, src_mem
));
528 emit_insn (gen_movhi (dst_mem
, tmp_reg
));
529 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const2_rtx
));
530 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const2_rtx
));
531 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-2)));
532 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
533 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
537 src_mem
= gen_rtx_MEM(QImode
, src_addr_reg
);
538 dst_mem
= gen_rtx_MEM(QImode
, dst_addr_reg
);
539 tmp_reg
= gen_reg_rtx(QImode
);
540 emit_insn (gen_movqi (tmp_reg
, src_mem
));
541 emit_insn (gen_movqi (dst_mem
, tmp_reg
));
542 emit_insn (gen_addhi3 (dst_addr_reg
, dst_addr_reg
, const1_rtx
));
543 emit_insn (gen_addhi3 (src_addr_reg
, src_addr_reg
, const1_rtx
));
544 emit_insn (gen_addhi3 (count_reg
, count_reg
, GEN_INT(-1)));
545 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
546 emit_cmp_and_jump_insns (count_reg
, const0_rtx
, GT
, 0, HImode
, 0, start_label
);
553 /* Return the register class for letter C. */
555 picochip_reg_class_from_letter (unsigned c
)
573 pico_leaf_reg_alloc_order
[] = LEAF_REG_ALLOC_ORDER
;
575 pico_nonleaf_reg_alloc_order
[] = REG_ALLOC_ORDER
;
578 picochip_order_regs_for_local_alloc (void)
580 /* We change the order for leaf functions alone. We put r12 at
581 the end since using it will prevent us to combine stw/ldws to
582 stl/ldl and it gives no benefit. In non-leaf functions, we
583 would anyway saveup/restore r12, so it makes sense to use it.*/
585 if (leaf_function_p())
587 memcpy ((char *)reg_alloc_order
, (const char *) pico_leaf_reg_alloc_order
,
588 FIRST_PSEUDO_REGISTER
* sizeof (int));
592 memcpy ((char *)reg_alloc_order
, (const char *) pico_nonleaf_reg_alloc_order
,
593 FIRST_PSEUDO_REGISTER
* sizeof (int));
597 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
599 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value
, unsigned c
)
604 case 'I': /* 4 bits signed. */
605 return value
+ 8 < 16;
606 case 'J': /* 4 bits unsigned. */
608 case 'K': /* 8 bits signed. */
609 return value
+ 128 < 256;
610 case 'M': /* 4-bit magnitude. */
611 return abs (value
) < 16;
612 case 'N': /* 10 bits signed. */
613 return value
+ 512 > 1024;
614 case 'O': /* 16 bits signed. */
615 return value
+ 32768 < 65536;
616 default: /* Unknown letter. */
621 /* Stack utility functions. */
623 picochip_return_addr_rtx(int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
626 return gen_rtx_REG (Pmode
, LINK_REGNUM
);
632 /* Emit a set of parallel register expressions used to store
633 blockmode values to pass to functions. */
635 picochip_emit_register_parallel (int size_in_units
, int offset
)
639 rtx vector
[MAX_CALL_PARAMETER_REGS
];
643 /* Compute the base register, and number of required registers. */
644 base_reg
= offset
/ 2;
645 num_regs
= size_in_units
/ 2;
646 if (size_in_units
% 2 == 1)
649 /* Emit a register for each part of the block mode value to be
650 passed in a register. */
651 for (i
= 0; i
< num_regs
; i
++)
652 vector
[i
] = gen_rtx_EXPR_LIST (VOIDmode
,
653 gen_rtx_REG (HImode
, base_reg
+ i
),
655 result
= gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (num_regs
, vector
));
661 /* Emit an instruction to allocate a suitable amount of space on the
662 stack, by decrementing the stack pointer. */
664 picochip_emit_stack_allocate (int adjustment
)
667 rtx stack_pointer_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
669 /* Use an addition of a negative value. */
670 insn
= emit_insn (gen_addhi3 (stack_pointer_reg
, stack_pointer_reg
,
671 GEN_INT (-adjustment
)));
673 /* Make the instruction frame related. Also add an expression note,
674 so that the correct Dwarf information is generated (see documention
675 for RTX_FRAME_RELATED_P for more details). */
676 RTX_FRAME_RELATED_P (insn
) = 1;
677 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
678 gen_rtx_SET (VOIDmode
, stack_pointer_reg
,
679 gen_rtx_PLUS (Pmode
, stack_pointer_reg
,
680 GEN_INT (-adjustment
))));
684 /* Emit an instruction to save a register of the given mode. The
685 offset at which to save the register is given relative to the stack
688 picochip_emit_save_register (rtx reg
, int offset
)
690 rtx stack_pointer
, address
, mem
, insn
;
692 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
694 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
696 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
698 insn
= emit_move_insn (mem
, reg
);
699 RTX_FRAME_RELATED_P (insn
) = 1;
701 /* For modes other than HImode, create a note explaining that
702 multiple registers have been saved. This allows the correct DWARF
703 call frame information to be generated. */
704 switch (GET_MODE (reg
))
707 /* The RTL is sufficient to explain HImode register saves. */
711 /* SImode must be broken down into parallel HImode register saves. */
719 gen_rtx_PLUS (Pmode
, stack_pointer
,
721 gen_rtx_REG (HImode
, REGNO (reg
)));
722 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 0)) = 1;
725 gen_rtx_SET (HImode
, gen_rtx_MEM (HImode
,
730 gen_rtx_REG (HImode
, REGNO (reg
) + 1));
731 RTX_FRAME_RELATED_P (RTVEC_ELT (p
, 1)) = 1;
733 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
734 gen_rtx_PARALLEL (VOIDmode
, p
));
741 ("unexpected mode %s encountered in picochip_emit_save_register",
742 GET_MODE_NAME (GET_MODE (reg
)));
747 /* Emit an instruction to restore a register of the given mode. The
748 offset from which to restore the register is given relative to the
751 picochip_emit_restore_register (rtx reg
, int offset
)
753 rtx stack_pointer
, address
, mem
;
755 stack_pointer
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
757 address
= gen_rtx_PLUS (Pmode
, stack_pointer
, GEN_INT (offset
));
759 mem
= gen_rtx_MEM (GET_MODE (reg
), address
);
761 emit_move_insn (reg
, mem
);
765 /* Check that the given byte offset is aligned to the given number of
768 picochip_is_aligned (int byte_offset
, int bit_alignment
)
770 int byte_alignment
= bit_alignment
/ BITS_PER_UNIT
;
771 return (byte_offset
% byte_alignment
) == 0;
774 /*****************************************************************************
777 * The following section contains code which controls how the stack is
780 * The stack is laid out as follows (high addresses first):
783 * Pretend arguments (ARG PTR)
787 * Outgoing arguments (SP)
789 * The (constant) offsets of the different areas must be calculated
790 * relative to the stack area immediately below, and aligned
791 * appropriately. For example, the frame offset is computed by
792 * determining the offset of the special register area, adding the
793 * size of the special register area, and then aligning the resulting
794 * offset correctly. In turn, the special register offset is computed
795 * from the general register offset, and so on. This enables the
796 * different offsets to change size and alignment, without requiring
797 * the code for other offset calculations to be rewritten.
799 * The argument pointer, and the frame pointer are eliminated wherever
800 * possible, by replacing them with a constant offset from the stack
801 * pointer. In the rare cases where constant offsets from the stack
802 * pointer cannot be computed, another register will be allocated to
803 * serve as the argument pointer, or the frame pointer.
805 * The save registers are stored at small offsets from the caller, to
806 * enable the more efficient SP-based ISA instructions to be used.
808 ****************************************************************************/
810 /* Compute the size of an argument in units. */
812 picochip_compute_arg_size (const_tree type
, enum machine_mode mode
)
814 int type_size_in_units
= 0;
817 type_size_in_units
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
819 type_size_in_units
= GET_MODE_SIZE (mode
);
821 return type_size_in_units
;
825 /* Determine where the next outgoing arg should be placed. */
827 picochip_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
828 const_tree type
, bool named ATTRIBUTE_UNUSED
)
830 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
832 int type_align_in_units
= 0;
833 int type_size_in_units
;
835 int offset_overflow
= 0;
837 /* VOIDmode is passed when computing the second argument to a `call'
838 pattern. This can be ignored. */
839 if (mode
== VOIDmode
)
842 /* Compute the alignment and size of the parameter. */
843 type_align_in_units
=
844 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
845 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
847 /* Compute the correct offset (i.e., ensure that the offset meets
848 the alignment requirements). */
849 offset_overflow
= *cum
% type_align_in_units
;
850 if (offset_overflow
== 0)
853 new_offset
= (*cum
- offset_overflow
) + type_align_in_units
;
857 printf ("Function arg:\n");
858 printf (" Type valid: %s\n", (type
? "yes" : "no"));
859 printf (" Cumulative Value: %d\n", *cum
);
860 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
861 printf (" Type size: %i units\n", type_size_in_units
);
862 printf (" Alignment: %i units\n", type_align_in_units
);
863 printf (" New offset: %i\n", new_offset
);
867 /* If the new offset is outside the register space, return. */
868 if (new_offset
>= MAX_CALL_PARAMETER_REGS
* 2)
871 /* If the end of the argument is outside the register space, then
872 the argument must overlap the register space. Return the first
873 available register. */
874 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
875 return gen_rtx_REG (HImode
, new_offset
/ 2);
877 /* Create a register of the required mode to hold the parameter. */
878 reg
= new_offset
/ 2;
893 return gen_rtx_REG (mode
, reg
);
897 /* Empty blockmode values can be passed as arguments (e.g.,
898 * empty structs). These require no registers
899 * whatsoever. Non-empty blockmode values are passed in a set
900 * of parallel registers. */
901 if (type_size_in_units
== 0)
904 return picochip_emit_register_parallel (type_size_in_units
, new_offset
);
909 (0, "defaulting to stack for %s register creation",
910 GET_MODE_NAME (mode
));
918 /* Determine where the next incoming function argument will
919 appear. Normally, this works in exactly the same way as
920 picochip_function_arg, except when the function in question is a
921 varadic function. In this case, the incoming arguments all appear
922 to be passed on the stack (actually, some of the arguments are
923 passed in registers, which are then pushed onto the stack by the
924 function prologue). */
926 picochip_incoming_function_arg (cumulative_args_t cum
,
927 enum machine_mode mode
,
928 const_tree type
, bool named
)
934 return picochip_function_arg (cum
, mode
, type
, named
);
938 /* Gives the alignment boundary, in bits, of an argument with the
941 picochip_function_arg_boundary (enum machine_mode mode
,
942 const_tree type ATTRIBUTE_UNUSED
)
947 align
= STACK_BOUNDARY
;
949 align
= GET_MODE_ALIGNMENT (mode
);
951 if (align
< PARM_BOUNDARY
)
952 align
= PARM_BOUNDARY
;
958 /* Compute partial registers. */
960 picochip_arg_partial_bytes (cumulative_args_t p_cum
, enum machine_mode mode
,
961 tree type
, bool named ATTRIBUTE_UNUSED
)
963 int type_align_in_units
= 0;
964 int type_size_in_units
;
966 int offset_overflow
= 0;
968 unsigned cum
= *get_cumulative_args (p_cum
);
970 /* VOIDmode is passed when computing the second argument to a `call'
971 pattern. This can be ignored. */
972 if (mode
== VOIDmode
)
975 /* Compute the alignment and size of the parameter. */
976 type_align_in_units
=
977 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
978 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
980 /* Compute the correct offset (i.e., ensure that the offset meets
981 the alignment requirements). */
982 offset_overflow
= cum
% type_align_in_units
;
983 if (offset_overflow
== 0)
986 new_offset
= (cum
- offset_overflow
) + type_align_in_units
;
990 printf ("Partial function arg nregs:\n");
991 printf (" Type valid: %s\n", (type
? "yes" : "no"));
992 printf (" Cumulative Value: %d\n", cum
);
993 printf (" Mode: %s\n", GET_MODE_NAME (mode
));
994 printf (" Type size: %i units\n", type_size_in_units
);
995 printf (" Alignment: %i units\n", type_align_in_units
);
996 printf (" New offset: %i\n", new_offset
);
1000 /* If the new offset is outside the register space, return. */
1001 if (new_offset
>= (MAX_CALL_PARAMETER_REGS
* 2))
1004 /* If the end of the argument is outside the register space, then
1005 the argument must overlap the register space. Return the number
1006 of bytes which are passed in registers. */
1007 if ((new_offset
+ type_size_in_units
) > (MAX_CALL_PARAMETER_REGS
* 2))
1008 return ((MAX_CALL_PARAMETER_REGS
* 2) - new_offset
);
1014 /* Advance the cumulative args counter CUM. */
1016 picochip_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
1017 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1019 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1020 int type_align_in_units
= 0;
1021 int type_size_in_units
;
1023 int offset_overflow
= 0;
1025 /* VOIDmode is passed when computing the second argument to a `call'
1026 pattern. This can be ignored. */
1027 if (mode
== VOIDmode
)
1030 /* Compute the alignment and size of the parameter. */
1031 type_align_in_units
=
1032 picochip_function_arg_boundary (mode
, type
) / BITS_PER_UNIT
;
1033 type_size_in_units
= picochip_compute_arg_size (type
, mode
);
1035 /* Compute the correct offset (i.e., ensure that the offset meets
1036 the alignment requirements). */
1037 offset_overflow
= *cum
% type_align_in_units
;
1038 if (offset_overflow
== 0)
1041 new_offset
= (*cum
- offset_overflow
) + type_align_in_units
;
1043 /* Advance past the last argument. */
1044 new_offset
+= type_size_in_units
;
1049 /* Determine whether a register needs saving/restoring. It does if it
1050 is live in a function, and isn't a call-used register. */
1052 picochip_reg_needs_saving (int reg_num
)
1054 return df_regs_ever_live_p(reg_num
) && !call_used_regs
[reg_num
];
1057 /* Compute and return offset of the main frame. */
1059 picochip_frame_byte_offset (void)
1061 gcc_assert(picochip_is_aligned
1062 (crtl
->outgoing_args_size
, BITS_PER_WORD
));
1064 return crtl
->outgoing_args_size
;
1067 /* Return the size of the main frame. */
1069 picochip_frame_size_in_bytes (void)
1071 int frame_size
= get_frame_size();
1072 int stack_align
= STACK_BOUNDARY
/BITS_PER_UNIT
;
1073 if (!picochip_is_aligned (frame_size
, STACK_BOUNDARY
))
1074 frame_size
= frame_size
+ (stack_align
- frame_size
%stack_align
);
1075 gcc_assert(picochip_is_aligned (frame_size
, STACK_BOUNDARY
));
1079 /* Compute and return the size (in bytes) of the register save/restore
1080 area for the current function. This only includes the general
1081 purpose registers - the special purpose stack pointer and link
1082 registers are not included in this area. */
1084 picochip_save_area_size_in_bytes (void)
1086 int num_regs_to_save
= 0;
1089 /* Read through all the registers, determining which need to be saved. */
1090 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1092 if (picochip_reg_needs_saving (i
))
1093 num_regs_to_save
+= 1;
1096 return num_regs_to_save
* UNITS_PER_WORD
;
1100 /* Compute and return offset of the save area base. */
1102 picochip_save_area_byte_offset (void)
1104 int base_offset
= (picochip_frame_byte_offset () +
1105 picochip_frame_size_in_bytes ());
1107 gcc_assert(picochip_is_aligned (base_offset
, BITS_PER_WORD
));
1113 /* Compute and return offset of the special register save area. This
1114 area can be found immediately above the normal save area. It must
1115 be aligned, to allow the registers to be saved and restored as a
1118 picochip_special_save_area_byte_offset (void)
1120 int byte_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
1121 int offset
= (picochip_save_area_byte_offset () +
1122 picochip_save_area_size_in_bytes ());
1124 if ((offset
% byte_alignment
) != 0)
1125 offset
= ((offset
/ byte_alignment
) + 1) * byte_alignment
;
1131 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1133 picochip_can_eliminate_link_sp_save (void)
1135 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1136 changing during optimizations phases. So, this function returns different
1137 values when called from initial_elimination_offset and then again when it
1138 is called from prologue/epilogue generation. This means that argument
1139 accesses become wrong. This wouldnt happen only if we were not using the
1140 stack at all. The following conditions ensures that.*/
1142 return (crtl
->is_leaf
&&
1143 !df_regs_ever_live_p(LINK_REGNUM
) &&
1144 !df_regs_ever_live_p(STACK_POINTER_REGNUM
) &&
1145 (picochip_special_save_area_byte_offset() == 0) &&
1146 (crtl
->args
.size
== 0) &&
1147 (crtl
->args
.pretend_args_size
== 0));
1150 /* Compute the size of the special reg save area (SP and LNK). If the
1151 SP/LNK registers don't need to be saved, this area can shrink to
1154 picochip_special_save_area_size_in_bytes (void)
1158 if (picochip_can_eliminate_link_sp_save ())
1161 return 2 * UNITS_PER_WORD
;
1164 /* Return the number of pretend arguments. If this function is
1165 varadic, all the incoming arguments are effectively passed on the
1166 stack. If this function has real pretend arguments (caused by a
1167 value being passed partially on the stack and partially in
1168 registers), then return the number of registers used. */
1170 picochip_pretend_arg_area_size (void)
1173 if (crtl
->args
.pretend_args_size
!= 0)
1175 gcc_assert(crtl
->args
.pretend_args_size
% 4 == 0);
1177 return crtl
->args
.pretend_args_size
;
1179 else if (cfun
->stdarg
)
1186 /* Compute and return the offset of the pretend arguments. The pretend
1187 arguments are contiguous with the incoming arguments, and must be
1188 correctly aligned. */
1190 picochip_pretend_arg_area_byte_offset (void)
1192 int base_offset
= 0;
1194 base_offset
= (picochip_special_save_area_byte_offset () +
1195 picochip_special_save_area_size_in_bytes ());
1197 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1198 gcc_assert(picochip_is_aligned
1199 (base_offset
+ picochip_pretend_arg_area_size (), STACK_BOUNDARY
));
1205 /* Compute and return the offset of the incoming arguments. If a
1206 static chain is in use, this will be passed just before the other
1207 arguments. This means that the pretend argument mechanism, used in
1208 variadic functions, doesn't work properly. Thus, static chains work
1209 on their own, as do variadic functions, but not the combination of
1210 the two. This isn't really a problem. */
1212 picochip_arg_area_byte_offset (void)
1214 int base_offset
= (picochip_pretend_arg_area_byte_offset () +
1215 picochip_pretend_arg_area_size ());
1217 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1218 the alignment on a 32-bit boundary must be maintained. */
1219 if (cfun
->static_chain_decl
!= NULL
)
1221 gcc_assert (!cfun
->stdarg
);
1225 gcc_assert(picochip_is_aligned (base_offset
, STACK_BOUNDARY
));
1232 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED
, int mode
)
1235 /* Special case - only one register needed. */
1236 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1239 /* We actually do not allocate acc0 ever. But, it seems like we need to
1240 make it look like a allocatable register for the dataflow checks to work
1241 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1246 /* General case - compute how much space in terms of units. */
1247 return ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1252 picochip_class_max_nregs (int reg_class
, int mode
)
1254 int size
= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
);
1256 if (reg_class
== ACC_REGS
)
1259 if (GET_MODE_CLASS (mode
) == MODE_CC
)
1266 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1267 argument pointer) by replacing it with a constant offset from the
1268 main stack register. */
1270 initial_elimination_offset (int from
, int to
)
1272 int offset_from_sp
= 0;
1274 if (FRAME_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1275 offset_from_sp
= picochip_frame_byte_offset ();
1276 else if (ARG_POINTER_REGNUM
== from
&& STACK_POINTER_REGNUM
== to
)
1277 offset_from_sp
= picochip_pretend_arg_area_byte_offset ();
1281 return offset_from_sp
;
1285 /* Compute and return the size of the incoming argument area. */
1287 picochip_arg_area_size_in_bytes (void)
1289 return crtl
->args
.size
;
1292 /* Determine whether the given register is valid. When the strict mode
1293 is used, only hard registers are valid, otherwise any register is
1296 picochip_legitimate_address_register (rtx x
, unsigned strict
)
1299 /* Sanity check - non-registers shouldn't make it here, but... */
1300 if (REG
!= GET_CODE (x
))
1304 return REGNO (x
) < FIRST_NONHARD_REGISTER
;
1310 /* Determine whether the given constant is in the range required for
1311 the given base register. */
1313 picochip_const_ok_for_base (enum machine_mode mode
, int regno
, int offset
)
1315 HOST_WIDE_INT corrected_offset
;
1317 if (GET_MODE_SIZE (mode
) != 0)
1319 if (GET_MODE_SIZE(mode
) <= 4)
1321 /* We used to allow incorrect offsets if strict is 0. But, this would
1322 then rely on reload doing the right thing. We have had problems
1323 there before, and on > 4.3 compiler, there are no benefits. */
1324 if (offset
% GET_MODE_SIZE (mode
) != 0)
1326 corrected_offset
= offset
/ GET_MODE_SIZE (mode
);
1330 if (offset
% 4 != 0)
1332 corrected_offset
= offset
/ 4;
1337 /* Default to the byte offset as supplied. */
1338 corrected_offset
= offset
;
1341 /* The offset from the base register can be different depending upon
1342 the base register. The stack/frame/argument pointer offsets can
1343 all be greater than a simple register-based offset. Note that the
1344 frame/argument pointer registers are actually eliminations of the
1345 stack pointer, so a value which is valid for an offset to, for
1346 example, the frame pointer, might be invalid for the stack
1347 pointer once the elimination has occurred. However, there is no
1348 need to handle this special case here, as the stack offset is
1349 always checked after elimination anyway, and the generated code
1350 seems to have identical performance. */
1351 if (regno
== STACK_POINTER_REGNUM
||
1352 regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1353 return picochip_const_ok_for_letter_p (corrected_offset
, 'K');
1355 return picochip_const_ok_for_letter_p (corrected_offset
, 'J');
1359 /* Determine whether a given rtx is a legitimate address for machine_mode
1360 MODE. STRICT is non-zero if we're being strict - any pseudo that
1361 is not a hard register must be a memory reference. */
1363 picochip_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1367 switch (GET_CODE (x
))
1370 valid
= picochip_legitimate_address_register (x
, strict
);
1375 rtx base
= XEXP (x
, 0);
1376 rtx offset
= XEXP (x
, 1);
1377 if (strict
&& !REGNO_OK_FOR_BASE_P (REGNO(base
)))
1383 valid
= (REG
== GET_CODE (base
) &&
1384 picochip_legitimate_address_register (base
, strict
) &&
1385 CONST_INT
== GET_CODE (offset
) &&
1386 picochip_const_ok_for_base (mode
, REGNO (base
),
1392 /* The user can select whether a symbol can be used as a memory
1393 address. Typically, this will decrease execution time (no
1394 register load is required first), but will increase code size
1395 (because the symbol will be used several times, rather than
1396 loaded once into a register.*/
1397 valid
= TARGET_SYMBOL_AS_ADDRESS
;
1402 /* A constant memory address must be a (plus (symbol_ref)
1403 (const_int)), and is only allowed when the symbols are
1404 permitted addresses. */
1405 rtx inner
= XEXP (x
, 0);
1407 valid
= (TARGET_SYMBOL_AS_ADDRESS
&&
1408 PLUS
== GET_CODE (inner
) &&
1409 SYMBOL_REF
== GET_CODE (XEXP (inner
, 0)) &&
1410 CONST_INT
== GET_CODE (XEXP (inner
, 1)));
1424 /* For all memory operations, picochip allows a uconst4 offset value. It
1425 is hence beneficial to turn an
1426 addr = <reg + long_const>
1431 X = reg + long_const & FFF0
1432 diff = long_const - (long_const & FFF0)
1435 X can be reused in subsequent memory operations.
1438 picochip_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1439 enum machine_mode mode
)
1446 /* Depending on mode, the offsets allowed are either 16/32/64.*/
1462 if (GET_CODE (x
) == PLUS
1463 && GET_CODE (XEXP (x
, 0)) == REG
1464 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1466 int high_val
, low_val
, offset
;
1467 offset
= INTVAL (XEXP (x
, 1));
1468 /* Ignore cases with negative offsets. */
1471 high_val
= offset
& mask_val
;
1472 low_val
= offset
- high_val
;
1475 rtx temp_reg
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, XEXP (x
, 0), GEN_INT(high_val
)));
1476 x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1483 /* For all memory operations, picochip allows a uconst4 offset value. It
1484 is hence beneficial to turn an
1485 addr = <reg + long_const>
1490 X = reg + long_const & FFF0
1491 diff = long_const - (long_const & FFF0)
1494 X can be reused in subsequent memory operations.
1497 picochip_legitimize_reload_address (rtx
*x
,
1498 enum machine_mode mode
,
1499 int opnum
, int type
,
1500 int ind_levels ATTRIBUTE_UNUSED
)
1504 if (picochip_symbol_offset(*x
))
1506 *x
= gen_rtx_CONST(mode
, *x
);
1512 /* We should recognise addresses that we created.*/
1513 if (GET_CODE (*x
) == PLUS
1514 && GET_CODE (XEXP (*x
, 0)) == PLUS
1515 && GET_CODE (XEXP (XEXP (*x
, 0), 0)) == REG
1516 && GET_CODE (XEXP (XEXP (*x
, 0), 1)) == CONST_INT
1517 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1519 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1520 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1521 opnum
, (enum reload_type
)type
);
1525 /* Depending on mode, the offsets allowed are either 16/32/64. */
1541 if (GET_CODE (*x
) == PLUS
1542 && GET_CODE (XEXP (*x
, 0)) == REG
1543 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
)
1545 int high_val
, low_val
, offset
;
1546 offset
= INTVAL (XEXP (*x
, 1));
1547 /* Ignore cases with negative offsets. */
1550 high_val
= offset
& mask_val
;
1551 low_val
= offset
- high_val
;
1554 rtx temp_reg
= gen_rtx_PLUS (Pmode
, XEXP (*x
, 0), GEN_INT(high_val
));
1555 *x
= gen_rtx_PLUS (Pmode
, temp_reg
, GEN_INT(low_val
));
1556 push_reload (XEXP (*x
, 0), NULL_RTX
, &XEXP (*x
, 0), NULL
,
1557 BASE_REG_CLASS
, GET_MODE (*x
), VOIDmode
, 0, 0,
1558 opnum
, (enum reload_type
)type
);
1566 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1568 picochip_symbol_offset (rtx operand
)
1571 return (PLUS
== GET_CODE (operand
) &&
1572 SYMBOL_REF
== GET_CODE (XEXP (operand
, 0)) &&
1573 CONST_INT
== GET_CODE (XEXP (operand
, 1)));
1577 /* Assembly output. */
1579 /* The format here should match the format used in the output of
1580 symbol_ref's elsewhere in this file. */
1582 picochip_output_label (FILE * stream
, const char name
[])
1584 int is_cfi_label
= (strncmp (name
, "picoMark_LCFI", 13) == 0);
1586 /* If VLIW scheduling is in use, any Call Frame Information labels
1587 generated inside a packet must have their output deferred until
1588 the end of the packet. */
1589 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1590 is_cfi_label
&& picochip_vliw_continuation
)
1592 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1594 internal_error ("LCFI labels have already been deferred");
1596 strcpy (picochip_current_vliw_state
.cfi_label_name
[
1597 picochip_current_vliw_state
.num_cfi_labels_deferred
], name
);
1598 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1602 assemble_name (stream
, name
);
1604 if (strncmp (name
, "picoMark_", 9) == 0)
1605 fprintf (stream
, "=\n");
1607 fprintf (stream
, ":\n");
1613 /* The format here should match the format used in the output of
1614 symbol_ref's elsewhere in this file. */
1616 picochip_output_labelref (FILE * stream
, const char name
[])
1618 fprintf (stream
, "_%s", name
);
1622 picochip_weaken_label (FILE * stream
, const char name
[])
1624 fprintf (stream
, ".weak ");
1625 assemble_name (stream
, name
);
1626 fprintf (stream
, "\n");
1629 /* Return true if the given label (or label prefix) denotes a marker
1630 label which should be emitted in the form LABEL= */
1632 picochip_is_marker_prefix (const char *prefix
)
1634 return (strcmp (prefix
, "L") != 0 && strcmp (prefix
, "LC") != 0
1635 && strcmp (prefix
, "LP") != 0);
1639 picochip_output_internal_label (FILE * stream
, const char *prefix
,
1643 /* Emit different types of label, based upon their prefix. They
1644 are handled differently to allow the assembler to ensure that
1645 branch target labels are properly aligned, while other labels
1646 will only serve as code markers, not branch targets. Aligning
1647 labels unnecessarily can result in much code wastage. */
1648 if (picochip_is_marker_prefix (prefix
))
1650 /* Special label marker. If it appears in the middle of a VLIW
1651 packet, defer it until the end of the packet. There has
1652 never been a need to handle more than one lm label at a time. */
1653 if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1654 (strcmp (prefix
, "LM")) == 0 && picochip_vliw_continuation
)
1656 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
1657 internal_error ("LM label has already been deferred");
1659 sprintf (picochip_current_vliw_state
.lm_label_name
,
1660 "picoMark_%s%ld", prefix
, num
);
1662 else if (picochip_schedule_type
== DFA_TYPE_SPEED
&&
1663 (strcmp (prefix
, "LCFI")) == 0 && picochip_vliw_continuation
)
1665 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
1667 internal_error ("LCFI labels have already been deferred.");
1669 sprintf(picochip_current_vliw_state
.cfi_label_name
[
1670 picochip_current_vliw_state
.num_cfi_labels_deferred
],
1671 "picoMark_%s%ld", prefix
, num
);
1672 picochip_current_vliw_state
.num_cfi_labels_deferred
++;
1677 fprintf (stream
, "_picoMark_%s%ld=\n", prefix
, num
);
1684 fprintf (stream
, "_%s%ld:\n", prefix
, num
);
1690 picochip_generate_internal_label (char *str
, const char *prefix
, long num
)
1692 /* Two types of internal label can be generated: branch target
1693 labels and code marker labels. Branch target labels must always
1694 be aligned (since code will execute at these
1695 points). Differentiate between the two by prepending markers with
1696 a unique prefix, which can later be used in output_label to
1697 figure out which label syntax to use. */
1698 if (picochip_is_marker_prefix (prefix
))
1699 sprintf (str
, "picoMark_%s%ld", prefix
, num
);
1701 sprintf (str
, "%s%ld", prefix
, num
);
1706 picochip_asm_output_anchor (rtx symbol
)
1708 fprintf (asm_out_file
, ".offsetData _%s, ",XSTR (symbol
, 0));
1709 fprintf (asm_out_file
, "+ " HOST_WIDE_INT_PRINT_DEC
"\n",SYMBOL_REF_BLOCK_OFFSET(symbol
));
1713 picochip_output_aligned_common (FILE * stream
, const char *name
,
1714 unsigned size
, unsigned alignment
)
1717 fprintf (stream
, ".commonData ");
1718 assemble_name (stream
, name
);
1719 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1720 picochip_output_global (stream
, name
);
1725 picochip_output_aligned_local (FILE * stream
, const char *name
,
1726 unsigned size
, unsigned alignment
)
1729 fprintf (stream
, ".commonData ");
1730 assemble_name (stream
, name
);
1731 fprintf (stream
, ", %u, %u\n", size
, alignment
/ 8);
1736 picochip_output_global (FILE * stream
, const char *name
)
1738 fprintf (stream
, ".global ");
1739 assemble_name (stream
, name
);
1740 fprintf (stream
, "\n");
1743 /* Output an assembly language string. Output as a sequence of decimal
1744 numbers, followed by the literal string to make it obvious what the
1745 numbers represent. */
1747 picochip_output_ascii (FILE * file
, const char *str
, int length
)
1751 fprintf (file
, ".ascii ");
1753 for (i
= 0; i
< length
; ++i
)
1755 fprintf (file
, "16#%x# ", (char) (str
[i
]));
1758 fprintf (file
, " ; ");
1760 for (i
= 0; i
< length
; ++i
)
1767 fprintf (file
, "\\n");
1770 fprintf (file
, "\\t");
1773 fprintf (file
, "\\0");
1776 fprintf (file
, "%c", c
);
1781 fprintf (file
, "\n");
1785 /* Output the beginning of an ASM file. */
1787 picochip_asm_file_start (void)
1789 default_file_start ();
1791 fprintf (asm_out_file
, "// picoChip ASM file\n");
1792 fprintf (asm_out_file
, "//.file \"%s\"\n", main_input_filename
);
1794 fprintf (asm_out_file
, "// Has byte access: %s\n",
1795 (TARGET_HAS_BYTE_ACCESS
? "Yes" : "No"));
1797 if (TARGET_HAS_MUL_UNIT
)
1798 fprintf (asm_out_file
, "// Has multiply: Yes (Multiply unit)\n");
1799 else if (TARGET_HAS_MAC_UNIT
)
1800 fprintf (asm_out_file
, "// Has multiply: Yes (Mac unit)\n");
1802 fprintf (asm_out_file
, "// Has multiply: No\n");
1805 /* Output the end of an ASM file. */
1807 picochip_asm_file_end (void)
1809 /* Include a segment end to make it easy for PERL scripts to grab
1810 segments. This is now done by assembler*/
1812 fprintf (asm_out_file
, "// End of picoChip ASM file\n");
1816 /* Output frame debug information to the given stream. */
1818 picochip_output_frame_debug (FILE * file
)
1823 fprintf (file
, "\t\t// Leaf function\n");
1825 fprintf (file
, "\t\t// Non-leaf function\n");
1827 if (picochip_can_eliminate_link_sp_save ())
1828 fprintf (file
, "\t\t// Link/fp save/restore can be eliminated\n");
1830 if (cfun
->static_chain_decl
!= NULL
)
1831 fprintf (file
, "\t\t// Static chain in use\n");
1833 fprintf (file
, "\t\t// Incoming argument size: %d bytes\n",
1834 picochip_arg_area_size_in_bytes ());
1835 fprintf (file
, "\t\t// Incoming arg offset: %d\n",
1836 picochip_arg_area_byte_offset ());
1837 fprintf (file
, "\t\t// Pretend arg size: %d\n",
1838 picochip_pretend_arg_area_size ());
1839 fprintf (file
, "\t\t// Pretend arg offset (ARGP): %d\n",
1840 picochip_pretend_arg_area_byte_offset ());
1841 fprintf (file
, "\t\t// Special reg area size: %d bytes\n",
1842 picochip_special_save_area_size_in_bytes ());
1843 fprintf (file
, "\t\t// Special reg area offset: %d\n",
1844 picochip_special_save_area_byte_offset ());
1846 /* Output which registers are saved. */
1847 fprintf (file
, "\t\t// Saved regs: ");
1848 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1850 if (picochip_reg_needs_saving (i
))
1851 fprintf (file
, "%s ", picochip_regnames
[i
]);
1853 fprintf (file
, "\t\t\n");
1855 fprintf (file
, "\t\t// Save area size: %d bytes\n",
1856 picochip_save_area_size_in_bytes ());
1857 fprintf (file
, "\t\t// Save area offset: %d\n",
1858 picochip_save_area_byte_offset ());
1860 fprintf (file
, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1861 fprintf (file
, "\t\t// Frame offset (FP): %d\n",
1862 picochip_frame_byte_offset ());
1864 fprintf (file
, "\t\t// Outgoing argument area size: %d bytes\n",
1865 crtl
->outgoing_args_size
);
1869 /* Output picoChip function prologue. This contains human-readable
1870 information about the function. */
1872 picochip_function_prologue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1874 /* Get the function's name, as described by its RTL. This may be
1875 different from the DECL_NAME name used in the source file. The
1876 real declaration name must be used, to ensure that the prologue
1877 emits the right information for the linker. */
1880 x
= DECL_RTL (current_function_decl
);
1881 gcc_assert (MEM_P (x
));
1883 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1884 fnname
= XSTR (x
, 0);
1886 /* Note that the name of the function is given in the &_%s
1887 form. This matches the name of the function as used in labels,
1888 and function calls, and enables processCallGraph to match
1889 function calls to the name of the function, as defined here. */
1890 fprintf (file
, "// picoChip Function Prologue : &_%s = %d bytes\n",
1891 fnname
, picochip_arg_area_byte_offset ());
1893 picochip_output_frame_debug (file
);
1894 fprintf (file
, "\n");
1898 /* Output picoChip function epilogue. */
1900 picochip_function_epilogue (FILE * file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1905 x
= DECL_RTL (current_function_decl
);
1906 gcc_assert (MEM_P (x
));
1908 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1909 fnname
= XSTR (x
, 0);
1910 fprintf (file
, "\n// picoChip Function Epilogue : %s\n\n",
1914 /* Manipulate the asm output. Some machines only execute the code when
1915 there is actually a chance of needing it (e.g., FRV doesn't execute
1916 it if the scheduling pass wasn't used). We always execute it,
1917 simple to ensure that it is exercised more often, and bugs are more
1920 This function's prime reason for existence is to insert the VLIW
1921 separators where appropriate. The separators must be inserted
1922 before any comments which appear at the end of the file.
1926 picochip_asm_output_opcode (FILE * f
, const char *ptr
)
1930 /* Flag to specify when a VLIW continuation has been inserted onto
1931 the line. Continuations are either inserted before any comments,
1932 or before the end of the line is reached. The flag ensures that
1933 we don't insert continuations twice (i.e., at the comment and the
1935 int continuation_inserted
= 0;
1937 /* If the instruction uses multiple lines (i.e., a new line
1938 character appears in the opcode), then ensure that no attempt is
1939 made to pack it into a VLIW. */
1940 if (strchr (ptr
, '\n') != NULL
&& picochip_vliw_continuation
)
1942 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s",
1946 /* If a delay slot is pending, output the directive to the assembler
1947 before the instruction. */
1948 if (picochip_is_delay_slot_pending
)
1950 picochip_is_delay_slot_pending
= 0;
1954 /* Keep going for entire opcode. All substitution performed ourselves. */
1959 /* Determine whether a VLIW continuation must be inserted before
1960 any comments, or the end of the opcode. A flag is set to show
1961 that we have inserted a continuation on this line, so that we
1962 don't try to insert another continuation when the end of the
1963 opcode is reached. The only other case for a continuation
1964 might have been a newline, but these aren't allowed in
1965 conjunction with VLIW continuations (see above code). */
1966 if (picochip_vliw_continuation
&&
1967 !continuation_inserted
&&
1968 ((c
== '/' && (*ptr
== '/')) || *ptr
== '\0'))
1971 continuation_inserted
= 1;
1974 /* Detect an explicit VLIW separator. */
1975 if (c
== '%' && (*ptr
== '|'))
1980 /* Detect the need for an ALU id operand. */
1981 else if (c
== '%' && (*ptr
== '#'))
1983 fputc (picochip_get_vliw_alu_id (), f
);
1986 printf ("Generated ALU char at %s for insn %d\n", ptr
,
1987 INSN_UID (picochip_current_prescan_insn
));
1989 /* Skip past unwanted # */
1992 /* Detect the need for branch delay slot. */
1993 else if (c
== '%' && (*ptr
== '>'))
1995 /* Only emit delay slots (NOP's, or otherwise) when delay
1996 * slot scheduling has actually been enabled, otherwise VLIW
1997 * scheduling and delay slot scheduling output combine to
1998 * produce nasty effects. */
1999 if (flag_delayed_branch
)
2001 if (dbr_sequence_length () == 0)
2002 fputs ("\n=->\tNOP", f
);
2004 picochip_is_delay_slot_pending
= 1;
2007 /* Skip past unwanted > */
2010 /* Detect any %digit specifiers. */
2011 else if (c
== '%' && (*ptr
>= '0' && *ptr
<= '9'))
2014 picochip_print_operand (f
, recog_data
.operand
[c
], 0);
2015 while ((c
= *ptr
) >= '0' && c
<= '9')
2018 /* Detect any %letterdigit specifiers. */
2019 else if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2020 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2022 int letter
= *ptr
++;
2029 output_asm_label (recog_data
.operand
[c
]);
2033 output_address (recog_data
.operand
[c
]);
2037 picochip_print_operand (f
, recog_data
.operand
[c
], letter
);
2040 while ((c
= *ptr
) >= '0' && c
<= '9')
2045 ("picochip_asm_output_opcode - can%'t output unknown operator %c",
2051 /* Reached the end of the packet. If any labels were deferred
2052 during output, emit them now. */
2053 if (!picochip_vliw_continuation
)
2055 if (picochip_current_vliw_state
.num_cfi_labels_deferred
!= 0)
2058 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[0]);
2060 if (picochip_current_vliw_state
.num_cfi_labels_deferred
== 2)
2063 assemble_name (f
, picochip_current_vliw_state
.cfi_label_name
[1]);
2068 if (strlen (picochip_current_vliw_state
.lm_label_name
) != 0)
2071 assemble_name (f
, picochip_current_vliw_state
.lm_label_name
);
2076 /* Output an end-of-packet marker if requested. */
2077 if (!picochip_vliw_continuation
&&
2078 TARGET_DEBUG
&& picochip_schedule_type
== DFA_TYPE_SPEED
)
2079 fprintf (f
, "\n\t//-------------- End of VLIW packet -----------------");
2084 /* Function RTL expansion. */
2086 /* Expand the prologue into RTL. */
2088 picochip_expand_prologue (void)
2090 int stack_adjustment
= 0;
2091 int special_save_offset
= 0;
2092 int general_save_offset
= 0;
2093 int reg_save_offset
= 0;
2096 stack_adjustment
= picochip_arg_area_byte_offset ();
2097 general_save_offset
=
2098 -(stack_adjustment
- picochip_save_area_byte_offset ());
2099 special_save_offset
=
2100 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2102 /* Save the link registers. We could try to save just one register
2103 here. This would reduce the amount of stack space required.
2104 There hasn't been a good reason to do that so far. */
2105 if (!picochip_can_eliminate_link_sp_save ())
2106 picochip_emit_save_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2107 special_save_offset
);
2109 /* Save callee-save registers. */
2110 reg_save_offset
= 0;
2111 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2113 if (picochip_reg_needs_saving (i
))
2116 /* If this register is an even numbered register, and the
2117 next register also needs to be saved, use a SImode save,
2118 which does both in one instruction. Note that a special
2119 check is performed to ensure that the double word aligned
2120 store is valid (e.g., it is possible that r6, r8, r9 need
2121 to be saved, in which case once r6 has been saved, the
2122 stored offset is no longer aligned, and an STL/LDL
2123 instruction becomes invalid). Alternately, we could store all
2124 aligned registers first and then save the single one(s). */
2126 picochip_reg_needs_saving (i
+ 1) &&
2127 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2129 picochip_emit_save_register (gen_rtx_REG (SImode
, i
),
2130 general_save_offset
+
2132 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2137 picochip_emit_save_register (gen_rtx_REG (HImode
, i
),
2138 general_save_offset
+
2140 reg_save_offset
+= UNITS_PER_WORD
;
2146 /* Emit a stack adjustment where required. */
2147 if (stack_adjustment
!= 0)
2148 picochip_emit_stack_allocate (stack_adjustment
);
2150 /* If this function uses varadic arguments, write any unnamed
2151 registers to the stack. */
2154 int stdarg_offset
= picochip_pretend_arg_area_byte_offset ();
2156 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2157 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2159 picochip_emit_save_register (gen_rtx_REG (SImode
, 0), stdarg_offset
);
2160 picochip_emit_save_register (gen_rtx_REG (SImode
, 2),
2162 picochip_emit_save_register (gen_rtx_REG (SImode
, 4),
2169 /* Expand the epilogue into RTL. */
2171 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED
)
2173 int stack_adjustment
= 0;
2174 int special_save_offset
= 0;
2175 int general_save_offset
= 0;
2176 int reg_save_offset
= 0;
2178 int use_link_fp_restore_stack_adjust
= 0; /* Default to using an explicit
2181 stack_adjustment
= picochip_arg_area_byte_offset ();
2182 general_save_offset
=
2183 -(stack_adjustment
- picochip_save_area_byte_offset ());
2184 special_save_offset
=
2185 -(stack_adjustment
- picochip_special_save_area_byte_offset ());
2187 /* Emit a stack adjustment where required. */
2188 if (stack_adjustment
!= 0)
2190 /* If the link/fp is already being restored, and the offset to
2191 their save location is small enough, don't bother adjusting
2192 the stack explicitly. */
2193 if (picochip_special_save_area_byte_offset () < 512 &&
2194 !picochip_can_eliminate_link_sp_save ())
2195 use_link_fp_restore_stack_adjust
= 1;
2197 /* Explicitly restore the stack. */
2198 picochip_emit_stack_allocate (-stack_adjustment
);
2201 /* Restore the Link/FP registers. Only save the link register? */
2202 if (!picochip_can_eliminate_link_sp_save ())
2204 if (use_link_fp_restore_stack_adjust
)
2205 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2206 picochip_special_save_area_byte_offset
2209 picochip_emit_restore_register (gen_rtx_REG (SImode
, LINK_REGNUM
),
2210 special_save_offset
);
2213 /* Restore callee-save registers. */
2214 reg_save_offset
= 0;
2215 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2217 if (picochip_reg_needs_saving (i
))
2220 /* If this register is an even numbered register, and the
2221 next register also needs to be saved, use a SImode save,
2222 which does both in one instruction. Note that a special
2223 check is performed to ensure that the double word aligned
2224 store is valid (e.g., it is possible that r6, r8, r9 need
2225 to be saved, in which case once r6 has been saved, the
2226 stored offset is no longer aligned, and an STL/LDL
2227 instruction becomes invalid). We could store all aligned
2228 registers first, and then save the single one(s). */
2230 picochip_reg_needs_saving (i
+ 1) &&
2231 picochip_is_aligned (reg_save_offset
, LONG_TYPE_SIZE
))
2233 picochip_emit_restore_register (gen_rtx_REG (SImode
, i
),
2234 general_save_offset
+
2236 reg_save_offset
+= 2 * UNITS_PER_WORD
;
2241 picochip_emit_restore_register (gen_rtx_REG (HImode
, i
),
2242 general_save_offset
+
2244 reg_save_offset
+= UNITS_PER_WORD
;
2250 /* Emit a return instruction, which matches a (parallel
2251 [(return) (use r12)]) */
2254 p
= rtvec_alloc (2);
2256 RTVEC_ELT (p
, 0) = ret_rtx
;
2257 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
,
2258 gen_rtx_REG (Pmode
, LINK_REGNUM
));
2259 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
2264 /* Assembly instruction output. */
2266 /* Test whether the given branch instruction is short, or long. Short
2267 * branches are equivalent to real branches, and may be DFA
2268 * scheduled. Long branches expand to a macro which is handled by the
2269 * elaborator, and cannot be scheduled. Occasionally, the branch
2270 * shortening pass, which is run after DFA scheduling, will change the
2271 * code layout and cause the short branch to be reverted into a long
2272 * branch. Instead of having to fix this up by emitting new assembly,
2273 * the short branch is emitted anyway. There is plenty of slack in the
2274 * calculation of long and short branches (10-bit offset, but only
2275 * 9-bits used in computation), so there is enough slack for this to
2278 picochip_is_short_branch (rtx insn
)
2280 int isRealShortBranch
= (get_attr_length(insn
) == SHORT_BRANCH_LENGTH
);
2282 return (isRealShortBranch
||
2283 picochip_current_vliw_state
.num_insns_in_packet
> 1);
2286 /* Output a compare-and-branch instruction (matching the cbranch
2289 picochip_output_cbranch (rtx operands
[])
2292 if (HImode
!= GET_MODE (operands
[1]) ||
2293 (HImode
!= GET_MODE (operands
[2]) &&
2294 GET_CODE (operands
[2]) != CONST_INT
))
2296 internal_error ("%s: at least one operand can%'t be handled",
2300 /* Use the type of comparison to output the appropriate condition
2302 switch (GET_CODE (operands
[0]))
2305 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2308 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2311 /* Reverse the operand order to be GE */
2312 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2315 /* Reverse operand order of GEU. */
2316 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2319 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2322 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2325 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2328 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2331 /* Reversed operand version of LT. */
2332 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2335 /* Reverse an LTU. */
2336 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2343 /* Output a compare-and-branch instruction (matching the cbranch
2344 pattern). This function is current unused since the cbranch
2345 split is disabled. The function is kept around so we can use
2346 it when we understand how to do cbranch split safely. */
2348 picochip_output_compare (rtx operands
[])
2352 if (HImode
!= GET_MODE (operands
[1]) ||
2353 (HImode
!= GET_MODE (operands
[2]) &&
2354 GET_CODE (operands
[2]) != CONST_INT
))
2356 internal_error ("%s: at least one operand can%'t be handled",
2360 code
= GET_CODE (operands
[0]);
2361 /* Use the type of comparison to output the appropriate condition
2366 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2369 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2372 /* Reverse the operand order to be GE */
2373 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2376 /* Reverse operand order of GEU. */
2377 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2380 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2383 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2386 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2389 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2392 /* Reversed operand version of LT. */
2393 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2396 /* Reverse an LTU. */
2397 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2404 /* Output the branch insn part of a compare-and-branch split. */
2406 picochip_output_branch (rtx operands
[], rtx insn
)
2409 int code
= GET_CODE(operands
[2]);
2410 if (picochip_is_short_branch (insn
))
2412 /* Short branches can be output directly using the
2413 appropriate instruction. */
2417 return ("BNE %l0 %>");
2419 return ("BEQ %l0 %>");
2421 return ("BGE %l0 %>");
2423 return ("BHS %l0 %>");
2425 return ("BGE %l0 %>");
2427 return ("BHS %l0 %>");
2429 return ("BLT %l0 %>");
2431 return ("BLO %l0 %>");
2433 return ("BLT %l0 %>");
2435 return ("BLO %l0 %>");
2437 internal_error ("unknown short branch in %s (type %d)",
2438 __FUNCTION__
, (int) INTVAL (operands
[1]));
2439 return "UNKNOWN_BRANCH";
2444 /* Long branches result in the emission of a special
2445 instruction, which the assembler expands into a suitable long
2448 /* Use the type of comparison to output the appropriate condition
2453 return ("JMPNE %l0 %>");
2455 return ("JMPEQ %l0 %>");
2457 return ("JMPGE %l0 %>");
2459 return ("JMPHS %l0 %>");
2461 return ("JMPGE %l0 %>");
2463 return ("JMPHS %l0 %>");
2465 return ("JMPLT %l0 %>");
2467 return ("JMPLO %l0 %>");
2469 return ("JMPLT %l0 %>");
2471 return ("JMPLO %l0 %>");
2474 internal_error ("unknown long branch in %s (type %d)",
2475 __FUNCTION__
, (int) INTVAL (operands
[1]));
2476 return "UNKNOWN_BRANCH";
2482 /* Output a jump instruction. */
2484 picochip_output_jump (rtx insn
)
2486 if (picochip_is_short_branch (insn
))
2489 return "JMPRA %l0%>";
2493 picochip_output_put_array (int alternative
, rtx operands
[])
2495 /* Local output buffer. */
2498 int portArraySize
= INTVAL(operands
[1]);
2499 int portBaseIndex
= INTVAL(operands
[2]);
2501 if (alternative
== 0)
2503 sprintf (buf
, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2504 portArraySize
, portBaseIndex
);
2505 output_asm_insn (buf
, operands
);
2507 else if (alternative
== 1)
2509 /* Constant port id. Emit a real instruction. */
2510 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2511 if (portIndex
< portBaseIndex
||
2512 portIndex
>= (portBaseIndex
+ portArraySize
))
2514 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2515 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2517 sprintf(buf
, "PUT R[0:1],%d", portIndex
);
2518 output_asm_insn (buf
, operands
);
2523 /* Both alternatives output the insn directly. */
2527 const char *picochip_output_get_array (int alternative
, rtx operands
[])
2529 /* Local output buffer. */
2532 int portArraySize
= INTVAL(operands
[1]);
2533 int portBaseIndex
= INTVAL(operands
[2]);
2535 if (alternative
== 0)
2537 sprintf (buf
, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2538 portArraySize
, portBaseIndex
);
2539 output_asm_insn (buf
, operands
);
2541 else if (alternative
== 1)
2543 /* Constant port id. Emit a real instruction. */
2544 int portIndex
= INTVAL(operands
[0]) + portBaseIndex
;
2545 if (portIndex
< portBaseIndex
||
2546 portIndex
>= (portBaseIndex
+ portArraySize
))
2548 error ("GET uses port array index %d, which is out of range [%d..%d)",
2549 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2551 sprintf(buf
, "GET %d,R[0:1]", portIndex
);
2552 output_asm_insn (buf
, operands
);
2557 /* Both alternatives output the insn directly. */
2561 const char *picochip_output_testport_array (int alternative
, rtx operands
[])
2563 /* Local output buffer. */
2566 int portArraySize
= INTVAL(operands
[2]);
2567 int portBaseIndex
= INTVAL(operands
[3]);
2569 if (alternative
== 0)
2571 sprintf (buf
, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2572 portArraySize
, portBaseIndex
);
2573 output_asm_insn (buf
, operands
);
2575 else if (alternative
== 1)
2577 /* Constant port id. Emit a real instruction. */
2578 int portIndex
= INTVAL(operands
[1]) + portBaseIndex
;
2579 if (portIndex
< portBaseIndex
||
2580 portIndex
>= (portBaseIndex
+ portArraySize
))
2582 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2583 portIndex
, portBaseIndex
, portBaseIndex
+ portArraySize
);
2585 sprintf(buf
, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex
);
2586 output_asm_insn (buf
, operands
);
2591 /* Both alternatives output the insn directly. */
2595 /* Output a comparison operand as a symbol (e.g., >). */
2597 picochip_print_comparison (FILE * file
, rtx operand
, int letter
)
2602 /* Output just the comparison symbol. */
2603 switch (GET_CODE (operand
))
2606 fprintf (file
, "!=");
2609 fprintf (file
, "==");
2612 fprintf (file
, ">=");
2615 fprintf (file
, ">={U}");
2618 fprintf (file
, "<");
2621 fprintf (file
, "<{U}");
2624 fprintf (file
, "<=");
2627 fprintf (file
, "<={U}");
2630 fprintf (file
, ">");
2633 fprintf (file
, ">{U}");
2641 /* Output the comparison formatted as operand,symbol,operand */
2642 rtx op0
= XEXP (operand
, 0);
2643 rtx op1
= XEXP (operand
, 1);
2645 picochip_print_operand (file
, op0
, 0);
2646 picochip_print_comparison (file
, operand
, 'i');
2647 picochip_print_operand (file
, op1
, 0);
2651 /* This function generates a memory address operand in the given
2652 mode. That is, if the address contains a constant offset, then the
2653 offset is divided by the required mode size to compute the
2654 mode specific offset. By default, picochip_print_operand_address calls
2655 this function using the natural mode of the operand, but special
2656 operand codes can be used to invoke the computation using an
2657 unnatural mode (e.g., compute the HI aligned address of an SI mode
2660 picochip_print_memory_address (FILE * file
, rtx operand
,
2661 enum machine_mode mode
)
2663 rtx address
= XEXP (operand
, 0);
2666 if (MEM
!= GET_CODE (operand
))
2667 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2672 printf ("picochip_print_memory_address: ");
2673 print_rtl (stdout
, operand
);
2677 switch (GET_CODE (address
))
2681 /* Grab the address components. */
2682 rtx base
= XEXP (address
, 0);
2683 rtx offset
= XEXP (address
, 1);
2685 /* Only handle reg+const addresses */
2686 if (REG
== GET_CODE (base
) && CONST_INT
== GET_CODE (offset
))
2688 /* Sanity check. If an FP+offset address is given, ensure
2689 that the offset lies within the given frame, or a lower
2691 if (REGNO (base
) == STACK_POINTER_REGNUM
)
2692 gcc_assert (INTVAL (offset
) <= (picochip_arg_area_byte_offset () +
2695 /* Print the base register - identical for all modes. */
2696 fprintf (file
, "(");
2697 picochip_print_operand (file
, base
, 'r');
2698 fprintf (file
, ")");
2700 /* Print the constant offset with compensation for the mode. */
2704 picochip_print_operand (file
, offset
, 'Q');
2708 picochip_print_operand (file
, offset
, 'H');
2713 picochip_print_operand (file
, offset
, 'S');
2717 picochip_print_operand (file
, offset
, 'D');
2731 picochip_print_operand (file
, address
, 's');
2740 inner
= XEXP (address
, 0);
2742 /* Sanity check - the CONST memory address must be a base+offset. */
2743 gcc_assert (PLUS
== GET_CODE (inner
));
2745 base
= XEXP (inner
, 0);
2746 offset
= XEXP (inner
, 1);
2748 fprintf (file
, "&_%s%+d", XSTR (base
, 0), XINT (offset
, 0));
2754 /* Register operand. Provide a zero offset. */
2755 fprintf (file
, "(");
2756 picochip_print_operand (file
, address
, 'r');
2757 fprintf (file
, ")0");
2766 /* Output an operand. Formatting letters allow particular parts of
2767 the operand to be output. */
2769 picochip_print_operand (FILE * file
, rtx operand
, int letter
)
2772 /* Handle special cases. */
2775 /* VLIW continuation, for explicit VLIW sequences. */
2777 fprintf (file
, "\\");
2782 fputc (picochip_get_vliw_alu_id (), file
);
2785 /* Delay slot specifier. */
2787 /* This should be handled in asm_output_opcode. */
2790 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2792 switch (GET_CODE (operand
))
2795 fprintf (file
, "AND");
2798 fprintf (file
, "OR");
2801 fprintf (file
, "XOR");
2804 fprintf (file
, "ADD");
2807 fprintf (file
, "SUB");
2814 /* Symbolic instructions (e.g., lshift becomes <<). */
2816 switch (GET_CODE (operand
))
2819 fprintf (file
, "&");
2822 fprintf (file
, "|");
2825 fprintf (file
, "^");
2828 fprintf (file
, "+");
2831 fprintf (file
, "-");
2834 fprintf (file
, "UNKNOWN_INSN");
2839 default: /* Not a punctuation character - process as normal. */
2843 switch (GET_CODE (operand
))
2849 /* Write a range of registers. */
2850 fprintf (file
, "R[%d:%d]", REGNO (operand
) + 1, REGNO (operand
));
2854 /* The upper register of a pair is requested. */
2855 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 1]);
2859 /* The lower register of a pair is requested. Equivalent to the
2860 default, but included for completeness. */
2861 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2865 /* The 3rd register of a DI mode register. */
2866 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 2]);
2870 /* The 4th register of a DI mode register. */
2871 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
) + 3]);
2875 fprintf (file
, "%s", picochip_regnames
[REGNO (operand
)]);
2880 /* A range of letters can be used to format integers. The
2881 letters Q/H/S are used to divide the constant by the width of
2882 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2883 to obtain the upper and lower 16-bits of a 32-bit
2884 constant. Where possible, signed numbers are used, since
2885 signed representations of numbers may be more compact (e.g.,
2886 65535 can be represented as -1, which fits into a small
2887 constant, whereas 65535 requires a large constant). */
2891 fprintf (file
, "%ld", INTVAL (operand
));
2895 fprintf (file
, "%ld", INTVAL (operand
) / 2);
2899 fprintf (file
, "%ld", INTVAL (operand
) / 4);
2903 fprintf (file
, "%d", exact_log2 (INTVAL(operand
)));
2907 fprintf (file
, "%hi", (short) ((INTVAL (operand
) >> 16) & 0xFFFF));
2911 fprintf (file
, "%hi", (short) (INTVAL (operand
) & 0xFFFF));
2915 fprintf (file
, "%ld", INTVAL (operand
));
2925 if (GET_MODE (operand
) != SFmode
)
2926 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2928 REAL_VALUE_FROM_CONST_DOUBLE (rv
, operand
);
2929 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
2934 fprintf (file
, "%hi", (short) ((val
>> 16) & 0xFFFF));
2938 fprintf (file
, "%hi", (short) (val
& 0xFFFF));
2946 /* Output a symbol. The output format must match that of
2947 picochip_output_label. */
2949 /* Ensure that the symbol is marked as referenced. Gcc can
2950 occasionally omit the function bodies when it believes them
2951 to be unreferenced. */
2952 if (SYMBOL_REF_DECL (operand
))
2953 mark_decl_referenced (SYMBOL_REF_DECL (operand
));
2954 fprintf (file
, "&");
2955 assemble_name (file
, XSTR (operand
, 0));
2959 /* This format must match that of picochip_output_label. */
2960 fprintf (file
, "&");
2961 output_asm_label (operand
);
2966 rtx addr
= XEXP (operand
, 0);
2971 if (PLUS
!= GET_CODE (addr
))
2972 fatal_insn ("Bad address, not (reg+disp):", addr
);
2974 picochip_print_operand (file
, XEXP (addr
, 1), 0);
2978 /* Output a memory address in byte mode notation (i.e., the
2979 constant address (if any) is the actual byte address. */
2980 picochip_print_memory_address (file
, operand
, QImode
);
2983 /* Output a constant offset of the given mode (i.e., divide
2984 the constant by the number of units in the mode to get the
2987 picochip_print_memory_address (file
, operand
, QImode
);
2991 picochip_print_memory_address (file
, operand
, HImode
);
2995 picochip_print_memory_address (file
, operand
, SImode
);
2999 picochip_print_memory_address (file
, operand
, SFmode
);
3003 if (PLUS
!= GET_CODE (addr
))
3004 fatal_insn ("Bad address, not (reg+disp):", addr
);
3006 picochip_print_operand (file
, XEXP (addr
, 0), 0);
3009 /* When the mem operand is (reg + big offset) which cannot
3010 be represented in an instruction as operand, the compiler
3011 automatically generates the instruction to put in (reg +
3012 big offset) into another register. In such cases, it
3013 returns '0' as the character. This needs to be handled
3017 if (REG
!= GET_CODE (addr
))
3018 fatal_insn ("Bad address, not register:", addr
);
3020 picochip_print_operand (file
, addr
, 0);
3024 fprintf (file
, "Unknown mem operand - letter %c ",
3026 print_rtl (file
, operand
);
3034 rtx const_exp
= XEXP (operand
, 0);
3036 /* Handle constant offsets to symbol references. */
3037 if (PLUS
== GET_CODE (const_exp
) &&
3038 SYMBOL_REF
== GET_CODE (XEXP (const_exp
, 0)) &&
3039 CONST_INT
== GET_CODE (XEXP (const_exp
, 1)))
3042 picochip_print_operand (file
, XEXP (const_exp
, 0), 0);
3043 if (INTVAL (XEXP (const_exp
, 1)) >= 0)
3044 fprintf (file
, "+");
3045 /* else use the - from the operand (i.e., AP-2)) */
3047 picochip_print_operand (file
, XEXP (const_exp
, 1), letter
);
3056 /* PLUS expressions are of the form (base + offset). Different
3057 options (analagous to those of memory PLUS expressions) are used
3058 to extract the base and offset components. */
3063 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3067 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3072 /* If the expression is composed entirely of constants,
3073 evaluate the result. This should only occur with the
3074 picoChip specific comms instructions, which are emitted as
3075 base+offset expressions. */
3076 if (CONST_INT
== GET_CODE (XEXP (operand
, 0)) &&
3077 CONST_INT
== GET_CODE (XEXP (operand
, 1)))
3079 HOST_WIDE_INT result
= (XINT (XEXP (operand
, 0), 0) +
3080 XINT (XEXP (operand
, 1), 0));
3081 fprintf (file
, "%ld", result
);
3085 fprintf (file
, "(");
3086 picochip_print_operand (file
, XEXP (operand
, 0), 0);
3087 fprintf (file
, "+");
3088 picochip_print_operand (file
, XEXP (operand
, 1), 0);
3089 fprintf (file
, ")");
3096 /* Comparison operations. */
3107 picochip_print_comparison (file
, operand
, letter
);
3111 fprintf (stderr
, "Unknown operand encountered in %s\n", __FUNCTION__
);
3112 print_rtl (file
, operand
);
3119 /* Output an operand address */
3121 picochip_print_operand_address (FILE * file
, rtx operand
)
3124 switch (GET_CODE (operand
))
3128 /* This format must match that of picochip_output_label. */
3129 assemble_name (file
, XSTR (operand
, 0));
3133 /* Note this format must match that of picochip_output_label. */
3134 fprintf (file
, "_L%d", XINT (operand
, 5));
3138 /* Pass on to a specialised memory address generator. */
3139 picochip_print_memory_address (file
, operand
, GET_MODE (operand
));
3150 /* Scheduling functions. */
3152 /* Save some of the contents of recog_data. */
3154 picochip_save_recog_data (void)
3156 picochip_saved_which_alternative
= which_alternative
;
3157 memcpy (&picochip_saved_recog_data
, &recog_data
,
3158 sizeof (struct recog_data_d
));
3161 /* Restore some of the contents of global variable recog_data. */
3163 picochip_restore_recog_data (void)
3165 which_alternative
= picochip_saved_which_alternative
;
3166 memcpy (&recog_data
, &picochip_saved_recog_data
,
3167 sizeof (struct recog_data_d
));
3170 /* Ensure that no var tracking notes are emitted in the middle of a
3171 three-instruction bundle. */
3173 reorder_var_tracking_notes (void)
3179 rtx insn
, next
, last_insn
= NULL_RTX
;
3180 rtx queue
= NULL_RTX
;
3182 /* Iterate through the bb and find the last non-debug insn */
3183 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= NEXT_INSN(insn
))
3185 if (NONDEBUG_INSN_P(insn
))
3189 /* In all normal cases, queue up notes and emit them just before a TImode
3190 instruction. For the last instruction, emit the queued notes just after
3191 the last instruction. */
3192 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN(BB_END (bb
)); insn
= next
)
3194 next
= NEXT_INSN (insn
);
3196 if (insn
== last_insn
)
3200 rtx next_queue
= PREV_INSN (queue
);
3201 PREV_INSN (NEXT_INSN(insn
)) = queue
;
3202 NEXT_INSN(queue
) = NEXT_INSN(insn
);
3203 PREV_INSN(queue
) = insn
;
3204 NEXT_INSN(insn
) = queue
;
3207 /* There is no more to do for this bb. break*/
3210 else if (NONDEBUG_INSN_P (insn
))
3212 /* Emit queued up notes before the first instruction of a bundle. */
3213 if (GET_MODE (insn
) == TImode
)
3217 rtx next_queue
= PREV_INSN (queue
);
3218 NEXT_INSN (PREV_INSN(insn
)) = queue
;
3219 PREV_INSN (queue
) = PREV_INSN(insn
);
3220 PREV_INSN (insn
) = queue
;
3221 NEXT_INSN (queue
) = insn
;
3226 else if (NOTE_P (insn
))
3228 rtx prev
= PREV_INSN (insn
);
3229 PREV_INSN (next
) = prev
;
3230 NEXT_INSN (prev
) = next
;
3231 /* Ignore call_arg notes. They are expected to be just after the
3232 call insn. If the call is start of a long VLIW, labels are
3233 emitted in the middle of a VLIW, which our assembler can not
3235 if (NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
3237 PREV_INSN (insn
) = queue
;
3242 /* Make sure we are not dropping debug instructions.*/
3243 gcc_assert (queue
== NULL_RTX
);
3247 /* Perform machine dependent operations on the rtl chain INSNS. */
3249 picochip_reorg (void)
3251 rtx insn
, insn1
, vliw_start
= NULL_RTX
;
3252 int vliw_insn_location
= 0;
3254 /* We are freeing block_for_insn in the toplev to keep compatibility
3255 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3256 compute_bb_for_insn ();
3261 if (picochip_schedule_type
!= DFA_TYPE_NONE
)
3263 timevar_push (TV_SCHED2
);
3265 /* Process the instruction list, computing the sizes of each
3266 instruction, and consequently branch distances. This can
3267 result in some branches becoming short enough to be treated
3268 as a real branch instruction, rather than an assembly branch
3269 macro which may expand into multiple instructions. The
3270 benefit of shortening branches is that real branch
3271 instructions can be properly DFA scheduled, whereas macro
3273 shorten_branches (get_insns ());
3275 /* Do control and data sched analysis again,
3276 and write some more of the results to dump file. */
3282 timevar_pop (TV_SCHED2
);
3286 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3288 /* Whenever a VLIW packet is generated, all instructions in
3289 that packet must appear to come from the same source
3290 location. The following code finds all the VLIW packets,
3291 and tags their instructions with the location of the first
3292 instruction from the packet. Clearly this will result in
3293 strange behaviour when debugging the code, but since
3294 debugging and optimisation are being used in conjunction,
3295 strange behaviour is certain to occur anyway. */
3296 /* Slight bit of change. If the vliw set contains a branch
3297 or call instruction, we pick its location.*/
3298 for (insn
= get_insns (); insn
; insn
= next_real_insn (insn
))
3301 /* If this is the first instruction in the VLIW packet,
3302 extract its location. */
3303 if (GET_MODE (insn
) == TImode
)
3306 vliw_insn_location
= INSN_LOCATION (insn
);
3308 if (JUMP_P (insn
) || CALL_P(insn
))
3310 vliw_insn_location
= INSN_LOCATION (insn
);
3311 for (insn1
= vliw_start
; insn1
!= insn
; insn1
= next_real_insn (insn1
))
3312 INSN_LOCATION (insn1
) = vliw_insn_location
;
3314 /* Tag subsequent instructions with the same location. */
3315 INSN_LOCATION (insn
) = vliw_insn_location
;
3321 /* Locate the note marking the end of the function's prologue. If
3322 the note appears in the middle of a VLIW packet, move the note to
3323 the end. This avoids unpleasant consequences such as trying to
3324 emit prologue markers (e.g., .loc/.file directives) in the middle
3326 if (picochip_schedule_type
== DFA_TYPE_SPEED
)
3328 rtx prologue_end_note
= NULL
;
3329 rtx last_insn_in_packet
= NULL
;
3331 for (insn
= get_insns (); insn
; insn
= next_insn (insn
))
3333 /* The prologue end must be moved to the end of the VLIW packet. */
3334 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_PROLOGUE_END
)
3336 prologue_end_note
= insn
;
3341 /* Find the last instruction in this packet. */
3342 for (insn
= prologue_end_note
; insn
; insn
= next_real_insn (insn
))
3344 if (GET_MODE (insn
) == TImode
)
3347 last_insn_in_packet
= insn
;
3350 if (last_insn_in_packet
!= NULL
)
3353 = emit_note_after ((enum insn_note
) NOTE_KIND (prologue_end_note
),
3354 last_insn_in_packet
);
3355 memcpy(&NOTE_DATA (tmp_note
), &NOTE_DATA(prologue_end_note
), sizeof(NOTE_DATA(prologue_end_note
)));
3356 delete_insn (prologue_end_note
);
3360 if (flag_var_tracking
)
3362 timevar_push (TV_VAR_TRACKING
);
3363 variable_tracking_main ();
3364 /* We also have to deal with variable tracking notes in the
3365 middle of VLIW packets. */
3366 reorder_var_tracking_notes();
3367 timevar_pop (TV_VAR_TRACKING
);
3371 /* Return the ALU character identifier for the current
3372 instruction. This will be 0 or 1. */
3374 picochip_get_vliw_alu_id (void)
3378 /* Always use ALU 0 if VLIW scheduling is disabled. */
3379 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3382 /* Get the attribute type of the instruction. Note that this can
3383 ruin the contents of recog_data, so save/restore around the
3385 picochip_save_recog_data ();
3386 attr_type
= get_attr_type (picochip_current_prescan_insn
);
3387 picochip_restore_recog_data ();
3389 if (picochip_current_vliw_state
.contains_pico_alu_insn
)
3392 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3393 else it must be the other ALU (either basic or nonCc)
3394 instruction which goes into 1. */
3395 if (attr_type
== TYPE_PICOALU
)
3401 else if (picochip_current_vliw_state
.contains_non_cc_alu_insn
)
3403 /* Is this the non CC instruction? If it is, then stuff it into
3404 ALU 1, else it must be a picoAlu or basicAlu, in which case
3405 it goes into ALU 0. */
3406 if (attr_type
== TYPE_NONCCALU
)
3413 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3414 whether an ALU instruction has already been scheduled in this
3416 switch (picochip_current_vliw_state
.num_alu_insns_so_far
)
3419 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3423 picochip_current_vliw_state
.num_alu_insns_so_far
++;
3427 internal_error ("too many ALU instructions emitted (%d)",
3428 picochip_current_vliw_state
.num_alu_insns_so_far
);
3435 /* Reset any information about the current VLIW packing status. */
3437 picochip_reset_vliw (rtx insn
)
3439 rtx local_insn
= insn
;
3441 /* Nothing to do if VLIW scheduling isn't being used. */
3442 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3446 printf ("%s on insn %d\n", __FUNCTION__
, INSN_UID (insn
));
3449 picochip_current_vliw_state
.contains_pico_alu_insn
= 0;
3450 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 0;
3451 picochip_current_vliw_state
.num_alu_insns_so_far
= 0;
3452 picochip_current_vliw_state
.num_cfi_labels_deferred
= 0;
3453 picochip_current_vliw_state
.lm_label_name
[0] = 0;
3454 picochip_current_vliw_state
.num_insns_in_packet
= 0;
3456 /* Read through the VLIW packet, classifying the instructions where
3461 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3463 local_insn
= NEXT_INSN (local_insn
);
3466 else if (!INSN_P (local_insn
))
3470 /* It is an instruction, but is it ours? */
3471 if (INSN_CODE (local_insn
) != -1)
3475 picochip_current_vliw_state
.num_insns_in_packet
+= 1;
3477 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3478 get_attr_type function can overwrite the values in
3479 the recog_data global, hence this is saved and
3480 restored around the call. Not doing so results in
3481 asm_output_opcode being called with a different
3482 instruction to final_prescan_insn, which is fatal. */
3483 picochip_save_recog_data ();
3484 attr_type
= get_attr_type (local_insn
);
3485 picochip_restore_recog_data ();
3487 if (attr_type
== TYPE_PICOALU
)
3488 picochip_current_vliw_state
.contains_pico_alu_insn
= 1;
3489 if (attr_type
== TYPE_NONCCALU
)
3490 picochip_current_vliw_state
.contains_non_cc_alu_insn
= 1;
3495 /* Get the next instruction. */
3496 local_insn
= NEXT_INSN (local_insn
);
3498 /* Keep going while the next instruction is part of the same
3499 VLIW packet (i.e., its a valid instruction and doesn't mark
3500 the start of a new VLIW packet. */
3502 while (local_insn
&&
3503 (GET_MODE (local_insn
) != TImode
) && (INSN_CODE (local_insn
) != -1));
3508 picochip_sched_reorder (FILE * file
, int verbose
,
3509 rtx
* ready ATTRIBUTE_UNUSED
,
3510 int *n_readyp ATTRIBUTE_UNUSED
, int clock
)
3514 fprintf (file
, ";;\tClock %d\n", clock
);
3516 return picochip_sched_issue_rate ();
3521 picochip_sched_lookahead (void)
3523 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3529 picochip_sched_issue_rate (void)
3534 /* Adjust the scheduling cost between the two given instructions,
3535 which have the given dependency. */
3537 picochip_sched_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
3542 printf ("Sched Adjust Cost: %d->%d is %d\n",
3543 INSN_UID (insn
), INSN_UID (dep_insn
), cost
);
3545 printf (" Dependency type:");
3546 switch (REG_NOTE_KIND (link
))
3554 case REG_DEP_OUTPUT
:
3555 printf ("OUTPUT\n");
3558 printf ("Unknown (%d)\n", REG_NOTE_KIND (link
));
3562 /* Anti-dependencies are used to enforce the ordering between a
3563 * branch, and any subsequent instructions. For example:
3568 * The ADD instruction must execute after the branch, and this is
3569 * enforced using an anti-dependency. Unfortunately, VLIW machines
3570 * are happy to execute anti-dependent instructions in the same
3571 * cycle, which then results in a schedule like the following being
3574 * BNE someLabel \ ADD.0 r0,r1,r2
3576 * The instruction which would normally be conditionally executed
3577 * depending upon the outcome of the branch, is now unconditionally
3578 * executed every time. To prevent this happening, any
3579 * anti-dependencies between a branch and another instruction are
3580 * promoted to become real dependencies.
3582 if ((JUMP_P (dep_insn
) || CALL_P(dep_insn
)) && REG_NOTE_KIND (link
) == REG_DEP_ANTI
)
3586 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3587 INSN_UID (insn
), INSN_UID (dep_insn
));
3596 /* Return the minimum of the two values */
3598 minimum (int a
, int b
)
3604 /* I dont expect to get to this function with a==b.*/
3609 /* This function checks if the memory of the two stores are just off by 2 bytes.
3610 It returns the lower memory operand's index.*/
3613 memory_just_off (rtx opnd1
, rtx opnd2
)
3615 int offset1
= 0, offset2
= 0;
3618 if (GET_CODE(XEXP(opnd1
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
, 0),1)) == CONST_INT
)
3620 offset1
= INTVAL(XEXP(XEXP(opnd1
, 0), 1));
3621 reg1
= REGNO(XEXP(XEXP(opnd1
, 0), 0));
3625 reg1
= REGNO(XEXP(opnd1
, 0));
3627 if (GET_CODE(XEXP(opnd2
, 0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
, 0), 1)) == CONST_INT
)
3629 offset2
= INTVAL(XEXP(XEXP(opnd2
, 0), 1));
3630 reg2
= REGNO(XEXP(XEXP(opnd2
, 0), 0));
3634 reg2
= REGNO(XEXP(opnd2
, 0));
3637 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3638 should be 4 byte aligned. We can currently guarantee that only if the base
3639 address is FP(R13) and the offset is aligned. */
3641 if (reg1
== reg2
&& reg1
== 13 && abs(offset1
-offset2
) == 2 && minimum(offset1
, offset2
) % 4 == 0)
3642 return (minimum(offset1
, offset2
) == offset1
) ? 1:2;
3648 registers_just_off (rtx opnd1
, rtx opnd2
)
3651 reg1
= REGNO(opnd1
);
3652 reg2
= REGNO(opnd2
);
3653 if (abs(reg1
-reg2
) == 1 && minimum(reg1
, reg2
) % 2 == 0)
3654 return (minimum(reg1
, reg2
) == reg1
)?1:2;
3658 /* Check to see if the two LDWs can be peepholed together into a LDL
3659 They can be if the registers getting loaded into are contiguous
3660 and the memory addresses are contiguous as well.
3664 can be merged together into
3668 1. The LDWs themselves only guarantee that r11 will be a 2-byte
3669 aligned address. Only FP can be assumed to be 4 byte aligned.
3670 2. The progression of addresses and the register numbers should
3671 be similar. For eg., if you swap r2 and r3 in the above instructions,
3672 the resultant pair cannot be merged.
3676 ok_to_peephole_ldw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3678 int memtest
=0,regtest
=0;
3679 regtest
= registers_just_off(opnd1
,opnd3
);
3683 memtest
= memory_just_off(opnd0
,opnd2
);
3687 if (regtest
== memtest
)
3694 /* Similar to LDW peephole */
3696 ok_to_peephole_stw(rtx opnd0
, rtx opnd1
, rtx opnd2
, rtx opnd3
)
3698 int memtest
=0,regtest
=0;
3699 regtest
= registers_just_off(opnd1
,opnd3
);
3703 memtest
= memory_just_off(opnd0
,opnd2
);
3707 if (regtest
== memtest
)
3715 /* Generate a SImode register with the register number that is the smaller of the two */
3717 gen_min_reg(rtx opnd1
,rtx opnd2
)
3719 return gen_rtx_REG (SImode
, minimum(REGNO(opnd1
),REGNO(opnd2
)));
3722 /* Generate a SImode memory with the address that is the smaller of the two */
3724 gen_SImode_mem(rtx opnd1
,rtx opnd2
)
3726 int offset1
=0,offset2
=0;
3729 if (GET_CODE(XEXP(opnd1
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd1
,0),1)) == CONST_INT
)
3731 offset1
= INTVAL(XEXP(XEXP(opnd1
,0),1));
3732 reg
= XEXP(XEXP(opnd1
,0),0);
3736 reg
= XEXP(opnd1
,0);
3738 if (GET_CODE(XEXP(opnd2
,0)) == PLUS
&& GET_CODE(XEXP(XEXP(opnd2
,0),1)) == CONST_INT
)
3740 offset2
= INTVAL(XEXP(XEXP(opnd2
,0),1));
3742 address
= gen_rtx_PLUS (HImode
, reg
, GEN_INT(minimum(offset1
,offset2
)));
3743 return gen_rtx_MEM(SImode
,address
);
3747 picochip_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
,
3748 int opno ATTRIBUTE_UNUSED
, int* total
, bool speed
)
3755 /* Need to penalize immediates that need to be encoded as long constants.*/
3756 if (code
== CONST_INT
&& !(INTVAL (x
) >= 0 && INTVAL (x
) < 16))
3758 *total
= COSTS_N_INSNS(1);
3766 *total
= COSTS_N_INSNS (outer_code
!= MEM
);
3771 /* if_then_else come out of cbranch instructions. It will get split into
3772 a condition code generating subtraction and a branch */
3773 *total
= COSTS_N_INSNS (2);
3780 if (GET_MODE(x
) == SImode
)
3781 *total
= COSTS_N_INSNS (2);
3782 if (GET_MODE(x
) == DImode
)
3783 *total
= COSTS_N_INSNS (4);
3787 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3788 if (GET_MODE(x
) == QImode
&& !TARGET_HAS_BYTE_ACCESS
)
3789 *total
= COSTS_N_INSNS (10);
3791 /* 64-bit accesses have to be done through 2 32-bit access */
3792 if (GET_MODE(x
) == DImode
)
3793 *total
= COSTS_N_INSNS (2);
3799 /* SImode shifts are expensive */
3800 if (GET_MODE(x
) == SImode
)
3801 *total
= COSTS_N_INSNS (10);
3803 /* Register shift by constant is cheap. */
3804 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3805 && GET_CODE(XEXP(x
, 0)) == REG
3806 && GET_CODE(XEXP(x
, 1)) == CONST_INT
)
3807 *total
= COSTS_N_INSNS (1);
3809 *total
= COSTS_N_INSNS (4);
3816 /* Divisions are more expensive than the default 7*/
3817 if (GET_MODE(x
) == SImode
)
3818 *total
= COSTS_N_INSNS (20);
3820 *total
= COSTS_N_INSNS (12);
3825 /* Look for the simple cases of multiplying register*register or
3826 register*constant. */
3827 if ((GET_MODE(x
) == QImode
|| GET_MODE(x
) == HImode
)
3828 && ((GET_CODE(XEXP(x
, 0)) == REG
3829 && (GET_CODE(XEXP(x
, 1)) == REG
|| GET_CODE(XEXP(x
,1)) == CONST_INT
))
3830 || (GET_CODE(XEXP(x
, 0)) == ZERO_EXTEND
3831 && GET_CODE(XEXP(XEXP(x
, 0),0)) == REG
3832 && GET_CODE(XEXP(x
, 1)) == ZERO_EXTEND
3833 && GET_CODE(XEXP(XEXP(x
, 1),0)) == REG
)))
3836 /* When optimising for size, multiplication by constant
3837 should be discouraged slightly over multiplication by a
3839 if (picochip_has_mac_unit
)
3841 /* Single cycle multiplication, but the result must be
3842 loaded back into a general register afterwards. */
3843 *total
= COSTS_N_INSNS(2);
3846 else if (picochip_has_mul_unit
)
3848 /* Single cycle multiplication. */
3849 *total
= COSTS_N_INSNS(1);
3852 /* Else no multiply available. Use default cost. */
3862 if (localTotal
!= 0)
3864 *total
= localTotal
;
3875 picochip_final_prescan_insn (rtx insn
, rtx
* opvec ATTRIBUTE_UNUSED
,
3876 int num_operands ATTRIBUTE_UNUSED
)
3880 picochip_current_prescan_insn
= insn
;
3883 printf ("Final prescan on INSN %d with mode %s\n",
3884 INSN_UID (insn
), GET_MODE_NAME (GET_MODE (insn
)));
3886 /* If this is the start of a new instruction cycle, or no scheduling
3887 is used, then reset the VLIW status. */
3888 if (GET_MODE (insn
) == TImode
|| !picochip_schedule_type
== DFA_TYPE_SPEED
)
3889 picochip_reset_vliw (insn
);
3891 /* No VLIW scheduling occurred, so don't go any further. */
3892 if (picochip_schedule_type
!= DFA_TYPE_SPEED
)
3895 /* Look for the next printable instruction. This loop terminates on
3896 any recognisable instruction, and on any unrecognisable
3897 instruction with TImode. */
3899 for (local_insn
= NEXT_INSN (local_insn
); local_insn
;
3900 local_insn
= NEXT_INSN (local_insn
))
3902 if (NOTE_P (local_insn
) || DEBUG_INSN_P(local_insn
))
3904 else if (!INSN_P (local_insn
))
3906 else if (GET_MODE (local_insn
) == TImode
3907 || INSN_CODE (local_insn
) != -1)
3911 /* Set the continuation flag if the next instruction can be packed
3912 with the current instruction (i.e., the next instruction is
3913 valid, and isn't the start of a new cycle). */
3914 picochip_vliw_continuation
= (local_insn
&& NONDEBUG_INSN_P (local_insn
) &&
3915 (GET_MODE (local_insn
) != TImode
));
3919 /* Builtin functions. */
3920 /* Given a builtin function taking 2 operands (i.e., target + source),
3921 emit the RTL for the underlying instruction. */
3923 picochip_expand_builtin_2op (enum insn_code icode
, tree call
, rtx target
)
3927 enum machine_mode tmode
, mode0
;
3929 /* Grab the incoming argument and emit its RTL. */
3930 arg0
= CALL_EXPR_ARG (call
, 0);
3931 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3933 /* Determine the modes of the instruction operands. */
3934 tmode
= insn_data
[icode
].operand
[0].mode
;
3935 mode0
= insn_data
[icode
].operand
[1].mode
;
3937 /* Ensure that the incoming argument RTL is in a register of the
3939 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3940 op0
= copy_to_mode_reg (mode0
, op0
);
3942 /* If there isn't a suitable target, emit a target register. */
3944 || GET_MODE (target
) != tmode
3945 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3946 target
= gen_reg_rtx (tmode
);
3948 /* Emit and return the new instruction. */
3949 pat
= GEN_FCN (icode
) (target
, op0
);
3958 /* Given a builtin function taking 3 operands (i.e., target + two
3959 source), emit the RTL for the underlying instruction. */
3961 picochip_expand_builtin_3op (enum insn_code icode
, tree call
, rtx target
)
3965 enum machine_mode tmode
, mode0
, mode1
;
3967 /* Grab the function's arguments. */
3968 arg0
= CALL_EXPR_ARG (call
, 0);
3969 arg1
= CALL_EXPR_ARG (call
, 1);
3971 /* Emit rtl sequences for the function arguments. */
3972 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3973 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
3975 /* Get the mode's of each of the instruction operands. */
3976 tmode
= insn_data
[icode
].operand
[0].mode
;
3977 mode0
= insn_data
[icode
].operand
[1].mode
;
3978 mode1
= insn_data
[icode
].operand
[2].mode
;
3980 /* Ensure that each of the function argument rtl sequences are in a
3981 register of the correct mode. */
3982 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
3983 op0
= copy_to_mode_reg (mode0
, op0
);
3984 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
3985 op1
= copy_to_mode_reg (mode1
, op1
);
3987 /* If no target has been given, create a register to use as the target. */
3989 || GET_MODE (target
) != tmode
3990 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
3991 target
= gen_reg_rtx (tmode
);
3993 /* Emit and return the new instruction. */
3994 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
4003 /* Expand a builtin function which takes two arguments, and returns a void. */
4005 picochip_expand_builtin_2opvoid (enum insn_code icode
, tree call
)
4009 enum machine_mode mode0
, mode1
;
4011 /* Grab the function's arguments. */
4012 arg0
= CALL_EXPR_ARG (call
, 0);
4013 arg1
= CALL_EXPR_ARG (call
, 1);
4015 /* Emit rtl sequences for the function arguments. */
4016 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4017 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4019 /* Get the mode's of each of the instruction operands. */
4020 mode0
= insn_data
[icode
].operand
[0].mode
;
4021 mode1
= insn_data
[icode
].operand
[1].mode
;
4023 /* Ensure that each of the function argument rtl sequences are in a
4024 register of the correct mode. */
4025 if (!(*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
4026 op0
= copy_to_mode_reg (mode0
, op0
);
4027 if (!(*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
4028 op1
= copy_to_mode_reg (mode1
, op1
);
4030 /* Emit and return the new instruction. */
4031 pat
= GEN_FCN (icode
) (op0
, op1
);
4040 /* Expand an array get into the corresponding RTL. */
4042 picochip_expand_array_get (tree call
, rtx target
)
4044 tree arg0
, arg1
, arg2
;
4045 rtx op0
, op1
, op2
, pat
;
4047 /* Grab the function's arguments. */
4048 arg0
= CALL_EXPR_ARG (call
, 0);
4049 arg1
= CALL_EXPR_ARG (call
, 1);
4050 arg2
= CALL_EXPR_ARG (call
, 2) ;
4052 /* Emit rtl sequences for the function arguments. */
4053 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4054 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4055 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4057 /* The second and third operands must be constant. Nothing else will
4059 if (CONST_INT
!= GET_CODE (op1
))
4060 internal_error ("%s: Second source operand is not a constant",
4062 if (CONST_INT
!= GET_CODE (op2
))
4063 internal_error ("%s: Third source operand is not a constant",
4066 /* If no target has been given, create a register to use as the target. */
4067 if (target
== 0 || GET_MODE (target
) != SImode
)
4068 target
= gen_reg_rtx (SImode
);
4070 /* The first operand must be a HImode register or a constant. If it
4071 isn't, force it into a HImode register. */
4072 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4073 op0
= copy_to_mode_reg (HImode
, op0
);
4076 /* Emit and return the new instruction. */
4077 pat
= gen_commsArrayGet (target
, op0
, op1
, op2
);
4084 /* Expand an array put into the corresponding RTL. */
4086 picochip_expand_array_put (tree call
, rtx target
)
4088 tree arg0
, arg1
, arg2
, arg3
;
4089 rtx op0
, op1
, op2
, op3
, pat
;
4091 /* Grab the function's arguments. */
4092 arg0
= CALL_EXPR_ARG (call
, 0);
4093 arg1
= CALL_EXPR_ARG (call
, 1);
4094 arg2
= CALL_EXPR_ARG (call
, 2);
4095 arg3
= CALL_EXPR_ARG (call
, 3);
4097 /* Emit rtl sequences for the function arguments. */
4098 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4099 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4100 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4101 op3
= expand_expr (arg3
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4103 /* The first operand must be an SImode register. */
4104 if (GET_MODE (op0
) != SImode
|| REG
!= GET_CODE (op0
))
4105 op0
= copy_to_mode_reg (SImode
, op0
);
4107 /* The second (index) operand must be a HImode register, or a
4108 constant. If it isn't, force it into a HImode register. */
4109 if (GET_MODE (op1
) != HImode
|| REG
!= GET_CODE (op1
))
4110 op1
= copy_to_mode_reg (HImode
, op1
);
4112 /* The remaining operands must be constant. Nothing else will do. */
4113 if (CONST_INT
!= GET_CODE (op2
))
4114 internal_error ("%s: Third source operand is not a constant",
4116 if (CONST_INT
!= GET_CODE (op3
))
4117 internal_error ("%s: Fourth source operand is not a constant",
4120 /* Emit and return the new instruction. */
4121 pat
= gen_commsArrayPut (op0
, op1
, op2
, op3
);
4128 /* Expand an array testport into the corresponding RTL. */
4130 picochip_expand_array_testport (tree call
, rtx target
)
4132 tree arg0
, arg1
, arg2
;
4133 rtx op0
, op1
, op2
, pat
;
4135 /* Grab the function's arguments. */
4136 arg0
= CALL_EXPR_ARG (call
, 0);
4137 arg1
= CALL_EXPR_ARG (call
, 1);
4138 arg2
= CALL_EXPR_ARG (call
, 2);
4140 /* Emit rtl sequences for the function arguments. */
4141 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4142 op1
= expand_expr (arg1
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4143 op2
= expand_expr (arg2
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
4145 /* The first operand must be a HImode register, or a constant. If it
4146 isn't, force it into a HImode register. */
4147 if (GET_MODE (op0
) != HImode
|| REG
!= GET_CODE (op0
))
4148 op0
= copy_to_mode_reg (HImode
, op0
);
4150 /* The second and third operands must be constant. Nothing else will
4152 if (CONST_INT
!= GET_CODE (op1
))
4153 internal_error ("%s: Second source operand is not a constant",
4155 if (CONST_INT
!= GET_CODE (op2
))
4156 internal_error ("%s: Third source operand is not a constant",
4159 /* If no target has been given, create a HImode register to use as
4161 if (target
== 0 || GET_MODE (target
) != HImode
)
4162 target
= gen_reg_rtx (HImode
);
4164 /* Emit and return the new instruction. */
4165 pat
= gen_commsArrayTestPort (target
, op0
, op1
, op2
);
4172 /* Generate a unique HALT instruction by giving the instruction a
4173 unique integer. This integer makes no difference to the assembly
4174 output (other than a comment indicating the supplied id), but the
4175 presence of the unique integer prevents the compiler from combining
4176 several different halt instructions into one instruction. This
4177 means that each use of the halt instruction is unique, which in
4178 turn means that assertions work as expected. */
4180 picochip_generate_halt (void)
4182 static int currentId
= 0;
4184 rtx id
= GEN_INT (currentId
);
4188 emit_insn (gen_halt (id
));
4190 /* A barrier is inserted to prevent the compiler from thinking that
4191 it has to continue execution after the HALT.*/
4194 insns
= get_insns();
4201 /* Initialise the builtin functions. Start by initialising
4202 descriptions of different types of functions (e.g., void fn(int),
4203 int fn(void)), and then use these to define the builtins. */
4205 picochip_init_builtins (void)
4209 tree int_ftype_int
, int_ftype_int_int
;
4210 tree long_ftype_int
, long_ftype_int_int_int
;
4211 tree void_ftype_int_long
, int_ftype_int_int_int
,
4212 void_ftype_long_int_int_int
;
4213 tree void_ftype_void
, unsigned_ftype_unsigned
;
4215 /* void func (void) */
4216 void_ftype_void
= build_function_type_list (void_type_node
, NULL_TREE
);
4218 /* int func (int) */
4219 int_ftype_int
= build_function_type_list (integer_type_node
,
4220 integer_type_node
, NULL_TREE
);
4222 /* unsigned int func (unsigned int) */
4223 unsigned_ftype_unsigned
4224 = build_function_type_list (unsigned_type_node
,
4225 unsigned_type_node
, NULL_TREE
);
4227 /* int func(int, int) */
4229 = build_function_type_list (integer_type_node
,
4230 integer_type_node
, integer_type_node
,
4233 /* long func(int) */
4234 long_ftype_int
= build_function_type_list (long_integer_type_node
,
4235 integer_type_node
, NULL_TREE
);
4237 /* long func(int, int, int) */
4238 long_ftype_int_int_int
4239 = build_function_type_list (long_integer_type_node
,
4240 integer_type_node
, integer_type_node
,
4241 integer_type_node
, NULL_TREE
);
4243 /* int func(int, int, int) */
4244 int_ftype_int_int_int
4245 = build_function_type_list (integer_type_node
,
4246 integer_type_node
, integer_type_node
,
4247 integer_type_node
, NULL_TREE
);
4249 /* void func(int, long) */
4251 = build_function_type_list (void_type_node
,
4252 integer_type_node
, long_integer_type_node
,
4255 /* void func(long, int, int, int) */
4256 void_ftype_long_int_int_int
4257 = build_function_type_list (void_type_node
,
4258 long_integer_type_node
, integer_type_node
,
4259 integer_type_node
, integer_type_node
,
4262 /* Initialise the sign-bit-count function. */
4263 add_builtin_function ("__builtin_sbc", int_ftype_int
,
4264 PICOCHIP_BUILTIN_SBC
, BUILT_IN_MD
, NULL
,
4266 add_builtin_function ("picoSbc", int_ftype_int
, PICOCHIP_BUILTIN_SBC
,
4267 BUILT_IN_MD
, NULL
, NULL_TREE
);
4269 /* Initialise the bit reverse function. */
4270 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned
,
4271 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4273 add_builtin_function ("picoBrev", unsigned_ftype_unsigned
,
4274 PICOCHIP_BUILTIN_BREV
, BUILT_IN_MD
, NULL
,
4277 /* Initialise the byte swap function. */
4278 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned
,
4279 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4281 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned
,
4282 PICOCHIP_BUILTIN_BYTESWAP
, BUILT_IN_MD
, NULL
,
4285 /* Initialise the ASRI function (note that while this can be coded
4286 using a signed shift in C, extra scratch registers are required,
4287 which we avoid by having a direct builtin to map to the
4289 add_builtin_function ("__builtin_asri", int_ftype_int_int
,
4290 PICOCHIP_BUILTIN_ASRI
, BUILT_IN_MD
, NULL
,
4293 /* Initialise saturating addition. */
4294 add_builtin_function ("__builtin_adds", int_ftype_int_int
,
4295 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4297 add_builtin_function ("picoAdds", int_ftype_int_int
,
4298 PICOCHIP_BUILTIN_ADDS
, BUILT_IN_MD
, NULL
,
4301 /* Initialise saturating subtraction. */
4302 add_builtin_function ("__builtin_subs", int_ftype_int_int
,
4303 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4305 add_builtin_function ("picoSubs", int_ftype_int_int
,
4306 PICOCHIP_BUILTIN_SUBS
, BUILT_IN_MD
, NULL
,
4309 /* Scalar comms builtins. */
4310 add_builtin_function ("__builtin_get", long_ftype_int
,
4311 PICOCHIP_BUILTIN_GET
, BUILT_IN_MD
, NULL
,
4313 add_builtin_function ("__builtin_put", void_ftype_int_long
,
4314 PICOCHIP_BUILTIN_PUT
, BUILT_IN_MD
, NULL
,
4316 add_builtin_function ("__builtin_testport", int_ftype_int
,
4317 PICOCHIP_BUILTIN_TESTPORT
, BUILT_IN_MD
, NULL
,
4320 /* Array comms builtins. */
4321 add_builtin_function ("__builtin_put_array",
4322 void_ftype_long_int_int_int
,
4323 PICOCHIP_BUILTIN_PUT_ARRAY
, BUILT_IN_MD
, NULL
,
4325 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int
,
4326 PICOCHIP_BUILTIN_GET_ARRAY
, BUILT_IN_MD
, NULL
,
4328 add_builtin_function ("__builtin_testport_array",
4329 int_ftype_int_int_int
,
4330 PICOCHIP_BUILTIN_TESTPORT_ARRAY
, BUILT_IN_MD
,
4333 /* Halt instruction. Note that the builtin function is marked as
4334 having the attribute `noreturn' so that the compiler realises
4335 that the halt stops the program dead. */
4336 noreturn
= tree_cons (get_identifier ("noreturn"), NULL
, NULL
);
4337 add_builtin_function ("__builtin_halt", void_ftype_void
,
4338 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4340 add_builtin_function ("picoHalt", void_ftype_void
,
4341 PICOCHIP_BUILTIN_HALT
, BUILT_IN_MD
, NULL
,
4346 /* Expand a call to a builtin function. */
4348 picochip_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
4349 enum machine_mode mode ATTRIBUTE_UNUSED
,
4350 int ignore ATTRIBUTE_UNUSED
)
4352 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
4353 int fcode
= DECL_FUNCTION_CODE (fndecl
);
4357 case PICOCHIP_BUILTIN_ASRI
:
4358 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri
, exp
,
4361 case PICOCHIP_BUILTIN_ADDS
:
4362 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3
, exp
,
4365 case PICOCHIP_BUILTIN_SUBS
:
4366 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3
, exp
,
4369 case PICOCHIP_BUILTIN_SBC
:
4370 return picochip_expand_builtin_2op (CODE_FOR_sbc
, exp
, target
);
4372 case PICOCHIP_BUILTIN_BREV
:
4373 return picochip_expand_builtin_2op (CODE_FOR_brev
, exp
, target
);
4375 case PICOCHIP_BUILTIN_BYTESWAP
:
4376 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2
, exp
, target
);
4378 case PICOCHIP_BUILTIN_GET
:
4379 return picochip_expand_builtin_2op (CODE_FOR_commsGet
, exp
, target
);
4381 case PICOCHIP_BUILTIN_PUT
:
4382 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut
, exp
);
4384 case PICOCHIP_BUILTIN_TESTPORT
:
4385 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort
, exp
,
4388 case PICOCHIP_BUILTIN_PUT_ARRAY
:
4389 return picochip_expand_array_put (exp
, target
);
4391 case PICOCHIP_BUILTIN_GET_ARRAY
:
4392 return picochip_expand_array_get (exp
, target
);
4394 case PICOCHIP_BUILTIN_TESTPORT_ARRAY
:
4395 return picochip_expand_array_testport (exp
, target
);
4397 case PICOCHIP_BUILTIN_HALT
:
4398 return picochip_generate_halt ();
4405 /* Should really do something sensible here. */
4409 /* Emit warnings. */
4411 picochip_warn_inefficient (const char *msg
)
4413 if (TARGET_INEFFICIENT_WARNINGS
)
4414 warning (OPT_minefficient_warnings
,
4415 "%s (disable warning using -mno-inefficient-warnings)", msg
);
4419 warn_of_byte_access (void)
4421 static int warned
= 0;
4425 picochip_warn_inefficient
4426 ("byte access is synthesised - consider using MUL AE");
4433 picochip_function_value (const_tree valtype
, const_tree func
,
4434 bool outgoing ATTRIBUTE_UNUSED
)
4436 enum machine_mode mode
= TYPE_MODE (valtype
);
4437 int unsignedp
= TYPE_UNSIGNED (valtype
);
4439 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4440 just as PROMOTE_MODE does. */
4441 mode
= promote_function_mode (valtype
, mode
, &unsignedp
, func
, 1);
4443 return gen_rtx_REG (mode
, 0);
4447 /* Check that the value of the given mode will fit in the register of
4450 picochip_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
4453 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4454 return regno
== CC_REGNUM
;
4456 /* If the CC register is being used, then only CC mode values are
4457 allowed (which have already been tested). */
4458 if (regno
== CC_REGNUM
|| regno
== ACC_REGNUM
)
4461 /* Must be a valid register. */
4465 /* Modes QI and HI may be placed in any register except the CC. */
4466 if (mode
== QImode
|| mode
== HImode
)
4469 /* DI must be in a quad register. */
4471 return (regno
% 4 == 0);
4473 /* All other modes must be placed in a even numbered register. */
4474 return !(regno
& 1);
4478 /* Extract the lower and upper components of a constant value. */
4481 picochip_get_low_const (rtx value
)
4483 return gen_int_mode (INTVAL (value
) & 0xFFFF, HImode
);
4487 picochip_get_high_const (rtx value
)
4489 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4490 return gen_int_mode ((INTVAL (value
) >> 16) & 0xFFFF, HImode
);
4494 /* Loading and storing QImode values to and from memory in a machine
4495 without byte access requires might require a scratch
4496 register. However, the scratch register might correspond to the
4497 register in which the value is being loaded. To ensure that a
4498 scratch register is supplied which is definitely different to the
4499 output register, request a register pair. This effectively gives a
4500 choice of two registers to choose from, so that we a guaranteed to
4501 get at least one register which is different to the output
4502 register. This trick is taken from the alpha implementation. */
4504 picochip_secondary_reload (bool in_p
,
4505 rtx x ATTRIBUTE_UNUSED
,
4506 reg_class_t cla ATTRIBUTE_UNUSED
,
4507 enum machine_mode mode
,
4508 secondary_reload_info
*sri
)
4510 if (mode
== QImode
&& !TARGET_HAS_BYTE_ACCESS
)
4513 sri
->icode
= CODE_FOR_reload_outqi
;
4515 sri
->icode
= CODE_FOR_reload_inqi
;
4518 /* We dont need to return a register class type when we need only a
4519 scratch register. It realizes the scratch register type by looking
4520 at the instruction definition for sri->icode. We only need to
4521 return the register type when we need intermediaries for copies.*/
4525 /* Return true if the given memory operand can be aligned to a
4526 word+offset memory reference (e.g., FP+3 can be converted into the
4527 memory operand FP+2, with the offset 1). */
4529 picochip_alignable_memory_operand (rtx mem_operand
,
4530 enum machine_mode mode ATTRIBUTE_UNUSED
)
4534 /* Not a mem operand. Refuse immediately. */
4535 if (MEM
!= GET_CODE (mem_operand
))
4538 address
= XEXP (mem_operand
, 0);
4540 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4541 return ((PLUS
== GET_CODE (address
) &&
4542 REGNO (XEXP (address
, 0)) == STACK_POINTER_REGNUM
&&
4543 CONST_INT
== GET_CODE (XEXP (address
, 1)) &&
4544 picochip_const_ok_for_letter_p (INTVAL (XEXP (address
, 1)), 'K'))
4545 || (REG
== GET_CODE (address
)
4546 && REGNO (address
) == STACK_POINTER_REGNUM
));
4550 /* Return true if the given memory reference is to a word aligned
4551 address. Currently this means it must be either SP, or
4552 SP+offset. We could replace this function with alignable
4553 memory references in the above function?. */
4555 picochip_word_aligned_memory_reference (rtx operand
)
4559 /* The address must be the SP register, or a constant, aligned
4560 offset from SP which doesn't exceed the FP+offset
4562 return ((PLUS
== GET_CODE (operand
)
4563 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
4564 && picochip_is_aligned (INTVAL (XEXP (operand
, 1)), 16)
4565 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand
, 1)),
4567 || (REG
== GET_CODE (operand
)
4568 && REGNO (operand
) == STACK_POINTER_REGNUM
));
4572 /* Given an alignable memory location, convert the memory location
4573 into a HI mode access, storing the new memory reference in
4574 paligned_mem, and the number of bits by which to shift in pbitnum
4575 (i.e., given a reference to FP+3, this creates an aligned reference
4576 of FP+2, with an 8-bit shift). This code is a modification of that
4577 found in the Alpha port. */
4579 picochip_get_hi_aligned_mem (rtx ref
, rtx
* paligned_mem
, rtx
* pbitnum
)
4582 HOST_WIDE_INT offset
= 0;
4584 gcc_assert (GET_CODE (ref
) == MEM
);
4586 if (reload_in_progress
&& !memory_address_p (GET_MODE (ref
), XEXP (ref
, 0)))
4588 base
= find_replacement (&XEXP (ref
, 0));
4590 gcc_assert(memory_address_p (GET_MODE (ref
), base
));
4594 base
= XEXP (ref
, 0);
4597 if (GET_CODE (base
) == PLUS
)
4599 offset
+= INTVAL (XEXP (base
, 1));
4600 base
= XEXP (base
, 0);
4603 *paligned_mem
= widen_memory_access (ref
, HImode
, (offset
& ~1) - offset
);
4610 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4614 *pbitnum
= GEN_INT ((offset
& 1) * 8);
4618 /* Return true if the given operand is an absolute address in memory
4619 (i.e., a symbolic offset). */
4621 picochip_absolute_memory_operand (rtx op
,
4622 enum machine_mode mode ATTRIBUTE_UNUSED
)
4625 if (MEM
== GET_CODE (op
))
4627 rtx address
= XEXP (op
, 0);
4629 /* Symbols are valid absolute addresses. */
4630 if (SYMBOL_REF
== GET_CODE (address
))
4633 /* Constant offsets to symbols are valid absolute addresses. */
4634 if (CONST
== GET_CODE (address
) &&
4635 PLUS
== GET_CODE (XEXP (address
, 0)) &&
4636 SYMBOL_REF
== GET_CODE (XEXP (XEXP (address
, 0), 0)) &&
4637 CONST_INT
== GET_CODE (XEXP (XEXP (address
, 0), 1)))
4644 /* Symbols are valid absolute addresses. */
4645 if (SYMBOL_REF
== GET_CODE (XEXP (op
, 0)))
4654 picochip_asm_named_section (const char *name
,
4655 unsigned int flags ATTRIBUTE_UNUSED
,
4656 tree decl ATTRIBUTE_UNUSED
)
4658 fprintf (asm_out_file
, ".section %s\n", name
);
4662 /* Check if we can make a conditional copy instruction. This is emitted as an
4663 instruction to set the condition register, followed by an instruction which
4664 uses the condition registers to perform the conditional move. */
4666 picochip_check_conditional_copy (rtx
* operands
)
4669 rtx branch_op_0
= XEXP (operands
[1], 0);
4670 rtx branch_op_1
= XEXP (operands
[1], 1);
4672 /* Only HI mode conditional moves are currently allowed. Can we add
4674 if (GET_CODE (operands
[1]) != EQ
&& GET_CODE (operands
[1]) != NE
)
4677 /* Is the comparison valid? Only allow operands which are registers
4678 if they are HImode. SI mode comparisons against 0 could be
4679 handled using logical operations (e.g., SIreg != 0 when low ||
4680 high). Need to find test cases to provoke this though (fixunssfdi
4681 in libgcc does, but is complicated). */
4682 if (register_operand(branch_op_0
, GET_MODE(branch_op_0
)) &&
4683 GET_MODE(branch_op_0
) != HImode
)
4685 if (register_operand(branch_op_1
, GET_MODE(branch_op_1
)) &&
4686 GET_MODE(branch_op_1
) != HImode
)
4695 picochip_static_chain (const_tree
ARG_UNUSED (fndecl
), bool incoming_p
)
4699 addr
= arg_pointer_rtx
;
4701 addr
= plus_constant (Pmode
, stack_pointer_rtx
, -2 * UNITS_PER_WORD
);
4702 return gen_frame_mem (Pmode
, addr
);