1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992-2017 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 Under Section 7 of GPL version 3, you are granted additional
18 permissions described in the GCC Runtime Library Exception, version
19 3.1, as published by the Free Software Foundation.
21 You should have received a copy of the GNU General Public License and
22 a copy of the GCC Runtime Library Exception along with this program;
23 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
24 <http://www.gnu.org/licenses/>. */
26 /* Note that some other tm.h files include this one and then override
27 many of the definitions. */
30 #include "config/powerpcspe/powerpcspe-opts.h"
33 /* Definitions for the object file format. These are set at
36 #define OBJECT_XCOFF 1
39 #define OBJECT_MACHO 4
41 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
42 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
43 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
44 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
51 #define TARGET_AIX_OS 0
54 /* Control whether function entry points use a "dot" symbol when
58 /* Default string to use for cpu if not specified. */
59 #ifndef TARGET_CPU_DEFAULT
60 #define TARGET_CPU_DEFAULT ((char *)0)
63 /* If configured for PPC405, support PPC405CR Erratum77. */
64 #ifdef CONFIG_PPC405CR
65 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405)
67 #define PPC405_ERRATUM77 0
70 #ifndef TARGET_PAIRED_FLOAT
71 #define TARGET_PAIRED_FLOAT 0
74 #ifdef HAVE_AS_POPCNTB
75 #define ASM_CPU_POWER5_SPEC "-mpower5"
77 #define ASM_CPU_POWER5_SPEC "-mpower4"
81 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec"
83 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec"
86 #ifdef HAVE_AS_POPCNTD
87 #define ASM_CPU_POWER7_SPEC "-mpower7"
89 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec"
93 #define ASM_CPU_POWER8_SPEC "-mpower8"
95 #define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC
99 #define ASM_CPU_POWER9_SPEC "-mpower9"
101 #define ASM_CPU_POWER9_SPEC ASM_CPU_POWER8_SPEC
105 #define ASM_CPU_476_SPEC "-m476"
107 #define ASM_CPU_476_SPEC "-mpower4"
110 /* Common ASM definitions used by ASM_SPEC among the various targets for
111 handling -mcpu=xxx switches. There is a parallel list in driver-powerpcspe.c to
112 provide the default assembler options if the user uses -mcpu=native, so if
113 you make changes here, make them also there. */
114 #define ASM_CPU_SPEC \
116 %{mpowerpc64*: -mppc64} \
117 %{!mpowerpc64*: %(asm_default)}} \
118 %{mcpu=native: %(asm_cpu_native)} \
119 %{mcpu=cell: -mcell} \
120 %{mcpu=power3: -mppc64} \
121 %{mcpu=power4: -mpower4} \
122 %{mcpu=power5: %(asm_cpu_power5)} \
123 %{mcpu=power5+: %(asm_cpu_power5)} \
124 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \
125 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \
126 %{mcpu=power7: %(asm_cpu_power7)} \
127 %{mcpu=power8: %(asm_cpu_power8)} \
128 %{mcpu=power9: %(asm_cpu_power9)} \
130 %{mcpu=powerpc: -mppc} \
131 %{mcpu=powerpc64le: %(asm_cpu_power8)} \
132 %{mcpu=rs64a: -mppc64} \
136 %{mcpu=405fp: -m405} \
138 %{mcpu=440fp: -m440} \
140 %{mcpu=464fp: -m440} \
141 %{mcpu=476: %(asm_cpu_476)} \
142 %{mcpu=476fp: %(asm_cpu_476)} \
147 %{mcpu=603e: -mppc} \
148 %{mcpu=ec603e: -mppc} \
150 %{mcpu=604e: -mppc} \
151 %{mcpu=620: -mppc64} \
152 %{mcpu=630: -mppc64} \
156 %{mcpu=7400: -mppc -maltivec} \
157 %{mcpu=7450: -mppc -maltivec} \
158 %{mcpu=G4: -mppc -maltivec} \
163 %{mcpu=970: -mpower4 -maltivec} \
164 %{mcpu=G5: -mpower4 -maltivec} \
165 %{mcpu=8540: -me500} \
166 %{mcpu=8548: -me500} \
167 %{mcpu=e300c2: -me300} \
168 %{mcpu=e300c3: -me300} \
169 %{mcpu=e500mc: -me500mc} \
170 %{mcpu=e500mc64: -me500mc64} \
171 %{mcpu=e5500: -me5500} \
172 %{mcpu=e6500: -me6500} \
173 %{maltivec: -maltivec} \
174 %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \
175 %{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \
178 #define CPP_DEFAULT_SPEC ""
180 #define ASM_DEFAULT_SPEC ""
182 /* This macro defines names of additional specifications to put in the specs
183 that can be used in various specifications like CC1_SPEC. Its definition
184 is an initializer with a subgrouping for each command option.
186 Each subgrouping contains a string constant, that defines the
187 specification name, and a string constant that used by the GCC driver
190 Do not define this macro if it does not need to do anything. */
192 #define SUBTARGET_EXTRA_SPECS
194 #define EXTRA_SPECS \
195 { "cpp_default", CPP_DEFAULT_SPEC }, \
196 { "asm_cpu", ASM_CPU_SPEC }, \
197 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \
198 { "asm_default", ASM_DEFAULT_SPEC }, \
199 { "cc1_cpu", CC1_CPU_SPEC }, \
200 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \
201 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \
202 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \
203 { "asm_cpu_power8", ASM_CPU_POWER8_SPEC }, \
204 { "asm_cpu_power9", ASM_CPU_POWER9_SPEC }, \
205 { "asm_cpu_476", ASM_CPU_476_SPEC }, \
206 SUBTARGET_EXTRA_SPECS
208 /* -mcpu=native handling only makes sense with compiler running on
209 an PowerPC chip. If changing this condition, also change
210 the condition in driver-powerpcspe.c. */
211 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX)
212 /* In driver-powerpcspe.c. */
213 extern const char *host_detect_local_cpu (int argc
, const char **argv
);
214 #define EXTRA_SPEC_FUNCTIONS \
215 { "local_cpu_detect", host_detect_local_cpu },
216 #define HAVE_LOCAL_CPU_DETECT
217 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)"
220 #define ASM_CPU_NATIVE_SPEC "%(asm_default)"
224 #ifdef HAVE_LOCAL_CPU_DETECT
225 #define CC1_CPU_SPEC \
226 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \
227 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}"
229 #define CC1_CPU_SPEC ""
233 /* Architecture type. */
235 /* Define TARGET_MFCRF if the target assembler does not support the
236 optional field operand for mfcr. */
238 #ifndef HAVE_AS_MFCRF
240 #define TARGET_MFCRF 0
243 /* Define TARGET_POPCNTB if the target assembler does not support the
244 popcount byte instruction. */
246 #ifndef HAVE_AS_POPCNTB
247 #undef TARGET_POPCNTB
248 #define TARGET_POPCNTB 0
251 /* Define TARGET_FPRND if the target assembler does not support the
252 fp rounding instructions. */
254 #ifndef HAVE_AS_FPRND
256 #define TARGET_FPRND 0
259 /* Define TARGET_CMPB if the target assembler does not support the
264 #define TARGET_CMPB 0
267 /* Define TARGET_MFPGPR if the target assembler does not support the
268 mffpr and mftgpr instructions. */
270 #ifndef HAVE_AS_MFPGPR
272 #define TARGET_MFPGPR 0
275 /* Define TARGET_DFP if the target assembler does not support decimal
276 floating point instructions. */
282 /* Define TARGET_POPCNTD if the target assembler does not support the
283 popcount word and double word instructions. */
285 #ifndef HAVE_AS_POPCNTD
286 #undef TARGET_POPCNTD
287 #define TARGET_POPCNTD 0
290 /* Define the ISA 2.07 flags as 0 if the target assembler does not support the
291 waitasecond instruction. Allow -mpower8-fusion, since it does not add new
294 #ifndef HAVE_AS_POWER8
295 #undef TARGET_DIRECT_MOVE
298 #undef TARGET_P8_VECTOR
299 #define TARGET_DIRECT_MOVE 0
300 #define TARGET_CRYPTO 0
302 #define TARGET_P8_VECTOR 0
305 /* Define the ISA 3.0 flags as 0 if the target assembler does not support
306 Power9 instructions. Allow -mpower9-fusion, since it does not add new
307 instructions. Allow -misel, since it predates ISA 3.0 and does
308 not require any Power9 features. */
310 #ifndef HAVE_AS_POWER9
311 #undef TARGET_FLOAT128_HW
313 #undef TARGET_P9_VECTOR
314 #undef TARGET_P9_MINMAX
315 #undef TARGET_P9_DFORM_SCALAR
316 #undef TARGET_P9_DFORM_VECTOR
317 #undef TARGET_P9_MISC
318 #define TARGET_FLOAT128_HW 0
319 #define TARGET_MODULO 0
320 #define TARGET_P9_VECTOR 0
321 #define TARGET_P9_MINMAX 0
322 #define TARGET_P9_DFORM_SCALAR 0
323 #define TARGET_P9_DFORM_VECTOR 0
324 #define TARGET_P9_MISC 0
327 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If
328 not, generate the lwsync code as an integer constant. */
329 #ifdef HAVE_AS_LWSYNC
330 #define TARGET_LWSYNC_INSTRUCTION 1
332 #define TARGET_LWSYNC_INSTRUCTION 0
335 /* Define TARGET_TLS_MARKERS if the target assembler does not support
336 arg markers for __tls_get_addr calls. */
337 #ifndef HAVE_AS_TLS_MARKERS
338 #undef TARGET_TLS_MARKERS
339 #define TARGET_TLS_MARKERS 0
341 #define TARGET_TLS_MARKERS tls_markers
344 #ifndef TARGET_SECURE_PLT
345 #define TARGET_SECURE_PLT 0
348 #ifndef TARGET_CMODEL
349 #define TARGET_CMODEL CMODEL_SMALL
352 #define TARGET_32BIT (! TARGET_64BIT)
355 #define HAVE_AS_TLS 0
358 #ifndef TARGET_LINK_STACK
359 #define TARGET_LINK_STACK 0
362 #ifndef SET_TARGET_LINK_STACK
363 #define SET_TARGET_LINK_STACK(X) do { } while (0)
366 #ifndef TARGET_FLOAT128_ENABLE_TYPE
367 #define TARGET_FLOAT128_ENABLE_TYPE 0
370 /* Return 1 for a symbol ref for a thread-local storage symbol. */
371 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
372 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
375 /* For libgcc2 we make sure this is a compile time constant */
376 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__)
377 #undef TARGET_POWERPC64
378 #define TARGET_POWERPC64 1
380 #undef TARGET_POWERPC64
381 #define TARGET_POWERPC64 0
384 /* The option machinery will define this. */
387 #define TARGET_DEFAULT (MASK_MULTIPLE | MASK_STRING)
389 /* FPU operations supported.
390 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must
391 also test TARGET_HARD_FLOAT. */
392 #define TARGET_SINGLE_FLOAT 1
393 #define TARGET_DOUBLE_FLOAT 1
394 #define TARGET_SINGLE_FPU 0
395 #define TARGET_SIMPLE_FPU 0
396 #define TARGET_XILINX_FPU 0
398 /* Recast the processor type to the cpu attribute. */
399 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
401 /* Define generic processor types based upon current deployment. */
402 #define PROCESSOR_COMMON PROCESSOR_PPC601
403 #define PROCESSOR_POWERPC PROCESSOR_PPC604
404 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
406 /* Define the default processor. This is overridden by other tm.h files. */
407 #define PROCESSOR_DEFAULT PROCESSOR_PPC603
408 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
410 /* Specify the dialect of assembler to use. Only new mnemonics are supported
411 starting with GCC 4.8, i.e. just one dialect, but for backwards
412 compatibility with older inline asm ASSEMBLER_DIALECT needs to be
414 #define ASSEMBLER_DIALECT 1
417 #define MASK_DEBUG_STACK 0x01 /* debug stack applications */
418 #define MASK_DEBUG_ARG 0x02 /* debug argument handling */
419 #define MASK_DEBUG_REG 0x04 /* debug register handling */
420 #define MASK_DEBUG_ADDR 0x08 /* debug memory addressing */
421 #define MASK_DEBUG_COST 0x10 /* debug rtx codes */
422 #define MASK_DEBUG_TARGET 0x20 /* debug target attribute/pragma */
423 #define MASK_DEBUG_BUILTIN 0x40 /* debug builtins */
424 #define MASK_DEBUG_ALL (MASK_DEBUG_STACK \
429 | MASK_DEBUG_TARGET \
430 | MASK_DEBUG_BUILTIN)
432 #define TARGET_DEBUG_STACK (rs6000_debug & MASK_DEBUG_STACK)
433 #define TARGET_DEBUG_ARG (rs6000_debug & MASK_DEBUG_ARG)
434 #define TARGET_DEBUG_REG (rs6000_debug & MASK_DEBUG_REG)
435 #define TARGET_DEBUG_ADDR (rs6000_debug & MASK_DEBUG_ADDR)
436 #define TARGET_DEBUG_COST (rs6000_debug & MASK_DEBUG_COST)
437 #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET)
438 #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN)
440 /* Helper macros for TFmode. Quad floating point (TFmode) can be either IBM
441 long double format that uses a pair of doubles, or IEEE 128-bit floating
442 point. KFmode was added as a way to represent IEEE 128-bit floating point,
443 even if the default for long double is the IBM long double format.
444 Similarly IFmode is the IBM long double format even if the default is IEEE
445 128-bit. Don't allow IFmode if -msoft-float. */
446 #define FLOAT128_IEEE_P(MODE) \
447 ((TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
448 || ((MODE) == KFmode) || ((MODE) == KCmode))
450 #define FLOAT128_IBM_P(MODE) \
451 ((!TARGET_IEEEQUAD && ((MODE) == TFmode || (MODE) == TCmode)) \
452 || (TARGET_HARD_FLOAT && TARGET_FPRS \
453 && ((MODE) == IFmode || (MODE) == ICmode)))
455 /* Helper macros to say whether a 128-bit floating point type can go in a
456 single vector register, or whether it needs paired scalar values. */
457 #define FLOAT128_VECTOR_P(MODE) (TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE))
459 #define FLOAT128_2REG_P(MODE) \
460 (FLOAT128_IBM_P (MODE) \
461 || ((MODE) == TDmode) \
462 || (!TARGET_FLOAT128_TYPE && FLOAT128_IEEE_P (MODE)))
464 /* Return true for floating point that does not use a vector register. */
465 #define SCALAR_FLOAT_MODE_NOT_VECTOR_P(MODE) \
466 (SCALAR_FLOAT_MODE_P (MODE) && !FLOAT128_VECTOR_P (MODE))
468 /* Describe the vector unit used for arithmetic operations. */
469 extern enum rs6000_vector rs6000_vector_unit
[];
471 #define VECTOR_UNIT_NONE_P(MODE) \
472 (rs6000_vector_unit[(MODE)] == VECTOR_NONE)
474 #define VECTOR_UNIT_VSX_P(MODE) \
475 (rs6000_vector_unit[(MODE)] == VECTOR_VSX)
477 #define VECTOR_UNIT_P8_VECTOR_P(MODE) \
478 (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR)
480 #define VECTOR_UNIT_ALTIVEC_P(MODE) \
481 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC)
483 #define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \
484 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
486 (int)VECTOR_P8_VECTOR))
488 /* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either
489 altivec (VMX) or VSX vector instructions. P8 vector support is upwards
490 compatible, so allow it as well, rather than changing all of the uses of the
492 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \
493 (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \
494 (int)VECTOR_ALTIVEC, \
495 (int)VECTOR_P8_VECTOR))
497 /* Describe whether to use VSX loads or Altivec loads. For now, just use the
498 same unit as the vector unit we are using, but we may want to migrate to
499 using VSX style loads even for types handled by altivec. */
500 extern enum rs6000_vector rs6000_vector_mem
[];
502 #define VECTOR_MEM_NONE_P(MODE) \
503 (rs6000_vector_mem[(MODE)] == VECTOR_NONE)
505 #define VECTOR_MEM_VSX_P(MODE) \
506 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
508 #define VECTOR_MEM_P8_VECTOR_P(MODE) \
509 (rs6000_vector_mem[(MODE)] == VECTOR_VSX)
511 #define VECTOR_MEM_ALTIVEC_P(MODE) \
512 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC)
514 #define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \
515 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
517 (int)VECTOR_P8_VECTOR))
519 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \
520 (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \
521 (int)VECTOR_ALTIVEC, \
522 (int)VECTOR_P8_VECTOR))
524 /* Return the alignment of a given vector type, which is set based on the
525 vector unit use. VSX for instance can load 32 or 64 bit aligned words
526 without problems, while Altivec requires 128-bit aligned vectors. */
527 extern int rs6000_vector_align
[];
529 #define VECTOR_ALIGN(MODE) \
530 ((rs6000_vector_align[(MODE)] != 0) \
531 ? rs6000_vector_align[(MODE)] \
532 : (int)GET_MODE_BITSIZE ((MODE)))
534 /* Determine the element order to use for vector instructions. By
535 default we use big-endian element order when targeting big-endian,
536 and little-endian element order when targeting little-endian. For
537 programs being ported from BE Power to LE Power, it can sometimes
538 be useful to use big-endian element order when targeting little-endian.
539 This is set via -maltivec=be, for example. */
540 #define VECTOR_ELT_ORDER_BIG \
541 (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2))
543 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
544 with scalar instructions. */
545 #define VECTOR_ELEMENT_SCALAR_64BIT ((BYTES_BIG_ENDIAN) ? 0 : 1)
547 /* Element number of the 64-bit value in a 128-bit vector that can be accessed
548 with the ISA 3.0 MFVSRLD instructions. */
549 #define VECTOR_ELEMENT_MFVSRLD_64BIT ((BYTES_BIG_ENDIAN) ? 1 : 0)
551 /* Alignment options for fields in structures for sub-targets following
553 ALIGN_POWER word-aligns FP doubles (default AIX ABI).
554 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size).
556 Override the macro definitions when compiling libobjc to avoid undefined
557 reference to rs6000_alignment_flags due to library's use of GCC alignment
558 macros which use the macros below. */
560 #ifndef IN_TARGET_LIBS
561 #define MASK_ALIGN_POWER 0x00000000
562 #define MASK_ALIGN_NATURAL 0x00000001
563 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL)
565 #define TARGET_ALIGN_NATURAL 0
568 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
569 #define TARGET_IEEEQUAD rs6000_ieeequad
570 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
571 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL)
573 #define TARGET_SPE_ABI 0
575 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
576 #define TARGET_FPRS 1
577 #define TARGET_E500_SINGLE 0
578 #define TARGET_E500_DOUBLE 0
579 #define CHECK_E500_OPTIONS do { } while (0)
581 /* ISA 2.01 allowed FCFID to be done in 32-bit, previously it was 64-bit only.
582 Enable 32-bit fcfid's on any of the switches for newer ISA machines or
584 #define TARGET_FCFID (TARGET_POWERPC64 \
585 || TARGET_PPC_GPOPT /* 970/power4 */ \
586 || TARGET_POPCNTB /* ISA 2.02 */ \
587 || TARGET_CMPB /* ISA 2.05 */ \
588 || TARGET_POPCNTD /* ISA 2.06 */ \
589 || TARGET_XILINX_FPU)
591 #define TARGET_FCTIDZ TARGET_FCFID
592 #define TARGET_STFIWX TARGET_PPC_GFXOPT
593 #define TARGET_LFIWAX TARGET_CMPB
594 #define TARGET_LFIWZX TARGET_POPCNTD
595 #define TARGET_FCFIDS TARGET_POPCNTD
596 #define TARGET_FCFIDU TARGET_POPCNTD
597 #define TARGET_FCFIDUS TARGET_POPCNTD
598 #define TARGET_FCTIDUZ TARGET_POPCNTD
599 #define TARGET_FCTIWUZ TARGET_POPCNTD
600 #define TARGET_CTZ TARGET_MODULO
601 #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
602 #define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
604 #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
605 #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
606 #define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64)
607 #define TARGET_DIRECT_MOVE_128 (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
609 #define TARGET_VEXTRACTUB (TARGET_P9_VECTOR && TARGET_DIRECT_MOVE \
610 && TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
613 /* Whether we should avoid (SUBREG:SI (REG:SF) and (SUBREG:SF (REG:SI). */
614 #define TARGET_NO_SF_SUBREG TARGET_DIRECT_MOVE_64BIT
615 #define TARGET_ALLOW_SF_SUBREG (!TARGET_DIRECT_MOVE_64BIT)
617 /* This wants to be set for p8 and newer. On p7, overlapping unaligned
619 #define TARGET_EFFICIENT_OVERLAPPING_UNALIGNED TARGET_EFFICIENT_UNALIGNED_VSX
621 /* Byte/char syncs were added as phased in for ISA 2.06B, but are not present
622 in power7, so conditionalize them on p8 features. TImode syncs need quad
624 #define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \
625 || TARGET_QUAD_MEMORY_ATOMIC \
626 || TARGET_DIRECT_MOVE)
628 #define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC
630 /* Power7 has both 32-bit load and store integer for the FPRs, so we don't need
631 to allocate the SDmode stack slot to get the value into the proper location
633 #define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP)
635 /* ISA 3.0 has new min/max functions that don't need fast math that are being
636 phased in. Min/max using FSEL or XSMAXDP/XSMINDP do not return the correct
637 answers if the arguments are not in the normal range. */
638 #define TARGET_MINMAX_SF (TARGET_SF_FPR && TARGET_PPC_GFXOPT \
639 && (TARGET_P9_MINMAX || !flag_trapping_math))
641 #define TARGET_MINMAX_DF (TARGET_DF_FPR && TARGET_PPC_GFXOPT \
642 && (TARGET_P9_MINMAX || !flag_trapping_math))
644 /* In switching from using target_flags to using rs6000_isa_flags, the options
645 machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
646 OPTION_MASK_<xxx> back into MASK_<xxx>. */
647 #define MASK_ALTIVEC OPTION_MASK_ALTIVEC
648 #define MASK_CMPB OPTION_MASK_CMPB
649 #define MASK_CRYPTO OPTION_MASK_CRYPTO
650 #define MASK_DFP OPTION_MASK_DFP
651 #define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
652 #define MASK_DLMZB OPTION_MASK_DLMZB
653 #define MASK_EABI OPTION_MASK_EABI
654 #define MASK_FLOAT128_TYPE OPTION_MASK_FLOAT128_TYPE
655 #define MASK_FPRND OPTION_MASK_FPRND
656 #define MASK_P8_FUSION OPTION_MASK_P8_FUSION
657 #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
658 #define MASK_HTM OPTION_MASK_HTM
659 #define MASK_ISEL OPTION_MASK_ISEL
660 #define MASK_MFCRF OPTION_MASK_MFCRF
661 #define MASK_MFPGPR OPTION_MASK_MFPGPR
662 #define MASK_MULHW OPTION_MASK_MULHW
663 #define MASK_MULTIPLE OPTION_MASK_MULTIPLE
664 #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE
665 #define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR
666 #define MASK_P9_VECTOR OPTION_MASK_P9_VECTOR
667 #define MASK_P9_MISC OPTION_MASK_P9_MISC
668 #define MASK_POPCNTB OPTION_MASK_POPCNTB
669 #define MASK_POPCNTD OPTION_MASK_POPCNTD
670 #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT
671 #define MASK_PPC_GPOPT OPTION_MASK_PPC_GPOPT
672 #define MASK_RECIP_PRECISION OPTION_MASK_RECIP_PRECISION
673 #define MASK_SOFT_FLOAT OPTION_MASK_SOFT_FLOAT
674 #define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
675 #define MASK_STRING OPTION_MASK_STRING
676 #define MASK_UPDATE OPTION_MASK_UPDATE
677 #define MASK_VSX OPTION_MASK_VSX
678 #define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE
681 #define MASK_POWERPC64 OPTION_MASK_POWERPC64
685 #define MASK_64BIT OPTION_MASK_64BIT
688 #ifdef TARGET_LITTLE_ENDIAN
689 #define MASK_LITTLE_ENDIAN OPTION_MASK_LITTLE_ENDIAN
692 #ifdef TARGET_REGNAMES
693 #define MASK_REGNAMES OPTION_MASK_REGNAMES
696 #ifdef TARGET_PROTOTYPE
697 #define MASK_PROTOTYPE OPTION_MASK_PROTOTYPE
701 #define RS6000_BTM_MODULO OPTION_MASK_MODULO
705 /* For power systems, we want to enable Altivec and VSX builtins even if the
706 user did not use -maltivec or -mvsx to allow the builtins to be used inside
707 of #pragma GCC target or the target attribute to change the code level for a
708 given system. The SPE and Paired builtins are only enabled if you configure
709 the compiler for those builtins, and those machines don't support altivec or
712 #define TARGET_EXTRA_BUILTINS (!TARGET_SPE && !TARGET_PAIRED_FLOAT \
713 && ((TARGET_POWERPC64 \
714 || TARGET_PPC_GPOPT /* 970/power4 */ \
715 || TARGET_POPCNTB /* ISA 2.02 */ \
716 || TARGET_CMPB /* ISA 2.05 */ \
717 || TARGET_POPCNTD /* ISA 2.06 */ \
720 || TARGET_HARD_FLOAT)))
722 /* E500 cores only support plain "sync", not lwsync. */
723 #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
724 || rs6000_cpu == PROCESSOR_PPC8548)
727 /* Whether SF/DF operations are supported on the E500. */
728 #define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \
731 #define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \
732 && !TARGET_FPRS && TARGET_E500_DOUBLE)
734 /* Whether SF/DF operations are supported by the normal floating point unit
735 (or the vector/scalar unit). */
736 #define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
737 && TARGET_SINGLE_FLOAT)
739 #define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \
740 && TARGET_DOUBLE_FLOAT)
742 /* Whether SF/DF operations are supported by any hardware. */
743 #define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE)
744 #define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE)
746 /* Which machine supports the various reciprocal estimate instructions. */
747 #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
748 && TARGET_FPRS && TARGET_SINGLE_FLOAT)
750 #define TARGET_FRE (TARGET_HARD_FLOAT && TARGET_FPRS \
751 && TARGET_DOUBLE_FLOAT \
752 && (TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)))
754 #define TARGET_FRSQRTES (TARGET_HARD_FLOAT && TARGET_POPCNTB \
755 && TARGET_PPC_GFXOPT && TARGET_FPRS \
756 && TARGET_SINGLE_FLOAT)
758 #define TARGET_FRSQRTE (TARGET_HARD_FLOAT && TARGET_FPRS \
759 && TARGET_DOUBLE_FLOAT \
760 && (TARGET_PPC_GFXOPT || VECTOR_UNIT_VSX_P (DFmode)))
762 /* Conditions to allow TOC fusion for loading/storing integers. */
763 #define TARGET_TOC_FUSION_INT (TARGET_P8_FUSION \
764 && TARGET_TOC_FUSION \
765 && (TARGET_CMODEL != CMODEL_SMALL) \
768 /* Conditions to allow TOC fusion for loading/storing floating point. */
769 #define TARGET_TOC_FUSION_FP (TARGET_P9_FUSION \
770 && TARGET_TOC_FUSION \
771 && (TARGET_CMODEL != CMODEL_SMALL) \
772 && TARGET_POWERPC64 \
773 && TARGET_HARD_FLOAT \
775 && TARGET_SINGLE_FLOAT \
776 && TARGET_DOUBLE_FLOAT)
778 /* Macro to say whether we can do optimizations where we need to do parts of
779 the calculation in 64-bit GPRs and then is transfered to the vector
780 registers. Do not allow -maltivec=be for these optimizations, because it
781 adds to the complexity of the code. */
782 #define TARGET_DIRECT_MOVE_64BIT (TARGET_DIRECT_MOVE \
783 && TARGET_P8_VECTOR \
784 && TARGET_POWERPC64 \
785 && TARGET_UPPER_REGS_DI \
786 && (rs6000_altivec_element_order != 2))
788 /* Whether the various reciprocal divide/square root estimate instructions
789 exist, and whether we should automatically generate code for the instruction
791 #define RS6000_RECIP_MASK_HAVE_RE 0x1 /* have RE instruction. */
792 #define RS6000_RECIP_MASK_AUTO_RE 0x2 /* generate RE by default. */
793 #define RS6000_RECIP_MASK_HAVE_RSQRTE 0x4 /* have RSQRTE instruction. */
794 #define RS6000_RECIP_MASK_AUTO_RSQRTE 0x8 /* gen. RSQRTE by default. */
796 extern unsigned char rs6000_recip_bits
[];
798 #define RS6000_RECIP_HAVE_RE_P(MODE) \
799 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RE)
801 #define RS6000_RECIP_AUTO_RE_P(MODE) \
802 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RE)
804 #define RS6000_RECIP_HAVE_RSQRTE_P(MODE) \
805 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_HAVE_RSQRTE)
807 #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \
808 (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE)
810 /* The default CPU for TARGET_OPTION_OVERRIDE. */
811 #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT
814 #define REGISTER_TARGET_PRAGMAS() do { \
815 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \
816 targetm.target_option.pragma_parse = rs6000_pragma_target_parse; \
817 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \
818 rs6000_target_modify_macros_ptr = rs6000_target_modify_macros; \
821 /* Target #defines. */
822 #define TARGET_CPU_CPP_BUILTINS() \
823 rs6000_cpu_cpp_builtins (pfile)
825 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
826 we're compiling for. Some configurations may need to override it. */
827 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
830 if (BYTES_BIG_ENDIAN) \
832 builtin_define ("__BIG_ENDIAN__"); \
833 builtin_define ("_BIG_ENDIAN"); \
834 builtin_assert ("machine=bigendian"); \
838 builtin_define ("__LITTLE_ENDIAN__"); \
839 builtin_define ("_LITTLE_ENDIAN"); \
840 builtin_assert ("machine=littleendian"); \
845 /* Target machine storage layout. */
847 /* Define this macro if it is advisable to hold scalars in registers
848 in a wider mode than that declared by the program. In such cases,
849 the value is constrained to be within the bounds of the declared
850 type, but kept valid in the wider mode. The signedness of the
851 extension may differ from that of the type. */
853 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
854 if (GET_MODE_CLASS (MODE) == MODE_INT \
855 && GET_MODE_SIZE (MODE) < (TARGET_32BIT ? 4 : 8)) \
856 (MODE) = TARGET_32BIT ? SImode : DImode;
858 /* Define this if most significant bit is lowest numbered
859 in instructions that operate on numbered bit-fields. */
860 /* That is true on RS/6000. */
861 #define BITS_BIG_ENDIAN 1
863 /* Define this if most significant byte of a word is the lowest numbered. */
864 /* That is true on RS/6000. */
865 #define BYTES_BIG_ENDIAN 1
867 /* Define this if most significant word of a multiword number is lowest
870 For RS/6000 we can decide arbitrarily since there are no machine
871 instructions for them. Might as well be consistent with bits and bytes. */
872 #define WORDS_BIG_ENDIAN 1
874 /* This says that for the IBM long double the larger magnitude double
875 comes first. It's really a two element double array, and arrays
876 don't index differently between little- and big-endian. */
877 #define LONG_DOUBLE_LARGE_FIRST 1
879 #define MAX_BITS_PER_WORD 64
881 /* Width of a word, in units (bytes). */
882 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
884 #define MIN_UNITS_PER_WORD UNITS_PER_WORD
886 #define MIN_UNITS_PER_WORD 4
888 #define UNITS_PER_FP_WORD 8
889 #define UNITS_PER_ALTIVEC_WORD 16
890 #define UNITS_PER_VSX_WORD 16
891 #define UNITS_PER_SPE_WORD 8
892 #define UNITS_PER_PAIRED_WORD 8
894 /* Type used for ptrdiff_t, as a string used in a declaration. */
895 #define PTRDIFF_TYPE "int"
897 /* Type used for size_t, as a string used in a declaration. */
898 #define SIZE_TYPE "long unsigned int"
900 /* Type used for wchar_t, as a string used in a declaration. */
901 #define WCHAR_TYPE "short unsigned int"
903 /* Width of wchar_t in bits. */
904 #define WCHAR_TYPE_SIZE 16
906 /* A C expression for the size in bits of the type `short' on the
907 target machine. If you don't define this, the default is half a
908 word. (If this would be less than one storage unit, it is
909 rounded up to one unit.) */
910 #define SHORT_TYPE_SIZE 16
912 /* A C expression for the size in bits of the type `int' on the
913 target machine. If you don't define this, the default is one
915 #define INT_TYPE_SIZE 32
917 /* A C expression for the size in bits of the type `long' on the
918 target machine. If you don't define this, the default is one
920 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
922 /* A C expression for the size in bits of the type `long long' on the
923 target machine. If you don't define this, the default is two
925 #define LONG_LONG_TYPE_SIZE 64
927 /* A C expression for the size in bits of the type `float' on the
928 target machine. If you don't define this, the default is one
930 #define FLOAT_TYPE_SIZE 32
932 /* A C expression for the size in bits of the type `double' on the
933 target machine. If you don't define this, the default is two
935 #define DOUBLE_TYPE_SIZE 64
937 /* A C expression for the size in bits of the type `long double' on
938 the target machine. If you don't define this, the default is two
940 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
942 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */
943 #define WIDEST_HARDWARE_FP_SIZE 64
945 /* Width in bits of a pointer.
946 See also the macro `Pmode' defined below. */
947 extern unsigned rs6000_pointer_size
;
948 #define POINTER_SIZE rs6000_pointer_size
950 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
951 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
953 /* Boundary (in *bits*) on which stack pointer should be aligned. */
954 #define STACK_BOUNDARY \
955 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \
958 /* Allocation boundary (in *bits*) for the code of a function. */
959 #define FUNCTION_BOUNDARY 32
961 /* No data type wants to be aligned rounder than this. */
962 #define BIGGEST_ALIGNMENT 128
964 /* Alignment of field after `int : 0' in a structure. */
965 #define EMPTY_FIELD_BOUNDARY 32
967 /* Every structure's size must be a multiple of this. */
968 #define STRUCTURE_SIZE_BOUNDARY 8
970 /* A bit-field declared as `int' forces `int' alignment for the struct. */
971 #define PCC_BITFIELD_TYPE_MATTERS 1
973 enum data_align
{ align_abi
, align_opt
, align_both
};
975 /* A C expression to compute the alignment for a variables in the
976 local store. TYPE is the data type, and ALIGN is the alignment
977 that the object would ordinarily have. */
978 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
979 rs6000_data_alignment (TYPE, ALIGN, align_both)
981 /* Make strings word-aligned so strcpy from constants will be faster. */
982 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
983 (TREE_CODE (EXP) == STRING_CST \
984 && (STRICT_ALIGNMENT || !optimize_size) \
985 && (ALIGN) < BITS_PER_WORD \
989 /* Make arrays of chars word-aligned for the same reasons. */
990 #define DATA_ALIGNMENT(TYPE, ALIGN) \
991 rs6000_data_alignment (TYPE, ALIGN, align_opt)
993 /* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to
995 #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \
996 rs6000_data_alignment (TYPE, ALIGN, align_abi)
998 /* Nonzero if move instructions will actually fail to work
999 when given unaligned data. */
1000 #define STRICT_ALIGNMENT 0
1002 /* Standard register usage. */
1004 /* Number of actual hardware registers.
1005 The hardware registers are assigned numbers for the compiler
1006 from 0 to just below FIRST_PSEUDO_REGISTER.
1007 All registers that the compiler knows about must be given numbers,
1008 even those that are not normally considered general registers.
1010 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
1011 a count register, a link register, and 8 condition register fields,
1012 which we view here as separate registers. AltiVec adds 32 vector
1013 registers and a VRsave register.
1015 In addition, the difference between the frame and argument pointers is
1016 a function of the number of registers saved, so we need to have a
1017 register for AP that will later be eliminated in favor of SP or FP.
1018 This is a normal register, but it is fixed.
1020 We also create a pseudo register for float/int conversions, that will
1021 really represent the memory location used. It is represented here as
1022 a register, in order to work around problems in allocating stack storage
1023 in inline functions.
1025 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
1026 pointer, which is eventually eliminated in favor of SP or FP.
1028 The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */
1030 #define FIRST_PSEUDO_REGISTER 149
1032 /* This must be included for pre gcc 3.0 glibc compatibility. */
1033 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
1035 /* True if register is an SPE High register. */
1036 #define SPE_HIGH_REGNO_P(N) \
1037 ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO)
1039 /* SPE high registers added as hard regs.
1040 The sfp register and 3 HTM registers
1041 aren't included in DWARF_FRAME_REGISTERS. */
1042 #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4)
1044 /* The SPE has an additional 32 synthetic registers, with DWARF debug
1045 info numbering for these registers starting at 1200. While eh_frame
1046 register numbering need not be the same as the debug info numbering,
1047 we choose to number these regs for eh_frame at 1200 too.
1049 We must map them here to avoid huge unwinder tables mostly consisting
1051 #define DWARF_REG_TO_UNWIND_COLUMN(r) \
1052 ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r))
1054 /* Use standard DWARF numbering for DWARF debugging information. */
1055 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number ((REGNO), 0)
1057 /* Use gcc hard register numbering for eh_frame. */
1058 #define DWARF_FRAME_REGNUM(REGNO) (REGNO)
1060 /* Map register numbers held in the call frame info that gcc has
1061 collected using DWARF_FRAME_REGNUM to those that should be output in
1062 .debug_frame and .eh_frame. */
1063 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \
1064 rs6000_dbx_register_number ((REGNO), (FOR_EH)? 2 : 1)
1066 /* 1 for registers that have pervasive standard uses
1067 and are not available for the register allocator.
1069 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
1070 as a local register; for all other OS's r2 is the TOC pointer.
1072 On System V implementations, r13 is fixed and not available for use. */
1074 #define FIXED_REGISTERS \
1075 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
1076 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1077 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1078 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1079 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
1080 /* AltiVec registers. */ \
1081 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1082 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1084 , 1, 1, 1, 1, 1, 1, \
1085 /* SPE High registers. */ \
1086 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1087 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1090 /* 1 for registers not available across function calls.
1091 These must include the FIXED_REGISTERS and also any
1092 registers that can be used without being saved.
1093 The latter must include the registers where values are returned
1094 and the register where structure-value addresses are passed.
1095 Aside from that, you can include as many other registers as you like. */
1097 #define CALL_USED_REGISTERS \
1098 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1099 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1100 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1101 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1102 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1103 /* AltiVec registers. */ \
1104 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1105 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1107 , 1, 1, 1, 1, 1, 1, \
1108 /* SPE High registers. */ \
1109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1110 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1113 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
1114 the entire set of `FIXED_REGISTERS' be included.
1115 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
1116 This macro is optional. If not specified, it defaults to the value
1117 of `CALL_USED_REGISTERS'. */
1119 #define CALL_REALLY_USED_REGISTERS \
1120 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
1121 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1122 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
1123 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1124 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
1125 /* AltiVec registers. */ \
1126 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1127 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1129 , 0, 0, 0, 0, 0, 0, \
1130 /* SPE High registers. */ \
1131 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1132 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1135 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
1137 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20)
1138 #define FIRST_SAVED_FP_REGNO (14+32)
1139 #define FIRST_SAVED_GP_REGNO (FIXED_R13 ? 14 : 13)
1141 /* List the order in which to allocate registers. Each register must be
1142 listed once, even those in FIXED_REGISTERS.
1144 We allocate in the following order:
1145 fp0 (not saved or used for anything)
1146 fp13 - fp2 (not saved; incoming fp arg registers)
1147 fp1 (not saved; return value)
1148 fp31 - fp14 (saved; order given to save least number)
1149 cr7, cr5 (not saved or special)
1150 cr6 (not saved, but used for vector operations)
1151 cr1 (not saved, but used for FP operations)
1152 cr0 (not saved, but used for arithmetic operations)
1153 cr4, cr3, cr2 (saved)
1154 r9 (not saved; best for TImode)
1155 r10, r8-r4 (not saved; highest first for less conflict with params)
1156 r3 (not saved; return value register)
1157 r11 (not saved; later alloc to help shrink-wrap)
1158 r0 (not saved; cannot be base reg)
1159 r31 - r13 (saved; order given to save least number)
1160 r12 (not saved; if used for DImode or DFmode would use r13)
1161 ctr (not saved; when we have the choice ctr is better)
1163 r1, r2, ap, ca (fixed)
1164 v0 - v1 (not saved or used for anything)
1165 v13 - v3 (not saved; incoming vector arg registers)
1166 v2 (not saved; incoming vector arg reg; return value)
1167 v19 - v14 (not saved or used for anything)
1168 v31 - v20 (saved; order given to save least number)
1169 vrsave, vscr (fixed)
1170 spe_acc, spefscr (fixed)
1178 #define MAYBE_R2_AVAILABLE
1179 #define MAYBE_R2_FIXED 2,
1181 #define MAYBE_R2_AVAILABLE 2,
1182 #define MAYBE_R2_FIXED
1186 #define EARLY_R12 12,
1190 #define LATE_R12 12,
1193 #define REG_ALLOC_ORDER \
1195 /* move fr13 (ie 45) later, so if we need TFmode, it does */ \
1196 /* not use fr14 which is a saved register. */ \
1197 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \
1199 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
1200 50, 49, 48, 47, 46, \
1201 75, 73, 74, 69, 68, 72, 71, 70, \
1202 MAYBE_R2_AVAILABLE \
1203 9, 10, 8, 7, 6, 5, 4, \
1204 3, EARLY_R12 11, 0, \
1205 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
1206 18, 17, 16, 15, 14, 13, LATE_R12 \
1208 1, MAYBE_R2_FIXED 67, 76, \
1209 /* AltiVec registers. */ \
1211 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
1213 96, 95, 94, 93, 92, 91, \
1214 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \
1216 111, 112, 113, 114, 115, 116, \
1217 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \
1218 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \
1219 141, 142, 143, 144, 145, 146, 147, 148 \
1222 /* True if register is floating-point. */
1223 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1225 /* True if register is a condition register. */
1226 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO)
1228 /* True if register is a condition register, but not cr0. */
1229 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO)
1231 /* True if register is an integer register. */
1232 #define INT_REGNO_P(N) \
1233 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM)
1235 /* SPE SIMD registers are just the GPRs. */
1236 #define SPE_SIMD_REGNO_P(N) ((N) <= 31)
1238 /* PAIRED SIMD registers are just the FPRs. */
1239 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63)
1241 /* True if register is the CA register. */
1242 #define CA_REGNO_P(N) ((N) == CA_REGNO)
1244 /* True if register is an AltiVec register. */
1245 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
1247 /* True if register is a VSX register. */
1248 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N))
1250 /* Alternate name for any vector register supporting floating point, no matter
1251 which instruction set(s) are available. */
1252 #define VFLOAT_REGNO_P(N) \
1253 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N)))
1255 /* Alternate name for any vector register supporting integer, no matter which
1256 instruction set(s) are available. */
1257 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N)
1259 /* Alternate name for any vector register supporting logical operations, no
1260 matter which instruction set(s) are available. Allow GPRs as well as the
1261 vector registers. */
1262 #define VLOGICAL_REGNO_P(N) \
1263 (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \
1264 || (TARGET_VSX && FP_REGNO_P (N))) \
1266 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate
1267 enough space to account for vectors in FP regs. However, TFmode/TDmode
1268 should not use VSX instructions to do a caller save. */
1269 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
1270 ((NREGS) <= rs6000_hard_regno_nregs[MODE][REGNO] \
1273 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \
1274 && FP_REGNO_P (REGNO) \
1276 : TARGET_E500_DOUBLE && (MODE) == SImode \
1278 : TARGET_E500_DOUBLE && ((MODE) == VOIDmode || (MODE) == DFmode) \
1280 : !TARGET_E500_DOUBLE && FLOAT128_IBM_P (MODE) && FP_REGNO_P (REGNO) \
1282 : !TARGET_E500_DOUBLE && (MODE) == TDmode && FP_REGNO_P (REGNO) \
1284 : choose_hard_reg_mode ((REGNO), (NREGS), false))
1286 #define VSX_VECTOR_MODE(MODE) \
1287 ((MODE) == V4SFmode \
1288 || (MODE) == V2DFmode) \
1290 /* Note KFmode and possibly TFmode (i.e. IEEE 128-bit floating point) are not
1291 really a vector, but we want to treat it as a vector for moves, and
1294 #define ALTIVEC_VECTOR_MODE(MODE) \
1295 ((MODE) == V16QImode \
1296 || (MODE) == V8HImode \
1297 || (MODE) == V4SFmode \
1298 || (MODE) == V4SImode \
1299 || FLOAT128_VECTOR_P (MODE))
1301 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \
1302 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \
1303 || (MODE) == V2DImode || (MODE) == V1TImode)
1305 #define SPE_VECTOR_MODE(MODE) \
1306 ((MODE) == V4HImode \
1307 || (MODE) == V2SFmode \
1308 || (MODE) == V1DImode \
1309 || (MODE) == V2SImode)
1311 #define PAIRED_VECTOR_MODE(MODE) \
1312 ((MODE) == V2SFmode)
1314 /* Post-reload, we can't use any new AltiVec registers, as we already
1315 emitted the vrsave mask. */
1317 #define HARD_REGNO_RENAME_OK(SRC, DST) \
1318 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST))
1320 /* Specify the cost of a branch insn; roughly the number of extra insns that
1321 should be added to avoid a branch.
1323 Set this to 3 on the RS/6000 since that is roughly the average cost of an
1324 unscheduled conditional branch. */
1326 #define BRANCH_COST(speed_p, predictable_p) 3
1328 /* Override BRANCH_COST heuristic which empirically produces worse
1329 performance for removing short circuiting from the logical ops. */
1331 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
1333 /* A fixed register used at epilogue generation to address SPE registers
1334 with negative offsets. The 64-bit load/store instructions on the SPE
1335 only take positive offsets (and small ones at that), so we need to
1336 reserve a register for consing up negative offsets. */
1338 #define FIXED_SCRATCH 0
1340 /* Specify the registers used for certain standard purposes.
1341 The values of these macros are register numbers. */
1343 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
1344 /* #define PC_REGNUM */
1346 /* Register to use for pushing function arguments. */
1347 #define STACK_POINTER_REGNUM 1
1349 /* Base register for access to local variables of the function. */
1350 #define HARD_FRAME_POINTER_REGNUM 31
1352 /* Base register for access to local variables of the function. */
1353 #define FRAME_POINTER_REGNUM 113
1355 /* Base register for access to arguments of the function. */
1356 #define ARG_POINTER_REGNUM 67
1358 /* Place to put static chain when calling a function that requires it. */
1359 #define STATIC_CHAIN_REGNUM 11
1361 /* Base register for access to thread local storage variables. */
1362 #define TLS_REGNUM ((TARGET_64BIT) ? 13 : 2)
1365 /* Define the classes of registers for register constraints in the
1366 machine description. Also define ranges of constants.
1368 One of the classes must always be named ALL_REGS and include all hard regs.
1369 If there is more than one class, another class must be named NO_REGS
1370 and contain no registers.
1372 The name GENERAL_REGS must be the name of a class (or an alias for
1373 another name such as ALL_REGS). This is the class of registers
1374 that is allowed by "g" or "r" in a register constraint.
1375 Also, registers outside this class are allocated only when
1376 instructions express preferences for them.
1378 The classes must be numbered in nondecreasing order; that is,
1379 a larger-numbered class must never be contained completely
1380 in a smaller-numbered class.
1382 For any two classes, it is very desirable that there be another
1383 class that represents their union. */
1385 /* The RS/6000 has three types of registers, fixed-point, floating-point, and
1386 condition registers, plus three special registers, CTR, and the link
1387 register. AltiVec adds a vector register class. VSX registers overlap the
1388 FPR registers and the Altivec registers.
1390 However, r0 is special in that it cannot be used as a base register.
1391 So make a class for registers valid as base registers.
1393 Also, cr0 is the only condition code register that can be used in
1394 arithmetic insns, so make a separate class for it. */
1424 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1426 /* Give names of register classes as strings for dump file. */
1428 #define REG_CLASS_NAMES \
1441 "NON_SPECIAL_REGS", \
1444 "LINK_OR_CTR_REGS", \
1446 "SPEC_OR_GEN_REGS", \
1455 /* Define which registers fit in which classes.
1456 This is an initializer for a vector of HARD_REG_SET
1457 of length N_REG_CLASSES. */
1459 #define REG_CLASS_CONTENTS \
1462 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \
1464 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
1465 /* GENERAL_REGS. */ \
1466 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \
1468 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \
1469 /* ALTIVEC_REGS. */ \
1470 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \
1472 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \
1473 /* VRSAVE_REGS. */ \
1474 { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \
1476 { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \
1477 /* SPE_ACC_REGS. */ \
1478 { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \
1479 /* SPEFSCR_REGS. */ \
1480 { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \
1482 { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \
1483 /* NON_SPECIAL_REGS. */ \
1484 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \
1486 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \
1488 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \
1489 /* LINK_OR_CTR_REGS. */ \
1490 { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \
1491 /* SPECIAL_REGS. */ \
1492 { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \
1493 /* SPEC_OR_GEN_REGS. */ \
1494 { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \
1496 { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \
1498 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \
1499 /* NON_FLOAT_REGS. */ \
1500 { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \
1502 { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \
1503 /* SPE_HIGH_REGS. */ \
1504 { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \
1506 { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \
1509 /* The same information, inverted:
1510 Return the class number of the smallest class containing
1511 reg number REGNO. This could be a conditional expression
1512 or could index an array. */
1514 extern enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
1516 #define REGNO_REG_CLASS(REGNO) \
1517 (gcc_checking_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)),\
1518 rs6000_regno_regclass[(REGNO)])
1520 /* Register classes for various constraints that are based on the target
1522 enum r6000_reg_class_enum
{
1523 RS6000_CONSTRAINT_d
, /* fpr registers for double values */
1524 RS6000_CONSTRAINT_f
, /* fpr registers for single values */
1525 RS6000_CONSTRAINT_v
, /* Altivec registers */
1526 RS6000_CONSTRAINT_wa
, /* Any VSX register */
1527 RS6000_CONSTRAINT_wb
, /* Altivec register if ISA 3.0 vector. */
1528 RS6000_CONSTRAINT_wd
, /* VSX register for V2DF */
1529 RS6000_CONSTRAINT_we
, /* VSX register if ISA 3.0 vector. */
1530 RS6000_CONSTRAINT_wf
, /* VSX register for V4SF */
1531 RS6000_CONSTRAINT_wg
, /* FPR register for -mmfpgpr */
1532 RS6000_CONSTRAINT_wh
, /* FPR register for direct moves. */
1533 RS6000_CONSTRAINT_wi
, /* FPR/VSX register to hold DImode */
1534 RS6000_CONSTRAINT_wj
, /* FPR/VSX register for DImode direct moves. */
1535 RS6000_CONSTRAINT_wk
, /* FPR/VSX register for DFmode direct moves. */
1536 RS6000_CONSTRAINT_wl
, /* FPR register for LFIWAX */
1537 RS6000_CONSTRAINT_wm
, /* VSX register for direct move */
1538 RS6000_CONSTRAINT_wo
, /* VSX register for power9 vector. */
1539 RS6000_CONSTRAINT_wp
, /* VSX reg for IEEE 128-bit fp TFmode. */
1540 RS6000_CONSTRAINT_wq
, /* VSX reg for IEEE 128-bit fp KFmode. */
1541 RS6000_CONSTRAINT_wr
, /* GPR register if 64-bit */
1542 RS6000_CONSTRAINT_ws
, /* VSX register for DF */
1543 RS6000_CONSTRAINT_wt
, /* VSX register for TImode */
1544 RS6000_CONSTRAINT_wu
, /* Altivec register for float load/stores. */
1545 RS6000_CONSTRAINT_wv
, /* Altivec register for double load/stores. */
1546 RS6000_CONSTRAINT_ww
, /* FP or VSX register for vsx float ops. */
1547 RS6000_CONSTRAINT_wx
, /* FPR register for STFIWX */
1548 RS6000_CONSTRAINT_wy
, /* VSX register for SF */
1549 RS6000_CONSTRAINT_wz
, /* FPR register for LFIWZX */
1550 RS6000_CONSTRAINT_wA
, /* BASE_REGS if 64-bit. */
1551 RS6000_CONSTRAINT_wH
, /* Altivec register for 32-bit integers. */
1552 RS6000_CONSTRAINT_wI
, /* VSX register for 32-bit integers. */
1553 RS6000_CONSTRAINT_wJ
, /* VSX register for 8/16-bit integers. */
1554 RS6000_CONSTRAINT_wK
, /* Altivec register for 16/32-bit integers. */
1555 RS6000_CONSTRAINT_MAX
1558 extern enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
1560 /* The class value for index registers, and the one for base regs. */
1561 #define INDEX_REG_CLASS GENERAL_REGS
1562 #define BASE_REG_CLASS BASE_REGS
1564 /* Return whether a given register class can hold VSX objects. */
1565 #define VSX_REG_CLASS_P(CLASS) \
1566 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS)
1568 /* Return whether a given register class targets general purpose registers. */
1569 #define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS)
1571 /* Given an rtx X being reloaded into a reg required to be
1572 in class CLASS, return the class of reg to actually use.
1573 In general this is just CLASS; but on some machines
1574 in some cases it is preferable to use a more restrictive class.
1576 On the RS/6000, we have to return NO_REGS when we want to reload a
1577 floating-point CONST_DOUBLE to force it to be copied to memory.
1579 We also don't want to reload integer values into floating-point
1580 registers if we can at all help it. In fact, this can
1581 cause reload to die, if it tries to generate a reload of CTR
1582 into a FP register and discovers it doesn't have the memory location
1585 ??? Would it be a good idea to have reload do the converse, that is
1586 try to reload floating modes into FP registers if possible?
1589 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1590 rs6000_preferred_reload_class_ptr (X, CLASS)
1592 /* Return the register class of a scratch register needed to copy IN into
1593 or out of a register in CLASS in MODE. If it can be done directly,
1594 NO_REGS is returned. */
1596 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1597 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN)
1599 /* For cpus that cannot load/store SDmode values from the 64-bit
1600 FP registers without using a full 64-bit load/store, we need
1601 to allocate a full 64-bit stack slot for them. */
1603 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
1604 rs6000_secondary_memory_needed_rtx (MODE)
1606 /* Return the maximum number of consecutive registers
1607 needed to represent mode MODE in a register of class CLASS.
1609 On RS/6000, this is the size of MODE in words, except in the FP regs, where
1610 a single reg is enough for two words, unless we have VSX, where the FP
1611 registers can hold 128 bits. */
1612 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)]
1614 /* Stack layout; function entry, exit and calling. */
1616 /* Define this if pushing a word on the stack
1617 makes the stack pointer a smaller address. */
1618 #define STACK_GROWS_DOWNWARD 1
1620 /* Offsets recorded in opcodes are a multiple of this alignment factor. */
1621 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8)))
1623 /* Define this to nonzero if the nominal address of the stack frame
1624 is at the high-address end of the local variables;
1625 that is, each additional local variable allocated
1626 goes at a more negative offset in the frame.
1628 On the RS/6000, we grow upwards, from the area after the outgoing
1630 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 \
1631 || (flag_sanitize & SANITIZE_ADDRESS) != 0)
1633 /* Size of the fixed area on the stack */
1634 #define RS6000_SAVE_AREA \
1635 ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \
1636 << (TARGET_64BIT ? 1 : 0))
1638 /* Stack offset for toc save slot. */
1639 #define RS6000_TOC_SAVE_SLOT \
1640 ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0))
1642 /* Align an address */
1643 #define RS6000_ALIGN(n,a) ROUND_UP ((n), (a))
1645 /* Offset within stack frame to start allocating local variables at.
1646 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1647 first local allocated. Otherwise, it is the offset to the BEGINNING
1648 of the first local allocated.
1650 On the RS/6000, the frame pointer is the same as the stack pointer,
1651 except for dynamic allocations. So we start after the fixed area and
1652 outgoing parameter area.
1654 If the function uses dynamic stack space (CALLS_ALLOCA is set), that
1655 space needs to be aligned to STACK_BOUNDARY, i.e. the sum of the
1656 sizes of the fixed area and the parameter area must be a multiple of
1659 #define STARTING_FRAME_OFFSET \
1660 (FRAME_GROWS_DOWNWARD \
1662 : (cfun->calls_alloca \
1663 ? (RS6000_ALIGN (crtl->outgoing_args_size + RS6000_SAVE_AREA, \
1664 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8 )) \
1665 : (RS6000_ALIGN (crtl->outgoing_args_size, \
1666 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \
1667 + RS6000_SAVE_AREA)))
1669 /* Offset from the stack pointer register to an item dynamically
1670 allocated on the stack, e.g., by `alloca'.
1672 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1673 length of the outgoing arguments. The default is correct for most
1674 machines. See `function.c' for details.
1676 This value must be a multiple of STACK_BOUNDARY (hard coded in
1678 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1679 RS6000_ALIGN (crtl->outgoing_args_size + STACK_POINTER_OFFSET, \
1680 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8)
1682 /* If we generate an insn to push BYTES bytes,
1683 this says how many the stack pointer really advances by.
1684 On RS/6000, don't define this because there are no push insns. */
1685 /* #define PUSH_ROUNDING(BYTES) */
1687 /* Offset of first parameter from the argument pointer register value.
1688 On the RS/6000, we define the argument pointer to the start of the fixed
1690 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1692 /* Offset from the argument pointer register value to the top of
1693 stack. This is different from FIRST_PARM_OFFSET because of the
1694 register save area. */
1695 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1697 /* Define this if stack space is still allocated for a parameter passed
1698 in a register. The value is the number of bytes allocated to this
1700 #define REG_PARM_STACK_SPACE(FNDECL) \
1701 rs6000_reg_parm_stack_space ((FNDECL), false)
1703 /* Define this macro if space guaranteed when compiling a function body
1704 is different to space required when making a call, a situation that
1705 can arise with K&R style function definitions. */
1706 #define INCOMING_REG_PARM_STACK_SPACE(FNDECL) \
1707 rs6000_reg_parm_stack_space ((FNDECL), true)
1709 /* Define this if the above stack space is to be considered part of the
1710 space allocated by the caller. */
1711 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
1713 /* This is the difference between the logical top of stack and the actual sp.
1715 For the RS/6000, sp points past the fixed area. */
1716 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1718 /* Define this if the maximum size of all the outgoing args is to be
1719 accumulated and pushed during the prologue. The amount can be
1720 found in the variable crtl->outgoing_args_size. */
1721 #define ACCUMULATE_OUTGOING_ARGS 1
1723 /* Define how to find the value returned by a library function
1724 assuming the value has mode MODE. */
1726 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE))
1728 /* DRAFT_V4_STRUCT_RET defaults off. */
1729 #define DRAFT_V4_STRUCT_RET 0
1731 /* Let TARGET_RETURN_IN_MEMORY control what happens. */
1732 #define DEFAULT_PCC_STRUCT_RETURN 0
1734 /* Mode of stack savearea.
1735 FUNCTION is VOIDmode because calling convention maintains SP.
1736 BLOCK needs Pmode for SP.
1737 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1738 #define STACK_SAVEAREA_MODE(LEVEL) \
1739 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1740 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode)
1742 /* Minimum and maximum general purpose registers used to hold arguments. */
1743 #define GP_ARG_MIN_REG 3
1744 #define GP_ARG_MAX_REG 10
1745 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1747 /* Minimum and maximum floating point registers used to hold arguments. */
1748 #define FP_ARG_MIN_REG 33
1749 #define FP_ARG_AIX_MAX_REG 45
1750 #define FP_ARG_V4_MAX_REG 40
1751 #define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \
1752 ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG)
1753 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1755 /* Minimum and maximum AltiVec registers used to hold arguments. */
1756 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1757 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1758 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1760 /* Maximum number of registers per ELFv2 homogeneous aggregate argument. */
1761 #define AGGR_ARG_NUM_REG 8
1763 /* Return registers */
1764 #define GP_ARG_RETURN GP_ARG_MIN_REG
1765 #define FP_ARG_RETURN FP_ARG_MIN_REG
1766 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1767 #define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \
1768 : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1769 #define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 \
1770 ? (ALTIVEC_ARG_RETURN \
1771 + (TARGET_FLOAT128_TYPE ? 1 : 0)) \
1772 : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1))
1774 /* Flags for the call/call_value rtl operations set up by function_arg */
1775 #define CALL_NORMAL 0x00000000 /* no special processing */
1776 /* Bits in 0x00000001 are unused. */
1777 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1778 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1779 #define CALL_LONG 0x00000008 /* always call indirect */
1780 #define CALL_LIBCALL 0x00000010 /* libcall */
1782 /* We don't have prologue and epilogue functions to save/restore
1783 everything for most ABIs. */
1784 #define WORLD_SAVE_P(INFO) 0
1786 /* 1 if N is a possible register number for a function value
1787 as seen by the caller.
1789 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1790 #define FUNCTION_VALUE_REGNO_P(N) \
1791 ((N) == GP_ARG_RETURN \
1792 || (IN_RANGE ((N), FP_ARG_RETURN, FP_ARG_MAX_RETURN) \
1793 && TARGET_HARD_FLOAT && TARGET_FPRS) \
1794 || (IN_RANGE ((N), ALTIVEC_ARG_RETURN, ALTIVEC_ARG_MAX_RETURN) \
1795 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI))
1797 /* 1 if N is a possible register number for function argument passing.
1798 On RS/6000, these are r3-r10 and fp1-fp13.
1799 On AltiVec, v2 - v13 are used for passing vectors. */
1800 #define FUNCTION_ARG_REGNO_P(N) \
1801 (IN_RANGE ((N), GP_ARG_MIN_REG, GP_ARG_MAX_REG) \
1802 || (IN_RANGE ((N), ALTIVEC_ARG_MIN_REG, ALTIVEC_ARG_MAX_REG) \
1803 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \
1804 || (IN_RANGE ((N), FP_ARG_MIN_REG, FP_ARG_MAX_REG) \
1805 && TARGET_HARD_FLOAT && TARGET_FPRS))
1807 /* Define a data type for recording info about an argument list
1808 during the scan of that argument list. This data type should
1809 hold all necessary information about the function itself
1810 and about the args processed so far, enough to enable macros
1811 such as FUNCTION_ARG to determine where the next arg should go.
1813 On the RS/6000, this is a structure. The first element is the number of
1814 total argument words, the second is used to store the next
1815 floating-point register number, and the third says how many more args we
1816 have prototype types for.
1818 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1819 the next available GP register, `fregno' is the next available FP
1820 register, and `words' is the number of words used on the stack.
1822 The varargs/stdarg support requires that this structure's size
1823 be a multiple of sizeof(int). */
1825 typedef struct rs6000_args
1827 int words
; /* # words used for passing GP registers */
1828 int fregno
; /* next available FP register */
1829 int vregno
; /* next available AltiVec register */
1830 int nargs_prototype
; /* # args left in the current prototype */
1831 int prototype
; /* Whether a prototype was defined */
1832 int stdarg
; /* Whether function is a stdarg function. */
1833 int call_cookie
; /* Do special things for this call */
1834 int sysv_gregno
; /* next available GP register */
1835 int intoffset
; /* running offset in struct (darwin64) */
1836 int use_stack
; /* any part of struct on stack (darwin64) */
1837 int floats_in_gpr
; /* count of SFmode floats taking up
1838 GPR space (darwin64) */
1839 int named
; /* false for varargs params */
1840 int escapes
; /* if function visible outside tu */
1841 int libcall
; /* If this is a compiler generated call. */
1844 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1845 for a call to a function whose data type is FNTYPE.
1846 For a library call, FNTYPE is 0. */
1848 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
1849 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, \
1850 N_NAMED_ARGS, FNDECL, VOIDmode)
1852 /* Similar, but when scanning the definition of a procedure. We always
1853 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1855 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
1856 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, \
1857 1000, current_function_decl, VOIDmode)
1859 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */
1861 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \
1862 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, \
1865 #define PAD_VARARGS_DOWN \
1866 (targetm.calls.function_arg_padding (TYPE_MODE (type), type) == PAD_DOWNWARD)
1868 /* Output assembler code to FILE to increment profiler label # LABELNO
1869 for profiling a function entry. */
1871 #define FUNCTION_PROFILER(FILE, LABELNO) \
1872 output_function_profiler ((FILE), (LABELNO));
1874 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1875 the stack pointer does not matter. No definition is equivalent to
1878 On the RS/6000, this is nonzero because we can restore the stack from
1879 its backpointer, which we maintain. */
1880 #define EXIT_IGNORE_STACK 1
1882 /* Define this macro as a C expression that is nonzero for registers
1883 that are used by the epilogue or the return' pattern. The stack
1884 and frame pointer registers are already be assumed to be used as
1887 #define EPILOGUE_USES(REGNO) \
1888 ((reload_completed && (REGNO) == LR_REGNO) \
1889 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1890 || (crtl->calls_eh_return \
1895 /* Length in units of the trampoline for entering a nested function. */
1897 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1899 /* Definitions for __builtin_return_address and __builtin_frame_address.
1900 __builtin_return_address (0) should give link register (LR_REGNO), enable
1902 /* This should be uncommented, so that the link register is used, but
1903 currently this would result in unmatched insns and spilling fixed
1904 registers so we'll leave it for another day. When these problems are
1905 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1907 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1909 /* Number of bytes into the frame return addresses can be found. See
1910 rs6000_stack_info in powerpcspe.c for more information on how the different
1911 abi's store the return address. */
1912 #define RETURN_ADDRESS_OFFSET \
1913 ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0))
1915 /* The current return address is in link register (65). The return address
1916 of anything farther back is accessed normally at an offset of 8 from the
1918 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1919 (rs6000_return_addr (COUNT, FRAME))
1922 /* Definitions for register eliminations.
1924 We have two registers that can be eliminated on the RS/6000. First, the
1925 frame pointer register can often be eliminated in favor of the stack
1926 pointer register. Secondly, the argument pointer register can always be
1927 eliminated; it is replaced with either the stack or frame pointer.
1929 In addition, we use the elimination mechanism to see if r30 is needed
1930 Initially we assume that it isn't. If it is, we spill it. This is done
1931 by making it an eliminable register. We replace it with itself so that
1932 if it isn't needed, then existing uses won't be modified. */
1934 /* This is an array of structures. Each structure initializes one pair
1935 of eliminable registers. The "from" register number is given first,
1936 followed by "to". Eliminations of the same "from" register are listed
1937 in order of preference. */
1938 #define ELIMINABLE_REGS \
1939 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1940 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1941 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1942 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1943 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
1944 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } }
1946 /* Define the offset between two registers, one to be eliminated, and the other
1947 its replacement, at the start of a routine. */
1948 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1949 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO))
1951 /* Addressing modes, and classification of registers for them. */
1953 #define HAVE_PRE_DECREMENT 1
1954 #define HAVE_PRE_INCREMENT 1
1955 #define HAVE_PRE_MODIFY_DISP 1
1956 #define HAVE_PRE_MODIFY_REG 1
1958 /* Macros to check register numbers against specific register classes. */
1960 /* These assume that REGNO is a hard or pseudo reg number.
1961 They give nonzero only if REGNO is a hard reg of the suitable class
1962 or a pseudo reg currently allocated to a suitable hard reg.
1963 Since they use reg_renumber, they are safe only once reg_renumber
1964 has been allocated, which happens in reginfo.c during register
1967 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1968 ((REGNO) < FIRST_PSEUDO_REGISTER \
1969 ? (REGNO) <= 31 || (REGNO) == 67 \
1970 || (REGNO) == FRAME_POINTER_REGNUM \
1971 : (reg_renumber[REGNO] >= 0 \
1972 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1973 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1975 #define REGNO_OK_FOR_BASE_P(REGNO) \
1976 ((REGNO) < FIRST_PSEUDO_REGISTER \
1977 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1978 || (REGNO) == FRAME_POINTER_REGNUM \
1979 : (reg_renumber[REGNO] > 0 \
1980 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \
1981 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM)))
1983 /* Nonzero if X is a hard reg that can be used as an index
1984 or if it is a pseudo reg in the non-strict case. */
1985 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1986 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1987 || REGNO_OK_FOR_INDEX_P (REGNO (X)))
1989 /* Nonzero if X is a hard reg that can be used as a base reg
1990 or if it is a pseudo reg in the non-strict case. */
1991 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1992 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
1993 || REGNO_OK_FOR_BASE_P (REGNO (X)))
1996 /* Maximum number of registers that can appear in a valid memory address. */
1998 #define MAX_REGS_PER_ADDRESS 2
2000 /* Recognize any constant value that is a valid address. */
2002 #define CONSTANT_ADDRESS_P(X) \
2003 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
2004 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
2005 || GET_CODE (X) == HIGH)
2007 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
2008 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \
2009 && EASY_VECTOR_15((n) >> 1) \
2012 #define EASY_VECTOR_MSB(n,mode) \
2013 ((((unsigned HOST_WIDE_INT) (n)) & GET_MODE_MASK (mode)) == \
2014 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1))
2017 /* Try a machine-dependent way of reloading an illegitimate address
2018 operand. If we find one, push the reload and jump to WIN. This
2019 macro is used in only one place: `find_reloads_address' in reload.c.
2021 Implemented on rs6000 by rs6000_legitimize_reload_address.
2022 Note that (X) is evaluated twice; this is safe in current usage. */
2024 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2027 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \
2028 (int)(TYPE), (IND_LEVELS), &win); \
2033 #define FIND_BASE_TERM rs6000_find_base_term
2035 /* The register number of the register used to address a table of
2036 static data addresses in memory. In some cases this register is
2037 defined by a processor's "application binary interface" (ABI).
2038 When this macro is defined, RTL is generated for this register
2039 once, as with the stack pointer and frame pointer registers. If
2040 this macro is not defined, it is up to the machine-dependent files
2041 to allocate such a register (if necessary). */
2043 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2044 #define PIC_OFFSET_TABLE_REGNUM \
2045 (TARGET_TOC ? TOC_REGISTER \
2046 : flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM \
2049 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2)
2051 /* Define this macro if the register defined by
2052 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2053 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2055 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2057 /* A C expression that is nonzero if X is a legitimate immediate
2058 operand on the target machine when generating position independent
2059 code. You can assume that X satisfies `CONSTANT_P', so you need
2060 not check this. You can also assume FLAG_PIC is true, so you need
2061 not check it either. You need not define this macro if all
2062 constants (including `SYMBOL_REF') can be immediate operands when
2063 generating position independent code. */
2065 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2067 /* Define this if some processing needs to be done immediately before
2068 emitting code for an insn. */
2070 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
2071 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
2073 /* Specify the machine mode that this machine uses
2074 for the index in the tablejump instruction. */
2075 #define CASE_VECTOR_MODE SImode
2077 /* Define as C expression which evaluates to nonzero if the tablejump
2078 instruction expects the table to contain offsets from the address of the
2080 Do not define this if the table should contain absolute addresses. */
2081 #define CASE_VECTOR_PC_RELATIVE 1
2083 /* Define this as 1 if `char' should by default be signed; else as 0. */
2084 #define DEFAULT_SIGNED_CHAR 0
2086 /* An integer expression for the size in bits of the largest integer machine
2087 mode that should actually be used. */
2089 /* Allow pairs of registers to be used, which is the intent of the default. */
2090 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode)
2092 /* Max number of bytes we can move from memory to memory
2093 in one reasonably fast instruction. */
2094 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2095 #define MAX_MOVE_MAX 8
2097 /* Nonzero if access to memory by bytes is no faster than for words.
2098 Also nonzero if doing byte operations (specifically shifts) in registers
2100 #define SLOW_BYTE_ACCESS 1
2102 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2103 will either zero-extend or sign-extend. The value of this macro should
2104 be the code that says which one of the two operations is implicitly
2105 done, UNKNOWN if none. */
2106 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2108 /* Define if loading short immediate values into registers sign extends. */
2109 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
2111 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2112 is done just by pretending it is already truncated. */
2113 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2115 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */
2116 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2117 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
2119 /* The CTZ patterns that are implemented in terms of CLZ return -1 for input of
2120 zero. The hardware instructions added in Power9 and the sequences using
2121 popcount return 32 or 64. */
2122 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
2123 (TARGET_CTZ || TARGET_POPCNTD \
2124 ? ((VALUE) = GET_MODE_BITSIZE (MODE), 2) \
2125 : ((VALUE) = -1, 2))
2127 /* Specify the machine mode that pointers have.
2128 After generation of rtl, the compiler makes no further distinction
2129 between pointers and any other objects of this machine mode. */
2130 extern scalar_int_mode rs6000_pmode
;
2131 #define Pmode rs6000_pmode
2133 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */
2134 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode)
2136 /* Mode of a function address in a call instruction (for indexing purposes).
2137 Doesn't matter on RS/6000. */
2138 #define FUNCTION_MODE SImode
2140 /* Define this if addresses of constant functions
2141 shouldn't be put through pseudo regs where they can be cse'd.
2142 Desirable on machines where ordinary constants are expensive
2143 but a CALL with constant address is cheap. */
2144 #define NO_FUNCTION_CSE 1
2146 /* Define this to be nonzero if shift instructions ignore all but the low-order
2149 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2150 have been dropped from the PowerPC architecture. */
2151 #define SHIFT_COUNT_TRUNCATED 0
2153 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2154 should be adjusted to reflect any required changes. This macro is used when
2155 there is some systematic length adjustment required that would be difficult
2156 to express in the length attribute. */
2158 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2160 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2161 COMPARE, return the mode to be used for the comparison. For
2162 floating-point, CCFPmode should be used. CCUNSmode should be used
2163 for unsigned comparisons. CCEQmode should be used when we are
2164 doing an inequality comparison on the result of a
2165 comparison. CCmode should be used in all other cases. */
2167 #define SELECT_CC_MODE(OP,X,Y) \
2168 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \
2169 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2170 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \
2171 ? CCEQmode : CCmode))
2173 /* Can the condition code MODE be safely reversed? This is safe in
2174 all cases on this port, because at present it doesn't use the
2175 trapping FP comparisons (fcmpo). */
2176 #define REVERSIBLE_CC_MODE(MODE) 1
2178 /* Given a condition code and a mode, return the inverse condition. */
2179 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE)
2182 /* Control the assembler format that we output. */
2184 /* A C string constant describing how to begin a comment in the target
2185 assembler language. The compiler assumes that the comment will end at
2186 the end of the line. */
2187 #define ASM_COMMENT_START " #"
2189 /* Flag to say the TOC is initialized */
2190 extern int toc_initialized
;
2192 /* Macro to output a special constant pool entry. Go to WIN if we output
2193 it. Otherwise, it is written the usual way.
2195 On the RS/6000, toc entries are handled this way. */
2197 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2198 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2200 output_toc (FILE, X, LABELNO, MODE); \
2205 #ifdef HAVE_GAS_WEAK
2206 #define RS6000_WEAK 1
2208 #define RS6000_WEAK 0
2212 /* Used in lieu of ASM_WEAKEN_LABEL. */
2213 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2214 rs6000_asm_weaken_decl ((FILE), (DECL), (NAME), (VAL))
2217 #if HAVE_GAS_WEAKREF
2218 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \
2221 fputs ("\t.weakref\t", (FILE)); \
2222 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2223 fputs (", ", (FILE)); \
2224 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2225 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2226 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2228 fputs ("\n\t.weakref\t.", (FILE)); \
2229 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2230 fputs (", .", (FILE)); \
2231 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \
2233 fputc ('\n', (FILE)); \
2237 /* This implements the `alias' attribute. */
2238 #undef ASM_OUTPUT_DEF_FROM_DECLS
2239 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2242 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2243 const char *name = IDENTIFIER_POINTER (TARGET); \
2244 if (TREE_CODE (DECL) == FUNCTION_DECL \
2245 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \
2247 if (TREE_PUBLIC (DECL)) \
2249 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2251 fputs ("\t.globl\t.", FILE); \
2252 RS6000_OUTPUT_BASENAME (FILE, alias); \
2253 putc ('\n', FILE); \
2256 else if (TARGET_XCOFF) \
2258 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2260 fputs ("\t.lglobl\t.", FILE); \
2261 RS6000_OUTPUT_BASENAME (FILE, alias); \
2262 putc ('\n', FILE); \
2263 fputs ("\t.lglobl\t", FILE); \
2264 RS6000_OUTPUT_BASENAME (FILE, alias); \
2265 putc ('\n', FILE); \
2268 fputs ("\t.set\t.", FILE); \
2269 RS6000_OUTPUT_BASENAME (FILE, alias); \
2270 fputs (",.", FILE); \
2271 RS6000_OUTPUT_BASENAME (FILE, name); \
2272 fputc ('\n', FILE); \
2274 ASM_OUTPUT_DEF (FILE, alias, name); \
2278 #define TARGET_ASM_FILE_START rs6000_file_start
2280 /* Output to assembler file text saying following lines
2281 may contain character constants, extra white space, comments, etc. */
2283 #define ASM_APP_ON ""
2285 /* Output to assembler file text saying following lines
2286 no longer contain unusual constructs. */
2288 #define ASM_APP_OFF ""
2290 /* How to refer to registers in assembler output.
2291 This sequence is indexed by compiler's hard-register-number (see above). */
2293 extern char rs6000_reg_names
[][8]; /* register names (0 vs. %r0). */
2295 #define REGISTER_NAMES \
2297 &rs6000_reg_names[ 0][0], /* r0 */ \
2298 &rs6000_reg_names[ 1][0], /* r1 */ \
2299 &rs6000_reg_names[ 2][0], /* r2 */ \
2300 &rs6000_reg_names[ 3][0], /* r3 */ \
2301 &rs6000_reg_names[ 4][0], /* r4 */ \
2302 &rs6000_reg_names[ 5][0], /* r5 */ \
2303 &rs6000_reg_names[ 6][0], /* r6 */ \
2304 &rs6000_reg_names[ 7][0], /* r7 */ \
2305 &rs6000_reg_names[ 8][0], /* r8 */ \
2306 &rs6000_reg_names[ 9][0], /* r9 */ \
2307 &rs6000_reg_names[10][0], /* r10 */ \
2308 &rs6000_reg_names[11][0], /* r11 */ \
2309 &rs6000_reg_names[12][0], /* r12 */ \
2310 &rs6000_reg_names[13][0], /* r13 */ \
2311 &rs6000_reg_names[14][0], /* r14 */ \
2312 &rs6000_reg_names[15][0], /* r15 */ \
2313 &rs6000_reg_names[16][0], /* r16 */ \
2314 &rs6000_reg_names[17][0], /* r17 */ \
2315 &rs6000_reg_names[18][0], /* r18 */ \
2316 &rs6000_reg_names[19][0], /* r19 */ \
2317 &rs6000_reg_names[20][0], /* r20 */ \
2318 &rs6000_reg_names[21][0], /* r21 */ \
2319 &rs6000_reg_names[22][0], /* r22 */ \
2320 &rs6000_reg_names[23][0], /* r23 */ \
2321 &rs6000_reg_names[24][0], /* r24 */ \
2322 &rs6000_reg_names[25][0], /* r25 */ \
2323 &rs6000_reg_names[26][0], /* r26 */ \
2324 &rs6000_reg_names[27][0], /* r27 */ \
2325 &rs6000_reg_names[28][0], /* r28 */ \
2326 &rs6000_reg_names[29][0], /* r29 */ \
2327 &rs6000_reg_names[30][0], /* r30 */ \
2328 &rs6000_reg_names[31][0], /* r31 */ \
2330 &rs6000_reg_names[32][0], /* fr0 */ \
2331 &rs6000_reg_names[33][0], /* fr1 */ \
2332 &rs6000_reg_names[34][0], /* fr2 */ \
2333 &rs6000_reg_names[35][0], /* fr3 */ \
2334 &rs6000_reg_names[36][0], /* fr4 */ \
2335 &rs6000_reg_names[37][0], /* fr5 */ \
2336 &rs6000_reg_names[38][0], /* fr6 */ \
2337 &rs6000_reg_names[39][0], /* fr7 */ \
2338 &rs6000_reg_names[40][0], /* fr8 */ \
2339 &rs6000_reg_names[41][0], /* fr9 */ \
2340 &rs6000_reg_names[42][0], /* fr10 */ \
2341 &rs6000_reg_names[43][0], /* fr11 */ \
2342 &rs6000_reg_names[44][0], /* fr12 */ \
2343 &rs6000_reg_names[45][0], /* fr13 */ \
2344 &rs6000_reg_names[46][0], /* fr14 */ \
2345 &rs6000_reg_names[47][0], /* fr15 */ \
2346 &rs6000_reg_names[48][0], /* fr16 */ \
2347 &rs6000_reg_names[49][0], /* fr17 */ \
2348 &rs6000_reg_names[50][0], /* fr18 */ \
2349 &rs6000_reg_names[51][0], /* fr19 */ \
2350 &rs6000_reg_names[52][0], /* fr20 */ \
2351 &rs6000_reg_names[53][0], /* fr21 */ \
2352 &rs6000_reg_names[54][0], /* fr22 */ \
2353 &rs6000_reg_names[55][0], /* fr23 */ \
2354 &rs6000_reg_names[56][0], /* fr24 */ \
2355 &rs6000_reg_names[57][0], /* fr25 */ \
2356 &rs6000_reg_names[58][0], /* fr26 */ \
2357 &rs6000_reg_names[59][0], /* fr27 */ \
2358 &rs6000_reg_names[60][0], /* fr28 */ \
2359 &rs6000_reg_names[61][0], /* fr29 */ \
2360 &rs6000_reg_names[62][0], /* fr30 */ \
2361 &rs6000_reg_names[63][0], /* fr31 */ \
2363 &rs6000_reg_names[64][0], /* was mq */ \
2364 &rs6000_reg_names[65][0], /* lr */ \
2365 &rs6000_reg_names[66][0], /* ctr */ \
2366 &rs6000_reg_names[67][0], /* ap */ \
2368 &rs6000_reg_names[68][0], /* cr0 */ \
2369 &rs6000_reg_names[69][0], /* cr1 */ \
2370 &rs6000_reg_names[70][0], /* cr2 */ \
2371 &rs6000_reg_names[71][0], /* cr3 */ \
2372 &rs6000_reg_names[72][0], /* cr4 */ \
2373 &rs6000_reg_names[73][0], /* cr5 */ \
2374 &rs6000_reg_names[74][0], /* cr6 */ \
2375 &rs6000_reg_names[75][0], /* cr7 */ \
2377 &rs6000_reg_names[76][0], /* ca */ \
2379 &rs6000_reg_names[77][0], /* v0 */ \
2380 &rs6000_reg_names[78][0], /* v1 */ \
2381 &rs6000_reg_names[79][0], /* v2 */ \
2382 &rs6000_reg_names[80][0], /* v3 */ \
2383 &rs6000_reg_names[81][0], /* v4 */ \
2384 &rs6000_reg_names[82][0], /* v5 */ \
2385 &rs6000_reg_names[83][0], /* v6 */ \
2386 &rs6000_reg_names[84][0], /* v7 */ \
2387 &rs6000_reg_names[85][0], /* v8 */ \
2388 &rs6000_reg_names[86][0], /* v9 */ \
2389 &rs6000_reg_names[87][0], /* v10 */ \
2390 &rs6000_reg_names[88][0], /* v11 */ \
2391 &rs6000_reg_names[89][0], /* v12 */ \
2392 &rs6000_reg_names[90][0], /* v13 */ \
2393 &rs6000_reg_names[91][0], /* v14 */ \
2394 &rs6000_reg_names[92][0], /* v15 */ \
2395 &rs6000_reg_names[93][0], /* v16 */ \
2396 &rs6000_reg_names[94][0], /* v17 */ \
2397 &rs6000_reg_names[95][0], /* v18 */ \
2398 &rs6000_reg_names[96][0], /* v19 */ \
2399 &rs6000_reg_names[97][0], /* v20 */ \
2400 &rs6000_reg_names[98][0], /* v21 */ \
2401 &rs6000_reg_names[99][0], /* v22 */ \
2402 &rs6000_reg_names[100][0], /* v23 */ \
2403 &rs6000_reg_names[101][0], /* v24 */ \
2404 &rs6000_reg_names[102][0], /* v25 */ \
2405 &rs6000_reg_names[103][0], /* v26 */ \
2406 &rs6000_reg_names[104][0], /* v27 */ \
2407 &rs6000_reg_names[105][0], /* v28 */ \
2408 &rs6000_reg_names[106][0], /* v29 */ \
2409 &rs6000_reg_names[107][0], /* v30 */ \
2410 &rs6000_reg_names[108][0], /* v31 */ \
2411 &rs6000_reg_names[109][0], /* vrsave */ \
2412 &rs6000_reg_names[110][0], /* vscr */ \
2413 &rs6000_reg_names[111][0], /* spe_acc */ \
2414 &rs6000_reg_names[112][0], /* spefscr */ \
2415 &rs6000_reg_names[113][0], /* sfp */ \
2416 &rs6000_reg_names[114][0], /* tfhar */ \
2417 &rs6000_reg_names[115][0], /* tfiar */ \
2418 &rs6000_reg_names[116][0], /* texasr */ \
2420 &rs6000_reg_names[117][0], /* SPE rh0. */ \
2421 &rs6000_reg_names[118][0], /* SPE rh1. */ \
2422 &rs6000_reg_names[119][0], /* SPE rh2. */ \
2423 &rs6000_reg_names[120][0], /* SPE rh3. */ \
2424 &rs6000_reg_names[121][0], /* SPE rh4. */ \
2425 &rs6000_reg_names[122][0], /* SPE rh5. */ \
2426 &rs6000_reg_names[123][0], /* SPE rh6. */ \
2427 &rs6000_reg_names[124][0], /* SPE rh7. */ \
2428 &rs6000_reg_names[125][0], /* SPE rh8. */ \
2429 &rs6000_reg_names[126][0], /* SPE rh9. */ \
2430 &rs6000_reg_names[127][0], /* SPE rh10. */ \
2431 &rs6000_reg_names[128][0], /* SPE rh11. */ \
2432 &rs6000_reg_names[129][0], /* SPE rh12. */ \
2433 &rs6000_reg_names[130][0], /* SPE rh13. */ \
2434 &rs6000_reg_names[131][0], /* SPE rh14. */ \
2435 &rs6000_reg_names[132][0], /* SPE rh15. */ \
2436 &rs6000_reg_names[133][0], /* SPE rh16. */ \
2437 &rs6000_reg_names[134][0], /* SPE rh17. */ \
2438 &rs6000_reg_names[135][0], /* SPE rh18. */ \
2439 &rs6000_reg_names[136][0], /* SPE rh19. */ \
2440 &rs6000_reg_names[137][0], /* SPE rh20. */ \
2441 &rs6000_reg_names[138][0], /* SPE rh21. */ \
2442 &rs6000_reg_names[139][0], /* SPE rh22. */ \
2443 &rs6000_reg_names[140][0], /* SPE rh22. */ \
2444 &rs6000_reg_names[141][0], /* SPE rh24. */ \
2445 &rs6000_reg_names[142][0], /* SPE rh25. */ \
2446 &rs6000_reg_names[143][0], /* SPE rh26. */ \
2447 &rs6000_reg_names[144][0], /* SPE rh27. */ \
2448 &rs6000_reg_names[145][0], /* SPE rh28. */ \
2449 &rs6000_reg_names[146][0], /* SPE rh29. */ \
2450 &rs6000_reg_names[147][0], /* SPE rh30. */ \
2451 &rs6000_reg_names[148][0], /* SPE rh31. */ \
2454 /* Table of additional register names to use in user input. */
2456 #define ADDITIONAL_REGISTER_NAMES \
2457 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2458 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2459 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2460 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2461 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2462 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2463 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2464 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2465 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2466 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2467 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2468 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2469 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2470 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2471 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2472 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2473 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2474 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2475 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2476 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2477 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2478 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2479 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2480 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2481 {"vrsave", 109}, {"vscr", 110}, \
2482 {"spe_acc", 111}, {"spefscr", 112}, \
2483 /* no additional names for: lr, ctr, ap */ \
2484 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2485 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2486 {"cc", 68}, {"sp", 1}, {"toc", 2}, \
2487 /* CA is only part of XER, but we do not model the other parts (yet). */ \
2489 /* VSX registers overlaid on top of FR, Altivec registers */ \
2490 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \
2491 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \
2492 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \
2493 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \
2494 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \
2495 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \
2496 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \
2497 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \
2498 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \
2499 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \
2500 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \
2501 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \
2502 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \
2503 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \
2504 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \
2505 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \
2506 /* Transactional Memory Facility (HTM) Registers. */ \
2507 {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \
2508 /* SPE high registers. */ \
2509 {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \
2510 {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \
2511 {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \
2512 {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \
2513 {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \
2514 {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \
2515 {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \
2516 {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \
2519 /* This is how to output an element of a case-vector that is relative. */
2521 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2522 do { char buf[100]; \
2523 fputs ("\t.long ", FILE); \
2524 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2525 assemble_name (FILE, buf); \
2527 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2528 assemble_name (FILE, buf); \
2529 putc ('\n', FILE); \
2532 /* This is how to output an assembler line
2533 that says to advance the location counter
2534 to a multiple of 2**LOG bytes. */
2536 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2538 fprintf (FILE, "\t.align %d\n", (LOG))
2540 /* How to align the given loop. */
2541 #define LOOP_ALIGN(LABEL) rs6000_loop_align(LABEL)
2543 /* Alignment guaranteed by __builtin_malloc. */
2544 /* FIXME: 128-bit alignment is guaranteed by glibc for TARGET_64BIT.
2545 However, specifying the stronger guarantee currently leads to
2546 a regression in SPEC CPU2006 437.leslie3d. The stronger
2547 guarantee should be implemented here once that's fixed. */
2548 #define MALLOC_ABI_ALIGNMENT (64)
2550 /* Pick up the return address upon entry to a procedure. Used for
2551 dwarf2 unwind information. This also enables the table driven
2554 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO)
2555 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO)
2557 /* Describe how we implement __builtin_eh_return. */
2558 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2559 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2561 /* Print operand X (an rtx) in assembler syntax to file FILE.
2562 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2563 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2565 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2567 /* Define which CODE values are valid. */
2569 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '&')
2571 /* Print a memory address as an operand to reference that memory location. */
2573 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2575 /* For switching between functions with different target attributes. */
2576 #define SWITCHABLE_TARGET 1
2578 /* uncomment for disabling the corresponding default options */
2579 /* #define MACHINE_no_sched_interblock */
2580 /* #define MACHINE_no_sched_speculative */
2581 /* #define MACHINE_no_sched_speculative_load */
2583 /* General flags. */
2584 extern int frame_pointer_needed
;
2586 /* Classification of the builtin functions as to which switches enable the
2587 builtin, and what attributes it should have. We used to use the target
2588 flags macros, but we've run out of bits, so we now map the options into new
2589 settings used here. */
2591 /* Builtin attributes. */
2592 #define RS6000_BTC_SPECIAL 0x00000000 /* Special function. */
2593 #define RS6000_BTC_UNARY 0x00000001 /* normal unary function. */
2594 #define RS6000_BTC_BINARY 0x00000002 /* normal binary function. */
2595 #define RS6000_BTC_TERNARY 0x00000003 /* normal ternary function. */
2596 #define RS6000_BTC_PREDICATE 0x00000004 /* predicate function. */
2597 #define RS6000_BTC_ABS 0x00000005 /* Altivec/VSX ABS function. */
2598 #define RS6000_BTC_EVSEL 0x00000006 /* SPE EVSEL function. */
2599 #define RS6000_BTC_DST 0x00000007 /* Altivec DST function. */
2600 #define RS6000_BTC_TYPE_MASK 0x0000000f /* Mask to isolate types */
2602 #define RS6000_BTC_MISC 0x00000000 /* No special attributes. */
2603 #define RS6000_BTC_CONST 0x00000100 /* Neither uses, nor
2604 modifies global state. */
2605 #define RS6000_BTC_PURE 0x00000200 /* reads global
2607 not modify global state. */
2608 #define RS6000_BTC_FP 0x00000400 /* depends on rounding mode. */
2609 #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */
2611 /* Miscellaneous information. */
2612 #define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */
2613 #define RS6000_BTC_VOID 0x02000000 /* function has no return value. */
2614 #define RS6000_BTC_CR 0x04000000 /* function references a CR. */
2615 #define RS6000_BTC_OVERLOADED 0x08000000 /* function is overloaded. */
2616 #define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */
2618 /* Convenience macros to document the instruction type. */
2619 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */
2620 #define RS6000_BTC_SAT RS6000_BTC_MISC /* saturate sets VSCR. */
2622 /* Builtin targets. For now, we reuse the masks for those options that are in
2623 target flags, and pick three random bits for SPE, paired and ldbl128 which
2624 aren't in target_flags. */
2625 #define RS6000_BTM_ALWAYS 0 /* Always enabled. */
2626 #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */
2627 #define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */
2628 #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */
2629 #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */
2630 #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */
2631 #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */
2632 #define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */
2633 #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */
2634 #define RS6000_BTM_SPE MASK_STRING /* E500 */
2635 #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */
2636 #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */
2637 #define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */
2638 #define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */
2639 #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */
2640 #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */
2641 #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */
2642 #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */
2643 #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
2644 #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
2645 #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
2646 #define RS6000_BTM_FLOAT128 MASK_FLOAT128_TYPE /* IEEE 128-bit float. */
2648 #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
2650 | RS6000_BTM_P8_VECTOR \
2651 | RS6000_BTM_P9_VECTOR \
2652 | RS6000_BTM_P9_MISC \
2653 | RS6000_BTM_MODULO \
2654 | RS6000_BTM_CRYPTO \
2657 | RS6000_BTM_FRSQRTE \
2658 | RS6000_BTM_FRSQRTES \
2660 | RS6000_BTM_POPCNTD \
2663 | RS6000_BTM_HARD_FLOAT \
2664 | RS6000_BTM_LDBL128 \
2665 | RS6000_BTM_FLOAT128)
2667 /* Define builtin enum index. */
2669 #undef RS6000_BUILTIN_0
2670 #undef RS6000_BUILTIN_1
2671 #undef RS6000_BUILTIN_2
2672 #undef RS6000_BUILTIN_3
2673 #undef RS6000_BUILTIN_A
2674 #undef RS6000_BUILTIN_D
2675 #undef RS6000_BUILTIN_E
2676 #undef RS6000_BUILTIN_H
2677 #undef RS6000_BUILTIN_P
2678 #undef RS6000_BUILTIN_Q
2679 #undef RS6000_BUILTIN_S
2680 #undef RS6000_BUILTIN_X
2682 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2683 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2684 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2685 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2686 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2687 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2688 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2689 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2690 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2691 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2692 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2693 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) ENUM,
2695 enum rs6000_builtins
2697 #include "powerpcspe-builtin.def"
2699 RS6000_BUILTIN_COUNT
2702 #undef RS6000_BUILTIN_0
2703 #undef RS6000_BUILTIN_1
2704 #undef RS6000_BUILTIN_2
2705 #undef RS6000_BUILTIN_3
2706 #undef RS6000_BUILTIN_A
2707 #undef RS6000_BUILTIN_D
2708 #undef RS6000_BUILTIN_E
2709 #undef RS6000_BUILTIN_H
2710 #undef RS6000_BUILTIN_P
2711 #undef RS6000_BUILTIN_Q
2712 #undef RS6000_BUILTIN_S
2713 #undef RS6000_BUILTIN_X
2715 enum rs6000_builtin_type_index
2717 RS6000_BTI_NOT_OPAQUE
,
2718 RS6000_BTI_opaque_V2SI
,
2719 RS6000_BTI_opaque_V2SF
,
2720 RS6000_BTI_opaque_p_V2SI
,
2721 RS6000_BTI_opaque_V4SI
,
2732 RS6000_BTI_unsigned_V16QI
,
2733 RS6000_BTI_unsigned_V1TI
,
2734 RS6000_BTI_unsigned_V8HI
,
2735 RS6000_BTI_unsigned_V4SI
,
2736 RS6000_BTI_unsigned_V2DI
,
2737 RS6000_BTI_bool_char
, /* __bool char */
2738 RS6000_BTI_bool_short
, /* __bool short */
2739 RS6000_BTI_bool_int
, /* __bool int */
2740 RS6000_BTI_bool_long
, /* __bool long */
2741 RS6000_BTI_pixel
, /* __pixel */
2742 RS6000_BTI_bool_V16QI
, /* __vector __bool char */
2743 RS6000_BTI_bool_V8HI
, /* __vector __bool short */
2744 RS6000_BTI_bool_V4SI
, /* __vector __bool int */
2745 RS6000_BTI_bool_V2DI
, /* __vector __bool long */
2746 RS6000_BTI_pixel_V8HI
, /* __vector __pixel */
2747 RS6000_BTI_long
, /* long_integer_type_node */
2748 RS6000_BTI_unsigned_long
, /* long_unsigned_type_node */
2749 RS6000_BTI_long_long
, /* long_long_integer_type_node */
2750 RS6000_BTI_unsigned_long_long
, /* long_long_unsigned_type_node */
2751 RS6000_BTI_INTQI
, /* intQI_type_node */
2752 RS6000_BTI_UINTQI
, /* unsigned_intQI_type_node */
2753 RS6000_BTI_INTHI
, /* intHI_type_node */
2754 RS6000_BTI_UINTHI
, /* unsigned_intHI_type_node */
2755 RS6000_BTI_INTSI
, /* intSI_type_node */
2756 RS6000_BTI_UINTSI
, /* unsigned_intSI_type_node */
2757 RS6000_BTI_INTDI
, /* intDI_type_node */
2758 RS6000_BTI_UINTDI
, /* unsigned_intDI_type_node */
2759 RS6000_BTI_INTTI
, /* intTI_type_node */
2760 RS6000_BTI_UINTTI
, /* unsigned_intTI_type_node */
2761 RS6000_BTI_float
, /* float_type_node */
2762 RS6000_BTI_double
, /* double_type_node */
2763 RS6000_BTI_long_double
, /* long_double_type_node */
2764 RS6000_BTI_dfloat64
, /* dfloat64_type_node */
2765 RS6000_BTI_dfloat128
, /* dfloat128_type_node */
2766 RS6000_BTI_void
, /* void_type_node */
2767 RS6000_BTI_ieee128_float
, /* ieee 128-bit floating point */
2768 RS6000_BTI_ibm128_float
, /* IBM 128-bit floating point */
2769 RS6000_BTI_const_str
, /* pointer to const char * */
2774 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI])
2775 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF])
2776 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI])
2777 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI])
2778 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI])
2779 #define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI])
2780 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI])
2781 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF])
2782 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI])
2783 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF])
2784 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI])
2785 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI])
2786 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF])
2787 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI])
2788 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI])
2789 #define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI])
2790 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI])
2791 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI])
2792 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI])
2793 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char])
2794 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short])
2795 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int])
2796 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long])
2797 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel])
2798 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI])
2799 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI])
2800 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI])
2801 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI])
2802 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI])
2804 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long])
2805 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long])
2806 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long])
2807 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long])
2808 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI])
2809 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI])
2810 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI])
2811 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI])
2812 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI])
2813 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI])
2814 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI])
2815 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI])
2816 #define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI])
2817 #define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI])
2818 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float])
2819 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double])
2820 #define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double])
2821 #define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64])
2822 #define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128])
2823 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void])
2824 #define ieee128_float_type_node (rs6000_builtin_types[RS6000_BTI_ieee128_float])
2825 #define ibm128_float_type_node (rs6000_builtin_types[RS6000_BTI_ibm128_float])
2826 #define const_str_type_node (rs6000_builtin_types[RS6000_BTI_const_str])
2828 extern GTY(()) tree rs6000_builtin_types
[RS6000_BTI_MAX
];
2829 extern GTY(()) tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
2831 #define TARGET_SUPPORTS_WIDE_INT 1
2833 #if (GCC_VERSION >= 3000)
2834 #pragma GCC poison TARGET_FLOAT128 OPTION_MASK_FLOAT128 MASK_FLOAT128