1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
35 #include "stringpool.h"
36 #include "stor-layout.h"
38 #include "print-tree.h"
46 #include "basic-block.h"
47 #include "diagnostic-core.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
58 #include "sched-int.h"
59 #include "pointer-set.h"
60 #include "hash-table.h"
62 #include "basic-block.h"
63 #include "tree-ssa-alias.h"
64 #include "internal-fn.h"
65 #include "gimple-fold.h"
67 #include "gimple-expr.h"
71 #include "gimple-iterator.h"
72 #include "gimple-walk.h"
75 #include "tm-constrs.h"
78 #include "tree-vectorizer.h"
82 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
85 #include "gstab.h" /* for N_SLINE */
88 #ifndef TARGET_NO_PROTOTYPE
89 #define TARGET_NO_PROTOTYPE 0
92 #define min(A,B) ((A) < (B) ? (A) : (B))
93 #define max(A,B) ((A) > (B) ? (A) : (B))
95 /* Structure used to define the rs6000 stack */
96 typedef struct rs6000_stack
{
97 int reload_completed
; /* stack info won't change from here on */
98 int first_gp_reg_save
; /* first callee saved GP register used */
99 int first_fp_reg_save
; /* first callee saved FP register used */
100 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
101 int lr_save_p
; /* true if the link reg needs to be saved */
102 int cr_save_p
; /* true if the CR reg needs to be saved */
103 unsigned int vrsave_mask
; /* mask of vec registers to save */
104 int push_p
; /* true if we need to allocate stack space */
105 int calls_p
; /* true if the function makes any calls */
106 int world_save_p
; /* true if we're saving *everything*:
107 r13-r31, cr, f14-f31, vrsave, v20-v31 */
108 enum rs6000_abi abi
; /* which ABI to use */
109 int gp_save_offset
; /* offset to save GP regs from initial SP */
110 int fp_save_offset
; /* offset to save FP regs from initial SP */
111 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
112 int lr_save_offset
; /* offset to save LR from initial SP */
113 int cr_save_offset
; /* offset to save CR from initial SP */
114 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
115 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
116 int varargs_save_offset
; /* offset to save the varargs registers */
117 int ehrd_offset
; /* offset to EH return data */
118 int ehcr_offset
; /* offset to EH CR field data */
119 int reg_size
; /* register size (4 or 8) */
120 HOST_WIDE_INT vars_size
; /* variable save area size */
121 int parm_size
; /* outgoing parameter size */
122 int save_size
; /* save area size */
123 int fixed_size
; /* fixed size of stack frame */
124 int gp_size
; /* size of saved GP registers */
125 int fp_size
; /* size of saved FP registers */
126 int altivec_size
; /* size of saved AltiVec registers */
127 int cr_size
; /* size to hold CR if not in save_size */
128 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
129 int altivec_padding_size
; /* size of altivec alignment padding if
131 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
132 int spe_padding_size
;
133 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
134 int spe_64bit_regs_used
;
138 /* A C structure for machine-specific, per-function data.
139 This is added to the cfun structure. */
140 typedef struct GTY(()) machine_function
142 /* Some local-dynamic symbol. */
143 const char *some_ld_name
;
144 /* Whether the instruction chain has been scanned already. */
145 int insn_chain_scanned_p
;
146 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
147 int ra_needs_full_frame
;
148 /* Flags if __builtin_return_address (0) was used. */
150 /* Cache lr_save_p after expansion of builtin_eh_return. */
152 /* Whether we need to save the TOC to the reserved stack location in the
153 function prologue. */
154 bool save_toc_in_prologue
;
155 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
156 varargs save area. */
157 HOST_WIDE_INT varargs_save_offset
;
158 /* Temporary stack slot to use for SDmode copies. This slot is
159 64-bits wide and is allocated early enough so that the offset
160 does not overflow the 16-bit load/store offset field. */
161 rtx sdmode_stack_slot
;
162 /* Flag if r2 setup is needed with ELFv2 ABI. */
163 bool r2_setup_needed
;
166 /* Support targetm.vectorize.builtin_mask_for_load. */
167 static GTY(()) tree altivec_builtin_mask_for_load
;
169 /* Set to nonzero once AIX common-mode calls have been defined. */
170 static GTY(()) int common_mode_defined
;
172 /* Label number of label created for -mrelocatable, to call to so we can
173 get the address of the GOT section */
174 static int rs6000_pic_labelno
;
177 /* Counter for labels which are to be placed in .fixup. */
178 int fixuplabelno
= 0;
181 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
184 /* Specify the machine mode that pointers have. After generation of rtl, the
185 compiler makes no further distinction between pointers and any other objects
186 of this machine mode. The type is unsigned since not all things that
187 include rs6000.h also include machmode.h. */
188 unsigned rs6000_pmode
;
190 /* Width in bits of a pointer. */
191 unsigned rs6000_pointer_size
;
193 #ifdef HAVE_AS_GNU_ATTRIBUTE
194 /* Flag whether floating point values have been passed/returned. */
195 static bool rs6000_passes_float
;
196 /* Flag whether vector values have been passed/returned. */
197 static bool rs6000_passes_vector
;
198 /* Flag whether small (<= 8 byte) structures have been returned. */
199 static bool rs6000_returns_struct
;
202 /* Value is TRUE if register/mode pair is acceptable. */
203 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
205 /* Maximum number of registers needed for a given register class and mode. */
206 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
208 /* How many registers are needed for a given register and mode. */
209 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
211 /* Map register number to register class. */
212 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
214 static int dbg_cost_ctrl
;
216 /* Built in types. */
217 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
218 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
220 /* Flag to say the TOC is initialized */
222 char toc_label_name
[10];
224 /* Cached value of rs6000_variable_issue. This is cached in
225 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
226 static short cached_can_issue_more
;
228 static GTY(()) section
*read_only_data_section
;
229 static GTY(()) section
*private_data_section
;
230 static GTY(()) section
*tls_data_section
;
231 static GTY(()) section
*tls_private_data_section
;
232 static GTY(()) section
*read_only_private_data_section
;
233 static GTY(()) section
*sdata2_section
;
234 static GTY(()) section
*toc_section
;
236 struct builtin_description
238 const HOST_WIDE_INT mask
;
239 const enum insn_code icode
;
240 const char *const name
;
241 const enum rs6000_builtins code
;
244 /* Describe the vector unit used for modes. */
245 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
246 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
248 /* Register classes for various constraints that are based on the target
250 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
252 /* Describe the alignment of a vector. */
253 int rs6000_vector_align
[NUM_MACHINE_MODES
];
255 /* Map selected modes to types for builtins. */
256 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
258 /* What modes to automatically generate reciprocal divide estimate (fre) and
259 reciprocal sqrt (frsqrte) for. */
260 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
262 /* Masks to determine which reciprocal esitmate instructions to generate
264 enum rs6000_recip_mask
{
265 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
266 RECIP_DF_DIV
= 0x002,
267 RECIP_V4SF_DIV
= 0x004,
268 RECIP_V2DF_DIV
= 0x008,
270 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
271 RECIP_DF_RSQRT
= 0x020,
272 RECIP_V4SF_RSQRT
= 0x040,
273 RECIP_V2DF_RSQRT
= 0x080,
275 /* Various combination of flags for -mrecip=xxx. */
277 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
278 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
279 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
281 RECIP_HIGH_PRECISION
= RECIP_ALL
,
283 /* On low precision machines like the power5, don't enable double precision
284 reciprocal square root estimate, since it isn't accurate enough. */
285 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
288 /* -mrecip options. */
291 const char *string
; /* option name */
292 unsigned int mask
; /* mask bits to set */
293 } recip_options
[] = {
294 { "all", RECIP_ALL
},
295 { "none", RECIP_NONE
},
296 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
298 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
299 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
300 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
301 | RECIP_V2DF_RSQRT
) },
302 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
303 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
306 /* Pointer to function (in rs6000-c.c) that can define or undefine target
307 macros that have changed. Languages that don't support the preprocessor
308 don't link in rs6000-c.c, so we can't call it directly. */
309 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
311 /* Simplfy register classes into simpler classifications. We assume
312 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
313 check for standard register classes (gpr/floating/altivec/vsx) and
314 floating/vector classes (float/altivec/vsx). */
316 enum rs6000_reg_type
{
329 /* Map register class to register type. */
330 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
332 /* First/last register type for the 'normal' register types (i.e. general
333 purpose, floating point, altivec, and VSX registers). */
334 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
336 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
339 /* Register classes we care about in secondary reload or go if legitimate
340 address. We only need to worry about GPR, FPR, and Altivec registers here,
341 along an ANY field that is the OR of the 3 register classes. */
343 enum rs6000_reload_reg_type
{
344 RELOAD_REG_GPR
, /* General purpose registers. */
345 RELOAD_REG_FPR
, /* Traditional floating point regs. */
346 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
347 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
351 /* For setting up register classes, loop through the 3 register classes mapping
352 into real registers, and skip the ANY class, which is just an OR of the
354 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
355 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
357 /* Map reload register type to a register in the register class. */
358 struct reload_reg_map_type
{
359 const char *name
; /* Register class name. */
360 int reg
; /* Register in the register class. */
363 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
364 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
365 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
366 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
367 { "Any", -1 }, /* RELOAD_REG_ANY. */
370 /* Mask bits for each register class, indexed per mode. Historically the
371 compiler has been more restrictive which types can do PRE_MODIFY instead of
372 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
373 typedef unsigned char addr_mask_type
;
375 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
376 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
377 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
378 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
379 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
380 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
382 /* Register type masks based on the type, of valid addressing modes. */
383 struct rs6000_reg_addr
{
384 enum insn_code reload_load
; /* INSN to reload for loading. */
385 enum insn_code reload_store
; /* INSN to reload for storing. */
386 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
387 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
388 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
389 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
392 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
394 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
396 mode_supports_pre_incdec_p (enum machine_mode mode
)
398 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
402 /* Helper function to say whether a mode supports PRE_MODIFY. */
404 mode_supports_pre_modify_p (enum machine_mode mode
)
406 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
411 /* Target cpu costs. */
413 struct processor_costs
{
414 const int mulsi
; /* cost of SImode multiplication. */
415 const int mulsi_const
; /* cost of SImode multiplication by constant. */
416 const int mulsi_const9
; /* cost of SImode mult by short constant. */
417 const int muldi
; /* cost of DImode multiplication. */
418 const int divsi
; /* cost of SImode division. */
419 const int divdi
; /* cost of DImode division. */
420 const int fp
; /* cost of simple SFmode and DFmode insns. */
421 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
422 const int sdiv
; /* cost of SFmode division (fdivs). */
423 const int ddiv
; /* cost of DFmode division (fdiv). */
424 const int cache_line_size
; /* cache line size in bytes. */
425 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
426 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
427 const int simultaneous_prefetches
; /* number of parallel prefetch
431 const struct processor_costs
*rs6000_cost
;
433 /* Processor costs (relative to an add) */
435 /* Instruction size costs on 32bit processors. */
437 struct processor_costs size32_cost
= {
438 COSTS_N_INSNS (1), /* mulsi */
439 COSTS_N_INSNS (1), /* mulsi_const */
440 COSTS_N_INSNS (1), /* mulsi_const9 */
441 COSTS_N_INSNS (1), /* muldi */
442 COSTS_N_INSNS (1), /* divsi */
443 COSTS_N_INSNS (1), /* divdi */
444 COSTS_N_INSNS (1), /* fp */
445 COSTS_N_INSNS (1), /* dmul */
446 COSTS_N_INSNS (1), /* sdiv */
447 COSTS_N_INSNS (1), /* ddiv */
454 /* Instruction size costs on 64bit processors. */
456 struct processor_costs size64_cost
= {
457 COSTS_N_INSNS (1), /* mulsi */
458 COSTS_N_INSNS (1), /* mulsi_const */
459 COSTS_N_INSNS (1), /* mulsi_const9 */
460 COSTS_N_INSNS (1), /* muldi */
461 COSTS_N_INSNS (1), /* divsi */
462 COSTS_N_INSNS (1), /* divdi */
463 COSTS_N_INSNS (1), /* fp */
464 COSTS_N_INSNS (1), /* dmul */
465 COSTS_N_INSNS (1), /* sdiv */
466 COSTS_N_INSNS (1), /* ddiv */
473 /* Instruction costs on RS64A processors. */
475 struct processor_costs rs64a_cost
= {
476 COSTS_N_INSNS (20), /* mulsi */
477 COSTS_N_INSNS (12), /* mulsi_const */
478 COSTS_N_INSNS (8), /* mulsi_const9 */
479 COSTS_N_INSNS (34), /* muldi */
480 COSTS_N_INSNS (65), /* divsi */
481 COSTS_N_INSNS (67), /* divdi */
482 COSTS_N_INSNS (4), /* fp */
483 COSTS_N_INSNS (4), /* dmul */
484 COSTS_N_INSNS (31), /* sdiv */
485 COSTS_N_INSNS (31), /* ddiv */
486 128, /* cache line size */
492 /* Instruction costs on MPCCORE processors. */
494 struct processor_costs mpccore_cost
= {
495 COSTS_N_INSNS (2), /* mulsi */
496 COSTS_N_INSNS (2), /* mulsi_const */
497 COSTS_N_INSNS (2), /* mulsi_const9 */
498 COSTS_N_INSNS (2), /* muldi */
499 COSTS_N_INSNS (6), /* divsi */
500 COSTS_N_INSNS (6), /* divdi */
501 COSTS_N_INSNS (4), /* fp */
502 COSTS_N_INSNS (5), /* dmul */
503 COSTS_N_INSNS (10), /* sdiv */
504 COSTS_N_INSNS (17), /* ddiv */
505 32, /* cache line size */
511 /* Instruction costs on PPC403 processors. */
513 struct processor_costs ppc403_cost
= {
514 COSTS_N_INSNS (4), /* mulsi */
515 COSTS_N_INSNS (4), /* mulsi_const */
516 COSTS_N_INSNS (4), /* mulsi_const9 */
517 COSTS_N_INSNS (4), /* muldi */
518 COSTS_N_INSNS (33), /* divsi */
519 COSTS_N_INSNS (33), /* divdi */
520 COSTS_N_INSNS (11), /* fp */
521 COSTS_N_INSNS (11), /* dmul */
522 COSTS_N_INSNS (11), /* sdiv */
523 COSTS_N_INSNS (11), /* ddiv */
524 32, /* cache line size */
530 /* Instruction costs on PPC405 processors. */
532 struct processor_costs ppc405_cost
= {
533 COSTS_N_INSNS (5), /* mulsi */
534 COSTS_N_INSNS (4), /* mulsi_const */
535 COSTS_N_INSNS (3), /* mulsi_const9 */
536 COSTS_N_INSNS (5), /* muldi */
537 COSTS_N_INSNS (35), /* divsi */
538 COSTS_N_INSNS (35), /* divdi */
539 COSTS_N_INSNS (11), /* fp */
540 COSTS_N_INSNS (11), /* dmul */
541 COSTS_N_INSNS (11), /* sdiv */
542 COSTS_N_INSNS (11), /* ddiv */
543 32, /* cache line size */
549 /* Instruction costs on PPC440 processors. */
551 struct processor_costs ppc440_cost
= {
552 COSTS_N_INSNS (3), /* mulsi */
553 COSTS_N_INSNS (2), /* mulsi_const */
554 COSTS_N_INSNS (2), /* mulsi_const9 */
555 COSTS_N_INSNS (3), /* muldi */
556 COSTS_N_INSNS (34), /* divsi */
557 COSTS_N_INSNS (34), /* divdi */
558 COSTS_N_INSNS (5), /* fp */
559 COSTS_N_INSNS (5), /* dmul */
560 COSTS_N_INSNS (19), /* sdiv */
561 COSTS_N_INSNS (33), /* ddiv */
562 32, /* cache line size */
568 /* Instruction costs on PPC476 processors. */
570 struct processor_costs ppc476_cost
= {
571 COSTS_N_INSNS (4), /* mulsi */
572 COSTS_N_INSNS (4), /* mulsi_const */
573 COSTS_N_INSNS (4), /* mulsi_const9 */
574 COSTS_N_INSNS (4), /* muldi */
575 COSTS_N_INSNS (11), /* divsi */
576 COSTS_N_INSNS (11), /* divdi */
577 COSTS_N_INSNS (6), /* fp */
578 COSTS_N_INSNS (6), /* dmul */
579 COSTS_N_INSNS (19), /* sdiv */
580 COSTS_N_INSNS (33), /* ddiv */
581 32, /* l1 cache line size */
587 /* Instruction costs on PPC601 processors. */
589 struct processor_costs ppc601_cost
= {
590 COSTS_N_INSNS (5), /* mulsi */
591 COSTS_N_INSNS (5), /* mulsi_const */
592 COSTS_N_INSNS (5), /* mulsi_const9 */
593 COSTS_N_INSNS (5), /* muldi */
594 COSTS_N_INSNS (36), /* divsi */
595 COSTS_N_INSNS (36), /* divdi */
596 COSTS_N_INSNS (4), /* fp */
597 COSTS_N_INSNS (5), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (31), /* ddiv */
600 32, /* cache line size */
606 /* Instruction costs on PPC603 processors. */
608 struct processor_costs ppc603_cost
= {
609 COSTS_N_INSNS (5), /* mulsi */
610 COSTS_N_INSNS (3), /* mulsi_const */
611 COSTS_N_INSNS (2), /* mulsi_const9 */
612 COSTS_N_INSNS (5), /* muldi */
613 COSTS_N_INSNS (37), /* divsi */
614 COSTS_N_INSNS (37), /* divdi */
615 COSTS_N_INSNS (3), /* fp */
616 COSTS_N_INSNS (4), /* dmul */
617 COSTS_N_INSNS (18), /* sdiv */
618 COSTS_N_INSNS (33), /* ddiv */
619 32, /* cache line size */
625 /* Instruction costs on PPC604 processors. */
627 struct processor_costs ppc604_cost
= {
628 COSTS_N_INSNS (4), /* mulsi */
629 COSTS_N_INSNS (4), /* mulsi_const */
630 COSTS_N_INSNS (4), /* mulsi_const9 */
631 COSTS_N_INSNS (4), /* muldi */
632 COSTS_N_INSNS (20), /* divsi */
633 COSTS_N_INSNS (20), /* divdi */
634 COSTS_N_INSNS (3), /* fp */
635 COSTS_N_INSNS (3), /* dmul */
636 COSTS_N_INSNS (18), /* sdiv */
637 COSTS_N_INSNS (32), /* ddiv */
638 32, /* cache line size */
644 /* Instruction costs on PPC604e processors. */
646 struct processor_costs ppc604e_cost
= {
647 COSTS_N_INSNS (2), /* mulsi */
648 COSTS_N_INSNS (2), /* mulsi_const */
649 COSTS_N_INSNS (2), /* mulsi_const9 */
650 COSTS_N_INSNS (2), /* muldi */
651 COSTS_N_INSNS (20), /* divsi */
652 COSTS_N_INSNS (20), /* divdi */
653 COSTS_N_INSNS (3), /* fp */
654 COSTS_N_INSNS (3), /* dmul */
655 COSTS_N_INSNS (18), /* sdiv */
656 COSTS_N_INSNS (32), /* ddiv */
657 32, /* cache line size */
663 /* Instruction costs on PPC620 processors. */
665 struct processor_costs ppc620_cost
= {
666 COSTS_N_INSNS (5), /* mulsi */
667 COSTS_N_INSNS (4), /* mulsi_const */
668 COSTS_N_INSNS (3), /* mulsi_const9 */
669 COSTS_N_INSNS (7), /* muldi */
670 COSTS_N_INSNS (21), /* divsi */
671 COSTS_N_INSNS (37), /* divdi */
672 COSTS_N_INSNS (3), /* fp */
673 COSTS_N_INSNS (3), /* dmul */
674 COSTS_N_INSNS (18), /* sdiv */
675 COSTS_N_INSNS (32), /* ddiv */
676 128, /* cache line size */
682 /* Instruction costs on PPC630 processors. */
684 struct processor_costs ppc630_cost
= {
685 COSTS_N_INSNS (5), /* mulsi */
686 COSTS_N_INSNS (4), /* mulsi_const */
687 COSTS_N_INSNS (3), /* mulsi_const9 */
688 COSTS_N_INSNS (7), /* muldi */
689 COSTS_N_INSNS (21), /* divsi */
690 COSTS_N_INSNS (37), /* divdi */
691 COSTS_N_INSNS (3), /* fp */
692 COSTS_N_INSNS (3), /* dmul */
693 COSTS_N_INSNS (17), /* sdiv */
694 COSTS_N_INSNS (21), /* ddiv */
695 128, /* cache line size */
701 /* Instruction costs on Cell processor. */
702 /* COSTS_N_INSNS (1) ~ one add. */
704 struct processor_costs ppccell_cost
= {
705 COSTS_N_INSNS (9/2)+2, /* mulsi */
706 COSTS_N_INSNS (6/2), /* mulsi_const */
707 COSTS_N_INSNS (6/2), /* mulsi_const9 */
708 COSTS_N_INSNS (15/2)+2, /* muldi */
709 COSTS_N_INSNS (38/2), /* divsi */
710 COSTS_N_INSNS (70/2), /* divdi */
711 COSTS_N_INSNS (10/2), /* fp */
712 COSTS_N_INSNS (10/2), /* dmul */
713 COSTS_N_INSNS (74/2), /* sdiv */
714 COSTS_N_INSNS (74/2), /* ddiv */
715 128, /* cache line size */
721 /* Instruction costs on PPC750 and PPC7400 processors. */
723 struct processor_costs ppc750_cost
= {
724 COSTS_N_INSNS (5), /* mulsi */
725 COSTS_N_INSNS (3), /* mulsi_const */
726 COSTS_N_INSNS (2), /* mulsi_const9 */
727 COSTS_N_INSNS (5), /* muldi */
728 COSTS_N_INSNS (17), /* divsi */
729 COSTS_N_INSNS (17), /* divdi */
730 COSTS_N_INSNS (3), /* fp */
731 COSTS_N_INSNS (3), /* dmul */
732 COSTS_N_INSNS (17), /* sdiv */
733 COSTS_N_INSNS (31), /* ddiv */
734 32, /* cache line size */
740 /* Instruction costs on PPC7450 processors. */
742 struct processor_costs ppc7450_cost
= {
743 COSTS_N_INSNS (4), /* mulsi */
744 COSTS_N_INSNS (3), /* mulsi_const */
745 COSTS_N_INSNS (3), /* mulsi_const9 */
746 COSTS_N_INSNS (4), /* muldi */
747 COSTS_N_INSNS (23), /* divsi */
748 COSTS_N_INSNS (23), /* divdi */
749 COSTS_N_INSNS (5), /* fp */
750 COSTS_N_INSNS (5), /* dmul */
751 COSTS_N_INSNS (21), /* sdiv */
752 COSTS_N_INSNS (35), /* ddiv */
753 32, /* cache line size */
759 /* Instruction costs on PPC8540 processors. */
761 struct processor_costs ppc8540_cost
= {
762 COSTS_N_INSNS (4), /* mulsi */
763 COSTS_N_INSNS (4), /* mulsi_const */
764 COSTS_N_INSNS (4), /* mulsi_const9 */
765 COSTS_N_INSNS (4), /* muldi */
766 COSTS_N_INSNS (19), /* divsi */
767 COSTS_N_INSNS (19), /* divdi */
768 COSTS_N_INSNS (4), /* fp */
769 COSTS_N_INSNS (4), /* dmul */
770 COSTS_N_INSNS (29), /* sdiv */
771 COSTS_N_INSNS (29), /* ddiv */
772 32, /* cache line size */
775 1, /* prefetch streams /*/
778 /* Instruction costs on E300C2 and E300C3 cores. */
780 struct processor_costs ppce300c2c3_cost
= {
781 COSTS_N_INSNS (4), /* mulsi */
782 COSTS_N_INSNS (4), /* mulsi_const */
783 COSTS_N_INSNS (4), /* mulsi_const9 */
784 COSTS_N_INSNS (4), /* muldi */
785 COSTS_N_INSNS (19), /* divsi */
786 COSTS_N_INSNS (19), /* divdi */
787 COSTS_N_INSNS (3), /* fp */
788 COSTS_N_INSNS (4), /* dmul */
789 COSTS_N_INSNS (18), /* sdiv */
790 COSTS_N_INSNS (33), /* ddiv */
794 1, /* prefetch streams /*/
797 /* Instruction costs on PPCE500MC processors. */
799 struct processor_costs ppce500mc_cost
= {
800 COSTS_N_INSNS (4), /* mulsi */
801 COSTS_N_INSNS (4), /* mulsi_const */
802 COSTS_N_INSNS (4), /* mulsi_const9 */
803 COSTS_N_INSNS (4), /* muldi */
804 COSTS_N_INSNS (14), /* divsi */
805 COSTS_N_INSNS (14), /* divdi */
806 COSTS_N_INSNS (8), /* fp */
807 COSTS_N_INSNS (10), /* dmul */
808 COSTS_N_INSNS (36), /* sdiv */
809 COSTS_N_INSNS (66), /* ddiv */
810 64, /* cache line size */
813 1, /* prefetch streams /*/
816 /* Instruction costs on PPCE500MC64 processors. */
818 struct processor_costs ppce500mc64_cost
= {
819 COSTS_N_INSNS (4), /* mulsi */
820 COSTS_N_INSNS (4), /* mulsi_const */
821 COSTS_N_INSNS (4), /* mulsi_const9 */
822 COSTS_N_INSNS (4), /* muldi */
823 COSTS_N_INSNS (14), /* divsi */
824 COSTS_N_INSNS (14), /* divdi */
825 COSTS_N_INSNS (4), /* fp */
826 COSTS_N_INSNS (10), /* dmul */
827 COSTS_N_INSNS (36), /* sdiv */
828 COSTS_N_INSNS (66), /* ddiv */
829 64, /* cache line size */
832 1, /* prefetch streams /*/
835 /* Instruction costs on PPCE5500 processors. */
837 struct processor_costs ppce5500_cost
= {
838 COSTS_N_INSNS (5), /* mulsi */
839 COSTS_N_INSNS (5), /* mulsi_const */
840 COSTS_N_INSNS (4), /* mulsi_const9 */
841 COSTS_N_INSNS (5), /* muldi */
842 COSTS_N_INSNS (14), /* divsi */
843 COSTS_N_INSNS (14), /* divdi */
844 COSTS_N_INSNS (7), /* fp */
845 COSTS_N_INSNS (10), /* dmul */
846 COSTS_N_INSNS (36), /* sdiv */
847 COSTS_N_INSNS (66), /* ddiv */
848 64, /* cache line size */
851 1, /* prefetch streams /*/
854 /* Instruction costs on PPCE6500 processors. */
856 struct processor_costs ppce6500_cost
= {
857 COSTS_N_INSNS (5), /* mulsi */
858 COSTS_N_INSNS (5), /* mulsi_const */
859 COSTS_N_INSNS (4), /* mulsi_const9 */
860 COSTS_N_INSNS (5), /* muldi */
861 COSTS_N_INSNS (14), /* divsi */
862 COSTS_N_INSNS (14), /* divdi */
863 COSTS_N_INSNS (7), /* fp */
864 COSTS_N_INSNS (10), /* dmul */
865 COSTS_N_INSNS (36), /* sdiv */
866 COSTS_N_INSNS (66), /* ddiv */
867 64, /* cache line size */
870 1, /* prefetch streams /*/
873 /* Instruction costs on AppliedMicro Titan processors. */
875 struct processor_costs titan_cost
= {
876 COSTS_N_INSNS (5), /* mulsi */
877 COSTS_N_INSNS (5), /* mulsi_const */
878 COSTS_N_INSNS (5), /* mulsi_const9 */
879 COSTS_N_INSNS (5), /* muldi */
880 COSTS_N_INSNS (18), /* divsi */
881 COSTS_N_INSNS (18), /* divdi */
882 COSTS_N_INSNS (10), /* fp */
883 COSTS_N_INSNS (10), /* dmul */
884 COSTS_N_INSNS (46), /* sdiv */
885 COSTS_N_INSNS (72), /* ddiv */
886 32, /* cache line size */
889 1, /* prefetch streams /*/
892 /* Instruction costs on POWER4 and POWER5 processors. */
894 struct processor_costs power4_cost
= {
895 COSTS_N_INSNS (3), /* mulsi */
896 COSTS_N_INSNS (2), /* mulsi_const */
897 COSTS_N_INSNS (2), /* mulsi_const9 */
898 COSTS_N_INSNS (4), /* muldi */
899 COSTS_N_INSNS (18), /* divsi */
900 COSTS_N_INSNS (34), /* divdi */
901 COSTS_N_INSNS (3), /* fp */
902 COSTS_N_INSNS (3), /* dmul */
903 COSTS_N_INSNS (17), /* sdiv */
904 COSTS_N_INSNS (17), /* ddiv */
905 128, /* cache line size */
908 8, /* prefetch streams /*/
911 /* Instruction costs on POWER6 processors. */
913 struct processor_costs power6_cost
= {
914 COSTS_N_INSNS (8), /* mulsi */
915 COSTS_N_INSNS (8), /* mulsi_const */
916 COSTS_N_INSNS (8), /* mulsi_const9 */
917 COSTS_N_INSNS (8), /* muldi */
918 COSTS_N_INSNS (22), /* divsi */
919 COSTS_N_INSNS (28), /* divdi */
920 COSTS_N_INSNS (3), /* fp */
921 COSTS_N_INSNS (3), /* dmul */
922 COSTS_N_INSNS (13), /* sdiv */
923 COSTS_N_INSNS (16), /* ddiv */
924 128, /* cache line size */
927 16, /* prefetch streams */
930 /* Instruction costs on POWER7 processors. */
932 struct processor_costs power7_cost
= {
933 COSTS_N_INSNS (2), /* mulsi */
934 COSTS_N_INSNS (2), /* mulsi_const */
935 COSTS_N_INSNS (2), /* mulsi_const9 */
936 COSTS_N_INSNS (2), /* muldi */
937 COSTS_N_INSNS (18), /* divsi */
938 COSTS_N_INSNS (34), /* divdi */
939 COSTS_N_INSNS (3), /* fp */
940 COSTS_N_INSNS (3), /* dmul */
941 COSTS_N_INSNS (13), /* sdiv */
942 COSTS_N_INSNS (16), /* ddiv */
943 128, /* cache line size */
946 12, /* prefetch streams */
949 /* Instruction costs on POWER8 processors. */
951 struct processor_costs power8_cost
= {
952 COSTS_N_INSNS (3), /* mulsi */
953 COSTS_N_INSNS (3), /* mulsi_const */
954 COSTS_N_INSNS (3), /* mulsi_const9 */
955 COSTS_N_INSNS (3), /* muldi */
956 COSTS_N_INSNS (19), /* divsi */
957 COSTS_N_INSNS (35), /* divdi */
958 COSTS_N_INSNS (3), /* fp */
959 COSTS_N_INSNS (3), /* dmul */
960 COSTS_N_INSNS (14), /* sdiv */
961 COSTS_N_INSNS (17), /* ddiv */
962 128, /* cache line size */
965 12, /* prefetch streams */
968 /* Instruction costs on POWER A2 processors. */
970 struct processor_costs ppca2_cost
= {
971 COSTS_N_INSNS (16), /* mulsi */
972 COSTS_N_INSNS (16), /* mulsi_const */
973 COSTS_N_INSNS (16), /* mulsi_const9 */
974 COSTS_N_INSNS (16), /* muldi */
975 COSTS_N_INSNS (22), /* divsi */
976 COSTS_N_INSNS (28), /* divdi */
977 COSTS_N_INSNS (3), /* fp */
978 COSTS_N_INSNS (3), /* dmul */
979 COSTS_N_INSNS (59), /* sdiv */
980 COSTS_N_INSNS (72), /* ddiv */
984 16, /* prefetch streams */
988 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
989 #undef RS6000_BUILTIN_1
990 #undef RS6000_BUILTIN_2
991 #undef RS6000_BUILTIN_3
992 #undef RS6000_BUILTIN_A
993 #undef RS6000_BUILTIN_D
994 #undef RS6000_BUILTIN_E
995 #undef RS6000_BUILTIN_H
996 #undef RS6000_BUILTIN_P
997 #undef RS6000_BUILTIN_Q
998 #undef RS6000_BUILTIN_S
999 #undef RS6000_BUILTIN_X
1001 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1002 { NAME, ICODE, MASK, ATTR },
1004 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1005 { NAME, ICODE, MASK, ATTR },
1007 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1008 { NAME, ICODE, MASK, ATTR },
1010 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1011 { NAME, ICODE, MASK, ATTR },
1013 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1014 { NAME, ICODE, MASK, ATTR },
1016 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1017 { NAME, ICODE, MASK, ATTR },
1019 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1020 { NAME, ICODE, MASK, ATTR },
1022 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1023 { NAME, ICODE, MASK, ATTR },
1025 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1026 { NAME, ICODE, MASK, ATTR },
1028 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1029 { NAME, ICODE, MASK, ATTR },
1031 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1032 { NAME, ICODE, MASK, ATTR },
1034 struct rs6000_builtin_info_type
{
1036 const enum insn_code icode
;
1037 const HOST_WIDE_INT mask
;
1038 const unsigned attr
;
1041 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1043 #include "rs6000-builtin.def"
1046 #undef RS6000_BUILTIN_1
1047 #undef RS6000_BUILTIN_2
1048 #undef RS6000_BUILTIN_3
1049 #undef RS6000_BUILTIN_A
1050 #undef RS6000_BUILTIN_D
1051 #undef RS6000_BUILTIN_E
1052 #undef RS6000_BUILTIN_H
1053 #undef RS6000_BUILTIN_P
1054 #undef RS6000_BUILTIN_Q
1055 #undef RS6000_BUILTIN_S
1056 #undef RS6000_BUILTIN_X
1058 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1059 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1062 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
1063 static bool spe_func_has_64bit_regs_p (void);
1064 static struct machine_function
* rs6000_init_machine_status (void);
1065 static int rs6000_ra_ever_killed (void);
1066 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1067 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1068 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1069 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1070 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
1071 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1072 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1073 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
1075 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
1076 static bool is_microcoded_insn (rtx
);
1077 static bool is_nonpipeline_insn (rtx
);
1078 static bool is_cracked_insn (rtx
);
1079 static bool is_load_insn (rtx
, rtx
*);
1080 static bool is_store_insn (rtx
, rtx
*);
1081 static bool set_to_load_agen (rtx
,rtx
);
1082 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1083 static bool insn_must_be_first_in_group (rtx
);
1084 static bool insn_must_be_last_in_group (rtx
);
1085 static void altivec_init_builtins (void);
1086 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1087 enum machine_mode
, enum machine_mode
,
1088 enum rs6000_builtins
, const char *name
);
1089 static void rs6000_common_init_builtins (void);
1090 static void paired_init_builtins (void);
1091 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1092 static void spe_init_builtins (void);
1093 static void htm_init_builtins (void);
1094 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1095 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1096 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1097 static rs6000_stack_t
*rs6000_stack_info (void);
1098 static void is_altivec_return_reg (rtx
, void *);
1099 int easy_vector_constant (rtx
, enum machine_mode
);
1100 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1101 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1102 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1103 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1104 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1107 static void macho_branch_islands (void);
1109 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1111 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1113 static bool rs6000_mode_dependent_address (const_rtx
);
1114 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1115 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1116 enum machine_mode
, rtx
);
1117 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1120 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1121 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1123 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1125 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1128 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1131 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1134 static bool rs6000_save_toc_in_prologue_p (void);
1136 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1138 = rs6000_legitimize_reload_address
;
1140 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1141 = rs6000_mode_dependent_address
;
1143 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1144 enum machine_mode
, rtx
)
1145 = rs6000_secondary_reload_class
;
1147 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1148 = rs6000_preferred_reload_class
;
1150 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1152 = rs6000_secondary_memory_needed
;
1154 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1157 = rs6000_cannot_change_mode_class
;
1159 const int INSN_NOT_AVAILABLE
= -1;
1161 static void rs6000_print_isa_options (FILE *, int, const char *,
1163 static void rs6000_print_builtin_options (FILE *, int, const char *,
1166 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1167 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1168 enum rs6000_reg_type
,
1170 secondary_reload_info
*,
1173 /* Hash table stuff for keeping track of TOC entries. */
1175 struct GTY(()) toc_hash_struct
1177 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1178 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1180 enum machine_mode key_mode
;
1184 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1186 /* Hash table to keep track of the argument types for builtin functions. */
1188 struct GTY(()) builtin_hash_struct
1191 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1192 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1195 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1198 /* Default register names. */
1199 char rs6000_reg_names
[][8] =
1201 "0", "1", "2", "3", "4", "5", "6", "7",
1202 "8", "9", "10", "11", "12", "13", "14", "15",
1203 "16", "17", "18", "19", "20", "21", "22", "23",
1204 "24", "25", "26", "27", "28", "29", "30", "31",
1205 "0", "1", "2", "3", "4", "5", "6", "7",
1206 "8", "9", "10", "11", "12", "13", "14", "15",
1207 "16", "17", "18", "19", "20", "21", "22", "23",
1208 "24", "25", "26", "27", "28", "29", "30", "31",
1209 "mq", "lr", "ctr","ap",
1210 "0", "1", "2", "3", "4", "5", "6", "7",
1212 /* AltiVec registers. */
1213 "0", "1", "2", "3", "4", "5", "6", "7",
1214 "8", "9", "10", "11", "12", "13", "14", "15",
1215 "16", "17", "18", "19", "20", "21", "22", "23",
1216 "24", "25", "26", "27", "28", "29", "30", "31",
1218 /* SPE registers. */
1219 "spe_acc", "spefscr",
1220 /* Soft frame pointer. */
1222 /* HTM SPR registers. */
1223 "tfhar", "tfiar", "texasr"
1226 #ifdef TARGET_REGNAMES
1227 static const char alt_reg_names
[][8] =
1229 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1230 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1231 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1232 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1233 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1234 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1235 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1236 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1237 "mq", "lr", "ctr", "ap",
1238 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1240 /* AltiVec registers. */
1241 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1242 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1243 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1244 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1246 /* SPE registers. */
1247 "spe_acc", "spefscr",
1248 /* Soft frame pointer. */
1250 /* HTM SPR registers. */
1251 "tfhar", "tfiar", "texasr"
1255 /* Table of valid machine attributes. */
1257 static const struct attribute_spec rs6000_attribute_table
[] =
1259 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1260 affects_type_identity } */
1261 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1263 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1265 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1267 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1269 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1271 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1272 SUBTARGET_ATTRIBUTE_TABLE
,
1274 { NULL
, 0, 0, false, false, false, NULL
, false }
1277 #ifndef TARGET_PROFILE_KERNEL
1278 #define TARGET_PROFILE_KERNEL 0
1281 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1282 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1284 /* Initialize the GCC target structure. */
1285 #undef TARGET_ATTRIBUTE_TABLE
1286 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1287 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1288 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1289 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1290 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1292 #undef TARGET_ASM_ALIGNED_DI_OP
1293 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1295 /* Default unaligned ops are only provided for ELF. Find the ops needed
1296 for non-ELF systems. */
1297 #ifndef OBJECT_FORMAT_ELF
1299 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1301 #undef TARGET_ASM_UNALIGNED_HI_OP
1302 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1303 #undef TARGET_ASM_UNALIGNED_SI_OP
1304 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1305 #undef TARGET_ASM_UNALIGNED_DI_OP
1306 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1309 #undef TARGET_ASM_UNALIGNED_HI_OP
1310 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1311 #undef TARGET_ASM_UNALIGNED_SI_OP
1312 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1313 #undef TARGET_ASM_UNALIGNED_DI_OP
1314 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1315 #undef TARGET_ASM_ALIGNED_DI_OP
1316 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1320 /* This hook deals with fixups for relocatable code and DI-mode objects
1322 #undef TARGET_ASM_INTEGER
1323 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1325 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1326 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1327 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1330 #undef TARGET_SET_UP_BY_PROLOGUE
1331 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1333 #undef TARGET_HAVE_TLS
1334 #define TARGET_HAVE_TLS HAVE_AS_TLS
1336 #undef TARGET_CANNOT_FORCE_CONST_MEM
1337 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1339 #undef TARGET_DELEGITIMIZE_ADDRESS
1340 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1342 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1343 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1345 #undef TARGET_ASM_FUNCTION_PROLOGUE
1346 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1347 #undef TARGET_ASM_FUNCTION_EPILOGUE
1348 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1350 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1351 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1353 #undef TARGET_LEGITIMIZE_ADDRESS
1354 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1356 #undef TARGET_SCHED_VARIABLE_ISSUE
1357 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1359 #undef TARGET_SCHED_ISSUE_RATE
1360 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1361 #undef TARGET_SCHED_ADJUST_COST
1362 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1363 #undef TARGET_SCHED_ADJUST_PRIORITY
1364 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1365 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1366 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1367 #undef TARGET_SCHED_INIT
1368 #define TARGET_SCHED_INIT rs6000_sched_init
1369 #undef TARGET_SCHED_FINISH
1370 #define TARGET_SCHED_FINISH rs6000_sched_finish
1371 #undef TARGET_SCHED_REORDER
1372 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1373 #undef TARGET_SCHED_REORDER2
1374 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1376 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1377 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1379 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1380 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1382 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1383 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1384 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1385 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1386 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1387 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1388 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1389 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1391 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1392 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1393 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1394 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1395 rs6000_builtin_support_vector_misalignment
1396 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1397 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1398 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1399 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1400 rs6000_builtin_vectorization_cost
1401 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1402 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1403 rs6000_preferred_simd_mode
1404 #undef TARGET_VECTORIZE_INIT_COST
1405 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1406 #undef TARGET_VECTORIZE_ADD_STMT_COST
1407 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1408 #undef TARGET_VECTORIZE_FINISH_COST
1409 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1410 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1411 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1413 #undef TARGET_INIT_BUILTINS
1414 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1415 #undef TARGET_BUILTIN_DECL
1416 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1418 #undef TARGET_EXPAND_BUILTIN
1419 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1421 #undef TARGET_MANGLE_TYPE
1422 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1424 #undef TARGET_INIT_LIBFUNCS
1425 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1428 #undef TARGET_BINDS_LOCAL_P
1429 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1432 #undef TARGET_MS_BITFIELD_LAYOUT_P
1433 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1435 #undef TARGET_ASM_OUTPUT_MI_THUNK
1436 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1438 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1439 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1441 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1442 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1444 #undef TARGET_REGISTER_MOVE_COST
1445 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1446 #undef TARGET_MEMORY_MOVE_COST
1447 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1448 #undef TARGET_RTX_COSTS
1449 #define TARGET_RTX_COSTS rs6000_rtx_costs
1450 #undef TARGET_ADDRESS_COST
1451 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1453 #undef TARGET_DWARF_REGISTER_SPAN
1454 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1456 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1457 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1459 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1460 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1462 /* On rs6000, function arguments are promoted, as are function return
1464 #undef TARGET_PROMOTE_FUNCTION_MODE
1465 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1467 #undef TARGET_RETURN_IN_MEMORY
1468 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1470 #undef TARGET_RETURN_IN_MSB
1471 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1473 #undef TARGET_SETUP_INCOMING_VARARGS
1474 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1476 /* Always strict argument naming on rs6000. */
1477 #undef TARGET_STRICT_ARGUMENT_NAMING
1478 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1479 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1480 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1481 #undef TARGET_SPLIT_COMPLEX_ARG
1482 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1483 #undef TARGET_MUST_PASS_IN_STACK
1484 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1485 #undef TARGET_PASS_BY_REFERENCE
1486 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1487 #undef TARGET_ARG_PARTIAL_BYTES
1488 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1489 #undef TARGET_FUNCTION_ARG_ADVANCE
1490 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1491 #undef TARGET_FUNCTION_ARG
1492 #define TARGET_FUNCTION_ARG rs6000_function_arg
1493 #undef TARGET_FUNCTION_ARG_BOUNDARY
1494 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1496 #undef TARGET_BUILD_BUILTIN_VA_LIST
1497 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1499 #undef TARGET_EXPAND_BUILTIN_VA_START
1500 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1502 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1503 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1505 #undef TARGET_EH_RETURN_FILTER_MODE
1506 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1508 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1509 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1511 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1512 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1514 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1515 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1517 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1518 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1520 #undef TARGET_OPTION_OVERRIDE
1521 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1523 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1524 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1525 rs6000_builtin_vectorized_function
1528 #undef TARGET_STACK_PROTECT_FAIL
1529 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1532 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1533 The PowerPC architecture requires only weak consistency among
1534 processors--that is, memory accesses between processors need not be
1535 sequentially consistent and memory accesses among processors can occur
1536 in any order. The ability to order memory accesses weakly provides
1537 opportunities for more efficient use of the system bus. Unless a
1538 dependency exists, the 604e allows read operations to precede store
1540 #undef TARGET_RELAXED_ORDERING
1541 #define TARGET_RELAXED_ORDERING true
1544 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1545 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1548 /* Use a 32-bit anchor range. This leads to sequences like:
1550 addis tmp,anchor,high
1553 where tmp itself acts as an anchor, and can be shared between
1554 accesses to the same 64k page. */
1555 #undef TARGET_MIN_ANCHOR_OFFSET
1556 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1557 #undef TARGET_MAX_ANCHOR_OFFSET
1558 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1559 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1560 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1561 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1562 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1564 #undef TARGET_BUILTIN_RECIPROCAL
1565 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1567 #undef TARGET_EXPAND_TO_RTL_HOOK
1568 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1570 #undef TARGET_INSTANTIATE_DECLS
1571 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1573 #undef TARGET_SECONDARY_RELOAD
1574 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1576 #undef TARGET_LEGITIMATE_ADDRESS_P
1577 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1579 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1580 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1583 #define TARGET_LRA_P rs6000_lra_p
1585 #undef TARGET_CAN_ELIMINATE
1586 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1588 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1589 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1591 #undef TARGET_TRAMPOLINE_INIT
1592 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1594 #undef TARGET_FUNCTION_VALUE
1595 #define TARGET_FUNCTION_VALUE rs6000_function_value
1597 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1598 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1600 #undef TARGET_OPTION_SAVE
1601 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1603 #undef TARGET_OPTION_RESTORE
1604 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1606 #undef TARGET_OPTION_PRINT
1607 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1609 #undef TARGET_CAN_INLINE_P
1610 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1612 #undef TARGET_SET_CURRENT_FUNCTION
1613 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1615 #undef TARGET_LEGITIMATE_CONSTANT_P
1616 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1618 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1619 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1621 #undef TARGET_CAN_USE_DOLOOP_P
1622 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1625 /* Processor table. */
1628 const char *const name
; /* Canonical processor name. */
1629 const enum processor_type processor
; /* Processor type enum value. */
1630 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1633 static struct rs6000_ptt
const processor_target_table
[] =
1635 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1636 #include "rs6000-cpus.def"
1640 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1644 rs6000_cpu_name_lookup (const char *name
)
1650 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1651 if (! strcmp (name
, processor_target_table
[i
].name
))
1659 /* Return number of consecutive hard regs needed starting at reg REGNO
1660 to hold something of mode MODE.
1661 This is ordinarily the length in words of a value of mode MODE
1662 but can be less for certain modes in special long registers.
1664 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1665 scalar instructions. The upper 32 bits are only available to the
1668 POWER and PowerPC GPRs hold 32 bits worth;
1669 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1672 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1674 unsigned HOST_WIDE_INT reg_size
;
1676 /* TF/TD modes are special in that they always take 2 registers. */
1677 if (FP_REGNO_P (regno
))
1678 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1679 ? UNITS_PER_VSX_WORD
1680 : UNITS_PER_FP_WORD
);
1682 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1683 reg_size
= UNITS_PER_SPE_WORD
;
1685 else if (ALTIVEC_REGNO_P (regno
))
1686 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1688 /* The value returned for SCmode in the E500 double case is 2 for
1689 ABI compatibility; storing an SCmode value in a single register
1690 would require function_arg and rs6000_spe_function_arg to handle
1691 SCmode so as to pass the value correctly in a pair of
1693 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1694 && !DECIMAL_FLOAT_MODE_P (mode
))
1695 reg_size
= UNITS_PER_FP_WORD
;
1698 reg_size
= UNITS_PER_WORD
;
1700 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1703 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1706 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1708 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1710 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1711 register combinations, and use PTImode where we need to deal with quad
1712 word memory operations. Don't allow quad words in the argument or frame
1713 pointer registers, just registers 0..31. */
1714 if (mode
== PTImode
)
1715 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1716 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1717 && ((regno
& 1) == 0));
1719 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1720 implementations. Don't allow an item to be split between a FP register
1721 and an Altivec register. Allow TImode in all VSX registers if the user
1723 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1724 && (VECTOR_MEM_VSX_P (mode
)
1725 || (TARGET_VSX_SCALAR_FLOAT
&& mode
== SFmode
)
1726 || (TARGET_VSX_SCALAR_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
1727 || (TARGET_VSX_TIMODE
&& mode
== TImode
)))
1729 if (FP_REGNO_P (regno
))
1730 return FP_REGNO_P (last_regno
);
1732 if (ALTIVEC_REGNO_P (regno
))
1734 if (mode
== SFmode
&& !TARGET_UPPER_REGS_SF
)
1737 if ((mode
== DFmode
|| mode
== DImode
) && !TARGET_UPPER_REGS_DF
)
1740 return ALTIVEC_REGNO_P (last_regno
);
1744 /* The GPRs can hold any mode, but values bigger than one register
1745 cannot go past R31. */
1746 if (INT_REGNO_P (regno
))
1747 return INT_REGNO_P (last_regno
);
1749 /* The float registers (except for VSX vector modes) can only hold floating
1750 modes and DImode. */
1751 if (FP_REGNO_P (regno
))
1753 if (SCALAR_FLOAT_MODE_P (mode
)
1754 && (mode
!= TDmode
|| (regno
% 2) == 0)
1755 && FP_REGNO_P (last_regno
))
1758 if (GET_MODE_CLASS (mode
) == MODE_INT
1759 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1762 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1763 && PAIRED_VECTOR_MODE (mode
))
1769 /* The CR register can only hold CC modes. */
1770 if (CR_REGNO_P (regno
))
1771 return GET_MODE_CLASS (mode
) == MODE_CC
;
1773 if (CA_REGNO_P (regno
))
1774 return mode
== BImode
;
1776 /* AltiVec only in AldyVec registers. */
1777 if (ALTIVEC_REGNO_P (regno
))
1778 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1780 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1781 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1784 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1785 and it must be able to fit within the register set. */
1787 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1790 /* Print interesting facts about registers. */
1792 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1796 for (r
= first_regno
; r
<= last_regno
; ++r
)
1798 const char *comma
= "";
1801 if (first_regno
== last_regno
)
1802 fprintf (stderr
, "%s:\t", reg_name
);
1804 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1807 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1808 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1812 fprintf (stderr
, ",\n\t");
1817 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1818 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1819 rs6000_hard_regno_nregs
[m
][r
]);
1821 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1826 if (call_used_regs
[r
])
1830 fprintf (stderr
, ",\n\t");
1835 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1843 fprintf (stderr
, ",\n\t");
1848 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1854 fprintf (stderr
, ",\n\t");
1858 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1859 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1864 fprintf (stderr
, ",\n\t");
1868 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1873 rs6000_debug_vector_unit (enum rs6000_vector v
)
1879 case VECTOR_NONE
: ret
= "none"; break;
1880 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1881 case VECTOR_VSX
: ret
= "vsx"; break;
1882 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1883 case VECTOR_PAIRED
: ret
= "paired"; break;
1884 case VECTOR_SPE
: ret
= "spe"; break;
1885 case VECTOR_OTHER
: ret
= "other"; break;
1886 default: ret
= "unknown"; break;
1892 /* Print the address masks in a human readble fashion. */
1894 rs6000_debug_print_mode (ssize_t m
)
1898 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
1899 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
1901 addr_mask_type mask
= reg_addr
[m
].addr_mask
[rc
];
1903 " %s: %c%c%c%c%c%c",
1904 reload_reg_map
[rc
].name
,
1905 (mask
& RELOAD_REG_VALID
) != 0 ? 'v' : ' ',
1906 (mask
& RELOAD_REG_MULTIPLE
) != 0 ? 'm' : ' ',
1907 (mask
& RELOAD_REG_INDEXED
) != 0 ? 'i' : ' ',
1908 (mask
& RELOAD_REG_OFFSET
) != 0 ? 'o' : ' ',
1909 (mask
& RELOAD_REG_PRE_INCDEC
) != 0 ? '+' : ' ',
1910 (mask
& RELOAD_REG_PRE_MODIFY
) != 0 ? '+' : ' ');
1913 if (rs6000_vector_unit
[m
] != VECTOR_NONE
1914 || rs6000_vector_mem
[m
] != VECTOR_NONE
1915 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
1916 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
1919 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
1920 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
1921 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
1922 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
1923 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
1926 fputs ("\n", stderr
);
1929 #define DEBUG_FMT_ID "%-32s= "
1930 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1931 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1932 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1934 /* Print various interesting information with -mdebug=reg. */
1936 rs6000_debug_reg_global (void)
1938 static const char *const tf
[2] = { "false", "true" };
1939 const char *nl
= (const char *)0;
1942 char costly_num
[20];
1944 char flags_buffer
[40];
1945 const char *costly_str
;
1946 const char *nop_str
;
1947 const char *trace_str
;
1948 const char *abi_str
;
1949 const char *cmodel_str
;
1950 struct cl_target_option cl_opts
;
1952 /* Modes we want tieable information on. */
1953 static const enum machine_mode print_tieable_modes
[] = {
1987 /* Virtual regs we are interested in. */
1988 const static struct {
1989 int regno
; /* register number. */
1990 const char *name
; /* register name. */
1991 } virtual_regs
[] = {
1992 { STACK_POINTER_REGNUM
, "stack pointer:" },
1993 { TOC_REGNUM
, "toc: " },
1994 { STATIC_CHAIN_REGNUM
, "static chain: " },
1995 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
1996 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
1997 { ARG_POINTER_REGNUM
, "arg pointer: " },
1998 { FRAME_POINTER_REGNUM
, "frame pointer:" },
1999 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2000 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2001 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2002 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2003 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2004 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2005 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2006 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2007 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2010 fputs ("\nHard register information:\n", stderr
);
2011 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2012 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2013 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2016 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2017 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2018 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2019 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2020 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2021 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2022 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2023 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2025 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2026 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2027 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2031 "d reg_class = %s\n"
2032 "f reg_class = %s\n"
2033 "v reg_class = %s\n"
2034 "wa reg_class = %s\n"
2035 "wd reg_class = %s\n"
2036 "wf reg_class = %s\n"
2037 "wg reg_class = %s\n"
2038 "wl reg_class = %s\n"
2039 "wm reg_class = %s\n"
2040 "wr reg_class = %s\n"
2041 "ws reg_class = %s\n"
2042 "wt reg_class = %s\n"
2043 "wu reg_class = %s\n"
2044 "wv reg_class = %s\n"
2045 "ww reg_class = %s\n"
2046 "wx reg_class = %s\n"
2047 "wy reg_class = %s\n"
2048 "wz reg_class = %s\n"
2050 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2051 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2052 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2053 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2054 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2055 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2056 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2057 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2058 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2059 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2060 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2061 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2062 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2063 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2064 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2065 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2066 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2067 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2070 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2071 rs6000_debug_print_mode (m
);
2073 fputs ("\n", stderr
);
2075 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2077 enum machine_mode mode1
= print_tieable_modes
[m1
];
2078 bool first_time
= true;
2080 nl
= (const char *)0;
2081 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2083 enum machine_mode mode2
= print_tieable_modes
[m2
];
2084 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2088 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2093 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2098 fputs ("\n", stderr
);
2104 if (rs6000_recip_control
)
2106 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2108 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2109 if (rs6000_recip_bits
[m
])
2112 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2114 (RS6000_RECIP_AUTO_RE_P (m
)
2116 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2117 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2119 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2122 fputs ("\n", stderr
);
2125 if (rs6000_cpu_index
>= 0)
2127 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2129 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2131 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2132 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2135 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2137 if (rs6000_tune_index
>= 0)
2139 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2141 = processor_target_table
[rs6000_tune_index
].target_enable
;
2143 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2144 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2147 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2149 cl_target_option_save (&cl_opts
, &global_options
);
2150 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2153 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2154 rs6000_isa_flags_explicit
);
2156 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2157 rs6000_builtin_mask
);
2159 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2161 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2162 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2164 switch (rs6000_sched_costly_dep
)
2166 case max_dep_latency
:
2167 costly_str
= "max_dep_latency";
2171 costly_str
= "no_dep_costly";
2174 case all_deps_costly
:
2175 costly_str
= "all_deps_costly";
2178 case true_store_to_load_dep_costly
:
2179 costly_str
= "true_store_to_load_dep_costly";
2182 case store_to_load_dep_costly
:
2183 costly_str
= "store_to_load_dep_costly";
2187 costly_str
= costly_num
;
2188 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2192 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2194 switch (rs6000_sched_insert_nops
)
2196 case sched_finish_regroup_exact
:
2197 nop_str
= "sched_finish_regroup_exact";
2200 case sched_finish_pad_groups
:
2201 nop_str
= "sched_finish_pad_groups";
2204 case sched_finish_none
:
2205 nop_str
= "sched_finish_none";
2210 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2214 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2216 switch (rs6000_sdata
)
2223 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2227 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2231 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2236 switch (rs6000_traceback
)
2238 case traceback_default
: trace_str
= "default"; break;
2239 case traceback_none
: trace_str
= "none"; break;
2240 case traceback_part
: trace_str
= "part"; break;
2241 case traceback_full
: trace_str
= "full"; break;
2242 default: trace_str
= "unknown"; break;
2245 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2247 switch (rs6000_current_cmodel
)
2249 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2250 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2251 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2252 default: cmodel_str
= "unknown"; break;
2255 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2257 switch (rs6000_current_abi
)
2259 case ABI_NONE
: abi_str
= "none"; break;
2260 case ABI_AIX
: abi_str
= "aix"; break;
2261 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2262 case ABI_V4
: abi_str
= "V4"; break;
2263 case ABI_DARWIN
: abi_str
= "darwin"; break;
2264 default: abi_str
= "unknown"; break;
2267 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2269 if (rs6000_altivec_abi
)
2270 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2273 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2275 if (rs6000_darwin64_abi
)
2276 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2278 if (rs6000_float_gprs
)
2279 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2281 if (TARGET_LINK_STACK
)
2282 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2284 if (targetm
.lra_p ())
2285 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2287 if (TARGET_P8_FUSION
)
2288 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2289 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2291 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2292 TARGET_SECURE_PLT
? "secure" : "bss");
2293 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2294 aix_struct_return
? "aix" : "sysv");
2295 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2296 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2297 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2298 tf
[!!rs6000_align_branch_targets
]);
2299 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2300 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2301 rs6000_long_double_type_size
);
2302 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2303 (int)rs6000_sched_restricted_insns_priority
);
2304 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2306 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2307 (int)RS6000_BUILTIN_COUNT
);
2311 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2312 legitimate address support to figure out the appropriate addressing to
2316 rs6000_setup_reg_addr_masks (void)
2318 ssize_t rc
, reg
, m
, nregs
;
2319 addr_mask_type any_addr_mask
, addr_mask
;
2321 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2323 /* SDmode is special in that we want to access it only via REG+REG
2324 addressing on power7 and above, since we want to use the LFIWZX and
2325 STFIWZX instructions to load it. */
2326 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2329 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2332 reg
= reload_reg_map
[rc
].reg
;
2334 /* Can mode values go in the GPR/FPR/Altivec registers? */
2335 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2337 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2338 addr_mask
|= RELOAD_REG_VALID
;
2340 /* Indicate if the mode takes more than 1 physical register. If
2341 it takes a single register, indicate it can do REG+REG
2343 if (nregs
> 1 || m
== BLKmode
)
2344 addr_mask
|= RELOAD_REG_MULTIPLE
;
2346 addr_mask
|= RELOAD_REG_INDEXED
;
2348 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2349 addressing. Restrict addressing on SPE for 64-bit types
2350 because of the SUBREG hackery used to address 64-bit floats in
2351 '32-bit' GPRs. To simplify secondary reload, don't allow
2352 update forms on scalar floating point types that can go in the
2356 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2357 && GET_MODE_SIZE (m
) <= 8
2358 && !VECTOR_MODE_P (m
)
2359 && !COMPLEX_MODE_P (m
)
2361 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m
) == 8)
2362 && !(m
== DFmode
&& TARGET_UPPER_REGS_DF
)
2363 && !(m
== SFmode
&& TARGET_UPPER_REGS_SF
))
2365 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2367 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2368 we don't allow PRE_MODIFY for some multi-register
2373 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2377 if (TARGET_POWERPC64
)
2378 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2384 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2390 /* GPR and FPR registers can do REG+OFFSET addressing, except
2391 possibly for SDmode. */
2392 if ((addr_mask
!= 0) && !indexed_only_p
2393 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2394 addr_mask
|= RELOAD_REG_OFFSET
;
2396 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2397 any_addr_mask
|= addr_mask
;
2400 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2405 /* Initialize the various global tables that are based on register size. */
2407 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2413 /* Precalculate REGNO_REG_CLASS. */
2414 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2415 for (r
= 1; r
< 32; ++r
)
2416 rs6000_regno_regclass
[r
] = BASE_REGS
;
2418 for (r
= 32; r
< 64; ++r
)
2419 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2421 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2422 rs6000_regno_regclass
[r
] = NO_REGS
;
2424 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2425 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2427 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2428 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2429 rs6000_regno_regclass
[r
] = CR_REGS
;
2431 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2432 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2433 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2434 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2435 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2436 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2437 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2438 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2439 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2440 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2441 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2442 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2444 /* Precalculate register class to simpler reload register class. We don't
2445 need all of the register classes that are combinations of different
2446 classes, just the simple ones that have constraint letters. */
2447 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2448 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2450 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2451 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2452 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2453 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2454 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2455 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2456 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2457 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2458 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2459 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2460 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2461 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2465 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2466 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2470 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2471 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2474 /* Precalculate the valid memory formats as well as the vector information,
2475 this must be set up before the rs6000_hard_regno_nregs_internal calls
2477 gcc_assert ((int)VECTOR_NONE
== 0);
2478 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2479 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2481 gcc_assert ((int)CODE_FOR_nothing
== 0);
2482 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2484 gcc_assert ((int)NO_REGS
== 0);
2485 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2487 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2488 believes it can use native alignment or still uses 128-bit alignment. */
2489 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2500 /* V2DF mode, VSX only. */
2503 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2504 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2505 rs6000_vector_align
[V2DFmode
] = align64
;
2508 /* V4SF mode, either VSX or Altivec. */
2511 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2512 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2513 rs6000_vector_align
[V4SFmode
] = align32
;
2515 else if (TARGET_ALTIVEC
)
2517 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2518 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2519 rs6000_vector_align
[V4SFmode
] = align32
;
2522 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2526 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2527 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2528 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2529 rs6000_vector_align
[V4SImode
] = align32
;
2530 rs6000_vector_align
[V8HImode
] = align32
;
2531 rs6000_vector_align
[V16QImode
] = align32
;
2535 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2536 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2537 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2541 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2542 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2543 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2547 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2548 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2551 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2552 rs6000_vector_unit
[V2DImode
]
2553 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2554 rs6000_vector_align
[V2DImode
] = align64
;
2557 /* DFmode, see if we want to use the VSX unit. */
2558 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2560 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2561 rs6000_vector_mem
[DFmode
]
2562 = (TARGET_UPPER_REGS_DF
? VECTOR_VSX
: VECTOR_NONE
);
2563 rs6000_vector_align
[DFmode
] = align64
;
2566 /* Allow TImode in VSX register and set the VSX memory macros. */
2567 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2569 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2570 rs6000_vector_align
[TImode
] = align64
;
2573 /* TODO add SPE and paired floating point vector support. */
2575 /* Register class constraints for the constraints that depend on compile
2576 switches. When the VSX code was added, different constraints were added
2577 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2578 of the VSX registers are used. The register classes for scalar floating
2579 point types is set, based on whether we allow that type into the upper
2580 (Altivec) registers. GCC has register classes to target the Altivec
2581 registers for load/store operations, to select using a VSX memory
2582 operation instead of the traditional floating point operation. The
2585 d - Register class to use with traditional DFmode instructions.
2586 f - Register class to use with traditional SFmode instructions.
2587 v - Altivec register.
2588 wa - Any VSX register.
2589 wd - Preferred register class for V2DFmode.
2590 wf - Preferred register class for V4SFmode.
2591 wg - Float register for power6x move insns.
2592 wl - Float register if we can do 32-bit signed int loads.
2593 wm - VSX register for ISA 2.07 direct move operations.
2594 wr - GPR if 64-bit mode is permitted.
2595 ws - Register class to do ISA 2.06 DF operations.
2596 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2597 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2598 wt - VSX register for TImode in VSX registers.
2599 ww - Register class to do SF conversions in with VSX operations.
2600 wx - Float register if we can do 32-bit int stores.
2601 wy - Register class to do ISA 2.07 SF operations.
2602 wz - Float register if we can do 32-bit unsigned int loads. */
2604 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2605 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2607 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2608 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2612 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2613 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2614 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2616 if (TARGET_VSX_TIMODE
)
2617 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2619 if (TARGET_UPPER_REGS_DF
)
2621 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2622 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2625 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2628 /* Add conditional constraints based on various options, to allow us to
2629 collapse multiple insn patterns. */
2631 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2634 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2637 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2639 if (TARGET_DIRECT_MOVE
)
2640 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2642 if (TARGET_POWERPC64
)
2643 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2645 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
)
2647 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2648 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2649 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2651 else if (TARGET_P8_VECTOR
)
2653 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2654 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2656 else if (TARGET_VSX
)
2657 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2660 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2663 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2665 /* Set up the reload helper and direct move functions. */
2666 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2670 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2671 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2672 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2673 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2674 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2675 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2676 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2677 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2678 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2679 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2680 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2681 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2682 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2684 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2685 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2686 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2687 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2689 if (TARGET_P8_VECTOR
)
2691 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2692 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2693 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2694 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2696 if (TARGET_VSX_TIMODE
)
2698 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2699 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2701 if (TARGET_DIRECT_MOVE
)
2703 if (TARGET_POWERPC64
)
2705 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2706 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2707 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2708 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2709 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2710 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2711 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2712 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2714 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2715 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2716 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2717 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2718 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2719 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2720 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2721 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2725 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2726 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2727 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2733 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2734 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2735 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2736 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2737 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2738 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2739 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2740 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2741 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2742 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2743 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2744 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2745 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2747 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2748 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2749 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2750 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2752 if (TARGET_P8_VECTOR
)
2754 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2755 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2756 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2757 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2759 if (TARGET_VSX_TIMODE
)
2761 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2762 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2767 /* Precalculate HARD_REGNO_NREGS. */
2768 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2769 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2770 rs6000_hard_regno_nregs
[m
][r
]
2771 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2773 /* Precalculate HARD_REGNO_MODE_OK. */
2774 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2775 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2776 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2777 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2779 /* Precalculate CLASS_MAX_NREGS sizes. */
2780 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2784 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2785 reg_size
= UNITS_PER_VSX_WORD
;
2787 else if (c
== ALTIVEC_REGS
)
2788 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2790 else if (c
== FLOAT_REGS
)
2791 reg_size
= UNITS_PER_FP_WORD
;
2794 reg_size
= UNITS_PER_WORD
;
2796 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2798 int reg_size2
= reg_size
;
2800 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2801 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2802 && (m
== TDmode
|| m
== TFmode
))
2803 reg_size2
= UNITS_PER_FP_WORD
;
2805 rs6000_class_max_nregs
[m
][c
]
2806 = (GET_MODE_SIZE (m
) + reg_size2
- 1) / reg_size2
;
2810 if (TARGET_E500_DOUBLE
)
2811 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2813 /* Calculate which modes to automatically generate code to use a the
2814 reciprocal divide and square root instructions. In the future, possibly
2815 automatically generate the instructions even if the user did not specify
2816 -mrecip. The older machines double precision reciprocal sqrt estimate is
2817 not accurate enough. */
2818 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2820 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2822 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2823 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2824 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2825 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2826 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2828 if (TARGET_FRSQRTES
)
2829 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2831 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2832 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2833 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2834 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2835 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2837 if (rs6000_recip_control
)
2839 if (!flag_finite_math_only
)
2840 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2841 if (flag_trapping_math
)
2842 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2843 if (!flag_reciprocal_math
)
2844 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2845 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2847 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2848 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2849 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2851 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2852 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2853 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2855 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2856 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2857 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2859 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2860 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2861 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2863 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2864 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2865 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2867 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2868 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2869 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2871 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2872 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2873 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2875 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2876 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2877 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2881 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2882 legitimate address support to figure out the appropriate addressing to
2884 rs6000_setup_reg_addr_masks ();
2886 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2888 if (TARGET_DEBUG_REG
)
2889 rs6000_debug_reg_global ();
2891 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2893 "SImode variable mult cost = %d\n"
2894 "SImode constant mult cost = %d\n"
2895 "SImode short constant mult cost = %d\n"
2896 "DImode multipliciation cost = %d\n"
2897 "SImode division cost = %d\n"
2898 "DImode division cost = %d\n"
2899 "Simple fp operation cost = %d\n"
2900 "DFmode multiplication cost = %d\n"
2901 "SFmode division cost = %d\n"
2902 "DFmode division cost = %d\n"
2903 "cache line size = %d\n"
2904 "l1 cache size = %d\n"
2905 "l2 cache size = %d\n"
2906 "simultaneous prefetches = %d\n"
2909 rs6000_cost
->mulsi_const
,
2910 rs6000_cost
->mulsi_const9
,
2918 rs6000_cost
->cache_line_size
,
2919 rs6000_cost
->l1_cache_size
,
2920 rs6000_cost
->l2_cache_size
,
2921 rs6000_cost
->simultaneous_prefetches
);
2926 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2929 darwin_rs6000_override_options (void)
2931 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2933 rs6000_altivec_abi
= 1;
2934 TARGET_ALTIVEC_VRSAVE
= 1;
2935 rs6000_current_abi
= ABI_DARWIN
;
2937 if (DEFAULT_ABI
== ABI_DARWIN
2939 darwin_one_byte_bool
= 1;
2941 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2943 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2944 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2948 rs6000_default_long_calls
= 1;
2949 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2952 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2954 if (!flag_mkernel
&& !flag_apple_kext
2956 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2957 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2959 /* Unless the user (not the configurer) has explicitly overridden
2960 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2961 G4 unless targeting the kernel. */
2964 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2965 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2966 && ! global_options_set
.x_rs6000_cpu_index
)
2968 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2973 /* If not otherwise specified by a target, make 'long double' equivalent to
2976 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2977 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2980 /* Return the builtin mask of the various options used that could affect which
2981 builtins were used. In the past we used target_flags, but we've run out of
2982 bits, and some options like SPE and PAIRED are no longer in
2986 rs6000_builtin_mask_calculate (void)
2988 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2989 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2990 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2991 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2992 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2993 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2994 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2995 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2996 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2997 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
2998 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
2999 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3000 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0));
3003 /* Override command line options. Mostly we process the processor type and
3004 sometimes adjust other TARGET_ options. */
3007 rs6000_option_override_internal (bool global_init_p
)
3010 bool have_cpu
= false;
3012 /* The default cpu requested at configure time, if any. */
3013 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3015 HOST_WIDE_INT set_masks
;
3018 struct cl_target_option
*main_target_opt
3019 = ((global_init_p
|| target_option_default_node
== NULL
)
3020 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3022 /* Remember the explicit arguments. */
3024 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3026 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3027 library functions, so warn about it. The flag may be useful for
3028 performance studies from time to time though, so don't disable it
3030 if (global_options_set
.x_rs6000_alignment_flags
3031 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3032 && DEFAULT_ABI
== ABI_DARWIN
3034 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3035 " it is incompatible with the installed C and C++ libraries");
3037 /* Numerous experiment shows that IRA based loop pressure
3038 calculation works better for RTL loop invariant motion on targets
3039 with enough (>= 32) registers. It is an expensive optimization.
3040 So it is on only for peak performance. */
3041 if (optimize
>= 3 && global_init_p
)
3042 flag_ira_loop_pressure
= 1;
3044 /* Set the pointer size. */
3047 rs6000_pmode
= (int)DImode
;
3048 rs6000_pointer_size
= 64;
3052 rs6000_pmode
= (int)SImode
;
3053 rs6000_pointer_size
= 32;
3056 /* Some OSs don't support saving the high part of 64-bit registers on context
3057 switch. Other OSs don't support saving Altivec registers. On those OSs,
3058 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3059 if the user wants either, the user must explicitly specify them and we
3060 won't interfere with the user's specification. */
3062 set_masks
= POWERPC_MASKS
;
3063 #ifdef OS_MISSING_POWERPC64
3064 if (OS_MISSING_POWERPC64
)
3065 set_masks
&= ~OPTION_MASK_POWERPC64
;
3067 #ifdef OS_MISSING_ALTIVEC
3068 if (OS_MISSING_ALTIVEC
)
3069 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3072 /* Don't override by the processor default if given explicitly. */
3073 set_masks
&= ~rs6000_isa_flags_explicit
;
3075 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3076 the cpu in a target attribute or pragma, but did not specify a tuning
3077 option, use the cpu for the tuning option rather than the option specified
3078 with -mtune on the command line. Process a '--with-cpu' configuration
3079 request as an implicit --cpu. */
3080 if (rs6000_cpu_index
>= 0)
3082 cpu_index
= rs6000_cpu_index
;
3085 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3087 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3090 else if (implicit_cpu
)
3092 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3097 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
3098 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3102 gcc_assert (cpu_index
>= 0);
3104 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3105 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3106 with those from the cpu, except for options that were explicitly set. If
3107 we don't have a cpu, do not override the target bits set in
3111 rs6000_isa_flags
&= ~set_masks
;
3112 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3116 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3117 & ~rs6000_isa_flags_explicit
);
3119 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3120 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3121 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3122 to using rs6000_isa_flags, we need to do the initialization here. */
3124 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
3126 if (rs6000_tune_index
>= 0)
3127 tune_index
= rs6000_tune_index
;
3129 rs6000_tune_index
= tune_index
= cpu_index
;
3133 enum processor_type tune_proc
3134 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3137 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3138 if (processor_target_table
[i
].processor
== tune_proc
)
3140 rs6000_tune_index
= tune_index
= i
;
3145 gcc_assert (tune_index
>= 0);
3146 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3148 /* Pick defaults for SPE related control flags. Do this early to make sure
3149 that the TARGET_ macros are representative ASAP. */
3151 int spe_capable_cpu
=
3152 (rs6000_cpu
== PROCESSOR_PPC8540
3153 || rs6000_cpu
== PROCESSOR_PPC8548
);
3155 if (!global_options_set
.x_rs6000_spe_abi
)
3156 rs6000_spe_abi
= spe_capable_cpu
;
3158 if (!global_options_set
.x_rs6000_spe
)
3159 rs6000_spe
= spe_capable_cpu
;
3161 if (!global_options_set
.x_rs6000_float_gprs
)
3163 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3164 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3168 if (global_options_set
.x_rs6000_spe_abi
3171 error ("not configured for SPE ABI");
3173 if (global_options_set
.x_rs6000_spe
3176 error ("not configured for SPE instruction set");
3178 if (main_target_opt
!= NULL
3179 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3180 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3181 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3182 error ("target attribute or pragma changes SPE ABI");
3184 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3185 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3186 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3189 error ("AltiVec not supported in this target");
3191 error ("SPE not supported in this target");
3193 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3196 error ("SPE not supported in this target");
3199 /* Disable Cell microcode if we are optimizing for the Cell
3200 and not optimizing for size. */
3201 if (rs6000_gen_cell_microcode
== -1)
3202 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3205 /* If we are optimizing big endian systems for space and it's OK to
3206 use instructions that would be microcoded on the Cell, use the
3207 load/store multiple and string instructions. */
3208 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3209 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3210 | OPTION_MASK_STRING
);
3212 /* Don't allow -mmultiple or -mstring on little endian systems
3213 unless the cpu is a 750, because the hardware doesn't support the
3214 instructions used in little endian mode, and causes an alignment
3215 trap. The 750 does not cause an alignment trap (except when the
3216 target is unaligned). */
3218 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3220 if (TARGET_MULTIPLE
)
3222 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3223 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3224 warning (0, "-mmultiple is not supported on little endian systems");
3229 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3230 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3231 warning (0, "-mstring is not supported on little endian systems");
3235 /* If little-endian, default to -mstrict-align on older processors.
3236 Testing for htm matches power8 and later. */
3237 if (!BYTES_BIG_ENDIAN
3238 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3239 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3241 /* Add some warnings for VSX. */
3244 const char *msg
= NULL
;
3245 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3246 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3248 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3249 msg
= N_("-mvsx requires hardware floating point");
3252 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3253 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3256 else if (TARGET_PAIRED_FLOAT
)
3257 msg
= N_("-mvsx and -mpaired are incompatible");
3258 else if (TARGET_AVOID_XFORM
> 0)
3259 msg
= N_("-mvsx needs indexed addressing");
3260 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3261 & OPTION_MASK_ALTIVEC
))
3263 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3264 msg
= N_("-mvsx and -mno-altivec are incompatible");
3266 msg
= N_("-mno-altivec disables vsx");
3272 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3273 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3277 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3278 the -mcpu setting to enable options that conflict. */
3279 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3280 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3281 | OPTION_MASK_ALTIVEC
3282 | OPTION_MASK_VSX
)) != 0)
3283 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3284 | OPTION_MASK_DIRECT_MOVE
)
3285 & ~rs6000_isa_flags_explicit
);
3287 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3288 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3290 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3291 unless the user explicitly used the -mno-<option> to disable the code. */
3292 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3293 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3294 else if (TARGET_VSX
)
3295 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3296 else if (TARGET_POPCNTD
)
3297 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3298 else if (TARGET_DFP
)
3299 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3300 else if (TARGET_CMPB
)
3301 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3302 else if (TARGET_FPRND
)
3303 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3304 else if (TARGET_POPCNTB
)
3305 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3306 else if (TARGET_ALTIVEC
)
3307 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3309 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3311 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3312 error ("-mcrypto requires -maltivec");
3313 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3316 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3318 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3319 error ("-mdirect-move requires -mvsx");
3320 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3323 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3325 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3326 error ("-mpower8-vector requires -maltivec");
3327 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3330 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3332 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3333 error ("-mpower8-vector requires -mvsx");
3334 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3337 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3339 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3340 error ("-mvsx-timode requires -mvsx");
3341 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3344 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3345 silently turn off quad memory mode. */
3346 if (TARGET_QUAD_MEMORY
&& !TARGET_POWERPC64
)
3348 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3349 warning (0, N_("-mquad-memory requires 64-bit mode"));
3351 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3354 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3355 generating power8 instructions. */
3356 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3357 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3358 & OPTION_MASK_P8_FUSION
);
3360 /* Power8 does not fuse sign extended loads with the addis. If we are
3361 optimizing at high levels for speed, convert a sign extended load into a
3362 zero extending load, and an explicit sign extension. */
3363 if (TARGET_P8_FUSION
3364 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3365 && optimize_function_for_speed_p (cfun
)
3367 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3369 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3370 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3372 /* E500mc does "better" if we inline more aggressively. Respect the
3373 user's opinion, though. */
3374 if (rs6000_block_move_inline_limit
== 0
3375 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3376 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3377 || rs6000_cpu
== PROCESSOR_PPCE5500
3378 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3379 rs6000_block_move_inline_limit
= 128;
3381 /* store_one_arg depends on expand_block_move to handle at least the
3382 size of reg_parm_stack_space. */
3383 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3384 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3388 /* If the appropriate debug option is enabled, replace the target hooks
3389 with debug versions that call the real version and then prints
3390 debugging information. */
3391 if (TARGET_DEBUG_COST
)
3393 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3394 targetm
.address_cost
= rs6000_debug_address_cost
;
3395 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3398 if (TARGET_DEBUG_ADDR
)
3400 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3401 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3402 rs6000_secondary_reload_class_ptr
3403 = rs6000_debug_secondary_reload_class
;
3404 rs6000_secondary_memory_needed_ptr
3405 = rs6000_debug_secondary_memory_needed
;
3406 rs6000_cannot_change_mode_class_ptr
3407 = rs6000_debug_cannot_change_mode_class
;
3408 rs6000_preferred_reload_class_ptr
3409 = rs6000_debug_preferred_reload_class
;
3410 rs6000_legitimize_reload_address_ptr
3411 = rs6000_debug_legitimize_reload_address
;
3412 rs6000_mode_dependent_address_ptr
3413 = rs6000_debug_mode_dependent_address
;
3416 if (rs6000_veclibabi_name
)
3418 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3419 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3422 error ("unknown vectorization library ABI type (%s) for "
3423 "-mveclibabi= switch", rs6000_veclibabi_name
);
3429 if (!global_options_set
.x_rs6000_long_double_type_size
)
3431 if (main_target_opt
!= NULL
3432 && (main_target_opt
->x_rs6000_long_double_type_size
3433 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3434 error ("target attribute or pragma changes long double size");
3436 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3439 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3440 if (!global_options_set
.x_rs6000_ieeequad
)
3441 rs6000_ieeequad
= 1;
3444 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3445 target attribute or pragma which automatically enables both options,
3446 unless the altivec ABI was set. This is set by default for 64-bit, but
3448 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3449 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3450 & ~rs6000_isa_flags_explicit
);
3452 /* Enable Altivec ABI for AIX -maltivec. */
3453 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3455 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3456 error ("target attribute or pragma changes AltiVec ABI");
3458 rs6000_altivec_abi
= 1;
3461 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3462 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3463 be explicitly overridden in either case. */
3466 if (!global_options_set
.x_rs6000_altivec_abi
3467 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3469 if (main_target_opt
!= NULL
&&
3470 !main_target_opt
->x_rs6000_altivec_abi
)
3471 error ("target attribute or pragma changes AltiVec ABI");
3473 rs6000_altivec_abi
= 1;
3477 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3478 So far, the only darwin64 targets are also MACH-O. */
3480 && DEFAULT_ABI
== ABI_DARWIN
3483 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3484 error ("target attribute or pragma changes darwin64 ABI");
3487 rs6000_darwin64_abi
= 1;
3488 /* Default to natural alignment, for better performance. */
3489 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3493 /* Place FP constants in the constant pool instead of TOC
3494 if section anchors enabled. */
3495 if (flag_section_anchors
3496 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3497 TARGET_NO_FP_IN_TOC
= 1;
3499 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3500 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3502 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3503 SUBTARGET_OVERRIDE_OPTIONS
;
3505 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3506 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3508 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3509 SUB3TARGET_OVERRIDE_OPTIONS
;
3512 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3513 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3515 /* For the E500 family of cores, reset the single/double FP flags to let us
3516 check that they remain constant across attributes or pragmas. Also,
3517 clear a possible request for string instructions, not supported and which
3518 we might have silently queried above for -Os.
3520 For other families, clear ISEL in case it was set implicitly.
3525 case PROCESSOR_PPC8540
:
3526 case PROCESSOR_PPC8548
:
3527 case PROCESSOR_PPCE500MC
:
3528 case PROCESSOR_PPCE500MC64
:
3529 case PROCESSOR_PPCE5500
:
3530 case PROCESSOR_PPCE6500
:
3532 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3533 rs6000_double_float
= TARGET_E500_DOUBLE
;
3535 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3541 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3542 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3547 if (main_target_opt
)
3549 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3550 error ("target attribute or pragma changes single precision floating "
3552 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3553 error ("target attribute or pragma changes double precision floating "
3557 /* Detect invalid option combinations with E500. */
3560 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3561 && rs6000_cpu
!= PROCESSOR_POWER5
3562 && rs6000_cpu
!= PROCESSOR_POWER6
3563 && rs6000_cpu
!= PROCESSOR_POWER7
3564 && rs6000_cpu
!= PROCESSOR_POWER8
3565 && rs6000_cpu
!= PROCESSOR_PPCA2
3566 && rs6000_cpu
!= PROCESSOR_CELL
3567 && rs6000_cpu
!= PROCESSOR_PPC476
);
3568 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3569 || rs6000_cpu
== PROCESSOR_POWER5
3570 || rs6000_cpu
== PROCESSOR_POWER7
3571 || rs6000_cpu
== PROCESSOR_POWER8
);
3572 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3573 || rs6000_cpu
== PROCESSOR_POWER5
3574 || rs6000_cpu
== PROCESSOR_POWER6
3575 || rs6000_cpu
== PROCESSOR_POWER7
3576 || rs6000_cpu
== PROCESSOR_POWER8
3577 || rs6000_cpu
== PROCESSOR_PPCE500MC
3578 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3579 || rs6000_cpu
== PROCESSOR_PPCE5500
3580 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3582 /* Allow debug switches to override the above settings. These are set to -1
3583 in rs6000.opt to indicate the user hasn't directly set the switch. */
3584 if (TARGET_ALWAYS_HINT
>= 0)
3585 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3587 if (TARGET_SCHED_GROUPS
>= 0)
3588 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3590 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3591 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3593 rs6000_sched_restricted_insns_priority
3594 = (rs6000_sched_groups
? 1 : 0);
3596 /* Handle -msched-costly-dep option. */
3597 rs6000_sched_costly_dep
3598 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3600 if (rs6000_sched_costly_dep_str
)
3602 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3603 rs6000_sched_costly_dep
= no_dep_costly
;
3604 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3605 rs6000_sched_costly_dep
= all_deps_costly
;
3606 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3607 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3608 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3609 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3611 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3612 atoi (rs6000_sched_costly_dep_str
));
3615 /* Handle -minsert-sched-nops option. */
3616 rs6000_sched_insert_nops
3617 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3619 if (rs6000_sched_insert_nops_str
)
3621 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3622 rs6000_sched_insert_nops
= sched_finish_none
;
3623 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3624 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3625 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3626 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3628 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3629 atoi (rs6000_sched_insert_nops_str
));
3634 #ifdef TARGET_REGNAMES
3635 /* If the user desires alternate register names, copy in the
3636 alternate names now. */
3637 if (TARGET_REGNAMES
)
3638 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3641 /* Set aix_struct_return last, after the ABI is determined.
3642 If -maix-struct-return or -msvr4-struct-return was explicitly
3643 used, don't override with the ABI default. */
3644 if (!global_options_set
.x_aix_struct_return
)
3645 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3648 /* IBM XL compiler defaults to unsigned bitfields. */
3649 if (TARGET_XL_COMPAT
)
3650 flag_signed_bitfields
= 0;
3653 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3654 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3657 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3659 /* We can only guarantee the availability of DI pseudo-ops when
3660 assembling for 64-bit targets. */
3663 targetm
.asm_out
.aligned_op
.di
= NULL
;
3664 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3668 /* Set branch target alignment, if not optimizing for size. */
3671 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3672 aligned 8byte to avoid misprediction by the branch predictor. */
3673 if (rs6000_cpu
== PROCESSOR_TITAN
3674 || rs6000_cpu
== PROCESSOR_CELL
)
3676 if (align_functions
<= 0)
3677 align_functions
= 8;
3678 if (align_jumps
<= 0)
3680 if (align_loops
<= 0)
3683 if (rs6000_align_branch_targets
)
3685 if (align_functions
<= 0)
3686 align_functions
= 16;
3687 if (align_jumps
<= 0)
3689 if (align_loops
<= 0)
3691 can_override_loop_align
= 1;
3695 if (align_jumps_max_skip
<= 0)
3696 align_jumps_max_skip
= 15;
3697 if (align_loops_max_skip
<= 0)
3698 align_loops_max_skip
= 15;
3701 /* Arrange to save and restore machine status around nested functions. */
3702 init_machine_status
= rs6000_init_machine_status
;
3704 /* We should always be splitting complex arguments, but we can't break
3705 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3706 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
3707 targetm
.calls
.split_complex_arg
= NULL
;
3710 /* Initialize rs6000_cost with the appropriate target costs. */
3712 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3716 case PROCESSOR_RS64A
:
3717 rs6000_cost
= &rs64a_cost
;
3720 case PROCESSOR_MPCCORE
:
3721 rs6000_cost
= &mpccore_cost
;
3724 case PROCESSOR_PPC403
:
3725 rs6000_cost
= &ppc403_cost
;
3728 case PROCESSOR_PPC405
:
3729 rs6000_cost
= &ppc405_cost
;
3732 case PROCESSOR_PPC440
:
3733 rs6000_cost
= &ppc440_cost
;
3736 case PROCESSOR_PPC476
:
3737 rs6000_cost
= &ppc476_cost
;
3740 case PROCESSOR_PPC601
:
3741 rs6000_cost
= &ppc601_cost
;
3744 case PROCESSOR_PPC603
:
3745 rs6000_cost
= &ppc603_cost
;
3748 case PROCESSOR_PPC604
:
3749 rs6000_cost
= &ppc604_cost
;
3752 case PROCESSOR_PPC604e
:
3753 rs6000_cost
= &ppc604e_cost
;
3756 case PROCESSOR_PPC620
:
3757 rs6000_cost
= &ppc620_cost
;
3760 case PROCESSOR_PPC630
:
3761 rs6000_cost
= &ppc630_cost
;
3764 case PROCESSOR_CELL
:
3765 rs6000_cost
= &ppccell_cost
;
3768 case PROCESSOR_PPC750
:
3769 case PROCESSOR_PPC7400
:
3770 rs6000_cost
= &ppc750_cost
;
3773 case PROCESSOR_PPC7450
:
3774 rs6000_cost
= &ppc7450_cost
;
3777 case PROCESSOR_PPC8540
:
3778 case PROCESSOR_PPC8548
:
3779 rs6000_cost
= &ppc8540_cost
;
3782 case PROCESSOR_PPCE300C2
:
3783 case PROCESSOR_PPCE300C3
:
3784 rs6000_cost
= &ppce300c2c3_cost
;
3787 case PROCESSOR_PPCE500MC
:
3788 rs6000_cost
= &ppce500mc_cost
;
3791 case PROCESSOR_PPCE500MC64
:
3792 rs6000_cost
= &ppce500mc64_cost
;
3795 case PROCESSOR_PPCE5500
:
3796 rs6000_cost
= &ppce5500_cost
;
3799 case PROCESSOR_PPCE6500
:
3800 rs6000_cost
= &ppce6500_cost
;
3803 case PROCESSOR_TITAN
:
3804 rs6000_cost
= &titan_cost
;
3807 case PROCESSOR_POWER4
:
3808 case PROCESSOR_POWER5
:
3809 rs6000_cost
= &power4_cost
;
3812 case PROCESSOR_POWER6
:
3813 rs6000_cost
= &power6_cost
;
3816 case PROCESSOR_POWER7
:
3817 rs6000_cost
= &power7_cost
;
3820 case PROCESSOR_POWER8
:
3821 rs6000_cost
= &power8_cost
;
3824 case PROCESSOR_PPCA2
:
3825 rs6000_cost
= &ppca2_cost
;
3834 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3835 rs6000_cost
->simultaneous_prefetches
,
3836 global_options
.x_param_values
,
3837 global_options_set
.x_param_values
);
3838 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3839 global_options
.x_param_values
,
3840 global_options_set
.x_param_values
);
3841 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3842 rs6000_cost
->cache_line_size
,
3843 global_options
.x_param_values
,
3844 global_options_set
.x_param_values
);
3845 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3846 global_options
.x_param_values
,
3847 global_options_set
.x_param_values
);
3849 /* Increase loop peeling limits based on performance analysis. */
3850 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3851 global_options
.x_param_values
,
3852 global_options_set
.x_param_values
);
3853 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3854 global_options
.x_param_values
,
3855 global_options_set
.x_param_values
);
3857 /* If using typedef char *va_list, signal that
3858 __builtin_va_start (&ap, 0) can be optimized to
3859 ap = __builtin_next_arg (0). */
3860 if (DEFAULT_ABI
!= ABI_V4
)
3861 targetm
.expand_builtin_va_start
= NULL
;
3864 /* Set up single/double float flags.
3865 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3866 then set both flags. */
3867 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3868 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3869 rs6000_single_float
= rs6000_double_float
= 1;
3871 /* If not explicitly specified via option, decide whether to generate indexed
3872 load/store instructions. */
3873 if (TARGET_AVOID_XFORM
== -1)
3874 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3875 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3876 need indexed accesses and the type used is the scalar type of the element
3877 being loaded or stored. */
3878 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3879 && !TARGET_ALTIVEC
);
3881 /* Set the -mrecip options. */
3882 if (rs6000_recip_name
)
3884 char *p
= ASTRDUP (rs6000_recip_name
);
3886 unsigned int mask
, i
;
3889 while ((q
= strtok (p
, ",")) != NULL
)
3900 if (!strcmp (q
, "default"))
3901 mask
= ((TARGET_RECIP_PRECISION
)
3902 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3905 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3906 if (!strcmp (q
, recip_options
[i
].string
))
3908 mask
= recip_options
[i
].mask
;
3912 if (i
== ARRAY_SIZE (recip_options
))
3914 error ("unknown option for -mrecip=%s", q
);
3922 rs6000_recip_control
&= ~mask
;
3924 rs6000_recip_control
|= mask
;
3928 /* Set the builtin mask of the various options used that could affect which
3929 builtins were used. In the past we used target_flags, but we've run out
3930 of bits, and some options like SPE and PAIRED are no longer in
3932 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3933 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3936 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3937 rs6000_builtin_mask
);
3938 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3941 /* Initialize all of the registers. */
3942 rs6000_init_hard_regno_mode_ok (global_init_p
);
3944 /* Save the initial options in case the user does function specific options */
3946 target_option_default_node
= target_option_current_node
3947 = build_target_option_node (&global_options
);
3949 /* If not explicitly specified via option, decide whether to generate the
3950 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3951 if (TARGET_LINK_STACK
== -1)
3952 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3957 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3958 define the target cpu type. */
3961 rs6000_option_override (void)
3963 (void) rs6000_option_override_internal (true);
3967 /* Implement targetm.vectorize.builtin_mask_for_load. */
3969 rs6000_builtin_mask_for_load (void)
3971 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3972 return altivec_builtin_mask_for_load
;
3977 /* Implement LOOP_ALIGN. */
3979 rs6000_loop_align (rtx label
)
3984 /* Don't override loop alignment if -falign-loops was specified. */
3985 if (!can_override_loop_align
)
3986 return align_loops_log
;
3988 bb
= BLOCK_FOR_INSN (label
);
3989 ninsns
= num_loop_insns(bb
->loop_father
);
3991 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3992 if (ninsns
> 4 && ninsns
<= 8
3993 && (rs6000_cpu
== PROCESSOR_POWER4
3994 || rs6000_cpu
== PROCESSOR_POWER5
3995 || rs6000_cpu
== PROCESSOR_POWER6
3996 || rs6000_cpu
== PROCESSOR_POWER7
3997 || rs6000_cpu
== PROCESSOR_POWER8
))
4000 return align_loops_log
;
4003 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
4005 rs6000_loop_align_max_skip (rtx label
)
4007 return (1 << rs6000_loop_align (label
)) - 1;
4010 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4011 after applying N number of iterations. This routine does not determine
4012 how may iterations are required to reach desired alignment. */
4015 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4022 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4025 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4035 /* Assuming that all other types are naturally aligned. CHECKME! */
4040 /* Return true if the vector misalignment factor is supported by the
4043 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
4050 /* Return if movmisalign pattern is not supported for this mode. */
4051 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4054 if (misalignment
== -1)
4056 /* Misalignment factor is unknown at compile time but we know
4057 it's word aligned. */
4058 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4060 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4062 if (element_size
== 64 || element_size
== 32)
4069 /* VSX supports word-aligned vector. */
4070 if (misalignment
% 4 == 0)
4076 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4078 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4079 tree vectype
, int misalign
)
4084 switch (type_of_cost
)
4094 case cond_branch_not_taken
:
4103 case vec_promote_demote
:
4109 case cond_branch_taken
:
4112 case unaligned_load
:
4113 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4115 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4117 /* Double word aligned. */
4125 /* Double word aligned. */
4129 /* Unknown misalignment. */
4142 /* Misaligned loads are not supported. */
4147 case unaligned_store
:
4148 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4150 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4152 /* Double word aligned. */
4160 /* Double word aligned. */
4164 /* Unknown misalignment. */
4177 /* Misaligned stores are not supported. */
4183 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4184 elem_type
= TREE_TYPE (vectype
);
4185 /* 32-bit vectors loaded into registers are stored as double
4186 precision, so we need n/2 converts in addition to the usual
4187 n/2 merges to construct a vector of short floats from them. */
4188 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4189 && TYPE_PRECISION (elem_type
) == 32)
4190 return elements
+ 1;
4192 return elements
/ 2 + 1;
4199 /* Implement targetm.vectorize.preferred_simd_mode. */
4201 static enum machine_mode
4202 rs6000_preferred_simd_mode (enum machine_mode mode
)
4211 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4235 if (TARGET_PAIRED_FLOAT
4241 typedef struct _rs6000_cost_data
4243 struct loop
*loop_info
;
4247 /* Test for likely overcommitment of vector hardware resources. If a
4248 loop iteration is relatively large, and too large a percentage of
4249 instructions in the loop are vectorized, the cost model may not
4250 adequately reflect delays from unavailable vector resources.
4251 Penalize the loop body cost for this case. */
4254 rs6000_density_test (rs6000_cost_data
*data
)
4256 const int DENSITY_PCT_THRESHOLD
= 85;
4257 const int DENSITY_SIZE_THRESHOLD
= 70;
4258 const int DENSITY_PENALTY
= 10;
4259 struct loop
*loop
= data
->loop_info
;
4260 basic_block
*bbs
= get_loop_body (loop
);
4261 int nbbs
= loop
->num_nodes
;
4262 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4265 for (i
= 0; i
< nbbs
; i
++)
4267 basic_block bb
= bbs
[i
];
4268 gimple_stmt_iterator gsi
;
4270 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4272 gimple stmt
= gsi_stmt (gsi
);
4273 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4275 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4276 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4282 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4284 if (density_pct
> DENSITY_PCT_THRESHOLD
4285 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4287 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4288 if (dump_enabled_p ())
4289 dump_printf_loc (MSG_NOTE
, vect_location
,
4290 "density %d%%, cost %d exceeds threshold, penalizing "
4291 "loop body cost by %d%%", density_pct
,
4292 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4296 /* Implement targetm.vectorize.init_cost. */
4299 rs6000_init_cost (struct loop
*loop_info
)
4301 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4302 data
->loop_info
= loop_info
;
4303 data
->cost
[vect_prologue
] = 0;
4304 data
->cost
[vect_body
] = 0;
4305 data
->cost
[vect_epilogue
] = 0;
4309 /* Implement targetm.vectorize.add_stmt_cost. */
4312 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4313 struct _stmt_vec_info
*stmt_info
, int misalign
,
4314 enum vect_cost_model_location where
)
4316 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4317 unsigned retval
= 0;
4319 if (flag_vect_cost_model
)
4321 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4322 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4324 /* Statements in an inner loop relative to the loop being
4325 vectorized are weighted more heavily. The value here is
4326 arbitrary and could potentially be improved with analysis. */
4327 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4328 count
*= 50; /* FIXME. */
4330 retval
= (unsigned) (count
* stmt_cost
);
4331 cost_data
->cost
[where
] += retval
;
4337 /* Implement targetm.vectorize.finish_cost. */
4340 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4341 unsigned *body_cost
, unsigned *epilogue_cost
)
4343 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4345 if (cost_data
->loop_info
)
4346 rs6000_density_test (cost_data
);
4348 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4349 *body_cost
= cost_data
->cost
[vect_body
];
4350 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4353 /* Implement targetm.vectorize.destroy_cost_data. */
4356 rs6000_destroy_cost_data (void *data
)
4361 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4362 library with vectorized intrinsics. */
4365 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4368 const char *suffix
= NULL
;
4369 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4372 enum machine_mode el_mode
, in_mode
;
4375 /* Libmass is suitable for unsafe math only as it does not correctly support
4376 parts of IEEE with the required precision such as denormals. Only support
4377 it if we have VSX to use the simd d2 or f4 functions.
4378 XXX: Add variable length support. */
4379 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4382 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4383 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4384 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4385 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4386 if (el_mode
!= in_mode
4390 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4392 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4395 case BUILT_IN_ATAN2
:
4396 case BUILT_IN_HYPOT
:
4402 case BUILT_IN_ACOSH
:
4404 case BUILT_IN_ASINH
:
4406 case BUILT_IN_ATANH
:
4414 case BUILT_IN_EXPM1
:
4415 case BUILT_IN_LGAMMA
:
4416 case BUILT_IN_LOG10
:
4417 case BUILT_IN_LOG1P
:
4425 bdecl
= builtin_decl_implicit (fn
);
4426 suffix
= "d2"; /* pow -> powd2 */
4427 if (el_mode
!= DFmode
4433 case BUILT_IN_ATAN2F
:
4434 case BUILT_IN_HYPOTF
:
4439 case BUILT_IN_ACOSF
:
4440 case BUILT_IN_ACOSHF
:
4441 case BUILT_IN_ASINF
:
4442 case BUILT_IN_ASINHF
:
4443 case BUILT_IN_ATANF
:
4444 case BUILT_IN_ATANHF
:
4445 case BUILT_IN_CBRTF
:
4447 case BUILT_IN_COSHF
:
4449 case BUILT_IN_ERFCF
:
4450 case BUILT_IN_EXP2F
:
4452 case BUILT_IN_EXPM1F
:
4453 case BUILT_IN_LGAMMAF
:
4454 case BUILT_IN_LOG10F
:
4455 case BUILT_IN_LOG1PF
:
4456 case BUILT_IN_LOG2F
:
4459 case BUILT_IN_SINHF
:
4460 case BUILT_IN_SQRTF
:
4462 case BUILT_IN_TANHF
:
4463 bdecl
= builtin_decl_implicit (fn
);
4464 suffix
= "4"; /* powf -> powf4 */
4465 if (el_mode
!= SFmode
4478 gcc_assert (suffix
!= NULL
);
4479 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4483 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4484 strcat (name
, suffix
);
4487 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4488 else if (n_args
== 2)
4489 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4493 /* Build a function declaration for the vectorized function. */
4494 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4495 FUNCTION_DECL
, get_identifier (name
), fntype
);
4496 TREE_PUBLIC (new_fndecl
) = 1;
4497 DECL_EXTERNAL (new_fndecl
) = 1;
4498 DECL_IS_NOVOPS (new_fndecl
) = 1;
4499 TREE_READONLY (new_fndecl
) = 1;
4504 /* Returns a function decl for a vectorized version of the builtin function
4505 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4506 if it is not available. */
4509 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4512 enum machine_mode in_mode
, out_mode
;
4515 if (TARGET_DEBUG_BUILTIN
)
4516 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4517 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4518 GET_MODE_NAME (TYPE_MODE (type_out
)),
4519 GET_MODE_NAME (TYPE_MODE (type_in
)));
4521 if (TREE_CODE (type_out
) != VECTOR_TYPE
4522 || TREE_CODE (type_in
) != VECTOR_TYPE
4523 || !TARGET_VECTORIZE_BUILTINS
)
4526 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4527 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4528 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4529 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4531 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4533 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4536 case BUILT_IN_CLZIMAX
:
4537 case BUILT_IN_CLZLL
:
4540 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4542 if (out_mode
== QImode
&& out_n
== 16)
4543 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4544 else if (out_mode
== HImode
&& out_n
== 8)
4545 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4546 else if (out_mode
== SImode
&& out_n
== 4)
4547 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4548 else if (out_mode
== DImode
&& out_n
== 2)
4549 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4552 case BUILT_IN_COPYSIGN
:
4553 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4554 && out_mode
== DFmode
&& out_n
== 2
4555 && in_mode
== DFmode
&& in_n
== 2)
4556 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4558 case BUILT_IN_COPYSIGNF
:
4559 if (out_mode
!= SFmode
|| out_n
!= 4
4560 || in_mode
!= SFmode
|| in_n
!= 4)
4562 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4563 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4564 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4565 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4567 case BUILT_IN_POPCOUNTIMAX
:
4568 case BUILT_IN_POPCOUNTLL
:
4569 case BUILT_IN_POPCOUNTL
:
4570 case BUILT_IN_POPCOUNT
:
4571 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4573 if (out_mode
== QImode
&& out_n
== 16)
4574 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4575 else if (out_mode
== HImode
&& out_n
== 8)
4576 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4577 else if (out_mode
== SImode
&& out_n
== 4)
4578 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4579 else if (out_mode
== DImode
&& out_n
== 2)
4580 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4584 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4585 && out_mode
== DFmode
&& out_n
== 2
4586 && in_mode
== DFmode
&& in_n
== 2)
4587 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4589 case BUILT_IN_SQRTF
:
4590 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4591 && out_mode
== SFmode
&& out_n
== 4
4592 && in_mode
== SFmode
&& in_n
== 4)
4593 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4596 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4597 && out_mode
== DFmode
&& out_n
== 2
4598 && in_mode
== DFmode
&& in_n
== 2)
4599 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4601 case BUILT_IN_CEILF
:
4602 if (out_mode
!= SFmode
|| out_n
!= 4
4603 || in_mode
!= SFmode
|| in_n
!= 4)
4605 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4606 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4607 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4608 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4610 case BUILT_IN_FLOOR
:
4611 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4612 && out_mode
== DFmode
&& out_n
== 2
4613 && in_mode
== DFmode
&& in_n
== 2)
4614 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4616 case BUILT_IN_FLOORF
:
4617 if (out_mode
!= SFmode
|| out_n
!= 4
4618 || in_mode
!= SFmode
|| in_n
!= 4)
4620 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4621 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4622 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4623 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4626 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4627 && out_mode
== DFmode
&& out_n
== 2
4628 && in_mode
== DFmode
&& in_n
== 2)
4629 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4632 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4633 && out_mode
== SFmode
&& out_n
== 4
4634 && in_mode
== SFmode
&& in_n
== 4)
4635 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4636 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4637 && out_mode
== SFmode
&& out_n
== 4
4638 && in_mode
== SFmode
&& in_n
== 4)
4639 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4641 case BUILT_IN_TRUNC
:
4642 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4643 && out_mode
== DFmode
&& out_n
== 2
4644 && in_mode
== DFmode
&& in_n
== 2)
4645 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4647 case BUILT_IN_TRUNCF
:
4648 if (out_mode
!= SFmode
|| out_n
!= 4
4649 || in_mode
!= SFmode
|| in_n
!= 4)
4651 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4652 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4653 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4654 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4656 case BUILT_IN_NEARBYINT
:
4657 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4658 && flag_unsafe_math_optimizations
4659 && out_mode
== DFmode
&& out_n
== 2
4660 && in_mode
== DFmode
&& in_n
== 2)
4661 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4663 case BUILT_IN_NEARBYINTF
:
4664 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4665 && flag_unsafe_math_optimizations
4666 && out_mode
== SFmode
&& out_n
== 4
4667 && in_mode
== SFmode
&& in_n
== 4)
4668 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4671 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4672 && !flag_trapping_math
4673 && out_mode
== DFmode
&& out_n
== 2
4674 && in_mode
== DFmode
&& in_n
== 2)
4675 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4677 case BUILT_IN_RINTF
:
4678 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4679 && !flag_trapping_math
4680 && out_mode
== SFmode
&& out_n
== 4
4681 && in_mode
== SFmode
&& in_n
== 4)
4682 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4689 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4691 enum rs6000_builtins fn
4692 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4695 case RS6000_BUILTIN_RSQRTF
:
4696 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4697 && out_mode
== SFmode
&& out_n
== 4
4698 && in_mode
== SFmode
&& in_n
== 4)
4699 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4701 case RS6000_BUILTIN_RSQRT
:
4702 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4703 && out_mode
== DFmode
&& out_n
== 2
4704 && in_mode
== DFmode
&& in_n
== 2)
4705 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4707 case RS6000_BUILTIN_RECIPF
:
4708 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4709 && out_mode
== SFmode
&& out_n
== 4
4710 && in_mode
== SFmode
&& in_n
== 4)
4711 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4713 case RS6000_BUILTIN_RECIP
:
4714 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4715 && out_mode
== DFmode
&& out_n
== 2
4716 && in_mode
== DFmode
&& in_n
== 2)
4717 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4724 /* Generate calls to libmass if appropriate. */
4725 if (rs6000_veclib_handler
)
4726 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4731 /* Default CPU string for rs6000*_file_start functions. */
4732 static const char *rs6000_default_cpu
;
4734 /* Do anything needed at the start of the asm file. */
4737 rs6000_file_start (void)
4740 const char *start
= buffer
;
4741 FILE *file
= asm_out_file
;
4743 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4745 default_file_start ();
4747 if (flag_verbose_asm
)
4749 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4751 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4753 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4757 if (global_options_set
.x_rs6000_cpu_index
)
4759 fprintf (file
, "%s -mcpu=%s", start
,
4760 processor_target_table
[rs6000_cpu_index
].name
);
4764 if (global_options_set
.x_rs6000_tune_index
)
4766 fprintf (file
, "%s -mtune=%s", start
,
4767 processor_target_table
[rs6000_tune_index
].name
);
4771 if (PPC405_ERRATUM77
)
4773 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4777 #ifdef USING_ELFOS_H
4778 switch (rs6000_sdata
)
4780 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4781 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4782 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4783 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4786 if (rs6000_sdata
&& g_switch_value
)
4788 fprintf (file
, "%s -G %d", start
,
4798 if (DEFAULT_ABI
== ABI_ELFv2
)
4799 fprintf (file
, "\t.abiversion 2\n");
4801 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
4802 || (TARGET_ELF
&& flag_pic
== 2))
4804 switch_to_section (toc_section
);
4805 switch_to_section (text_section
);
4810 /* Return nonzero if this function is known to have a null epilogue. */
4813 direct_return (void)
4815 if (reload_completed
)
4817 rs6000_stack_t
*info
= rs6000_stack_info ();
4819 if (info
->first_gp_reg_save
== 32
4820 && info
->first_fp_reg_save
== 64
4821 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4822 && ! info
->lr_save_p
4823 && ! info
->cr_save_p
4824 && info
->vrsave_mask
== 0
4832 /* Return the number of instructions it takes to form a constant in an
4833 integer register. */
4836 num_insns_constant_wide (HOST_WIDE_INT value
)
4838 /* signed constant loadable with addi */
4839 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4842 /* constant loadable with addis */
4843 else if ((value
& 0xffff) == 0
4844 && (value
>> 31 == -1 || value
>> 31 == 0))
4847 else if (TARGET_POWERPC64
)
4849 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4850 HOST_WIDE_INT high
= value
>> 31;
4852 if (high
== 0 || high
== -1)
4858 return num_insns_constant_wide (high
) + 1;
4860 return num_insns_constant_wide (low
) + 1;
4862 return (num_insns_constant_wide (high
)
4863 + num_insns_constant_wide (low
) + 1);
4871 num_insns_constant (rtx op
, enum machine_mode mode
)
4873 HOST_WIDE_INT low
, high
;
4875 switch (GET_CODE (op
))
4878 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4879 && mask64_operand (op
, mode
))
4882 return num_insns_constant_wide (INTVAL (op
));
4885 if (mode
== SFmode
|| mode
== SDmode
)
4890 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4891 if (DECIMAL_FLOAT_MODE_P (mode
))
4892 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4894 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4895 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4901 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4902 if (DECIMAL_FLOAT_MODE_P (mode
))
4903 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4905 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4906 high
= l
[WORDS_BIG_ENDIAN
== 0];
4907 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4910 return (num_insns_constant_wide (low
)
4911 + num_insns_constant_wide (high
));
4914 if ((high
== 0 && low
>= 0)
4915 || (high
== -1 && low
< 0))
4916 return num_insns_constant_wide (low
);
4918 else if (mask64_operand (op
, mode
))
4922 return num_insns_constant_wide (high
) + 1;
4925 return (num_insns_constant_wide (high
)
4926 + num_insns_constant_wide (low
) + 1);
4934 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4935 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4936 corresponding element of the vector, but for V4SFmode and V2SFmode,
4937 the corresponding "float" is interpreted as an SImode integer. */
4940 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4944 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4945 gcc_assert (GET_MODE (op
) != V2DImode
4946 && GET_MODE (op
) != V2DFmode
);
4948 tmp
= CONST_VECTOR_ELT (op
, elt
);
4949 if (GET_MODE (op
) == V4SFmode
4950 || GET_MODE (op
) == V2SFmode
)
4951 tmp
= gen_lowpart (SImode
, tmp
);
4952 return INTVAL (tmp
);
4955 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4956 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4957 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4958 all items are set to the same value and contain COPIES replicas of the
4959 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4960 operand and the others are set to the value of the operand's msb. */
4963 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4965 enum machine_mode mode
= GET_MODE (op
);
4966 enum machine_mode inner
= GET_MODE_INNER (mode
);
4974 HOST_WIDE_INT splat_val
;
4975 HOST_WIDE_INT msb_val
;
4977 if (mode
== V2DImode
|| mode
== V2DFmode
)
4980 nunits
= GET_MODE_NUNITS (mode
);
4981 bitsize
= GET_MODE_BITSIZE (inner
);
4982 mask
= GET_MODE_MASK (inner
);
4984 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
4986 msb_val
= val
> 0 ? 0 : -1;
4988 /* Construct the value to be splatted, if possible. If not, return 0. */
4989 for (i
= 2; i
<= copies
; i
*= 2)
4991 HOST_WIDE_INT small_val
;
4993 small_val
= splat_val
>> bitsize
;
4995 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4997 splat_val
= small_val
;
5000 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5001 if (EASY_VECTOR_15 (splat_val
))
5004 /* Also check if we can splat, and then add the result to itself. Do so if
5005 the value is positive, of if the splat instruction is using OP's mode;
5006 for splat_val < 0, the splat and the add should use the same mode. */
5007 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5008 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5011 /* Also check if are loading up the most significant bit which can be done by
5012 loading up -1 and shifting the value left by -1. */
5013 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5019 /* Check if VAL is present in every STEP-th element, and the
5020 other elements are filled with its most significant bit. */
5021 for (i
= 1; i
< nunits
; ++i
)
5023 HOST_WIDE_INT desired_val
;
5024 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5025 if ((i
& (step
- 1)) == 0)
5028 desired_val
= msb_val
;
5030 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5038 /* Return true if OP is of the given MODE and can be synthesized
5039 with a vspltisb, vspltish or vspltisw. */
5042 easy_altivec_constant (rtx op
, enum machine_mode mode
)
5044 unsigned step
, copies
;
5046 if (mode
== VOIDmode
)
5047 mode
= GET_MODE (op
);
5048 else if (mode
!= GET_MODE (op
))
5051 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5053 if (mode
== V2DFmode
)
5054 return zero_constant (op
, mode
);
5056 if (mode
== V2DImode
)
5058 /* In case the compiler is built 32-bit, CONST_DOUBLE constants are not
5060 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5061 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5064 if (zero_constant (op
, mode
))
5067 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5068 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5074 /* Start with a vspltisw. */
5075 step
= GET_MODE_NUNITS (mode
) / 4;
5078 if (vspltis_constant (op
, step
, copies
))
5081 /* Then try with a vspltish. */
5087 if (vspltis_constant (op
, step
, copies
))
5090 /* And finally a vspltisb. */
5096 if (vspltis_constant (op
, step
, copies
))
5102 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5103 result is OP. Abort if it is not possible. */
5106 gen_easy_altivec_constant (rtx op
)
5108 enum machine_mode mode
= GET_MODE (op
);
5109 int nunits
= GET_MODE_NUNITS (mode
);
5110 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5111 unsigned step
= nunits
/ 4;
5112 unsigned copies
= 1;
5114 /* Start with a vspltisw. */
5115 if (vspltis_constant (op
, step
, copies
))
5116 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5118 /* Then try with a vspltish. */
5124 if (vspltis_constant (op
, step
, copies
))
5125 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5127 /* And finally a vspltisb. */
5133 if (vspltis_constant (op
, step
, copies
))
5134 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5140 output_vec_const_move (rtx
*operands
)
5143 enum machine_mode mode
;
5148 mode
= GET_MODE (dest
);
5152 if (zero_constant (vec
, mode
))
5153 return "xxlxor %x0,%x0,%x0";
5155 if (mode
== V2DImode
5156 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5157 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5158 return "vspltisw %0,-1";
5164 if (zero_constant (vec
, mode
))
5165 return "vxor %0,%0,%0";
5167 splat_vec
= gen_easy_altivec_constant (vec
);
5168 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5169 operands
[1] = XEXP (splat_vec
, 0);
5170 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5173 switch (GET_MODE (splat_vec
))
5176 return "vspltisw %0,%1";
5179 return "vspltish %0,%1";
5182 return "vspltisb %0,%1";
5189 gcc_assert (TARGET_SPE
);
5191 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5192 pattern of V1DI, V4HI, and V2SF.
5194 FIXME: We should probably return # and add post reload
5195 splitters for these, but this way is so easy ;-). */
5196 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5197 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5198 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5199 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5201 return "li %0,%1\n\tevmergelo %0,%0,%0";
5203 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5206 /* Initialize TARGET of vector PAIRED to VALS. */
5209 paired_expand_vector_init (rtx target
, rtx vals
)
5211 enum machine_mode mode
= GET_MODE (target
);
5212 int n_elts
= GET_MODE_NUNITS (mode
);
5214 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5217 for (i
= 0; i
< n_elts
; ++i
)
5219 x
= XVECEXP (vals
, 0, i
);
5220 if (!(CONST_INT_P (x
)
5221 || GET_CODE (x
) == CONST_DOUBLE
5222 || GET_CODE (x
) == CONST_FIXED
))
5227 /* Load from constant pool. */
5228 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5234 /* The vector is initialized only with non-constants. */
5235 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5236 XVECEXP (vals
, 0, 1));
5238 emit_move_insn (target
, new_rtx
);
5242 /* One field is non-constant and the other one is a constant. Load the
5243 constant from the constant pool and use ps_merge instruction to
5244 construct the whole vector. */
5245 op1
= XVECEXP (vals
, 0, 0);
5246 op2
= XVECEXP (vals
, 0, 1);
5248 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5250 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5251 emit_move_insn (tmp
, constant_op
);
5253 if (CONSTANT_P (op1
))
5254 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5256 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5258 emit_move_insn (target
, new_rtx
);
5262 paired_expand_vector_move (rtx operands
[])
5264 rtx op0
= operands
[0], op1
= operands
[1];
5266 emit_move_insn (op0
, op1
);
5269 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5270 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5271 operands for the relation operation COND. This is a recursive
5275 paired_emit_vector_compare (enum rtx_code rcode
,
5276 rtx dest
, rtx op0
, rtx op1
,
5277 rtx cc_op0
, rtx cc_op1
)
5279 rtx tmp
= gen_reg_rtx (V2SFmode
);
5282 gcc_assert (TARGET_PAIRED_FLOAT
);
5283 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5289 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5293 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5294 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5298 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5301 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5304 tmp1
= gen_reg_rtx (V2SFmode
);
5305 max
= gen_reg_rtx (V2SFmode
);
5306 min
= gen_reg_rtx (V2SFmode
);
5307 gen_reg_rtx (V2SFmode
);
5309 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5310 emit_insn (gen_selv2sf4
5311 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5312 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5313 emit_insn (gen_selv2sf4
5314 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5315 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5316 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5319 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5322 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5325 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5328 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5331 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5340 /* Emit vector conditional expression.
5341 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5342 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5345 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5346 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5348 enum rtx_code rcode
= GET_CODE (cond
);
5350 if (!TARGET_PAIRED_FLOAT
)
5353 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5358 /* Initialize vector TARGET to VALS. */
5361 rs6000_expand_vector_init (rtx target
, rtx vals
)
5363 enum machine_mode mode
= GET_MODE (target
);
5364 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5365 int n_elts
= GET_MODE_NUNITS (mode
);
5366 int n_var
= 0, one_var
= -1;
5367 bool all_same
= true, all_const_zero
= true;
5371 for (i
= 0; i
< n_elts
; ++i
)
5373 x
= XVECEXP (vals
, 0, i
);
5374 if (!(CONST_INT_P (x
)
5375 || GET_CODE (x
) == CONST_DOUBLE
5376 || GET_CODE (x
) == CONST_FIXED
))
5377 ++n_var
, one_var
= i
;
5378 else if (x
!= CONST0_RTX (inner_mode
))
5379 all_const_zero
= false;
5381 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5387 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5388 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5389 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5391 /* Zero register. */
5392 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5393 gen_rtx_XOR (mode
, target
, target
)));
5396 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5398 /* Splat immediate. */
5399 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5404 /* Load from constant pool. */
5405 emit_move_insn (target
, const_vec
);
5410 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5411 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5413 rtx op0
= XVECEXP (vals
, 0, 0);
5414 rtx op1
= XVECEXP (vals
, 0, 1);
5417 if (!MEM_P (op0
) && !REG_P (op0
))
5418 op0
= force_reg (inner_mode
, op0
);
5419 if (mode
== V2DFmode
)
5420 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5422 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5426 op0
= force_reg (inner_mode
, op0
);
5427 op1
= force_reg (inner_mode
, op1
);
5428 if (mode
== V2DFmode
)
5429 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5431 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5436 /* With single precision floating point on VSX, know that internally single
5437 precision is actually represented as a double, and either make 2 V2DF
5438 vectors, and convert these vectors to single precision, or do one
5439 conversion, and splat the result to the other elements. */
5440 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5444 rtx freg
= gen_reg_rtx (V4SFmode
);
5445 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5446 rtx cvt
= ((TARGET_XSCVDPSPN
)
5447 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5448 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5451 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
5455 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5456 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5457 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5458 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5459 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5460 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5461 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5462 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5464 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5465 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5466 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5467 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5468 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5473 /* Store value to stack temp. Load vector element. Splat. However, splat
5474 of 64-bit items is not supported on Altivec. */
5475 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5478 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5479 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5480 XVECEXP (vals
, 0, 0));
5481 x
= gen_rtx_UNSPEC (VOIDmode
,
5482 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5483 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5485 gen_rtx_SET (VOIDmode
,
5488 field
= (BYTES_BIG_ENDIAN
? const0_rtx
5489 : GEN_INT (GET_MODE_NUNITS (mode
) - 1));
5490 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5491 gen_rtx_PARALLEL (VOIDmode
,
5492 gen_rtvec (1, field
)));
5493 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5494 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5498 /* One field is non-constant. Load constant then overwrite
5502 rtx copy
= copy_rtx (vals
);
5504 /* Load constant part of vector, substitute neighboring value for
5506 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5507 rs6000_expand_vector_init (target
, copy
);
5509 /* Insert variable. */
5510 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5514 /* Construct the vector in memory one field at a time
5515 and load the whole vector. */
5516 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5517 for (i
= 0; i
< n_elts
; i
++)
5518 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5519 i
* GET_MODE_SIZE (inner_mode
)),
5520 XVECEXP (vals
, 0, i
));
5521 emit_move_insn (target
, mem
);
5524 /* Set field ELT of TARGET to VAL. */
5527 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5529 enum machine_mode mode
= GET_MODE (target
);
5530 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5531 rtx reg
= gen_reg_rtx (mode
);
5533 int width
= GET_MODE_SIZE (inner_mode
);
5536 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5538 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5539 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5540 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5544 /* Load single variable value. */
5545 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5546 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5547 x
= gen_rtx_UNSPEC (VOIDmode
,
5548 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5549 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5551 gen_rtx_SET (VOIDmode
,
5555 /* Linear sequence. */
5556 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5557 for (i
= 0; i
< 16; ++i
)
5558 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5560 /* Set permute mask to insert element into target. */
5561 for (i
= 0; i
< width
; ++i
)
5562 XVECEXP (mask
, 0, elt
*width
+ i
)
5563 = GEN_INT (i
+ 0x10);
5564 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5566 if (BYTES_BIG_ENDIAN
)
5567 x
= gen_rtx_UNSPEC (mode
,
5568 gen_rtvec (3, target
, reg
,
5569 force_reg (V16QImode
, x
)),
5573 /* Invert selector. */
5574 rtx splat
= gen_rtx_VEC_DUPLICATE (V16QImode
,
5575 gen_rtx_CONST_INT (QImode
, -1));
5576 rtx tmp
= gen_reg_rtx (V16QImode
);
5577 emit_move_insn (tmp
, splat
);
5578 x
= gen_rtx_MINUS (V16QImode
, tmp
, force_reg (V16QImode
, x
));
5579 emit_move_insn (tmp
, x
);
5581 /* Permute with operands reversed and adjusted selector. */
5582 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5586 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5589 /* Extract field ELT from VEC into TARGET. */
5592 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5594 enum machine_mode mode
= GET_MODE (vec
);
5595 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5598 if (VECTOR_MEM_VSX_P (mode
))
5605 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5608 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5611 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5616 /* Allocate mode-sized buffer. */
5617 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5619 emit_move_insn (mem
, vec
);
5621 /* Add offset to field within buffer matching vector element. */
5622 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5624 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5627 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5628 implement ANDing by the mask IN. */
5630 build_mask64_2_operands (rtx in
, rtx
*out
)
5632 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5635 gcc_assert (GET_CODE (in
) == CONST_INT
);
5640 /* Assume c initially something like 0x00fff000000fffff. The idea
5641 is to rotate the word so that the middle ^^^^^^ group of zeros
5642 is at the MS end and can be cleared with an rldicl mask. We then
5643 rotate back and clear off the MS ^^ group of zeros with a
5645 c
= ~c
; /* c == 0xff000ffffff00000 */
5646 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5647 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5648 c
= ~c
; /* c == 0x00fff000000fffff */
5649 c
&= -lsb
; /* c == 0x00fff00000000000 */
5650 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5651 c
= ~c
; /* c == 0xff000fffffffffff */
5652 c
&= -lsb
; /* c == 0xff00000000000000 */
5654 while ((lsb
>>= 1) != 0)
5655 shift
++; /* shift == 44 on exit from loop */
5656 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5657 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5658 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5662 /* Assume c initially something like 0xff000f0000000000. The idea
5663 is to rotate the word so that the ^^^ middle group of zeros
5664 is at the LS end and can be cleared with an rldicr mask. We then
5665 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5667 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5668 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5669 c
= ~c
; /* c == 0x00fff0ffffffffff */
5670 c
&= -lsb
; /* c == 0x00fff00000000000 */
5671 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5672 c
= ~c
; /* c == 0xff000fffffffffff */
5673 c
&= -lsb
; /* c == 0xff00000000000000 */
5675 while ((lsb
>>= 1) != 0)
5676 shift
++; /* shift == 44 on exit from loop */
5677 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5678 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5679 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5682 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5683 masks will be all 1's. We are guaranteed more than one transition. */
5684 out
[0] = GEN_INT (64 - shift
);
5685 out
[1] = GEN_INT (m1
);
5686 out
[2] = GEN_INT (shift
);
5687 out
[3] = GEN_INT (m2
);
5690 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5693 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5695 if (TARGET_E500_DOUBLE
)
5697 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5698 subreg:TI and reg:TF. Decimal float modes are like integer
5699 modes (only low part of each register used) for this
5701 if (GET_CODE (op
) == SUBREG
5702 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5703 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5704 && REG_P (SUBREG_REG (op
))
5705 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5706 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5709 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5711 if (GET_CODE (op
) == SUBREG
5712 && (mode
== DFmode
|| mode
== TFmode
)
5713 && REG_P (SUBREG_REG (op
))
5714 && (GET_MODE (SUBREG_REG (op
)) == DImode
5715 || GET_MODE (SUBREG_REG (op
)) == TImode
5716 || GET_MODE (SUBREG_REG (op
)) == PTImode
5717 || GET_MODE (SUBREG_REG (op
)) == DDmode
5718 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5723 && GET_CODE (op
) == SUBREG
5725 && REG_P (SUBREG_REG (op
))
5726 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5732 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5733 selects whether the alignment is abi mandated, optional, or
5734 both abi and optional alignment. */
5737 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5739 if (how
!= align_opt
)
5741 if (TREE_CODE (type
) == VECTOR_TYPE
)
5743 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5744 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5749 else if (align
< 128)
5752 else if (TARGET_E500_DOUBLE
5753 && TREE_CODE (type
) == REAL_TYPE
5754 && TYPE_MODE (type
) == DFmode
)
5761 if (how
!= align_abi
)
5763 if (TREE_CODE (type
) == ARRAY_TYPE
5764 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5766 if (align
< BITS_PER_WORD
)
5767 align
= BITS_PER_WORD
;
5774 /* AIX increases natural record alignment to doubleword if the first
5775 field is an FP double while the FP fields remain word aligned. */
5778 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5779 unsigned int specified
)
5781 unsigned int align
= MAX (computed
, specified
);
5782 tree field
= TYPE_FIELDS (type
);
5784 /* Skip all non field decls */
5785 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5786 field
= DECL_CHAIN (field
);
5788 if (field
!= NULL
&& field
!= type
)
5790 type
= TREE_TYPE (field
);
5791 while (TREE_CODE (type
) == ARRAY_TYPE
)
5792 type
= TREE_TYPE (type
);
5794 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5795 align
= MAX (align
, 64);
5801 /* Darwin increases record alignment to the natural alignment of
5805 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5806 unsigned int specified
)
5808 unsigned int align
= MAX (computed
, specified
);
5810 if (TYPE_PACKED (type
))
5813 /* Find the first field, looking down into aggregates. */
5815 tree field
= TYPE_FIELDS (type
);
5816 /* Skip all non field decls */
5817 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5818 field
= DECL_CHAIN (field
);
5821 /* A packed field does not contribute any extra alignment. */
5822 if (DECL_PACKED (field
))
5824 type
= TREE_TYPE (field
);
5825 while (TREE_CODE (type
) == ARRAY_TYPE
)
5826 type
= TREE_TYPE (type
);
5827 } while (AGGREGATE_TYPE_P (type
));
5829 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5830 align
= MAX (align
, TYPE_ALIGN (type
));
5835 /* Return 1 for an operand in small memory on V.4/eabi. */
5838 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5839 enum machine_mode mode ATTRIBUTE_UNUSED
)
5844 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5847 if (DEFAULT_ABI
!= ABI_V4
)
5850 /* Vector and float memory instructions have a limited offset on the
5851 SPE, so using a vector or float variable directly as an operand is
5854 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5857 if (GET_CODE (op
) == SYMBOL_REF
)
5860 else if (GET_CODE (op
) != CONST
5861 || GET_CODE (XEXP (op
, 0)) != PLUS
5862 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5863 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5868 rtx sum
= XEXP (op
, 0);
5869 HOST_WIDE_INT summand
;
5871 /* We have to be careful here, because it is the referenced address
5872 that must be 32k from _SDA_BASE_, not just the symbol. */
5873 summand
= INTVAL (XEXP (sum
, 1));
5874 if (summand
< 0 || summand
> g_switch_value
)
5877 sym_ref
= XEXP (sum
, 0);
5880 return SYMBOL_REF_SMALL_P (sym_ref
);
5886 /* Return true if either operand is a general purpose register. */
5889 gpr_or_gpr_p (rtx op0
, rtx op1
)
5891 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5892 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5895 /* Return true if this is a move direct operation between GPR registers and
5896 floating point/VSX registers. */
5899 direct_move_p (rtx op0
, rtx op1
)
5903 if (!REG_P (op0
) || !REG_P (op1
))
5906 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
5909 regno0
= REGNO (op0
);
5910 regno1
= REGNO (op1
);
5911 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
5914 if (INT_REGNO_P (regno0
))
5915 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
5917 else if (INT_REGNO_P (regno1
))
5919 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
5922 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
5929 /* Return true if this is a load or store quad operation. */
5932 quad_load_store_p (rtx op0
, rtx op1
)
5936 if (!TARGET_QUAD_MEMORY
)
5939 else if (REG_P (op0
) && MEM_P (op1
))
5940 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
5941 && quad_memory_operand (op1
, GET_MODE (op1
))
5942 && !reg_overlap_mentioned_p (op0
, op1
));
5944 else if (MEM_P (op0
) && REG_P (op1
))
5945 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
5946 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
5951 if (TARGET_DEBUG_ADDR
)
5953 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
5954 ret
? "true" : "false");
5955 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
5961 /* Given an address, return a constant offset term if one exists. */
5964 address_offset (rtx op
)
5966 if (GET_CODE (op
) == PRE_INC
5967 || GET_CODE (op
) == PRE_DEC
)
5969 else if (GET_CODE (op
) == PRE_MODIFY
5970 || GET_CODE (op
) == LO_SUM
)
5973 if (GET_CODE (op
) == CONST
)
5976 if (GET_CODE (op
) == PLUS
)
5979 if (CONST_INT_P (op
))
5985 /* Return true if the MEM operand is a memory operand suitable for use
5986 with a (full width, possibly multiple) gpr load/store. On
5987 powerpc64 this means the offset must be divisible by 4.
5988 Implements 'Y' constraint.
5990 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5991 a constraint function we know the operand has satisfied a suitable
5992 memory predicate. Also accept some odd rtl generated by reload
5993 (see rs6000_legitimize_reload_address for various forms). It is
5994 important that reload rtl be accepted by appropriate constraints
5995 but not by the operand predicate.
5997 Offsetting a lo_sum should not be allowed, except where we know by
5998 alignment that a 32k boundary is not crossed, but see the ???
5999 comment in rs6000_legitimize_reload_address. Note that by
6000 "offsetting" here we mean a further offset to access parts of the
6001 MEM. It's fine to have a lo_sum where the inner address is offset
6002 from a sym, since the same sym+offset will appear in the high part
6003 of the address calculation. */
6006 mem_operand_gpr (rtx op
, enum machine_mode mode
)
6008 unsigned HOST_WIDE_INT offset
;
6010 rtx addr
= XEXP (op
, 0);
6012 op
= address_offset (addr
);
6016 offset
= INTVAL (op
);
6017 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6020 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6021 gcc_assert (extra
>= 0);
6023 if (GET_CODE (addr
) == LO_SUM
)
6024 /* For lo_sum addresses, we must allow any offset except one that
6025 causes a wrap, so test only the low 16 bits. */
6026 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6028 return offset
+ 0x8000 < 0x10000u
- extra
;
6031 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6034 reg_offset_addressing_ok_p (enum machine_mode mode
)
6045 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6046 TImode is not a vector mode, if we want to use the VSX registers to
6047 move it around, we need to restrict ourselves to reg+reg
6049 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6057 /* Paired vector modes. Only reg+reg addressing is valid. */
6058 if (TARGET_PAIRED_FLOAT
)
6063 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6064 addressing for the LFIWZX and STFIWX instructions. */
6065 if (TARGET_NO_SDMODE_STACK
)
6077 virtual_stack_registers_memory_p (rtx op
)
6081 if (GET_CODE (op
) == REG
)
6082 regnum
= REGNO (op
);
6084 else if (GET_CODE (op
) == PLUS
6085 && GET_CODE (XEXP (op
, 0)) == REG
6086 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6087 regnum
= REGNO (XEXP (op
, 0));
6092 return (regnum
>= FIRST_VIRTUAL_REGISTER
6093 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6096 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6097 is known to not straddle a 32k boundary. */
6100 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6101 enum machine_mode mode
)
6104 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6106 if (GET_CODE (op
) != SYMBOL_REF
)
6109 dsize
= GET_MODE_SIZE (mode
);
6110 decl
= SYMBOL_REF_DECL (op
);
6116 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6117 replacing memory addresses with an anchor plus offset. We
6118 could find the decl by rummaging around in the block->objects
6119 VEC for the given offset but that seems like too much work. */
6120 dalign
= BITS_PER_UNIT
;
6121 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6122 && SYMBOL_REF_ANCHOR_P (op
)
6123 && SYMBOL_REF_BLOCK (op
) != NULL
)
6125 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6127 dalign
= block
->alignment
;
6128 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6130 else if (CONSTANT_POOL_ADDRESS_P (op
))
6132 /* It would be nice to have get_pool_align().. */
6133 enum machine_mode cmode
= get_pool_mode (op
);
6135 dalign
= GET_MODE_ALIGNMENT (cmode
);
6138 else if (DECL_P (decl
))
6140 dalign
= DECL_ALIGN (decl
);
6144 /* Allow BLKmode when the entire object is known to not
6145 cross a 32k boundary. */
6146 if (!DECL_SIZE_UNIT (decl
))
6149 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6152 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6156 return dalign
/ BITS_PER_UNIT
>= dsize
;
6161 type
= TREE_TYPE (decl
);
6163 dalign
= TYPE_ALIGN (type
);
6164 if (CONSTANT_CLASS_P (decl
))
6165 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
6167 dalign
= DATA_ALIGNMENT (decl
, dalign
);
6171 /* BLKmode, check the entire object. */
6172 if (TREE_CODE (decl
) == STRING_CST
)
6173 dsize
= TREE_STRING_LENGTH (decl
);
6174 else if (TYPE_SIZE_UNIT (type
)
6175 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
6176 dsize
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
6182 return dalign
/ BITS_PER_UNIT
>= dsize
;
6186 /* Find how many bits of the alignment we know for this access. */
6187 mask
= dalign
/ BITS_PER_UNIT
- 1;
6188 lsb
= offset
& -offset
;
6192 return dalign
>= dsize
;
6196 constant_pool_expr_p (rtx op
)
6200 split_const (op
, &base
, &offset
);
6201 return (GET_CODE (base
) == SYMBOL_REF
6202 && CONSTANT_POOL_ADDRESS_P (base
)
6203 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6206 static const_rtx tocrel_base
, tocrel_offset
;
6208 /* Return true if OP is a toc pointer relative address (the output
6209 of create_TOC_reference). If STRICT, do not match high part or
6210 non-split -mcmodel=large/medium toc pointer relative addresses. */
6213 toc_relative_expr_p (const_rtx op
, bool strict
)
6218 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6220 /* Only match the low part. */
6221 if (GET_CODE (op
) == LO_SUM
6222 && REG_P (XEXP (op
, 0))
6223 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6230 tocrel_offset
= const0_rtx
;
6231 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6233 tocrel_base
= XEXP (op
, 0);
6234 tocrel_offset
= XEXP (op
, 1);
6237 return (GET_CODE (tocrel_base
) == UNSPEC
6238 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6241 /* Return true if X is a constant pool address, and also for cmodel=medium
6242 if X is a toc-relative address known to be offsettable within MODE. */
6245 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
6248 return (toc_relative_expr_p (x
, strict
)
6249 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6250 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6252 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6253 INTVAL (tocrel_offset
), mode
)));
6257 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
6259 return (DEFAULT_ABI
== ABI_V4
6260 && !flag_pic
&& !TARGET_TOC
6261 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6262 && small_data_operand (x
, mode
));
6265 /* SPE offset addressing is limited to 5-bits worth of double words. */
6266 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6269 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
6270 bool strict
, bool worst_case
)
6272 unsigned HOST_WIDE_INT offset
;
6275 if (GET_CODE (x
) != PLUS
)
6277 if (!REG_P (XEXP (x
, 0)))
6279 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6281 if (!reg_offset_addressing_ok_p (mode
))
6282 return virtual_stack_registers_memory_p (x
);
6283 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6285 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6288 offset
= INTVAL (XEXP (x
, 1));
6296 /* SPE vector modes. */
6297 return SPE_CONST_OFFSET_OK (offset
);
6302 /* On e500v2, we may have:
6304 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6306 Which gets addressed with evldd instructions. */
6307 if (TARGET_E500_DOUBLE
)
6308 return SPE_CONST_OFFSET_OK (offset
);
6310 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6312 if (VECTOR_MEM_VSX_P (mode
))
6317 if (!TARGET_POWERPC64
)
6319 else if (offset
& 3)
6327 if (TARGET_E500_DOUBLE
)
6328 return (SPE_CONST_OFFSET_OK (offset
)
6329 && SPE_CONST_OFFSET_OK (offset
+ 8));
6334 if (!TARGET_POWERPC64
)
6336 else if (offset
& 3)
6345 return offset
< 0x10000 - extra
;
6349 legitimate_indexed_address_p (rtx x
, int strict
)
6353 if (GET_CODE (x
) != PLUS
)
6359 /* Recognize the rtl generated by reload which we know will later be
6360 replaced with proper base and index regs. */
6362 && reload_in_progress
6363 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6367 return (REG_P (op0
) && REG_P (op1
)
6368 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6369 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6370 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6371 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6375 avoiding_indexed_address_p (enum machine_mode mode
)
6377 /* Avoid indexed addressing for modes that have non-indexed
6378 load/store instruction forms. */
6379 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6383 legitimate_indirect_address_p (rtx x
, int strict
)
6385 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6389 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6391 if (!TARGET_MACHO
|| !flag_pic
6392 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6396 if (GET_CODE (x
) != LO_SUM
)
6398 if (GET_CODE (XEXP (x
, 0)) != REG
)
6400 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6404 return CONSTANT_P (x
);
6408 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6410 if (GET_CODE (x
) != LO_SUM
)
6412 if (GET_CODE (XEXP (x
, 0)) != REG
)
6414 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6416 /* Restrict addressing for DI because of our SUBREG hackery. */
6417 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6421 if (TARGET_ELF
|| TARGET_MACHO
)
6425 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6427 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6428 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6429 recognizes some LO_SUM addresses as valid although this
6430 function says opposite. In most cases, LRA through different
6431 transformations can generate correct code for address reloads.
6432 It can not manage only some LO_SUM cases. So we need to add
6433 code analogous to one in rs6000_legitimize_reload_address for
6434 LOW_SUM here saying that some addresses are still valid. */
6435 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6436 && small_toc_ref (x
, VOIDmode
));
6437 if (TARGET_TOC
&& ! large_toc_ok
)
6439 if (GET_MODE_NUNITS (mode
) != 1)
6441 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6442 && !(/* ??? Assume floating point reg based on mode? */
6443 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6444 && (mode
== DFmode
|| mode
== DDmode
)))
6447 return CONSTANT_P (x
) || large_toc_ok
;
6454 /* Try machine-dependent ways of modifying an illegitimate address
6455 to be legitimate. If we find one, return the new, valid address.
6456 This is used from only one place: `memory_address' in explow.c.
6458 OLDX is the address as it was before break_out_memory_refs was
6459 called. In some cases it is useful to look at this to decide what
6462 It is always safe for this function to do nothing. It exists to
6463 recognize opportunities to optimize the output.
6465 On RS/6000, first check for the sum of a register with a constant
6466 integer that is out of range. If so, generate code to add the
6467 constant with the low-order 16 bits masked to the register and force
6468 this result into another register (this can be done with `cau').
6469 Then generate an address of REG+(CONST&0xffff), allowing for the
6470 possibility of bit 16 being a one.
6472 Then check for the sum of a register and something not constant, try to
6473 load the other things into a register and return the sum. */
6476 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6477 enum machine_mode mode
)
6481 if (!reg_offset_addressing_ok_p (mode
))
6483 if (virtual_stack_registers_memory_p (x
))
6486 /* In theory we should not be seeing addresses of the form reg+0,
6487 but just in case it is generated, optimize it away. */
6488 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6489 return force_reg (Pmode
, XEXP (x
, 0));
6491 /* For TImode with load/store quad, restrict addresses to just a single
6492 pointer, so it works with both GPRs and VSX registers. */
6493 /* Make sure both operands are registers. */
6494 else if (GET_CODE (x
) == PLUS
6495 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6496 return gen_rtx_PLUS (Pmode
,
6497 force_reg (Pmode
, XEXP (x
, 0)),
6498 force_reg (Pmode
, XEXP (x
, 1)));
6500 return force_reg (Pmode
, x
);
6502 if (GET_CODE (x
) == SYMBOL_REF
)
6504 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6506 return rs6000_legitimize_tls_address (x
, model
);
6516 /* As in legitimate_offset_address_p we do not assume
6517 worst-case. The mode here is just a hint as to the registers
6518 used. A TImode is usually in gprs, but may actually be in
6519 fprs. Leave worst-case scenario for reload to handle via
6520 insn constraints. PTImode is only GPRs. */
6527 if (GET_CODE (x
) == PLUS
6528 && GET_CODE (XEXP (x
, 0)) == REG
6529 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6530 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6532 && !(SPE_VECTOR_MODE (mode
)
6533 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6535 HOST_WIDE_INT high_int
, low_int
;
6537 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6538 if (low_int
>= 0x8000 - extra
)
6540 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6541 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6542 GEN_INT (high_int
)), 0);
6543 return plus_constant (Pmode
, sum
, low_int
);
6545 else if (GET_CODE (x
) == PLUS
6546 && GET_CODE (XEXP (x
, 0)) == REG
6547 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6548 && GET_MODE_NUNITS (mode
) == 1
6549 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6550 || (/* ??? Assume floating point reg based on mode? */
6551 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6552 && (mode
== DFmode
|| mode
== DDmode
)))
6553 && !avoiding_indexed_address_p (mode
))
6555 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6556 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6558 else if (SPE_VECTOR_MODE (mode
)
6559 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6563 /* We accept [reg + reg] and [reg + OFFSET]. */
6565 if (GET_CODE (x
) == PLUS
)
6567 rtx op1
= XEXP (x
, 0);
6568 rtx op2
= XEXP (x
, 1);
6571 op1
= force_reg (Pmode
, op1
);
6573 if (GET_CODE (op2
) != REG
6574 && (GET_CODE (op2
) != CONST_INT
6575 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6576 || (GET_MODE_SIZE (mode
) > 8
6577 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6578 op2
= force_reg (Pmode
, op2
);
6580 /* We can't always do [reg + reg] for these, because [reg +
6581 reg + offset] is not a legitimate addressing mode. */
6582 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6584 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6585 return force_reg (Pmode
, y
);
6590 return force_reg (Pmode
, x
);
6592 else if ((TARGET_ELF
6594 || !MACHO_DYNAMIC_NO_PIC_P
6600 && GET_CODE (x
) != CONST_INT
6601 && GET_CODE (x
) != CONST_DOUBLE
6603 && GET_MODE_NUNITS (mode
) == 1
6604 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6605 || (/* ??? Assume floating point reg based on mode? */
6606 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6607 && (mode
== DFmode
|| mode
== DDmode
))))
6609 rtx reg
= gen_reg_rtx (Pmode
);
6611 emit_insn (gen_elf_high (reg
, x
));
6613 emit_insn (gen_macho_high (reg
, x
));
6614 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6617 && GET_CODE (x
) == SYMBOL_REF
6618 && constant_pool_expr_p (x
)
6619 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6620 return create_TOC_reference (x
, NULL_RTX
);
6625 /* Debug version of rs6000_legitimize_address. */
6627 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6633 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6634 insns
= get_insns ();
6640 "\nrs6000_legitimize_address: mode %s, old code %s, "
6641 "new code %s, modified\n",
6642 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6643 GET_RTX_NAME (GET_CODE (ret
)));
6645 fprintf (stderr
, "Original address:\n");
6648 fprintf (stderr
, "oldx:\n");
6651 fprintf (stderr
, "New address:\n");
6656 fprintf (stderr
, "Insns added:\n");
6657 debug_rtx_list (insns
, 20);
6663 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6664 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6675 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6676 We need to emit DTP-relative relocations. */
6678 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6680 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6685 fputs ("\t.long\t", file
);
6688 fputs (DOUBLE_INT_ASM_OP
, file
);
6693 output_addr_const (file
, x
);
6694 fputs ("@dtprel+0x8000", file
);
6697 /* In the name of slightly smaller debug output, and to cater to
6698 general assembler lossage, recognize various UNSPEC sequences
6699 and turn them back into a direct symbol reference. */
6702 rs6000_delegitimize_address (rtx orig_x
)
6706 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6712 if (TARGET_CMODEL
!= CMODEL_SMALL
6713 && GET_CODE (y
) == LO_SUM
)
6717 if (GET_CODE (y
) == PLUS
6718 && GET_MODE (y
) == Pmode
6719 && CONST_INT_P (XEXP (y
, 1)))
6721 offset
= XEXP (y
, 1);
6725 if (GET_CODE (y
) == UNSPEC
6726 && XINT (y
, 1) == UNSPEC_TOCREL
)
6728 #ifdef ENABLE_CHECKING
6729 if (REG_P (XVECEXP (y
, 0, 1))
6730 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6734 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6736 /* Weirdness alert. df_note_compute can replace r2 with a
6737 debug_expr when this unspec is in a debug_insn.
6738 Seen in gcc.dg/pr51957-1.c */
6746 y
= XVECEXP (y
, 0, 0);
6749 /* Do not associate thread-local symbols with the original
6750 constant pool symbol. */
6752 && GET_CODE (y
) == SYMBOL_REF
6753 && CONSTANT_POOL_ADDRESS_P (y
)
6754 && SYMBOL_REF_TLS_MODEL (get_pool_constant (y
)) >= TLS_MODEL_REAL
)
6758 if (offset
!= NULL_RTX
)
6759 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6760 if (!MEM_P (orig_x
))
6763 return replace_equiv_address_nv (orig_x
, y
);
6767 && GET_CODE (orig_x
) == LO_SUM
6768 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6770 y
= XEXP (XEXP (orig_x
, 1), 0);
6771 if (GET_CODE (y
) == UNSPEC
6772 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6773 return XVECEXP (y
, 0, 0);
6779 /* Return true if X shouldn't be emitted into the debug info.
6780 The linker doesn't like .toc section references from
6781 .debug_* sections, so reject .toc section symbols. */
6784 rs6000_const_not_ok_for_debug_p (rtx x
)
6786 if (GET_CODE (x
) == SYMBOL_REF
6787 && CONSTANT_POOL_ADDRESS_P (x
))
6789 rtx c
= get_pool_constant (x
);
6790 enum machine_mode cmode
= get_pool_mode (x
);
6791 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6798 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6800 static GTY(()) rtx rs6000_tls_symbol
;
6802 rs6000_tls_get_addr (void)
6804 if (!rs6000_tls_symbol
)
6805 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6807 return rs6000_tls_symbol
;
6810 /* Construct the SYMBOL_REF for TLS GOT references. */
6812 static GTY(()) rtx rs6000_got_symbol
;
6814 rs6000_got_sym (void)
6816 if (!rs6000_got_symbol
)
6818 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6819 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6820 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6823 return rs6000_got_symbol
;
6826 /* AIX Thread-Local Address support. */
6829 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6831 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6835 name
= XSTR (addr
, 0);
6836 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6837 or the symbol will be in TLS private data section. */
6838 if (name
[strlen (name
) - 1] != ']'
6839 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6840 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6842 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6843 strcpy (tlsname
, name
);
6845 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6846 tlsaddr
= copy_rtx (addr
);
6847 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6852 /* Place addr into TOC constant pool. */
6853 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6855 /* Output the TOC entry and create the MEM referencing the value. */
6856 if (constant_pool_expr_p (XEXP (sym
, 0))
6857 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6859 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6860 mem
= gen_const_mem (Pmode
, tocref
);
6861 set_mem_alias_set (mem
, get_TOC_alias_set ());
6866 /* Use global-dynamic for local-dynamic. */
6867 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6868 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6870 /* Create new TOC reference for @m symbol. */
6871 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6872 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6873 strcpy (tlsname
, "*LCM");
6874 strcat (tlsname
, name
+ 3);
6875 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6876 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6877 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
6878 rtx modmem
= gen_const_mem (Pmode
, tocref
);
6879 set_mem_alias_set (modmem
, get_TOC_alias_set ());
6881 rtx modreg
= gen_reg_rtx (Pmode
);
6882 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
6884 tmpreg
= gen_reg_rtx (Pmode
);
6885 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6887 dest
= gen_reg_rtx (Pmode
);
6889 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
6891 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
6894 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
6895 else if (TARGET_32BIT
)
6897 tlsreg
= gen_reg_rtx (SImode
);
6898 emit_insn (gen_tls_get_tpointer (tlsreg
));
6901 tlsreg
= gen_rtx_REG (DImode
, 13);
6903 /* Load the TOC value into temporary register. */
6904 tmpreg
= gen_reg_rtx (Pmode
);
6905 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6906 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
6907 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
6909 /* Add TOC symbol value to TLS pointer. */
6910 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
6915 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
6916 this (thread-local) address. */
6919 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
6924 return rs6000_legitimize_tls_address_aix (addr
, model
);
6926 dest
= gen_reg_rtx (Pmode
);
6927 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
6933 tlsreg
= gen_rtx_REG (Pmode
, 13);
6934 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
6938 tlsreg
= gen_rtx_REG (Pmode
, 2);
6939 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
6943 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
6947 tmp
= gen_reg_rtx (Pmode
);
6950 tlsreg
= gen_rtx_REG (Pmode
, 13);
6951 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
6955 tlsreg
= gen_rtx_REG (Pmode
, 2);
6956 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
6960 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
6962 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
6967 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
6969 /* We currently use relocations like @got@tlsgd for tls, which
6970 means the linker will handle allocation of tls entries, placing
6971 them in the .got section. So use a pointer to the .got section,
6972 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6973 or to secondary GOT sections used by 32-bit -fPIC. */
6975 got
= gen_rtx_REG (Pmode
, 2);
6979 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
6982 rtx gsym
= rs6000_got_sym ();
6983 got
= gen_reg_rtx (Pmode
);
6985 rs6000_emit_move (got
, gsym
, Pmode
);
6990 tmp1
= gen_reg_rtx (Pmode
);
6991 tmp2
= gen_reg_rtx (Pmode
);
6992 mem
= gen_const_mem (Pmode
, tmp1
);
6993 lab
= gen_label_rtx ();
6994 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
6995 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
6996 if (TARGET_LINK_STACK
)
6997 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
6998 emit_move_insn (tmp2
, mem
);
6999 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
7000 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7005 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7007 tga
= rs6000_tls_get_addr ();
7008 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7009 1, const0_rtx
, Pmode
);
7011 r3
= gen_rtx_REG (Pmode
, 3);
7012 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7015 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7017 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7019 else if (DEFAULT_ABI
== ABI_V4
)
7020 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7023 call_insn
= last_call_insn ();
7024 PATTERN (call_insn
) = insn
;
7025 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7026 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7027 pic_offset_table_rtx
);
7029 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7031 tga
= rs6000_tls_get_addr ();
7032 tmp1
= gen_reg_rtx (Pmode
);
7033 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7034 1, const0_rtx
, Pmode
);
7036 r3
= gen_rtx_REG (Pmode
, 3);
7037 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7040 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7042 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7044 else if (DEFAULT_ABI
== ABI_V4
)
7045 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7048 call_insn
= last_call_insn ();
7049 PATTERN (call_insn
) = insn
;
7050 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7051 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7052 pic_offset_table_rtx
);
7054 if (rs6000_tls_size
== 16)
7057 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7059 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7061 else if (rs6000_tls_size
== 32)
7063 tmp2
= gen_reg_rtx (Pmode
);
7065 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7067 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7070 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7072 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7076 tmp2
= gen_reg_rtx (Pmode
);
7078 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7080 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7082 insn
= gen_rtx_SET (Pmode
, dest
,
7083 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7089 /* IE, or 64-bit offset LE. */
7090 tmp2
= gen_reg_rtx (Pmode
);
7092 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7094 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7097 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7099 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7107 /* Return 1 if X contains a thread-local symbol. */
7110 rs6000_tls_referenced_p (rtx x
)
7112 if (! TARGET_HAVE_TLS
)
7115 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
7118 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7121 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7123 if (GET_CODE (x
) == HIGH
7124 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7127 /* A TLS symbol in the TOC cannot contain a sum. */
7128 if (GET_CODE (x
) == CONST
7129 && GET_CODE (XEXP (x
, 0)) == PLUS
7130 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7131 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7134 /* Do not place an ELF TLS symbol in the constant pool. */
7135 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
7138 /* Return 1 if *X is a thread-local symbol. This is the same as
7139 rs6000_tls_symbol_ref except for the type of the unused argument. */
7142 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7144 return RS6000_SYMBOL_REF_TLS_P (*x
);
7147 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7148 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7149 can be addressed relative to the toc pointer. */
7152 use_toc_relative_ref (rtx sym
)
7154 return ((constant_pool_expr_p (sym
)
7155 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7156 get_pool_mode (sym
)))
7157 || (TARGET_CMODEL
== CMODEL_MEDIUM
7158 && SYMBOL_REF_LOCAL_P (sym
)));
7161 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7162 replace the input X, or the original X if no replacement is called for.
7163 The output parameter *WIN is 1 if the calling macro should goto WIN,
7166 For RS/6000, we wish to handle large displacements off a base
7167 register by splitting the addend across an addiu/addis and the mem insn.
7168 This cuts number of extra insns needed from 3 to 1.
7170 On Darwin, we use this to generate code for floating point constants.
7171 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7172 The Darwin code is inside #if TARGET_MACHO because only then are the
7173 machopic_* functions defined. */
7175 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7176 int opnum
, int type
,
7177 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7179 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7181 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7182 DFmode/DImode MEM. */
7185 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7186 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7187 reg_offset_p
= false;
7189 /* We must recognize output that we have already generated ourselves. */
7190 if (GET_CODE (x
) == PLUS
7191 && GET_CODE (XEXP (x
, 0)) == PLUS
7192 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7193 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7194 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7196 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7197 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7198 opnum
, (enum reload_type
) type
);
7203 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7204 if (GET_CODE (x
) == LO_SUM
7205 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7207 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7208 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7209 opnum
, (enum reload_type
) type
);
7215 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7216 && GET_CODE (x
) == LO_SUM
7217 && GET_CODE (XEXP (x
, 0)) == PLUS
7218 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7219 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7220 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7221 && machopic_operand_p (XEXP (x
, 1)))
7223 /* Result of previous invocation of this function on Darwin
7224 floating point constant. */
7225 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7226 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7227 opnum
, (enum reload_type
) type
);
7233 if (TARGET_CMODEL
!= CMODEL_SMALL
7235 && small_toc_ref (x
, VOIDmode
))
7237 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7238 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7239 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7240 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7241 opnum
, (enum reload_type
) type
);
7246 if (GET_CODE (x
) == PLUS
7247 && GET_CODE (XEXP (x
, 0)) == REG
7248 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7249 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7250 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7252 && !SPE_VECTOR_MODE (mode
)
7253 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7254 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7256 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7257 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7259 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7261 /* Check for 32-bit overflow. */
7262 if (high
+ low
!= val
)
7268 /* Reload the high part into a base reg; leave the low part
7269 in the mem directly. */
7271 x
= gen_rtx_PLUS (GET_MODE (x
),
7272 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7276 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7277 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7278 opnum
, (enum reload_type
) type
);
7283 if (GET_CODE (x
) == SYMBOL_REF
7285 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7286 && !SPE_VECTOR_MODE (mode
)
7288 && DEFAULT_ABI
== ABI_DARWIN
7289 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7290 && machopic_symbol_defined_p (x
)
7292 && DEFAULT_ABI
== ABI_V4
7295 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7296 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7298 ??? Assume floating point reg based on mode? This assumption is
7299 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7300 where reload ends up doing a DFmode load of a constant from
7301 mem using two gprs. Unfortunately, at this point reload
7302 hasn't yet selected regs so poking around in reload data
7303 won't help and even if we could figure out the regs reliably,
7304 we'd still want to allow this transformation when the mem is
7305 naturally aligned. Since we say the address is good here, we
7306 can't disable offsets from LO_SUMs in mem_operand_gpr.
7307 FIXME: Allow offset from lo_sum for other modes too, when
7308 mem is sufficiently aligned. */
7311 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7313 && (mode
!= DImode
|| TARGET_POWERPC64
)
7314 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7315 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7320 rtx offset
= machopic_gen_offset (x
);
7321 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7322 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7323 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7327 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7328 gen_rtx_HIGH (Pmode
, x
), x
);
7330 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7331 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7332 opnum
, (enum reload_type
) type
);
7337 /* Reload an offset address wrapped by an AND that represents the
7338 masking of the lower bits. Strip the outer AND and let reload
7339 convert the offset address into an indirect address. For VSX,
7340 force reload to create the address with an AND in a separate
7341 register, because we can't guarantee an altivec register will
7343 if (VECTOR_MEM_ALTIVEC_P (mode
)
7344 && GET_CODE (x
) == AND
7345 && GET_CODE (XEXP (x
, 0)) == PLUS
7346 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7347 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7348 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7349 && INTVAL (XEXP (x
, 1)) == -16)
7358 && GET_CODE (x
) == SYMBOL_REF
7359 && use_toc_relative_ref (x
))
7361 x
= create_TOC_reference (x
, NULL_RTX
);
7362 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7363 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7364 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7365 opnum
, (enum reload_type
) type
);
7373 /* Debug version of rs6000_legitimize_reload_address. */
7375 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7376 int opnum
, int type
,
7377 int ind_levels
, int *win
)
7379 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7382 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7383 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7384 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7388 fprintf (stderr
, "Same address returned\n");
7390 fprintf (stderr
, "NULL returned\n");
7393 fprintf (stderr
, "New address:\n");
7400 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7401 that is a valid memory address for an instruction.
7402 The MODE argument is the machine mode for the MEM expression
7403 that wants to use this address.
7405 On the RS/6000, there are four valid address: a SYMBOL_REF that
7406 refers to a constant pool entry of an address (or the sum of it
7407 plus a constant), a short (16-bit signed) constant plus a register,
7408 the sum of two registers, or a register indirect, possibly with an
7409 auto-increment. For DFmode, DDmode and DImode with a constant plus
7410 register, we must ensure that both words are addressable or PowerPC64
7411 with offset word aligned.
7413 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7414 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7415 because adjacent memory cells are accessed by adding word-sized offsets
7416 during assembly output. */
7418 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7420 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7422 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7423 if (VECTOR_MEM_ALTIVEC_P (mode
)
7424 && GET_CODE (x
) == AND
7425 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7426 && INTVAL (XEXP (x
, 1)) == -16)
7429 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7431 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7434 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7435 && mode_supports_pre_incdec_p (mode
)
7436 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7438 if (virtual_stack_registers_memory_p (x
))
7440 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7443 && legitimate_constant_pool_address_p (x
, mode
,
7444 reg_ok_strict
|| lra_in_progress
))
7446 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7447 allow register indirect addresses. This will allow the values to go in
7448 either GPRs or VSX registers without reloading. The vector types would
7449 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7450 somewhat split, in that some uses are GPR based, and some VSX based. */
7451 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7453 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7456 && GET_CODE (x
) == PLUS
7457 && GET_CODE (XEXP (x
, 0)) == REG
7458 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7459 || XEXP (x
, 0) == arg_pointer_rtx
)
7460 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7462 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7466 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7468 || (mode
!= DFmode
&& mode
!= DDmode
)
7469 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7470 && (TARGET_POWERPC64
|| mode
!= DImode
)
7471 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7473 && !avoiding_indexed_address_p (mode
)
7474 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7476 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7477 && mode_supports_pre_modify_p (mode
)
7478 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7479 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7480 reg_ok_strict
, false)
7481 || (!avoiding_indexed_address_p (mode
)
7482 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7483 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7485 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7490 /* Debug version of rs6000_legitimate_address_p. */
7492 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7495 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7497 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7498 "strict = %d, reload = %s, code = %s\n",
7499 ret
? "true" : "false",
7500 GET_MODE_NAME (mode
),
7504 : (reload_in_progress
? "progress" : "before")),
7505 GET_RTX_NAME (GET_CODE (x
)));
7511 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7514 rs6000_mode_dependent_address_p (const_rtx addr
,
7515 addr_space_t as ATTRIBUTE_UNUSED
)
7517 return rs6000_mode_dependent_address_ptr (addr
);
7520 /* Go to LABEL if ADDR (a legitimate address expression)
7521 has an effect that depends on the machine mode it is used for.
7523 On the RS/6000 this is true of all integral offsets (since AltiVec
7524 and VSX modes don't allow them) or is a pre-increment or decrement.
7526 ??? Except that due to conceptual problems in offsettable_address_p
7527 we can't really report the problems of integral offsets. So leave
7528 this assuming that the adjustable offset must be valid for the
7529 sub-words of a TFmode operand, which is what we had before. */
7532 rs6000_mode_dependent_address (const_rtx addr
)
7534 switch (GET_CODE (addr
))
7537 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7538 is considered a legitimate address before reload, so there
7539 are no offset restrictions in that case. Note that this
7540 condition is safe in strict mode because any address involving
7541 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7542 been rejected as illegitimate. */
7543 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7544 && XEXP (addr
, 0) != arg_pointer_rtx
7545 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7547 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7548 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7553 /* Anything in the constant pool is sufficiently aligned that
7554 all bytes have the same high part address. */
7555 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7557 /* Auto-increment cases are now treated generically in recog.c. */
7559 return TARGET_UPDATE
;
7561 /* AND is only allowed in Altivec loads. */
7572 /* Debug version of rs6000_mode_dependent_address. */
7574 rs6000_debug_mode_dependent_address (const_rtx addr
)
7576 bool ret
= rs6000_mode_dependent_address (addr
);
7578 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7579 ret
? "true" : "false");
7585 /* Implement FIND_BASE_TERM. */
7588 rs6000_find_base_term (rtx op
)
7593 if (GET_CODE (base
) == CONST
)
7594 base
= XEXP (base
, 0);
7595 if (GET_CODE (base
) == PLUS
)
7596 base
= XEXP (base
, 0);
7597 if (GET_CODE (base
) == UNSPEC
)
7598 switch (XINT (base
, 1))
7601 case UNSPEC_MACHOPIC_OFFSET
:
7602 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7603 for aliasing purposes. */
7604 return XVECEXP (base
, 0, 0);
7610 /* More elaborate version of recog's offsettable_memref_p predicate
7611 that works around the ??? note of rs6000_mode_dependent_address.
7612 In particular it accepts
7614 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7616 in 32-bit mode, that the recog predicate rejects. */
7619 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7626 /* First mimic offsettable_memref_p. */
7627 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7630 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7631 the latter predicate knows nothing about the mode of the memory
7632 reference and, therefore, assumes that it is the largest supported
7633 mode (TFmode). As a consequence, legitimate offsettable memory
7634 references are rejected. rs6000_legitimate_offset_address_p contains
7635 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7636 at least with a little bit of help here given that we know the
7637 actual registers used. */
7638 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7639 || GET_MODE_SIZE (reg_mode
) == 4);
7640 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7644 /* Change register usage conditional on target flags. */
7646 rs6000_conditional_register_usage (void)
7650 if (TARGET_DEBUG_TARGET
)
7651 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7653 /* Set MQ register fixed (already call_used) so that it will not be
7657 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7659 fixed_regs
[13] = call_used_regs
[13]
7660 = call_really_used_regs
[13] = 1;
7662 /* Conditionally disable FPRs. */
7663 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7664 for (i
= 32; i
< 64; i
++)
7665 fixed_regs
[i
] = call_used_regs
[i
]
7666 = call_really_used_regs
[i
] = 1;
7668 /* The TOC register is not killed across calls in a way that is
7669 visible to the compiler. */
7670 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7671 call_really_used_regs
[2] = 0;
7673 if (DEFAULT_ABI
== ABI_V4
7674 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7676 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7678 if (DEFAULT_ABI
== ABI_V4
7679 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7681 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7682 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7683 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7685 if (DEFAULT_ABI
== ABI_DARWIN
7686 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7687 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7688 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7689 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7691 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7692 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7693 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7697 global_regs
[SPEFSCR_REGNO
] = 1;
7698 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7699 registers in prologues and epilogues. We no longer use r14
7700 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7701 pool for link-compatibility with older versions of GCC. Once
7702 "old" code has died out, we can return r14 to the allocation
7705 = call_used_regs
[14]
7706 = call_really_used_regs
[14] = 1;
7709 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7711 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7712 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7713 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7716 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7717 global_regs
[VSCR_REGNO
] = 1;
7719 if (TARGET_ALTIVEC_ABI
)
7721 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7722 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7724 /* AIX reserves VR20:31 in non-extended ABI mode. */
7726 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7727 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7732 /* Try to output insns to set TARGET equal to the constant C if it can
7733 be done in less than N insns. Do all computations in MODE.
7734 Returns the place where the output has been placed if it can be
7735 done and the insns have been emitted. If it would take more than N
7736 insns, zero is returned and no insns and emitted. */
7739 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
7740 rtx source
, int n ATTRIBUTE_UNUSED
)
7742 rtx result
, insn
, set
;
7743 HOST_WIDE_INT c0
, c1
;
7750 dest
= gen_reg_rtx (mode
);
7751 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7755 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7757 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
7758 GEN_INT (INTVAL (source
)
7759 & (~ (HOST_WIDE_INT
) 0xffff))));
7760 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7761 gen_rtx_IOR (SImode
, copy_rtx (result
),
7762 GEN_INT (INTVAL (source
) & 0xffff))));
7767 switch (GET_CODE (source
))
7770 c0
= INTVAL (source
);
7778 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
7785 insn
= get_last_insn ();
7786 set
= single_set (insn
);
7787 if (! CONSTANT_P (SET_SRC (set
)))
7788 set_unique_reg_note (insn
, REG_EQUAL
, source
);
7793 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
7794 fall back to a straight forward decomposition. We do this to avoid
7795 exponential run times encountered when looking for longer sequences
7796 with rs6000_emit_set_const. */
7798 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
7800 if (!TARGET_POWERPC64
)
7802 rtx operand1
, operand2
;
7804 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
7806 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
7808 emit_move_insn (operand1
, GEN_INT (c1
));
7809 emit_move_insn (operand2
, GEN_INT (c2
));
7813 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7816 ud2
= (c1
& 0xffff0000) >> 16;
7819 ud4
= (c2
& 0xffff0000) >> 16;
7821 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7822 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7823 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7825 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7826 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7828 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7831 emit_move_insn (copy_rtx (dest
),
7832 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7835 else if (ud3
== 0 && ud4
== 0)
7837 gcc_assert (ud2
& 0x8000);
7838 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7841 emit_move_insn (copy_rtx (dest
),
7842 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7844 emit_move_insn (copy_rtx (dest
),
7845 gen_rtx_ZERO_EXTEND (DImode
,
7846 gen_lowpart (SImode
,
7849 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7850 || (ud4
== 0 && ! (ud3
& 0x8000)))
7852 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
7855 emit_move_insn (copy_rtx (dest
),
7856 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7858 emit_move_insn (copy_rtx (dest
),
7859 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7862 emit_move_insn (copy_rtx (dest
),
7863 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7868 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
7871 emit_move_insn (copy_rtx (dest
),
7872 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7875 emit_move_insn (copy_rtx (dest
),
7876 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7879 emit_move_insn (copy_rtx (dest
),
7880 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7881 GEN_INT (ud2
<< 16)));
7883 emit_move_insn (copy_rtx (dest
),
7884 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7891 /* Helper for the following. Get rid of [r+r] memory refs
7892 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
7895 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
7897 if (reload_in_progress
)
7900 if (GET_CODE (operands
[0]) == MEM
7901 && GET_CODE (XEXP (operands
[0], 0)) != REG
7902 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
7903 GET_MODE (operands
[0]), false))
7905 = replace_equiv_address (operands
[0],
7906 copy_addr_to_reg (XEXP (operands
[0], 0)));
7908 if (GET_CODE (operands
[1]) == MEM
7909 && GET_CODE (XEXP (operands
[1], 0)) != REG
7910 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
7911 GET_MODE (operands
[1]), false))
7913 = replace_equiv_address (operands
[1],
7914 copy_addr_to_reg (XEXP (operands
[1], 0)));
7917 /* Generate a vector of constants to permute MODE for a little-endian
7918 storage operation by swapping the two halves of a vector. */
7920 rs6000_const_vec (enum machine_mode mode
)
7945 v
= rtvec_alloc (subparts
);
7947 for (i
= 0; i
< subparts
/ 2; ++i
)
7948 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
7949 for (i
= subparts
/ 2; i
< subparts
; ++i
)
7950 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
7955 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
7956 for a VSX load or store operation. */
7958 rs6000_gen_le_vsx_permute (rtx source
, enum machine_mode mode
)
7960 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
7961 return gen_rtx_VEC_SELECT (mode
, source
, par
);
7964 /* Emit a little-endian load from vector memory location SOURCE to VSX
7965 register DEST in mode MODE. The load is done with two permuting
7966 insn's that represent an lxvd2x and xxpermdi. */
7968 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, enum machine_mode mode
)
7970 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
7971 rtx permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
7972 rtx permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
7973 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_mem
));
7974 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_reg
));
7977 /* Emit a little-endian store to vector memory location DEST from VSX
7978 register SOURCE in mode MODE. The store is done with two permuting
7979 insn's that represent an xxpermdi and an stxvd2x. */
7981 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, enum machine_mode mode
)
7983 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
7984 rtx permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
7985 rtx permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
7986 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_src
));
7987 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_tmp
));
7990 /* Emit a sequence representing a little-endian VSX load or store,
7991 moving data from SOURCE to DEST in mode MODE. This is done
7992 separately from rs6000_emit_move to ensure it is called only
7993 during expand. LE VSX loads and stores introduced later are
7994 handled with a split. The expand-time RTL generation allows
7995 us to optimize away redundant pairs of register-permutes. */
7997 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, enum machine_mode mode
)
7999 gcc_assert (!BYTES_BIG_ENDIAN
8000 && VECTOR_MEM_VSX_P (mode
)
8002 && !gpr_or_gpr_p (dest
, source
)
8003 && (MEM_P (source
) ^ MEM_P (dest
)));
8007 gcc_assert (REG_P (dest
));
8008 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8012 if (!REG_P (source
))
8013 source
= force_reg (mode
, source
);
8014 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8018 /* Emit a move from SOURCE to DEST in mode MODE. */
8020 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
8024 operands
[1] = source
;
8026 if (TARGET_DEBUG_ADDR
)
8029 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8030 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8031 GET_MODE_NAME (mode
),
8034 can_create_pseudo_p ());
8036 fprintf (stderr
, "source:\n");
8040 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8041 if (GET_CODE (operands
[1]) == CONST_DOUBLE
8042 && ! FLOAT_MODE_P (mode
)
8043 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8045 /* FIXME. This should never happen. */
8046 /* Since it seems that it does, do the safe thing and convert
8048 operands
[1] = gen_int_mode (CONST_DOUBLE_LOW (operands
[1]), mode
);
8050 gcc_assert (GET_CODE (operands
[1]) != CONST_DOUBLE
8051 || FLOAT_MODE_P (mode
)
8052 || ((CONST_DOUBLE_HIGH (operands
[1]) != 0
8053 || CONST_DOUBLE_LOW (operands
[1]) < 0)
8054 && (CONST_DOUBLE_HIGH (operands
[1]) != -1
8055 || CONST_DOUBLE_LOW (operands
[1]) >= 0)));
8057 /* Check if GCC is setting up a block move that will end up using FP
8058 registers as temporaries. We must make sure this is acceptable. */
8059 if (GET_CODE (operands
[0]) == MEM
8060 && GET_CODE (operands
[1]) == MEM
8062 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8063 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8064 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8065 ? 32 : MEM_ALIGN (operands
[0])))
8066 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8068 : MEM_ALIGN (operands
[1]))))
8069 && ! MEM_VOLATILE_P (operands
[0])
8070 && ! MEM_VOLATILE_P (operands
[1]))
8072 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8073 adjust_address (operands
[1], SImode
, 0));
8074 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8075 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8079 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8080 && !gpc_reg_operand (operands
[1], mode
))
8081 operands
[1] = force_reg (mode
, operands
[1]);
8083 /* Recognize the case where operand[1] is a reference to thread-local
8084 data and load its address to a register. */
8085 if (rs6000_tls_referenced_p (operands
[1]))
8087 enum tls_model model
;
8088 rtx tmp
= operands
[1];
8091 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8093 addend
= XEXP (XEXP (tmp
, 0), 1);
8094 tmp
= XEXP (XEXP (tmp
, 0), 0);
8097 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8098 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8099 gcc_assert (model
!= 0);
8101 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8104 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8105 tmp
= force_operand (tmp
, operands
[0]);
8110 /* Handle the case where reload calls us with an invalid address. */
8111 if (reload_in_progress
&& mode
== Pmode
8112 && (! general_operand (operands
[1], mode
)
8113 || ! nonimmediate_operand (operands
[0], mode
)))
8116 /* 128-bit constant floating-point values on Darwin should really be
8117 loaded as two parts. */
8118 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8119 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8121 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8122 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8124 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8125 GET_MODE_SIZE (DFmode
)),
8126 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8127 GET_MODE_SIZE (DFmode
)),
8132 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8133 cfun
->machine
->sdmode_stack_slot
=
8134 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8139 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8140 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8141 && (REG_P (operands
[1])
8142 || (GET_CODE (operands
[1]) == SUBREG
8143 && REG_P (SUBREG_REG (operands
[1])))))
8145 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8146 ? SUBREG_REG (operands
[1]) : operands
[1]);
8149 if (regno
>= FIRST_PSEUDO_REGISTER
)
8151 cl
= reg_preferred_class (regno
);
8152 gcc_assert (cl
!= NO_REGS
);
8153 regno
= ira_class_hard_regs
[cl
][0];
8155 if (FP_REGNO_P (regno
))
8157 if (GET_MODE (operands
[0]) != DDmode
)
8158 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8159 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8161 else if (INT_REGNO_P (regno
))
8162 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8169 && (REG_P (operands
[0])
8170 || (GET_CODE (operands
[0]) == SUBREG
8171 && REG_P (SUBREG_REG (operands
[0]))))
8172 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8173 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8175 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8176 ? SUBREG_REG (operands
[0]) : operands
[0]);
8179 if (regno
>= FIRST_PSEUDO_REGISTER
)
8181 cl
= reg_preferred_class (regno
);
8182 gcc_assert (cl
!= NO_REGS
);
8183 regno
= ira_class_hard_regs
[cl
][0];
8185 if (FP_REGNO_P (regno
))
8187 if (GET_MODE (operands
[1]) != DDmode
)
8188 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8189 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8191 else if (INT_REGNO_P (regno
))
8192 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8198 if (reload_in_progress
8200 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8201 && MEM_P (operands
[0])
8202 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8203 && REG_P (operands
[1]))
8205 if (FP_REGNO_P (REGNO (operands
[1])))
8207 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8208 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8209 emit_insn (gen_movsd_store (mem
, operands
[1]));
8211 else if (INT_REGNO_P (REGNO (operands
[1])))
8213 rtx mem
= operands
[0];
8214 if (BYTES_BIG_ENDIAN
)
8215 mem
= adjust_address_nv (mem
, mode
, 4);
8216 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8217 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8223 if (reload_in_progress
8225 && REG_P (operands
[0])
8226 && MEM_P (operands
[1])
8227 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8228 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8230 if (FP_REGNO_P (REGNO (operands
[0])))
8232 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8233 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8234 emit_insn (gen_movsd_load (operands
[0], mem
));
8236 else if (INT_REGNO_P (REGNO (operands
[0])))
8238 rtx mem
= operands
[1];
8239 if (BYTES_BIG_ENDIAN
)
8240 mem
= adjust_address_nv (mem
, mode
, 4);
8241 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8242 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8249 /* FIXME: In the long term, this switch statement should go away
8250 and be replaced by a sequence of tests based on things like
8256 if (CONSTANT_P (operands
[1])
8257 && GET_CODE (operands
[1]) != CONST_INT
)
8258 operands
[1] = force_const_mem (mode
, operands
[1]);
8263 rs6000_eliminate_indexed_memrefs (operands
);
8270 if (CONSTANT_P (operands
[1])
8271 && ! easy_fp_constant (operands
[1], mode
))
8272 operands
[1] = force_const_mem (mode
, operands
[1]);
8285 if (CONSTANT_P (operands
[1])
8286 && !easy_vector_constant (operands
[1], mode
))
8287 operands
[1] = force_const_mem (mode
, operands
[1]);
8292 /* Use default pattern for address of ELF small data */
8295 && DEFAULT_ABI
== ABI_V4
8296 && (GET_CODE (operands
[1]) == SYMBOL_REF
8297 || GET_CODE (operands
[1]) == CONST
)
8298 && small_data_operand (operands
[1], mode
))
8300 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8304 if (DEFAULT_ABI
== ABI_V4
8305 && mode
== Pmode
&& mode
== SImode
8306 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8308 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8312 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8316 && CONSTANT_P (operands
[1])
8317 && GET_CODE (operands
[1]) != HIGH
8318 && GET_CODE (operands
[1]) != CONST_INT
)
8320 rtx target
= (!can_create_pseudo_p ()
8322 : gen_reg_rtx (mode
));
8324 /* If this is a function address on -mcall-aixdesc,
8325 convert it to the address of the descriptor. */
8326 if (DEFAULT_ABI
== ABI_AIX
8327 && GET_CODE (operands
[1]) == SYMBOL_REF
8328 && XSTR (operands
[1], 0)[0] == '.')
8330 const char *name
= XSTR (operands
[1], 0);
8332 while (*name
== '.')
8334 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8335 CONSTANT_POOL_ADDRESS_P (new_ref
)
8336 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8337 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8338 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8339 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8340 operands
[1] = new_ref
;
8343 if (DEFAULT_ABI
== ABI_DARWIN
)
8346 if (MACHO_DYNAMIC_NO_PIC_P
)
8348 /* Take care of any required data indirection. */
8349 operands
[1] = rs6000_machopic_legitimize_pic_address (
8350 operands
[1], mode
, operands
[0]);
8351 if (operands
[0] != operands
[1])
8352 emit_insn (gen_rtx_SET (VOIDmode
,
8353 operands
[0], operands
[1]));
8357 emit_insn (gen_macho_high (target
, operands
[1]));
8358 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8362 emit_insn (gen_elf_high (target
, operands
[1]));
8363 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8367 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8368 and we have put it in the TOC, we just need to make a TOC-relative
8371 && GET_CODE (operands
[1]) == SYMBOL_REF
8372 && use_toc_relative_ref (operands
[1]))
8373 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8374 else if (mode
== Pmode
8375 && CONSTANT_P (operands
[1])
8376 && GET_CODE (operands
[1]) != HIGH
8377 && ((GET_CODE (operands
[1]) != CONST_INT
8378 && ! easy_fp_constant (operands
[1], mode
))
8379 || (GET_CODE (operands
[1]) == CONST_INT
8380 && (num_insns_constant (operands
[1], mode
)
8381 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8382 || (GET_CODE (operands
[0]) == REG
8383 && FP_REGNO_P (REGNO (operands
[0]))))
8384 && !toc_relative_expr_p (operands
[1], false)
8385 && (TARGET_CMODEL
== CMODEL_SMALL
8386 || can_create_pseudo_p ()
8387 || (REG_P (operands
[0])
8388 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8392 /* Darwin uses a special PIC legitimizer. */
8393 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8396 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8398 if (operands
[0] != operands
[1])
8399 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8404 /* If we are to limit the number of things we put in the TOC and
8405 this is a symbol plus a constant we can add in one insn,
8406 just put the symbol in the TOC and add the constant. Don't do
8407 this if reload is in progress. */
8408 if (GET_CODE (operands
[1]) == CONST
8409 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8410 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8411 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8412 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8413 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8414 && ! side_effects_p (operands
[0]))
8417 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8418 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8420 sym
= force_reg (mode
, sym
);
8421 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8425 operands
[1] = force_const_mem (mode
, operands
[1]);
8428 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8429 && constant_pool_expr_p (XEXP (operands
[1], 0))
8430 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8431 get_pool_constant (XEXP (operands
[1], 0)),
8432 get_pool_mode (XEXP (operands
[1], 0))))
8434 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8436 operands
[1] = gen_const_mem (mode
, tocref
);
8437 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8443 if (!VECTOR_MEM_VSX_P (TImode
))
8444 rs6000_eliminate_indexed_memrefs (operands
);
8448 rs6000_eliminate_indexed_memrefs (operands
);
8452 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
8455 /* Above, we may have called force_const_mem which may have returned
8456 an invalid address. If we can, fix this up; otherwise, reload will
8457 have to deal with it. */
8458 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8459 operands
[1] = validize_mem (operands
[1]);
8462 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8465 /* Return true if a structure, union or array containing FIELD should be
8466 accessed using `BLKMODE'.
8468 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8469 entire thing in a DI and use subregs to access the internals.
8470 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8471 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8472 best thing to do is set structs to BLKmode and avoid Severe Tire
8475 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8476 fit into 1, whereas DI still needs two. */
8479 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8481 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8482 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8485 /* Nonzero if we can use a floating-point register to pass this arg. */
8486 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8487 (SCALAR_FLOAT_MODE_P (MODE) \
8488 && (CUM)->fregno <= FP_ARG_MAX_REG \
8489 && TARGET_HARD_FLOAT && TARGET_FPRS)
8491 /* Nonzero if we can use an AltiVec register to pass this arg. */
8492 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8493 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8494 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8495 && TARGET_ALTIVEC_ABI \
8498 /* Walk down the type tree of TYPE counting consecutive base elements.
8499 If *MODEP is VOIDmode, then set it to the first valid floating point
8500 or vector type. If a non-floating point or vector type is found, or
8501 if a floating point or vector type that doesn't match a non-VOIDmode
8502 *MODEP is found, then return -1, otherwise return the count in the
8506 rs6000_aggregate_candidate (const_tree type
, enum machine_mode
*modep
)
8508 enum machine_mode mode
;
8511 switch (TREE_CODE (type
))
8514 mode
= TYPE_MODE (type
);
8515 if (!SCALAR_FLOAT_MODE_P (mode
))
8518 if (*modep
== VOIDmode
)
8527 mode
= TYPE_MODE (TREE_TYPE (type
));
8528 if (!SCALAR_FLOAT_MODE_P (mode
))
8531 if (*modep
== VOIDmode
)
8540 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
8543 /* Use V4SImode as representative of all 128-bit vector types. */
8544 size
= int_size_in_bytes (type
);
8554 if (*modep
== VOIDmode
)
8557 /* Vector modes are considered to be opaque: two vectors are
8558 equivalent for the purposes of being homogeneous aggregates
8559 if they are the same size. */
8568 tree index
= TYPE_DOMAIN (type
);
8570 /* Can't handle incomplete types. */
8571 if (!COMPLETE_TYPE_P (type
))
8574 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
8577 || !TYPE_MAX_VALUE (index
)
8578 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
8579 || !TYPE_MIN_VALUE (index
)
8580 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
8584 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
8585 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
8587 /* There must be no padding. */
8588 if (!tree_fits_uhwi_p (TYPE_SIZE (type
))
8589 || ((HOST_WIDE_INT
) tree_to_uhwi (TYPE_SIZE (type
))
8590 != count
* GET_MODE_BITSIZE (*modep
)))
8602 /* Can't handle incomplete types. */
8603 if (!COMPLETE_TYPE_P (type
))
8606 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8608 if (TREE_CODE (field
) != FIELD_DECL
)
8611 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8617 /* There must be no padding. */
8618 if (!tree_fits_uhwi_p (TYPE_SIZE (type
))
8619 || ((HOST_WIDE_INT
) tree_to_uhwi (TYPE_SIZE (type
))
8620 != count
* GET_MODE_BITSIZE (*modep
)))
8627 case QUAL_UNION_TYPE
:
8629 /* These aren't very interesting except in a degenerate case. */
8634 /* Can't handle incomplete types. */
8635 if (!COMPLETE_TYPE_P (type
))
8638 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8640 if (TREE_CODE (field
) != FIELD_DECL
)
8643 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8646 count
= count
> sub_count
? count
: sub_count
;
8649 /* There must be no padding. */
8650 if (!tree_fits_uhwi_p (TYPE_SIZE (type
))
8651 || ((HOST_WIDE_INT
) tree_to_uhwi (TYPE_SIZE (type
))
8652 != count
* GET_MODE_BITSIZE (*modep
)))
8665 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
8666 float or vector aggregate that shall be passed in FP/vector registers
8667 according to the ELFv2 ABI, return the homogeneous element mode in
8668 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
8670 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
8673 rs6000_discover_homogeneous_aggregate (enum machine_mode mode
, const_tree type
,
8674 enum machine_mode
*elt_mode
,
8677 /* Note that we do not accept complex types at the top level as
8678 homogeneous aggregates; these types are handled via the
8679 targetm.calls.split_complex_arg mechanism. Complex types
8680 can be elements of homogeneous aggregates, however. */
8681 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
8683 enum machine_mode field_mode
= VOIDmode
;
8684 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
8686 if (field_count
> 0)
8688 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
)?
8689 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
8691 /* The ELFv2 ABI allows homogeneous aggregates to occupy
8692 up to AGGR_ARG_NUM_REG registers. */
8693 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
8696 *elt_mode
= field_mode
;
8698 *n_elts
= field_count
;
8711 /* Return a nonzero value to say to return the function value in
8712 memory, just as large structures are always returned. TYPE will be
8713 the data type of the value, and FNTYPE will be the type of the
8714 function doing the returning, or @code{NULL} for libcalls.
8716 The AIX ABI for the RS/6000 specifies that all structures are
8717 returned in memory. The Darwin ABI does the same.
8719 For the Darwin 64 Bit ABI, a function result can be returned in
8720 registers or in memory, depending on the size of the return data
8721 type. If it is returned in registers, the value occupies the same
8722 registers as it would if it were the first and only function
8723 argument. Otherwise, the function places its result in memory at
8724 the location pointed to by GPR3.
8726 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8727 but a draft put them in memory, and GCC used to implement the draft
8728 instead of the final standard. Therefore, aix_struct_return
8729 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8730 compatibility can change DRAFT_V4_STRUCT_RET to override the
8731 default, and -m switches get the final word. See
8732 rs6000_option_override_internal for more details.
8734 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8735 long double support is enabled. These values are returned in memory.
8737 int_size_in_bytes returns -1 for variable size objects, which go in
8738 memory always. The cast to unsigned makes -1 > 8. */
8741 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8743 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8745 && rs6000_darwin64_abi
8746 && TREE_CODE (type
) == RECORD_TYPE
8747 && int_size_in_bytes (type
) > 0)
8749 CUMULATIVE_ARGS valcum
;
8753 valcum
.fregno
= FP_ARG_MIN_REG
;
8754 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8755 /* Do a trial code generation as if this were going to be passed
8756 as an argument; if any part goes in memory, we return NULL. */
8757 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8760 /* Otherwise fall through to more conventional ABI rules. */
8763 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
8764 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
8768 /* The ELFv2 ABI returns aggregates up to 16B in registers */
8769 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
8770 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
8773 if (AGGREGATE_TYPE_P (type
)
8774 && (aix_struct_return
8775 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8778 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8779 modes only exist for GCC vector types if -maltivec. */
8780 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8781 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8784 /* Return synthetic vectors in memory. */
8785 if (TREE_CODE (type
) == VECTOR_TYPE
8786 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8788 static bool warned_for_return_big_vectors
= false;
8789 if (!warned_for_return_big_vectors
)
8791 warning (0, "GCC vector returned by reference: "
8792 "non-standard ABI extension with no compatibility guarantee");
8793 warned_for_return_big_vectors
= true;
8798 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8804 /* Specify whether values returned in registers should be at the most
8805 significant end of a register. We want aggregates returned by
8806 value to match the way aggregates are passed to functions. */
8809 rs6000_return_in_msb (const_tree valtype
)
8811 return (DEFAULT_ABI
== ABI_ELFv2
8813 && AGGREGATE_TYPE_P (valtype
)
8814 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
8817 #ifdef HAVE_AS_GNU_ATTRIBUTE
8818 /* Return TRUE if a call to function FNDECL may be one that
8819 potentially affects the function calling ABI of the object file. */
8822 call_ABI_of_interest (tree fndecl
)
8824 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8826 struct cgraph_node
*c_node
;
8828 /* Libcalls are always interesting. */
8829 if (fndecl
== NULL_TREE
)
8832 /* Any call to an external function is interesting. */
8833 if (DECL_EXTERNAL (fndecl
))
8836 /* Interesting functions that we are emitting in this object file. */
8837 c_node
= cgraph_get_node (fndecl
);
8838 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8839 return !cgraph_only_called_directly_p (c_node
);
8845 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8846 for a call to a function whose data type is FNTYPE.
8847 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8849 For incoming args we set the number of arguments in the prototype large
8850 so we never return a PARALLEL. */
8853 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8854 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8855 int libcall
, int n_named_args
,
8856 tree fndecl ATTRIBUTE_UNUSED
,
8857 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8859 static CUMULATIVE_ARGS zero_cumulative
;
8861 *cum
= zero_cumulative
;
8863 cum
->fregno
= FP_ARG_MIN_REG
;
8864 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8865 cum
->prototype
= (fntype
&& prototype_p (fntype
));
8866 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
8867 ? CALL_LIBCALL
: CALL_NORMAL
);
8868 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
8869 cum
->stdarg
= stdarg_p (fntype
);
8871 cum
->nargs_prototype
= 0;
8872 if (incoming
|| cum
->prototype
)
8873 cum
->nargs_prototype
= n_named_args
;
8875 /* Check for a longcall attribute. */
8876 if ((!fntype
&& rs6000_default_long_calls
)
8878 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
8879 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
8880 cum
->call_cookie
|= CALL_LONG
;
8882 if (TARGET_DEBUG_ARG
)
8884 fprintf (stderr
, "\ninit_cumulative_args:");
8887 tree ret_type
= TREE_TYPE (fntype
);
8888 fprintf (stderr
, " ret code = %s,",
8889 get_tree_code_name (TREE_CODE (ret_type
)));
8892 if (cum
->call_cookie
& CALL_LONG
)
8893 fprintf (stderr
, " longcall,");
8895 fprintf (stderr
, " proto = %d, nargs = %d\n",
8896 cum
->prototype
, cum
->nargs_prototype
);
8899 #ifdef HAVE_AS_GNU_ATTRIBUTE
8900 if (DEFAULT_ABI
== ABI_V4
)
8902 cum
->escapes
= call_ABI_of_interest (fndecl
);
8909 return_type
= TREE_TYPE (fntype
);
8910 return_mode
= TYPE_MODE (return_type
);
8913 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
8915 if (return_type
!= NULL
)
8917 if (TREE_CODE (return_type
) == RECORD_TYPE
8918 && TYPE_TRANSPARENT_AGGR (return_type
))
8920 return_type
= TREE_TYPE (first_field (return_type
));
8921 return_mode
= TYPE_MODE (return_type
);
8923 if (AGGREGATE_TYPE_P (return_type
)
8924 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
8926 rs6000_returns_struct
= true;
8928 if (SCALAR_FLOAT_MODE_P (return_mode
))
8929 rs6000_passes_float
= true;
8930 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
8931 || SPE_VECTOR_MODE (return_mode
))
8932 rs6000_passes_vector
= true;
8939 && TARGET_ALTIVEC_ABI
8940 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
8942 error ("cannot return value in vector register because"
8943 " altivec instructions are disabled, use -maltivec"
8948 /* Return true if TYPE must be passed on the stack and not in registers. */
8951 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
8953 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
8954 return must_pass_in_stack_var_size (mode
, type
);
8956 return must_pass_in_stack_var_size_or_pad (mode
, type
);
8959 /* If defined, a C expression which determines whether, and in which
8960 direction, to pad out an argument with extra space. The value
8961 should be of type `enum direction': either `upward' to pad above
8962 the argument, `downward' to pad below, or `none' to inhibit
8965 For the AIX ABI structs are always stored left shifted in their
8969 function_arg_padding (enum machine_mode mode
, const_tree type
)
8971 #ifndef AGGREGATE_PADDING_FIXED
8972 #define AGGREGATE_PADDING_FIXED 0
8974 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
8975 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
8978 if (!AGGREGATE_PADDING_FIXED
)
8980 /* GCC used to pass structures of the same size as integer types as
8981 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
8982 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
8983 passed padded downward, except that -mstrict-align further
8984 muddied the water in that multi-component structures of 2 and 4
8985 bytes in size were passed padded upward.
8987 The following arranges for best compatibility with previous
8988 versions of gcc, but removes the -mstrict-align dependency. */
8989 if (BYTES_BIG_ENDIAN
)
8991 HOST_WIDE_INT size
= 0;
8993 if (mode
== BLKmode
)
8995 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
8996 size
= int_size_in_bytes (type
);
8999 size
= GET_MODE_SIZE (mode
);
9001 if (size
== 1 || size
== 2 || size
== 4)
9007 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
9009 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
9013 /* Fall back to the default. */
9014 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
9017 /* If defined, a C expression that gives the alignment boundary, in bits,
9018 of an argument with the specified mode and type. If it is not defined,
9019 PARM_BOUNDARY is used for all arguments.
9021 V.4 wants long longs and doubles to be double word aligned. Just
9022 testing the mode size is a boneheaded way to do this as it means
9023 that other types such as complex int are also double word aligned.
9024 However, we're stuck with this because changing the ABI might break
9025 existing library interfaces.
9027 Doubleword align SPE vectors.
9028 Quadword align Altivec/VSX vectors.
9029 Quadword align large synthetic vector types. */
9032 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
9034 enum machine_mode elt_mode
;
9037 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9039 if (DEFAULT_ABI
== ABI_V4
9040 && (GET_MODE_SIZE (mode
) == 8
9041 || (TARGET_HARD_FLOAT
9043 && (mode
== TFmode
|| mode
== TDmode
))))
9045 else if (SPE_VECTOR_MODE (mode
)
9046 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9047 && int_size_in_bytes (type
) >= 8
9048 && int_size_in_bytes (type
) < 16))
9050 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9051 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9052 && int_size_in_bytes (type
) >= 16))
9054 else if (((TARGET_MACHO
&& rs6000_darwin64_abi
)
9055 || DEFAULT_ABI
== ABI_ELFv2
9056 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
9058 && type
&& TYPE_ALIGN (type
) > 64)
9061 return PARM_BOUNDARY
;
9064 /* The offset in words to the start of the parameter save area. */
9067 rs6000_parm_offset (void)
9069 return (DEFAULT_ABI
== ABI_V4
? 2
9070 : DEFAULT_ABI
== ABI_ELFv2
? 4
9074 /* For a function parm of MODE and TYPE, return the starting word in
9075 the parameter area. NWORDS of the parameter area are already used. */
9078 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
9079 unsigned int nwords
)
9083 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9084 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9087 /* Compute the size (in words) of a function argument. */
9089 static unsigned long
9090 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
9094 if (mode
!= BLKmode
)
9095 size
= GET_MODE_SIZE (mode
);
9097 size
= int_size_in_bytes (type
);
9100 return (size
+ 3) >> 2;
9102 return (size
+ 7) >> 3;
9105 /* Use this to flush pending int fields. */
9108 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9109 HOST_WIDE_INT bitpos
, int final
)
9111 unsigned int startbit
, endbit
;
9112 int intregs
, intoffset
;
9113 enum machine_mode mode
;
9115 /* Handle the situations where a float is taking up the first half
9116 of the GPR, and the other half is empty (typically due to
9117 alignment restrictions). We can detect this by a 8-byte-aligned
9118 int field, or by seeing that this is the final flush for this
9119 argument. Count the word and continue on. */
9120 if (cum
->floats_in_gpr
== 1
9121 && (cum
->intoffset
% 64 == 0
9122 || (cum
->intoffset
== -1 && final
)))
9125 cum
->floats_in_gpr
= 0;
9128 if (cum
->intoffset
== -1)
9131 intoffset
= cum
->intoffset
;
9132 cum
->intoffset
= -1;
9133 cum
->floats_in_gpr
= 0;
9135 if (intoffset
% BITS_PER_WORD
!= 0)
9137 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9139 if (mode
== BLKmode
)
9141 /* We couldn't find an appropriate mode, which happens,
9142 e.g., in packed structs when there are 3 bytes to load.
9143 Back intoffset back to the beginning of the word in this
9145 intoffset
= intoffset
& -BITS_PER_WORD
;
9149 startbit
= intoffset
& -BITS_PER_WORD
;
9150 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9151 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9152 cum
->words
+= intregs
;
9153 /* words should be unsigned. */
9154 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9156 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9161 /* The darwin64 ABI calls for us to recurse down through structs,
9162 looking for elements passed in registers. Unfortunately, we have
9163 to track int register count here also because of misalignments
9164 in powerpc alignment mode. */
9167 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9169 HOST_WIDE_INT startbitpos
)
9173 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9174 if (TREE_CODE (f
) == FIELD_DECL
)
9176 HOST_WIDE_INT bitpos
= startbitpos
;
9177 tree ftype
= TREE_TYPE (f
);
9178 enum machine_mode mode
;
9179 if (ftype
== error_mark_node
)
9181 mode
= TYPE_MODE (ftype
);
9183 if (DECL_SIZE (f
) != 0
9184 && tree_fits_uhwi_p (bit_position (f
)))
9185 bitpos
+= int_bit_position (f
);
9187 /* ??? FIXME: else assume zero offset. */
9189 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9190 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9191 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9193 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9194 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9195 cum
->fregno
+= n_fpregs
;
9196 /* Single-precision floats present a special problem for
9197 us, because they are smaller than an 8-byte GPR, and so
9198 the structure-packing rules combined with the standard
9199 varargs behavior mean that we want to pack float/float
9200 and float/int combinations into a single register's
9201 space. This is complicated by the arg advance flushing,
9202 which works on arbitrarily large groups of int-type
9206 if (cum
->floats_in_gpr
== 1)
9208 /* Two floats in a word; count the word and reset
9211 cum
->floats_in_gpr
= 0;
9213 else if (bitpos
% 64 == 0)
9215 /* A float at the beginning of an 8-byte word;
9216 count it and put off adjusting cum->words until
9217 we see if a arg advance flush is going to do it
9219 cum
->floats_in_gpr
++;
9223 /* The float is at the end of a word, preceded
9224 by integer fields, so the arg advance flush
9225 just above has already set cum->words and
9226 everything is taken care of. */
9230 cum
->words
+= n_fpregs
;
9232 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9234 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9238 else if (cum
->intoffset
== -1)
9239 cum
->intoffset
= bitpos
;
9243 /* Check for an item that needs to be considered specially under the darwin 64
9244 bit ABI. These are record types where the mode is BLK or the structure is
9247 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
9249 return rs6000_darwin64_abi
9250 && ((mode
== BLKmode
9251 && TREE_CODE (type
) == RECORD_TYPE
9252 && int_size_in_bytes (type
) > 0)
9253 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9254 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9257 /* Update the data in CUM to advance over an argument
9258 of mode MODE and data type TYPE.
9259 (TYPE is null for libcalls where that information may not be available.)
9261 Note that for args passed by reference, function_arg will be called
9262 with MODE and TYPE set to that of the pointer to the arg, not the arg
9266 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9267 const_tree type
, bool named
, int depth
)
9269 enum machine_mode elt_mode
;
9272 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9274 /* Only tick off an argument if we're not recursing. */
9276 cum
->nargs_prototype
--;
9278 #ifdef HAVE_AS_GNU_ATTRIBUTE
9279 if (DEFAULT_ABI
== ABI_V4
9282 if (SCALAR_FLOAT_MODE_P (mode
))
9283 rs6000_passes_float
= true;
9284 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9285 rs6000_passes_vector
= true;
9286 else if (SPE_VECTOR_MODE (mode
)
9288 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9289 rs6000_passes_vector
= true;
9293 if (TARGET_ALTIVEC_ABI
9294 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9295 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9296 && int_size_in_bytes (type
) == 16)))
9300 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9302 cum
->vregno
+= n_elts
;
9304 if (!TARGET_ALTIVEC
)
9305 error ("cannot pass argument in vector register because"
9306 " altivec instructions are disabled, use -maltivec"
9309 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9310 even if it is going to be passed in a vector register.
9311 Darwin does the same for variable-argument functions. */
9312 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9314 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9324 /* Vector parameters must be 16-byte aligned. In 32-bit
9325 mode this means we need to take into account the offset
9326 to the parameter save area. In 64-bit mode, they just
9327 have to start on an even word, since the parameter save
9328 area is 16-byte aligned. */
9330 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9332 align
= cum
->words
& 1;
9333 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9335 if (TARGET_DEBUG_ARG
)
9337 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9339 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9340 cum
->nargs_prototype
, cum
->prototype
,
9341 GET_MODE_NAME (mode
));
9345 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9347 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9350 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9352 int size
= int_size_in_bytes (type
);
9353 /* Variable sized types have size == -1 and are
9354 treated as if consisting entirely of ints.
9355 Pad to 16 byte boundary if needed. */
9356 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9357 && (cum
->words
% 2) != 0)
9359 /* For varargs, we can just go up by the size of the struct. */
9361 cum
->words
+= (size
+ 7) / 8;
9364 /* It is tempting to say int register count just goes up by
9365 sizeof(type)/8, but this is wrong in a case such as
9366 { int; double; int; } [powerpc alignment]. We have to
9367 grovel through the fields for these too. */
9369 cum
->floats_in_gpr
= 0;
9370 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9371 rs6000_darwin64_record_arg_advance_flush (cum
,
9372 size
* BITS_PER_UNIT
, 1);
9374 if (TARGET_DEBUG_ARG
)
9376 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9377 cum
->words
, TYPE_ALIGN (type
), size
);
9379 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9380 cum
->nargs_prototype
, cum
->prototype
,
9381 GET_MODE_NAME (mode
));
9384 else if (DEFAULT_ABI
== ABI_V4
)
9386 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9387 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9388 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9389 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9390 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9392 /* _Decimal128 must use an even/odd register pair. This assumes
9393 that the register number is odd when fregno is odd. */
9394 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9397 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9398 <= FP_ARG_V4_MAX_REG
)
9399 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9402 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9403 if (mode
== DFmode
|| mode
== TFmode
9404 || mode
== DDmode
|| mode
== TDmode
)
9405 cum
->words
+= cum
->words
& 1;
9406 cum
->words
+= rs6000_arg_size (mode
, type
);
9411 int n_words
= rs6000_arg_size (mode
, type
);
9412 int gregno
= cum
->sysv_gregno
;
9414 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9415 (r7,r8) or (r9,r10). As does any other 2 word item such
9416 as complex int due to a historical mistake. */
9418 gregno
+= (1 - gregno
) & 1;
9420 /* Multi-reg args are not split between registers and stack. */
9421 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9423 /* Long long and SPE vectors are aligned on the stack.
9424 So are other 2 word items such as complex int due to
9425 a historical mistake. */
9427 cum
->words
+= cum
->words
& 1;
9428 cum
->words
+= n_words
;
9431 /* Note: continuing to accumulate gregno past when we've started
9432 spilling to the stack indicates the fact that we've started
9433 spilling to the stack to expand_builtin_saveregs. */
9434 cum
->sysv_gregno
= gregno
+ n_words
;
9437 if (TARGET_DEBUG_ARG
)
9439 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9440 cum
->words
, cum
->fregno
);
9441 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9442 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9443 fprintf (stderr
, "mode = %4s, named = %d\n",
9444 GET_MODE_NAME (mode
), named
);
9449 int n_words
= rs6000_arg_size (mode
, type
);
9450 int start_words
= cum
->words
;
9451 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9453 cum
->words
= align_words
+ n_words
;
9455 if (SCALAR_FLOAT_MODE_P (elt_mode
)
9456 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9458 /* _Decimal128 must be passed in an even/odd float register pair.
9459 This assumes that the register number is odd when fregno is
9461 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9463 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
9466 if (TARGET_DEBUG_ARG
)
9468 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9469 cum
->words
, cum
->fregno
);
9470 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9471 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9472 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9473 named
, align_words
- start_words
, depth
);
9479 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
9480 const_tree type
, bool named
)
9482 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
9487 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
9494 r1
= gen_rtx_REG (DImode
, gregno
);
9495 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9496 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
9500 r1
= gen_rtx_REG (DImode
, gregno
);
9501 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9502 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9503 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9504 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
9507 r1
= gen_rtx_REG (DImode
, gregno
);
9508 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9509 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9510 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9511 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
9512 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
9513 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
9514 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
9515 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
9522 /* Determine where to put a SIMD argument on the SPE. */
9524 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9527 int gregno
= cum
->sysv_gregno
;
9529 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9530 are passed and returned in a pair of GPRs for ABI compatibility. */
9531 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
9532 || mode
== DCmode
|| mode
== TCmode
))
9534 int n_words
= rs6000_arg_size (mode
, type
);
9536 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9538 gregno
+= (1 - gregno
) & 1;
9540 /* Multi-reg args are not split between registers and stack. */
9541 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9544 return spe_build_register_parallel (mode
, gregno
);
9548 int n_words
= rs6000_arg_size (mode
, type
);
9550 /* SPE vectors are put in odd registers. */
9551 if (n_words
== 2 && (gregno
& 1) == 0)
9554 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
9557 enum machine_mode m
= SImode
;
9559 r1
= gen_rtx_REG (m
, gregno
);
9560 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
9561 r2
= gen_rtx_REG (m
, gregno
+ 1);
9562 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
9563 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
9570 if (gregno
<= GP_ARG_MAX_REG
)
9571 return gen_rtx_REG (mode
, gregno
);
9577 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9578 structure between cum->intoffset and bitpos to integer registers. */
9581 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
9582 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
9584 enum machine_mode mode
;
9586 unsigned int startbit
, endbit
;
9587 int this_regno
, intregs
, intoffset
;
9590 if (cum
->intoffset
== -1)
9593 intoffset
= cum
->intoffset
;
9594 cum
->intoffset
= -1;
9596 /* If this is the trailing part of a word, try to only load that
9597 much into the register. Otherwise load the whole register. Note
9598 that in the latter case we may pick up unwanted bits. It's not a
9599 problem at the moment but may wish to revisit. */
9601 if (intoffset
% BITS_PER_WORD
!= 0)
9603 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9605 if (mode
== BLKmode
)
9607 /* We couldn't find an appropriate mode, which happens,
9608 e.g., in packed structs when there are 3 bytes to load.
9609 Back intoffset back to the beginning of the word in this
9611 intoffset
= intoffset
& -BITS_PER_WORD
;
9618 startbit
= intoffset
& -BITS_PER_WORD
;
9619 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9620 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9621 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
9623 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
9626 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
9630 intoffset
/= BITS_PER_UNIT
;
9633 regno
= GP_ARG_MIN_REG
+ this_regno
;
9634 reg
= gen_rtx_REG (mode
, regno
);
9636 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
9639 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
9643 while (intregs
> 0);
9646 /* Recursive workhorse for the following. */
9649 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
9650 HOST_WIDE_INT startbitpos
, rtx rvec
[],
9655 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9656 if (TREE_CODE (f
) == FIELD_DECL
)
9658 HOST_WIDE_INT bitpos
= startbitpos
;
9659 tree ftype
= TREE_TYPE (f
);
9660 enum machine_mode mode
;
9661 if (ftype
== error_mark_node
)
9663 mode
= TYPE_MODE (ftype
);
9665 if (DECL_SIZE (f
) != 0
9666 && tree_fits_uhwi_p (bit_position (f
)))
9667 bitpos
+= int_bit_position (f
);
9669 /* ??? FIXME: else assume zero offset. */
9671 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9672 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
9673 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
9675 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9679 case SCmode
: mode
= SFmode
; break;
9680 case DCmode
: mode
= DFmode
; break;
9681 case TCmode
: mode
= TFmode
; break;
9685 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9686 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9688 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9689 && (mode
== TFmode
|| mode
== TDmode
));
9690 /* Long double or _Decimal128 split over regs and memory. */
9691 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
9695 = gen_rtx_EXPR_LIST (VOIDmode
,
9696 gen_rtx_REG (mode
, cum
->fregno
++),
9697 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9698 if (mode
== TFmode
|| mode
== TDmode
)
9701 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9703 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9705 = gen_rtx_EXPR_LIST (VOIDmode
,
9706 gen_rtx_REG (mode
, cum
->vregno
++),
9707 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9709 else if (cum
->intoffset
== -1)
9710 cum
->intoffset
= bitpos
;
9714 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
9715 the register(s) to be used for each field and subfield of a struct
9716 being passed by value, along with the offset of where the
9717 register's value may be found in the block. FP fields go in FP
9718 register, vector fields go in vector registers, and everything
9719 else goes in int registers, packed as in memory.
9721 This code is also used for function return values. RETVAL indicates
9722 whether this is the case.
9724 Much of this is taken from the SPARC V9 port, which has a similar
9725 calling convention. */
9728 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
9729 bool named
, bool retval
)
9731 rtx rvec
[FIRST_PSEUDO_REGISTER
];
9732 int k
= 1, kbase
= 1;
9733 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
9734 /* This is a copy; modifications are not visible to our caller. */
9735 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
9736 CUMULATIVE_ARGS
*cum
= ©_cum
;
9738 /* Pad to 16 byte boundary if needed. */
9739 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9740 && (cum
->words
% 2) != 0)
9747 /* Put entries into rvec[] for individual FP and vector fields, and
9748 for the chunks of memory that go in int regs. Note we start at
9749 element 1; 0 is reserved for an indication of using memory, and
9750 may or may not be filled in below. */
9751 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
9752 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
9754 /* If any part of the struct went on the stack put all of it there.
9755 This hack is because the generic code for
9756 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
9757 parts of the struct are not at the beginning. */
9761 return NULL_RTX
; /* doesn't go in registers at all */
9763 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9765 if (k
> 1 || cum
->use_stack
)
9766 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
9771 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
9774 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
9779 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9781 if (align_words
>= GP_ARG_NUM_REG
)
9784 n_units
= rs6000_arg_size (mode
, type
);
9786 /* Optimize the simple case where the arg fits in one gpr, except in
9787 the case of BLKmode due to assign_parms assuming that registers are
9788 BITS_PER_WORD wide. */
9790 || (n_units
== 1 && mode
!= BLKmode
))
9791 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9794 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
9795 /* Not all of the arg fits in gprs. Say that it goes in memory too,
9796 using a magic NULL_RTX component.
9797 This is not strictly correct. Only some of the arg belongs in
9798 memory, not all of it. However, the normal scheme using
9799 function_arg_partial_nregs can result in unusual subregs, eg.
9800 (subreg:SI (reg:DF) 4), which are not handled well. The code to
9801 store the whole arg to memory is often more efficient than code
9802 to store pieces, and we know that space is available in the right
9803 place for the whole arg. */
9804 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9809 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9810 rtx off
= GEN_INT (i
++ * 4);
9811 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9813 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9815 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9818 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
9819 but must also be copied into the parameter save area starting at
9820 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
9821 to the GPRs and/or memory. Return the number of elements used. */
9824 rs6000_psave_function_arg (enum machine_mode mode
, const_tree type
,
9825 int align_words
, rtx
*rvec
)
9829 if (align_words
< GP_ARG_NUM_REG
)
9831 int n_words
= rs6000_arg_size (mode
, type
);
9833 if (align_words
+ n_words
> GP_ARG_NUM_REG
9835 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9837 /* If this is partially on the stack, then we only
9838 include the portion actually in registers here. */
9839 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9842 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9844 /* Not all of the arg fits in gprs. Say that it goes in memory
9845 too, using a magic NULL_RTX component. Also see comment in
9846 rs6000_mixed_function_arg for why the normal
9847 function_arg_partial_nregs scheme doesn't work in this case. */
9848 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9853 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
9854 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9855 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9857 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9861 /* The whole arg fits in gprs. */
9862 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9863 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9868 /* It's entirely in memory. */
9869 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9875 /* RVEC is a vector of K components of an argument of mode MODE.
9876 Construct the final function_arg return value from it. */
9879 rs6000_finish_function_arg (enum machine_mode mode
, rtx
*rvec
, int k
)
9881 gcc_assert (k
>= 1);
9883 /* Avoid returning a PARALLEL in the trivial cases. */
9886 if (XEXP (rvec
[0], 0) == NULL_RTX
)
9889 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
9890 return XEXP (rvec
[0], 0);
9893 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9896 /* Determine where to put an argument to a function.
9897 Value is zero to push the argument on the stack,
9898 or a hard register in which to store the argument.
9900 MODE is the argument's machine mode.
9901 TYPE is the data type of the argument (as a tree).
9902 This is null for libcalls where that information may
9904 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9905 the preceding args and about the function being called. It is
9906 not modified in this routine.
9907 NAMED is nonzero if this argument is a named parameter
9908 (otherwise it is an extra parameter matching an ellipsis).
9910 On RS/6000 the first eight words of non-FP are normally in registers
9911 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
9912 Under V.4, the first 8 FP args are in registers.
9914 If this is floating-point and no prototype is specified, we use
9915 both an FP and integer register (or possibly FP reg and stack). Library
9916 functions (when CALL_LIBCALL is set) always have the proper types for args,
9917 so we can pass the FP value just in one register. emit_library_function
9918 doesn't support PARALLEL anyway.
9920 Note that for args passed by reference, function_arg will be called
9921 with MODE and TYPE set to that of the pointer to the arg, not the arg
9925 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
9926 const_tree type
, bool named
)
9928 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9929 enum rs6000_abi abi
= DEFAULT_ABI
;
9930 enum machine_mode elt_mode
;
9933 /* Return a marker to indicate whether CR1 needs to set or clear the
9934 bit that V.4 uses to say fp args were passed in registers.
9935 Assume that we don't need the marker for software floating point,
9936 or compiler generated library calls. */
9937 if (mode
== VOIDmode
)
9940 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
9942 || (cum
->nargs_prototype
< 0
9943 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
9945 /* For the SPE, we need to crxor CR6 always. */
9947 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
9948 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9949 return GEN_INT (cum
->call_cookie
9950 | ((cum
->fregno
== FP_ARG_MIN_REG
)
9951 ? CALL_V4_SET_FP_ARGS
9952 : CALL_V4_CLEAR_FP_ARGS
));
9955 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
9958 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9960 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9962 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
9963 if (rslt
!= NULL_RTX
)
9965 /* Else fall through to usual handling. */
9968 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9970 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
9974 /* Do we also need to pass this argument in the parameter
9976 if (TARGET_64BIT
&& ! cum
->prototype
)
9978 int align_words
= (cum
->words
+ 1) & ~1;
9979 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
9982 /* Describe where this argument goes in the vector registers. */
9983 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
9985 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
9986 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
9987 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9990 return rs6000_finish_function_arg (mode
, rvec
, k
);
9992 else if (TARGET_ALTIVEC_ABI
9993 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
9994 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9995 && int_size_in_bytes (type
) == 16)))
9997 if (named
|| abi
== ABI_V4
)
10001 /* Vector parameters to varargs functions under AIX or Darwin
10002 get passed in memory and possibly also in GPRs. */
10003 int align
, align_words
, n_words
;
10004 enum machine_mode part_mode
;
10006 /* Vector parameters must be 16-byte aligned. In 32-bit
10007 mode this means we need to take into account the offset
10008 to the parameter save area. In 64-bit mode, they just
10009 have to start on an even word, since the parameter save
10010 area is 16-byte aligned. */
10012 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
10014 align
= cum
->words
& 1;
10015 align_words
= cum
->words
+ align
;
10017 /* Out of registers? Memory, then. */
10018 if (align_words
>= GP_ARG_NUM_REG
)
10021 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10022 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10024 /* The vector value goes in GPRs. Only the part of the
10025 value in GPRs is reported here. */
10027 n_words
= rs6000_arg_size (mode
, type
);
10028 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10029 /* Fortunately, there are only two possibilities, the value
10030 is either wholly in GPRs or half in GPRs and half not. */
10031 part_mode
= DImode
;
10033 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10036 else if (TARGET_SPE_ABI
&& TARGET_SPE
10037 && (SPE_VECTOR_MODE (mode
)
10038 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10041 || mode
== TCmode
))))
10042 return rs6000_spe_function_arg (cum
, mode
, type
);
10044 else if (abi
== ABI_V4
)
10046 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10047 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10048 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10049 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
10050 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
10052 /* _Decimal128 must use an even/odd register pair. This assumes
10053 that the register number is odd when fregno is odd. */
10054 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10057 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
10058 <= FP_ARG_V4_MAX_REG
)
10059 return gen_rtx_REG (mode
, cum
->fregno
);
10065 int n_words
= rs6000_arg_size (mode
, type
);
10066 int gregno
= cum
->sysv_gregno
;
10068 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10069 (r7,r8) or (r9,r10). As does any other 2 word item such
10070 as complex int due to a historical mistake. */
10072 gregno
+= (1 - gregno
) & 1;
10074 /* Multi-reg args are not split between registers and stack. */
10075 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10078 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10079 return rs6000_mixed_function_arg (mode
, type
,
10080 gregno
- GP_ARG_MIN_REG
);
10081 return gen_rtx_REG (mode
, gregno
);
10086 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10088 /* _Decimal128 must be passed in an even/odd float register pair.
10089 This assumes that the register number is odd when fregno is odd. */
10090 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10093 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10095 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10098 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10100 /* Do we also need to pass this argument in the parameter
10102 if (type
&& (cum
->nargs_prototype
<= 0
10103 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10104 && TARGET_XL_COMPAT
10105 && align_words
>= GP_ARG_NUM_REG
)))
10106 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10108 /* Describe where this argument goes in the fprs. */
10109 for (i
= 0; i
< n_elts
10110 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10112 /* Check if the argument is split over registers and memory.
10113 This can only ever happen for long double or _Decimal128;
10114 complex types are handled via split_complex_arg. */
10115 enum machine_mode fmode
= elt_mode
;
10116 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10118 gcc_assert (fmode
== TFmode
|| fmode
== TDmode
);
10119 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10122 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10123 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10124 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10127 return rs6000_finish_function_arg (mode
, rvec
, k
);
10129 else if (align_words
< GP_ARG_NUM_REG
)
10131 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10132 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10134 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10141 /* For an arg passed partly in registers and partly in memory, this is
10142 the number of bytes passed in registers. For args passed entirely in
10143 registers or entirely in memory, zero. When an arg is described by a
10144 PARALLEL, perhaps using more than one register type, this function
10145 returns the number of bytes used by the first element of the PARALLEL. */
10148 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
10149 tree type
, bool named
)
10151 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10152 bool passed_in_gprs
= true;
10155 enum machine_mode elt_mode
;
10158 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10160 if (DEFAULT_ABI
== ABI_V4
)
10163 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10165 /* If we are passing this arg in the fixed parameter save area
10166 (gprs or memory) as well as VRs, we do not use the partial
10167 bytes mechanism; instead, rs6000_function_arg will return a
10168 PARALLEL including a memory element as necessary. */
10169 if (TARGET_64BIT
&& ! cum
->prototype
)
10172 /* Otherwise, we pass in VRs only. Check for partial copies. */
10173 passed_in_gprs
= false;
10174 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10175 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10178 /* In this complicated case we just disable the partial_nregs code. */
10179 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10182 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10184 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10186 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10188 /* If we are passing this arg in the fixed parameter save area
10189 (gprs or memory) as well as FPRs, we do not use the partial
10190 bytes mechanism; instead, rs6000_function_arg will return a
10191 PARALLEL including a memory element as necessary. */
10193 && (cum
->nargs_prototype
<= 0
10194 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10195 && TARGET_XL_COMPAT
10196 && align_words
>= GP_ARG_NUM_REG
)))
10199 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10200 passed_in_gprs
= false;
10201 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10202 ret
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10203 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10207 && align_words
< GP_ARG_NUM_REG
10208 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10209 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10211 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10212 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10217 /* A C expression that indicates when an argument must be passed by
10218 reference. If nonzero for an argument, a copy of that argument is
10219 made in memory and a pointer to the argument is passed instead of
10220 the argument itself. The pointer is passed in whatever way is
10221 appropriate for passing a pointer to that type.
10223 Under V.4, aggregates and long double are passed by reference.
10225 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10226 reference unless the AltiVec vector extension ABI is in force.
10228 As an extension to all ABIs, variable sized types are passed by
10232 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10233 enum machine_mode mode
, const_tree type
,
10234 bool named ATTRIBUTE_UNUSED
)
10236 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
10238 if (TARGET_DEBUG_ARG
)
10239 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
10246 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10248 if (TARGET_DEBUG_ARG
)
10249 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10253 if (int_size_in_bytes (type
) < 0)
10255 if (TARGET_DEBUG_ARG
)
10256 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10260 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10261 modes only exist for GCC vector types if -maltivec. */
10262 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10264 if (TARGET_DEBUG_ARG
)
10265 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10269 /* Pass synthetic vectors in memory. */
10270 if (TREE_CODE (type
) == VECTOR_TYPE
10271 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10273 static bool warned_for_pass_big_vectors
= false;
10274 if (TARGET_DEBUG_ARG
)
10275 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10276 if (!warned_for_pass_big_vectors
)
10278 warning (0, "GCC vector passed by reference: "
10279 "non-standard ABI extension with no compatibility guarantee");
10280 warned_for_pass_big_vectors
= true;
10288 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10289 already processes. Return true if the parameter must be passed
10290 (fully or partially) on the stack. */
10293 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10295 enum machine_mode mode
;
10299 /* Catch errors. */
10300 if (type
== NULL
|| type
== error_mark_node
)
10303 /* Handle types with no storage requirement. */
10304 if (TYPE_MODE (type
) == VOIDmode
)
10307 /* Handle complex types. */
10308 if (TREE_CODE (type
) == COMPLEX_TYPE
)
10309 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
10310 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
10312 /* Handle transparent aggregates. */
10313 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
10314 && TYPE_TRANSPARENT_AGGR (type
))
10315 type
= TREE_TYPE (first_field (type
));
10317 /* See if this arg was passed by invisible reference. */
10318 if (pass_by_reference (get_cumulative_args (args_so_far
),
10319 TYPE_MODE (type
), type
, true))
10320 type
= build_pointer_type (type
);
10322 /* Find mode as it is passed by the ABI. */
10323 unsignedp
= TYPE_UNSIGNED (type
);
10324 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
10326 /* If we must pass in stack, we need a stack. */
10327 if (rs6000_must_pass_in_stack (mode
, type
))
10330 /* If there is no incoming register, we need a stack. */
10331 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
10332 if (entry_parm
== NULL
)
10335 /* Likewise if we need to pass both in registers and on the stack. */
10336 if (GET_CODE (entry_parm
) == PARALLEL
10337 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
10340 /* Also true if we're partially in registers and partially not. */
10341 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
10344 /* Update info on where next arg arrives in registers. */
10345 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
10349 /* Return true if FUN has no prototype, has a variable argument
10350 list, or passes any parameter in memory. */
10353 rs6000_function_parms_need_stack (tree fun
)
10355 function_args_iterator args_iter
;
10357 CUMULATIVE_ARGS args_so_far_v
;
10358 cumulative_args_t args_so_far
;
10361 /* Must be a libcall, all of which only use reg parms. */
10364 fun
= TREE_TYPE (fun
);
10366 /* Varargs functions need the parameter save area. */
10367 if (!prototype_p (fun
) || stdarg_p (fun
))
10370 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fun
, NULL_RTX
);
10371 args_so_far
= pack_cumulative_args (&args_so_far_v
);
10373 if (aggregate_value_p (TREE_TYPE (fun
), fun
))
10375 tree type
= build_pointer_type (TREE_TYPE (fun
));
10376 rs6000_parm_needs_stack (args_so_far
, type
);
10379 FOREACH_FUNCTION_ARGS (fun
, arg_type
, args_iter
)
10380 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
10386 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10387 usually a constant depending on the ABI. However, in the ELFv2 ABI
10388 the register parameter area is optional when calling a function that
10389 has a prototype is scope, has no variable argument list, and passes
10390 all parameters in registers. */
10393 rs6000_reg_parm_stack_space (tree fun
)
10395 int reg_parm_stack_space
;
10397 switch (DEFAULT_ABI
)
10400 reg_parm_stack_space
= 0;
10405 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10409 /* ??? Recomputing this every time is a bit expensive. Is there
10410 a place to cache this information? */
10411 if (rs6000_function_parms_need_stack (fun
))
10412 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10414 reg_parm_stack_space
= 0;
10418 return reg_parm_stack_space
;
10422 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
10425 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
10430 for (i
= 0; i
< nregs
; i
++)
10432 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
10433 if (reload_completed
)
10435 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
10438 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
10439 i
* GET_MODE_SIZE (reg_mode
));
10442 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
10446 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
10450 /* Perform any needed actions needed for a function that is receiving a
10451 variable number of arguments.
10455 MODE and TYPE are the mode and type of the current parameter.
10457 PRETEND_SIZE is a variable that should be set to the amount of stack
10458 that must be pushed by the prolog to pretend that our caller pushed
10461 Normally, this macro will push all remaining incoming registers on the
10462 stack and set PRETEND_SIZE to the length of the registers pushed. */
10465 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
10466 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
10469 CUMULATIVE_ARGS next_cum
;
10470 int reg_size
= TARGET_32BIT
? 4 : 8;
10471 rtx save_area
= NULL_RTX
, mem
;
10472 int first_reg_offset
;
10473 alias_set_type set
;
10475 /* Skip the last named argument. */
10476 next_cum
= *get_cumulative_args (cum
);
10477 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
10479 if (DEFAULT_ABI
== ABI_V4
)
10481 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
10485 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
10486 HOST_WIDE_INT offset
= 0;
10488 /* Try to optimize the size of the varargs save area.
10489 The ABI requires that ap.reg_save_area is doubleword
10490 aligned, but we don't need to allocate space for all
10491 the bytes, only those to which we actually will save
10493 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
10494 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
10495 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10496 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10497 && cfun
->va_list_fpr_size
)
10500 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
10501 * UNITS_PER_FP_WORD
;
10502 if (cfun
->va_list_fpr_size
10503 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10504 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
10506 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10507 * UNITS_PER_FP_WORD
;
10511 offset
= -((first_reg_offset
* reg_size
) & ~7);
10512 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
10514 gpr_reg_num
= cfun
->va_list_gpr_size
;
10515 if (reg_size
== 4 && (first_reg_offset
& 1))
10518 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
10521 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
10522 * UNITS_PER_FP_WORD
10523 - (int) (GP_ARG_NUM_REG
* reg_size
);
10525 if (gpr_size
+ fpr_size
)
10528 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
10529 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
10530 reg_save_area
= XEXP (reg_save_area
, 0);
10531 if (GET_CODE (reg_save_area
) == PLUS
)
10533 gcc_assert (XEXP (reg_save_area
, 0)
10534 == virtual_stack_vars_rtx
);
10535 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
10536 offset
+= INTVAL (XEXP (reg_save_area
, 1));
10539 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
10542 cfun
->machine
->varargs_save_offset
= offset
;
10543 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
10548 first_reg_offset
= next_cum
.words
;
10549 save_area
= virtual_incoming_args_rtx
;
10551 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
10552 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
10555 set
= get_varargs_alias_set ();
10556 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
10557 && cfun
->va_list_gpr_size
)
10559 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
10561 if (va_list_gpr_counter_field
)
10562 /* V4 va_list_gpr_size counts number of registers needed. */
10563 n_gpr
= cfun
->va_list_gpr_size
;
10565 /* char * va_list instead counts number of bytes needed. */
10566 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
10571 mem
= gen_rtx_MEM (BLKmode
,
10572 plus_constant (Pmode
, save_area
,
10573 first_reg_offset
* reg_size
));
10574 MEM_NOTRAP_P (mem
) = 1;
10575 set_mem_alias_set (mem
, set
);
10576 set_mem_align (mem
, BITS_PER_WORD
);
10578 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
10582 /* Save FP registers if needed. */
10583 if (DEFAULT_ABI
== ABI_V4
10584 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10586 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10587 && cfun
->va_list_fpr_size
)
10589 int fregno
= next_cum
.fregno
, nregs
;
10590 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
10591 rtx lab
= gen_label_rtx ();
10592 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
10593 * UNITS_PER_FP_WORD
);
10596 (gen_rtx_SET (VOIDmode
,
10598 gen_rtx_IF_THEN_ELSE (VOIDmode
,
10599 gen_rtx_NE (VOIDmode
, cr1
,
10601 gen_rtx_LABEL_REF (VOIDmode
, lab
),
10605 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
10606 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
10608 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10610 plus_constant (Pmode
, save_area
, off
));
10611 MEM_NOTRAP_P (mem
) = 1;
10612 set_mem_alias_set (mem
, set
);
10613 set_mem_align (mem
, GET_MODE_ALIGNMENT (
10614 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10615 ? DFmode
: SFmode
));
10616 emit_move_insn (mem
, gen_rtx_REG (
10617 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10618 ? DFmode
: SFmode
, fregno
));
10625 /* Create the va_list data type. */
10628 rs6000_build_builtin_va_list (void)
10630 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
10632 /* For AIX, prefer 'char *' because that's what the system
10633 header files like. */
10634 if (DEFAULT_ABI
!= ABI_V4
)
10635 return build_pointer_type (char_type_node
);
10637 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
10638 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
10639 get_identifier ("__va_list_tag"), record
);
10641 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
10642 unsigned_char_type_node
);
10643 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
10644 unsigned_char_type_node
);
10645 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
10646 every user file. */
10647 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10648 get_identifier ("reserved"), short_unsigned_type_node
);
10649 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10650 get_identifier ("overflow_arg_area"),
10652 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10653 get_identifier ("reg_save_area"),
10656 va_list_gpr_counter_field
= f_gpr
;
10657 va_list_fpr_counter_field
= f_fpr
;
10659 DECL_FIELD_CONTEXT (f_gpr
) = record
;
10660 DECL_FIELD_CONTEXT (f_fpr
) = record
;
10661 DECL_FIELD_CONTEXT (f_res
) = record
;
10662 DECL_FIELD_CONTEXT (f_ovf
) = record
;
10663 DECL_FIELD_CONTEXT (f_sav
) = record
;
10665 TYPE_STUB_DECL (record
) = type_decl
;
10666 TYPE_NAME (record
) = type_decl
;
10667 TYPE_FIELDS (record
) = f_gpr
;
10668 DECL_CHAIN (f_gpr
) = f_fpr
;
10669 DECL_CHAIN (f_fpr
) = f_res
;
10670 DECL_CHAIN (f_res
) = f_ovf
;
10671 DECL_CHAIN (f_ovf
) = f_sav
;
10673 layout_type (record
);
10675 /* The correct type is an array type of one element. */
10676 return build_array_type (record
, build_index_type (size_zero_node
));
10679 /* Implement va_start. */
10682 rs6000_va_start (tree valist
, rtx nextarg
)
10684 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
10685 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10686 tree gpr
, fpr
, ovf
, sav
, t
;
10688 /* Only SVR4 needs something special. */
10689 if (DEFAULT_ABI
!= ABI_V4
)
10691 std_expand_builtin_va_start (valist
, nextarg
);
10695 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10696 f_fpr
= DECL_CHAIN (f_gpr
);
10697 f_res
= DECL_CHAIN (f_fpr
);
10698 f_ovf
= DECL_CHAIN (f_res
);
10699 f_sav
= DECL_CHAIN (f_ovf
);
10701 valist
= build_simple_mem_ref (valist
);
10702 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10703 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10705 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10707 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10710 /* Count number of gp and fp argument registers used. */
10711 words
= crtl
->args
.info
.words
;
10712 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
10714 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
10717 if (TARGET_DEBUG_ARG
)
10718 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
10719 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
10720 words
, n_gpr
, n_fpr
);
10722 if (cfun
->va_list_gpr_size
)
10724 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
10725 build_int_cst (NULL_TREE
, n_gpr
));
10726 TREE_SIDE_EFFECTS (t
) = 1;
10727 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10730 if (cfun
->va_list_fpr_size
)
10732 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
10733 build_int_cst (NULL_TREE
, n_fpr
));
10734 TREE_SIDE_EFFECTS (t
) = 1;
10735 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10737 #ifdef HAVE_AS_GNU_ATTRIBUTE
10738 if (call_ABI_of_interest (cfun
->decl
))
10739 rs6000_passes_float
= true;
10743 /* Find the overflow area. */
10744 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
10746 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
10747 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
10748 TREE_SIDE_EFFECTS (t
) = 1;
10749 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10751 /* If there were no va_arg invocations, don't set up the register
10753 if (!cfun
->va_list_gpr_size
10754 && !cfun
->va_list_fpr_size
10755 && n_gpr
< GP_ARG_NUM_REG
10756 && n_fpr
< FP_ARG_V4_MAX_REG
)
10759 /* Find the register save area. */
10760 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
10761 if (cfun
->machine
->varargs_save_offset
)
10762 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
10763 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
10764 TREE_SIDE_EFFECTS (t
) = 1;
10765 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10768 /* Implement va_arg. */
10771 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
10772 gimple_seq
*post_p
)
10774 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10775 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
10776 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
10777 tree lab_false
, lab_over
, addr
;
10779 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
10783 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
10785 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
10786 return build_va_arg_indirect_ref (t
);
10789 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
10790 earlier version of gcc, with the property that it always applied alignment
10791 adjustments to the va-args (even for zero-sized types). The cheapest way
10792 to deal with this is to replicate the effect of the part of
10793 std_gimplify_va_arg_expr that carries out the align adjust, for the case
10795 We don't need to check for pass-by-reference because of the test above.
10796 We can return a simplifed answer, since we know there's no offset to add. */
10799 && rs6000_darwin64_abi
)
10800 || DEFAULT_ABI
== ABI_ELFv2
10801 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
10802 && integer_zerop (TYPE_SIZE (type
)))
10804 unsigned HOST_WIDE_INT align
, boundary
;
10805 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
10806 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
10807 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
10808 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
10809 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
10810 boundary
/= BITS_PER_UNIT
;
10811 if (boundary
> align
)
10814 /* This updates arg ptr by the amount that would be necessary
10815 to align the zero-sized (but not zero-alignment) item. */
10816 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10817 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
10818 gimplify_and_add (t
, pre_p
);
10820 t
= fold_convert (sizetype
, valist_tmp
);
10821 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10822 fold_convert (TREE_TYPE (valist
),
10823 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
10824 size_int (-boundary
))));
10825 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
10826 gimplify_and_add (t
, pre_p
);
10828 /* Since it is zero-sized there's no increment for the item itself. */
10829 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
10830 return build_va_arg_indirect_ref (valist_tmp
);
10833 if (DEFAULT_ABI
!= ABI_V4
)
10835 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
10837 tree elem_type
= TREE_TYPE (type
);
10838 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
10839 int elem_size
= GET_MODE_SIZE (elem_mode
);
10841 if (elem_size
< UNITS_PER_WORD
)
10843 tree real_part
, imag_part
;
10844 gimple_seq post
= NULL
;
10846 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10848 /* Copy the value into a temporary, lest the formal temporary
10849 be reused out from under us. */
10850 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
10851 gimple_seq_add_seq (pre_p
, post
);
10853 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10856 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
10860 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
10863 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10864 f_fpr
= DECL_CHAIN (f_gpr
);
10865 f_res
= DECL_CHAIN (f_fpr
);
10866 f_ovf
= DECL_CHAIN (f_res
);
10867 f_sav
= DECL_CHAIN (f_ovf
);
10869 valist
= build_va_arg_indirect_ref (valist
);
10870 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10871 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10873 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10875 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10878 size
= int_size_in_bytes (type
);
10879 rsize
= (size
+ 3) / 4;
10882 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10883 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
10884 || (TARGET_DOUBLE_FLOAT
10885 && (TYPE_MODE (type
) == DFmode
10886 || TYPE_MODE (type
) == TFmode
10887 || TYPE_MODE (type
) == SDmode
10888 || TYPE_MODE (type
) == DDmode
10889 || TYPE_MODE (type
) == TDmode
))))
10891 /* FP args go in FP registers, if present. */
10893 n_reg
= (size
+ 7) / 8;
10894 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
10895 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
10896 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
10901 /* Otherwise into GP registers. */
10910 /* Pull the value out of the saved registers.... */
10913 addr
= create_tmp_var (ptr_type_node
, "addr");
10915 /* AltiVec vectors never go in registers when -mabi=altivec. */
10916 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
10920 lab_false
= create_artificial_label (input_location
);
10921 lab_over
= create_artificial_label (input_location
);
10923 /* Long long and SPE vectors are aligned in the registers.
10924 As are any other 2 gpr item such as complex int due to a
10925 historical mistake. */
10927 if (n_reg
== 2 && reg
== gpr
)
10930 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10931 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
10932 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
10933 unshare_expr (reg
), u
);
10935 /* _Decimal128 is passed in even/odd fpr pairs; the stored
10936 reg number is 0 for f1, so we want to make it odd. */
10937 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
10939 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10940 build_int_cst (TREE_TYPE (reg
), 1));
10941 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
10944 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
10945 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
10946 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
10947 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
10948 gimplify_and_add (t
, pre_p
);
10952 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
10954 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10955 build_int_cst (TREE_TYPE (reg
), n_reg
));
10956 u
= fold_convert (sizetype
, u
);
10957 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
10958 t
= fold_build_pointer_plus (t
, u
);
10960 /* _Decimal32 varargs are located in the second word of the 64-bit
10961 FP register for 32-bit binaries. */
10962 if (!TARGET_POWERPC64
10963 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10964 && TYPE_MODE (type
) == SDmode
)
10965 t
= fold_build_pointer_plus_hwi (t
, size
);
10967 gimplify_assign (addr
, t
, pre_p
);
10969 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
10971 stmt
= gimple_build_label (lab_false
);
10972 gimple_seq_add_stmt (pre_p
, stmt
);
10974 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
10976 /* Ensure that we don't find any more args in regs.
10977 Alignment has taken care of for special cases. */
10978 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
10982 /* ... otherwise out of the overflow area. */
10984 /* Care for on-stack alignment if needed. */
10988 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
10989 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
10990 build_int_cst (TREE_TYPE (t
), -align
));
10992 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
10994 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
10996 t
= fold_build_pointer_plus_hwi (t
, size
);
10997 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
11001 stmt
= gimple_build_label (lab_over
);
11002 gimple_seq_add_stmt (pre_p
, stmt
);
11005 if (STRICT_ALIGNMENT
11006 && (TYPE_ALIGN (type
)
11007 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
11009 /* The value (of type complex double, for example) may not be
11010 aligned in memory in the saved registers, so copy via a
11011 temporary. (This is the same code as used for SPARC.) */
11012 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
11013 tree dest_addr
= build_fold_addr_expr (tmp
);
11015 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
11016 3, dest_addr
, addr
, size_int (rsize
* 4));
11018 gimplify_and_add (copy
, pre_p
);
11022 addr
= fold_convert (ptrtype
, addr
);
11023 return build_va_arg_indirect_ref (addr
);
11029 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11032 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11033 const char *attr_string
= "";
11035 gcc_assert (name
!= NULL
);
11036 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11038 if (rs6000_builtin_decls
[(int)code
])
11039 fatal_error ("internal error: builtin function %s already processed", name
);
11041 rs6000_builtin_decls
[(int)code
] = t
=
11042 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11044 /* Set any special attributes. */
11045 if ((classify
& RS6000_BTC_CONST
) != 0)
11047 /* const function, function only depends on the inputs. */
11048 TREE_READONLY (t
) = 1;
11049 TREE_NOTHROW (t
) = 1;
11050 attr_string
= ", pure";
11052 else if ((classify
& RS6000_BTC_PURE
) != 0)
11054 /* pure function, function can read global memory, but does not set any
11056 DECL_PURE_P (t
) = 1;
11057 TREE_NOTHROW (t
) = 1;
11058 attr_string
= ", const";
11060 else if ((classify
& RS6000_BTC_FP
) != 0)
11062 /* Function is a math function. If rounding mode is on, then treat the
11063 function as not reading global memory, but it can have arbitrary side
11064 effects. If it is off, then assume the function is a const function.
11065 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11066 builtin-attribute.def that is used for the math functions. */
11067 TREE_NOTHROW (t
) = 1;
11068 if (flag_rounding_math
)
11070 DECL_PURE_P (t
) = 1;
11071 DECL_IS_NOVOPS (t
) = 1;
11072 attr_string
= ", fp, pure";
11076 TREE_READONLY (t
) = 1;
11077 attr_string
= ", fp, const";
11080 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11081 gcc_unreachable ();
11083 if (TARGET_DEBUG_BUILTIN
)
11084 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11085 (int)code
, name
, attr_string
);
11088 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11090 #undef RS6000_BUILTIN_1
11091 #undef RS6000_BUILTIN_2
11092 #undef RS6000_BUILTIN_3
11093 #undef RS6000_BUILTIN_A
11094 #undef RS6000_BUILTIN_D
11095 #undef RS6000_BUILTIN_E
11096 #undef RS6000_BUILTIN_H
11097 #undef RS6000_BUILTIN_P
11098 #undef RS6000_BUILTIN_Q
11099 #undef RS6000_BUILTIN_S
11100 #undef RS6000_BUILTIN_X
11102 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11103 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11104 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11105 { MASK, ICODE, NAME, ENUM },
11107 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11108 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11109 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11110 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11111 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11112 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11113 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11114 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11116 static const struct builtin_description bdesc_3arg
[] =
11118 #include "rs6000-builtin.def"
11121 /* DST operations: void foo (void *, const int, const char). */
11123 #undef RS6000_BUILTIN_1
11124 #undef RS6000_BUILTIN_2
11125 #undef RS6000_BUILTIN_3
11126 #undef RS6000_BUILTIN_A
11127 #undef RS6000_BUILTIN_D
11128 #undef RS6000_BUILTIN_E
11129 #undef RS6000_BUILTIN_H
11130 #undef RS6000_BUILTIN_P
11131 #undef RS6000_BUILTIN_Q
11132 #undef RS6000_BUILTIN_S
11133 #undef RS6000_BUILTIN_X
11135 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11136 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11137 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11138 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11139 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11140 { MASK, ICODE, NAME, ENUM },
11142 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11143 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11144 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11145 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11146 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11147 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11149 static const struct builtin_description bdesc_dst
[] =
11151 #include "rs6000-builtin.def"
11154 /* Simple binary operations: VECc = foo (VECa, VECb). */
11156 #undef RS6000_BUILTIN_1
11157 #undef RS6000_BUILTIN_2
11158 #undef RS6000_BUILTIN_3
11159 #undef RS6000_BUILTIN_A
11160 #undef RS6000_BUILTIN_D
11161 #undef RS6000_BUILTIN_E
11162 #undef RS6000_BUILTIN_H
11163 #undef RS6000_BUILTIN_P
11164 #undef RS6000_BUILTIN_Q
11165 #undef RS6000_BUILTIN_S
11166 #undef RS6000_BUILTIN_X
11168 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11169 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11170 { MASK, ICODE, NAME, ENUM },
11172 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11173 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11174 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11175 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11176 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11177 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11178 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11179 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11180 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11182 static const struct builtin_description bdesc_2arg
[] =
11184 #include "rs6000-builtin.def"
11187 #undef RS6000_BUILTIN_1
11188 #undef RS6000_BUILTIN_2
11189 #undef RS6000_BUILTIN_3
11190 #undef RS6000_BUILTIN_A
11191 #undef RS6000_BUILTIN_D
11192 #undef RS6000_BUILTIN_E
11193 #undef RS6000_BUILTIN_H
11194 #undef RS6000_BUILTIN_P
11195 #undef RS6000_BUILTIN_Q
11196 #undef RS6000_BUILTIN_S
11197 #undef RS6000_BUILTIN_X
11199 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11200 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11201 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11202 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11203 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11204 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11205 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11206 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11207 { MASK, ICODE, NAME, ENUM },
11209 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11210 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11211 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11213 /* AltiVec predicates. */
11215 static const struct builtin_description bdesc_altivec_preds
[] =
11217 #include "rs6000-builtin.def"
11220 /* SPE predicates. */
11221 #undef RS6000_BUILTIN_1
11222 #undef RS6000_BUILTIN_2
11223 #undef RS6000_BUILTIN_3
11224 #undef RS6000_BUILTIN_A
11225 #undef RS6000_BUILTIN_D
11226 #undef RS6000_BUILTIN_E
11227 #undef RS6000_BUILTIN_H
11228 #undef RS6000_BUILTIN_P
11229 #undef RS6000_BUILTIN_Q
11230 #undef RS6000_BUILTIN_S
11231 #undef RS6000_BUILTIN_X
11233 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11234 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11235 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11236 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11237 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11238 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11239 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11240 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11241 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11242 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11243 { MASK, ICODE, NAME, ENUM },
11245 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11247 static const struct builtin_description bdesc_spe_predicates
[] =
11249 #include "rs6000-builtin.def"
11252 /* SPE evsel predicates. */
11253 #undef RS6000_BUILTIN_1
11254 #undef RS6000_BUILTIN_2
11255 #undef RS6000_BUILTIN_3
11256 #undef RS6000_BUILTIN_A
11257 #undef RS6000_BUILTIN_D
11258 #undef RS6000_BUILTIN_E
11259 #undef RS6000_BUILTIN_H
11260 #undef RS6000_BUILTIN_P
11261 #undef RS6000_BUILTIN_Q
11262 #undef RS6000_BUILTIN_S
11263 #undef RS6000_BUILTIN_X
11265 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11266 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11267 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11268 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11269 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11270 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11271 { MASK, ICODE, NAME, ENUM },
11273 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11274 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11275 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11276 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11277 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11279 static const struct builtin_description bdesc_spe_evsel
[] =
11281 #include "rs6000-builtin.def"
11284 /* PAIRED predicates. */
11285 #undef RS6000_BUILTIN_1
11286 #undef RS6000_BUILTIN_2
11287 #undef RS6000_BUILTIN_3
11288 #undef RS6000_BUILTIN_A
11289 #undef RS6000_BUILTIN_D
11290 #undef RS6000_BUILTIN_E
11291 #undef RS6000_BUILTIN_H
11292 #undef RS6000_BUILTIN_P
11293 #undef RS6000_BUILTIN_Q
11294 #undef RS6000_BUILTIN_S
11295 #undef RS6000_BUILTIN_X
11297 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11298 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11299 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11300 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11301 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11302 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11303 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11304 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11305 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11306 { MASK, ICODE, NAME, ENUM },
11308 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11309 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11311 static const struct builtin_description bdesc_paired_preds
[] =
11313 #include "rs6000-builtin.def"
11316 /* ABS* operations. */
11318 #undef RS6000_BUILTIN_1
11319 #undef RS6000_BUILTIN_2
11320 #undef RS6000_BUILTIN_3
11321 #undef RS6000_BUILTIN_A
11322 #undef RS6000_BUILTIN_D
11323 #undef RS6000_BUILTIN_E
11324 #undef RS6000_BUILTIN_H
11325 #undef RS6000_BUILTIN_P
11326 #undef RS6000_BUILTIN_Q
11327 #undef RS6000_BUILTIN_S
11328 #undef RS6000_BUILTIN_X
11330 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11331 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11332 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11333 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11334 { MASK, ICODE, NAME, ENUM },
11336 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11337 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11338 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11339 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11340 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11341 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11342 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11344 static const struct builtin_description bdesc_abs
[] =
11346 #include "rs6000-builtin.def"
11349 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11352 #undef RS6000_BUILTIN_1
11353 #undef RS6000_BUILTIN_2
11354 #undef RS6000_BUILTIN_3
11355 #undef RS6000_BUILTIN_A
11356 #undef RS6000_BUILTIN_D
11357 #undef RS6000_BUILTIN_E
11358 #undef RS6000_BUILTIN_H
11359 #undef RS6000_BUILTIN_P
11360 #undef RS6000_BUILTIN_Q
11361 #undef RS6000_BUILTIN_S
11362 #undef RS6000_BUILTIN_X
11364 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11365 { MASK, ICODE, NAME, ENUM },
11367 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11368 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11369 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11370 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11371 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11372 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11373 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11374 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11375 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11376 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11378 static const struct builtin_description bdesc_1arg
[] =
11380 #include "rs6000-builtin.def"
11383 /* HTM builtins. */
11384 #undef RS6000_BUILTIN_1
11385 #undef RS6000_BUILTIN_2
11386 #undef RS6000_BUILTIN_3
11387 #undef RS6000_BUILTIN_A
11388 #undef RS6000_BUILTIN_D
11389 #undef RS6000_BUILTIN_E
11390 #undef RS6000_BUILTIN_H
11391 #undef RS6000_BUILTIN_P
11392 #undef RS6000_BUILTIN_Q
11393 #undef RS6000_BUILTIN_S
11394 #undef RS6000_BUILTIN_X
11396 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11397 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11398 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11399 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11400 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11401 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11402 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
11403 { MASK, ICODE, NAME, ENUM },
11405 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11406 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11407 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11408 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11410 static const struct builtin_description bdesc_htm
[] =
11412 #include "rs6000-builtin.def"
11415 #undef RS6000_BUILTIN_1
11416 #undef RS6000_BUILTIN_2
11417 #undef RS6000_BUILTIN_3
11418 #undef RS6000_BUILTIN_A
11419 #undef RS6000_BUILTIN_D
11420 #undef RS6000_BUILTIN_E
11421 #undef RS6000_BUILTIN_H
11422 #undef RS6000_BUILTIN_P
11423 #undef RS6000_BUILTIN_Q
11424 #undef RS6000_BUILTIN_S
11426 /* Return true if a builtin function is overloaded. */
11428 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
11430 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
11433 /* Expand an expression EXP that calls a builtin without arguments. */
11435 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
11438 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11440 if (icode
== CODE_FOR_nothing
)
11441 /* Builtin not supported on this processor. */
11445 || GET_MODE (target
) != tmode
11446 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11447 target
= gen_reg_rtx (tmode
);
11449 pat
= GEN_FCN (icode
) (target
);
11459 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11462 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11463 rtx op0
= expand_normal (arg0
);
11464 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11465 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11467 if (icode
== CODE_FOR_nothing
)
11468 /* Builtin not supported on this processor. */
11471 /* If we got invalid arguments bail out before generating bad rtl. */
11472 if (arg0
== error_mark_node
)
11475 if (icode
== CODE_FOR_altivec_vspltisb
11476 || icode
== CODE_FOR_altivec_vspltish
11477 || icode
== CODE_FOR_altivec_vspltisw
11478 || icode
== CODE_FOR_spe_evsplatfi
11479 || icode
== CODE_FOR_spe_evsplati
)
11481 /* Only allow 5-bit *signed* literals. */
11482 if (GET_CODE (op0
) != CONST_INT
11483 || INTVAL (op0
) > 15
11484 || INTVAL (op0
) < -16)
11486 error ("argument 1 must be a 5-bit signed literal");
11492 || GET_MODE (target
) != tmode
11493 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11494 target
= gen_reg_rtx (tmode
);
11496 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11497 op0
= copy_to_mode_reg (mode0
, op0
);
11499 pat
= GEN_FCN (icode
) (target
, op0
);
11508 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
11510 rtx pat
, scratch1
, scratch2
;
11511 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11512 rtx op0
= expand_normal (arg0
);
11513 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11514 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11516 /* If we have invalid arguments, bail out before generating bad rtl. */
11517 if (arg0
== error_mark_node
)
11521 || GET_MODE (target
) != tmode
11522 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11523 target
= gen_reg_rtx (tmode
);
11525 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11526 op0
= copy_to_mode_reg (mode0
, op0
);
11528 scratch1
= gen_reg_rtx (mode0
);
11529 scratch2
= gen_reg_rtx (mode0
);
11531 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
11540 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11543 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11544 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11545 rtx op0
= expand_normal (arg0
);
11546 rtx op1
= expand_normal (arg1
);
11547 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11548 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11549 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11551 if (icode
== CODE_FOR_nothing
)
11552 /* Builtin not supported on this processor. */
11555 /* If we got invalid arguments bail out before generating bad rtl. */
11556 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11559 if (icode
== CODE_FOR_altivec_vcfux
11560 || icode
== CODE_FOR_altivec_vcfsx
11561 || icode
== CODE_FOR_altivec_vctsxs
11562 || icode
== CODE_FOR_altivec_vctuxs
11563 || icode
== CODE_FOR_altivec_vspltb
11564 || icode
== CODE_FOR_altivec_vsplth
11565 || icode
== CODE_FOR_altivec_vspltw
11566 || icode
== CODE_FOR_spe_evaddiw
11567 || icode
== CODE_FOR_spe_evldd
11568 || icode
== CODE_FOR_spe_evldh
11569 || icode
== CODE_FOR_spe_evldw
11570 || icode
== CODE_FOR_spe_evlhhesplat
11571 || icode
== CODE_FOR_spe_evlhhossplat
11572 || icode
== CODE_FOR_spe_evlhhousplat
11573 || icode
== CODE_FOR_spe_evlwhe
11574 || icode
== CODE_FOR_spe_evlwhos
11575 || icode
== CODE_FOR_spe_evlwhou
11576 || icode
== CODE_FOR_spe_evlwhsplat
11577 || icode
== CODE_FOR_spe_evlwwsplat
11578 || icode
== CODE_FOR_spe_evrlwi
11579 || icode
== CODE_FOR_spe_evslwi
11580 || icode
== CODE_FOR_spe_evsrwis
11581 || icode
== CODE_FOR_spe_evsubifw
11582 || icode
== CODE_FOR_spe_evsrwiu
)
11584 /* Only allow 5-bit unsigned literals. */
11586 if (TREE_CODE (arg1
) != INTEGER_CST
11587 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11589 error ("argument 2 must be a 5-bit unsigned literal");
11595 || GET_MODE (target
) != tmode
11596 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11597 target
= gen_reg_rtx (tmode
);
11599 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11600 op0
= copy_to_mode_reg (mode0
, op0
);
11601 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11602 op1
= copy_to_mode_reg (mode1
, op1
);
11604 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11613 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11616 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
11617 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11618 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11619 rtx op0
= expand_normal (arg0
);
11620 rtx op1
= expand_normal (arg1
);
11621 enum machine_mode tmode
= SImode
;
11622 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11623 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11626 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
11628 error ("argument 1 of __builtin_altivec_predicate must be a constant");
11632 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
11634 gcc_assert (mode0
== mode1
);
11636 /* If we have invalid arguments, bail out before generating bad rtl. */
11637 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11641 || GET_MODE (target
) != tmode
11642 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11643 target
= gen_reg_rtx (tmode
);
11645 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11646 op0
= copy_to_mode_reg (mode0
, op0
);
11647 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11648 op1
= copy_to_mode_reg (mode1
, op1
);
11650 scratch
= gen_reg_rtx (mode0
);
11652 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11657 /* The vec_any* and vec_all* predicates use the same opcodes for two
11658 different operations, but the bits in CR6 will be different
11659 depending on what information we want. So we have to play tricks
11660 with CR6 to get the right bits out.
11662 If you think this is disgusting, look at the specs for the
11663 AltiVec predicates. */
11665 switch (cr6_form_int
)
11668 emit_insn (gen_cr6_test_for_zero (target
));
11671 emit_insn (gen_cr6_test_for_zero_reverse (target
));
11674 emit_insn (gen_cr6_test_for_lt (target
));
11677 emit_insn (gen_cr6_test_for_lt_reverse (target
));
11680 error ("argument 1 of __builtin_altivec_predicate is out of range");
11688 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
11691 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11692 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11693 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11694 enum machine_mode mode0
= Pmode
;
11695 enum machine_mode mode1
= Pmode
;
11696 rtx op0
= expand_normal (arg0
);
11697 rtx op1
= expand_normal (arg1
);
11699 if (icode
== CODE_FOR_nothing
)
11700 /* Builtin not supported on this processor. */
11703 /* If we got invalid arguments bail out before generating bad rtl. */
11704 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11708 || GET_MODE (target
) != tmode
11709 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11710 target
= gen_reg_rtx (tmode
);
11712 op1
= copy_to_mode_reg (mode1
, op1
);
11714 if (op0
== const0_rtx
)
11716 addr
= gen_rtx_MEM (tmode
, op1
);
11720 op0
= copy_to_mode_reg (mode0
, op0
);
11721 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11724 pat
= GEN_FCN (icode
) (target
, addr
);
11734 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
11737 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11738 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11739 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11740 enum machine_mode mode0
= Pmode
;
11741 enum machine_mode mode1
= Pmode
;
11742 rtx op0
= expand_normal (arg0
);
11743 rtx op1
= expand_normal (arg1
);
11745 if (icode
== CODE_FOR_nothing
)
11746 /* Builtin not supported on this processor. */
11749 /* If we got invalid arguments bail out before generating bad rtl. */
11750 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11754 || GET_MODE (target
) != tmode
11755 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11756 target
= gen_reg_rtx (tmode
);
11758 op1
= copy_to_mode_reg (mode1
, op1
);
11760 if (op0
== const0_rtx
)
11762 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
11766 op0
= copy_to_mode_reg (mode0
, op0
);
11767 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11770 pat
= GEN_FCN (icode
) (target
, addr
);
11780 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
11782 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11783 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11784 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11785 rtx op0
= expand_normal (arg0
);
11786 rtx op1
= expand_normal (arg1
);
11787 rtx op2
= expand_normal (arg2
);
11789 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11790 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11791 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
11793 /* Invalid arguments. Bail before doing anything stoopid! */
11794 if (arg0
== error_mark_node
11795 || arg1
== error_mark_node
11796 || arg2
== error_mark_node
)
11799 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
11800 op0
= copy_to_mode_reg (mode2
, op0
);
11801 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
11802 op1
= copy_to_mode_reg (mode0
, op1
);
11803 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
11804 op2
= copy_to_mode_reg (mode1
, op2
);
11806 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
11813 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
11815 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11816 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11817 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11818 rtx op0
= expand_normal (arg0
);
11819 rtx op1
= expand_normal (arg1
);
11820 rtx op2
= expand_normal (arg2
);
11822 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11823 enum machine_mode mode1
= Pmode
;
11824 enum machine_mode mode2
= Pmode
;
11826 /* Invalid arguments. Bail before doing anything stoopid! */
11827 if (arg0
== error_mark_node
11828 || arg1
== error_mark_node
11829 || arg2
== error_mark_node
)
11832 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
11833 op0
= copy_to_mode_reg (tmode
, op0
);
11835 op2
= copy_to_mode_reg (mode2
, op2
);
11837 if (op1
== const0_rtx
)
11839 addr
= gen_rtx_MEM (tmode
, op2
);
11843 op1
= copy_to_mode_reg (mode1
, op1
);
11844 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
11847 pat
= GEN_FCN (icode
) (addr
, op0
);
11854 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
11856 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11857 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11858 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11859 rtx op0
= expand_normal (arg0
);
11860 rtx op1
= expand_normal (arg1
);
11861 rtx op2
= expand_normal (arg2
);
11863 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11864 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
11865 enum machine_mode mode1
= Pmode
;
11866 enum machine_mode mode2
= Pmode
;
11868 /* Invalid arguments. Bail before doing anything stoopid! */
11869 if (arg0
== error_mark_node
11870 || arg1
== error_mark_node
11871 || arg2
== error_mark_node
)
11874 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
11875 op0
= copy_to_mode_reg (smode
, op0
);
11877 op2
= copy_to_mode_reg (mode2
, op2
);
11879 if (op1
== const0_rtx
)
11881 addr
= gen_rtx_MEM (tmode
, op2
);
11885 op1
= copy_to_mode_reg (mode1
, op1
);
11886 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
11889 pat
= GEN_FCN (icode
) (addr
, op0
);
11895 /* Return the appropriate SPR number associated with the given builtin. */
11896 static inline HOST_WIDE_INT
11897 htm_spr_num (enum rs6000_builtins code
)
11899 if (code
== HTM_BUILTIN_GET_TFHAR
11900 || code
== HTM_BUILTIN_SET_TFHAR
)
11902 else if (code
== HTM_BUILTIN_GET_TFIAR
11903 || code
== HTM_BUILTIN_SET_TFIAR
)
11905 else if (code
== HTM_BUILTIN_GET_TEXASR
11906 || code
== HTM_BUILTIN_SET_TEXASR
)
11908 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
11909 || code
== HTM_BUILTIN_SET_TEXASRU
);
11910 return TEXASRU_SPR
;
11913 /* Return the appropriate SPR regno associated with the given builtin. */
11914 static inline HOST_WIDE_INT
11915 htm_spr_regno (enum rs6000_builtins code
)
11917 if (code
== HTM_BUILTIN_GET_TFHAR
11918 || code
== HTM_BUILTIN_SET_TFHAR
)
11919 return TFHAR_REGNO
;
11920 else if (code
== HTM_BUILTIN_GET_TFIAR
11921 || code
== HTM_BUILTIN_SET_TFIAR
)
11922 return TFIAR_REGNO
;
11923 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
11924 || code
== HTM_BUILTIN_SET_TEXASR
11925 || code
== HTM_BUILTIN_GET_TEXASRU
11926 || code
== HTM_BUILTIN_SET_TEXASRU
);
11927 return TEXASR_REGNO
;
11930 /* Return the correct ICODE value depending on whether we are
11931 setting or reading the HTM SPRs. */
11932 static inline enum insn_code
11933 rs6000_htm_spr_icode (bool nonvoid
)
11936 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
11938 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
11941 /* Expand the HTM builtin in EXP and store the result in TARGET.
11942 Store true in *EXPANDEDP if we found a builtin to expand. */
11944 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
11946 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11947 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11948 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11949 const struct builtin_description
*d
;
11952 *expandedp
= false;
11954 /* Expand the HTM builtins. */
11956 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
11957 if (d
->code
== fcode
)
11959 rtx op
[MAX_HTM_OPERANDS
], pat
;
11962 call_expr_arg_iterator iter
;
11963 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
11964 enum insn_code icode
= d
->icode
;
11966 if (attr
& RS6000_BTC_SPR
)
11967 icode
= rs6000_htm_spr_icode (nonvoid
);
11971 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11973 || GET_MODE (target
) != tmode
11974 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11975 target
= gen_reg_rtx (tmode
);
11976 op
[nopnds
++] = target
;
11979 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11981 const struct insn_operand_data
*insn_op
;
11983 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
11986 insn_op
= &insn_data
[icode
].operand
[nopnds
];
11988 op
[nopnds
] = expand_normal (arg
);
11990 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
11992 if (!strcmp (insn_op
->constraint
, "n"))
11994 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
11995 if (!CONST_INT_P (op
[nopnds
]))
11996 error ("argument %d must be an unsigned literal", arg_num
);
11998 error ("argument %d is an unsigned literal that is "
11999 "out of range", arg_num
);
12002 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
12008 /* Handle the builtins for extended mnemonics. These accept
12009 no arguments, but map to builtins that take arguments. */
12012 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
12013 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
12014 op
[nopnds
++] = GEN_INT (1);
12015 #ifdef ENABLE_CHECKING
12016 attr
|= RS6000_BTC_UNARY
;
12019 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12020 op
[nopnds
++] = GEN_INT (0);
12021 #ifdef ENABLE_CHECKING
12022 attr
|= RS6000_BTC_UNARY
;
12029 /* If this builtin accesses SPRs, then pass in the appropriate
12030 SPR number and SPR regno as the last two operands. */
12031 if (attr
& RS6000_BTC_SPR
)
12033 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
12034 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
12037 #ifdef ENABLE_CHECKING
12038 int expected_nopnds
= 0;
12039 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12040 expected_nopnds
= 1;
12041 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12042 expected_nopnds
= 2;
12043 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12044 expected_nopnds
= 3;
12045 if (!(attr
& RS6000_BTC_VOID
))
12046 expected_nopnds
+= 1;
12047 if (attr
& RS6000_BTC_SPR
)
12048 expected_nopnds
+= 2;
12050 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12056 pat
= GEN_FCN (icode
) (op
[0]);
12059 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12062 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12065 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12068 gcc_unreachable ();
12084 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12087 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12088 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12089 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12090 rtx op0
= expand_normal (arg0
);
12091 rtx op1
= expand_normal (arg1
);
12092 rtx op2
= expand_normal (arg2
);
12093 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12094 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12095 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12096 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
12098 if (icode
== CODE_FOR_nothing
)
12099 /* Builtin not supported on this processor. */
12102 /* If we got invalid arguments bail out before generating bad rtl. */
12103 if (arg0
== error_mark_node
12104 || arg1
== error_mark_node
12105 || arg2
== error_mark_node
)
12108 /* Check and prepare argument depending on the instruction code.
12110 Note that a switch statement instead of the sequence of tests
12111 would be incorrect as many of the CODE_FOR values could be
12112 CODE_FOR_nothing and that would yield multiple alternatives
12113 with identical values. We'd never reach here at runtime in
12115 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
12116 || icode
== CODE_FOR_altivec_vsldoi_v4si
12117 || icode
== CODE_FOR_altivec_vsldoi_v8hi
12118 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
12120 /* Only allow 4-bit unsigned literals. */
12122 if (TREE_CODE (arg2
) != INTEGER_CST
12123 || TREE_INT_CST_LOW (arg2
) & ~0xf)
12125 error ("argument 3 must be a 4-bit unsigned literal");
12129 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
12130 || icode
== CODE_FOR_vsx_xxpermdi_v2di
12131 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
12132 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
12133 || icode
== CODE_FOR_vsx_xxsldwi_v4si
12134 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
12135 || icode
== CODE_FOR_vsx_xxsldwi_v2di
12136 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
12138 /* Only allow 2-bit unsigned literals. */
12140 if (TREE_CODE (arg2
) != INTEGER_CST
12141 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12143 error ("argument 3 must be a 2-bit unsigned literal");
12147 else if (icode
== CODE_FOR_vsx_set_v2df
12148 || icode
== CODE_FOR_vsx_set_v2di
)
12150 /* Only allow 1-bit unsigned literals. */
12152 if (TREE_CODE (arg2
) != INTEGER_CST
12153 || TREE_INT_CST_LOW (arg2
) & ~0x1)
12155 error ("argument 3 must be a 1-bit unsigned literal");
12159 else if (icode
== CODE_FOR_crypto_vshasigmaw
12160 || icode
== CODE_FOR_crypto_vshasigmad
)
12162 /* Check whether the 2nd and 3rd arguments are integer constants and in
12163 range and prepare arguments. */
12165 if (TREE_CODE (arg1
) != INTEGER_CST
12166 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 1))
12168 error ("argument 2 must be 0 or 1");
12173 if (TREE_CODE (arg2
) != INTEGER_CST
12174 || !IN_RANGE (TREE_INT_CST_LOW (arg2
), 0, 15))
12176 error ("argument 3 must be in the range 0..15");
12182 || GET_MODE (target
) != tmode
12183 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12184 target
= gen_reg_rtx (tmode
);
12186 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12187 op0
= copy_to_mode_reg (mode0
, op0
);
12188 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12189 op1
= copy_to_mode_reg (mode1
, op1
);
12190 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12191 op2
= copy_to_mode_reg (mode2
, op2
);
12193 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
12194 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
12196 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12204 /* Expand the lvx builtins. */
12206 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
12208 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12209 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12211 enum machine_mode tmode
, mode0
;
12213 enum insn_code icode
;
12217 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
12218 icode
= CODE_FOR_vector_altivec_load_v16qi
;
12220 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
12221 icode
= CODE_FOR_vector_altivec_load_v8hi
;
12223 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
12224 icode
= CODE_FOR_vector_altivec_load_v4si
;
12226 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
12227 icode
= CODE_FOR_vector_altivec_load_v4sf
;
12229 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
12230 icode
= CODE_FOR_vector_altivec_load_v2df
;
12232 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
12233 icode
= CODE_FOR_vector_altivec_load_v2di
;
12236 *expandedp
= false;
12242 arg0
= CALL_EXPR_ARG (exp
, 0);
12243 op0
= expand_normal (arg0
);
12244 tmode
= insn_data
[icode
].operand
[0].mode
;
12245 mode0
= insn_data
[icode
].operand
[1].mode
;
12248 || GET_MODE (target
) != tmode
12249 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12250 target
= gen_reg_rtx (tmode
);
12252 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12253 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12255 pat
= GEN_FCN (icode
) (target
, op0
);
12262 /* Expand the stvx builtins. */
12264 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12267 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12268 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12270 enum machine_mode mode0
, mode1
;
12272 enum insn_code icode
;
12276 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
12277 icode
= CODE_FOR_vector_altivec_store_v16qi
;
12279 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
12280 icode
= CODE_FOR_vector_altivec_store_v8hi
;
12282 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
12283 icode
= CODE_FOR_vector_altivec_store_v4si
;
12285 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
12286 icode
= CODE_FOR_vector_altivec_store_v4sf
;
12288 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
12289 icode
= CODE_FOR_vector_altivec_store_v2df
;
12291 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
12292 icode
= CODE_FOR_vector_altivec_store_v2di
;
12295 *expandedp
= false;
12299 arg0
= CALL_EXPR_ARG (exp
, 0);
12300 arg1
= CALL_EXPR_ARG (exp
, 1);
12301 op0
= expand_normal (arg0
);
12302 op1
= expand_normal (arg1
);
12303 mode0
= insn_data
[icode
].operand
[0].mode
;
12304 mode1
= insn_data
[icode
].operand
[1].mode
;
12306 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12307 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12308 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12309 op1
= copy_to_mode_reg (mode1
, op1
);
12311 pat
= GEN_FCN (icode
) (op0
, op1
);
12319 /* Expand the dst builtins. */
12321 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12324 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12325 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12326 tree arg0
, arg1
, arg2
;
12327 enum machine_mode mode0
, mode1
;
12328 rtx pat
, op0
, op1
, op2
;
12329 const struct builtin_description
*d
;
12332 *expandedp
= false;
12334 /* Handle DST variants. */
12336 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12337 if (d
->code
== fcode
)
12339 arg0
= CALL_EXPR_ARG (exp
, 0);
12340 arg1
= CALL_EXPR_ARG (exp
, 1);
12341 arg2
= CALL_EXPR_ARG (exp
, 2);
12342 op0
= expand_normal (arg0
);
12343 op1
= expand_normal (arg1
);
12344 op2
= expand_normal (arg2
);
12345 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12346 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12348 /* Invalid arguments, bail out before generating bad rtl. */
12349 if (arg0
== error_mark_node
12350 || arg1
== error_mark_node
12351 || arg2
== error_mark_node
)
12356 if (TREE_CODE (arg2
) != INTEGER_CST
12357 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12359 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
12363 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
12364 op0
= copy_to_mode_reg (Pmode
, op0
);
12365 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
12366 op1
= copy_to_mode_reg (mode1
, op1
);
12368 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
12378 /* Expand vec_init builtin. */
12380 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
12382 enum machine_mode tmode
= TYPE_MODE (type
);
12383 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
12384 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
12385 rtvec v
= rtvec_alloc (n_elt
);
12387 gcc_assert (VECTOR_MODE_P (tmode
));
12388 gcc_assert (n_elt
== call_expr_nargs (exp
));
12390 for (i
= 0; i
< n_elt
; ++i
)
12392 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
12393 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
12396 if (!target
|| !register_operand (target
, tmode
))
12397 target
= gen_reg_rtx (tmode
);
12399 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
12403 /* Return the integer constant in ARG. Constrain it to be in the range
12404 of the subparts of VEC_TYPE; issue an error if not. */
12407 get_element_number (tree vec_type
, tree arg
)
12409 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
12411 if (!tree_fits_uhwi_p (arg
)
12412 || (elt
= tree_to_uhwi (arg
), elt
> max
))
12414 error ("selector must be an integer constant in the range 0..%wi", max
);
12421 /* Expand vec_set builtin. */
12423 altivec_expand_vec_set_builtin (tree exp
)
12425 enum machine_mode tmode
, mode1
;
12426 tree arg0
, arg1
, arg2
;
12430 arg0
= CALL_EXPR_ARG (exp
, 0);
12431 arg1
= CALL_EXPR_ARG (exp
, 1);
12432 arg2
= CALL_EXPR_ARG (exp
, 2);
12434 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
12435 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12436 gcc_assert (VECTOR_MODE_P (tmode
));
12438 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
12439 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
12440 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
12442 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
12443 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
12445 op0
= force_reg (tmode
, op0
);
12446 op1
= force_reg (mode1
, op1
);
12448 rs6000_expand_vector_set (op0
, op1
, elt
);
12453 /* Expand vec_ext builtin. */
12455 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
12457 enum machine_mode tmode
, mode0
;
12462 arg0
= CALL_EXPR_ARG (exp
, 0);
12463 arg1
= CALL_EXPR_ARG (exp
, 1);
12465 op0
= expand_normal (arg0
);
12466 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
12468 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12469 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
12470 gcc_assert (VECTOR_MODE_P (mode0
));
12472 op0
= force_reg (mode0
, op0
);
12474 if (optimize
|| !target
|| !register_operand (target
, tmode
))
12475 target
= gen_reg_rtx (tmode
);
12477 rs6000_expand_vector_extract (target
, op0
, elt
);
12482 /* Expand the builtin in EXP and store the result in TARGET. Store
12483 true in *EXPANDEDP if we found a builtin to expand. */
12485 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12487 const struct builtin_description
*d
;
12489 enum insn_code icode
;
12490 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12493 enum machine_mode tmode
, mode0
;
12494 enum rs6000_builtins fcode
12495 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12497 if (rs6000_overloaded_builtin_p (fcode
))
12500 error ("unresolved overload for Altivec builtin %qF", fndecl
);
12502 /* Given it is invalid, just generate a normal call. */
12503 return expand_call (exp
, target
, false);
12506 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
12510 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
12514 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
12522 case ALTIVEC_BUILTIN_STVX
:
12523 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
12524 case ALTIVEC_BUILTIN_STVEBX
:
12525 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
12526 case ALTIVEC_BUILTIN_STVEHX
:
12527 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
12528 case ALTIVEC_BUILTIN_STVEWX
:
12529 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
12530 case ALTIVEC_BUILTIN_STVXL
:
12531 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
12533 case ALTIVEC_BUILTIN_STVLX
:
12534 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
12535 case ALTIVEC_BUILTIN_STVLXL
:
12536 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
12537 case ALTIVEC_BUILTIN_STVRX
:
12538 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
12539 case ALTIVEC_BUILTIN_STVRXL
:
12540 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
12542 case VSX_BUILTIN_STXVD2X_V2DF
:
12543 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
12544 case VSX_BUILTIN_STXVD2X_V2DI
:
12545 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
12546 case VSX_BUILTIN_STXVW4X_V4SF
:
12547 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
12548 case VSX_BUILTIN_STXVW4X_V4SI
:
12549 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
12550 case VSX_BUILTIN_STXVW4X_V8HI
:
12551 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
12552 case VSX_BUILTIN_STXVW4X_V16QI
:
12553 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
12555 case ALTIVEC_BUILTIN_MFVSCR
:
12556 icode
= CODE_FOR_altivec_mfvscr
;
12557 tmode
= insn_data
[icode
].operand
[0].mode
;
12560 || GET_MODE (target
) != tmode
12561 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12562 target
= gen_reg_rtx (tmode
);
12564 pat
= GEN_FCN (icode
) (target
);
12570 case ALTIVEC_BUILTIN_MTVSCR
:
12571 icode
= CODE_FOR_altivec_mtvscr
;
12572 arg0
= CALL_EXPR_ARG (exp
, 0);
12573 op0
= expand_normal (arg0
);
12574 mode0
= insn_data
[icode
].operand
[0].mode
;
12576 /* If we got invalid arguments bail out before generating bad rtl. */
12577 if (arg0
== error_mark_node
)
12580 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12581 op0
= copy_to_mode_reg (mode0
, op0
);
12583 pat
= GEN_FCN (icode
) (op0
);
12588 case ALTIVEC_BUILTIN_DSSALL
:
12589 emit_insn (gen_altivec_dssall ());
12592 case ALTIVEC_BUILTIN_DSS
:
12593 icode
= CODE_FOR_altivec_dss
;
12594 arg0
= CALL_EXPR_ARG (exp
, 0);
12596 op0
= expand_normal (arg0
);
12597 mode0
= insn_data
[icode
].operand
[0].mode
;
12599 /* If we got invalid arguments bail out before generating bad rtl. */
12600 if (arg0
== error_mark_node
)
12603 if (TREE_CODE (arg0
) != INTEGER_CST
12604 || TREE_INT_CST_LOW (arg0
) & ~0x3)
12606 error ("argument to dss must be a 2-bit unsigned literal");
12610 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12611 op0
= copy_to_mode_reg (mode0
, op0
);
12613 emit_insn (gen_altivec_dss (op0
));
12616 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
12617 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
12618 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
12619 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
12620 case VSX_BUILTIN_VEC_INIT_V2DF
:
12621 case VSX_BUILTIN_VEC_INIT_V2DI
:
12622 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
12624 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
12625 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
12626 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
12627 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
12628 case VSX_BUILTIN_VEC_SET_V2DF
:
12629 case VSX_BUILTIN_VEC_SET_V2DI
:
12630 return altivec_expand_vec_set_builtin (exp
);
12632 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
12633 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
12634 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
12635 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
12636 case VSX_BUILTIN_VEC_EXT_V2DF
:
12637 case VSX_BUILTIN_VEC_EXT_V2DI
:
12638 return altivec_expand_vec_ext_builtin (exp
, target
);
12642 /* Fall through. */
12645 /* Expand abs* operations. */
12647 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12648 if (d
->code
== fcode
)
12649 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
12651 /* Expand the AltiVec predicates. */
12652 d
= bdesc_altivec_preds
;
12653 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12654 if (d
->code
== fcode
)
12655 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
12657 /* LV* are funky. We initialized them differently. */
12660 case ALTIVEC_BUILTIN_LVSL
:
12661 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
12662 exp
, target
, false);
12663 case ALTIVEC_BUILTIN_LVSR
:
12664 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
12665 exp
, target
, false);
12666 case ALTIVEC_BUILTIN_LVEBX
:
12667 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
12668 exp
, target
, false);
12669 case ALTIVEC_BUILTIN_LVEHX
:
12670 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
12671 exp
, target
, false);
12672 case ALTIVEC_BUILTIN_LVEWX
:
12673 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
12674 exp
, target
, false);
12675 case ALTIVEC_BUILTIN_LVXL
:
12676 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
12677 exp
, target
, false);
12678 case ALTIVEC_BUILTIN_LVX
:
12679 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
12680 exp
, target
, false);
12681 case ALTIVEC_BUILTIN_LVLX
:
12682 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
12683 exp
, target
, true);
12684 case ALTIVEC_BUILTIN_LVLXL
:
12685 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
12686 exp
, target
, true);
12687 case ALTIVEC_BUILTIN_LVRX
:
12688 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
12689 exp
, target
, true);
12690 case ALTIVEC_BUILTIN_LVRXL
:
12691 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
12692 exp
, target
, true);
12693 case VSX_BUILTIN_LXVD2X_V2DF
:
12694 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
12695 exp
, target
, false);
12696 case VSX_BUILTIN_LXVD2X_V2DI
:
12697 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
12698 exp
, target
, false);
12699 case VSX_BUILTIN_LXVW4X_V4SF
:
12700 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
12701 exp
, target
, false);
12702 case VSX_BUILTIN_LXVW4X_V4SI
:
12703 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
12704 exp
, target
, false);
12705 case VSX_BUILTIN_LXVW4X_V8HI
:
12706 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
12707 exp
, target
, false);
12708 case VSX_BUILTIN_LXVW4X_V16QI
:
12709 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
12710 exp
, target
, false);
12714 /* Fall through. */
12717 *expandedp
= false;
12721 /* Expand the builtin in EXP and store the result in TARGET. Store
12722 true in *EXPANDEDP if we found a builtin to expand. */
12724 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12726 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12727 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12728 const struct builtin_description
*d
;
12735 case PAIRED_BUILTIN_STX
:
12736 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
12737 case PAIRED_BUILTIN_LX
:
12738 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
12741 /* Fall through. */
12744 /* Expand the paired predicates. */
12745 d
= bdesc_paired_preds
;
12746 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
12747 if (d
->code
== fcode
)
12748 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
12750 *expandedp
= false;
12754 /* Binops that need to be initialized manually, but can be expanded
12755 automagically by rs6000_expand_binop_builtin. */
12756 static const struct builtin_description bdesc_2arg_spe
[] =
12758 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
12759 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
12760 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
12761 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
12762 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
12763 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
12764 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
12765 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
12766 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
12767 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
12768 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
12769 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
12770 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
12771 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
12772 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
12773 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
12774 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
12775 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
12776 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
12777 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
12778 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
12779 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
12782 /* Expand the builtin in EXP and store the result in TARGET. Store
12783 true in *EXPANDEDP if we found a builtin to expand.
12785 This expands the SPE builtins that are not simple unary and binary
12788 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12790 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12792 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12793 enum insn_code icode
;
12794 enum machine_mode tmode
, mode0
;
12796 const struct builtin_description
*d
;
12801 /* Syntax check for a 5-bit unsigned immediate. */
12804 case SPE_BUILTIN_EVSTDD
:
12805 case SPE_BUILTIN_EVSTDH
:
12806 case SPE_BUILTIN_EVSTDW
:
12807 case SPE_BUILTIN_EVSTWHE
:
12808 case SPE_BUILTIN_EVSTWHO
:
12809 case SPE_BUILTIN_EVSTWWE
:
12810 case SPE_BUILTIN_EVSTWWO
:
12811 arg1
= CALL_EXPR_ARG (exp
, 2);
12812 if (TREE_CODE (arg1
) != INTEGER_CST
12813 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
12815 error ("argument 2 must be a 5-bit unsigned literal");
12823 /* The evsplat*i instructions are not quite generic. */
12826 case SPE_BUILTIN_EVSPLATFI
:
12827 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
12829 case SPE_BUILTIN_EVSPLATI
:
12830 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
12836 d
= bdesc_2arg_spe
;
12837 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
12838 if (d
->code
== fcode
)
12839 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
12841 d
= bdesc_spe_predicates
;
12842 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
12843 if (d
->code
== fcode
)
12844 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
12846 d
= bdesc_spe_evsel
;
12847 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
12848 if (d
->code
== fcode
)
12849 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
12853 case SPE_BUILTIN_EVSTDDX
:
12854 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
12855 case SPE_BUILTIN_EVSTDHX
:
12856 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
12857 case SPE_BUILTIN_EVSTDWX
:
12858 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
12859 case SPE_BUILTIN_EVSTWHEX
:
12860 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
12861 case SPE_BUILTIN_EVSTWHOX
:
12862 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
12863 case SPE_BUILTIN_EVSTWWEX
:
12864 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
12865 case SPE_BUILTIN_EVSTWWOX
:
12866 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
12867 case SPE_BUILTIN_EVSTDD
:
12868 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
12869 case SPE_BUILTIN_EVSTDH
:
12870 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
12871 case SPE_BUILTIN_EVSTDW
:
12872 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
12873 case SPE_BUILTIN_EVSTWHE
:
12874 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
12875 case SPE_BUILTIN_EVSTWHO
:
12876 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
12877 case SPE_BUILTIN_EVSTWWE
:
12878 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
12879 case SPE_BUILTIN_EVSTWWO
:
12880 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
12881 case SPE_BUILTIN_MFSPEFSCR
:
12882 icode
= CODE_FOR_spe_mfspefscr
;
12883 tmode
= insn_data
[icode
].operand
[0].mode
;
12886 || GET_MODE (target
) != tmode
12887 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12888 target
= gen_reg_rtx (tmode
);
12890 pat
= GEN_FCN (icode
) (target
);
12895 case SPE_BUILTIN_MTSPEFSCR
:
12896 icode
= CODE_FOR_spe_mtspefscr
;
12897 arg0
= CALL_EXPR_ARG (exp
, 0);
12898 op0
= expand_normal (arg0
);
12899 mode0
= insn_data
[icode
].operand
[0].mode
;
12901 if (arg0
== error_mark_node
)
12904 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12905 op0
= copy_to_mode_reg (mode0
, op0
);
12907 pat
= GEN_FCN (icode
) (op0
);
12915 *expandedp
= false;
12920 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12922 rtx pat
, scratch
, tmp
;
12923 tree form
= CALL_EXPR_ARG (exp
, 0);
12924 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12925 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12926 rtx op0
= expand_normal (arg0
);
12927 rtx op1
= expand_normal (arg1
);
12928 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12929 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12931 enum rtx_code code
;
12933 if (TREE_CODE (form
) != INTEGER_CST
)
12935 error ("argument 1 of __builtin_paired_predicate must be a constant");
12939 form_int
= TREE_INT_CST_LOW (form
);
12941 gcc_assert (mode0
== mode1
);
12943 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12947 || GET_MODE (target
) != SImode
12948 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
12949 target
= gen_reg_rtx (SImode
);
12950 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12951 op0
= copy_to_mode_reg (mode0
, op0
);
12952 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12953 op1
= copy_to_mode_reg (mode1
, op1
);
12955 scratch
= gen_reg_rtx (CCFPmode
);
12957 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12979 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
12982 error ("argument 1 of __builtin_paired_predicate is out of range");
12986 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
12987 emit_move_insn (target
, tmp
);
12992 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12994 rtx pat
, scratch
, tmp
;
12995 tree form
= CALL_EXPR_ARG (exp
, 0);
12996 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12997 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12998 rtx op0
= expand_normal (arg0
);
12999 rtx op1
= expand_normal (arg1
);
13000 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13001 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13003 enum rtx_code code
;
13005 if (TREE_CODE (form
) != INTEGER_CST
)
13007 error ("argument 1 of __builtin_spe_predicate must be a constant");
13011 form_int
= TREE_INT_CST_LOW (form
);
13013 gcc_assert (mode0
== mode1
);
13015 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13019 || GET_MODE (target
) != SImode
13020 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13021 target
= gen_reg_rtx (SImode
);
13023 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13024 op0
= copy_to_mode_reg (mode0
, op0
);
13025 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13026 op1
= copy_to_mode_reg (mode1
, op1
);
13028 scratch
= gen_reg_rtx (CCmode
);
13030 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13035 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13036 _lower_. We use one compare, but look in different bits of the
13037 CR for each variant.
13039 There are 2 elements in each SPE simd type (upper/lower). The CR
13040 bits are set as follows:
13042 BIT0 | BIT 1 | BIT 2 | BIT 3
13043 U | L | (U | L) | (U & L)
13045 So, for an "all" relationship, BIT 3 would be set.
13046 For an "any" relationship, BIT 2 would be set. Etc.
13048 Following traditional nomenclature, these bits map to:
13050 BIT0 | BIT 1 | BIT 2 | BIT 3
13053 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13058 /* All variant. OV bit. */
13060 /* We need to get to the OV bit, which is the ORDERED bit. We
13061 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13062 that's ugly and will make validate_condition_mode die.
13063 So let's just use another pattern. */
13064 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13066 /* Any variant. EQ bit. */
13070 /* Upper variant. LT bit. */
13074 /* Lower variant. GT bit. */
13079 error ("argument 1 of __builtin_spe_predicate is out of range");
13083 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13084 emit_move_insn (target
, tmp
);
13089 /* The evsel builtins look like this:
13091 e = __builtin_spe_evsel_OP (a, b, c, d);
13093 and work like this:
13095 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
13096 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
13100 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
13103 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13104 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13105 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13106 tree arg3
= CALL_EXPR_ARG (exp
, 3);
13107 rtx op0
= expand_normal (arg0
);
13108 rtx op1
= expand_normal (arg1
);
13109 rtx op2
= expand_normal (arg2
);
13110 rtx op3
= expand_normal (arg3
);
13111 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13112 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13114 gcc_assert (mode0
== mode1
);
13116 if (arg0
== error_mark_node
|| arg1
== error_mark_node
13117 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
13121 || GET_MODE (target
) != mode0
13122 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
13123 target
= gen_reg_rtx (mode0
);
13125 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13126 op0
= copy_to_mode_reg (mode0
, op0
);
13127 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13128 op1
= copy_to_mode_reg (mode0
, op1
);
13129 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
13130 op2
= copy_to_mode_reg (mode0
, op2
);
13131 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
13132 op3
= copy_to_mode_reg (mode0
, op3
);
13134 /* Generate the compare. */
13135 scratch
= gen_reg_rtx (CCmode
);
13136 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13141 if (mode0
== V2SImode
)
13142 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
13144 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
13149 /* Raise an error message for a builtin function that is called without the
13150 appropriate target options being set. */
13153 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
13155 size_t uns_fncode
= (size_t)fncode
;
13156 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
13157 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
13159 gcc_assert (name
!= NULL
);
13160 if ((fnmask
& RS6000_BTM_CELL
) != 0)
13161 error ("Builtin function %s is only valid for the cell processor", name
);
13162 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
13163 error ("Builtin function %s requires the -mvsx option", name
);
13164 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
13165 error ("Builtin function %s requires the -mhtm option", name
);
13166 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
13167 error ("Builtin function %s requires the -maltivec option", name
);
13168 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
13169 error ("Builtin function %s requires the -mpaired option", name
);
13170 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
13171 error ("Builtin function %s requires the -mspe option", name
);
13173 error ("Builtin function %s is not supported with the current options",
13177 /* Expand an expression EXP that calls a built-in function,
13178 with result going to TARGET if that's convenient
13179 (and in mode MODE if that's convenient).
13180 SUBTARGET may be used as the target for computing one of EXP's operands.
13181 IGNORE is nonzero if the value is to be ignored. */
13184 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13185 enum machine_mode mode ATTRIBUTE_UNUSED
,
13186 int ignore ATTRIBUTE_UNUSED
)
13188 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13189 enum rs6000_builtins fcode
13190 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
13191 size_t uns_fcode
= (size_t)fcode
;
13192 const struct builtin_description
*d
;
13196 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
13197 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
13199 if (TARGET_DEBUG_BUILTIN
)
13201 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
13202 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
13203 const char *name2
= ((icode
!= CODE_FOR_nothing
)
13204 ? get_insn_name ((int)icode
)
13208 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
13210 default: name3
= "unknown"; break;
13211 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
13212 case RS6000_BTC_UNARY
: name3
= "unary"; break;
13213 case RS6000_BTC_BINARY
: name3
= "binary"; break;
13214 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
13215 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
13216 case RS6000_BTC_ABS
: name3
= "abs"; break;
13217 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
13218 case RS6000_BTC_DST
: name3
= "dst"; break;
13223 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13224 (name1
) ? name1
: "---", fcode
,
13225 (name2
) ? name2
: "---", (int)icode
,
13227 func_valid_p
? "" : ", not valid");
13232 rs6000_invalid_builtin (fcode
);
13234 /* Given it is invalid, just generate a normal call. */
13235 return expand_call (exp
, target
, ignore
);
13240 case RS6000_BUILTIN_RECIP
:
13241 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
13243 case RS6000_BUILTIN_RECIPF
:
13244 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
13246 case RS6000_BUILTIN_RSQRTF
:
13247 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
13249 case RS6000_BUILTIN_RSQRT
:
13250 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
13252 case POWER7_BUILTIN_BPERMD
:
13253 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
13254 ? CODE_FOR_bpermd_di
13255 : CODE_FOR_bpermd_si
), exp
, target
);
13257 case RS6000_BUILTIN_GET_TB
:
13258 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
13261 case RS6000_BUILTIN_MFTB
:
13262 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
13263 ? CODE_FOR_rs6000_mftb_di
13264 : CODE_FOR_rs6000_mftb_si
),
13267 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
13268 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
13270 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr
13271 : (int) CODE_FOR_altivec_lvsl
);
13272 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13273 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
13277 gcc_assert (TARGET_ALTIVEC
);
13279 arg
= CALL_EXPR_ARG (exp
, 0);
13280 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
13281 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
13282 addr
= memory_address (mode
, op
);
13283 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
13287 /* For the load case need to negate the address. */
13288 op
= gen_reg_rtx (GET_MODE (addr
));
13289 emit_insn (gen_rtx_SET (VOIDmode
, op
,
13290 gen_rtx_NEG (GET_MODE (addr
), addr
)));
13292 op
= gen_rtx_MEM (mode
, op
);
13295 || GET_MODE (target
) != tmode
13296 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13297 target
= gen_reg_rtx (tmode
);
13299 /*pat = gen_altivec_lvsr (target, op);*/
13300 pat
= GEN_FCN (icode
) (target
, op
);
13308 case ALTIVEC_BUILTIN_VCFUX
:
13309 case ALTIVEC_BUILTIN_VCFSX
:
13310 case ALTIVEC_BUILTIN_VCTUXS
:
13311 case ALTIVEC_BUILTIN_VCTSXS
:
13312 /* FIXME: There's got to be a nicer way to handle this case than
13313 constructing a new CALL_EXPR. */
13314 if (call_expr_nargs (exp
) == 1)
13316 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
13317 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
13325 if (TARGET_ALTIVEC
)
13327 ret
= altivec_expand_builtin (exp
, target
, &success
);
13334 ret
= spe_expand_builtin (exp
, target
, &success
);
13339 if (TARGET_PAIRED_FLOAT
)
13341 ret
= paired_expand_builtin (exp
, target
, &success
);
13348 ret
= htm_expand_builtin (exp
, target
, &success
);
13354 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
13356 /* Handle simple unary operations. */
13358 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13359 if (d
->code
== fcode
)
13360 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
13362 /* Handle simple binary operations. */
13364 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13365 if (d
->code
== fcode
)
13366 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13368 /* Handle simple ternary operations. */
13370 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
13371 if (d
->code
== fcode
)
13372 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
13374 gcc_unreachable ();
13378 rs6000_init_builtins (void)
13382 enum machine_mode mode
;
13384 if (TARGET_DEBUG_BUILTIN
)
13385 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
13386 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
13387 (TARGET_SPE
) ? ", spe" : "",
13388 (TARGET_ALTIVEC
) ? ", altivec" : "",
13389 (TARGET_VSX
) ? ", vsx" : "");
13391 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
13392 V2SF_type_node
= build_vector_type (float_type_node
, 2);
13393 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
13394 V2DF_type_node
= build_vector_type (double_type_node
, 2);
13395 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
13396 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
13397 V4SF_type_node
= build_vector_type (float_type_node
, 4);
13398 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
13399 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
13401 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
13402 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
13403 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
13404 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
13406 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
13407 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
13408 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
13409 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
13411 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
13412 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
13413 'vector unsigned short'. */
13415 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
13416 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13417 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
13418 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
13419 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13421 long_integer_type_internal_node
= long_integer_type_node
;
13422 long_unsigned_type_internal_node
= long_unsigned_type_node
;
13423 long_long_integer_type_internal_node
= long_long_integer_type_node
;
13424 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
13425 intQI_type_internal_node
= intQI_type_node
;
13426 uintQI_type_internal_node
= unsigned_intQI_type_node
;
13427 intHI_type_internal_node
= intHI_type_node
;
13428 uintHI_type_internal_node
= unsigned_intHI_type_node
;
13429 intSI_type_internal_node
= intSI_type_node
;
13430 uintSI_type_internal_node
= unsigned_intSI_type_node
;
13431 intDI_type_internal_node
= intDI_type_node
;
13432 uintDI_type_internal_node
= unsigned_intDI_type_node
;
13433 float_type_internal_node
= float_type_node
;
13434 double_type_internal_node
= double_type_node
;
13435 void_type_internal_node
= void_type_node
;
13437 /* Initialize the modes for builtin_function_type, mapping a machine mode to
13439 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
13440 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
13441 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
13442 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
13443 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
13444 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
13445 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
13446 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
13447 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
13448 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
13449 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
13450 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
13451 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
13452 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
13453 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
13454 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
13455 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
13456 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
13457 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
13458 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
13459 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
13461 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
13462 TYPE_NAME (bool_char_type_node
) = tdecl
;
13464 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
13465 TYPE_NAME (bool_short_type_node
) = tdecl
;
13467 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
13468 TYPE_NAME (bool_int_type_node
) = tdecl
;
13470 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
13471 TYPE_NAME (pixel_type_node
) = tdecl
;
13473 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
13474 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
13475 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
13476 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
13477 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
13479 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
13480 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
13482 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
13483 TYPE_NAME (V16QI_type_node
) = tdecl
;
13485 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
13486 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
13488 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
13489 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
13491 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
13492 TYPE_NAME (V8HI_type_node
) = tdecl
;
13494 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
13495 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
13497 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
13498 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
13500 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
13501 TYPE_NAME (V4SI_type_node
) = tdecl
;
13503 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
13504 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
13506 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
13507 TYPE_NAME (V4SF_type_node
) = tdecl
;
13509 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
13510 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
13512 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
13513 TYPE_NAME (V2DF_type_node
) = tdecl
;
13515 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
13516 TYPE_NAME (V2DI_type_node
) = tdecl
;
13518 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
13519 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13521 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
13522 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13524 /* Paired and SPE builtins are only available if you build a compiler with
13525 the appropriate options, so only create those builtins with the
13526 appropriate compiler option. Create Altivec and VSX builtins on machines
13527 with at least the general purpose extensions (970 and newer) to allow the
13528 use of the target attribute. */
13529 if (TARGET_PAIRED_FLOAT
)
13530 paired_init_builtins ();
13532 spe_init_builtins ();
13533 if (TARGET_EXTRA_BUILTINS
)
13534 altivec_init_builtins ();
13536 htm_init_builtins ();
13538 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
13539 rs6000_common_init_builtins ();
13541 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
13542 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
13543 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
13545 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
13546 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
13547 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
13549 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
13550 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
13551 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
13553 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
13554 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
13555 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
13557 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
13558 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
13559 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
13560 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
13562 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13564 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
13567 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13570 ftype
= build_function_type_list (unsigned_intSI_type_node
,
13572 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
13575 /* AIX libm provides clog as __clog. */
13576 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
13577 set_user_assembler_name (tdecl
, "__clog");
13580 #ifdef SUBTARGET_INIT_BUILTINS
13581 SUBTARGET_INIT_BUILTINS
;
13585 /* Returns the rs6000 builtin decl for CODE. */
13588 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
13590 HOST_WIDE_INT fnmask
;
13592 if (code
>= RS6000_BUILTIN_COUNT
)
13593 return error_mark_node
;
13595 fnmask
= rs6000_builtin_info
[code
].mask
;
13596 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
13598 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
13599 return error_mark_node
;
13602 return rs6000_builtin_decls
[code
];
13606 spe_init_builtins (void)
13608 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
13609 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
13610 const struct builtin_description
*d
;
13613 tree v2si_ftype_4_v2si
13614 = build_function_type_list (opaque_V2SI_type_node
,
13615 opaque_V2SI_type_node
,
13616 opaque_V2SI_type_node
,
13617 opaque_V2SI_type_node
,
13618 opaque_V2SI_type_node
,
13621 tree v2sf_ftype_4_v2sf
13622 = build_function_type_list (opaque_V2SF_type_node
,
13623 opaque_V2SF_type_node
,
13624 opaque_V2SF_type_node
,
13625 opaque_V2SF_type_node
,
13626 opaque_V2SF_type_node
,
13629 tree int_ftype_int_v2si_v2si
13630 = build_function_type_list (integer_type_node
,
13632 opaque_V2SI_type_node
,
13633 opaque_V2SI_type_node
,
13636 tree int_ftype_int_v2sf_v2sf
13637 = build_function_type_list (integer_type_node
,
13639 opaque_V2SF_type_node
,
13640 opaque_V2SF_type_node
,
13643 tree void_ftype_v2si_puint_int
13644 = build_function_type_list (void_type_node
,
13645 opaque_V2SI_type_node
,
13650 tree void_ftype_v2si_puint_char
13651 = build_function_type_list (void_type_node
,
13652 opaque_V2SI_type_node
,
13657 tree void_ftype_v2si_pv2si_int
13658 = build_function_type_list (void_type_node
,
13659 opaque_V2SI_type_node
,
13660 opaque_p_V2SI_type_node
,
13664 tree void_ftype_v2si_pv2si_char
13665 = build_function_type_list (void_type_node
,
13666 opaque_V2SI_type_node
,
13667 opaque_p_V2SI_type_node
,
13671 tree void_ftype_int
13672 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
13674 tree int_ftype_void
13675 = build_function_type_list (integer_type_node
, NULL_TREE
);
13677 tree v2si_ftype_pv2si_int
13678 = build_function_type_list (opaque_V2SI_type_node
,
13679 opaque_p_V2SI_type_node
,
13683 tree v2si_ftype_puint_int
13684 = build_function_type_list (opaque_V2SI_type_node
,
13689 tree v2si_ftype_pushort_int
13690 = build_function_type_list (opaque_V2SI_type_node
,
13695 tree v2si_ftype_signed_char
13696 = build_function_type_list (opaque_V2SI_type_node
,
13697 signed_char_type_node
,
13700 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
13702 /* Initialize irregular SPE builtins. */
13704 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
13705 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
13706 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
13707 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
13708 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
13709 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
13710 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
13711 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
13712 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
13713 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
13714 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
13715 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
13716 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
13717 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
13718 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
13719 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
13720 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
13721 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
13724 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
13725 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
13726 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
13727 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
13728 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
13729 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
13730 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
13731 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
13732 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
13733 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
13734 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
13735 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
13736 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
13737 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
13738 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
13739 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
13740 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
13741 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
13742 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
13743 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
13744 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
13745 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
13748 d
= bdesc_spe_predicates
;
13749 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
13753 switch (insn_data
[d
->icode
].operand
[1].mode
)
13756 type
= int_ftype_int_v2si_v2si
;
13759 type
= int_ftype_int_v2sf_v2sf
;
13762 gcc_unreachable ();
13765 def_builtin (d
->name
, type
, d
->code
);
13768 /* Evsel predicates. */
13769 d
= bdesc_spe_evsel
;
13770 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
13774 switch (insn_data
[d
->icode
].operand
[1].mode
)
13777 type
= v2si_ftype_4_v2si
;
13780 type
= v2sf_ftype_4_v2sf
;
13783 gcc_unreachable ();
13786 def_builtin (d
->name
, type
, d
->code
);
13791 paired_init_builtins (void)
13793 const struct builtin_description
*d
;
13796 tree int_ftype_int_v2sf_v2sf
13797 = build_function_type_list (integer_type_node
,
13802 tree pcfloat_type_node
=
13803 build_pointer_type (build_qualified_type
13804 (float_type_node
, TYPE_QUAL_CONST
));
13806 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
13807 long_integer_type_node
,
13810 tree void_ftype_v2sf_long_pcfloat
=
13811 build_function_type_list (void_type_node
,
13813 long_integer_type_node
,
13818 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
13819 PAIRED_BUILTIN_LX
);
13822 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
13823 PAIRED_BUILTIN_STX
);
13826 d
= bdesc_paired_preds
;
13827 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
13831 if (TARGET_DEBUG_BUILTIN
)
13832 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
13833 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
13834 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
13836 switch (insn_data
[d
->icode
].operand
[1].mode
)
13839 type
= int_ftype_int_v2sf_v2sf
;
13842 gcc_unreachable ();
13845 def_builtin (d
->name
, type
, d
->code
);
13850 altivec_init_builtins (void)
13852 const struct builtin_description
*d
;
13857 tree pvoid_type_node
= build_pointer_type (void_type_node
);
13859 tree pcvoid_type_node
13860 = build_pointer_type (build_qualified_type (void_type_node
,
13863 tree int_ftype_opaque
13864 = build_function_type_list (integer_type_node
,
13865 opaque_V4SI_type_node
, NULL_TREE
);
13866 tree opaque_ftype_opaque
13867 = build_function_type_list (integer_type_node
, NULL_TREE
);
13868 tree opaque_ftype_opaque_int
13869 = build_function_type_list (opaque_V4SI_type_node
,
13870 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
13871 tree opaque_ftype_opaque_opaque_int
13872 = build_function_type_list (opaque_V4SI_type_node
,
13873 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
13874 integer_type_node
, NULL_TREE
);
13875 tree int_ftype_int_opaque_opaque
13876 = build_function_type_list (integer_type_node
,
13877 integer_type_node
, opaque_V4SI_type_node
,
13878 opaque_V4SI_type_node
, NULL_TREE
);
13879 tree int_ftype_int_v4si_v4si
13880 = build_function_type_list (integer_type_node
,
13881 integer_type_node
, V4SI_type_node
,
13882 V4SI_type_node
, NULL_TREE
);
13883 tree int_ftype_int_v2di_v2di
13884 = build_function_type_list (integer_type_node
,
13885 integer_type_node
, V2DI_type_node
,
13886 V2DI_type_node
, NULL_TREE
);
13887 tree void_ftype_v4si
13888 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
13889 tree v8hi_ftype_void
13890 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
13891 tree void_ftype_void
13892 = build_function_type_list (void_type_node
, NULL_TREE
);
13893 tree void_ftype_int
13894 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
13896 tree opaque_ftype_long_pcvoid
13897 = build_function_type_list (opaque_V4SI_type_node
,
13898 long_integer_type_node
, pcvoid_type_node
,
13900 tree v16qi_ftype_long_pcvoid
13901 = build_function_type_list (V16QI_type_node
,
13902 long_integer_type_node
, pcvoid_type_node
,
13904 tree v8hi_ftype_long_pcvoid
13905 = build_function_type_list (V8HI_type_node
,
13906 long_integer_type_node
, pcvoid_type_node
,
13908 tree v4si_ftype_long_pcvoid
13909 = build_function_type_list (V4SI_type_node
,
13910 long_integer_type_node
, pcvoid_type_node
,
13912 tree v4sf_ftype_long_pcvoid
13913 = build_function_type_list (V4SF_type_node
,
13914 long_integer_type_node
, pcvoid_type_node
,
13916 tree v2df_ftype_long_pcvoid
13917 = build_function_type_list (V2DF_type_node
,
13918 long_integer_type_node
, pcvoid_type_node
,
13920 tree v2di_ftype_long_pcvoid
13921 = build_function_type_list (V2DI_type_node
,
13922 long_integer_type_node
, pcvoid_type_node
,
13925 tree void_ftype_opaque_long_pvoid
13926 = build_function_type_list (void_type_node
,
13927 opaque_V4SI_type_node
, long_integer_type_node
,
13928 pvoid_type_node
, NULL_TREE
);
13929 tree void_ftype_v4si_long_pvoid
13930 = build_function_type_list (void_type_node
,
13931 V4SI_type_node
, long_integer_type_node
,
13932 pvoid_type_node
, NULL_TREE
);
13933 tree void_ftype_v16qi_long_pvoid
13934 = build_function_type_list (void_type_node
,
13935 V16QI_type_node
, long_integer_type_node
,
13936 pvoid_type_node
, NULL_TREE
);
13937 tree void_ftype_v8hi_long_pvoid
13938 = build_function_type_list (void_type_node
,
13939 V8HI_type_node
, long_integer_type_node
,
13940 pvoid_type_node
, NULL_TREE
);
13941 tree void_ftype_v4sf_long_pvoid
13942 = build_function_type_list (void_type_node
,
13943 V4SF_type_node
, long_integer_type_node
,
13944 pvoid_type_node
, NULL_TREE
);
13945 tree void_ftype_v2df_long_pvoid
13946 = build_function_type_list (void_type_node
,
13947 V2DF_type_node
, long_integer_type_node
,
13948 pvoid_type_node
, NULL_TREE
);
13949 tree void_ftype_v2di_long_pvoid
13950 = build_function_type_list (void_type_node
,
13951 V2DI_type_node
, long_integer_type_node
,
13952 pvoid_type_node
, NULL_TREE
);
13953 tree int_ftype_int_v8hi_v8hi
13954 = build_function_type_list (integer_type_node
,
13955 integer_type_node
, V8HI_type_node
,
13956 V8HI_type_node
, NULL_TREE
);
13957 tree int_ftype_int_v16qi_v16qi
13958 = build_function_type_list (integer_type_node
,
13959 integer_type_node
, V16QI_type_node
,
13960 V16QI_type_node
, NULL_TREE
);
13961 tree int_ftype_int_v4sf_v4sf
13962 = build_function_type_list (integer_type_node
,
13963 integer_type_node
, V4SF_type_node
,
13964 V4SF_type_node
, NULL_TREE
);
13965 tree int_ftype_int_v2df_v2df
13966 = build_function_type_list (integer_type_node
,
13967 integer_type_node
, V2DF_type_node
,
13968 V2DF_type_node
, NULL_TREE
);
13969 tree v2di_ftype_v2di
13970 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
13971 tree v4si_ftype_v4si
13972 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
13973 tree v8hi_ftype_v8hi
13974 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
13975 tree v16qi_ftype_v16qi
13976 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
13977 tree v4sf_ftype_v4sf
13978 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
13979 tree v2df_ftype_v2df
13980 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
13981 tree void_ftype_pcvoid_int_int
13982 = build_function_type_list (void_type_node
,
13983 pcvoid_type_node
, integer_type_node
,
13984 integer_type_node
, NULL_TREE
);
13986 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
13987 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
13988 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
13989 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
13990 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
13991 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
13992 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
13993 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
13994 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
13995 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
13996 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
13997 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
13998 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
13999 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
14000 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
14001 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
14002 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
14003 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
14004 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
14005 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
14006 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
14007 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
14008 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
14009 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
14010 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
14011 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
14012 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
14013 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
14014 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
14015 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
14017 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
14018 VSX_BUILTIN_LXVD2X_V2DF
);
14019 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
14020 VSX_BUILTIN_LXVD2X_V2DI
);
14021 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
14022 VSX_BUILTIN_LXVW4X_V4SF
);
14023 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
14024 VSX_BUILTIN_LXVW4X_V4SI
);
14025 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
14026 VSX_BUILTIN_LXVW4X_V8HI
);
14027 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
14028 VSX_BUILTIN_LXVW4X_V16QI
);
14029 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
14030 VSX_BUILTIN_STXVD2X_V2DF
);
14031 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
14032 VSX_BUILTIN_STXVD2X_V2DI
);
14033 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
14034 VSX_BUILTIN_STXVW4X_V4SF
);
14035 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
14036 VSX_BUILTIN_STXVW4X_V4SI
);
14037 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
14038 VSX_BUILTIN_STXVW4X_V8HI
);
14039 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
14040 VSX_BUILTIN_STXVW4X_V16QI
);
14041 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
14042 VSX_BUILTIN_VEC_LD
);
14043 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
14044 VSX_BUILTIN_VEC_ST
);
14046 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
14047 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
14048 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
14050 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
14051 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
14052 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
14053 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
14054 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
14055 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
14056 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
14057 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
14058 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
14059 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
14060 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
14061 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
14063 /* Cell builtins. */
14064 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
14065 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
14066 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
14067 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
14069 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
14070 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
14071 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
14072 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
14074 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
14075 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
14076 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
14077 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
14079 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
14080 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
14081 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
14082 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
14084 /* Add the DST variants. */
14086 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14087 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
14089 /* Initialize the predicates. */
14090 d
= bdesc_altivec_preds
;
14091 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14093 enum machine_mode mode1
;
14096 if (rs6000_overloaded_builtin_p (d
->code
))
14099 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14104 type
= int_ftype_int_opaque_opaque
;
14107 type
= int_ftype_int_v2di_v2di
;
14110 type
= int_ftype_int_v4si_v4si
;
14113 type
= int_ftype_int_v8hi_v8hi
;
14116 type
= int_ftype_int_v16qi_v16qi
;
14119 type
= int_ftype_int_v4sf_v4sf
;
14122 type
= int_ftype_int_v2df_v2df
;
14125 gcc_unreachable ();
14128 def_builtin (d
->name
, type
, d
->code
);
14131 /* Initialize the abs* operators. */
14133 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14135 enum machine_mode mode0
;
14138 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14143 type
= v2di_ftype_v2di
;
14146 type
= v4si_ftype_v4si
;
14149 type
= v8hi_ftype_v8hi
;
14152 type
= v16qi_ftype_v16qi
;
14155 type
= v4sf_ftype_v4sf
;
14158 type
= v2df_ftype_v2df
;
14161 gcc_unreachable ();
14164 def_builtin (d
->name
, type
, d
->code
);
14167 /* Initialize target builtin that implements
14168 targetm.vectorize.builtin_mask_for_load. */
14170 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
14171 v16qi_ftype_long_pcvoid
,
14172 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
14173 BUILT_IN_MD
, NULL
, NULL_TREE
);
14174 TREE_READONLY (decl
) = 1;
14175 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
14176 altivec_builtin_mask_for_load
= decl
;
14178 /* Access to the vec_init patterns. */
14179 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
14180 integer_type_node
, integer_type_node
,
14181 integer_type_node
, NULL_TREE
);
14182 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
14184 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
14185 short_integer_type_node
,
14186 short_integer_type_node
,
14187 short_integer_type_node
,
14188 short_integer_type_node
,
14189 short_integer_type_node
,
14190 short_integer_type_node
,
14191 short_integer_type_node
, NULL_TREE
);
14192 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
14194 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
14195 char_type_node
, char_type_node
,
14196 char_type_node
, char_type_node
,
14197 char_type_node
, char_type_node
,
14198 char_type_node
, char_type_node
,
14199 char_type_node
, char_type_node
,
14200 char_type_node
, char_type_node
,
14201 char_type_node
, char_type_node
,
14202 char_type_node
, NULL_TREE
);
14203 def_builtin ("__builtin_vec_init_v16qi", ftype
,
14204 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
14206 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
14207 float_type_node
, float_type_node
,
14208 float_type_node
, NULL_TREE
);
14209 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
14211 /* VSX builtins. */
14212 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
14213 double_type_node
, NULL_TREE
);
14214 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
14216 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
14217 intDI_type_node
, NULL_TREE
);
14218 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
14220 /* Access to the vec_set patterns. */
14221 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
14223 integer_type_node
, NULL_TREE
);
14224 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
14226 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
14228 integer_type_node
, NULL_TREE
);
14229 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
14231 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
14233 integer_type_node
, NULL_TREE
);
14234 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
14236 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
14238 integer_type_node
, NULL_TREE
);
14239 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
14241 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
14243 integer_type_node
, NULL_TREE
);
14244 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
14246 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
14248 integer_type_node
, NULL_TREE
);
14249 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
14251 /* Access to the vec_extract patterns. */
14252 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
14253 integer_type_node
, NULL_TREE
);
14254 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
14256 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
14257 integer_type_node
, NULL_TREE
);
14258 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
14260 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
14261 integer_type_node
, NULL_TREE
);
14262 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
14264 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
14265 integer_type_node
, NULL_TREE
);
14266 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
14268 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
14269 integer_type_node
, NULL_TREE
);
14270 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
14272 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
14273 integer_type_node
, NULL_TREE
);
14274 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
14278 htm_init_builtins (void)
14280 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14281 const struct builtin_description
*d
;
14285 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14287 tree op
[MAX_HTM_OPERANDS
], type
;
14288 HOST_WIDE_INT mask
= d
->mask
;
14289 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
14290 bool void_func
= (attr
& RS6000_BTC_VOID
);
14291 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
14293 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
14294 : unsigned_type_node
;
14296 if ((mask
& builtin_mask
) != mask
)
14298 if (TARGET_DEBUG_BUILTIN
)
14299 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
14305 if (TARGET_DEBUG_BUILTIN
)
14306 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
14307 (long unsigned) i
);
14311 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
14313 if (attr_args
== RS6000_BTC_UNARY
)
14314 op
[nopnds
++] = argtype
;
14315 else if (attr_args
== RS6000_BTC_BINARY
)
14317 op
[nopnds
++] = argtype
;
14318 op
[nopnds
++] = argtype
;
14320 else if (attr_args
== RS6000_BTC_TERNARY
)
14322 op
[nopnds
++] = argtype
;
14323 op
[nopnds
++] = argtype
;
14324 op
[nopnds
++] = argtype
;
14330 type
= build_function_type_list (op
[0], NULL_TREE
);
14333 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
14336 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
14339 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
14343 gcc_unreachable ();
14346 def_builtin (d
->name
, type
, d
->code
);
14350 /* Hash function for builtin functions with up to 3 arguments and a return
14353 builtin_hash_function (const void *hash_entry
)
14357 const struct builtin_hash_struct
*bh
=
14358 (const struct builtin_hash_struct
*) hash_entry
;
14360 for (i
= 0; i
< 4; i
++)
14362 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
14363 ret
= (ret
* 2) + bh
->uns_p
[i
];
14369 /* Compare builtin hash entries H1 and H2 for equivalence. */
14371 builtin_hash_eq (const void *h1
, const void *h2
)
14373 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
14374 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
14376 return ((p1
->mode
[0] == p2
->mode
[0])
14377 && (p1
->mode
[1] == p2
->mode
[1])
14378 && (p1
->mode
[2] == p2
->mode
[2])
14379 && (p1
->mode
[3] == p2
->mode
[3])
14380 && (p1
->uns_p
[0] == p2
->uns_p
[0])
14381 && (p1
->uns_p
[1] == p2
->uns_p
[1])
14382 && (p1
->uns_p
[2] == p2
->uns_p
[2])
14383 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
14386 /* Map types for builtin functions with an explicit return type and up to 3
14387 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
14388 of the argument. */
14390 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
14391 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
14392 enum rs6000_builtins builtin
, const char *name
)
14394 struct builtin_hash_struct h
;
14395 struct builtin_hash_struct
*h2
;
14399 tree ret_type
= NULL_TREE
;
14400 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
14402 /* Create builtin_hash_table. */
14403 if (builtin_hash_table
== NULL
)
14404 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
14405 builtin_hash_eq
, NULL
);
14407 h
.type
= NULL_TREE
;
14408 h
.mode
[0] = mode_ret
;
14409 h
.mode
[1] = mode_arg0
;
14410 h
.mode
[2] = mode_arg1
;
14411 h
.mode
[3] = mode_arg2
;
14417 /* If the builtin is a type that produces unsigned results or takes unsigned
14418 arguments, and it is returned as a decl for the vectorizer (such as
14419 widening multiplies, permute), make sure the arguments and return value
14420 are type correct. */
14423 /* unsigned 1 argument functions. */
14424 case CRYPTO_BUILTIN_VSBOX
:
14425 case P8V_BUILTIN_VGBBD
:
14430 /* unsigned 2 argument functions. */
14431 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
14432 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
14433 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
14434 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
14435 case CRYPTO_BUILTIN_VCIPHER
:
14436 case CRYPTO_BUILTIN_VCIPHERLAST
:
14437 case CRYPTO_BUILTIN_VNCIPHER
:
14438 case CRYPTO_BUILTIN_VNCIPHERLAST
:
14439 case CRYPTO_BUILTIN_VPMSUMB
:
14440 case CRYPTO_BUILTIN_VPMSUMH
:
14441 case CRYPTO_BUILTIN_VPMSUMW
:
14442 case CRYPTO_BUILTIN_VPMSUMD
:
14443 case CRYPTO_BUILTIN_VPMSUM
:
14449 /* unsigned 3 argument functions. */
14450 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
14451 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
14452 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
14453 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
14454 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
14455 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
14456 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
14457 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
14458 case VSX_BUILTIN_VPERM_16QI_UNS
:
14459 case VSX_BUILTIN_VPERM_8HI_UNS
:
14460 case VSX_BUILTIN_VPERM_4SI_UNS
:
14461 case VSX_BUILTIN_VPERM_2DI_UNS
:
14462 case VSX_BUILTIN_XXSEL_16QI_UNS
:
14463 case VSX_BUILTIN_XXSEL_8HI_UNS
:
14464 case VSX_BUILTIN_XXSEL_4SI_UNS
:
14465 case VSX_BUILTIN_XXSEL_2DI_UNS
:
14466 case CRYPTO_BUILTIN_VPERMXOR
:
14467 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
14468 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
14469 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
14470 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
14471 case CRYPTO_BUILTIN_VSHASIGMAW
:
14472 case CRYPTO_BUILTIN_VSHASIGMAD
:
14473 case CRYPTO_BUILTIN_VSHASIGMA
:
14480 /* signed permute functions with unsigned char mask. */
14481 case ALTIVEC_BUILTIN_VPERM_16QI
:
14482 case ALTIVEC_BUILTIN_VPERM_8HI
:
14483 case ALTIVEC_BUILTIN_VPERM_4SI
:
14484 case ALTIVEC_BUILTIN_VPERM_4SF
:
14485 case ALTIVEC_BUILTIN_VPERM_2DI
:
14486 case ALTIVEC_BUILTIN_VPERM_2DF
:
14487 case VSX_BUILTIN_VPERM_16QI
:
14488 case VSX_BUILTIN_VPERM_8HI
:
14489 case VSX_BUILTIN_VPERM_4SI
:
14490 case VSX_BUILTIN_VPERM_4SF
:
14491 case VSX_BUILTIN_VPERM_2DI
:
14492 case VSX_BUILTIN_VPERM_2DF
:
14496 /* unsigned args, signed return. */
14497 case VSX_BUILTIN_XVCVUXDDP_UNS
:
14498 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
14502 /* signed args, unsigned return. */
14503 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
14504 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
14512 /* Figure out how many args are present. */
14513 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
14517 fatal_error ("internal error: builtin function %s had no type", name
);
14519 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
14520 if (!ret_type
&& h
.uns_p
[0])
14521 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
14524 fatal_error ("internal error: builtin function %s had an unexpected "
14525 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
14527 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
14528 arg_type
[i
] = NULL_TREE
;
14530 for (i
= 0; i
< num_args
; i
++)
14532 int m
= (int) h
.mode
[i
+1];
14533 int uns_p
= h
.uns_p
[i
+1];
14535 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
14536 if (!arg_type
[i
] && uns_p
)
14537 arg_type
[i
] = builtin_mode_to_type
[m
][0];
14540 fatal_error ("internal error: builtin function %s, argument %d "
14541 "had unexpected argument type %s", name
, i
,
14542 GET_MODE_NAME (m
));
14545 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
14546 if (*found
== NULL
)
14548 h2
= ggc_alloc_builtin_hash_struct ();
14550 *found
= (void *)h2
;
14552 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
14553 arg_type
[2], NULL_TREE
);
14556 return ((struct builtin_hash_struct
*)(*found
))->type
;
14560 rs6000_common_init_builtins (void)
14562 const struct builtin_description
*d
;
14565 tree opaque_ftype_opaque
= NULL_TREE
;
14566 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
14567 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
14568 tree v2si_ftype_qi
= NULL_TREE
;
14569 tree v2si_ftype_v2si_qi
= NULL_TREE
;
14570 tree v2si_ftype_int_qi
= NULL_TREE
;
14571 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14573 if (!TARGET_PAIRED_FLOAT
)
14575 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
14576 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
14579 /* Paired and SPE builtins are only available if you build a compiler with
14580 the appropriate options, so only create those builtins with the
14581 appropriate compiler option. Create Altivec and VSX builtins on machines
14582 with at least the general purpose extensions (970 and newer) to allow the
14583 use of the target attribute.. */
14585 if (TARGET_EXTRA_BUILTINS
)
14586 builtin_mask
|= RS6000_BTM_COMMON
;
14588 /* Add the ternary operators. */
14590 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
14593 HOST_WIDE_INT mask
= d
->mask
;
14595 if ((mask
& builtin_mask
) != mask
)
14597 if (TARGET_DEBUG_BUILTIN
)
14598 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
14602 if (rs6000_overloaded_builtin_p (d
->code
))
14604 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
14605 type
= opaque_ftype_opaque_opaque_opaque
14606 = build_function_type_list (opaque_V4SI_type_node
,
14607 opaque_V4SI_type_node
,
14608 opaque_V4SI_type_node
,
14609 opaque_V4SI_type_node
,
14614 enum insn_code icode
= d
->icode
;
14617 if (TARGET_DEBUG_BUILTIN
)
14618 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
14624 if (icode
== CODE_FOR_nothing
)
14626 if (TARGET_DEBUG_BUILTIN
)
14627 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
14633 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
14634 insn_data
[icode
].operand
[1].mode
,
14635 insn_data
[icode
].operand
[2].mode
,
14636 insn_data
[icode
].operand
[3].mode
,
14640 def_builtin (d
->name
, type
, d
->code
);
14643 /* Add the binary operators. */
14645 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
14647 enum machine_mode mode0
, mode1
, mode2
;
14649 HOST_WIDE_INT mask
= d
->mask
;
14651 if ((mask
& builtin_mask
) != mask
)
14653 if (TARGET_DEBUG_BUILTIN
)
14654 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
14658 if (rs6000_overloaded_builtin_p (d
->code
))
14660 if (! (type
= opaque_ftype_opaque_opaque
))
14661 type
= opaque_ftype_opaque_opaque
14662 = build_function_type_list (opaque_V4SI_type_node
,
14663 opaque_V4SI_type_node
,
14664 opaque_V4SI_type_node
,
14669 enum insn_code icode
= d
->icode
;
14672 if (TARGET_DEBUG_BUILTIN
)
14673 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
14679 if (icode
== CODE_FOR_nothing
)
14681 if (TARGET_DEBUG_BUILTIN
)
14682 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
14688 mode0
= insn_data
[icode
].operand
[0].mode
;
14689 mode1
= insn_data
[icode
].operand
[1].mode
;
14690 mode2
= insn_data
[icode
].operand
[2].mode
;
14692 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
14694 if (! (type
= v2si_ftype_v2si_qi
))
14695 type
= v2si_ftype_v2si_qi
14696 = build_function_type_list (opaque_V2SI_type_node
,
14697 opaque_V2SI_type_node
,
14702 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
14703 && mode2
== QImode
)
14705 if (! (type
= v2si_ftype_int_qi
))
14706 type
= v2si_ftype_int_qi
14707 = build_function_type_list (opaque_V2SI_type_node
,
14714 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
14718 def_builtin (d
->name
, type
, d
->code
);
14721 /* Add the simple unary operators. */
14723 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
14725 enum machine_mode mode0
, mode1
;
14727 HOST_WIDE_INT mask
= d
->mask
;
14729 if ((mask
& builtin_mask
) != mask
)
14731 if (TARGET_DEBUG_BUILTIN
)
14732 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
14736 if (rs6000_overloaded_builtin_p (d
->code
))
14738 if (! (type
= opaque_ftype_opaque
))
14739 type
= opaque_ftype_opaque
14740 = build_function_type_list (opaque_V4SI_type_node
,
14741 opaque_V4SI_type_node
,
14746 enum insn_code icode
= d
->icode
;
14749 if (TARGET_DEBUG_BUILTIN
)
14750 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
14756 if (icode
== CODE_FOR_nothing
)
14758 if (TARGET_DEBUG_BUILTIN
)
14759 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
14765 mode0
= insn_data
[icode
].operand
[0].mode
;
14766 mode1
= insn_data
[icode
].operand
[1].mode
;
14768 if (mode0
== V2SImode
&& mode1
== QImode
)
14770 if (! (type
= v2si_ftype_qi
))
14771 type
= v2si_ftype_qi
14772 = build_function_type_list (opaque_V2SI_type_node
,
14778 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
14782 def_builtin (d
->name
, type
, d
->code
);
14787 rs6000_init_libfuncs (void)
14789 if (!TARGET_IEEEQUAD
)
14790 /* AIX/Darwin/64-bit Linux quad floating point routines. */
14791 if (!TARGET_XL_COMPAT
)
14793 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
14794 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
14795 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
14796 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
14798 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
14800 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
14801 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
14802 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
14803 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
14804 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
14805 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
14806 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
14808 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
14809 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
14810 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
14811 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
14812 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
14813 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
14814 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
14815 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
14818 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
14819 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
14823 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
14824 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
14825 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
14826 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
14830 /* 32-bit SVR4 quad floating point routines. */
14832 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
14833 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
14834 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
14835 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
14836 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
14837 if (TARGET_PPC_GPOPT
)
14838 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
14840 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
14841 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
14842 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
14843 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
14844 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
14845 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
14847 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
14848 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
14849 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
14850 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
14851 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
14852 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
14853 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
14854 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
14859 /* Expand a block clear operation, and return 1 if successful. Return 0
14860 if we should let the compiler generate normal code.
14862 operands[0] is the destination
14863 operands[1] is the length
14864 operands[3] is the alignment */
14867 expand_block_clear (rtx operands
[])
14869 rtx orig_dest
= operands
[0];
14870 rtx bytes_rtx
= operands
[1];
14871 rtx align_rtx
= operands
[3];
14872 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14873 HOST_WIDE_INT align
;
14874 HOST_WIDE_INT bytes
;
14879 /* If this is not a fixed size move, just call memcpy */
14883 /* This must be a fixed size alignment */
14884 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14885 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14887 /* Anything to clear? */
14888 bytes
= INTVAL (bytes_rtx
);
14892 /* Use the builtin memset after a point, to avoid huge code bloat.
14893 When optimize_size, avoid any significant code bloat; calling
14894 memset is about 4 instructions, so allow for one instruction to
14895 load zero and three to do clearing. */
14896 if (TARGET_ALTIVEC
&& align
>= 128)
14898 else if (TARGET_POWERPC64
&& align
>= 32)
14900 else if (TARGET_SPE
&& align
>= 64)
14905 if (optimize_size
&& bytes
> 3 * clear_step
)
14907 if (! optimize_size
&& bytes
> 8 * clear_step
)
14910 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
14912 enum machine_mode mode
= BLKmode
;
14915 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
14920 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
14925 else if (bytes
>= 8 && TARGET_POWERPC64
14926 /* 64-bit loads and stores require word-aligned
14928 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
14933 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
14934 { /* move 4 bytes */
14938 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
14939 { /* move 2 bytes */
14943 else /* move 1 byte at a time */
14949 dest
= adjust_address (orig_dest
, mode
, offset
);
14951 emit_move_insn (dest
, CONST0_RTX (mode
));
14958 /* Expand a block move operation, and return 1 if successful. Return 0
14959 if we should let the compiler generate normal code.
14961 operands[0] is the destination
14962 operands[1] is the source
14963 operands[2] is the length
14964 operands[3] is the alignment */
14966 #define MAX_MOVE_REG 4
14969 expand_block_move (rtx operands
[])
14971 rtx orig_dest
= operands
[0];
14972 rtx orig_src
= operands
[1];
14973 rtx bytes_rtx
= operands
[2];
14974 rtx align_rtx
= operands
[3];
14975 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14980 rtx stores
[MAX_MOVE_REG
];
14983 /* If this is not a fixed size move, just call memcpy */
14987 /* This must be a fixed size alignment */
14988 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14989 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14991 /* Anything to move? */
14992 bytes
= INTVAL (bytes_rtx
);
14996 if (bytes
> rs6000_block_move_inline_limit
)
14999 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
15002 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
15003 rtx (*mov
) (rtx
, rtx
);
15005 enum machine_mode mode
= BLKmode
;
15008 /* Altivec first, since it will be faster than a string move
15009 when it applies, and usually not significantly larger. */
15010 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
15014 gen_func
.mov
= gen_movv4si
;
15016 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
15020 gen_func
.mov
= gen_movv2si
;
15022 else if (TARGET_STRING
15023 && bytes
> 24 /* move up to 32 bytes at a time */
15029 && ! fixed_regs
[10]
15030 && ! fixed_regs
[11]
15031 && ! fixed_regs
[12])
15033 move_bytes
= (bytes
> 32) ? 32 : bytes
;
15034 gen_func
.movmemsi
= gen_movmemsi_8reg
;
15036 else if (TARGET_STRING
15037 && bytes
> 16 /* move up to 24 bytes at a time */
15043 && ! fixed_regs
[10])
15045 move_bytes
= (bytes
> 24) ? 24 : bytes
;
15046 gen_func
.movmemsi
= gen_movmemsi_6reg
;
15048 else if (TARGET_STRING
15049 && bytes
> 8 /* move up to 16 bytes at a time */
15053 && ! fixed_regs
[8])
15055 move_bytes
= (bytes
> 16) ? 16 : bytes
;
15056 gen_func
.movmemsi
= gen_movmemsi_4reg
;
15058 else if (bytes
>= 8 && TARGET_POWERPC64
15059 /* 64-bit loads and stores require word-aligned
15061 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
15065 gen_func
.mov
= gen_movdi
;
15067 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
15068 { /* move up to 8 bytes at a time */
15069 move_bytes
= (bytes
> 8) ? 8 : bytes
;
15070 gen_func
.movmemsi
= gen_movmemsi_2reg
;
15072 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15073 { /* move 4 bytes */
15076 gen_func
.mov
= gen_movsi
;
15078 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15079 { /* move 2 bytes */
15082 gen_func
.mov
= gen_movhi
;
15084 else if (TARGET_STRING
&& bytes
> 1)
15085 { /* move up to 4 bytes at a time */
15086 move_bytes
= (bytes
> 4) ? 4 : bytes
;
15087 gen_func
.movmemsi
= gen_movmemsi_1reg
;
15089 else /* move 1 byte at a time */
15093 gen_func
.mov
= gen_movqi
;
15096 src
= adjust_address (orig_src
, mode
, offset
);
15097 dest
= adjust_address (orig_dest
, mode
, offset
);
15099 if (mode
!= BLKmode
)
15101 rtx tmp_reg
= gen_reg_rtx (mode
);
15103 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
15104 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
15107 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
15110 for (i
= 0; i
< num_reg
; i
++)
15111 emit_insn (stores
[i
]);
15115 if (mode
== BLKmode
)
15117 /* Move the address into scratch registers. The movmemsi
15118 patterns require zero offset. */
15119 if (!REG_P (XEXP (src
, 0)))
15121 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
15122 src
= replace_equiv_address (src
, src_reg
);
15124 set_mem_size (src
, move_bytes
);
15126 if (!REG_P (XEXP (dest
, 0)))
15128 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
15129 dest
= replace_equiv_address (dest
, dest_reg
);
15131 set_mem_size (dest
, move_bytes
);
15133 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
15134 GEN_INT (move_bytes
& 31),
15143 /* Return a string to perform a load_multiple operation.
15144 operands[0] is the vector.
15145 operands[1] is the source address.
15146 operands[2] is the first destination register. */
15149 rs6000_output_load_multiple (rtx operands
[3])
15151 /* We have to handle the case where the pseudo used to contain the address
15152 is assigned to one of the output registers. */
15154 int words
= XVECLEN (operands
[0], 0);
15157 if (XVECLEN (operands
[0], 0) == 1)
15158 return "lwz %2,0(%1)";
15160 for (i
= 0; i
< words
; i
++)
15161 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
15162 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
15166 xop
[0] = GEN_INT (4 * (words
-1));
15167 xop
[1] = operands
[1];
15168 xop
[2] = operands
[2];
15169 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
15174 xop
[0] = GEN_INT (4 * (words
-1));
15175 xop
[1] = operands
[1];
15176 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
15177 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
15182 for (j
= 0; j
< words
; j
++)
15185 xop
[0] = GEN_INT (j
* 4);
15186 xop
[1] = operands
[1];
15187 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
15188 output_asm_insn ("lwz %2,%0(%1)", xop
);
15190 xop
[0] = GEN_INT (i
* 4);
15191 xop
[1] = operands
[1];
15192 output_asm_insn ("lwz %1,%0(%1)", xop
);
15197 return "lswi %2,%1,%N0";
15201 /* A validation routine: say whether CODE, a condition code, and MODE
15202 match. The other alternatives either don't make sense or should
15203 never be generated. */
15206 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
15208 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
15209 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
15210 && GET_MODE_CLASS (mode
) == MODE_CC
);
15212 /* These don't make sense. */
15213 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
15214 || mode
!= CCUNSmode
);
15216 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
15217 || mode
== CCUNSmode
);
15219 gcc_assert (mode
== CCFPmode
15220 || (code
!= ORDERED
&& code
!= UNORDERED
15221 && code
!= UNEQ
&& code
!= LTGT
15222 && code
!= UNGT
&& code
!= UNLT
15223 && code
!= UNGE
&& code
!= UNLE
));
15225 /* These should never be generated except for
15226 flag_finite_math_only. */
15227 gcc_assert (mode
!= CCFPmode
15228 || flag_finite_math_only
15229 || (code
!= LE
&& code
!= GE
15230 && code
!= UNEQ
&& code
!= LTGT
15231 && code
!= UNGT
&& code
!= UNLT
));
15233 /* These are invalid; the information is not there. */
15234 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
15238 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
15239 mask required to convert the result of a rotate insn into a shift
15240 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
15243 includes_lshift_p (rtx shiftop
, rtx andop
)
15245 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15247 shift_mask
<<= INTVAL (shiftop
);
15249 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15252 /* Similar, but for right shift. */
15255 includes_rshift_p (rtx shiftop
, rtx andop
)
15257 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15259 shift_mask
>>= INTVAL (shiftop
);
15261 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15264 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
15265 to perform a left shift. It must have exactly SHIFTOP least
15266 significant 0's, then one or more 1's, then zero or more 0's. */
15269 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
15271 if (GET_CODE (andop
) == CONST_INT
)
15273 HOST_WIDE_INT c
, lsb
, shift_mask
;
15275 c
= INTVAL (andop
);
15276 if (c
== 0 || c
== ~0)
15280 shift_mask
<<= INTVAL (shiftop
);
15282 /* Find the least significant one bit. */
15285 /* It must coincide with the LSB of the shift mask. */
15286 if (-lsb
!= shift_mask
)
15289 /* Invert to look for the next transition (if any). */
15292 /* Remove the low group of ones (originally low group of zeros). */
15295 /* Again find the lsb, and check we have all 1's above. */
15303 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
15304 to perform a left shift. It must have SHIFTOP or more least
15305 significant 0's, with the remainder of the word 1's. */
15308 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
15310 if (GET_CODE (andop
) == CONST_INT
)
15312 HOST_WIDE_INT c
, lsb
, shift_mask
;
15315 shift_mask
<<= INTVAL (shiftop
);
15316 c
= INTVAL (andop
);
15318 /* Find the least significant one bit. */
15321 /* It must be covered by the shift mask.
15322 This test also rejects c == 0. */
15323 if ((lsb
& shift_mask
) == 0)
15326 /* Check we have all 1's above the transition, and reject all 1's. */
15327 return c
== -lsb
&& lsb
!= 1;
15333 /* Return 1 if operands will generate a valid arguments to rlwimi
15334 instruction for insert with right shift in 64-bit mode. The mask may
15335 not start on the first bit or stop on the last bit because wrap-around
15336 effects of instruction do not correspond to semantics of RTL insn. */
15339 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
15341 if (INTVAL (startop
) > 32
15342 && INTVAL (startop
) < 64
15343 && INTVAL (sizeop
) > 1
15344 && INTVAL (sizeop
) + INTVAL (startop
) < 64
15345 && INTVAL (shiftop
) > 0
15346 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
15347 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
15353 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
15354 for lfq and stfq insns iff the registers are hard registers. */
15357 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
15359 /* We might have been passed a SUBREG. */
15360 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
15363 /* We might have been passed non floating point registers. */
15364 if (!FP_REGNO_P (REGNO (reg1
))
15365 || !FP_REGNO_P (REGNO (reg2
)))
15368 return (REGNO (reg1
) == REGNO (reg2
) - 1);
15371 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
15372 addr1 and addr2 must be in consecutive memory locations
15373 (addr2 == addr1 + 8). */
15376 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
15379 unsigned int reg1
, reg2
;
15380 int offset1
, offset2
;
15382 /* The mems cannot be volatile. */
15383 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
15386 addr1
= XEXP (mem1
, 0);
15387 addr2
= XEXP (mem2
, 0);
15389 /* Extract an offset (if used) from the first addr. */
15390 if (GET_CODE (addr1
) == PLUS
)
15392 /* If not a REG, return zero. */
15393 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
15397 reg1
= REGNO (XEXP (addr1
, 0));
15398 /* The offset must be constant! */
15399 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
15401 offset1
= INTVAL (XEXP (addr1
, 1));
15404 else if (GET_CODE (addr1
) != REG
)
15408 reg1
= REGNO (addr1
);
15409 /* This was a simple (mem (reg)) expression. Offset is 0. */
15413 /* And now for the second addr. */
15414 if (GET_CODE (addr2
) == PLUS
)
15416 /* If not a REG, return zero. */
15417 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
15421 reg2
= REGNO (XEXP (addr2
, 0));
15422 /* The offset must be constant. */
15423 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
15425 offset2
= INTVAL (XEXP (addr2
, 1));
15428 else if (GET_CODE (addr2
) != REG
)
15432 reg2
= REGNO (addr2
);
15433 /* This was a simple (mem (reg)) expression. Offset is 0. */
15437 /* Both of these must have the same base register. */
15441 /* The offset for the second addr must be 8 more than the first addr. */
15442 if (offset2
!= offset1
+ 8)
15445 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
15452 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
15454 static bool eliminated
= false;
15457 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
15458 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
15461 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
15462 gcc_assert (mem
!= NULL_RTX
);
15466 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
15467 cfun
->machine
->sdmode_stack_slot
= mem
;
15473 if (TARGET_DEBUG_ADDR
)
15475 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
15476 GET_MODE_NAME (mode
));
15478 fprintf (stderr
, "\tNULL_RTX\n");
15486 /* Return the mode to be used for memory when a secondary memory
15487 location is needed. For SDmode values we need to use DDmode, in
15488 all other cases we can use the same mode. */
15490 rs6000_secondary_memory_needed_mode (enum machine_mode mode
)
15492 if (mode
== SDmode
)
15498 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
15500 /* Don't walk into types. */
15501 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
15503 *walk_subtrees
= 0;
15507 switch (TREE_CODE (*tp
))
15516 case VIEW_CONVERT_EXPR
:
15517 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
15527 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
15528 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
15529 only work on the traditional altivec registers, note if an altivec register
15532 static enum rs6000_reg_type
15533 register_to_reg_type (rtx reg
, bool *is_altivec
)
15535 HOST_WIDE_INT regno
;
15536 enum reg_class rclass
;
15538 if (GET_CODE (reg
) == SUBREG
)
15539 reg
= SUBREG_REG (reg
);
15542 return NO_REG_TYPE
;
15544 regno
= REGNO (reg
);
15545 if (regno
>= FIRST_PSEUDO_REGISTER
)
15547 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
15548 return PSEUDO_REG_TYPE
;
15550 regno
= true_regnum (reg
);
15551 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15552 return PSEUDO_REG_TYPE
;
15555 gcc_assert (regno
>= 0);
15557 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
15558 *is_altivec
= true;
15560 rclass
= rs6000_regno_regclass
[regno
];
15561 return reg_class_to_reg_type
[(int)rclass
];
15564 /* Helper function for rs6000_secondary_reload to return true if a move to a
15565 different register classe is really a simple move. */
15568 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
15569 enum rs6000_reg_type from_type
,
15570 enum machine_mode mode
)
15574 /* Add support for various direct moves available. In this function, we only
15575 look at cases where we don't need any extra registers, and one or more
15576 simple move insns are issued. At present, 32-bit integers are not allowed
15577 in FPR/VSX registers. Single precision binary floating is not a simple
15578 move because we need to convert to the single precision memory layout.
15579 The 4-byte SDmode can be moved. */
15580 size
= GET_MODE_SIZE (mode
);
15581 if (TARGET_DIRECT_MOVE
15582 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
15583 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15584 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15587 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
15588 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
15589 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15592 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
15593 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
15594 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15600 /* Power8 helper function for rs6000_secondary_reload, handle all of the
15601 special direct moves that involve allocating an extra register, return the
15602 insn code of the helper function if there is such a function or
15603 CODE_FOR_nothing if not. */
15606 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
15607 enum rs6000_reg_type from_type
,
15608 enum machine_mode mode
,
15609 secondary_reload_info
*sri
,
15613 enum insn_code icode
= CODE_FOR_nothing
;
15615 int size
= GET_MODE_SIZE (mode
);
15617 if (TARGET_POWERPC64
)
15621 /* Handle moving 128-bit values from GPRs to VSX point registers on
15622 power8 when running in 64-bit mode using XXPERMDI to glue the two
15623 64-bit values back together. */
15624 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15626 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
15627 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15630 /* Handle moving 128-bit values from VSX point registers to GPRs on
15631 power8 when running in 64-bit mode using XXPERMDI to get access to the
15632 bottom 64-bit value. */
15633 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15635 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
15636 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15640 else if (mode
== SFmode
)
15642 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15644 cost
= 3; /* xscvdpspn, mfvsrd, and. */
15645 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15648 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15650 cost
= 2; /* mtvsrz, xscvspdpn. */
15651 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15656 if (TARGET_POWERPC64
&& size
== 16)
15658 /* Handle moving 128-bit values from GPRs to VSX point registers on
15659 power8 when running in 64-bit mode using XXPERMDI to glue the two
15660 64-bit values back together. */
15661 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15663 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
15664 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15667 /* Handle moving 128-bit values from VSX point registers to GPRs on
15668 power8 when running in 64-bit mode using XXPERMDI to get access to the
15669 bottom 64-bit value. */
15670 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15672 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
15673 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15677 else if (!TARGET_POWERPC64
&& size
== 8)
15679 /* Handle moving 64-bit values from GPRs to floating point registers on
15680 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
15681 values back together. Altivec register classes must be handled
15682 specially since a different instruction is used, and the secondary
15683 reload support requires a single instruction class in the scratch
15684 register constraint. However, right now TFmode is not allowed in
15685 Altivec registers, so the pattern will never match. */
15686 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
15688 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
15689 icode
= reg_addr
[mode
].reload_fpr_gpr
;
15693 if (icode
!= CODE_FOR_nothing
)
15698 sri
->icode
= icode
;
15699 sri
->extra_cost
= cost
;
15706 /* Return whether a move between two register classes can be done either
15707 directly (simple move) or via a pattern that uses a single extra temporary
15708 (using power8's direct move in this case. */
15711 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
15712 enum rs6000_reg_type from_type
,
15713 enum machine_mode mode
,
15714 secondary_reload_info
*sri
,
15717 /* Fall back to load/store reloads if either type is not a register. */
15718 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
15721 /* If we haven't allocated registers yet, assume the move can be done for the
15722 standard register types. */
15723 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
15724 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
15725 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
15728 /* Moves to the same set of registers is a simple move for non-specialized
15730 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
15733 /* Check whether a simple move can be done directly. */
15734 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
15738 sri
->icode
= CODE_FOR_nothing
;
15739 sri
->extra_cost
= 0;
15744 /* Now check if we can do it in a few steps. */
15745 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
15749 /* Inform reload about cases where moving X with a mode MODE to a register in
15750 RCLASS requires an extra scratch or immediate register. Return the class
15751 needed for the immediate register.
15753 For VSX and Altivec, we may need a register to convert sp+offset into
15756 For misaligned 64-bit gpr loads and stores we need a register to
15757 convert an offset address to indirect. */
15760 rs6000_secondary_reload (bool in_p
,
15762 reg_class_t rclass_i
,
15763 enum machine_mode mode
,
15764 secondary_reload_info
*sri
)
15766 enum reg_class rclass
= (enum reg_class
) rclass_i
;
15767 reg_class_t ret
= ALL_REGS
;
15768 enum insn_code icode
;
15769 bool default_p
= false;
15771 sri
->icode
= CODE_FOR_nothing
;
15773 ? reg_addr
[mode
].reload_load
15774 : reg_addr
[mode
].reload_store
);
15776 if (REG_P (x
) || register_operand (x
, mode
))
15778 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
15779 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
15780 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
15784 enum rs6000_reg_type exchange
= to_type
;
15785 to_type
= from_type
;
15786 from_type
= exchange
;
15789 /* Can we do a direct move of some sort? */
15790 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
15793 icode
= (enum insn_code
)sri
->icode
;
15799 /* Handle vector moves with reload helper functions. */
15800 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
15803 sri
->icode
= CODE_FOR_nothing
;
15804 sri
->extra_cost
= 0;
15806 if (GET_CODE (x
) == MEM
)
15808 rtx addr
= XEXP (x
, 0);
15810 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
15811 an extra register in that case, but it would need an extra
15812 register if the addressing is reg+reg or (reg+reg)&(-16). Special
15813 case load/store quad. */
15814 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
15816 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
15817 && GET_MODE_SIZE (mode
) == 16
15818 && quad_memory_operand (x
, mode
))
15820 sri
->icode
= icode
;
15821 sri
->extra_cost
= 2;
15824 else if (!legitimate_indirect_address_p (addr
, false)
15825 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
15828 sri
->icode
= icode
;
15829 /* account for splitting the loads, and converting the
15830 address from reg+reg to reg. */
15831 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
15832 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
15835 /* Allow scalar loads to/from the traditional floating point
15836 registers, even if VSX memory is set. */
15837 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
15838 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
15839 && (legitimate_indirect_address_p (addr
, false)
15840 || legitimate_indirect_address_p (addr
, false)
15841 || rs6000_legitimate_offset_address_p (mode
, addr
,
15845 /* Loads to and stores from vector registers can only do reg+reg
15846 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
15847 scalar modes loading up the traditional floating point registers
15848 to use offset addresses. */
15849 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
15850 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
15852 if (!VECTOR_MEM_ALTIVEC_P (mode
)
15853 && GET_CODE (addr
) == AND
15854 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15855 && INTVAL (XEXP (addr
, 1)) == -16
15856 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
15857 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
15859 sri
->icode
= icode
;
15860 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
15863 else if (!legitimate_indirect_address_p (addr
, false)
15864 && (rclass
== NO_REGS
15865 || !legitimate_indexed_address_p (addr
, false)))
15867 sri
->icode
= icode
;
15868 sri
->extra_cost
= 1;
15871 icode
= CODE_FOR_nothing
;
15873 /* Any other loads, including to pseudo registers which haven't been
15874 assigned to a register yet, default to require a scratch
15878 sri
->icode
= icode
;
15879 sri
->extra_cost
= 2;
15882 else if (REG_P (x
))
15884 int regno
= true_regnum (x
);
15886 icode
= CODE_FOR_nothing
;
15887 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15891 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
15892 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
15893 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
15895 /* If memory is needed, use default_secondary_reload to create the
15897 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
15906 else if (TARGET_POWERPC64
15907 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15909 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
15911 rtx addr
= XEXP (x
, 0);
15912 rtx off
= address_offset (addr
);
15914 if (off
!= NULL_RTX
)
15916 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15917 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15919 /* We need a secondary reload when our legitimate_address_p
15920 says the address is good (as otherwise the entire address
15921 will be reloaded), and the offset is not a multiple of
15922 four or we have an address wrap. Address wrap will only
15923 occur for LO_SUMs since legitimate_offset_address_p
15924 rejects addresses for 16-byte mems that will wrap. */
15925 if (GET_CODE (addr
) == LO_SUM
15926 ? (1 /* legitimate_address_p allows any offset for lo_sum */
15927 && ((offset
& 3) != 0
15928 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
15929 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
15930 && (offset
& 3) != 0))
15933 sri
->icode
= CODE_FOR_reload_di_load
;
15935 sri
->icode
= CODE_FOR_reload_di_store
;
15936 sri
->extra_cost
= 2;
15945 else if (!TARGET_POWERPC64
15946 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15948 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
15950 rtx addr
= XEXP (x
, 0);
15951 rtx off
= address_offset (addr
);
15953 if (off
!= NULL_RTX
)
15955 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15956 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15958 /* We need a secondary reload when our legitimate_address_p
15959 says the address is good (as otherwise the entire address
15960 will be reloaded), and we have a wrap.
15962 legitimate_lo_sum_address_p allows LO_SUM addresses to
15963 have any offset so test for wrap in the low 16 bits.
15965 legitimate_offset_address_p checks for the range
15966 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
15967 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
15968 [0x7ff4,0x7fff] respectively, so test for the
15969 intersection of these ranges, [0x7ffc,0x7fff] and
15970 [0x7ff4,0x7ff7] respectively.
15972 Note that the address we see here may have been
15973 manipulated by legitimize_reload_address. */
15974 if (GET_CODE (addr
) == LO_SUM
15975 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
15976 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
15979 sri
->icode
= CODE_FOR_reload_si_load
;
15981 sri
->icode
= CODE_FOR_reload_si_store
;
15982 sri
->extra_cost
= 2;
15995 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
15997 gcc_assert (ret
!= ALL_REGS
);
15999 if (TARGET_DEBUG_ADDR
)
16002 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
16004 reg_class_names
[ret
],
16005 in_p
? "true" : "false",
16006 reg_class_names
[rclass
],
16007 GET_MODE_NAME (mode
));
16010 fprintf (stderr
, ", default secondary reload");
16012 if (sri
->icode
!= CODE_FOR_nothing
)
16013 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
16014 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
16016 fprintf (stderr
, "\n");
16024 /* Better tracing for rs6000_secondary_reload_inner. */
16027 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
16032 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
16034 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
16035 store_p
? "store" : "load");
16038 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
16040 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
16042 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
16043 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
16047 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
16050 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
16051 gcc_unreachable ();
16054 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
16055 to SP+reg addressing. */
16058 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16060 int regno
= true_regnum (reg
);
16061 enum machine_mode mode
= GET_MODE (reg
);
16062 enum reg_class rclass
;
16064 rtx and_op2
= NULL_RTX
;
16067 rtx scratch_or_premodify
= scratch
;
16071 if (TARGET_DEBUG_ADDR
)
16072 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
16074 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16075 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16077 if (GET_CODE (mem
) != MEM
)
16078 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16080 rclass
= REGNO_REG_CLASS (regno
);
16081 addr
= XEXP (mem
, 0);
16085 /* GPRs can handle reg + small constant, all other addresses need to use
16086 the scratch register. */
16089 if (GET_CODE (addr
) == AND
)
16091 and_op2
= XEXP (addr
, 1);
16092 addr
= XEXP (addr
, 0);
16095 if (GET_CODE (addr
) == PRE_MODIFY
)
16097 scratch_or_premodify
= XEXP (addr
, 0);
16098 if (!REG_P (scratch_or_premodify
))
16099 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16101 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
16102 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16104 addr
= XEXP (addr
, 1);
16107 if (GET_CODE (addr
) == PLUS
16108 && (and_op2
!= NULL_RTX
16109 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16112 addr_op1
= XEXP (addr
, 0);
16113 addr_op2
= XEXP (addr
, 1);
16114 if (!legitimate_indirect_address_p (addr_op1
, false))
16115 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16117 if (!REG_P (addr_op2
)
16118 && (GET_CODE (addr_op2
) != CONST_INT
16119 || !satisfies_constraint_I (addr_op2
)))
16121 if (TARGET_DEBUG_ADDR
)
16124 "\nMove plus addr to register %s, mode = %s: ",
16125 rs6000_reg_names
[REGNO (scratch
)],
16126 GET_MODE_NAME (mode
));
16127 debug_rtx (addr_op2
);
16129 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16130 addr_op2
= scratch
;
16133 emit_insn (gen_rtx_SET (VOIDmode
,
16134 scratch_or_premodify
,
16135 gen_rtx_PLUS (Pmode
,
16139 addr
= scratch_or_premodify
;
16140 scratch_or_premodify
= scratch
;
16142 else if (!legitimate_indirect_address_p (addr
, false)
16143 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16146 if (TARGET_DEBUG_ADDR
)
16148 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16149 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16150 GET_MODE_NAME (mode
));
16153 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16154 addr
= scratch_or_premodify
;
16155 scratch_or_premodify
= scratch
;
16159 /* Float registers can do offset+reg addressing for scalar types. */
16161 if (legitimate_indirect_address_p (addr
, false) /* reg */
16162 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16163 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16164 && and_op2
== NULL_RTX
16165 && scratch_or_premodify
== scratch
16166 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
16169 /* If this isn't a legacy floating point load/store, fall through to the
16172 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
16173 addresses into a scratch register. */
16177 /* With float regs, we need to handle the AND ourselves, since we can't
16178 use the Altivec instruction with an implicit AND -16. Allow scalar
16179 loads to float registers to use reg+offset even if VSX. */
16180 if (GET_CODE (addr
) == AND
16181 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
16182 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
16183 || INTVAL (XEXP (addr
, 1)) != -16
16184 || !VECTOR_MEM_ALTIVEC_P (mode
)))
16186 and_op2
= XEXP (addr
, 1);
16187 addr
= XEXP (addr
, 0);
16190 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
16191 as the address later. */
16192 if (GET_CODE (addr
) == PRE_MODIFY
16193 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
16194 && (rclass
!= FLOAT_REGS
16195 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
16196 || and_op2
!= NULL_RTX
16197 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
16199 scratch_or_premodify
= XEXP (addr
, 0);
16200 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
16201 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16203 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
16204 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16206 addr
= XEXP (addr
, 1);
16209 if (legitimate_indirect_address_p (addr
, false) /* reg */
16210 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16211 || (GET_CODE (addr
) == AND
/* Altivec memory */
16212 && rclass
== ALTIVEC_REGS
16213 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16214 && INTVAL (XEXP (addr
, 1)) == -16
16215 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16216 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
16219 else if (GET_CODE (addr
) == PLUS
)
16221 addr_op1
= XEXP (addr
, 0);
16222 addr_op2
= XEXP (addr
, 1);
16223 if (!REG_P (addr_op1
))
16224 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16226 if (TARGET_DEBUG_ADDR
)
16228 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
16229 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16230 debug_rtx (addr_op2
);
16232 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16233 emit_insn (gen_rtx_SET (VOIDmode
,
16234 scratch_or_premodify
,
16235 gen_rtx_PLUS (Pmode
,
16238 addr
= scratch_or_premodify
;
16239 scratch_or_premodify
= scratch
;
16242 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
16243 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
16246 if (TARGET_DEBUG_ADDR
)
16248 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16249 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16250 GET_MODE_NAME (mode
));
16254 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16255 addr
= scratch_or_premodify
;
16256 scratch_or_premodify
= scratch
;
16260 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16265 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16268 /* If the original address involved a pre-modify that we couldn't use the VSX
16269 memory instruction with update, and we haven't taken care of already,
16270 store the address in the pre-modify register and use that as the
16272 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
16274 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
16275 addr
= scratch_or_premodify
;
16278 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
16279 memory instruction, recreate the AND now, including the clobber which is
16280 generated by the general ANDSI3/ANDDI3 patterns for the
16281 andi. instruction. */
16282 if (and_op2
!= NULL_RTX
)
16284 if (! legitimate_indirect_address_p (addr
, false))
16286 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
16290 if (TARGET_DEBUG_ADDR
)
16292 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
16293 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16294 debug_rtx (and_op2
);
16297 and_rtx
= gen_rtx_SET (VOIDmode
,
16299 gen_rtx_AND (Pmode
,
16303 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
16304 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
16305 gen_rtvec (2, and_rtx
, cc_clobber
)));
16309 /* Adjust the address if it changed. */
16310 if (addr
!= XEXP (mem
, 0))
16312 mem
= replace_equiv_address_nv (mem
, addr
);
16313 if (TARGET_DEBUG_ADDR
)
16314 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
16317 /* Now create the move. */
16319 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16321 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16326 /* Convert reloads involving 64-bit gprs and misaligned offset
16327 addressing, or multiple 32-bit gprs and offsets that are too large,
16328 to use indirect addressing. */
16331 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16333 int regno
= true_regnum (reg
);
16334 enum reg_class rclass
;
16336 rtx scratch_or_premodify
= scratch
;
16338 if (TARGET_DEBUG_ADDR
)
16340 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
16341 store_p
? "store" : "load");
16342 fprintf (stderr
, "reg:\n");
16344 fprintf (stderr
, "mem:\n");
16346 fprintf (stderr
, "scratch:\n");
16347 debug_rtx (scratch
);
16350 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
16351 gcc_assert (GET_CODE (mem
) == MEM
);
16352 rclass
= REGNO_REG_CLASS (regno
);
16353 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
16354 addr
= XEXP (mem
, 0);
16356 if (GET_CODE (addr
) == PRE_MODIFY
)
16358 scratch_or_premodify
= XEXP (addr
, 0);
16359 gcc_assert (REG_P (scratch_or_premodify
));
16360 addr
= XEXP (addr
, 1);
16362 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
16364 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16366 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
16368 /* Now create the move. */
16370 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16372 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16377 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
16378 this function has any SDmode references. If we are on a power7 or later, we
16379 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
16380 can load/store the value. */
16383 rs6000_alloc_sdmode_stack_slot (void)
16387 gimple_stmt_iterator gsi
;
16389 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
16390 /* We use a different approach for dealing with the secondary
16395 if (TARGET_NO_SDMODE_STACK
)
16399 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
16401 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
16404 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
16405 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
16411 /* Check for any SDmode parameters of the function. */
16412 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
16414 if (TREE_TYPE (t
) == error_mark_node
)
16417 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
16418 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
16420 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
16421 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
16429 rs6000_instantiate_decls (void)
16431 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
16432 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
16435 /* Given an rtx X being reloaded into a reg required to be
16436 in class CLASS, return the class of reg to actually use.
16437 In general this is just CLASS; but on some machines
16438 in some cases it is preferable to use a more restrictive class.
16440 On the RS/6000, we have to return NO_REGS when we want to reload a
16441 floating-point CONST_DOUBLE to force it to be copied to memory.
16443 We also don't want to reload integer values into floating-point
16444 registers if we can at all help it. In fact, this can
16445 cause reload to die, if it tries to generate a reload of CTR
16446 into a FP register and discovers it doesn't have the memory location
16449 ??? Would it be a good idea to have reload do the converse, that is
16450 try to reload floating modes into FP registers if possible?
16453 static enum reg_class
16454 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
16456 enum machine_mode mode
= GET_MODE (x
);
16458 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
16461 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
16462 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
16463 && easy_vector_constant (x
, mode
))
16464 return ALTIVEC_REGS
;
16466 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
16469 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
16470 return GENERAL_REGS
;
16472 /* For VSX, prefer the traditional registers for 64-bit values because we can
16473 use the non-VSX loads. Prefer the Altivec registers if Altivec is
16474 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
16475 prefer Altivec loads.. */
16476 if (rclass
== VSX_REGS
)
16478 if (GET_MODE_SIZE (mode
) <= 8)
16481 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
16482 return ALTIVEC_REGS
;
16490 /* Debug version of rs6000_preferred_reload_class. */
16491 static enum reg_class
16492 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
16494 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
16497 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
16499 reg_class_names
[ret
], reg_class_names
[rclass
],
16500 GET_MODE_NAME (GET_MODE (x
)));
16506 /* If we are copying between FP or AltiVec registers and anything else, we need
16507 a memory location. The exception is when we are targeting ppc64 and the
16508 move to/from fpr to gpr instructions are available. Also, under VSX, you
16509 can copy vector registers from the FP register set to the Altivec register
16510 set and vice versa. */
16513 rs6000_secondary_memory_needed (enum reg_class from_class
,
16514 enum reg_class to_class
,
16515 enum machine_mode mode
)
16517 enum rs6000_reg_type from_type
, to_type
;
16518 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
16519 || (to_class
== ALTIVEC_REGS
));
16521 /* If a simple/direct move is available, we don't need secondary memory */
16522 from_type
= reg_class_to_reg_type
[(int)from_class
];
16523 to_type
= reg_class_to_reg_type
[(int)to_class
];
16525 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
16526 (secondary_reload_info
*)0, altivec_p
))
16529 /* If we have a floating point or vector register class, we need to use
16530 memory to transfer the data. */
16531 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
16537 /* Debug version of rs6000_secondary_memory_needed. */
16539 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
16540 enum reg_class to_class
,
16541 enum machine_mode mode
)
16543 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
16546 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
16547 "to_class = %s, mode = %s\n",
16548 ret
? "true" : "false",
16549 reg_class_names
[from_class
],
16550 reg_class_names
[to_class
],
16551 GET_MODE_NAME (mode
));
16556 /* Return the register class of a scratch register needed to copy IN into
16557 or out of a register in RCLASS in MODE. If it can be done directly,
16558 NO_REGS is returned. */
16560 static enum reg_class
16561 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
16566 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
16568 && MACHOPIC_INDIRECT
16572 /* We cannot copy a symbolic operand directly into anything
16573 other than BASE_REGS for TARGET_ELF. So indicate that a
16574 register from BASE_REGS is needed as an intermediate
16577 On Darwin, pic addresses require a load from memory, which
16578 needs a base register. */
16579 if (rclass
!= BASE_REGS
16580 && (GET_CODE (in
) == SYMBOL_REF
16581 || GET_CODE (in
) == HIGH
16582 || GET_CODE (in
) == LABEL_REF
16583 || GET_CODE (in
) == CONST
))
16587 if (GET_CODE (in
) == REG
)
16589 regno
= REGNO (in
);
16590 if (regno
>= FIRST_PSEUDO_REGISTER
)
16592 regno
= true_regnum (in
);
16593 if (regno
>= FIRST_PSEUDO_REGISTER
)
16597 else if (GET_CODE (in
) == SUBREG
)
16599 regno
= true_regnum (in
);
16600 if (regno
>= FIRST_PSEUDO_REGISTER
)
16606 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
16608 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
16609 || (regno
>= 0 && INT_REGNO_P (regno
)))
16612 /* Constants, memory, and FP registers can go into FP registers. */
16613 if ((regno
== -1 || FP_REGNO_P (regno
))
16614 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
16615 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
16617 /* Memory, and FP/altivec registers can go into fp/altivec registers under
16618 VSX. However, for scalar variables, use the traditional floating point
16619 registers so that we can use offset+register addressing. */
16621 && (regno
== -1 || VSX_REGNO_P (regno
))
16622 && VSX_REG_CLASS_P (rclass
))
16624 if (GET_MODE_SIZE (mode
) < 16)
16630 /* Memory, and AltiVec registers can go into AltiVec registers. */
16631 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
16632 && rclass
== ALTIVEC_REGS
)
16635 /* We can copy among the CR registers. */
16636 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
16637 && regno
>= 0 && CR_REGNO_P (regno
))
16640 /* Otherwise, we need GENERAL_REGS. */
16641 return GENERAL_REGS
;
16644 /* Debug version of rs6000_secondary_reload_class. */
16645 static enum reg_class
16646 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
16647 enum machine_mode mode
, rtx in
)
16649 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
16651 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
16652 "mode = %s, input rtx:\n",
16653 reg_class_names
[ret
], reg_class_names
[rclass
],
16654 GET_MODE_NAME (mode
));
16660 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
16663 rs6000_cannot_change_mode_class (enum machine_mode from
,
16664 enum machine_mode to
,
16665 enum reg_class rclass
)
16667 unsigned from_size
= GET_MODE_SIZE (from
);
16668 unsigned to_size
= GET_MODE_SIZE (to
);
16670 if (from_size
!= to_size
)
16672 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
16674 if (reg_classes_intersect_p (xclass
, rclass
))
16676 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
16677 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
16679 /* Don't allow 64-bit types to overlap with 128-bit types that take a
16680 single register under VSX because the scalar part of the register
16681 is in the upper 64-bits, and not the lower 64-bits. Types like
16682 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
16683 IEEE floating point can't overlap, and neither can small
16686 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
16689 /* TDmode in floating-mode registers must always go into a register
16690 pair with the most significant word in the even-numbered register
16691 to match ISA requirements. In little-endian mode, this does not
16692 match subreg numbering, so we cannot allow subregs. */
16693 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
16696 if (from_size
< 8 || to_size
< 8)
16699 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
16702 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
16711 if (TARGET_E500_DOUBLE
16712 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
16713 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
16714 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
16715 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
16716 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
16719 /* Since the VSX register set includes traditional floating point registers
16720 and altivec registers, just check for the size being different instead of
16721 trying to check whether the modes are vector modes. Otherwise it won't
16722 allow say DF and DI to change classes. For types like TFmode and TDmode
16723 that take 2 64-bit registers, rather than a single 128-bit register, don't
16724 allow subregs of those types to other 128 bit types. */
16725 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
16727 unsigned num_regs
= (from_size
+ 15) / 16;
16728 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
16729 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
16732 return (from_size
!= 8 && from_size
!= 16);
16735 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
16736 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
16739 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
16740 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
16746 /* Debug version of rs6000_cannot_change_mode_class. */
16748 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
16749 enum machine_mode to
,
16750 enum reg_class rclass
)
16752 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
16755 "rs6000_cannot_change_mode_class, return %s, from = %s, "
16756 "to = %s, rclass = %s\n",
16757 ret
? "true" : "false",
16758 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
16759 reg_class_names
[rclass
]);
16764 /* Return a string to do a move operation of 128 bits of data. */
16767 rs6000_output_move_128bit (rtx operands
[])
16769 rtx dest
= operands
[0];
16770 rtx src
= operands
[1];
16771 enum machine_mode mode
= GET_MODE (dest
);
16774 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
16775 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
16779 dest_regno
= REGNO (dest
);
16780 dest_gpr_p
= INT_REGNO_P (dest_regno
);
16781 dest_fp_p
= FP_REGNO_P (dest_regno
);
16782 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
16783 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
16788 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
16793 src_regno
= REGNO (src
);
16794 src_gpr_p
= INT_REGNO_P (src_regno
);
16795 src_fp_p
= FP_REGNO_P (src_regno
);
16796 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
16797 src_vsx_p
= src_fp_p
| src_vmx_p
;
16802 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
16805 /* Register moves. */
16806 if (dest_regno
>= 0 && src_regno
>= 0)
16813 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
16817 else if (TARGET_VSX
&& dest_vsx_p
)
16820 return "xxlor %x0,%x1,%x1";
16822 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
16826 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
16827 return "vor %0,%1,%1";
16829 else if (dest_fp_p
&& src_fp_p
)
16834 else if (dest_regno
>= 0 && MEM_P (src
))
16838 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
16844 else if (TARGET_ALTIVEC
&& dest_vmx_p
16845 && altivec_indexed_or_indirect_operand (src
, mode
))
16846 return "lvx %0,%y1";
16848 else if (TARGET_VSX
&& dest_vsx_p
)
16850 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
16851 return "lxvw4x %x0,%y1";
16853 return "lxvd2x %x0,%y1";
16856 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
16857 return "lvx %0,%y1";
16859 else if (dest_fp_p
)
16864 else if (src_regno
>= 0 && MEM_P (dest
))
16868 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
16869 return "stq %1,%0";
16874 else if (TARGET_ALTIVEC
&& src_vmx_p
16875 && altivec_indexed_or_indirect_operand (src
, mode
))
16876 return "stvx %1,%y0";
16878 else if (TARGET_VSX
&& src_vsx_p
)
16880 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
16881 return "stxvw4x %x1,%y0";
16883 return "stxvd2x %x1,%y0";
16886 else if (TARGET_ALTIVEC
&& src_vmx_p
)
16887 return "stvx %1,%y0";
16894 else if (dest_regno
>= 0
16895 && (GET_CODE (src
) == CONST_INT
16896 || GET_CODE (src
) == CONST_DOUBLE
16897 || GET_CODE (src
) == CONST_VECTOR
))
16902 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
16903 return "xxlxor %x0,%x0,%x0";
16905 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
16906 return output_vec_const_move (operands
);
16909 if (TARGET_DEBUG_ADDR
)
16911 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
16912 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
16915 gcc_unreachable ();
16919 /* Given a comparison operation, return the bit number in CCR to test. We
16920 know this is a valid comparison.
16922 SCC_P is 1 if this is for an scc. That means that %D will have been
16923 used instead of %C, so the bits will be in different places.
16925 Return -1 if OP isn't a valid comparison for some reason. */
16928 ccr_bit (rtx op
, int scc_p
)
16930 enum rtx_code code
= GET_CODE (op
);
16931 enum machine_mode cc_mode
;
16936 if (!COMPARISON_P (op
))
16939 reg
= XEXP (op
, 0);
16941 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
16943 cc_mode
= GET_MODE (reg
);
16944 cc_regnum
= REGNO (reg
);
16945 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
16947 validate_condition_mode (code
, cc_mode
);
16949 /* When generating a sCOND operation, only positive conditions are
16952 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
16953 || code
== GTU
|| code
== LTU
);
16958 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
16960 return base_bit
+ 2;
16961 case GT
: case GTU
: case UNLE
:
16962 return base_bit
+ 1;
16963 case LT
: case LTU
: case UNGE
:
16965 case ORDERED
: case UNORDERED
:
16966 return base_bit
+ 3;
16969 /* If scc, we will have done a cror to put the bit in the
16970 unordered position. So test that bit. For integer, this is ! LT
16971 unless this is an scc insn. */
16972 return scc_p
? base_bit
+ 3 : base_bit
;
16975 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
16978 gcc_unreachable ();
16982 /* Return the GOT register. */
16985 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
16987 /* The second flow pass currently (June 1999) can't update
16988 regs_ever_live without disturbing other parts of the compiler, so
16989 update it here to make the prolog/epilogue code happy. */
16990 if (!can_create_pseudo_p ()
16991 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
16992 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
16994 crtl
->uses_pic_offset_table
= 1;
16996 return pic_offset_table_rtx
;
16999 static rs6000_stack_t stack_info
;
17001 /* Function to init struct machine_function.
17002 This will be called, via a pointer variable,
17003 from push_function_context. */
17005 static struct machine_function
*
17006 rs6000_init_machine_status (void)
17008 stack_info
.reload_completed
= 0;
17009 return ggc_alloc_cleared_machine_function ();
17012 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
17015 extract_MB (rtx op
)
17018 unsigned long val
= INTVAL (op
);
17020 /* If the high bit is zero, the value is the first 1 bit we find
17022 if ((val
& 0x80000000) == 0)
17024 gcc_assert (val
& 0xffffffff);
17027 while (((val
<<= 1) & 0x80000000) == 0)
17032 /* If the high bit is set and the low bit is not, or the mask is all
17033 1's, the value is zero. */
17034 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
17037 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17040 while (((val
>>= 1) & 1) != 0)
17047 extract_ME (rtx op
)
17050 unsigned long val
= INTVAL (op
);
17052 /* If the low bit is zero, the value is the first 1 bit we find from
17054 if ((val
& 1) == 0)
17056 gcc_assert (val
& 0xffffffff);
17059 while (((val
>>= 1) & 1) == 0)
17065 /* If the low bit is set and the high bit is not, or the mask is all
17066 1's, the value is 31. */
17067 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
17070 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17073 while (((val
<<= 1) & 0x80000000) != 0)
17079 /* Locate some local-dynamic symbol still in use by this function
17080 so that we can print its name in some tls_ld pattern. */
17082 static const char *
17083 rs6000_get_some_local_dynamic_name (void)
17087 if (cfun
->machine
->some_ld_name
)
17088 return cfun
->machine
->some_ld_name
;
17090 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17092 && for_each_rtx (&PATTERN (insn
),
17093 rs6000_get_some_local_dynamic_name_1
, 0))
17094 return cfun
->machine
->some_ld_name
;
17096 gcc_unreachable ();
17099 /* Helper function for rs6000_get_some_local_dynamic_name. */
17102 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
17106 if (GET_CODE (x
) == SYMBOL_REF
)
17108 const char *str
= XSTR (x
, 0);
17109 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
17111 cfun
->machine
->some_ld_name
= str
;
17119 /* Write out a function code label. */
17122 rs6000_output_function_entry (FILE *file
, const char *fname
)
17124 if (fname
[0] != '.')
17126 switch (DEFAULT_ABI
)
17129 gcc_unreachable ();
17135 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
17145 RS6000_OUTPUT_BASENAME (file
, fname
);
17148 /* Print an operand. Recognize special options, documented below. */
17151 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
17152 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
17154 #define SMALL_DATA_RELOC "sda21"
17155 #define SMALL_DATA_REG 0
17159 print_operand (FILE *file
, rtx x
, int code
)
17162 unsigned HOST_WIDE_INT uval
;
17166 /* %a is output_address. */
17169 /* If constant, low-order 16 bits of constant, unsigned.
17170 Otherwise, write normally. */
17172 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
17174 print_operand (file
, x
, 0);
17178 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
17179 for 64-bit mask direction. */
17180 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
17183 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
17187 /* Like 'J' but get to the GT bit only. */
17188 gcc_assert (REG_P (x
));
17190 /* Bit 1 is GT bit. */
17191 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
17193 /* Add one for shift count in rlinm for scc. */
17194 fprintf (file
, "%d", i
+ 1);
17198 /* X is a CR register. Print the number of the EQ bit of the CR */
17199 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17200 output_operand_lossage ("invalid %%E value");
17202 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
17206 /* X is a CR register. Print the shift count needed to move it
17207 to the high-order four bits. */
17208 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17209 output_operand_lossage ("invalid %%f value");
17211 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
17215 /* Similar, but print the count for the rotate in the opposite
17217 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17218 output_operand_lossage ("invalid %%F value");
17220 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
17224 /* X is a constant integer. If it is negative, print "m",
17225 otherwise print "z". This is to make an aze or ame insn. */
17226 if (GET_CODE (x
) != CONST_INT
)
17227 output_operand_lossage ("invalid %%G value");
17228 else if (INTVAL (x
) >= 0)
17235 /* If constant, output low-order five bits. Otherwise, write
17238 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
17240 print_operand (file
, x
, 0);
17244 /* If constant, output low-order six bits. Otherwise, write
17247 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
17249 print_operand (file
, x
, 0);
17253 /* Print `i' if this is a constant, else nothing. */
17259 /* Write the bit number in CCR for jump. */
17260 i
= ccr_bit (x
, 0);
17262 output_operand_lossage ("invalid %%j code");
17264 fprintf (file
, "%d", i
);
17268 /* Similar, but add one for shift count in rlinm for scc and pass
17269 scc flag to `ccr_bit'. */
17270 i
= ccr_bit (x
, 1);
17272 output_operand_lossage ("invalid %%J code");
17274 /* If we want bit 31, write a shift count of zero, not 32. */
17275 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17279 /* X must be a constant. Write the 1's complement of the
17282 output_operand_lossage ("invalid %%k value");
17284 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
17288 /* X must be a symbolic constant on ELF. Write an
17289 expression suitable for an 'addi' that adds in the low 16
17290 bits of the MEM. */
17291 if (GET_CODE (x
) == CONST
)
17293 if (GET_CODE (XEXP (x
, 0)) != PLUS
17294 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
17295 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
17296 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
17297 output_operand_lossage ("invalid %%K value");
17299 print_operand_address (file
, x
);
17300 fputs ("@l", file
);
17303 /* %l is output_asm_label. */
17306 /* Write second word of DImode or DFmode reference. Works on register
17307 or non-indexed memory only. */
17309 fputs (reg_names
[REGNO (x
) + 1], file
);
17310 else if (MEM_P (x
))
17312 /* Handle possible auto-increment. Since it is pre-increment and
17313 we have already done it, we can just use an offset of word. */
17314 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17315 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17316 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17318 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17319 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17322 output_address (XEXP (adjust_address_nv (x
, SImode
,
17326 if (small_data_operand (x
, GET_MODE (x
)))
17327 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17328 reg_names
[SMALL_DATA_REG
]);
17333 /* MB value for a mask operand. */
17334 if (! mask_operand (x
, SImode
))
17335 output_operand_lossage ("invalid %%m value");
17337 fprintf (file
, "%d", extract_MB (x
));
17341 /* ME value for a mask operand. */
17342 if (! mask_operand (x
, SImode
))
17343 output_operand_lossage ("invalid %%M value");
17345 fprintf (file
, "%d", extract_ME (x
));
17348 /* %n outputs the negative of its operand. */
17351 /* Write the number of elements in the vector times 4. */
17352 if (GET_CODE (x
) != PARALLEL
)
17353 output_operand_lossage ("invalid %%N value");
17355 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
17359 /* Similar, but subtract 1 first. */
17360 if (GET_CODE (x
) != PARALLEL
)
17361 output_operand_lossage ("invalid %%O value");
17363 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
17367 /* X is a CONST_INT that is a power of two. Output the logarithm. */
17370 || (i
= exact_log2 (INTVAL (x
))) < 0)
17371 output_operand_lossage ("invalid %%p value");
17373 fprintf (file
, "%d", i
);
17377 /* The operand must be an indirect memory reference. The result
17378 is the register name. */
17379 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
17380 || REGNO (XEXP (x
, 0)) >= 32)
17381 output_operand_lossage ("invalid %%P value");
17383 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
17387 /* This outputs the logical code corresponding to a boolean
17388 expression. The expression may have one or both operands
17389 negated (if one, only the first one). For condition register
17390 logical operations, it will also treat the negated
17391 CR codes as NOTs, but not handle NOTs of them. */
17393 const char *const *t
= 0;
17395 enum rtx_code code
= GET_CODE (x
);
17396 static const char * const tbl
[3][3] = {
17397 { "and", "andc", "nor" },
17398 { "or", "orc", "nand" },
17399 { "xor", "eqv", "xor" } };
17403 else if (code
== IOR
)
17405 else if (code
== XOR
)
17408 output_operand_lossage ("invalid %%q value");
17410 if (GET_CODE (XEXP (x
, 0)) != NOT
)
17414 if (GET_CODE (XEXP (x
, 1)) == NOT
)
17425 if (! TARGET_MFCRF
)
17431 /* X is a CR register. Print the mask for `mtcrf'. */
17432 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17433 output_operand_lossage ("invalid %%R value");
17435 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
17439 /* Low 5 bits of 32 - value */
17441 output_operand_lossage ("invalid %%s value");
17443 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
17447 /* PowerPC64 mask position. All 0's is excluded.
17448 CONST_INT 32-bit mask is considered sign-extended so any
17449 transition must occur within the CONST_INT, not on the boundary. */
17450 if (! mask64_operand (x
, DImode
))
17451 output_operand_lossage ("invalid %%S value");
17455 if (uval
& 1) /* Clear Left */
17457 #if HOST_BITS_PER_WIDE_INT > 64
17458 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
17462 else /* Clear Right */
17465 #if HOST_BITS_PER_WIDE_INT > 64
17466 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
17472 gcc_assert (i
>= 0);
17473 fprintf (file
, "%d", i
);
17477 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
17478 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
17480 /* Bit 3 is OV bit. */
17481 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
17483 /* If we want bit 31, write a shift count of zero, not 32. */
17484 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17488 /* Print the symbolic name of a branch target register. */
17489 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
17490 && REGNO (x
) != CTR_REGNO
))
17491 output_operand_lossage ("invalid %%T value");
17492 else if (REGNO (x
) == LR_REGNO
)
17493 fputs ("lr", file
);
17495 fputs ("ctr", file
);
17499 /* High-order 16 bits of constant for use in unsigned operand. */
17501 output_operand_lossage ("invalid %%u value");
17503 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17504 (INTVAL (x
) >> 16) & 0xffff);
17508 /* High-order 16 bits of constant for use in signed operand. */
17510 output_operand_lossage ("invalid %%v value");
17512 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17513 (INTVAL (x
) >> 16) & 0xffff);
17517 /* Print `u' if this has an auto-increment or auto-decrement. */
17519 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
17520 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
17521 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
17526 /* Print the trap code for this operand. */
17527 switch (GET_CODE (x
))
17530 fputs ("eq", file
); /* 4 */
17533 fputs ("ne", file
); /* 24 */
17536 fputs ("lt", file
); /* 16 */
17539 fputs ("le", file
); /* 20 */
17542 fputs ("gt", file
); /* 8 */
17545 fputs ("ge", file
); /* 12 */
17548 fputs ("llt", file
); /* 2 */
17551 fputs ("lle", file
); /* 6 */
17554 fputs ("lgt", file
); /* 1 */
17557 fputs ("lge", file
); /* 5 */
17560 gcc_unreachable ();
17565 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
17568 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
17569 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
17571 print_operand (file
, x
, 0);
17575 /* MB value for a PowerPC64 rldic operand. */
17576 i
= clz_hwi (INTVAL (x
));
17578 fprintf (file
, "%d", i
);
17582 /* X is a FPR or Altivec register used in a VSX context. */
17583 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
17584 output_operand_lossage ("invalid %%x value");
17587 int reg
= REGNO (x
);
17588 int vsx_reg
= (FP_REGNO_P (reg
)
17590 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
17592 #ifdef TARGET_REGNAMES
17593 if (TARGET_REGNAMES
)
17594 fprintf (file
, "%%vs%d", vsx_reg
);
17597 fprintf (file
, "%d", vsx_reg
);
17603 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
17604 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
17605 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
17610 /* Like 'L', for third word of TImode/PTImode */
17612 fputs (reg_names
[REGNO (x
) + 2], file
);
17613 else if (MEM_P (x
))
17615 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17616 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17617 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
17618 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17619 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
17621 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
17622 if (small_data_operand (x
, GET_MODE (x
)))
17623 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17624 reg_names
[SMALL_DATA_REG
]);
17629 /* X is a SYMBOL_REF. Write out the name preceded by a
17630 period and without any trailing data in brackets. Used for function
17631 names. If we are configured for System V (or the embedded ABI) on
17632 the PowerPC, do not emit the period, since those systems do not use
17633 TOCs and the like. */
17634 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
17636 /* For macho, check to see if we need a stub. */
17639 const char *name
= XSTR (x
, 0);
17641 if (darwin_emit_branch_islands
17642 && MACHOPIC_INDIRECT
17643 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
17644 name
= machopic_indirection_name (x
, /*stub_p=*/true);
17646 assemble_name (file
, name
);
17648 else if (!DOT_SYMBOLS
)
17649 assemble_name (file
, XSTR (x
, 0));
17651 rs6000_output_function_entry (file
, XSTR (x
, 0));
17655 /* Like 'L', for last word of TImode/PTImode. */
17657 fputs (reg_names
[REGNO (x
) + 3], file
);
17658 else if (MEM_P (x
))
17660 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17661 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17662 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
17663 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17664 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
17666 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
17667 if (small_data_operand (x
, GET_MODE (x
)))
17668 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17669 reg_names
[SMALL_DATA_REG
]);
17673 /* Print AltiVec or SPE memory operand. */
17678 gcc_assert (MEM_P (x
));
17682 /* Ugly hack because %y is overloaded. */
17683 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
17684 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
17685 || GET_MODE (x
) == TFmode
17686 || GET_MODE (x
) == TImode
17687 || GET_MODE (x
) == PTImode
))
17689 /* Handle [reg]. */
17692 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
17695 /* Handle [reg+UIMM]. */
17696 else if (GET_CODE (tmp
) == PLUS
&&
17697 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
17701 gcc_assert (REG_P (XEXP (tmp
, 0)));
17703 x
= INTVAL (XEXP (tmp
, 1));
17704 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
17708 /* Fall through. Must be [reg+reg]. */
17710 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
17711 && GET_CODE (tmp
) == AND
17712 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
17713 && INTVAL (XEXP (tmp
, 1)) == -16)
17714 tmp
= XEXP (tmp
, 0);
17715 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
17716 && GET_CODE (tmp
) == PRE_MODIFY
)
17717 tmp
= XEXP (tmp
, 1);
17719 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
17722 if (!GET_CODE (tmp
) == PLUS
17723 || !REG_P (XEXP (tmp
, 0))
17724 || !REG_P (XEXP (tmp
, 1)))
17726 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
17730 if (REGNO (XEXP (tmp
, 0)) == 0)
17731 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
17732 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
17734 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
17735 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
17742 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
17743 else if (MEM_P (x
))
17745 /* We need to handle PRE_INC and PRE_DEC here, since we need to
17746 know the width from the mode. */
17747 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
17748 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
17749 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
17750 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17751 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
17752 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
17753 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17754 output_address (XEXP (XEXP (x
, 0), 1));
17756 output_address (XEXP (x
, 0));
17760 if (toc_relative_expr_p (x
, false))
17761 /* This hack along with a corresponding hack in
17762 rs6000_output_addr_const_extra arranges to output addends
17763 where the assembler expects to find them. eg.
17764 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
17765 without this hack would be output as "x@toc+4". We
17767 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
17769 output_addr_const (file
, x
);
17774 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
17778 output_operand_lossage ("invalid %%xn code");
17782 /* Print the address of an operand. */
17785 print_operand_address (FILE *file
, rtx x
)
17788 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
17789 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
17790 || GET_CODE (x
) == LABEL_REF
)
17792 output_addr_const (file
, x
);
17793 if (small_data_operand (x
, GET_MODE (x
)))
17794 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17795 reg_names
[SMALL_DATA_REG
]);
17797 gcc_assert (!TARGET_TOC
);
17799 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
17800 && REG_P (XEXP (x
, 1)))
17802 if (REGNO (XEXP (x
, 0)) == 0)
17803 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
17804 reg_names
[ REGNO (XEXP (x
, 0)) ]);
17806 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
17807 reg_names
[ REGNO (XEXP (x
, 1)) ]);
17809 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
17810 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
17811 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
17812 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
17814 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
17815 && CONSTANT_P (XEXP (x
, 1)))
17817 fprintf (file
, "lo16(");
17818 output_addr_const (file
, XEXP (x
, 1));
17819 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
17823 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
17824 && CONSTANT_P (XEXP (x
, 1)))
17826 output_addr_const (file
, XEXP (x
, 1));
17827 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
17830 else if (toc_relative_expr_p (x
, false))
17832 /* This hack along with a corresponding hack in
17833 rs6000_output_addr_const_extra arranges to output addends
17834 where the assembler expects to find them. eg.
17836 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
17837 without this hack would be output as "x@toc+8@l(9)". We
17838 want "x+8@toc@l(9)". */
17839 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
17840 if (GET_CODE (x
) == LO_SUM
)
17841 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
17843 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
17846 gcc_unreachable ();
17849 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
17852 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
17854 if (GET_CODE (x
) == UNSPEC
)
17855 switch (XINT (x
, 1))
17857 case UNSPEC_TOCREL
:
17858 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
17859 && REG_P (XVECEXP (x
, 0, 1))
17860 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
17861 output_addr_const (file
, XVECEXP (x
, 0, 0));
17862 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
17864 if (INTVAL (tocrel_offset
) >= 0)
17865 fprintf (file
, "+");
17866 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
17868 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
17871 assemble_name (file
, toc_label_name
);
17873 else if (TARGET_ELF
)
17874 fputs ("@toc", file
);
17878 case UNSPEC_MACHOPIC_OFFSET
:
17879 output_addr_const (file
, XVECEXP (x
, 0, 0));
17881 machopic_output_function_base_name (file
);
17888 /* Target hook for assembling integer objects. The PowerPC version has
17889 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
17890 is defined. It also needs to handle DI-mode objects on 64-bit
17894 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
17896 #ifdef RELOCATABLE_NEEDS_FIXUP
17897 /* Special handling for SI values. */
17898 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
17900 static int recurse
= 0;
17902 /* For -mrelocatable, we mark all addresses that need to be fixed up in
17903 the .fixup section. Since the TOC section is already relocated, we
17904 don't need to mark it here. We used to skip the text section, but it
17905 should never be valid for relocated addresses to be placed in the text
17907 if (TARGET_RELOCATABLE
17908 && in_section
!= toc_section
17910 && GET_CODE (x
) != CONST_INT
17911 && GET_CODE (x
) != CONST_DOUBLE
17917 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
17919 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
17920 fprintf (asm_out_file
, "\t.long\t(");
17921 output_addr_const (asm_out_file
, x
);
17922 fprintf (asm_out_file
, ")@fixup\n");
17923 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
17924 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
17925 fprintf (asm_out_file
, "\t.long\t");
17926 assemble_name (asm_out_file
, buf
);
17927 fprintf (asm_out_file
, "\n\t.previous\n");
17931 /* Remove initial .'s to turn a -mcall-aixdesc function
17932 address into the address of the descriptor, not the function
17934 else if (GET_CODE (x
) == SYMBOL_REF
17935 && XSTR (x
, 0)[0] == '.'
17936 && DEFAULT_ABI
== ABI_AIX
)
17938 const char *name
= XSTR (x
, 0);
17939 while (*name
== '.')
17942 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
17946 #endif /* RELOCATABLE_NEEDS_FIXUP */
17947 return default_assemble_integer (x
, size
, aligned_p
);
17950 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
17951 /* Emit an assembler directive to set symbol visibility for DECL to
17952 VISIBILITY_TYPE. */
17955 rs6000_assemble_visibility (tree decl
, int vis
)
17960 /* Functions need to have their entry point symbol visibility set as
17961 well as their descriptor symbol visibility. */
17962 if (DEFAULT_ABI
== ABI_AIX
17964 && TREE_CODE (decl
) == FUNCTION_DECL
)
17966 static const char * const visibility_types
[] = {
17967 NULL
, "internal", "hidden", "protected"
17970 const char *name
, *type
;
17972 name
= ((* targetm
.strip_name_encoding
)
17973 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
17974 type
= visibility_types
[vis
];
17976 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
17977 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
17980 default_assemble_visibility (decl
, vis
);
17985 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
17987 /* Reversal of FP compares takes care -- an ordered compare
17988 becomes an unordered compare and vice versa. */
17989 if (mode
== CCFPmode
17990 && (!flag_finite_math_only
17991 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
17992 || code
== UNEQ
|| code
== LTGT
))
17993 return reverse_condition_maybe_unordered (code
);
17995 return reverse_condition (code
);
17998 /* Generate a compare for CODE. Return a brand-new rtx that
17999 represents the result of the compare. */
18002 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
18004 enum machine_mode comp_mode
;
18005 rtx compare_result
;
18006 enum rtx_code code
= GET_CODE (cmp
);
18007 rtx op0
= XEXP (cmp
, 0);
18008 rtx op1
= XEXP (cmp
, 1);
18010 if (FLOAT_MODE_P (mode
))
18011 comp_mode
= CCFPmode
;
18012 else if (code
== GTU
|| code
== LTU
18013 || code
== GEU
|| code
== LEU
)
18014 comp_mode
= CCUNSmode
;
18015 else if ((code
== EQ
|| code
== NE
)
18016 && unsigned_reg_p (op0
)
18017 && (unsigned_reg_p (op1
)
18018 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
18019 /* These are unsigned values, perhaps there will be a later
18020 ordering compare that can be shared with this one. */
18021 comp_mode
= CCUNSmode
;
18023 comp_mode
= CCmode
;
18025 /* If we have an unsigned compare, make sure we don't have a signed value as
18027 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
18028 && INTVAL (op1
) < 0)
18030 op0
= copy_rtx_if_shared (op0
);
18031 op1
= force_reg (GET_MODE (op0
), op1
);
18032 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
18035 /* First, the compare. */
18036 compare_result
= gen_reg_rtx (comp_mode
);
18038 /* E500 FP compare instructions on the GPRs. Yuck! */
18039 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18040 && FLOAT_MODE_P (mode
))
18042 rtx cmp
, or_result
, compare_result2
;
18043 enum machine_mode op_mode
= GET_MODE (op0
);
18046 if (op_mode
== VOIDmode
)
18047 op_mode
= GET_MODE (op1
);
18049 /* First reverse the condition codes that aren't directly supported. */
18057 code
= reverse_condition_maybe_unordered (code
);
18070 gcc_unreachable ();
18073 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
18074 This explains the following mess. */
18082 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18083 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
18084 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
18088 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18089 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
18090 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
18094 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18095 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
18096 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
18100 gcc_unreachable ();
18109 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18110 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
18111 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
18115 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18116 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
18117 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
18121 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18122 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
18123 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
18127 gcc_unreachable ();
18136 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18137 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
18138 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
18142 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18143 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
18144 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
18148 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18149 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
18150 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
18154 gcc_unreachable ();
18159 gcc_unreachable ();
18162 /* Synthesize LE and GE from LT/GT || EQ. */
18163 if (code
== LE
|| code
== GE
)
18167 compare_result2
= gen_reg_rtx (CCFPmode
);
18173 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18174 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
18175 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
18179 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18180 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
18181 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
18185 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18186 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
18187 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
18191 gcc_unreachable ();
18196 /* OR them together. */
18197 or_result
= gen_reg_rtx (CCFPmode
);
18198 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
18200 compare_result
= or_result
;
18203 code
= reverse_p
? NE
: EQ
;
18209 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
18210 CLOBBERs to match cmptf_internal2 pattern. */
18211 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
18212 && GET_MODE (op0
) == TFmode
18213 && !TARGET_IEEEQUAD
18214 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
18215 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
18217 gen_rtx_SET (VOIDmode
,
18219 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
18220 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18221 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18222 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18223 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18224 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18225 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18226 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18227 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18228 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
18229 else if (GET_CODE (op1
) == UNSPEC
18230 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
18232 rtx op1b
= XVECEXP (op1
, 0, 0);
18233 comp_mode
= CCEQmode
;
18234 compare_result
= gen_reg_rtx (CCEQmode
);
18236 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
18238 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
18241 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
18242 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
18245 /* Some kinds of FP comparisons need an OR operation;
18246 under flag_finite_math_only we don't bother. */
18247 if (FLOAT_MODE_P (mode
)
18248 && !flag_finite_math_only
18249 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
18250 && (code
== LE
|| code
== GE
18251 || code
== UNEQ
|| code
== LTGT
18252 || code
== UNGT
|| code
== UNLT
))
18254 enum rtx_code or1
, or2
;
18255 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
18256 rtx or_result
= gen_reg_rtx (CCEQmode
);
18260 case LE
: or1
= LT
; or2
= EQ
; break;
18261 case GE
: or1
= GT
; or2
= EQ
; break;
18262 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
18263 case LTGT
: or1
= LT
; or2
= GT
; break;
18264 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
18265 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
18266 default: gcc_unreachable ();
18268 validate_condition_mode (or1
, comp_mode
);
18269 validate_condition_mode (or2
, comp_mode
);
18270 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
18271 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
18272 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
18273 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
18275 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
18277 compare_result
= or_result
;
18281 validate_condition_mode (code
, GET_MODE (compare_result
));
18283 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
18287 /* Emit the RTL for an sISEL pattern. */
18290 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
18292 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
18296 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
18299 enum machine_mode op_mode
;
18300 enum rtx_code cond_code
;
18301 rtx result
= operands
[0];
18303 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
18305 rs6000_emit_sISEL (mode
, operands
);
18309 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
18310 cond_code
= GET_CODE (condition_rtx
);
18312 if (FLOAT_MODE_P (mode
)
18313 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18317 PUT_MODE (condition_rtx
, SImode
);
18318 t
= XEXP (condition_rtx
, 0);
18320 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
18322 if (cond_code
== NE
)
18323 emit_insn (gen_e500_flip_gt_bit (t
, t
));
18325 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
18329 if (cond_code
== NE
18330 || cond_code
== GE
|| cond_code
== LE
18331 || cond_code
== GEU
|| cond_code
== LEU
18332 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
18334 rtx not_result
= gen_reg_rtx (CCEQmode
);
18335 rtx not_op
, rev_cond_rtx
;
18336 enum machine_mode cc_mode
;
18338 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
18340 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
18341 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
18342 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
18343 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
18344 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
18347 op_mode
= GET_MODE (XEXP (operands
[1], 0));
18348 if (op_mode
== VOIDmode
)
18349 op_mode
= GET_MODE (XEXP (operands
[1], 1));
18351 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
18353 PUT_MODE (condition_rtx
, DImode
);
18354 convert_move (result
, condition_rtx
, 0);
18358 PUT_MODE (condition_rtx
, SImode
);
18359 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
18363 /* Emit a branch of kind CODE to location LOC. */
18366 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
18368 rtx condition_rtx
, loc_ref
;
18370 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
18371 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
18372 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
18373 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
18374 loc_ref
, pc_rtx
)));
18377 /* Return the string to output a conditional branch to LABEL, which is
18378 the operand template of the label, or NULL if the branch is really a
18379 conditional return.
18381 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
18382 condition code register and its mode specifies what kind of
18383 comparison we made.
18385 REVERSED is nonzero if we should reverse the sense of the comparison.
18387 INSN is the insn. */
18390 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
18392 static char string
[64];
18393 enum rtx_code code
= GET_CODE (op
);
18394 rtx cc_reg
= XEXP (op
, 0);
18395 enum machine_mode mode
= GET_MODE (cc_reg
);
18396 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
18397 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
18398 int really_reversed
= reversed
^ need_longbranch
;
18404 validate_condition_mode (code
, mode
);
18406 /* Work out which way this really branches. We could use
18407 reverse_condition_maybe_unordered here always but this
18408 makes the resulting assembler clearer. */
18409 if (really_reversed
)
18411 /* Reversal of FP compares takes care -- an ordered compare
18412 becomes an unordered compare and vice versa. */
18413 if (mode
== CCFPmode
)
18414 code
= reverse_condition_maybe_unordered (code
);
18416 code
= reverse_condition (code
);
18419 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
18421 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
18426 /* Opposite of GT. */
18435 gcc_unreachable ();
18441 /* Not all of these are actually distinct opcodes, but
18442 we distinguish them for clarity of the resulting assembler. */
18443 case NE
: case LTGT
:
18444 ccode
= "ne"; break;
18445 case EQ
: case UNEQ
:
18446 ccode
= "eq"; break;
18448 ccode
= "ge"; break;
18449 case GT
: case GTU
: case UNGT
:
18450 ccode
= "gt"; break;
18452 ccode
= "le"; break;
18453 case LT
: case LTU
: case UNLT
:
18454 ccode
= "lt"; break;
18455 case UNORDERED
: ccode
= "un"; break;
18456 case ORDERED
: ccode
= "nu"; break;
18457 case UNGE
: ccode
= "nl"; break;
18458 case UNLE
: ccode
= "ng"; break;
18460 gcc_unreachable ();
18463 /* Maybe we have a guess as to how likely the branch is. */
18465 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
18466 if (note
!= NULL_RTX
)
18468 /* PROB is the difference from 50%. */
18469 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
18471 /* Only hint for highly probable/improbable branches on newer
18472 cpus as static prediction overrides processor dynamic
18473 prediction. For older cpus we may as well always hint, but
18474 assume not taken for branches that are very close to 50% as a
18475 mispredicted taken branch is more expensive than a
18476 mispredicted not-taken branch. */
18477 if (rs6000_always_hint
18478 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
18479 && br_prob_note_reliable_p (note
)))
18481 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
18482 && ((prob
> 0) ^ need_longbranch
))
18490 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
18492 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
18494 /* We need to escape any '%' characters in the reg_names string.
18495 Assume they'd only be the first character.... */
18496 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
18498 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
18502 /* If the branch distance was too far, we may have to use an
18503 unconditional branch to go the distance. */
18504 if (need_longbranch
)
18505 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
18507 s
+= sprintf (s
, ",%s", label
);
18513 /* Return the string to flip the GT bit on a CR. */
18515 output_e500_flip_gt_bit (rtx dst
, rtx src
)
18517 static char string
[64];
18520 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
18521 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
18524 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
18525 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
18527 sprintf (string
, "crnot %d,%d", a
, b
);
18531 /* Return insn for VSX or Altivec comparisons. */
18534 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
18537 enum machine_mode mode
= GET_MODE (op0
);
18545 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
18555 mask
= gen_reg_rtx (mode
);
18556 emit_insn (gen_rtx_SET (VOIDmode
,
18558 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
18565 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
18566 DMODE is expected destination mode. This is a recursive function. */
18569 rs6000_emit_vector_compare (enum rtx_code rcode
,
18571 enum machine_mode dmode
)
18574 bool swap_operands
= false;
18575 bool try_again
= false;
18577 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
18578 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
18580 /* See if the comparison works as is. */
18581 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
18589 swap_operands
= true;
18594 swap_operands
= true;
18602 /* Invert condition and try again.
18603 e.g., A != B becomes ~(A==B). */
18605 enum rtx_code rev_code
;
18606 enum insn_code nor_code
;
18609 rev_code
= reverse_condition_maybe_unordered (rcode
);
18610 if (rev_code
== UNKNOWN
)
18613 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
18614 if (nor_code
== CODE_FOR_nothing
)
18617 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
18621 mask
= gen_reg_rtx (dmode
);
18622 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
18630 /* Try GT/GTU/LT/LTU OR EQ */
18633 enum insn_code ior_code
;
18634 enum rtx_code new_code
;
18655 gcc_unreachable ();
18658 ior_code
= optab_handler (ior_optab
, dmode
);
18659 if (ior_code
== CODE_FOR_nothing
)
18662 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
18666 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
18670 mask
= gen_reg_rtx (dmode
);
18671 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
18689 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
18694 /* You only get two chances. */
18698 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
18699 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
18700 operands for the relation operation COND. */
18703 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
18704 rtx cond
, rtx cc_op0
, rtx cc_op1
)
18706 enum machine_mode dest_mode
= GET_MODE (dest
);
18707 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
18708 enum rtx_code rcode
= GET_CODE (cond
);
18709 enum machine_mode cc_mode
= CCmode
;
18713 bool invert_move
= false;
18715 if (VECTOR_UNIT_NONE_P (dest_mode
))
18718 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
18719 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
18723 /* Swap operands if we can, and fall back to doing the operation as
18724 specified, and doing a NOR to invert the test. */
18730 /* Invert condition and try again.
18731 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
18732 invert_move
= true;
18733 rcode
= reverse_condition_maybe_unordered (rcode
);
18734 if (rcode
== UNKNOWN
)
18738 /* Mark unsigned tests with CCUNSmode. */
18743 cc_mode
= CCUNSmode
;
18750 /* Get the vector mask for the given relational operations. */
18751 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
18759 op_true
= op_false
;
18763 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
18764 CONST0_RTX (dest_mode
));
18765 emit_insn (gen_rtx_SET (VOIDmode
,
18767 gen_rtx_IF_THEN_ELSE (dest_mode
,
18774 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
18775 operands of the last comparison is nonzero/true, FALSE_COND if it
18776 is zero/false. Return 0 if the hardware has no such operation. */
18779 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18781 enum rtx_code code
= GET_CODE (op
);
18782 rtx op0
= XEXP (op
, 0);
18783 rtx op1
= XEXP (op
, 1);
18784 REAL_VALUE_TYPE c1
;
18785 enum machine_mode compare_mode
= GET_MODE (op0
);
18786 enum machine_mode result_mode
= GET_MODE (dest
);
18788 bool is_against_zero
;
18790 /* These modes should always match. */
18791 if (GET_MODE (op1
) != compare_mode
18792 /* In the isel case however, we can use a compare immediate, so
18793 op1 may be a small constant. */
18794 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
18796 if (GET_MODE (true_cond
) != result_mode
)
18798 if (GET_MODE (false_cond
) != result_mode
)
18801 /* Don't allow using floating point comparisons for integer results for
18803 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
18806 /* First, work out if the hardware can do this at all, or
18807 if it's too slow.... */
18808 if (!FLOAT_MODE_P (compare_mode
))
18811 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
18814 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
18815 && SCALAR_FLOAT_MODE_P (compare_mode
))
18818 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
18820 /* A floating-point subtract might overflow, underflow, or produce
18821 an inexact result, thus changing the floating-point flags, so it
18822 can't be generated if we care about that. It's safe if one side
18823 of the construct is zero, since then no subtract will be
18825 if (SCALAR_FLOAT_MODE_P (compare_mode
)
18826 && flag_trapping_math
&& ! is_against_zero
)
18829 /* Eliminate half of the comparisons by switching operands, this
18830 makes the remaining code simpler. */
18831 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
18832 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
18834 code
= reverse_condition_maybe_unordered (code
);
18836 true_cond
= false_cond
;
18840 /* UNEQ and LTGT take four instructions for a comparison with zero,
18841 it'll probably be faster to use a branch here too. */
18842 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
18845 if (GET_CODE (op1
) == CONST_DOUBLE
)
18846 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
18848 /* We're going to try to implement comparisons by performing
18849 a subtract, then comparing against zero. Unfortunately,
18850 Inf - Inf is NaN which is not zero, and so if we don't
18851 know that the operand is finite and the comparison
18852 would treat EQ different to UNORDERED, we can't do it. */
18853 if (HONOR_INFINITIES (compare_mode
)
18854 && code
!= GT
&& code
!= UNGE
18855 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
18856 /* Constructs of the form (a OP b ? a : b) are safe. */
18857 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
18858 || (! rtx_equal_p (op0
, true_cond
)
18859 && ! rtx_equal_p (op1
, true_cond
))))
18862 /* At this point we know we can use fsel. */
18864 /* Reduce the comparison to a comparison against zero. */
18865 if (! is_against_zero
)
18867 temp
= gen_reg_rtx (compare_mode
);
18868 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18869 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
18871 op1
= CONST0_RTX (compare_mode
);
18874 /* If we don't care about NaNs we can reduce some of the comparisons
18875 down to faster ones. */
18876 if (! HONOR_NANS (compare_mode
))
18882 true_cond
= false_cond
;
18895 /* Now, reduce everything down to a GE. */
18902 temp
= gen_reg_rtx (compare_mode
);
18903 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18908 temp
= gen_reg_rtx (compare_mode
);
18909 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
18914 temp
= gen_reg_rtx (compare_mode
);
18915 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18916 gen_rtx_NEG (compare_mode
,
18917 gen_rtx_ABS (compare_mode
, op0
))));
18922 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
18923 temp
= gen_reg_rtx (result_mode
);
18924 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18925 gen_rtx_IF_THEN_ELSE (result_mode
,
18926 gen_rtx_GE (VOIDmode
,
18928 true_cond
, false_cond
)));
18929 false_cond
= true_cond
;
18932 temp
= gen_reg_rtx (compare_mode
);
18933 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18938 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
18939 temp
= gen_reg_rtx (result_mode
);
18940 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18941 gen_rtx_IF_THEN_ELSE (result_mode
,
18942 gen_rtx_GE (VOIDmode
,
18944 true_cond
, false_cond
)));
18945 true_cond
= false_cond
;
18948 temp
= gen_reg_rtx (compare_mode
);
18949 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18954 gcc_unreachable ();
18957 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
18958 gen_rtx_IF_THEN_ELSE (result_mode
,
18959 gen_rtx_GE (VOIDmode
,
18961 true_cond
, false_cond
)));
18965 /* Same as above, but for ints (isel). */
18968 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18970 rtx condition_rtx
, cr
;
18971 enum machine_mode mode
= GET_MODE (dest
);
18972 enum rtx_code cond_code
;
18973 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
18976 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
18979 /* We still have to do the compare, because isel doesn't do a
18980 compare, it just looks at the CRx bits set by a previous compare
18982 condition_rtx
= rs6000_generate_compare (op
, mode
);
18983 cond_code
= GET_CODE (condition_rtx
);
18984 cr
= XEXP (condition_rtx
, 0);
18985 signedp
= GET_MODE (cr
) == CCmode
;
18987 isel_func
= (mode
== SImode
18988 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
18989 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
18993 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
18994 /* isel handles these directly. */
18998 /* We need to swap the sense of the comparison. */
19001 true_cond
= false_cond
;
19003 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
19008 false_cond
= force_reg (mode
, false_cond
);
19009 if (true_cond
!= const0_rtx
)
19010 true_cond
= force_reg (mode
, true_cond
);
19012 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
19018 output_isel (rtx
*operands
)
19020 enum rtx_code code
;
19022 code
= GET_CODE (operands
[1]);
19024 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
19026 gcc_assert (GET_CODE (operands
[2]) == REG
19027 && GET_CODE (operands
[3]) == REG
);
19028 PUT_CODE (operands
[1], reverse_condition (code
));
19029 return "isel %0,%3,%2,%j1";
19032 return "isel %0,%2,%3,%j1";
19036 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
19038 enum machine_mode mode
= GET_MODE (op0
);
19042 /* VSX/altivec have direct min/max insns. */
19043 if ((code
== SMAX
|| code
== SMIN
)
19044 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
19045 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
19047 emit_insn (gen_rtx_SET (VOIDmode
,
19049 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19053 if (code
== SMAX
|| code
== SMIN
)
19058 if (code
== SMAX
|| code
== UMAX
)
19059 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19060 op0
, op1
, mode
, 0);
19062 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19063 op1
, op0
, mode
, 0);
19064 gcc_assert (target
);
19065 if (target
!= dest
)
19066 emit_move_insn (dest
, target
);
19069 /* A subroutine of the atomic operation splitters. Jump to LABEL if
19070 COND is true. Mark the jump as unlikely to be taken. */
19073 emit_unlikely_jump (rtx cond
, rtx label
)
19075 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
19078 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
19079 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
19080 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
19083 /* A subroutine of the atomic operation splitters. Emit a load-locked
19084 instruction in MODE. For QI/HImode, possibly use a pattern than includes
19085 the zero_extend operation. */
19088 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
19090 rtx (*fn
) (rtx
, rtx
) = NULL
;
19095 fn
= gen_load_lockedqi
;
19098 fn
= gen_load_lockedhi
;
19101 if (GET_MODE (mem
) == QImode
)
19102 fn
= gen_load_lockedqi_si
;
19103 else if (GET_MODE (mem
) == HImode
)
19104 fn
= gen_load_lockedhi_si
;
19106 fn
= gen_load_lockedsi
;
19109 fn
= gen_load_lockeddi
;
19112 fn
= gen_load_lockedti
;
19115 gcc_unreachable ();
19117 emit_insn (fn (reg
, mem
));
19120 /* A subroutine of the atomic operation splitters. Emit a store-conditional
19121 instruction in MODE. */
19124 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
19126 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
19131 fn
= gen_store_conditionalqi
;
19134 fn
= gen_store_conditionalhi
;
19137 fn
= gen_store_conditionalsi
;
19140 fn
= gen_store_conditionaldi
;
19143 fn
= gen_store_conditionalti
;
19146 gcc_unreachable ();
19149 /* Emit sync before stwcx. to address PPC405 Erratum. */
19150 if (PPC405_ERRATUM77
)
19151 emit_insn (gen_hwsync ());
19153 emit_insn (fn (res
, mem
, val
));
19156 /* Expand barriers before and after a load_locked/store_cond sequence. */
19159 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
19161 rtx addr
= XEXP (mem
, 0);
19162 int strict_p
= (reload_in_progress
|| reload_completed
);
19164 if (!legitimate_indirect_address_p (addr
, strict_p
)
19165 && !legitimate_indexed_address_p (addr
, strict_p
))
19167 addr
= force_reg (Pmode
, addr
);
19168 mem
= replace_equiv_address_nv (mem
, addr
);
19173 case MEMMODEL_RELAXED
:
19174 case MEMMODEL_CONSUME
:
19175 case MEMMODEL_ACQUIRE
:
19177 case MEMMODEL_RELEASE
:
19178 case MEMMODEL_ACQ_REL
:
19179 emit_insn (gen_lwsync ());
19181 case MEMMODEL_SEQ_CST
:
19182 emit_insn (gen_hwsync ());
19185 gcc_unreachable ();
19191 rs6000_post_atomic_barrier (enum memmodel model
)
19195 case MEMMODEL_RELAXED
:
19196 case MEMMODEL_CONSUME
:
19197 case MEMMODEL_RELEASE
:
19199 case MEMMODEL_ACQUIRE
:
19200 case MEMMODEL_ACQ_REL
:
19201 case MEMMODEL_SEQ_CST
:
19202 emit_insn (gen_isync ());
19205 gcc_unreachable ();
19209 /* A subroutine of the various atomic expanders. For sub-word operations,
19210 we must adjust things to operate on SImode. Given the original MEM,
19211 return a new aligned memory. Also build and return the quantities by
19212 which to shift and mask. */
19215 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
19217 rtx addr
, align
, shift
, mask
, mem
;
19218 HOST_WIDE_INT shift_mask
;
19219 enum machine_mode mode
= GET_MODE (orig_mem
);
19221 /* For smaller modes, we have to implement this via SImode. */
19222 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
19224 addr
= XEXP (orig_mem
, 0);
19225 addr
= force_reg (GET_MODE (addr
), addr
);
19227 /* Aligned memory containing subword. Generate a new memory. We
19228 do not want any of the existing MEM_ATTR data, as we're now
19229 accessing memory outside the original object. */
19230 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
19231 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19232 mem
= gen_rtx_MEM (SImode
, align
);
19233 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
19234 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
19235 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
19237 /* Shift amount for subword relative to aligned word. */
19238 shift
= gen_reg_rtx (SImode
);
19239 addr
= gen_lowpart (SImode
, addr
);
19240 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
19241 if (WORDS_BIG_ENDIAN
)
19242 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
19243 shift
, 1, OPTAB_LIB_WIDEN
);
19246 /* Mask for insertion. */
19247 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
19248 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19254 /* A subroutine of the various atomic expanders. For sub-word operands,
19255 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
19258 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
19262 x
= gen_reg_rtx (SImode
);
19263 emit_insn (gen_rtx_SET (VOIDmode
, x
,
19264 gen_rtx_AND (SImode
,
19265 gen_rtx_NOT (SImode
, mask
),
19268 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
19273 /* A subroutine of the various atomic expanders. For sub-word operands,
19274 extract WIDE to NARROW via SHIFT. */
19277 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
19279 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
19280 wide
, 1, OPTAB_LIB_WIDEN
);
19281 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
19284 /* Expand an atomic compare and swap operation. */
19287 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
19289 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
19290 rtx label1
, label2
, x
, mask
, shift
;
19291 enum machine_mode mode
, orig_mode
;
19292 enum memmodel mod_s
, mod_f
;
19295 boolval
= operands
[0];
19296 retval
= operands
[1];
19298 oldval
= operands
[3];
19299 newval
= operands
[4];
19300 is_weak
= (INTVAL (operands
[5]) != 0);
19301 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
19302 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
19303 orig_mode
= mode
= GET_MODE (mem
);
19305 mask
= shift
= NULL_RTX
;
19306 if (mode
== QImode
|| mode
== HImode
)
19308 /* Before power8, we didn't have access to lbarx/lharx, so generate a
19309 lwarx and shift/mask operations. With power8, we need to do the
19310 comparison in SImode, but the store is still done in QI/HImode. */
19311 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
19313 if (!TARGET_SYNC_HI_QI
)
19315 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19317 /* Shift and mask OLDVAL into position with the word. */
19318 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
19319 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19321 /* Shift and mask NEWVAL into position within the word. */
19322 newval
= convert_modes (SImode
, mode
, newval
, 1);
19323 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
19324 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19327 /* Prepare to adjust the return value. */
19328 retval
= gen_reg_rtx (SImode
);
19331 else if (reg_overlap_mentioned_p (retval
, oldval
))
19332 oldval
= copy_to_reg (oldval
);
19334 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
19339 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19340 emit_label (XEXP (label1
, 0));
19342 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19344 emit_load_locked (mode
, retval
, mem
);
19349 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
19350 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19353 cond
= gen_reg_rtx (CCmode
);
19354 /* If we have TImode, synthesize a comparison. */
19355 if (mode
!= TImode
)
19356 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
19359 rtx xor1_result
= gen_reg_rtx (DImode
);
19360 rtx xor2_result
= gen_reg_rtx (DImode
);
19361 rtx or_result
= gen_reg_rtx (DImode
);
19362 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
19363 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
19364 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
19365 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
19367 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
19368 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
19369 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
19370 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
19373 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
19375 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19376 emit_unlikely_jump (x
, label2
);
19380 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
19382 emit_store_conditional (orig_mode
, cond
, mem
, x
);
19386 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19387 emit_unlikely_jump (x
, label1
);
19390 if (mod_f
!= MEMMODEL_RELAXED
)
19391 emit_label (XEXP (label2
, 0));
19393 rs6000_post_atomic_barrier (mod_s
);
19395 if (mod_f
== MEMMODEL_RELAXED
)
19396 emit_label (XEXP (label2
, 0));
19399 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
19400 else if (mode
!= GET_MODE (operands
[1]))
19401 convert_move (operands
[1], retval
, 1);
19403 /* In all cases, CR0 contains EQ on success, and NE on failure. */
19404 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
19405 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
19408 /* Expand an atomic exchange operation. */
19411 rs6000_expand_atomic_exchange (rtx operands
[])
19413 rtx retval
, mem
, val
, cond
;
19414 enum machine_mode mode
;
19415 enum memmodel model
;
19416 rtx label
, x
, mask
, shift
;
19418 retval
= operands
[0];
19421 model
= (enum memmodel
) INTVAL (operands
[3]);
19422 mode
= GET_MODE (mem
);
19424 mask
= shift
= NULL_RTX
;
19425 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
19427 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19429 /* Shift and mask VAL into position with the word. */
19430 val
= convert_modes (SImode
, mode
, val
, 1);
19431 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19432 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19434 /* Prepare to adjust the return value. */
19435 retval
= gen_reg_rtx (SImode
);
19439 mem
= rs6000_pre_atomic_barrier (mem
, model
);
19441 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19442 emit_label (XEXP (label
, 0));
19444 emit_load_locked (mode
, retval
, mem
);
19448 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
19450 cond
= gen_reg_rtx (CCmode
);
19451 emit_store_conditional (mode
, cond
, mem
, x
);
19453 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19454 emit_unlikely_jump (x
, label
);
19456 rs6000_post_atomic_barrier (model
);
19459 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
19462 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
19463 to perform. MEM is the memory on which to operate. VAL is the second
19464 operand of the binary operator. BEFORE and AFTER are optional locations to
19465 return the value of MEM either before of after the operation. MODEL_RTX
19466 is a CONST_INT containing the memory model to use. */
19469 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
19470 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
19472 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
19473 enum machine_mode mode
= GET_MODE (mem
);
19474 enum machine_mode store_mode
= mode
;
19475 rtx label
, x
, cond
, mask
, shift
;
19476 rtx before
= orig_before
, after
= orig_after
;
19478 mask
= shift
= NULL_RTX
;
19479 /* On power8, we want to use SImode for the operation. On previous systems,
19480 use the operation in a subword and shift/mask to get the proper byte or
19482 if (mode
== QImode
|| mode
== HImode
)
19484 if (TARGET_SYNC_HI_QI
)
19486 val
= convert_modes (SImode
, mode
, val
, 1);
19488 /* Prepare to adjust the return value. */
19489 before
= gen_reg_rtx (SImode
);
19491 after
= gen_reg_rtx (SImode
);
19496 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19498 /* Shift and mask VAL into position with the word. */
19499 val
= convert_modes (SImode
, mode
, val
, 1);
19500 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19501 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19507 /* We've already zero-extended VAL. That is sufficient to
19508 make certain that it does not affect other bits. */
19513 /* If we make certain that all of the other bits in VAL are
19514 set, that will be sufficient to not affect other bits. */
19515 x
= gen_rtx_NOT (SImode
, mask
);
19516 x
= gen_rtx_IOR (SImode
, x
, val
);
19517 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
19524 /* These will all affect bits outside the field and need
19525 adjustment via MASK within the loop. */
19529 gcc_unreachable ();
19532 /* Prepare to adjust the return value. */
19533 before
= gen_reg_rtx (SImode
);
19535 after
= gen_reg_rtx (SImode
);
19536 store_mode
= mode
= SImode
;
19540 mem
= rs6000_pre_atomic_barrier (mem
, model
);
19542 label
= gen_label_rtx ();
19543 emit_label (label
);
19544 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
19546 if (before
== NULL_RTX
)
19547 before
= gen_reg_rtx (mode
);
19549 emit_load_locked (mode
, before
, mem
);
19553 x
= expand_simple_binop (mode
, AND
, before
, val
,
19554 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19555 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
19559 after
= expand_simple_binop (mode
, code
, before
, val
,
19560 after
, 1, OPTAB_LIB_WIDEN
);
19566 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
19567 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19568 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
19570 else if (store_mode
!= mode
)
19571 x
= convert_modes (store_mode
, mode
, x
, 1);
19573 cond
= gen_reg_rtx (CCmode
);
19574 emit_store_conditional (store_mode
, cond
, mem
, x
);
19576 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19577 emit_unlikely_jump (x
, label
);
19579 rs6000_post_atomic_barrier (model
);
19583 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
19584 then do the calcuations in a SImode register. */
19586 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
19588 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
19590 else if (store_mode
!= mode
)
19592 /* QImode/HImode on machines with lbarx/lharx where we do the native
19593 operation and then do the calcuations in a SImode register. */
19595 convert_move (orig_before
, before
, 1);
19597 convert_move (orig_after
, after
, 1);
19599 else if (orig_after
&& after
!= orig_after
)
19600 emit_move_insn (orig_after
, after
);
19603 /* Emit instructions to move SRC to DST. Called by splitters for
19604 multi-register moves. It will emit at most one instruction for
19605 each register that is accessed; that is, it won't emit li/lis pairs
19606 (or equivalent for 64-bit code). One of SRC or DST must be a hard
19610 rs6000_split_multireg_move (rtx dst
, rtx src
)
19612 /* The register number of the first register being moved. */
19614 /* The mode that is to be moved. */
19615 enum machine_mode mode
;
19616 /* The mode that the move is being done in, and its size. */
19617 enum machine_mode reg_mode
;
19619 /* The number of registers that will be moved. */
19622 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
19623 mode
= GET_MODE (dst
);
19624 nregs
= hard_regno_nregs
[reg
][mode
];
19625 if (FP_REGNO_P (reg
))
19626 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
19627 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
19628 else if (ALTIVEC_REGNO_P (reg
))
19629 reg_mode
= V16QImode
;
19630 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
19633 reg_mode
= word_mode
;
19634 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
19636 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
19638 /* TDmode residing in FP registers is special, since the ISA requires that
19639 the lower-numbered word of a register pair is always the most significant
19640 word, even in little-endian mode. This does not match the usual subreg
19641 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
19642 the appropriate constituent registers "by hand" in little-endian mode.
19644 Note we do not need to check for destructive overlap here since TDmode
19645 can only reside in even/odd register pairs. */
19646 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
19651 for (i
= 0; i
< nregs
; i
++)
19653 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
19654 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
19656 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
19657 i
* reg_mode_size
);
19659 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
19660 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
19662 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
19663 i
* reg_mode_size
);
19665 emit_insn (gen_rtx_SET (VOIDmode
, p_dst
, p_src
));
19671 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
19673 /* Move register range backwards, if we might have destructive
19676 for (i
= nregs
- 1; i
>= 0; i
--)
19677 emit_insn (gen_rtx_SET (VOIDmode
,
19678 simplify_gen_subreg (reg_mode
, dst
, mode
,
19679 i
* reg_mode_size
),
19680 simplify_gen_subreg (reg_mode
, src
, mode
,
19681 i
* reg_mode_size
)));
19687 bool used_update
= false;
19688 rtx restore_basereg
= NULL_RTX
;
19690 if (MEM_P (src
) && INT_REGNO_P (reg
))
19694 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
19695 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
19698 breg
= XEXP (XEXP (src
, 0), 0);
19699 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
19700 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
19701 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
19702 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
19703 src
= replace_equiv_address (src
, breg
);
19705 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
19707 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
19709 rtx basereg
= XEXP (XEXP (src
, 0), 0);
19712 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
19713 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
19714 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
19715 used_update
= true;
19718 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
19719 XEXP (XEXP (src
, 0), 1)));
19720 src
= replace_equiv_address (src
, basereg
);
19724 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
19725 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
19726 src
= replace_equiv_address (src
, basereg
);
19730 breg
= XEXP (src
, 0);
19731 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
19732 breg
= XEXP (breg
, 0);
19734 /* If the base register we are using to address memory is
19735 also a destination reg, then change that register last. */
19737 && REGNO (breg
) >= REGNO (dst
)
19738 && REGNO (breg
) < REGNO (dst
) + nregs
)
19739 j
= REGNO (breg
) - REGNO (dst
);
19741 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
19745 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
19746 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
19749 breg
= XEXP (XEXP (dst
, 0), 0);
19750 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
19751 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
19752 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
19754 /* We have to update the breg before doing the store.
19755 Use store with update, if available. */
19759 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
19760 emit_insn (TARGET_32BIT
19761 ? (TARGET_POWERPC64
19762 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
19763 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
19764 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
19765 used_update
= true;
19768 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
19769 dst
= replace_equiv_address (dst
, breg
);
19771 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
19772 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
19774 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
19776 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
19779 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
19780 emit_insn (gen_rtx_SET (VOIDmode
,
19781 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
19782 used_update
= true;
19785 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
19786 XEXP (XEXP (dst
, 0), 1)));
19787 dst
= replace_equiv_address (dst
, basereg
);
19791 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
19792 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
19793 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
19795 && REG_P (offsetreg
)
19796 && REGNO (basereg
) != REGNO (offsetreg
));
19797 if (REGNO (basereg
) == 0)
19799 rtx tmp
= offsetreg
;
19800 offsetreg
= basereg
;
19803 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
19804 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
19805 dst
= replace_equiv_address (dst
, basereg
);
19808 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
19809 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
19812 for (i
= 0; i
< nregs
; i
++)
19814 /* Calculate index to next subword. */
19819 /* If compiler already emitted move of first word by
19820 store with update, no need to do anything. */
19821 if (j
== 0 && used_update
)
19824 emit_insn (gen_rtx_SET (VOIDmode
,
19825 simplify_gen_subreg (reg_mode
, dst
, mode
,
19826 j
* reg_mode_size
),
19827 simplify_gen_subreg (reg_mode
, src
, mode
,
19828 j
* reg_mode_size
)));
19830 if (restore_basereg
!= NULL_RTX
)
19831 emit_insn (restore_basereg
);
19836 /* This page contains routines that are used to determine what the
19837 function prologue and epilogue code will do and write them out. */
19842 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
19845 /* Return the first fixed-point register that is required to be
19846 saved. 32 if none. */
19849 first_reg_to_save (void)
19853 /* Find lowest numbered live register. */
19854 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
19855 if (save_reg_p (first_reg
))
19858 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
19859 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
19860 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
19861 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
19862 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
19863 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
19867 && crtl
->uses_pic_offset_table
19868 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
19869 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
19875 /* Similar, for FP regs. */
19878 first_fp_reg_to_save (void)
19882 /* Find lowest numbered live register. */
19883 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
19884 if (save_reg_p (first_reg
))
19890 /* Similar, for AltiVec regs. */
19893 first_altivec_reg_to_save (void)
19897 /* Stack frame remains as is unless we are in AltiVec ABI. */
19898 if (! TARGET_ALTIVEC_ABI
)
19899 return LAST_ALTIVEC_REGNO
+ 1;
19901 /* On Darwin, the unwind routines are compiled without
19902 TARGET_ALTIVEC, and use save_world to save/restore the
19903 altivec registers when necessary. */
19904 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
19905 && ! TARGET_ALTIVEC
)
19906 return FIRST_ALTIVEC_REGNO
+ 20;
19908 /* Find lowest numbered live register. */
19909 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19910 if (save_reg_p (i
))
19916 /* Return a 32-bit mask of the AltiVec registers we need to set in
19917 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
19918 the 32-bit word is 0. */
19920 static unsigned int
19921 compute_vrsave_mask (void)
19923 unsigned int i
, mask
= 0;
19925 /* On Darwin, the unwind routines are compiled without
19926 TARGET_ALTIVEC, and use save_world to save/restore the
19927 call-saved altivec registers when necessary. */
19928 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
19929 && ! TARGET_ALTIVEC
)
19932 /* First, find out if we use _any_ altivec registers. */
19933 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19934 if (df_regs_ever_live_p (i
))
19935 mask
|= ALTIVEC_REG_BIT (i
);
19940 /* Next, remove the argument registers from the set. These must
19941 be in the VRSAVE mask set by the caller, so we don't need to add
19942 them in again. More importantly, the mask we compute here is
19943 used to generate CLOBBERs in the set_vrsave insn, and we do not
19944 wish the argument registers to die. */
19945 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
19946 mask
&= ~ALTIVEC_REG_BIT (i
);
19948 /* Similarly, remove the return value from the set. */
19951 diddle_return_value (is_altivec_return_reg
, &yes
);
19953 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
19959 /* For a very restricted set of circumstances, we can cut down the
19960 size of prologues/epilogues by calling our own save/restore-the-world
19964 compute_save_world_info (rs6000_stack_t
*info_ptr
)
19966 info_ptr
->world_save_p
= 1;
19967 info_ptr
->world_save_p
19968 = (WORLD_SAVE_P (info_ptr
)
19969 && DEFAULT_ABI
== ABI_DARWIN
19970 && !cfun
->has_nonlocal_label
19971 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
19972 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
19973 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
19974 && info_ptr
->cr_save_p
);
19976 /* This will not work in conjunction with sibcalls. Make sure there
19977 are none. (This check is expensive, but seldom executed.) */
19978 if (WORLD_SAVE_P (info_ptr
))
19981 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
19982 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
19984 info_ptr
->world_save_p
= 0;
19989 if (WORLD_SAVE_P (info_ptr
))
19991 /* Even if we're not touching VRsave, make sure there's room on the
19992 stack for it, if it looks like we're calling SAVE_WORLD, which
19993 will attempt to save it. */
19994 info_ptr
->vrsave_size
= 4;
19996 /* If we are going to save the world, we need to save the link register too. */
19997 info_ptr
->lr_save_p
= 1;
19999 /* "Save" the VRsave register too if we're saving the world. */
20000 if (info_ptr
->vrsave_mask
== 0)
20001 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20003 /* Because the Darwin register save/restore routines only handle
20004 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
20006 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
20007 && (info_ptr
->first_altivec_reg_save
20008 >= FIRST_SAVED_ALTIVEC_REGNO
));
20015 is_altivec_return_reg (rtx reg
, void *xyes
)
20017 bool *yes
= (bool *) xyes
;
20018 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
20023 /* Look for user-defined global regs in the range FIRST to LAST-1.
20024 We should not restore these, and so cannot use lmw or out-of-line
20025 restore functions if there are any. We also can't save them
20026 (well, emit frame notes for them), because frame unwinding during
20027 exception handling will restore saved registers. */
20030 global_regs_p (unsigned first
, unsigned last
)
20032 while (first
< last
)
20033 if (global_regs
[first
++])
20038 /* Determine the strategy for savings/restoring registers. */
20041 SAVRES_MULTIPLE
= 0x1,
20042 SAVE_INLINE_FPRS
= 0x2,
20043 SAVE_INLINE_GPRS
= 0x4,
20044 REST_INLINE_FPRS
= 0x8,
20045 REST_INLINE_GPRS
= 0x10,
20046 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
20047 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
20048 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
20049 SAVE_INLINE_VRS
= 0x100,
20050 REST_INLINE_VRS
= 0x200
20054 rs6000_savres_strategy (rs6000_stack_t
*info
,
20055 bool using_static_chain_p
)
20060 if (TARGET_MULTIPLE
20061 && !TARGET_POWERPC64
20062 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
20063 && info
->first_gp_reg_save
< 31
20064 && !global_regs_p (info
->first_gp_reg_save
, 32))
20065 strategy
|= SAVRES_MULTIPLE
;
20067 if (crtl
->calls_eh_return
20068 || cfun
->machine
->ra_need_lr
)
20069 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
20070 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
20071 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20073 if (info
->first_fp_reg_save
== 64
20074 /* The out-of-line FP routines use double-precision stores;
20075 we can't use those routines if we don't have such stores. */
20076 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
20077 || global_regs_p (info
->first_fp_reg_save
, 64))
20078 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20080 if (info
->first_gp_reg_save
== 32
20081 || (!(strategy
& SAVRES_MULTIPLE
)
20082 && global_regs_p (info
->first_gp_reg_save
, 32)))
20083 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20085 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
20086 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
20087 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20089 /* Define cutoff for using out-of-line functions to save registers. */
20090 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
20092 if (!optimize_size
)
20094 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20095 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20096 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20100 /* Prefer out-of-line restore if it will exit. */
20101 if (info
->first_fp_reg_save
> 61)
20102 strategy
|= SAVE_INLINE_FPRS
;
20103 if (info
->first_gp_reg_save
> 29)
20105 if (info
->first_fp_reg_save
== 64)
20106 strategy
|= SAVE_INLINE_GPRS
;
20108 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20110 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
20111 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20114 else if (DEFAULT_ABI
== ABI_DARWIN
)
20116 if (info
->first_fp_reg_save
> 60)
20117 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20118 if (info
->first_gp_reg_save
> 29)
20119 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20120 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20124 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
20125 if (info
->first_fp_reg_save
> 61)
20126 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20127 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20128 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20131 /* Don't bother to try to save things out-of-line if r11 is occupied
20132 by the static chain. It would require too much fiddling and the
20133 static chain is rarely used anyway. FPRs are saved w.r.t the stack
20134 pointer on Darwin, and AIX uses r1 or r12. */
20135 if (using_static_chain_p
20136 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
20137 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
20139 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20141 /* We can only use the out-of-line routines to restore if we've
20142 saved all the registers from first_fp_reg_save in the prologue.
20143 Otherwise, we risk loading garbage. */
20144 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
20148 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
20149 if (!save_reg_p (i
))
20151 strategy
|= REST_INLINE_FPRS
;
20156 /* If we are going to use store multiple, then don't even bother
20157 with the out-of-line routines, since the store-multiple
20158 instruction will always be smaller. */
20159 if ((strategy
& SAVRES_MULTIPLE
))
20160 strategy
|= SAVE_INLINE_GPRS
;
20162 /* info->lr_save_p isn't yet set if the only reason lr needs to be
20163 saved is an out-of-line save or restore. Set up the value for
20164 the next test (excluding out-of-line gpr restore). */
20165 lr_save_p
= (info
->lr_save_p
20166 || !(strategy
& SAVE_INLINE_GPRS
)
20167 || !(strategy
& SAVE_INLINE_FPRS
)
20168 || !(strategy
& SAVE_INLINE_VRS
)
20169 || !(strategy
& REST_INLINE_FPRS
)
20170 || !(strategy
& REST_INLINE_VRS
));
20172 /* The situation is more complicated with load multiple. We'd
20173 prefer to use the out-of-line routines for restores, since the
20174 "exit" out-of-line routines can handle the restore of LR and the
20175 frame teardown. However if doesn't make sense to use the
20176 out-of-line routine if that is the only reason we'd need to save
20177 LR, and we can't use the "exit" out-of-line gpr restore if we
20178 have saved some fprs; In those cases it is advantageous to use
20179 load multiple when available. */
20180 if ((strategy
& SAVRES_MULTIPLE
)
20182 || info
->first_fp_reg_save
!= 64))
20183 strategy
|= REST_INLINE_GPRS
;
20185 /* Saving CR interferes with the exit routines used on the SPE, so
20188 && info
->spe_64bit_regs_used
20189 && info
->cr_save_p
)
20190 strategy
|= REST_INLINE_GPRS
;
20192 /* We can only use load multiple or the out-of-line routines to
20193 restore if we've used store multiple or out-of-line routines
20194 in the prologue, i.e. if we've saved all the registers from
20195 first_gp_reg_save. Otherwise, we risk loading garbage. */
20196 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
20197 == SAVE_INLINE_GPRS
)
20201 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
20202 if (!save_reg_p (i
))
20204 strategy
|= REST_INLINE_GPRS
;
20209 if (TARGET_ELF
&& TARGET_64BIT
)
20211 if (!(strategy
& SAVE_INLINE_FPRS
))
20212 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20213 else if (!(strategy
& SAVE_INLINE_GPRS
)
20214 && info
->first_fp_reg_save
== 64)
20215 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
20217 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
20218 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
20220 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
20221 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20226 /* Calculate the stack information for the current function. This is
20227 complicated by having two separate calling sequences, the AIX calling
20228 sequence and the V.4 calling sequence.
20230 AIX (and Darwin/Mac OS X) stack frames look like:
20232 SP----> +---------------------------------------+
20233 | back chain to caller | 0 0
20234 +---------------------------------------+
20235 | saved CR | 4 8 (8-11)
20236 +---------------------------------------+
20238 +---------------------------------------+
20239 | reserved for compilers | 12 24
20240 +---------------------------------------+
20241 | reserved for binders | 16 32
20242 +---------------------------------------+
20243 | saved TOC pointer | 20 40
20244 +---------------------------------------+
20245 | Parameter save area (P) | 24 48
20246 +---------------------------------------+
20247 | Alloca space (A) | 24+P etc.
20248 +---------------------------------------+
20249 | Local variable space (L) | 24+P+A
20250 +---------------------------------------+
20251 | Float/int conversion temporary (X) | 24+P+A+L
20252 +---------------------------------------+
20253 | Save area for AltiVec registers (W) | 24+P+A+L+X
20254 +---------------------------------------+
20255 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
20256 +---------------------------------------+
20257 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
20258 +---------------------------------------+
20259 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
20260 +---------------------------------------+
20261 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
20262 +---------------------------------------+
20263 old SP->| back chain to caller's caller |
20264 +---------------------------------------+
20266 The required alignment for AIX configurations is two words (i.e., 8
20269 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
20271 SP----> +---------------------------------------+
20272 | Back chain to caller | 0
20273 +---------------------------------------+
20274 | Save area for CR | 8
20275 +---------------------------------------+
20277 +---------------------------------------+
20278 | Saved TOC pointer | 24
20279 +---------------------------------------+
20280 | Parameter save area (P) | 32
20281 +---------------------------------------+
20282 | Alloca space (A) | 32+P
20283 +---------------------------------------+
20284 | Local variable space (L) | 32+P+A
20285 +---------------------------------------+
20286 | Save area for AltiVec registers (W) | 32+P+A+L
20287 +---------------------------------------+
20288 | AltiVec alignment padding (Y) | 32+P+A+L+W
20289 +---------------------------------------+
20290 | Save area for GP registers (G) | 32+P+A+L+W+Y
20291 +---------------------------------------+
20292 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
20293 +---------------------------------------+
20294 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
20295 +---------------------------------------+
20298 V.4 stack frames look like:
20300 SP----> +---------------------------------------+
20301 | back chain to caller | 0
20302 +---------------------------------------+
20303 | caller's saved LR | 4
20304 +---------------------------------------+
20305 | Parameter save area (P) | 8
20306 +---------------------------------------+
20307 | Alloca space (A) | 8+P
20308 +---------------------------------------+
20309 | Varargs save area (V) | 8+P+A
20310 +---------------------------------------+
20311 | Local variable space (L) | 8+P+A+V
20312 +---------------------------------------+
20313 | Float/int conversion temporary (X) | 8+P+A+V+L
20314 +---------------------------------------+
20315 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
20316 +---------------------------------------+
20317 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
20318 +---------------------------------------+
20319 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
20320 +---------------------------------------+
20321 | SPE: area for 64-bit GP registers |
20322 +---------------------------------------+
20323 | SPE alignment padding |
20324 +---------------------------------------+
20325 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
20326 +---------------------------------------+
20327 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
20328 +---------------------------------------+
20329 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
20330 +---------------------------------------+
20331 old SP->| back chain to caller's caller |
20332 +---------------------------------------+
20334 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
20335 given. (But note below and in sysv4.h that we require only 8 and
20336 may round up the size of our stack frame anyways. The historical
20337 reason is early versions of powerpc-linux which didn't properly
20338 align the stack at program startup. A happy side-effect is that
20339 -mno-eabi libraries can be used with -meabi programs.)
20341 The EABI configuration defaults to the V.4 layout. However,
20342 the stack alignment requirements may differ. If -mno-eabi is not
20343 given, the required stack alignment is 8 bytes; if -mno-eabi is
20344 given, the required alignment is 16 bytes. (But see V.4 comment
20347 #ifndef ABI_STACK_BOUNDARY
20348 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
20351 static rs6000_stack_t
*
20352 rs6000_stack_info (void)
20354 rs6000_stack_t
*info_ptr
= &stack_info
;
20355 int reg_size
= TARGET_32BIT
? 4 : 8;
20360 HOST_WIDE_INT non_fixed_size
;
20361 bool using_static_chain_p
;
20363 if (reload_completed
&& info_ptr
->reload_completed
)
20366 memset (info_ptr
, 0, sizeof (*info_ptr
));
20367 info_ptr
->reload_completed
= reload_completed
;
20371 /* Cache value so we don't rescan instruction chain over and over. */
20372 if (cfun
->machine
->insn_chain_scanned_p
== 0)
20373 cfun
->machine
->insn_chain_scanned_p
20374 = spe_func_has_64bit_regs_p () + 1;
20375 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
20378 /* Select which calling sequence. */
20379 info_ptr
->abi
= DEFAULT_ABI
;
20381 /* Calculate which registers need to be saved & save area size. */
20382 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
20383 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
20384 even if it currently looks like we won't. Reload may need it to
20385 get at a constant; if so, it will have already created a constant
20386 pool entry for it. */
20387 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
20388 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
20389 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
20390 && crtl
->uses_const_pool
20391 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
20392 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
20394 first_gp
= info_ptr
->first_gp_reg_save
;
20396 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
20398 /* For the SPE, we have an additional upper 32-bits on each GPR.
20399 Ideally we should save the entire 64-bits only when the upper
20400 half is used in SIMD instructions. Since we only record
20401 registers live (not the size they are used in), this proves
20402 difficult because we'd have to traverse the instruction chain at
20403 the right time, taking reload into account. This is a real pain,
20404 so we opt to save the GPRs in 64-bits always if but one register
20405 gets used in 64-bits. Otherwise, all the registers in the frame
20406 get saved in 32-bits.
20408 So... since when we save all GPRs (except the SP) in 64-bits, the
20409 traditional GP save area will be empty. */
20410 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20411 info_ptr
->gp_size
= 0;
20413 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
20414 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
20416 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
20417 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
20418 - info_ptr
->first_altivec_reg_save
);
20420 /* Does this function call anything? */
20421 info_ptr
->calls_p
= (! crtl
->is_leaf
20422 || cfun
->machine
->ra_needs_full_frame
);
20424 /* Determine if we need to save the condition code registers. */
20425 if (df_regs_ever_live_p (CR2_REGNO
)
20426 || df_regs_ever_live_p (CR3_REGNO
)
20427 || df_regs_ever_live_p (CR4_REGNO
))
20429 info_ptr
->cr_save_p
= 1;
20430 if (DEFAULT_ABI
== ABI_V4
)
20431 info_ptr
->cr_size
= reg_size
;
20434 /* If the current function calls __builtin_eh_return, then we need
20435 to allocate stack space for registers that will hold data for
20436 the exception handler. */
20437 if (crtl
->calls_eh_return
)
20440 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
20443 /* SPE saves EH registers in 64-bits. */
20444 ehrd_size
= i
* (TARGET_SPE_ABI
20445 && info_ptr
->spe_64bit_regs_used
!= 0
20446 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
20451 /* In the ELFv2 ABI, we also need to allocate space for separate
20452 CR field save areas if the function calls __builtin_eh_return. */
20453 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
20455 /* This hard-codes that we have three call-saved CR fields. */
20456 ehcr_size
= 3 * reg_size
;
20457 /* We do *not* use the regular CR save mechanism. */
20458 info_ptr
->cr_save_p
= 0;
20463 /* Determine various sizes. */
20464 info_ptr
->reg_size
= reg_size
;
20465 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
20466 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
20467 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
20468 TARGET_ALTIVEC
? 16 : 8);
20469 if (FRAME_GROWS_DOWNWARD
)
20470 info_ptr
->vars_size
20471 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
20472 + info_ptr
->parm_size
,
20473 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
20474 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
20475 + info_ptr
->parm_size
);
20477 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20478 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
20480 info_ptr
->spe_gp_size
= 0;
20482 if (TARGET_ALTIVEC_ABI
)
20483 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20485 info_ptr
->vrsave_mask
= 0;
20487 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
20488 info_ptr
->vrsave_size
= 4;
20490 info_ptr
->vrsave_size
= 0;
20492 compute_save_world_info (info_ptr
);
20494 /* Calculate the offsets. */
20495 switch (DEFAULT_ABI
)
20499 gcc_unreachable ();
20504 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
20505 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
20507 if (TARGET_ALTIVEC_ABI
)
20509 info_ptr
->vrsave_save_offset
20510 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
20512 /* Align stack so vector save area is on a quadword boundary.
20513 The padding goes above the vectors. */
20514 if (info_ptr
->altivec_size
!= 0)
20515 info_ptr
->altivec_padding_size
20516 = info_ptr
->vrsave_save_offset
& 0xF;
20518 info_ptr
->altivec_padding_size
= 0;
20520 info_ptr
->altivec_save_offset
20521 = info_ptr
->vrsave_save_offset
20522 - info_ptr
->altivec_padding_size
20523 - info_ptr
->altivec_size
;
20524 gcc_assert (info_ptr
->altivec_size
== 0
20525 || info_ptr
->altivec_save_offset
% 16 == 0);
20527 /* Adjust for AltiVec case. */
20528 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
20531 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
20533 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
20534 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
20535 info_ptr
->lr_save_offset
= 2*reg_size
;
20539 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
20540 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
20541 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
20543 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20545 /* Align stack so SPE GPR save area is aligned on a
20546 double-word boundary. */
20547 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
20548 info_ptr
->spe_padding_size
20549 = 8 - (-info_ptr
->cr_save_offset
% 8);
20551 info_ptr
->spe_padding_size
= 0;
20553 info_ptr
->spe_gp_save_offset
20554 = info_ptr
->cr_save_offset
20555 - info_ptr
->spe_padding_size
20556 - info_ptr
->spe_gp_size
;
20558 /* Adjust for SPE case. */
20559 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
20561 else if (TARGET_ALTIVEC_ABI
)
20563 info_ptr
->vrsave_save_offset
20564 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
20566 /* Align stack so vector save area is on a quadword boundary. */
20567 if (info_ptr
->altivec_size
!= 0)
20568 info_ptr
->altivec_padding_size
20569 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
20571 info_ptr
->altivec_padding_size
= 0;
20573 info_ptr
->altivec_save_offset
20574 = info_ptr
->vrsave_save_offset
20575 - info_ptr
->altivec_padding_size
20576 - info_ptr
->altivec_size
;
20578 /* Adjust for AltiVec case. */
20579 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
20582 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
20583 info_ptr
->ehrd_offset
-= ehrd_size
;
20584 info_ptr
->lr_save_offset
= reg_size
;
20588 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
20589 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
20590 + info_ptr
->gp_size
20591 + info_ptr
->altivec_size
20592 + info_ptr
->altivec_padding_size
20593 + info_ptr
->spe_gp_size
20594 + info_ptr
->spe_padding_size
20597 + info_ptr
->cr_size
20598 + info_ptr
->vrsave_size
,
20601 non_fixed_size
= (info_ptr
->vars_size
20602 + info_ptr
->parm_size
20603 + info_ptr
->save_size
);
20605 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
20606 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
20608 /* Determine if we need to save the link register. */
20609 if (info_ptr
->calls_p
20610 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
20612 && !TARGET_PROFILE_KERNEL
)
20613 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
20614 #ifdef TARGET_RELOCATABLE
20615 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
20617 || rs6000_ra_ever_killed ())
20618 info_ptr
->lr_save_p
= 1;
20620 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
20621 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
20622 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
20623 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
20624 using_static_chain_p
);
20626 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
20627 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
20628 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
20629 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
20630 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
20631 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
20632 info_ptr
->lr_save_p
= 1;
20634 if (info_ptr
->lr_save_p
)
20635 df_set_regs_ever_live (LR_REGNO
, true);
20637 /* Determine if we need to allocate any stack frame:
20639 For AIX we need to push the stack if a frame pointer is needed
20640 (because the stack might be dynamically adjusted), if we are
20641 debugging, if we make calls, or if the sum of fp_save, gp_save,
20642 and local variables are more than the space needed to save all
20643 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
20644 + 18*8 = 288 (GPR13 reserved).
20646 For V.4 we don't have the stack cushion that AIX uses, but assume
20647 that the debugger can handle stackless frames. */
20649 if (info_ptr
->calls_p
)
20650 info_ptr
->push_p
= 1;
20652 else if (DEFAULT_ABI
== ABI_V4
)
20653 info_ptr
->push_p
= non_fixed_size
!= 0;
20655 else if (frame_pointer_needed
)
20656 info_ptr
->push_p
= 1;
20658 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
20659 info_ptr
->push_p
= 1;
20662 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
20664 /* Zero offsets if we're not saving those registers. */
20665 if (info_ptr
->fp_size
== 0)
20666 info_ptr
->fp_save_offset
= 0;
20668 if (info_ptr
->gp_size
== 0)
20669 info_ptr
->gp_save_offset
= 0;
20671 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
20672 info_ptr
->altivec_save_offset
= 0;
20674 /* Zero VRSAVE offset if not saved and restored. */
20675 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
20676 info_ptr
->vrsave_save_offset
= 0;
20678 if (! TARGET_SPE_ABI
20679 || info_ptr
->spe_64bit_regs_used
== 0
20680 || info_ptr
->spe_gp_size
== 0)
20681 info_ptr
->spe_gp_save_offset
= 0;
20683 if (! info_ptr
->lr_save_p
)
20684 info_ptr
->lr_save_offset
= 0;
20686 if (! info_ptr
->cr_save_p
)
20687 info_ptr
->cr_save_offset
= 0;
20692 /* Return true if the current function uses any GPRs in 64-bit SIMD
20696 spe_func_has_64bit_regs_p (void)
20700 /* Functions that save and restore all the call-saved registers will
20701 need to save/restore the registers in 64-bits. */
20702 if (crtl
->calls_eh_return
20703 || cfun
->calls_setjmp
20704 || crtl
->has_nonlocal_goto
)
20707 insns
= get_insns ();
20709 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
20715 /* FIXME: This should be implemented with attributes...
20717 (set_attr "spe64" "true")....then,
20718 if (get_spe64(insn)) return true;
20720 It's the only reliable way to do the stuff below. */
20722 i
= PATTERN (insn
);
20723 if (GET_CODE (i
) == SET
)
20725 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
20727 if (SPE_VECTOR_MODE (mode
))
20729 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
20739 debug_stack_info (rs6000_stack_t
*info
)
20741 const char *abi_string
;
20744 info
= rs6000_stack_info ();
20746 fprintf (stderr
, "\nStack information for function %s:\n",
20747 ((current_function_decl
&& DECL_NAME (current_function_decl
))
20748 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
20753 default: abi_string
= "Unknown"; break;
20754 case ABI_NONE
: abi_string
= "NONE"; break;
20755 case ABI_AIX
: abi_string
= "AIX"; break;
20756 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
20757 case ABI_DARWIN
: abi_string
= "Darwin"; break;
20758 case ABI_V4
: abi_string
= "V.4"; break;
20761 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
20763 if (TARGET_ALTIVEC_ABI
)
20764 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
20766 if (TARGET_SPE_ABI
)
20767 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
20769 if (info
->first_gp_reg_save
!= 32)
20770 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
20772 if (info
->first_fp_reg_save
!= 64)
20773 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
20775 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
20776 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
20777 info
->first_altivec_reg_save
);
20779 if (info
->lr_save_p
)
20780 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
20782 if (info
->cr_save_p
)
20783 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
20785 if (info
->vrsave_mask
)
20786 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
20789 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
20792 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
20794 if (info
->gp_save_offset
)
20795 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
20797 if (info
->fp_save_offset
)
20798 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
20800 if (info
->altivec_save_offset
)
20801 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
20802 info
->altivec_save_offset
);
20804 if (info
->spe_gp_save_offset
)
20805 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
20806 info
->spe_gp_save_offset
);
20808 if (info
->vrsave_save_offset
)
20809 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
20810 info
->vrsave_save_offset
);
20812 if (info
->lr_save_offset
)
20813 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
20815 if (info
->cr_save_offset
)
20816 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
20818 if (info
->varargs_save_offset
)
20819 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
20821 if (info
->total_size
)
20822 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
20825 if (info
->vars_size
)
20826 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
20829 if (info
->parm_size
)
20830 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
20832 if (info
->fixed_size
)
20833 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
20836 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
20838 if (info
->spe_gp_size
)
20839 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
20842 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
20844 if (info
->altivec_size
)
20845 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
20847 if (info
->vrsave_size
)
20848 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
20850 if (info
->altivec_padding_size
)
20851 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
20852 info
->altivec_padding_size
);
20854 if (info
->spe_padding_size
)
20855 fprintf (stderr
, "\tspe_padding_size = %5d\n",
20856 info
->spe_padding_size
);
20859 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
20861 if (info
->save_size
)
20862 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
20864 if (info
->reg_size
!= 4)
20865 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
20867 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
20869 fprintf (stderr
, "\n");
20873 rs6000_return_addr (int count
, rtx frame
)
20875 /* Currently we don't optimize very well between prolog and body
20876 code and for PIC code the code can be actually quite bad, so
20877 don't try to be too clever here. */
20879 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
20881 cfun
->machine
->ra_needs_full_frame
= 1;
20888 plus_constant (Pmode
,
20890 (gen_rtx_MEM (Pmode
,
20891 memory_address (Pmode
, frame
))),
20892 RETURN_ADDRESS_OFFSET
)));
20895 cfun
->machine
->ra_need_lr
= 1;
20896 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
20899 /* Say whether a function is a candidate for sibcall handling or not. */
20902 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
20907 fntype
= TREE_TYPE (decl
);
20909 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
20911 /* We can't do it if the called function has more vector parameters
20912 than the current function; there's nowhere to put the VRsave code. */
20913 if (TARGET_ALTIVEC_ABI
20914 && TARGET_ALTIVEC_VRSAVE
20915 && !(decl
&& decl
== current_function_decl
))
20917 function_args_iterator args_iter
;
20921 /* Functions with vector parameters are required to have a
20922 prototype, so the argument type info must be available
20924 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
20925 if (TREE_CODE (type
) == VECTOR_TYPE
20926 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
20929 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
20930 if (TREE_CODE (type
) == VECTOR_TYPE
20931 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
20938 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
20939 functions, because the callee may have a different TOC pointer to
20940 the caller and there's no way to ensure we restore the TOC when
20941 we return. With the secure-plt SYSV ABI we can't make non-local
20942 calls when -fpic/PIC because the plt call stubs use r30. */
20943 if (DEFAULT_ABI
== ABI_DARWIN
20944 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
20946 && !DECL_EXTERNAL (decl
)
20947 && (*targetm
.binds_local_p
) (decl
))
20948 || (DEFAULT_ABI
== ABI_V4
20949 && (!TARGET_SECURE_PLT
20952 && (*targetm
.binds_local_p
) (decl
)))))
20954 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
20956 if (!lookup_attribute ("longcall", attr_list
)
20957 || lookup_attribute ("shortcall", attr_list
))
20965 rs6000_ra_ever_killed (void)
20971 if (cfun
->is_thunk
)
20974 if (cfun
->machine
->lr_save_state
)
20975 return cfun
->machine
->lr_save_state
- 1;
20977 /* regs_ever_live has LR marked as used if any sibcalls are present,
20978 but this should not force saving and restoring in the
20979 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
20980 clobbers LR, so that is inappropriate. */
20982 /* Also, the prologue can generate a store into LR that
20983 doesn't really count, like this:
20986 bcl to set PIC register
20990 When we're called from the epilogue, we need to avoid counting
20991 this as a store. */
20993 push_topmost_sequence ();
20994 top
= get_insns ();
20995 pop_topmost_sequence ();
20996 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
20998 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
21004 if (!SIBLING_CALL_P (insn
))
21007 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
21009 else if (set_of (reg
, insn
) != NULL_RTX
21010 && !prologue_epilogue_contains (insn
))
21017 /* Emit instructions needed to load the TOC register.
21018 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
21019 a constant pool; or for SVR4 -fpic. */
21022 rs6000_emit_load_toc_table (int fromprolog
)
21025 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
21027 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
21030 rtx lab
, tmp1
, tmp2
, got
;
21032 lab
= gen_label_rtx ();
21033 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
21034 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21036 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21038 got
= rs6000_got_sym ();
21039 tmp1
= tmp2
= dest
;
21042 tmp1
= gen_reg_rtx (Pmode
);
21043 tmp2
= gen_reg_rtx (Pmode
);
21045 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
21046 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
21047 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
21048 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
21050 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
21052 emit_insn (gen_load_toc_v4_pic_si ());
21053 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21055 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
21058 rtx temp0
= (fromprolog
21059 ? gen_rtx_REG (Pmode
, 0)
21060 : gen_reg_rtx (Pmode
));
21066 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21067 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21069 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
21070 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21072 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
21073 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21074 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
21080 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21081 lab
= gen_label_rtx ();
21082 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
21083 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21084 if (TARGET_LINK_STACK
)
21085 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
21086 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
21088 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
21090 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
21092 /* This is for AIX code running in non-PIC ELF32. */
21095 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21096 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21098 emit_insn (gen_elf_high (dest
, realsym
));
21099 emit_insn (gen_elf_low (dest
, dest
, realsym
));
21103 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
21106 emit_insn (gen_load_toc_aix_si (dest
));
21108 emit_insn (gen_load_toc_aix_di (dest
));
21112 /* Emit instructions to restore the link register after determining where
21113 its value has been stored. */
21116 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
21118 rs6000_stack_t
*info
= rs6000_stack_info ();
21121 operands
[0] = source
;
21122 operands
[1] = scratch
;
21124 if (info
->lr_save_p
)
21126 rtx frame_rtx
= stack_pointer_rtx
;
21127 HOST_WIDE_INT sp_offset
= 0;
21130 if (frame_pointer_needed
21131 || cfun
->calls_alloca
21132 || info
->total_size
> 32767)
21134 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
21135 emit_move_insn (operands
[1], tmp
);
21136 frame_rtx
= operands
[1];
21138 else if (info
->push_p
)
21139 sp_offset
= info
->total_size
;
21141 tmp
= plus_constant (Pmode
, frame_rtx
,
21142 info
->lr_save_offset
+ sp_offset
);
21143 tmp
= gen_frame_mem (Pmode
, tmp
);
21144 emit_move_insn (tmp
, operands
[0]);
21147 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
21149 /* Freeze lr_save_p. We've just emitted rtl that depends on the
21150 state of lr_save_p so any change from here on would be a bug. In
21151 particular, stop rs6000_ra_ever_killed from considering the SET
21152 of lr we may have added just above. */
21153 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
21156 static GTY(()) alias_set_type set
= -1;
21159 get_TOC_alias_set (void)
21162 set
= new_alias_set ();
21166 /* This returns nonzero if the current function uses the TOC. This is
21167 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
21168 is generated by the ABI_V4 load_toc_* patterns. */
21175 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
21178 rtx pat
= PATTERN (insn
);
21181 if (GET_CODE (pat
) == PARALLEL
)
21182 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
21184 rtx sub
= XVECEXP (pat
, 0, i
);
21185 if (GET_CODE (sub
) == USE
)
21187 sub
= XEXP (sub
, 0);
21188 if (GET_CODE (sub
) == UNSPEC
21189 && XINT (sub
, 1) == UNSPEC_TOC
)
21199 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
21201 rtx tocrel
, tocreg
, hi
;
21203 if (TARGET_DEBUG_ADDR
)
21205 if (GET_CODE (symbol
) == SYMBOL_REF
)
21206 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
21210 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
21211 GET_RTX_NAME (GET_CODE (symbol
)));
21212 debug_rtx (symbol
);
21216 if (!can_create_pseudo_p ())
21217 df_set_regs_ever_live (TOC_REGISTER
, true);
21219 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
21220 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
21221 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
21224 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
21225 if (largetoc_reg
!= NULL
)
21227 emit_move_insn (largetoc_reg
, hi
);
21230 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
21233 /* Issue assembly directives that create a reference to the given DWARF
21234 FRAME_TABLE_LABEL from the current function section. */
21236 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
21238 fprintf (asm_out_file
, "\t.ref %s\n",
21239 (* targetm
.strip_name_encoding
) (frame_table_label
));
21242 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
21243 and the change to the stack pointer. */
21246 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
21253 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21254 if (hard_frame_needed
)
21255 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
21256 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
21257 || (hard_frame_needed
21258 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
21261 p
= rtvec_alloc (i
);
21264 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
21265 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
21268 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
21271 /* Emit the correct code for allocating stack space, as insns.
21272 If COPY_REG, make sure a copy of the old frame is left there.
21273 The generated code may use hard register 0 as a temporary. */
21276 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
21279 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21280 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
21281 rtx todec
= gen_int_mode (-size
, Pmode
);
21284 if (INTVAL (todec
) != -size
)
21286 warning (0, "stack frame too large");
21287 emit_insn (gen_trap ());
21291 if (crtl
->limit_stack
)
21293 if (REG_P (stack_limit_rtx
)
21294 && REGNO (stack_limit_rtx
) > 1
21295 && REGNO (stack_limit_rtx
) <= 31)
21297 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
21298 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21301 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
21303 && DEFAULT_ABI
== ABI_V4
)
21305 rtx toload
= gen_rtx_CONST (VOIDmode
,
21306 gen_rtx_PLUS (Pmode
,
21310 emit_insn (gen_elf_high (tmp_reg
, toload
));
21311 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
21312 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21316 warning (0, "stack limit expression is not supported");
21322 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
21324 emit_move_insn (copy_reg
, stack_reg
);
21329 /* Need a note here so that try_split doesn't get confused. */
21330 if (get_last_insn () == NULL_RTX
)
21331 emit_note (NOTE_INSN_DELETED
);
21332 insn
= emit_move_insn (tmp_reg
, todec
);
21333 try_split (PATTERN (insn
), insn
, 0);
21337 insn
= emit_insn (TARGET_32BIT
21338 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
21340 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
21341 todec
, stack_reg
));
21342 /* Since we didn't use gen_frame_mem to generate the MEM, grab
21343 it now and set the alias set/attributes. The above gen_*_update
21344 calls will generate a PARALLEL with the MEM set being the first
21346 par
= PATTERN (insn
);
21347 gcc_assert (GET_CODE (par
) == PARALLEL
);
21348 set
= XVECEXP (par
, 0, 0);
21349 gcc_assert (GET_CODE (set
) == SET
);
21350 mem
= SET_DEST (set
);
21351 gcc_assert (MEM_P (mem
));
21352 MEM_NOTRAP_P (mem
) = 1;
21353 set_mem_alias_set (mem
, get_frame_alias_set ());
21355 RTX_FRAME_RELATED_P (insn
) = 1;
21356 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
21357 gen_rtx_SET (VOIDmode
, stack_reg
,
21358 gen_rtx_PLUS (Pmode
, stack_reg
,
21359 GEN_INT (-size
))));
21362 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
21364 #if PROBE_INTERVAL > 32768
21365 #error Cannot use indexed addressing mode for stack probing
21368 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
21369 inclusive. These are offsets from the current stack pointer. */
21372 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
21374 /* See if we have a constant small number of probes to generate. If so,
21375 that's the easy case. */
21376 if (first
+ size
<= 32768)
21380 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
21381 it exceeds SIZE. If only one probe is needed, this will not
21382 generate any code. Then probe at FIRST + SIZE. */
21383 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
21384 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
21387 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
21391 /* Otherwise, do the same as above, but in a loop. Note that we must be
21392 extra careful with variables wrapping around because we might be at
21393 the very top (or the very bottom) of the address space and we have
21394 to be able to handle this case properly; in particular, we use an
21395 equality test for the loop condition. */
21398 HOST_WIDE_INT rounded_size
;
21399 rtx r12
= gen_rtx_REG (Pmode
, 12);
21400 rtx r0
= gen_rtx_REG (Pmode
, 0);
21402 /* Sanity check for the addressing mode we're going to use. */
21403 gcc_assert (first
<= 32768);
21405 /* Step 1: round SIZE to the previous multiple of the interval. */
21407 rounded_size
= size
& -PROBE_INTERVAL
;
21410 /* Step 2: compute initial and final value of the loop counter. */
21412 /* TEST_ADDR = SP + FIRST. */
21413 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
21414 plus_constant (Pmode
, stack_pointer_rtx
,
21417 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
21418 if (rounded_size
> 32768)
21420 emit_move_insn (r0
, GEN_INT (-rounded_size
));
21421 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
21422 gen_rtx_PLUS (Pmode
, r12
, r0
)));
21425 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
21426 plus_constant (Pmode
, r12
, -rounded_size
)));
21429 /* Step 3: the loop
21431 while (TEST_ADDR != LAST_ADDR)
21433 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
21437 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
21438 until it is equal to ROUNDED_SIZE. */
21441 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
21443 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
21446 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
21447 that SIZE is equal to ROUNDED_SIZE. */
21449 if (size
!= rounded_size
)
21450 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
21454 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
21455 absolute addresses. */
21458 output_probe_stack_range (rtx reg1
, rtx reg2
)
21460 static int labelno
= 0;
21461 char loop_lab
[32], end_lab
[32];
21464 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
21465 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
21467 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
21469 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
21473 output_asm_insn ("cmpd 0,%0,%1", xops
);
21475 output_asm_insn ("cmpw 0,%0,%1", xops
);
21477 fputs ("\tbeq 0,", asm_out_file
);
21478 assemble_name_raw (asm_out_file
, end_lab
);
21479 fputc ('\n', asm_out_file
);
21481 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
21482 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
21483 output_asm_insn ("addi %0,%0,%1", xops
);
21485 /* Probe at TEST_ADDR and branch. */
21486 xops
[1] = gen_rtx_REG (Pmode
, 0);
21487 output_asm_insn ("stw %1,0(%0)", xops
);
21488 fprintf (asm_out_file
, "\tb ");
21489 assemble_name_raw (asm_out_file
, loop_lab
);
21490 fputc ('\n', asm_out_file
);
21492 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
21497 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
21498 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
21499 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
21500 deduce these equivalences by itself so it wasn't necessary to hold
21501 its hand so much. Don't be tempted to always supply d2_f_d_e with
21502 the actual cfa register, ie. r31 when we are using a hard frame
21503 pointer. That fails when saving regs off r1, and sched moves the
21504 r31 setup past the reg saves. */
21507 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
21508 rtx reg2
, rtx rreg
, rtx split_reg
)
21512 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
21514 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
21517 gcc_checking_assert (val
== 0);
21518 real
= PATTERN (insn
);
21519 if (GET_CODE (real
) == PARALLEL
)
21520 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
21521 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
21523 rtx set
= XVECEXP (real
, 0, i
);
21525 RTX_FRAME_RELATED_P (set
) = 1;
21527 RTX_FRAME_RELATED_P (insn
) = 1;
21531 /* copy_rtx will not make unique copies of registers, so we need to
21532 ensure we don't have unwanted sharing here. */
21534 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
21537 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
21539 real
= copy_rtx (PATTERN (insn
));
21541 if (reg2
!= NULL_RTX
)
21542 real
= replace_rtx (real
, reg2
, rreg
);
21544 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
21545 gcc_checking_assert (val
== 0);
21547 real
= replace_rtx (real
, reg
,
21548 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
21549 STACK_POINTER_REGNUM
),
21552 /* We expect that 'real' is either a SET or a PARALLEL containing
21553 SETs (and possibly other stuff). In a PARALLEL, all the SETs
21554 are important so they all have to be marked RTX_FRAME_RELATED_P. */
21556 if (GET_CODE (real
) == SET
)
21560 temp
= simplify_rtx (SET_SRC (set
));
21562 SET_SRC (set
) = temp
;
21563 temp
= simplify_rtx (SET_DEST (set
));
21565 SET_DEST (set
) = temp
;
21566 if (GET_CODE (SET_DEST (set
)) == MEM
)
21568 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
21570 XEXP (SET_DEST (set
), 0) = temp
;
21577 gcc_assert (GET_CODE (real
) == PARALLEL
);
21578 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
21579 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
21581 rtx set
= XVECEXP (real
, 0, i
);
21583 temp
= simplify_rtx (SET_SRC (set
));
21585 SET_SRC (set
) = temp
;
21586 temp
= simplify_rtx (SET_DEST (set
));
21588 SET_DEST (set
) = temp
;
21589 if (GET_CODE (SET_DEST (set
)) == MEM
)
21591 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
21593 XEXP (SET_DEST (set
), 0) = temp
;
21595 RTX_FRAME_RELATED_P (set
) = 1;
21599 /* If a store insn has been split into multiple insns, the
21600 true source register is given by split_reg. */
21601 if (split_reg
!= NULL_RTX
)
21602 real
= gen_rtx_SET (VOIDmode
, SET_DEST (real
), split_reg
);
21604 RTX_FRAME_RELATED_P (insn
) = 1;
21605 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
21610 /* Returns an insn that has a vrsave set operation with the
21611 appropriate CLOBBERs. */
21614 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
21617 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
21618 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
21621 = gen_rtx_SET (VOIDmode
,
21623 gen_rtx_UNSPEC_VOLATILE (SImode
,
21624 gen_rtvec (2, reg
, vrsave
),
21625 UNSPECV_SET_VRSAVE
));
21629 /* We need to clobber the registers in the mask so the scheduler
21630 does not move sets to VRSAVE before sets of AltiVec registers.
21632 However, if the function receives nonlocal gotos, reload will set
21633 all call saved registers live. We will end up with:
21635 (set (reg 999) (mem))
21636 (parallel [ (set (reg vrsave) (unspec blah))
21637 (clobber (reg 999))])
21639 The clobber will cause the store into reg 999 to be dead, and
21640 flow will attempt to delete an epilogue insn. In this case, we
21641 need an unspec use/set of the register. */
21643 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21644 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
21646 if (!epiloguep
|| call_used_regs
[i
])
21647 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
21648 gen_rtx_REG (V4SImode
, i
));
21651 rtx reg
= gen_rtx_REG (V4SImode
, i
);
21654 = gen_rtx_SET (VOIDmode
,
21656 gen_rtx_UNSPEC (V4SImode
,
21657 gen_rtvec (1, reg
), 27));
21661 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
21663 for (i
= 0; i
< nclobs
; ++i
)
21664 XVECEXP (insn
, 0, i
) = clobs
[i
];
21670 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
21674 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
21675 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
21676 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
21680 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
21682 return gen_frame_set (reg
, frame_reg
, offset
, false);
21686 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
21688 return gen_frame_set (reg
, frame_reg
, offset
, true);
21691 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
21692 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
21695 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
21696 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
21700 /* Some cases that need register indexed addressing. */
21701 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
21702 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
21703 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
21705 && SPE_VECTOR_MODE (mode
)
21706 && !SPE_CONST_OFFSET_OK (offset
))));
21708 reg
= gen_rtx_REG (mode
, regno
);
21709 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
21710 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
21711 NULL_RTX
, NULL_RTX
, NULL_RTX
);
21714 /* Emit an offset memory reference suitable for a frame store, while
21715 converting to a valid addressing mode. */
21718 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
21720 rtx int_rtx
, offset_rtx
;
21722 int_rtx
= GEN_INT (offset
);
21724 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
21725 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
21727 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
21728 emit_move_insn (offset_rtx
, int_rtx
);
21731 offset_rtx
= int_rtx
;
21733 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
21736 #ifndef TARGET_FIX_AND_CONTINUE
21737 #define TARGET_FIX_AND_CONTINUE 0
21740 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
21741 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
21742 #define LAST_SAVRES_REGISTER 31
21743 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
21754 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
21756 /* Temporary holding space for an out-of-line register save/restore
21758 static char savres_routine_name
[30];
21760 /* Return the name for an out-of-line register save/restore routine.
21761 We are saving/restoring GPRs if GPR is true. */
21764 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
21766 const char *prefix
= "";
21767 const char *suffix
= "";
21769 /* Different targets are supposed to define
21770 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
21771 routine name could be defined with:
21773 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
21775 This is a nice idea in practice, but in reality, things are
21776 complicated in several ways:
21778 - ELF targets have save/restore routines for GPRs.
21780 - SPE targets use different prefixes for 32/64-bit registers, and
21781 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
21783 - PPC64 ELF targets have routines for save/restore of GPRs that
21784 differ in what they do with the link register, so having a set
21785 prefix doesn't work. (We only use one of the save routines at
21786 the moment, though.)
21788 - PPC32 elf targets have "exit" versions of the restore routines
21789 that restore the link register and can save some extra space.
21790 These require an extra suffix. (There are also "tail" versions
21791 of the restore routines and "GOT" versions of the save routines,
21792 but we don't generate those at present. Same problems apply,
21795 We deal with all this by synthesizing our own prefix/suffix and
21796 using that for the simple sprintf call shown above. */
21799 /* No floating point saves on the SPE. */
21800 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
21802 if ((sel
& SAVRES_SAVE
))
21803 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
21805 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
21807 if ((sel
& SAVRES_LR
))
21810 else if (DEFAULT_ABI
== ABI_V4
)
21815 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21816 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
21817 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21818 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
21819 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21820 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
21824 if ((sel
& SAVRES_LR
))
21827 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21829 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
21830 /* No out-of-line save/restore routines for GPRs on AIX. */
21831 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
21835 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21836 prefix
= ((sel
& SAVRES_SAVE
)
21837 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
21838 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
21839 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21841 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
21842 if ((sel
& SAVRES_LR
))
21843 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
21847 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
21848 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
21851 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21852 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
21857 if (DEFAULT_ABI
== ABI_DARWIN
)
21859 /* The Darwin approach is (slightly) different, in order to be
21860 compatible with code generated by the system toolchain. There is a
21861 single symbol for the start of save sequence, and the code here
21862 embeds an offset into that code on the basis of the first register
21864 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
21865 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21866 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
21867 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
21868 (regno
- 13) * 4, prefix
, regno
);
21869 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21870 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
21871 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
21872 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21873 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
21874 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
21879 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
21881 return savres_routine_name
;
21884 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
21885 We are saving/restoring GPRs if GPR is true. */
21888 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
21890 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21891 ? info
->first_gp_reg_save
21892 : (sel
& SAVRES_REG
) == SAVRES_FPR
21893 ? info
->first_fp_reg_save
- 32
21894 : (sel
& SAVRES_REG
) == SAVRES_VR
21895 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
21900 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
21901 versions of the gpr routines. */
21902 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
21903 && info
->spe_64bit_regs_used
)
21904 select
^= SAVRES_FPR
^ SAVRES_GPR
;
21906 /* Don't generate bogus routine names. */
21907 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
21908 && regno
<= LAST_SAVRES_REGISTER
21909 && select
>= 0 && select
<= 12);
21911 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
21917 name
= rs6000_savres_routine_name (info
, regno
, sel
);
21919 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
21920 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
21921 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
21927 /* Emit a sequence of insns, including a stack tie if needed, for
21928 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
21929 reset the stack pointer, but move the base of the frame into
21930 reg UPDT_REGNO for use by out-of-line register restore routines. */
21933 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
21934 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
21935 unsigned updt_regno
)
21939 /* This blockage is needed so that sched doesn't decide to move
21940 the sp change before the register restores. */
21941 if (DEFAULT_ABI
== ABI_V4
21943 && info
->spe_64bit_regs_used
!= 0
21944 && info
->first_gp_reg_save
!= 32))
21945 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
21947 /* If we are restoring registers out-of-line, we will be using the
21948 "exit" variants of the restore routines, which will reset the
21949 stack for us. But we do need to point updt_reg into the
21950 right place for those routines. */
21951 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
21953 if (frame_off
!= 0)
21954 return emit_insn (gen_add3_insn (updt_reg_rtx
,
21955 frame_reg_rtx
, GEN_INT (frame_off
)));
21956 else if (REGNO (frame_reg_rtx
) != updt_regno
)
21957 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
21962 /* Return the register number used as a pointer by out-of-line
21963 save/restore functions. */
21965 static inline unsigned
21966 ptr_regno_for_savres (int sel
)
21968 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21969 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
21970 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
21973 /* Construct a parallel rtx describing the effect of a call to an
21974 out-of-line register save/restore routine, and emit the insn
21975 or jump_insn as appropriate. */
21978 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
21979 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
21980 enum machine_mode reg_mode
, int sel
)
21983 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
21984 int reg_size
= GET_MODE_SIZE (reg_mode
);
21990 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21991 ? info
->first_gp_reg_save
21992 : (sel
& SAVRES_REG
) == SAVRES_FPR
21993 ? info
->first_fp_reg_save
21994 : (sel
& SAVRES_REG
) == SAVRES_VR
21995 ? info
->first_altivec_reg_save
21997 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21999 : (sel
& SAVRES_REG
) == SAVRES_FPR
22001 : (sel
& SAVRES_REG
) == SAVRES_VR
22002 ? LAST_ALTIVEC_REGNO
+ 1
22004 n_regs
= end_reg
- start_reg
;
22005 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
22006 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
22009 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22010 RTVEC_ELT (p
, offset
++) = ret_rtx
;
22012 RTVEC_ELT (p
, offset
++)
22013 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
22015 sym
= rs6000_savres_routine_sym (info
, sel
);
22016 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
22018 use_reg
= ptr_regno_for_savres (sel
);
22019 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
22021 /* Vector regs are saved/restored using [reg+reg] addressing. */
22022 RTVEC_ELT (p
, offset
++)
22023 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22024 RTVEC_ELT (p
, offset
++)
22025 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
22028 RTVEC_ELT (p
, offset
++)
22029 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
22031 for (i
= 0; i
< end_reg
- start_reg
; i
++)
22032 RTVEC_ELT (p
, i
+ offset
)
22033 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
22034 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
22035 (sel
& SAVRES_SAVE
) != 0);
22037 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22038 RTVEC_ELT (p
, i
+ offset
)
22039 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
22041 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
22043 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
22045 insn
= emit_jump_insn (par
);
22046 JUMP_LABEL (insn
) = ret_rtx
;
22049 insn
= emit_insn (par
);
22053 /* Emit code to store CR fields that need to be saved into REG. */
22056 rs6000_emit_move_from_cr (rtx reg
)
22058 /* Only the ELFv2 ABI allows storing only selected fields. */
22059 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
22061 int i
, cr_reg
[8], count
= 0;
22063 /* Collect CR fields that must be saved. */
22064 for (i
= 0; i
< 8; i
++)
22065 if (save_reg_p (CR0_REGNO
+ i
))
22066 cr_reg
[count
++] = i
;
22068 /* If it's just a single one, use mfcrf. */
22071 rtvec p
= rtvec_alloc (1);
22072 rtvec r
= rtvec_alloc (2);
22073 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
22074 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
22076 = gen_rtx_SET (VOIDmode
, reg
,
22077 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
22079 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22083 /* ??? It might be better to handle count == 2 / 3 cases here
22084 as well, using logical operations to combine the values. */
22087 emit_insn (gen_movesi_from_cr (reg
));
22090 /* Determine whether the gp REG is really used. */
22093 rs6000_reg_live_or_pic_offset_p (int reg
)
22095 /* If the function calls eh_return, claim used all the registers that would
22096 be checked for liveness otherwise. This is required for the PIC offset
22097 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
22098 register allocation purposes in this case. */
22100 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
22101 && (!call_used_regs
[reg
]
22102 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22103 && !TARGET_SINGLE_PIC_BASE
22104 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
22105 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22106 && !TARGET_SINGLE_PIC_BASE
22107 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
22108 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
22111 /* Emit function prologue as insns. */
22114 rs6000_emit_prologue (void)
22116 rs6000_stack_t
*info
= rs6000_stack_info ();
22117 enum machine_mode reg_mode
= Pmode
;
22118 int reg_size
= TARGET_32BIT
? 4 : 8;
22119 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22120 rtx frame_reg_rtx
= sp_reg_rtx
;
22121 unsigned int cr_save_regno
;
22122 rtx cr_save_rtx
= NULL_RTX
;
22125 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
22126 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
22127 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
22128 /* Offset to top of frame for frame_reg and sp respectively. */
22129 HOST_WIDE_INT frame_off
= 0;
22130 HOST_WIDE_INT sp_off
= 0;
22132 #ifdef ENABLE_CHECKING
22133 /* Track and check usage of r0, r11, r12. */
22134 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
22135 #define START_USE(R) do \
22137 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22138 reg_inuse |= 1 << (R); \
22140 #define END_USE(R) do \
22142 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
22143 reg_inuse &= ~(1 << (R)); \
22145 #define NOT_INUSE(R) do \
22147 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22150 #define START_USE(R) do {} while (0)
22151 #define END_USE(R) do {} while (0)
22152 #define NOT_INUSE(R) do {} while (0)
22155 if (DEFAULT_ABI
== ABI_ELFv2
)
22157 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
22159 /* With -mminimal-toc we may generate an extra use of r2 below. */
22160 if (!TARGET_SINGLE_PIC_BASE
22161 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22162 cfun
->machine
->r2_setup_needed
= true;
22166 if (flag_stack_usage_info
)
22167 current_function_static_stack_size
= info
->total_size
;
22169 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
22171 HOST_WIDE_INT size
= info
->total_size
;
22173 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
22175 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
22176 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
22177 size
- STACK_CHECK_PROTECT
);
22180 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
22183 if (TARGET_FIX_AND_CONTINUE
)
22185 /* gdb on darwin arranges to forward a function from the old
22186 address by modifying the first 5 instructions of the function
22187 to branch to the overriding function. This is necessary to
22188 permit function pointers that point to the old function to
22189 actually forward to the new function. */
22190 emit_insn (gen_nop ());
22191 emit_insn (gen_nop ());
22192 emit_insn (gen_nop ());
22193 emit_insn (gen_nop ());
22194 emit_insn (gen_nop ());
22197 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
22199 reg_mode
= V2SImode
;
22203 /* Handle world saves specially here. */
22204 if (WORLD_SAVE_P (info
))
22211 /* save_world expects lr in r0. */
22212 reg0
= gen_rtx_REG (Pmode
, 0);
22213 if (info
->lr_save_p
)
22215 insn
= emit_move_insn (reg0
,
22216 gen_rtx_REG (Pmode
, LR_REGNO
));
22217 RTX_FRAME_RELATED_P (insn
) = 1;
22220 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
22221 assumptions about the offsets of various bits of the stack
22223 gcc_assert (info
->gp_save_offset
== -220
22224 && info
->fp_save_offset
== -144
22225 && info
->lr_save_offset
== 8
22226 && info
->cr_save_offset
== 4
22229 && (!crtl
->calls_eh_return
22230 || info
->ehrd_offset
== -432)
22231 && info
->vrsave_save_offset
== -224
22232 && info
->altivec_save_offset
== -416);
22234 treg
= gen_rtx_REG (SImode
, 11);
22235 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
22237 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
22238 in R11. It also clobbers R12, so beware! */
22240 /* Preserve CR2 for save_world prologues */
22242 sz
+= 32 - info
->first_gp_reg_save
;
22243 sz
+= 64 - info
->first_fp_reg_save
;
22244 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
22245 p
= rtvec_alloc (sz
);
22247 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
22248 gen_rtx_REG (SImode
,
22250 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
22251 gen_rtx_SYMBOL_REF (Pmode
,
22253 /* We do floats first so that the instruction pattern matches
22255 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22257 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22259 info
->first_fp_reg_save
+ i
),
22261 info
->fp_save_offset
+ frame_off
+ 8 * i
);
22262 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
22264 = gen_frame_store (gen_rtx_REG (V4SImode
,
22265 info
->first_altivec_reg_save
+ i
),
22267 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
22268 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22270 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22272 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22274 /* CR register traditionally saved as CR2. */
22276 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
22277 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
22278 /* Explain about use of R0. */
22279 if (info
->lr_save_p
)
22281 = gen_frame_store (reg0
,
22282 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22283 /* Explain what happens to the stack pointer. */
22285 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
22286 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
22289 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22290 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22291 treg
, GEN_INT (-info
->total_size
), NULL_RTX
);
22292 sp_off
= frame_off
= info
->total_size
;
22295 strategy
= info
->savres_strategy
;
22297 /* For V.4, update stack before we do any saving and set back pointer. */
22298 if (! WORLD_SAVE_P (info
)
22300 && (DEFAULT_ABI
== ABI_V4
22301 || crtl
->calls_eh_return
))
22303 bool need_r11
= (TARGET_SPE
22304 ? (!(strategy
& SAVE_INLINE_GPRS
)
22305 && info
->spe_64bit_regs_used
== 0)
22306 : (!(strategy
& SAVE_INLINE_FPRS
)
22307 || !(strategy
& SAVE_INLINE_GPRS
)
22308 || !(strategy
& SAVE_INLINE_VRS
)));
22309 int ptr_regno
= -1;
22310 rtx ptr_reg
= NULL_RTX
;
22313 if (info
->total_size
< 32767)
22314 frame_off
= info
->total_size
;
22317 else if (info
->cr_save_p
22319 || info
->first_fp_reg_save
< 64
22320 || info
->first_gp_reg_save
< 32
22321 || info
->altivec_size
!= 0
22322 || info
->vrsave_mask
!= 0
22323 || crtl
->calls_eh_return
)
22327 /* The prologue won't be saving any regs so there is no need
22328 to set up a frame register to access any frame save area.
22329 We also won't be using frame_off anywhere below, but set
22330 the correct value anyway to protect against future
22331 changes to this function. */
22332 frame_off
= info
->total_size
;
22334 if (ptr_regno
!= -1)
22336 /* Set up the frame offset to that needed by the first
22337 out-of-line save function. */
22338 START_USE (ptr_regno
);
22339 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22340 frame_reg_rtx
= ptr_reg
;
22341 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
22342 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
22343 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
22344 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
22345 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
22346 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22347 frame_off
= -ptr_off
;
22349 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22350 sp_off
= info
->total_size
;
22351 if (frame_reg_rtx
!= sp_reg_rtx
)
22352 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22355 /* If we use the link register, get it into r0. */
22356 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
22358 rtx addr
, reg
, mem
;
22360 reg
= gen_rtx_REG (Pmode
, 0);
22362 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22363 RTX_FRAME_RELATED_P (insn
) = 1;
22365 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
22366 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
22368 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22369 GEN_INT (info
->lr_save_offset
+ frame_off
));
22370 mem
= gen_rtx_MEM (Pmode
, addr
);
22371 /* This should not be of rs6000_sr_alias_set, because of
22372 __builtin_return_address. */
22374 insn
= emit_move_insn (mem
, reg
);
22375 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22376 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22381 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
22382 r12 will be needed by out-of-line gpr restore. */
22383 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22384 && !(strategy
& (SAVE_INLINE_GPRS
22385 | SAVE_NOINLINE_GPRS_SAVES_LR
))
22387 if (!WORLD_SAVE_P (info
)
22389 && REGNO (frame_reg_rtx
) != cr_save_regno
22390 && !(using_static_chain_p
&& cr_save_regno
== 11))
22392 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
22393 START_USE (cr_save_regno
);
22394 rs6000_emit_move_from_cr (cr_save_rtx
);
22397 /* Do any required saving of fpr's. If only one or two to save, do
22398 it ourselves. Otherwise, call function. */
22399 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
22402 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22403 if (save_reg_p (info
->first_fp_reg_save
+ i
))
22404 emit_frame_save (frame_reg_rtx
,
22405 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22406 ? DFmode
: SFmode
),
22407 info
->first_fp_reg_save
+ i
,
22408 info
->fp_save_offset
+ frame_off
+ 8 * i
,
22409 sp_off
- frame_off
);
22411 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
22413 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
22414 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22415 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22416 rtx ptr_reg
= frame_reg_rtx
;
22418 if (REGNO (frame_reg_rtx
) == ptr_regno
)
22419 gcc_checking_assert (frame_off
== 0);
22422 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22423 NOT_INUSE (ptr_regno
);
22424 emit_insn (gen_add3_insn (ptr_reg
,
22425 frame_reg_rtx
, GEN_INT (frame_off
)));
22427 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
22428 info
->fp_save_offset
,
22429 info
->lr_save_offset
,
22431 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
22432 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22437 /* Save GPRs. This is done as a PARALLEL if we are using
22438 the store-multiple instructions. */
22439 if (!WORLD_SAVE_P (info
)
22441 && info
->spe_64bit_regs_used
!= 0
22442 && info
->first_gp_reg_save
!= 32)
22445 rtx spe_save_area_ptr
;
22446 HOST_WIDE_INT save_off
;
22447 int ool_adjust
= 0;
22449 /* Determine whether we can address all of the registers that need
22450 to be saved with an offset from frame_reg_rtx that fits in
22451 the small const field for SPE memory instructions. */
22452 int spe_regs_addressable
22453 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
22454 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
22455 && (strategy
& SAVE_INLINE_GPRS
));
22457 if (spe_regs_addressable
)
22459 spe_save_area_ptr
= frame_reg_rtx
;
22460 save_off
= frame_off
;
22464 /* Make r11 point to the start of the SPE save area. We need
22465 to be careful here if r11 is holding the static chain. If
22466 it is, then temporarily save it in r0. */
22467 HOST_WIDE_INT offset
;
22469 if (!(strategy
& SAVE_INLINE_GPRS
))
22470 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
22471 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
22472 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
22473 save_off
= frame_off
- offset
;
22475 if (using_static_chain_p
)
22477 rtx r0
= gen_rtx_REG (Pmode
, 0);
22480 gcc_assert (info
->first_gp_reg_save
> 11);
22482 emit_move_insn (r0
, spe_save_area_ptr
);
22484 else if (REGNO (frame_reg_rtx
) != 11)
22487 emit_insn (gen_addsi3 (spe_save_area_ptr
,
22488 frame_reg_rtx
, GEN_INT (offset
)));
22489 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
22490 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
22493 if ((strategy
& SAVE_INLINE_GPRS
))
22495 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22496 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22497 emit_frame_save (spe_save_area_ptr
, reg_mode
,
22498 info
->first_gp_reg_save
+ i
,
22499 (info
->spe_gp_save_offset
+ save_off
22501 sp_off
- save_off
);
22505 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
22506 info
->spe_gp_save_offset
+ save_off
,
22508 SAVRES_SAVE
| SAVRES_GPR
);
22510 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
22511 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22514 /* Move the static chain pointer back. */
22515 if (!spe_regs_addressable
)
22517 if (using_static_chain_p
)
22519 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
22522 else if (REGNO (frame_reg_rtx
) != 11)
22526 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
22528 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
22529 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
22530 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22531 rtx ptr_reg
= frame_reg_rtx
;
22532 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
22533 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
22537 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22539 /* Need to adjust r11 (r12) if we saved any FPRs. */
22540 if (end_save
+ frame_off
!= 0)
22542 rtx offset
= GEN_INT (end_save
+ frame_off
);
22545 frame_off
= -end_save
;
22547 NOT_INUSE (ptr_regno
);
22548 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22550 else if (!ptr_set_up
)
22552 NOT_INUSE (ptr_regno
);
22553 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22555 ptr_off
= -end_save
;
22556 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
22557 info
->gp_save_offset
+ ptr_off
,
22558 info
->lr_save_offset
+ ptr_off
,
22560 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
22561 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22565 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
22569 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
22570 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22572 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22574 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22575 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22576 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22577 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22579 else if (!WORLD_SAVE_P (info
))
22582 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22583 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22584 emit_frame_save (frame_reg_rtx
, reg_mode
,
22585 info
->first_gp_reg_save
+ i
,
22586 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
22587 sp_off
- frame_off
);
22590 if (crtl
->calls_eh_return
)
22597 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
22598 if (regno
== INVALID_REGNUM
)
22602 p
= rtvec_alloc (i
);
22606 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
22607 if (regno
== INVALID_REGNUM
)
22611 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
22613 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
22614 RTVEC_ELT (p
, i
) = insn
;
22615 RTX_FRAME_RELATED_P (insn
) = 1;
22618 insn
= emit_insn (gen_blockage ());
22619 RTX_FRAME_RELATED_P (insn
) = 1;
22620 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
22623 /* In AIX ABI we need to make sure r2 is really saved. */
22624 if (TARGET_AIX
&& crtl
->calls_eh_return
)
22626 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
22627 rtx save_insn
, join_insn
, note
;
22628 long toc_restore_insn
;
22630 tmp_reg
= gen_rtx_REG (Pmode
, 11);
22631 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
22632 if (using_static_chain_p
)
22635 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
22639 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22640 /* Peek at instruction to which this function returns. If it's
22641 restoring r2, then we know we've already saved r2. We can't
22642 unconditionally save r2 because the value we have will already
22643 be updated if we arrived at this function via a plt call or
22644 toc adjusting stub. */
22645 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
22646 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
22647 + RS6000_TOC_SAVE_SLOT
);
22648 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
22649 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
22650 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
22651 validate_condition_mode (EQ
, CCUNSmode
);
22652 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
22653 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
22654 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
22655 toc_save_done
= gen_label_rtx ();
22656 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
22657 gen_rtx_EQ (VOIDmode
, compare_result
,
22659 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
22661 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
22662 JUMP_LABEL (jump
) = toc_save_done
;
22663 LABEL_NUSES (toc_save_done
) += 1;
22665 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
22666 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
22667 sp_off
- frame_off
);
22669 emit_label (toc_save_done
);
22671 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
22672 have a CFG that has different saves along different paths.
22673 Move the note to a dummy blockage insn, which describes that
22674 R2 is unconditionally saved after the label. */
22675 /* ??? An alternate representation might be a special insn pattern
22676 containing both the branch and the store. That might let the
22677 code that minimizes the number of DW_CFA_advance opcodes better
22678 freedom in placing the annotations. */
22679 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
22681 remove_note (save_insn
, note
);
22683 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
22684 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
22685 RTX_FRAME_RELATED_P (save_insn
) = 0;
22687 join_insn
= emit_insn (gen_blockage ());
22688 REG_NOTES (join_insn
) = note
;
22689 RTX_FRAME_RELATED_P (join_insn
) = 1;
22691 if (using_static_chain_p
)
22693 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
22700 /* Save CR if we use any that must be preserved. */
22701 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
22703 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22704 GEN_INT (info
->cr_save_offset
+ frame_off
));
22705 rtx mem
= gen_frame_mem (SImode
, addr
);
22707 /* If we didn't copy cr before, do so now using r0. */
22708 if (cr_save_rtx
== NULL_RTX
)
22711 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
22712 rs6000_emit_move_from_cr (cr_save_rtx
);
22715 /* Saving CR requires a two-instruction sequence: one instruction
22716 to move the CR to a general-purpose register, and a second
22717 instruction that stores the GPR to memory.
22719 We do not emit any DWARF CFI records for the first of these,
22720 because we cannot properly represent the fact that CR is saved in
22721 a register. One reason is that we cannot express that multiple
22722 CR fields are saved; another reason is that on 64-bit, the size
22723 of the CR register in DWARF (4 bytes) differs from the size of
22724 a general-purpose register.
22726 This means if any intervening instruction were to clobber one of
22727 the call-saved CR fields, we'd have incorrect CFI. To prevent
22728 this from happening, we mark the store to memory as a use of
22729 those CR fields, which prevents any such instruction from being
22730 scheduled in between the two instructions. */
22735 crsave_v
[n_crsave
++] = gen_rtx_SET (VOIDmode
, mem
, cr_save_rtx
);
22736 for (i
= 0; i
< 8; i
++)
22737 if (save_reg_p (CR0_REGNO
+ i
))
22738 crsave_v
[n_crsave
++]
22739 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
22741 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
22742 gen_rtvec_v (n_crsave
, crsave_v
)));
22743 END_USE (REGNO (cr_save_rtx
));
22745 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
22746 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
22747 so we need to construct a frame expression manually. */
22748 RTX_FRAME_RELATED_P (insn
) = 1;
22750 /* Update address to be stack-pointer relative, like
22751 rs6000_frame_related would do. */
22752 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
22753 GEN_INT (info
->cr_save_offset
+ sp_off
));
22754 mem
= gen_frame_mem (SImode
, addr
);
22756 if (DEFAULT_ABI
== ABI_ELFv2
)
22758 /* In the ELFv2 ABI we generate separate CFI records for each
22759 CR field that was actually saved. They all point to the
22760 same 32-bit stack slot. */
22764 for (i
= 0; i
< 8; i
++)
22765 if (save_reg_p (CR0_REGNO
+ i
))
22768 = gen_rtx_SET (VOIDmode
, mem
,
22769 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
22771 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
22775 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22776 gen_rtx_PARALLEL (VOIDmode
,
22777 gen_rtvec_v (n_crframe
, crframe
)));
22781 /* In other ABIs, by convention, we use a single CR regnum to
22782 represent the fact that all call-saved CR fields are saved.
22783 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
22784 rtx set
= gen_rtx_SET (VOIDmode
, mem
,
22785 gen_rtx_REG (SImode
, CR2_REGNO
));
22786 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
22790 /* In the ELFv2 ABI we need to save all call-saved CR fields into
22791 *separate* slots if the routine calls __builtin_eh_return, so
22792 that they can be independently restored by the unwinder. */
22793 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
22795 int i
, cr_off
= info
->ehcr_offset
;
22798 /* ??? We might get better performance by using multiple mfocrf
22800 crsave
= gen_rtx_REG (SImode
, 0);
22801 emit_insn (gen_movesi_from_cr (crsave
));
22803 for (i
= 0; i
< 8; i
++)
22804 if (!call_used_regs
[CR0_REGNO
+ i
])
22806 rtvec p
= rtvec_alloc (2);
22808 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
22810 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
22812 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22814 RTX_FRAME_RELATED_P (insn
) = 1;
22815 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22816 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
22817 sp_reg_rtx
, cr_off
+ sp_off
));
22819 cr_off
+= reg_size
;
22823 /* Update stack and set back pointer unless this is V.4,
22824 for which it was done previously. */
22825 if (!WORLD_SAVE_P (info
) && info
->push_p
22826 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
22828 rtx ptr_reg
= NULL
;
22831 /* If saving altivec regs we need to be able to address all save
22832 locations using a 16-bit offset. */
22833 if ((strategy
& SAVE_INLINE_VRS
) == 0
22834 || (info
->altivec_size
!= 0
22835 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
22836 + info
->total_size
- frame_off
) > 32767)
22837 || (info
->vrsave_size
!= 0
22838 && (info
->vrsave_save_offset
22839 + info
->total_size
- frame_off
) > 32767))
22841 int sel
= SAVRES_SAVE
| SAVRES_VR
;
22842 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22844 if (using_static_chain_p
22845 && ptr_regno
== STATIC_CHAIN_REGNUM
)
22847 if (REGNO (frame_reg_rtx
) != ptr_regno
)
22848 START_USE (ptr_regno
);
22849 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22850 frame_reg_rtx
= ptr_reg
;
22851 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22852 frame_off
= -ptr_off
;
22854 else if (REGNO (frame_reg_rtx
) == 1)
22855 frame_off
= info
->total_size
;
22856 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22857 sp_off
= info
->total_size
;
22858 if (frame_reg_rtx
!= sp_reg_rtx
)
22859 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22862 /* Set frame pointer, if needed. */
22863 if (frame_pointer_needed
)
22865 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
22867 RTX_FRAME_RELATED_P (insn
) = 1;
22870 /* Save AltiVec registers if needed. Save here because the red zone does
22871 not always include AltiVec registers. */
22872 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
22873 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
22875 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
22877 /* Oddly, the vector save/restore functions point r0 at the end
22878 of the save area, then use r11 or r12 to load offsets for
22879 [reg+reg] addressing. */
22880 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
22881 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
22882 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
22884 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
22886 if (end_save
+ frame_off
!= 0)
22888 rtx offset
= GEN_INT (end_save
+ frame_off
);
22890 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22893 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22895 ptr_off
= -end_save
;
22896 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
22897 info
->altivec_save_offset
+ ptr_off
,
22898 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
22899 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
22900 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22901 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
22903 /* The oddity mentioned above clobbered our frame reg. */
22904 emit_move_insn (frame_reg_rtx
, ptr_reg
);
22905 frame_off
= ptr_off
;
22908 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
22909 && info
->altivec_size
!= 0)
22913 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22914 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22916 rtx areg
, savereg
, mem
, split_reg
;
22919 offset
= (info
->altivec_save_offset
+ frame_off
22920 + 16 * (i
- info
->first_altivec_reg_save
));
22922 savereg
= gen_rtx_REG (V4SImode
, i
);
22925 areg
= gen_rtx_REG (Pmode
, 0);
22926 emit_move_insn (areg
, GEN_INT (offset
));
22928 /* AltiVec addressing mode is [reg+reg]. */
22929 mem
= gen_frame_mem (V4SImode
,
22930 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
22932 insn
= emit_move_insn (mem
, savereg
);
22934 /* When we split a VSX store into two insns, we need to make
22935 sure the DWARF info knows which register we are storing.
22936 Pass it in to be used on the appropriate note. */
22937 if (!BYTES_BIG_ENDIAN
22938 && GET_CODE (PATTERN (insn
)) == SET
22939 && GET_CODE (SET_SRC (PATTERN (insn
))) == VEC_SELECT
)
22940 split_reg
= savereg
;
22942 split_reg
= NULL_RTX
;
22944 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22945 areg
, GEN_INT (offset
), split_reg
);
22949 /* VRSAVE is a bit vector representing which AltiVec registers
22950 are used. The OS uses this to determine which vector
22951 registers to save on a context switch. We need to save
22952 VRSAVE on the stack frame, add whatever AltiVec registers we
22953 used in this function, and do the corresponding magic in the
22956 if (!WORLD_SAVE_P (info
)
22958 && TARGET_ALTIVEC_VRSAVE
22959 && info
->vrsave_mask
!= 0)
22965 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
22966 be using r12 as frame_reg_rtx and r11 as the static chain
22967 pointer for nested functions. */
22969 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22970 && !using_static_chain_p
)
22972 else if (REGNO (frame_reg_rtx
) == 12)
22975 if (using_static_chain_p
)
22979 NOT_INUSE (save_regno
);
22980 reg
= gen_rtx_REG (SImode
, save_regno
);
22981 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22983 emit_insn (gen_get_vrsave_internal (reg
));
22985 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
22988 offset
= info
->vrsave_save_offset
+ frame_off
;
22989 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
22991 /* Include the registers in the mask. */
22992 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
22994 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
22997 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
22998 if (!TARGET_SINGLE_PIC_BASE
22999 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
23000 || (DEFAULT_ABI
== ABI_V4
23001 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
23002 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
23004 /* If emit_load_toc_table will use the link register, we need to save
23005 it. We use R12 for this purpose because emit_load_toc_table
23006 can use register 0. This allows us to use a plain 'blr' to return
23007 from the procedure more often. */
23008 int save_LR_around_toc_setup
= (TARGET_ELF
23009 && DEFAULT_ABI
== ABI_V4
23011 && ! info
->lr_save_p
23012 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
23013 if (save_LR_around_toc_setup
)
23015 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23016 rtx tmp
= gen_rtx_REG (Pmode
, 12);
23018 insn
= emit_move_insn (tmp
, lr
);
23019 RTX_FRAME_RELATED_P (insn
) = 1;
23021 rs6000_emit_load_toc_table (TRUE
);
23023 insn
= emit_move_insn (lr
, tmp
);
23024 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23025 RTX_FRAME_RELATED_P (insn
) = 1;
23028 rs6000_emit_load_toc_table (TRUE
);
23032 if (!TARGET_SINGLE_PIC_BASE
23033 && DEFAULT_ABI
== ABI_DARWIN
23034 && flag_pic
&& crtl
->uses_pic_offset_table
)
23036 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23037 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
23039 /* Save and restore LR locally around this call (in R0). */
23040 if (!info
->lr_save_p
)
23041 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
23043 emit_insn (gen_load_macho_picbase (src
));
23045 emit_move_insn (gen_rtx_REG (Pmode
,
23046 RS6000_PIC_OFFSET_TABLE_REGNUM
),
23049 if (!info
->lr_save_p
)
23050 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
23054 /* If we need to, save the TOC register after doing the stack setup.
23055 Do not emit eh frame info for this save. The unwinder wants info,
23056 conceptually attached to instructions in this function, about
23057 register values in the caller of this function. This R2 may have
23058 already been changed from the value in the caller.
23059 We don't attempt to write accurate DWARF EH frame info for R2
23060 because code emitted by gcc for a (non-pointer) function call
23061 doesn't save and restore R2. Instead, R2 is managed out-of-line
23062 by a linker generated plt call stub when the function resides in
23063 a shared library. This behaviour is costly to describe in DWARF,
23064 both in terms of the size of DWARF info and the time taken in the
23065 unwinder to interpret it. R2 changes, apart from the
23066 calls_eh_return case earlier in this function, are handled by
23067 linux-unwind.h frob_update_context. */
23068 if (rs6000_save_toc_in_prologue_p ())
23070 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
23071 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
23075 /* Write function prologue. */
23078 rs6000_output_function_prologue (FILE *file
,
23079 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
23081 rs6000_stack_t
*info
= rs6000_stack_info ();
23083 if (TARGET_DEBUG_STACK
)
23084 debug_stack_info (info
);
23086 /* Write .extern for any function we will call to save and restore
23088 if (info
->first_fp_reg_save
< 64
23093 int regno
= info
->first_fp_reg_save
- 32;
23095 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
23097 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23098 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23099 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23100 fprintf (file
, "\t.extern %s\n", name
);
23102 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
23104 bool lr
= (info
->savres_strategy
23105 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23106 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23107 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23108 fprintf (file
, "\t.extern %s\n", name
);
23112 /* ELFv2 ABI r2 setup code and local entry point. This must follow
23113 immediately after the global entry point label. */
23114 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
23116 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
23118 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
23119 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
23121 fputs ("\t.localentry\t", file
);
23122 assemble_name (file
, name
);
23123 fputs (",.-", file
);
23124 assemble_name (file
, name
);
23125 fputs ("\n", file
);
23128 /* Output -mprofile-kernel code. This needs to be done here instead of
23129 in output_function_profile since it must go after the ELFv2 ABI
23130 local entry point. */
23131 if (TARGET_PROFILE_KERNEL
)
23133 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23134 gcc_assert (!TARGET_32BIT
);
23136 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23137 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
23139 /* In the ELFv2 ABI we have no compiler stack word. It must be
23140 the resposibility of _mcount to preserve the static chain
23141 register if required. */
23142 if (DEFAULT_ABI
!= ABI_ELFv2
23143 && cfun
->static_chain_decl
!= NULL
)
23145 asm_fprintf (file
, "\tstd %s,24(%s)\n",
23146 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23147 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23148 asm_fprintf (file
, "\tld %s,24(%s)\n",
23149 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23152 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23155 rs6000_pic_labelno
++;
23158 /* Non-zero if vmx regs are restored before the frame pop, zero if
23159 we restore after the pop when possible. */
23160 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
23162 /* Restoring cr is a two step process: loading a reg from the frame
23163 save, then moving the reg to cr. For ABI_V4 we must let the
23164 unwinder know that the stack location is no longer valid at or
23165 before the stack deallocation, but we can't emit a cfa_restore for
23166 cr at the stack deallocation like we do for other registers.
23167 The trouble is that it is possible for the move to cr to be
23168 scheduled after the stack deallocation. So say exactly where cr
23169 is located on each of the two insns. */
23172 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
23174 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
23175 rtx reg
= gen_rtx_REG (SImode
, regno
);
23176 rtx insn
= emit_move_insn (reg
, mem
);
23178 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
23180 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23181 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
23183 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
23184 RTX_FRAME_RELATED_P (insn
) = 1;
23189 /* Reload CR from REG. */
23192 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
23197 if (using_mfcr_multiple
)
23199 for (i
= 0; i
< 8; i
++)
23200 if (save_reg_p (CR0_REGNO
+ i
))
23202 gcc_assert (count
);
23205 if (using_mfcr_multiple
&& count
> 1)
23211 p
= rtvec_alloc (count
);
23214 for (i
= 0; i
< 8; i
++)
23215 if (save_reg_p (CR0_REGNO
+ i
))
23217 rtvec r
= rtvec_alloc (2);
23218 RTVEC_ELT (r
, 0) = reg
;
23219 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
23220 RTVEC_ELT (p
, ndx
) =
23221 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
23222 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
23225 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23226 gcc_assert (ndx
== count
);
23228 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23229 CR field separately. */
23230 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23232 for (i
= 0; i
< 8; i
++)
23233 if (save_reg_p (CR0_REGNO
+ i
))
23234 add_reg_note (insn
, REG_CFA_RESTORE
,
23235 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23237 RTX_FRAME_RELATED_P (insn
) = 1;
23241 for (i
= 0; i
< 8; i
++)
23242 if (save_reg_p (CR0_REGNO
+ i
))
23244 rtx insn
= emit_insn (gen_movsi_to_cr_one
23245 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23247 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23248 CR field separately, attached to the insn that in fact
23249 restores this particular CR field. */
23250 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23252 add_reg_note (insn
, REG_CFA_RESTORE
,
23253 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23255 RTX_FRAME_RELATED_P (insn
) = 1;
23259 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
23260 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
23261 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23263 rtx insn
= get_last_insn ();
23264 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23266 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
23267 RTX_FRAME_RELATED_P (insn
) = 1;
23271 /* Like cr, the move to lr instruction can be scheduled after the
23272 stack deallocation, but unlike cr, its stack frame save is still
23273 valid. So we only need to emit the cfa_restore on the correct
23277 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
23279 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
23280 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23282 emit_move_insn (reg
, mem
);
23286 restore_saved_lr (int regno
, bool exit_func
)
23288 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23289 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23290 rtx insn
= emit_move_insn (lr
, reg
);
23292 if (!exit_func
&& flag_shrink_wrap
)
23294 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23295 RTX_FRAME_RELATED_P (insn
) = 1;
23300 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
23302 if (DEFAULT_ABI
== ABI_ELFv2
)
23305 for (i
= 0; i
< 8; i
++)
23306 if (save_reg_p (CR0_REGNO
+ i
))
23308 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
23309 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
23313 else if (info
->cr_save_p
)
23314 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23315 gen_rtx_REG (SImode
, CR2_REGNO
),
23318 if (info
->lr_save_p
)
23319 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23320 gen_rtx_REG (Pmode
, LR_REGNO
),
23322 return cfa_restores
;
23325 /* Return true if OFFSET from stack pointer can be clobbered by signals.
23326 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
23327 below stack pointer not cloberred by signals. */
23330 offset_below_red_zone_p (HOST_WIDE_INT offset
)
23332 return offset
< (DEFAULT_ABI
== ABI_V4
23334 : TARGET_32BIT
? -220 : -288);
23337 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
23340 emit_cfa_restores (rtx cfa_restores
)
23342 rtx insn
= get_last_insn ();
23343 rtx
*loc
= ®_NOTES (insn
);
23346 loc
= &XEXP (*loc
, 1);
23347 *loc
= cfa_restores
;
23348 RTX_FRAME_RELATED_P (insn
) = 1;
23351 /* Emit function epilogue as insns. */
23354 rs6000_emit_epilogue (int sibcall
)
23356 rs6000_stack_t
*info
;
23357 int restoring_GPRs_inline
;
23358 int restoring_FPRs_inline
;
23359 int using_load_multiple
;
23360 int using_mtcr_multiple
;
23361 int use_backchain_to_restore_sp
;
23364 HOST_WIDE_INT frame_off
= 0;
23365 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
23366 rtx frame_reg_rtx
= sp_reg_rtx
;
23367 rtx cfa_restores
= NULL_RTX
;
23369 rtx cr_save_reg
= NULL_RTX
;
23370 enum machine_mode reg_mode
= Pmode
;
23371 int reg_size
= TARGET_32BIT
? 4 : 8;
23374 unsigned ptr_regno
;
23376 info
= rs6000_stack_info ();
23378 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
23380 reg_mode
= V2SImode
;
23384 strategy
= info
->savres_strategy
;
23385 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
23386 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
23387 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
23388 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
23389 || rs6000_cpu
== PROCESSOR_PPC603
23390 || rs6000_cpu
== PROCESSOR_PPC750
23392 /* Restore via the backchain when we have a large frame, since this
23393 is more efficient than an addis, addi pair. The second condition
23394 here will not trigger at the moment; We don't actually need a
23395 frame pointer for alloca, but the generic parts of the compiler
23396 give us one anyway. */
23397 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
23398 || (cfun
->calls_alloca
23399 && !frame_pointer_needed
));
23400 restore_lr
= (info
->lr_save_p
23401 && (restoring_FPRs_inline
23402 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
23403 && (restoring_GPRs_inline
23404 || info
->first_fp_reg_save
< 64));
23406 if (WORLD_SAVE_P (info
))
23410 const char *alloc_rname
;
23413 /* eh_rest_world_r10 will return to the location saved in the LR
23414 stack slot (which is not likely to be our caller.)
23415 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
23416 rest_world is similar, except any R10 parameter is ignored.
23417 The exception-handling stuff that was here in 2.95 is no
23418 longer necessary. */
23422 + 32 - info
->first_gp_reg_save
23423 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
23424 + 63 + 1 - info
->first_fp_reg_save
);
23426 strcpy (rname
, ((crtl
->calls_eh_return
) ?
23427 "*eh_rest_world_r10" : "*rest_world"));
23428 alloc_rname
= ggc_strdup (rname
);
23431 RTVEC_ELT (p
, j
++) = ret_rtx
;
23432 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
23433 gen_rtx_REG (Pmode
,
23436 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
23437 /* The instruction pattern requires a clobber here;
23438 it is shared with the restVEC helper. */
23440 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
23443 /* CR register traditionally saved as CR2. */
23444 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
23446 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
23447 if (flag_shrink_wrap
)
23449 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23450 gen_rtx_REG (Pmode
, LR_REGNO
),
23452 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23456 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23458 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
23460 = gen_frame_load (reg
,
23461 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
23462 if (flag_shrink_wrap
)
23463 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23465 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
23467 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
23469 = gen_frame_load (reg
,
23470 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
23471 if (flag_shrink_wrap
)
23472 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23474 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
23476 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23477 ? DFmode
: SFmode
),
23478 info
->first_fp_reg_save
+ i
);
23480 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
23481 if (flag_shrink_wrap
)
23482 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23485 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
23487 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
23489 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
23491 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
23493 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
23494 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23496 if (flag_shrink_wrap
)
23498 REG_NOTES (insn
) = cfa_restores
;
23499 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
23500 RTX_FRAME_RELATED_P (insn
) = 1;
23505 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
23507 frame_off
= info
->total_size
;
23509 /* Restore AltiVec registers if we must do so before adjusting the
23511 if (TARGET_ALTIVEC_ABI
23512 && info
->altivec_size
!= 0
23513 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23514 || (DEFAULT_ABI
!= ABI_V4
23515 && offset_below_red_zone_p (info
->altivec_save_offset
))))
23518 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
23520 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
23521 if (use_backchain_to_restore_sp
)
23523 int frame_regno
= 11;
23525 if ((strategy
& REST_INLINE_VRS
) == 0)
23527 /* Of r11 and r12, select the one not clobbered by an
23528 out-of-line restore function for the frame register. */
23529 frame_regno
= 11 + 12 - scratch_regno
;
23531 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
23532 emit_move_insn (frame_reg_rtx
,
23533 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23536 else if (frame_pointer_needed
)
23537 frame_reg_rtx
= hard_frame_pointer_rtx
;
23539 if ((strategy
& REST_INLINE_VRS
) == 0)
23541 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23543 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23544 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23546 if (end_save
+ frame_off
!= 0)
23548 rtx offset
= GEN_INT (end_save
+ frame_off
);
23550 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23553 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23555 ptr_off
= -end_save
;
23556 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23557 info
->altivec_save_offset
+ ptr_off
,
23558 0, V4SImode
, SAVRES_VR
);
23562 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23563 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23565 rtx addr
, areg
, mem
, reg
;
23567 areg
= gen_rtx_REG (Pmode
, 0);
23569 (areg
, GEN_INT (info
->altivec_save_offset
23571 + 16 * (i
- info
->first_altivec_reg_save
)));
23573 /* AltiVec addressing mode is [reg+reg]. */
23574 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
23575 mem
= gen_frame_mem (V4SImode
, addr
);
23577 reg
= gen_rtx_REG (V4SImode
, i
);
23578 emit_move_insn (reg
, mem
);
23582 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23583 if (((strategy
& REST_INLINE_VRS
) == 0
23584 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
23585 && (flag_shrink_wrap
23586 || (offset_below_red_zone_p
23587 (info
->altivec_save_offset
23588 + 16 * (i
- info
->first_altivec_reg_save
)))))
23590 rtx reg
= gen_rtx_REG (V4SImode
, i
);
23591 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23595 /* Restore VRSAVE if we must do so before adjusting the stack. */
23597 && TARGET_ALTIVEC_VRSAVE
23598 && info
->vrsave_mask
!= 0
23599 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23600 || (DEFAULT_ABI
!= ABI_V4
23601 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
23605 if (frame_reg_rtx
== sp_reg_rtx
)
23607 if (use_backchain_to_restore_sp
)
23609 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23610 emit_move_insn (frame_reg_rtx
,
23611 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23614 else if (frame_pointer_needed
)
23615 frame_reg_rtx
= hard_frame_pointer_rtx
;
23618 reg
= gen_rtx_REG (SImode
, 12);
23619 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23620 info
->vrsave_save_offset
+ frame_off
));
23622 emit_insn (generate_set_vrsave (reg
, info
, 1));
23626 /* If we have a large stack frame, restore the old stack pointer
23627 using the backchain. */
23628 if (use_backchain_to_restore_sp
)
23630 if (frame_reg_rtx
== sp_reg_rtx
)
23632 /* Under V.4, don't reset the stack pointer until after we're done
23633 loading the saved registers. */
23634 if (DEFAULT_ABI
== ABI_V4
)
23635 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23637 insn
= emit_move_insn (frame_reg_rtx
,
23638 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23641 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23642 && DEFAULT_ABI
== ABI_V4
)
23643 /* frame_reg_rtx has been set up by the altivec restore. */
23647 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
23648 frame_reg_rtx
= sp_reg_rtx
;
23651 /* If we have a frame pointer, we can restore the old stack pointer
23653 else if (frame_pointer_needed
)
23655 frame_reg_rtx
= sp_reg_rtx
;
23656 if (DEFAULT_ABI
== ABI_V4
)
23657 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23658 /* Prevent reordering memory accesses against stack pointer restore. */
23659 else if (cfun
->calls_alloca
23660 || offset_below_red_zone_p (-info
->total_size
))
23661 rs6000_emit_stack_tie (frame_reg_rtx
, true);
23663 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
23664 GEN_INT (info
->total_size
)));
23667 else if (info
->push_p
23668 && DEFAULT_ABI
!= ABI_V4
23669 && !crtl
->calls_eh_return
)
23671 /* Prevent reordering memory accesses against stack pointer restore. */
23672 if (cfun
->calls_alloca
23673 || offset_below_red_zone_p (-info
->total_size
))
23674 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23675 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
23676 GEN_INT (info
->total_size
)));
23679 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
23683 REG_NOTES (insn
) = cfa_restores
;
23684 cfa_restores
= NULL_RTX
;
23686 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
23687 RTX_FRAME_RELATED_P (insn
) = 1;
23690 /* Restore AltiVec registers if we have not done so already. */
23691 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23692 && TARGET_ALTIVEC_ABI
23693 && info
->altivec_size
!= 0
23694 && (DEFAULT_ABI
== ABI_V4
23695 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
23699 if ((strategy
& REST_INLINE_VRS
) == 0)
23701 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23703 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23704 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
23705 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23707 if (end_save
+ frame_off
!= 0)
23709 rtx offset
= GEN_INT (end_save
+ frame_off
);
23711 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23714 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23716 ptr_off
= -end_save
;
23717 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23718 info
->altivec_save_offset
+ ptr_off
,
23719 0, V4SImode
, SAVRES_VR
);
23720 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
23722 /* Frame reg was clobbered by out-of-line save. Restore it
23723 from ptr_reg, and if we are calling out-of-line gpr or
23724 fpr restore set up the correct pointer and offset. */
23725 unsigned newptr_regno
= 1;
23726 if (!restoring_GPRs_inline
)
23728 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
23729 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23730 newptr_regno
= ptr_regno_for_savres (sel
);
23731 end_save
= info
->gp_save_offset
+ info
->gp_size
;
23733 else if (!restoring_FPRs_inline
)
23735 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
23736 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23737 newptr_regno
= ptr_regno_for_savres (sel
);
23738 end_save
= info
->gp_save_offset
+ info
->gp_size
;
23741 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
23742 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
23744 if (end_save
+ ptr_off
!= 0)
23746 rtx offset
= GEN_INT (end_save
+ ptr_off
);
23748 frame_off
= -end_save
;
23749 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
23753 frame_off
= ptr_off
;
23754 emit_move_insn (frame_reg_rtx
, ptr_reg
);
23760 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23761 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23763 rtx addr
, areg
, mem
, reg
;
23765 areg
= gen_rtx_REG (Pmode
, 0);
23767 (areg
, GEN_INT (info
->altivec_save_offset
23769 + 16 * (i
- info
->first_altivec_reg_save
)));
23771 /* AltiVec addressing mode is [reg+reg]. */
23772 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
23773 mem
= gen_frame_mem (V4SImode
, addr
);
23775 reg
= gen_rtx_REG (V4SImode
, i
);
23776 emit_move_insn (reg
, mem
);
23780 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23781 if (((strategy
& REST_INLINE_VRS
) == 0
23782 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
23783 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23785 rtx reg
= gen_rtx_REG (V4SImode
, i
);
23786 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23790 /* Restore VRSAVE if we have not done so already. */
23791 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23793 && TARGET_ALTIVEC_VRSAVE
23794 && info
->vrsave_mask
!= 0
23795 && (DEFAULT_ABI
== ABI_V4
23796 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
23800 reg
= gen_rtx_REG (SImode
, 12);
23801 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23802 info
->vrsave_save_offset
+ frame_off
));
23804 emit_insn (generate_set_vrsave (reg
, info
, 1));
23807 /* If we exit by an out-of-line restore function on ABI_V4 then that
23808 function will deallocate the stack, so we don't need to worry
23809 about the unwinder restoring cr from an invalid stack frame
23811 exit_func
= (!restoring_FPRs_inline
23812 || (!restoring_GPRs_inline
23813 && info
->first_fp_reg_save
== 64));
23815 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
23816 *separate* slots if the routine calls __builtin_eh_return, so
23817 that they can be independently restored by the unwinder. */
23818 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
23820 int i
, cr_off
= info
->ehcr_offset
;
23822 for (i
= 0; i
< 8; i
++)
23823 if (!call_used_regs
[CR0_REGNO
+ i
])
23825 rtx reg
= gen_rtx_REG (SImode
, 0);
23826 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23827 cr_off
+ frame_off
));
23829 insn
= emit_insn (gen_movsi_to_cr_one
23830 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23832 if (!exit_func
&& flag_shrink_wrap
)
23834 add_reg_note (insn
, REG_CFA_RESTORE
,
23835 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23837 RTX_FRAME_RELATED_P (insn
) = 1;
23840 cr_off
+= reg_size
;
23844 /* Get the old lr if we saved it. If we are restoring registers
23845 out-of-line, then the out-of-line routines can do this for us. */
23846 if (restore_lr
&& restoring_GPRs_inline
)
23847 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
23849 /* Get the old cr if we saved it. */
23850 if (info
->cr_save_p
)
23852 unsigned cr_save_regno
= 12;
23854 if (!restoring_GPRs_inline
)
23856 /* Ensure we don't use the register used by the out-of-line
23857 gpr register restore below. */
23858 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
23859 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23860 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
23862 if (gpr_ptr_regno
== 12)
23863 cr_save_regno
= 11;
23864 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
23866 else if (REGNO (frame_reg_rtx
) == 12)
23867 cr_save_regno
= 11;
23869 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
23870 info
->cr_save_offset
+ frame_off
,
23874 /* Set LR here to try to overlap restores below. */
23875 if (restore_lr
&& restoring_GPRs_inline
)
23876 restore_saved_lr (0, exit_func
);
23878 /* Load exception handler data registers, if needed. */
23879 if (crtl
->calls_eh_return
)
23881 unsigned int i
, regno
;
23885 rtx reg
= gen_rtx_REG (reg_mode
, 2);
23886 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23887 frame_off
+ RS6000_TOC_SAVE_SLOT
));
23894 regno
= EH_RETURN_DATA_REGNO (i
);
23895 if (regno
== INVALID_REGNUM
)
23898 /* Note: possible use of r0 here to address SPE regs. */
23899 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
23900 info
->ehrd_offset
+ frame_off
23901 + reg_size
* (int) i
);
23903 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
23907 /* Restore GPRs. This is done as a PARALLEL if we are using
23908 the load-multiple instructions. */
23910 && info
->spe_64bit_regs_used
23911 && info
->first_gp_reg_save
!= 32)
23913 /* Determine whether we can address all of the registers that need
23914 to be saved with an offset from frame_reg_rtx that fits in
23915 the small const field for SPE memory instructions. */
23916 int spe_regs_addressable
23917 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
23918 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
23919 && restoring_GPRs_inline
);
23921 if (!spe_regs_addressable
)
23923 int ool_adjust
= 0;
23924 rtx old_frame_reg_rtx
= frame_reg_rtx
;
23925 /* Make r11 point to the start of the SPE save area. We worried about
23926 not clobbering it when we were saving registers in the prologue.
23927 There's no need to worry here because the static chain is passed
23928 anew to every function. */
23930 if (!restoring_GPRs_inline
)
23931 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
23932 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23933 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
23934 GEN_INT (info
->spe_gp_save_offset
23937 /* Keep the invariant that frame_reg_rtx + frame_off points
23938 at the top of the stack frame. */
23939 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
23942 if (restoring_GPRs_inline
)
23944 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
23946 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23947 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23949 rtx offset
, addr
, mem
, reg
;
23951 /* We're doing all this to ensure that the immediate offset
23952 fits into the immediate field of 'evldd'. */
23953 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
23955 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
23956 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
23957 mem
= gen_rtx_MEM (V2SImode
, addr
);
23958 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
23960 emit_move_insn (reg
, mem
);
23964 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
23965 info
->spe_gp_save_offset
+ frame_off
,
23966 info
->lr_save_offset
+ frame_off
,
23968 SAVRES_GPR
| SAVRES_LR
);
23970 else if (!restoring_GPRs_inline
)
23972 /* We are jumping to an out-of-line function. */
23974 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23975 bool can_use_exit
= end_save
== 0;
23976 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
23979 /* Emit stack reset code if we need it. */
23980 ptr_regno
= ptr_regno_for_savres (sel
);
23981 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23983 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
23984 else if (end_save
+ frame_off
!= 0)
23985 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
23986 GEN_INT (end_save
+ frame_off
)));
23987 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
23988 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23989 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23990 frame_off
= -end_save
;
23992 if (can_use_exit
&& info
->cr_save_p
)
23993 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
23995 ptr_off
= -end_save
;
23996 rs6000_emit_savres_rtx (info
, ptr_reg
,
23997 info
->gp_save_offset
+ ptr_off
,
23998 info
->lr_save_offset
+ ptr_off
,
24001 else if (using_load_multiple
)
24004 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
24005 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24007 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24009 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
24010 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24014 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
24015 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
24016 emit_insn (gen_frame_load
24017 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
24019 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
24022 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24024 /* If the frame pointer was used then we can't delay emitting
24025 a REG_CFA_DEF_CFA note. This must happen on the insn that
24026 restores the frame pointer, r31. We may have already emitted
24027 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
24028 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
24029 be harmless if emitted. */
24030 if (frame_pointer_needed
)
24032 insn
= get_last_insn ();
24033 add_reg_note (insn
, REG_CFA_DEF_CFA
,
24034 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
24035 RTX_FRAME_RELATED_P (insn
) = 1;
24038 /* Set up cfa_restores. We always need these when
24039 shrink-wrapping. If not shrink-wrapping then we only need
24040 the cfa_restore when the stack location is no longer valid.
24041 The cfa_restores must be emitted on or before the insn that
24042 invalidates the stack, and of course must not be emitted
24043 before the insn that actually does the restore. The latter
24044 is why it is a bad idea to emit the cfa_restores as a group
24045 on the last instruction here that actually does a restore:
24046 That insn may be reordered with respect to others doing
24048 if (flag_shrink_wrap
24049 && !restoring_GPRs_inline
24050 && info
->first_fp_reg_save
== 64)
24051 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24053 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
24054 if (!restoring_GPRs_inline
24055 || using_load_multiple
24056 || rs6000_reg_live_or_pic_offset_p (i
))
24058 rtx reg
= gen_rtx_REG (reg_mode
, i
);
24060 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24064 if (!restoring_GPRs_inline
24065 && info
->first_fp_reg_save
== 64)
24067 /* We are jumping to an out-of-line function. */
24069 emit_cfa_restores (cfa_restores
);
24073 if (restore_lr
&& !restoring_GPRs_inline
)
24075 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24076 restore_saved_lr (0, exit_func
);
24079 /* Restore fpr's if we need to do it without calling a function. */
24080 if (restoring_FPRs_inline
)
24081 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24082 if (save_reg_p (info
->first_fp_reg_save
+ i
))
24084 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24085 ? DFmode
: SFmode
),
24086 info
->first_fp_reg_save
+ i
);
24087 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24088 info
->fp_save_offset
+ frame_off
+ 8 * i
));
24089 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24090 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24093 /* If we saved cr, restore it here. Just those that were used. */
24094 if (info
->cr_save_p
)
24095 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
24097 /* If this is V.4, unwind the stack pointer after all of the loads
24098 have been done, or set up r11 if we are restoring fp out of line. */
24100 if (!restoring_FPRs_inline
)
24102 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24103 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24104 ptr_regno
= ptr_regno_for_savres (sel
);
24107 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24108 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24111 if (insn
&& restoring_FPRs_inline
)
24115 REG_NOTES (insn
) = cfa_restores
;
24116 cfa_restores
= NULL_RTX
;
24118 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24119 RTX_FRAME_RELATED_P (insn
) = 1;
24122 if (crtl
->calls_eh_return
)
24124 rtx sa
= EH_RETURN_STACKADJ_RTX
;
24125 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
24131 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24132 if (! restoring_FPRs_inline
)
24134 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
24135 RTVEC_ELT (p
, 0) = ret_rtx
;
24141 /* We can't hang the cfa_restores off a simple return,
24142 since the shrink-wrap code sometimes uses an existing
24143 return. This means there might be a path from
24144 pre-prologue code to this return, and dwarf2cfi code
24145 wants the eh_frame unwinder state to be the same on
24146 all paths to any point. So we need to emit the
24147 cfa_restores before the return. For -m64 we really
24148 don't need epilogue cfa_restores at all, except for
24149 this irritating dwarf2cfi with shrink-wrap
24150 requirement; The stack red-zone means eh_frame info
24151 from the prologue telling the unwinder to restore
24152 from the stack is perfectly good right to the end of
24154 emit_insn (gen_blockage ());
24155 emit_cfa_restores (cfa_restores
);
24156 cfa_restores
= NULL_RTX
;
24158 p
= rtvec_alloc (2);
24159 RTVEC_ELT (p
, 0) = simple_return_rtx
;
24162 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
24163 ? gen_rtx_USE (VOIDmode
,
24164 gen_rtx_REG (Pmode
, LR_REGNO
))
24165 : gen_rtx_CLOBBER (VOIDmode
,
24166 gen_rtx_REG (Pmode
, LR_REGNO
)));
24168 /* If we have to restore more than two FP registers, branch to the
24169 restore function. It will return to our caller. */
24170 if (! restoring_FPRs_inline
)
24176 if (flag_shrink_wrap
)
24177 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24179 sym
= rs6000_savres_routine_sym (info
,
24180 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
24181 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
24182 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
24183 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
24185 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24187 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
24189 RTVEC_ELT (p
, i
+ 4)
24190 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24191 if (flag_shrink_wrap
)
24192 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
24197 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24203 /* Ensure the cfa_restores are hung off an insn that won't
24204 be reordered above other restores. */
24205 emit_insn (gen_blockage ());
24207 emit_cfa_restores (cfa_restores
);
24211 /* Write function epilogue. */
24214 rs6000_output_function_epilogue (FILE *file
,
24215 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
24218 macho_branch_islands ();
24219 /* Mach-O doesn't support labels at the end of objects, so if
24220 it looks like we might want one, insert a NOP. */
24222 rtx insn
= get_last_insn ();
24223 rtx deleted_debug_label
= NULL_RTX
;
24226 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
24228 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
24229 notes only, instead set their CODE_LABEL_NUMBER to -1,
24230 otherwise there would be code generation differences
24231 in between -g and -g0. */
24232 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24233 deleted_debug_label
= insn
;
24234 insn
= PREV_INSN (insn
);
24239 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
24240 fputs ("\tnop\n", file
);
24241 else if (deleted_debug_label
)
24242 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
24243 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24244 CODE_LABEL_NUMBER (insn
) = -1;
24248 /* Output a traceback table here. See /usr/include/sys/debug.h for info
24251 We don't output a traceback table if -finhibit-size-directive was
24252 used. The documentation for -finhibit-size-directive reads
24253 ``don't output a @code{.size} assembler directive, or anything
24254 else that would cause trouble if the function is split in the
24255 middle, and the two halves are placed at locations far apart in
24256 memory.'' The traceback table has this property, since it
24257 includes the offset from the start of the function to the
24258 traceback table itself.
24260 System V.4 Powerpc's (and the embedded ABI derived from it) use a
24261 different traceback table. */
24262 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24263 && ! flag_inhibit_size_directive
24264 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
24266 const char *fname
= NULL
;
24267 const char *language_string
= lang_hooks
.name
;
24268 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
24270 int optional_tbtab
;
24271 rs6000_stack_t
*info
= rs6000_stack_info ();
24273 if (rs6000_traceback
== traceback_full
)
24274 optional_tbtab
= 1;
24275 else if (rs6000_traceback
== traceback_part
)
24276 optional_tbtab
= 0;
24278 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
24280 if (optional_tbtab
)
24282 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
24283 while (*fname
== '.') /* V.4 encodes . in the name */
24286 /* Need label immediately before tbtab, so we can compute
24287 its offset from the function start. */
24288 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24289 ASM_OUTPUT_LABEL (file
, fname
);
24292 /* The .tbtab pseudo-op can only be used for the first eight
24293 expressions, since it can't handle the possibly variable
24294 length fields that follow. However, if you omit the optional
24295 fields, the assembler outputs zeros for all optional fields
24296 anyways, giving each variable length field is minimum length
24297 (as defined in sys/debug.h). Thus we can not use the .tbtab
24298 pseudo-op at all. */
24300 /* An all-zero word flags the start of the tbtab, for debuggers
24301 that have to find it by searching forward from the entry
24302 point or from the current pc. */
24303 fputs ("\t.long 0\n", file
);
24305 /* Tbtab format type. Use format type 0. */
24306 fputs ("\t.byte 0,", file
);
24308 /* Language type. Unfortunately, there does not seem to be any
24309 official way to discover the language being compiled, so we
24310 use language_string.
24311 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
24312 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
24313 a number, so for now use 9. LTO and Go aren't assigned numbers
24314 either, so for now use 0. */
24315 if (! strcmp (language_string
, "GNU C")
24316 || ! strcmp (language_string
, "GNU GIMPLE")
24317 || ! strcmp (language_string
, "GNU Go"))
24319 else if (! strcmp (language_string
, "GNU F77")
24320 || ! strcmp (language_string
, "GNU Fortran"))
24322 else if (! strcmp (language_string
, "GNU Pascal"))
24324 else if (! strcmp (language_string
, "GNU Ada"))
24326 else if (! strcmp (language_string
, "GNU C++")
24327 || ! strcmp (language_string
, "GNU Objective-C++"))
24329 else if (! strcmp (language_string
, "GNU Java"))
24331 else if (! strcmp (language_string
, "GNU Objective-C"))
24334 gcc_unreachable ();
24335 fprintf (file
, "%d,", i
);
24337 /* 8 single bit fields: global linkage (not set for C extern linkage,
24338 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
24339 from start of procedure stored in tbtab, internal function, function
24340 has controlled storage, function has no toc, function uses fp,
24341 function logs/aborts fp operations. */
24342 /* Assume that fp operations are used if any fp reg must be saved. */
24343 fprintf (file
, "%d,",
24344 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
24346 /* 6 bitfields: function is interrupt handler, name present in
24347 proc table, function calls alloca, on condition directives
24348 (controls stack walks, 3 bits), saves condition reg, saves
24350 /* The `function calls alloca' bit seems to be set whenever reg 31 is
24351 set up as a frame pointer, even when there is no alloca call. */
24352 fprintf (file
, "%d,",
24353 ((optional_tbtab
<< 6)
24354 | ((optional_tbtab
& frame_pointer_needed
) << 5)
24355 | (info
->cr_save_p
<< 1)
24356 | (info
->lr_save_p
)));
24358 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
24360 fprintf (file
, "%d,",
24361 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
24363 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
24364 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
24366 if (optional_tbtab
)
24368 /* Compute the parameter info from the function decl argument
24371 int next_parm_info_bit
= 31;
24373 for (decl
= DECL_ARGUMENTS (current_function_decl
);
24374 decl
; decl
= DECL_CHAIN (decl
))
24376 rtx parameter
= DECL_INCOMING_RTL (decl
);
24377 enum machine_mode mode
= GET_MODE (parameter
);
24379 if (GET_CODE (parameter
) == REG
)
24381 if (SCALAR_FLOAT_MODE_P (mode
))
24402 gcc_unreachable ();
24405 /* If only one bit will fit, don't or in this entry. */
24406 if (next_parm_info_bit
> 0)
24407 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
24408 next_parm_info_bit
-= 2;
24412 fixed_parms
+= ((GET_MODE_SIZE (mode
)
24413 + (UNITS_PER_WORD
- 1))
24415 next_parm_info_bit
-= 1;
24421 /* Number of fixed point parameters. */
24422 /* This is actually the number of words of fixed point parameters; thus
24423 an 8 byte struct counts as 2; and thus the maximum value is 8. */
24424 fprintf (file
, "%d,", fixed_parms
);
24426 /* 2 bitfields: number of floating point parameters (7 bits), parameters
24428 /* This is actually the number of fp registers that hold parameters;
24429 and thus the maximum value is 13. */
24430 /* Set parameters on stack bit if parameters are not in their original
24431 registers, regardless of whether they are on the stack? Xlc
24432 seems to set the bit when not optimizing. */
24433 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
24435 if (! optional_tbtab
)
24438 /* Optional fields follow. Some are variable length. */
24440 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
24441 11 double float. */
24442 /* There is an entry for each parameter in a register, in the order that
24443 they occur in the parameter list. Any intervening arguments on the
24444 stack are ignored. If the list overflows a long (max possible length
24445 34 bits) then completely leave off all elements that don't fit. */
24446 /* Only emit this long if there was at least one parameter. */
24447 if (fixed_parms
|| float_parms
)
24448 fprintf (file
, "\t.long %d\n", parm_info
);
24450 /* Offset from start of code to tb table. */
24451 fputs ("\t.long ", file
);
24452 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24453 RS6000_OUTPUT_BASENAME (file
, fname
);
24455 rs6000_output_function_entry (file
, fname
);
24458 /* Interrupt handler mask. */
24459 /* Omit this long, since we never set the interrupt handler bit
24462 /* Number of CTL (controlled storage) anchors. */
24463 /* Omit this long, since the has_ctl bit is never set above. */
24465 /* Displacement into stack of each CTL anchor. */
24466 /* Omit this list of longs, because there are no CTL anchors. */
24468 /* Length of function name. */
24471 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
24473 /* Function name. */
24474 assemble_string (fname
, strlen (fname
));
24476 /* Register for alloca automatic storage; this is always reg 31.
24477 Only emit this if the alloca bit was set above. */
24478 if (frame_pointer_needed
)
24479 fputs ("\t.byte 31\n", file
);
24481 fputs ("\t.align 2\n", file
);
24485 /* A C compound statement that outputs the assembler code for a thunk
24486 function, used to implement C++ virtual function calls with
24487 multiple inheritance. The thunk acts as a wrapper around a virtual
24488 function, adjusting the implicit object parameter before handing
24489 control off to the real function.
24491 First, emit code to add the integer DELTA to the location that
24492 contains the incoming first argument. Assume that this argument
24493 contains a pointer, and is the one used to pass the `this' pointer
24494 in C++. This is the incoming argument *before* the function
24495 prologue, e.g. `%o0' on a sparc. The addition must preserve the
24496 values of all other incoming arguments.
24498 After the addition, emit code to jump to FUNCTION, which is a
24499 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
24500 not touch the return address. Hence returning from FUNCTION will
24501 return to whoever called the current `thunk'.
24503 The effect must be as if FUNCTION had been called directly with the
24504 adjusted first argument. This macro is responsible for emitting
24505 all of the code for a thunk function; output_function_prologue()
24506 and output_function_epilogue() are not invoked.
24508 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
24509 been extracted from it.) It might possibly be useful on some
24510 targets, but probably not.
24512 If you do not define this macro, the target-independent code in the
24513 C++ frontend will generate a less efficient heavyweight thunk that
24514 calls FUNCTION instead of jumping to it. The generic approach does
24515 not support varargs. */
24518 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
24519 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
24522 rtx this_rtx
, insn
, funexp
;
24524 reload_completed
= 1;
24525 epilogue_completed
= 1;
24527 /* Mark the end of the (empty) prologue. */
24528 emit_note (NOTE_INSN_PROLOGUE_END
);
24530 /* Find the "this" pointer. If the function returns a structure,
24531 the structure return pointer is in r3. */
24532 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
24533 this_rtx
= gen_rtx_REG (Pmode
, 4);
24535 this_rtx
= gen_rtx_REG (Pmode
, 3);
24537 /* Apply the constant offset, if required. */
24539 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
24541 /* Apply the offset from the vtable, if required. */
24544 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
24545 rtx tmp
= gen_rtx_REG (Pmode
, 12);
24547 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
24548 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
24550 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
24551 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
24555 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
24557 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
24559 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
24562 /* Generate a tail call to the target function. */
24563 if (!TREE_USED (function
))
24565 assemble_external (function
);
24566 TREE_USED (function
) = 1;
24568 funexp
= XEXP (DECL_RTL (function
), 0);
24569 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
24572 if (MACHOPIC_INDIRECT
)
24573 funexp
= machopic_indirect_call_target (funexp
);
24576 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
24577 generate sibcall RTL explicitly. */
24578 insn
= emit_call_insn (
24579 gen_rtx_PARALLEL (VOIDmode
,
24581 gen_rtx_CALL (VOIDmode
,
24582 funexp
, const0_rtx
),
24583 gen_rtx_USE (VOIDmode
, const0_rtx
),
24584 gen_rtx_USE (VOIDmode
,
24585 gen_rtx_REG (SImode
,
24587 simple_return_rtx
)));
24588 SIBLING_CALL_P (insn
) = 1;
24591 /* Ensure we have a global entry point for the thunk. ??? We could
24592 avoid that if the target routine doesn't need a global entry point,
24593 but we do not know whether this is the case at this point. */
24594 if (DEFAULT_ABI
== ABI_ELFv2
)
24595 cfun
->machine
->r2_setup_needed
= true;
24597 /* Run just enough of rest_of_compilation to get the insns emitted.
24598 There's not really enough bulk here to make other passes such as
24599 instruction scheduling worth while. Note that use_thunk calls
24600 assemble_start_function and assemble_end_function. */
24601 insn
= get_insns ();
24602 shorten_branches (insn
);
24603 final_start_function (insn
, file
, 1);
24604 final (insn
, file
, 1);
24605 final_end_function ();
24607 reload_completed
= 0;
24608 epilogue_completed
= 0;
24611 /* A quick summary of the various types of 'constant-pool tables'
24614 Target Flags Name One table per
24615 AIX (none) AIX TOC object file
24616 AIX -mfull-toc AIX TOC object file
24617 AIX -mminimal-toc AIX minimal TOC translation unit
24618 SVR4/EABI (none) SVR4 SDATA object file
24619 SVR4/EABI -fpic SVR4 pic object file
24620 SVR4/EABI -fPIC SVR4 PIC translation unit
24621 SVR4/EABI -mrelocatable EABI TOC function
24622 SVR4/EABI -maix AIX TOC object file
24623 SVR4/EABI -maix -mminimal-toc
24624 AIX minimal TOC translation unit
24626 Name Reg. Set by entries contains:
24627 made by addrs? fp? sum?
24629 AIX TOC 2 crt0 as Y option option
24630 AIX minimal TOC 30 prolog gcc Y Y option
24631 SVR4 SDATA 13 crt0 gcc N Y N
24632 SVR4 pic 30 prolog ld Y not yet N
24633 SVR4 PIC 30 prolog gcc Y option option
24634 EABI TOC 30 prolog gcc Y option option
24638 /* Hash functions for the hash table. */
24641 rs6000_hash_constant (rtx k
)
24643 enum rtx_code code
= GET_CODE (k
);
24644 enum machine_mode mode
= GET_MODE (k
);
24645 unsigned result
= (code
<< 3) ^ mode
;
24646 const char *format
;
24649 format
= GET_RTX_FORMAT (code
);
24650 flen
= strlen (format
);
24656 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
24659 if (mode
!= VOIDmode
)
24660 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
24672 for (; fidx
< flen
; fidx
++)
24673 switch (format
[fidx
])
24678 const char *str
= XSTR (k
, fidx
);
24679 len
= strlen (str
);
24680 result
= result
* 613 + len
;
24681 for (i
= 0; i
< len
; i
++)
24682 result
= result
* 613 + (unsigned) str
[i
];
24687 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
24691 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
24694 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
24695 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
24699 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
24700 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
24707 gcc_unreachable ();
24714 toc_hash_function (const void *hash_entry
)
24716 const struct toc_hash_struct
*thc
=
24717 (const struct toc_hash_struct
*) hash_entry
;
24718 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
24721 /* Compare H1 and H2 for equivalence. */
24724 toc_hash_eq (const void *h1
, const void *h2
)
24726 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
24727 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
24729 if (((const struct toc_hash_struct
*) h1
)->key_mode
24730 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
24733 return rtx_equal_p (r1
, r2
);
24736 /* These are the names given by the C++ front-end to vtables, and
24737 vtable-like objects. Ideally, this logic should not be here;
24738 instead, there should be some programmatic way of inquiring as
24739 to whether or not an object is a vtable. */
24741 #define VTABLE_NAME_P(NAME) \
24742 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
24743 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
24744 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
24745 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
24746 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
24748 #ifdef NO_DOLLAR_IN_LABEL
24749 /* Return a GGC-allocated character string translating dollar signs in
24750 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
24753 rs6000_xcoff_strip_dollar (const char *name
)
24759 q
= (const char *) strchr (name
, '$');
24761 if (q
== 0 || q
== name
)
24764 len
= strlen (name
);
24765 strip
= XALLOCAVEC (char, len
+ 1);
24766 strcpy (strip
, name
);
24767 p
= strip
+ (q
- name
);
24771 p
= strchr (p
+ 1, '$');
24774 return ggc_alloc_string (strip
, len
);
24779 rs6000_output_symbol_ref (FILE *file
, rtx x
)
24781 /* Currently C++ toc references to vtables can be emitted before it
24782 is decided whether the vtable is public or private. If this is
24783 the case, then the linker will eventually complain that there is
24784 a reference to an unknown section. Thus, for vtables only,
24785 we emit the TOC reference to reference the symbol and not the
24787 const char *name
= XSTR (x
, 0);
24789 if (VTABLE_NAME_P (name
))
24791 RS6000_OUTPUT_BASENAME (file
, name
);
24794 assemble_name (file
, name
);
24797 /* Output a TOC entry. We derive the entry name from what is being
24801 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
24804 const char *name
= buf
;
24806 HOST_WIDE_INT offset
= 0;
24808 gcc_assert (!TARGET_NO_TOC
);
24810 /* When the linker won't eliminate them, don't output duplicate
24811 TOC entries (this happens on AIX if there is any kind of TOC,
24812 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
24814 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
24816 struct toc_hash_struct
*h
;
24819 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
24820 time because GGC is not initialized at that point. */
24821 if (toc_hash_table
== NULL
)
24822 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
24823 toc_hash_eq
, NULL
);
24825 h
= ggc_alloc_toc_hash_struct ();
24827 h
->key_mode
= mode
;
24828 h
->labelno
= labelno
;
24830 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
24831 if (*found
== NULL
)
24833 else /* This is indeed a duplicate.
24834 Set this label equal to that label. */
24836 fputs ("\t.set ", file
);
24837 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
24838 fprintf (file
, "%d,", labelno
);
24839 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
24840 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
24844 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
24845 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
24846 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
24848 fputs ("\t.set ", file
);
24849 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
24850 fprintf (file
, "%d,", labelno
);
24851 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
24852 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
24860 /* If we're going to put a double constant in the TOC, make sure it's
24861 aligned properly when strict alignment is on. */
24862 if (GET_CODE (x
) == CONST_DOUBLE
24863 && STRICT_ALIGNMENT
24864 && GET_MODE_BITSIZE (mode
) >= 64
24865 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
24866 ASM_OUTPUT_ALIGN (file
, 3);
24869 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
24871 /* Handle FP constants specially. Note that if we have a minimal
24872 TOC, things we put here aren't actually in the TOC, so we can allow
24874 if (GET_CODE (x
) == CONST_DOUBLE
&&
24875 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
24877 REAL_VALUE_TYPE rv
;
24880 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24881 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24882 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
24884 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
24888 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24889 fputs (DOUBLE_INT_ASM_OP
, file
);
24891 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
24892 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24893 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24894 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
24895 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
24896 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
24897 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
24898 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
24903 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24904 fputs ("\t.long ", file
);
24906 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
24907 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24908 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24909 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
24910 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24911 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24915 else if (GET_CODE (x
) == CONST_DOUBLE
&&
24916 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
24918 REAL_VALUE_TYPE rv
;
24921 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24923 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24924 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
24926 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
24930 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24931 fputs (DOUBLE_INT_ASM_OP
, file
);
24933 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
24934 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24935 fprintf (file
, "0x%lx%08lx\n",
24936 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
24937 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
24942 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24943 fputs ("\t.long ", file
);
24945 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
24946 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24947 fprintf (file
, "0x%lx,0x%lx\n",
24948 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24952 else if (GET_CODE (x
) == CONST_DOUBLE
&&
24953 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
24955 REAL_VALUE_TYPE rv
;
24958 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24959 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24960 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
24962 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
24966 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24967 fputs (DOUBLE_INT_ASM_OP
, file
);
24969 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
24970 if (WORDS_BIG_ENDIAN
)
24971 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
24973 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
24978 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24979 fputs ("\t.long ", file
);
24981 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
24982 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
24986 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
24988 unsigned HOST_WIDE_INT low
;
24989 HOST_WIDE_INT high
;
24991 low
= INTVAL (x
) & 0xffffffff;
24992 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
24994 /* TOC entries are always Pmode-sized, so when big-endian
24995 smaller integer constants in the TOC need to be padded.
24996 (This is still a win over putting the constants in
24997 a separate constant pool, because then we'd have
24998 to have both a TOC entry _and_ the actual constant.)
25000 For a 32-bit target, CONST_INT values are loaded and shifted
25001 entirely within `low' and can be stored in one TOC entry. */
25003 /* It would be easy to make this work, but it doesn't now. */
25004 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
25006 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
25009 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
25010 high
= (HOST_WIDE_INT
) low
>> 32;
25016 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25017 fputs (DOUBLE_INT_ASM_OP
, file
);
25019 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25020 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25021 fprintf (file
, "0x%lx%08lx\n",
25022 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25027 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
25029 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25030 fputs ("\t.long ", file
);
25032 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
25033 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25034 fprintf (file
, "0x%lx,0x%lx\n",
25035 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
25039 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25040 fputs ("\t.long ", file
);
25042 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
25043 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
25049 if (GET_CODE (x
) == CONST
)
25051 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
25052 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
25054 base
= XEXP (XEXP (x
, 0), 0);
25055 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
25058 switch (GET_CODE (base
))
25061 name
= XSTR (base
, 0);
25065 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
25066 CODE_LABEL_NUMBER (XEXP (base
, 0)));
25070 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
25074 gcc_unreachable ();
25077 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25078 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
25081 fputs ("\t.tc ", file
);
25082 RS6000_OUTPUT_BASENAME (file
, name
);
25085 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
25087 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
25089 /* Mark large TOC symbols on AIX with [TE] so they are mapped
25090 after other TOC symbols, reducing overflow of small TOC access
25091 to [TC] symbols. */
25092 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
25093 ? "[TE]," : "[TC],", file
);
25096 /* Currently C++ toc references to vtables can be emitted before it
25097 is decided whether the vtable is public or private. If this is
25098 the case, then the linker will eventually complain that there is
25099 a TOC reference to an unknown section. Thus, for vtables only,
25100 we emit the TOC reference to reference the symbol and not the
25102 if (VTABLE_NAME_P (name
))
25104 RS6000_OUTPUT_BASENAME (file
, name
);
25106 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
25107 else if (offset
> 0)
25108 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
25111 output_addr_const (file
, x
);
25114 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
25115 && SYMBOL_REF_TLS_MODEL (base
) != 0)
25117 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
25118 fputs ("@le", file
);
25119 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
25120 fputs ("@ie", file
);
25121 /* Use global-dynamic for local-dynamic. */
25122 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
25123 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
25126 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
25127 fputs ("\t.tc .", file
);
25128 RS6000_OUTPUT_BASENAME (file
, name
);
25129 fputs ("[TC],", file
);
25130 output_addr_const (file
, x
);
25131 fputs ("@m", file
);
25139 /* Output an assembler pseudo-op to write an ASCII string of N characters
25140 starting at P to FILE.
25142 On the RS/6000, we have to do this using the .byte operation and
25143 write out special characters outside the quoted string.
25144 Also, the assembler is broken; very long strings are truncated,
25145 so we must artificially break them up early. */
25148 output_ascii (FILE *file
, const char *p
, int n
)
25151 int i
, count_string
;
25152 const char *for_string
= "\t.byte \"";
25153 const char *for_decimal
= "\t.byte ";
25154 const char *to_close
= NULL
;
25157 for (i
= 0; i
< n
; i
++)
25160 if (c
>= ' ' && c
< 0177)
25163 fputs (for_string
, file
);
25166 /* Write two quotes to get one. */
25174 for_decimal
= "\"\n\t.byte ";
25178 if (count_string
>= 512)
25180 fputs (to_close
, file
);
25182 for_string
= "\t.byte \"";
25183 for_decimal
= "\t.byte ";
25191 fputs (for_decimal
, file
);
25192 fprintf (file
, "%d", c
);
25194 for_string
= "\n\t.byte \"";
25195 for_decimal
= ", ";
25201 /* Now close the string if we have written one. Then end the line. */
25203 fputs (to_close
, file
);
25206 /* Generate a unique section name for FILENAME for a section type
25207 represented by SECTION_DESC. Output goes into BUF.
25209 SECTION_DESC can be any string, as long as it is different for each
25210 possible section type.
25212 We name the section in the same manner as xlc. The name begins with an
25213 underscore followed by the filename (after stripping any leading directory
25214 names) with the last period replaced by the string SECTION_DESC. If
25215 FILENAME does not contain a period, SECTION_DESC is appended to the end of
25219 rs6000_gen_section_name (char **buf
, const char *filename
,
25220 const char *section_desc
)
25222 const char *q
, *after_last_slash
, *last_period
= 0;
25226 after_last_slash
= filename
;
25227 for (q
= filename
; *q
; q
++)
25230 after_last_slash
= q
+ 1;
25231 else if (*q
== '.')
25235 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
25236 *buf
= (char *) xmalloc (len
);
25241 for (q
= after_last_slash
; *q
; q
++)
25243 if (q
== last_period
)
25245 strcpy (p
, section_desc
);
25246 p
+= strlen (section_desc
);
25250 else if (ISALNUM (*q
))
25254 if (last_period
== 0)
25255 strcpy (p
, section_desc
);
25260 /* Emit profile function. */
25263 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
25265 /* Non-standard profiling for kernels, which just saves LR then calls
25266 _mcount without worrying about arg saves. The idea is to change
25267 the function prologue as little as possible as it isn't easy to
25268 account for arg save/restore code added just for _mcount. */
25269 if (TARGET_PROFILE_KERNEL
)
25272 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25274 #ifndef NO_PROFILE_COUNTERS
25275 # define NO_PROFILE_COUNTERS 0
25277 if (NO_PROFILE_COUNTERS
)
25278 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25279 LCT_NORMAL
, VOIDmode
, 0);
25283 const char *label_name
;
25286 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25287 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
25288 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
25290 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25291 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
25294 else if (DEFAULT_ABI
== ABI_DARWIN
)
25296 const char *mcount_name
= RS6000_MCOUNT
;
25297 int caller_addr_regno
= LR_REGNO
;
25299 /* Be conservative and always set this, at least for now. */
25300 crtl
->uses_pic_offset_table
= 1;
25303 /* For PIC code, set up a stub and collect the caller's address
25304 from r0, which is where the prologue puts it. */
25305 if (MACHOPIC_INDIRECT
25306 && crtl
->uses_pic_offset_table
)
25307 caller_addr_regno
= 0;
25309 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
25310 LCT_NORMAL
, VOIDmode
, 1,
25311 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
25315 /* Write function profiler code. */
25318 output_function_profiler (FILE *file
, int labelno
)
25322 switch (DEFAULT_ABI
)
25325 gcc_unreachable ();
25330 warning (0, "no profiling of 64-bit code for this ABI");
25333 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25334 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
25335 if (NO_PROFILE_COUNTERS
)
25337 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25338 reg_names
[0], reg_names
[1]);
25340 else if (TARGET_SECURE_PLT
&& flag_pic
)
25342 if (TARGET_LINK_STACK
)
25345 get_ppc476_thunk_name (name
);
25346 asm_fprintf (file
, "\tbl %s\n", name
);
25349 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
25350 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25351 reg_names
[0], reg_names
[1]);
25352 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25353 asm_fprintf (file
, "\taddis %s,%s,",
25354 reg_names
[12], reg_names
[12]);
25355 assemble_name (file
, buf
);
25356 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
25357 assemble_name (file
, buf
);
25358 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
25360 else if (flag_pic
== 1)
25362 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
25363 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25364 reg_names
[0], reg_names
[1]);
25365 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25366 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
25367 assemble_name (file
, buf
);
25368 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
25370 else if (flag_pic
> 1)
25372 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25373 reg_names
[0], reg_names
[1]);
25374 /* Now, we need to get the address of the label. */
25375 if (TARGET_LINK_STACK
)
25378 get_ppc476_thunk_name (name
);
25379 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
25380 assemble_name (file
, buf
);
25381 fputs ("-.\n1:", file
);
25382 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
25383 asm_fprintf (file
, "\taddi %s,%s,4\n",
25384 reg_names
[11], reg_names
[11]);
25388 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
25389 assemble_name (file
, buf
);
25390 fputs ("-.\n1:", file
);
25391 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
25393 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
25394 reg_names
[0], reg_names
[11]);
25395 asm_fprintf (file
, "\tadd %s,%s,%s\n",
25396 reg_names
[0], reg_names
[0], reg_names
[11]);
25400 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
25401 assemble_name (file
, buf
);
25402 fputs ("@ha\n", file
);
25403 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25404 reg_names
[0], reg_names
[1]);
25405 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
25406 assemble_name (file
, buf
);
25407 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
25410 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
25411 fprintf (file
, "\tbl %s%s\n",
25412 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
25418 /* Don't do anything, done in output_profile_hook (). */
25425 /* The following variable value is the last issued insn. */
25427 static rtx last_scheduled_insn
;
25429 /* The following variable helps to balance issuing of load and
25430 store instructions */
25432 static int load_store_pendulum
;
25434 /* Power4 load update and store update instructions are cracked into a
25435 load or store and an integer insn which are executed in the same cycle.
25436 Branches have their own dispatch slot which does not count against the
25437 GCC issue rate, but it changes the program flow so there are no other
25438 instructions to issue in this cycle. */
25441 rs6000_variable_issue_1 (rtx insn
, int more
)
25443 last_scheduled_insn
= insn
;
25444 if (GET_CODE (PATTERN (insn
)) == USE
25445 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25447 cached_can_issue_more
= more
;
25448 return cached_can_issue_more
;
25451 if (insn_terminates_group_p (insn
, current_group
))
25453 cached_can_issue_more
= 0;
25454 return cached_can_issue_more
;
25457 /* If no reservation, but reach here */
25458 if (recog_memoized (insn
) < 0)
25461 if (rs6000_sched_groups
)
25463 if (is_microcoded_insn (insn
))
25464 cached_can_issue_more
= 0;
25465 else if (is_cracked_insn (insn
))
25466 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
25468 cached_can_issue_more
= more
- 1;
25470 return cached_can_issue_more
;
25473 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
25476 cached_can_issue_more
= more
- 1;
25477 return cached_can_issue_more
;
25481 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
25483 int r
= rs6000_variable_issue_1 (insn
, more
);
25485 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
25489 /* Adjust the cost of a scheduling dependency. Return the new cost of
25490 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
25493 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
25495 enum attr_type attr_type
;
25497 if (! recog_memoized (insn
))
25500 switch (REG_NOTE_KIND (link
))
25504 /* Data dependency; DEP_INSN writes a register that INSN reads
25505 some cycles later. */
25507 /* Separate a load from a narrower, dependent store. */
25508 if (rs6000_sched_groups
25509 && GET_CODE (PATTERN (insn
)) == SET
25510 && GET_CODE (PATTERN (dep_insn
)) == SET
25511 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
25512 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
25513 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
25514 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
25517 attr_type
= get_attr_type (insn
);
25522 /* Tell the first scheduling pass about the latency between
25523 a mtctr and bctr (and mtlr and br/blr). The first
25524 scheduling pass will not know about this latency since
25525 the mtctr instruction, which has the latency associated
25526 to it, will be generated by reload. */
25529 /* Leave some extra cycles between a compare and its
25530 dependent branch, to inhibit expensive mispredicts. */
25531 if ((rs6000_cpu_attr
== CPU_PPC603
25532 || rs6000_cpu_attr
== CPU_PPC604
25533 || rs6000_cpu_attr
== CPU_PPC604E
25534 || rs6000_cpu_attr
== CPU_PPC620
25535 || rs6000_cpu_attr
== CPU_PPC630
25536 || rs6000_cpu_attr
== CPU_PPC750
25537 || rs6000_cpu_attr
== CPU_PPC7400
25538 || rs6000_cpu_attr
== CPU_PPC7450
25539 || rs6000_cpu_attr
== CPU_PPCE5500
25540 || rs6000_cpu_attr
== CPU_PPCE6500
25541 || rs6000_cpu_attr
== CPU_POWER4
25542 || rs6000_cpu_attr
== CPU_POWER5
25543 || rs6000_cpu_attr
== CPU_POWER7
25544 || rs6000_cpu_attr
== CPU_POWER8
25545 || rs6000_cpu_attr
== CPU_CELL
)
25546 && recog_memoized (dep_insn
)
25547 && (INSN_CODE (dep_insn
) >= 0))
25549 switch (get_attr_type (dep_insn
))
25553 case TYPE_DELAYED_COMPARE
:
25554 case TYPE_IMUL_COMPARE
:
25555 case TYPE_LMUL_COMPARE
:
25556 case TYPE_FPCOMPARE
:
25557 case TYPE_CR_LOGICAL
:
25558 case TYPE_DELAYED_CR
:
25567 case TYPE_STORE_UX
:
25569 case TYPE_FPSTORE_U
:
25570 case TYPE_FPSTORE_UX
:
25571 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25572 && recog_memoized (dep_insn
)
25573 && (INSN_CODE (dep_insn
) >= 0))
25576 if (GET_CODE (PATTERN (insn
)) != SET
)
25577 /* If this happens, we have to extend this to schedule
25578 optimally. Return default for now. */
25581 /* Adjust the cost for the case where the value written
25582 by a fixed point operation is used as the address
25583 gen value on a store. */
25584 switch (get_attr_type (dep_insn
))
25591 if (! store_data_bypass_p (dep_insn
, insn
))
25595 case TYPE_LOAD_EXT
:
25596 case TYPE_LOAD_EXT_U
:
25597 case TYPE_LOAD_EXT_UX
:
25598 case TYPE_VAR_SHIFT_ROTATE
:
25599 case TYPE_VAR_DELAYED_COMPARE
:
25601 if (! store_data_bypass_p (dep_insn
, insn
))
25607 case TYPE_FAST_COMPARE
:
25610 case TYPE_INSERT_WORD
:
25611 case TYPE_INSERT_DWORD
:
25612 case TYPE_FPLOAD_U
:
25613 case TYPE_FPLOAD_UX
:
25615 case TYPE_STORE_UX
:
25616 case TYPE_FPSTORE_U
:
25617 case TYPE_FPSTORE_UX
:
25619 if (! store_data_bypass_p (dep_insn
, insn
))
25627 case TYPE_IMUL_COMPARE
:
25628 case TYPE_LMUL_COMPARE
:
25630 if (! store_data_bypass_p (dep_insn
, insn
))
25636 if (! store_data_bypass_p (dep_insn
, insn
))
25642 if (! store_data_bypass_p (dep_insn
, insn
))
25655 case TYPE_LOAD_EXT
:
25656 case TYPE_LOAD_EXT_U
:
25657 case TYPE_LOAD_EXT_UX
:
25658 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25659 && recog_memoized (dep_insn
)
25660 && (INSN_CODE (dep_insn
) >= 0))
25663 /* Adjust the cost for the case where the value written
25664 by a fixed point instruction is used within the address
25665 gen portion of a subsequent load(u)(x) */
25666 switch (get_attr_type (dep_insn
))
25673 if (set_to_load_agen (dep_insn
, insn
))
25677 case TYPE_LOAD_EXT
:
25678 case TYPE_LOAD_EXT_U
:
25679 case TYPE_LOAD_EXT_UX
:
25680 case TYPE_VAR_SHIFT_ROTATE
:
25681 case TYPE_VAR_DELAYED_COMPARE
:
25683 if (set_to_load_agen (dep_insn
, insn
))
25689 case TYPE_FAST_COMPARE
:
25692 case TYPE_INSERT_WORD
:
25693 case TYPE_INSERT_DWORD
:
25694 case TYPE_FPLOAD_U
:
25695 case TYPE_FPLOAD_UX
:
25697 case TYPE_STORE_UX
:
25698 case TYPE_FPSTORE_U
:
25699 case TYPE_FPSTORE_UX
:
25701 if (set_to_load_agen (dep_insn
, insn
))
25709 case TYPE_IMUL_COMPARE
:
25710 case TYPE_LMUL_COMPARE
:
25712 if (set_to_load_agen (dep_insn
, insn
))
25718 if (set_to_load_agen (dep_insn
, insn
))
25724 if (set_to_load_agen (dep_insn
, insn
))
25735 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25736 && recog_memoized (dep_insn
)
25737 && (INSN_CODE (dep_insn
) >= 0)
25738 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
25745 /* Fall out to return default cost. */
25749 case REG_DEP_OUTPUT
:
25750 /* Output dependency; DEP_INSN writes a register that INSN writes some
25752 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25753 && recog_memoized (dep_insn
)
25754 && (INSN_CODE (dep_insn
) >= 0))
25756 attr_type
= get_attr_type (insn
);
25761 if (get_attr_type (dep_insn
) == TYPE_FP
)
25765 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
25773 /* Anti dependency; DEP_INSN reads a register that INSN writes some
25778 gcc_unreachable ();
25784 /* Debug version of rs6000_adjust_cost. */
25787 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
25789 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
25795 switch (REG_NOTE_KIND (link
))
25797 default: dep
= "unknown depencency"; break;
25798 case REG_DEP_TRUE
: dep
= "data dependency"; break;
25799 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
25800 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
25804 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
25805 "%s, insn:\n", ret
, cost
, dep
);
25813 /* The function returns a true if INSN is microcoded.
25814 Return false otherwise. */
25817 is_microcoded_insn (rtx insn
)
25819 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25820 || GET_CODE (PATTERN (insn
)) == USE
25821 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25824 if (rs6000_cpu_attr
== CPU_CELL
)
25825 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
25827 if (rs6000_sched_groups
25828 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
25830 enum attr_type type
= get_attr_type (insn
);
25831 if (type
== TYPE_LOAD_EXT_U
25832 || type
== TYPE_LOAD_EXT_UX
25833 || type
== TYPE_LOAD_UX
25834 || type
== TYPE_STORE_UX
25835 || type
== TYPE_MFCR
)
25842 /* The function returns true if INSN is cracked into 2 instructions
25843 by the processor (and therefore occupies 2 issue slots). */
25846 is_cracked_insn (rtx insn
)
25848 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25849 || GET_CODE (PATTERN (insn
)) == USE
25850 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25853 if (rs6000_sched_groups
25854 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
25856 enum attr_type type
= get_attr_type (insn
);
25857 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
25858 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
25859 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
25860 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
25861 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
25862 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
25863 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
25864 || type
== TYPE_INSERT_WORD
)
25871 /* The function returns true if INSN can be issued only from
25872 the branch slot. */
25875 is_branch_slot_insn (rtx insn
)
25877 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25878 || GET_CODE (PATTERN (insn
)) == USE
25879 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25882 if (rs6000_sched_groups
)
25884 enum attr_type type
= get_attr_type (insn
);
25885 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
25893 /* The function returns true if out_inst sets a value that is
25894 used in the address generation computation of in_insn */
25896 set_to_load_agen (rtx out_insn
, rtx in_insn
)
25898 rtx out_set
, in_set
;
25900 /* For performance reasons, only handle the simple case where
25901 both loads are a single_set. */
25902 out_set
= single_set (out_insn
);
25905 in_set
= single_set (in_insn
);
25907 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
25913 /* Try to determine base/offset/size parts of the given MEM.
25914 Return true if successful, false if all the values couldn't
25917 This function only looks for REG or REG+CONST address forms.
25918 REG+REG address form will return false. */
25921 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
25922 HOST_WIDE_INT
*size
)
25925 if MEM_SIZE_KNOWN_P (mem
)
25926 *size
= MEM_SIZE (mem
);
25930 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
25931 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
25933 addr_rtx
= (XEXP (mem
, 0));
25935 if (GET_CODE (addr_rtx
) == REG
)
25940 else if (GET_CODE (addr_rtx
) == PLUS
25941 && CONST_INT_P (XEXP (addr_rtx
, 1)))
25943 *base
= XEXP (addr_rtx
, 0);
25944 *offset
= INTVAL (XEXP (addr_rtx
, 1));
25952 /* The function returns true if the target storage location of
25953 mem1 is adjacent to the target storage location of mem2 */
25954 /* Return 1 if memory locations are adjacent. */
25957 adjacent_mem_locations (rtx mem1
, rtx mem2
)
25960 HOST_WIDE_INT off1
, size1
, off2
, size2
;
25962 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
25963 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
25964 return ((REGNO (reg1
) == REGNO (reg2
))
25965 && ((off1
+ size1
== off2
)
25966 || (off2
+ size2
== off1
)));
25971 /* This function returns true if it can be determined that the two MEM
25972 locations overlap by at least 1 byte based on base reg/offset/size. */
25975 mem_locations_overlap (rtx mem1
, rtx mem2
)
25978 HOST_WIDE_INT off1
, size1
, off2
, size2
;
25980 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
25981 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
25982 return ((REGNO (reg1
) == REGNO (reg2
))
25983 && (((off1
<= off2
) && (off1
+ size1
> off2
))
25984 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
25989 /* A C statement (sans semicolon) to update the integer scheduling
25990 priority INSN_PRIORITY (INSN). Increase the priority to execute the
25991 INSN earlier, reduce the priority to execute INSN later. Do not
25992 define this macro if you do not need to adjust the scheduling
25993 priorities of insns. */
25996 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
25998 rtx load_mem
, str_mem
;
25999 /* On machines (like the 750) which have asymmetric integer units,
26000 where one integer unit can do multiply and divides and the other
26001 can't, reduce the priority of multiply/divide so it is scheduled
26002 before other integer operations. */
26005 if (! INSN_P (insn
))
26008 if (GET_CODE (PATTERN (insn
)) == USE
)
26011 switch (rs6000_cpu_attr
) {
26013 switch (get_attr_type (insn
))
26020 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
26021 priority
, priority
);
26022 if (priority
>= 0 && priority
< 0x01000000)
26029 if (insn_must_be_first_in_group (insn
)
26030 && reload_completed
26031 && current_sched_info
->sched_max_insns_priority
26032 && rs6000_sched_restricted_insns_priority
)
26035 /* Prioritize insns that can be dispatched only in the first
26037 if (rs6000_sched_restricted_insns_priority
== 1)
26038 /* Attach highest priority to insn. This means that in
26039 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
26040 precede 'priority' (critical path) considerations. */
26041 return current_sched_info
->sched_max_insns_priority
;
26042 else if (rs6000_sched_restricted_insns_priority
== 2)
26043 /* Increase priority of insn by a minimal amount. This means that in
26044 haifa-sched.c:ready_sort(), only 'priority' (critical path)
26045 considerations precede dispatch-slot restriction considerations. */
26046 return (priority
+ 1);
26049 if (rs6000_cpu
== PROCESSOR_POWER6
26050 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
26051 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
26052 /* Attach highest priority to insn if the scheduler has just issued two
26053 stores and this instruction is a load, or two loads and this instruction
26054 is a store. Power6 wants loads and stores scheduled alternately
26056 return current_sched_info
->sched_max_insns_priority
;
26061 /* Return true if the instruction is nonpipelined on the Cell. */
26063 is_nonpipeline_insn (rtx insn
)
26065 enum attr_type type
;
26066 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26067 || GET_CODE (PATTERN (insn
)) == USE
26068 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26071 type
= get_attr_type (insn
);
26072 if (type
== TYPE_IMUL
26073 || type
== TYPE_IMUL2
26074 || type
== TYPE_IMUL3
26075 || type
== TYPE_LMUL
26076 || type
== TYPE_IDIV
26077 || type
== TYPE_LDIV
26078 || type
== TYPE_SDIV
26079 || type
== TYPE_DDIV
26080 || type
== TYPE_SSQRT
26081 || type
== TYPE_DSQRT
26082 || type
== TYPE_MFCR
26083 || type
== TYPE_MFCRF
26084 || type
== TYPE_MFJMPR
)
26092 /* Return how many instructions the machine can issue per cycle. */
26095 rs6000_issue_rate (void)
26097 /* Unless scheduling for register pressure, use issue rate of 1 for
26098 first scheduling pass to decrease degradation. */
26099 if (!reload_completed
&& !flag_sched_pressure
)
26102 switch (rs6000_cpu_attr
) {
26104 case CPU_PPC601
: /* ? */
26114 case CPU_PPCE300C2
:
26115 case CPU_PPCE300C3
:
26116 case CPU_PPCE500MC
:
26117 case CPU_PPCE500MC64
:
26140 /* Return how many instructions to look ahead for better insn
26144 rs6000_use_sched_lookahead (void)
26146 switch (rs6000_cpu_attr
)
26153 return (reload_completed
? 8 : 0);
26160 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
26162 rs6000_use_sched_lookahead_guard (rtx insn
)
26164 if (rs6000_cpu_attr
!= CPU_CELL
)
26167 if (insn
== NULL_RTX
|| !INSN_P (insn
))
26170 if (!reload_completed
26171 || is_nonpipeline_insn (insn
)
26172 || is_microcoded_insn (insn
))
26178 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
26179 and return true. */
26182 find_mem_ref (rtx pat
, rtx
*mem_ref
)
26187 /* stack_tie does not produce any real memory traffic. */
26188 if (tie_operand (pat
, VOIDmode
))
26191 if (GET_CODE (pat
) == MEM
)
26197 /* Recursively process the pattern. */
26198 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
26200 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
26204 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
26207 else if (fmt
[i
] == 'E')
26208 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
26210 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
26218 /* Determine if PAT is a PATTERN of a load insn. */
26221 is_load_insn1 (rtx pat
, rtx
*load_mem
)
26223 if (!pat
|| pat
== NULL_RTX
)
26226 if (GET_CODE (pat
) == SET
)
26227 return find_mem_ref (SET_SRC (pat
), load_mem
);
26229 if (GET_CODE (pat
) == PARALLEL
)
26233 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26234 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
26241 /* Determine if INSN loads from memory. */
26244 is_load_insn (rtx insn
, rtx
*load_mem
)
26246 if (!insn
|| !INSN_P (insn
))
26252 return is_load_insn1 (PATTERN (insn
), load_mem
);
26255 /* Determine if PAT is a PATTERN of a store insn. */
26258 is_store_insn1 (rtx pat
, rtx
*str_mem
)
26260 if (!pat
|| pat
== NULL_RTX
)
26263 if (GET_CODE (pat
) == SET
)
26264 return find_mem_ref (SET_DEST (pat
), str_mem
);
26266 if (GET_CODE (pat
) == PARALLEL
)
26270 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26271 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
26278 /* Determine if INSN stores to memory. */
26281 is_store_insn (rtx insn
, rtx
*str_mem
)
26283 if (!insn
|| !INSN_P (insn
))
26286 return is_store_insn1 (PATTERN (insn
), str_mem
);
26289 /* Returns whether the dependence between INSN and NEXT is considered
26290 costly by the given target. */
26293 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
26297 rtx load_mem
, str_mem
;
26299 /* If the flag is not enabled - no dependence is considered costly;
26300 allow all dependent insns in the same group.
26301 This is the most aggressive option. */
26302 if (rs6000_sched_costly_dep
== no_dep_costly
)
26305 /* If the flag is set to 1 - a dependence is always considered costly;
26306 do not allow dependent instructions in the same group.
26307 This is the most conservative option. */
26308 if (rs6000_sched_costly_dep
== all_deps_costly
)
26311 insn
= DEP_PRO (dep
);
26312 next
= DEP_CON (dep
);
26314 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
26315 && is_load_insn (next
, &load_mem
)
26316 && is_store_insn (insn
, &str_mem
))
26317 /* Prevent load after store in the same group. */
26320 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
26321 && is_load_insn (next
, &load_mem
)
26322 && is_store_insn (insn
, &str_mem
)
26323 && DEP_TYPE (dep
) == REG_DEP_TRUE
26324 && mem_locations_overlap(str_mem
, load_mem
))
26325 /* Prevent load after store in the same group if it is a true
26329 /* The flag is set to X; dependences with latency >= X are considered costly,
26330 and will not be scheduled in the same group. */
26331 if (rs6000_sched_costly_dep
<= max_dep_latency
26332 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
26338 /* Return the next insn after INSN that is found before TAIL is reached,
26339 skipping any "non-active" insns - insns that will not actually occupy
26340 an issue slot. Return NULL_RTX if such an insn is not found. */
26343 get_next_active_insn (rtx insn
, rtx tail
)
26345 if (insn
== NULL_RTX
|| insn
== tail
)
26350 insn
= NEXT_INSN (insn
);
26351 if (insn
== NULL_RTX
|| insn
== tail
)
26355 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
26356 || (NONJUMP_INSN_P (insn
)
26357 && GET_CODE (PATTERN (insn
)) != USE
26358 && GET_CODE (PATTERN (insn
)) != CLOBBER
26359 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
26365 /* We are about to begin issuing insns for this clock cycle. */
26368 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
26369 rtx
*ready ATTRIBUTE_UNUSED
,
26370 int *pn_ready ATTRIBUTE_UNUSED
,
26371 int clock_var ATTRIBUTE_UNUSED
)
26373 int n_ready
= *pn_ready
;
26376 fprintf (dump
, "// rs6000_sched_reorder :\n");
26378 /* Reorder the ready list, if the second to last ready insn
26379 is a nonepipeline insn. */
26380 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
26382 if (is_nonpipeline_insn (ready
[n_ready
- 1])
26383 && (recog_memoized (ready
[n_ready
- 2]) > 0))
26384 /* Simply swap first two insns. */
26386 rtx tmp
= ready
[n_ready
- 1];
26387 ready
[n_ready
- 1] = ready
[n_ready
- 2];
26388 ready
[n_ready
- 2] = tmp
;
26392 if (rs6000_cpu
== PROCESSOR_POWER6
)
26393 load_store_pendulum
= 0;
26395 return rs6000_issue_rate ();
26398 /* Like rs6000_sched_reorder, but called after issuing each insn. */
26401 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
26402 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
26405 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
26407 /* For Power6, we need to handle some special cases to try and keep the
26408 store queue from overflowing and triggering expensive flushes.
26410 This code monitors how load and store instructions are being issued
26411 and skews the ready list one way or the other to increase the likelihood
26412 that a desired instruction is issued at the proper time.
26414 A couple of things are done. First, we maintain a "load_store_pendulum"
26415 to track the current state of load/store issue.
26417 - If the pendulum is at zero, then no loads or stores have been
26418 issued in the current cycle so we do nothing.
26420 - If the pendulum is 1, then a single load has been issued in this
26421 cycle and we attempt to locate another load in the ready list to
26424 - If the pendulum is -2, then two stores have already been
26425 issued in this cycle, so we increase the priority of the first load
26426 in the ready list to increase it's likelihood of being chosen first
26429 - If the pendulum is -1, then a single store has been issued in this
26430 cycle and we attempt to locate another store in the ready list to
26431 issue with it, preferring a store to an adjacent memory location to
26432 facilitate store pairing in the store queue.
26434 - If the pendulum is 2, then two loads have already been
26435 issued in this cycle, so we increase the priority of the first store
26436 in the ready list to increase it's likelihood of being chosen first
26439 - If the pendulum < -2 or > 2, then do nothing.
26441 Note: This code covers the most common scenarios. There exist non
26442 load/store instructions which make use of the LSU and which
26443 would need to be accounted for to strictly model the behavior
26444 of the machine. Those instructions are currently unaccounted
26445 for to help minimize compile time overhead of this code.
26447 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
26451 rtx tmp
, load_mem
, str_mem
;
26453 if (is_store_insn (last_scheduled_insn
, &str_mem
))
26454 /* Issuing a store, swing the load_store_pendulum to the left */
26455 load_store_pendulum
--;
26456 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
26457 /* Issuing a load, swing the load_store_pendulum to the right */
26458 load_store_pendulum
++;
26460 return cached_can_issue_more
;
26462 /* If the pendulum is balanced, or there is only one instruction on
26463 the ready list, then all is well, so return. */
26464 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
26465 return cached_can_issue_more
;
26467 if (load_store_pendulum
== 1)
26469 /* A load has been issued in this cycle. Scan the ready list
26470 for another load to issue with it */
26475 if (is_load_insn (ready
[pos
], &load_mem
))
26477 /* Found a load. Move it to the head of the ready list,
26478 and adjust it's priority so that it is more likely to
26481 for (i
=pos
; i
<*pn_ready
-1; i
++)
26482 ready
[i
] = ready
[i
+ 1];
26483 ready
[*pn_ready
-1] = tmp
;
26485 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26486 INSN_PRIORITY (tmp
)++;
26492 else if (load_store_pendulum
== -2)
26494 /* Two stores have been issued in this cycle. Increase the
26495 priority of the first load in the ready list to favor it for
26496 issuing in the next cycle. */
26501 if (is_load_insn (ready
[pos
], &load_mem
)
26503 && INSN_PRIORITY_KNOWN (ready
[pos
]))
26505 INSN_PRIORITY (ready
[pos
])++;
26507 /* Adjust the pendulum to account for the fact that a load
26508 was found and increased in priority. This is to prevent
26509 increasing the priority of multiple loads */
26510 load_store_pendulum
--;
26517 else if (load_store_pendulum
== -1)
26519 /* A store has been issued in this cycle. Scan the ready list for
26520 another store to issue with it, preferring a store to an adjacent
26522 int first_store_pos
= -1;
26528 if (is_store_insn (ready
[pos
], &str_mem
))
26531 /* Maintain the index of the first store found on the
26533 if (first_store_pos
== -1)
26534 first_store_pos
= pos
;
26536 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
26537 && adjacent_mem_locations (str_mem
, str_mem2
))
26539 /* Found an adjacent store. Move it to the head of the
26540 ready list, and adjust it's priority so that it is
26541 more likely to stay there */
26543 for (i
=pos
; i
<*pn_ready
-1; i
++)
26544 ready
[i
] = ready
[i
+ 1];
26545 ready
[*pn_ready
-1] = tmp
;
26547 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26548 INSN_PRIORITY (tmp
)++;
26550 first_store_pos
= -1;
26558 if (first_store_pos
>= 0)
26560 /* An adjacent store wasn't found, but a non-adjacent store was,
26561 so move the non-adjacent store to the front of the ready
26562 list, and adjust its priority so that it is more likely to
26564 tmp
= ready
[first_store_pos
];
26565 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
26566 ready
[i
] = ready
[i
+ 1];
26567 ready
[*pn_ready
-1] = tmp
;
26568 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26569 INSN_PRIORITY (tmp
)++;
26572 else if (load_store_pendulum
== 2)
26574 /* Two loads have been issued in this cycle. Increase the priority
26575 of the first store in the ready list to favor it for issuing in
26581 if (is_store_insn (ready
[pos
], &str_mem
)
26583 && INSN_PRIORITY_KNOWN (ready
[pos
]))
26585 INSN_PRIORITY (ready
[pos
])++;
26587 /* Adjust the pendulum to account for the fact that a store
26588 was found and increased in priority. This is to prevent
26589 increasing the priority of multiple stores */
26590 load_store_pendulum
++;
26599 return cached_can_issue_more
;
26602 /* Return whether the presence of INSN causes a dispatch group termination
26603 of group WHICH_GROUP.
26605 If WHICH_GROUP == current_group, this function will return true if INSN
26606 causes the termination of the current group (i.e, the dispatch group to
26607 which INSN belongs). This means that INSN will be the last insn in the
26608 group it belongs to.
26610 If WHICH_GROUP == previous_group, this function will return true if INSN
26611 causes the termination of the previous group (i.e, the dispatch group that
26612 precedes the group to which INSN belongs). This means that INSN will be
26613 the first insn in the group it belongs to). */
26616 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
26623 first
= insn_must_be_first_in_group (insn
);
26624 last
= insn_must_be_last_in_group (insn
);
26629 if (which_group
== current_group
)
26631 else if (which_group
== previous_group
)
26639 insn_must_be_first_in_group (rtx insn
)
26641 enum attr_type type
;
26645 || DEBUG_INSN_P (insn
)
26646 || GET_CODE (PATTERN (insn
)) == USE
26647 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26650 switch (rs6000_cpu
)
26652 case PROCESSOR_POWER5
:
26653 if (is_cracked_insn (insn
))
26655 case PROCESSOR_POWER4
:
26656 if (is_microcoded_insn (insn
))
26659 if (!rs6000_sched_groups
)
26662 type
= get_attr_type (insn
);
26669 case TYPE_DELAYED_CR
:
26670 case TYPE_CR_LOGICAL
:
26684 case PROCESSOR_POWER6
:
26685 type
= get_attr_type (insn
);
26689 case TYPE_INSERT_DWORD
:
26693 case TYPE_VAR_SHIFT_ROTATE
:
26700 case TYPE_INSERT_WORD
:
26701 case TYPE_DELAYED_COMPARE
:
26702 case TYPE_IMUL_COMPARE
:
26703 case TYPE_LMUL_COMPARE
:
26704 case TYPE_FPCOMPARE
:
26715 case TYPE_LOAD_EXT_UX
:
26717 case TYPE_STORE_UX
:
26718 case TYPE_FPLOAD_U
:
26719 case TYPE_FPLOAD_UX
:
26720 case TYPE_FPSTORE_U
:
26721 case TYPE_FPSTORE_UX
:
26727 case PROCESSOR_POWER7
:
26728 type
= get_attr_type (insn
);
26732 case TYPE_CR_LOGICAL
:
26739 case TYPE_DELAYED_COMPARE
:
26740 case TYPE_VAR_DELAYED_COMPARE
:
26746 case TYPE_LOAD_EXT
:
26747 case TYPE_LOAD_EXT_U
:
26748 case TYPE_LOAD_EXT_UX
:
26750 case TYPE_STORE_UX
:
26751 case TYPE_FPLOAD_U
:
26752 case TYPE_FPLOAD_UX
:
26753 case TYPE_FPSTORE_U
:
26754 case TYPE_FPSTORE_UX
:
26762 case PROCESSOR_POWER8
:
26763 type
= get_attr_type (insn
);
26767 case TYPE_CR_LOGICAL
:
26768 case TYPE_DELAYED_CR
:
26773 case TYPE_DELAYED_COMPARE
:
26774 case TYPE_VAR_DELAYED_COMPARE
:
26775 case TYPE_IMUL_COMPARE
:
26776 case TYPE_LMUL_COMPARE
:
26783 case TYPE_LOAD_EXT
:
26784 case TYPE_LOAD_EXT_U
:
26785 case TYPE_LOAD_EXT_UX
:
26786 case TYPE_STORE_UX
:
26787 case TYPE_VECSTORE
:
26803 insn_must_be_last_in_group (rtx insn
)
26805 enum attr_type type
;
26809 || DEBUG_INSN_P (insn
)
26810 || GET_CODE (PATTERN (insn
)) == USE
26811 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26814 switch (rs6000_cpu
) {
26815 case PROCESSOR_POWER4
:
26816 case PROCESSOR_POWER5
:
26817 if (is_microcoded_insn (insn
))
26820 if (is_branch_slot_insn (insn
))
26824 case PROCESSOR_POWER6
:
26825 type
= get_attr_type (insn
);
26832 case TYPE_VAR_SHIFT_ROTATE
:
26839 case TYPE_DELAYED_COMPARE
:
26840 case TYPE_IMUL_COMPARE
:
26841 case TYPE_LMUL_COMPARE
:
26842 case TYPE_FPCOMPARE
:
26856 case PROCESSOR_POWER7
:
26857 type
= get_attr_type (insn
);
26865 case TYPE_LOAD_EXT_U
:
26866 case TYPE_LOAD_EXT_UX
:
26867 case TYPE_STORE_UX
:
26873 case PROCESSOR_POWER8
:
26874 type
= get_attr_type (insn
);
26884 case TYPE_LOAD_EXT_U
:
26885 case TYPE_LOAD_EXT_UX
:
26886 case TYPE_STORE_UX
:
26899 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
26900 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
26903 is_costly_group (rtx
*group_insns
, rtx next_insn
)
26906 int issue_rate
= rs6000_issue_rate ();
26908 for (i
= 0; i
< issue_rate
; i
++)
26910 sd_iterator_def sd_it
;
26912 rtx insn
= group_insns
[i
];
26917 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
26919 rtx next
= DEP_CON (dep
);
26921 if (next
== next_insn
26922 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
26930 /* Utility of the function redefine_groups.
26931 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
26932 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
26933 to keep it "far" (in a separate group) from GROUP_INSNS, following
26934 one of the following schemes, depending on the value of the flag
26935 -minsert_sched_nops = X:
26936 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
26937 in order to force NEXT_INSN into a separate group.
26938 (2) X < sched_finish_regroup_exact: insert exactly X nops.
26939 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
26940 insertion (has a group just ended, how many vacant issue slots remain in the
26941 last group, and how many dispatch groups were encountered so far). */
26944 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
26945 rtx next_insn
, bool *group_end
, int can_issue_more
,
26950 int issue_rate
= rs6000_issue_rate ();
26951 bool end
= *group_end
;
26954 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
26955 return can_issue_more
;
26957 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
26958 return can_issue_more
;
26960 force
= is_costly_group (group_insns
, next_insn
);
26962 return can_issue_more
;
26964 if (sched_verbose
> 6)
26965 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
26966 *group_count
,can_issue_more
);
26968 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
26971 can_issue_more
= 0;
26973 /* Since only a branch can be issued in the last issue_slot, it is
26974 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
26975 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
26976 in this case the last nop will start a new group and the branch
26977 will be forced to the new group. */
26978 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
26981 /* Do we have a special group ending nop? */
26982 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
26983 || rs6000_cpu_attr
== CPU_POWER8
)
26985 nop
= gen_group_ending_nop ();
26986 emit_insn_before (nop
, next_insn
);
26987 can_issue_more
= 0;
26990 while (can_issue_more
> 0)
26993 emit_insn_before (nop
, next_insn
);
27001 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
27003 int n_nops
= rs6000_sched_insert_nops
;
27005 /* Nops can't be issued from the branch slot, so the effective
27006 issue_rate for nops is 'issue_rate - 1'. */
27007 if (can_issue_more
== 0)
27008 can_issue_more
= issue_rate
;
27010 if (can_issue_more
== 0)
27012 can_issue_more
= issue_rate
- 1;
27015 for (i
= 0; i
< issue_rate
; i
++)
27017 group_insns
[i
] = 0;
27024 emit_insn_before (nop
, next_insn
);
27025 if (can_issue_more
== issue_rate
- 1) /* new group begins */
27028 if (can_issue_more
== 0)
27030 can_issue_more
= issue_rate
- 1;
27033 for (i
= 0; i
< issue_rate
; i
++)
27035 group_insns
[i
] = 0;
27041 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
27044 /* Is next_insn going to start a new group? */
27047 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27048 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27049 || (can_issue_more
< issue_rate
&&
27050 insn_terminates_group_p (next_insn
, previous_group
)));
27051 if (*group_end
&& end
)
27054 if (sched_verbose
> 6)
27055 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
27056 *group_count
, can_issue_more
);
27057 return can_issue_more
;
27060 return can_issue_more
;
27063 /* This function tries to synch the dispatch groups that the compiler "sees"
27064 with the dispatch groups that the processor dispatcher is expected to
27065 form in practice. It tries to achieve this synchronization by forcing the
27066 estimated processor grouping on the compiler (as opposed to the function
27067 'pad_goups' which tries to force the scheduler's grouping on the processor).
27069 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
27070 examines the (estimated) dispatch groups that will be formed by the processor
27071 dispatcher. It marks these group boundaries to reflect the estimated
27072 processor grouping, overriding the grouping that the scheduler had marked.
27073 Depending on the value of the flag '-minsert-sched-nops' this function can
27074 force certain insns into separate groups or force a certain distance between
27075 them by inserting nops, for example, if there exists a "costly dependence"
27078 The function estimates the group boundaries that the processor will form as
27079 follows: It keeps track of how many vacant issue slots are available after
27080 each insn. A subsequent insn will start a new group if one of the following
27082 - no more vacant issue slots remain in the current dispatch group.
27083 - only the last issue slot, which is the branch slot, is vacant, but the next
27084 insn is not a branch.
27085 - only the last 2 or less issue slots, including the branch slot, are vacant,
27086 which means that a cracked insn (which occupies two issue slots) can't be
27087 issued in this group.
27088 - less than 'issue_rate' slots are vacant, and the next insn always needs to
27089 start a new group. */
27092 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27094 rtx insn
, next_insn
;
27096 int can_issue_more
;
27099 int group_count
= 0;
27103 issue_rate
= rs6000_issue_rate ();
27104 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
27105 for (i
= 0; i
< issue_rate
; i
++)
27107 group_insns
[i
] = 0;
27109 can_issue_more
= issue_rate
;
27111 insn
= get_next_active_insn (prev_head_insn
, tail
);
27114 while (insn
!= NULL_RTX
)
27116 slot
= (issue_rate
- can_issue_more
);
27117 group_insns
[slot
] = insn
;
27119 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27120 if (insn_terminates_group_p (insn
, current_group
))
27121 can_issue_more
= 0;
27123 next_insn
= get_next_active_insn (insn
, tail
);
27124 if (next_insn
== NULL_RTX
)
27125 return group_count
+ 1;
27127 /* Is next_insn going to start a new group? */
27129 = (can_issue_more
== 0
27130 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27131 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27132 || (can_issue_more
< issue_rate
&&
27133 insn_terminates_group_p (next_insn
, previous_group
)));
27135 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
27136 next_insn
, &group_end
, can_issue_more
,
27142 can_issue_more
= 0;
27143 for (i
= 0; i
< issue_rate
; i
++)
27145 group_insns
[i
] = 0;
27149 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
27150 PUT_MODE (next_insn
, VOIDmode
);
27151 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
27152 PUT_MODE (next_insn
, TImode
);
27155 if (can_issue_more
== 0)
27156 can_issue_more
= issue_rate
;
27159 return group_count
;
27162 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
27163 dispatch group boundaries that the scheduler had marked. Pad with nops
27164 any dispatch groups which have vacant issue slots, in order to force the
27165 scheduler's grouping on the processor dispatcher. The function
27166 returns the number of dispatch groups found. */
27169 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27171 rtx insn
, next_insn
;
27174 int can_issue_more
;
27176 int group_count
= 0;
27178 /* Initialize issue_rate. */
27179 issue_rate
= rs6000_issue_rate ();
27180 can_issue_more
= issue_rate
;
27182 insn
= get_next_active_insn (prev_head_insn
, tail
);
27183 next_insn
= get_next_active_insn (insn
, tail
);
27185 while (insn
!= NULL_RTX
)
27188 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27190 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
27192 if (next_insn
== NULL_RTX
)
27197 /* If the scheduler had marked group termination at this location
27198 (between insn and next_insn), and neither insn nor next_insn will
27199 force group termination, pad the group with nops to force group
27202 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27203 && !insn_terminates_group_p (insn
, current_group
)
27204 && !insn_terminates_group_p (next_insn
, previous_group
))
27206 if (!is_branch_slot_insn (next_insn
))
27209 while (can_issue_more
)
27212 emit_insn_before (nop
, next_insn
);
27217 can_issue_more
= issue_rate
;
27222 next_insn
= get_next_active_insn (insn
, tail
);
27225 return group_count
;
27228 /* We're beginning a new block. Initialize data structures as necessary. */
27231 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
27232 int sched_verbose ATTRIBUTE_UNUSED
,
27233 int max_ready ATTRIBUTE_UNUSED
)
27235 last_scheduled_insn
= NULL_RTX
;
27236 load_store_pendulum
= 0;
27239 /* The following function is called at the end of scheduling BB.
27240 After reload, it inserts nops at insn group bundling. */
27243 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
27248 fprintf (dump
, "=== Finishing schedule.\n");
27250 if (reload_completed
&& rs6000_sched_groups
)
27252 /* Do not run sched_finish hook when selective scheduling enabled. */
27253 if (sel_sched_p ())
27256 if (rs6000_sched_insert_nops
== sched_finish_none
)
27259 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27260 n_groups
= pad_groups (dump
, sched_verbose
,
27261 current_sched_info
->prev_head
,
27262 current_sched_info
->next_tail
);
27264 n_groups
= redefine_groups (dump
, sched_verbose
,
27265 current_sched_info
->prev_head
,
27266 current_sched_info
->next_tail
);
27268 if (sched_verbose
>= 6)
27270 fprintf (dump
, "ngroups = %d\n", n_groups
);
27271 print_rtl (dump
, current_sched_info
->prev_head
);
27272 fprintf (dump
, "Done finish_sched\n");
27277 struct _rs6000_sched_context
27279 short cached_can_issue_more
;
27280 rtx last_scheduled_insn
;
27281 int load_store_pendulum
;
27284 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
27285 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
27287 /* Allocate store for new scheduling context. */
27289 rs6000_alloc_sched_context (void)
27291 return xmalloc (sizeof (rs6000_sched_context_def
));
27294 /* If CLEAN_P is true then initializes _SC with clean data,
27295 and from the global context otherwise. */
27297 rs6000_init_sched_context (void *_sc
, bool clean_p
)
27299 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27303 sc
->cached_can_issue_more
= 0;
27304 sc
->last_scheduled_insn
= NULL_RTX
;
27305 sc
->load_store_pendulum
= 0;
27309 sc
->cached_can_issue_more
= cached_can_issue_more
;
27310 sc
->last_scheduled_insn
= last_scheduled_insn
;
27311 sc
->load_store_pendulum
= load_store_pendulum
;
27315 /* Sets the global scheduling context to the one pointed to by _SC. */
27317 rs6000_set_sched_context (void *_sc
)
27319 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27321 gcc_assert (sc
!= NULL
);
27323 cached_can_issue_more
= sc
->cached_can_issue_more
;
27324 last_scheduled_insn
= sc
->last_scheduled_insn
;
27325 load_store_pendulum
= sc
->load_store_pendulum
;
27330 rs6000_free_sched_context (void *_sc
)
27332 gcc_assert (_sc
!= NULL
);
27338 /* Length in units of the trampoline for entering a nested function. */
27341 rs6000_trampoline_size (void)
27345 switch (DEFAULT_ABI
)
27348 gcc_unreachable ();
27351 ret
= (TARGET_32BIT
) ? 12 : 24;
27355 gcc_assert (!TARGET_32BIT
);
27361 ret
= (TARGET_32BIT
) ? 40 : 48;
27368 /* Emit RTL insns to initialize the variable parts of a trampoline.
27369 FNADDR is an RTX for the address of the function's pure code.
27370 CXT is an RTX for the static chain value for the function. */
27373 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
27375 int regsize
= (TARGET_32BIT
) ? 4 : 8;
27376 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
27377 rtx ctx_reg
= force_reg (Pmode
, cxt
);
27378 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
27380 switch (DEFAULT_ABI
)
27383 gcc_unreachable ();
27385 /* Under AIX, just build the 3 word function descriptor */
27388 rtx fnmem
, fn_reg
, toc_reg
;
27390 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
27391 error ("You cannot take the address of a nested function if you use "
27392 "the -mno-pointers-to-nested-functions option.");
27394 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
27395 fn_reg
= gen_reg_rtx (Pmode
);
27396 toc_reg
= gen_reg_rtx (Pmode
);
27398 /* Macro to shorten the code expansions below. */
27399 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
27401 m_tramp
= replace_equiv_address (m_tramp
, addr
);
27403 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
27404 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
27405 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
27406 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
27407 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
27413 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
27417 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
27418 LCT_NORMAL
, VOIDmode
, 4,
27420 GEN_INT (rs6000_trampoline_size ()), SImode
,
27428 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
27429 identifier as an argument, so the front end shouldn't look it up. */
27432 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
27434 return is_attribute_p ("altivec", attr_id
);
27437 /* Handle the "altivec" attribute. The attribute may have
27438 arguments as follows:
27440 __attribute__((altivec(vector__)))
27441 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
27442 __attribute__((altivec(bool__))) (always followed by 'unsigned')
27444 and may appear more than once (e.g., 'vector bool char') in a
27445 given declaration. */
27448 rs6000_handle_altivec_attribute (tree
*node
,
27449 tree name ATTRIBUTE_UNUSED
,
27451 int flags ATTRIBUTE_UNUSED
,
27452 bool *no_add_attrs
)
27454 tree type
= *node
, result
= NULL_TREE
;
27455 enum machine_mode mode
;
27458 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
27459 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
27460 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
27463 while (POINTER_TYPE_P (type
)
27464 || TREE_CODE (type
) == FUNCTION_TYPE
27465 || TREE_CODE (type
) == METHOD_TYPE
27466 || TREE_CODE (type
) == ARRAY_TYPE
)
27467 type
= TREE_TYPE (type
);
27469 mode
= TYPE_MODE (type
);
27471 /* Check for invalid AltiVec type qualifiers. */
27472 if (type
== long_double_type_node
)
27473 error ("use of %<long double%> in AltiVec types is invalid");
27474 else if (type
== boolean_type_node
)
27475 error ("use of boolean types in AltiVec types is invalid");
27476 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
27477 error ("use of %<complex%> in AltiVec types is invalid");
27478 else if (DECIMAL_FLOAT_MODE_P (mode
))
27479 error ("use of decimal floating point types in AltiVec types is invalid");
27480 else if (!TARGET_VSX
)
27482 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
27485 error ("use of %<long%> in AltiVec types is invalid for "
27486 "64-bit code without -mvsx");
27487 else if (rs6000_warn_altivec_long
)
27488 warning (0, "use of %<long%> in AltiVec types is deprecated; "
27491 else if (type
== long_long_unsigned_type_node
27492 || type
== long_long_integer_type_node
)
27493 error ("use of %<long long%> in AltiVec types is invalid without "
27495 else if (type
== double_type_node
)
27496 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
27499 switch (altivec_type
)
27502 unsigned_p
= TYPE_UNSIGNED (type
);
27506 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
27509 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
27512 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
27515 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
27517 case SFmode
: result
= V4SF_type_node
; break;
27518 case DFmode
: result
= V2DF_type_node
; break;
27519 /* If the user says 'vector int bool', we may be handed the 'bool'
27520 attribute _before_ the 'vector' attribute, and so select the
27521 proper type in the 'b' case below. */
27522 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
27523 case V2DImode
: case V2DFmode
:
27531 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
27532 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
27533 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
27534 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
27541 case V8HImode
: result
= pixel_V8HI_type_node
;
27547 /* Propagate qualifiers attached to the element type
27548 onto the vector type. */
27549 if (result
&& result
!= type
&& TYPE_QUALS (type
))
27550 result
= build_qualified_type (result
, TYPE_QUALS (type
));
27552 *no_add_attrs
= true; /* No need to hang on to the attribute. */
27555 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
27560 /* AltiVec defines four built-in scalar types that serve as vector
27561 elements; we must teach the compiler how to mangle them. */
27563 static const char *
27564 rs6000_mangle_type (const_tree type
)
27566 type
= TYPE_MAIN_VARIANT (type
);
27568 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
27569 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
27572 if (type
== bool_char_type_node
) return "U6__boolc";
27573 if (type
== bool_short_type_node
) return "U6__bools";
27574 if (type
== pixel_type_node
) return "u7__pixel";
27575 if (type
== bool_int_type_node
) return "U6__booli";
27576 if (type
== bool_long_type_node
) return "U6__booll";
27578 /* Mangle IBM extended float long double as `g' (__float128) on
27579 powerpc*-linux where long-double-64 previously was the default. */
27580 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
27582 && TARGET_LONG_DOUBLE_128
27583 && !TARGET_IEEEQUAD
)
27586 /* For all other types, use normal C++ mangling. */
27590 /* Handle a "longcall" or "shortcall" attribute; arguments as in
27591 struct attribute_spec.handler. */
27594 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
27595 tree args ATTRIBUTE_UNUSED
,
27596 int flags ATTRIBUTE_UNUSED
,
27597 bool *no_add_attrs
)
27599 if (TREE_CODE (*node
) != FUNCTION_TYPE
27600 && TREE_CODE (*node
) != FIELD_DECL
27601 && TREE_CODE (*node
) != TYPE_DECL
)
27603 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
27605 *no_add_attrs
= true;
27611 /* Set longcall attributes on all functions declared when
27612 rs6000_default_long_calls is true. */
27614 rs6000_set_default_type_attributes (tree type
)
27616 if (rs6000_default_long_calls
27617 && (TREE_CODE (type
) == FUNCTION_TYPE
27618 || TREE_CODE (type
) == METHOD_TYPE
))
27619 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
27621 TYPE_ATTRIBUTES (type
));
27624 darwin_set_default_type_attributes (type
);
27628 /* Return a reference suitable for calling a function with the
27629 longcall attribute. */
27632 rs6000_longcall_ref (rtx call_ref
)
27634 const char *call_name
;
27637 if (GET_CODE (call_ref
) != SYMBOL_REF
)
27640 /* System V adds '.' to the internal name, so skip them. */
27641 call_name
= XSTR (call_ref
, 0);
27642 if (*call_name
== '.')
27644 while (*call_name
== '.')
27647 node
= get_identifier (call_name
);
27648 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
27651 return force_reg (Pmode
, call_ref
);
27654 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
27655 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
27658 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
27659 struct attribute_spec.handler. */
27661 rs6000_handle_struct_attribute (tree
*node
, tree name
,
27662 tree args ATTRIBUTE_UNUSED
,
27663 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
27666 if (DECL_P (*node
))
27668 if (TREE_CODE (*node
) == TYPE_DECL
)
27669 type
= &TREE_TYPE (*node
);
27674 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
27675 || TREE_CODE (*type
) == UNION_TYPE
)))
27677 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
27678 *no_add_attrs
= true;
27681 else if ((is_attribute_p ("ms_struct", name
)
27682 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
27683 || ((is_attribute_p ("gcc_struct", name
)
27684 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
27686 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
27688 *no_add_attrs
= true;
27695 rs6000_ms_bitfield_layout_p (const_tree record_type
)
27697 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
27698 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
27699 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
27702 #ifdef USING_ELFOS_H
27704 /* A get_unnamed_section callback, used for switching to toc_section. */
27707 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
27709 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27710 && TARGET_MINIMAL_TOC
27711 && !TARGET_RELOCATABLE
)
27713 if (!toc_initialized
)
27715 toc_initialized
= 1;
27716 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
27717 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
27718 fprintf (asm_out_file
, "\t.tc ");
27719 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
27720 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27721 fprintf (asm_out_file
, "\n");
27723 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27724 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27725 fprintf (asm_out_file
, " = .+32768\n");
27728 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27730 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27731 && !TARGET_RELOCATABLE
)
27732 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
27735 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27736 if (!toc_initialized
)
27738 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27739 fprintf (asm_out_file
, " = .+32768\n");
27740 toc_initialized
= 1;
27745 /* Implement TARGET_ASM_INIT_SECTIONS. */
27748 rs6000_elf_asm_init_sections (void)
27751 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
27754 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
27755 SDATA2_SECTION_ASM_OP
);
27758 /* Implement TARGET_SELECT_RTX_SECTION. */
27761 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
27762 unsigned HOST_WIDE_INT align
)
27764 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
27765 return toc_section
;
27767 return default_elf_select_rtx_section (mode
, x
, align
);
27770 /* For a SYMBOL_REF, set generic flags and then perform some
27771 target-specific processing.
27773 When the AIX ABI is requested on a non-AIX system, replace the
27774 function name with the real name (with a leading .) rather than the
27775 function descriptor name. This saves a lot of overriding code to
27776 read the prefixes. */
27778 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
27780 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
27782 default_encode_section_info (decl
, rtl
, first
);
27785 && TREE_CODE (decl
) == FUNCTION_DECL
27787 && DEFAULT_ABI
== ABI_AIX
)
27789 rtx sym_ref
= XEXP (rtl
, 0);
27790 size_t len
= strlen (XSTR (sym_ref
, 0));
27791 char *str
= XALLOCAVEC (char, len
+ 2);
27793 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
27794 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
27799 compare_section_name (const char *section
, const char *templ
)
27803 len
= strlen (templ
);
27804 return (strncmp (section
, templ
, len
) == 0
27805 && (section
[len
] == 0 || section
[len
] == '.'));
27809 rs6000_elf_in_small_data_p (const_tree decl
)
27811 if (rs6000_sdata
== SDATA_NONE
)
27814 /* We want to merge strings, so we never consider them small data. */
27815 if (TREE_CODE (decl
) == STRING_CST
)
27818 /* Functions are never in the small data area. */
27819 if (TREE_CODE (decl
) == FUNCTION_DECL
)
27822 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
27824 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
27825 if (compare_section_name (section
, ".sdata")
27826 || compare_section_name (section
, ".sdata2")
27827 || compare_section_name (section
, ".gnu.linkonce.s")
27828 || compare_section_name (section
, ".sbss")
27829 || compare_section_name (section
, ".sbss2")
27830 || compare_section_name (section
, ".gnu.linkonce.sb")
27831 || strcmp (section
, ".PPC.EMB.sdata0") == 0
27832 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
27837 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
27840 && size
<= g_switch_value
27841 /* If it's not public, and we're not going to reference it there,
27842 there's no need to put it in the small data section. */
27843 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
27850 #endif /* USING_ELFOS_H */
27852 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
27855 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
27857 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
27860 /* Do not place thread-local symbols refs in the object blocks. */
27863 rs6000_use_blocks_for_decl_p (const_tree decl
)
27865 return !DECL_THREAD_LOCAL_P (decl
);
27868 /* Return a REG that occurs in ADDR with coefficient 1.
27869 ADDR can be effectively incremented by incrementing REG.
27871 r0 is special and we must not select it as an address
27872 register by this routine since our caller will try to
27873 increment the returned register via an "la" instruction. */
27876 find_addr_reg (rtx addr
)
27878 while (GET_CODE (addr
) == PLUS
)
27880 if (GET_CODE (XEXP (addr
, 0)) == REG
27881 && REGNO (XEXP (addr
, 0)) != 0)
27882 addr
= XEXP (addr
, 0);
27883 else if (GET_CODE (XEXP (addr
, 1)) == REG
27884 && REGNO (XEXP (addr
, 1)) != 0)
27885 addr
= XEXP (addr
, 1);
27886 else if (CONSTANT_P (XEXP (addr
, 0)))
27887 addr
= XEXP (addr
, 1);
27888 else if (CONSTANT_P (XEXP (addr
, 1)))
27889 addr
= XEXP (addr
, 0);
27891 gcc_unreachable ();
27893 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
27898 rs6000_fatal_bad_address (rtx op
)
27900 fatal_insn ("bad address", op
);
27905 typedef struct branch_island_d
{
27906 tree function_name
;
27912 static vec
<branch_island
, va_gc
> *branch_islands
;
27914 /* Remember to generate a branch island for far calls to the given
27918 add_compiler_branch_island (tree label_name
, tree function_name
,
27921 branch_island bi
= {function_name
, label_name
, line_number
};
27922 vec_safe_push (branch_islands
, bi
);
27925 /* Generate far-jump branch islands for everything recorded in
27926 branch_islands. Invoked immediately after the last instruction of
27927 the epilogue has been emitted; the branch islands must be appended
27928 to, and contiguous with, the function body. Mach-O stubs are
27929 generated in machopic_output_stub(). */
27932 macho_branch_islands (void)
27936 while (!vec_safe_is_empty (branch_islands
))
27938 branch_island
*bi
= &branch_islands
->last ();
27939 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
27940 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
27941 char name_buf
[512];
27942 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
27943 if (name
[0] == '*' || name
[0] == '&')
27944 strcpy (name_buf
, name
+1);
27948 strcpy (name_buf
+1, name
);
27950 strcpy (tmp_buf
, "\n");
27951 strcat (tmp_buf
, label
);
27952 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
27953 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
27954 dbxout_stabd (N_SLINE
, bi
->line_number
);
27955 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
27958 if (TARGET_LINK_STACK
)
27961 get_ppc476_thunk_name (name
);
27962 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
27963 strcat (tmp_buf
, name
);
27964 strcat (tmp_buf
, "\n");
27965 strcat (tmp_buf
, label
);
27966 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
27970 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
27971 strcat (tmp_buf
, label
);
27972 strcat (tmp_buf
, "_pic\n");
27973 strcat (tmp_buf
, label
);
27974 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
27977 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
27978 strcat (tmp_buf
, name_buf
);
27979 strcat (tmp_buf
, " - ");
27980 strcat (tmp_buf
, label
);
27981 strcat (tmp_buf
, "_pic)\n");
27983 strcat (tmp_buf
, "\tmtlr r0\n");
27985 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
27986 strcat (tmp_buf
, name_buf
);
27987 strcat (tmp_buf
, " - ");
27988 strcat (tmp_buf
, label
);
27989 strcat (tmp_buf
, "_pic)\n");
27991 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
27995 strcat (tmp_buf
, ":\nlis r12,hi16(");
27996 strcat (tmp_buf
, name_buf
);
27997 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
27998 strcat (tmp_buf
, name_buf
);
27999 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
28001 output_asm_insn (tmp_buf
, 0);
28002 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
28003 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
28004 dbxout_stabd (N_SLINE
, bi
->line_number
);
28005 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
28006 branch_islands
->pop ();
28010 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
28011 already there or not. */
28014 no_previous_def (tree function_name
)
28019 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28020 if (function_name
== bi
->function_name
)
28025 /* GET_PREV_LABEL gets the label name from the previous definition of
28029 get_prev_label (tree function_name
)
28034 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
28035 if (function_name
== bi
->function_name
)
28036 return bi
->label_name
;
28040 /* INSN is either a function call or a millicode call. It may have an
28041 unconditional jump in its delay slot.
28043 CALL_DEST is the routine we are calling. */
28046 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
28047 int cookie_operand_number
)
28049 static char buf
[256];
28050 if (darwin_emit_branch_islands
28051 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
28052 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
28055 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
28057 if (no_previous_def (funname
))
28059 rtx label_rtx
= gen_label_rtx ();
28060 char *label_buf
, temp_buf
[256];
28061 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
28062 CODE_LABEL_NUMBER (label_rtx
));
28063 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
28064 labelname
= get_identifier (label_buf
);
28065 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
28068 labelname
= get_prev_label (funname
);
28070 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
28071 instruction will reach 'foo', otherwise link as 'bl L42'".
28072 "L42" should be a 'branch island', that will do a far jump to
28073 'foo'. Branch islands are generated in
28074 macho_branch_islands(). */
28075 sprintf (buf
, "jbsr %%z%d,%.246s",
28076 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
28079 sprintf (buf
, "bl %%z%d", dest_operand_number
);
28083 /* Generate PIC and indirect symbol stubs. */
28086 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
28088 unsigned int length
;
28089 char *symbol_name
, *lazy_ptr_name
;
28090 char *local_label_0
;
28091 static int label
= 0;
28093 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
28094 symb
= (*targetm
.strip_name_encoding
) (symb
);
28097 length
= strlen (symb
);
28098 symbol_name
= XALLOCAVEC (char, length
+ 32);
28099 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
28101 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
28102 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
28105 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
28107 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
28111 fprintf (file
, "\t.align 5\n");
28113 fprintf (file
, "%s:\n", stub
);
28114 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28117 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
28118 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
28120 fprintf (file
, "\tmflr r0\n");
28121 if (TARGET_LINK_STACK
)
28124 get_ppc476_thunk_name (name
);
28125 fprintf (file
, "\tbl %s\n", name
);
28126 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28130 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
28131 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28133 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
28134 lazy_ptr_name
, local_label_0
);
28135 fprintf (file
, "\tmtlr r0\n");
28136 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
28137 (TARGET_64BIT
? "ldu" : "lwzu"),
28138 lazy_ptr_name
, local_label_0
);
28139 fprintf (file
, "\tmtctr r12\n");
28140 fprintf (file
, "\tbctr\n");
28144 fprintf (file
, "\t.align 4\n");
28146 fprintf (file
, "%s:\n", stub
);
28147 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28149 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
28150 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
28151 (TARGET_64BIT
? "ldu" : "lwzu"),
28153 fprintf (file
, "\tmtctr r12\n");
28154 fprintf (file
, "\tbctr\n");
28157 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
28158 fprintf (file
, "%s:\n", lazy_ptr_name
);
28159 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28160 fprintf (file
, "%sdyld_stub_binding_helper\n",
28161 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
28164 /* Legitimize PIC addresses. If the address is already
28165 position-independent, we return ORIG. Newly generated
28166 position-independent addresses go into a reg. This is REG if non
28167 zero, otherwise we allocate register(s) as necessary. */
28169 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
28172 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
28177 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
28178 reg
= gen_reg_rtx (Pmode
);
28180 if (GET_CODE (orig
) == CONST
)
28184 if (GET_CODE (XEXP (orig
, 0)) == PLUS
28185 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
28188 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
28190 /* Use a different reg for the intermediate value, as
28191 it will be marked UNCHANGING. */
28192 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
28193 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
28196 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
28199 if (GET_CODE (offset
) == CONST_INT
)
28201 if (SMALL_INT (offset
))
28202 return plus_constant (Pmode
, base
, INTVAL (offset
));
28203 else if (! reload_in_progress
&& ! reload_completed
)
28204 offset
= force_reg (Pmode
, offset
);
28207 rtx mem
= force_const_mem (Pmode
, orig
);
28208 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
28211 return gen_rtx_PLUS (Pmode
, base
, offset
);
28214 /* Fall back on generic machopic code. */
28215 return machopic_legitimize_pic_address (orig
, mode
, reg
);
28218 /* Output a .machine directive for the Darwin assembler, and call
28219 the generic start_file routine. */
28222 rs6000_darwin_file_start (void)
28224 static const struct
28228 HOST_WIDE_INT if_set
;
28230 { "ppc64", "ppc64", MASK_64BIT
},
28231 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
28232 { "power4", "ppc970", 0 },
28233 { "G5", "ppc970", 0 },
28234 { "7450", "ppc7450", 0 },
28235 { "7400", "ppc7400", MASK_ALTIVEC
},
28236 { "G4", "ppc7400", 0 },
28237 { "750", "ppc750", 0 },
28238 { "740", "ppc750", 0 },
28239 { "G3", "ppc750", 0 },
28240 { "604e", "ppc604e", 0 },
28241 { "604", "ppc604", 0 },
28242 { "603e", "ppc603", 0 },
28243 { "603", "ppc603", 0 },
28244 { "601", "ppc601", 0 },
28245 { NULL
, "ppc", 0 } };
28246 const char *cpu_id
= "";
28249 rs6000_file_start ();
28250 darwin_file_start ();
28252 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
28254 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
28255 cpu_id
= rs6000_default_cpu
;
28257 if (global_options_set
.x_rs6000_cpu_index
)
28258 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
28260 /* Look through the mapping array. Pick the first name that either
28261 matches the argument, has a bit set in IF_SET that is also set
28262 in the target flags, or has a NULL name. */
28265 while (mapping
[i
].arg
!= NULL
28266 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
28267 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
28270 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
28273 #endif /* TARGET_MACHO */
28277 rs6000_elf_reloc_rw_mask (void)
28281 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28287 /* Record an element in the table of global constructors. SYMBOL is
28288 a SYMBOL_REF of the function to be called; PRIORITY is a number
28289 between 0 and MAX_INIT_PRIORITY.
28291 This differs from default_named_section_asm_out_constructor in
28292 that we have special handling for -mrelocatable. */
28294 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
28296 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
28298 const char *section
= ".ctors";
28301 if (priority
!= DEFAULT_INIT_PRIORITY
)
28303 sprintf (buf
, ".ctors.%.5u",
28304 /* Invert the numbering so the linker puts us in the proper
28305 order; constructors are run from right to left, and the
28306 linker sorts in increasing order. */
28307 MAX_INIT_PRIORITY
- priority
);
28311 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28312 assemble_align (POINTER_SIZE
);
28314 if (TARGET_RELOCATABLE
)
28316 fputs ("\t.long (", asm_out_file
);
28317 output_addr_const (asm_out_file
, symbol
);
28318 fputs (")@fixup\n", asm_out_file
);
28321 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28324 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
28326 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
28328 const char *section
= ".dtors";
28331 if (priority
!= DEFAULT_INIT_PRIORITY
)
28333 sprintf (buf
, ".dtors.%.5u",
28334 /* Invert the numbering so the linker puts us in the proper
28335 order; constructors are run from right to left, and the
28336 linker sorts in increasing order. */
28337 MAX_INIT_PRIORITY
- priority
);
28341 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28342 assemble_align (POINTER_SIZE
);
28344 if (TARGET_RELOCATABLE
)
28346 fputs ("\t.long (", asm_out_file
);
28347 output_addr_const (asm_out_file
, symbol
);
28348 fputs (")@fixup\n", asm_out_file
);
28351 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28355 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
28357 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
28359 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
28360 ASM_OUTPUT_LABEL (file
, name
);
28361 fputs (DOUBLE_INT_ASM_OP
, file
);
28362 rs6000_output_function_entry (file
, name
);
28363 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
28366 fputs ("\t.size\t", file
);
28367 assemble_name (file
, name
);
28368 fputs (",24\n\t.type\t.", file
);
28369 assemble_name (file
, name
);
28370 fputs (",@function\n", file
);
28371 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
28373 fputs ("\t.globl\t.", file
);
28374 assemble_name (file
, name
);
28379 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
28380 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
28381 rs6000_output_function_entry (file
, name
);
28382 fputs (":\n", file
);
28386 if (TARGET_RELOCATABLE
28387 && !TARGET_SECURE_PLT
28388 && (get_pool_size () != 0 || crtl
->profile
)
28393 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
28395 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
28396 fprintf (file
, "\t.long ");
28397 assemble_name (file
, buf
);
28399 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
28400 assemble_name (file
, buf
);
28404 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
28405 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
28407 if (DEFAULT_ABI
== ABI_AIX
)
28409 const char *desc_name
, *orig_name
;
28411 orig_name
= (*targetm
.strip_name_encoding
) (name
);
28412 desc_name
= orig_name
;
28413 while (*desc_name
== '.')
28416 if (TREE_PUBLIC (decl
))
28417 fprintf (file
, "\t.globl %s\n", desc_name
);
28419 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28420 fprintf (file
, "%s:\n", desc_name
);
28421 fprintf (file
, "\t.long %s\n", orig_name
);
28422 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
28423 fputs ("\t.long 0\n", file
);
28424 fprintf (file
, "\t.previous\n");
28426 ASM_OUTPUT_LABEL (file
, name
);
28429 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
28431 rs6000_elf_file_end (void)
28433 #ifdef HAVE_AS_GNU_ATTRIBUTE
28434 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
28436 if (rs6000_passes_float
)
28437 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
28438 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
28439 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
28441 if (rs6000_passes_vector
)
28442 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
28443 (TARGET_ALTIVEC_ABI
? 2
28444 : TARGET_SPE_ABI
? 3
28446 if (rs6000_returns_struct
)
28447 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
28448 aix_struct_return
? 2 : 1);
28451 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
28452 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
28453 file_end_indicate_exec_stack ();
28460 rs6000_xcoff_asm_output_anchor (rtx symbol
)
28464 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
28465 SYMBOL_REF_BLOCK_OFFSET (symbol
));
28466 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
28470 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
28472 fputs (GLOBAL_ASM_OP
, stream
);
28473 RS6000_OUTPUT_BASENAME (stream
, name
);
28474 putc ('\n', stream
);
28477 /* A get_unnamed_decl callback, used for read-only sections. PTR
28478 points to the section string variable. */
28481 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
28483 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
28484 *(const char *const *) directive
,
28485 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28488 /* Likewise for read-write sections. */
28491 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
28493 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
28494 *(const char *const *) directive
,
28495 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28499 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
28501 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
28502 *(const char *const *) directive
,
28503 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28506 /* A get_unnamed_section callback, used for switching to toc_section. */
28509 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
28511 if (TARGET_MINIMAL_TOC
)
28513 /* toc_section is always selected at least once from
28514 rs6000_xcoff_file_start, so this is guaranteed to
28515 always be defined once and only once in each file. */
28516 if (!toc_initialized
)
28518 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
28519 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
28520 toc_initialized
= 1;
28522 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
28523 (TARGET_32BIT
? "" : ",3"));
28526 fputs ("\t.toc\n", asm_out_file
);
28529 /* Implement TARGET_ASM_INIT_SECTIONS. */
28532 rs6000_xcoff_asm_init_sections (void)
28534 read_only_data_section
28535 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
28536 &xcoff_read_only_section_name
);
28538 private_data_section
28539 = get_unnamed_section (SECTION_WRITE
,
28540 rs6000_xcoff_output_readwrite_section_asm_op
,
28541 &xcoff_private_data_section_name
);
28544 = get_unnamed_section (SECTION_TLS
,
28545 rs6000_xcoff_output_tls_section_asm_op
,
28546 &xcoff_tls_data_section_name
);
28548 tls_private_data_section
28549 = get_unnamed_section (SECTION_TLS
,
28550 rs6000_xcoff_output_tls_section_asm_op
,
28551 &xcoff_private_data_section_name
);
28553 read_only_private_data_section
28554 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
28555 &xcoff_private_data_section_name
);
28558 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
28560 readonly_data_section
= read_only_data_section
;
28561 exception_section
= data_section
;
28565 rs6000_xcoff_reloc_rw_mask (void)
28571 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
28572 tree decl ATTRIBUTE_UNUSED
)
28575 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
28577 if (flags
& SECTION_CODE
)
28579 else if (flags
& SECTION_TLS
)
28581 else if (flags
& SECTION_WRITE
)
28586 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
28587 (flags
& SECTION_CODE
) ? "." : "",
28588 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
28591 #define IN_NAMED_SECTION(DECL) \
28592 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
28593 && DECL_SECTION_NAME (DECL) != NULL_TREE)
28596 rs6000_xcoff_select_section (tree decl
, int reloc
,
28597 unsigned HOST_WIDE_INT align
)
28599 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
28601 if (align
> BIGGEST_ALIGNMENT
)
28603 resolve_unique_section (decl
, reloc
, true);
28604 if (IN_NAMED_SECTION (decl
))
28605 return get_named_section (decl
, NULL
, reloc
);
28608 if (decl_readonly_section (decl
, reloc
))
28610 if (TREE_PUBLIC (decl
))
28611 return read_only_data_section
;
28613 return read_only_private_data_section
;
28618 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
28620 if (TREE_PUBLIC (decl
))
28621 return tls_data_section
;
28622 else if (bss_initializer_p (decl
))
28624 /* Convert to COMMON to emit in BSS. */
28625 DECL_COMMON (decl
) = 1;
28626 return tls_comm_section
;
28629 return tls_private_data_section
;
28633 if (TREE_PUBLIC (decl
))
28634 return data_section
;
28636 return private_data_section
;
28641 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
28645 /* Use select_section for private data and uninitialized data with
28646 alignment <= BIGGEST_ALIGNMENT. */
28647 if (!TREE_PUBLIC (decl
)
28648 || DECL_COMMON (decl
)
28649 || (DECL_INITIAL (decl
) == NULL_TREE
28650 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
28651 || DECL_INITIAL (decl
) == error_mark_node
28652 || (flag_zero_initialized_in_bss
28653 && initializer_zerop (DECL_INITIAL (decl
))))
28656 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
28657 name
= (*targetm
.strip_name_encoding
) (name
);
28658 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
28661 /* Select section for constant in constant pool.
28663 On RS/6000, all constants are in the private read-only data area.
28664 However, if this is being placed in the TOC it must be output as a
28668 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
28669 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
28671 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
28672 return toc_section
;
28674 return read_only_private_data_section
;
28677 /* Remove any trailing [DS] or the like from the symbol name. */
28679 static const char *
28680 rs6000_xcoff_strip_name_encoding (const char *name
)
28685 len
= strlen (name
);
28686 if (name
[len
- 1] == ']')
28687 return ggc_alloc_string (name
, len
- 4);
28692 /* Section attributes. AIX is always PIC. */
28694 static unsigned int
28695 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
28697 unsigned int align
;
28698 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
28700 /* Align to at least UNIT size. */
28701 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
28702 align
= MIN_UNITS_PER_WORD
;
28704 /* Increase alignment of large objects if not already stricter. */
28705 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
28706 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
28707 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
28709 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
28712 /* Output at beginning of assembler file.
28714 Initialize the section names for the RS/6000 at this point.
28716 Specify filename, including full path, to assembler.
28718 We want to go into the TOC section so at least one .toc will be emitted.
28719 Also, in order to output proper .bs/.es pairs, we need at least one static
28720 [RW] section emitted.
28722 Finally, declare mcount when profiling to make the assembler happy. */
28725 rs6000_xcoff_file_start (void)
28727 rs6000_gen_section_name (&xcoff_bss_section_name
,
28728 main_input_filename
, ".bss_");
28729 rs6000_gen_section_name (&xcoff_private_data_section_name
,
28730 main_input_filename
, ".rw_");
28731 rs6000_gen_section_name (&xcoff_read_only_section_name
,
28732 main_input_filename
, ".ro_");
28733 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
28734 main_input_filename
, ".tls_");
28735 rs6000_gen_section_name (&xcoff_tbss_section_name
,
28736 main_input_filename
, ".tbss_[UL]");
28738 fputs ("\t.file\t", asm_out_file
);
28739 output_quoted_string (asm_out_file
, main_input_filename
);
28740 fputc ('\n', asm_out_file
);
28741 if (write_symbols
!= NO_DEBUG
)
28742 switch_to_section (private_data_section
);
28743 switch_to_section (text_section
);
28745 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
28746 rs6000_file_start ();
28749 /* Output at end of assembler file.
28750 On the RS/6000, referencing data should automatically pull in text. */
28753 rs6000_xcoff_file_end (void)
28755 switch_to_section (text_section
);
28756 fputs ("_section_.text:\n", asm_out_file
);
28757 switch_to_section (data_section
);
28758 fputs (TARGET_32BIT
28759 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
28765 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
28770 default_encode_section_info (decl
, rtl
, first
);
28772 /* Careful not to prod global register variables. */
28775 symbol
= XEXP (rtl
, 0);
28776 if (GET_CODE (symbol
) != SYMBOL_REF
)
28779 flags
= SYMBOL_REF_FLAGS (symbol
);
28781 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
28782 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
28784 SYMBOL_REF_FLAGS (symbol
) = flags
;
28786 #endif /* HAVE_AS_TLS */
28787 #endif /* TARGET_XCOFF */
28789 /* Compute a (partial) cost for rtx X. Return true if the complete
28790 cost has been computed, and false if subexpressions should be
28791 scanned. In either case, *TOTAL contains the cost result. */
28794 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
28795 int *total
, bool speed
)
28797 enum machine_mode mode
= GET_MODE (x
);
28801 /* On the RS/6000, if it is valid in the insn, it is free. */
28803 if (((outer_code
== SET
28804 || outer_code
== PLUS
28805 || outer_code
== MINUS
)
28806 && (satisfies_constraint_I (x
)
28807 || satisfies_constraint_L (x
)))
28808 || (outer_code
== AND
28809 && (satisfies_constraint_K (x
)
28811 ? satisfies_constraint_L (x
)
28812 : satisfies_constraint_J (x
))
28813 || mask_operand (x
, mode
)
28815 && mask64_operand (x
, DImode
))))
28816 || ((outer_code
== IOR
|| outer_code
== XOR
)
28817 && (satisfies_constraint_K (x
)
28819 ? satisfies_constraint_L (x
)
28820 : satisfies_constraint_J (x
))))
28821 || outer_code
== ASHIFT
28822 || outer_code
== ASHIFTRT
28823 || outer_code
== LSHIFTRT
28824 || outer_code
== ROTATE
28825 || outer_code
== ROTATERT
28826 || outer_code
== ZERO_EXTRACT
28827 || (outer_code
== MULT
28828 && satisfies_constraint_I (x
))
28829 || ((outer_code
== DIV
|| outer_code
== UDIV
28830 || outer_code
== MOD
|| outer_code
== UMOD
)
28831 && exact_log2 (INTVAL (x
)) >= 0)
28832 || (outer_code
== COMPARE
28833 && (satisfies_constraint_I (x
)
28834 || satisfies_constraint_K (x
)))
28835 || ((outer_code
== EQ
|| outer_code
== NE
)
28836 && (satisfies_constraint_I (x
)
28837 || satisfies_constraint_K (x
)
28839 ? satisfies_constraint_L (x
)
28840 : satisfies_constraint_J (x
))))
28841 || (outer_code
== GTU
28842 && satisfies_constraint_I (x
))
28843 || (outer_code
== LTU
28844 && satisfies_constraint_P (x
)))
28849 else if ((outer_code
== PLUS
28850 && reg_or_add_cint_operand (x
, VOIDmode
))
28851 || (outer_code
== MINUS
28852 && reg_or_sub_cint_operand (x
, VOIDmode
))
28853 || ((outer_code
== SET
28854 || outer_code
== IOR
28855 || outer_code
== XOR
)
28857 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
28859 *total
= COSTS_N_INSNS (1);
28869 /* When optimizing for size, MEM should be slightly more expensive
28870 than generating address, e.g., (plus (reg) (const)).
28871 L1 cache latency is about two instructions. */
28872 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
28881 if (FLOAT_MODE_P (mode
))
28882 *total
= rs6000_cost
->fp
;
28884 *total
= COSTS_N_INSNS (1);
28888 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
28889 && satisfies_constraint_I (XEXP (x
, 1)))
28891 if (INTVAL (XEXP (x
, 1)) >= -256
28892 && INTVAL (XEXP (x
, 1)) <= 255)
28893 *total
= rs6000_cost
->mulsi_const9
;
28895 *total
= rs6000_cost
->mulsi_const
;
28897 else if (mode
== SFmode
)
28898 *total
= rs6000_cost
->fp
;
28899 else if (FLOAT_MODE_P (mode
))
28900 *total
= rs6000_cost
->dmul
;
28901 else if (mode
== DImode
)
28902 *total
= rs6000_cost
->muldi
;
28904 *total
= rs6000_cost
->mulsi
;
28908 if (mode
== SFmode
)
28909 *total
= rs6000_cost
->fp
;
28911 *total
= rs6000_cost
->dmul
;
28916 if (FLOAT_MODE_P (mode
))
28918 *total
= mode
== DFmode
? rs6000_cost
->ddiv
28919 : rs6000_cost
->sdiv
;
28926 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
28927 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
28929 if (code
== DIV
|| code
== MOD
)
28931 *total
= COSTS_N_INSNS (2);
28934 *total
= COSTS_N_INSNS (1);
28938 if (GET_MODE (XEXP (x
, 1)) == DImode
)
28939 *total
= rs6000_cost
->divdi
;
28941 *total
= rs6000_cost
->divsi
;
28943 /* Add in shift and subtract for MOD. */
28944 if (code
== MOD
|| code
== UMOD
)
28945 *total
+= COSTS_N_INSNS (2);
28950 *total
= COSTS_N_INSNS (4);
28954 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
28958 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
28962 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
28974 *total
= COSTS_N_INSNS (1);
28982 /* Handle mul_highpart. */
28983 if (outer_code
== TRUNCATE
28984 && GET_CODE (XEXP (x
, 0)) == MULT
)
28986 if (mode
== DImode
)
28987 *total
= rs6000_cost
->muldi
;
28989 *total
= rs6000_cost
->mulsi
;
28992 else if (outer_code
== AND
)
28995 *total
= COSTS_N_INSNS (1);
29000 if (GET_CODE (XEXP (x
, 0)) == MEM
)
29003 *total
= COSTS_N_INSNS (1);
29009 if (!FLOAT_MODE_P (mode
))
29011 *total
= COSTS_N_INSNS (1);
29017 case UNSIGNED_FLOAT
:
29020 case FLOAT_TRUNCATE
:
29021 *total
= rs6000_cost
->fp
;
29025 if (mode
== DFmode
)
29028 *total
= rs6000_cost
->fp
;
29032 switch (XINT (x
, 1))
29035 *total
= rs6000_cost
->fp
;
29047 *total
= COSTS_N_INSNS (1);
29050 else if (FLOAT_MODE_P (mode
)
29051 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
29053 *total
= rs6000_cost
->fp
;
29061 /* Carry bit requires mode == Pmode.
29062 NEG or PLUS already counted so only add one. */
29064 && (outer_code
== NEG
|| outer_code
== PLUS
))
29066 *total
= COSTS_N_INSNS (1);
29069 if (outer_code
== SET
)
29071 if (XEXP (x
, 1) == const0_rtx
)
29073 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29074 *total
= COSTS_N_INSNS (8);
29076 *total
= COSTS_N_INSNS (2);
29079 else if (mode
== Pmode
)
29081 *total
= COSTS_N_INSNS (3);
29090 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
29092 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29093 *total
= COSTS_N_INSNS (8);
29095 *total
= COSTS_N_INSNS (2);
29099 if (outer_code
== COMPARE
)
29113 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
29116 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
29119 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
29122 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
29123 "opno = %d, total = %d, speed = %s, x:\n",
29124 ret
? "complete" : "scan inner",
29125 GET_RTX_NAME (code
),
29126 GET_RTX_NAME (outer_code
),
29129 speed
? "true" : "false");
29136 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
29139 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
29140 addr_space_t as
, bool speed
)
29142 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
29144 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
29145 ret
, speed
? "true" : "false");
29152 /* A C expression returning the cost of moving data from a register of class
29153 CLASS1 to one of CLASS2. */
29156 rs6000_register_move_cost (enum machine_mode mode
,
29157 reg_class_t from
, reg_class_t to
)
29161 if (TARGET_DEBUG_COST
)
29164 /* Moves from/to GENERAL_REGS. */
29165 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
29166 || reg_classes_intersect_p (from
, GENERAL_REGS
))
29168 reg_class_t rclass
= from
;
29170 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
29173 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
29174 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
29175 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
29177 /* It's more expensive to move CR_REGS than CR0_REGS because of the
29179 else if (rclass
== CR_REGS
)
29182 /* For those processors that have slow LR/CTR moves, make them more
29183 expensive than memory in order to bias spills to memory .*/
29184 else if ((rs6000_cpu
== PROCESSOR_POWER6
29185 || rs6000_cpu
== PROCESSOR_POWER7
29186 || rs6000_cpu
== PROCESSOR_POWER8
)
29187 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
29188 ret
= 6 * hard_regno_nregs
[0][mode
];
29191 /* A move will cost one instruction per GPR moved. */
29192 ret
= 2 * hard_regno_nregs
[0][mode
];
29195 /* If we have VSX, we can easily move between FPR or Altivec registers. */
29196 else if (VECTOR_MEM_VSX_P (mode
)
29197 && reg_classes_intersect_p (to
, VSX_REGS
)
29198 && reg_classes_intersect_p (from
, VSX_REGS
))
29199 ret
= 2 * hard_regno_nregs
[32][mode
];
29201 /* Moving between two similar registers is just one instruction. */
29202 else if (reg_classes_intersect_p (to
, from
))
29203 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
29205 /* Everything else has to go through GENERAL_REGS. */
29207 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
29208 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
29210 if (TARGET_DEBUG_COST
)
29212 if (dbg_cost_ctrl
== 1)
29214 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
29215 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
29216 reg_class_names
[to
]);
29223 /* A C expressions returning the cost of moving data of MODE from a register to
29227 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
29228 bool in ATTRIBUTE_UNUSED
)
29232 if (TARGET_DEBUG_COST
)
29235 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
29236 ret
= 4 * hard_regno_nregs
[0][mode
];
29237 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
29238 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
29239 ret
= 4 * hard_regno_nregs
[32][mode
];
29240 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
29241 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
29243 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
29245 if (TARGET_DEBUG_COST
)
29247 if (dbg_cost_ctrl
== 1)
29249 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
29250 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
29257 /* Returns a code for a target-specific builtin that implements
29258 reciprocal of the function, or NULL_TREE if not available. */
29261 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
29262 bool sqrt ATTRIBUTE_UNUSED
)
29264 if (optimize_insn_for_size_p ())
29270 case VSX_BUILTIN_XVSQRTDP
:
29271 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
29274 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
29276 case VSX_BUILTIN_XVSQRTSP
:
29277 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
29280 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
29289 case BUILT_IN_SQRT
:
29290 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
29293 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
29295 case BUILT_IN_SQRTF
:
29296 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
29299 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
29306 /* Load up a constant. If the mode is a vector mode, splat the value across
29307 all of the vector elements. */
29310 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
29314 if (mode
== SFmode
|| mode
== DFmode
)
29316 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
29317 reg
= force_reg (mode
, d
);
29319 else if (mode
== V4SFmode
)
29321 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
29322 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
29323 reg
= gen_reg_rtx (mode
);
29324 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29326 else if (mode
== V2DFmode
)
29328 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
29329 rtvec v
= gen_rtvec (2, d
, d
);
29330 reg
= gen_reg_rtx (mode
);
29331 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29334 gcc_unreachable ();
29339 /* Generate an FMA instruction. */
29342 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
29344 enum machine_mode mode
= GET_MODE (target
);
29347 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
29348 gcc_assert (dst
!= NULL
);
29351 emit_move_insn (target
, dst
);
29354 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
29357 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
29359 enum machine_mode mode
= GET_MODE (target
);
29362 /* Altivec does not support fms directly;
29363 generate in terms of fma in that case. */
29364 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
29365 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
29368 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
29369 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
29371 gcc_assert (dst
!= NULL
);
29374 emit_move_insn (target
, dst
);
29377 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
29380 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
29382 enum machine_mode mode
= GET_MODE (dst
);
29385 /* This is a tad more complicated, since the fnma_optab is for
29386 a different expression: fma(-m1, m2, a), which is the same
29387 thing except in the case of signed zeros.
29389 Fortunately we know that if FMA is supported that FNMSUB is
29390 also supported in the ISA. Just expand it directly. */
29392 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
29394 r
= gen_rtx_NEG (mode
, a
);
29395 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
29396 r
= gen_rtx_NEG (mode
, r
);
29397 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
29400 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
29401 add a reg_note saying that this was a division. Support both scalar and
29402 vector divide. Assumes no trapping math and finite arguments. */
29405 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
29407 enum machine_mode mode
= GET_MODE (dst
);
29408 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
29411 /* Low precision estimates guarantee 5 bits of accuracy. High
29412 precision estimates guarantee 14 bits of accuracy. SFmode
29413 requires 23 bits of accuracy. DFmode requires 52 bits of
29414 accuracy. Each pass at least doubles the accuracy, leading
29415 to the following. */
29416 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
29417 if (mode
== DFmode
|| mode
== V2DFmode
)
29420 enum insn_code code
= optab_handler (smul_optab
, mode
);
29421 insn_gen_fn gen_mul
= GEN_FCN (code
);
29423 gcc_assert (code
!= CODE_FOR_nothing
);
29425 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
29427 /* x0 = 1./d estimate */
29428 x0
= gen_reg_rtx (mode
);
29429 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
29430 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
29433 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
29436 /* e0 = 1. - d * x0 */
29437 e0
= gen_reg_rtx (mode
);
29438 rs6000_emit_nmsub (e0
, d
, x0
, one
);
29440 /* x1 = x0 + e0 * x0 */
29441 x1
= gen_reg_rtx (mode
);
29442 rs6000_emit_madd (x1
, e0
, x0
, x0
);
29444 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
29445 ++i
, xprev
= xnext
, eprev
= enext
) {
29447 /* enext = eprev * eprev */
29448 enext
= gen_reg_rtx (mode
);
29449 emit_insn (gen_mul (enext
, eprev
, eprev
));
29451 /* xnext = xprev + enext * xprev */
29452 xnext
= gen_reg_rtx (mode
);
29453 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
29459 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
29461 /* u = n * xprev */
29462 u
= gen_reg_rtx (mode
);
29463 emit_insn (gen_mul (u
, n
, xprev
));
29465 /* v = n - (d * u) */
29466 v
= gen_reg_rtx (mode
);
29467 rs6000_emit_nmsub (v
, d
, u
, n
);
29469 /* dst = (v * xprev) + u */
29470 rs6000_emit_madd (dst
, v
, xprev
, u
);
29473 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
29476 /* Newton-Raphson approximation of single/double-precision floating point
29477 rsqrt. Assumes no trapping math and finite arguments. */
29480 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
29482 enum machine_mode mode
= GET_MODE (src
);
29483 rtx x0
= gen_reg_rtx (mode
);
29484 rtx y
= gen_reg_rtx (mode
);
29486 /* Low precision estimates guarantee 5 bits of accuracy. High
29487 precision estimates guarantee 14 bits of accuracy. SFmode
29488 requires 23 bits of accuracy. DFmode requires 52 bits of
29489 accuracy. Each pass at least doubles the accuracy, leading
29490 to the following. */
29491 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
29492 if (mode
== DFmode
|| mode
== V2DFmode
)
29495 REAL_VALUE_TYPE dconst3_2
;
29498 enum insn_code code
= optab_handler (smul_optab
, mode
);
29499 insn_gen_fn gen_mul
= GEN_FCN (code
);
29501 gcc_assert (code
!= CODE_FOR_nothing
);
29503 /* Load up the constant 1.5 either as a scalar, or as a vector. */
29504 real_from_integer (&dconst3_2
, VOIDmode
, 3, 0, 0);
29505 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
29507 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
29509 /* x0 = rsqrt estimate */
29510 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
29511 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
29514 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
29515 rs6000_emit_msub (y
, src
, halfthree
, src
);
29517 for (i
= 0; i
< passes
; i
++)
29519 rtx x1
= gen_reg_rtx (mode
);
29520 rtx u
= gen_reg_rtx (mode
);
29521 rtx v
= gen_reg_rtx (mode
);
29523 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
29524 emit_insn (gen_mul (u
, x0
, x0
));
29525 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
29526 emit_insn (gen_mul (x1
, x0
, v
));
29530 emit_move_insn (dst
, x0
);
29534 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
29535 (Power7) targets. DST is the target, and SRC is the argument operand. */
29538 rs6000_emit_popcount (rtx dst
, rtx src
)
29540 enum machine_mode mode
= GET_MODE (dst
);
29543 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
29544 if (TARGET_POPCNTD
)
29546 if (mode
== SImode
)
29547 emit_insn (gen_popcntdsi2 (dst
, src
));
29549 emit_insn (gen_popcntddi2 (dst
, src
));
29553 tmp1
= gen_reg_rtx (mode
);
29555 if (mode
== SImode
)
29557 emit_insn (gen_popcntbsi2 (tmp1
, src
));
29558 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
29560 tmp2
= force_reg (SImode
, tmp2
);
29561 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
29565 emit_insn (gen_popcntbdi2 (tmp1
, src
));
29566 tmp2
= expand_mult (DImode
, tmp1
,
29567 GEN_INT ((HOST_WIDE_INT
)
29568 0x01010101 << 32 | 0x01010101),
29570 tmp2
= force_reg (DImode
, tmp2
);
29571 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
29576 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
29577 target, and SRC is the argument operand. */
29580 rs6000_emit_parity (rtx dst
, rtx src
)
29582 enum machine_mode mode
= GET_MODE (dst
);
29585 tmp
= gen_reg_rtx (mode
);
29587 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
29590 if (mode
== SImode
)
29592 emit_insn (gen_popcntbsi2 (tmp
, src
));
29593 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
29597 emit_insn (gen_popcntbdi2 (tmp
, src
));
29598 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
29603 if (mode
== SImode
)
29605 /* Is mult+shift >= shift+xor+shift+xor? */
29606 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
29608 rtx tmp1
, tmp2
, tmp3
, tmp4
;
29610 tmp1
= gen_reg_rtx (SImode
);
29611 emit_insn (gen_popcntbsi2 (tmp1
, src
));
29613 tmp2
= gen_reg_rtx (SImode
);
29614 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
29615 tmp3
= gen_reg_rtx (SImode
);
29616 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
29618 tmp4
= gen_reg_rtx (SImode
);
29619 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
29620 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
29623 rs6000_emit_popcount (tmp
, src
);
29624 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
29628 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
29629 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
29631 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
29633 tmp1
= gen_reg_rtx (DImode
);
29634 emit_insn (gen_popcntbdi2 (tmp1
, src
));
29636 tmp2
= gen_reg_rtx (DImode
);
29637 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
29638 tmp3
= gen_reg_rtx (DImode
);
29639 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
29641 tmp4
= gen_reg_rtx (DImode
);
29642 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
29643 tmp5
= gen_reg_rtx (DImode
);
29644 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
29646 tmp6
= gen_reg_rtx (DImode
);
29647 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
29648 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
29651 rs6000_emit_popcount (tmp
, src
);
29652 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
29656 /* Expand an Altivec constant permutation for little endian mode.
29657 There are two issues: First, the two input operands must be
29658 swapped so that together they form a double-wide array in LE
29659 order. Second, the vperm instruction has surprising behavior
29660 in LE mode: it interprets the elements of the source vectors
29661 in BE mode ("left to right") and interprets the elements of
29662 the destination vector in LE mode ("right to left"). To
29663 correct for this, we must subtract each element of the permute
29664 control vector from 31.
29666 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
29667 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
29668 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
29669 serve as the permute control vector. Then, in BE mode,
29673 places the desired result in vr9. However, in LE mode the
29674 vector contents will be
29676 vr10 = 00000003 00000002 00000001 00000000
29677 vr11 = 00000007 00000006 00000005 00000004
29679 The result of the vperm using the same permute control vector is
29681 vr9 = 05000000 07000000 01000000 03000000
29683 That is, the leftmost 4 bytes of vr10 are interpreted as the
29684 source for the rightmost 4 bytes of vr9, and so on.
29686 If we change the permute control vector to
29688 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
29696 vr9 = 00000006 00000004 00000002 00000000. */
29699 altivec_expand_vec_perm_const_le (rtx operands
[4])
29703 rtx constv
, unspec
;
29704 rtx target
= operands
[0];
29705 rtx op0
= operands
[1];
29706 rtx op1
= operands
[2];
29707 rtx sel
= operands
[3];
29709 /* Unpack and adjust the constant selector. */
29710 for (i
= 0; i
< 16; ++i
)
29712 rtx e
= XVECEXP (sel
, 0, i
);
29713 unsigned int elt
= 31 - (INTVAL (e
) & 31);
29714 perm
[i
] = GEN_INT (elt
);
29717 /* Expand to a permute, swapping the inputs and using the
29718 adjusted selector. */
29720 op0
= force_reg (V16QImode
, op0
);
29722 op1
= force_reg (V16QImode
, op1
);
29724 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
29725 constv
= force_reg (V16QImode
, constv
);
29726 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
29728 if (!REG_P (target
))
29730 rtx tmp
= gen_reg_rtx (V16QImode
);
29731 emit_move_insn (tmp
, unspec
);
29735 emit_move_insn (target
, unspec
);
29738 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
29739 permute control vector. But here it's not a constant, so we must
29740 generate a vector splat/subtract to do the adjustment. */
29743 altivec_expand_vec_perm_le (rtx operands
[4])
29746 rtx target
= operands
[0];
29747 rtx op0
= operands
[1];
29748 rtx op1
= operands
[2];
29749 rtx sel
= operands
[3];
29752 /* Get everything in regs so the pattern matches. */
29754 op0
= force_reg (V16QImode
, op0
);
29756 op1
= force_reg (V16QImode
, op1
);
29758 sel
= force_reg (V16QImode
, sel
);
29759 if (!REG_P (target
))
29760 tmp
= gen_reg_rtx (V16QImode
);
29762 /* SEL = splat(31) - SEL. */
29763 /* We want to subtract from 31, but we can't vspltisb 31 since
29764 it's out of range. -1 works as well because only the low-order
29765 five bits of the permute control vector elements are used. */
29766 splat
= gen_rtx_VEC_DUPLICATE (V16QImode
,
29767 gen_rtx_CONST_INT (QImode
, -1));
29768 emit_move_insn (tmp
, splat
);
29769 sel
= gen_rtx_MINUS (V16QImode
, tmp
, sel
);
29770 emit_move_insn (tmp
, sel
);
29772 /* Permute with operands reversed and adjusted selector. */
29773 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, tmp
),
29776 /* Copy into target, possibly by way of a register. */
29777 if (!REG_P (target
))
29779 emit_move_insn (tmp
, unspec
);
29783 emit_move_insn (target
, unspec
);
29786 /* Expand an Altivec constant permutation. Return true if we match
29787 an efficient implementation; false to fall back to VPERM. */
29790 altivec_expand_vec_perm_const (rtx operands
[4])
29792 struct altivec_perm_insn
{
29793 HOST_WIDE_INT mask
;
29794 enum insn_code impl
;
29795 unsigned char perm
[16];
29797 static const struct altivec_perm_insn patterns
[] = {
29798 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
,
29799 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
29800 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
,
29801 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
29802 { OPTION_MASK_ALTIVEC
,
29803 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb
: CODE_FOR_altivec_vmrglb
,
29804 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
29805 { OPTION_MASK_ALTIVEC
,
29806 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh
: CODE_FOR_altivec_vmrglh
,
29807 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
29808 { OPTION_MASK_ALTIVEC
,
29809 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw
: CODE_FOR_altivec_vmrglw
,
29810 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
29811 { OPTION_MASK_ALTIVEC
,
29812 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb
: CODE_FOR_altivec_vmrghb
,
29813 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
29814 { OPTION_MASK_ALTIVEC
,
29815 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh
: CODE_FOR_altivec_vmrghh
,
29816 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
29817 { OPTION_MASK_ALTIVEC
,
29818 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw
: CODE_FOR_altivec_vmrghw
,
29819 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
29820 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
29821 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
29822 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
29823 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
29826 unsigned int i
, j
, elt
, which
;
29827 unsigned char perm
[16];
29828 rtx target
, op0
, op1
, sel
, x
;
29831 target
= operands
[0];
29836 /* Unpack the constant selector. */
29837 for (i
= which
= 0; i
< 16; ++i
)
29839 rtx e
= XVECEXP (sel
, 0, i
);
29840 elt
= INTVAL (e
) & 31;
29841 which
|= (elt
< 16 ? 1 : 2);
29845 /* Simplify the constant selector based on operands. */
29849 gcc_unreachable ();
29853 if (!rtx_equal_p (op0
, op1
))
29858 for (i
= 0; i
< 16; ++i
)
29870 /* Look for splat patterns. */
29875 for (i
= 0; i
< 16; ++i
)
29876 if (perm
[i
] != elt
)
29880 if (!BYTES_BIG_ENDIAN
)
29882 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
29888 for (i
= 0; i
< 16; i
+= 2)
29889 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
29893 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
29894 x
= gen_reg_rtx (V8HImode
);
29895 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
29897 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29904 for (i
= 0; i
< 16; i
+= 4)
29906 || perm
[i
+ 1] != elt
+ 1
29907 || perm
[i
+ 2] != elt
+ 2
29908 || perm
[i
+ 3] != elt
+ 3)
29912 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
29913 x
= gen_reg_rtx (V4SImode
);
29914 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
29916 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29922 /* Look for merge and pack patterns. */
29923 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
29927 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
29930 elt
= patterns
[j
].perm
[0];
29931 if (perm
[0] == elt
)
29933 else if (perm
[0] == elt
+ 16)
29937 for (i
= 1; i
< 16; ++i
)
29939 elt
= patterns
[j
].perm
[i
];
29941 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
29942 else if (one_vec
&& elt
>= 16)
29944 if (perm
[i
] != elt
)
29949 enum insn_code icode
= patterns
[j
].impl
;
29950 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
29951 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
29953 /* For little-endian, don't use vpkuwum and vpkuhum if the
29954 underlying vector type is not V4SI and V8HI, respectively.
29955 For example, using vpkuwum with a V8HI picks up the even
29956 halfwords (BE numbering) when the even halfwords (LE
29957 numbering) are what we need. */
29958 if (!BYTES_BIG_ENDIAN
29959 && icode
== CODE_FOR_altivec_vpkuwum
29960 && ((GET_CODE (op0
) == REG
29961 && GET_MODE (op0
) != V4SImode
)
29962 || (GET_CODE (op0
) == SUBREG
29963 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
29965 if (!BYTES_BIG_ENDIAN
29966 && icode
== CODE_FOR_altivec_vpkuhum
29967 && ((GET_CODE (op0
) == REG
29968 && GET_MODE (op0
) != V8HImode
)
29969 || (GET_CODE (op0
) == SUBREG
29970 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
29973 /* For little-endian, the two input operands must be swapped
29974 (or swapped back) to ensure proper right-to-left numbering
29976 if (swapped
^ !BYTES_BIG_ENDIAN
)
29977 x
= op0
, op0
= op1
, op1
= x
;
29978 if (imode
!= V16QImode
)
29980 op0
= gen_lowpart (imode
, op0
);
29981 op1
= gen_lowpart (imode
, op1
);
29983 if (omode
== V16QImode
)
29986 x
= gen_reg_rtx (omode
);
29987 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
29988 if (omode
!= V16QImode
)
29989 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29994 if (!BYTES_BIG_ENDIAN
)
29996 altivec_expand_vec_perm_const_le (operands
);
30003 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
30004 Return true if we match an efficient implementation. */
30007 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
30008 unsigned char perm0
, unsigned char perm1
)
30012 /* If both selectors come from the same operand, fold to single op. */
30013 if ((perm0
& 2) == (perm1
& 2))
30020 /* If both operands are equal, fold to simpler permutation. */
30021 if (rtx_equal_p (op0
, op1
))
30024 perm1
= (perm1
& 1) + 2;
30026 /* If the first selector comes from the second operand, swap. */
30027 else if (perm0
& 2)
30033 x
= op0
, op0
= op1
, op1
= x
;
30035 /* If the second selector does not come from the second operand, fail. */
30036 else if ((perm1
& 2) == 0)
30040 if (target
!= NULL
)
30042 enum machine_mode vmode
, dmode
;
30045 vmode
= GET_MODE (target
);
30046 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
30047 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
30049 /* For little endian, swap operands and invert/swap selectors
30050 to get the correct xxpermdi. The operand swap sets up the
30051 inputs as a little endian array. The selectors are swapped
30052 because they are defined to use big endian ordering. The
30053 selectors are inverted to get the correct doublewords for
30054 little endian ordering. */
30055 if (!BYTES_BIG_ENDIAN
)
30060 n
= perm0
, perm0
= perm1
, perm1
= n
;
30061 x
= op0
, op0
= op1
, op1
= x
;
30064 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
30065 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
30066 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
30067 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
30073 rs6000_expand_vec_perm_const (rtx operands
[4])
30075 rtx target
, op0
, op1
, sel
;
30076 unsigned char perm0
, perm1
;
30078 target
= operands
[0];
30083 /* Unpack the constant selector. */
30084 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
30085 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
30087 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
30090 /* Test whether a constant permutation is supported. */
30093 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
30094 const unsigned char *sel
)
30096 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
30097 if (TARGET_ALTIVEC
)
30100 /* Check for ps_merge* or evmerge* insns. */
30101 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
30102 || (TARGET_SPE
&& vmode
== V2SImode
))
30104 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
30105 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
30106 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
30112 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
30115 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
30116 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
30118 enum machine_mode imode
;
30122 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
30124 imode
= GET_MODE_INNER (vmode
);
30125 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
30126 imode
= mode_for_vector (imode
, nelt
);
30129 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
30130 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
30132 emit_move_insn (target
, x
);
30135 /* Expand an extract even operation. */
30138 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
30140 enum machine_mode vmode
= GET_MODE (target
);
30141 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
30144 for (i
= 0; i
< nelt
; i
++)
30145 perm
[i
] = GEN_INT (i
* 2);
30147 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30150 /* Expand a vector interleave operation. */
30153 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
30155 enum machine_mode vmode
= GET_MODE (target
);
30156 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
30159 high
= (highp
? 0 : nelt
/ 2);
30160 for (i
= 0; i
< nelt
/ 2; i
++)
30162 perm
[i
* 2] = GEN_INT (i
+ high
);
30163 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
30166 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30169 /* Return an RTX representing where to find the function value of a
30170 function returning MODE. */
30172 rs6000_complex_function_value (enum machine_mode mode
)
30174 unsigned int regno
;
30176 enum machine_mode inner
= GET_MODE_INNER (mode
);
30177 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
30179 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30180 regno
= FP_ARG_RETURN
;
30183 regno
= GP_ARG_RETURN
;
30185 /* 32-bit is OK since it'll go in r3/r4. */
30186 if (TARGET_32BIT
&& inner_bytes
>= 4)
30187 return gen_rtx_REG (mode
, regno
);
30190 if (inner_bytes
>= 8)
30191 return gen_rtx_REG (mode
, regno
);
30193 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
30195 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
30196 GEN_INT (inner_bytes
));
30197 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
30200 /* Target hook for TARGET_FUNCTION_VALUE.
30202 On the SPE, both FPs and vectors are returned in r3.
30204 On RS/6000 an integer value is in r3 and a floating-point value is in
30205 fp1, unless -msoft-float. */
30208 rs6000_function_value (const_tree valtype
,
30209 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
30210 bool outgoing ATTRIBUTE_UNUSED
)
30212 enum machine_mode mode
;
30213 unsigned int regno
;
30214 enum machine_mode elt_mode
;
30217 /* Special handling for structs in darwin64. */
30219 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
30221 CUMULATIVE_ARGS valcum
;
30225 valcum
.fregno
= FP_ARG_MIN_REG
;
30226 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
30227 /* Do a trial code generation as if this were going to be passed as
30228 an argument; if any part goes in memory, we return NULL. */
30229 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
30232 /* Otherwise fall through to standard ABI rules. */
30235 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
30236 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype
), valtype
,
30237 &elt_mode
, &n_elts
))
30239 int first_reg
, n_regs
, i
;
30242 if (SCALAR_FLOAT_MODE_P (elt_mode
))
30244 /* _Decimal128 must use even/odd register pairs. */
30245 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30246 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
30250 first_reg
= ALTIVEC_ARG_RETURN
;
30254 par
= gen_rtx_PARALLEL (TYPE_MODE (valtype
), rtvec_alloc (n_elts
));
30255 for (i
= 0; i
< n_elts
; i
++)
30257 rtx r
= gen_rtx_REG (elt_mode
, first_reg
+ i
* n_regs
);
30258 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
30259 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
30265 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
30267 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30268 return gen_rtx_PARALLEL (DImode
,
30270 gen_rtx_EXPR_LIST (VOIDmode
,
30271 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30273 gen_rtx_EXPR_LIST (VOIDmode
,
30274 gen_rtx_REG (SImode
,
30275 GP_ARG_RETURN
+ 1),
30278 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
30280 return gen_rtx_PARALLEL (DCmode
,
30282 gen_rtx_EXPR_LIST (VOIDmode
,
30283 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30285 gen_rtx_EXPR_LIST (VOIDmode
,
30286 gen_rtx_REG (SImode
,
30287 GP_ARG_RETURN
+ 1),
30289 gen_rtx_EXPR_LIST (VOIDmode
,
30290 gen_rtx_REG (SImode
,
30291 GP_ARG_RETURN
+ 2),
30293 gen_rtx_EXPR_LIST (VOIDmode
,
30294 gen_rtx_REG (SImode
,
30295 GP_ARG_RETURN
+ 3),
30299 mode
= TYPE_MODE (valtype
);
30300 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
30301 || POINTER_TYPE_P (valtype
))
30302 mode
= TARGET_32BIT
? SImode
: DImode
;
30304 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30305 /* _Decimal128 must use an even/odd register pair. */
30306 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30307 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
30308 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
30309 regno
= FP_ARG_RETURN
;
30310 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
30311 && targetm
.calls
.split_complex_arg
)
30312 return rs6000_complex_function_value (mode
);
30313 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30314 return register is used in both cases, and we won't see V2DImode/V2DFmode
30315 for pure altivec, combine the two cases. */
30316 else if (TREE_CODE (valtype
) == VECTOR_TYPE
30317 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
30318 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
30319 regno
= ALTIVEC_ARG_RETURN
;
30320 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30321 && (mode
== DFmode
|| mode
== DCmode
30322 || mode
== TFmode
|| mode
== TCmode
))
30323 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30325 regno
= GP_ARG_RETURN
;
30327 return gen_rtx_REG (mode
, regno
);
30330 /* Define how to find the value returned by a library function
30331 assuming the value has mode MODE. */
30333 rs6000_libcall_value (enum machine_mode mode
)
30335 unsigned int regno
;
30337 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
30339 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30340 return gen_rtx_PARALLEL (DImode
,
30342 gen_rtx_EXPR_LIST (VOIDmode
,
30343 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30345 gen_rtx_EXPR_LIST (VOIDmode
,
30346 gen_rtx_REG (SImode
,
30347 GP_ARG_RETURN
+ 1),
30351 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30352 /* _Decimal128 must use an even/odd register pair. */
30353 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30354 else if (SCALAR_FLOAT_MODE_P (mode
)
30355 && TARGET_HARD_FLOAT
&& TARGET_FPRS
30356 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
30357 regno
= FP_ARG_RETURN
;
30358 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30359 return register is used in both cases, and we won't see V2DImode/V2DFmode
30360 for pure altivec, combine the two cases. */
30361 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
30362 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
30363 regno
= ALTIVEC_ARG_RETURN
;
30364 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
30365 return rs6000_complex_function_value (mode
);
30366 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30367 && (mode
== DFmode
|| mode
== DCmode
30368 || mode
== TFmode
|| mode
== TCmode
))
30369 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30371 regno
= GP_ARG_RETURN
;
30373 return gen_rtx_REG (mode
, regno
);
30377 /* Return true if we use LRA instead of reload pass. */
30379 rs6000_lra_p (void)
30381 return rs6000_lra_flag
;
30384 /* Given FROM and TO register numbers, say whether this elimination is allowed.
30385 Frame pointer elimination is automatically handled.
30387 For the RS/6000, if frame pointer elimination is being done, we would like
30388 to convert ap into fp, not sp.
30390 We need r30 if -mminimal-toc was specified, and there are constant pool
30394 rs6000_can_eliminate (const int from
, const int to
)
30396 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
30397 ? ! frame_pointer_needed
30398 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
30399 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
30403 /* Define the offset between two registers, FROM to be eliminated and its
30404 replacement TO, at the start of a routine. */
30406 rs6000_initial_elimination_offset (int from
, int to
)
30408 rs6000_stack_t
*info
= rs6000_stack_info ();
30409 HOST_WIDE_INT offset
;
30411 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30412 offset
= info
->push_p
? 0 : -info
->total_size
;
30413 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30415 offset
= info
->push_p
? 0 : -info
->total_size
;
30416 if (FRAME_GROWS_DOWNWARD
)
30417 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
30419 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
30420 offset
= FRAME_GROWS_DOWNWARD
30421 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
30423 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
30424 offset
= info
->total_size
;
30425 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30426 offset
= info
->push_p
? info
->total_size
: 0;
30427 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
30430 gcc_unreachable ();
30436 rs6000_dwarf_register_span (rtx reg
)
30440 unsigned regno
= REGNO (reg
);
30441 enum machine_mode mode
= GET_MODE (reg
);
30445 && (SPE_VECTOR_MODE (GET_MODE (reg
))
30446 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
30447 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
30452 regno
= REGNO (reg
);
30454 /* The duality of the SPE register size wreaks all kinds of havoc.
30455 This is a way of distinguishing r0 in 32-bits from r0 in
30457 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
30458 gcc_assert (words
<= 4);
30459 for (i
= 0; i
< words
; i
++, regno
++)
30461 if (BYTES_BIG_ENDIAN
)
30463 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
30464 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
30468 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
30469 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
30473 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
30476 /* Fill in sizes for SPE register high parts in table used by unwinder. */
30479 rs6000_init_dwarf_reg_sizes_extra (tree address
)
30484 enum machine_mode mode
= TYPE_MODE (char_type_node
);
30485 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
30486 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
30487 rtx value
= gen_int_mode (4, mode
);
30489 for (i
= 1201; i
< 1232; i
++)
30491 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
30492 HOST_WIDE_INT offset
30493 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
30495 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
30499 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
30502 enum machine_mode mode
= TYPE_MODE (char_type_node
);
30503 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
30504 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
30505 rtx value
= gen_int_mode (16, mode
);
30507 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
30508 The unwinder still needs to know the size of Altivec registers. */
30510 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
30512 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
30513 HOST_WIDE_INT offset
30514 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
30516 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
30521 /* Map internal gcc register numbers to DWARF2 register numbers. */
30524 rs6000_dbx_register_number (unsigned int regno
)
30526 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
30528 if (regno
== LR_REGNO
)
30530 if (regno
== CTR_REGNO
)
30532 if (CR_REGNO_P (regno
))
30533 return regno
- CR0_REGNO
+ 86;
30534 if (regno
== CA_REGNO
)
30535 return 101; /* XER */
30536 if (ALTIVEC_REGNO_P (regno
))
30537 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
30538 if (regno
== VRSAVE_REGNO
)
30540 if (regno
== VSCR_REGNO
)
30542 if (regno
== SPE_ACC_REGNO
)
30544 if (regno
== SPEFSCR_REGNO
)
30546 /* SPE high reg number. We get these values of regno from
30547 rs6000_dwarf_register_span. */
30548 gcc_assert (regno
>= 1200 && regno
< 1232);
30552 /* target hook eh_return_filter_mode */
30553 static enum machine_mode
30554 rs6000_eh_return_filter_mode (void)
30556 return TARGET_32BIT
? SImode
: word_mode
;
30559 /* Target hook for scalar_mode_supported_p. */
30561 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
30563 if (DECIMAL_FLOAT_MODE_P (mode
))
30564 return default_decimal_float_supported_p ();
30566 return default_scalar_mode_supported_p (mode
);
30569 /* Target hook for vector_mode_supported_p. */
30571 rs6000_vector_mode_supported_p (enum machine_mode mode
)
30574 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
30577 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
30580 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
30587 /* Target hook for invalid_arg_for_unprototyped_fn. */
30588 static const char *
30589 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
30591 return (!rs6000_darwin64_abi
30593 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
30594 && (funcdecl
== NULL_TREE
30595 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
30596 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
30597 ? N_("AltiVec argument passed to unprototyped function")
30601 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
30602 setup by using __stack_chk_fail_local hidden function instead of
30603 calling __stack_chk_fail directly. Otherwise it is better to call
30604 __stack_chk_fail directly. */
30606 static tree ATTRIBUTE_UNUSED
30607 rs6000_stack_protect_fail (void)
30609 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
30610 ? default_hidden_stack_protect_fail ()
30611 : default_external_stack_protect_fail ();
30615 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
30616 int num_operands ATTRIBUTE_UNUSED
)
30618 if (rs6000_warn_cell_microcode
)
30621 int insn_code_number
= recog_memoized (insn
);
30622 location_t location
= INSN_LOCATION (insn
);
30624 /* Punt on insns we cannot recognize. */
30625 if (insn_code_number
< 0)
30628 temp
= get_insn_template (insn_code_number
, insn
);
30630 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
30631 warning_at (location
, OPT_mwarn_cell_microcode
,
30632 "emitting microcode insn %s\t[%s] #%d",
30633 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
30634 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
30635 warning_at (location
, OPT_mwarn_cell_microcode
,
30636 "emitting conditional microcode insn %s\t[%s] #%d",
30637 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
30641 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
30644 static unsigned HOST_WIDE_INT
30645 rs6000_asan_shadow_offset (void)
30647 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
30651 /* Mask options that we want to support inside of attribute((target)) and
30652 #pragma GCC target operations. Note, we do not include things like
30653 64/32-bit, endianess, hard/soft floating point, etc. that would have
30654 different calling sequences. */
30656 struct rs6000_opt_mask
{
30657 const char *name
; /* option name */
30658 HOST_WIDE_INT mask
; /* mask to set */
30659 bool invert
; /* invert sense of mask */
30660 bool valid_target
; /* option is a target option */
30663 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
30665 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
30666 { "cmpb", OPTION_MASK_CMPB
, false, true },
30667 { "crypto", OPTION_MASK_CRYPTO
, false, true },
30668 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
30669 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
30670 { "fprnd", OPTION_MASK_FPRND
, false, true },
30671 { "hard-dfp", OPTION_MASK_DFP
, false, true },
30672 { "htm", OPTION_MASK_HTM
, false, true },
30673 { "isel", OPTION_MASK_ISEL
, false, true },
30674 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
30675 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
30676 { "mulhw", OPTION_MASK_MULHW
, false, true },
30677 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
30678 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
30679 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
30680 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
30681 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
30682 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
30683 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
30684 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
30685 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
30686 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
30687 { "string", OPTION_MASK_STRING
, false, true },
30688 { "update", OPTION_MASK_NO_UPDATE
, true , true },
30689 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, false },
30690 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, false },
30691 { "vsx", OPTION_MASK_VSX
, false, true },
30692 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
30693 #ifdef OPTION_MASK_64BIT
30695 { "aix64", OPTION_MASK_64BIT
, false, false },
30696 { "aix32", OPTION_MASK_64BIT
, true, false },
30698 { "64", OPTION_MASK_64BIT
, false, false },
30699 { "32", OPTION_MASK_64BIT
, true, false },
30702 #ifdef OPTION_MASK_EABI
30703 { "eabi", OPTION_MASK_EABI
, false, false },
30705 #ifdef OPTION_MASK_LITTLE_ENDIAN
30706 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
30707 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
30709 #ifdef OPTION_MASK_RELOCATABLE
30710 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
30712 #ifdef OPTION_MASK_STRICT_ALIGN
30713 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
30715 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
30716 { "string", OPTION_MASK_STRING
, false, false },
30719 /* Builtin mask mapping for printing the flags. */
30720 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
30722 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
30723 { "vsx", RS6000_BTM_VSX
, false, false },
30724 { "spe", RS6000_BTM_SPE
, false, false },
30725 { "paired", RS6000_BTM_PAIRED
, false, false },
30726 { "fre", RS6000_BTM_FRE
, false, false },
30727 { "fres", RS6000_BTM_FRES
, false, false },
30728 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
30729 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
30730 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
30731 { "cell", RS6000_BTM_CELL
, false, false },
30732 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
30733 { "crypto", RS6000_BTM_CRYPTO
, false, false },
30734 { "htm", RS6000_BTM_HTM
, false, false },
30737 /* Option variables that we want to support inside attribute((target)) and
30738 #pragma GCC target operations. */
30740 struct rs6000_opt_var
{
30741 const char *name
; /* option name */
30742 size_t global_offset
; /* offset of the option in global_options. */
30743 size_t target_offset
; /* offset of the option in target optiosn. */
30746 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
30749 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
30750 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
30751 { "avoid-indexed-addresses",
30752 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
30753 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
30755 offsetof (struct gcc_options
, x_rs6000_paired_float
),
30756 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
30758 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
30759 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
30762 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
30763 parsing. Return true if there were no errors. */
30766 rs6000_inner_target_options (tree args
, bool attr_p
)
30770 if (args
== NULL_TREE
)
30773 else if (TREE_CODE (args
) == STRING_CST
)
30775 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
30778 while ((q
= strtok (p
, ",")) != NULL
)
30780 bool error_p
= false;
30781 bool not_valid_p
= false;
30782 const char *cpu_opt
= NULL
;
30785 if (strncmp (q
, "cpu=", 4) == 0)
30787 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
30788 if (cpu_index
>= 0)
30789 rs6000_cpu_index
= cpu_index
;
30796 else if (strncmp (q
, "tune=", 5) == 0)
30798 int tune_index
= rs6000_cpu_name_lookup (q
+5);
30799 if (tune_index
>= 0)
30800 rs6000_tune_index
= tune_index
;
30810 bool invert
= false;
30814 if (strncmp (r
, "no-", 3) == 0)
30820 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
30821 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
30823 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
30825 if (!rs6000_opt_masks
[i
].valid_target
)
30826 not_valid_p
= true;
30830 rs6000_isa_flags_explicit
|= mask
;
30832 /* VSX needs altivec, so -mvsx automagically sets
30834 if (mask
== OPTION_MASK_VSX
&& !invert
)
30835 mask
|= OPTION_MASK_ALTIVEC
;
30837 if (rs6000_opt_masks
[i
].invert
)
30841 rs6000_isa_flags
&= ~mask
;
30843 rs6000_isa_flags
|= mask
;
30848 if (error_p
&& !not_valid_p
)
30850 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
30851 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
30853 size_t j
= rs6000_opt_vars
[i
].global_offset
;
30854 *((int *) ((char *)&global_options
+ j
)) = !invert
;
30863 const char *eprefix
, *esuffix
;
30868 eprefix
= "__attribute__((__target__(";
30873 eprefix
= "#pragma GCC target ";
30878 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
30880 else if (not_valid_p
)
30881 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
30883 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
30888 else if (TREE_CODE (args
) == TREE_LIST
)
30892 tree value
= TREE_VALUE (args
);
30895 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
30899 args
= TREE_CHAIN (args
);
30901 while (args
!= NULL_TREE
);
30905 gcc_unreachable ();
30910 /* Print out the target options as a list for -mdebug=target. */
30913 rs6000_debug_target_options (tree args
, const char *prefix
)
30915 if (args
== NULL_TREE
)
30916 fprintf (stderr
, "%s<NULL>", prefix
);
30918 else if (TREE_CODE (args
) == STRING_CST
)
30920 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
30923 while ((q
= strtok (p
, ",")) != NULL
)
30926 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
30931 else if (TREE_CODE (args
) == TREE_LIST
)
30935 tree value
= TREE_VALUE (args
);
30938 rs6000_debug_target_options (value
, prefix
);
30941 args
= TREE_CHAIN (args
);
30943 while (args
!= NULL_TREE
);
30947 gcc_unreachable ();
30953 /* Hook to validate attribute((target("..."))). */
30956 rs6000_valid_attribute_p (tree fndecl
,
30957 tree
ARG_UNUSED (name
),
30961 struct cl_target_option cur_target
;
30963 tree old_optimize
= build_optimization_node (&global_options
);
30964 tree new_target
, new_optimize
;
30965 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
30967 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
30969 if (TARGET_DEBUG_TARGET
)
30971 tree tname
= DECL_NAME (fndecl
);
30972 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
30974 fprintf (stderr
, "function: %.*s\n",
30975 (int) IDENTIFIER_LENGTH (tname
),
30976 IDENTIFIER_POINTER (tname
));
30978 fprintf (stderr
, "function: unknown\n");
30980 fprintf (stderr
, "args:");
30981 rs6000_debug_target_options (args
, " ");
30982 fprintf (stderr
, "\n");
30985 fprintf (stderr
, "flags: 0x%x\n", flags
);
30987 fprintf (stderr
, "--------------------\n");
30990 old_optimize
= build_optimization_node (&global_options
);
30991 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
30993 /* If the function changed the optimization levels as well as setting target
30994 options, start with the optimizations specified. */
30995 if (func_optimize
&& func_optimize
!= old_optimize
)
30996 cl_optimization_restore (&global_options
,
30997 TREE_OPTIMIZATION (func_optimize
));
30999 /* The target attributes may also change some optimization flags, so update
31000 the optimization options if necessary. */
31001 cl_target_option_save (&cur_target
, &global_options
);
31002 rs6000_cpu_index
= rs6000_tune_index
= -1;
31003 ret
= rs6000_inner_target_options (args
, true);
31005 /* Set up any additional state. */
31008 ret
= rs6000_option_override_internal (false);
31009 new_target
= build_target_option_node (&global_options
);
31014 new_optimize
= build_optimization_node (&global_options
);
31021 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
31023 if (old_optimize
!= new_optimize
)
31024 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
31027 cl_target_option_restore (&global_options
, &cur_target
);
31029 if (old_optimize
!= new_optimize
)
31030 cl_optimization_restore (&global_options
,
31031 TREE_OPTIMIZATION (old_optimize
));
31037 /* Hook to validate the current #pragma GCC target and set the state, and
31038 update the macros based on what was changed. If ARGS is NULL, then
31039 POP_TARGET is used to reset the options. */
31042 rs6000_pragma_target_parse (tree args
, tree pop_target
)
31044 tree prev_tree
= build_target_option_node (&global_options
);
31046 struct cl_target_option
*prev_opt
, *cur_opt
;
31047 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
31048 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
31050 if (TARGET_DEBUG_TARGET
)
31052 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
31053 fprintf (stderr
, "args:");
31054 rs6000_debug_target_options (args
, " ");
31055 fprintf (stderr
, "\n");
31059 fprintf (stderr
, "pop_target:\n");
31060 debug_tree (pop_target
);
31063 fprintf (stderr
, "pop_target: <NULL>\n");
31065 fprintf (stderr
, "--------------------\n");
31070 cur_tree
= ((pop_target
)
31072 : target_option_default_node
);
31073 cl_target_option_restore (&global_options
,
31074 TREE_TARGET_OPTION (cur_tree
));
31078 rs6000_cpu_index
= rs6000_tune_index
= -1;
31079 if (!rs6000_inner_target_options (args
, false)
31080 || !rs6000_option_override_internal (false)
31081 || (cur_tree
= build_target_option_node (&global_options
))
31084 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
31085 fprintf (stderr
, "invalid pragma\n");
31091 target_option_current_node
= cur_tree
;
31093 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
31094 change the macros that are defined. */
31095 if (rs6000_target_modify_macros_ptr
)
31097 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
31098 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
31099 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
31101 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
31102 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
31103 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
31105 diff_bumask
= (prev_bumask
^ cur_bumask
);
31106 diff_flags
= (prev_flags
^ cur_flags
);
31108 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
31110 /* Delete old macros. */
31111 rs6000_target_modify_macros_ptr (false,
31112 prev_flags
& diff_flags
,
31113 prev_bumask
& diff_bumask
);
31115 /* Define new macros. */
31116 rs6000_target_modify_macros_ptr (true,
31117 cur_flags
& diff_flags
,
31118 cur_bumask
& diff_bumask
);
31126 /* Remember the last target of rs6000_set_current_function. */
31127 static GTY(()) tree rs6000_previous_fndecl
;
31129 /* Establish appropriate back-end context for processing the function
31130 FNDECL. The argument might be NULL to indicate processing at top
31131 level, outside of any function scope. */
31133 rs6000_set_current_function (tree fndecl
)
31135 tree old_tree
= (rs6000_previous_fndecl
31136 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
31139 tree new_tree
= (fndecl
31140 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
31143 if (TARGET_DEBUG_TARGET
)
31145 bool print_final
= false;
31146 fprintf (stderr
, "\n==================== rs6000_set_current_function");
31149 fprintf (stderr
, ", fndecl %s (%p)",
31150 (DECL_NAME (fndecl
)
31151 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
31152 : "<unknown>"), (void *)fndecl
);
31154 if (rs6000_previous_fndecl
)
31155 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
31157 fprintf (stderr
, "\n");
31160 fprintf (stderr
, "\nnew fndecl target specific options:\n");
31161 debug_tree (new_tree
);
31162 print_final
= true;
31167 fprintf (stderr
, "\nold fndecl target specific options:\n");
31168 debug_tree (old_tree
);
31169 print_final
= true;
31173 fprintf (stderr
, "--------------------\n");
31176 /* Only change the context if the function changes. This hook is called
31177 several times in the course of compiling a function, and we don't want to
31178 slow things down too much or call target_reinit when it isn't safe. */
31179 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
31181 rs6000_previous_fndecl
= fndecl
;
31182 if (old_tree
== new_tree
)
31187 cl_target_option_restore (&global_options
,
31188 TREE_TARGET_OPTION (new_tree
));
31194 struct cl_target_option
*def
31195 = TREE_TARGET_OPTION (target_option_current_node
);
31197 cl_target_option_restore (&global_options
, def
);
31204 /* Save the current options */
31207 rs6000_function_specific_save (struct cl_target_option
*ptr
,
31208 struct gcc_options
*opts
)
31210 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
31211 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
31214 /* Restore the current options */
31217 rs6000_function_specific_restore (struct gcc_options
*opts
,
31218 struct cl_target_option
*ptr
)
31221 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
31222 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
31223 (void) rs6000_option_override_internal (false);
31226 /* Print the current options */
31229 rs6000_function_specific_print (FILE *file
, int indent
,
31230 struct cl_target_option
*ptr
)
31232 rs6000_print_isa_options (file
, indent
, "Isa options set",
31233 ptr
->x_rs6000_isa_flags
);
31235 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
31236 ptr
->x_rs6000_isa_flags_explicit
);
31239 /* Helper function to print the current isa or misc options on a line. */
31242 rs6000_print_options_internal (FILE *file
,
31244 const char *string
,
31245 HOST_WIDE_INT flags
,
31246 const char *prefix
,
31247 const struct rs6000_opt_mask
*opts
,
31248 size_t num_elements
)
31251 size_t start_column
= 0;
31253 size_t max_column
= 76;
31254 const char *comma
= "";
31257 start_column
+= fprintf (file
, "%*s", indent
, "");
31261 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
31265 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
31267 /* Print the various mask options. */
31268 cur_column
= start_column
;
31269 for (i
= 0; i
< num_elements
; i
++)
31271 if ((flags
& opts
[i
].mask
) != 0)
31273 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
31274 size_t len
= (strlen (comma
)
31277 + strlen (rs6000_opt_masks
[i
].name
));
31280 if (cur_column
> max_column
)
31282 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
31283 cur_column
= start_column
+ len
;
31287 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
31288 rs6000_opt_masks
[i
].name
);
31289 flags
&= ~ opts
[i
].mask
;
31294 fputs ("\n", file
);
31297 /* Helper function to print the current isa options on a line. */
31300 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
31301 HOST_WIDE_INT flags
)
31303 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
31304 &rs6000_opt_masks
[0],
31305 ARRAY_SIZE (rs6000_opt_masks
));
31309 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
31310 HOST_WIDE_INT flags
)
31312 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
31313 &rs6000_builtin_mask_names
[0],
31314 ARRAY_SIZE (rs6000_builtin_mask_names
));
31318 /* Hook to determine if one function can safely inline another. */
31321 rs6000_can_inline_p (tree caller
, tree callee
)
31324 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
31325 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
31327 /* If callee has no option attributes, then it is ok to inline. */
31331 /* If caller has no option attributes, but callee does then it is not ok to
31333 else if (!caller_tree
)
31338 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
31339 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
31341 /* Callee's options should a subset of the caller's, i.e. a vsx function
31342 can inline an altivec function but a non-vsx function can't inline a
31344 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
31345 == callee_opts
->x_rs6000_isa_flags
)
31349 if (TARGET_DEBUG_TARGET
)
31350 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
31351 (DECL_NAME (caller
)
31352 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
31354 (DECL_NAME (callee
)
31355 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
31357 (ret
? "can" : "cannot"));
31362 /* Allocate a stack temp and fixup the address so it meets the particular
31363 memory requirements (either offetable or REG+REG addressing). */
31366 rs6000_allocate_stack_temp (enum machine_mode mode
,
31367 bool offsettable_p
,
31370 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
31371 rtx addr
= XEXP (stack
, 0);
31372 int strict_p
= (reload_in_progress
|| reload_completed
);
31374 if (!legitimate_indirect_address_p (addr
, strict_p
))
31377 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
31378 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
31380 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
31381 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
31387 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
31388 to such a form to deal with memory reference instructions like STFIWX that
31389 only take reg+reg addressing. */
31392 rs6000_address_for_fpconvert (rtx x
)
31394 int strict_p
= (reload_in_progress
|| reload_completed
);
31397 gcc_assert (MEM_P (x
));
31398 addr
= XEXP (x
, 0);
31399 if (! legitimate_indirect_address_p (addr
, strict_p
)
31400 && ! legitimate_indexed_address_p (addr
, strict_p
))
31402 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
31404 rtx reg
= XEXP (addr
, 0);
31405 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
31406 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
31407 gcc_assert (REG_P (reg
));
31408 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
31411 else if (GET_CODE (addr
) == PRE_MODIFY
)
31413 rtx reg
= XEXP (addr
, 0);
31414 rtx expr
= XEXP (addr
, 1);
31415 gcc_assert (REG_P (reg
));
31416 gcc_assert (GET_CODE (expr
) == PLUS
);
31417 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
31421 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
31427 /* Given a memory reference, if it is not in the form for altivec memory
31428 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
31429 convert to the altivec format. */
31432 rs6000_address_for_altivec (rtx x
)
31434 gcc_assert (MEM_P (x
));
31435 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
31437 rtx addr
= XEXP (x
, 0);
31438 int strict_p
= (reload_in_progress
|| reload_completed
);
31440 if (!legitimate_indexed_address_p (addr
, strict_p
)
31441 && !legitimate_indirect_address_p (addr
, strict_p
))
31442 addr
= copy_to_mode_reg (Pmode
, addr
);
31444 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
31445 x
= change_address (x
, GET_MODE (x
), addr
);
31451 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
31453 On the RS/6000, all integer constants are acceptable, most won't be valid
31454 for particular insns, though. Only easy FP constants are acceptable. */
31457 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
31459 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
31462 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
31463 || GET_MODE (x
) == VOIDmode
31464 || (TARGET_POWERPC64
&& mode
== DImode
)
31465 || easy_fp_constant (x
, mode
)
31466 || easy_vector_constant (x
, mode
));
31471 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
31474 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
31476 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
31477 rtx toc_load
= NULL_RTX
;
31478 rtx toc_restore
= NULL_RTX
;
31480 rtx abi_reg
= NULL_RTX
;
31485 /* Handle longcall attributes. */
31486 if (INTVAL (cookie
) & CALL_LONG
)
31487 func_desc
= rs6000_longcall_ref (func_desc
);
31489 /* Handle indirect calls. */
31490 if (GET_CODE (func_desc
) != SYMBOL_REF
31491 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
31493 /* Save the TOC into its reserved slot before the call,
31494 and prepare to restore it after the call. */
31495 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
31496 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
31497 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
31498 gen_rtx_PLUS (Pmode
, stack_ptr
,
31499 stack_toc_offset
));
31500 toc_restore
= gen_rtx_SET (VOIDmode
, toc_reg
, stack_toc_mem
);
31502 /* Can we optimize saving the TOC in the prologue or
31503 do we need to do it at every call? */
31504 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
31505 cfun
->machine
->save_toc_in_prologue
= true;
31508 MEM_VOLATILE_P (stack_toc_mem
) = 1;
31509 emit_move_insn (stack_toc_mem
, toc_reg
);
31512 if (DEFAULT_ABI
== ABI_ELFv2
)
31514 /* A function pointer in the ELFv2 ABI is just a plain address, but
31515 the ABI requires it to be loaded into r12 before the call. */
31516 func_addr
= gen_rtx_REG (Pmode
, 12);
31517 emit_move_insn (func_addr
, func_desc
);
31518 abi_reg
= func_addr
;
31522 /* A function pointer under AIX is a pointer to a data area whose
31523 first word contains the actual address of the function, whose
31524 second word contains a pointer to its TOC, and whose third word
31525 contains a value to place in the static chain register (r11).
31526 Note that if we load the static chain, our "trampoline" need
31527 not have any executable code. */
31529 /* Load up address of the actual function. */
31530 func_desc
= force_reg (Pmode
, func_desc
);
31531 func_addr
= gen_reg_rtx (Pmode
);
31532 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
31534 /* Prepare to load the TOC of the called function. Note that the
31535 TOC load must happen immediately before the actual call so
31536 that unwinding the TOC registers works correctly. See the
31537 comment in frob_update_context. */
31538 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
31539 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
31540 gen_rtx_PLUS (Pmode
, func_desc
,
31542 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
31544 /* If we have a static chain, load it up. */
31545 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
31547 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
31548 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
31549 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
31550 gen_rtx_PLUS (Pmode
, func_desc
,
31552 emit_move_insn (sc_reg
, func_sc_mem
);
31559 /* Direct calls use the TOC: for local calls, the callee will
31560 assume the TOC register is set; for non-local calls, the
31561 PLT stub needs the TOC register. */
31563 func_addr
= func_desc
;
31566 /* Create the call. */
31567 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
31568 if (value
!= NULL_RTX
)
31569 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
31573 call
[n_call
++] = toc_load
;
31575 call
[n_call
++] = toc_restore
;
31577 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
31579 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
31580 insn
= emit_call_insn (insn
);
31582 /* Mention all registers defined by the ABI to hold information
31583 as uses in CALL_INSN_FUNCTION_USAGE. */
31585 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
31588 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
31591 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
31596 gcc_assert (INTVAL (cookie
) == 0);
31598 /* Create the call. */
31599 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
31600 if (value
!= NULL_RTX
)
31601 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
31603 call
[1] = simple_return_rtx
;
31605 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
31606 insn
= emit_call_insn (insn
);
31608 /* Note use of the TOC register. */
31609 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
31610 /* We need to also mark a use of the link register since the function we
31611 sibling-call to will use it to return to our caller. */
31612 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
31615 /* Return whether we need to always update the saved TOC pointer when we update
31616 the stack pointer. */
31619 rs6000_save_toc_in_prologue_p (void)
31621 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
31624 #ifdef HAVE_GAS_HIDDEN
31625 # define USE_HIDDEN_LINKONCE 1
31627 # define USE_HIDDEN_LINKONCE 0
31630 /* Fills in the label name that should be used for a 476 link stack thunk. */
31633 get_ppc476_thunk_name (char name
[32])
31635 gcc_assert (TARGET_LINK_STACK
);
31637 if (USE_HIDDEN_LINKONCE
)
31638 sprintf (name
, "__ppc476.get_thunk");
31640 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
31643 /* This function emits the simple thunk routine that is used to preserve
31644 the link stack on the 476 cpu. */
31646 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
31648 rs6000_code_end (void)
31653 if (!TARGET_LINK_STACK
)
31656 get_ppc476_thunk_name (name
);
31658 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
31659 build_function_type_list (void_type_node
, NULL_TREE
));
31660 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
31661 NULL_TREE
, void_type_node
);
31662 TREE_PUBLIC (decl
) = 1;
31663 TREE_STATIC (decl
) = 1;
31666 if (USE_HIDDEN_LINKONCE
)
31668 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
31669 targetm
.asm_out
.unique_section (decl
, 0);
31670 switch_to_section (get_named_section (decl
, NULL
, 0));
31671 DECL_WEAK (decl
) = 1;
31672 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
31673 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
31674 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
31675 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
31680 switch_to_section (text_section
);
31681 ASM_OUTPUT_LABEL (asm_out_file
, name
);
31684 DECL_INITIAL (decl
) = make_node (BLOCK
);
31685 current_function_decl
= decl
;
31686 init_function_start (decl
);
31687 first_function_block_is_cold
= false;
31688 /* Make sure unwind info is emitted for the thunk if needed. */
31689 final_start_function (emit_barrier (), asm_out_file
, 1);
31691 fputs ("\tblr\n", asm_out_file
);
31693 final_end_function ();
31694 init_insn_lengths ();
31695 free_after_compilation (cfun
);
31697 current_function_decl
= NULL
;
31700 /* Add r30 to hard reg set if the prologue sets it up and it is not
31701 pic_offset_table_rtx. */
31704 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
31706 if (!TARGET_SINGLE_PIC_BASE
31708 && TARGET_MINIMAL_TOC
31709 && get_pool_size () != 0)
31710 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
31714 /* Helper function for rs6000_split_logical to emit a logical instruction after
31715 spliting the operation to single GPR registers.
31717 DEST is the destination register.
31718 OP1 and OP2 are the input source registers.
31719 CODE is the base operation (AND, IOR, XOR, NOT).
31720 MODE is the machine mode.
31721 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31722 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31723 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31724 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31725 formation of the AND instructions. */
31728 rs6000_split_logical_inner (rtx dest
,
31731 enum rtx_code code
,
31732 enum machine_mode mode
,
31733 bool complement_final_p
,
31734 bool complement_op1_p
,
31735 bool complement_op2_p
,
31741 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
31742 if (op2
&& GET_CODE (op2
) == CONST_INT
31743 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
31744 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
31746 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
31747 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
31749 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
31754 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
31758 else if (value
== mask
)
31760 if (!rtx_equal_p (dest
, op1
))
31761 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
31766 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
31767 into separate ORI/ORIS or XORI/XORIS instrucitons. */
31768 else if (code
== IOR
|| code
== XOR
)
31772 if (!rtx_equal_p (dest
, op1
))
31773 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
31779 if (complement_op1_p
)
31780 op1
= gen_rtx_NOT (mode
, op1
);
31782 if (complement_op2_p
)
31783 op2
= gen_rtx_NOT (mode
, op2
);
31785 bool_rtx
= ((code
== NOT
)
31786 ? gen_rtx_NOT (mode
, op1
)
31787 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
31789 if (complement_final_p
)
31790 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
31792 set_rtx
= gen_rtx_SET (VOIDmode
, dest
, bool_rtx
);
31794 /* Is this AND with an explicit clobber? */
31797 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, clobber_reg
);
31798 set_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set_rtx
, clobber
));
31801 emit_insn (set_rtx
);
31805 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
31806 operations are split immediately during RTL generation to allow for more
31807 optimizations of the AND/IOR/XOR.
31809 OPERANDS is an array containing the destination and two input operands.
31810 CODE is the base operation (AND, IOR, XOR, NOT).
31811 MODE is the machine mode.
31812 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31813 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31814 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31815 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31816 formation of the AND instructions. */
31819 rs6000_split_logical_di (rtx operands
[3],
31820 enum rtx_code code
,
31821 bool complement_final_p
,
31822 bool complement_op1_p
,
31823 bool complement_op2_p
,
31826 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
31827 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
31828 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
31829 enum hi_lo
{ hi
= 0, lo
= 1 };
31830 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
31833 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
31834 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
31835 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
31836 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
31839 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
31842 if (GET_CODE (operands
[2]) != CONST_INT
)
31844 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
31845 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
31849 HOST_WIDE_INT value
= INTVAL (operands
[2]);
31850 HOST_WIDE_INT value_hi_lo
[2];
31852 gcc_assert (!complement_final_p
);
31853 gcc_assert (!complement_op1_p
);
31854 gcc_assert (!complement_op2_p
);
31856 value_hi_lo
[hi
] = value
>> 32;
31857 value_hi_lo
[lo
] = value
& lower_32bits
;
31859 for (i
= 0; i
< 2; i
++)
31861 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
31863 if (sub_value
& sign_bit
)
31864 sub_value
|= upper_32bits
;
31866 op2_hi_lo
[i
] = GEN_INT (sub_value
);
31868 /* If this is an AND instruction, check to see if we need to load
31869 the value in a register. */
31870 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
31871 && !and_operand (op2_hi_lo
[i
], SImode
))
31872 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
31877 for (i
= 0; i
< 2; i
++)
31879 /* Split large IOR/XOR operations. */
31880 if ((code
== IOR
|| code
== XOR
)
31881 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
31882 && !complement_final_p
31883 && !complement_op1_p
31884 && !complement_op2_p
31885 && clobber_reg
== NULL_RTX
31886 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
31888 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
31889 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
31890 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
31891 rtx tmp
= gen_reg_rtx (SImode
);
31893 /* Make sure the constant is sign extended. */
31894 if ((hi_16bits
& sign_bit
) != 0)
31895 hi_16bits
|= upper_32bits
;
31897 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
31898 code
, SImode
, false, false, false,
31901 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
31902 code
, SImode
, false, false, false,
31906 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
31907 code
, SImode
, complement_final_p
,
31908 complement_op1_p
, complement_op2_p
,
31915 /* Split the insns that make up boolean operations operating on multiple GPR
31916 registers. The boolean MD patterns ensure that the inputs either are
31917 exactly the same as the output registers, or there is no overlap.
31919 OPERANDS is an array containing the destination and two input operands.
31920 CODE is the base operation (AND, IOR, XOR, NOT).
31921 MODE is the machine mode.
31922 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31923 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31924 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31925 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31926 formation of the AND instructions. */
31929 rs6000_split_logical (rtx operands
[3],
31930 enum rtx_code code
,
31931 bool complement_final_p
,
31932 bool complement_op1_p
,
31933 bool complement_op2_p
,
31936 enum machine_mode mode
= GET_MODE (operands
[0]);
31937 enum machine_mode sub_mode
;
31939 int sub_size
, regno0
, regno1
, nregs
, i
;
31941 /* If this is DImode, use the specialized version that can run before
31942 register allocation. */
31943 if (mode
== DImode
&& !TARGET_POWERPC64
)
31945 rs6000_split_logical_di (operands
, code
, complement_final_p
,
31946 complement_op1_p
, complement_op2_p
,
31953 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
31954 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
31955 sub_size
= GET_MODE_SIZE (sub_mode
);
31956 regno0
= REGNO (op0
);
31957 regno1
= REGNO (op1
);
31959 gcc_assert (reload_completed
);
31960 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31961 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31963 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
31964 gcc_assert (nregs
> 1);
31966 if (op2
&& REG_P (op2
))
31967 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31969 for (i
= 0; i
< nregs
; i
++)
31971 int offset
= i
* sub_size
;
31972 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
31973 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
31974 rtx sub_op2
= ((code
== NOT
)
31976 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
31978 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
31979 complement_final_p
, complement_op1_p
,
31980 complement_op2_p
, clobber_reg
);
31987 /* Return true if the peephole2 can combine a load involving a combination of
31988 an addis instruction and a load with an offset that can be fused together on
31992 operands[0] register set with addis
31993 operands[1] value set via addis
31994 operands[2] target register being loaded
31995 operands[3] D-form memory reference using operands[0].
31997 In addition, we are passed a boolean that is true if this is a peephole2,
31998 and we can use see if the addis_reg is dead after the insn and can be
31999 replaced by the target register. */
32002 fusion_gpr_load_p (rtx
*operands
, bool peep2_p
)
32004 rtx addis_reg
= operands
[0];
32005 rtx addis_value
= operands
[1];
32006 rtx target
= operands
[2];
32007 rtx mem
= operands
[3];
32011 /* Validate arguments. */
32012 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
32015 if (!base_reg_operand (target
, GET_MODE (target
)))
32018 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
32021 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
32024 /* Allow sign/zero extension. */
32025 if (GET_CODE (mem
) == ZERO_EXTEND
32026 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
32027 mem
= XEXP (mem
, 0);
32032 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
32033 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32036 /* Validate that the register used to load the high value is either the
32037 register being loaded, or we can safely replace its use in a peephole2.
32039 If this is a peephole2, we assume that there are 2 instructions in the
32040 peephole (addis and load), so we want to check if the target register was
32041 not used in the memory address and the register to hold the addis result
32042 is dead after the peephole. */
32043 if (REGNO (addis_reg
) != REGNO (target
))
32048 if (reg_mentioned_p (target
, mem
))
32051 if (!peep2_reg_dead_p (2, addis_reg
))
32055 base_reg
= XEXP (addr
, 0);
32056 return REGNO (addis_reg
) == REGNO (base_reg
);
32059 /* During the peephole2 pass, adjust and expand the insns for a load fusion
32060 sequence. We adjust the addis register to use the target register. If the
32061 load sign extends, we adjust the code to do the zero extending load, and an
32062 explicit sign extension later since the fusion only covers zero extending
32066 operands[0] register set with addis (to be replaced with target)
32067 operands[1] value set via addis
32068 operands[2] target register being loaded
32069 operands[3] D-form memory reference using operands[0]. */
32072 expand_fusion_gpr_load (rtx
*operands
)
32074 rtx addis_value
= operands
[1];
32075 rtx target
= operands
[2];
32076 rtx orig_mem
= operands
[3];
32077 rtx new_addr
, new_mem
, orig_addr
, offset
;
32078 enum rtx_code plus_or_lo_sum
;
32079 enum machine_mode target_mode
= GET_MODE (target
);
32080 enum machine_mode extend_mode
= target_mode
;
32081 enum machine_mode ptr_mode
= Pmode
;
32082 enum rtx_code extend
= UNKNOWN
;
32083 rtx addis_reg
= ((ptr_mode
== target_mode
)
32085 : simplify_subreg (ptr_mode
, target
, target_mode
, 0));
32087 if (GET_CODE (orig_mem
) == ZERO_EXTEND
32088 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
32090 extend
= GET_CODE (orig_mem
);
32091 orig_mem
= XEXP (orig_mem
, 0);
32092 target_mode
= GET_MODE (orig_mem
);
32095 gcc_assert (MEM_P (orig_mem
));
32097 orig_addr
= XEXP (orig_mem
, 0);
32098 plus_or_lo_sum
= GET_CODE (orig_addr
);
32099 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
32101 offset
= XEXP (orig_addr
, 1);
32102 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_reg
, offset
);
32103 new_mem
= change_address (orig_mem
, target_mode
, new_addr
);
32105 if (extend
!= UNKNOWN
)
32106 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
32108 emit_insn (gen_rtx_SET (VOIDmode
, addis_reg
, addis_value
));
32109 emit_insn (gen_rtx_SET (VOIDmode
, target
, new_mem
));
32111 if (extend
== SIGN_EXTEND
)
32113 int sub_off
= ((BYTES_BIG_ENDIAN
)
32114 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
32117 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
32119 emit_insn (gen_rtx_SET (VOIDmode
, target
,
32120 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
32126 /* Return a string to fuse an addis instruction with a gpr load to the same
32127 register that we loaded up the addis instruction. The code is complicated,
32128 so we call output_asm_insn directly, and just return "".
32131 operands[0] register set with addis (must be same reg as target).
32132 operands[1] value set via addis
32133 operands[2] target register being loaded
32134 operands[3] D-form memory reference using operands[0]. */
32137 emit_fusion_gpr_load (rtx
*operands
)
32139 rtx addis_reg
= operands
[0];
32140 rtx addis_value
= operands
[1];
32141 rtx target
= operands
[2];
32142 rtx mem
= operands
[3];
32146 const char *addis_str
= NULL
;
32147 const char *load_str
= NULL
;
32148 const char *extend_insn
= NULL
;
32149 const char *mode_name
= NULL
;
32150 char insn_template
[80];
32151 enum machine_mode mode
;
32152 const char *comment_str
= ASM_COMMENT_START
;
32153 bool sign_p
= false;
32155 gcc_assert (REG_P (addis_reg
) && REG_P (target
));
32156 gcc_assert (REGNO (addis_reg
) == REGNO (target
));
32158 if (*comment_str
== ' ')
32161 /* Allow sign/zero extension. */
32162 if (GET_CODE (mem
) == ZERO_EXTEND
)
32163 mem
= XEXP (mem
, 0);
32165 else if (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
)
32168 mem
= XEXP (mem
, 0);
32171 gcc_assert (MEM_P (mem
));
32172 addr
= XEXP (mem
, 0);
32173 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32174 gcc_unreachable ();
32176 load_offset
= XEXP (addr
, 1);
32178 /* Now emit the load instruction to the same register. */
32179 mode
= GET_MODE (mem
);
32183 mode_name
= "char";
32185 extend_insn
= "extsb %0,%0";
32189 mode_name
= "short";
32191 extend_insn
= "extsh %0,%0";
32197 extend_insn
= "extsw %0,%0";
32201 if (TARGET_POWERPC64
)
32203 mode_name
= "long";
32207 gcc_unreachable ();
32211 gcc_unreachable ();
32214 /* Emit the addis instruction. */
32215 fuse_ops
[0] = target
;
32216 if (satisfies_constraint_L (addis_value
))
32218 fuse_ops
[1] = addis_value
;
32219 addis_str
= "lis %0,%v1";
32222 else if (GET_CODE (addis_value
) == PLUS
)
32224 rtx op0
= XEXP (addis_value
, 0);
32225 rtx op1
= XEXP (addis_value
, 1);
32227 if (REG_P (op0
) && CONST_INT_P (op1
)
32228 && satisfies_constraint_L (op1
))
32232 addis_str
= "addis %0,%1,%v2";
32236 else if (GET_CODE (addis_value
) == HIGH
)
32238 rtx value
= XEXP (addis_value
, 0);
32239 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
32241 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
32242 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
32244 addis_str
= "addis %0,%2,%1@toc@ha";
32246 else if (TARGET_XCOFF
)
32247 addis_str
= "addis %0,%1@u(%2)";
32250 gcc_unreachable ();
32253 else if (GET_CODE (value
) == PLUS
)
32255 rtx op0
= XEXP (value
, 0);
32256 rtx op1
= XEXP (value
, 1);
32258 if (GET_CODE (op0
) == UNSPEC
32259 && XINT (op0
, 1) == UNSPEC_TOCREL
32260 && CONST_INT_P (op1
))
32262 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
32263 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
32266 addis_str
= "addis %0,%2,%1+%3@toc@ha";
32268 else if (TARGET_XCOFF
)
32269 addis_str
= "addis %0,%1+%3@u(%2)";
32272 gcc_unreachable ();
32276 else if (satisfies_constraint_L (value
))
32278 fuse_ops
[1] = value
;
32279 addis_str
= "lis %0,%v1";
32282 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
32284 fuse_ops
[1] = value
;
32285 addis_str
= "lis %0,%1@ha";
32290 fatal_insn ("Could not generate addis value for fusion", addis_value
);
32292 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
32293 comment_str
, mode_name
);
32294 output_asm_insn (insn_template
, fuse_ops
);
32296 /* Emit the D-form load instruction. */
32297 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
32299 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
32300 fuse_ops
[1] = load_offset
;
32301 output_asm_insn (insn_template
, fuse_ops
);
32304 else if (GET_CODE (load_offset
) == UNSPEC
32305 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
32308 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
32310 else if (TARGET_XCOFF
)
32311 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32314 gcc_unreachable ();
32316 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
32317 output_asm_insn (insn_template
, fuse_ops
);
32320 else if (GET_CODE (load_offset
) == PLUS
32321 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
32322 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
32323 && CONST_INT_P (XEXP (load_offset
, 1)))
32325 rtx tocrel_unspec
= XEXP (load_offset
, 0);
32327 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
32329 else if (TARGET_XCOFF
)
32330 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
32333 gcc_unreachable ();
32335 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
32336 fuse_ops
[2] = XEXP (load_offset
, 1);
32337 output_asm_insn (insn_template
, fuse_ops
);
32340 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
32342 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32344 fuse_ops
[1] = load_offset
;
32345 output_asm_insn (insn_template
, fuse_ops
);
32349 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
32351 /* Handle sign extension. The peephole2 pass generates this as a separate
32352 insn, but we handle it just in case it got reattached. */
32355 gcc_assert (extend_insn
!= NULL
);
32356 output_asm_insn (extend_insn
, fuse_ops
);
32363 struct gcc_target targetm
= TARGET_INITIALIZER
;
32365 #include "gt-rs6000.h"