1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2016 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
33 #include "stringpool.h"
40 #include "diagnostic-core.h"
41 #include "insn-attr.h"
44 #include "fold-const.h"
45 #include "stor-layout.h"
47 #include "print-tree.h"
53 #include "common/common-target.h"
54 #include "langhooks.h"
56 #include "sched-int.h"
58 #include "gimple-iterator.h"
59 #include "gimple-ssa.h"
60 #include "gimple-walk.h"
63 #include "tm-constrs.h"
64 #include "tree-vectorizer.h"
65 #include "target-globals.h"
68 #include "tree-pass.h"
70 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
73 #include "gstab.h" /* for N_SLINE */
75 #include "case-cfn-macros.h"
78 /* This file should be included last. */
79 #include "target-def.h"
81 #ifndef TARGET_NO_PROTOTYPE
82 #define TARGET_NO_PROTOTYPE 0
85 #define min(A,B) ((A) < (B) ? (A) : (B))
86 #define max(A,B) ((A) > (B) ? (A) : (B))
88 /* Structure used to define the rs6000 stack */
89 typedef struct rs6000_stack
{
90 int reload_completed
; /* stack info won't change from here on */
91 int first_gp_reg_save
; /* first callee saved GP register used */
92 int first_fp_reg_save
; /* first callee saved FP register used */
93 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
94 int lr_save_p
; /* true if the link reg needs to be saved */
95 int cr_save_p
; /* true if the CR reg needs to be saved */
96 unsigned int vrsave_mask
; /* mask of vec registers to save */
97 int push_p
; /* true if we need to allocate stack space */
98 int calls_p
; /* true if the function makes any calls */
99 int world_save_p
; /* true if we're saving *everything*:
100 r13-r31, cr, f14-f31, vrsave, v20-v31 */
101 enum rs6000_abi abi
; /* which ABI to use */
102 int gp_save_offset
; /* offset to save GP regs from initial SP */
103 int fp_save_offset
; /* offset to save FP regs from initial SP */
104 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
105 int lr_save_offset
; /* offset to save LR from initial SP */
106 int cr_save_offset
; /* offset to save CR from initial SP */
107 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
108 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
109 int varargs_save_offset
; /* offset to save the varargs registers */
110 int ehrd_offset
; /* offset to EH return data */
111 int ehcr_offset
; /* offset to EH CR field data */
112 int reg_size
; /* register size (4 or 8) */
113 HOST_WIDE_INT vars_size
; /* variable save area size */
114 int parm_size
; /* outgoing parameter size */
115 int save_size
; /* save area size */
116 int fixed_size
; /* fixed size of stack frame */
117 int gp_size
; /* size of saved GP registers */
118 int fp_size
; /* size of saved FP registers */
119 int altivec_size
; /* size of saved AltiVec registers */
120 int cr_size
; /* size to hold CR if not in fixed area */
121 int vrsave_size
; /* size to hold VRSAVE */
122 int altivec_padding_size
; /* size of altivec alignment padding */
123 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
124 int spe_padding_size
;
125 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
126 int spe_64bit_regs_used
;
130 /* A C structure for machine-specific, per-function data.
131 This is added to the cfun structure. */
132 typedef struct GTY(()) machine_function
134 /* Whether the instruction chain has been scanned already. */
135 int spe_insn_chain_scanned_p
;
136 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
137 int ra_needs_full_frame
;
138 /* Flags if __builtin_return_address (0) was used. */
140 /* Cache lr_save_p after expansion of builtin_eh_return. */
142 /* Whether we need to save the TOC to the reserved stack location in the
143 function prologue. */
144 bool save_toc_in_prologue
;
145 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
146 varargs save area. */
147 HOST_WIDE_INT varargs_save_offset
;
148 /* Temporary stack slot to use for SDmode copies. This slot is
149 64-bits wide and is allocated early enough so that the offset
150 does not overflow the 16-bit load/store offset field. */
151 rtx sdmode_stack_slot
;
152 /* Alternative internal arg pointer for -fsplit-stack. */
153 rtx split_stack_arg_pointer
;
154 bool split_stack_argp_used
;
155 /* Flag if r2 setup is needed with ELFv2 ABI. */
156 bool r2_setup_needed
;
157 /* The components already handled by separate shrink-wrapping, which should
158 not be considered by the prologue and epilogue. */
159 bool gpr_is_wrapped_separately
[32];
160 bool lr_is_wrapped_separately
;
163 /* Support targetm.vectorize.builtin_mask_for_load. */
164 static GTY(()) tree altivec_builtin_mask_for_load
;
166 /* Set to nonzero once AIX common-mode calls have been defined. */
167 static GTY(()) int common_mode_defined
;
169 /* Label number of label created for -mrelocatable, to call to so we can
170 get the address of the GOT section */
171 static int rs6000_pic_labelno
;
174 /* Counter for labels which are to be placed in .fixup. */
175 int fixuplabelno
= 0;
178 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
181 /* Specify the machine mode that pointers have. After generation of rtl, the
182 compiler makes no further distinction between pointers and any other objects
183 of this machine mode. The type is unsigned since not all things that
184 include rs6000.h also include machmode.h. */
185 unsigned rs6000_pmode
;
187 /* Width in bits of a pointer. */
188 unsigned rs6000_pointer_size
;
190 #ifdef HAVE_AS_GNU_ATTRIBUTE
191 # ifndef HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
192 # define HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE 0
194 /* Flag whether floating point values have been passed/returned.
195 Note that this doesn't say whether fprs are used, since the
196 Tag_GNU_Power_ABI_FP .gnu.attributes value this flag controls
197 should be set for soft-float values passed in gprs and ieee128
198 values passed in vsx registers. */
199 static bool rs6000_passes_float
;
200 static bool rs6000_passes_long_double
;
201 /* Flag whether vector values have been passed/returned. */
202 static bool rs6000_passes_vector
;
203 /* Flag whether small (<= 8 byte) structures have been returned. */
204 static bool rs6000_returns_struct
;
207 /* Value is TRUE if register/mode pair is acceptable. */
208 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
210 /* Maximum number of registers needed for a given register class and mode. */
211 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
213 /* How many registers are needed for a given register and mode. */
214 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
216 /* Map register number to register class. */
217 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
219 static int dbg_cost_ctrl
;
221 /* Built in types. */
222 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
223 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
225 /* Flag to say the TOC is initialized */
226 int toc_initialized
, need_toc_init
;
227 char toc_label_name
[10];
229 /* Cached value of rs6000_variable_issue. This is cached in
230 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
231 static short cached_can_issue_more
;
233 static GTY(()) section
*read_only_data_section
;
234 static GTY(()) section
*private_data_section
;
235 static GTY(()) section
*tls_data_section
;
236 static GTY(()) section
*tls_private_data_section
;
237 static GTY(()) section
*read_only_private_data_section
;
238 static GTY(()) section
*sdata2_section
;
239 static GTY(()) section
*toc_section
;
241 struct builtin_description
243 const HOST_WIDE_INT mask
;
244 const enum insn_code icode
;
245 const char *const name
;
246 const enum rs6000_builtins code
;
249 /* Describe the vector unit used for modes. */
250 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
251 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
253 /* Register classes for various constraints that are based on the target
255 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
257 /* Describe the alignment of a vector. */
258 int rs6000_vector_align
[NUM_MACHINE_MODES
];
260 /* Map selected modes to types for builtins. */
261 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
263 /* What modes to automatically generate reciprocal divide estimate (fre) and
264 reciprocal sqrt (frsqrte) for. */
265 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
267 /* Masks to determine which reciprocal esitmate instructions to generate
269 enum rs6000_recip_mask
{
270 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
271 RECIP_DF_DIV
= 0x002,
272 RECIP_V4SF_DIV
= 0x004,
273 RECIP_V2DF_DIV
= 0x008,
275 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
276 RECIP_DF_RSQRT
= 0x020,
277 RECIP_V4SF_RSQRT
= 0x040,
278 RECIP_V2DF_RSQRT
= 0x080,
280 /* Various combination of flags for -mrecip=xxx. */
282 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
283 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
284 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
286 RECIP_HIGH_PRECISION
= RECIP_ALL
,
288 /* On low precision machines like the power5, don't enable double precision
289 reciprocal square root estimate, since it isn't accurate enough. */
290 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
293 /* -mrecip options. */
296 const char *string
; /* option name */
297 unsigned int mask
; /* mask bits to set */
298 } recip_options
[] = {
299 { "all", RECIP_ALL
},
300 { "none", RECIP_NONE
},
301 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
303 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
304 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
305 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
306 | RECIP_V2DF_RSQRT
) },
307 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
308 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
311 /* Used by __builtin_cpu_is(), mapping from PLATFORM names to values. */
317 { "power9", PPC_PLATFORM_POWER9
},
318 { "power8", PPC_PLATFORM_POWER8
},
319 { "power7", PPC_PLATFORM_POWER7
},
320 { "power6x", PPC_PLATFORM_POWER6X
},
321 { "power6", PPC_PLATFORM_POWER6
},
322 { "power5+", PPC_PLATFORM_POWER5_PLUS
},
323 { "power5", PPC_PLATFORM_POWER5
},
324 { "ppc970", PPC_PLATFORM_PPC970
},
325 { "power4", PPC_PLATFORM_POWER4
},
326 { "ppca2", PPC_PLATFORM_PPCA2
},
327 { "ppc476", PPC_PLATFORM_PPC476
},
328 { "ppc464", PPC_PLATFORM_PPC464
},
329 { "ppc440", PPC_PLATFORM_PPC440
},
330 { "ppc405", PPC_PLATFORM_PPC405
},
331 { "ppc-cell-be", PPC_PLATFORM_CELL_BE
}
334 /* Used by __builtin_cpu_supports(), mapping from HWCAP names to masks. */
340 } cpu_supports_info
[] = {
341 /* AT_HWCAP masks. */
342 { "4xxmac", PPC_FEATURE_HAS_4xxMAC
, 0 },
343 { "altivec", PPC_FEATURE_HAS_ALTIVEC
, 0 },
344 { "arch_2_05", PPC_FEATURE_ARCH_2_05
, 0 },
345 { "arch_2_06", PPC_FEATURE_ARCH_2_06
, 0 },
346 { "archpmu", PPC_FEATURE_PERFMON_COMPAT
, 0 },
347 { "booke", PPC_FEATURE_BOOKE
, 0 },
348 { "cellbe", PPC_FEATURE_CELL_BE
, 0 },
349 { "dfp", PPC_FEATURE_HAS_DFP
, 0 },
350 { "efpdouble", PPC_FEATURE_HAS_EFP_DOUBLE
, 0 },
351 { "efpsingle", PPC_FEATURE_HAS_EFP_SINGLE
, 0 },
352 { "fpu", PPC_FEATURE_HAS_FPU
, 0 },
353 { "ic_snoop", PPC_FEATURE_ICACHE_SNOOP
, 0 },
354 { "mmu", PPC_FEATURE_HAS_MMU
, 0 },
355 { "notb", PPC_FEATURE_NO_TB
, 0 },
356 { "pa6t", PPC_FEATURE_PA6T
, 0 },
357 { "power4", PPC_FEATURE_POWER4
, 0 },
358 { "power5", PPC_FEATURE_POWER5
, 0 },
359 { "power5+", PPC_FEATURE_POWER5_PLUS
, 0 },
360 { "power6x", PPC_FEATURE_POWER6_EXT
, 0 },
361 { "ppc32", PPC_FEATURE_32
, 0 },
362 { "ppc601", PPC_FEATURE_601_INSTR
, 0 },
363 { "ppc64", PPC_FEATURE_64
, 0 },
364 { "ppcle", PPC_FEATURE_PPC_LE
, 0 },
365 { "smt", PPC_FEATURE_SMT
, 0 },
366 { "spe", PPC_FEATURE_HAS_SPE
, 0 },
367 { "true_le", PPC_FEATURE_TRUE_LE
, 0 },
368 { "ucache", PPC_FEATURE_UNIFIED_CACHE
, 0 },
369 { "vsx", PPC_FEATURE_HAS_VSX
, 0 },
371 /* AT_HWCAP2 masks. */
372 { "arch_2_07", PPC_FEATURE2_ARCH_2_07
, 1 },
373 { "dscr", PPC_FEATURE2_HAS_DSCR
, 1 },
374 { "ebb", PPC_FEATURE2_HAS_EBB
, 1 },
375 { "htm", PPC_FEATURE2_HAS_HTM
, 1 },
376 { "htm-nosc", PPC_FEATURE2_HTM_NOSC
, 1 },
377 { "isel", PPC_FEATURE2_HAS_ISEL
, 1 },
378 { "tar", PPC_FEATURE2_HAS_TAR
, 1 },
379 { "vcrypto", PPC_FEATURE2_HAS_VEC_CRYPTO
, 1 },
380 { "arch_3_00", PPC_FEATURE2_ARCH_3_00
, 1 },
381 { "ieee128", PPC_FEATURE2_HAS_IEEE128
, 1 }
384 /* Newer LIBCs explicitly export this symbol to declare that they provide
385 the AT_PLATFORM and AT_HWCAP/AT_HWCAP2 values in the TCB. We emit a
386 reference to this symbol whenever we expand a CPU builtin, so that
387 we never link against an old LIBC. */
388 const char *tcb_verification_symbol
= "__parse_hwcap_and_convert_at_platform";
390 /* True if we have expanded a CPU builtin. */
393 /* Pointer to function (in rs6000-c.c) that can define or undefine target
394 macros that have changed. Languages that don't support the preprocessor
395 don't link in rs6000-c.c, so we can't call it directly. */
396 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
398 /* Simplfy register classes into simpler classifications. We assume
399 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
400 check for standard register classes (gpr/floating/altivec/vsx) and
401 floating/vector classes (float/altivec/vsx). */
403 enum rs6000_reg_type
{
416 /* Map register class to register type. */
417 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
419 /* First/last register type for the 'normal' register types (i.e. general
420 purpose, floating point, altivec, and VSX registers). */
421 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
423 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
426 /* Register classes we care about in secondary reload or go if legitimate
427 address. We only need to worry about GPR, FPR, and Altivec registers here,
428 along an ANY field that is the OR of the 3 register classes. */
430 enum rs6000_reload_reg_type
{
431 RELOAD_REG_GPR
, /* General purpose registers. */
432 RELOAD_REG_FPR
, /* Traditional floating point regs. */
433 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
434 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
438 /* For setting up register classes, loop through the 3 register classes mapping
439 into real registers, and skip the ANY class, which is just an OR of the
441 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
442 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
444 /* Map reload register type to a register in the register class. */
445 struct reload_reg_map_type
{
446 const char *name
; /* Register class name. */
447 int reg
; /* Register in the register class. */
450 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
451 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
452 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
453 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
454 { "Any", -1 }, /* RELOAD_REG_ANY. */
457 /* Mask bits for each register class, indexed per mode. Historically the
458 compiler has been more restrictive which types can do PRE_MODIFY instead of
459 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
460 typedef unsigned char addr_mask_type
;
462 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
463 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
464 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
465 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
466 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
467 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
468 #define RELOAD_REG_AND_M16 0x40 /* AND -16 addressing. */
469 #define RELOAD_REG_QUAD_OFFSET 0x80 /* quad offset is limited. */
471 /* Register type masks based on the type, of valid addressing modes. */
472 struct rs6000_reg_addr
{
473 enum insn_code reload_load
; /* INSN to reload for loading. */
474 enum insn_code reload_store
; /* INSN to reload for storing. */
475 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
476 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
477 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
478 enum insn_code fusion_gpr_ld
; /* INSN for fusing gpr ADDIS/loads. */
479 /* INSNs for fusing addi with loads
480 or stores for each reg. class. */
481 enum insn_code fusion_addi_ld
[(int)N_RELOAD_REG
];
482 enum insn_code fusion_addi_st
[(int)N_RELOAD_REG
];
483 /* INSNs for fusing addis with loads
484 or stores for each reg. class. */
485 enum insn_code fusion_addis_ld
[(int)N_RELOAD_REG
];
486 enum insn_code fusion_addis_st
[(int)N_RELOAD_REG
];
487 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
488 bool scalar_in_vmx_p
; /* Scalar value can go in VMX. */
489 bool fused_toc
; /* Mode supports TOC fusion. */
492 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
494 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
496 mode_supports_pre_incdec_p (machine_mode mode
)
498 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
502 /* Helper function to say whether a mode supports PRE_MODIFY. */
504 mode_supports_pre_modify_p (machine_mode mode
)
506 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
510 /* Return true if we have D-form addressing in altivec registers. */
512 mode_supports_vmx_dform (machine_mode mode
)
514 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_OFFSET
) != 0);
517 /* Return true if we have D-form addressing in VSX registers. This addressing
518 is more limited than normal d-form addressing in that the offset must be
519 aligned on a 16-byte boundary. */
521 mode_supports_vsx_dform_quad (machine_mode mode
)
523 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_QUAD_OFFSET
)
528 /* Target cpu costs. */
530 struct processor_costs
{
531 const int mulsi
; /* cost of SImode multiplication. */
532 const int mulsi_const
; /* cost of SImode multiplication by constant. */
533 const int mulsi_const9
; /* cost of SImode mult by short constant. */
534 const int muldi
; /* cost of DImode multiplication. */
535 const int divsi
; /* cost of SImode division. */
536 const int divdi
; /* cost of DImode division. */
537 const int fp
; /* cost of simple SFmode and DFmode insns. */
538 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
539 const int sdiv
; /* cost of SFmode division (fdivs). */
540 const int ddiv
; /* cost of DFmode division (fdiv). */
541 const int cache_line_size
; /* cache line size in bytes. */
542 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
543 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
544 const int simultaneous_prefetches
; /* number of parallel prefetch
546 const int sfdf_convert
; /* cost of SF->DF conversion. */
549 const struct processor_costs
*rs6000_cost
;
551 /* Processor costs (relative to an add) */
553 /* Instruction size costs on 32bit processors. */
555 struct processor_costs size32_cost
= {
556 COSTS_N_INSNS (1), /* mulsi */
557 COSTS_N_INSNS (1), /* mulsi_const */
558 COSTS_N_INSNS (1), /* mulsi_const9 */
559 COSTS_N_INSNS (1), /* muldi */
560 COSTS_N_INSNS (1), /* divsi */
561 COSTS_N_INSNS (1), /* divdi */
562 COSTS_N_INSNS (1), /* fp */
563 COSTS_N_INSNS (1), /* dmul */
564 COSTS_N_INSNS (1), /* sdiv */
565 COSTS_N_INSNS (1), /* ddiv */
566 32, /* cache line size */
570 0, /* SF->DF convert */
573 /* Instruction size costs on 64bit processors. */
575 struct processor_costs size64_cost
= {
576 COSTS_N_INSNS (1), /* mulsi */
577 COSTS_N_INSNS (1), /* mulsi_const */
578 COSTS_N_INSNS (1), /* mulsi_const9 */
579 COSTS_N_INSNS (1), /* muldi */
580 COSTS_N_INSNS (1), /* divsi */
581 COSTS_N_INSNS (1), /* divdi */
582 COSTS_N_INSNS (1), /* fp */
583 COSTS_N_INSNS (1), /* dmul */
584 COSTS_N_INSNS (1), /* sdiv */
585 COSTS_N_INSNS (1), /* ddiv */
586 128, /* cache line size */
590 0, /* SF->DF convert */
593 /* Instruction costs on RS64A processors. */
595 struct processor_costs rs64a_cost
= {
596 COSTS_N_INSNS (20), /* mulsi */
597 COSTS_N_INSNS (12), /* mulsi_const */
598 COSTS_N_INSNS (8), /* mulsi_const9 */
599 COSTS_N_INSNS (34), /* muldi */
600 COSTS_N_INSNS (65), /* divsi */
601 COSTS_N_INSNS (67), /* divdi */
602 COSTS_N_INSNS (4), /* fp */
603 COSTS_N_INSNS (4), /* dmul */
604 COSTS_N_INSNS (31), /* sdiv */
605 COSTS_N_INSNS (31), /* ddiv */
606 128, /* cache line size */
610 0, /* SF->DF convert */
613 /* Instruction costs on MPCCORE processors. */
615 struct processor_costs mpccore_cost
= {
616 COSTS_N_INSNS (2), /* mulsi */
617 COSTS_N_INSNS (2), /* mulsi_const */
618 COSTS_N_INSNS (2), /* mulsi_const9 */
619 COSTS_N_INSNS (2), /* muldi */
620 COSTS_N_INSNS (6), /* divsi */
621 COSTS_N_INSNS (6), /* divdi */
622 COSTS_N_INSNS (4), /* fp */
623 COSTS_N_INSNS (5), /* dmul */
624 COSTS_N_INSNS (10), /* sdiv */
625 COSTS_N_INSNS (17), /* ddiv */
626 32, /* cache line size */
630 0, /* SF->DF convert */
633 /* Instruction costs on PPC403 processors. */
635 struct processor_costs ppc403_cost
= {
636 COSTS_N_INSNS (4), /* mulsi */
637 COSTS_N_INSNS (4), /* mulsi_const */
638 COSTS_N_INSNS (4), /* mulsi_const9 */
639 COSTS_N_INSNS (4), /* muldi */
640 COSTS_N_INSNS (33), /* divsi */
641 COSTS_N_INSNS (33), /* divdi */
642 COSTS_N_INSNS (11), /* fp */
643 COSTS_N_INSNS (11), /* dmul */
644 COSTS_N_INSNS (11), /* sdiv */
645 COSTS_N_INSNS (11), /* ddiv */
646 32, /* cache line size */
650 0, /* SF->DF convert */
653 /* Instruction costs on PPC405 processors. */
655 struct processor_costs ppc405_cost
= {
656 COSTS_N_INSNS (5), /* mulsi */
657 COSTS_N_INSNS (4), /* mulsi_const */
658 COSTS_N_INSNS (3), /* mulsi_const9 */
659 COSTS_N_INSNS (5), /* muldi */
660 COSTS_N_INSNS (35), /* divsi */
661 COSTS_N_INSNS (35), /* divdi */
662 COSTS_N_INSNS (11), /* fp */
663 COSTS_N_INSNS (11), /* dmul */
664 COSTS_N_INSNS (11), /* sdiv */
665 COSTS_N_INSNS (11), /* ddiv */
666 32, /* cache line size */
670 0, /* SF->DF convert */
673 /* Instruction costs on PPC440 processors. */
675 struct processor_costs ppc440_cost
= {
676 COSTS_N_INSNS (3), /* mulsi */
677 COSTS_N_INSNS (2), /* mulsi_const */
678 COSTS_N_INSNS (2), /* mulsi_const9 */
679 COSTS_N_INSNS (3), /* muldi */
680 COSTS_N_INSNS (34), /* divsi */
681 COSTS_N_INSNS (34), /* divdi */
682 COSTS_N_INSNS (5), /* fp */
683 COSTS_N_INSNS (5), /* dmul */
684 COSTS_N_INSNS (19), /* sdiv */
685 COSTS_N_INSNS (33), /* ddiv */
686 32, /* cache line size */
690 0, /* SF->DF convert */
693 /* Instruction costs on PPC476 processors. */
695 struct processor_costs ppc476_cost
= {
696 COSTS_N_INSNS (4), /* mulsi */
697 COSTS_N_INSNS (4), /* mulsi_const */
698 COSTS_N_INSNS (4), /* mulsi_const9 */
699 COSTS_N_INSNS (4), /* muldi */
700 COSTS_N_INSNS (11), /* divsi */
701 COSTS_N_INSNS (11), /* divdi */
702 COSTS_N_INSNS (6), /* fp */
703 COSTS_N_INSNS (6), /* dmul */
704 COSTS_N_INSNS (19), /* sdiv */
705 COSTS_N_INSNS (33), /* ddiv */
706 32, /* l1 cache line size */
710 0, /* SF->DF convert */
713 /* Instruction costs on PPC601 processors. */
715 struct processor_costs ppc601_cost
= {
716 COSTS_N_INSNS (5), /* mulsi */
717 COSTS_N_INSNS (5), /* mulsi_const */
718 COSTS_N_INSNS (5), /* mulsi_const9 */
719 COSTS_N_INSNS (5), /* muldi */
720 COSTS_N_INSNS (36), /* divsi */
721 COSTS_N_INSNS (36), /* divdi */
722 COSTS_N_INSNS (4), /* fp */
723 COSTS_N_INSNS (5), /* dmul */
724 COSTS_N_INSNS (17), /* sdiv */
725 COSTS_N_INSNS (31), /* ddiv */
726 32, /* cache line size */
730 0, /* SF->DF convert */
733 /* Instruction costs on PPC603 processors. */
735 struct processor_costs ppc603_cost
= {
736 COSTS_N_INSNS (5), /* mulsi */
737 COSTS_N_INSNS (3), /* mulsi_const */
738 COSTS_N_INSNS (2), /* mulsi_const9 */
739 COSTS_N_INSNS (5), /* muldi */
740 COSTS_N_INSNS (37), /* divsi */
741 COSTS_N_INSNS (37), /* divdi */
742 COSTS_N_INSNS (3), /* fp */
743 COSTS_N_INSNS (4), /* dmul */
744 COSTS_N_INSNS (18), /* sdiv */
745 COSTS_N_INSNS (33), /* ddiv */
746 32, /* cache line size */
750 0, /* SF->DF convert */
753 /* Instruction costs on PPC604 processors. */
755 struct processor_costs ppc604_cost
= {
756 COSTS_N_INSNS (4), /* mulsi */
757 COSTS_N_INSNS (4), /* mulsi_const */
758 COSTS_N_INSNS (4), /* mulsi_const9 */
759 COSTS_N_INSNS (4), /* muldi */
760 COSTS_N_INSNS (20), /* divsi */
761 COSTS_N_INSNS (20), /* divdi */
762 COSTS_N_INSNS (3), /* fp */
763 COSTS_N_INSNS (3), /* dmul */
764 COSTS_N_INSNS (18), /* sdiv */
765 COSTS_N_INSNS (32), /* ddiv */
766 32, /* cache line size */
770 0, /* SF->DF convert */
773 /* Instruction costs on PPC604e processors. */
775 struct processor_costs ppc604e_cost
= {
776 COSTS_N_INSNS (2), /* mulsi */
777 COSTS_N_INSNS (2), /* mulsi_const */
778 COSTS_N_INSNS (2), /* mulsi_const9 */
779 COSTS_N_INSNS (2), /* muldi */
780 COSTS_N_INSNS (20), /* divsi */
781 COSTS_N_INSNS (20), /* divdi */
782 COSTS_N_INSNS (3), /* fp */
783 COSTS_N_INSNS (3), /* dmul */
784 COSTS_N_INSNS (18), /* sdiv */
785 COSTS_N_INSNS (32), /* ddiv */
786 32, /* cache line size */
790 0, /* SF->DF convert */
793 /* Instruction costs on PPC620 processors. */
795 struct processor_costs ppc620_cost
= {
796 COSTS_N_INSNS (5), /* mulsi */
797 COSTS_N_INSNS (4), /* mulsi_const */
798 COSTS_N_INSNS (3), /* mulsi_const9 */
799 COSTS_N_INSNS (7), /* muldi */
800 COSTS_N_INSNS (21), /* divsi */
801 COSTS_N_INSNS (37), /* divdi */
802 COSTS_N_INSNS (3), /* fp */
803 COSTS_N_INSNS (3), /* dmul */
804 COSTS_N_INSNS (18), /* sdiv */
805 COSTS_N_INSNS (32), /* ddiv */
806 128, /* cache line size */
810 0, /* SF->DF convert */
813 /* Instruction costs on PPC630 processors. */
815 struct processor_costs ppc630_cost
= {
816 COSTS_N_INSNS (5), /* mulsi */
817 COSTS_N_INSNS (4), /* mulsi_const */
818 COSTS_N_INSNS (3), /* mulsi_const9 */
819 COSTS_N_INSNS (7), /* muldi */
820 COSTS_N_INSNS (21), /* divsi */
821 COSTS_N_INSNS (37), /* divdi */
822 COSTS_N_INSNS (3), /* fp */
823 COSTS_N_INSNS (3), /* dmul */
824 COSTS_N_INSNS (17), /* sdiv */
825 COSTS_N_INSNS (21), /* ddiv */
826 128, /* cache line size */
830 0, /* SF->DF convert */
833 /* Instruction costs on Cell processor. */
834 /* COSTS_N_INSNS (1) ~ one add. */
836 struct processor_costs ppccell_cost
= {
837 COSTS_N_INSNS (9/2)+2, /* mulsi */
838 COSTS_N_INSNS (6/2), /* mulsi_const */
839 COSTS_N_INSNS (6/2), /* mulsi_const9 */
840 COSTS_N_INSNS (15/2)+2, /* muldi */
841 COSTS_N_INSNS (38/2), /* divsi */
842 COSTS_N_INSNS (70/2), /* divdi */
843 COSTS_N_INSNS (10/2), /* fp */
844 COSTS_N_INSNS (10/2), /* dmul */
845 COSTS_N_INSNS (74/2), /* sdiv */
846 COSTS_N_INSNS (74/2), /* ddiv */
847 128, /* cache line size */
851 0, /* SF->DF convert */
854 /* Instruction costs on PPC750 and PPC7400 processors. */
856 struct processor_costs ppc750_cost
= {
857 COSTS_N_INSNS (5), /* mulsi */
858 COSTS_N_INSNS (3), /* mulsi_const */
859 COSTS_N_INSNS (2), /* mulsi_const9 */
860 COSTS_N_INSNS (5), /* muldi */
861 COSTS_N_INSNS (17), /* divsi */
862 COSTS_N_INSNS (17), /* divdi */
863 COSTS_N_INSNS (3), /* fp */
864 COSTS_N_INSNS (3), /* dmul */
865 COSTS_N_INSNS (17), /* sdiv */
866 COSTS_N_INSNS (31), /* ddiv */
867 32, /* cache line size */
871 0, /* SF->DF convert */
874 /* Instruction costs on PPC7450 processors. */
876 struct processor_costs ppc7450_cost
= {
877 COSTS_N_INSNS (4), /* mulsi */
878 COSTS_N_INSNS (3), /* mulsi_const */
879 COSTS_N_INSNS (3), /* mulsi_const9 */
880 COSTS_N_INSNS (4), /* muldi */
881 COSTS_N_INSNS (23), /* divsi */
882 COSTS_N_INSNS (23), /* divdi */
883 COSTS_N_INSNS (5), /* fp */
884 COSTS_N_INSNS (5), /* dmul */
885 COSTS_N_INSNS (21), /* sdiv */
886 COSTS_N_INSNS (35), /* ddiv */
887 32, /* cache line size */
891 0, /* SF->DF convert */
894 /* Instruction costs on PPC8540 processors. */
896 struct processor_costs ppc8540_cost
= {
897 COSTS_N_INSNS (4), /* mulsi */
898 COSTS_N_INSNS (4), /* mulsi_const */
899 COSTS_N_INSNS (4), /* mulsi_const9 */
900 COSTS_N_INSNS (4), /* muldi */
901 COSTS_N_INSNS (19), /* divsi */
902 COSTS_N_INSNS (19), /* divdi */
903 COSTS_N_INSNS (4), /* fp */
904 COSTS_N_INSNS (4), /* dmul */
905 COSTS_N_INSNS (29), /* sdiv */
906 COSTS_N_INSNS (29), /* ddiv */
907 32, /* cache line size */
910 1, /* prefetch streams /*/
911 0, /* SF->DF convert */
914 /* Instruction costs on E300C2 and E300C3 cores. */
916 struct processor_costs ppce300c2c3_cost
= {
917 COSTS_N_INSNS (4), /* mulsi */
918 COSTS_N_INSNS (4), /* mulsi_const */
919 COSTS_N_INSNS (4), /* mulsi_const9 */
920 COSTS_N_INSNS (4), /* muldi */
921 COSTS_N_INSNS (19), /* divsi */
922 COSTS_N_INSNS (19), /* divdi */
923 COSTS_N_INSNS (3), /* fp */
924 COSTS_N_INSNS (4), /* dmul */
925 COSTS_N_INSNS (18), /* sdiv */
926 COSTS_N_INSNS (33), /* ddiv */
930 1, /* prefetch streams /*/
931 0, /* SF->DF convert */
934 /* Instruction costs on PPCE500MC processors. */
936 struct processor_costs ppce500mc_cost
= {
937 COSTS_N_INSNS (4), /* mulsi */
938 COSTS_N_INSNS (4), /* mulsi_const */
939 COSTS_N_INSNS (4), /* mulsi_const9 */
940 COSTS_N_INSNS (4), /* muldi */
941 COSTS_N_INSNS (14), /* divsi */
942 COSTS_N_INSNS (14), /* divdi */
943 COSTS_N_INSNS (8), /* fp */
944 COSTS_N_INSNS (10), /* dmul */
945 COSTS_N_INSNS (36), /* sdiv */
946 COSTS_N_INSNS (66), /* ddiv */
947 64, /* cache line size */
950 1, /* prefetch streams /*/
951 0, /* SF->DF convert */
954 /* Instruction costs on PPCE500MC64 processors. */
956 struct processor_costs ppce500mc64_cost
= {
957 COSTS_N_INSNS (4), /* mulsi */
958 COSTS_N_INSNS (4), /* mulsi_const */
959 COSTS_N_INSNS (4), /* mulsi_const9 */
960 COSTS_N_INSNS (4), /* muldi */
961 COSTS_N_INSNS (14), /* divsi */
962 COSTS_N_INSNS (14), /* divdi */
963 COSTS_N_INSNS (4), /* fp */
964 COSTS_N_INSNS (10), /* dmul */
965 COSTS_N_INSNS (36), /* sdiv */
966 COSTS_N_INSNS (66), /* ddiv */
967 64, /* cache line size */
970 1, /* prefetch streams /*/
971 0, /* SF->DF convert */
974 /* Instruction costs on PPCE5500 processors. */
976 struct processor_costs ppce5500_cost
= {
977 COSTS_N_INSNS (5), /* mulsi */
978 COSTS_N_INSNS (5), /* mulsi_const */
979 COSTS_N_INSNS (4), /* mulsi_const9 */
980 COSTS_N_INSNS (5), /* muldi */
981 COSTS_N_INSNS (14), /* divsi */
982 COSTS_N_INSNS (14), /* divdi */
983 COSTS_N_INSNS (7), /* fp */
984 COSTS_N_INSNS (10), /* dmul */
985 COSTS_N_INSNS (36), /* sdiv */
986 COSTS_N_INSNS (66), /* ddiv */
987 64, /* cache line size */
990 1, /* prefetch streams /*/
991 0, /* SF->DF convert */
994 /* Instruction costs on PPCE6500 processors. */
996 struct processor_costs ppce6500_cost
= {
997 COSTS_N_INSNS (5), /* mulsi */
998 COSTS_N_INSNS (5), /* mulsi_const */
999 COSTS_N_INSNS (4), /* mulsi_const9 */
1000 COSTS_N_INSNS (5), /* muldi */
1001 COSTS_N_INSNS (14), /* divsi */
1002 COSTS_N_INSNS (14), /* divdi */
1003 COSTS_N_INSNS (7), /* fp */
1004 COSTS_N_INSNS (10), /* dmul */
1005 COSTS_N_INSNS (36), /* sdiv */
1006 COSTS_N_INSNS (66), /* ddiv */
1007 64, /* cache line size */
1010 1, /* prefetch streams /*/
1011 0, /* SF->DF convert */
1014 /* Instruction costs on AppliedMicro Titan processors. */
1016 struct processor_costs titan_cost
= {
1017 COSTS_N_INSNS (5), /* mulsi */
1018 COSTS_N_INSNS (5), /* mulsi_const */
1019 COSTS_N_INSNS (5), /* mulsi_const9 */
1020 COSTS_N_INSNS (5), /* muldi */
1021 COSTS_N_INSNS (18), /* divsi */
1022 COSTS_N_INSNS (18), /* divdi */
1023 COSTS_N_INSNS (10), /* fp */
1024 COSTS_N_INSNS (10), /* dmul */
1025 COSTS_N_INSNS (46), /* sdiv */
1026 COSTS_N_INSNS (72), /* ddiv */
1027 32, /* cache line size */
1030 1, /* prefetch streams /*/
1031 0, /* SF->DF convert */
1034 /* Instruction costs on POWER4 and POWER5 processors. */
1036 struct processor_costs power4_cost
= {
1037 COSTS_N_INSNS (3), /* mulsi */
1038 COSTS_N_INSNS (2), /* mulsi_const */
1039 COSTS_N_INSNS (2), /* mulsi_const9 */
1040 COSTS_N_INSNS (4), /* muldi */
1041 COSTS_N_INSNS (18), /* divsi */
1042 COSTS_N_INSNS (34), /* divdi */
1043 COSTS_N_INSNS (3), /* fp */
1044 COSTS_N_INSNS (3), /* dmul */
1045 COSTS_N_INSNS (17), /* sdiv */
1046 COSTS_N_INSNS (17), /* ddiv */
1047 128, /* cache line size */
1049 1024, /* l2 cache */
1050 8, /* prefetch streams /*/
1051 0, /* SF->DF convert */
1054 /* Instruction costs on POWER6 processors. */
1056 struct processor_costs power6_cost
= {
1057 COSTS_N_INSNS (8), /* mulsi */
1058 COSTS_N_INSNS (8), /* mulsi_const */
1059 COSTS_N_INSNS (8), /* mulsi_const9 */
1060 COSTS_N_INSNS (8), /* muldi */
1061 COSTS_N_INSNS (22), /* divsi */
1062 COSTS_N_INSNS (28), /* divdi */
1063 COSTS_N_INSNS (3), /* fp */
1064 COSTS_N_INSNS (3), /* dmul */
1065 COSTS_N_INSNS (13), /* sdiv */
1066 COSTS_N_INSNS (16), /* ddiv */
1067 128, /* cache line size */
1069 2048, /* l2 cache */
1070 16, /* prefetch streams */
1071 0, /* SF->DF convert */
1074 /* Instruction costs on POWER7 processors. */
1076 struct processor_costs power7_cost
= {
1077 COSTS_N_INSNS (2), /* mulsi */
1078 COSTS_N_INSNS (2), /* mulsi_const */
1079 COSTS_N_INSNS (2), /* mulsi_const9 */
1080 COSTS_N_INSNS (2), /* muldi */
1081 COSTS_N_INSNS (18), /* divsi */
1082 COSTS_N_INSNS (34), /* divdi */
1083 COSTS_N_INSNS (3), /* fp */
1084 COSTS_N_INSNS (3), /* dmul */
1085 COSTS_N_INSNS (13), /* sdiv */
1086 COSTS_N_INSNS (16), /* ddiv */
1087 128, /* cache line size */
1090 12, /* prefetch streams */
1091 COSTS_N_INSNS (3), /* SF->DF convert */
1094 /* Instruction costs on POWER8 processors. */
1096 struct processor_costs power8_cost
= {
1097 COSTS_N_INSNS (3), /* mulsi */
1098 COSTS_N_INSNS (3), /* mulsi_const */
1099 COSTS_N_INSNS (3), /* mulsi_const9 */
1100 COSTS_N_INSNS (3), /* muldi */
1101 COSTS_N_INSNS (19), /* divsi */
1102 COSTS_N_INSNS (35), /* divdi */
1103 COSTS_N_INSNS (3), /* fp */
1104 COSTS_N_INSNS (3), /* dmul */
1105 COSTS_N_INSNS (14), /* sdiv */
1106 COSTS_N_INSNS (17), /* ddiv */
1107 128, /* cache line size */
1110 12, /* prefetch streams */
1111 COSTS_N_INSNS (3), /* SF->DF convert */
1114 /* Instruction costs on POWER9 processors. */
1116 struct processor_costs power9_cost
= {
1117 COSTS_N_INSNS (3), /* mulsi */
1118 COSTS_N_INSNS (3), /* mulsi_const */
1119 COSTS_N_INSNS (3), /* mulsi_const9 */
1120 COSTS_N_INSNS (3), /* muldi */
1121 COSTS_N_INSNS (8), /* divsi */
1122 COSTS_N_INSNS (12), /* divdi */
1123 COSTS_N_INSNS (3), /* fp */
1124 COSTS_N_INSNS (3), /* dmul */
1125 COSTS_N_INSNS (13), /* sdiv */
1126 COSTS_N_INSNS (18), /* ddiv */
1127 128, /* cache line size */
1130 8, /* prefetch streams */
1131 COSTS_N_INSNS (3), /* SF->DF convert */
1134 /* Instruction costs on POWER A2 processors. */
1136 struct processor_costs ppca2_cost
= {
1137 COSTS_N_INSNS (16), /* mulsi */
1138 COSTS_N_INSNS (16), /* mulsi_const */
1139 COSTS_N_INSNS (16), /* mulsi_const9 */
1140 COSTS_N_INSNS (16), /* muldi */
1141 COSTS_N_INSNS (22), /* divsi */
1142 COSTS_N_INSNS (28), /* divdi */
1143 COSTS_N_INSNS (3), /* fp */
1144 COSTS_N_INSNS (3), /* dmul */
1145 COSTS_N_INSNS (59), /* sdiv */
1146 COSTS_N_INSNS (72), /* ddiv */
1149 2048, /* l2 cache */
1150 16, /* prefetch streams */
1151 0, /* SF->DF convert */
1155 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
1156 #undef RS6000_BUILTIN_0
1157 #undef RS6000_BUILTIN_1
1158 #undef RS6000_BUILTIN_2
1159 #undef RS6000_BUILTIN_3
1160 #undef RS6000_BUILTIN_A
1161 #undef RS6000_BUILTIN_D
1162 #undef RS6000_BUILTIN_E
1163 #undef RS6000_BUILTIN_H
1164 #undef RS6000_BUILTIN_P
1165 #undef RS6000_BUILTIN_Q
1166 #undef RS6000_BUILTIN_S
1167 #undef RS6000_BUILTIN_X
1169 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
1170 { NAME, ICODE, MASK, ATTR },
1172 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
1173 { NAME, ICODE, MASK, ATTR },
1175 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
1176 { NAME, ICODE, MASK, ATTR },
1178 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
1179 { NAME, ICODE, MASK, ATTR },
1181 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1182 { NAME, ICODE, MASK, ATTR },
1184 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1185 { NAME, ICODE, MASK, ATTR },
1187 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1188 { NAME, ICODE, MASK, ATTR },
1190 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1191 { NAME, ICODE, MASK, ATTR },
1193 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1194 { NAME, ICODE, MASK, ATTR },
1196 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1197 { NAME, ICODE, MASK, ATTR },
1199 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1200 { NAME, ICODE, MASK, ATTR },
1202 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1203 { NAME, ICODE, MASK, ATTR },
1205 struct rs6000_builtin_info_type
{
1207 const enum insn_code icode
;
1208 const HOST_WIDE_INT mask
;
1209 const unsigned attr
;
1212 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1214 #include "rs6000-builtin.def"
1217 #undef RS6000_BUILTIN_0
1218 #undef RS6000_BUILTIN_1
1219 #undef RS6000_BUILTIN_2
1220 #undef RS6000_BUILTIN_3
1221 #undef RS6000_BUILTIN_A
1222 #undef RS6000_BUILTIN_D
1223 #undef RS6000_BUILTIN_E
1224 #undef RS6000_BUILTIN_H
1225 #undef RS6000_BUILTIN_P
1226 #undef RS6000_BUILTIN_Q
1227 #undef RS6000_BUILTIN_S
1228 #undef RS6000_BUILTIN_X
1230 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1231 static tree (*rs6000_veclib_handler
) (combined_fn
, tree
, tree
);
1234 static bool rs6000_debug_legitimate_address_p (machine_mode
, rtx
, bool);
1235 static bool spe_func_has_64bit_regs_p (void);
1236 static struct machine_function
* rs6000_init_machine_status (void);
1237 static int rs6000_ra_ever_killed (void);
1238 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1239 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1240 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1241 static tree
rs6000_builtin_vectorized_libmass (combined_fn
, tree
, tree
);
1242 static void rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
);
1243 static int rs6000_memory_move_cost (machine_mode
, reg_class_t
, bool);
1244 static bool rs6000_debug_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
1245 static int rs6000_debug_address_cost (rtx
, machine_mode
, addr_space_t
,
1247 static int rs6000_debug_adjust_cost (rtx_insn
*, int, rtx_insn
*, int,
1249 static bool is_microcoded_insn (rtx_insn
*);
1250 static bool is_nonpipeline_insn (rtx_insn
*);
1251 static bool is_cracked_insn (rtx_insn
*);
1252 static bool is_load_insn (rtx
, rtx
*);
1253 static bool is_store_insn (rtx
, rtx
*);
1254 static bool set_to_load_agen (rtx_insn
*,rtx_insn
*);
1255 static bool insn_terminates_group_p (rtx_insn
*, enum group_termination
);
1256 static bool insn_must_be_first_in_group (rtx_insn
*);
1257 static bool insn_must_be_last_in_group (rtx_insn
*);
1258 static void altivec_init_builtins (void);
1259 static tree
builtin_function_type (machine_mode
, machine_mode
,
1260 machine_mode
, machine_mode
,
1261 enum rs6000_builtins
, const char *name
);
1262 static void rs6000_common_init_builtins (void);
1263 static void paired_init_builtins (void);
1264 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1265 static void spe_init_builtins (void);
1266 static void htm_init_builtins (void);
1267 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1268 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1269 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1270 static rs6000_stack_t
*rs6000_stack_info (void);
1271 static void is_altivec_return_reg (rtx
, void *);
1272 int easy_vector_constant (rtx
, machine_mode
);
1273 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, machine_mode
);
1274 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1275 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1278 static void macho_branch_islands (void);
1280 static rtx
rs6000_legitimize_reload_address (rtx
, machine_mode
, int, int,
1282 static rtx
rs6000_debug_legitimize_reload_address (rtx
, machine_mode
, int,
1284 static bool rs6000_mode_dependent_address (const_rtx
);
1285 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1286 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1288 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1291 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1292 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1294 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1296 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1299 static bool rs6000_cannot_change_mode_class (machine_mode
,
1302 static bool rs6000_debug_cannot_change_mode_class (machine_mode
,
1305 static bool rs6000_save_toc_in_prologue_p (void);
1306 static rtx
rs6000_internal_arg_pointer (void);
1308 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, machine_mode
, int, int,
1310 = rs6000_legitimize_reload_address
;
1312 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1313 = rs6000_mode_dependent_address
;
1315 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1317 = rs6000_secondary_reload_class
;
1319 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1320 = rs6000_preferred_reload_class
;
1322 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1324 = rs6000_secondary_memory_needed
;
1326 bool (*rs6000_cannot_change_mode_class_ptr
) (machine_mode
,
1329 = rs6000_cannot_change_mode_class
;
1331 const int INSN_NOT_AVAILABLE
= -1;
1333 static void rs6000_print_isa_options (FILE *, int, const char *,
1335 static void rs6000_print_builtin_options (FILE *, int, const char *,
1338 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1339 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1340 enum rs6000_reg_type
,
1342 secondary_reload_info
*,
1344 rtl_opt_pass
*make_pass_analyze_swaps (gcc::context
*);
1345 static bool rs6000_keep_leaf_when_profiled () __attribute__ ((unused
));
1346 static tree
rs6000_fold_builtin (tree
, int, tree
*, bool);
1348 /* Hash table stuff for keeping track of TOC entries. */
1350 struct GTY((for_user
)) toc_hash_struct
1352 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1353 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1355 machine_mode key_mode
;
1359 struct toc_hasher
: ggc_ptr_hash
<toc_hash_struct
>
1361 static hashval_t
hash (toc_hash_struct
*);
1362 static bool equal (toc_hash_struct
*, toc_hash_struct
*);
1365 static GTY (()) hash_table
<toc_hasher
> *toc_hash_table
;
1367 /* Hash table to keep track of the argument types for builtin functions. */
1369 struct GTY((for_user
)) builtin_hash_struct
1372 machine_mode mode
[4]; /* return value + 3 arguments. */
1373 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1376 struct builtin_hasher
: ggc_ptr_hash
<builtin_hash_struct
>
1378 static hashval_t
hash (builtin_hash_struct
*);
1379 static bool equal (builtin_hash_struct
*, builtin_hash_struct
*);
1382 static GTY (()) hash_table
<builtin_hasher
> *builtin_hash_table
;
1385 /* Default register names. */
1386 char rs6000_reg_names
[][8] =
1388 "0", "1", "2", "3", "4", "5", "6", "7",
1389 "8", "9", "10", "11", "12", "13", "14", "15",
1390 "16", "17", "18", "19", "20", "21", "22", "23",
1391 "24", "25", "26", "27", "28", "29", "30", "31",
1392 "0", "1", "2", "3", "4", "5", "6", "7",
1393 "8", "9", "10", "11", "12", "13", "14", "15",
1394 "16", "17", "18", "19", "20", "21", "22", "23",
1395 "24", "25", "26", "27", "28", "29", "30", "31",
1396 "mq", "lr", "ctr","ap",
1397 "0", "1", "2", "3", "4", "5", "6", "7",
1399 /* AltiVec registers. */
1400 "0", "1", "2", "3", "4", "5", "6", "7",
1401 "8", "9", "10", "11", "12", "13", "14", "15",
1402 "16", "17", "18", "19", "20", "21", "22", "23",
1403 "24", "25", "26", "27", "28", "29", "30", "31",
1405 /* SPE registers. */
1406 "spe_acc", "spefscr",
1407 /* Soft frame pointer. */
1409 /* HTM SPR registers. */
1410 "tfhar", "tfiar", "texasr",
1411 /* SPE High registers. */
1412 "0", "1", "2", "3", "4", "5", "6", "7",
1413 "8", "9", "10", "11", "12", "13", "14", "15",
1414 "16", "17", "18", "19", "20", "21", "22", "23",
1415 "24", "25", "26", "27", "28", "29", "30", "31"
1418 #ifdef TARGET_REGNAMES
1419 static const char alt_reg_names
[][8] =
1421 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1422 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1423 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1424 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1425 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1426 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1427 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1428 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1429 "mq", "lr", "ctr", "ap",
1430 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1432 /* AltiVec registers. */
1433 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1434 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1435 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1436 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1438 /* SPE registers. */
1439 "spe_acc", "spefscr",
1440 /* Soft frame pointer. */
1442 /* HTM SPR registers. */
1443 "tfhar", "tfiar", "texasr",
1444 /* SPE High registers. */
1445 "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7",
1446 "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15",
1447 "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23",
1448 "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31"
1452 /* Table of valid machine attributes. */
1454 static const struct attribute_spec rs6000_attribute_table
[] =
1456 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1457 affects_type_identity } */
1458 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1460 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1462 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1464 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1466 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1468 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1469 SUBTARGET_ATTRIBUTE_TABLE
,
1471 { NULL
, 0, 0, false, false, false, NULL
, false }
1474 #ifndef TARGET_PROFILE_KERNEL
1475 #define TARGET_PROFILE_KERNEL 0
1478 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1479 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1481 /* Initialize the GCC target structure. */
1482 #undef TARGET_ATTRIBUTE_TABLE
1483 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1484 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1485 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1486 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1487 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1489 #undef TARGET_ASM_ALIGNED_DI_OP
1490 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1492 /* Default unaligned ops are only provided for ELF. Find the ops needed
1493 for non-ELF systems. */
1494 #ifndef OBJECT_FORMAT_ELF
1496 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1498 #undef TARGET_ASM_UNALIGNED_HI_OP
1499 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1500 #undef TARGET_ASM_UNALIGNED_SI_OP
1501 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1502 #undef TARGET_ASM_UNALIGNED_DI_OP
1503 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1506 #undef TARGET_ASM_UNALIGNED_HI_OP
1507 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1508 #undef TARGET_ASM_UNALIGNED_SI_OP
1509 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1510 #undef TARGET_ASM_UNALIGNED_DI_OP
1511 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1512 #undef TARGET_ASM_ALIGNED_DI_OP
1513 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1517 /* This hook deals with fixups for relocatable code and DI-mode objects
1519 #undef TARGET_ASM_INTEGER
1520 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1522 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1523 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1524 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1527 #undef TARGET_SET_UP_BY_PROLOGUE
1528 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1530 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
1531 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS rs6000_get_separate_components
1532 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
1533 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB rs6000_components_for_bb
1534 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
1535 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS rs6000_disqualify_components
1536 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
1537 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS rs6000_emit_prologue_components
1538 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
1539 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS rs6000_emit_epilogue_components
1540 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
1541 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS rs6000_set_handled_components
1543 #undef TARGET_EXTRA_LIVE_ON_ENTRY
1544 #define TARGET_EXTRA_LIVE_ON_ENTRY rs6000_live_on_entry
1546 #undef TARGET_INTERNAL_ARG_POINTER
1547 #define TARGET_INTERNAL_ARG_POINTER rs6000_internal_arg_pointer
1549 #undef TARGET_HAVE_TLS
1550 #define TARGET_HAVE_TLS HAVE_AS_TLS
1552 #undef TARGET_CANNOT_FORCE_CONST_MEM
1553 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1555 #undef TARGET_DELEGITIMIZE_ADDRESS
1556 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1558 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1559 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1561 #undef TARGET_ASM_FUNCTION_PROLOGUE
1562 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1563 #undef TARGET_ASM_FUNCTION_EPILOGUE
1564 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1566 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1567 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1569 #undef TARGET_LEGITIMIZE_ADDRESS
1570 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1572 #undef TARGET_SCHED_VARIABLE_ISSUE
1573 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1575 #undef TARGET_SCHED_ISSUE_RATE
1576 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1577 #undef TARGET_SCHED_ADJUST_COST
1578 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1579 #undef TARGET_SCHED_ADJUST_PRIORITY
1580 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1581 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1582 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1583 #undef TARGET_SCHED_INIT
1584 #define TARGET_SCHED_INIT rs6000_sched_init
1585 #undef TARGET_SCHED_FINISH
1586 #define TARGET_SCHED_FINISH rs6000_sched_finish
1587 #undef TARGET_SCHED_REORDER
1588 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1589 #undef TARGET_SCHED_REORDER2
1590 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1592 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1593 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1595 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1596 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1598 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1599 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1600 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1601 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1602 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1603 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1604 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1605 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1607 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1608 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1609 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1610 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1611 rs6000_builtin_support_vector_misalignment
1612 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1613 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1614 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1615 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1616 rs6000_builtin_vectorization_cost
1617 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1618 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1619 rs6000_preferred_simd_mode
1620 #undef TARGET_VECTORIZE_INIT_COST
1621 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1622 #undef TARGET_VECTORIZE_ADD_STMT_COST
1623 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1624 #undef TARGET_VECTORIZE_FINISH_COST
1625 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1626 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1627 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1629 #undef TARGET_INIT_BUILTINS
1630 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1631 #undef TARGET_BUILTIN_DECL
1632 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1634 #undef TARGET_FOLD_BUILTIN
1635 #define TARGET_FOLD_BUILTIN rs6000_fold_builtin
1636 #undef TARGET_GIMPLE_FOLD_BUILTIN
1637 #define TARGET_GIMPLE_FOLD_BUILTIN rs6000_gimple_fold_builtin
1639 #undef TARGET_EXPAND_BUILTIN
1640 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1642 #undef TARGET_MANGLE_TYPE
1643 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1645 #undef TARGET_INIT_LIBFUNCS
1646 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1649 #undef TARGET_BINDS_LOCAL_P
1650 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1653 #undef TARGET_MS_BITFIELD_LAYOUT_P
1654 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1656 #undef TARGET_ASM_OUTPUT_MI_THUNK
1657 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1659 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1660 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1662 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1663 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1665 #undef TARGET_REGISTER_MOVE_COST
1666 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1667 #undef TARGET_MEMORY_MOVE_COST
1668 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1669 #undef TARGET_CANNOT_COPY_INSN_P
1670 #define TARGET_CANNOT_COPY_INSN_P rs6000_cannot_copy_insn_p
1671 #undef TARGET_RTX_COSTS
1672 #define TARGET_RTX_COSTS rs6000_rtx_costs
1673 #undef TARGET_ADDRESS_COST
1674 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1676 #undef TARGET_DWARF_REGISTER_SPAN
1677 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1679 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1680 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1682 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1683 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1685 #undef TARGET_PROMOTE_FUNCTION_MODE
1686 #define TARGET_PROMOTE_FUNCTION_MODE rs6000_promote_function_mode
1688 #undef TARGET_RETURN_IN_MEMORY
1689 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1691 #undef TARGET_RETURN_IN_MSB
1692 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1694 #undef TARGET_SETUP_INCOMING_VARARGS
1695 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1697 /* Always strict argument naming on rs6000. */
1698 #undef TARGET_STRICT_ARGUMENT_NAMING
1699 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1700 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1701 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1702 #undef TARGET_SPLIT_COMPLEX_ARG
1703 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1704 #undef TARGET_MUST_PASS_IN_STACK
1705 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1706 #undef TARGET_PASS_BY_REFERENCE
1707 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1708 #undef TARGET_ARG_PARTIAL_BYTES
1709 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1710 #undef TARGET_FUNCTION_ARG_ADVANCE
1711 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1712 #undef TARGET_FUNCTION_ARG
1713 #define TARGET_FUNCTION_ARG rs6000_function_arg
1714 #undef TARGET_FUNCTION_ARG_BOUNDARY
1715 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1717 #undef TARGET_BUILD_BUILTIN_VA_LIST
1718 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1720 #undef TARGET_EXPAND_BUILTIN_VA_START
1721 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1723 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1724 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1726 #undef TARGET_EH_RETURN_FILTER_MODE
1727 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1729 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1730 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1732 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1733 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1735 #undef TARGET_FLOATN_MODE
1736 #define TARGET_FLOATN_MODE rs6000_floatn_mode
1738 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1739 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1741 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1742 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1744 #undef TARGET_MD_ASM_ADJUST
1745 #define TARGET_MD_ASM_ADJUST rs6000_md_asm_adjust
1747 #undef TARGET_OPTION_OVERRIDE
1748 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1750 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1751 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1752 rs6000_builtin_vectorized_function
1754 #undef TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION
1755 #define TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION \
1756 rs6000_builtin_md_vectorized_function
1758 #ifdef TARGET_THREAD_SSP_OFFSET
1759 #undef TARGET_STACK_PROTECT_GUARD
1760 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null
1764 #undef TARGET_STACK_PROTECT_FAIL
1765 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1769 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1770 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1773 /* Use a 32-bit anchor range. This leads to sequences like:
1775 addis tmp,anchor,high
1778 where tmp itself acts as an anchor, and can be shared between
1779 accesses to the same 64k page. */
1780 #undef TARGET_MIN_ANCHOR_OFFSET
1781 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1782 #undef TARGET_MAX_ANCHOR_OFFSET
1783 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1784 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1785 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1786 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1787 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1789 #undef TARGET_BUILTIN_RECIPROCAL
1790 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1792 #undef TARGET_EXPAND_TO_RTL_HOOK
1793 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1795 #undef TARGET_INSTANTIATE_DECLS
1796 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1798 #undef TARGET_SECONDARY_RELOAD
1799 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1801 #undef TARGET_LEGITIMATE_ADDRESS_P
1802 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1804 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1805 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1808 #define TARGET_LRA_P rs6000_lra_p
1810 #undef TARGET_CAN_ELIMINATE
1811 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1813 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1814 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1816 #undef TARGET_SCHED_REASSOCIATION_WIDTH
1817 #define TARGET_SCHED_REASSOCIATION_WIDTH rs6000_reassociation_width
1819 #undef TARGET_TRAMPOLINE_INIT
1820 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1822 #undef TARGET_FUNCTION_VALUE
1823 #define TARGET_FUNCTION_VALUE rs6000_function_value
1825 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1826 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1828 #undef TARGET_OPTION_SAVE
1829 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1831 #undef TARGET_OPTION_RESTORE
1832 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1834 #undef TARGET_OPTION_PRINT
1835 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1837 #undef TARGET_CAN_INLINE_P
1838 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1840 #undef TARGET_SET_CURRENT_FUNCTION
1841 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1843 #undef TARGET_LEGITIMATE_CONSTANT_P
1844 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1846 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1847 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1849 #undef TARGET_CAN_USE_DOLOOP_P
1850 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1852 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
1853 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV rs6000_atomic_assign_expand_fenv
1855 #undef TARGET_LIBGCC_CMP_RETURN_MODE
1856 #define TARGET_LIBGCC_CMP_RETURN_MODE rs6000_abi_word_mode
1857 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
1858 #define TARGET_LIBGCC_SHIFT_COUNT_MODE rs6000_abi_word_mode
1859 #undef TARGET_UNWIND_WORD_MODE
1860 #define TARGET_UNWIND_WORD_MODE rs6000_abi_word_mode
1862 #undef TARGET_OFFLOAD_OPTIONS
1863 #define TARGET_OFFLOAD_OPTIONS rs6000_offload_options
1865 #undef TARGET_C_MODE_FOR_SUFFIX
1866 #define TARGET_C_MODE_FOR_SUFFIX rs6000_c_mode_for_suffix
1868 #undef TARGET_INVALID_BINARY_OP
1869 #define TARGET_INVALID_BINARY_OP rs6000_invalid_binary_op
1871 #undef TARGET_OPTAB_SUPPORTED_P
1872 #define TARGET_OPTAB_SUPPORTED_P rs6000_optab_supported_p
1874 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
1875 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
1878 /* Processor table. */
1881 const char *const name
; /* Canonical processor name. */
1882 const enum processor_type processor
; /* Processor type enum value. */
1883 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1886 static struct rs6000_ptt
const processor_target_table
[] =
1888 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1889 #include "rs6000-cpus.def"
1893 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1897 rs6000_cpu_name_lookup (const char *name
)
1903 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1904 if (! strcmp (name
, processor_target_table
[i
].name
))
1912 /* Return number of consecutive hard regs needed starting at reg REGNO
1913 to hold something of mode MODE.
1914 This is ordinarily the length in words of a value of mode MODE
1915 but can be less for certain modes in special long registers.
1917 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1918 scalar instructions. The upper 32 bits are only available to the
1921 POWER and PowerPC GPRs hold 32 bits worth;
1922 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1925 rs6000_hard_regno_nregs_internal (int regno
, machine_mode mode
)
1927 unsigned HOST_WIDE_INT reg_size
;
1929 /* 128-bit floating point usually takes 2 registers, unless it is IEEE
1930 128-bit floating point that can go in vector registers, which has VSX
1931 memory addressing. */
1932 if (FP_REGNO_P (regno
))
1933 reg_size
= (VECTOR_MEM_VSX_P (mode
) || FLOAT128_VECTOR_P (mode
)
1934 ? UNITS_PER_VSX_WORD
1935 : UNITS_PER_FP_WORD
);
1937 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1938 reg_size
= UNITS_PER_SPE_WORD
;
1940 else if (ALTIVEC_REGNO_P (regno
))
1941 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1943 /* The value returned for SCmode in the E500 double case is 2 for
1944 ABI compatibility; storing an SCmode value in a single register
1945 would require function_arg and rs6000_spe_function_arg to handle
1946 SCmode so as to pass the value correctly in a pair of
1948 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1949 && !DECIMAL_FLOAT_MODE_P (mode
) && SPE_SIMD_REGNO_P (regno
))
1950 reg_size
= UNITS_PER_FP_WORD
;
1953 reg_size
= UNITS_PER_WORD
;
1955 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1958 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1961 rs6000_hard_regno_mode_ok (int regno
, machine_mode mode
)
1963 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1965 if (COMPLEX_MODE_P (mode
))
1966 mode
= GET_MODE_INNER (mode
);
1968 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1969 register combinations, and use PTImode where we need to deal with quad
1970 word memory operations. Don't allow quad words in the argument or frame
1971 pointer registers, just registers 0..31. */
1972 if (mode
== PTImode
)
1973 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1974 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1975 && ((regno
& 1) == 0));
1977 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1978 implementations. Don't allow an item to be split between a FP register
1979 and an Altivec register. Allow TImode in all VSX registers if the user
1981 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1982 && (VECTOR_MEM_VSX_P (mode
)
1983 || FLOAT128_VECTOR_P (mode
)
1984 || reg_addr
[mode
].scalar_in_vmx_p
1985 || (TARGET_VSX_TIMODE
&& mode
== TImode
)
1986 || (TARGET_VADDUQM
&& mode
== V1TImode
)))
1988 if (FP_REGNO_P (regno
))
1989 return FP_REGNO_P (last_regno
);
1991 if (ALTIVEC_REGNO_P (regno
))
1993 if (GET_MODE_SIZE (mode
) != 16 && !reg_addr
[mode
].scalar_in_vmx_p
)
1996 return ALTIVEC_REGNO_P (last_regno
);
2000 /* The GPRs can hold any mode, but values bigger than one register
2001 cannot go past R31. */
2002 if (INT_REGNO_P (regno
))
2003 return INT_REGNO_P (last_regno
);
2005 /* The float registers (except for VSX vector modes) can only hold floating
2006 modes and DImode. */
2007 if (FP_REGNO_P (regno
))
2009 if (FLOAT128_VECTOR_P (mode
))
2012 if (SCALAR_FLOAT_MODE_P (mode
)
2013 && (mode
!= TDmode
|| (regno
% 2) == 0)
2014 && FP_REGNO_P (last_regno
))
2017 if (GET_MODE_CLASS (mode
) == MODE_INT
)
2019 if(GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
2022 if (TARGET_VSX_SMALL_INTEGER
&& mode
== SImode
)
2026 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
2027 && PAIRED_VECTOR_MODE (mode
))
2033 /* The CR register can only hold CC modes. */
2034 if (CR_REGNO_P (regno
))
2035 return GET_MODE_CLASS (mode
) == MODE_CC
;
2037 if (CA_REGNO_P (regno
))
2038 return mode
== Pmode
|| mode
== SImode
;
2040 /* AltiVec only in AldyVec registers. */
2041 if (ALTIVEC_REGNO_P (regno
))
2042 return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
)
2043 || mode
== V1TImode
);
2045 /* ...but GPRs can hold SIMD data on the SPE in one register. */
2046 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
2049 /* We cannot put non-VSX TImode or PTImode anywhere except general register
2050 and it must be able to fit within the register set. */
2052 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
2055 /* Print interesting facts about registers. */
2057 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
2061 for (r
= first_regno
; r
<= last_regno
; ++r
)
2063 const char *comma
= "";
2066 if (first_regno
== last_regno
)
2067 fprintf (stderr
, "%s:\t", reg_name
);
2069 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
2072 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2073 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
2077 fprintf (stderr
, ",\n\t");
2082 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
2083 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
2084 rs6000_hard_regno_nregs
[m
][r
]);
2086 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
2091 if (call_used_regs
[r
])
2095 fprintf (stderr
, ",\n\t");
2100 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
2108 fprintf (stderr
, ",\n\t");
2113 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
2119 fprintf (stderr
, ",\n\t");
2123 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
2124 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
2129 fprintf (stderr
, ",\n\t");
2133 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
2138 rs6000_debug_vector_unit (enum rs6000_vector v
)
2144 case VECTOR_NONE
: ret
= "none"; break;
2145 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
2146 case VECTOR_VSX
: ret
= "vsx"; break;
2147 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
2148 case VECTOR_PAIRED
: ret
= "paired"; break;
2149 case VECTOR_SPE
: ret
= "spe"; break;
2150 case VECTOR_OTHER
: ret
= "other"; break;
2151 default: ret
= "unknown"; break;
2157 /* Inner function printing just the address mask for a particular reload
2159 DEBUG_FUNCTION
char *
2160 rs6000_debug_addr_mask (addr_mask_type mask
, bool keep_spaces
)
2165 if ((mask
& RELOAD_REG_VALID
) != 0)
2167 else if (keep_spaces
)
2170 if ((mask
& RELOAD_REG_MULTIPLE
) != 0)
2172 else if (keep_spaces
)
2175 if ((mask
& RELOAD_REG_INDEXED
) != 0)
2177 else if (keep_spaces
)
2180 if ((mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
2182 else if ((mask
& RELOAD_REG_OFFSET
) != 0)
2184 else if (keep_spaces
)
2187 if ((mask
& RELOAD_REG_PRE_INCDEC
) != 0)
2189 else if (keep_spaces
)
2192 if ((mask
& RELOAD_REG_PRE_MODIFY
) != 0)
2194 else if (keep_spaces
)
2197 if ((mask
& RELOAD_REG_AND_M16
) != 0)
2199 else if (keep_spaces
)
2207 /* Print the address masks in a human readble fashion. */
2209 rs6000_debug_print_mode (ssize_t m
)
2215 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
2216 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2217 fprintf (stderr
, " %s: %s", reload_reg_map
[rc
].name
,
2218 rs6000_debug_addr_mask (reg_addr
[m
].addr_mask
[rc
], true));
2220 if ((reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
2221 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
2222 fprintf (stderr
, " Reload=%c%c",
2223 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
2224 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
2226 spaces
+= sizeof (" Reload=sl") - 1;
2228 if (reg_addr
[m
].scalar_in_vmx_p
)
2230 fprintf (stderr
, "%*s Upper=y", spaces
, "");
2234 spaces
+= sizeof (" Upper=y") - 1;
2236 fuse_extra_p
= ((reg_addr
[m
].fusion_gpr_ld
!= CODE_FOR_nothing
)
2237 || reg_addr
[m
].fused_toc
);
2240 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2242 if (rc
!= RELOAD_REG_ANY
)
2244 if (reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
2245 || reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
2246 || reg_addr
[m
].fusion_addi_st
[rc
] != CODE_FOR_nothing
2247 || reg_addr
[m
].fusion_addis_ld
[rc
] != CODE_FOR_nothing
2248 || reg_addr
[m
].fusion_addis_st
[rc
] != CODE_FOR_nothing
)
2250 fuse_extra_p
= true;
2259 fprintf (stderr
, "%*s Fuse:", spaces
, "");
2262 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
2264 if (rc
!= RELOAD_REG_ANY
)
2268 if (reg_addr
[m
].fusion_addis_ld
[rc
] != CODE_FOR_nothing
)
2270 else if (reg_addr
[m
].fusion_addi_ld
[rc
] != CODE_FOR_nothing
)
2275 if (reg_addr
[m
].fusion_addis_st
[rc
] != CODE_FOR_nothing
)
2277 else if (reg_addr
[m
].fusion_addi_st
[rc
] != CODE_FOR_nothing
)
2282 if (load
== '-' && store
== '-')
2286 fprintf (stderr
, "%*s%c=%c%c", (spaces
+ 1), "",
2287 reload_reg_map
[rc
].name
[0], load
, store
);
2293 if (reg_addr
[m
].fusion_gpr_ld
!= CODE_FOR_nothing
)
2295 fprintf (stderr
, "%*sP8gpr", (spaces
+ 1), "");
2299 spaces
+= sizeof (" P8gpr") - 1;
2301 if (reg_addr
[m
].fused_toc
)
2303 fprintf (stderr
, "%*sToc", (spaces
+ 1), "");
2307 spaces
+= sizeof (" Toc") - 1;
2310 spaces
+= sizeof (" Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
2312 if (rs6000_vector_unit
[m
] != VECTOR_NONE
2313 || rs6000_vector_mem
[m
] != VECTOR_NONE
)
2315 fprintf (stderr
, "%*s vector: arith=%-10s mem=%s",
2317 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
2318 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]));
2321 fputs ("\n", stderr
);
2324 #define DEBUG_FMT_ID "%-32s= "
2325 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
2326 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
2327 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
2329 /* Print various interesting information with -mdebug=reg. */
2331 rs6000_debug_reg_global (void)
2333 static const char *const tf
[2] = { "false", "true" };
2334 const char *nl
= (const char *)0;
2337 char costly_num
[20];
2339 char flags_buffer
[40];
2340 const char *costly_str
;
2341 const char *nop_str
;
2342 const char *trace_str
;
2343 const char *abi_str
;
2344 const char *cmodel_str
;
2345 struct cl_target_option cl_opts
;
2347 /* Modes we want tieable information on. */
2348 static const machine_mode print_tieable_modes
[] = {
2386 /* Virtual regs we are interested in. */
2387 const static struct {
2388 int regno
; /* register number. */
2389 const char *name
; /* register name. */
2390 } virtual_regs
[] = {
2391 { STACK_POINTER_REGNUM
, "stack pointer:" },
2392 { TOC_REGNUM
, "toc: " },
2393 { STATIC_CHAIN_REGNUM
, "static chain: " },
2394 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
2395 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
2396 { ARG_POINTER_REGNUM
, "arg pointer: " },
2397 { FRAME_POINTER_REGNUM
, "frame pointer:" },
2398 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
2399 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
2400 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
2401 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
2402 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
2403 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
2404 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
2405 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
2406 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2409 fputs ("\nHard register information:\n", stderr
);
2410 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2411 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2412 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2415 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2416 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2417 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2418 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2419 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2420 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2421 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2422 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2424 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2425 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2426 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2430 "d reg_class = %s\n"
2431 "f reg_class = %s\n"
2432 "v reg_class = %s\n"
2433 "wa reg_class = %s\n"
2434 "wb reg_class = %s\n"
2435 "wd reg_class = %s\n"
2436 "we reg_class = %s\n"
2437 "wf reg_class = %s\n"
2438 "wg reg_class = %s\n"
2439 "wh reg_class = %s\n"
2440 "wi reg_class = %s\n"
2441 "wj reg_class = %s\n"
2442 "wk reg_class = %s\n"
2443 "wl reg_class = %s\n"
2444 "wm reg_class = %s\n"
2445 "wo reg_class = %s\n"
2446 "wp reg_class = %s\n"
2447 "wq reg_class = %s\n"
2448 "wr reg_class = %s\n"
2449 "ws reg_class = %s\n"
2450 "wt reg_class = %s\n"
2451 "wu reg_class = %s\n"
2452 "wv reg_class = %s\n"
2453 "ww reg_class = %s\n"
2454 "wx reg_class = %s\n"
2455 "wy reg_class = %s\n"
2456 "wz reg_class = %s\n"
2457 "wH reg_class = %s\n"
2458 "wI reg_class = %s\n"
2459 "wJ reg_class = %s\n"
2460 "wK reg_class = %s\n"
2462 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2463 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2464 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2465 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2466 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wb
]],
2467 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2468 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_we
]],
2469 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2470 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2471 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wh
]],
2472 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wi
]],
2473 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wj
]],
2474 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wk
]],
2475 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2476 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2477 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wo
]],
2478 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wp
]],
2479 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wq
]],
2480 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2481 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2482 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2483 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2484 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2485 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2486 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2487 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2488 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]],
2489 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wH
]],
2490 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wI
]],
2491 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wJ
]],
2492 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wK
]]);
2495 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2496 rs6000_debug_print_mode (m
);
2498 fputs ("\n", stderr
);
2500 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2502 machine_mode mode1
= print_tieable_modes
[m1
];
2503 bool first_time
= true;
2505 nl
= (const char *)0;
2506 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2508 machine_mode mode2
= print_tieable_modes
[m2
];
2509 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2513 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2518 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2523 fputs ("\n", stderr
);
2529 if (rs6000_recip_control
)
2531 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2533 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2534 if (rs6000_recip_bits
[m
])
2537 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2539 (RS6000_RECIP_AUTO_RE_P (m
)
2541 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2542 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2544 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2547 fputs ("\n", stderr
);
2550 if (rs6000_cpu_index
>= 0)
2552 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2554 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2556 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2557 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2560 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2562 if (rs6000_tune_index
>= 0)
2564 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2566 = processor_target_table
[rs6000_tune_index
].target_enable
;
2568 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2569 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2572 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2574 cl_target_option_save (&cl_opts
, &global_options
);
2575 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2578 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2579 rs6000_isa_flags_explicit
);
2581 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2582 rs6000_builtin_mask
);
2584 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2586 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2587 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2589 switch (rs6000_sched_costly_dep
)
2591 case max_dep_latency
:
2592 costly_str
= "max_dep_latency";
2596 costly_str
= "no_dep_costly";
2599 case all_deps_costly
:
2600 costly_str
= "all_deps_costly";
2603 case true_store_to_load_dep_costly
:
2604 costly_str
= "true_store_to_load_dep_costly";
2607 case store_to_load_dep_costly
:
2608 costly_str
= "store_to_load_dep_costly";
2612 costly_str
= costly_num
;
2613 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2617 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2619 switch (rs6000_sched_insert_nops
)
2621 case sched_finish_regroup_exact
:
2622 nop_str
= "sched_finish_regroup_exact";
2625 case sched_finish_pad_groups
:
2626 nop_str
= "sched_finish_pad_groups";
2629 case sched_finish_none
:
2630 nop_str
= "sched_finish_none";
2635 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2639 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2641 switch (rs6000_sdata
)
2648 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2652 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2656 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2661 switch (rs6000_traceback
)
2663 case traceback_default
: trace_str
= "default"; break;
2664 case traceback_none
: trace_str
= "none"; break;
2665 case traceback_part
: trace_str
= "part"; break;
2666 case traceback_full
: trace_str
= "full"; break;
2667 default: trace_str
= "unknown"; break;
2670 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2672 switch (rs6000_current_cmodel
)
2674 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2675 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2676 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2677 default: cmodel_str
= "unknown"; break;
2680 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2682 switch (rs6000_current_abi
)
2684 case ABI_NONE
: abi_str
= "none"; break;
2685 case ABI_AIX
: abi_str
= "aix"; break;
2686 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2687 case ABI_V4
: abi_str
= "V4"; break;
2688 case ABI_DARWIN
: abi_str
= "darwin"; break;
2689 default: abi_str
= "unknown"; break;
2692 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2694 if (rs6000_altivec_abi
)
2695 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2698 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2700 if (rs6000_darwin64_abi
)
2701 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2703 if (rs6000_float_gprs
)
2704 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2706 fprintf (stderr
, DEBUG_FMT_S
, "fprs",
2707 (TARGET_FPRS
? "true" : "false"));
2709 fprintf (stderr
, DEBUG_FMT_S
, "single_float",
2710 (TARGET_SINGLE_FLOAT
? "true" : "false"));
2712 fprintf (stderr
, DEBUG_FMT_S
, "double_float",
2713 (TARGET_DOUBLE_FLOAT
? "true" : "false"));
2715 fprintf (stderr
, DEBUG_FMT_S
, "soft_float",
2716 (TARGET_SOFT_FLOAT
? "true" : "false"));
2718 fprintf (stderr
, DEBUG_FMT_S
, "e500_single",
2719 (TARGET_E500_SINGLE
? "true" : "false"));
2721 fprintf (stderr
, DEBUG_FMT_S
, "e500_double",
2722 (TARGET_E500_DOUBLE
? "true" : "false"));
2724 if (TARGET_LINK_STACK
)
2725 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2727 fprintf (stderr
, DEBUG_FMT_S
, "lra", TARGET_LRA
? "true" : "false");
2729 if (TARGET_P8_FUSION
)
2733 strcpy (options
, (TARGET_P9_FUSION
) ? "power9" : "power8");
2734 if (TARGET_TOC_FUSION
)
2735 strcat (options
, ", toc");
2737 if (TARGET_P8_FUSION_SIGN
)
2738 strcat (options
, ", sign");
2740 fprintf (stderr
, DEBUG_FMT_S
, "fusion", options
);
2743 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2744 TARGET_SECURE_PLT
? "secure" : "bss");
2745 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2746 aix_struct_return
? "aix" : "sysv");
2747 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2748 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2749 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2750 tf
[!!rs6000_align_branch_targets
]);
2751 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2752 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2753 rs6000_long_double_type_size
);
2754 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2755 (int)rs6000_sched_restricted_insns_priority
);
2756 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2758 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2759 (int)RS6000_BUILTIN_COUNT
);
2761 fprintf (stderr
, DEBUG_FMT_D
, "Enable float128 on VSX",
2762 (int)TARGET_FLOAT128_ENABLE_TYPE
);
2765 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit scalar element",
2766 (int)VECTOR_ELEMENT_SCALAR_64BIT
);
2768 if (TARGET_DIRECT_MOVE_128
)
2769 fprintf (stderr
, DEBUG_FMT_D
, "VSX easy 64-bit mfvsrld element",
2770 (int)VECTOR_ELEMENT_MFVSRLD_64BIT
);
2774 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2775 legitimate address support to figure out the appropriate addressing to
2779 rs6000_setup_reg_addr_masks (void)
2781 ssize_t rc
, reg
, m
, nregs
;
2782 addr_mask_type any_addr_mask
, addr_mask
;
2784 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2786 machine_mode m2
= (machine_mode
) m
;
2787 bool complex_p
= false;
2788 bool small_int_p
= (m2
== QImode
|| m2
== HImode
|| m2
== SImode
);
2791 if (COMPLEX_MODE_P (m2
))
2794 m2
= GET_MODE_INNER (m2
);
2797 msize
= GET_MODE_SIZE (m2
);
2799 /* SDmode is special in that we want to access it only via REG+REG
2800 addressing on power7 and above, since we want to use the LFIWZX and
2801 STFIWZX instructions to load it. */
2802 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2805 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2808 reg
= reload_reg_map
[rc
].reg
;
2810 /* Can mode values go in the GPR/FPR/Altivec registers? */
2811 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2813 bool small_int_vsx_p
= (small_int_p
2814 && (rc
== RELOAD_REG_FPR
2815 || rc
== RELOAD_REG_VMX
));
2817 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2818 addr_mask
|= RELOAD_REG_VALID
;
2820 /* Indicate if the mode takes more than 1 physical register. If
2821 it takes a single register, indicate it can do REG+REG
2822 addressing. Small integers in VSX registers can only do
2823 REG+REG addressing. */
2824 if (small_int_vsx_p
)
2825 addr_mask
|= RELOAD_REG_INDEXED
;
2826 else if (nregs
> 1 || m
== BLKmode
|| complex_p
)
2827 addr_mask
|= RELOAD_REG_MULTIPLE
;
2829 addr_mask
|= RELOAD_REG_INDEXED
;
2831 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2832 addressing. Restrict addressing on SPE for 64-bit types
2833 because of the SUBREG hackery used to address 64-bit floats in
2834 '32-bit' GPRs. If we allow scalars into Altivec registers,
2835 don't allow PRE_INC, PRE_DEC, or PRE_MODIFY. */
2838 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2840 && !VECTOR_MODE_P (m2
)
2841 && !FLOAT128_VECTOR_P (m2
)
2844 && (m2
!= DFmode
|| !TARGET_UPPER_REGS_DF
)
2845 && (m2
!= SFmode
|| !TARGET_UPPER_REGS_SF
)
2846 && !(TARGET_E500_DOUBLE
&& msize
== 8))
2848 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2850 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2851 we don't allow PRE_MODIFY for some multi-register
2856 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2860 if (TARGET_POWERPC64
)
2861 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2867 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2873 /* GPR and FPR registers can do REG+OFFSET addressing, except
2874 possibly for SDmode. ISA 3.0 (i.e. power9) adds D-form addressing
2875 for 64-bit scalars and 32-bit SFmode to altivec registers. */
2876 if ((addr_mask
!= 0) && !indexed_only_p
2878 && (rc
== RELOAD_REG_GPR
2879 || ((msize
== 8 || m2
== SFmode
)
2880 && (rc
== RELOAD_REG_FPR
2881 || (rc
== RELOAD_REG_VMX
2882 && TARGET_P9_DFORM_SCALAR
)))))
2883 addr_mask
|= RELOAD_REG_OFFSET
;
2885 /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
2886 instructions are enabled. The offset for 128-bit VSX registers is
2887 only 12-bits. While GPRs can handle the full offset range, VSX
2888 registers can only handle the restricted range. */
2889 else if ((addr_mask
!= 0) && !indexed_only_p
2890 && msize
== 16 && TARGET_P9_DFORM_VECTOR
2891 && (ALTIVEC_OR_VSX_VECTOR_MODE (m2
)
2892 || (m2
== TImode
&& TARGET_VSX_TIMODE
)))
2894 addr_mask
|= RELOAD_REG_OFFSET
;
2895 if (rc
== RELOAD_REG_FPR
|| rc
== RELOAD_REG_VMX
)
2896 addr_mask
|= RELOAD_REG_QUAD_OFFSET
;
2899 /* VMX registers can do (REG & -16) and ((REG+REG) & -16)
2900 addressing on 128-bit types. */
2901 if (rc
== RELOAD_REG_VMX
&& msize
== 16
2902 && (addr_mask
& RELOAD_REG_VALID
) != 0)
2903 addr_mask
|= RELOAD_REG_AND_M16
;
2905 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2906 any_addr_mask
|= addr_mask
;
2909 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2914 /* Initialize the various global tables that are based on register size. */
2916 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2922 /* Precalculate REGNO_REG_CLASS. */
2923 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2924 for (r
= 1; r
< 32; ++r
)
2925 rs6000_regno_regclass
[r
] = BASE_REGS
;
2927 for (r
= 32; r
< 64; ++r
)
2928 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2930 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2931 rs6000_regno_regclass
[r
] = NO_REGS
;
2933 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2934 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2936 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2937 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2938 rs6000_regno_regclass
[r
] = CR_REGS
;
2940 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2941 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2942 rs6000_regno_regclass
[CA_REGNO
] = NO_REGS
;
2943 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2944 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2945 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2946 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2947 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2948 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2949 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2950 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2951 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2953 /* Precalculate register class to simpler reload register class. We don't
2954 need all of the register classes that are combinations of different
2955 classes, just the simple ones that have constraint letters. */
2956 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2957 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2959 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2960 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2961 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2962 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2963 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2964 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2965 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2966 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2967 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2968 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2969 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2970 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2974 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2975 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2979 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2980 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2983 /* Precalculate the valid memory formats as well as the vector information,
2984 this must be set up before the rs6000_hard_regno_nregs_internal calls
2986 gcc_assert ((int)VECTOR_NONE
== 0);
2987 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2988 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2990 gcc_assert ((int)CODE_FOR_nothing
== 0);
2991 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2993 gcc_assert ((int)NO_REGS
== 0);
2994 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2996 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2997 believes it can use native alignment or still uses 128-bit alignment. */
2998 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
3009 /* KF mode (IEEE 128-bit in VSX registers). We do not have arithmetic, so
3010 only set the memory modes. Include TFmode if -mabi=ieeelongdouble. */
3011 if (TARGET_FLOAT128_TYPE
)
3013 rs6000_vector_mem
[KFmode
] = VECTOR_VSX
;
3014 rs6000_vector_align
[KFmode
] = 128;
3016 if (FLOAT128_IEEE_P (TFmode
))
3018 rs6000_vector_mem
[TFmode
] = VECTOR_VSX
;
3019 rs6000_vector_align
[TFmode
] = 128;
3023 /* V2DF mode, VSX only. */
3026 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
3027 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
3028 rs6000_vector_align
[V2DFmode
] = align64
;
3031 /* V4SF mode, either VSX or Altivec. */
3034 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
3035 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
3036 rs6000_vector_align
[V4SFmode
] = align32
;
3038 else if (TARGET_ALTIVEC
)
3040 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
3041 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
3042 rs6000_vector_align
[V4SFmode
] = align32
;
3045 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
3049 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
3050 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
3051 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
3052 rs6000_vector_align
[V4SImode
] = align32
;
3053 rs6000_vector_align
[V8HImode
] = align32
;
3054 rs6000_vector_align
[V16QImode
] = align32
;
3058 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
3059 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
3060 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
3064 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
3065 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
3066 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
3070 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
3071 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
3074 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
3075 rs6000_vector_unit
[V2DImode
]
3076 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3077 rs6000_vector_align
[V2DImode
] = align64
;
3079 rs6000_vector_mem
[V1TImode
] = VECTOR_VSX
;
3080 rs6000_vector_unit
[V1TImode
]
3081 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
3082 rs6000_vector_align
[V1TImode
] = 128;
3085 /* DFmode, see if we want to use the VSX unit. Memory is handled
3086 differently, so don't set rs6000_vector_mem. */
3087 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
3089 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
3090 rs6000_vector_align
[DFmode
] = 64;
3093 /* SFmode, see if we want to use the VSX unit. */
3094 if (TARGET_P8_VECTOR
&& TARGET_VSX_SCALAR_FLOAT
)
3096 rs6000_vector_unit
[SFmode
] = VECTOR_VSX
;
3097 rs6000_vector_align
[SFmode
] = 32;
3100 /* Allow TImode in VSX register and set the VSX memory macros. */
3101 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
3103 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
3104 rs6000_vector_align
[TImode
] = align64
;
3107 /* TODO add SPE and paired floating point vector support. */
3109 /* Register class constraints for the constraints that depend on compile
3110 switches. When the VSX code was added, different constraints were added
3111 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
3112 of the VSX registers are used. The register classes for scalar floating
3113 point types is set, based on whether we allow that type into the upper
3114 (Altivec) registers. GCC has register classes to target the Altivec
3115 registers for load/store operations, to select using a VSX memory
3116 operation instead of the traditional floating point operation. The
3119 d - Register class to use with traditional DFmode instructions.
3120 f - Register class to use with traditional SFmode instructions.
3121 v - Altivec register.
3122 wa - Any VSX register.
3123 wc - Reserved to represent individual CR bits (used in LLVM).
3124 wd - Preferred register class for V2DFmode.
3125 wf - Preferred register class for V4SFmode.
3126 wg - Float register for power6x move insns.
3127 wh - FP register for direct move instructions.
3128 wi - FP or VSX register to hold 64-bit integers for VSX insns.
3129 wj - FP or VSX register to hold 64-bit integers for direct moves.
3130 wk - FP or VSX register to hold 64-bit doubles for direct moves.
3131 wl - Float register if we can do 32-bit signed int loads.
3132 wm - VSX register for ISA 2.07 direct move operations.
3133 wn - always NO_REGS.
3134 wr - GPR if 64-bit mode is permitted.
3135 ws - Register class to do ISA 2.06 DF operations.
3136 wt - VSX register for TImode in VSX registers.
3137 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
3138 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
3139 ww - Register class to do SF conversions in with VSX operations.
3140 wx - Float register if we can do 32-bit int stores.
3141 wy - Register class to do ISA 2.07 SF operations.
3142 wz - Float register if we can do 32-bit unsigned int loads.
3143 wH - Altivec register if SImode is allowed in VSX registers.
3144 wI - VSX register if SImode is allowed in VSX registers.
3145 wJ - VSX register if QImode/HImode are allowed in VSX registers.
3146 wK - Altivec register if QImode/HImode are allowed in VSX registers. */
3148 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3149 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
; /* SFmode */
3151 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
3152 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
; /* DFmode */
3156 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
3157 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
; /* V2DFmode */
3158 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
; /* V4SFmode */
3160 if (TARGET_VSX_TIMODE
)
3161 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
; /* TImode */
3163 if (TARGET_UPPER_REGS_DF
) /* DFmode */
3165 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
3166 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
3169 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
3171 if (TARGET_UPPER_REGS_DF
) /* DImode */
3172 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = VSX_REGS
;
3174 rs6000_constraints
[RS6000_CONSTRAINT_wi
] = FLOAT_REGS
;
3177 /* Add conditional constraints based on various options, to allow us to
3178 collapse multiple insn patterns. */
3180 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
3182 if (TARGET_MFPGPR
) /* DFmode */
3183 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
3186 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
; /* DImode */
3188 if (TARGET_DIRECT_MOVE
)
3190 rs6000_constraints
[RS6000_CONSTRAINT_wh
] = FLOAT_REGS
;
3191 rs6000_constraints
[RS6000_CONSTRAINT_wj
] /* DImode */
3192 = rs6000_constraints
[RS6000_CONSTRAINT_wi
];
3193 rs6000_constraints
[RS6000_CONSTRAINT_wk
] /* DFmode */
3194 = rs6000_constraints
[RS6000_CONSTRAINT_ws
];
3195 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
3198 if (TARGET_POWERPC64
)
3199 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
3201 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
) /* SFmode */
3203 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
3204 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
3205 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
3207 else if (TARGET_P8_VECTOR
)
3209 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
3210 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
3212 else if (TARGET_VSX
)
3213 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
3216 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
; /* DImode */
3219 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
; /* DImode */
3221 if (TARGET_FLOAT128_TYPE
)
3223 rs6000_constraints
[RS6000_CONSTRAINT_wq
] = VSX_REGS
; /* KFmode */
3224 if (FLOAT128_IEEE_P (TFmode
))
3225 rs6000_constraints
[RS6000_CONSTRAINT_wp
] = VSX_REGS
; /* TFmode */
3228 /* Support for new D-form instructions. */
3229 if (TARGET_P9_DFORM_SCALAR
)
3230 rs6000_constraints
[RS6000_CONSTRAINT_wb
] = ALTIVEC_REGS
;
3232 /* Support for ISA 3.0 (power9) vectors. */
3233 if (TARGET_P9_VECTOR
)
3234 rs6000_constraints
[RS6000_CONSTRAINT_wo
] = VSX_REGS
;
3236 /* Support for new direct moves (ISA 3.0 + 64bit). */
3237 if (TARGET_DIRECT_MOVE_128
)
3238 rs6000_constraints
[RS6000_CONSTRAINT_we
] = VSX_REGS
;
3240 /* Support small integers in VSX registers. */
3241 if (TARGET_VSX_SMALL_INTEGER
)
3243 rs6000_constraints
[RS6000_CONSTRAINT_wH
] = ALTIVEC_REGS
;
3244 rs6000_constraints
[RS6000_CONSTRAINT_wI
] = FLOAT_REGS
;
3245 if (TARGET_P9_VECTOR
)
3247 rs6000_constraints
[RS6000_CONSTRAINT_wJ
] = FLOAT_REGS
;
3248 rs6000_constraints
[RS6000_CONSTRAINT_wK
] = ALTIVEC_REGS
;
3252 /* Set up the reload helper and direct move functions. */
3253 if (TARGET_VSX
|| TARGET_ALTIVEC
)
3257 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
3258 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
3259 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
3260 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
3261 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
3262 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
3263 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
3264 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
3265 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_di_store
;
3266 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_di_load
;
3267 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
3268 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
3269 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
3270 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
3271 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
3272 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
3273 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
3274 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
3275 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
3276 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
3278 if (FLOAT128_VECTOR_P (KFmode
))
3280 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_di_store
;
3281 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_di_load
;
3284 if (FLOAT128_VECTOR_P (TFmode
))
3286 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_di_store
;
3287 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_di_load
;
3290 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3292 if (TARGET_NO_SDMODE_STACK
)
3294 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
3295 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
3298 if (TARGET_VSX_TIMODE
)
3300 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
3301 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
3304 if (TARGET_DIRECT_MOVE
&& !TARGET_DIRECT_MOVE_128
)
3306 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
3307 reg_addr
[V1TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv1ti
;
3308 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
3309 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
3310 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
3311 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
3312 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
3313 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
3314 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
3316 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
3317 reg_addr
[V1TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv1ti
;
3318 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
3319 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
3320 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
3321 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
3322 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
3323 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
3324 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
3326 if (FLOAT128_VECTOR_P (KFmode
))
3328 reg_addr
[KFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxkf
;
3329 reg_addr
[KFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprkf
;
3332 if (FLOAT128_VECTOR_P (TFmode
))
3334 reg_addr
[TFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxtf
;
3335 reg_addr
[TFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprtf
;
3341 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
3342 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
3343 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
3344 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
3345 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
3346 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
3347 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
3348 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
3349 reg_addr
[V1TImode
].reload_store
= CODE_FOR_reload_v1ti_si_store
;
3350 reg_addr
[V1TImode
].reload_load
= CODE_FOR_reload_v1ti_si_load
;
3351 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
3352 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
3353 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
3354 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
3355 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
3356 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
3357 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
3358 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
3359 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
3360 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
3362 if (FLOAT128_VECTOR_P (KFmode
))
3364 reg_addr
[KFmode
].reload_store
= CODE_FOR_reload_kf_si_store
;
3365 reg_addr
[KFmode
].reload_load
= CODE_FOR_reload_kf_si_load
;
3368 if (FLOAT128_IEEE_P (TFmode
))
3370 reg_addr
[TFmode
].reload_store
= CODE_FOR_reload_tf_si_store
;
3371 reg_addr
[TFmode
].reload_load
= CODE_FOR_reload_tf_si_load
;
3374 /* Only provide a reload handler for SDmode if lfiwzx/stfiwx are
3376 if (TARGET_NO_SDMODE_STACK
)
3378 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
3379 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
3382 if (TARGET_VSX_TIMODE
)
3384 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
3385 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
3388 if (TARGET_DIRECT_MOVE
)
3390 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
3391 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
3392 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
3396 if (TARGET_UPPER_REGS_DF
)
3397 reg_addr
[DFmode
].scalar_in_vmx_p
= true;
3399 if (TARGET_UPPER_REGS_DI
)
3400 reg_addr
[DImode
].scalar_in_vmx_p
= true;
3402 if (TARGET_UPPER_REGS_SF
)
3403 reg_addr
[SFmode
].scalar_in_vmx_p
= true;
3405 if (TARGET_VSX_SMALL_INTEGER
)
3406 reg_addr
[SImode
].scalar_in_vmx_p
= true;
3409 /* Setup the fusion operations. */
3410 if (TARGET_P8_FUSION
)
3412 reg_addr
[QImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_qi
;
3413 reg_addr
[HImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_hi
;
3414 reg_addr
[SImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_si
;
3416 reg_addr
[DImode
].fusion_gpr_ld
= CODE_FOR_fusion_gpr_load_di
;
3419 if (TARGET_P9_FUSION
)
3422 enum machine_mode mode
; /* mode of the fused type. */
3423 enum machine_mode pmode
; /* pointer mode. */
3424 enum rs6000_reload_reg_type rtype
; /* register type. */
3425 enum insn_code load
; /* load insn. */
3426 enum insn_code store
; /* store insn. */
3429 static const struct fuse_insns addis_insns
[] = {
3430 { SFmode
, DImode
, RELOAD_REG_FPR
,
3431 CODE_FOR_fusion_fpr_di_sf_load
,
3432 CODE_FOR_fusion_fpr_di_sf_store
},
3434 { SFmode
, SImode
, RELOAD_REG_FPR
,
3435 CODE_FOR_fusion_fpr_si_sf_load
,
3436 CODE_FOR_fusion_fpr_si_sf_store
},
3438 { DFmode
, DImode
, RELOAD_REG_FPR
,
3439 CODE_FOR_fusion_fpr_di_df_load
,
3440 CODE_FOR_fusion_fpr_di_df_store
},
3442 { DFmode
, SImode
, RELOAD_REG_FPR
,
3443 CODE_FOR_fusion_fpr_si_df_load
,
3444 CODE_FOR_fusion_fpr_si_df_store
},
3446 { DImode
, DImode
, RELOAD_REG_FPR
,
3447 CODE_FOR_fusion_fpr_di_di_load
,
3448 CODE_FOR_fusion_fpr_di_di_store
},
3450 { DImode
, SImode
, RELOAD_REG_FPR
,
3451 CODE_FOR_fusion_fpr_si_di_load
,
3452 CODE_FOR_fusion_fpr_si_di_store
},
3454 { QImode
, DImode
, RELOAD_REG_GPR
,
3455 CODE_FOR_fusion_gpr_di_qi_load
,
3456 CODE_FOR_fusion_gpr_di_qi_store
},
3458 { QImode
, SImode
, RELOAD_REG_GPR
,
3459 CODE_FOR_fusion_gpr_si_qi_load
,
3460 CODE_FOR_fusion_gpr_si_qi_store
},
3462 { HImode
, DImode
, RELOAD_REG_GPR
,
3463 CODE_FOR_fusion_gpr_di_hi_load
,
3464 CODE_FOR_fusion_gpr_di_hi_store
},
3466 { HImode
, SImode
, RELOAD_REG_GPR
,
3467 CODE_FOR_fusion_gpr_si_hi_load
,
3468 CODE_FOR_fusion_gpr_si_hi_store
},
3470 { SImode
, DImode
, RELOAD_REG_GPR
,
3471 CODE_FOR_fusion_gpr_di_si_load
,
3472 CODE_FOR_fusion_gpr_di_si_store
},
3474 { SImode
, SImode
, RELOAD_REG_GPR
,
3475 CODE_FOR_fusion_gpr_si_si_load
,
3476 CODE_FOR_fusion_gpr_si_si_store
},
3478 { SFmode
, DImode
, RELOAD_REG_GPR
,
3479 CODE_FOR_fusion_gpr_di_sf_load
,
3480 CODE_FOR_fusion_gpr_di_sf_store
},
3482 { SFmode
, SImode
, RELOAD_REG_GPR
,
3483 CODE_FOR_fusion_gpr_si_sf_load
,
3484 CODE_FOR_fusion_gpr_si_sf_store
},
3486 { DImode
, DImode
, RELOAD_REG_GPR
,
3487 CODE_FOR_fusion_gpr_di_di_load
,
3488 CODE_FOR_fusion_gpr_di_di_store
},
3490 { DFmode
, DImode
, RELOAD_REG_GPR
,
3491 CODE_FOR_fusion_gpr_di_df_load
,
3492 CODE_FOR_fusion_gpr_di_df_store
},
3495 enum machine_mode cur_pmode
= Pmode
;
3498 for (i
= 0; i
< ARRAY_SIZE (addis_insns
); i
++)
3500 enum machine_mode xmode
= addis_insns
[i
].mode
;
3501 enum rs6000_reload_reg_type rtype
= addis_insns
[i
].rtype
;
3503 if (addis_insns
[i
].pmode
!= cur_pmode
)
3506 if (rtype
== RELOAD_REG_FPR
3507 && (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
))
3510 reg_addr
[xmode
].fusion_addis_ld
[rtype
] = addis_insns
[i
].load
;
3511 reg_addr
[xmode
].fusion_addis_st
[rtype
] = addis_insns
[i
].store
;
3515 /* Note which types we support fusing TOC setup plus memory insn. We only do
3516 fused TOCs for medium/large code models. */
3517 if (TARGET_P8_FUSION
&& TARGET_TOC_FUSION
&& TARGET_POWERPC64
3518 && (TARGET_CMODEL
!= CMODEL_SMALL
))
3520 reg_addr
[QImode
].fused_toc
= true;
3521 reg_addr
[HImode
].fused_toc
= true;
3522 reg_addr
[SImode
].fused_toc
= true;
3523 reg_addr
[DImode
].fused_toc
= true;
3524 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
3526 if (TARGET_SINGLE_FLOAT
)
3527 reg_addr
[SFmode
].fused_toc
= true;
3528 if (TARGET_DOUBLE_FLOAT
)
3529 reg_addr
[DFmode
].fused_toc
= true;
3533 /* Precalculate HARD_REGNO_NREGS. */
3534 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3535 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3536 rs6000_hard_regno_nregs
[m
][r
]
3537 = rs6000_hard_regno_nregs_internal (r
, (machine_mode
)m
);
3539 /* Precalculate HARD_REGNO_MODE_OK. */
3540 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
3541 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3542 if (rs6000_hard_regno_mode_ok (r
, (machine_mode
)m
))
3543 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
3545 /* Precalculate CLASS_MAX_NREGS sizes. */
3546 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
3550 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
3551 reg_size
= UNITS_PER_VSX_WORD
;
3553 else if (c
== ALTIVEC_REGS
)
3554 reg_size
= UNITS_PER_ALTIVEC_WORD
;
3556 else if (c
== FLOAT_REGS
)
3557 reg_size
= UNITS_PER_FP_WORD
;
3560 reg_size
= UNITS_PER_WORD
;
3562 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
3564 machine_mode m2
= (machine_mode
)m
;
3565 int reg_size2
= reg_size
;
3567 /* TDmode & IBM 128-bit floating point always takes 2 registers, even
3569 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
) && FLOAT128_2REG_P (m
))
3570 reg_size2
= UNITS_PER_FP_WORD
;
3572 rs6000_class_max_nregs
[m
][c
]
3573 = (GET_MODE_SIZE (m2
) + reg_size2
- 1) / reg_size2
;
3577 if (TARGET_E500_DOUBLE
)
3578 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
3580 /* Calculate which modes to automatically generate code to use a the
3581 reciprocal divide and square root instructions. In the future, possibly
3582 automatically generate the instructions even if the user did not specify
3583 -mrecip. The older machines double precision reciprocal sqrt estimate is
3584 not accurate enough. */
3585 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
3587 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3589 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3590 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3591 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3592 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3593 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
3595 if (TARGET_FRSQRTES
)
3596 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3598 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3599 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
3600 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3601 if (VECTOR_UNIT_VSX_P (V2DFmode
))
3602 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
3604 if (rs6000_recip_control
)
3606 if (!flag_finite_math_only
)
3607 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
3608 if (flag_trapping_math
)
3609 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
3610 if (!flag_reciprocal_math
)
3611 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
3612 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
3614 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
3615 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
3616 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3618 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
3619 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
3620 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3622 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
3623 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
3624 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3626 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
3627 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
3628 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
3630 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
3631 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
3632 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3634 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
3635 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
3636 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3638 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
3639 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
3640 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3642 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
3643 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
3644 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
3648 /* Update the addr mask bits in reg_addr to help secondary reload and go if
3649 legitimate address support to figure out the appropriate addressing to
3651 rs6000_setup_reg_addr_masks ();
3653 if (global_init_p
|| TARGET_DEBUG_TARGET
)
3655 if (TARGET_DEBUG_REG
)
3656 rs6000_debug_reg_global ();
3658 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
3660 "SImode variable mult cost = %d\n"
3661 "SImode constant mult cost = %d\n"
3662 "SImode short constant mult cost = %d\n"
3663 "DImode multipliciation cost = %d\n"
3664 "SImode division cost = %d\n"
3665 "DImode division cost = %d\n"
3666 "Simple fp operation cost = %d\n"
3667 "DFmode multiplication cost = %d\n"
3668 "SFmode division cost = %d\n"
3669 "DFmode division cost = %d\n"
3670 "cache line size = %d\n"
3671 "l1 cache size = %d\n"
3672 "l2 cache size = %d\n"
3673 "simultaneous prefetches = %d\n"
3676 rs6000_cost
->mulsi_const
,
3677 rs6000_cost
->mulsi_const9
,
3685 rs6000_cost
->cache_line_size
,
3686 rs6000_cost
->l1_cache_size
,
3687 rs6000_cost
->l2_cache_size
,
3688 rs6000_cost
->simultaneous_prefetches
);
3693 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
3696 darwin_rs6000_override_options (void)
3698 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
3700 rs6000_altivec_abi
= 1;
3701 TARGET_ALTIVEC_VRSAVE
= 1;
3702 rs6000_current_abi
= ABI_DARWIN
;
3704 if (DEFAULT_ABI
== ABI_DARWIN
3706 darwin_one_byte_bool
= 1;
3708 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
3710 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
3711 warning (0, "-m64 requires PowerPC64 architecture, enabling");
3715 rs6000_default_long_calls
= 1;
3716 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
3719 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
3721 if (!flag_mkernel
&& !flag_apple_kext
3723 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
3724 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3726 /* Unless the user (not the configurer) has explicitly overridden
3727 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
3728 G4 unless targeting the kernel. */
3731 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
3732 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
3733 && ! global_options_set
.x_rs6000_cpu_index
)
3735 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
3740 /* If not otherwise specified by a target, make 'long double' equivalent to
3743 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
3744 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
3747 /* Return the builtin mask of the various options used that could affect which
3748 builtins were used. In the past we used target_flags, but we've run out of
3749 bits, and some options like SPE and PAIRED are no longer in
3753 rs6000_builtin_mask_calculate (void)
3755 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
3756 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
3757 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
3758 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
3759 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
3760 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
3761 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
3762 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
3763 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
3764 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
3765 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
3766 | ((TARGET_P9_VECTOR
) ? RS6000_BTM_P9_VECTOR
: 0)
3767 | ((TARGET_P9_MISC
) ? RS6000_BTM_P9_MISC
: 0)
3768 | ((TARGET_MODULO
) ? RS6000_BTM_MODULO
: 0)
3769 | ((TARGET_64BIT
) ? RS6000_BTM_64BIT
: 0)
3770 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
3771 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0)
3772 | ((TARGET_DFP
) ? RS6000_BTM_DFP
: 0)
3773 | ((TARGET_HARD_FLOAT
) ? RS6000_BTM_HARD_FLOAT
: 0)
3774 | ((TARGET_LONG_DOUBLE_128
) ? RS6000_BTM_LDBL128
: 0)
3775 | ((TARGET_FLOAT128_TYPE
) ? RS6000_BTM_FLOAT128
: 0));
3778 /* Implement TARGET_MD_ASM_ADJUST. All asm statements are considered
3779 to clobber the XER[CA] bit because clobbering that bit without telling
3780 the compiler worked just fine with versions of GCC before GCC 5, and
3781 breaking a lot of older code in ways that are hard to track down is
3782 not such a great idea. */
3785 rs6000_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
3786 vec
<const char *> &/*constraints*/,
3787 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
3789 clobbers
.safe_push (gen_rtx_REG (SImode
, CA_REGNO
));
3790 SET_HARD_REG_BIT (clobbered_regs
, CA_REGNO
);
3794 /* Override command line options. Mostly we process the processor type and
3795 sometimes adjust other TARGET_ options. */
3798 rs6000_option_override_internal (bool global_init_p
)
3801 bool have_cpu
= false;
3803 /* The default cpu requested at configure time, if any. */
3804 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3806 HOST_WIDE_INT set_masks
;
3809 struct cl_target_option
*main_target_opt
3810 = ((global_init_p
|| target_option_default_node
== NULL
)
3811 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3813 /* Print defaults. */
3814 if ((TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
) && global_init_p
)
3815 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
3817 /* Remember the explicit arguments. */
3819 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3821 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3822 library functions, so warn about it. The flag may be useful for
3823 performance studies from time to time though, so don't disable it
3825 if (global_options_set
.x_rs6000_alignment_flags
3826 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3827 && DEFAULT_ABI
== ABI_DARWIN
3829 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3830 " it is incompatible with the installed C and C++ libraries");
3832 /* Numerous experiment shows that IRA based loop pressure
3833 calculation works better for RTL loop invariant motion on targets
3834 with enough (>= 32) registers. It is an expensive optimization.
3835 So it is on only for peak performance. */
3836 if (optimize
>= 3 && global_init_p
3837 && !global_options_set
.x_flag_ira_loop_pressure
)
3838 flag_ira_loop_pressure
= 1;
3840 /* Set the pointer size. */
3843 rs6000_pmode
= (int)DImode
;
3844 rs6000_pointer_size
= 64;
3848 rs6000_pmode
= (int)SImode
;
3849 rs6000_pointer_size
= 32;
3852 /* Some OSs don't support saving the high part of 64-bit registers on context
3853 switch. Other OSs don't support saving Altivec registers. On those OSs,
3854 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3855 if the user wants either, the user must explicitly specify them and we
3856 won't interfere with the user's specification. */
3858 set_masks
= POWERPC_MASKS
;
3859 #ifdef OS_MISSING_POWERPC64
3860 if (OS_MISSING_POWERPC64
)
3861 set_masks
&= ~OPTION_MASK_POWERPC64
;
3863 #ifdef OS_MISSING_ALTIVEC
3864 if (OS_MISSING_ALTIVEC
)
3865 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3868 /* Don't override by the processor default if given explicitly. */
3869 set_masks
&= ~rs6000_isa_flags_explicit
;
3871 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3872 the cpu in a target attribute or pragma, but did not specify a tuning
3873 option, use the cpu for the tuning option rather than the option specified
3874 with -mtune on the command line. Process a '--with-cpu' configuration
3875 request as an implicit --cpu. */
3876 if (rs6000_cpu_index
>= 0)
3878 cpu_index
= rs6000_cpu_index
;
3881 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3883 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3886 else if (implicit_cpu
)
3888 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3893 /* PowerPC 64-bit LE requires at least ISA 2.07. */
3894 const char *default_cpu
= ((!TARGET_POWERPC64
)
3896 : ((BYTES_BIG_ENDIAN
)
3900 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3904 gcc_assert (cpu_index
>= 0);
3906 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3907 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3908 with those from the cpu, except for options that were explicitly set. If
3909 we don't have a cpu, do not override the target bits set in
3913 rs6000_isa_flags
&= ~set_masks
;
3914 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3919 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3920 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3921 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3922 to using rs6000_isa_flags, we need to do the initialization here.
3924 If there is a TARGET_DEFAULT, use that. Otherwise fall back to using
3925 -mcpu=powerpc, -mcpu=powerpc64, or -mcpu=powerpc64le defaults. */
3926 HOST_WIDE_INT flags
= ((TARGET_DEFAULT
) ? TARGET_DEFAULT
3927 : processor_target_table
[cpu_index
].target_enable
);
3928 rs6000_isa_flags
|= (flags
& ~rs6000_isa_flags_explicit
);
3931 if (rs6000_tune_index
>= 0)
3932 tune_index
= rs6000_tune_index
;
3934 rs6000_tune_index
= tune_index
= cpu_index
;
3938 enum processor_type tune_proc
3939 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3942 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3943 if (processor_target_table
[i
].processor
== tune_proc
)
3945 rs6000_tune_index
= tune_index
= i
;
3950 gcc_assert (tune_index
>= 0);
3951 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3953 /* Pick defaults for SPE related control flags. Do this early to make sure
3954 that the TARGET_ macros are representative ASAP. */
3956 int spe_capable_cpu
=
3957 (rs6000_cpu
== PROCESSOR_PPC8540
3958 || rs6000_cpu
== PROCESSOR_PPC8548
);
3960 if (!global_options_set
.x_rs6000_spe_abi
)
3961 rs6000_spe_abi
= spe_capable_cpu
;
3963 if (!global_options_set
.x_rs6000_spe
)
3964 rs6000_spe
= spe_capable_cpu
;
3966 if (!global_options_set
.x_rs6000_float_gprs
)
3968 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3969 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3973 if (global_options_set
.x_rs6000_spe_abi
3976 error ("not configured for SPE ABI");
3978 if (global_options_set
.x_rs6000_spe
3981 error ("not configured for SPE instruction set");
3983 if (main_target_opt
!= NULL
3984 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3985 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3986 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3987 error ("target attribute or pragma changes SPE ABI");
3989 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3990 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3991 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3994 error ("AltiVec not supported in this target");
3996 error ("SPE not supported in this target");
3998 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
4001 error ("SPE not supported in this target");
4004 /* Disable Cell microcode if we are optimizing for the Cell
4005 and not optimizing for size. */
4006 if (rs6000_gen_cell_microcode
== -1)
4007 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
4010 /* If we are optimizing big endian systems for space and it's OK to
4011 use instructions that would be microcoded on the Cell, use the
4012 load/store multiple and string instructions. */
4013 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
4014 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
4015 | OPTION_MASK_STRING
);
4017 /* Don't allow -mmultiple or -mstring on little endian systems
4018 unless the cpu is a 750, because the hardware doesn't support the
4019 instructions used in little endian mode, and causes an alignment
4020 trap. The 750 does not cause an alignment trap (except when the
4021 target is unaligned). */
4023 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
4025 if (TARGET_MULTIPLE
)
4027 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
4028 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
4029 warning (0, "-mmultiple is not supported on little endian systems");
4034 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
4035 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
4036 warning (0, "-mstring is not supported on little endian systems");
4040 /* If little-endian, default to -mstrict-align on older processors.
4041 Testing for htm matches power8 and later. */
4042 if (!BYTES_BIG_ENDIAN
4043 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
4044 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
4046 /* -maltivec={le,be} implies -maltivec. */
4047 if (rs6000_altivec_element_order
!= 0)
4048 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
4050 /* Disallow -maltivec=le in big endian mode for now. This is not
4051 known to be useful for anyone. */
4052 if (BYTES_BIG_ENDIAN
&& rs6000_altivec_element_order
== 1)
4054 warning (0, N_("-maltivec=le not allowed for big-endian targets"));
4055 rs6000_altivec_element_order
= 0;
4058 /* Add some warnings for VSX. */
4061 const char *msg
= NULL
;
4062 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
4063 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
4065 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4066 msg
= N_("-mvsx requires hardware floating point");
4069 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
4070 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4073 else if (TARGET_PAIRED_FLOAT
)
4074 msg
= N_("-mvsx and -mpaired are incompatible");
4075 else if (TARGET_AVOID_XFORM
> 0)
4076 msg
= N_("-mvsx needs indexed addressing");
4077 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
4078 & OPTION_MASK_ALTIVEC
))
4080 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
4081 msg
= N_("-mvsx and -mno-altivec are incompatible");
4083 msg
= N_("-mno-altivec disables vsx");
4089 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
4090 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
4094 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
4095 the -mcpu setting to enable options that conflict. */
4096 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
4097 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
4098 | OPTION_MASK_ALTIVEC
4099 | OPTION_MASK_VSX
)) != 0)
4100 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
4101 | OPTION_MASK_DIRECT_MOVE
)
4102 & ~rs6000_isa_flags_explicit
);
4104 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4105 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
4107 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
4108 unless the user explicitly used the -mno-<option> to disable the code. */
4109 if (TARGET_P9_VECTOR
|| TARGET_MODULO
|| TARGET_P9_DFORM_SCALAR
4110 || TARGET_P9_DFORM_VECTOR
|| TARGET_P9_DFORM_BOTH
> 0 || TARGET_P9_MINMAX
)
4111 rs6000_isa_flags
|= (ISA_3_0_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
4112 else if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
4113 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
4114 else if (TARGET_VSX
)
4115 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
4116 else if (TARGET_POPCNTD
)
4117 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
4118 else if (TARGET_DFP
)
4119 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
4120 else if (TARGET_CMPB
)
4121 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
4122 else if (TARGET_FPRND
)
4123 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
4124 else if (TARGET_POPCNTB
)
4125 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
4126 else if (TARGET_ALTIVEC
)
4127 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
4129 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
4131 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
4132 error ("-mcrypto requires -maltivec");
4133 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
4136 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
4138 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
4139 error ("-mdirect-move requires -mvsx");
4140 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
4143 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
4145 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4146 error ("-mpower8-vector requires -maltivec");
4147 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4150 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
4152 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4153 error ("-mpower8-vector requires -mvsx");
4154 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
4157 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
4159 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
4160 error ("-mvsx-timode requires -mvsx");
4161 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
4164 if (TARGET_DFP
&& !TARGET_HARD_FLOAT
)
4166 if (rs6000_isa_flags_explicit
& OPTION_MASK_DFP
)
4167 error ("-mhard-dfp requires -mhard-float");
4168 rs6000_isa_flags
&= ~OPTION_MASK_DFP
;
4171 /* Allow an explicit -mupper-regs to set -mupper-regs-df, -mupper-regs-di,
4172 and -mupper-regs-sf, depending on the cpu, unless the user explicitly also
4173 set the individual option. */
4174 if (TARGET_UPPER_REGS
> 0)
4177 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
))
4179 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_DF
;
4180 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DF
;
4183 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DI
))
4185 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_DI
;
4186 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DI
;
4188 if (TARGET_P8_VECTOR
4189 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
))
4191 rs6000_isa_flags
|= OPTION_MASK_UPPER_REGS_SF
;
4192 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_SF
;
4195 else if (TARGET_UPPER_REGS
== 0)
4198 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
))
4200 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
4201 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DF
;
4204 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DI
))
4206 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DI
;
4207 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_DI
;
4209 if (TARGET_P8_VECTOR
4210 && !(rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
))
4212 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_SF
;
4213 rs6000_isa_flags_explicit
|= OPTION_MASK_UPPER_REGS_SF
;
4217 if (TARGET_UPPER_REGS_DF
&& !TARGET_VSX
)
4219 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
)
4220 error ("-mupper-regs-df requires -mvsx");
4221 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
4224 if (TARGET_UPPER_REGS_DI
&& !TARGET_VSX
)
4226 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
)
4227 error ("-mupper-regs-di requires -mvsx");
4228 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_DF
;
4231 if (TARGET_UPPER_REGS_SF
&& !TARGET_P8_VECTOR
)
4233 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
)
4234 error ("-mupper-regs-sf requires -mpower8-vector");
4235 rs6000_isa_flags
&= ~OPTION_MASK_UPPER_REGS_SF
;
4238 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
4239 silently turn off quad memory mode. */
4240 if ((TARGET_QUAD_MEMORY
|| TARGET_QUAD_MEMORY_ATOMIC
) && !TARGET_POWERPC64
)
4242 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4243 warning (0, N_("-mquad-memory requires 64-bit mode"));
4245 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) != 0)
4246 warning (0, N_("-mquad-memory-atomic requires 64-bit mode"));
4248 rs6000_isa_flags
&= ~(OPTION_MASK_QUAD_MEMORY
4249 | OPTION_MASK_QUAD_MEMORY_ATOMIC
);
4252 /* Non-atomic quad memory load/store are disabled for little endian, since
4253 the words are reversed, but atomic operations can still be done by
4254 swapping the words. */
4255 if (TARGET_QUAD_MEMORY
&& !WORDS_BIG_ENDIAN
)
4257 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
4258 warning (0, N_("-mquad-memory is not available in little endian mode"));
4260 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
4263 /* Assume if the user asked for normal quad memory instructions, they want
4264 the atomic versions as well, unless they explicity told us not to use quad
4265 word atomic instructions. */
4266 if (TARGET_QUAD_MEMORY
4267 && !TARGET_QUAD_MEMORY_ATOMIC
4268 && ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY_ATOMIC
) == 0))
4269 rs6000_isa_flags
|= OPTION_MASK_QUAD_MEMORY_ATOMIC
;
4271 /* Enable power8 fusion if we are tuning for power8, even if we aren't
4272 generating power8 instructions. */
4273 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
4274 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
4275 & OPTION_MASK_P8_FUSION
);
4277 /* Setting additional fusion flags turns on base fusion. */
4278 if (!TARGET_P8_FUSION
&& (TARGET_P8_FUSION_SIGN
|| TARGET_TOC_FUSION
))
4280 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4282 if (TARGET_P8_FUSION_SIGN
)
4283 error ("-mpower8-fusion-sign requires -mpower8-fusion");
4285 if (TARGET_TOC_FUSION
)
4286 error ("-mtoc-fusion requires -mpower8-fusion");
4288 rs6000_isa_flags
&= ~OPTION_MASK_P8_FUSION
;
4291 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4294 /* Power9 fusion is a superset over power8 fusion. */
4295 if (TARGET_P9_FUSION
&& !TARGET_P8_FUSION
)
4297 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
)
4299 /* We prefer to not mention undocumented options in
4300 error messages. However, if users have managed to select
4301 power9-fusion without selecting power8-fusion, they
4302 already know about undocumented flags. */
4303 error ("-mpower9-fusion requires -mpower8-fusion");
4304 rs6000_isa_flags
&= ~OPTION_MASK_P9_FUSION
;
4307 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION
;
4310 /* Enable power9 fusion if we are tuning for power9, even if we aren't
4311 generating power9 instructions. */
4312 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_FUSION
))
4313 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
4314 & OPTION_MASK_P9_FUSION
);
4316 /* Power8 does not fuse sign extended loads with the addis. If we are
4317 optimizing at high levels for speed, convert a sign extended load into a
4318 zero extending load, and an explicit sign extension. */
4319 if (TARGET_P8_FUSION
4320 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
4321 && optimize_function_for_speed_p (cfun
)
4323 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
4325 /* TOC fusion requires 64-bit and medium/large code model. */
4326 if (TARGET_TOC_FUSION
&& !TARGET_POWERPC64
)
4328 rs6000_isa_flags
&= ~OPTION_MASK_TOC_FUSION
;
4329 if ((rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
) != 0)
4330 warning (0, N_("-mtoc-fusion requires 64-bit"));
4333 if (TARGET_TOC_FUSION
&& (TARGET_CMODEL
== CMODEL_SMALL
))
4335 rs6000_isa_flags
&= ~OPTION_MASK_TOC_FUSION
;
4336 if ((rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
) != 0)
4337 warning (0, N_("-mtoc-fusion requires medium/large code model"));
4340 /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
4342 if (TARGET_P8_FUSION
&& !TARGET_TOC_FUSION
&& TARGET_POWERPC64
4343 && (TARGET_CMODEL
!= CMODEL_SMALL
)
4344 && !(rs6000_isa_flags_explicit
& OPTION_MASK_TOC_FUSION
))
4345 rs6000_isa_flags
|= OPTION_MASK_TOC_FUSION
;
4347 /* ISA 3.0 vector instructions include ISA 2.07. */
4348 if (TARGET_P9_VECTOR
&& !TARGET_P8_VECTOR
)
4350 /* We prefer to not mention undocumented options in
4351 error messages. However, if users have managed to select
4352 power9-vector without selecting power8-vector, they
4353 already know about undocumented flags. */
4354 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
4355 error ("-mpower9-vector requires -mpower8-vector");
4356 rs6000_isa_flags
&= ~OPTION_MASK_P9_VECTOR
;
4359 /* -mpower9-dform turns on both -mpower9-dform-scalar and
4360 -mpower9-dform-vector. */
4361 if (TARGET_P9_DFORM_BOTH
> 0)
4363 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_VECTOR
))
4364 rs6000_isa_flags
|= OPTION_MASK_P9_DFORM_VECTOR
;
4366 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_SCALAR
))
4367 rs6000_isa_flags
|= OPTION_MASK_P9_DFORM_SCALAR
;
4369 else if (TARGET_P9_DFORM_BOTH
== 0)
4371 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_VECTOR
))
4372 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM_VECTOR
;
4374 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P9_DFORM_SCALAR
))
4375 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM_SCALAR
;
4378 /* ISA 3.0 D-form instructions require p9-vector and upper-regs. */
4379 if ((TARGET_P9_DFORM_SCALAR
|| TARGET_P9_DFORM_VECTOR
) && !TARGET_P9_VECTOR
)
4381 /* We prefer to not mention undocumented options in
4382 error messages. However, if users have managed to select
4383 power9-dform without selecting power9-vector, they
4384 already know about undocumented flags. */
4385 if (rs6000_isa_flags_explicit
& OPTION_MASK_P9_VECTOR
)
4386 error ("-mpower9-dform requires -mpower9-vector");
4387 rs6000_isa_flags
&= ~(OPTION_MASK_P9_DFORM_SCALAR
4388 | OPTION_MASK_P9_DFORM_VECTOR
);
4391 if (TARGET_P9_DFORM_SCALAR
&& !TARGET_UPPER_REGS_DF
)
4393 /* We prefer to not mention undocumented options in
4394 error messages. However, if users have managed to select
4395 power9-dform without selecting upper-regs-df, they
4396 already know about undocumented flags. */
4397 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_DF
)
4398 error ("-mpower9-dform requires -mupper-regs-df");
4399 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM_SCALAR
;
4402 if (TARGET_P9_DFORM_SCALAR
&& !TARGET_UPPER_REGS_SF
)
4404 if (rs6000_isa_flags_explicit
& OPTION_MASK_UPPER_REGS_SF
)
4405 error ("-mpower9-dform requires -mupper-regs-sf");
4406 rs6000_isa_flags
&= ~OPTION_MASK_P9_DFORM_SCALAR
;
4409 /* Enable LRA by default. */
4410 if ((rs6000_isa_flags_explicit
& OPTION_MASK_LRA
) == 0)
4411 rs6000_isa_flags
|= OPTION_MASK_LRA
;
4413 /* There have been bugs with -mvsx-timode that don't show up with -mlra,
4414 but do show up with -mno-lra. Given -mlra will become the default once
4415 PR 69847 is fixed, turn off the options with problems by default if
4416 -mno-lra was used, and warn if the user explicitly asked for the option.
4418 Enable -mpower9-dform-vector by default if LRA and other power9 options.
4419 Enable -mvsx-timode by default if LRA and VSX. */
4422 if (TARGET_VSX_TIMODE
)
4424 if ((rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
) != 0)
4425 warning (0, "-mvsx-timode might need -mlra");
4428 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
4434 if (TARGET_VSX
&& !TARGET_VSX_TIMODE
4435 && (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
) == 0)
4436 rs6000_isa_flags
|= OPTION_MASK_VSX_TIMODE
;
4439 /* Set -mallow-movmisalign to explicitly on if we have full ISA 2.07
4440 support. If we only have ISA 2.06 support, and the user did not specify
4441 the switch, leave it set to -1 so the movmisalign patterns are enabled,
4442 but we don't enable the full vectorization support */
4443 if (TARGET_ALLOW_MOVMISALIGN
== -1 && TARGET_P8_VECTOR
&& TARGET_DIRECT_MOVE
)
4444 TARGET_ALLOW_MOVMISALIGN
= 1;
4446 else if (TARGET_ALLOW_MOVMISALIGN
&& !TARGET_VSX
)
4448 if (TARGET_ALLOW_MOVMISALIGN
> 0
4449 && global_options_set
.x_TARGET_ALLOW_MOVMISALIGN
)
4450 error ("-mallow-movmisalign requires -mvsx");
4452 TARGET_ALLOW_MOVMISALIGN
= 0;
4455 /* Determine when unaligned vector accesses are permitted, and when
4456 they are preferred over masked Altivec loads. Note that if
4457 TARGET_ALLOW_MOVMISALIGN has been disabled by the user, then
4458 TARGET_EFFICIENT_UNALIGNED_VSX must be as well. The converse is
4460 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
4464 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4465 error ("-mefficient-unaligned-vsx requires -mvsx");
4467 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4470 else if (!TARGET_ALLOW_MOVMISALIGN
)
4472 if (rs6000_isa_flags_explicit
& OPTION_MASK_EFFICIENT_UNALIGNED_VSX
)
4473 error ("-mefficient-unaligned-vsx requires -mallow-movmisalign");
4475 rs6000_isa_flags
&= ~OPTION_MASK_EFFICIENT_UNALIGNED_VSX
;
4479 /* Check whether we should allow small integers into VSX registers. We
4480 require direct move to prevent the register allocator from having to move
4481 variables through memory to do moves. SImode can be used on ISA 2.07,
4482 while HImode and QImode require ISA 3.0. */
4483 if (TARGET_VSX_SMALL_INTEGER
4484 && (!TARGET_DIRECT_MOVE
|| !TARGET_P8_VECTOR
|| !TARGET_UPPER_REGS_DI
))
4486 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_SMALL_INTEGER
)
4487 error ("-mvsx-small-integer requires -mpower8-vector, "
4488 "-mupper-regs-di, and -mdirect-move");
4490 rs6000_isa_flags
&= ~OPTION_MASK_VSX_SMALL_INTEGER
;
4493 /* Set long double size before the IEEE 128-bit tests. */
4494 if (!global_options_set
.x_rs6000_long_double_type_size
)
4496 if (main_target_opt
!= NULL
4497 && (main_target_opt
->x_rs6000_long_double_type_size
4498 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
4499 error ("target attribute or pragma changes long double size");
4501 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
4504 /* Set -mabi=ieeelongdouble on some old targets. Note, AIX and Darwin
4505 explicitly redefine TARGET_IEEEQUAD to 0, so those systems will not
4506 pick up this default. */
4507 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
4508 if (!global_options_set
.x_rs6000_ieeequad
)
4509 rs6000_ieeequad
= 1;
4512 /* Enable the default support for IEEE 128-bit floating point on Linux VSX
4513 sytems, but don't enable the __float128 keyword. */
4514 if (TARGET_VSX
&& TARGET_LONG_DOUBLE_128
4515 && (TARGET_FLOAT128_ENABLE_TYPE
|| TARGET_IEEEQUAD
)
4516 && ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_TYPE
) == 0))
4517 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_TYPE
;
4519 /* IEEE 128-bit floating point requires VSX support. */
4522 if (TARGET_FLOAT128_KEYWORD
)
4524 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) != 0)
4525 error ("-mfloat128 requires VSX support");
4527 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_TYPE
4528 | OPTION_MASK_FLOAT128_KEYWORD
4529 | OPTION_MASK_FLOAT128_HW
);
4532 else if (TARGET_FLOAT128_TYPE
)
4534 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_TYPE
) != 0)
4535 error ("-mfloat128-type requires VSX support");
4537 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_TYPE
4538 | OPTION_MASK_FLOAT128_KEYWORD
4539 | OPTION_MASK_FLOAT128_HW
);
4543 /* -mfloat128 and -mfloat128-hardware internally require the underlying IEEE
4544 128-bit floating point support to be enabled. */
4545 if (!TARGET_FLOAT128_TYPE
)
4547 if (TARGET_FLOAT128_KEYWORD
)
4549 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) != 0)
4551 error ("-mfloat128 requires -mfloat128-type");
4552 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_TYPE
4553 | OPTION_MASK_FLOAT128_KEYWORD
4554 | OPTION_MASK_FLOAT128_HW
);
4557 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_TYPE
;
4560 if (TARGET_FLOAT128_HW
)
4562 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4564 error ("-mfloat128-hardware requires -mfloat128-type");
4565 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4568 rs6000_isa_flags
&= ~(OPTION_MASK_FLOAT128_TYPE
4569 | OPTION_MASK_FLOAT128_KEYWORD
4570 | OPTION_MASK_FLOAT128_HW
);
4574 /* If we have -mfloat128-type and full ISA 3.0 support, enable
4575 -mfloat128-hardware by default. However, don't enable the __float128
4576 keyword. If the user explicitly turned on -mfloat128-hardware, enable the
4577 -mfloat128 option as well if it was not already set. */
4578 if (TARGET_FLOAT128_TYPE
&& !TARGET_FLOAT128_HW
4579 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) == ISA_3_0_MASKS_IEEE
4580 && !(rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
))
4581 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_HW
;
4583 if (TARGET_FLOAT128_HW
4584 && (rs6000_isa_flags
& ISA_3_0_MASKS_IEEE
) != ISA_3_0_MASKS_IEEE
)
4586 if ((rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0)
4587 error ("-mfloat128-hardware requires full ISA 3.0 support");
4589 rs6000_isa_flags
&= ~OPTION_MASK_FLOAT128_HW
;
4592 if (TARGET_FLOAT128_HW
&& !TARGET_FLOAT128_KEYWORD
4593 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_HW
) != 0
4594 && (rs6000_isa_flags_explicit
& OPTION_MASK_FLOAT128_KEYWORD
) == 0)
4595 rs6000_isa_flags
|= OPTION_MASK_FLOAT128_KEYWORD
;
4597 /* Print the options after updating the defaults. */
4598 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4599 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
4601 /* E500mc does "better" if we inline more aggressively. Respect the
4602 user's opinion, though. */
4603 if (rs6000_block_move_inline_limit
== 0
4604 && (rs6000_cpu
== PROCESSOR_PPCE500MC
4605 || rs6000_cpu
== PROCESSOR_PPCE500MC64
4606 || rs6000_cpu
== PROCESSOR_PPCE5500
4607 || rs6000_cpu
== PROCESSOR_PPCE6500
))
4608 rs6000_block_move_inline_limit
= 128;
4610 /* store_one_arg depends on expand_block_move to handle at least the
4611 size of reg_parm_stack_space. */
4612 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
4613 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
4617 /* If the appropriate debug option is enabled, replace the target hooks
4618 with debug versions that call the real version and then prints
4619 debugging information. */
4620 if (TARGET_DEBUG_COST
)
4622 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
4623 targetm
.address_cost
= rs6000_debug_address_cost
;
4624 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
4627 if (TARGET_DEBUG_ADDR
)
4629 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
4630 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
4631 rs6000_secondary_reload_class_ptr
4632 = rs6000_debug_secondary_reload_class
;
4633 rs6000_secondary_memory_needed_ptr
4634 = rs6000_debug_secondary_memory_needed
;
4635 rs6000_cannot_change_mode_class_ptr
4636 = rs6000_debug_cannot_change_mode_class
;
4637 rs6000_preferred_reload_class_ptr
4638 = rs6000_debug_preferred_reload_class
;
4639 rs6000_legitimize_reload_address_ptr
4640 = rs6000_debug_legitimize_reload_address
;
4641 rs6000_mode_dependent_address_ptr
4642 = rs6000_debug_mode_dependent_address
;
4645 if (rs6000_veclibabi_name
)
4647 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
4648 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
4651 error ("unknown vectorization library ABI type (%s) for "
4652 "-mveclibabi= switch", rs6000_veclibabi_name
);
4658 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
4659 target attribute or pragma which automatically enables both options,
4660 unless the altivec ABI was set. This is set by default for 64-bit, but
4662 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4663 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
4664 | OPTION_MASK_FLOAT128_TYPE
4665 | OPTION_MASK_FLOAT128_KEYWORD
)
4666 & ~rs6000_isa_flags_explicit
);
4668 /* Enable Altivec ABI for AIX -maltivec. */
4669 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
4671 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
4672 error ("target attribute or pragma changes AltiVec ABI");
4674 rs6000_altivec_abi
= 1;
4677 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
4678 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
4679 be explicitly overridden in either case. */
4682 if (!global_options_set
.x_rs6000_altivec_abi
4683 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
4685 if (main_target_opt
!= NULL
&&
4686 !main_target_opt
->x_rs6000_altivec_abi
)
4687 error ("target attribute or pragma changes AltiVec ABI");
4689 rs6000_altivec_abi
= 1;
4693 /* Set the Darwin64 ABI as default for 64-bit Darwin.
4694 So far, the only darwin64 targets are also MACH-O. */
4696 && DEFAULT_ABI
== ABI_DARWIN
4699 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
4700 error ("target attribute or pragma changes darwin64 ABI");
4703 rs6000_darwin64_abi
= 1;
4704 /* Default to natural alignment, for better performance. */
4705 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
4709 /* Place FP constants in the constant pool instead of TOC
4710 if section anchors enabled. */
4711 if (flag_section_anchors
4712 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
4713 TARGET_NO_FP_IN_TOC
= 1;
4715 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4716 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
4718 #ifdef SUBTARGET_OVERRIDE_OPTIONS
4719 SUBTARGET_OVERRIDE_OPTIONS
;
4721 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
4722 SUBSUBTARGET_OVERRIDE_OPTIONS
;
4724 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
4725 SUB3TARGET_OVERRIDE_OPTIONS
;
4728 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
4729 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
4731 /* For the E500 family of cores, reset the single/double FP flags to let us
4732 check that they remain constant across attributes or pragmas. Also,
4733 clear a possible request for string instructions, not supported and which
4734 we might have silently queried above for -Os.
4736 For other families, clear ISEL in case it was set implicitly.
4741 case PROCESSOR_PPC8540
:
4742 case PROCESSOR_PPC8548
:
4743 case PROCESSOR_PPCE500MC
:
4744 case PROCESSOR_PPCE500MC64
:
4745 case PROCESSOR_PPCE5500
:
4746 case PROCESSOR_PPCE6500
:
4748 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
4749 rs6000_double_float
= TARGET_E500_DOUBLE
;
4751 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
4757 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
4758 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
4763 if (main_target_opt
)
4765 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
4766 error ("target attribute or pragma changes single precision floating "
4768 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
4769 error ("target attribute or pragma changes double precision floating "
4773 /* Detect invalid option combinations with E500. */
4776 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
4777 && rs6000_cpu
!= PROCESSOR_POWER5
4778 && rs6000_cpu
!= PROCESSOR_POWER6
4779 && rs6000_cpu
!= PROCESSOR_POWER7
4780 && rs6000_cpu
!= PROCESSOR_POWER8
4781 && rs6000_cpu
!= PROCESSOR_POWER9
4782 && rs6000_cpu
!= PROCESSOR_PPCA2
4783 && rs6000_cpu
!= PROCESSOR_CELL
4784 && rs6000_cpu
!= PROCESSOR_PPC476
);
4785 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
4786 || rs6000_cpu
== PROCESSOR_POWER5
4787 || rs6000_cpu
== PROCESSOR_POWER7
4788 || rs6000_cpu
== PROCESSOR_POWER8
);
4789 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
4790 || rs6000_cpu
== PROCESSOR_POWER5
4791 || rs6000_cpu
== PROCESSOR_POWER6
4792 || rs6000_cpu
== PROCESSOR_POWER7
4793 || rs6000_cpu
== PROCESSOR_POWER8
4794 || rs6000_cpu
== PROCESSOR_POWER9
4795 || rs6000_cpu
== PROCESSOR_PPCE500MC
4796 || rs6000_cpu
== PROCESSOR_PPCE500MC64
4797 || rs6000_cpu
== PROCESSOR_PPCE5500
4798 || rs6000_cpu
== PROCESSOR_PPCE6500
);
4800 /* Allow debug switches to override the above settings. These are set to -1
4801 in rs6000.opt to indicate the user hasn't directly set the switch. */
4802 if (TARGET_ALWAYS_HINT
>= 0)
4803 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
4805 if (TARGET_SCHED_GROUPS
>= 0)
4806 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
4808 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
4809 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
4811 rs6000_sched_restricted_insns_priority
4812 = (rs6000_sched_groups
? 1 : 0);
4814 /* Handle -msched-costly-dep option. */
4815 rs6000_sched_costly_dep
4816 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
4818 if (rs6000_sched_costly_dep_str
)
4820 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
4821 rs6000_sched_costly_dep
= no_dep_costly
;
4822 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
4823 rs6000_sched_costly_dep
= all_deps_costly
;
4824 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
4825 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
4826 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
4827 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
4829 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
4830 atoi (rs6000_sched_costly_dep_str
));
4833 /* Handle -minsert-sched-nops option. */
4834 rs6000_sched_insert_nops
4835 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
4837 if (rs6000_sched_insert_nops_str
)
4839 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
4840 rs6000_sched_insert_nops
= sched_finish_none
;
4841 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
4842 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
4843 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
4844 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
4846 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
4847 atoi (rs6000_sched_insert_nops_str
));
4852 #ifdef TARGET_REGNAMES
4853 /* If the user desires alternate register names, copy in the
4854 alternate names now. */
4855 if (TARGET_REGNAMES
)
4856 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
4859 /* Set aix_struct_return last, after the ABI is determined.
4860 If -maix-struct-return or -msvr4-struct-return was explicitly
4861 used, don't override with the ABI default. */
4862 if (!global_options_set
.x_aix_struct_return
)
4863 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
4866 /* IBM XL compiler defaults to unsigned bitfields. */
4867 if (TARGET_XL_COMPAT
)
4868 flag_signed_bitfields
= 0;
4871 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
4872 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
4874 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
4876 /* We can only guarantee the availability of DI pseudo-ops when
4877 assembling for 64-bit targets. */
4880 targetm
.asm_out
.aligned_op
.di
= NULL
;
4881 targetm
.asm_out
.unaligned_op
.di
= NULL
;
4885 /* Set branch target alignment, if not optimizing for size. */
4888 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
4889 aligned 8byte to avoid misprediction by the branch predictor. */
4890 if (rs6000_cpu
== PROCESSOR_TITAN
4891 || rs6000_cpu
== PROCESSOR_CELL
)
4893 if (align_functions
<= 0)
4894 align_functions
= 8;
4895 if (align_jumps
<= 0)
4897 if (align_loops
<= 0)
4900 if (rs6000_align_branch_targets
)
4902 if (align_functions
<= 0)
4903 align_functions
= 16;
4904 if (align_jumps
<= 0)
4906 if (align_loops
<= 0)
4908 can_override_loop_align
= 1;
4912 if (align_jumps_max_skip
<= 0)
4913 align_jumps_max_skip
= 15;
4914 if (align_loops_max_skip
<= 0)
4915 align_loops_max_skip
= 15;
4918 /* Arrange to save and restore machine status around nested functions. */
4919 init_machine_status
= rs6000_init_machine_status
;
4921 /* We should always be splitting complex arguments, but we can't break
4922 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
4923 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
4924 targetm
.calls
.split_complex_arg
= NULL
;
4926 /* The AIX and ELFv1 ABIs define standard function descriptors. */
4927 if (DEFAULT_ABI
== ABI_AIX
)
4928 targetm
.calls
.custom_function_descriptors
= 0;
4931 /* Initialize rs6000_cost with the appropriate target costs. */
4933 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
4937 case PROCESSOR_RS64A
:
4938 rs6000_cost
= &rs64a_cost
;
4941 case PROCESSOR_MPCCORE
:
4942 rs6000_cost
= &mpccore_cost
;
4945 case PROCESSOR_PPC403
:
4946 rs6000_cost
= &ppc403_cost
;
4949 case PROCESSOR_PPC405
:
4950 rs6000_cost
= &ppc405_cost
;
4953 case PROCESSOR_PPC440
:
4954 rs6000_cost
= &ppc440_cost
;
4957 case PROCESSOR_PPC476
:
4958 rs6000_cost
= &ppc476_cost
;
4961 case PROCESSOR_PPC601
:
4962 rs6000_cost
= &ppc601_cost
;
4965 case PROCESSOR_PPC603
:
4966 rs6000_cost
= &ppc603_cost
;
4969 case PROCESSOR_PPC604
:
4970 rs6000_cost
= &ppc604_cost
;
4973 case PROCESSOR_PPC604e
:
4974 rs6000_cost
= &ppc604e_cost
;
4977 case PROCESSOR_PPC620
:
4978 rs6000_cost
= &ppc620_cost
;
4981 case PROCESSOR_PPC630
:
4982 rs6000_cost
= &ppc630_cost
;
4985 case PROCESSOR_CELL
:
4986 rs6000_cost
= &ppccell_cost
;
4989 case PROCESSOR_PPC750
:
4990 case PROCESSOR_PPC7400
:
4991 rs6000_cost
= &ppc750_cost
;
4994 case PROCESSOR_PPC7450
:
4995 rs6000_cost
= &ppc7450_cost
;
4998 case PROCESSOR_PPC8540
:
4999 case PROCESSOR_PPC8548
:
5000 rs6000_cost
= &ppc8540_cost
;
5003 case PROCESSOR_PPCE300C2
:
5004 case PROCESSOR_PPCE300C3
:
5005 rs6000_cost
= &ppce300c2c3_cost
;
5008 case PROCESSOR_PPCE500MC
:
5009 rs6000_cost
= &ppce500mc_cost
;
5012 case PROCESSOR_PPCE500MC64
:
5013 rs6000_cost
= &ppce500mc64_cost
;
5016 case PROCESSOR_PPCE5500
:
5017 rs6000_cost
= &ppce5500_cost
;
5020 case PROCESSOR_PPCE6500
:
5021 rs6000_cost
= &ppce6500_cost
;
5024 case PROCESSOR_TITAN
:
5025 rs6000_cost
= &titan_cost
;
5028 case PROCESSOR_POWER4
:
5029 case PROCESSOR_POWER5
:
5030 rs6000_cost
= &power4_cost
;
5033 case PROCESSOR_POWER6
:
5034 rs6000_cost
= &power6_cost
;
5037 case PROCESSOR_POWER7
:
5038 rs6000_cost
= &power7_cost
;
5041 case PROCESSOR_POWER8
:
5042 rs6000_cost
= &power8_cost
;
5045 case PROCESSOR_POWER9
:
5046 rs6000_cost
= &power9_cost
;
5049 case PROCESSOR_PPCA2
:
5050 rs6000_cost
= &ppca2_cost
;
5059 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
5060 rs6000_cost
->simultaneous_prefetches
,
5061 global_options
.x_param_values
,
5062 global_options_set
.x_param_values
);
5063 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
5064 global_options
.x_param_values
,
5065 global_options_set
.x_param_values
);
5066 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
5067 rs6000_cost
->cache_line_size
,
5068 global_options
.x_param_values
,
5069 global_options_set
.x_param_values
);
5070 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
5071 global_options
.x_param_values
,
5072 global_options_set
.x_param_values
);
5074 /* Increase loop peeling limits based on performance analysis. */
5075 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
5076 global_options
.x_param_values
,
5077 global_options_set
.x_param_values
);
5078 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
5079 global_options
.x_param_values
,
5080 global_options_set
.x_param_values
);
5082 /* If using typedef char *va_list, signal that
5083 __builtin_va_start (&ap, 0) can be optimized to
5084 ap = __builtin_next_arg (0). */
5085 if (DEFAULT_ABI
!= ABI_V4
)
5086 targetm
.expand_builtin_va_start
= NULL
;
5089 /* Set up single/double float flags.
5090 If TARGET_HARD_FLOAT is set, but neither single or double is set,
5091 then set both flags. */
5092 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
5093 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
5094 rs6000_single_float
= rs6000_double_float
= 1;
5096 /* If not explicitly specified via option, decide whether to generate indexed
5097 load/store instructions. */
5098 if (TARGET_AVOID_XFORM
== -1)
5099 /* Avoid indexed addressing when targeting Power6 in order to avoid the
5100 DERAT mispredict penalty. However the LVE and STVE altivec instructions
5101 need indexed accesses and the type used is the scalar type of the element
5102 being loaded or stored. */
5103 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
5104 && !TARGET_ALTIVEC
);
5106 /* Set the -mrecip options. */
5107 if (rs6000_recip_name
)
5109 char *p
= ASTRDUP (rs6000_recip_name
);
5111 unsigned int mask
, i
;
5114 while ((q
= strtok (p
, ",")) != NULL
)
5125 if (!strcmp (q
, "default"))
5126 mask
= ((TARGET_RECIP_PRECISION
)
5127 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
5130 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
5131 if (!strcmp (q
, recip_options
[i
].string
))
5133 mask
= recip_options
[i
].mask
;
5137 if (i
== ARRAY_SIZE (recip_options
))
5139 error ("unknown option for -mrecip=%s", q
);
5147 rs6000_recip_control
&= ~mask
;
5149 rs6000_recip_control
|= mask
;
5153 /* Set the builtin mask of the various options used that could affect which
5154 builtins were used. In the past we used target_flags, but we've run out
5155 of bits, and some options like SPE and PAIRED are no longer in
5157 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
5158 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
5159 rs6000_print_builtin_options (stderr
, 0, "builtin mask",
5160 rs6000_builtin_mask
);
5162 /* Initialize all of the registers. */
5163 rs6000_init_hard_regno_mode_ok (global_init_p
);
5165 /* Save the initial options in case the user does function specific options */
5167 target_option_default_node
= target_option_current_node
5168 = build_target_option_node (&global_options
);
5170 /* If not explicitly specified via option, decide whether to generate the
5171 extra blr's required to preserve the link stack on some cpus (eg, 476). */
5172 if (TARGET_LINK_STACK
== -1)
5173 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
5178 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
5179 define the target cpu type. */
5182 rs6000_option_override (void)
5184 (void) rs6000_option_override_internal (true);
5186 /* Register machine-specific passes. This needs to be done at start-up.
5187 It's convenient to do it here (like i386 does). */
5188 opt_pass
*pass_analyze_swaps
= make_pass_analyze_swaps (g
);
5190 struct register_pass_info analyze_swaps_info
5191 = { pass_analyze_swaps
, "cse1", 1, PASS_POS_INSERT_BEFORE
};
5193 register_pass (&analyze_swaps_info
);
5197 /* Implement targetm.vectorize.builtin_mask_for_load. */
5199 rs6000_builtin_mask_for_load (void)
5201 /* Don't use lvsl/vperm for P8 and similarly efficient machines. */
5202 if ((TARGET_ALTIVEC
&& !TARGET_VSX
)
5203 || (TARGET_VSX
&& !TARGET_EFFICIENT_UNALIGNED_VSX
))
5204 return altivec_builtin_mask_for_load
;
5209 /* Implement LOOP_ALIGN. */
5211 rs6000_loop_align (rtx label
)
5216 /* Don't override loop alignment if -falign-loops was specified. */
5217 if (!can_override_loop_align
)
5218 return align_loops_log
;
5220 bb
= BLOCK_FOR_INSN (label
);
5221 ninsns
= num_loop_insns(bb
->loop_father
);
5223 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
5224 if (ninsns
> 4 && ninsns
<= 8
5225 && (rs6000_cpu
== PROCESSOR_POWER4
5226 || rs6000_cpu
== PROCESSOR_POWER5
5227 || rs6000_cpu
== PROCESSOR_POWER6
5228 || rs6000_cpu
== PROCESSOR_POWER7
5229 || rs6000_cpu
== PROCESSOR_POWER8
5230 || rs6000_cpu
== PROCESSOR_POWER9
))
5233 return align_loops_log
;
5236 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
5238 rs6000_loop_align_max_skip (rtx_insn
*label
)
5240 return (1 << rs6000_loop_align (label
)) - 1;
5243 /* Return true iff, data reference of TYPE can reach vector alignment (16)
5244 after applying N number of iterations. This routine does not determine
5245 how may iterations are required to reach desired alignment. */
5248 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
5255 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
5258 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
5268 /* Assuming that all other types are naturally aligned. CHECKME! */
5273 /* Return true if the vector misalignment factor is supported by the
5276 rs6000_builtin_support_vector_misalignment (machine_mode mode
,
5283 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5286 /* Return if movmisalign pattern is not supported for this mode. */
5287 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
5290 if (misalignment
== -1)
5292 /* Misalignment factor is unknown at compile time but we know
5293 it's word aligned. */
5294 if (rs6000_vector_alignment_reachable (type
, is_packed
))
5296 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
5298 if (element_size
== 64 || element_size
== 32)
5305 /* VSX supports word-aligned vector. */
5306 if (misalignment
% 4 == 0)
5312 /* Implement targetm.vectorize.builtin_vectorization_cost. */
5314 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
5315 tree vectype
, int misalign
)
5320 switch (type_of_cost
)
5330 case cond_branch_not_taken
:
5339 case vec_promote_demote
:
5345 case cond_branch_taken
:
5348 case unaligned_load
:
5349 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5352 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5354 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5356 /* Double word aligned. */
5364 /* Double word aligned. */
5368 /* Unknown misalignment. */
5381 /* Misaligned loads are not supported. */
5386 case unaligned_store
:
5387 if (TARGET_EFFICIENT_UNALIGNED_VSX
)
5390 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
5392 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
5394 /* Double word aligned. */
5402 /* Double word aligned. */
5406 /* Unknown misalignment. */
5419 /* Misaligned stores are not supported. */
5425 /* This is a rough approximation assuming non-constant elements
5426 constructed into a vector via element insertion. FIXME:
5427 vec_construct is not granular enough for uniformly good
5428 decisions. If the initialization is a splat, this is
5429 cheaper than we estimate. Improve this someday. */
5430 elem_type
= TREE_TYPE (vectype
);
5431 /* 32-bit vectors loaded into registers are stored as double
5432 precision, so we need 2 permutes, 2 converts, and 1 merge
5433 to construct a vector of short floats from them. */
5434 if (SCALAR_FLOAT_TYPE_P (elem_type
)
5435 && TYPE_PRECISION (elem_type
) == 32)
5438 return max (2, TYPE_VECTOR_SUBPARTS (vectype
) - 1);
5445 /* Implement targetm.vectorize.preferred_simd_mode. */
5448 rs6000_preferred_simd_mode (machine_mode mode
)
5457 if (TARGET_ALTIVEC
|| TARGET_VSX
)
5483 if (TARGET_PAIRED_FLOAT
5489 typedef struct _rs6000_cost_data
5491 struct loop
*loop_info
;
5495 /* Test for likely overcommitment of vector hardware resources. If a
5496 loop iteration is relatively large, and too large a percentage of
5497 instructions in the loop are vectorized, the cost model may not
5498 adequately reflect delays from unavailable vector resources.
5499 Penalize the loop body cost for this case. */
5502 rs6000_density_test (rs6000_cost_data
*data
)
5504 const int DENSITY_PCT_THRESHOLD
= 85;
5505 const int DENSITY_SIZE_THRESHOLD
= 70;
5506 const int DENSITY_PENALTY
= 10;
5507 struct loop
*loop
= data
->loop_info
;
5508 basic_block
*bbs
= get_loop_body (loop
);
5509 int nbbs
= loop
->num_nodes
;
5510 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
5513 for (i
= 0; i
< nbbs
; i
++)
5515 basic_block bb
= bbs
[i
];
5516 gimple_stmt_iterator gsi
;
5518 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
5520 gimple
*stmt
= gsi_stmt (gsi
);
5521 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
5523 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
5524 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
5530 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
5532 if (density_pct
> DENSITY_PCT_THRESHOLD
5533 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
5535 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
5536 if (dump_enabled_p ())
5537 dump_printf_loc (MSG_NOTE
, vect_location
,
5538 "density %d%%, cost %d exceeds threshold, penalizing "
5539 "loop body cost by %d%%", density_pct
,
5540 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
5544 /* Implement targetm.vectorize.init_cost. */
5547 rs6000_init_cost (struct loop
*loop_info
)
5549 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
5550 data
->loop_info
= loop_info
;
5551 data
->cost
[vect_prologue
] = 0;
5552 data
->cost
[vect_body
] = 0;
5553 data
->cost
[vect_epilogue
] = 0;
5557 /* Implement targetm.vectorize.add_stmt_cost. */
5560 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
5561 struct _stmt_vec_info
*stmt_info
, int misalign
,
5562 enum vect_cost_model_location where
)
5564 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5565 unsigned retval
= 0;
5567 if (flag_vect_cost_model
)
5569 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
5570 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
5572 /* Statements in an inner loop relative to the loop being
5573 vectorized are weighted more heavily. The value here is
5574 arbitrary and could potentially be improved with analysis. */
5575 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
5576 count
*= 50; /* FIXME. */
5578 retval
= (unsigned) (count
* stmt_cost
);
5579 cost_data
->cost
[where
] += retval
;
5585 /* Implement targetm.vectorize.finish_cost. */
5588 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
5589 unsigned *body_cost
, unsigned *epilogue_cost
)
5591 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
5593 if (cost_data
->loop_info
)
5594 rs6000_density_test (cost_data
);
5596 *prologue_cost
= cost_data
->cost
[vect_prologue
];
5597 *body_cost
= cost_data
->cost
[vect_body
];
5598 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
5601 /* Implement targetm.vectorize.destroy_cost_data. */
5604 rs6000_destroy_cost_data (void *data
)
5609 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
5610 library with vectorized intrinsics. */
5613 rs6000_builtin_vectorized_libmass (combined_fn fn
, tree type_out
,
5617 const char *suffix
= NULL
;
5618 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
5621 machine_mode el_mode
, in_mode
;
5624 /* Libmass is suitable for unsafe math only as it does not correctly support
5625 parts of IEEE with the required precision such as denormals. Only support
5626 it if we have VSX to use the simd d2 or f4 functions.
5627 XXX: Add variable length support. */
5628 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
5631 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5632 n
= TYPE_VECTOR_SUBPARTS (type_out
);
5633 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5634 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5635 if (el_mode
!= in_mode
5671 if (el_mode
== DFmode
&& n
== 2)
5673 bdecl
= mathfn_built_in (double_type_node
, fn
);
5674 suffix
= "d2"; /* pow -> powd2 */
5676 else if (el_mode
== SFmode
&& n
== 4)
5678 bdecl
= mathfn_built_in (float_type_node
, fn
);
5679 suffix
= "4"; /* powf -> powf4 */
5691 gcc_assert (suffix
!= NULL
);
5692 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
5696 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
5697 strcat (name
, suffix
);
5700 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
5701 else if (n_args
== 2)
5702 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
5706 /* Build a function declaration for the vectorized function. */
5707 new_fndecl
= build_decl (BUILTINS_LOCATION
,
5708 FUNCTION_DECL
, get_identifier (name
), fntype
);
5709 TREE_PUBLIC (new_fndecl
) = 1;
5710 DECL_EXTERNAL (new_fndecl
) = 1;
5711 DECL_IS_NOVOPS (new_fndecl
) = 1;
5712 TREE_READONLY (new_fndecl
) = 1;
5717 /* Returns a function decl for a vectorized version of the builtin function
5718 with builtin function code FN and the result vector type TYPE, or NULL_TREE
5719 if it is not available. */
5722 rs6000_builtin_vectorized_function (unsigned int fn
, tree type_out
,
5725 machine_mode in_mode
, out_mode
;
5728 if (TARGET_DEBUG_BUILTIN
)
5729 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
5730 combined_fn_name (combined_fn (fn
)),
5731 GET_MODE_NAME (TYPE_MODE (type_out
)),
5732 GET_MODE_NAME (TYPE_MODE (type_in
)));
5734 if (TREE_CODE (type_out
) != VECTOR_TYPE
5735 || TREE_CODE (type_in
) != VECTOR_TYPE
5736 || !TARGET_VECTORIZE_BUILTINS
)
5739 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5740 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5741 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5742 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5747 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5748 && out_mode
== DFmode
&& out_n
== 2
5749 && in_mode
== DFmode
&& in_n
== 2)
5750 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
5751 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5752 && out_mode
== SFmode
&& out_n
== 4
5753 && in_mode
== SFmode
&& in_n
== 4)
5754 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
5755 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5756 && out_mode
== SFmode
&& out_n
== 4
5757 && in_mode
== SFmode
&& in_n
== 4)
5758 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
5761 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5762 && out_mode
== DFmode
&& out_n
== 2
5763 && in_mode
== DFmode
&& in_n
== 2)
5764 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
5765 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5766 && out_mode
== SFmode
&& out_n
== 4
5767 && in_mode
== SFmode
&& in_n
== 4)
5768 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
5769 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5770 && out_mode
== SFmode
&& out_n
== 4
5771 && in_mode
== SFmode
&& in_n
== 4)
5772 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
5775 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5776 && out_mode
== DFmode
&& out_n
== 2
5777 && in_mode
== DFmode
&& in_n
== 2)
5778 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
5779 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5780 && out_mode
== SFmode
&& out_n
== 4
5781 && in_mode
== SFmode
&& in_n
== 4)
5782 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
5783 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5784 && out_mode
== SFmode
&& out_n
== 4
5785 && in_mode
== SFmode
&& in_n
== 4)
5786 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
5789 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5790 && out_mode
== DFmode
&& out_n
== 2
5791 && in_mode
== DFmode
&& in_n
== 2)
5792 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
5793 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5794 && out_mode
== SFmode
&& out_n
== 4
5795 && in_mode
== SFmode
&& in_n
== 4)
5796 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
5797 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5798 && out_mode
== SFmode
&& out_n
== 4
5799 && in_mode
== SFmode
&& in_n
== 4)
5800 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
5803 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5804 && out_mode
== DFmode
&& out_n
== 2
5805 && in_mode
== DFmode
&& in_n
== 2)
5806 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
5807 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5808 && out_mode
== SFmode
&& out_n
== 4
5809 && in_mode
== SFmode
&& in_n
== 4)
5810 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
5811 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
5812 && out_mode
== SFmode
&& out_n
== 4
5813 && in_mode
== SFmode
&& in_n
== 4)
5814 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
5817 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5818 && flag_unsafe_math_optimizations
5819 && out_mode
== DFmode
&& out_n
== 2
5820 && in_mode
== DFmode
&& in_n
== 2)
5821 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
5822 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5823 && flag_unsafe_math_optimizations
5824 && out_mode
== SFmode
&& out_n
== 4
5825 && in_mode
== SFmode
&& in_n
== 4)
5826 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
5829 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5830 && !flag_trapping_math
5831 && out_mode
== DFmode
&& out_n
== 2
5832 && in_mode
== DFmode
&& in_n
== 2)
5833 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
5834 if (VECTOR_UNIT_VSX_P (V4SFmode
)
5835 && !flag_trapping_math
5836 && out_mode
== SFmode
&& out_n
== 4
5837 && in_mode
== SFmode
&& in_n
== 4)
5838 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
5844 /* Generate calls to libmass if appropriate. */
5845 if (rs6000_veclib_handler
)
5846 return rs6000_veclib_handler (combined_fn (fn
), type_out
, type_in
);
5851 /* Implement TARGET_VECTORIZE_BUILTIN_MD_VECTORIZED_FUNCTION. */
5854 rs6000_builtin_md_vectorized_function (tree fndecl
, tree type_out
,
5857 machine_mode in_mode
, out_mode
;
5860 if (TARGET_DEBUG_BUILTIN
)
5861 fprintf (stderr
, "rs6000_builtin_md_vectorized_function (%s, %s, %s)\n",
5862 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
5863 GET_MODE_NAME (TYPE_MODE (type_out
)),
5864 GET_MODE_NAME (TYPE_MODE (type_in
)));
5866 if (TREE_CODE (type_out
) != VECTOR_TYPE
5867 || TREE_CODE (type_in
) != VECTOR_TYPE
5868 || !TARGET_VECTORIZE_BUILTINS
)
5871 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
5872 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
5873 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
5874 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
5876 enum rs6000_builtins fn
5877 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
5880 case RS6000_BUILTIN_RSQRTF
:
5881 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5882 && out_mode
== SFmode
&& out_n
== 4
5883 && in_mode
== SFmode
&& in_n
== 4)
5884 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
5886 case RS6000_BUILTIN_RSQRT
:
5887 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5888 && out_mode
== DFmode
&& out_n
== 2
5889 && in_mode
== DFmode
&& in_n
== 2)
5890 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
5892 case RS6000_BUILTIN_RECIPF
:
5893 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
5894 && out_mode
== SFmode
&& out_n
== 4
5895 && in_mode
== SFmode
&& in_n
== 4)
5896 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
5898 case RS6000_BUILTIN_RECIP
:
5899 if (VECTOR_UNIT_VSX_P (V2DFmode
)
5900 && out_mode
== DFmode
&& out_n
== 2
5901 && in_mode
== DFmode
&& in_n
== 2)
5902 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
5910 /* Default CPU string for rs6000*_file_start functions. */
5911 static const char *rs6000_default_cpu
;
5913 /* Do anything needed at the start of the asm file. */
5916 rs6000_file_start (void)
5919 const char *start
= buffer
;
5920 FILE *file
= asm_out_file
;
5922 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
5924 default_file_start ();
5926 if (flag_verbose_asm
)
5928 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
5930 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
5932 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
5936 if (global_options_set
.x_rs6000_cpu_index
)
5938 fprintf (file
, "%s -mcpu=%s", start
,
5939 processor_target_table
[rs6000_cpu_index
].name
);
5943 if (global_options_set
.x_rs6000_tune_index
)
5945 fprintf (file
, "%s -mtune=%s", start
,
5946 processor_target_table
[rs6000_tune_index
].name
);
5950 if (PPC405_ERRATUM77
)
5952 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
5956 #ifdef USING_ELFOS_H
5957 switch (rs6000_sdata
)
5959 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
5960 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
5961 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
5962 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
5965 if (rs6000_sdata
&& g_switch_value
)
5967 fprintf (file
, "%s -G %d", start
,
5977 #ifdef USING_ELFOS_H
5978 if (!(rs6000_default_cpu
&& rs6000_default_cpu
[0])
5979 && !global_options_set
.x_rs6000_cpu_index
)
5981 fputs ("\t.machine ", asm_out_file
);
5982 if ((rs6000_isa_flags
& OPTION_MASK_MODULO
) != 0)
5983 fputs ("power9\n", asm_out_file
);
5984 else if ((rs6000_isa_flags
& OPTION_MASK_DIRECT_MOVE
) != 0)
5985 fputs ("power8\n", asm_out_file
);
5986 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTD
) != 0)
5987 fputs ("power7\n", asm_out_file
);
5988 else if ((rs6000_isa_flags
& OPTION_MASK_CMPB
) != 0)
5989 fputs ("power6\n", asm_out_file
);
5990 else if ((rs6000_isa_flags
& OPTION_MASK_POPCNTB
) != 0)
5991 fputs ("power5\n", asm_out_file
);
5992 else if ((rs6000_isa_flags
& OPTION_MASK_MFCRF
) != 0)
5993 fputs ("power4\n", asm_out_file
);
5994 else if ((rs6000_isa_flags
& OPTION_MASK_POWERPC64
) != 0)
5995 fputs ("ppc64\n", asm_out_file
);
5997 fputs ("ppc\n", asm_out_file
);
6001 if (DEFAULT_ABI
== ABI_ELFv2
)
6002 fprintf (file
, "\t.abiversion 2\n");
6006 /* Return nonzero if this function is known to have a null epilogue. */
6009 direct_return (void)
6011 if (reload_completed
)
6013 rs6000_stack_t
*info
= rs6000_stack_info ();
6015 if (info
->first_gp_reg_save
== 32
6016 && info
->first_fp_reg_save
== 64
6017 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
6018 && ! info
->lr_save_p
6019 && ! info
->cr_save_p
6020 && info
->vrsave_size
== 0
6028 /* Return the number of instructions it takes to form a constant in an
6029 integer register. */
6032 num_insns_constant_wide (HOST_WIDE_INT value
)
6034 /* signed constant loadable with addi */
6035 if (((unsigned HOST_WIDE_INT
) value
+ 0x8000) < 0x10000)
6038 /* constant loadable with addis */
6039 else if ((value
& 0xffff) == 0
6040 && (value
>> 31 == -1 || value
>> 31 == 0))
6043 else if (TARGET_POWERPC64
)
6045 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
6046 HOST_WIDE_INT high
= value
>> 31;
6048 if (high
== 0 || high
== -1)
6054 return num_insns_constant_wide (high
) + 1;
6056 return num_insns_constant_wide (low
) + 1;
6058 return (num_insns_constant_wide (high
)
6059 + num_insns_constant_wide (low
) + 1);
6067 num_insns_constant (rtx op
, machine_mode mode
)
6069 HOST_WIDE_INT low
, high
;
6071 switch (GET_CODE (op
))
6074 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
6075 && rs6000_is_valid_and_mask (op
, mode
))
6078 return num_insns_constant_wide (INTVAL (op
));
6080 case CONST_WIDE_INT
:
6083 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
6084 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
6085 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
6090 if (mode
== SFmode
|| mode
== SDmode
)
6094 if (DECIMAL_FLOAT_MODE_P (mode
))
6095 REAL_VALUE_TO_TARGET_DECIMAL32
6096 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
6098 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
6099 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
6103 if (DECIMAL_FLOAT_MODE_P (mode
))
6104 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (op
), l
);
6106 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op
), l
);
6107 high
= l
[WORDS_BIG_ENDIAN
== 0];
6108 low
= l
[WORDS_BIG_ENDIAN
!= 0];
6111 return (num_insns_constant_wide (low
)
6112 + num_insns_constant_wide (high
));
6115 if ((high
== 0 && low
>= 0)
6116 || (high
== -1 && low
< 0))
6117 return num_insns_constant_wide (low
);
6119 else if (rs6000_is_valid_and_mask (op
, mode
))
6123 return num_insns_constant_wide (high
) + 1;
6126 return (num_insns_constant_wide (high
)
6127 + num_insns_constant_wide (low
) + 1);
6135 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
6136 If the mode of OP is MODE_VECTOR_INT, this simply returns the
6137 corresponding element of the vector, but for V4SFmode and V2SFmode,
6138 the corresponding "float" is interpreted as an SImode integer. */
6141 const_vector_elt_as_int (rtx op
, unsigned int elt
)
6145 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
6146 gcc_assert (GET_MODE (op
) != V2DImode
6147 && GET_MODE (op
) != V2DFmode
);
6149 tmp
= CONST_VECTOR_ELT (op
, elt
);
6150 if (GET_MODE (op
) == V4SFmode
6151 || GET_MODE (op
) == V2SFmode
)
6152 tmp
= gen_lowpart (SImode
, tmp
);
6153 return INTVAL (tmp
);
6156 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
6157 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
6158 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
6159 all items are set to the same value and contain COPIES replicas of the
6160 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
6161 operand and the others are set to the value of the operand's msb. */
6164 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
6166 machine_mode mode
= GET_MODE (op
);
6167 machine_mode inner
= GET_MODE_INNER (mode
);
6175 HOST_WIDE_INT splat_val
;
6176 HOST_WIDE_INT msb_val
;
6178 if (mode
== V2DImode
|| mode
== V2DFmode
|| mode
== V1TImode
)
6181 nunits
= GET_MODE_NUNITS (mode
);
6182 bitsize
= GET_MODE_BITSIZE (inner
);
6183 mask
= GET_MODE_MASK (inner
);
6185 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6187 msb_val
= val
>= 0 ? 0 : -1;
6189 /* Construct the value to be splatted, if possible. If not, return 0. */
6190 for (i
= 2; i
<= copies
; i
*= 2)
6192 HOST_WIDE_INT small_val
;
6194 small_val
= splat_val
>> bitsize
;
6196 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
6198 splat_val
= small_val
;
6201 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
6202 if (EASY_VECTOR_15 (splat_val
))
6205 /* Also check if we can splat, and then add the result to itself. Do so if
6206 the value is positive, of if the splat instruction is using OP's mode;
6207 for splat_val < 0, the splat and the add should use the same mode. */
6208 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
6209 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
6212 /* Also check if are loading up the most significant bit which can be done by
6213 loading up -1 and shifting the value left by -1. */
6214 else if (EASY_VECTOR_MSB (splat_val
, inner
))
6220 /* Check if VAL is present in every STEP-th element, and the
6221 other elements are filled with its most significant bit. */
6222 for (i
= 1; i
< nunits
; ++i
)
6224 HOST_WIDE_INT desired_val
;
6225 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
6226 if ((i
& (step
- 1)) == 0)
6229 desired_val
= msb_val
;
6231 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
6238 /* Like vsplitis_constant, but allow the value to be shifted left with a VSLDOI
6239 instruction, filling in the bottom elements with 0 or -1.
6241 Return 0 if the constant cannot be generated with VSLDOI. Return positive
6242 for the number of zeroes to shift in, or negative for the number of 0xff
6245 OP is a CONST_VECTOR. */
6248 vspltis_shifted (rtx op
)
6250 machine_mode mode
= GET_MODE (op
);
6251 machine_mode inner
= GET_MODE_INNER (mode
);
6259 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
)
6262 /* We need to create pseudo registers to do the shift, so don't recognize
6263 shift vector constants after reload. */
6264 if (!can_create_pseudo_p ())
6267 nunits
= GET_MODE_NUNITS (mode
);
6268 mask
= GET_MODE_MASK (inner
);
6270 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? 0 : nunits
- 1);
6272 /* Check if the value can really be the operand of a vspltis[bhw]. */
6273 if (EASY_VECTOR_15 (val
))
6276 /* Also check if we are loading up the most significant bit which can be done
6277 by loading up -1 and shifting the value left by -1. */
6278 else if (EASY_VECTOR_MSB (val
, inner
))
6284 /* Check if VAL is present in every STEP-th element until we find elements
6285 that are 0 or all 1 bits. */
6286 for (i
= 1; i
< nunits
; ++i
)
6288 unsigned elt
= BYTES_BIG_ENDIAN
? i
: nunits
- 1 - i
;
6289 HOST_WIDE_INT elt_val
= const_vector_elt_as_int (op
, elt
);
6291 /* If the value isn't the splat value, check for the remaining elements
6297 for (j
= i
+1; j
< nunits
; ++j
)
6299 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6300 if (const_vector_elt_as_int (op
, elt2
) != 0)
6304 return (nunits
- i
) * GET_MODE_SIZE (inner
);
6307 else if ((elt_val
& mask
) == mask
)
6309 for (j
= i
+1; j
< nunits
; ++j
)
6311 unsigned elt2
= BYTES_BIG_ENDIAN
? j
: nunits
- 1 - j
;
6312 if ((const_vector_elt_as_int (op
, elt2
) & mask
) != mask
)
6316 return -((nunits
- i
) * GET_MODE_SIZE (inner
));
6324 /* If all elements are equal, we don't need to do VLSDOI. */
6329 /* Return true if OP is of the given MODE and can be synthesized
6330 with a vspltisb, vspltish or vspltisw. */
6333 easy_altivec_constant (rtx op
, machine_mode mode
)
6335 unsigned step
, copies
;
6337 if (mode
== VOIDmode
)
6338 mode
= GET_MODE (op
);
6339 else if (mode
!= GET_MODE (op
))
6342 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
6344 if (mode
== V2DFmode
)
6345 return zero_constant (op
, mode
);
6347 else if (mode
== V2DImode
)
6349 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
6350 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
6353 if (zero_constant (op
, mode
))
6356 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
6357 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
6363 /* V1TImode is a special container for TImode. Ignore for now. */
6364 else if (mode
== V1TImode
)
6367 /* Start with a vspltisw. */
6368 step
= GET_MODE_NUNITS (mode
) / 4;
6371 if (vspltis_constant (op
, step
, copies
))
6374 /* Then try with a vspltish. */
6380 if (vspltis_constant (op
, step
, copies
))
6383 /* And finally a vspltisb. */
6389 if (vspltis_constant (op
, step
, copies
))
6392 if (vspltis_shifted (op
) != 0)
6398 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
6399 result is OP. Abort if it is not possible. */
6402 gen_easy_altivec_constant (rtx op
)
6404 machine_mode mode
= GET_MODE (op
);
6405 int nunits
= GET_MODE_NUNITS (mode
);
6406 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
6407 unsigned step
= nunits
/ 4;
6408 unsigned copies
= 1;
6410 /* Start with a vspltisw. */
6411 if (vspltis_constant (op
, step
, copies
))
6412 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
6414 /* Then try with a vspltish. */
6420 if (vspltis_constant (op
, step
, copies
))
6421 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
6423 /* And finally a vspltisb. */
6429 if (vspltis_constant (op
, step
, copies
))
6430 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
6435 /* Return true if OP is of the given MODE and can be synthesized with ISA 3.0
6436 instructions (xxspltib, vupkhsb/vextsb2w/vextb2d).
6438 Return the number of instructions needed (1 or 2) into the address pointed
6441 Return the constant that is being split via CONSTANT_PTR. */
6444 xxspltib_constant_p (rtx op
,
6449 size_t nunits
= GET_MODE_NUNITS (mode
);
6451 HOST_WIDE_INT value
;
6454 /* Set the returned values to out of bound values. */
6455 *num_insns_ptr
= -1;
6456 *constant_ptr
= 256;
6458 if (!TARGET_P9_VECTOR
)
6461 if (mode
== VOIDmode
)
6462 mode
= GET_MODE (op
);
6464 else if (mode
!= GET_MODE (op
) && GET_MODE (op
) != VOIDmode
)
6467 /* Handle (vec_duplicate <constant>). */
6468 if (GET_CODE (op
) == VEC_DUPLICATE
)
6470 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6471 && mode
!= V2DImode
)
6474 element
= XEXP (op
, 0);
6475 if (!CONST_INT_P (element
))
6478 value
= INTVAL (element
);
6479 if (!IN_RANGE (value
, -128, 127))
6483 /* Handle (const_vector [...]). */
6484 else if (GET_CODE (op
) == CONST_VECTOR
)
6486 if (mode
!= V16QImode
&& mode
!= V8HImode
&& mode
!= V4SImode
6487 && mode
!= V2DImode
)
6490 element
= CONST_VECTOR_ELT (op
, 0);
6491 if (!CONST_INT_P (element
))
6494 value
= INTVAL (element
);
6495 if (!IN_RANGE (value
, -128, 127))
6498 for (i
= 1; i
< nunits
; i
++)
6500 element
= CONST_VECTOR_ELT (op
, i
);
6501 if (!CONST_INT_P (element
))
6504 if (value
!= INTVAL (element
))
6509 /* Handle integer constants being loaded into the upper part of the VSX
6510 register as a scalar. If the value isn't 0/-1, only allow it if the mode
6511 can go in Altivec registers. Prefer VSPLTISW/VUPKHSW over XXSPLITIB. */
6512 else if (CONST_INT_P (op
))
6514 if (!SCALAR_INT_MODE_P (mode
))
6517 value
= INTVAL (op
);
6518 if (!IN_RANGE (value
, -128, 127))
6521 if (!IN_RANGE (value
, -1, 0))
6523 if (!(reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
))
6526 if (EASY_VECTOR_15 (value
))
6534 /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
6535 sign extend. Special case 0/-1 to allow getting any VSX register instead
6536 of an Altivec register. */
6537 if ((mode
== V4SImode
|| mode
== V8HImode
) && !IN_RANGE (value
, -1, 0)
6538 && EASY_VECTOR_15 (value
))
6541 /* Return # of instructions and the constant byte for XXSPLTIB. */
6542 if (mode
== V16QImode
)
6545 else if (IN_RANGE (value
, -1, 0))
6551 *constant_ptr
= (int) value
;
6556 output_vec_const_move (rtx
*operands
)
6558 int cst
, cst2
, shift
;
6564 mode
= GET_MODE (dest
);
6568 bool dest_vmx_p
= ALTIVEC_REGNO_P (REGNO (dest
));
6569 int xxspltib_value
= 256;
6572 if (zero_constant (vec
, mode
))
6574 if (TARGET_P9_VECTOR
)
6575 return "xxspltib %x0,0";
6577 else if (dest_vmx_p
)
6578 return "vspltisw %0,0";
6581 return "xxlxor %x0,%x0,%x0";
6584 if (all_ones_constant (vec
, mode
))
6586 if (TARGET_P9_VECTOR
)
6587 return "xxspltib %x0,255";
6589 else if (dest_vmx_p
)
6590 return "vspltisw %0,-1";
6592 else if (TARGET_P8_VECTOR
)
6593 return "xxlorc %x0,%x0,%x0";
6599 if (TARGET_P9_VECTOR
6600 && xxspltib_constant_p (vec
, mode
, &num_insns
, &xxspltib_value
))
6604 operands
[2] = GEN_INT (xxspltib_value
& 0xff);
6605 return "xxspltib %x0,%2";
6616 gcc_assert (ALTIVEC_REGNO_P (REGNO (dest
)));
6617 if (zero_constant (vec
, mode
))
6618 return "vspltisw %0,0";
6620 if (all_ones_constant (vec
, mode
))
6621 return "vspltisw %0,-1";
6623 /* Do we need to construct a value using VSLDOI? */
6624 shift
= vspltis_shifted (vec
);
6628 splat_vec
= gen_easy_altivec_constant (vec
);
6629 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
6630 operands
[1] = XEXP (splat_vec
, 0);
6631 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
6634 switch (GET_MODE (splat_vec
))
6637 return "vspltisw %0,%1";
6640 return "vspltish %0,%1";
6643 return "vspltisb %0,%1";
6650 gcc_assert (TARGET_SPE
);
6652 /* Vector constant 0 is handled as a splitter of V2SI, and in the
6653 pattern of V1DI, V4HI, and V2SF.
6655 FIXME: We should probably return # and add post reload
6656 splitters for these, but this way is so easy ;-). */
6657 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
6658 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
6659 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
6660 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
6662 return "li %0,%1\n\tevmergelo %0,%0,%0";
6663 else if (WORDS_BIG_ENDIAN
)
6664 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
6666 return "li %0,%2\n\tevmergelo %0,%0,%0\n\tli %0,%1";
6669 /* Initialize TARGET of vector PAIRED to VALS. */
6672 paired_expand_vector_init (rtx target
, rtx vals
)
6674 machine_mode mode
= GET_MODE (target
);
6675 int n_elts
= GET_MODE_NUNITS (mode
);
6677 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
6680 for (i
= 0; i
< n_elts
; ++i
)
6682 x
= XVECEXP (vals
, 0, i
);
6683 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6688 /* Load from constant pool. */
6689 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
6695 /* The vector is initialized only with non-constants. */
6696 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
6697 XVECEXP (vals
, 0, 1));
6699 emit_move_insn (target
, new_rtx
);
6703 /* One field is non-constant and the other one is a constant. Load the
6704 constant from the constant pool and use ps_merge instruction to
6705 construct the whole vector. */
6706 op1
= XVECEXP (vals
, 0, 0);
6707 op2
= XVECEXP (vals
, 0, 1);
6709 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
6711 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
6712 emit_move_insn (tmp
, constant_op
);
6714 if (CONSTANT_P (op1
))
6715 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
6717 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
6719 emit_move_insn (target
, new_rtx
);
6723 paired_expand_vector_move (rtx operands
[])
6725 rtx op0
= operands
[0], op1
= operands
[1];
6727 emit_move_insn (op0
, op1
);
6730 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
6731 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
6732 operands for the relation operation COND. This is a recursive
6736 paired_emit_vector_compare (enum rtx_code rcode
,
6737 rtx dest
, rtx op0
, rtx op1
,
6738 rtx cc_op0
, rtx cc_op1
)
6740 rtx tmp
= gen_reg_rtx (V2SFmode
);
6743 gcc_assert (TARGET_PAIRED_FLOAT
);
6744 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
6750 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6754 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
6755 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
6759 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
6762 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6765 tmp1
= gen_reg_rtx (V2SFmode
);
6766 max
= gen_reg_rtx (V2SFmode
);
6767 min
= gen_reg_rtx (V2SFmode
);
6768 gen_reg_rtx (V2SFmode
);
6770 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
6771 emit_insn (gen_selv2sf4
6772 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
6773 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
6774 emit_insn (gen_selv2sf4
6775 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
6776 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
6777 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
6780 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6783 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6786 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6789 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6792 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
6801 /* Emit vector conditional expression.
6802 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
6803 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
6806 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
6807 rtx cond
, rtx cc_op0
, rtx cc_op1
)
6809 enum rtx_code rcode
= GET_CODE (cond
);
6811 if (!TARGET_PAIRED_FLOAT
)
6814 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
6819 /* Initialize vector TARGET to VALS. */
6822 rs6000_expand_vector_init (rtx target
, rtx vals
)
6824 machine_mode mode
= GET_MODE (target
);
6825 machine_mode inner_mode
= GET_MODE_INNER (mode
);
6826 int n_elts
= GET_MODE_NUNITS (mode
);
6827 int n_var
= 0, one_var
= -1;
6828 bool all_same
= true, all_const_zero
= true;
6832 for (i
= 0; i
< n_elts
; ++i
)
6834 x
= XVECEXP (vals
, 0, i
);
6835 if (!(CONST_SCALAR_INT_P (x
) || CONST_DOUBLE_P (x
) || CONST_FIXED_P (x
)))
6836 ++n_var
, one_var
= i
;
6837 else if (x
!= CONST0_RTX (inner_mode
))
6838 all_const_zero
= false;
6840 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
6846 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
6847 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
6848 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
6850 /* Zero register. */
6851 emit_move_insn (target
, CONST0_RTX (mode
));
6854 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
6856 /* Splat immediate. */
6857 emit_insn (gen_rtx_SET (target
, const_vec
));
6862 /* Load from constant pool. */
6863 emit_move_insn (target
, const_vec
);
6868 /* Double word values on VSX can use xxpermdi or lxvdsx. */
6869 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
6871 rtx op0
= XVECEXP (vals
, 0, 0);
6872 rtx op1
= XVECEXP (vals
, 0, 1);
6875 if (!MEM_P (op0
) && !REG_P (op0
))
6876 op0
= force_reg (inner_mode
, op0
);
6877 if (mode
== V2DFmode
)
6878 emit_insn (gen_vsx_splat_v2df (target
, op0
));
6880 emit_insn (gen_vsx_splat_v2di (target
, op0
));
6884 op0
= force_reg (inner_mode
, op0
);
6885 op1
= force_reg (inner_mode
, op1
);
6886 if (mode
== V2DFmode
)
6887 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
6889 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
6894 /* Special case initializing vector int if we are on 64-bit systems with
6895 direct move or we have the ISA 3.0 instructions. */
6896 if (mode
== V4SImode
&& VECTOR_MEM_VSX_P (V4SImode
)
6897 && TARGET_DIRECT_MOVE_64BIT
)
6901 rtx element0
= XVECEXP (vals
, 0, 0);
6902 if (MEM_P (element0
))
6903 element0
= rs6000_address_for_fpconvert (element0
);
6905 element0
= force_reg (SImode
, element0
);
6907 if (TARGET_P9_VECTOR
)
6908 emit_insn (gen_vsx_splat_v4si (target
, element0
));
6911 rtx tmp
= gen_reg_rtx (DImode
);
6912 emit_insn (gen_zero_extendsidi2 (tmp
, element0
));
6913 emit_insn (gen_vsx_splat_v4si_di (target
, tmp
));
6922 for (i
= 0; i
< 4; i
++)
6924 elements
[i
] = XVECEXP (vals
, 0, i
);
6925 if (!CONST_INT_P (elements
[i
]) && !REG_P (elements
[i
]))
6926 elements
[i
] = copy_to_mode_reg (SImode
, elements
[i
]);
6929 emit_insn (gen_vsx_init_v4si (target
, elements
[0], elements
[1],
6930 elements
[2], elements
[3]));
6935 /* With single precision floating point on VSX, know that internally single
6936 precision is actually represented as a double, and either make 2 V2DF
6937 vectors, and convert these vectors to single precision, or do one
6938 conversion, and splat the result to the other elements. */
6939 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (V4SFmode
))
6943 rtx element0
= XVECEXP (vals
, 0, 0);
6945 if (TARGET_P9_VECTOR
)
6947 if (MEM_P (element0
))
6948 element0
= rs6000_address_for_fpconvert (element0
);
6950 emit_insn (gen_vsx_splat_v4sf (target
, element0
));
6955 rtx freg
= gen_reg_rtx (V4SFmode
);
6956 rtx sreg
= force_reg (SFmode
, element0
);
6957 rtx cvt
= (TARGET_XSCVDPSPN
6958 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
6959 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
6962 emit_insn (gen_vsx_xxspltw_v4sf_direct (target
, freg
,
6968 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
6969 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
6970 rtx flt_even
= gen_reg_rtx (V4SFmode
);
6971 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
6972 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
6973 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
6974 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
6975 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
6977 /* Use VMRGEW if we can instead of doing a permute. */
6978 if (TARGET_P8_VECTOR
)
6980 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op2
));
6981 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op1
, op3
));
6982 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6983 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6984 if (BYTES_BIG_ENDIAN
)
6985 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_even
, flt_odd
));
6987 emit_insn (gen_p8_vmrgew_v4sf_direct (target
, flt_odd
, flt_even
));
6991 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
6992 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
6993 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
6994 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
6995 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
7001 /* Special case initializing vector short/char that are splats if we are on
7002 64-bit systems with direct move. */
7003 if (all_same
&& TARGET_DIRECT_MOVE_64BIT
7004 && (mode
== V16QImode
|| mode
== V8HImode
))
7006 rtx op0
= XVECEXP (vals
, 0, 0);
7007 rtx di_tmp
= gen_reg_rtx (DImode
);
7010 op0
= force_reg (GET_MODE_INNER (mode
), op0
);
7012 if (mode
== V16QImode
)
7014 emit_insn (gen_zero_extendqidi2 (di_tmp
, op0
));
7015 emit_insn (gen_vsx_vspltb_di (target
, di_tmp
));
7019 if (mode
== V8HImode
)
7021 emit_insn (gen_zero_extendhidi2 (di_tmp
, op0
));
7022 emit_insn (gen_vsx_vsplth_di (target
, di_tmp
));
7027 /* Store value to stack temp. Load vector element. Splat. However, splat
7028 of 64-bit items is not supported on Altivec. */
7029 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
7031 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
7032 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
7033 XVECEXP (vals
, 0, 0));
7034 x
= gen_rtx_UNSPEC (VOIDmode
,
7035 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
7036 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
7038 gen_rtx_SET (target
, mem
),
7040 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
7041 gen_rtx_PARALLEL (VOIDmode
,
7042 gen_rtvec (1, const0_rtx
)));
7043 emit_insn (gen_rtx_SET (target
, gen_rtx_VEC_DUPLICATE (mode
, x
)));
7047 /* One field is non-constant. Load constant then overwrite
7051 rtx copy
= copy_rtx (vals
);
7053 /* Load constant part of vector, substitute neighboring value for
7055 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
7056 rs6000_expand_vector_init (target
, copy
);
7058 /* Insert variable. */
7059 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
7063 /* Construct the vector in memory one field at a time
7064 and load the whole vector. */
7065 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
7066 for (i
= 0; i
< n_elts
; i
++)
7067 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
7068 i
* GET_MODE_SIZE (inner_mode
)),
7069 XVECEXP (vals
, 0, i
));
7070 emit_move_insn (target
, mem
);
7073 /* Set field ELT of TARGET to VAL. */
7076 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
7078 machine_mode mode
= GET_MODE (target
);
7079 machine_mode inner_mode
= GET_MODE_INNER (mode
);
7080 rtx reg
= gen_reg_rtx (mode
);
7082 int width
= GET_MODE_SIZE (inner_mode
);
7085 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
7087 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
7088 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
7089 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
7093 /* Simplify setting single element vectors like V1TImode. */
7094 if (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (inner_mode
) && elt
== 0)
7096 emit_move_insn (target
, gen_lowpart (mode
, val
));
7100 /* Load single variable value. */
7101 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
7102 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
7103 x
= gen_rtx_UNSPEC (VOIDmode
,
7104 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
7105 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
7107 gen_rtx_SET (reg
, mem
),
7110 /* Linear sequence. */
7111 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
7112 for (i
= 0; i
< 16; ++i
)
7113 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
7115 /* Set permute mask to insert element into target. */
7116 for (i
= 0; i
< width
; ++i
)
7117 XVECEXP (mask
, 0, elt
*width
+ i
)
7118 = GEN_INT (i
+ 0x10);
7119 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
7121 if (BYTES_BIG_ENDIAN
)
7122 x
= gen_rtx_UNSPEC (mode
,
7123 gen_rtvec (3, target
, reg
,
7124 force_reg (V16QImode
, x
)),
7128 if (TARGET_P9_VECTOR
)
7129 x
= gen_rtx_UNSPEC (mode
,
7130 gen_rtvec (3, target
, reg
,
7131 force_reg (V16QImode
, x
)),
7135 /* Invert selector. We prefer to generate VNAND on P8 so
7136 that future fusion opportunities can kick in, but must
7137 generate VNOR elsewhere. */
7138 rtx notx
= gen_rtx_NOT (V16QImode
, force_reg (V16QImode
, x
));
7139 rtx iorx
= (TARGET_P8_VECTOR
7140 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
7141 : gen_rtx_AND (V16QImode
, notx
, notx
));
7142 rtx tmp
= gen_reg_rtx (V16QImode
);
7143 emit_insn (gen_rtx_SET (tmp
, iorx
));
7145 /* Permute with operands reversed and adjusted selector. */
7146 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
7151 emit_insn (gen_rtx_SET (target
, x
));
7154 /* Extract field ELT from VEC into TARGET. */
7157 rs6000_expand_vector_extract (rtx target
, rtx vec
, rtx elt
)
7159 machine_mode mode
= GET_MODE (vec
);
7160 machine_mode inner_mode
= GET_MODE_INNER (mode
);
7163 if (VECTOR_MEM_VSX_P (mode
) && CONST_INT_P (elt
))
7170 gcc_assert (INTVAL (elt
) == 0 && inner_mode
== TImode
);
7171 emit_move_insn (target
, gen_lowpart (TImode
, vec
));
7174 emit_insn (gen_vsx_extract_v2df (target
, vec
, elt
));
7177 emit_insn (gen_vsx_extract_v2di (target
, vec
, elt
));
7180 emit_insn (gen_vsx_extract_v4sf (target
, vec
, elt
));
7183 if (TARGET_DIRECT_MOVE_64BIT
)
7185 emit_insn (gen_vsx_extract_v16qi (target
, vec
, elt
));
7191 if (TARGET_DIRECT_MOVE_64BIT
)
7193 emit_insn (gen_vsx_extract_v8hi (target
, vec
, elt
));
7199 if (TARGET_DIRECT_MOVE_64BIT
)
7201 emit_insn (gen_vsx_extract_v4si (target
, vec
, elt
));
7207 else if (VECTOR_MEM_VSX_P (mode
) && !CONST_INT_P (elt
)
7208 && TARGET_DIRECT_MOVE_64BIT
)
7210 if (GET_MODE (elt
) != DImode
)
7212 rtx tmp
= gen_reg_rtx (DImode
);
7213 convert_move (tmp
, elt
, 0);
7220 emit_insn (gen_vsx_extract_v2df_var (target
, vec
, elt
));
7224 emit_insn (gen_vsx_extract_v2di_var (target
, vec
, elt
));
7228 if (TARGET_UPPER_REGS_SF
)
7230 emit_insn (gen_vsx_extract_v4sf_var (target
, vec
, elt
));
7236 emit_insn (gen_vsx_extract_v4si_var (target
, vec
, elt
));
7240 emit_insn (gen_vsx_extract_v8hi_var (target
, vec
, elt
));
7244 emit_insn (gen_vsx_extract_v16qi_var (target
, vec
, elt
));
7252 gcc_assert (CONST_INT_P (elt
));
7254 /* Allocate mode-sized buffer. */
7255 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
7257 emit_move_insn (mem
, vec
);
7259 /* Add offset to field within buffer matching vector element. */
7260 mem
= adjust_address_nv (mem
, inner_mode
,
7261 INTVAL (elt
) * GET_MODE_SIZE (inner_mode
));
7263 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
7266 /* Helper function to return the register number of a RTX. */
7268 regno_or_subregno (rtx op
)
7272 else if (SUBREG_P (op
))
7273 return subreg_regno (op
);
7278 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
7279 within the vector (ELEMENT) with a mode (SCALAR_MODE). Use a base register
7280 temporary (BASE_TMP) to fixup the address. Return the new memory address
7281 that is valid for reads or writes to a given register (SCALAR_REG). */
7284 rs6000_adjust_vec_address (rtx scalar_reg
,
7288 machine_mode scalar_mode
)
7290 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
7291 rtx addr
= XEXP (mem
, 0);
7296 /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY. */
7297 gcc_assert (GET_RTX_CLASS (GET_CODE (addr
)) != RTX_AUTOINC
);
7299 /* Calculate what we need to add to the address to get the element
7301 if (CONST_INT_P (element
))
7302 element_offset
= GEN_INT (INTVAL (element
) * scalar_size
);
7305 int byte_shift
= exact_log2 (scalar_size
);
7306 gcc_assert (byte_shift
>= 0);
7308 if (byte_shift
== 0)
7309 element_offset
= element
;
7313 if (TARGET_POWERPC64
)
7314 emit_insn (gen_ashldi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
7316 emit_insn (gen_ashlsi3 (base_tmp
, element
, GEN_INT (byte_shift
)));
7318 element_offset
= base_tmp
;
7322 /* Create the new address pointing to the element within the vector. If we
7323 are adding 0, we don't have to change the address. */
7324 if (element_offset
== const0_rtx
)
7327 /* A simple indirect address can be converted into a reg + offset
7329 else if (REG_P (addr
) || SUBREG_P (addr
))
7330 new_addr
= gen_rtx_PLUS (Pmode
, addr
, element_offset
);
7332 /* Optimize D-FORM addresses with constant offset with a constant element, to
7333 include the element offset in the address directly. */
7334 else if (GET_CODE (addr
) == PLUS
)
7336 rtx op0
= XEXP (addr
, 0);
7337 rtx op1
= XEXP (addr
, 1);
7340 gcc_assert (REG_P (op0
) || SUBREG_P (op0
));
7341 if (CONST_INT_P (op1
) && CONST_INT_P (element_offset
))
7343 HOST_WIDE_INT offset
= INTVAL (op1
) + INTVAL (element_offset
);
7344 rtx offset_rtx
= GEN_INT (offset
);
7346 if (IN_RANGE (offset
, -32768, 32767)
7347 && (scalar_size
< 8 || (offset
& 0x3) == 0))
7348 new_addr
= gen_rtx_PLUS (Pmode
, op0
, offset_rtx
);
7351 emit_move_insn (base_tmp
, offset_rtx
);
7352 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7357 bool op1_reg_p
= (REG_P (op1
) || SUBREG_P (op1
));
7358 bool ele_reg_p
= (REG_P (element_offset
) || SUBREG_P (element_offset
));
7360 /* Note, ADDI requires the register being added to be a base
7361 register. If the register was R0, load it up into the temporary
7364 && (ele_reg_p
|| reg_or_subregno (op1
) != FIRST_GPR_REGNO
))
7366 insn
= gen_add3_insn (base_tmp
, op1
, element_offset
);
7367 gcc_assert (insn
!= NULL_RTX
);
7372 && reg_or_subregno (element_offset
) != FIRST_GPR_REGNO
)
7374 insn
= gen_add3_insn (base_tmp
, element_offset
, op1
);
7375 gcc_assert (insn
!= NULL_RTX
);
7381 emit_move_insn (base_tmp
, op1
);
7382 emit_insn (gen_add2_insn (base_tmp
, element_offset
));
7385 new_addr
= gen_rtx_PLUS (Pmode
, op0
, base_tmp
);
7391 emit_move_insn (base_tmp
, addr
);
7392 new_addr
= gen_rtx_PLUS (Pmode
, base_tmp
, element_offset
);
7395 /* If we have a PLUS, we need to see whether the particular register class
7396 allows for D-FORM or X-FORM addressing. */
7397 if (GET_CODE (new_addr
) == PLUS
)
7399 rtx op1
= XEXP (new_addr
, 1);
7400 addr_mask_type addr_mask
;
7401 int scalar_regno
= regno_or_subregno (scalar_reg
);
7403 gcc_assert (scalar_regno
< FIRST_PSEUDO_REGISTER
);
7404 if (INT_REGNO_P (scalar_regno
))
7405 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_GPR
];
7407 else if (FP_REGNO_P (scalar_regno
))
7408 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_FPR
];
7410 else if (ALTIVEC_REGNO_P (scalar_regno
))
7411 addr_mask
= reg_addr
[scalar_mode
].addr_mask
[RELOAD_REG_VMX
];
7416 if (REG_P (op1
) || SUBREG_P (op1
))
7417 valid_addr_p
= (addr_mask
& RELOAD_REG_INDEXED
) != 0;
7419 valid_addr_p
= (addr_mask
& RELOAD_REG_OFFSET
) != 0;
7422 else if (REG_P (new_addr
) || SUBREG_P (new_addr
))
7423 valid_addr_p
= true;
7426 valid_addr_p
= false;
7430 emit_move_insn (base_tmp
, new_addr
);
7431 new_addr
= base_tmp
;
7434 return change_address (mem
, scalar_mode
, new_addr
);
7437 /* Split a variable vec_extract operation into the component instructions. */
7440 rs6000_split_vec_extract_var (rtx dest
, rtx src
, rtx element
, rtx tmp_gpr
,
7443 machine_mode mode
= GET_MODE (src
);
7444 machine_mode scalar_mode
= GET_MODE (dest
);
7445 unsigned scalar_size
= GET_MODE_SIZE (scalar_mode
);
7446 int byte_shift
= exact_log2 (scalar_size
);
7448 gcc_assert (byte_shift
>= 0);
7450 /* If we are given a memory address, optimize to load just the element. We
7451 don't have to adjust the vector element number on little endian
7455 gcc_assert (REG_P (tmp_gpr
));
7456 emit_move_insn (dest
, rs6000_adjust_vec_address (dest
, src
, element
,
7457 tmp_gpr
, scalar_mode
));
7461 else if (REG_P (src
) || SUBREG_P (src
))
7463 int bit_shift
= byte_shift
+ 3;
7466 gcc_assert (REG_P (tmp_gpr
) && REG_P (tmp_altivec
));
7468 /* For little endian, adjust element ordering. For V2DI/V2DF, we can use
7469 an XOR, otherwise we need to subtract. The shift amount is so VSLO
7470 will shift the element into the upper position (adding 3 to convert a
7471 byte shift into a bit shift). */
7472 if (scalar_size
== 8)
7474 if (!VECTOR_ELT_ORDER_BIG
)
7476 emit_insn (gen_xordi3 (tmp_gpr
, element
, const1_rtx
));
7482 /* Generate RLDIC directly to shift left 6 bits and retrieve 1
7484 emit_insn (gen_rtx_SET (tmp_gpr
,
7485 gen_rtx_AND (DImode
,
7486 gen_rtx_ASHIFT (DImode
,
7493 if (!VECTOR_ELT_ORDER_BIG
)
7495 rtx num_ele_m1
= GEN_INT (GET_MODE_NUNITS (mode
) - 1);
7497 emit_insn (gen_anddi3 (tmp_gpr
, element
, num_ele_m1
));
7498 emit_insn (gen_subdi3 (tmp_gpr
, num_ele_m1
, tmp_gpr
));
7504 emit_insn (gen_ashldi3 (tmp_gpr
, element2
, GEN_INT (bit_shift
)));
7507 /* Get the value into the lower byte of the Altivec register where VSLO
7509 if (TARGET_P9_VECTOR
)
7510 emit_insn (gen_vsx_splat_v2di (tmp_altivec
, tmp_gpr
));
7511 else if (can_create_pseudo_p ())
7512 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_gpr
, tmp_gpr
));
7515 rtx tmp_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7516 emit_move_insn (tmp_di
, tmp_gpr
);
7517 emit_insn (gen_vsx_concat_v2di (tmp_altivec
, tmp_di
, tmp_di
));
7520 /* Do the VSLO to get the value into the final location. */
7524 emit_insn (gen_vsx_vslo_v2df (dest
, src
, tmp_altivec
));
7528 emit_insn (gen_vsx_vslo_v2di (dest
, src
, tmp_altivec
));
7533 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7534 rtx tmp_altivec_v4sf
= gen_rtx_REG (V4SFmode
, REGNO (tmp_altivec
));
7535 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7536 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7539 emit_insn (gen_vsx_xscvspdp_scalar2 (dest
, tmp_altivec_v4sf
));
7547 rtx tmp_altivec_di
= gen_rtx_REG (DImode
, REGNO (tmp_altivec
));
7548 rtx src_v2di
= gen_rtx_REG (V2DImode
, REGNO (src
));
7549 rtx tmp_gpr_di
= gen_rtx_REG (DImode
, REGNO (dest
));
7550 emit_insn (gen_vsx_vslo_v2di (tmp_altivec_di
, src_v2di
,
7552 emit_move_insn (tmp_gpr_di
, tmp_altivec_di
);
7553 emit_insn (gen_ashrdi3 (tmp_gpr_di
, tmp_gpr_di
,
7554 GEN_INT (64 - (8 * scalar_size
))));
7568 /* Helper function for rs6000_split_v4si_init to build up a DImode value from
7569 two SImode values. */
7572 rs6000_split_v4si_init_di_reg (rtx dest
, rtx si1
, rtx si2
, rtx tmp
)
7574 const unsigned HOST_WIDE_INT mask_32bit
= HOST_WIDE_INT_C (0xffffffff);
7576 if (CONST_INT_P (si1
) && CONST_INT_P (si2
))
7578 unsigned HOST_WIDE_INT const1
= (UINTVAL (si1
) & mask_32bit
) << 32;
7579 unsigned HOST_WIDE_INT const2
= UINTVAL (si2
) & mask_32bit
;
7581 emit_move_insn (dest
, GEN_INT (const1
| const2
));
7585 /* Put si1 into upper 32-bits of dest. */
7586 if (CONST_INT_P (si1
))
7587 emit_move_insn (dest
, GEN_INT ((UINTVAL (si1
) & mask_32bit
) << 32));
7590 /* Generate RLDIC. */
7591 rtx si1_di
= gen_rtx_REG (DImode
, regno_or_subregno (si1
));
7592 rtx shift_rtx
= gen_rtx_ASHIFT (DImode
, si1_di
, GEN_INT (32));
7593 rtx mask_rtx
= GEN_INT (mask_32bit
<< 32);
7594 rtx and_rtx
= gen_rtx_AND (DImode
, shift_rtx
, mask_rtx
);
7595 gcc_assert (!reg_overlap_mentioned_p (dest
, si1
));
7596 emit_insn (gen_rtx_SET (dest
, and_rtx
));
7599 /* Put si2 into the temporary. */
7600 gcc_assert (!reg_overlap_mentioned_p (dest
, tmp
));
7601 if (CONST_INT_P (si2
))
7602 emit_move_insn (tmp
, GEN_INT (UINTVAL (si2
) & mask_32bit
));
7604 emit_insn (gen_zero_extendsidi2 (tmp
, si2
));
7606 /* Combine the two parts. */
7607 emit_insn (gen_iordi3 (dest
, dest
, tmp
));
7611 /* Split a V4SI initialization. */
7614 rs6000_split_v4si_init (rtx operands
[])
7616 rtx dest
= operands
[0];
7618 /* Destination is a GPR, build up the two DImode parts in place. */
7619 if (REG_P (dest
) || SUBREG_P (dest
))
7621 int d_regno
= regno_or_subregno (dest
);
7622 rtx scalar1
= operands
[1];
7623 rtx scalar2
= operands
[2];
7624 rtx scalar3
= operands
[3];
7625 rtx scalar4
= operands
[4];
7626 rtx tmp1
= operands
[5];
7627 rtx tmp2
= operands
[6];
7629 /* Even though we only need one temporary (plus the destination, which
7630 has an early clobber constraint, try to use two temporaries, one for
7631 each double word created. That way the 2nd insn scheduling pass can
7632 rearrange things so the two parts are done in parallel. */
7633 if (BYTES_BIG_ENDIAN
)
7635 rtx di_lo
= gen_rtx_REG (DImode
, d_regno
);
7636 rtx di_hi
= gen_rtx_REG (DImode
, d_regno
+ 1);
7637 rs6000_split_v4si_init_di_reg (di_lo
, scalar1
, scalar2
, tmp1
);
7638 rs6000_split_v4si_init_di_reg (di_hi
, scalar3
, scalar4
, tmp2
);
7642 rtx di_lo
= gen_rtx_REG (DImode
, d_regno
+ 1);
7643 rtx di_hi
= gen_rtx_REG (DImode
, d_regno
);
7644 gcc_assert (!VECTOR_ELT_ORDER_BIG
);
7645 rs6000_split_v4si_init_di_reg (di_lo
, scalar4
, scalar3
, tmp1
);
7646 rs6000_split_v4si_init_di_reg (di_hi
, scalar2
, scalar1
, tmp2
);
7655 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
7658 invalid_e500_subreg (rtx op
, machine_mode mode
)
7660 if (TARGET_E500_DOUBLE
)
7662 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
7663 subreg:TI and reg:TF. Decimal float modes are like integer
7664 modes (only low part of each register used) for this
7666 if (GET_CODE (op
) == SUBREG
7667 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
7668 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
7669 && REG_P (SUBREG_REG (op
))
7670 && (GET_MODE (SUBREG_REG (op
)) == DFmode
7671 || GET_MODE (SUBREG_REG (op
)) == TFmode
7672 || GET_MODE (SUBREG_REG (op
)) == IFmode
7673 || GET_MODE (SUBREG_REG (op
)) == KFmode
))
7676 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
7678 if (GET_CODE (op
) == SUBREG
7679 && (mode
== DFmode
|| mode
== TFmode
|| mode
== IFmode
7681 && REG_P (SUBREG_REG (op
))
7682 && (GET_MODE (SUBREG_REG (op
)) == DImode
7683 || GET_MODE (SUBREG_REG (op
)) == TImode
7684 || GET_MODE (SUBREG_REG (op
)) == PTImode
7685 || GET_MODE (SUBREG_REG (op
)) == DDmode
7686 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
7691 && GET_CODE (op
) == SUBREG
7693 && REG_P (SUBREG_REG (op
))
7694 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
7700 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
7701 selects whether the alignment is abi mandated, optional, or
7702 both abi and optional alignment. */
7705 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
7707 if (how
!= align_opt
)
7709 if (TREE_CODE (type
) == VECTOR_TYPE
)
7711 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
7712 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
7717 else if (align
< 128)
7720 else if (TARGET_E500_DOUBLE
7721 && TREE_CODE (type
) == REAL_TYPE
7722 && TYPE_MODE (type
) == DFmode
)
7729 if (how
!= align_abi
)
7731 if (TREE_CODE (type
) == ARRAY_TYPE
7732 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
7734 if (align
< BITS_PER_WORD
)
7735 align
= BITS_PER_WORD
;
7742 /* Previous GCC releases forced all vector types to have 16-byte alignment. */
7745 rs6000_special_adjust_field_align_p (tree field
, unsigned int computed
)
7747 if (TARGET_ALTIVEC
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
7749 if (computed
!= 128)
7752 if (!warned
&& warn_psabi
)
7755 inform (input_location
,
7756 "the layout of aggregates containing vectors with"
7757 " %d-byte alignment has changed in GCC 5",
7758 computed
/ BITS_PER_UNIT
);
7761 /* In current GCC there is no special case. */
7768 /* AIX increases natural record alignment to doubleword if the first
7769 field is an FP double while the FP fields remain word aligned. */
7772 rs6000_special_round_type_align (tree type
, unsigned int computed
,
7773 unsigned int specified
)
7775 unsigned int align
= MAX (computed
, specified
);
7776 tree field
= TYPE_FIELDS (type
);
7778 /* Skip all non field decls */
7779 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7780 field
= DECL_CHAIN (field
);
7782 if (field
!= NULL
&& field
!= type
)
7784 type
= TREE_TYPE (field
);
7785 while (TREE_CODE (type
) == ARRAY_TYPE
)
7786 type
= TREE_TYPE (type
);
7788 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
7789 align
= MAX (align
, 64);
7795 /* Darwin increases record alignment to the natural alignment of
7799 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
7800 unsigned int specified
)
7802 unsigned int align
= MAX (computed
, specified
);
7804 if (TYPE_PACKED (type
))
7807 /* Find the first field, looking down into aggregates. */
7809 tree field
= TYPE_FIELDS (type
);
7810 /* Skip all non field decls */
7811 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
7812 field
= DECL_CHAIN (field
);
7815 /* A packed field does not contribute any extra alignment. */
7816 if (DECL_PACKED (field
))
7818 type
= TREE_TYPE (field
);
7819 while (TREE_CODE (type
) == ARRAY_TYPE
)
7820 type
= TREE_TYPE (type
);
7821 } while (AGGREGATE_TYPE_P (type
));
7823 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
7824 align
= MAX (align
, TYPE_ALIGN (type
));
7829 /* Return 1 for an operand in small memory on V.4/eabi. */
7832 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
7833 machine_mode mode ATTRIBUTE_UNUSED
)
7838 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
7841 if (DEFAULT_ABI
!= ABI_V4
)
7844 /* Vector and float memory instructions have a limited offset on the
7845 SPE, so using a vector or float variable directly as an operand is
7848 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
7851 if (GET_CODE (op
) == SYMBOL_REF
)
7854 else if (GET_CODE (op
) != CONST
7855 || GET_CODE (XEXP (op
, 0)) != PLUS
7856 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
7857 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
7862 rtx sum
= XEXP (op
, 0);
7863 HOST_WIDE_INT summand
;
7865 /* We have to be careful here, because it is the referenced address
7866 that must be 32k from _SDA_BASE_, not just the symbol. */
7867 summand
= INTVAL (XEXP (sum
, 1));
7868 if (summand
< 0 || summand
> g_switch_value
)
7871 sym_ref
= XEXP (sum
, 0);
7874 return SYMBOL_REF_SMALL_P (sym_ref
);
7880 /* Return true if either operand is a general purpose register. */
7883 gpr_or_gpr_p (rtx op0
, rtx op1
)
7885 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
7886 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
7889 /* Return true if this is a move direct operation between GPR registers and
7890 floating point/VSX registers. */
7893 direct_move_p (rtx op0
, rtx op1
)
7897 if (!REG_P (op0
) || !REG_P (op1
))
7900 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
7903 regno0
= REGNO (op0
);
7904 regno1
= REGNO (op1
);
7905 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
7908 if (INT_REGNO_P (regno0
))
7909 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
7911 else if (INT_REGNO_P (regno1
))
7913 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
7916 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
7923 /* Return true if the OFFSET is valid for the quad address instructions that
7924 use d-form (register + offset) addressing. */
7927 quad_address_offset_p (HOST_WIDE_INT offset
)
7929 return (IN_RANGE (offset
, -32768, 32767) && ((offset
) & 0xf) == 0);
7932 /* Return true if the ADDR is an acceptable address for a quad memory
7933 operation of mode MODE (either LQ/STQ for general purpose registers, or
7934 LXV/STXV for vector registers under ISA 3.0. GPR_P is true if this address
7935 is intended for LQ/STQ. If it is false, the address is intended for the ISA
7936 3.0 LXV/STXV instruction. */
7939 quad_address_p (rtx addr
, machine_mode mode
, bool strict
)
7943 if (GET_MODE_SIZE (mode
) != 16)
7946 if (legitimate_indirect_address_p (addr
, strict
))
7949 if (VECTOR_MODE_P (mode
) && !mode_supports_vsx_dform_quad (mode
))
7952 if (GET_CODE (addr
) != PLUS
)
7955 op0
= XEXP (addr
, 0);
7956 if (!REG_P (op0
) || !INT_REG_OK_FOR_BASE_P (op0
, strict
))
7959 op1
= XEXP (addr
, 1);
7960 if (!CONST_INT_P (op1
))
7963 return quad_address_offset_p (INTVAL (op1
));
7966 /* Return true if this is a load or store quad operation. This function does
7967 not handle the atomic quad memory instructions. */
7970 quad_load_store_p (rtx op0
, rtx op1
)
7974 if (!TARGET_QUAD_MEMORY
)
7977 else if (REG_P (op0
) && MEM_P (op1
))
7978 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
7979 && quad_memory_operand (op1
, GET_MODE (op1
))
7980 && !reg_overlap_mentioned_p (op0
, op1
));
7982 else if (MEM_P (op0
) && REG_P (op1
))
7983 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
7984 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
7989 if (TARGET_DEBUG_ADDR
)
7991 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
7992 ret
? "true" : "false");
7993 debug_rtx (gen_rtx_SET (op0
, op1
));
7999 /* Given an address, return a constant offset term if one exists. */
8002 address_offset (rtx op
)
8004 if (GET_CODE (op
) == PRE_INC
8005 || GET_CODE (op
) == PRE_DEC
)
8007 else if (GET_CODE (op
) == PRE_MODIFY
8008 || GET_CODE (op
) == LO_SUM
)
8011 if (GET_CODE (op
) == CONST
)
8014 if (GET_CODE (op
) == PLUS
)
8017 if (CONST_INT_P (op
))
8023 /* Return true if the MEM operand is a memory operand suitable for use
8024 with a (full width, possibly multiple) gpr load/store. On
8025 powerpc64 this means the offset must be divisible by 4.
8026 Implements 'Y' constraint.
8028 Accept direct, indexed, offset, lo_sum and tocref. Since this is
8029 a constraint function we know the operand has satisfied a suitable
8030 memory predicate. Also accept some odd rtl generated by reload
8031 (see rs6000_legitimize_reload_address for various forms). It is
8032 important that reload rtl be accepted by appropriate constraints
8033 but not by the operand predicate.
8035 Offsetting a lo_sum should not be allowed, except where we know by
8036 alignment that a 32k boundary is not crossed, but see the ???
8037 comment in rs6000_legitimize_reload_address. Note that by
8038 "offsetting" here we mean a further offset to access parts of the
8039 MEM. It's fine to have a lo_sum where the inner address is offset
8040 from a sym, since the same sym+offset will appear in the high part
8041 of the address calculation. */
8044 mem_operand_gpr (rtx op
, machine_mode mode
)
8046 unsigned HOST_WIDE_INT offset
;
8048 rtx addr
= XEXP (op
, 0);
8050 op
= address_offset (addr
);
8054 offset
= INTVAL (op
);
8055 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
8058 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
8062 if (GET_CODE (addr
) == LO_SUM
)
8063 /* For lo_sum addresses, we must allow any offset except one that
8064 causes a wrap, so test only the low 16 bits. */
8065 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
8067 return offset
+ 0x8000 < 0x10000u
- extra
;
8070 /* As above, but for DS-FORM VSX insns. Unlike mem_operand_gpr,
8071 enforce an offset divisible by 4 even for 32-bit. */
8074 mem_operand_ds_form (rtx op
, machine_mode mode
)
8076 unsigned HOST_WIDE_INT offset
;
8078 rtx addr
= XEXP (op
, 0);
8080 if (!offsettable_address_p (false, mode
, addr
))
8083 op
= address_offset (addr
);
8087 offset
= INTVAL (op
);
8088 if ((offset
& 3) != 0)
8091 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
8095 if (GET_CODE (addr
) == LO_SUM
)
8096 /* For lo_sum addresses, we must allow any offset except one that
8097 causes a wrap, so test only the low 16 bits. */
8098 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
8100 return offset
+ 0x8000 < 0x10000u
- extra
;
8103 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
8106 reg_offset_addressing_ok_p (machine_mode mode
)
8120 /* AltiVec/VSX vector modes. Only reg+reg addressing was valid until the
8121 ISA 3.0 vector d-form addressing mode was added. While TImode is not
8122 a vector mode, if we want to use the VSX registers to move it around,
8123 we need to restrict ourselves to reg+reg addressing. Similarly for
8124 IEEE 128-bit floating point that is passed in a single vector
8126 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
8127 return mode_supports_vsx_dform_quad (mode
);
8134 /* Paired vector modes. Only reg+reg addressing is valid. */
8135 if (TARGET_PAIRED_FLOAT
)
8140 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
8141 addressing for the LFIWZX and STFIWX instructions. */
8142 if (TARGET_NO_SDMODE_STACK
)
8154 virtual_stack_registers_memory_p (rtx op
)
8158 if (GET_CODE (op
) == REG
)
8159 regnum
= REGNO (op
);
8161 else if (GET_CODE (op
) == PLUS
8162 && GET_CODE (XEXP (op
, 0)) == REG
8163 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
8164 regnum
= REGNO (XEXP (op
, 0));
8169 return (regnum
>= FIRST_VIRTUAL_REGISTER
8170 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
8173 /* Return true if a MODE sized memory accesses to OP plus OFFSET
8174 is known to not straddle a 32k boundary. This function is used
8175 to determine whether -mcmodel=medium code can use TOC pointer
8176 relative addressing for OP. This means the alignment of the TOC
8177 pointer must also be taken into account, and unfortunately that is
8180 #ifndef POWERPC64_TOC_POINTER_ALIGNMENT
8181 #define POWERPC64_TOC_POINTER_ALIGNMENT 8
8185 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
8189 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
8191 if (GET_CODE (op
) != SYMBOL_REF
)
8194 /* ISA 3.0 vector d-form addressing is restricted, don't allow
8196 if (mode_supports_vsx_dform_quad (mode
))
8199 dsize
= GET_MODE_SIZE (mode
);
8200 decl
= SYMBOL_REF_DECL (op
);
8206 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
8207 replacing memory addresses with an anchor plus offset. We
8208 could find the decl by rummaging around in the block->objects
8209 VEC for the given offset but that seems like too much work. */
8210 dalign
= BITS_PER_UNIT
;
8211 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
8212 && SYMBOL_REF_ANCHOR_P (op
)
8213 && SYMBOL_REF_BLOCK (op
) != NULL
)
8215 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
8217 dalign
= block
->alignment
;
8218 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
8220 else if (CONSTANT_POOL_ADDRESS_P (op
))
8222 /* It would be nice to have get_pool_align().. */
8223 machine_mode cmode
= get_pool_mode (op
);
8225 dalign
= GET_MODE_ALIGNMENT (cmode
);
8228 else if (DECL_P (decl
))
8230 dalign
= DECL_ALIGN (decl
);
8234 /* Allow BLKmode when the entire object is known to not
8235 cross a 32k boundary. */
8236 if (!DECL_SIZE_UNIT (decl
))
8239 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
8242 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
8246 dalign
/= BITS_PER_UNIT
;
8247 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
8248 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
8249 return dalign
>= dsize
;
8255 /* Find how many bits of the alignment we know for this access. */
8256 dalign
/= BITS_PER_UNIT
;
8257 if (dalign
> POWERPC64_TOC_POINTER_ALIGNMENT
)
8258 dalign
= POWERPC64_TOC_POINTER_ALIGNMENT
;
8260 lsb
= offset
& -offset
;
8264 return dalign
>= dsize
;
8268 constant_pool_expr_p (rtx op
)
8272 split_const (op
, &base
, &offset
);
8273 return (GET_CODE (base
) == SYMBOL_REF
8274 && CONSTANT_POOL_ADDRESS_P (base
)
8275 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
8278 static const_rtx tocrel_base
, tocrel_offset
;
8280 /* Return true if OP is a toc pointer relative address (the output
8281 of create_TOC_reference). If STRICT, do not match non-split
8282 -mcmodel=large/medium toc pointer relative addresses. */
8285 toc_relative_expr_p (const_rtx op
, bool strict
)
8290 if (TARGET_CMODEL
!= CMODEL_SMALL
)
8292 /* When strict ensure we have everything tidy. */
8294 && !(GET_CODE (op
) == LO_SUM
8295 && REG_P (XEXP (op
, 0))
8296 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
)))
8299 /* When not strict, allow non-split TOC addresses and also allow
8300 (lo_sum (high ..)) TOC addresses created during reload. */
8301 if (GET_CODE (op
) == LO_SUM
)
8306 tocrel_offset
= const0_rtx
;
8307 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
8309 tocrel_base
= XEXP (op
, 0);
8310 tocrel_offset
= XEXP (op
, 1);
8313 return (GET_CODE (tocrel_base
) == UNSPEC
8314 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
8317 /* Return true if X is a constant pool address, and also for cmodel=medium
8318 if X is a toc-relative address known to be offsettable within MODE. */
8321 legitimate_constant_pool_address_p (const_rtx x
, machine_mode mode
,
8324 return (toc_relative_expr_p (x
, strict
)
8325 && (TARGET_CMODEL
!= CMODEL_MEDIUM
8326 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
8328 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
8329 INTVAL (tocrel_offset
), mode
)));
8333 legitimate_small_data_p (machine_mode mode
, rtx x
)
8335 return (DEFAULT_ABI
== ABI_V4
8336 && !flag_pic
&& !TARGET_TOC
8337 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
8338 && small_data_operand (x
, mode
));
8341 /* SPE offset addressing is limited to 5-bits worth of double words. */
8342 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
8345 rs6000_legitimate_offset_address_p (machine_mode mode
, rtx x
,
8346 bool strict
, bool worst_case
)
8348 unsigned HOST_WIDE_INT offset
;
8351 if (GET_CODE (x
) != PLUS
)
8353 if (!REG_P (XEXP (x
, 0)))
8355 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
8357 if (mode_supports_vsx_dform_quad (mode
))
8358 return quad_address_p (x
, mode
, strict
);
8359 if (!reg_offset_addressing_ok_p (mode
))
8360 return virtual_stack_registers_memory_p (x
);
8361 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
8363 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
8366 offset
= INTVAL (XEXP (x
, 1));
8374 /* SPE vector modes. */
8375 return SPE_CONST_OFFSET_OK (offset
);
8380 /* On e500v2, we may have:
8382 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
8384 Which gets addressed with evldd instructions. */
8385 if (TARGET_E500_DOUBLE
)
8386 return SPE_CONST_OFFSET_OK (offset
);
8388 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
8390 if (VECTOR_MEM_VSX_P (mode
))
8395 if (!TARGET_POWERPC64
)
8397 else if (offset
& 3)
8404 if (TARGET_E500_DOUBLE
)
8405 return (SPE_CONST_OFFSET_OK (offset
)
8406 && SPE_CONST_OFFSET_OK (offset
+ 8));
8415 if (!TARGET_POWERPC64
)
8417 else if (offset
& 3)
8426 return offset
< 0x10000 - extra
;
8430 legitimate_indexed_address_p (rtx x
, int strict
)
8434 if (GET_CODE (x
) != PLUS
)
8440 /* Recognize the rtl generated by reload which we know will later be
8441 replaced with proper base and index regs. */
8443 && reload_in_progress
8444 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
8448 return (REG_P (op0
) && REG_P (op1
)
8449 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
8450 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
8451 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
8452 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
8456 avoiding_indexed_address_p (machine_mode mode
)
8458 /* Avoid indexed addressing for modes that have non-indexed
8459 load/store instruction forms. */
8460 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
8464 legitimate_indirect_address_p (rtx x
, int strict
)
8466 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
8470 macho_lo_sum_memory_operand (rtx x
, machine_mode mode
)
8472 if (!TARGET_MACHO
|| !flag_pic
8473 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
8477 if (GET_CODE (x
) != LO_SUM
)
8479 if (GET_CODE (XEXP (x
, 0)) != REG
)
8481 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
8485 return CONSTANT_P (x
);
8489 legitimate_lo_sum_address_p (machine_mode mode
, rtx x
, int strict
)
8491 if (GET_CODE (x
) != LO_SUM
)
8493 if (GET_CODE (XEXP (x
, 0)) != REG
)
8495 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
8497 /* quad word addresses are restricted, and we can't use LO_SUM. */
8498 if (mode_supports_vsx_dform_quad (mode
))
8500 /* Restrict addressing for DI because of our SUBREG hackery. */
8501 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
8505 if (TARGET_ELF
|| TARGET_MACHO
)
8509 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
8511 /* LRA doesn't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
8512 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
8513 recognizes some LO_SUM addresses as valid although this
8514 function says opposite. In most cases, LRA through different
8515 transformations can generate correct code for address reloads.
8516 It can not manage only some LO_SUM cases. So we need to add
8517 code analogous to one in rs6000_legitimize_reload_address for
8518 LOW_SUM here saying that some addresses are still valid. */
8519 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
8520 && small_toc_ref (x
, VOIDmode
));
8521 if (TARGET_TOC
&& ! large_toc_ok
)
8523 if (GET_MODE_NUNITS (mode
) != 1)
8525 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
8526 && !(/* ??? Assume floating point reg based on mode? */
8527 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
8528 && (mode
== DFmode
|| mode
== DDmode
)))
8531 return CONSTANT_P (x
) || large_toc_ok
;
8538 /* Try machine-dependent ways of modifying an illegitimate address
8539 to be legitimate. If we find one, return the new, valid address.
8540 This is used from only one place: `memory_address' in explow.c.
8542 OLDX is the address as it was before break_out_memory_refs was
8543 called. In some cases it is useful to look at this to decide what
8546 It is always safe for this function to do nothing. It exists to
8547 recognize opportunities to optimize the output.
8549 On RS/6000, first check for the sum of a register with a constant
8550 integer that is out of range. If so, generate code to add the
8551 constant with the low-order 16 bits masked to the register and force
8552 this result into another register (this can be done with `cau').
8553 Then generate an address of REG+(CONST&0xffff), allowing for the
8554 possibility of bit 16 being a one.
8556 Then check for the sum of a register and something not constant, try to
8557 load the other things into a register and return the sum. */
8560 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
8565 if (!reg_offset_addressing_ok_p (mode
)
8566 || mode_supports_vsx_dform_quad (mode
))
8568 if (virtual_stack_registers_memory_p (x
))
8571 /* In theory we should not be seeing addresses of the form reg+0,
8572 but just in case it is generated, optimize it away. */
8573 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
8574 return force_reg (Pmode
, XEXP (x
, 0));
8576 /* For TImode with load/store quad, restrict addresses to just a single
8577 pointer, so it works with both GPRs and VSX registers. */
8578 /* Make sure both operands are registers. */
8579 else if (GET_CODE (x
) == PLUS
8580 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
))
8581 return gen_rtx_PLUS (Pmode
,
8582 force_reg (Pmode
, XEXP (x
, 0)),
8583 force_reg (Pmode
, XEXP (x
, 1)));
8585 return force_reg (Pmode
, x
);
8587 if (GET_CODE (x
) == SYMBOL_REF
)
8589 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
8591 return rs6000_legitimize_tls_address (x
, model
);
8603 /* As in legitimate_offset_address_p we do not assume
8604 worst-case. The mode here is just a hint as to the registers
8605 used. A TImode is usually in gprs, but may actually be in
8606 fprs. Leave worst-case scenario for reload to handle via
8607 insn constraints. PTImode is only GPRs. */
8614 if (GET_CODE (x
) == PLUS
8615 && GET_CODE (XEXP (x
, 0)) == REG
8616 && GET_CODE (XEXP (x
, 1)) == CONST_INT
8617 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
8619 && !(SPE_VECTOR_MODE (mode
)
8620 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
8622 HOST_WIDE_INT high_int
, low_int
;
8624 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
8625 if (low_int
>= 0x8000 - extra
)
8627 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
8628 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8629 GEN_INT (high_int
)), 0);
8630 return plus_constant (Pmode
, sum
, low_int
);
8632 else if (GET_CODE (x
) == PLUS
8633 && GET_CODE (XEXP (x
, 0)) == REG
8634 && GET_CODE (XEXP (x
, 1)) != CONST_INT
8635 && GET_MODE_NUNITS (mode
) == 1
8636 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8637 || (/* ??? Assume floating point reg based on mode? */
8638 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
8639 && (mode
== DFmode
|| mode
== DDmode
)))
8640 && !avoiding_indexed_address_p (mode
))
8642 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
8643 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
8645 else if (SPE_VECTOR_MODE (mode
)
8646 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
8650 /* We accept [reg + reg] and [reg + OFFSET]. */
8652 if (GET_CODE (x
) == PLUS
)
8654 rtx op1
= XEXP (x
, 0);
8655 rtx op2
= XEXP (x
, 1);
8658 op1
= force_reg (Pmode
, op1
);
8660 if (GET_CODE (op2
) != REG
8661 && (GET_CODE (op2
) != CONST_INT
8662 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
8663 || (GET_MODE_SIZE (mode
) > 8
8664 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
8665 op2
= force_reg (Pmode
, op2
);
8667 /* We can't always do [reg + reg] for these, because [reg +
8668 reg + offset] is not a legitimate addressing mode. */
8669 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
8671 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
8672 return force_reg (Pmode
, y
);
8677 return force_reg (Pmode
, x
);
8679 else if ((TARGET_ELF
8681 || !MACHO_DYNAMIC_NO_PIC_P
8687 && GET_CODE (x
) != CONST_INT
8688 && GET_CODE (x
) != CONST_WIDE_INT
8689 && GET_CODE (x
) != CONST_DOUBLE
8691 && GET_MODE_NUNITS (mode
) == 1
8692 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
8693 || (/* ??? Assume floating point reg based on mode? */
8694 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
8695 && (mode
== DFmode
|| mode
== DDmode
))))
8697 rtx reg
= gen_reg_rtx (Pmode
);
8699 emit_insn (gen_elf_high (reg
, x
));
8701 emit_insn (gen_macho_high (reg
, x
));
8702 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
8705 && GET_CODE (x
) == SYMBOL_REF
8706 && constant_pool_expr_p (x
)
8707 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
8708 return create_TOC_reference (x
, NULL_RTX
);
8713 /* Debug version of rs6000_legitimize_address. */
8715 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, machine_mode mode
)
8721 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
8722 insns
= get_insns ();
8728 "\nrs6000_legitimize_address: mode %s, old code %s, "
8729 "new code %s, modified\n",
8730 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
8731 GET_RTX_NAME (GET_CODE (ret
)));
8733 fprintf (stderr
, "Original address:\n");
8736 fprintf (stderr
, "oldx:\n");
8739 fprintf (stderr
, "New address:\n");
8744 fprintf (stderr
, "Insns added:\n");
8745 debug_rtx_list (insns
, 20);
8751 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
8752 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
8763 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
8764 We need to emit DTP-relative relocations. */
8766 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
8768 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
8773 fputs ("\t.long\t", file
);
8776 fputs (DOUBLE_INT_ASM_OP
, file
);
8781 output_addr_const (file
, x
);
8783 fputs ("@dtprel+0x8000", file
);
8784 else if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
)
8786 switch (SYMBOL_REF_TLS_MODEL (x
))
8790 case TLS_MODEL_LOCAL_EXEC
:
8791 fputs ("@le", file
);
8793 case TLS_MODEL_INITIAL_EXEC
:
8794 fputs ("@ie", file
);
8796 case TLS_MODEL_GLOBAL_DYNAMIC
:
8797 case TLS_MODEL_LOCAL_DYNAMIC
:
8806 /* Return true if X is a symbol that refers to real (rather than emulated)
8810 rs6000_real_tls_symbol_ref_p (rtx x
)
8812 return (GET_CODE (x
) == SYMBOL_REF
8813 && SYMBOL_REF_TLS_MODEL (x
) >= TLS_MODEL_REAL
);
8816 /* In the name of slightly smaller debug output, and to cater to
8817 general assembler lossage, recognize various UNSPEC sequences
8818 and turn them back into a direct symbol reference. */
8821 rs6000_delegitimize_address (rtx orig_x
)
8825 orig_x
= delegitimize_mem_from_attrs (orig_x
);
8831 if (TARGET_CMODEL
!= CMODEL_SMALL
8832 && GET_CODE (y
) == LO_SUM
)
8836 if (GET_CODE (y
) == PLUS
8837 && GET_MODE (y
) == Pmode
8838 && CONST_INT_P (XEXP (y
, 1)))
8840 offset
= XEXP (y
, 1);
8844 if (GET_CODE (y
) == UNSPEC
8845 && XINT (y
, 1) == UNSPEC_TOCREL
)
8847 y
= XVECEXP (y
, 0, 0);
8850 /* Do not associate thread-local symbols with the original
8851 constant pool symbol. */
8853 && GET_CODE (y
) == SYMBOL_REF
8854 && CONSTANT_POOL_ADDRESS_P (y
)
8855 && rs6000_real_tls_symbol_ref_p (get_pool_constant (y
)))
8859 if (offset
!= NULL_RTX
)
8860 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
8861 if (!MEM_P (orig_x
))
8864 return replace_equiv_address_nv (orig_x
, y
);
8868 && GET_CODE (orig_x
) == LO_SUM
8869 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
8871 y
= XEXP (XEXP (orig_x
, 1), 0);
8872 if (GET_CODE (y
) == UNSPEC
8873 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
8874 return XVECEXP (y
, 0, 0);
8880 /* Return true if X shouldn't be emitted into the debug info.
8881 The linker doesn't like .toc section references from
8882 .debug_* sections, so reject .toc section symbols. */
8885 rs6000_const_not_ok_for_debug_p (rtx x
)
8887 if (GET_CODE (x
) == SYMBOL_REF
8888 && CONSTANT_POOL_ADDRESS_P (x
))
8890 rtx c
= get_pool_constant (x
);
8891 machine_mode cmode
= get_pool_mode (x
);
8892 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
8899 /* Construct the SYMBOL_REF for the tls_get_addr function. */
8901 static GTY(()) rtx rs6000_tls_symbol
;
8903 rs6000_tls_get_addr (void)
8905 if (!rs6000_tls_symbol
)
8906 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
8908 return rs6000_tls_symbol
;
8911 /* Construct the SYMBOL_REF for TLS GOT references. */
8913 static GTY(()) rtx rs6000_got_symbol
;
8915 rs6000_got_sym (void)
8917 if (!rs6000_got_symbol
)
8919 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8920 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
8921 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
8924 return rs6000_got_symbol
;
8927 /* AIX Thread-Local Address support. */
8930 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
8932 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
8936 name
= XSTR (addr
, 0);
8937 /* Append TLS CSECT qualifier, unless the symbol already is qualified
8938 or the symbol will be in TLS private data section. */
8939 if (name
[strlen (name
) - 1] != ']'
8940 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
8941 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
8943 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
8944 strcpy (tlsname
, name
);
8946 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
8947 tlsaddr
= copy_rtx (addr
);
8948 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
8953 /* Place addr into TOC constant pool. */
8954 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
8956 /* Output the TOC entry and create the MEM referencing the value. */
8957 if (constant_pool_expr_p (XEXP (sym
, 0))
8958 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
8960 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
8961 mem
= gen_const_mem (Pmode
, tocref
);
8962 set_mem_alias_set (mem
, get_TOC_alias_set ());
8967 /* Use global-dynamic for local-dynamic. */
8968 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
8969 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
8971 /* Create new TOC reference for @m symbol. */
8972 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
8973 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
8974 strcpy (tlsname
, "*LCM");
8975 strcat (tlsname
, name
+ 3);
8976 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
8977 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
8978 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
8979 rtx modmem
= gen_const_mem (Pmode
, tocref
);
8980 set_mem_alias_set (modmem
, get_TOC_alias_set ());
8982 rtx modreg
= gen_reg_rtx (Pmode
);
8983 emit_insn (gen_rtx_SET (modreg
, modmem
));
8985 tmpreg
= gen_reg_rtx (Pmode
);
8986 emit_insn (gen_rtx_SET (tmpreg
, mem
));
8988 dest
= gen_reg_rtx (Pmode
);
8990 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
8992 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
8995 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
8996 else if (TARGET_32BIT
)
8998 tlsreg
= gen_reg_rtx (SImode
);
8999 emit_insn (gen_tls_get_tpointer (tlsreg
));
9002 tlsreg
= gen_rtx_REG (DImode
, 13);
9004 /* Load the TOC value into temporary register. */
9005 tmpreg
= gen_reg_rtx (Pmode
);
9006 emit_insn (gen_rtx_SET (tmpreg
, mem
));
9007 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
9008 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
9010 /* Add TOC symbol value to TLS pointer. */
9011 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
9016 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
9017 this (thread-local) address. */
9020 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
9025 return rs6000_legitimize_tls_address_aix (addr
, model
);
9027 dest
= gen_reg_rtx (Pmode
);
9028 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
9034 tlsreg
= gen_rtx_REG (Pmode
, 13);
9035 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
9039 tlsreg
= gen_rtx_REG (Pmode
, 2);
9040 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
9044 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
9048 tmp
= gen_reg_rtx (Pmode
);
9051 tlsreg
= gen_rtx_REG (Pmode
, 13);
9052 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
9056 tlsreg
= gen_rtx_REG (Pmode
, 2);
9057 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
9061 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
9063 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
9068 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
9070 /* We currently use relocations like @got@tlsgd for tls, which
9071 means the linker will handle allocation of tls entries, placing
9072 them in the .got section. So use a pointer to the .got section,
9073 not one to secondary TOC sections used by 64-bit -mminimal-toc,
9074 or to secondary GOT sections used by 32-bit -fPIC. */
9076 got
= gen_rtx_REG (Pmode
, 2);
9080 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
9083 rtx gsym
= rs6000_got_sym ();
9084 got
= gen_reg_rtx (Pmode
);
9086 rs6000_emit_move (got
, gsym
, Pmode
);
9091 tmp1
= gen_reg_rtx (Pmode
);
9092 tmp2
= gen_reg_rtx (Pmode
);
9093 mem
= gen_const_mem (Pmode
, tmp1
);
9094 lab
= gen_label_rtx ();
9095 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
9096 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
9097 if (TARGET_LINK_STACK
)
9098 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
9099 emit_move_insn (tmp2
, mem
);
9100 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
9101 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
9106 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
9108 tga
= rs6000_tls_get_addr ();
9109 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
9110 1, const0_rtx
, Pmode
);
9112 r3
= gen_rtx_REG (Pmode
, 3);
9113 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9116 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
9118 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
9120 else if (DEFAULT_ABI
== ABI_V4
)
9121 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
9124 call_insn
= last_call_insn ();
9125 PATTERN (call_insn
) = insn
;
9126 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
9127 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
9128 pic_offset_table_rtx
);
9130 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
9132 tga
= rs6000_tls_get_addr ();
9133 tmp1
= gen_reg_rtx (Pmode
);
9134 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
9135 1, const0_rtx
, Pmode
);
9137 r3
= gen_rtx_REG (Pmode
, 3);
9138 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9141 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
9143 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
9145 else if (DEFAULT_ABI
== ABI_V4
)
9146 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
9149 call_insn
= last_call_insn ();
9150 PATTERN (call_insn
) = insn
;
9151 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
9152 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
9153 pic_offset_table_rtx
);
9155 if (rs6000_tls_size
== 16)
9158 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
9160 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
9162 else if (rs6000_tls_size
== 32)
9164 tmp2
= gen_reg_rtx (Pmode
);
9166 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
9168 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
9171 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
9173 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
9177 tmp2
= gen_reg_rtx (Pmode
);
9179 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
9181 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
9183 insn
= gen_rtx_SET (dest
, gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
9189 /* IE, or 64-bit offset LE. */
9190 tmp2
= gen_reg_rtx (Pmode
);
9192 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
9194 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
9197 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
9199 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
9207 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
9210 rs6000_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
9212 if (GET_CODE (x
) == HIGH
9213 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
9216 /* A TLS symbol in the TOC cannot contain a sum. */
9217 if (GET_CODE (x
) == CONST
9218 && GET_CODE (XEXP (x
, 0)) == PLUS
9219 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
9220 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
9223 /* Do not place an ELF TLS symbol in the constant pool. */
9224 return TARGET_ELF
&& tls_referenced_p (x
);
9227 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
9228 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
9229 can be addressed relative to the toc pointer. */
9232 use_toc_relative_ref (rtx sym
, machine_mode mode
)
9234 return ((constant_pool_expr_p (sym
)
9235 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
9236 get_pool_mode (sym
)))
9237 || (TARGET_CMODEL
== CMODEL_MEDIUM
9238 && SYMBOL_REF_LOCAL_P (sym
)
9239 && GET_MODE_SIZE (mode
) <= POWERPC64_TOC_POINTER_ALIGNMENT
));
9242 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
9243 replace the input X, or the original X if no replacement is called for.
9244 The output parameter *WIN is 1 if the calling macro should goto WIN,
9247 For RS/6000, we wish to handle large displacements off a base
9248 register by splitting the addend across an addiu/addis and the mem insn.
9249 This cuts number of extra insns needed from 3 to 1.
9251 On Darwin, we use this to generate code for floating point constants.
9252 A movsf_low is generated so we wind up with 2 instructions rather than 3.
9253 The Darwin code is inside #if TARGET_MACHO because only then are the
9254 machopic_* functions defined. */
9256 rs6000_legitimize_reload_address (rtx x
, machine_mode mode
,
9257 int opnum
, int type
,
9258 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
9260 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
9261 bool quad_offset_p
= mode_supports_vsx_dform_quad (mode
);
9263 /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
9264 DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
9267 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
9268 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)
9269 || (mode
== SFmode
&& recog_data
.operand_mode
[0] == V4SFmode
9270 && TARGET_P9_VECTOR
)
9271 || (mode
== SImode
&& recog_data
.operand_mode
[0] == V4SImode
9272 && TARGET_P9_VECTOR
)))
9273 reg_offset_p
= false;
9275 /* We must recognize output that we have already generated ourselves. */
9276 if (GET_CODE (x
) == PLUS
9277 && GET_CODE (XEXP (x
, 0)) == PLUS
9278 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
9279 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
9280 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9282 if (TARGET_DEBUG_ADDR
)
9284 fprintf (stderr
, "\nlegitimize_reload_address push_reload #1:\n");
9287 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9288 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
9289 opnum
, (enum reload_type
) type
);
9294 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
9295 if (GET_CODE (x
) == LO_SUM
9296 && GET_CODE (XEXP (x
, 0)) == HIGH
)
9298 if (TARGET_DEBUG_ADDR
)
9300 fprintf (stderr
, "\nlegitimize_reload_address push_reload #2:\n");
9303 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9304 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9305 opnum
, (enum reload_type
) type
);
9311 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
9312 && GET_CODE (x
) == LO_SUM
9313 && GET_CODE (XEXP (x
, 0)) == PLUS
9314 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
9315 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
9316 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
9317 && machopic_operand_p (XEXP (x
, 1)))
9319 /* Result of previous invocation of this function on Darwin
9320 floating point constant. */
9321 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9322 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9323 opnum
, (enum reload_type
) type
);
9329 if (TARGET_CMODEL
!= CMODEL_SMALL
9332 && small_toc_ref (x
, VOIDmode
))
9334 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
9335 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
9336 if (TARGET_DEBUG_ADDR
)
9338 fprintf (stderr
, "\nlegitimize_reload_address push_reload #3:\n");
9341 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9342 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9343 opnum
, (enum reload_type
) type
);
9348 if (GET_CODE (x
) == PLUS
9349 && REG_P (XEXP (x
, 0))
9350 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
9351 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
9352 && CONST_INT_P (XEXP (x
, 1))
9354 && !SPE_VECTOR_MODE (mode
)
9355 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
9356 && (quad_offset_p
|| !VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
9358 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
9359 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
9361 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
9363 /* Check for 32-bit overflow or quad addresses with one of the
9364 four least significant bits set. */
9365 if (high
+ low
!= val
9366 || (quad_offset_p
&& (low
& 0xf)))
9372 /* Reload the high part into a base reg; leave the low part
9373 in the mem directly. */
9375 x
= gen_rtx_PLUS (GET_MODE (x
),
9376 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
9380 if (TARGET_DEBUG_ADDR
)
9382 fprintf (stderr
, "\nlegitimize_reload_address push_reload #4:\n");
9385 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9386 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
9387 opnum
, (enum reload_type
) type
);
9392 if (GET_CODE (x
) == SYMBOL_REF
9395 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
9396 && !SPE_VECTOR_MODE (mode
)
9398 && DEFAULT_ABI
== ABI_DARWIN
9399 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
9400 && machopic_symbol_defined_p (x
)
9402 && DEFAULT_ABI
== ABI_V4
9405 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
9406 The same goes for DImode without 64-bit gprs and DFmode and DDmode
9408 ??? Assume floating point reg based on mode? This assumption is
9409 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
9410 where reload ends up doing a DFmode load of a constant from
9411 mem using two gprs. Unfortunately, at this point reload
9412 hasn't yet selected regs so poking around in reload data
9413 won't help and even if we could figure out the regs reliably,
9414 we'd still want to allow this transformation when the mem is
9415 naturally aligned. Since we say the address is good here, we
9416 can't disable offsets from LO_SUMs in mem_operand_gpr.
9417 FIXME: Allow offset from lo_sum for other modes too, when
9418 mem is sufficiently aligned.
9420 Also disallow this if the type can go in VMX/Altivec registers, since
9421 those registers do not have d-form (reg+offset) address modes. */
9422 && !reg_addr
[mode
].scalar_in_vmx_p
9427 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
9429 && (mode
!= DImode
|| TARGET_POWERPC64
)
9430 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
9431 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
9436 rtx offset
= machopic_gen_offset (x
);
9437 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9438 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
9439 gen_rtx_HIGH (Pmode
, offset
)), offset
);
9443 x
= gen_rtx_LO_SUM (GET_MODE (x
),
9444 gen_rtx_HIGH (Pmode
, x
), x
);
9446 if (TARGET_DEBUG_ADDR
)
9448 fprintf (stderr
, "\nlegitimize_reload_address push_reload #5:\n");
9451 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9452 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9453 opnum
, (enum reload_type
) type
);
9458 /* Reload an offset address wrapped by an AND that represents the
9459 masking of the lower bits. Strip the outer AND and let reload
9460 convert the offset address into an indirect address. For VSX,
9461 force reload to create the address with an AND in a separate
9462 register, because we can't guarantee an altivec register will
9464 if (VECTOR_MEM_ALTIVEC_P (mode
)
9465 && GET_CODE (x
) == AND
9466 && GET_CODE (XEXP (x
, 0)) == PLUS
9467 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
9468 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
9469 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9470 && INTVAL (XEXP (x
, 1)) == -16)
9480 && GET_CODE (x
) == SYMBOL_REF
9481 && use_toc_relative_ref (x
, mode
))
9483 x
= create_TOC_reference (x
, NULL_RTX
);
9484 if (TARGET_CMODEL
!= CMODEL_SMALL
)
9486 if (TARGET_DEBUG_ADDR
)
9488 fprintf (stderr
, "\nlegitimize_reload_address push_reload #6:\n");
9491 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
9492 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
9493 opnum
, (enum reload_type
) type
);
9502 /* Debug version of rs6000_legitimize_reload_address. */
9504 rs6000_debug_legitimize_reload_address (rtx x
, machine_mode mode
,
9505 int opnum
, int type
,
9506 int ind_levels
, int *win
)
9508 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
9511 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
9512 "type = %d, ind_levels = %d, win = %d, original addr:\n",
9513 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
9517 fprintf (stderr
, "Same address returned\n");
9519 fprintf (stderr
, "NULL returned\n");
9522 fprintf (stderr
, "New address:\n");
9529 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
9530 that is a valid memory address for an instruction.
9531 The MODE argument is the machine mode for the MEM expression
9532 that wants to use this address.
9534 On the RS/6000, there are four valid address: a SYMBOL_REF that
9535 refers to a constant pool entry of an address (or the sum of it
9536 plus a constant), a short (16-bit signed) constant plus a register,
9537 the sum of two registers, or a register indirect, possibly with an
9538 auto-increment. For DFmode, DDmode and DImode with a constant plus
9539 register, we must ensure that both words are addressable or PowerPC64
9540 with offset word aligned.
9542 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
9543 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
9544 because adjacent memory cells are accessed by adding word-sized offsets
9545 during assembly output. */
9547 rs6000_legitimate_address_p (machine_mode mode
, rtx x
, bool reg_ok_strict
)
9549 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
9550 bool quad_offset_p
= mode_supports_vsx_dform_quad (mode
);
9552 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
9553 if (VECTOR_MEM_ALTIVEC_P (mode
)
9554 && GET_CODE (x
) == AND
9555 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9556 && INTVAL (XEXP (x
, 1)) == -16)
9559 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
9561 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
9564 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
9565 && mode_supports_pre_incdec_p (mode
)
9566 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
9568 /* Handle restricted vector d-form offsets in ISA 3.0. */
9571 if (quad_address_p (x
, mode
, reg_ok_strict
))
9574 else if (virtual_stack_registers_memory_p (x
))
9577 else if (reg_offset_p
)
9579 if (legitimate_small_data_p (mode
, x
))
9581 if (legitimate_constant_pool_address_p (x
, mode
,
9582 reg_ok_strict
|| lra_in_progress
))
9584 if (reg_addr
[mode
].fused_toc
&& GET_CODE (x
) == UNSPEC
9585 && XINT (x
, 1) == UNSPEC_FUSION_ADDIS
)
9589 /* For TImode, if we have TImode in VSX registers, only allow register
9590 indirect addresses. This will allow the values to go in either GPRs
9591 or VSX registers without reloading. The vector types would tend to
9592 go into VSX registers, so we allow REG+REG, while TImode seems
9593 somewhat split, in that some uses are GPR based, and some VSX based. */
9594 /* FIXME: We could loosen this by changing the following to
9595 if (mode == TImode && TARGET_QUAD_MEMORY && TARGET_VSX_TIMODE)
9596 but currently we cannot allow REG+REG addressing for TImode. See
9597 PR72827 for complete details on how this ends up hoodwinking DSE. */
9598 if (mode
== TImode
&& TARGET_VSX_TIMODE
)
9600 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
9603 && GET_CODE (x
) == PLUS
9604 && GET_CODE (XEXP (x
, 0)) == REG
9605 && (XEXP (x
, 0) == virtual_stack_vars_rtx
9606 || XEXP (x
, 0) == arg_pointer_rtx
)
9607 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9609 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
9611 if (!FLOAT128_2REG_P (mode
)
9612 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
9614 || (mode
!= DFmode
&& mode
!= DDmode
)
9615 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
9616 && (TARGET_POWERPC64
|| mode
!= DImode
)
9617 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
9619 && !avoiding_indexed_address_p (mode
)
9620 && legitimate_indexed_address_p (x
, reg_ok_strict
))
9622 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
9623 && mode_supports_pre_modify_p (mode
)
9624 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
9625 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
9626 reg_ok_strict
, false)
9627 || (!avoiding_indexed_address_p (mode
)
9628 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
9629 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
9631 if (reg_offset_p
&& !quad_offset_p
9632 && legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
9637 /* Debug version of rs6000_legitimate_address_p. */
9639 rs6000_debug_legitimate_address_p (machine_mode mode
, rtx x
,
9642 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
9644 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
9645 "strict = %d, reload = %s, code = %s\n",
9646 ret
? "true" : "false",
9647 GET_MODE_NAME (mode
),
9651 : (reload_in_progress
? "progress" : "before")),
9652 GET_RTX_NAME (GET_CODE (x
)));
9658 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
9661 rs6000_mode_dependent_address_p (const_rtx addr
,
9662 addr_space_t as ATTRIBUTE_UNUSED
)
9664 return rs6000_mode_dependent_address_ptr (addr
);
9667 /* Go to LABEL if ADDR (a legitimate address expression)
9668 has an effect that depends on the machine mode it is used for.
9670 On the RS/6000 this is true of all integral offsets (since AltiVec
9671 and VSX modes don't allow them) or is a pre-increment or decrement.
9673 ??? Except that due to conceptual problems in offsettable_address_p
9674 we can't really report the problems of integral offsets. So leave
9675 this assuming that the adjustable offset must be valid for the
9676 sub-words of a TFmode operand, which is what we had before. */
9679 rs6000_mode_dependent_address (const_rtx addr
)
9681 switch (GET_CODE (addr
))
9684 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
9685 is considered a legitimate address before reload, so there
9686 are no offset restrictions in that case. Note that this
9687 condition is safe in strict mode because any address involving
9688 virtual_stack_vars_rtx or arg_pointer_rtx would already have
9689 been rejected as illegitimate. */
9690 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
9691 && XEXP (addr
, 0) != arg_pointer_rtx
9692 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
9694 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
9695 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
9700 /* Anything in the constant pool is sufficiently aligned that
9701 all bytes have the same high part address. */
9702 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
9704 /* Auto-increment cases are now treated generically in recog.c. */
9706 return TARGET_UPDATE
;
9708 /* AND is only allowed in Altivec loads. */
9719 /* Debug version of rs6000_mode_dependent_address. */
9721 rs6000_debug_mode_dependent_address (const_rtx addr
)
9723 bool ret
= rs6000_mode_dependent_address (addr
);
9725 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
9726 ret
? "true" : "false");
9732 /* Implement FIND_BASE_TERM. */
9735 rs6000_find_base_term (rtx op
)
9740 if (GET_CODE (base
) == CONST
)
9741 base
= XEXP (base
, 0);
9742 if (GET_CODE (base
) == PLUS
)
9743 base
= XEXP (base
, 0);
9744 if (GET_CODE (base
) == UNSPEC
)
9745 switch (XINT (base
, 1))
9748 case UNSPEC_MACHOPIC_OFFSET
:
9749 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
9750 for aliasing purposes. */
9751 return XVECEXP (base
, 0, 0);
9757 /* More elaborate version of recog's offsettable_memref_p predicate
9758 that works around the ??? note of rs6000_mode_dependent_address.
9759 In particular it accepts
9761 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
9763 in 32-bit mode, that the recog predicate rejects. */
9766 rs6000_offsettable_memref_p (rtx op
, machine_mode reg_mode
)
9773 /* First mimic offsettable_memref_p. */
9774 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
9777 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
9778 the latter predicate knows nothing about the mode of the memory
9779 reference and, therefore, assumes that it is the largest supported
9780 mode (TFmode). As a consequence, legitimate offsettable memory
9781 references are rejected. rs6000_legitimate_offset_address_p contains
9782 the correct logic for the PLUS case of rs6000_mode_dependent_address,
9783 at least with a little bit of help here given that we know the
9784 actual registers used. */
9785 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
9786 || GET_MODE_SIZE (reg_mode
) == 4);
9787 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
9791 /* Determine the reassociation width to be used in reassociate_bb.
9792 This takes into account how many parallel operations we
9793 can actually do of a given type, and also the latency.
9797 vect add/sub/mul 2/cycle
9798 fp add/sub/mul 2/cycle
9803 rs6000_reassociation_width (unsigned int opc ATTRIBUTE_UNUSED
,
9804 enum machine_mode mode
)
9808 case PROCESSOR_POWER8
:
9809 case PROCESSOR_POWER9
:
9810 if (DECIMAL_FLOAT_MODE_P (mode
))
9812 if (VECTOR_MODE_P (mode
))
9814 if (INTEGRAL_MODE_P (mode
))
9815 return opc
== MULT_EXPR
? 4 : 6;
9816 if (FLOAT_MODE_P (mode
))
9825 /* Change register usage conditional on target flags. */
9827 rs6000_conditional_register_usage (void)
9831 if (TARGET_DEBUG_TARGET
)
9832 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
9834 /* Set MQ register fixed (already call_used) so that it will not be
9838 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
9840 fixed_regs
[13] = call_used_regs
[13]
9841 = call_really_used_regs
[13] = 1;
9843 /* Conditionally disable FPRs. */
9844 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
9845 for (i
= 32; i
< 64; i
++)
9846 fixed_regs
[i
] = call_used_regs
[i
]
9847 = call_really_used_regs
[i
] = 1;
9849 /* The TOC register is not killed across calls in a way that is
9850 visible to the compiler. */
9851 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9852 call_really_used_regs
[2] = 0;
9854 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
9855 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9857 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
9858 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9859 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9860 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9862 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
9863 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9864 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9865 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9867 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
9868 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
9869 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
9873 global_regs
[SPEFSCR_REGNO
] = 1;
9874 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
9875 registers in prologues and epilogues. We no longer use r14
9876 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
9877 pool for link-compatibility with older versions of GCC. Once
9878 "old" code has died out, we can return r14 to the allocation
9881 = call_used_regs
[14]
9882 = call_really_used_regs
[14] = 1;
9885 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
9887 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
9888 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9889 call_really_used_regs
[VRSAVE_REGNO
] = 1;
9892 if (TARGET_ALTIVEC
|| TARGET_VSX
)
9893 global_regs
[VSCR_REGNO
] = 1;
9895 if (TARGET_ALTIVEC_ABI
)
9897 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
9898 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9900 /* AIX reserves VR20:31 in non-extended ABI mode. */
9902 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
9903 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
9908 /* Output insns to set DEST equal to the constant SOURCE as a series of
9909 lis, ori and shl instructions and return TRUE. */
9912 rs6000_emit_set_const (rtx dest
, rtx source
)
9914 machine_mode mode
= GET_MODE (dest
);
9919 gcc_checking_assert (CONST_INT_P (source
));
9920 c
= INTVAL (source
);
9925 emit_insn (gen_rtx_SET (dest
, source
));
9929 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
9931 emit_insn (gen_rtx_SET (copy_rtx (temp
),
9932 GEN_INT (c
& ~(HOST_WIDE_INT
) 0xffff)));
9933 emit_insn (gen_rtx_SET (dest
,
9934 gen_rtx_IOR (SImode
, copy_rtx (temp
),
9935 GEN_INT (c
& 0xffff))));
9939 if (!TARGET_POWERPC64
)
9943 hi
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
== 0,
9945 lo
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
!= 0,
9947 emit_move_insn (hi
, GEN_INT (c
>> 32));
9948 c
= ((c
& 0xffffffff) ^ 0x80000000) - 0x80000000;
9949 emit_move_insn (lo
, GEN_INT (c
));
9952 rs6000_emit_set_long_const (dest
, c
);
9959 insn
= get_last_insn ();
9960 set
= single_set (insn
);
9961 if (! CONSTANT_P (SET_SRC (set
)))
9962 set_unique_reg_note (insn
, REG_EQUAL
, GEN_INT (c
));
9967 /* Subroutine of rs6000_emit_set_const, handling PowerPC64 DImode.
9968 Output insns to set DEST equal to the constant C as a series of
9969 lis, ori and shl instructions. */
9972 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c
)
9975 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
9985 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
9986 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
9987 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
9989 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
9990 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
9992 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
9994 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
9995 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
9997 emit_move_insn (dest
,
9998 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10001 else if (ud3
== 0 && ud4
== 0)
10003 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
10005 gcc_assert (ud2
& 0x8000);
10006 emit_move_insn (copy_rtx (temp
),
10007 GEN_INT (((ud2
<< 16) ^ 0x80000000) - 0x80000000));
10009 emit_move_insn (copy_rtx (temp
),
10010 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10012 emit_move_insn (dest
,
10013 gen_rtx_ZERO_EXTEND (DImode
,
10014 gen_lowpart (SImode
,
10015 copy_rtx (temp
))));
10017 else if ((ud4
== 0xffff && (ud3
& 0x8000))
10018 || (ud4
== 0 && ! (ud3
& 0x8000)))
10020 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
10022 emit_move_insn (copy_rtx (temp
),
10023 GEN_INT (((ud3
<< 16) ^ 0x80000000) - 0x80000000));
10025 emit_move_insn (copy_rtx (temp
),
10026 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10028 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
10029 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
10032 emit_move_insn (dest
,
10033 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10038 temp
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (DImode
);
10040 emit_move_insn (copy_rtx (temp
),
10041 GEN_INT (((ud4
<< 16) ^ 0x80000000) - 0x80000000));
10043 emit_move_insn (copy_rtx (temp
),
10044 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10047 emit_move_insn (ud2
!= 0 || ud1
!= 0 ? copy_rtx (temp
) : dest
,
10048 gen_rtx_ASHIFT (DImode
, copy_rtx (temp
),
10051 emit_move_insn (ud1
!= 0 ? copy_rtx (temp
) : dest
,
10052 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10053 GEN_INT (ud2
<< 16)));
10055 emit_move_insn (dest
,
10056 gen_rtx_IOR (DImode
, copy_rtx (temp
),
10061 /* Helper for the following. Get rid of [r+r] memory refs
10062 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
10065 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
10067 if (reload_in_progress
)
10070 if (GET_CODE (operands
[0]) == MEM
10071 && GET_CODE (XEXP (operands
[0], 0)) != REG
10072 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
10073 GET_MODE (operands
[0]), false))
10075 = replace_equiv_address (operands
[0],
10076 copy_addr_to_reg (XEXP (operands
[0], 0)));
10078 if (GET_CODE (operands
[1]) == MEM
10079 && GET_CODE (XEXP (operands
[1], 0)) != REG
10080 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
10081 GET_MODE (operands
[1]), false))
10083 = replace_equiv_address (operands
[1],
10084 copy_addr_to_reg (XEXP (operands
[1], 0)));
10087 /* Generate a vector of constants to permute MODE for a little-endian
10088 storage operation by swapping the two halves of a vector. */
10090 rs6000_const_vec (machine_mode mode
)
10118 v
= rtvec_alloc (subparts
);
10120 for (i
= 0; i
< subparts
/ 2; ++i
)
10121 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
10122 for (i
= subparts
/ 2; i
< subparts
; ++i
)
10123 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
10128 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
10129 for a VSX load or store operation. */
10131 rs6000_gen_le_vsx_permute (rtx source
, machine_mode mode
)
10133 /* Use ROTATE instead of VEC_SELECT on IEEE 128-bit floating point, and
10134 128-bit integers if they are allowed in VSX registers. */
10135 if (FLOAT128_VECTOR_P (mode
) || mode
== TImode
)
10136 return gen_rtx_ROTATE (mode
, source
, GEN_INT (64));
10139 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
10140 return gen_rtx_VEC_SELECT (mode
, source
, par
);
10144 /* Emit a little-endian load from vector memory location SOURCE to VSX
10145 register DEST in mode MODE. The load is done with two permuting
10146 insn's that represent an lxvd2x and xxpermdi. */
10148 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, machine_mode mode
)
10150 rtx tmp
, permute_mem
, permute_reg
;
10152 /* Use V2DImode to do swaps of types with 128-bit scalare parts (TImode,
10154 if (mode
== TImode
|| mode
== V1TImode
)
10157 dest
= gen_lowpart (V2DImode
, dest
);
10158 source
= adjust_address (source
, V2DImode
, 0);
10161 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
10162 permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
10163 permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
10164 emit_insn (gen_rtx_SET (tmp
, permute_mem
));
10165 emit_insn (gen_rtx_SET (dest
, permute_reg
));
10168 /* Emit a little-endian store to vector memory location DEST from VSX
10169 register SOURCE in mode MODE. The store is done with two permuting
10170 insn's that represent an xxpermdi and an stxvd2x. */
10172 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, machine_mode mode
)
10174 rtx tmp
, permute_src
, permute_tmp
;
10176 /* This should never be called during or after reload, because it does
10177 not re-permute the source register. It is intended only for use
10179 gcc_assert (!reload_in_progress
&& !lra_in_progress
&& !reload_completed
);
10181 /* Use V2DImode to do swaps of types with 128-bit scalar parts (TImode,
10183 if (mode
== TImode
|| mode
== V1TImode
)
10186 dest
= adjust_address (dest
, V2DImode
, 0);
10187 source
= gen_lowpart (V2DImode
, source
);
10190 tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
10191 permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
10192 permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
10193 emit_insn (gen_rtx_SET (tmp
, permute_src
));
10194 emit_insn (gen_rtx_SET (dest
, permute_tmp
));
10197 /* Emit a sequence representing a little-endian VSX load or store,
10198 moving data from SOURCE to DEST in mode MODE. This is done
10199 separately from rs6000_emit_move to ensure it is called only
10200 during expand. LE VSX loads and stores introduced later are
10201 handled with a split. The expand-time RTL generation allows
10202 us to optimize away redundant pairs of register-permutes. */
10204 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, machine_mode mode
)
10206 gcc_assert (!BYTES_BIG_ENDIAN
10207 && VECTOR_MEM_VSX_P (mode
)
10208 && !TARGET_P9_VECTOR
10209 && !gpr_or_gpr_p (dest
, source
)
10210 && (MEM_P (source
) ^ MEM_P (dest
)));
10212 if (MEM_P (source
))
10214 gcc_assert (REG_P (dest
) || GET_CODE (dest
) == SUBREG
);
10215 rs6000_emit_le_vsx_load (dest
, source
, mode
);
10219 if (!REG_P (source
))
10220 source
= force_reg (mode
, source
);
10221 rs6000_emit_le_vsx_store (dest
, source
, mode
);
10225 /* Emit a move from SOURCE to DEST in mode MODE. */
10227 rs6000_emit_move (rtx dest
, rtx source
, machine_mode mode
)
10230 operands
[0] = dest
;
10231 operands
[1] = source
;
10233 if (TARGET_DEBUG_ADDR
)
10236 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
10237 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
10238 GET_MODE_NAME (mode
),
10239 reload_in_progress
,
10241 can_create_pseudo_p ());
10243 fprintf (stderr
, "source:\n");
10244 debug_rtx (source
);
10247 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
10248 if (CONST_WIDE_INT_P (operands
[1])
10249 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10251 /* This should be fixed with the introduction of CONST_WIDE_INT. */
10252 gcc_unreachable ();
10255 /* Check if GCC is setting up a block move that will end up using FP
10256 registers as temporaries. We must make sure this is acceptable. */
10257 if (GET_CODE (operands
[0]) == MEM
10258 && GET_CODE (operands
[1]) == MEM
10260 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
10261 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
10262 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
10263 ? 32 : MEM_ALIGN (operands
[0])))
10264 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
10266 : MEM_ALIGN (operands
[1]))))
10267 && ! MEM_VOLATILE_P (operands
[0])
10268 && ! MEM_VOLATILE_P (operands
[1]))
10270 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
10271 adjust_address (operands
[1], SImode
, 0));
10272 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
10273 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
10277 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
10278 && !gpc_reg_operand (operands
[1], mode
))
10279 operands
[1] = force_reg (mode
, operands
[1]);
10281 /* Recognize the case where operand[1] is a reference to thread-local
10282 data and load its address to a register. */
10283 if (tls_referenced_p (operands
[1]))
10285 enum tls_model model
;
10286 rtx tmp
= operands
[1];
10289 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
10291 addend
= XEXP (XEXP (tmp
, 0), 1);
10292 tmp
= XEXP (XEXP (tmp
, 0), 0);
10295 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
10296 model
= SYMBOL_REF_TLS_MODEL (tmp
);
10297 gcc_assert (model
!= 0);
10299 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
10302 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
10303 tmp
= force_operand (tmp
, operands
[0]);
10308 /* Handle the case where reload calls us with an invalid address. */
10309 if (reload_in_progress
&& mode
== Pmode
10310 && (! general_operand (operands
[1], mode
)
10311 || ! nonimmediate_operand (operands
[0], mode
)))
10314 /* 128-bit constant floating-point values on Darwin should really be loaded
10315 as two parts. However, this premature splitting is a problem when DFmode
10316 values can go into Altivec registers. */
10317 if (FLOAT128_IBM_P (mode
) && !reg_addr
[DFmode
].scalar_in_vmx_p
10318 && GET_CODE (operands
[1]) == CONST_DOUBLE
)
10320 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
10321 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
10323 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
10324 GET_MODE_SIZE (DFmode
)),
10325 simplify_gen_subreg (DFmode
, operands
[1], mode
,
10326 GET_MODE_SIZE (DFmode
)),
10331 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
10332 cfun
->machine
->sdmode_stack_slot
=
10333 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
10336 /* Transform (p0:DD, (SUBREG:DD p1:SD)) to ((SUBREG:SD p0:DD),
10337 p1:SD) if p1 is not of floating point class and p0 is spilled as
10338 we can have no analogous movsd_store for this. */
10339 if (lra_in_progress
&& mode
== DDmode
10340 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
10341 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
10342 && GET_CODE (operands
[1]) == SUBREG
&& REG_P (SUBREG_REG (operands
[1]))
10343 && GET_MODE (SUBREG_REG (operands
[1])) == SDmode
)
10346 int regno
= REGNO (SUBREG_REG (operands
[1]));
10348 if (regno
>= FIRST_PSEUDO_REGISTER
)
10350 cl
= reg_preferred_class (regno
);
10351 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][1];
10353 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10356 operands
[0] = gen_lowpart_SUBREG (SDmode
, operands
[0]);
10357 operands
[1] = SUBREG_REG (operands
[1]);
10360 if (lra_in_progress
10362 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
10363 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
10364 && (REG_P (operands
[1])
10365 || (GET_CODE (operands
[1]) == SUBREG
10366 && REG_P (SUBREG_REG (operands
[1])))))
10368 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
10369 ? SUBREG_REG (operands
[1]) : operands
[1]);
10372 if (regno
>= FIRST_PSEUDO_REGISTER
)
10374 cl
= reg_preferred_class (regno
);
10375 gcc_assert (cl
!= NO_REGS
);
10376 regno
= ira_class_hard_regs
[cl
][0];
10378 if (FP_REGNO_P (regno
))
10380 if (GET_MODE (operands
[0]) != DDmode
)
10381 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
10382 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
10384 else if (INT_REGNO_P (regno
))
10385 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10390 /* Transform ((SUBREG:DD p0:SD), p1:DD) to (p0:SD, (SUBREG:SD
10391 p:DD)) if p0 is not of floating point class and p1 is spilled as
10392 we can have no analogous movsd_load for this. */
10393 if (lra_in_progress
&& mode
== DDmode
10394 && GET_CODE (operands
[0]) == SUBREG
&& REG_P (SUBREG_REG (operands
[0]))
10395 && GET_MODE (SUBREG_REG (operands
[0])) == SDmode
10396 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
10397 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10400 int regno
= REGNO (SUBREG_REG (operands
[0]));
10402 if (regno
>= FIRST_PSEUDO_REGISTER
)
10404 cl
= reg_preferred_class (regno
);
10405 regno
= cl
== NO_REGS
? -1 : ira_class_hard_regs
[cl
][0];
10407 if (regno
>= 0 && ! FP_REGNO_P (regno
))
10410 operands
[0] = SUBREG_REG (operands
[0]);
10411 operands
[1] = gen_lowpart_SUBREG (SDmode
, operands
[1]);
10414 if (lra_in_progress
10416 && (REG_P (operands
[0])
10417 || (GET_CODE (operands
[0]) == SUBREG
10418 && REG_P (SUBREG_REG (operands
[0]))))
10419 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
10420 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
10422 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
10423 ? SUBREG_REG (operands
[0]) : operands
[0]);
10426 if (regno
>= FIRST_PSEUDO_REGISTER
)
10428 cl
= reg_preferred_class (regno
);
10429 gcc_assert (cl
!= NO_REGS
);
10430 regno
= ira_class_hard_regs
[cl
][0];
10432 if (FP_REGNO_P (regno
))
10434 if (GET_MODE (operands
[1]) != DDmode
)
10435 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
10436 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
10438 else if (INT_REGNO_P (regno
))
10439 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
10445 if (reload_in_progress
10447 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
10448 && MEM_P (operands
[0])
10449 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
10450 && REG_P (operands
[1]))
10452 if (FP_REGNO_P (REGNO (operands
[1])))
10454 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
10455 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
10456 emit_insn (gen_movsd_store (mem
, operands
[1]));
10458 else if (INT_REGNO_P (REGNO (operands
[1])))
10460 rtx mem
= operands
[0];
10461 if (BYTES_BIG_ENDIAN
)
10462 mem
= adjust_address_nv (mem
, mode
, 4);
10463 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
10464 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
10470 if (reload_in_progress
10472 && REG_P (operands
[0])
10473 && MEM_P (operands
[1])
10474 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
10475 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
10477 if (FP_REGNO_P (REGNO (operands
[0])))
10479 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
10480 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
10481 emit_insn (gen_movsd_load (operands
[0], mem
));
10483 else if (INT_REGNO_P (REGNO (operands
[0])))
10485 rtx mem
= operands
[1];
10486 if (BYTES_BIG_ENDIAN
)
10487 mem
= adjust_address_nv (mem
, mode
, 4);
10488 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
10489 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
10496 /* FIXME: In the long term, this switch statement should go away
10497 and be replaced by a sequence of tests based on things like
10503 if (CONSTANT_P (operands
[1])
10504 && GET_CODE (operands
[1]) != CONST_INT
)
10505 operands
[1] = force_const_mem (mode
, operands
[1]);
10512 if (FLOAT128_2REG_P (mode
))
10513 rs6000_eliminate_indexed_memrefs (operands
);
10520 if (CONSTANT_P (operands
[1])
10521 && ! easy_fp_constant (operands
[1], mode
))
10522 operands
[1] = force_const_mem (mode
, operands
[1]);
10536 if (CONSTANT_P (operands
[1])
10537 && !easy_vector_constant (operands
[1], mode
))
10538 operands
[1] = force_const_mem (mode
, operands
[1]);
10543 /* Use default pattern for address of ELF small data */
10546 && DEFAULT_ABI
== ABI_V4
10547 && (GET_CODE (operands
[1]) == SYMBOL_REF
10548 || GET_CODE (operands
[1]) == CONST
)
10549 && small_data_operand (operands
[1], mode
))
10551 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10555 if (DEFAULT_ABI
== ABI_V4
10556 && mode
== Pmode
&& mode
== SImode
10557 && flag_pic
== 1 && got_operand (operands
[1], mode
))
10559 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
10563 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
10567 && CONSTANT_P (operands
[1])
10568 && GET_CODE (operands
[1]) != HIGH
10569 && GET_CODE (operands
[1]) != CONST_INT
)
10571 rtx target
= (!can_create_pseudo_p ()
10573 : gen_reg_rtx (mode
));
10575 /* If this is a function address on -mcall-aixdesc,
10576 convert it to the address of the descriptor. */
10577 if (DEFAULT_ABI
== ABI_AIX
10578 && GET_CODE (operands
[1]) == SYMBOL_REF
10579 && XSTR (operands
[1], 0)[0] == '.')
10581 const char *name
= XSTR (operands
[1], 0);
10583 while (*name
== '.')
10585 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
10586 CONSTANT_POOL_ADDRESS_P (new_ref
)
10587 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
10588 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
10589 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
10590 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
10591 operands
[1] = new_ref
;
10594 if (DEFAULT_ABI
== ABI_DARWIN
)
10597 if (MACHO_DYNAMIC_NO_PIC_P
)
10599 /* Take care of any required data indirection. */
10600 operands
[1] = rs6000_machopic_legitimize_pic_address (
10601 operands
[1], mode
, operands
[0]);
10602 if (operands
[0] != operands
[1])
10603 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10607 emit_insn (gen_macho_high (target
, operands
[1]));
10608 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
10612 emit_insn (gen_elf_high (target
, operands
[1]));
10613 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
10617 /* If this is a SYMBOL_REF that refers to a constant pool entry,
10618 and we have put it in the TOC, we just need to make a TOC-relative
10619 reference to it. */
10621 && GET_CODE (operands
[1]) == SYMBOL_REF
10622 && use_toc_relative_ref (operands
[1], mode
))
10623 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
10624 else if (mode
== Pmode
10625 && CONSTANT_P (operands
[1])
10626 && GET_CODE (operands
[1]) != HIGH
10627 && ((GET_CODE (operands
[1]) != CONST_INT
10628 && ! easy_fp_constant (operands
[1], mode
))
10629 || (GET_CODE (operands
[1]) == CONST_INT
10630 && (num_insns_constant (operands
[1], mode
)
10631 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
10632 || (GET_CODE (operands
[0]) == REG
10633 && FP_REGNO_P (REGNO (operands
[0]))))
10634 && !toc_relative_expr_p (operands
[1], false)
10635 && (TARGET_CMODEL
== CMODEL_SMALL
10636 || can_create_pseudo_p ()
10637 || (REG_P (operands
[0])
10638 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
10642 /* Darwin uses a special PIC legitimizer. */
10643 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
10646 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
10648 if (operands
[0] != operands
[1])
10649 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10654 /* If we are to limit the number of things we put in the TOC and
10655 this is a symbol plus a constant we can add in one insn,
10656 just put the symbol in the TOC and add the constant. Don't do
10657 this if reload is in progress. */
10658 if (GET_CODE (operands
[1]) == CONST
10659 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
10660 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
10661 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
10662 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
10663 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
10664 && ! side_effects_p (operands
[0]))
10667 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
10668 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
10670 sym
= force_reg (mode
, sym
);
10671 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
10675 operands
[1] = force_const_mem (mode
, operands
[1]);
10678 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
10679 && constant_pool_expr_p (XEXP (operands
[1], 0))
10680 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
10681 get_pool_constant (XEXP (operands
[1], 0)),
10682 get_pool_mode (XEXP (operands
[1], 0))))
10684 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
10686 operands
[1] = gen_const_mem (mode
, tocref
);
10687 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
10693 if (!VECTOR_MEM_VSX_P (TImode
))
10694 rs6000_eliminate_indexed_memrefs (operands
);
10698 rs6000_eliminate_indexed_memrefs (operands
);
10702 fatal_insn ("bad move", gen_rtx_SET (dest
, source
));
10705 /* Above, we may have called force_const_mem which may have returned
10706 an invalid address. If we can, fix this up; otherwise, reload will
10707 have to deal with it. */
10708 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
10709 operands
[1] = validize_mem (operands
[1]);
10712 emit_insn (gen_rtx_SET (operands
[0], operands
[1]));
10715 /* Return true if a structure, union or array containing FIELD should be
10716 accessed using `BLKMODE'.
10718 For the SPE, simd types are V2SI, and gcc can be tempted to put the
10719 entire thing in a DI and use subregs to access the internals.
10720 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
10721 back-end. Because a single GPR can hold a V2SI, but not a DI, the
10722 best thing to do is set structs to BLKmode and avoid Severe Tire
10725 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
10726 fit into 1, whereas DI still needs two. */
10729 rs6000_member_type_forces_blk (const_tree field
, machine_mode mode
)
10731 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
10732 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
10735 /* Nonzero if we can use a floating-point register to pass this arg. */
10736 #define USE_FP_FOR_ARG_P(CUM,MODE) \
10737 (SCALAR_FLOAT_MODE_NOT_VECTOR_P (MODE) \
10738 && (CUM)->fregno <= FP_ARG_MAX_REG \
10739 && TARGET_HARD_FLOAT && TARGET_FPRS)
10741 /* Nonzero if we can use an AltiVec register to pass this arg. */
10742 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
10743 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
10744 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
10745 && TARGET_ALTIVEC_ABI \
10748 /* Walk down the type tree of TYPE counting consecutive base elements.
10749 If *MODEP is VOIDmode, then set it to the first valid floating point
10750 or vector type. If a non-floating point or vector type is found, or
10751 if a floating point or vector type that doesn't match a non-VOIDmode
10752 *MODEP is found, then return -1, otherwise return the count in the
10756 rs6000_aggregate_candidate (const_tree type
, machine_mode
*modep
)
10759 HOST_WIDE_INT size
;
10761 switch (TREE_CODE (type
))
10764 mode
= TYPE_MODE (type
);
10765 if (!SCALAR_FLOAT_MODE_P (mode
))
10768 if (*modep
== VOIDmode
)
10771 if (*modep
== mode
)
10777 mode
= TYPE_MODE (TREE_TYPE (type
));
10778 if (!SCALAR_FLOAT_MODE_P (mode
))
10781 if (*modep
== VOIDmode
)
10784 if (*modep
== mode
)
10790 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
10793 /* Use V4SImode as representative of all 128-bit vector types. */
10794 size
= int_size_in_bytes (type
);
10804 if (*modep
== VOIDmode
)
10807 /* Vector modes are considered to be opaque: two vectors are
10808 equivalent for the purposes of being homogeneous aggregates
10809 if they are the same size. */
10810 if (*modep
== mode
)
10818 tree index
= TYPE_DOMAIN (type
);
10820 /* Can't handle incomplete types nor sizes that are not
10822 if (!COMPLETE_TYPE_P (type
)
10823 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10826 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
10829 || !TYPE_MAX_VALUE (index
)
10830 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
10831 || !TYPE_MIN_VALUE (index
)
10832 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
10836 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
10837 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
10839 /* There must be no padding. */
10840 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
10852 /* Can't handle incomplete types nor sizes that are not
10854 if (!COMPLETE_TYPE_P (type
)
10855 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10858 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
10860 if (TREE_CODE (field
) != FIELD_DECL
)
10863 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
10866 count
+= sub_count
;
10869 /* There must be no padding. */
10870 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
10877 case QUAL_UNION_TYPE
:
10879 /* These aren't very interesting except in a degenerate case. */
10884 /* Can't handle incomplete types nor sizes that are not
10886 if (!COMPLETE_TYPE_P (type
)
10887 || TREE_CODE (TYPE_SIZE (type
)) != INTEGER_CST
)
10890 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
10892 if (TREE_CODE (field
) != FIELD_DECL
)
10895 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
10898 count
= count
> sub_count
? count
: sub_count
;
10901 /* There must be no padding. */
10902 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
10915 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
10916 float or vector aggregate that shall be passed in FP/vector registers
10917 according to the ELFv2 ABI, return the homogeneous element mode in
10918 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
10920 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
10923 rs6000_discover_homogeneous_aggregate (machine_mode mode
, const_tree type
,
10924 machine_mode
*elt_mode
,
10927 /* Note that we do not accept complex types at the top level as
10928 homogeneous aggregates; these types are handled via the
10929 targetm.calls.split_complex_arg mechanism. Complex types
10930 can be elements of homogeneous aggregates, however. */
10931 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
10933 machine_mode field_mode
= VOIDmode
;
10934 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
10936 if (field_count
> 0)
10938 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
) ?
10939 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
10941 /* The ELFv2 ABI allows homogeneous aggregates to occupy
10942 up to AGGR_ARG_NUM_REG registers. */
10943 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
10946 *elt_mode
= field_mode
;
10948 *n_elts
= field_count
;
10961 /* Return a nonzero value to say to return the function value in
10962 memory, just as large structures are always returned. TYPE will be
10963 the data type of the value, and FNTYPE will be the type of the
10964 function doing the returning, or @code{NULL} for libcalls.
10966 The AIX ABI for the RS/6000 specifies that all structures are
10967 returned in memory. The Darwin ABI does the same.
10969 For the Darwin 64 Bit ABI, a function result can be returned in
10970 registers or in memory, depending on the size of the return data
10971 type. If it is returned in registers, the value occupies the same
10972 registers as it would if it were the first and only function
10973 argument. Otherwise, the function places its result in memory at
10974 the location pointed to by GPR3.
10976 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
10977 but a draft put them in memory, and GCC used to implement the draft
10978 instead of the final standard. Therefore, aix_struct_return
10979 controls this instead of DEFAULT_ABI; V.4 targets needing backward
10980 compatibility can change DRAFT_V4_STRUCT_RET to override the
10981 default, and -m switches get the final word. See
10982 rs6000_option_override_internal for more details.
10984 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
10985 long double support is enabled. These values are returned in memory.
10987 int_size_in_bytes returns -1 for variable size objects, which go in
10988 memory always. The cast to unsigned makes -1 > 8. */
10991 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
10993 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
10995 && rs6000_darwin64_abi
10996 && TREE_CODE (type
) == RECORD_TYPE
10997 && int_size_in_bytes (type
) > 0)
10999 CUMULATIVE_ARGS valcum
;
11003 valcum
.fregno
= FP_ARG_MIN_REG
;
11004 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
11005 /* Do a trial code generation as if this were going to be passed
11006 as an argument; if any part goes in memory, we return NULL. */
11007 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
11010 /* Otherwise fall through to more conventional ABI rules. */
11013 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
11014 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
11018 /* The ELFv2 ABI returns aggregates up to 16B in registers */
11019 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
11020 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
11023 if (AGGREGATE_TYPE_P (type
)
11024 && (aix_struct_return
11025 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
11028 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
11029 modes only exist for GCC vector types if -maltivec. */
11030 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
11031 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
11034 /* Return synthetic vectors in memory. */
11035 if (TREE_CODE (type
) == VECTOR_TYPE
11036 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
11038 static bool warned_for_return_big_vectors
= false;
11039 if (!warned_for_return_big_vectors
)
11041 warning (OPT_Wpsabi
, "GCC vector returned by reference: "
11042 "non-standard ABI extension with no compatibility guarantee");
11043 warned_for_return_big_vectors
= true;
11048 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
11049 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
11055 /* Specify whether values returned in registers should be at the most
11056 significant end of a register. We want aggregates returned by
11057 value to match the way aggregates are passed to functions. */
11060 rs6000_return_in_msb (const_tree valtype
)
11062 return (DEFAULT_ABI
== ABI_ELFv2
11063 && BYTES_BIG_ENDIAN
11064 && AGGREGATE_TYPE_P (valtype
)
11065 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
11068 #ifdef HAVE_AS_GNU_ATTRIBUTE
11069 /* Return TRUE if a call to function FNDECL may be one that
11070 potentially affects the function calling ABI of the object file. */
11073 call_ABI_of_interest (tree fndecl
)
11075 if (rs6000_gnu_attr
&& symtab
->state
== EXPANSION
)
11077 struct cgraph_node
*c_node
;
11079 /* Libcalls are always interesting. */
11080 if (fndecl
== NULL_TREE
)
11083 /* Any call to an external function is interesting. */
11084 if (DECL_EXTERNAL (fndecl
))
11087 /* Interesting functions that we are emitting in this object file. */
11088 c_node
= cgraph_node::get (fndecl
);
11089 c_node
= c_node
->ultimate_alias_target ();
11090 return !c_node
->only_called_directly_p ();
11096 /* Initialize a variable CUM of type CUMULATIVE_ARGS
11097 for a call to a function whose data type is FNTYPE.
11098 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
11100 For incoming args we set the number of arguments in the prototype large
11101 so we never return a PARALLEL. */
11104 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
11105 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
11106 int libcall
, int n_named_args
,
11107 tree fndecl ATTRIBUTE_UNUSED
,
11108 machine_mode return_mode ATTRIBUTE_UNUSED
)
11110 static CUMULATIVE_ARGS zero_cumulative
;
11112 *cum
= zero_cumulative
;
11114 cum
->fregno
= FP_ARG_MIN_REG
;
11115 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
11116 cum
->prototype
= (fntype
&& prototype_p (fntype
));
11117 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
11118 ? CALL_LIBCALL
: CALL_NORMAL
);
11119 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
11120 cum
->stdarg
= stdarg_p (fntype
);
11121 cum
->libcall
= libcall
;
11123 cum
->nargs_prototype
= 0;
11124 if (incoming
|| cum
->prototype
)
11125 cum
->nargs_prototype
= n_named_args
;
11127 /* Check for a longcall attribute. */
11128 if ((!fntype
&& rs6000_default_long_calls
)
11130 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
11131 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
11132 cum
->call_cookie
|= CALL_LONG
;
11134 if (TARGET_DEBUG_ARG
)
11136 fprintf (stderr
, "\ninit_cumulative_args:");
11139 tree ret_type
= TREE_TYPE (fntype
);
11140 fprintf (stderr
, " ret code = %s,",
11141 get_tree_code_name (TREE_CODE (ret_type
)));
11144 if (cum
->call_cookie
& CALL_LONG
)
11145 fprintf (stderr
, " longcall,");
11147 fprintf (stderr
, " proto = %d, nargs = %d\n",
11148 cum
->prototype
, cum
->nargs_prototype
);
11151 #ifdef HAVE_AS_GNU_ATTRIBUTE
11152 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
))
11154 cum
->escapes
= call_ABI_of_interest (fndecl
);
11161 return_type
= TREE_TYPE (fntype
);
11162 return_mode
= TYPE_MODE (return_type
);
11165 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
11167 if (return_type
!= NULL
)
11169 if (TREE_CODE (return_type
) == RECORD_TYPE
11170 && TYPE_TRANSPARENT_AGGR (return_type
))
11172 return_type
= TREE_TYPE (first_field (return_type
));
11173 return_mode
= TYPE_MODE (return_type
);
11175 if (AGGREGATE_TYPE_P (return_type
)
11176 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
11178 rs6000_returns_struct
= true;
11180 if (SCALAR_FLOAT_MODE_P (return_mode
))
11182 rs6000_passes_float
= true;
11183 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
11184 && (FLOAT128_IBM_P (return_mode
)
11185 || FLOAT128_IEEE_P (return_mode
)
11186 || (return_type
!= NULL
11187 && (TYPE_MAIN_VARIANT (return_type
)
11188 == long_double_type_node
))))
11189 rs6000_passes_long_double
= true;
11191 if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
11192 || SPE_VECTOR_MODE (return_mode
))
11193 rs6000_passes_vector
= true;
11200 && TARGET_ALTIVEC_ABI
11201 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
11203 error ("cannot return value in vector register because"
11204 " altivec instructions are disabled, use -maltivec"
11205 " to enable them");
11209 /* The mode the ABI uses for a word. This is not the same as word_mode
11210 for -m32 -mpowerpc64. This is used to implement various target hooks. */
11212 static machine_mode
11213 rs6000_abi_word_mode (void)
11215 return TARGET_32BIT
? SImode
: DImode
;
11218 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
11220 rs6000_offload_options (void)
11223 return xstrdup ("-foffload-abi=lp64");
11225 return xstrdup ("-foffload-abi=ilp32");
11228 /* On rs6000, function arguments are promoted, as are function return
11231 static machine_mode
11232 rs6000_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
11234 int *punsignedp ATTRIBUTE_UNUSED
,
11237 PROMOTE_MODE (mode
, *punsignedp
, type
);
11242 /* Return true if TYPE must be passed on the stack and not in registers. */
11245 rs6000_must_pass_in_stack (machine_mode mode
, const_tree type
)
11247 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
11248 return must_pass_in_stack_var_size (mode
, type
);
11250 return must_pass_in_stack_var_size_or_pad (mode
, type
);
11254 is_complex_IBM_long_double (machine_mode mode
)
11256 return mode
== ICmode
|| (!TARGET_IEEEQUAD
&& mode
== TCmode
);
11259 /* Whether ABI_V4 passes MODE args to a function in floating point
11263 abi_v4_pass_in_fpr (machine_mode mode
)
11265 if (!TARGET_FPRS
|| !TARGET_HARD_FLOAT
)
11267 if (TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
11269 if (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
11271 /* ABI_V4 passes complex IBM long double in 8 gprs.
11272 Stupid, but we can't change the ABI now. */
11273 if (is_complex_IBM_long_double (mode
))
11275 if (FLOAT128_2REG_P (mode
))
11277 if (DECIMAL_FLOAT_MODE_P (mode
))
11282 /* If defined, a C expression which determines whether, and in which
11283 direction, to pad out an argument with extra space. The value
11284 should be of type `enum direction': either `upward' to pad above
11285 the argument, `downward' to pad below, or `none' to inhibit
11288 For the AIX ABI structs are always stored left shifted in their
11292 function_arg_padding (machine_mode mode
, const_tree type
)
11294 #ifndef AGGREGATE_PADDING_FIXED
11295 #define AGGREGATE_PADDING_FIXED 0
11297 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
11298 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
11301 if (!AGGREGATE_PADDING_FIXED
)
11303 /* GCC used to pass structures of the same size as integer types as
11304 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
11305 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
11306 passed padded downward, except that -mstrict-align further
11307 muddied the water in that multi-component structures of 2 and 4
11308 bytes in size were passed padded upward.
11310 The following arranges for best compatibility with previous
11311 versions of gcc, but removes the -mstrict-align dependency. */
11312 if (BYTES_BIG_ENDIAN
)
11314 HOST_WIDE_INT size
= 0;
11316 if (mode
== BLKmode
)
11318 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
11319 size
= int_size_in_bytes (type
);
11322 size
= GET_MODE_SIZE (mode
);
11324 if (size
== 1 || size
== 2 || size
== 4)
11330 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
11332 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
11336 /* Fall back to the default. */
11337 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
11340 /* If defined, a C expression that gives the alignment boundary, in bits,
11341 of an argument with the specified mode and type. If it is not defined,
11342 PARM_BOUNDARY is used for all arguments.
11344 V.4 wants long longs and doubles to be double word aligned. Just
11345 testing the mode size is a boneheaded way to do this as it means
11346 that other types such as complex int are also double word aligned.
11347 However, we're stuck with this because changing the ABI might break
11348 existing library interfaces.
11350 Doubleword align SPE vectors.
11351 Quadword align Altivec/VSX vectors.
11352 Quadword align large synthetic vector types. */
11354 static unsigned int
11355 rs6000_function_arg_boundary (machine_mode mode
, const_tree type
)
11357 machine_mode elt_mode
;
11360 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11362 if (DEFAULT_ABI
== ABI_V4
11363 && (GET_MODE_SIZE (mode
) == 8
11364 || (TARGET_HARD_FLOAT
11366 && !is_complex_IBM_long_double (mode
)
11367 && FLOAT128_2REG_P (mode
))))
11369 else if (FLOAT128_VECTOR_P (mode
))
11371 else if (SPE_VECTOR_MODE (mode
)
11372 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11373 && int_size_in_bytes (type
) >= 8
11374 && int_size_in_bytes (type
) < 16))
11376 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
11377 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11378 && int_size_in_bytes (type
) >= 16))
11381 /* Aggregate types that need > 8 byte alignment are quadword-aligned
11382 in the parameter area in the ELFv2 ABI, and in the AIX ABI unless
11383 -mcompat-align-parm is used. */
11384 if (((DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
)
11385 || DEFAULT_ABI
== ABI_ELFv2
)
11386 && type
&& TYPE_ALIGN (type
) > 64)
11388 /* "Aggregate" means any AGGREGATE_TYPE except for single-element
11389 or homogeneous float/vector aggregates here. We already handled
11390 vector aggregates above, but still need to check for float here. */
11391 bool aggregate_p
= (AGGREGATE_TYPE_P (type
)
11392 && !SCALAR_FLOAT_MODE_P (elt_mode
));
11394 /* We used to check for BLKmode instead of the above aggregate type
11395 check. Warn when this results in any difference to the ABI. */
11396 if (aggregate_p
!= (mode
== BLKmode
))
11398 static bool warned
;
11399 if (!warned
&& warn_psabi
)
11402 inform (input_location
,
11403 "the ABI of passing aggregates with %d-byte alignment"
11404 " has changed in GCC 5",
11405 (int) TYPE_ALIGN (type
) / BITS_PER_UNIT
);
11413 /* Similar for the Darwin64 ABI. Note that for historical reasons we
11414 implement the "aggregate type" check as a BLKmode check here; this
11415 means certain aggregate types are in fact not aligned. */
11416 if (TARGET_MACHO
&& rs6000_darwin64_abi
11418 && type
&& TYPE_ALIGN (type
) > 64)
11421 return PARM_BOUNDARY
;
11424 /* The offset in words to the start of the parameter save area. */
11426 static unsigned int
11427 rs6000_parm_offset (void)
11429 return (DEFAULT_ABI
== ABI_V4
? 2
11430 : DEFAULT_ABI
== ABI_ELFv2
? 4
11434 /* For a function parm of MODE and TYPE, return the starting word in
11435 the parameter area. NWORDS of the parameter area are already used. */
11437 static unsigned int
11438 rs6000_parm_start (machine_mode mode
, const_tree type
,
11439 unsigned int nwords
)
11441 unsigned int align
;
11443 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
11444 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
11447 /* Compute the size (in words) of a function argument. */
11449 static unsigned long
11450 rs6000_arg_size (machine_mode mode
, const_tree type
)
11452 unsigned long size
;
11454 if (mode
!= BLKmode
)
11455 size
= GET_MODE_SIZE (mode
);
11457 size
= int_size_in_bytes (type
);
11460 return (size
+ 3) >> 2;
11462 return (size
+ 7) >> 3;
11465 /* Use this to flush pending int fields. */
11468 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
11469 HOST_WIDE_INT bitpos
, int final
)
11471 unsigned int startbit
, endbit
;
11472 int intregs
, intoffset
;
11475 /* Handle the situations where a float is taking up the first half
11476 of the GPR, and the other half is empty (typically due to
11477 alignment restrictions). We can detect this by a 8-byte-aligned
11478 int field, or by seeing that this is the final flush for this
11479 argument. Count the word and continue on. */
11480 if (cum
->floats_in_gpr
== 1
11481 && (cum
->intoffset
% 64 == 0
11482 || (cum
->intoffset
== -1 && final
)))
11485 cum
->floats_in_gpr
= 0;
11488 if (cum
->intoffset
== -1)
11491 intoffset
= cum
->intoffset
;
11492 cum
->intoffset
= -1;
11493 cum
->floats_in_gpr
= 0;
11495 if (intoffset
% BITS_PER_WORD
!= 0)
11497 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
11499 if (mode
== BLKmode
)
11501 /* We couldn't find an appropriate mode, which happens,
11502 e.g., in packed structs when there are 3 bytes to load.
11503 Back intoffset back to the beginning of the word in this
11505 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11509 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11510 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11511 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11512 cum
->words
+= intregs
;
11513 /* words should be unsigned. */
11514 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
11516 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
11521 /* The darwin64 ABI calls for us to recurse down through structs,
11522 looking for elements passed in registers. Unfortunately, we have
11523 to track int register count here also because of misalignments
11524 in powerpc alignment mode. */
11527 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
11529 HOST_WIDE_INT startbitpos
)
11533 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
11534 if (TREE_CODE (f
) == FIELD_DECL
)
11536 HOST_WIDE_INT bitpos
= startbitpos
;
11537 tree ftype
= TREE_TYPE (f
);
11539 if (ftype
== error_mark_node
)
11541 mode
= TYPE_MODE (ftype
);
11543 if (DECL_SIZE (f
) != 0
11544 && tree_fits_uhwi_p (bit_position (f
)))
11545 bitpos
+= int_bit_position (f
);
11547 /* ??? FIXME: else assume zero offset. */
11549 if (TREE_CODE (ftype
) == RECORD_TYPE
)
11550 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
11551 else if (USE_FP_FOR_ARG_P (cum
, mode
))
11553 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
11554 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11555 cum
->fregno
+= n_fpregs
;
11556 /* Single-precision floats present a special problem for
11557 us, because they are smaller than an 8-byte GPR, and so
11558 the structure-packing rules combined with the standard
11559 varargs behavior mean that we want to pack float/float
11560 and float/int combinations into a single register's
11561 space. This is complicated by the arg advance flushing,
11562 which works on arbitrarily large groups of int-type
11564 if (mode
== SFmode
)
11566 if (cum
->floats_in_gpr
== 1)
11568 /* Two floats in a word; count the word and reset
11569 the float count. */
11571 cum
->floats_in_gpr
= 0;
11573 else if (bitpos
% 64 == 0)
11575 /* A float at the beginning of an 8-byte word;
11576 count it and put off adjusting cum->words until
11577 we see if a arg advance flush is going to do it
11579 cum
->floats_in_gpr
++;
11583 /* The float is at the end of a word, preceded
11584 by integer fields, so the arg advance flush
11585 just above has already set cum->words and
11586 everything is taken care of. */
11590 cum
->words
+= n_fpregs
;
11592 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
11594 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
11598 else if (cum
->intoffset
== -1)
11599 cum
->intoffset
= bitpos
;
11603 /* Check for an item that needs to be considered specially under the darwin 64
11604 bit ABI. These are record types where the mode is BLK or the structure is
11605 8 bytes in size. */
11607 rs6000_darwin64_struct_check_p (machine_mode mode
, const_tree type
)
11609 return rs6000_darwin64_abi
11610 && ((mode
== BLKmode
11611 && TREE_CODE (type
) == RECORD_TYPE
11612 && int_size_in_bytes (type
) > 0)
11613 || (type
&& TREE_CODE (type
) == RECORD_TYPE
11614 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
11617 /* Update the data in CUM to advance over an argument
11618 of mode MODE and data type TYPE.
11619 (TYPE is null for libcalls where that information may not be available.)
11621 Note that for args passed by reference, function_arg will be called
11622 with MODE and TYPE set to that of the pointer to the arg, not the arg
11626 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, machine_mode mode
,
11627 const_tree type
, bool named
, int depth
)
11629 machine_mode elt_mode
;
11632 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
11634 /* Only tick off an argument if we're not recursing. */
11636 cum
->nargs_prototype
--;
11638 #ifdef HAVE_AS_GNU_ATTRIBUTE
11639 if (TARGET_ELF
&& (TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
11642 if (SCALAR_FLOAT_MODE_P (mode
))
11644 rs6000_passes_float
= true;
11645 if ((HAVE_LD_PPC_GNU_ATTR_LONG_DOUBLE
|| TARGET_64BIT
)
11646 && (FLOAT128_IBM_P (mode
)
11647 || FLOAT128_IEEE_P (mode
)
11649 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
)))
11650 rs6000_passes_long_double
= true;
11652 if ((named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
11653 || (SPE_VECTOR_MODE (mode
)
11655 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
))
11656 rs6000_passes_vector
= true;
11660 if (TARGET_ALTIVEC_ABI
11661 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
11662 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
11663 && int_size_in_bytes (type
) == 16)))
11665 bool stack
= false;
11667 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
11669 cum
->vregno
+= n_elts
;
11671 if (!TARGET_ALTIVEC
)
11672 error ("cannot pass argument in vector register because"
11673 " altivec instructions are disabled, use -maltivec"
11674 " to enable them");
11676 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
11677 even if it is going to be passed in a vector register.
11678 Darwin does the same for variable-argument functions. */
11679 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
11681 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
11691 /* Vector parameters must be 16-byte aligned. In 32-bit
11692 mode this means we need to take into account the offset
11693 to the parameter save area. In 64-bit mode, they just
11694 have to start on an even word, since the parameter save
11695 area is 16-byte aligned. */
11697 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
11699 align
= cum
->words
& 1;
11700 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
11702 if (TARGET_DEBUG_ARG
)
11704 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
11705 cum
->words
, align
);
11706 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
11707 cum
->nargs_prototype
, cum
->prototype
,
11708 GET_MODE_NAME (mode
));
11712 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
11714 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
11715 cum
->sysv_gregno
++;
11717 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
11719 int size
= int_size_in_bytes (type
);
11720 /* Variable sized types have size == -1 and are
11721 treated as if consisting entirely of ints.
11722 Pad to 16 byte boundary if needed. */
11723 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
11724 && (cum
->words
% 2) != 0)
11726 /* For varargs, we can just go up by the size of the struct. */
11728 cum
->words
+= (size
+ 7) / 8;
11731 /* It is tempting to say int register count just goes up by
11732 sizeof(type)/8, but this is wrong in a case such as
11733 { int; double; int; } [powerpc alignment]. We have to
11734 grovel through the fields for these too. */
11735 cum
->intoffset
= 0;
11736 cum
->floats_in_gpr
= 0;
11737 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
11738 rs6000_darwin64_record_arg_advance_flush (cum
,
11739 size
* BITS_PER_UNIT
, 1);
11741 if (TARGET_DEBUG_ARG
)
11743 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
11744 cum
->words
, TYPE_ALIGN (type
), size
);
11746 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
11747 cum
->nargs_prototype
, cum
->prototype
,
11748 GET_MODE_NAME (mode
));
11751 else if (DEFAULT_ABI
== ABI_V4
)
11753 if (abi_v4_pass_in_fpr (mode
))
11755 /* _Decimal128 must use an even/odd register pair. This assumes
11756 that the register number is odd when fregno is odd. */
11757 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11760 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
11761 <= FP_ARG_V4_MAX_REG
)
11762 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
11765 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
11766 if (mode
== DFmode
|| FLOAT128_IBM_P (mode
)
11767 || mode
== DDmode
|| mode
== TDmode
)
11768 cum
->words
+= cum
->words
& 1;
11769 cum
->words
+= rs6000_arg_size (mode
, type
);
11774 int n_words
= rs6000_arg_size (mode
, type
);
11775 int gregno
= cum
->sysv_gregno
;
11777 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
11778 (r7,r8) or (r9,r10). As does any other 2 word item such
11779 as complex int due to a historical mistake. */
11781 gregno
+= (1 - gregno
) & 1;
11783 /* Multi-reg args are not split between registers and stack. */
11784 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11786 /* Long long and SPE vectors are aligned on the stack.
11787 So are other 2 word items such as complex int due to
11788 a historical mistake. */
11790 cum
->words
+= cum
->words
& 1;
11791 cum
->words
+= n_words
;
11794 /* Note: continuing to accumulate gregno past when we've started
11795 spilling to the stack indicates the fact that we've started
11796 spilling to the stack to expand_builtin_saveregs. */
11797 cum
->sysv_gregno
= gregno
+ n_words
;
11800 if (TARGET_DEBUG_ARG
)
11802 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11803 cum
->words
, cum
->fregno
);
11804 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
11805 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
11806 fprintf (stderr
, "mode = %4s, named = %d\n",
11807 GET_MODE_NAME (mode
), named
);
11812 int n_words
= rs6000_arg_size (mode
, type
);
11813 int start_words
= cum
->words
;
11814 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
11816 cum
->words
= align_words
+ n_words
;
11818 if (SCALAR_FLOAT_MODE_P (elt_mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
11820 /* _Decimal128 must be passed in an even/odd float register pair.
11821 This assumes that the register number is odd when fregno is
11823 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
11825 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
11828 if (TARGET_DEBUG_ARG
)
11830 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
11831 cum
->words
, cum
->fregno
);
11832 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
11833 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
11834 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
11835 named
, align_words
- start_words
, depth
);
11841 rs6000_function_arg_advance (cumulative_args_t cum
, machine_mode mode
,
11842 const_tree type
, bool named
)
11844 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
11849 spe_build_register_parallel (machine_mode mode
, int gregno
)
11851 rtx r1
, r3
, r5
, r7
;
11856 r1
= gen_rtx_REG (DImode
, gregno
);
11857 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
11858 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
11862 r1
= gen_rtx_REG (DImode
, gregno
);
11863 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
11864 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
11865 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
11866 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
11869 r1
= gen_rtx_REG (DImode
, gregno
);
11870 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
11871 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
11872 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
11873 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
11874 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
11875 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
11876 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
11877 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
11880 gcc_unreachable ();
11884 /* Determine where to put a SIMD argument on the SPE. */
11886 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, machine_mode mode
,
11889 int gregno
= cum
->sysv_gregno
;
11891 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
11892 are passed and returned in a pair of GPRs for ABI compatibility. */
11893 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
11894 || mode
== DCmode
|| mode
== TCmode
))
11896 int n_words
= rs6000_arg_size (mode
, type
);
11898 /* Doubles go in an odd/even register pair (r5/r6, etc). */
11899 if (mode
== DFmode
)
11900 gregno
+= (1 - gregno
) & 1;
11902 /* Multi-reg args are not split between registers and stack. */
11903 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
11906 return spe_build_register_parallel (mode
, gregno
);
11910 int n_words
= rs6000_arg_size (mode
, type
);
11912 /* SPE vectors are put in odd registers. */
11913 if (n_words
== 2 && (gregno
& 1) == 0)
11916 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
11919 machine_mode m
= SImode
;
11921 r1
= gen_rtx_REG (m
, gregno
);
11922 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
11923 r2
= gen_rtx_REG (m
, gregno
+ 1);
11924 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
11925 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
11932 if (gregno
<= GP_ARG_MAX_REG
)
11933 return gen_rtx_REG (mode
, gregno
);
11939 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
11940 structure between cum->intoffset and bitpos to integer registers. */
11943 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
11944 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
11947 unsigned int regno
;
11948 unsigned int startbit
, endbit
;
11949 int this_regno
, intregs
, intoffset
;
11952 if (cum
->intoffset
== -1)
11955 intoffset
= cum
->intoffset
;
11956 cum
->intoffset
= -1;
11958 /* If this is the trailing part of a word, try to only load that
11959 much into the register. Otherwise load the whole register. Note
11960 that in the latter case we may pick up unwanted bits. It's not a
11961 problem at the moment but may wish to revisit. */
11963 if (intoffset
% BITS_PER_WORD
!= 0)
11965 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
11967 if (mode
== BLKmode
)
11969 /* We couldn't find an appropriate mode, which happens,
11970 e.g., in packed structs when there are 3 bytes to load.
11971 Back intoffset back to the beginning of the word in this
11973 intoffset
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11980 startbit
= ROUND_DOWN (intoffset
, BITS_PER_WORD
);
11981 endbit
= ROUND_UP (bitpos
, BITS_PER_WORD
);
11982 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
11983 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
11985 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
11986 cum
->use_stack
= 1;
11988 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
11992 intoffset
/= BITS_PER_UNIT
;
11995 regno
= GP_ARG_MIN_REG
+ this_regno
;
11996 reg
= gen_rtx_REG (mode
, regno
);
11998 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
12001 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
12005 while (intregs
> 0);
12008 /* Recursive workhorse for the following. */
12011 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
12012 HOST_WIDE_INT startbitpos
, rtx rvec
[],
12017 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
12018 if (TREE_CODE (f
) == FIELD_DECL
)
12020 HOST_WIDE_INT bitpos
= startbitpos
;
12021 tree ftype
= TREE_TYPE (f
);
12023 if (ftype
== error_mark_node
)
12025 mode
= TYPE_MODE (ftype
);
12027 if (DECL_SIZE (f
) != 0
12028 && tree_fits_uhwi_p (bit_position (f
)))
12029 bitpos
+= int_bit_position (f
);
12031 /* ??? FIXME: else assume zero offset. */
12033 if (TREE_CODE (ftype
) == RECORD_TYPE
)
12034 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
12035 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
12037 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
12041 case SCmode
: mode
= SFmode
; break;
12042 case DCmode
: mode
= DFmode
; break;
12043 case TCmode
: mode
= TFmode
; break;
12047 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
12048 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
12050 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
12051 && (mode
== TFmode
|| mode
== TDmode
));
12052 /* Long double or _Decimal128 split over regs and memory. */
12053 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
12057 = gen_rtx_EXPR_LIST (VOIDmode
,
12058 gen_rtx_REG (mode
, cum
->fregno
++),
12059 GEN_INT (bitpos
/ BITS_PER_UNIT
));
12060 if (FLOAT128_2REG_P (mode
))
12063 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
12065 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
12067 = gen_rtx_EXPR_LIST (VOIDmode
,
12068 gen_rtx_REG (mode
, cum
->vregno
++),
12069 GEN_INT (bitpos
/ BITS_PER_UNIT
));
12071 else if (cum
->intoffset
== -1)
12072 cum
->intoffset
= bitpos
;
12076 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
12077 the register(s) to be used for each field and subfield of a struct
12078 being passed by value, along with the offset of where the
12079 register's value may be found in the block. FP fields go in FP
12080 register, vector fields go in vector registers, and everything
12081 else goes in int registers, packed as in memory.
12083 This code is also used for function return values. RETVAL indicates
12084 whether this is the case.
12086 Much of this is taken from the SPARC V9 port, which has a similar
12087 calling convention. */
12090 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
12091 bool named
, bool retval
)
12093 rtx rvec
[FIRST_PSEUDO_REGISTER
];
12094 int k
= 1, kbase
= 1;
12095 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
12096 /* This is a copy; modifications are not visible to our caller. */
12097 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
12098 CUMULATIVE_ARGS
*cum
= ©_cum
;
12100 /* Pad to 16 byte boundary if needed. */
12101 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
12102 && (cum
->words
% 2) != 0)
12105 cum
->intoffset
= 0;
12106 cum
->use_stack
= 0;
12107 cum
->named
= named
;
12109 /* Put entries into rvec[] for individual FP and vector fields, and
12110 for the chunks of memory that go in int regs. Note we start at
12111 element 1; 0 is reserved for an indication of using memory, and
12112 may or may not be filled in below. */
12113 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
12114 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
12116 /* If any part of the struct went on the stack put all of it there.
12117 This hack is because the generic code for
12118 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
12119 parts of the struct are not at the beginning. */
12120 if (cum
->use_stack
)
12123 return NULL_RTX
; /* doesn't go in registers at all */
12125 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
12127 if (k
> 1 || cum
->use_stack
)
12128 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
12133 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
12136 rs6000_mixed_function_arg (machine_mode mode
, const_tree type
,
12141 rtx rvec
[GP_ARG_NUM_REG
+ 1];
12143 if (align_words
>= GP_ARG_NUM_REG
)
12146 n_units
= rs6000_arg_size (mode
, type
);
12148 /* Optimize the simple case where the arg fits in one gpr, except in
12149 the case of BLKmode due to assign_parms assuming that registers are
12150 BITS_PER_WORD wide. */
12152 || (n_units
== 1 && mode
!= BLKmode
))
12153 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12156 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
12157 /* Not all of the arg fits in gprs. Say that it goes in memory too,
12158 using a magic NULL_RTX component.
12159 This is not strictly correct. Only some of the arg belongs in
12160 memory, not all of it. However, the normal scheme using
12161 function_arg_partial_nregs can result in unusual subregs, eg.
12162 (subreg:SI (reg:DF) 4), which are not handled well. The code to
12163 store the whole arg to memory is often more efficient than code
12164 to store pieces, and we know that space is available in the right
12165 place for the whole arg. */
12166 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
12171 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
12172 rtx off
= GEN_INT (i
++ * 4);
12173 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12175 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
12177 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
12180 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
12181 but must also be copied into the parameter save area starting at
12182 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
12183 to the GPRs and/or memory. Return the number of elements used. */
12186 rs6000_psave_function_arg (machine_mode mode
, const_tree type
,
12187 int align_words
, rtx
*rvec
)
12191 if (align_words
< GP_ARG_NUM_REG
)
12193 int n_words
= rs6000_arg_size (mode
, type
);
12195 if (align_words
+ n_words
> GP_ARG_NUM_REG
12197 || (TARGET_32BIT
&& TARGET_POWERPC64
))
12199 /* If this is partially on the stack, then we only
12200 include the portion actually in registers here. */
12201 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
12204 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
12206 /* Not all of the arg fits in gprs. Say that it goes in memory
12207 too, using a magic NULL_RTX component. Also see comment in
12208 rs6000_mixed_function_arg for why the normal
12209 function_arg_partial_nregs scheme doesn't work in this case. */
12210 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
12215 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
12216 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
12217 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12219 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
12223 /* The whole arg fits in gprs. */
12224 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12225 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
12230 /* It's entirely in memory. */
12231 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
12237 /* RVEC is a vector of K components of an argument of mode MODE.
12238 Construct the final function_arg return value from it. */
12241 rs6000_finish_function_arg (machine_mode mode
, rtx
*rvec
, int k
)
12243 gcc_assert (k
>= 1);
12245 /* Avoid returning a PARALLEL in the trivial cases. */
12248 if (XEXP (rvec
[0], 0) == NULL_RTX
)
12251 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
12252 return XEXP (rvec
[0], 0);
12255 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
12258 /* Determine where to put an argument to a function.
12259 Value is zero to push the argument on the stack,
12260 or a hard register in which to store the argument.
12262 MODE is the argument's machine mode.
12263 TYPE is the data type of the argument (as a tree).
12264 This is null for libcalls where that information may
12266 CUM is a variable of type CUMULATIVE_ARGS which gives info about
12267 the preceding args and about the function being called. It is
12268 not modified in this routine.
12269 NAMED is nonzero if this argument is a named parameter
12270 (otherwise it is an extra parameter matching an ellipsis).
12272 On RS/6000 the first eight words of non-FP are normally in registers
12273 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
12274 Under V.4, the first 8 FP args are in registers.
12276 If this is floating-point and no prototype is specified, we use
12277 both an FP and integer register (or possibly FP reg and stack). Library
12278 functions (when CALL_LIBCALL is set) always have the proper types for args,
12279 so we can pass the FP value just in one register. emit_library_function
12280 doesn't support PARALLEL anyway.
12282 Note that for args passed by reference, function_arg will be called
12283 with MODE and TYPE set to that of the pointer to the arg, not the arg
12287 rs6000_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
12288 const_tree type
, bool named
)
12290 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12291 enum rs6000_abi abi
= DEFAULT_ABI
;
12292 machine_mode elt_mode
;
12295 /* Return a marker to indicate whether CR1 needs to set or clear the
12296 bit that V.4 uses to say fp args were passed in registers.
12297 Assume that we don't need the marker for software floating point,
12298 or compiler generated library calls. */
12299 if (mode
== VOIDmode
)
12302 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
12304 || (cum
->nargs_prototype
< 0
12305 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
12307 /* For the SPE, we need to crxor CR6 always. */
12308 if (TARGET_SPE_ABI
)
12309 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
12310 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
12311 return GEN_INT (cum
->call_cookie
12312 | ((cum
->fregno
== FP_ARG_MIN_REG
)
12313 ? CALL_V4_SET_FP_ARGS
12314 : CALL_V4_CLEAR_FP_ARGS
));
12317 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
12320 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
12322 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
12324 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
12325 if (rslt
!= NULL_RTX
)
12327 /* Else fall through to usual handling. */
12330 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
12332 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
12336 /* Do we also need to pass this argument in the parameter save area?
12337 Library support functions for IEEE 128-bit are assumed to not need the
12338 value passed both in GPRs and in vector registers. */
12339 if (TARGET_64BIT
&& !cum
->prototype
12340 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
12342 int align_words
= ROUND_UP (cum
->words
, 2);
12343 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
12346 /* Describe where this argument goes in the vector registers. */
12347 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
12349 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
12350 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
12351 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12354 return rs6000_finish_function_arg (mode
, rvec
, k
);
12356 else if (TARGET_ALTIVEC_ABI
12357 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
12358 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
12359 && int_size_in_bytes (type
) == 16)))
12361 if (named
|| abi
== ABI_V4
)
12365 /* Vector parameters to varargs functions under AIX or Darwin
12366 get passed in memory and possibly also in GPRs. */
12367 int align
, align_words
, n_words
;
12368 machine_mode part_mode
;
12370 /* Vector parameters must be 16-byte aligned. In 32-bit
12371 mode this means we need to take into account the offset
12372 to the parameter save area. In 64-bit mode, they just
12373 have to start on an even word, since the parameter save
12374 area is 16-byte aligned. */
12376 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
12378 align
= cum
->words
& 1;
12379 align_words
= cum
->words
+ align
;
12381 /* Out of registers? Memory, then. */
12382 if (align_words
>= GP_ARG_NUM_REG
)
12385 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12386 return rs6000_mixed_function_arg (mode
, type
, align_words
);
12388 /* The vector value goes in GPRs. Only the part of the
12389 value in GPRs is reported here. */
12391 n_words
= rs6000_arg_size (mode
, type
);
12392 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
12393 /* Fortunately, there are only two possibilities, the value
12394 is either wholly in GPRs or half in GPRs and half not. */
12395 part_mode
= DImode
;
12397 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
12400 else if (TARGET_SPE_ABI
&& TARGET_SPE
12401 && (SPE_VECTOR_MODE (mode
)
12402 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
12405 || mode
== TCmode
))))
12406 return rs6000_spe_function_arg (cum
, mode
, type
);
12408 else if (abi
== ABI_V4
)
12410 if (abi_v4_pass_in_fpr (mode
))
12412 /* _Decimal128 must use an even/odd register pair. This assumes
12413 that the register number is odd when fregno is odd. */
12414 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
12417 if (cum
->fregno
+ (FLOAT128_2REG_P (mode
) ? 1 : 0)
12418 <= FP_ARG_V4_MAX_REG
)
12419 return gen_rtx_REG (mode
, cum
->fregno
);
12425 int n_words
= rs6000_arg_size (mode
, type
);
12426 int gregno
= cum
->sysv_gregno
;
12428 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
12429 (r7,r8) or (r9,r10). As does any other 2 word item such
12430 as complex int due to a historical mistake. */
12432 gregno
+= (1 - gregno
) & 1;
12434 /* Multi-reg args are not split between registers and stack. */
12435 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
12438 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12439 return rs6000_mixed_function_arg (mode
, type
,
12440 gregno
- GP_ARG_MIN_REG
);
12441 return gen_rtx_REG (mode
, gregno
);
12446 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
12448 /* _Decimal128 must be passed in an even/odd float register pair.
12449 This assumes that the register number is odd when fregno is odd. */
12450 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
12453 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
12455 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
12458 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
12461 /* Do we also need to pass this argument in the parameter
12463 if (type
&& (cum
->nargs_prototype
<= 0
12464 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
12465 && TARGET_XL_COMPAT
12466 && align_words
>= GP_ARG_NUM_REG
)))
12467 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
12469 /* Describe where this argument goes in the fprs. */
12470 for (i
= 0; i
< n_elts
12471 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
12473 /* Check if the argument is split over registers and memory.
12474 This can only ever happen for long double or _Decimal128;
12475 complex types are handled via split_complex_arg. */
12476 machine_mode fmode
= elt_mode
;
12477 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
12479 gcc_assert (FLOAT128_2REG_P (fmode
));
12480 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
12483 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
12484 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
12485 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12488 /* If there were not enough FPRs to hold the argument, the rest
12489 usually goes into memory. However, if the current position
12490 is still within the register parameter area, a portion may
12491 actually have to go into GPRs.
12493 Note that it may happen that the portion of the argument
12494 passed in the first "half" of the first GPR was already
12495 passed in the last FPR as well.
12497 For unnamed arguments, we already set up GPRs to cover the
12498 whole argument in rs6000_psave_function_arg, so there is
12499 nothing further to do at this point. */
12500 fpr_words
= (i
* GET_MODE_SIZE (elt_mode
)) / (TARGET_32BIT
? 4 : 8);
12501 if (i
< n_elts
&& align_words
+ fpr_words
< GP_ARG_NUM_REG
12502 && cum
->nargs_prototype
> 0)
12504 static bool warned
;
12506 machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
12507 int n_words
= rs6000_arg_size (mode
, type
);
12509 align_words
+= fpr_words
;
12510 n_words
-= fpr_words
;
12514 r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
12515 off
= GEN_INT (fpr_words
++ * GET_MODE_SIZE (rmode
));
12516 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
12518 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
12520 if (!warned
&& warn_psabi
)
12523 inform (input_location
,
12524 "the ABI of passing homogeneous float aggregates"
12525 " has changed in GCC 5");
12529 return rs6000_finish_function_arg (mode
, rvec
, k
);
12531 else if (align_words
< GP_ARG_NUM_REG
)
12533 if (TARGET_32BIT
&& TARGET_POWERPC64
)
12534 return rs6000_mixed_function_arg (mode
, type
, align_words
);
12536 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
12543 /* For an arg passed partly in registers and partly in memory, this is
12544 the number of bytes passed in registers. For args passed entirely in
12545 registers or entirely in memory, zero. When an arg is described by a
12546 PARALLEL, perhaps using more than one register type, this function
12547 returns the number of bytes used by the first element of the PARALLEL. */
12550 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
12551 tree type
, bool named
)
12553 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
12554 bool passed_in_gprs
= true;
12557 machine_mode elt_mode
;
12560 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
12562 if (DEFAULT_ABI
== ABI_V4
)
12565 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
12567 /* If we are passing this arg in the fixed parameter save area (gprs or
12568 memory) as well as VRs, we do not use the partial bytes mechanism;
12569 instead, rs6000_function_arg will return a PARALLEL including a memory
12570 element as necessary. Library support functions for IEEE 128-bit are
12571 assumed to not need the value passed both in GPRs and in vector
12573 if (TARGET_64BIT
&& !cum
->prototype
12574 && (!cum
->libcall
|| !FLOAT128_VECTOR_P (elt_mode
)))
12577 /* Otherwise, we pass in VRs only. Check for partial copies. */
12578 passed_in_gprs
= false;
12579 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
12580 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
12583 /* In this complicated case we just disable the partial_nregs code. */
12584 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
12587 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
12589 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
12591 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
12593 /* If we are passing this arg in the fixed parameter save area
12594 (gprs or memory) as well as FPRs, we do not use the partial
12595 bytes mechanism; instead, rs6000_function_arg will return a
12596 PARALLEL including a memory element as necessary. */
12598 && (cum
->nargs_prototype
<= 0
12599 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
12600 && TARGET_XL_COMPAT
12601 && align_words
>= GP_ARG_NUM_REG
)))
12604 /* Otherwise, we pass in FPRs only. Check for partial copies. */
12605 passed_in_gprs
= false;
12606 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
12608 /* Compute number of bytes / words passed in FPRs. If there
12609 is still space available in the register parameter area
12610 *after* that amount, a part of the argument will be passed
12611 in GPRs. In that case, the total amount passed in any
12612 registers is equal to the amount that would have been passed
12613 in GPRs if everything were passed there, so we fall back to
12614 the GPR code below to compute the appropriate value. */
12615 int fpr
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
12616 * MIN (8, GET_MODE_SIZE (elt_mode
)));
12617 int fpr_words
= fpr
/ (TARGET_32BIT
? 4 : 8);
12619 if (align_words
+ fpr_words
< GP_ARG_NUM_REG
)
12620 passed_in_gprs
= true;
12627 && align_words
< GP_ARG_NUM_REG
12628 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
12629 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
12631 if (ret
!= 0 && TARGET_DEBUG_ARG
)
12632 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
12637 /* A C expression that indicates when an argument must be passed by
12638 reference. If nonzero for an argument, a copy of that argument is
12639 made in memory and a pointer to the argument is passed instead of
12640 the argument itself. The pointer is passed in whatever way is
12641 appropriate for passing a pointer to that type.
12643 Under V.4, aggregates and long double are passed by reference.
12645 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
12646 reference unless the AltiVec vector extension ABI is in force.
12648 As an extension to all ABIs, variable sized types are passed by
12652 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
12653 machine_mode mode
, const_tree type
,
12654 bool named ATTRIBUTE_UNUSED
)
12659 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
12660 && FLOAT128_IEEE_P (TYPE_MODE (type
)))
12662 if (TARGET_DEBUG_ARG
)
12663 fprintf (stderr
, "function_arg_pass_by_reference: V4 IEEE 128-bit\n");
12667 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
12669 if (TARGET_DEBUG_ARG
)
12670 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
12674 if (int_size_in_bytes (type
) < 0)
12676 if (TARGET_DEBUG_ARG
)
12677 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
12681 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
12682 modes only exist for GCC vector types if -maltivec. */
12683 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
12685 if (TARGET_DEBUG_ARG
)
12686 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
12690 /* Pass synthetic vectors in memory. */
12691 if (TREE_CODE (type
) == VECTOR_TYPE
12692 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
12694 static bool warned_for_pass_big_vectors
= false;
12695 if (TARGET_DEBUG_ARG
)
12696 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
12697 if (!warned_for_pass_big_vectors
)
12699 warning (OPT_Wpsabi
, "GCC vector passed by reference: "
12700 "non-standard ABI extension with no compatibility guarantee");
12701 warned_for_pass_big_vectors
= true;
12709 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
12710 already processes. Return true if the parameter must be passed
12711 (fully or partially) on the stack. */
12714 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
12720 /* Catch errors. */
12721 if (type
== NULL
|| type
== error_mark_node
)
12724 /* Handle types with no storage requirement. */
12725 if (TYPE_MODE (type
) == VOIDmode
)
12728 /* Handle complex types. */
12729 if (TREE_CODE (type
) == COMPLEX_TYPE
)
12730 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
12731 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
12733 /* Handle transparent aggregates. */
12734 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
12735 && TYPE_TRANSPARENT_AGGR (type
))
12736 type
= TREE_TYPE (first_field (type
));
12738 /* See if this arg was passed by invisible reference. */
12739 if (pass_by_reference (get_cumulative_args (args_so_far
),
12740 TYPE_MODE (type
), type
, true))
12741 type
= build_pointer_type (type
);
12743 /* Find mode as it is passed by the ABI. */
12744 unsignedp
= TYPE_UNSIGNED (type
);
12745 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
12747 /* If we must pass in stack, we need a stack. */
12748 if (rs6000_must_pass_in_stack (mode
, type
))
12751 /* If there is no incoming register, we need a stack. */
12752 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
12753 if (entry_parm
== NULL
)
12756 /* Likewise if we need to pass both in registers and on the stack. */
12757 if (GET_CODE (entry_parm
) == PARALLEL
12758 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
12761 /* Also true if we're partially in registers and partially not. */
12762 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
12765 /* Update info on where next arg arrives in registers. */
12766 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
12770 /* Return true if FUN has no prototype, has a variable argument
12771 list, or passes any parameter in memory. */
12774 rs6000_function_parms_need_stack (tree fun
, bool incoming
)
12776 tree fntype
, result
;
12777 CUMULATIVE_ARGS args_so_far_v
;
12778 cumulative_args_t args_so_far
;
12781 /* Must be a libcall, all of which only use reg parms. */
12786 fntype
= TREE_TYPE (fun
);
12788 /* Varargs functions need the parameter save area. */
12789 if ((!incoming
&& !prototype_p (fntype
)) || stdarg_p (fntype
))
12792 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fntype
, NULL_RTX
);
12793 args_so_far
= pack_cumulative_args (&args_so_far_v
);
12795 /* When incoming, we will have been passed the function decl.
12796 It is necessary to use the decl to handle K&R style functions,
12797 where TYPE_ARG_TYPES may not be available. */
12800 gcc_assert (DECL_P (fun
));
12801 result
= DECL_RESULT (fun
);
12804 result
= TREE_TYPE (fntype
);
12806 if (result
&& aggregate_value_p (result
, fntype
))
12808 if (!TYPE_P (result
))
12809 result
= TREE_TYPE (result
);
12810 result
= build_pointer_type (result
);
12811 rs6000_parm_needs_stack (args_so_far
, result
);
12818 for (parm
= DECL_ARGUMENTS (fun
);
12819 parm
&& parm
!= void_list_node
;
12820 parm
= TREE_CHAIN (parm
))
12821 if (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (parm
)))
12826 function_args_iterator args_iter
;
12829 FOREACH_FUNCTION_ARGS (fntype
, arg_type
, args_iter
)
12830 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
12837 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
12838 usually a constant depending on the ABI. However, in the ELFv2 ABI
12839 the register parameter area is optional when calling a function that
12840 has a prototype is scope, has no variable argument list, and passes
12841 all parameters in registers. */
12844 rs6000_reg_parm_stack_space (tree fun
, bool incoming
)
12846 int reg_parm_stack_space
;
12848 switch (DEFAULT_ABI
)
12851 reg_parm_stack_space
= 0;
12856 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12860 /* ??? Recomputing this every time is a bit expensive. Is there
12861 a place to cache this information? */
12862 if (rs6000_function_parms_need_stack (fun
, incoming
))
12863 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
12865 reg_parm_stack_space
= 0;
12869 return reg_parm_stack_space
;
12873 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
12876 machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
12881 for (i
= 0; i
< nregs
; i
++)
12883 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
12884 if (reload_completed
)
12886 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
12889 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
12890 i
* GET_MODE_SIZE (reg_mode
));
12893 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
12897 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
12901 /* Perform any needed actions needed for a function that is receiving a
12902 variable number of arguments.
12906 MODE and TYPE are the mode and type of the current parameter.
12908 PRETEND_SIZE is a variable that should be set to the amount of stack
12909 that must be pushed by the prolog to pretend that our caller pushed
12912 Normally, this macro will push all remaining incoming registers on the
12913 stack and set PRETEND_SIZE to the length of the registers pushed. */
12916 setup_incoming_varargs (cumulative_args_t cum
, machine_mode mode
,
12917 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
12920 CUMULATIVE_ARGS next_cum
;
12921 int reg_size
= TARGET_32BIT
? 4 : 8;
12922 rtx save_area
= NULL_RTX
, mem
;
12923 int first_reg_offset
;
12924 alias_set_type set
;
12926 /* Skip the last named argument. */
12927 next_cum
= *get_cumulative_args (cum
);
12928 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
12930 if (DEFAULT_ABI
== ABI_V4
)
12932 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
12936 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
12937 HOST_WIDE_INT offset
= 0;
12939 /* Try to optimize the size of the varargs save area.
12940 The ABI requires that ap.reg_save_area is doubleword
12941 aligned, but we don't need to allocate space for all
12942 the bytes, only those to which we actually will save
12944 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
12945 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
12946 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
12947 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
12948 && cfun
->va_list_fpr_size
)
12951 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
12952 * UNITS_PER_FP_WORD
;
12953 if (cfun
->va_list_fpr_size
12954 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
12955 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
12957 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
12958 * UNITS_PER_FP_WORD
;
12962 offset
= -((first_reg_offset
* reg_size
) & ~7);
12963 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
12965 gpr_reg_num
= cfun
->va_list_gpr_size
;
12966 if (reg_size
== 4 && (first_reg_offset
& 1))
12969 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
12972 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
12973 * UNITS_PER_FP_WORD
12974 - (int) (GP_ARG_NUM_REG
* reg_size
);
12976 if (gpr_size
+ fpr_size
)
12979 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
12980 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
12981 reg_save_area
= XEXP (reg_save_area
, 0);
12982 if (GET_CODE (reg_save_area
) == PLUS
)
12984 gcc_assert (XEXP (reg_save_area
, 0)
12985 == virtual_stack_vars_rtx
);
12986 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
12987 offset
+= INTVAL (XEXP (reg_save_area
, 1));
12990 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
12993 cfun
->machine
->varargs_save_offset
= offset
;
12994 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
12999 first_reg_offset
= next_cum
.words
;
13000 save_area
= crtl
->args
.internal_arg_pointer
;
13002 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
13003 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
13006 set
= get_varargs_alias_set ();
13007 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
13008 && cfun
->va_list_gpr_size
)
13010 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
13012 if (va_list_gpr_counter_field
)
13013 /* V4 va_list_gpr_size counts number of registers needed. */
13014 n_gpr
= cfun
->va_list_gpr_size
;
13016 /* char * va_list instead counts number of bytes needed. */
13017 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
13022 mem
= gen_rtx_MEM (BLKmode
,
13023 plus_constant (Pmode
, save_area
,
13024 first_reg_offset
* reg_size
));
13025 MEM_NOTRAP_P (mem
) = 1;
13026 set_mem_alias_set (mem
, set
);
13027 set_mem_align (mem
, BITS_PER_WORD
);
13029 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
13033 /* Save FP registers if needed. */
13034 if (DEFAULT_ABI
== ABI_V4
13035 && TARGET_HARD_FLOAT
&& TARGET_FPRS
13037 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
13038 && cfun
->va_list_fpr_size
)
13040 int fregno
= next_cum
.fregno
, nregs
;
13041 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
13042 rtx lab
= gen_label_rtx ();
13043 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
13044 * UNITS_PER_FP_WORD
);
13047 (gen_rtx_SET (pc_rtx
,
13048 gen_rtx_IF_THEN_ELSE (VOIDmode
,
13049 gen_rtx_NE (VOIDmode
, cr1
,
13051 gen_rtx_LABEL_REF (VOIDmode
, lab
),
13055 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
13056 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
13058 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
13060 plus_constant (Pmode
, save_area
, off
));
13061 MEM_NOTRAP_P (mem
) = 1;
13062 set_mem_alias_set (mem
, set
);
13063 set_mem_align (mem
, GET_MODE_ALIGNMENT (
13064 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
13065 ? DFmode
: SFmode
));
13066 emit_move_insn (mem
, gen_rtx_REG (
13067 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
13068 ? DFmode
: SFmode
, fregno
));
13075 /* Create the va_list data type. */
13078 rs6000_build_builtin_va_list (void)
13080 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
13082 /* For AIX, prefer 'char *' because that's what the system
13083 header files like. */
13084 if (DEFAULT_ABI
!= ABI_V4
)
13085 return build_pointer_type (char_type_node
);
13087 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
13088 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
13089 get_identifier ("__va_list_tag"), record
);
13091 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
13092 unsigned_char_type_node
);
13093 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
13094 unsigned_char_type_node
);
13095 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
13096 every user file. */
13097 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
13098 get_identifier ("reserved"), short_unsigned_type_node
);
13099 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
13100 get_identifier ("overflow_arg_area"),
13102 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
13103 get_identifier ("reg_save_area"),
13106 va_list_gpr_counter_field
= f_gpr
;
13107 va_list_fpr_counter_field
= f_fpr
;
13109 DECL_FIELD_CONTEXT (f_gpr
) = record
;
13110 DECL_FIELD_CONTEXT (f_fpr
) = record
;
13111 DECL_FIELD_CONTEXT (f_res
) = record
;
13112 DECL_FIELD_CONTEXT (f_ovf
) = record
;
13113 DECL_FIELD_CONTEXT (f_sav
) = record
;
13115 TYPE_STUB_DECL (record
) = type_decl
;
13116 TYPE_NAME (record
) = type_decl
;
13117 TYPE_FIELDS (record
) = f_gpr
;
13118 DECL_CHAIN (f_gpr
) = f_fpr
;
13119 DECL_CHAIN (f_fpr
) = f_res
;
13120 DECL_CHAIN (f_res
) = f_ovf
;
13121 DECL_CHAIN (f_ovf
) = f_sav
;
13123 layout_type (record
);
13125 /* The correct type is an array type of one element. */
13126 return build_array_type (record
, build_index_type (size_zero_node
));
13129 /* Implement va_start. */
13132 rs6000_va_start (tree valist
, rtx nextarg
)
13134 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
13135 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
13136 tree gpr
, fpr
, ovf
, sav
, t
;
13138 /* Only SVR4 needs something special. */
13139 if (DEFAULT_ABI
!= ABI_V4
)
13141 std_expand_builtin_va_start (valist
, nextarg
);
13145 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
13146 f_fpr
= DECL_CHAIN (f_gpr
);
13147 f_res
= DECL_CHAIN (f_fpr
);
13148 f_ovf
= DECL_CHAIN (f_res
);
13149 f_sav
= DECL_CHAIN (f_ovf
);
13151 valist
= build_simple_mem_ref (valist
);
13152 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
13153 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
13155 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
13157 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
13160 /* Count number of gp and fp argument registers used. */
13161 words
= crtl
->args
.info
.words
;
13162 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
13164 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
13167 if (TARGET_DEBUG_ARG
)
13168 fprintf (stderr
, "va_start: words = " HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
13169 HOST_WIDE_INT_PRINT_DEC
", n_fpr = " HOST_WIDE_INT_PRINT_DEC
"\n",
13170 words
, n_gpr
, n_fpr
);
13172 if (cfun
->va_list_gpr_size
)
13174 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
13175 build_int_cst (NULL_TREE
, n_gpr
));
13176 TREE_SIDE_EFFECTS (t
) = 1;
13177 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
13180 if (cfun
->va_list_fpr_size
)
13182 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
13183 build_int_cst (NULL_TREE
, n_fpr
));
13184 TREE_SIDE_EFFECTS (t
) = 1;
13185 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
13187 #ifdef HAVE_AS_GNU_ATTRIBUTE
13188 if (call_ABI_of_interest (cfun
->decl
))
13189 rs6000_passes_float
= true;
13193 /* Find the overflow area. */
13194 t
= make_tree (TREE_TYPE (ovf
), crtl
->args
.internal_arg_pointer
);
13196 t
= fold_build_pointer_plus_hwi (t
, words
* MIN_UNITS_PER_WORD
);
13197 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
13198 TREE_SIDE_EFFECTS (t
) = 1;
13199 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
13201 /* If there were no va_arg invocations, don't set up the register
13203 if (!cfun
->va_list_gpr_size
13204 && !cfun
->va_list_fpr_size
13205 && n_gpr
< GP_ARG_NUM_REG
13206 && n_fpr
< FP_ARG_V4_MAX_REG
)
13209 /* Find the register save area. */
13210 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
13211 if (cfun
->machine
->varargs_save_offset
)
13212 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
13213 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
13214 TREE_SIDE_EFFECTS (t
) = 1;
13215 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
13218 /* Implement va_arg. */
13221 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
13222 gimple_seq
*post_p
)
13224 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
13225 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
13226 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
13227 tree lab_false
, lab_over
, addr
;
13229 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
13233 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
13235 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
13236 return build_va_arg_indirect_ref (t
);
13239 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
13240 earlier version of gcc, with the property that it always applied alignment
13241 adjustments to the va-args (even for zero-sized types). The cheapest way
13242 to deal with this is to replicate the effect of the part of
13243 std_gimplify_va_arg_expr that carries out the align adjust, for the case
13245 We don't need to check for pass-by-reference because of the test above.
13246 We can return a simplifed answer, since we know there's no offset to add. */
13249 && rs6000_darwin64_abi
)
13250 || DEFAULT_ABI
== ABI_ELFv2
13251 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
13252 && integer_zerop (TYPE_SIZE (type
)))
13254 unsigned HOST_WIDE_INT align
, boundary
;
13255 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
13256 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
13257 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
13258 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
13259 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
13260 boundary
/= BITS_PER_UNIT
;
13261 if (boundary
> align
)
13264 /* This updates arg ptr by the amount that would be necessary
13265 to align the zero-sized (but not zero-alignment) item. */
13266 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
13267 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
13268 gimplify_and_add (t
, pre_p
);
13270 t
= fold_convert (sizetype
, valist_tmp
);
13271 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
13272 fold_convert (TREE_TYPE (valist
),
13273 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
13274 size_int (-boundary
))));
13275 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
13276 gimplify_and_add (t
, pre_p
);
13278 /* Since it is zero-sized there's no increment for the item itself. */
13279 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
13280 return build_va_arg_indirect_ref (valist_tmp
);
13283 if (DEFAULT_ABI
!= ABI_V4
)
13285 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
13287 tree elem_type
= TREE_TYPE (type
);
13288 machine_mode elem_mode
= TYPE_MODE (elem_type
);
13289 int elem_size
= GET_MODE_SIZE (elem_mode
);
13291 if (elem_size
< UNITS_PER_WORD
)
13293 tree real_part
, imag_part
;
13294 gimple_seq post
= NULL
;
13296 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
13298 /* Copy the value into a temporary, lest the formal temporary
13299 be reused out from under us. */
13300 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
13301 gimple_seq_add_seq (pre_p
, post
);
13303 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
13306 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
13310 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
13313 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
13314 f_fpr
= DECL_CHAIN (f_gpr
);
13315 f_res
= DECL_CHAIN (f_fpr
);
13316 f_ovf
= DECL_CHAIN (f_res
);
13317 f_sav
= DECL_CHAIN (f_ovf
);
13319 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
13320 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
13322 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
13324 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
13327 size
= int_size_in_bytes (type
);
13328 rsize
= (size
+ 3) / 4;
13331 machine_mode mode
= TYPE_MODE (type
);
13332 if (abi_v4_pass_in_fpr (mode
))
13334 /* FP args go in FP registers, if present. */
13336 n_reg
= (size
+ 7) / 8;
13337 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
13338 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
13339 if (mode
!= SFmode
&& mode
!= SDmode
)
13344 /* Otherwise into GP registers. */
13353 /* Pull the value out of the saved registers.... */
13356 addr
= create_tmp_var (ptr_type_node
, "addr");
13358 /* AltiVec vectors never go in registers when -mabi=altivec. */
13359 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
13363 lab_false
= create_artificial_label (input_location
);
13364 lab_over
= create_artificial_label (input_location
);
13366 /* Long long and SPE vectors are aligned in the registers.
13367 As are any other 2 gpr item such as complex int due to a
13368 historical mistake. */
13370 if (n_reg
== 2 && reg
== gpr
)
13373 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
13374 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
13375 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
13376 unshare_expr (reg
), u
);
13378 /* _Decimal128 is passed in even/odd fpr pairs; the stored
13379 reg number is 0 for f1, so we want to make it odd. */
13380 else if (reg
== fpr
&& mode
== TDmode
)
13382 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
13383 build_int_cst (TREE_TYPE (reg
), 1));
13384 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
13387 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
13388 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
13389 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
13390 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
13391 gimplify_and_add (t
, pre_p
);
13395 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
13397 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
13398 build_int_cst (TREE_TYPE (reg
), n_reg
));
13399 u
= fold_convert (sizetype
, u
);
13400 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
13401 t
= fold_build_pointer_plus (t
, u
);
13403 /* _Decimal32 varargs are located in the second word of the 64-bit
13404 FP register for 32-bit binaries. */
13406 && TARGET_HARD_FLOAT
&& TARGET_FPRS
13408 t
= fold_build_pointer_plus_hwi (t
, size
);
13410 gimplify_assign (addr
, t
, pre_p
);
13412 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
13414 stmt
= gimple_build_label (lab_false
);
13415 gimple_seq_add_stmt (pre_p
, stmt
);
13417 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
13419 /* Ensure that we don't find any more args in regs.
13420 Alignment has taken care of for special cases. */
13421 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
13425 /* ... otherwise out of the overflow area. */
13427 /* Care for on-stack alignment if needed. */
13431 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
13432 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
13433 build_int_cst (TREE_TYPE (t
), -align
));
13435 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
13437 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
13439 t
= fold_build_pointer_plus_hwi (t
, size
);
13440 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
13444 stmt
= gimple_build_label (lab_over
);
13445 gimple_seq_add_stmt (pre_p
, stmt
);
13448 if (STRICT_ALIGNMENT
13449 && (TYPE_ALIGN (type
)
13450 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
13452 /* The value (of type complex double, for example) may not be
13453 aligned in memory in the saved registers, so copy via a
13454 temporary. (This is the same code as used for SPARC.) */
13455 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
13456 tree dest_addr
= build_fold_addr_expr (tmp
);
13458 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
13459 3, dest_addr
, addr
, size_int (rsize
* 4));
13461 gimplify_and_add (copy
, pre_p
);
13465 addr
= fold_convert (ptrtype
, addr
);
13466 return build_va_arg_indirect_ref (addr
);
13472 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
13475 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
13476 const char *attr_string
= "";
13478 gcc_assert (name
!= NULL
);
13479 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
13481 if (rs6000_builtin_decls
[(int)code
])
13482 fatal_error (input_location
,
13483 "internal error: builtin function %s already processed", name
);
13485 rs6000_builtin_decls
[(int)code
] = t
=
13486 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
13488 /* Set any special attributes. */
13489 if ((classify
& RS6000_BTC_CONST
) != 0)
13491 /* const function, function only depends on the inputs. */
13492 TREE_READONLY (t
) = 1;
13493 TREE_NOTHROW (t
) = 1;
13494 attr_string
= ", const";
13496 else if ((classify
& RS6000_BTC_PURE
) != 0)
13498 /* pure function, function can read global memory, but does not set any
13500 DECL_PURE_P (t
) = 1;
13501 TREE_NOTHROW (t
) = 1;
13502 attr_string
= ", pure";
13504 else if ((classify
& RS6000_BTC_FP
) != 0)
13506 /* Function is a math function. If rounding mode is on, then treat the
13507 function as not reading global memory, but it can have arbitrary side
13508 effects. If it is off, then assume the function is a const function.
13509 This mimics the ATTR_MATHFN_FPROUNDING attribute in
13510 builtin-attribute.def that is used for the math functions. */
13511 TREE_NOTHROW (t
) = 1;
13512 if (flag_rounding_math
)
13514 DECL_PURE_P (t
) = 1;
13515 DECL_IS_NOVOPS (t
) = 1;
13516 attr_string
= ", fp, pure";
13520 TREE_READONLY (t
) = 1;
13521 attr_string
= ", fp, const";
13524 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
13525 gcc_unreachable ();
13527 if (TARGET_DEBUG_BUILTIN
)
13528 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
13529 (int)code
, name
, attr_string
);
13532 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
13534 #undef RS6000_BUILTIN_0
13535 #undef RS6000_BUILTIN_1
13536 #undef RS6000_BUILTIN_2
13537 #undef RS6000_BUILTIN_3
13538 #undef RS6000_BUILTIN_A
13539 #undef RS6000_BUILTIN_D
13540 #undef RS6000_BUILTIN_E
13541 #undef RS6000_BUILTIN_H
13542 #undef RS6000_BUILTIN_P
13543 #undef RS6000_BUILTIN_Q
13544 #undef RS6000_BUILTIN_S
13545 #undef RS6000_BUILTIN_X
13547 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13548 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13549 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13550 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
13551 { MASK, ICODE, NAME, ENUM },
13553 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13554 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13555 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13556 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13557 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13558 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13559 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13560 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13562 static const struct builtin_description bdesc_3arg
[] =
13564 #include "rs6000-builtin.def"
13567 /* DST operations: void foo (void *, const int, const char). */
13569 #undef RS6000_BUILTIN_0
13570 #undef RS6000_BUILTIN_1
13571 #undef RS6000_BUILTIN_2
13572 #undef RS6000_BUILTIN_3
13573 #undef RS6000_BUILTIN_A
13574 #undef RS6000_BUILTIN_D
13575 #undef RS6000_BUILTIN_E
13576 #undef RS6000_BUILTIN_H
13577 #undef RS6000_BUILTIN_P
13578 #undef RS6000_BUILTIN_Q
13579 #undef RS6000_BUILTIN_S
13580 #undef RS6000_BUILTIN_X
13582 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13583 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13584 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13585 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13586 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13587 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
13588 { MASK, ICODE, NAME, ENUM },
13590 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13591 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13592 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13593 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13594 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13595 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13597 static const struct builtin_description bdesc_dst
[] =
13599 #include "rs6000-builtin.def"
13602 /* Simple binary operations: VECc = foo (VECa, VECb). */
13604 #undef RS6000_BUILTIN_0
13605 #undef RS6000_BUILTIN_1
13606 #undef RS6000_BUILTIN_2
13607 #undef RS6000_BUILTIN_3
13608 #undef RS6000_BUILTIN_A
13609 #undef RS6000_BUILTIN_D
13610 #undef RS6000_BUILTIN_E
13611 #undef RS6000_BUILTIN_H
13612 #undef RS6000_BUILTIN_P
13613 #undef RS6000_BUILTIN_Q
13614 #undef RS6000_BUILTIN_S
13615 #undef RS6000_BUILTIN_X
13617 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13618 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13619 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
13620 { MASK, ICODE, NAME, ENUM },
13622 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13623 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13624 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13625 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13626 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13627 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13628 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13629 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13630 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13632 static const struct builtin_description bdesc_2arg
[] =
13634 #include "rs6000-builtin.def"
13637 #undef RS6000_BUILTIN_0
13638 #undef RS6000_BUILTIN_1
13639 #undef RS6000_BUILTIN_2
13640 #undef RS6000_BUILTIN_3
13641 #undef RS6000_BUILTIN_A
13642 #undef RS6000_BUILTIN_D
13643 #undef RS6000_BUILTIN_E
13644 #undef RS6000_BUILTIN_H
13645 #undef RS6000_BUILTIN_P
13646 #undef RS6000_BUILTIN_Q
13647 #undef RS6000_BUILTIN_S
13648 #undef RS6000_BUILTIN_X
13650 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13651 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13652 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13653 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13654 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13655 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13656 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13657 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13658 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
13659 { MASK, ICODE, NAME, ENUM },
13661 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13662 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13663 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13665 /* AltiVec predicates. */
13667 static const struct builtin_description bdesc_altivec_preds
[] =
13669 #include "rs6000-builtin.def"
13672 /* SPE predicates. */
13673 #undef RS6000_BUILTIN_0
13674 #undef RS6000_BUILTIN_1
13675 #undef RS6000_BUILTIN_2
13676 #undef RS6000_BUILTIN_3
13677 #undef RS6000_BUILTIN_A
13678 #undef RS6000_BUILTIN_D
13679 #undef RS6000_BUILTIN_E
13680 #undef RS6000_BUILTIN_H
13681 #undef RS6000_BUILTIN_P
13682 #undef RS6000_BUILTIN_Q
13683 #undef RS6000_BUILTIN_S
13684 #undef RS6000_BUILTIN_X
13686 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13687 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13688 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13689 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13690 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13691 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13692 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13693 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13694 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13695 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13696 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
13697 { MASK, ICODE, NAME, ENUM },
13699 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13701 static const struct builtin_description bdesc_spe_predicates
[] =
13703 #include "rs6000-builtin.def"
13706 /* SPE evsel predicates. */
13707 #undef RS6000_BUILTIN_0
13708 #undef RS6000_BUILTIN_1
13709 #undef RS6000_BUILTIN_2
13710 #undef RS6000_BUILTIN_3
13711 #undef RS6000_BUILTIN_A
13712 #undef RS6000_BUILTIN_D
13713 #undef RS6000_BUILTIN_E
13714 #undef RS6000_BUILTIN_H
13715 #undef RS6000_BUILTIN_P
13716 #undef RS6000_BUILTIN_Q
13717 #undef RS6000_BUILTIN_S
13718 #undef RS6000_BUILTIN_X
13720 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13721 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13722 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13723 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13724 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13725 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13726 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
13727 { MASK, ICODE, NAME, ENUM },
13729 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13730 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13731 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13732 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13733 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13735 static const struct builtin_description bdesc_spe_evsel
[] =
13737 #include "rs6000-builtin.def"
13740 /* PAIRED predicates. */
13741 #undef RS6000_BUILTIN_0
13742 #undef RS6000_BUILTIN_1
13743 #undef RS6000_BUILTIN_2
13744 #undef RS6000_BUILTIN_3
13745 #undef RS6000_BUILTIN_A
13746 #undef RS6000_BUILTIN_D
13747 #undef RS6000_BUILTIN_E
13748 #undef RS6000_BUILTIN_H
13749 #undef RS6000_BUILTIN_P
13750 #undef RS6000_BUILTIN_Q
13751 #undef RS6000_BUILTIN_S
13752 #undef RS6000_BUILTIN_X
13754 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13755 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13756 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13757 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13758 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13759 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13760 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13761 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13762 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13763 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
13764 { MASK, ICODE, NAME, ENUM },
13766 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13767 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13769 static const struct builtin_description bdesc_paired_preds
[] =
13771 #include "rs6000-builtin.def"
13774 /* ABS* operations. */
13776 #undef RS6000_BUILTIN_0
13777 #undef RS6000_BUILTIN_1
13778 #undef RS6000_BUILTIN_2
13779 #undef RS6000_BUILTIN_3
13780 #undef RS6000_BUILTIN_A
13781 #undef RS6000_BUILTIN_D
13782 #undef RS6000_BUILTIN_E
13783 #undef RS6000_BUILTIN_H
13784 #undef RS6000_BUILTIN_P
13785 #undef RS6000_BUILTIN_Q
13786 #undef RS6000_BUILTIN_S
13787 #undef RS6000_BUILTIN_X
13789 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13790 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13791 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13792 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13793 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
13794 { MASK, ICODE, NAME, ENUM },
13796 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13797 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13798 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13799 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13800 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13801 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13802 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13804 static const struct builtin_description bdesc_abs
[] =
13806 #include "rs6000-builtin.def"
13809 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
13812 #undef RS6000_BUILTIN_0
13813 #undef RS6000_BUILTIN_1
13814 #undef RS6000_BUILTIN_2
13815 #undef RS6000_BUILTIN_3
13816 #undef RS6000_BUILTIN_A
13817 #undef RS6000_BUILTIN_D
13818 #undef RS6000_BUILTIN_E
13819 #undef RS6000_BUILTIN_H
13820 #undef RS6000_BUILTIN_P
13821 #undef RS6000_BUILTIN_Q
13822 #undef RS6000_BUILTIN_S
13823 #undef RS6000_BUILTIN_X
13825 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13826 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
13827 { MASK, ICODE, NAME, ENUM },
13829 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13830 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13831 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13832 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13833 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13834 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13835 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13836 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13837 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13838 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13840 static const struct builtin_description bdesc_1arg
[] =
13842 #include "rs6000-builtin.def"
13845 /* Simple no-argument operations: result = __builtin_darn_32 () */
13847 #undef RS6000_BUILTIN_0
13848 #undef RS6000_BUILTIN_1
13849 #undef RS6000_BUILTIN_2
13850 #undef RS6000_BUILTIN_3
13851 #undef RS6000_BUILTIN_A
13852 #undef RS6000_BUILTIN_D
13853 #undef RS6000_BUILTIN_E
13854 #undef RS6000_BUILTIN_H
13855 #undef RS6000_BUILTIN_P
13856 #undef RS6000_BUILTIN_Q
13857 #undef RS6000_BUILTIN_S
13858 #undef RS6000_BUILTIN_X
13860 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE) \
13861 { MASK, ICODE, NAME, ENUM },
13863 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13864 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13865 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13866 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13867 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13868 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13869 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
13870 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13871 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13872 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13873 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13875 static const struct builtin_description bdesc_0arg
[] =
13877 #include "rs6000-builtin.def"
13880 /* HTM builtins. */
13881 #undef RS6000_BUILTIN_0
13882 #undef RS6000_BUILTIN_1
13883 #undef RS6000_BUILTIN_2
13884 #undef RS6000_BUILTIN_3
13885 #undef RS6000_BUILTIN_A
13886 #undef RS6000_BUILTIN_D
13887 #undef RS6000_BUILTIN_E
13888 #undef RS6000_BUILTIN_H
13889 #undef RS6000_BUILTIN_P
13890 #undef RS6000_BUILTIN_Q
13891 #undef RS6000_BUILTIN_S
13892 #undef RS6000_BUILTIN_X
13894 #define RS6000_BUILTIN_0(ENUM, NAME, MASK, ATTR, ICODE)
13895 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
13896 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
13897 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
13898 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
13899 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
13900 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
13901 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
13902 { MASK, ICODE, NAME, ENUM },
13904 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
13905 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
13906 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
13907 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
13909 static const struct builtin_description bdesc_htm
[] =
13911 #include "rs6000-builtin.def"
13914 #undef RS6000_BUILTIN_0
13915 #undef RS6000_BUILTIN_1
13916 #undef RS6000_BUILTIN_2
13917 #undef RS6000_BUILTIN_3
13918 #undef RS6000_BUILTIN_A
13919 #undef RS6000_BUILTIN_D
13920 #undef RS6000_BUILTIN_E
13921 #undef RS6000_BUILTIN_H
13922 #undef RS6000_BUILTIN_P
13923 #undef RS6000_BUILTIN_Q
13924 #undef RS6000_BUILTIN_S
13926 /* Return true if a builtin function is overloaded. */
13928 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
13930 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
13934 rs6000_overloaded_builtin_name (enum rs6000_builtins fncode
)
13936 return rs6000_builtin_info
[(int)fncode
].name
;
13939 /* Expand an expression EXP that calls a builtin without arguments. */
13941 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
13944 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13946 if (icode
== CODE_FOR_nothing
)
13947 /* Builtin not supported on this processor. */
13951 || GET_MODE (target
) != tmode
13952 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13953 target
= gen_reg_rtx (tmode
);
13955 pat
= GEN_FCN (icode
) (target
);
13965 rs6000_expand_mtfsf_builtin (enum insn_code icode
, tree exp
)
13968 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13969 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13970 rtx op0
= expand_normal (arg0
);
13971 rtx op1
= expand_normal (arg1
);
13972 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
13973 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
13975 if (icode
== CODE_FOR_nothing
)
13976 /* Builtin not supported on this processor. */
13979 /* If we got invalid arguments bail out before generating bad rtl. */
13980 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13983 if (GET_CODE (op0
) != CONST_INT
13984 || INTVAL (op0
) > 255
13985 || INTVAL (op0
) < 0)
13987 error ("argument 1 must be an 8-bit field value");
13991 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
13992 op0
= copy_to_mode_reg (mode0
, op0
);
13994 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13995 op1
= copy_to_mode_reg (mode1
, op1
);
13997 pat
= GEN_FCN (icode
) (op0
, op1
);
14006 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
14009 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14010 rtx op0
= expand_normal (arg0
);
14011 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14012 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14014 if (icode
== CODE_FOR_nothing
)
14015 /* Builtin not supported on this processor. */
14018 /* If we got invalid arguments bail out before generating bad rtl. */
14019 if (arg0
== error_mark_node
)
14022 if (icode
== CODE_FOR_altivec_vspltisb
14023 || icode
== CODE_FOR_altivec_vspltish
14024 || icode
== CODE_FOR_altivec_vspltisw
14025 || icode
== CODE_FOR_spe_evsplatfi
14026 || icode
== CODE_FOR_spe_evsplati
)
14028 /* Only allow 5-bit *signed* literals. */
14029 if (GET_CODE (op0
) != CONST_INT
14030 || INTVAL (op0
) > 15
14031 || INTVAL (op0
) < -16)
14033 error ("argument 1 must be a 5-bit signed literal");
14039 || GET_MODE (target
) != tmode
14040 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14041 target
= gen_reg_rtx (tmode
);
14043 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14044 op0
= copy_to_mode_reg (mode0
, op0
);
14046 pat
= GEN_FCN (icode
) (target
, op0
);
14055 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
14057 rtx pat
, scratch1
, scratch2
;
14058 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14059 rtx op0
= expand_normal (arg0
);
14060 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14061 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14063 /* If we have invalid arguments, bail out before generating bad rtl. */
14064 if (arg0
== error_mark_node
)
14068 || GET_MODE (target
) != tmode
14069 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14070 target
= gen_reg_rtx (tmode
);
14072 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14073 op0
= copy_to_mode_reg (mode0
, op0
);
14075 scratch1
= gen_reg_rtx (mode0
);
14076 scratch2
= gen_reg_rtx (mode0
);
14078 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
14087 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
14090 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14091 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14092 rtx op0
= expand_normal (arg0
);
14093 rtx op1
= expand_normal (arg1
);
14094 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14095 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14096 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14098 if (icode
== CODE_FOR_nothing
)
14099 /* Builtin not supported on this processor. */
14102 /* If we got invalid arguments bail out before generating bad rtl. */
14103 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14106 if (icode
== CODE_FOR_altivec_vcfux
14107 || icode
== CODE_FOR_altivec_vcfsx
14108 || icode
== CODE_FOR_altivec_vctsxs
14109 || icode
== CODE_FOR_altivec_vctuxs
14110 || icode
== CODE_FOR_altivec_vspltb
14111 || icode
== CODE_FOR_altivec_vsplth
14112 || icode
== CODE_FOR_altivec_vspltw
14113 || icode
== CODE_FOR_spe_evaddiw
14114 || icode
== CODE_FOR_spe_evldd
14115 || icode
== CODE_FOR_spe_evldh
14116 || icode
== CODE_FOR_spe_evldw
14117 || icode
== CODE_FOR_spe_evlhhesplat
14118 || icode
== CODE_FOR_spe_evlhhossplat
14119 || icode
== CODE_FOR_spe_evlhhousplat
14120 || icode
== CODE_FOR_spe_evlwhe
14121 || icode
== CODE_FOR_spe_evlwhos
14122 || icode
== CODE_FOR_spe_evlwhou
14123 || icode
== CODE_FOR_spe_evlwhsplat
14124 || icode
== CODE_FOR_spe_evlwwsplat
14125 || icode
== CODE_FOR_spe_evrlwi
14126 || icode
== CODE_FOR_spe_evslwi
14127 || icode
== CODE_FOR_spe_evsrwis
14128 || icode
== CODE_FOR_spe_evsubifw
14129 || icode
== CODE_FOR_spe_evsrwiu
)
14131 /* Only allow 5-bit unsigned literals. */
14133 if (TREE_CODE (arg1
) != INTEGER_CST
14134 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
14136 error ("argument 2 must be a 5-bit unsigned literal");
14140 else if (icode
== CODE_FOR_dfptstsfi_eq_dd
14141 || icode
== CODE_FOR_dfptstsfi_lt_dd
14142 || icode
== CODE_FOR_dfptstsfi_gt_dd
14143 || icode
== CODE_FOR_dfptstsfi_unordered_dd
14144 || icode
== CODE_FOR_dfptstsfi_eq_td
14145 || icode
== CODE_FOR_dfptstsfi_lt_td
14146 || icode
== CODE_FOR_dfptstsfi_gt_td
14147 || icode
== CODE_FOR_dfptstsfi_unordered_td
)
14149 /* Only allow 6-bit unsigned literals. */
14151 if (TREE_CODE (arg0
) != INTEGER_CST
14152 || !IN_RANGE (TREE_INT_CST_LOW (arg0
), 0, 63))
14154 error ("argument 1 must be a 6-bit unsigned literal");
14155 return CONST0_RTX (tmode
);
14158 else if (icode
== CODE_FOR_xststdcdp
14159 || icode
== CODE_FOR_xststdcsp
14160 || icode
== CODE_FOR_xvtstdcdp
14161 || icode
== CODE_FOR_xvtstdcsp
)
14163 /* Only allow 7-bit unsigned literals. */
14165 if (TREE_CODE (arg1
) != INTEGER_CST
14166 || !IN_RANGE (TREE_INT_CST_LOW (arg1
), 0, 127))
14168 error ("argument 2 must be a 7-bit unsigned literal");
14169 return CONST0_RTX (tmode
);
14174 || GET_MODE (target
) != tmode
14175 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14176 target
= gen_reg_rtx (tmode
);
14178 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14179 op0
= copy_to_mode_reg (mode0
, op0
);
14180 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14181 op1
= copy_to_mode_reg (mode1
, op1
);
14183 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
14192 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
14195 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
14196 tree arg0
= CALL_EXPR_ARG (exp
, 1);
14197 tree arg1
= CALL_EXPR_ARG (exp
, 2);
14198 rtx op0
= expand_normal (arg0
);
14199 rtx op1
= expand_normal (arg1
);
14200 machine_mode tmode
= SImode
;
14201 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
14202 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
14205 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
14207 error ("argument 1 of __builtin_altivec_predicate must be a constant");
14211 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
14213 gcc_assert (mode0
== mode1
);
14215 /* If we have invalid arguments, bail out before generating bad rtl. */
14216 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14220 || GET_MODE (target
) != tmode
14221 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14222 target
= gen_reg_rtx (tmode
);
14224 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14225 op0
= copy_to_mode_reg (mode0
, op0
);
14226 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14227 op1
= copy_to_mode_reg (mode1
, op1
);
14229 /* Note that for many of the relevant operations (e.g. cmpne or
14230 cmpeq) with float or double operands, it makes more sense for the
14231 mode of the allocated scratch register to select a vector of
14232 integer. But the choice to copy the mode of operand 0 was made
14233 long ago and there are no plans to change it. */
14234 scratch
= gen_reg_rtx (mode0
);
14236 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
14241 /* The vec_any* and vec_all* predicates use the same opcodes for two
14242 different operations, but the bits in CR6 will be different
14243 depending on what information we want. So we have to play tricks
14244 with CR6 to get the right bits out.
14246 If you think this is disgusting, look at the specs for the
14247 AltiVec predicates. */
14249 switch (cr6_form_int
)
14252 emit_insn (gen_cr6_test_for_zero (target
));
14255 emit_insn (gen_cr6_test_for_zero_reverse (target
));
14258 emit_insn (gen_cr6_test_for_lt (target
));
14261 emit_insn (gen_cr6_test_for_lt_reverse (target
));
14264 error ("argument 1 of __builtin_altivec_predicate is out of range");
14272 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
14275 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14276 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14277 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14278 machine_mode mode0
= Pmode
;
14279 machine_mode mode1
= Pmode
;
14280 rtx op0
= expand_normal (arg0
);
14281 rtx op1
= expand_normal (arg1
);
14283 if (icode
== CODE_FOR_nothing
)
14284 /* Builtin not supported on this processor. */
14287 /* If we got invalid arguments bail out before generating bad rtl. */
14288 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14292 || GET_MODE (target
) != tmode
14293 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14294 target
= gen_reg_rtx (tmode
);
14296 op1
= copy_to_mode_reg (mode1
, op1
);
14298 if (op0
== const0_rtx
)
14300 addr
= gen_rtx_MEM (tmode
, op1
);
14304 op0
= copy_to_mode_reg (mode0
, op0
);
14305 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
14308 pat
= GEN_FCN (icode
) (target
, addr
);
14317 /* Return a constant vector for use as a little-endian permute control vector
14318 to reverse the order of elements of the given vector mode. */
14320 swap_selector_for_mode (machine_mode mode
)
14322 /* These are little endian vectors, so their elements are reversed
14323 from what you would normally expect for a permute control vector. */
14324 unsigned int swap2
[16] = {7,6,5,4,3,2,1,0,15,14,13,12,11,10,9,8};
14325 unsigned int swap4
[16] = {3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12};
14326 unsigned int swap8
[16] = {1,0,3,2,5,4,7,6,9,8,11,10,13,12,15,14};
14327 unsigned int swap16
[16] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
14328 unsigned int *swaparray
, i
;
14345 swaparray
= swap16
;
14348 gcc_unreachable ();
14351 for (i
= 0; i
< 16; ++i
)
14352 perm
[i
] = GEN_INT (swaparray
[i
]);
14354 return force_reg (V16QImode
, gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
)));
14357 /* Generate code for an "lvxl", or "lve*x" built-in for a little endian target
14358 with -maltivec=be specified. Issue the load followed by an element-
14359 reversing permute. */
14361 altivec_expand_lvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
14363 rtx tmp
= gen_reg_rtx (mode
);
14364 rtx load
= gen_rtx_SET (tmp
, op1
);
14365 rtx lvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
14366 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, load
, lvx
));
14367 rtx sel
= swap_selector_for_mode (mode
);
14368 rtx vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, tmp
, tmp
, sel
), UNSPEC_VPERM
);
14370 gcc_assert (REG_P (op0
));
14372 emit_insn (gen_rtx_SET (op0
, vperm
));
14375 /* Generate code for a "stvxl" built-in for a little endian target with
14376 -maltivec=be specified. Issue the store preceded by an element-reversing
14379 altivec_expand_stvx_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
14381 rtx tmp
= gen_reg_rtx (mode
);
14382 rtx store
= gen_rtx_SET (op0
, tmp
);
14383 rtx stvx
= gen_rtx_UNSPEC (mode
, gen_rtvec (1, const0_rtx
), unspec
);
14384 rtx par
= gen_rtx_PARALLEL (mode
, gen_rtvec (2, store
, stvx
));
14385 rtx sel
= swap_selector_for_mode (mode
);
14388 gcc_assert (REG_P (op1
));
14389 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
14390 emit_insn (gen_rtx_SET (tmp
, vperm
));
14394 /* Generate code for a "stve*x" built-in for a little endian target with -maltivec=be
14395 specified. Issue the store preceded by an element-reversing permute. */
14397 altivec_expand_stvex_be (rtx op0
, rtx op1
, machine_mode mode
, unsigned unspec
)
14399 machine_mode inner_mode
= GET_MODE_INNER (mode
);
14400 rtx tmp
= gen_reg_rtx (mode
);
14401 rtx stvx
= gen_rtx_UNSPEC (inner_mode
, gen_rtvec (1, tmp
), unspec
);
14402 rtx sel
= swap_selector_for_mode (mode
);
14405 gcc_assert (REG_P (op1
));
14406 vperm
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op1
, sel
), UNSPEC_VPERM
);
14407 emit_insn (gen_rtx_SET (tmp
, vperm
));
14408 emit_insn (gen_rtx_SET (op0
, stvx
));
14412 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
14415 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14416 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14417 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14418 machine_mode mode0
= Pmode
;
14419 machine_mode mode1
= Pmode
;
14420 rtx op0
= expand_normal (arg0
);
14421 rtx op1
= expand_normal (arg1
);
14423 if (icode
== CODE_FOR_nothing
)
14424 /* Builtin not supported on this processor. */
14427 /* If we got invalid arguments bail out before generating bad rtl. */
14428 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
14432 || GET_MODE (target
) != tmode
14433 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
14434 target
= gen_reg_rtx (tmode
);
14436 op1
= copy_to_mode_reg (mode1
, op1
);
14438 /* For LVX, express the RTL accurately by ANDing the address with -16.
14439 LVXL and LVE*X expand to use UNSPECs to hide their special behavior,
14440 so the raw address is fine. */
14441 if (icode
== CODE_FOR_altivec_lvx_v2df_2op
14442 || icode
== CODE_FOR_altivec_lvx_v2di_2op
14443 || icode
== CODE_FOR_altivec_lvx_v4sf_2op
14444 || icode
== CODE_FOR_altivec_lvx_v4si_2op
14445 || icode
== CODE_FOR_altivec_lvx_v8hi_2op
14446 || icode
== CODE_FOR_altivec_lvx_v16qi_2op
)
14449 if (op0
== const0_rtx
)
14453 op0
= copy_to_mode_reg (mode0
, op0
);
14454 rawaddr
= gen_rtx_PLUS (Pmode
, op1
, op0
);
14456 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
14457 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, addr
);
14459 /* For -maltivec=be, emit the load and follow it up with a
14460 permute to swap the elements. */
14461 if (!BYTES_BIG_ENDIAN
&& VECTOR_ELT_ORDER_BIG
)
14463 rtx temp
= gen_reg_rtx (tmode
);
14464 emit_insn (gen_rtx_SET (temp
, addr
));
14466 rtx sel
= swap_selector_for_mode (tmode
);
14467 rtx vperm
= gen_rtx_UNSPEC (tmode
, gen_rtvec (3, temp
, temp
, sel
),
14469 emit_insn (gen_rtx_SET (target
, vperm
));
14472 emit_insn (gen_rtx_SET (target
, addr
));
14476 if (op0
== const0_rtx
)
14477 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
14480 op0
= copy_to_mode_reg (mode0
, op0
);
14481 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
,
14482 gen_rtx_PLUS (Pmode
, op1
, op0
));
14485 pat
= GEN_FCN (icode
) (target
, addr
);
14495 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
14497 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14498 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14499 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14500 rtx op0
= expand_normal (arg0
);
14501 rtx op1
= expand_normal (arg1
);
14502 rtx op2
= expand_normal (arg2
);
14504 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
14505 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
14506 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
14508 /* Invalid arguments. Bail before doing anything stoopid! */
14509 if (arg0
== error_mark_node
14510 || arg1
== error_mark_node
14511 || arg2
== error_mark_node
)
14514 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
14515 op0
= copy_to_mode_reg (mode2
, op0
);
14516 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
14517 op1
= copy_to_mode_reg (mode0
, op1
);
14518 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
14519 op2
= copy_to_mode_reg (mode1
, op2
);
14521 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
14528 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
14530 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14531 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14532 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14533 rtx op0
= expand_normal (arg0
);
14534 rtx op1
= expand_normal (arg1
);
14535 rtx op2
= expand_normal (arg2
);
14537 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14538 machine_mode mode1
= Pmode
;
14539 machine_mode mode2
= Pmode
;
14541 /* Invalid arguments. Bail before doing anything stoopid! */
14542 if (arg0
== error_mark_node
14543 || arg1
== error_mark_node
14544 || arg2
== error_mark_node
)
14547 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
14548 op0
= copy_to_mode_reg (tmode
, op0
);
14550 op2
= copy_to_mode_reg (mode2
, op2
);
14552 if (op1
== const0_rtx
)
14554 addr
= gen_rtx_MEM (tmode
, op2
);
14558 op1
= copy_to_mode_reg (mode1
, op1
);
14559 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
14562 pat
= GEN_FCN (icode
) (addr
, op0
);
14569 altivec_expand_stxvl_builtin (enum insn_code icode
, tree exp
)
14572 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14573 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14574 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14575 rtx op0
= expand_normal (arg0
);
14576 rtx op1
= expand_normal (arg1
);
14577 rtx op2
= expand_normal (arg2
);
14578 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
14579 machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
14580 machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
14582 if (icode
== CODE_FOR_nothing
)
14583 /* Builtin not supported on this processor. */
14586 /* If we got invalid arguments bail out before generating bad rtl. */
14587 if (arg0
== error_mark_node
14588 || arg1
== error_mark_node
14589 || arg2
== error_mark_node
)
14592 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
14593 op0
= copy_to_mode_reg (mode0
, op0
);
14594 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
14595 op1
= copy_to_mode_reg (mode1
, op1
);
14596 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
14597 op2
= copy_to_mode_reg (mode2
, op2
);
14599 pat
= GEN_FCN (icode
) (op0
, op1
, op2
);
14607 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
14609 tree arg0
= CALL_EXPR_ARG (exp
, 0);
14610 tree arg1
= CALL_EXPR_ARG (exp
, 1);
14611 tree arg2
= CALL_EXPR_ARG (exp
, 2);
14612 rtx op0
= expand_normal (arg0
);
14613 rtx op1
= expand_normal (arg1
);
14614 rtx op2
= expand_normal (arg2
);
14615 rtx pat
, addr
, rawaddr
;
14616 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
14617 machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
14618 machine_mode mode1
= Pmode
;
14619 machine_mode mode2
= Pmode
;
14621 /* Invalid arguments. Bail before doing anything stoopid! */
14622 if (arg0
== error_mark_node
14623 || arg1
== error_mark_node
14624 || arg2
== error_mark_node
)
14627 op2
= copy_to_mode_reg (mode2
, op2
);
14629 /* For STVX, express the RTL accurately by ANDing the address with -16.
14630 STVXL and STVE*X expand to use UNSPECs to hide their special behavior,
14631 so the raw address is fine. */
14632 if (icode
== CODE_FOR_altivec_stvx_v2df_2op
14633 || icode
== CODE_FOR_altivec_stvx_v2di_2op
14634 || icode
== CODE_FOR_altivec_stvx_v4sf_2op
14635 || icode
== CODE_FOR_altivec_stvx_v4si_2op
14636 || icode
== CODE_FOR_altivec_stvx_v8hi_2op
14637 || icode
== CODE_FOR_altivec_stvx_v16qi_2op
)
14639 if (op1
== const0_rtx
)
14643 op1
= copy_to_mode_reg (mode1
, op1
);
14644 rawaddr
= gen_rtx_PLUS (Pmode
, op2
, op1
);
14647 addr
= gen_rtx_AND (Pmode
, rawaddr
, gen_rtx_CONST_INT (Pmode
, -16));
14648 addr
= gen_rtx_MEM (tmode
, addr
);
14650 op0
= copy_to_mode_reg (tmode
, op0
);
14652 /* For -maltivec=be, emit a permute to swap the elements, followed
14654 if (!BYTES_BIG_ENDIAN
&& VECTOR_ELT_ORDER_BIG
)
14656 rtx temp
= gen_reg_rtx (tmode
);
14657 rtx sel
= swap_selector_for_mode (tmode
);
14658 rtx vperm
= gen_rtx_UNSPEC (tmode
, gen_rtvec (3, op0
, op0
, sel
),
14660 emit_insn (gen_rtx_SET (temp
, vperm
));
14661 emit_insn (gen_rtx_SET (addr
, temp
));
14664 emit_insn (gen_rtx_SET (addr
, op0
));
14668 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
14669 op0
= copy_to_mode_reg (smode
, op0
);
14671 if (op1
== const0_rtx
)
14672 addr
= gen_rtx_MEM (tmode
, op2
);
14675 op1
= copy_to_mode_reg (mode1
, op1
);
14676 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op2
, op1
));
14679 pat
= GEN_FCN (icode
) (addr
, op0
);
14687 /* Return the appropriate SPR number associated with the given builtin. */
14688 static inline HOST_WIDE_INT
14689 htm_spr_num (enum rs6000_builtins code
)
14691 if (code
== HTM_BUILTIN_GET_TFHAR
14692 || code
== HTM_BUILTIN_SET_TFHAR
)
14694 else if (code
== HTM_BUILTIN_GET_TFIAR
14695 || code
== HTM_BUILTIN_SET_TFIAR
)
14697 else if (code
== HTM_BUILTIN_GET_TEXASR
14698 || code
== HTM_BUILTIN_SET_TEXASR
)
14700 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
14701 || code
== HTM_BUILTIN_SET_TEXASRU
);
14702 return TEXASRU_SPR
;
14705 /* Return the appropriate SPR regno associated with the given builtin. */
14706 static inline HOST_WIDE_INT
14707 htm_spr_regno (enum rs6000_builtins code
)
14709 if (code
== HTM_BUILTIN_GET_TFHAR
14710 || code
== HTM_BUILTIN_SET_TFHAR
)
14711 return TFHAR_REGNO
;
14712 else if (code
== HTM_BUILTIN_GET_TFIAR
14713 || code
== HTM_BUILTIN_SET_TFIAR
)
14714 return TFIAR_REGNO
;
14715 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
14716 || code
== HTM_BUILTIN_SET_TEXASR
14717 || code
== HTM_BUILTIN_GET_TEXASRU
14718 || code
== HTM_BUILTIN_SET_TEXASRU
);
14719 return TEXASR_REGNO
;
14722 /* Return the correct ICODE value depending on whether we are
14723 setting or reading the HTM SPRs. */
14724 static inline enum insn_code
14725 rs6000_htm_spr_icode (bool nonvoid
)
14728 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
14730 return (TARGET_POWERPC64
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
14733 /* Expand the HTM builtin in EXP and store the result in TARGET.
14734 Store true in *EXPANDEDP if we found a builtin to expand. */
14736 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
14738 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
14739 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
14740 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
14741 const struct builtin_description
*d
;
14746 if (!TARGET_POWERPC64
14747 && (fcode
== HTM_BUILTIN_TABORTDC
14748 || fcode
== HTM_BUILTIN_TABORTDCI
))
14750 size_t uns_fcode
= (size_t)fcode
;
14751 const char *name
= rs6000_builtin_info
[uns_fcode
].name
;
14752 error ("builtin %s is only valid in 64-bit mode", name
);
14756 /* Expand the HTM builtins. */
14758 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14759 if (d
->code
== fcode
)
14761 rtx op
[MAX_HTM_OPERANDS
], pat
;
14764 call_expr_arg_iterator iter
;
14765 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
14766 enum insn_code icode
= d
->icode
;
14767 const struct insn_operand_data
*insn_op
;
14768 bool uses_spr
= (attr
& RS6000_BTC_SPR
);
14772 icode
= rs6000_htm_spr_icode (nonvoid
);
14773 insn_op
= &insn_data
[icode
].operand
[0];
14777 machine_mode tmode
= (uses_spr
) ? insn_op
->mode
: SImode
;
14779 || GET_MODE (target
) != tmode
14780 || (uses_spr
&& !(*insn_op
->predicate
) (target
, tmode
)))
14781 target
= gen_reg_rtx (tmode
);
14783 op
[nopnds
++] = target
;
14786 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
14788 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
14791 insn_op
= &insn_data
[icode
].operand
[nopnds
];
14793 op
[nopnds
] = expand_normal (arg
);
14795 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
14797 if (!strcmp (insn_op
->constraint
, "n"))
14799 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
14800 if (!CONST_INT_P (op
[nopnds
]))
14801 error ("argument %d must be an unsigned literal", arg_num
);
14803 error ("argument %d is an unsigned literal that is "
14804 "out of range", arg_num
);
14807 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
14813 /* Handle the builtins for extended mnemonics. These accept
14814 no arguments, but map to builtins that take arguments. */
14817 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
14818 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
14819 op
[nopnds
++] = GEN_INT (1);
14821 attr
|= RS6000_BTC_UNARY
;
14823 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
14824 op
[nopnds
++] = GEN_INT (0);
14826 attr
|= RS6000_BTC_UNARY
;
14832 /* If this builtin accesses SPRs, then pass in the appropriate
14833 SPR number and SPR regno as the last two operands. */
14836 machine_mode mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
14837 op
[nopnds
++] = gen_rtx_CONST_INT (mode
, htm_spr_num (fcode
));
14838 op
[nopnds
++] = gen_rtx_REG (mode
, htm_spr_regno (fcode
));
14840 /* If this builtin accesses a CR, then pass in a scratch
14841 CR as the last operand. */
14842 else if (attr
& RS6000_BTC_CR
)
14843 { cr
= gen_reg_rtx (CCmode
);
14849 int expected_nopnds
= 0;
14850 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
14851 expected_nopnds
= 1;
14852 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
14853 expected_nopnds
= 2;
14854 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
14855 expected_nopnds
= 3;
14856 if (!(attr
& RS6000_BTC_VOID
))
14857 expected_nopnds
+= 1;
14859 expected_nopnds
+= 2;
14861 gcc_assert (nopnds
== expected_nopnds
14862 && nopnds
<= MAX_HTM_OPERANDS
);
14868 pat
= GEN_FCN (icode
) (op
[0]);
14871 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
14874 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
14877 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
14880 gcc_unreachable ();
14886 if (attr
& RS6000_BTC_CR
)
14888 if (fcode
== HTM_BUILTIN_TBEGIN
)
14890 /* Emit code to set TARGET to true or false depending on
14891 whether the tbegin. instruction successfully or failed
14892 to start a transaction. We do this by placing the 1's
14893 complement of CR's EQ bit into TARGET. */
14894 rtx scratch
= gen_reg_rtx (SImode
);
14895 emit_insn (gen_rtx_SET (scratch
,
14896 gen_rtx_EQ (SImode
, cr
,
14898 emit_insn (gen_rtx_SET (target
,
14899 gen_rtx_XOR (SImode
, scratch
,
14904 /* Emit code to copy the 4-bit condition register field
14905 CR into the least significant end of register TARGET. */
14906 rtx scratch1
= gen_reg_rtx (SImode
);
14907 rtx scratch2
= gen_reg_rtx (SImode
);
14908 rtx subreg
= simplify_gen_subreg (CCmode
, scratch1
, SImode
, 0);
14909 emit_insn (gen_movcc (subreg
, cr
));
14910 emit_insn (gen_lshrsi3 (scratch2
, scratch1
, GEN_INT (28)));
14911 emit_insn (gen_andsi3 (target
, scratch2
, GEN_INT (0xf)));
14920 *expandedp
= false;
14924 /* Expand the CPU builtin in FCODE and store the result in TARGET. */
14927 cpu_expand_builtin (enum rs6000_builtins fcode
, tree exp ATTRIBUTE_UNUSED
,
14930 /* __builtin_cpu_init () is a nop, so expand to nothing. */
14931 if (fcode
== RS6000_BUILTIN_CPU_INIT
)
14934 if (target
== 0 || GET_MODE (target
) != SImode
)
14935 target
= gen_reg_rtx (SImode
);
14937 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB
14938 tree arg
= TREE_OPERAND (CALL_EXPR_ARG (exp
, 0), 0);
14939 if (TREE_CODE (arg
) != STRING_CST
)
14941 error ("builtin %s only accepts a string argument",
14942 rs6000_builtin_info
[(size_t) fcode
].name
);
14946 if (fcode
== RS6000_BUILTIN_CPU_IS
)
14948 const char *cpu
= TREE_STRING_POINTER (arg
);
14949 rtx cpuid
= NULL_RTX
;
14950 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_is_info
); i
++)
14951 if (strcmp (cpu
, cpu_is_info
[i
].cpu
) == 0)
14953 /* The CPUID value in the TCB is offset by _DL_FIRST_PLATFORM. */
14954 cpuid
= GEN_INT (cpu_is_info
[i
].cpuid
+ _DL_FIRST_PLATFORM
);
14957 if (cpuid
== NULL_RTX
)
14959 /* Invalid CPU argument. */
14960 error ("cpu %s is an invalid argument to builtin %s",
14961 cpu
, rs6000_builtin_info
[(size_t) fcode
].name
);
14965 rtx platform
= gen_reg_rtx (SImode
);
14966 rtx tcbmem
= gen_const_mem (SImode
,
14967 gen_rtx_PLUS (Pmode
,
14968 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14969 GEN_INT (TCB_PLATFORM_OFFSET
)));
14970 emit_move_insn (platform
, tcbmem
);
14971 emit_insn (gen_eqsi3 (target
, platform
, cpuid
));
14973 else if (fcode
== RS6000_BUILTIN_CPU_SUPPORTS
)
14975 const char *hwcap
= TREE_STRING_POINTER (arg
);
14976 rtx mask
= NULL_RTX
;
14978 for (size_t i
= 0; i
< ARRAY_SIZE (cpu_supports_info
); i
++)
14979 if (strcmp (hwcap
, cpu_supports_info
[i
].hwcap
) == 0)
14981 mask
= GEN_INT (cpu_supports_info
[i
].mask
);
14982 hwcap_offset
= TCB_HWCAP_OFFSET (cpu_supports_info
[i
].id
);
14985 if (mask
== NULL_RTX
)
14987 /* Invalid HWCAP argument. */
14988 error ("hwcap %s is an invalid argument to builtin %s",
14989 hwcap
, rs6000_builtin_info
[(size_t) fcode
].name
);
14993 rtx tcb_hwcap
= gen_reg_rtx (SImode
);
14994 rtx tcbmem
= gen_const_mem (SImode
,
14995 gen_rtx_PLUS (Pmode
,
14996 gen_rtx_REG (Pmode
, TLS_REGNUM
),
14997 GEN_INT (hwcap_offset
)));
14998 emit_move_insn (tcb_hwcap
, tcbmem
);
14999 rtx scratch1
= gen_reg_rtx (SImode
);
15000 emit_insn (gen_rtx_SET (scratch1
, gen_rtx_AND (SImode
, tcb_hwcap
, mask
)));
15001 rtx scratch2
= gen_reg_rtx (SImode
);
15002 emit_insn (gen_eqsi3 (scratch2
, scratch1
, const0_rtx
));
15003 emit_insn (gen_rtx_SET (target
, gen_rtx_XOR (SImode
, scratch2
, const1_rtx
)));
15006 /* Record that we have expanded a CPU builtin, so that we can later
15007 emit a reference to the special symbol exported by LIBC to ensure we
15008 do not link against an old LIBC that doesn't support this feature. */
15009 cpu_builtin_p
= true;
15012 /* For old LIBCs, always return FALSE. */
15013 emit_move_insn (target
, GEN_INT (0));
15014 #endif /* TARGET_LIBC_PROVIDES_HWCAP_IN_TCB */
15020 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
15023 tree arg0
= CALL_EXPR_ARG (exp
, 0);
15024 tree arg1
= CALL_EXPR_ARG (exp
, 1);
15025 tree arg2
= CALL_EXPR_ARG (exp
, 2);
15026 rtx op0
= expand_normal (arg0
);
15027 rtx op1
= expand_normal (arg1
);
15028 rtx op2
= expand_normal (arg2
);
15029 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
15030 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
15031 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
15032 machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
15034 if (icode
== CODE_FOR_nothing
)
15035 /* Builtin not supported on this processor. */
15038 /* If we got invalid arguments bail out before generating bad rtl. */
15039 if (arg0
== error_mark_node
15040 || arg1
== error_mark_node
15041 || arg2
== error_mark_node
)
15044 /* Check and prepare argument depending on the instruction code.
15046 Note that a switch statement instead of the sequence of tests
15047 would be incorrect as many of the CODE_FOR values could be
15048 CODE_FOR_nothing and that would yield multiple alternatives
15049 with identical values. We'd never reach here at runtime in
15051 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
15052 || icode
== CODE_FOR_altivec_vsldoi_v4si
15053 || icode
== CODE_FOR_altivec_vsldoi_v8hi
15054 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
15056 /* Only allow 4-bit unsigned literals. */
15058 if (TREE_CODE (arg2
) != INTEGER_CST
15059 || TREE_INT_CST_LOW (arg2
) & ~0xf)
15061 error ("argument 3 must be a 4-bit unsigned literal");
15065 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
15066 || icode
== CODE_FOR_vsx_xxpermdi_v2di
15067 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
15068 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
15069 || icode
== CODE_FOR_vsx_xxsldwi_v4si
15070 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
15071 || icode
== CODE_FOR_vsx_xxsldwi_v2di
15072 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
15074 /* Only allow 2-bit unsigned literals. */
15076 if (TREE_CODE (arg2
) != INTEGER_CST
15077 || TREE_INT_CST_LOW (arg2
) & ~0x3)
15079 error ("argument 3 must be a 2-bit unsigned literal");
15083 else if (icode
== CODE_FOR_vsx_set_v2df
15084 || icode
== CODE_FOR_vsx_set_v2di
15085 || icode
== CODE_FOR_bcdadd
15086 || icode
== CODE_FOR_bcdadd_lt
15087 || icode
== CODE_FOR_bcdadd_eq
15088 || icode
== CODE_FOR_bcdadd_gt
15089 || icode
== CODE_FOR_bcdsub
15090 || icode
== CODE_FOR_bcdsub_lt
15091 || icode
== CODE_FOR_bcdsub_eq
15092 || icode
== CODE_FOR_bcdsub_gt
)
15094 /* Only allow 1-bit unsigned literals. */
15096 if (TREE_CODE (arg2
) != INTEGER_CST
15097 || TREE_INT_CST_LOW (arg2
) & ~0x1)
15099 error ("argument 3 must be a 1-bit unsigned literal");
15103 else if (icode
== CODE_FOR_dfp_ddedpd_dd
15104 || icode
== CODE_FOR_dfp_ddedpd_td
)
15106 /* Only allow 2-bit unsigned literals where the value is 0 or 2. */
15108 if (TREE_CODE (arg0
) != INTEGER_CST
15109 || TREE_INT_CST_LOW (arg2
) & ~0x3)
15111 error ("argument 1 must be 0 or 2");
15115 else if (icode
== CODE_FOR_dfp_denbcd_dd
15116 || icode
== CODE_FOR_dfp_denbcd_td
)
15118 /* Only allow 1-bit unsigned literals. */
15120 if (TREE_CODE (arg0
) != INTEGER_CST
15121 || TREE_INT_CST_LOW (arg0
) & ~0x1)
15123 error ("argument 1 must be a 1-bit unsigned literal");
15127 else if (icode
== CODE_FOR_dfp_dscli_dd
15128 || icode
== CODE_FOR_dfp_dscli_td
15129 || icode
== CODE_FOR_dfp_dscri_dd
15130 || icode
== CODE_FOR_dfp_dscri_td
)
15132 /* Only allow 6-bit unsigned literals. */
15134 if (TREE_CODE (arg1
) != INTEGER_CST
15135 || TREE_INT_CST_LOW (arg1
) & ~0x3f)
15137 error ("argument 2 must be a 6-bit unsigned literal");
15141 else if (icode
== CODE_FOR_crypto_vshasigmaw
15142 || icode
== CODE_FOR_crypto_vshasigmad
)
15144 /* Check whether the 2nd and 3rd arguments are integer constants and in
15145 range and prepare arguments. */
15147 if (TREE_CODE (arg1
) != INTEGER_CST
|| wi::geu_p (arg1
, 2))
15149 error ("argument 2 must be 0 or 1");
15154 if (TREE_CODE (arg2
) != INTEGER_CST
|| wi::geu_p (arg1
, 16))
15156 error ("argument 3 must be in the range 0..15");
15162 || GET_MODE (target
) != tmode
15163 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
15164 target
= gen_reg_rtx (tmode
);
15166 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
15167 op0
= copy_to_mode_reg (mode0
, op0
);
15168 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
15169 op1
= copy_to_mode_reg (mode1
, op1
);
15170 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
15171 op2
= copy_to_mode_reg (mode2
, op2
);
15173 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
15174 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
15176 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
15184 /* Expand the lvx builtins. */
15186 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
15188 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15189 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
15191 machine_mode tmode
, mode0
;
15193 enum insn_code icode
;
15197 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
15198 icode
= CODE_FOR_vector_altivec_load_v16qi
;
15200 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
15201 icode
= CODE_FOR_vector_altivec_load_v8hi
;
15203 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
15204 icode
= CODE_FOR_vector_altivec_load_v4si
;
15206 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
15207 icode
= CODE_FOR_vector_altivec_load_v4sf
;
15209 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
15210 icode
= CODE_FOR_vector_altivec_load_v2df
;
15212 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
15213 icode
= CODE_FOR_vector_altivec_load_v2di
;
15215 case ALTIVEC_BUILTIN_LD_INTERNAL_1ti
:
15216 icode
= CODE_FOR_vector_altivec_load_v1ti
;
15219 *expandedp
= false;
15225 arg0
= CALL_EXPR_ARG (exp
, 0);
15226 op0
= expand_normal (arg0
);
15227 tmode
= insn_data
[icode
].operand
[0].mode
;
15228 mode0
= insn_data
[icode
].operand
[1].mode
;
15231 || GET_MODE (target
) != tmode
15232 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
15233 target
= gen_reg_rtx (tmode
);
15235 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
15236 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
15238 pat
= GEN_FCN (icode
) (target
, op0
);
15245 /* Expand the stvx builtins. */
15247 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
15250 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15251 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
15253 machine_mode mode0
, mode1
;
15255 enum insn_code icode
;
15259 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
15260 icode
= CODE_FOR_vector_altivec_store_v16qi
;
15262 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
15263 icode
= CODE_FOR_vector_altivec_store_v8hi
;
15265 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
15266 icode
= CODE_FOR_vector_altivec_store_v4si
;
15268 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
15269 icode
= CODE_FOR_vector_altivec_store_v4sf
;
15271 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
15272 icode
= CODE_FOR_vector_altivec_store_v2df
;
15274 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
15275 icode
= CODE_FOR_vector_altivec_store_v2di
;
15277 case ALTIVEC_BUILTIN_ST_INTERNAL_1ti
:
15278 icode
= CODE_FOR_vector_altivec_store_v1ti
;
15281 *expandedp
= false;
15285 arg0
= CALL_EXPR_ARG (exp
, 0);
15286 arg1
= CALL_EXPR_ARG (exp
, 1);
15287 op0
= expand_normal (arg0
);
15288 op1
= expand_normal (arg1
);
15289 mode0
= insn_data
[icode
].operand
[0].mode
;
15290 mode1
= insn_data
[icode
].operand
[1].mode
;
15292 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
15293 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
15294 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
15295 op1
= copy_to_mode_reg (mode1
, op1
);
15297 pat
= GEN_FCN (icode
) (op0
, op1
);
15305 /* Expand the dst builtins. */
15307 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
15310 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15311 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15312 tree arg0
, arg1
, arg2
;
15313 machine_mode mode0
, mode1
;
15314 rtx pat
, op0
, op1
, op2
;
15315 const struct builtin_description
*d
;
15318 *expandedp
= false;
15320 /* Handle DST variants. */
15322 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
15323 if (d
->code
== fcode
)
15325 arg0
= CALL_EXPR_ARG (exp
, 0);
15326 arg1
= CALL_EXPR_ARG (exp
, 1);
15327 arg2
= CALL_EXPR_ARG (exp
, 2);
15328 op0
= expand_normal (arg0
);
15329 op1
= expand_normal (arg1
);
15330 op2
= expand_normal (arg2
);
15331 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
15332 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
15334 /* Invalid arguments, bail out before generating bad rtl. */
15335 if (arg0
== error_mark_node
15336 || arg1
== error_mark_node
15337 || arg2
== error_mark_node
)
15342 if (TREE_CODE (arg2
) != INTEGER_CST
15343 || TREE_INT_CST_LOW (arg2
) & ~0x3)
15345 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
15349 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
15350 op0
= copy_to_mode_reg (Pmode
, op0
);
15351 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
15352 op1
= copy_to_mode_reg (mode1
, op1
);
15354 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
15364 /* Expand vec_init builtin. */
15366 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
15368 machine_mode tmode
= TYPE_MODE (type
);
15369 machine_mode inner_mode
= GET_MODE_INNER (tmode
);
15370 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
15372 gcc_assert (VECTOR_MODE_P (tmode
));
15373 gcc_assert (n_elt
== call_expr_nargs (exp
));
15375 if (!target
|| !register_operand (target
, tmode
))
15376 target
= gen_reg_rtx (tmode
);
15378 /* If we have a vector compromised of a single element, such as V1TImode, do
15379 the initialization directly. */
15380 if (n_elt
== 1 && GET_MODE_SIZE (tmode
) == GET_MODE_SIZE (inner_mode
))
15382 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, 0));
15383 emit_move_insn (target
, gen_lowpart (tmode
, x
));
15387 rtvec v
= rtvec_alloc (n_elt
);
15389 for (i
= 0; i
< n_elt
; ++i
)
15391 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
15392 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
15395 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
15401 /* Return the integer constant in ARG. Constrain it to be in the range
15402 of the subparts of VEC_TYPE; issue an error if not. */
15405 get_element_number (tree vec_type
, tree arg
)
15407 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
15409 if (!tree_fits_uhwi_p (arg
)
15410 || (elt
= tree_to_uhwi (arg
), elt
> max
))
15412 error ("selector must be an integer constant in the range 0..%wi", max
);
15419 /* Expand vec_set builtin. */
15421 altivec_expand_vec_set_builtin (tree exp
)
15423 machine_mode tmode
, mode1
;
15424 tree arg0
, arg1
, arg2
;
15428 arg0
= CALL_EXPR_ARG (exp
, 0);
15429 arg1
= CALL_EXPR_ARG (exp
, 1);
15430 arg2
= CALL_EXPR_ARG (exp
, 2);
15432 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
15433 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
15434 gcc_assert (VECTOR_MODE_P (tmode
));
15436 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
15437 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
15438 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
15440 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
15441 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
15443 op0
= force_reg (tmode
, op0
);
15444 op1
= force_reg (mode1
, op1
);
15446 rs6000_expand_vector_set (op0
, op1
, elt
);
15451 /* Expand vec_ext builtin. */
15453 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
15455 machine_mode tmode
, mode0
;
15460 arg0
= CALL_EXPR_ARG (exp
, 0);
15461 arg1
= CALL_EXPR_ARG (exp
, 1);
15463 op0
= expand_normal (arg0
);
15464 op1
= expand_normal (arg1
);
15466 /* Call get_element_number to validate arg1 if it is a constant. */
15467 if (TREE_CODE (arg1
) == INTEGER_CST
)
15468 (void) get_element_number (TREE_TYPE (arg0
), arg1
);
15470 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
15471 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
15472 gcc_assert (VECTOR_MODE_P (mode0
));
15474 op0
= force_reg (mode0
, op0
);
15476 if (optimize
|| !target
|| !register_operand (target
, tmode
))
15477 target
= gen_reg_rtx (tmode
);
15479 rs6000_expand_vector_extract (target
, op0
, op1
);
15484 /* Expand the builtin in EXP and store the result in TARGET. Store
15485 true in *EXPANDEDP if we found a builtin to expand. */
15487 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
15489 const struct builtin_description
*d
;
15491 enum insn_code icode
;
15492 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15495 machine_mode tmode
, mode0
;
15496 enum rs6000_builtins fcode
15497 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15499 if (rs6000_overloaded_builtin_p (fcode
))
15502 error ("unresolved overload for Altivec builtin %qF", fndecl
);
15504 /* Given it is invalid, just generate a normal call. */
15505 return expand_call (exp
, target
, false);
15508 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
15512 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
15516 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
15524 case ALTIVEC_BUILTIN_STVX_V2DF
:
15525 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2df_2op
, exp
);
15526 case ALTIVEC_BUILTIN_STVX_V2DI
:
15527 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v2di_2op
, exp
);
15528 case ALTIVEC_BUILTIN_STVX_V4SF
:
15529 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4sf_2op
, exp
);
15530 case ALTIVEC_BUILTIN_STVX
:
15531 case ALTIVEC_BUILTIN_STVX_V4SI
:
15532 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si_2op
, exp
);
15533 case ALTIVEC_BUILTIN_STVX_V8HI
:
15534 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v8hi_2op
, exp
);
15535 case ALTIVEC_BUILTIN_STVX_V16QI
:
15536 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v16qi_2op
, exp
);
15537 case ALTIVEC_BUILTIN_STVEBX
:
15538 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
15539 case ALTIVEC_BUILTIN_STVEHX
:
15540 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
15541 case ALTIVEC_BUILTIN_STVEWX
:
15542 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
15543 case ALTIVEC_BUILTIN_STVXL_V2DF
:
15544 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2df
, exp
);
15545 case ALTIVEC_BUILTIN_STVXL_V2DI
:
15546 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v2di
, exp
);
15547 case ALTIVEC_BUILTIN_STVXL_V4SF
:
15548 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4sf
, exp
);
15549 case ALTIVEC_BUILTIN_STVXL
:
15550 case ALTIVEC_BUILTIN_STVXL_V4SI
:
15551 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v4si
, exp
);
15552 case ALTIVEC_BUILTIN_STVXL_V8HI
:
15553 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v8hi
, exp
);
15554 case ALTIVEC_BUILTIN_STVXL_V16QI
:
15555 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl_v16qi
, exp
);
15557 case ALTIVEC_BUILTIN_STVLX
:
15558 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
15559 case ALTIVEC_BUILTIN_STVLXL
:
15560 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
15561 case ALTIVEC_BUILTIN_STVRX
:
15562 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
15563 case ALTIVEC_BUILTIN_STVRXL
:
15564 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
15566 case P9V_BUILTIN_STXVL
:
15567 return altivec_expand_stxvl_builtin (CODE_FOR_stxvl
, exp
);
15569 case VSX_BUILTIN_STXVD2X_V1TI
:
15570 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v1ti
, exp
);
15571 case VSX_BUILTIN_STXVD2X_V2DF
:
15572 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
15573 case VSX_BUILTIN_STXVD2X_V2DI
:
15574 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
15575 case VSX_BUILTIN_STXVW4X_V4SF
:
15576 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
15577 case VSX_BUILTIN_STXVW4X_V4SI
:
15578 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
15579 case VSX_BUILTIN_STXVW4X_V8HI
:
15580 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
15581 case VSX_BUILTIN_STXVW4X_V16QI
:
15582 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
15584 /* For the following on big endian, it's ok to use any appropriate
15585 unaligned-supporting store, so use a generic expander. For
15586 little-endian, the exact element-reversing instruction must
15588 case VSX_BUILTIN_ST_ELEMREV_V2DF
:
15590 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2df
15591 : CODE_FOR_vsx_st_elemrev_v2df
);
15592 return altivec_expand_stv_builtin (code
, exp
);
15594 case VSX_BUILTIN_ST_ELEMREV_V2DI
:
15596 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v2di
15597 : CODE_FOR_vsx_st_elemrev_v2di
);
15598 return altivec_expand_stv_builtin (code
, exp
);
15600 case VSX_BUILTIN_ST_ELEMREV_V4SF
:
15602 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4sf
15603 : CODE_FOR_vsx_st_elemrev_v4sf
);
15604 return altivec_expand_stv_builtin (code
, exp
);
15606 case VSX_BUILTIN_ST_ELEMREV_V4SI
:
15608 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v4si
15609 : CODE_FOR_vsx_st_elemrev_v4si
);
15610 return altivec_expand_stv_builtin (code
, exp
);
15612 case VSX_BUILTIN_ST_ELEMREV_V8HI
:
15614 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v8hi
15615 : CODE_FOR_vsx_st_elemrev_v8hi
);
15616 return altivec_expand_stv_builtin (code
, exp
);
15618 case VSX_BUILTIN_ST_ELEMREV_V16QI
:
15620 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_store_v16qi
15621 : CODE_FOR_vsx_st_elemrev_v16qi
);
15622 return altivec_expand_stv_builtin (code
, exp
);
15625 case ALTIVEC_BUILTIN_MFVSCR
:
15626 icode
= CODE_FOR_altivec_mfvscr
;
15627 tmode
= insn_data
[icode
].operand
[0].mode
;
15630 || GET_MODE (target
) != tmode
15631 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
15632 target
= gen_reg_rtx (tmode
);
15634 pat
= GEN_FCN (icode
) (target
);
15640 case ALTIVEC_BUILTIN_MTVSCR
:
15641 icode
= CODE_FOR_altivec_mtvscr
;
15642 arg0
= CALL_EXPR_ARG (exp
, 0);
15643 op0
= expand_normal (arg0
);
15644 mode0
= insn_data
[icode
].operand
[0].mode
;
15646 /* If we got invalid arguments bail out before generating bad rtl. */
15647 if (arg0
== error_mark_node
)
15650 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
15651 op0
= copy_to_mode_reg (mode0
, op0
);
15653 pat
= GEN_FCN (icode
) (op0
);
15658 case ALTIVEC_BUILTIN_DSSALL
:
15659 emit_insn (gen_altivec_dssall ());
15662 case ALTIVEC_BUILTIN_DSS
:
15663 icode
= CODE_FOR_altivec_dss
;
15664 arg0
= CALL_EXPR_ARG (exp
, 0);
15666 op0
= expand_normal (arg0
);
15667 mode0
= insn_data
[icode
].operand
[0].mode
;
15669 /* If we got invalid arguments bail out before generating bad rtl. */
15670 if (arg0
== error_mark_node
)
15673 if (TREE_CODE (arg0
) != INTEGER_CST
15674 || TREE_INT_CST_LOW (arg0
) & ~0x3)
15676 error ("argument to dss must be a 2-bit unsigned literal");
15680 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
15681 op0
= copy_to_mode_reg (mode0
, op0
);
15683 emit_insn (gen_altivec_dss (op0
));
15686 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
15687 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
15688 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
15689 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
15690 case VSX_BUILTIN_VEC_INIT_V2DF
:
15691 case VSX_BUILTIN_VEC_INIT_V2DI
:
15692 case VSX_BUILTIN_VEC_INIT_V1TI
:
15693 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
15695 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
15696 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
15697 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
15698 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
15699 case VSX_BUILTIN_VEC_SET_V2DF
:
15700 case VSX_BUILTIN_VEC_SET_V2DI
:
15701 case VSX_BUILTIN_VEC_SET_V1TI
:
15702 return altivec_expand_vec_set_builtin (exp
);
15704 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
15705 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
15706 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
15707 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
15708 case VSX_BUILTIN_VEC_EXT_V2DF
:
15709 case VSX_BUILTIN_VEC_EXT_V2DI
:
15710 case VSX_BUILTIN_VEC_EXT_V1TI
:
15711 return altivec_expand_vec_ext_builtin (exp
, target
);
15715 /* Fall through. */
15718 /* Expand abs* operations. */
15720 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
15721 if (d
->code
== fcode
)
15722 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
15724 /* Expand the AltiVec predicates. */
15725 d
= bdesc_altivec_preds
;
15726 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
15727 if (d
->code
== fcode
)
15728 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
15730 /* LV* are funky. We initialized them differently. */
15733 case ALTIVEC_BUILTIN_LVSL
:
15734 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
15735 exp
, target
, false);
15736 case ALTIVEC_BUILTIN_LVSR
:
15737 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
15738 exp
, target
, false);
15739 case ALTIVEC_BUILTIN_LVEBX
:
15740 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
15741 exp
, target
, false);
15742 case ALTIVEC_BUILTIN_LVEHX
:
15743 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
15744 exp
, target
, false);
15745 case ALTIVEC_BUILTIN_LVEWX
:
15746 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
15747 exp
, target
, false);
15748 case ALTIVEC_BUILTIN_LVXL_V2DF
:
15749 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2df
,
15750 exp
, target
, false);
15751 case ALTIVEC_BUILTIN_LVXL_V2DI
:
15752 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v2di
,
15753 exp
, target
, false);
15754 case ALTIVEC_BUILTIN_LVXL_V4SF
:
15755 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4sf
,
15756 exp
, target
, false);
15757 case ALTIVEC_BUILTIN_LVXL
:
15758 case ALTIVEC_BUILTIN_LVXL_V4SI
:
15759 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v4si
,
15760 exp
, target
, false);
15761 case ALTIVEC_BUILTIN_LVXL_V8HI
:
15762 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v8hi
,
15763 exp
, target
, false);
15764 case ALTIVEC_BUILTIN_LVXL_V16QI
:
15765 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl_v16qi
,
15766 exp
, target
, false);
15767 case ALTIVEC_BUILTIN_LVX_V2DF
:
15768 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2df_2op
,
15769 exp
, target
, false);
15770 case ALTIVEC_BUILTIN_LVX_V2DI
:
15771 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v2di_2op
,
15772 exp
, target
, false);
15773 case ALTIVEC_BUILTIN_LVX_V4SF
:
15774 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4sf_2op
,
15775 exp
, target
, false);
15776 case ALTIVEC_BUILTIN_LVX
:
15777 case ALTIVEC_BUILTIN_LVX_V4SI
:
15778 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si_2op
,
15779 exp
, target
, false);
15780 case ALTIVEC_BUILTIN_LVX_V8HI
:
15781 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v8hi_2op
,
15782 exp
, target
, false);
15783 case ALTIVEC_BUILTIN_LVX_V16QI
:
15784 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v16qi_2op
,
15785 exp
, target
, false);
15786 case ALTIVEC_BUILTIN_LVLX
:
15787 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
15788 exp
, target
, true);
15789 case ALTIVEC_BUILTIN_LVLXL
:
15790 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
15791 exp
, target
, true);
15792 case ALTIVEC_BUILTIN_LVRX
:
15793 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
15794 exp
, target
, true);
15795 case ALTIVEC_BUILTIN_LVRXL
:
15796 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
15797 exp
, target
, true);
15798 case VSX_BUILTIN_LXVD2X_V1TI
:
15799 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v1ti
,
15800 exp
, target
, false);
15801 case VSX_BUILTIN_LXVD2X_V2DF
:
15802 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
15803 exp
, target
, false);
15804 case VSX_BUILTIN_LXVD2X_V2DI
:
15805 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
15806 exp
, target
, false);
15807 case VSX_BUILTIN_LXVW4X_V4SF
:
15808 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
15809 exp
, target
, false);
15810 case VSX_BUILTIN_LXVW4X_V4SI
:
15811 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
15812 exp
, target
, false);
15813 case VSX_BUILTIN_LXVW4X_V8HI
:
15814 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
15815 exp
, target
, false);
15816 case VSX_BUILTIN_LXVW4X_V16QI
:
15817 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
15818 exp
, target
, false);
15819 /* For the following on big endian, it's ok to use any appropriate
15820 unaligned-supporting load, so use a generic expander. For
15821 little-endian, the exact element-reversing instruction must
15823 case VSX_BUILTIN_LD_ELEMREV_V2DF
:
15825 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2df
15826 : CODE_FOR_vsx_ld_elemrev_v2df
);
15827 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15829 case VSX_BUILTIN_LD_ELEMREV_V2DI
:
15831 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v2di
15832 : CODE_FOR_vsx_ld_elemrev_v2di
);
15833 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15835 case VSX_BUILTIN_LD_ELEMREV_V4SF
:
15837 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4sf
15838 : CODE_FOR_vsx_ld_elemrev_v4sf
);
15839 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15841 case VSX_BUILTIN_LD_ELEMREV_V4SI
:
15843 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v4si
15844 : CODE_FOR_vsx_ld_elemrev_v4si
);
15845 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15847 case VSX_BUILTIN_LD_ELEMREV_V8HI
:
15849 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v8hi
15850 : CODE_FOR_vsx_ld_elemrev_v8hi
);
15851 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15853 case VSX_BUILTIN_LD_ELEMREV_V16QI
:
15855 enum insn_code code
= (BYTES_BIG_ENDIAN
? CODE_FOR_vsx_load_v16qi
15856 : CODE_FOR_vsx_ld_elemrev_v16qi
);
15857 return altivec_expand_lv_builtin (code
, exp
, target
, false);
15862 /* Fall through. */
15865 *expandedp
= false;
15869 /* Expand the builtin in EXP and store the result in TARGET. Store
15870 true in *EXPANDEDP if we found a builtin to expand. */
15872 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
15874 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15875 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15876 const struct builtin_description
*d
;
15883 case PAIRED_BUILTIN_STX
:
15884 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
15885 case PAIRED_BUILTIN_LX
:
15886 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
15889 /* Fall through. */
15892 /* Expand the paired predicates. */
15893 d
= bdesc_paired_preds
;
15894 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
15895 if (d
->code
== fcode
)
15896 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
15898 *expandedp
= false;
15902 /* Binops that need to be initialized manually, but can be expanded
15903 automagically by rs6000_expand_binop_builtin. */
15904 static const struct builtin_description bdesc_2arg_spe
[] =
15906 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
15907 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
15908 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
15909 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
15910 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
15911 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
15912 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
15913 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
15914 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
15915 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
15916 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
15917 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
15918 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
15919 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
15920 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
15921 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
15922 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
15923 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
15924 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
15925 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
15926 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
15927 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
15930 /* Expand the builtin in EXP and store the result in TARGET. Store
15931 true in *EXPANDEDP if we found a builtin to expand.
15933 This expands the SPE builtins that are not simple unary and binary
15936 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
15938 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
15940 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
15941 enum insn_code icode
;
15942 machine_mode tmode
, mode0
;
15944 const struct builtin_description
*d
;
15949 /* Syntax check for a 5-bit unsigned immediate. */
15952 case SPE_BUILTIN_EVSTDD
:
15953 case SPE_BUILTIN_EVSTDH
:
15954 case SPE_BUILTIN_EVSTDW
:
15955 case SPE_BUILTIN_EVSTWHE
:
15956 case SPE_BUILTIN_EVSTWHO
:
15957 case SPE_BUILTIN_EVSTWWE
:
15958 case SPE_BUILTIN_EVSTWWO
:
15959 arg1
= CALL_EXPR_ARG (exp
, 2);
15960 if (TREE_CODE (arg1
) != INTEGER_CST
15961 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
15963 error ("argument 2 must be a 5-bit unsigned literal");
15971 /* The evsplat*i instructions are not quite generic. */
15974 case SPE_BUILTIN_EVSPLATFI
:
15975 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
15977 case SPE_BUILTIN_EVSPLATI
:
15978 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
15984 d
= bdesc_2arg_spe
;
15985 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
15986 if (d
->code
== fcode
)
15987 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
15989 d
= bdesc_spe_predicates
;
15990 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
15991 if (d
->code
== fcode
)
15992 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
15994 d
= bdesc_spe_evsel
;
15995 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
15996 if (d
->code
== fcode
)
15997 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
16001 case SPE_BUILTIN_EVSTDDX
:
16002 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
16003 case SPE_BUILTIN_EVSTDHX
:
16004 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
16005 case SPE_BUILTIN_EVSTDWX
:
16006 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
16007 case SPE_BUILTIN_EVSTWHEX
:
16008 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
16009 case SPE_BUILTIN_EVSTWHOX
:
16010 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
16011 case SPE_BUILTIN_EVSTWWEX
:
16012 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
16013 case SPE_BUILTIN_EVSTWWOX
:
16014 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
16015 case SPE_BUILTIN_EVSTDD
:
16016 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
16017 case SPE_BUILTIN_EVSTDH
:
16018 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
16019 case SPE_BUILTIN_EVSTDW
:
16020 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
16021 case SPE_BUILTIN_EVSTWHE
:
16022 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
16023 case SPE_BUILTIN_EVSTWHO
:
16024 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
16025 case SPE_BUILTIN_EVSTWWE
:
16026 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
16027 case SPE_BUILTIN_EVSTWWO
:
16028 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
16029 case SPE_BUILTIN_MFSPEFSCR
:
16030 icode
= CODE_FOR_spe_mfspefscr
;
16031 tmode
= insn_data
[icode
].operand
[0].mode
;
16034 || GET_MODE (target
) != tmode
16035 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
16036 target
= gen_reg_rtx (tmode
);
16038 pat
= GEN_FCN (icode
) (target
);
16043 case SPE_BUILTIN_MTSPEFSCR
:
16044 icode
= CODE_FOR_spe_mtspefscr
;
16045 arg0
= CALL_EXPR_ARG (exp
, 0);
16046 op0
= expand_normal (arg0
);
16047 mode0
= insn_data
[icode
].operand
[0].mode
;
16049 if (arg0
== error_mark_node
)
16052 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
16053 op0
= copy_to_mode_reg (mode0
, op0
);
16055 pat
= GEN_FCN (icode
) (op0
);
16063 *expandedp
= false;
16068 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
16070 rtx pat
, scratch
, tmp
;
16071 tree form
= CALL_EXPR_ARG (exp
, 0);
16072 tree arg0
= CALL_EXPR_ARG (exp
, 1);
16073 tree arg1
= CALL_EXPR_ARG (exp
, 2);
16074 rtx op0
= expand_normal (arg0
);
16075 rtx op1
= expand_normal (arg1
);
16076 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
16077 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
16079 enum rtx_code code
;
16081 if (TREE_CODE (form
) != INTEGER_CST
)
16083 error ("argument 1 of __builtin_paired_predicate must be a constant");
16087 form_int
= TREE_INT_CST_LOW (form
);
16089 gcc_assert (mode0
== mode1
);
16091 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
16095 || GET_MODE (target
) != SImode
16096 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
16097 target
= gen_reg_rtx (SImode
);
16098 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
16099 op0
= copy_to_mode_reg (mode0
, op0
);
16100 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
16101 op1
= copy_to_mode_reg (mode1
, op1
);
16103 scratch
= gen_reg_rtx (CCFPmode
);
16105 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
16127 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
16130 error ("argument 1 of __builtin_paired_predicate is out of range");
16134 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
16135 emit_move_insn (target
, tmp
);
16140 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
16142 rtx pat
, scratch
, tmp
;
16143 tree form
= CALL_EXPR_ARG (exp
, 0);
16144 tree arg0
= CALL_EXPR_ARG (exp
, 1);
16145 tree arg1
= CALL_EXPR_ARG (exp
, 2);
16146 rtx op0
= expand_normal (arg0
);
16147 rtx op1
= expand_normal (arg1
);
16148 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
16149 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
16151 enum rtx_code code
;
16153 if (TREE_CODE (form
) != INTEGER_CST
)
16155 error ("argument 1 of __builtin_spe_predicate must be a constant");
16159 form_int
= TREE_INT_CST_LOW (form
);
16161 gcc_assert (mode0
== mode1
);
16163 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
16167 || GET_MODE (target
) != SImode
16168 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
16169 target
= gen_reg_rtx (SImode
);
16171 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
16172 op0
= copy_to_mode_reg (mode0
, op0
);
16173 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
16174 op1
= copy_to_mode_reg (mode1
, op1
);
16176 scratch
= gen_reg_rtx (CCmode
);
16178 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
16183 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
16184 _lower_. We use one compare, but look in different bits of the
16185 CR for each variant.
16187 There are 2 elements in each SPE simd type (upper/lower). The CR
16188 bits are set as follows:
16190 BIT0 | BIT 1 | BIT 2 | BIT 3
16191 U | L | (U | L) | (U & L)
16193 So, for an "all" relationship, BIT 3 would be set.
16194 For an "any" relationship, BIT 2 would be set. Etc.
16196 Following traditional nomenclature, these bits map to:
16198 BIT0 | BIT 1 | BIT 2 | BIT 3
16201 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
16206 /* All variant. OV bit. */
16208 /* We need to get to the OV bit, which is the ORDERED bit. We
16209 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
16210 that's ugly and will make validate_condition_mode die.
16211 So let's just use another pattern. */
16212 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
16214 /* Any variant. EQ bit. */
16218 /* Upper variant. LT bit. */
16222 /* Lower variant. GT bit. */
16227 error ("argument 1 of __builtin_spe_predicate is out of range");
16231 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
16232 emit_move_insn (target
, tmp
);
16237 /* The evsel builtins look like this:
16239 e = __builtin_spe_evsel_OP (a, b, c, d);
16241 and work like this:
16243 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
16244 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
16248 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
16251 tree arg0
= CALL_EXPR_ARG (exp
, 0);
16252 tree arg1
= CALL_EXPR_ARG (exp
, 1);
16253 tree arg2
= CALL_EXPR_ARG (exp
, 2);
16254 tree arg3
= CALL_EXPR_ARG (exp
, 3);
16255 rtx op0
= expand_normal (arg0
);
16256 rtx op1
= expand_normal (arg1
);
16257 rtx op2
= expand_normal (arg2
);
16258 rtx op3
= expand_normal (arg3
);
16259 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
16260 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
16262 gcc_assert (mode0
== mode1
);
16264 if (arg0
== error_mark_node
|| arg1
== error_mark_node
16265 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
16269 || GET_MODE (target
) != mode0
16270 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
16271 target
= gen_reg_rtx (mode0
);
16273 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
16274 op0
= copy_to_mode_reg (mode0
, op0
);
16275 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
16276 op1
= copy_to_mode_reg (mode0
, op1
);
16277 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
16278 op2
= copy_to_mode_reg (mode0
, op2
);
16279 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
16280 op3
= copy_to_mode_reg (mode0
, op3
);
16282 /* Generate the compare. */
16283 scratch
= gen_reg_rtx (CCmode
);
16284 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
16289 if (mode0
== V2SImode
)
16290 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
16292 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
16297 /* Raise an error message for a builtin function that is called without the
16298 appropriate target options being set. */
16301 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
16303 size_t uns_fncode
= (size_t)fncode
;
16304 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
16305 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
16307 gcc_assert (name
!= NULL
);
16308 if ((fnmask
& RS6000_BTM_CELL
) != 0)
16309 error ("Builtin function %s is only valid for the cell processor", name
);
16310 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
16311 error ("Builtin function %s requires the -mvsx option", name
);
16312 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
16313 error ("Builtin function %s requires the -mhtm option", name
);
16314 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
16315 error ("Builtin function %s requires the -maltivec option", name
);
16316 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
16317 error ("Builtin function %s requires the -mpaired option", name
);
16318 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
16319 error ("Builtin function %s requires the -mspe option", name
);
16320 else if ((fnmask
& (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
16321 == (RS6000_BTM_DFP
| RS6000_BTM_P8_VECTOR
))
16322 error ("Builtin function %s requires the -mhard-dfp and"
16323 " -mpower8-vector options", name
);
16324 else if ((fnmask
& RS6000_BTM_DFP
) != 0)
16325 error ("Builtin function %s requires the -mhard-dfp option", name
);
16326 else if ((fnmask
& RS6000_BTM_P8_VECTOR
) != 0)
16327 error ("Builtin function %s requires the -mpower8-vector option", name
);
16328 else if ((fnmask
& (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
16329 == (RS6000_BTM_P9_VECTOR
| RS6000_BTM_64BIT
))
16330 error ("Builtin function %s requires the -mcpu=power9 and"
16331 " -m64 options", name
);
16332 else if ((fnmask
& RS6000_BTM_P9_VECTOR
) != 0)
16333 error ("Builtin function %s requires the -mcpu=power9 option", name
);
16334 else if ((fnmask
& (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
16335 == (RS6000_BTM_P9_MISC
| RS6000_BTM_64BIT
))
16336 error ("Builtin function %s requires the -mcpu=power9 and"
16337 " -m64 options", name
);
16338 else if ((fnmask
& RS6000_BTM_P9_MISC
) == RS6000_BTM_P9_MISC
)
16339 error ("Builtin function %s requires the -mcpu=power9 option", name
);
16340 else if ((fnmask
& (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
16341 == (RS6000_BTM_HARD_FLOAT
| RS6000_BTM_LDBL128
))
16342 error ("Builtin function %s requires the -mhard-float and"
16343 " -mlong-double-128 options", name
);
16344 else if ((fnmask
& RS6000_BTM_HARD_FLOAT
) != 0)
16345 error ("Builtin function %s requires the -mhard-float option", name
);
16346 else if ((fnmask
& RS6000_BTM_FLOAT128
) != 0)
16347 error ("Builtin function %s requires the -mfloat128 option", name
);
16349 error ("Builtin function %s is not supported with the current options",
16353 /* Target hook for early folding of built-ins, shamelessly stolen
16357 rs6000_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
16358 tree
*args
, bool ignore ATTRIBUTE_UNUSED
)
16360 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
16362 enum rs6000_builtins fn_code
16363 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
16366 case RS6000_BUILTIN_NANQ
:
16367 case RS6000_BUILTIN_NANSQ
:
16369 tree type
= TREE_TYPE (TREE_TYPE (fndecl
));
16370 const char *str
= c_getstr (*args
);
16371 int quiet
= fn_code
== RS6000_BUILTIN_NANQ
;
16372 REAL_VALUE_TYPE real
;
16374 if (str
&& real_nan (&real
, str
, quiet
, TYPE_MODE (type
)))
16375 return build_real (type
, real
);
16378 case RS6000_BUILTIN_INFQ
:
16379 case RS6000_BUILTIN_HUGE_VALQ
:
16381 tree type
= TREE_TYPE (TREE_TYPE (fndecl
));
16382 REAL_VALUE_TYPE inf
;
16384 return build_real (type
, inf
);
16390 #ifdef SUBTARGET_FOLD_BUILTIN
16391 return SUBTARGET_FOLD_BUILTIN (fndecl
, n_args
, args
, ignore
);
16397 /* Fold a machine-dependent built-in in GIMPLE. (For folding into
16398 a constant, use rs6000_fold_builtin.) */
16401 rs6000_gimple_fold_builtin (gimple_stmt_iterator
*gsi
)
16403 gimple
*stmt
= gsi_stmt (*gsi
);
16404 tree fndecl
= gimple_call_fndecl (stmt
);
16405 gcc_checking_assert (fndecl
&& DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
);
16406 enum rs6000_builtins fn_code
16407 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
16408 tree arg0
, arg1
, lhs
;
16412 /* Flavors of vec_add. We deliberately don't expand
16413 P8V_BUILTIN_VADDUQM as it gets lowered from V1TImode to
16414 TImode, resulting in much poorer code generation. */
16415 case ALTIVEC_BUILTIN_VADDUBM
:
16416 case ALTIVEC_BUILTIN_VADDUHM
:
16417 case ALTIVEC_BUILTIN_VADDUWM
:
16418 case P8V_BUILTIN_VADDUDM
:
16419 case ALTIVEC_BUILTIN_VADDFP
:
16420 case VSX_BUILTIN_XVADDDP
:
16422 arg0
= gimple_call_arg (stmt
, 0);
16423 arg1
= gimple_call_arg (stmt
, 1);
16424 lhs
= gimple_call_lhs (stmt
);
16425 gimple
*g
= gimple_build_assign (lhs
, PLUS_EXPR
, arg0
, arg1
);
16426 gimple_set_location (g
, gimple_location (stmt
));
16427 gsi_replace (gsi
, g
, true);
16437 /* Expand an expression EXP that calls a built-in function,
16438 with result going to TARGET if that's convenient
16439 (and in mode MODE if that's convenient).
16440 SUBTARGET may be used as the target for computing one of EXP's operands.
16441 IGNORE is nonzero if the value is to be ignored. */
16444 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
16445 machine_mode mode ATTRIBUTE_UNUSED
,
16446 int ignore ATTRIBUTE_UNUSED
)
16448 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
16449 enum rs6000_builtins fcode
16450 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
16451 size_t uns_fcode
= (size_t)fcode
;
16452 const struct builtin_description
*d
;
16456 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
16457 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
16459 if (TARGET_DEBUG_BUILTIN
)
16461 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
16462 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
16463 const char *name2
= ((icode
!= CODE_FOR_nothing
)
16464 ? get_insn_name ((int)icode
)
16468 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
16470 default: name3
= "unknown"; break;
16471 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
16472 case RS6000_BTC_UNARY
: name3
= "unary"; break;
16473 case RS6000_BTC_BINARY
: name3
= "binary"; break;
16474 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
16475 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
16476 case RS6000_BTC_ABS
: name3
= "abs"; break;
16477 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
16478 case RS6000_BTC_DST
: name3
= "dst"; break;
16483 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
16484 (name1
) ? name1
: "---", fcode
,
16485 (name2
) ? name2
: "---", (int)icode
,
16487 func_valid_p
? "" : ", not valid");
16492 rs6000_invalid_builtin (fcode
);
16494 /* Given it is invalid, just generate a normal call. */
16495 return expand_call (exp
, target
, ignore
);
16500 case RS6000_BUILTIN_RECIP
:
16501 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
16503 case RS6000_BUILTIN_RECIPF
:
16504 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
16506 case RS6000_BUILTIN_RSQRTF
:
16507 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
16509 case RS6000_BUILTIN_RSQRT
:
16510 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
16512 case POWER7_BUILTIN_BPERMD
:
16513 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
16514 ? CODE_FOR_bpermd_di
16515 : CODE_FOR_bpermd_si
), exp
, target
);
16517 case RS6000_BUILTIN_GET_TB
:
16518 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
16521 case RS6000_BUILTIN_MFTB
:
16522 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
16523 ? CODE_FOR_rs6000_mftb_di
16524 : CODE_FOR_rs6000_mftb_si
),
16527 case RS6000_BUILTIN_MFFS
:
16528 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_mffs
, target
);
16530 case RS6000_BUILTIN_MTFSF
:
16531 return rs6000_expand_mtfsf_builtin (CODE_FOR_rs6000_mtfsf
, exp
);
16533 case RS6000_BUILTIN_CPU_INIT
:
16534 case RS6000_BUILTIN_CPU_IS
:
16535 case RS6000_BUILTIN_CPU_SUPPORTS
:
16536 return cpu_expand_builtin (fcode
, exp
, target
);
16538 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
16539 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
16541 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr_direct
16542 : (int) CODE_FOR_altivec_lvsl_direct
);
16543 machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
16544 machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
16548 gcc_assert (TARGET_ALTIVEC
);
16550 arg
= CALL_EXPR_ARG (exp
, 0);
16551 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
16552 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
16553 addr
= memory_address (mode
, op
);
16554 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
16558 /* For the load case need to negate the address. */
16559 op
= gen_reg_rtx (GET_MODE (addr
));
16560 emit_insn (gen_rtx_SET (op
, gen_rtx_NEG (GET_MODE (addr
), addr
)));
16562 op
= gen_rtx_MEM (mode
, op
);
16565 || GET_MODE (target
) != tmode
16566 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
16567 target
= gen_reg_rtx (tmode
);
16569 pat
= GEN_FCN (icode
) (target
, op
);
16577 case ALTIVEC_BUILTIN_VCFUX
:
16578 case ALTIVEC_BUILTIN_VCFSX
:
16579 case ALTIVEC_BUILTIN_VCTUXS
:
16580 case ALTIVEC_BUILTIN_VCTSXS
:
16581 /* FIXME: There's got to be a nicer way to handle this case than
16582 constructing a new CALL_EXPR. */
16583 if (call_expr_nargs (exp
) == 1)
16585 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
16586 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
16594 if (TARGET_ALTIVEC
)
16596 ret
= altivec_expand_builtin (exp
, target
, &success
);
16603 ret
= spe_expand_builtin (exp
, target
, &success
);
16608 if (TARGET_PAIRED_FLOAT
)
16610 ret
= paired_expand_builtin (exp
, target
, &success
);
16617 ret
= htm_expand_builtin (exp
, target
, &success
);
16623 unsigned attr
= rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
;
16624 /* RS6000_BTC_SPECIAL represents no-operand operators. */
16625 gcc_assert (attr
== RS6000_BTC_UNARY
16626 || attr
== RS6000_BTC_BINARY
16627 || attr
== RS6000_BTC_TERNARY
16628 || attr
== RS6000_BTC_SPECIAL
);
16630 /* Handle simple unary operations. */
16632 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
16633 if (d
->code
== fcode
)
16634 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
16636 /* Handle simple binary operations. */
16638 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
16639 if (d
->code
== fcode
)
16640 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
16642 /* Handle simple ternary operations. */
16644 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
16645 if (d
->code
== fcode
)
16646 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
16648 /* Handle simple no-argument operations. */
16650 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
16651 if (d
->code
== fcode
)
16652 return rs6000_expand_zeroop_builtin (d
->icode
, target
);
16654 gcc_unreachable ();
16658 rs6000_init_builtins (void)
16664 if (TARGET_DEBUG_BUILTIN
)
16665 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
16666 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
16667 (TARGET_SPE
) ? ", spe" : "",
16668 (TARGET_ALTIVEC
) ? ", altivec" : "",
16669 (TARGET_VSX
) ? ", vsx" : "");
16671 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
16672 V2SF_type_node
= build_vector_type (float_type_node
, 2);
16673 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
16674 V2DF_type_node
= build_vector_type (double_type_node
, 2);
16675 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
16676 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
16677 V4SF_type_node
= build_vector_type (float_type_node
, 4);
16678 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
16679 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
16681 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
16682 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
16683 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
16684 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
16686 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
16687 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
16688 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
16689 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
16691 const_str_type_node
16692 = build_pointer_type (build_qualified_type (char_type_node
,
16695 /* We use V1TI mode as a special container to hold __int128_t items that
16696 must live in VSX registers. */
16697 if (intTI_type_node
)
16699 V1TI_type_node
= build_vector_type (intTI_type_node
, 1);
16700 unsigned_V1TI_type_node
= build_vector_type (unsigned_intTI_type_node
, 1);
16703 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
16704 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
16705 'vector unsigned short'. */
16707 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
16708 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16709 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
16710 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
16711 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
16713 long_integer_type_internal_node
= long_integer_type_node
;
16714 long_unsigned_type_internal_node
= long_unsigned_type_node
;
16715 long_long_integer_type_internal_node
= long_long_integer_type_node
;
16716 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
16717 intQI_type_internal_node
= intQI_type_node
;
16718 uintQI_type_internal_node
= unsigned_intQI_type_node
;
16719 intHI_type_internal_node
= intHI_type_node
;
16720 uintHI_type_internal_node
= unsigned_intHI_type_node
;
16721 intSI_type_internal_node
= intSI_type_node
;
16722 uintSI_type_internal_node
= unsigned_intSI_type_node
;
16723 intDI_type_internal_node
= intDI_type_node
;
16724 uintDI_type_internal_node
= unsigned_intDI_type_node
;
16725 intTI_type_internal_node
= intTI_type_node
;
16726 uintTI_type_internal_node
= unsigned_intTI_type_node
;
16727 float_type_internal_node
= float_type_node
;
16728 double_type_internal_node
= double_type_node
;
16729 long_double_type_internal_node
= long_double_type_node
;
16730 dfloat64_type_internal_node
= dfloat64_type_node
;
16731 dfloat128_type_internal_node
= dfloat128_type_node
;
16732 void_type_internal_node
= void_type_node
;
16734 /* 128-bit floating point support. KFmode is IEEE 128-bit floating point.
16735 IFmode is the IBM extended 128-bit format that is a pair of doubles.
16736 TFmode will be either IEEE 128-bit floating point or the IBM double-double
16737 format that uses a pair of doubles, depending on the switches and
16740 We do not enable the actual __float128 keyword unless the user explicitly
16741 asks for it, because the library support is not yet complete.
16743 If we don't support for either 128-bit IBM double double or IEEE 128-bit
16744 floating point, we need make sure the type is non-zero or else self-test
16745 fails during bootstrap.
16747 We don't register a built-in type for __ibm128 if the type is the same as
16748 long double. Instead we add a #define for __ibm128 in
16749 rs6000_cpu_cpp_builtins to long double. */
16750 if (TARGET_LONG_DOUBLE_128
&& FLOAT128_IEEE_P (TFmode
))
16752 ibm128_float_type_node
= make_node (REAL_TYPE
);
16753 TYPE_PRECISION (ibm128_float_type_node
) = 128;
16754 layout_type (ibm128_float_type_node
);
16755 SET_TYPE_MODE (ibm128_float_type_node
, IFmode
);
16757 lang_hooks
.types
.register_builtin_type (ibm128_float_type_node
,
16761 ibm128_float_type_node
= long_double_type_node
;
16763 if (TARGET_FLOAT128_KEYWORD
)
16765 ieee128_float_type_node
= float128_type_node
;
16766 lang_hooks
.types
.register_builtin_type (ieee128_float_type_node
,
16770 else if (TARGET_FLOAT128_TYPE
)
16772 ieee128_float_type_node
= make_node (REAL_TYPE
);
16773 TYPE_PRECISION (ibm128_float_type_node
) = 128;
16774 layout_type (ieee128_float_type_node
);
16775 SET_TYPE_MODE (ieee128_float_type_node
, KFmode
);
16777 /* If we are not exporting the __float128/_Float128 keywords, we need a
16778 keyword to get the types created. Use __ieee128 as the dummy
16780 lang_hooks
.types
.register_builtin_type (ieee128_float_type_node
,
16785 ieee128_float_type_node
= long_double_type_node
;
16787 /* Initialize the modes for builtin_function_type, mapping a machine mode to
16789 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
16790 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
16791 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
16792 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
16793 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
16794 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
16795 builtin_mode_to_type
[TImode
][0] = intTI_type_node
;
16796 builtin_mode_to_type
[TImode
][1] = unsigned_intTI_type_node
;
16797 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
16798 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
16799 builtin_mode_to_type
[IFmode
][0] = ibm128_float_type_node
;
16800 builtin_mode_to_type
[KFmode
][0] = ieee128_float_type_node
;
16801 builtin_mode_to_type
[TFmode
][0] = long_double_type_node
;
16802 builtin_mode_to_type
[DDmode
][0] = dfloat64_type_node
;
16803 builtin_mode_to_type
[TDmode
][0] = dfloat128_type_node
;
16804 builtin_mode_to_type
[V1TImode
][0] = V1TI_type_node
;
16805 builtin_mode_to_type
[V1TImode
][1] = unsigned_V1TI_type_node
;
16806 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
16807 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
16808 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
16809 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
16810 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
16811 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
16812 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
16813 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
16814 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
16815 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
16816 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
16817 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
16818 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
16820 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
16821 TYPE_NAME (bool_char_type_node
) = tdecl
;
16823 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
16824 TYPE_NAME (bool_short_type_node
) = tdecl
;
16826 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
16827 TYPE_NAME (bool_int_type_node
) = tdecl
;
16829 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
16830 TYPE_NAME (pixel_type_node
) = tdecl
;
16832 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
16833 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
16834 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
16835 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
16836 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
16838 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
16839 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
16841 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
16842 TYPE_NAME (V16QI_type_node
) = tdecl
;
16844 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
16845 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
16847 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
16848 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
16850 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
16851 TYPE_NAME (V8HI_type_node
) = tdecl
;
16853 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
16854 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
16856 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
16857 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
16859 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
16860 TYPE_NAME (V4SI_type_node
) = tdecl
;
16862 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
16863 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
16865 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
16866 TYPE_NAME (V4SF_type_node
) = tdecl
;
16868 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
16869 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
16871 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
16872 TYPE_NAME (V2DF_type_node
) = tdecl
;
16874 if (TARGET_POWERPC64
)
16876 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
16877 TYPE_NAME (V2DI_type_node
) = tdecl
;
16879 tdecl
= add_builtin_type ("__vector unsigned long",
16880 unsigned_V2DI_type_node
);
16881 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
16883 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
16884 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
16888 tdecl
= add_builtin_type ("__vector long long", V2DI_type_node
);
16889 TYPE_NAME (V2DI_type_node
) = tdecl
;
16891 tdecl
= add_builtin_type ("__vector unsigned long long",
16892 unsigned_V2DI_type_node
);
16893 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
16895 tdecl
= add_builtin_type ("__vector __bool long long",
16896 bool_V2DI_type_node
);
16897 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
16900 if (V1TI_type_node
)
16902 tdecl
= add_builtin_type ("__vector __int128", V1TI_type_node
);
16903 TYPE_NAME (V1TI_type_node
) = tdecl
;
16905 tdecl
= add_builtin_type ("__vector unsigned __int128",
16906 unsigned_V1TI_type_node
);
16907 TYPE_NAME (unsigned_V1TI_type_node
) = tdecl
;
16910 /* Paired and SPE builtins are only available if you build a compiler with
16911 the appropriate options, so only create those builtins with the
16912 appropriate compiler option. Create Altivec and VSX builtins on machines
16913 with at least the general purpose extensions (970 and newer) to allow the
16914 use of the target attribute. */
16915 if (TARGET_PAIRED_FLOAT
)
16916 paired_init_builtins ();
16918 spe_init_builtins ();
16919 if (TARGET_EXTRA_BUILTINS
)
16920 altivec_init_builtins ();
16922 htm_init_builtins ();
16924 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
16925 rs6000_common_init_builtins ();
16927 ftype
= build_function_type_list (ieee128_float_type_node
,
16928 const_str_type_node
, NULL_TREE
);
16929 def_builtin ("__builtin_nanq", ftype
, RS6000_BUILTIN_NANQ
);
16930 def_builtin ("__builtin_nansq", ftype
, RS6000_BUILTIN_NANSQ
);
16932 ftype
= build_function_type_list (ieee128_float_type_node
, NULL_TREE
);
16933 def_builtin ("__builtin_infq", ftype
, RS6000_BUILTIN_INFQ
);
16934 def_builtin ("__builtin_huge_valq", ftype
, RS6000_BUILTIN_HUGE_VALQ
);
16936 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
16937 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
16938 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
16940 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
16941 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
16942 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
16944 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
16945 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
16946 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
16948 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
16949 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
16950 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
16952 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
16953 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
16954 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
16955 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
16957 ftype
= build_function_type_list (unsigned_intDI_type_node
,
16959 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
16962 ftype
= build_function_type_list (unsigned_intDI_type_node
,
16965 ftype
= build_function_type_list (unsigned_intSI_type_node
,
16967 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
16969 ftype
= build_function_type_list (double_type_node
, NULL_TREE
);
16970 def_builtin ("__builtin_mffs", ftype
, RS6000_BUILTIN_MFFS
);
16972 ftype
= build_function_type_list (void_type_node
,
16973 intSI_type_node
, double_type_node
,
16975 def_builtin ("__builtin_mtfsf", ftype
, RS6000_BUILTIN_MTFSF
);
16977 ftype
= build_function_type_list (void_type_node
, NULL_TREE
);
16978 def_builtin ("__builtin_cpu_init", ftype
, RS6000_BUILTIN_CPU_INIT
);
16980 ftype
= build_function_type_list (bool_int_type_node
, const_ptr_type_node
,
16982 def_builtin ("__builtin_cpu_is", ftype
, RS6000_BUILTIN_CPU_IS
);
16983 def_builtin ("__builtin_cpu_supports", ftype
, RS6000_BUILTIN_CPU_SUPPORTS
);
16986 /* AIX libm provides clog as __clog. */
16987 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
16988 set_user_assembler_name (tdecl
, "__clog");
16991 #ifdef SUBTARGET_INIT_BUILTINS
16992 SUBTARGET_INIT_BUILTINS
;
16996 /* Returns the rs6000 builtin decl for CODE. */
16999 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
17001 HOST_WIDE_INT fnmask
;
17003 if (code
>= RS6000_BUILTIN_COUNT
)
17004 return error_mark_node
;
17006 fnmask
= rs6000_builtin_info
[code
].mask
;
17007 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
17009 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
17010 return error_mark_node
;
17013 return rs6000_builtin_decls
[code
];
17017 spe_init_builtins (void)
17019 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
17020 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
17021 const struct builtin_description
*d
;
17023 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17025 tree v2si_ftype_4_v2si
17026 = build_function_type_list (opaque_V2SI_type_node
,
17027 opaque_V2SI_type_node
,
17028 opaque_V2SI_type_node
,
17029 opaque_V2SI_type_node
,
17030 opaque_V2SI_type_node
,
17033 tree v2sf_ftype_4_v2sf
17034 = build_function_type_list (opaque_V2SF_type_node
,
17035 opaque_V2SF_type_node
,
17036 opaque_V2SF_type_node
,
17037 opaque_V2SF_type_node
,
17038 opaque_V2SF_type_node
,
17041 tree int_ftype_int_v2si_v2si
17042 = build_function_type_list (integer_type_node
,
17044 opaque_V2SI_type_node
,
17045 opaque_V2SI_type_node
,
17048 tree int_ftype_int_v2sf_v2sf
17049 = build_function_type_list (integer_type_node
,
17051 opaque_V2SF_type_node
,
17052 opaque_V2SF_type_node
,
17055 tree void_ftype_v2si_puint_int
17056 = build_function_type_list (void_type_node
,
17057 opaque_V2SI_type_node
,
17062 tree void_ftype_v2si_puint_char
17063 = build_function_type_list (void_type_node
,
17064 opaque_V2SI_type_node
,
17069 tree void_ftype_v2si_pv2si_int
17070 = build_function_type_list (void_type_node
,
17071 opaque_V2SI_type_node
,
17072 opaque_p_V2SI_type_node
,
17076 tree void_ftype_v2si_pv2si_char
17077 = build_function_type_list (void_type_node
,
17078 opaque_V2SI_type_node
,
17079 opaque_p_V2SI_type_node
,
17083 tree void_ftype_int
17084 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
17086 tree int_ftype_void
17087 = build_function_type_list (integer_type_node
, NULL_TREE
);
17089 tree v2si_ftype_pv2si_int
17090 = build_function_type_list (opaque_V2SI_type_node
,
17091 opaque_p_V2SI_type_node
,
17095 tree v2si_ftype_puint_int
17096 = build_function_type_list (opaque_V2SI_type_node
,
17101 tree v2si_ftype_pushort_int
17102 = build_function_type_list (opaque_V2SI_type_node
,
17107 tree v2si_ftype_signed_char
17108 = build_function_type_list (opaque_V2SI_type_node
,
17109 signed_char_type_node
,
17112 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
17114 /* Initialize irregular SPE builtins. */
17116 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
17117 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
17118 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
17119 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
17120 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
17121 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
17122 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
17123 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
17124 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
17125 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
17126 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
17127 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
17128 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
17129 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
17130 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
17131 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
17132 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
17133 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
17136 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
17137 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
17138 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
17139 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
17140 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
17141 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
17142 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
17143 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
17144 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
17145 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
17146 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
17147 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
17148 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
17149 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
17150 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
17151 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
17152 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
17153 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
17154 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
17155 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
17156 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
17157 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
17160 d
= bdesc_spe_predicates
;
17161 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
17164 HOST_WIDE_INT mask
= d
->mask
;
17166 if ((mask
& builtin_mask
) != mask
)
17168 if (TARGET_DEBUG_BUILTIN
)
17169 fprintf (stderr
, "spe_init_builtins, skip predicate %s\n",
17174 switch (insn_data
[d
->icode
].operand
[1].mode
)
17177 type
= int_ftype_int_v2si_v2si
;
17180 type
= int_ftype_int_v2sf_v2sf
;
17183 gcc_unreachable ();
17186 def_builtin (d
->name
, type
, d
->code
);
17189 /* Evsel predicates. */
17190 d
= bdesc_spe_evsel
;
17191 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
17194 HOST_WIDE_INT mask
= d
->mask
;
17196 if ((mask
& builtin_mask
) != mask
)
17198 if (TARGET_DEBUG_BUILTIN
)
17199 fprintf (stderr
, "spe_init_builtins, skip evsel %s\n",
17204 switch (insn_data
[d
->icode
].operand
[1].mode
)
17207 type
= v2si_ftype_4_v2si
;
17210 type
= v2sf_ftype_4_v2sf
;
17213 gcc_unreachable ();
17216 def_builtin (d
->name
, type
, d
->code
);
17221 paired_init_builtins (void)
17223 const struct builtin_description
*d
;
17225 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17227 tree int_ftype_int_v2sf_v2sf
17228 = build_function_type_list (integer_type_node
,
17233 tree pcfloat_type_node
=
17234 build_pointer_type (build_qualified_type
17235 (float_type_node
, TYPE_QUAL_CONST
));
17237 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
17238 long_integer_type_node
,
17241 tree void_ftype_v2sf_long_pcfloat
=
17242 build_function_type_list (void_type_node
,
17244 long_integer_type_node
,
17249 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
17250 PAIRED_BUILTIN_LX
);
17253 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
17254 PAIRED_BUILTIN_STX
);
17257 d
= bdesc_paired_preds
;
17258 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
17261 HOST_WIDE_INT mask
= d
->mask
;
17263 if ((mask
& builtin_mask
) != mask
)
17265 if (TARGET_DEBUG_BUILTIN
)
17266 fprintf (stderr
, "paired_init_builtins, skip predicate %s\n",
17271 if (TARGET_DEBUG_BUILTIN
)
17272 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
17273 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
17274 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
17276 switch (insn_data
[d
->icode
].operand
[1].mode
)
17279 type
= int_ftype_int_v2sf_v2sf
;
17282 gcc_unreachable ();
17285 def_builtin (d
->name
, type
, d
->code
);
17290 altivec_init_builtins (void)
17292 const struct builtin_description
*d
;
17296 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17298 tree pvoid_type_node
= build_pointer_type (void_type_node
);
17300 tree pcvoid_type_node
17301 = build_pointer_type (build_qualified_type (void_type_node
,
17304 tree int_ftype_opaque
17305 = build_function_type_list (integer_type_node
,
17306 opaque_V4SI_type_node
, NULL_TREE
);
17307 tree opaque_ftype_opaque
17308 = build_function_type_list (integer_type_node
, NULL_TREE
);
17309 tree opaque_ftype_opaque_int
17310 = build_function_type_list (opaque_V4SI_type_node
,
17311 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
17312 tree opaque_ftype_opaque_opaque_int
17313 = build_function_type_list (opaque_V4SI_type_node
,
17314 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
17315 integer_type_node
, NULL_TREE
);
17316 tree opaque_ftype_opaque_opaque_opaque
17317 = build_function_type_list (opaque_V4SI_type_node
,
17318 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
17319 opaque_V4SI_type_node
, NULL_TREE
);
17320 tree opaque_ftype_opaque_opaque
17321 = build_function_type_list (opaque_V4SI_type_node
,
17322 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
17324 tree int_ftype_int_opaque_opaque
17325 = build_function_type_list (integer_type_node
,
17326 integer_type_node
, opaque_V4SI_type_node
,
17327 opaque_V4SI_type_node
, NULL_TREE
);
17328 tree int_ftype_int_v4si_v4si
17329 = build_function_type_list (integer_type_node
,
17330 integer_type_node
, V4SI_type_node
,
17331 V4SI_type_node
, NULL_TREE
);
17332 tree int_ftype_int_v2di_v2di
17333 = build_function_type_list (integer_type_node
,
17334 integer_type_node
, V2DI_type_node
,
17335 V2DI_type_node
, NULL_TREE
);
17336 tree void_ftype_v4si
17337 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
17338 tree v8hi_ftype_void
17339 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
17340 tree void_ftype_void
17341 = build_function_type_list (void_type_node
, NULL_TREE
);
17342 tree void_ftype_int
17343 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
17345 tree opaque_ftype_long_pcvoid
17346 = build_function_type_list (opaque_V4SI_type_node
,
17347 long_integer_type_node
, pcvoid_type_node
,
17349 tree v16qi_ftype_long_pcvoid
17350 = build_function_type_list (V16QI_type_node
,
17351 long_integer_type_node
, pcvoid_type_node
,
17353 tree v8hi_ftype_long_pcvoid
17354 = build_function_type_list (V8HI_type_node
,
17355 long_integer_type_node
, pcvoid_type_node
,
17357 tree v4si_ftype_long_pcvoid
17358 = build_function_type_list (V4SI_type_node
,
17359 long_integer_type_node
, pcvoid_type_node
,
17361 tree v4sf_ftype_long_pcvoid
17362 = build_function_type_list (V4SF_type_node
,
17363 long_integer_type_node
, pcvoid_type_node
,
17365 tree v2df_ftype_long_pcvoid
17366 = build_function_type_list (V2DF_type_node
,
17367 long_integer_type_node
, pcvoid_type_node
,
17369 tree v2di_ftype_long_pcvoid
17370 = build_function_type_list (V2DI_type_node
,
17371 long_integer_type_node
, pcvoid_type_node
,
17374 tree void_ftype_opaque_long_pvoid
17375 = build_function_type_list (void_type_node
,
17376 opaque_V4SI_type_node
, long_integer_type_node
,
17377 pvoid_type_node
, NULL_TREE
);
17378 tree void_ftype_v4si_long_pvoid
17379 = build_function_type_list (void_type_node
,
17380 V4SI_type_node
, long_integer_type_node
,
17381 pvoid_type_node
, NULL_TREE
);
17382 tree void_ftype_v16qi_long_pvoid
17383 = build_function_type_list (void_type_node
,
17384 V16QI_type_node
, long_integer_type_node
,
17385 pvoid_type_node
, NULL_TREE
);
17387 tree void_ftype_v16qi_pvoid_long
17388 = build_function_type_list (void_type_node
,
17389 V16QI_type_node
, pvoid_type_node
,
17390 long_integer_type_node
, NULL_TREE
);
17392 tree void_ftype_v8hi_long_pvoid
17393 = build_function_type_list (void_type_node
,
17394 V8HI_type_node
, long_integer_type_node
,
17395 pvoid_type_node
, NULL_TREE
);
17396 tree void_ftype_v4sf_long_pvoid
17397 = build_function_type_list (void_type_node
,
17398 V4SF_type_node
, long_integer_type_node
,
17399 pvoid_type_node
, NULL_TREE
);
17400 tree void_ftype_v2df_long_pvoid
17401 = build_function_type_list (void_type_node
,
17402 V2DF_type_node
, long_integer_type_node
,
17403 pvoid_type_node
, NULL_TREE
);
17404 tree void_ftype_v2di_long_pvoid
17405 = build_function_type_list (void_type_node
,
17406 V2DI_type_node
, long_integer_type_node
,
17407 pvoid_type_node
, NULL_TREE
);
17408 tree int_ftype_int_v8hi_v8hi
17409 = build_function_type_list (integer_type_node
,
17410 integer_type_node
, V8HI_type_node
,
17411 V8HI_type_node
, NULL_TREE
);
17412 tree int_ftype_int_v16qi_v16qi
17413 = build_function_type_list (integer_type_node
,
17414 integer_type_node
, V16QI_type_node
,
17415 V16QI_type_node
, NULL_TREE
);
17416 tree int_ftype_int_v4sf_v4sf
17417 = build_function_type_list (integer_type_node
,
17418 integer_type_node
, V4SF_type_node
,
17419 V4SF_type_node
, NULL_TREE
);
17420 tree int_ftype_int_v2df_v2df
17421 = build_function_type_list (integer_type_node
,
17422 integer_type_node
, V2DF_type_node
,
17423 V2DF_type_node
, NULL_TREE
);
17424 tree v2di_ftype_v2di
17425 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
17426 tree v4si_ftype_v4si
17427 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
17428 tree v8hi_ftype_v8hi
17429 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
17430 tree v16qi_ftype_v16qi
17431 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
17432 tree v4sf_ftype_v4sf
17433 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
17434 tree v2df_ftype_v2df
17435 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
17436 tree void_ftype_pcvoid_int_int
17437 = build_function_type_list (void_type_node
,
17438 pcvoid_type_node
, integer_type_node
,
17439 integer_type_node
, NULL_TREE
);
17441 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
17442 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
17443 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
17444 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
17445 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
17446 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
17447 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
17448 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
17449 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
17450 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
17451 def_builtin ("__builtin_altivec_lvxl_v2df", v2df_ftype_long_pcvoid
,
17452 ALTIVEC_BUILTIN_LVXL_V2DF
);
17453 def_builtin ("__builtin_altivec_lvxl_v2di", v2di_ftype_long_pcvoid
,
17454 ALTIVEC_BUILTIN_LVXL_V2DI
);
17455 def_builtin ("__builtin_altivec_lvxl_v4sf", v4sf_ftype_long_pcvoid
,
17456 ALTIVEC_BUILTIN_LVXL_V4SF
);
17457 def_builtin ("__builtin_altivec_lvxl_v4si", v4si_ftype_long_pcvoid
,
17458 ALTIVEC_BUILTIN_LVXL_V4SI
);
17459 def_builtin ("__builtin_altivec_lvxl_v8hi", v8hi_ftype_long_pcvoid
,
17460 ALTIVEC_BUILTIN_LVXL_V8HI
);
17461 def_builtin ("__builtin_altivec_lvxl_v16qi", v16qi_ftype_long_pcvoid
,
17462 ALTIVEC_BUILTIN_LVXL_V16QI
);
17463 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
17464 def_builtin ("__builtin_altivec_lvx_v2df", v2df_ftype_long_pcvoid
,
17465 ALTIVEC_BUILTIN_LVX_V2DF
);
17466 def_builtin ("__builtin_altivec_lvx_v2di", v2di_ftype_long_pcvoid
,
17467 ALTIVEC_BUILTIN_LVX_V2DI
);
17468 def_builtin ("__builtin_altivec_lvx_v4sf", v4sf_ftype_long_pcvoid
,
17469 ALTIVEC_BUILTIN_LVX_V4SF
);
17470 def_builtin ("__builtin_altivec_lvx_v4si", v4si_ftype_long_pcvoid
,
17471 ALTIVEC_BUILTIN_LVX_V4SI
);
17472 def_builtin ("__builtin_altivec_lvx_v8hi", v8hi_ftype_long_pcvoid
,
17473 ALTIVEC_BUILTIN_LVX_V8HI
);
17474 def_builtin ("__builtin_altivec_lvx_v16qi", v16qi_ftype_long_pcvoid
,
17475 ALTIVEC_BUILTIN_LVX_V16QI
);
17476 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
17477 def_builtin ("__builtin_altivec_stvx_v2df", void_ftype_v2df_long_pvoid
,
17478 ALTIVEC_BUILTIN_STVX_V2DF
);
17479 def_builtin ("__builtin_altivec_stvx_v2di", void_ftype_v2di_long_pvoid
,
17480 ALTIVEC_BUILTIN_STVX_V2DI
);
17481 def_builtin ("__builtin_altivec_stvx_v4sf", void_ftype_v4sf_long_pvoid
,
17482 ALTIVEC_BUILTIN_STVX_V4SF
);
17483 def_builtin ("__builtin_altivec_stvx_v4si", void_ftype_v4si_long_pvoid
,
17484 ALTIVEC_BUILTIN_STVX_V4SI
);
17485 def_builtin ("__builtin_altivec_stvx_v8hi", void_ftype_v8hi_long_pvoid
,
17486 ALTIVEC_BUILTIN_STVX_V8HI
);
17487 def_builtin ("__builtin_altivec_stvx_v16qi", void_ftype_v16qi_long_pvoid
,
17488 ALTIVEC_BUILTIN_STVX_V16QI
);
17489 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
17490 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
17491 def_builtin ("__builtin_altivec_stvxl_v2df", void_ftype_v2df_long_pvoid
,
17492 ALTIVEC_BUILTIN_STVXL_V2DF
);
17493 def_builtin ("__builtin_altivec_stvxl_v2di", void_ftype_v2di_long_pvoid
,
17494 ALTIVEC_BUILTIN_STVXL_V2DI
);
17495 def_builtin ("__builtin_altivec_stvxl_v4sf", void_ftype_v4sf_long_pvoid
,
17496 ALTIVEC_BUILTIN_STVXL_V4SF
);
17497 def_builtin ("__builtin_altivec_stvxl_v4si", void_ftype_v4si_long_pvoid
,
17498 ALTIVEC_BUILTIN_STVXL_V4SI
);
17499 def_builtin ("__builtin_altivec_stvxl_v8hi", void_ftype_v8hi_long_pvoid
,
17500 ALTIVEC_BUILTIN_STVXL_V8HI
);
17501 def_builtin ("__builtin_altivec_stvxl_v16qi", void_ftype_v16qi_long_pvoid
,
17502 ALTIVEC_BUILTIN_STVXL_V16QI
);
17503 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
17504 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
17505 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
17506 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
17507 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
17508 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
17509 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
17510 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
17511 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
17512 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
17513 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
17514 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
17515 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
17516 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
17517 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
17518 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
17520 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
17521 VSX_BUILTIN_LXVD2X_V2DF
);
17522 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
17523 VSX_BUILTIN_LXVD2X_V2DI
);
17524 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
17525 VSX_BUILTIN_LXVW4X_V4SF
);
17526 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
17527 VSX_BUILTIN_LXVW4X_V4SI
);
17528 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
17529 VSX_BUILTIN_LXVW4X_V8HI
);
17530 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
17531 VSX_BUILTIN_LXVW4X_V16QI
);
17532 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
17533 VSX_BUILTIN_STXVD2X_V2DF
);
17534 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
17535 VSX_BUILTIN_STXVD2X_V2DI
);
17536 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
17537 VSX_BUILTIN_STXVW4X_V4SF
);
17538 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
17539 VSX_BUILTIN_STXVW4X_V4SI
);
17540 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
17541 VSX_BUILTIN_STXVW4X_V8HI
);
17542 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
17543 VSX_BUILTIN_STXVW4X_V16QI
);
17545 def_builtin ("__builtin_vsx_ld_elemrev_v2df", v2df_ftype_long_pcvoid
,
17546 VSX_BUILTIN_LD_ELEMREV_V2DF
);
17547 def_builtin ("__builtin_vsx_ld_elemrev_v2di", v2di_ftype_long_pcvoid
,
17548 VSX_BUILTIN_LD_ELEMREV_V2DI
);
17549 def_builtin ("__builtin_vsx_ld_elemrev_v4sf", v4sf_ftype_long_pcvoid
,
17550 VSX_BUILTIN_LD_ELEMREV_V4SF
);
17551 def_builtin ("__builtin_vsx_ld_elemrev_v4si", v4si_ftype_long_pcvoid
,
17552 VSX_BUILTIN_LD_ELEMREV_V4SI
);
17553 def_builtin ("__builtin_vsx_st_elemrev_v2df", void_ftype_v2df_long_pvoid
,
17554 VSX_BUILTIN_ST_ELEMREV_V2DF
);
17555 def_builtin ("__builtin_vsx_st_elemrev_v2di", void_ftype_v2di_long_pvoid
,
17556 VSX_BUILTIN_ST_ELEMREV_V2DI
);
17557 def_builtin ("__builtin_vsx_st_elemrev_v4sf", void_ftype_v4sf_long_pvoid
,
17558 VSX_BUILTIN_ST_ELEMREV_V4SF
);
17559 def_builtin ("__builtin_vsx_st_elemrev_v4si", void_ftype_v4si_long_pvoid
,
17560 VSX_BUILTIN_ST_ELEMREV_V4SI
);
17562 if (TARGET_P9_VECTOR
)
17564 def_builtin ("__builtin_vsx_ld_elemrev_v8hi", v8hi_ftype_long_pcvoid
,
17565 VSX_BUILTIN_LD_ELEMREV_V8HI
);
17566 def_builtin ("__builtin_vsx_ld_elemrev_v16qi", v16qi_ftype_long_pcvoid
,
17567 VSX_BUILTIN_LD_ELEMREV_V16QI
);
17568 def_builtin ("__builtin_vsx_st_elemrev_v8hi",
17569 void_ftype_v8hi_long_pvoid
, VSX_BUILTIN_ST_ELEMREV_V8HI
);
17570 def_builtin ("__builtin_vsx_st_elemrev_v16qi",
17571 void_ftype_v16qi_long_pvoid
, VSX_BUILTIN_ST_ELEMREV_V16QI
);
17574 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
17575 VSX_BUILTIN_VEC_LD
);
17576 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
17577 VSX_BUILTIN_VEC_ST
);
17578 def_builtin ("__builtin_vec_xl", opaque_ftype_long_pcvoid
,
17579 VSX_BUILTIN_VEC_XL
);
17580 def_builtin ("__builtin_vec_xst", void_ftype_opaque_long_pvoid
,
17581 VSX_BUILTIN_VEC_XST
);
17583 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
17584 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
17585 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
17587 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
17588 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
17589 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
17590 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
17591 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
17592 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
17593 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
17594 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
17595 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
17596 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
17597 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
17598 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
17600 def_builtin ("__builtin_vec_adde", opaque_ftype_opaque_opaque_opaque
,
17601 ALTIVEC_BUILTIN_VEC_ADDE
);
17602 def_builtin ("__builtin_vec_addec", opaque_ftype_opaque_opaque_opaque
,
17603 ALTIVEC_BUILTIN_VEC_ADDEC
);
17604 def_builtin ("__builtin_vec_cmpne", opaque_ftype_opaque_opaque
,
17605 ALTIVEC_BUILTIN_VEC_CMPNE
);
17606 def_builtin ("__builtin_vec_mul", opaque_ftype_opaque_opaque
,
17607 ALTIVEC_BUILTIN_VEC_MUL
);
17609 /* Cell builtins. */
17610 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
17611 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
17612 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
17613 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
17615 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
17616 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
17617 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
17618 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
17620 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
17621 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
17622 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
17623 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
17625 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
17626 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
17627 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
17628 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
17630 if (TARGET_P9_VECTOR
)
17631 def_builtin ("__builtin_altivec_stxvl", void_ftype_v16qi_pvoid_long
,
17632 P9V_BUILTIN_STXVL
);
17634 /* Add the DST variants. */
17636 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
17638 HOST_WIDE_INT mask
= d
->mask
;
17640 if ((mask
& builtin_mask
) != mask
)
17642 if (TARGET_DEBUG_BUILTIN
)
17643 fprintf (stderr
, "altivec_init_builtins, skip dst %s\n",
17647 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
17650 /* Initialize the predicates. */
17651 d
= bdesc_altivec_preds
;
17652 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
17654 machine_mode mode1
;
17656 HOST_WIDE_INT mask
= d
->mask
;
17658 if ((mask
& builtin_mask
) != mask
)
17660 if (TARGET_DEBUG_BUILTIN
)
17661 fprintf (stderr
, "altivec_init_builtins, skip predicate %s\n",
17666 if (rs6000_overloaded_builtin_p (d
->code
))
17669 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
17674 type
= int_ftype_int_opaque_opaque
;
17677 type
= int_ftype_int_v2di_v2di
;
17680 type
= int_ftype_int_v4si_v4si
;
17683 type
= int_ftype_int_v8hi_v8hi
;
17686 type
= int_ftype_int_v16qi_v16qi
;
17689 type
= int_ftype_int_v4sf_v4sf
;
17692 type
= int_ftype_int_v2df_v2df
;
17695 gcc_unreachable ();
17698 def_builtin (d
->name
, type
, d
->code
);
17701 /* Initialize the abs* operators. */
17703 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
17705 machine_mode mode0
;
17707 HOST_WIDE_INT mask
= d
->mask
;
17709 if ((mask
& builtin_mask
) != mask
)
17711 if (TARGET_DEBUG_BUILTIN
)
17712 fprintf (stderr
, "altivec_init_builtins, skip abs %s\n",
17717 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
17722 type
= v2di_ftype_v2di
;
17725 type
= v4si_ftype_v4si
;
17728 type
= v8hi_ftype_v8hi
;
17731 type
= v16qi_ftype_v16qi
;
17734 type
= v4sf_ftype_v4sf
;
17737 type
= v2df_ftype_v2df
;
17740 gcc_unreachable ();
17743 def_builtin (d
->name
, type
, d
->code
);
17746 /* Initialize target builtin that implements
17747 targetm.vectorize.builtin_mask_for_load. */
17749 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
17750 v16qi_ftype_long_pcvoid
,
17751 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
17752 BUILT_IN_MD
, NULL
, NULL_TREE
);
17753 TREE_READONLY (decl
) = 1;
17754 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
17755 altivec_builtin_mask_for_load
= decl
;
17757 /* Access to the vec_init patterns. */
17758 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
17759 integer_type_node
, integer_type_node
,
17760 integer_type_node
, NULL_TREE
);
17761 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
17763 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
17764 short_integer_type_node
,
17765 short_integer_type_node
,
17766 short_integer_type_node
,
17767 short_integer_type_node
,
17768 short_integer_type_node
,
17769 short_integer_type_node
,
17770 short_integer_type_node
, NULL_TREE
);
17771 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
17773 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
17774 char_type_node
, char_type_node
,
17775 char_type_node
, char_type_node
,
17776 char_type_node
, char_type_node
,
17777 char_type_node
, char_type_node
,
17778 char_type_node
, char_type_node
,
17779 char_type_node
, char_type_node
,
17780 char_type_node
, char_type_node
,
17781 char_type_node
, NULL_TREE
);
17782 def_builtin ("__builtin_vec_init_v16qi", ftype
,
17783 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
17785 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
17786 float_type_node
, float_type_node
,
17787 float_type_node
, NULL_TREE
);
17788 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
17790 /* VSX builtins. */
17791 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
17792 double_type_node
, NULL_TREE
);
17793 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
17795 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
17796 intDI_type_node
, NULL_TREE
);
17797 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
17799 /* Access to the vec_set patterns. */
17800 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
17802 integer_type_node
, NULL_TREE
);
17803 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
17805 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
17807 integer_type_node
, NULL_TREE
);
17808 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
17810 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
17812 integer_type_node
, NULL_TREE
);
17813 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
17815 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
17817 integer_type_node
, NULL_TREE
);
17818 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
17820 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
17822 integer_type_node
, NULL_TREE
);
17823 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
17825 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
17827 integer_type_node
, NULL_TREE
);
17828 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
17830 /* Access to the vec_extract patterns. */
17831 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
17832 integer_type_node
, NULL_TREE
);
17833 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
17835 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
17836 integer_type_node
, NULL_TREE
);
17837 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
17839 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
17840 integer_type_node
, NULL_TREE
);
17841 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
17843 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
17844 integer_type_node
, NULL_TREE
);
17845 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
17847 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
17848 integer_type_node
, NULL_TREE
);
17849 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
17851 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
17852 integer_type_node
, NULL_TREE
);
17853 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
17856 if (V1TI_type_node
)
17858 tree v1ti_ftype_long_pcvoid
17859 = build_function_type_list (V1TI_type_node
,
17860 long_integer_type_node
, pcvoid_type_node
,
17862 tree void_ftype_v1ti_long_pvoid
17863 = build_function_type_list (void_type_node
,
17864 V1TI_type_node
, long_integer_type_node
,
17865 pvoid_type_node
, NULL_TREE
);
17866 def_builtin ("__builtin_vsx_lxvd2x_v1ti", v1ti_ftype_long_pcvoid
,
17867 VSX_BUILTIN_LXVD2X_V1TI
);
17868 def_builtin ("__builtin_vsx_stxvd2x_v1ti", void_ftype_v1ti_long_pvoid
,
17869 VSX_BUILTIN_STXVD2X_V1TI
);
17870 ftype
= build_function_type_list (V1TI_type_node
, intTI_type_node
,
17871 NULL_TREE
, NULL_TREE
);
17872 def_builtin ("__builtin_vec_init_v1ti", ftype
, VSX_BUILTIN_VEC_INIT_V1TI
);
17873 ftype
= build_function_type_list (V1TI_type_node
, V1TI_type_node
,
17875 integer_type_node
, NULL_TREE
);
17876 def_builtin ("__builtin_vec_set_v1ti", ftype
, VSX_BUILTIN_VEC_SET_V1TI
);
17877 ftype
= build_function_type_list (intTI_type_node
, V1TI_type_node
,
17878 integer_type_node
, NULL_TREE
);
17879 def_builtin ("__builtin_vec_ext_v1ti", ftype
, VSX_BUILTIN_VEC_EXT_V1TI
);
17885 htm_init_builtins (void)
17887 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
17888 const struct builtin_description
*d
;
17892 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
17894 tree op
[MAX_HTM_OPERANDS
], type
;
17895 HOST_WIDE_INT mask
= d
->mask
;
17896 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
17897 bool void_func
= (attr
& RS6000_BTC_VOID
);
17898 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
17900 tree gpr_type_node
;
17904 if (TARGET_32BIT
&& TARGET_POWERPC64
)
17905 gpr_type_node
= long_long_unsigned_type_node
;
17907 gpr_type_node
= long_unsigned_type_node
;
17909 if (attr
& RS6000_BTC_SPR
)
17911 rettype
= gpr_type_node
;
17912 argtype
= gpr_type_node
;
17914 else if (d
->code
== HTM_BUILTIN_TABORTDC
17915 || d
->code
== HTM_BUILTIN_TABORTDCI
)
17917 rettype
= unsigned_type_node
;
17918 argtype
= gpr_type_node
;
17922 rettype
= unsigned_type_node
;
17923 argtype
= unsigned_type_node
;
17926 if ((mask
& builtin_mask
) != mask
)
17928 if (TARGET_DEBUG_BUILTIN
)
17929 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
17935 if (TARGET_DEBUG_BUILTIN
)
17936 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
17937 (long unsigned) i
);
17941 op
[nopnds
++] = (void_func
) ? void_type_node
: rettype
;
17943 if (attr_args
== RS6000_BTC_UNARY
)
17944 op
[nopnds
++] = argtype
;
17945 else if (attr_args
== RS6000_BTC_BINARY
)
17947 op
[nopnds
++] = argtype
;
17948 op
[nopnds
++] = argtype
;
17950 else if (attr_args
== RS6000_BTC_TERNARY
)
17952 op
[nopnds
++] = argtype
;
17953 op
[nopnds
++] = argtype
;
17954 op
[nopnds
++] = argtype
;
17960 type
= build_function_type_list (op
[0], NULL_TREE
);
17963 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
17966 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
17969 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
17973 gcc_unreachable ();
17976 def_builtin (d
->name
, type
, d
->code
);
17980 /* Hash function for builtin functions with up to 3 arguments and a return
17983 builtin_hasher::hash (builtin_hash_struct
*bh
)
17988 for (i
= 0; i
< 4; i
++)
17990 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
17991 ret
= (ret
* 2) + bh
->uns_p
[i
];
17997 /* Compare builtin hash entries H1 and H2 for equivalence. */
17999 builtin_hasher::equal (builtin_hash_struct
*p1
, builtin_hash_struct
*p2
)
18001 return ((p1
->mode
[0] == p2
->mode
[0])
18002 && (p1
->mode
[1] == p2
->mode
[1])
18003 && (p1
->mode
[2] == p2
->mode
[2])
18004 && (p1
->mode
[3] == p2
->mode
[3])
18005 && (p1
->uns_p
[0] == p2
->uns_p
[0])
18006 && (p1
->uns_p
[1] == p2
->uns_p
[1])
18007 && (p1
->uns_p
[2] == p2
->uns_p
[2])
18008 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
18011 /* Map types for builtin functions with an explicit return type and up to 3
18012 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
18013 of the argument. */
18015 builtin_function_type (machine_mode mode_ret
, machine_mode mode_arg0
,
18016 machine_mode mode_arg1
, machine_mode mode_arg2
,
18017 enum rs6000_builtins builtin
, const char *name
)
18019 struct builtin_hash_struct h
;
18020 struct builtin_hash_struct
*h2
;
18023 tree ret_type
= NULL_TREE
;
18024 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
18026 /* Create builtin_hash_table. */
18027 if (builtin_hash_table
== NULL
)
18028 builtin_hash_table
= hash_table
<builtin_hasher
>::create_ggc (1500);
18030 h
.type
= NULL_TREE
;
18031 h
.mode
[0] = mode_ret
;
18032 h
.mode
[1] = mode_arg0
;
18033 h
.mode
[2] = mode_arg1
;
18034 h
.mode
[3] = mode_arg2
;
18040 /* If the builtin is a type that produces unsigned results or takes unsigned
18041 arguments, and it is returned as a decl for the vectorizer (such as
18042 widening multiplies, permute), make sure the arguments and return value
18043 are type correct. */
18046 /* unsigned 1 argument functions. */
18047 case CRYPTO_BUILTIN_VSBOX
:
18048 case P8V_BUILTIN_VGBBD
:
18049 case MISC_BUILTIN_CDTBCD
:
18050 case MISC_BUILTIN_CBCDTD
:
18055 /* unsigned 2 argument functions. */
18056 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
18057 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
18058 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
18059 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
18060 case CRYPTO_BUILTIN_VCIPHER
:
18061 case CRYPTO_BUILTIN_VCIPHERLAST
:
18062 case CRYPTO_BUILTIN_VNCIPHER
:
18063 case CRYPTO_BUILTIN_VNCIPHERLAST
:
18064 case CRYPTO_BUILTIN_VPMSUMB
:
18065 case CRYPTO_BUILTIN_VPMSUMH
:
18066 case CRYPTO_BUILTIN_VPMSUMW
:
18067 case CRYPTO_BUILTIN_VPMSUMD
:
18068 case CRYPTO_BUILTIN_VPMSUM
:
18069 case MISC_BUILTIN_ADDG6S
:
18070 case MISC_BUILTIN_DIVWEU
:
18071 case MISC_BUILTIN_DIVWEUO
:
18072 case MISC_BUILTIN_DIVDEU
:
18073 case MISC_BUILTIN_DIVDEUO
:
18079 /* unsigned 3 argument functions. */
18080 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
18081 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
18082 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
18083 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
18084 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
18085 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
18086 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
18087 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
18088 case VSX_BUILTIN_VPERM_16QI_UNS
:
18089 case VSX_BUILTIN_VPERM_8HI_UNS
:
18090 case VSX_BUILTIN_VPERM_4SI_UNS
:
18091 case VSX_BUILTIN_VPERM_2DI_UNS
:
18092 case VSX_BUILTIN_XXSEL_16QI_UNS
:
18093 case VSX_BUILTIN_XXSEL_8HI_UNS
:
18094 case VSX_BUILTIN_XXSEL_4SI_UNS
:
18095 case VSX_BUILTIN_XXSEL_2DI_UNS
:
18096 case CRYPTO_BUILTIN_VPERMXOR
:
18097 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
18098 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
18099 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
18100 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
18101 case CRYPTO_BUILTIN_VSHASIGMAW
:
18102 case CRYPTO_BUILTIN_VSHASIGMAD
:
18103 case CRYPTO_BUILTIN_VSHASIGMA
:
18110 /* signed permute functions with unsigned char mask. */
18111 case ALTIVEC_BUILTIN_VPERM_16QI
:
18112 case ALTIVEC_BUILTIN_VPERM_8HI
:
18113 case ALTIVEC_BUILTIN_VPERM_4SI
:
18114 case ALTIVEC_BUILTIN_VPERM_4SF
:
18115 case ALTIVEC_BUILTIN_VPERM_2DI
:
18116 case ALTIVEC_BUILTIN_VPERM_2DF
:
18117 case VSX_BUILTIN_VPERM_16QI
:
18118 case VSX_BUILTIN_VPERM_8HI
:
18119 case VSX_BUILTIN_VPERM_4SI
:
18120 case VSX_BUILTIN_VPERM_4SF
:
18121 case VSX_BUILTIN_VPERM_2DI
:
18122 case VSX_BUILTIN_VPERM_2DF
:
18126 /* unsigned args, signed return. */
18127 case VSX_BUILTIN_XVCVUXDDP_UNS
:
18128 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
18132 /* signed args, unsigned return. */
18133 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
18134 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
18135 case MISC_BUILTIN_UNPACK_TD
:
18136 case MISC_BUILTIN_UNPACK_V1TI
:
18140 /* unsigned arguments for 128-bit pack instructions. */
18141 case MISC_BUILTIN_PACK_TD
:
18142 case MISC_BUILTIN_PACK_V1TI
:
18151 /* Figure out how many args are present. */
18152 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
18155 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
18156 if (!ret_type
&& h
.uns_p
[0])
18157 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
18160 fatal_error (input_location
,
18161 "internal error: builtin function %s had an unexpected "
18162 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
18164 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
18165 arg_type
[i
] = NULL_TREE
;
18167 for (i
= 0; i
< num_args
; i
++)
18169 int m
= (int) h
.mode
[i
+1];
18170 int uns_p
= h
.uns_p
[i
+1];
18172 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
18173 if (!arg_type
[i
] && uns_p
)
18174 arg_type
[i
] = builtin_mode_to_type
[m
][0];
18177 fatal_error (input_location
,
18178 "internal error: builtin function %s, argument %d "
18179 "had unexpected argument type %s", name
, i
,
18180 GET_MODE_NAME (m
));
18183 builtin_hash_struct
**found
= builtin_hash_table
->find_slot (&h
, INSERT
);
18184 if (*found
== NULL
)
18186 h2
= ggc_alloc
<builtin_hash_struct
> ();
18190 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
18191 arg_type
[2], NULL_TREE
);
18194 return (*found
)->type
;
18198 rs6000_common_init_builtins (void)
18200 const struct builtin_description
*d
;
18203 tree opaque_ftype_opaque
= NULL_TREE
;
18204 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
18205 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
18206 tree v2si_ftype
= NULL_TREE
;
18207 tree v2si_ftype_qi
= NULL_TREE
;
18208 tree v2si_ftype_v2si_qi
= NULL_TREE
;
18209 tree v2si_ftype_int_qi
= NULL_TREE
;
18210 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
18212 if (!TARGET_PAIRED_FLOAT
)
18214 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
18215 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
18218 /* Paired and SPE builtins are only available if you build a compiler with
18219 the appropriate options, so only create those builtins with the
18220 appropriate compiler option. Create Altivec and VSX builtins on machines
18221 with at least the general purpose extensions (970 and newer) to allow the
18222 use of the target attribute.. */
18224 if (TARGET_EXTRA_BUILTINS
)
18225 builtin_mask
|= RS6000_BTM_COMMON
;
18227 /* Add the ternary operators. */
18229 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
18232 HOST_WIDE_INT mask
= d
->mask
;
18234 if ((mask
& builtin_mask
) != mask
)
18236 if (TARGET_DEBUG_BUILTIN
)
18237 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
18241 if (rs6000_overloaded_builtin_p (d
->code
))
18243 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
18244 type
= opaque_ftype_opaque_opaque_opaque
18245 = build_function_type_list (opaque_V4SI_type_node
,
18246 opaque_V4SI_type_node
,
18247 opaque_V4SI_type_node
,
18248 opaque_V4SI_type_node
,
18253 enum insn_code icode
= d
->icode
;
18256 if (TARGET_DEBUG_BUILTIN
)
18257 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
18263 if (icode
== CODE_FOR_nothing
)
18265 if (TARGET_DEBUG_BUILTIN
)
18266 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
18272 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
18273 insn_data
[icode
].operand
[1].mode
,
18274 insn_data
[icode
].operand
[2].mode
,
18275 insn_data
[icode
].operand
[3].mode
,
18279 def_builtin (d
->name
, type
, d
->code
);
18282 /* Add the binary operators. */
18284 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
18286 machine_mode mode0
, mode1
, mode2
;
18288 HOST_WIDE_INT mask
= d
->mask
;
18290 if ((mask
& builtin_mask
) != mask
)
18292 if (TARGET_DEBUG_BUILTIN
)
18293 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
18297 if (rs6000_overloaded_builtin_p (d
->code
))
18299 if (! (type
= opaque_ftype_opaque_opaque
))
18300 type
= opaque_ftype_opaque_opaque
18301 = build_function_type_list (opaque_V4SI_type_node
,
18302 opaque_V4SI_type_node
,
18303 opaque_V4SI_type_node
,
18308 enum insn_code icode
= d
->icode
;
18311 if (TARGET_DEBUG_BUILTIN
)
18312 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
18318 if (icode
== CODE_FOR_nothing
)
18320 if (TARGET_DEBUG_BUILTIN
)
18321 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
18327 mode0
= insn_data
[icode
].operand
[0].mode
;
18328 mode1
= insn_data
[icode
].operand
[1].mode
;
18329 mode2
= insn_data
[icode
].operand
[2].mode
;
18331 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
18333 if (! (type
= v2si_ftype_v2si_qi
))
18334 type
= v2si_ftype_v2si_qi
18335 = build_function_type_list (opaque_V2SI_type_node
,
18336 opaque_V2SI_type_node
,
18341 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
18342 && mode2
== QImode
)
18344 if (! (type
= v2si_ftype_int_qi
))
18345 type
= v2si_ftype_int_qi
18346 = build_function_type_list (opaque_V2SI_type_node
,
18353 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
18357 def_builtin (d
->name
, type
, d
->code
);
18360 /* Add the simple unary operators. */
18362 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
18364 machine_mode mode0
, mode1
;
18366 HOST_WIDE_INT mask
= d
->mask
;
18368 if ((mask
& builtin_mask
) != mask
)
18370 if (TARGET_DEBUG_BUILTIN
)
18371 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
18375 if (rs6000_overloaded_builtin_p (d
->code
))
18377 if (! (type
= opaque_ftype_opaque
))
18378 type
= opaque_ftype_opaque
18379 = build_function_type_list (opaque_V4SI_type_node
,
18380 opaque_V4SI_type_node
,
18385 enum insn_code icode
= d
->icode
;
18388 if (TARGET_DEBUG_BUILTIN
)
18389 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
18395 if (icode
== CODE_FOR_nothing
)
18397 if (TARGET_DEBUG_BUILTIN
)
18398 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
18404 mode0
= insn_data
[icode
].operand
[0].mode
;
18405 mode1
= insn_data
[icode
].operand
[1].mode
;
18407 if (mode0
== V2SImode
&& mode1
== QImode
)
18409 if (! (type
= v2si_ftype_qi
))
18410 type
= v2si_ftype_qi
18411 = build_function_type_list (opaque_V2SI_type_node
,
18417 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
18421 def_builtin (d
->name
, type
, d
->code
);
18424 /* Add the simple no-argument operators. */
18426 for (i
= 0; i
< ARRAY_SIZE (bdesc_0arg
); i
++, d
++)
18428 machine_mode mode0
;
18430 HOST_WIDE_INT mask
= d
->mask
;
18432 if ((mask
& builtin_mask
) != mask
)
18434 if (TARGET_DEBUG_BUILTIN
)
18435 fprintf (stderr
, "rs6000_builtin, skip no-argument %s\n", d
->name
);
18438 if (rs6000_overloaded_builtin_p (d
->code
))
18440 if (!opaque_ftype_opaque
)
18441 opaque_ftype_opaque
18442 = build_function_type_list (opaque_V4SI_type_node
, NULL_TREE
);
18443 type
= opaque_ftype_opaque
;
18447 enum insn_code icode
= d
->icode
;
18450 if (TARGET_DEBUG_BUILTIN
)
18451 fprintf (stderr
, "rs6000_builtin, bdesc_0arg[%lu] no name\n",
18452 (long unsigned) i
);
18455 if (icode
== CODE_FOR_nothing
)
18457 if (TARGET_DEBUG_BUILTIN
)
18459 "rs6000_builtin, skip no-argument %s (no code)\n",
18463 mode0
= insn_data
[icode
].operand
[0].mode
;
18464 if (mode0
== V2SImode
)
18467 if (! (type
= v2si_ftype
))
18470 = build_function_type_list (opaque_V2SI_type_node
,
18476 type
= builtin_function_type (mode0
, VOIDmode
, VOIDmode
, VOIDmode
,
18479 def_builtin (d
->name
, type
, d
->code
);
18483 /* Set up AIX/Darwin/64-bit Linux quad floating point routines. */
18485 init_float128_ibm (machine_mode mode
)
18487 if (!TARGET_XL_COMPAT
)
18489 set_optab_libfunc (add_optab
, mode
, "__gcc_qadd");
18490 set_optab_libfunc (sub_optab
, mode
, "__gcc_qsub");
18491 set_optab_libfunc (smul_optab
, mode
, "__gcc_qmul");
18492 set_optab_libfunc (sdiv_optab
, mode
, "__gcc_qdiv");
18494 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
18496 set_optab_libfunc (neg_optab
, mode
, "__gcc_qneg");
18497 set_optab_libfunc (eq_optab
, mode
, "__gcc_qeq");
18498 set_optab_libfunc (ne_optab
, mode
, "__gcc_qne");
18499 set_optab_libfunc (gt_optab
, mode
, "__gcc_qgt");
18500 set_optab_libfunc (ge_optab
, mode
, "__gcc_qge");
18501 set_optab_libfunc (lt_optab
, mode
, "__gcc_qlt");
18502 set_optab_libfunc (le_optab
, mode
, "__gcc_qle");
18504 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__gcc_stoq");
18505 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__gcc_dtoq");
18506 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__gcc_qtos");
18507 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__gcc_qtod");
18508 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__gcc_qtoi");
18509 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__gcc_qtou");
18510 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__gcc_itoq");
18511 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__gcc_utoq");
18514 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
18515 set_optab_libfunc (unord_optab
, mode
, "__gcc_qunord");
18519 set_optab_libfunc (add_optab
, mode
, "_xlqadd");
18520 set_optab_libfunc (sub_optab
, mode
, "_xlqsub");
18521 set_optab_libfunc (smul_optab
, mode
, "_xlqmul");
18522 set_optab_libfunc (sdiv_optab
, mode
, "_xlqdiv");
18525 /* Add various conversions for IFmode to use the traditional TFmode
18527 if (mode
== IFmode
)
18529 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdtf2");
18530 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddtf2");
18531 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunctftd2");
18532 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunctfsd2");
18533 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunctfdd2");
18534 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtdtf2");
18536 if (TARGET_POWERPC64
)
18538 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixtfti");
18539 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunstfti");
18540 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattitf");
18541 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntitf");
18546 /* Set up IEEE 128-bit floating point routines. Use different names if the
18547 arguments can be passed in a vector register. The historical PowerPC
18548 implementation of IEEE 128-bit floating point used _q_<op> for the names, so
18549 continue to use that if we aren't using vector registers to pass IEEE
18550 128-bit floating point. */
18553 init_float128_ieee (machine_mode mode
)
18555 if (FLOAT128_VECTOR_P (mode
))
18557 set_optab_libfunc (add_optab
, mode
, "__addkf3");
18558 set_optab_libfunc (sub_optab
, mode
, "__subkf3");
18559 set_optab_libfunc (neg_optab
, mode
, "__negkf2");
18560 set_optab_libfunc (smul_optab
, mode
, "__mulkf3");
18561 set_optab_libfunc (sdiv_optab
, mode
, "__divkf3");
18562 set_optab_libfunc (sqrt_optab
, mode
, "__sqrtkf2");
18563 set_optab_libfunc (abs_optab
, mode
, "__abstkf2");
18565 set_optab_libfunc (eq_optab
, mode
, "__eqkf2");
18566 set_optab_libfunc (ne_optab
, mode
, "__nekf2");
18567 set_optab_libfunc (gt_optab
, mode
, "__gtkf2");
18568 set_optab_libfunc (ge_optab
, mode
, "__gekf2");
18569 set_optab_libfunc (lt_optab
, mode
, "__ltkf2");
18570 set_optab_libfunc (le_optab
, mode
, "__lekf2");
18571 set_optab_libfunc (unord_optab
, mode
, "__unordkf2");
18573 set_conv_libfunc (sext_optab
, mode
, SFmode
, "__extendsfkf2");
18574 set_conv_libfunc (sext_optab
, mode
, DFmode
, "__extenddfkf2");
18575 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "__trunckfsf2");
18576 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "__trunckfdf2");
18578 set_conv_libfunc (sext_optab
, mode
, IFmode
, "__extendtfkf2");
18579 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18580 set_conv_libfunc (sext_optab
, mode
, TFmode
, "__extendtfkf2");
18582 set_conv_libfunc (trunc_optab
, IFmode
, mode
, "__trunckftf2");
18583 if (mode
!= TFmode
&& FLOAT128_IBM_P (TFmode
))
18584 set_conv_libfunc (trunc_optab
, TFmode
, mode
, "__trunckftf2");
18586 set_conv_libfunc (sext_optab
, mode
, SDmode
, "__dpd_extendsdkf2");
18587 set_conv_libfunc (sext_optab
, mode
, DDmode
, "__dpd_extendddkf2");
18588 set_conv_libfunc (trunc_optab
, mode
, TDmode
, "__dpd_trunckftd2");
18589 set_conv_libfunc (trunc_optab
, SDmode
, mode
, "__dpd_trunckfsd2");
18590 set_conv_libfunc (trunc_optab
, DDmode
, mode
, "__dpd_trunckfdd2");
18591 set_conv_libfunc (sext_optab
, TDmode
, mode
, "__dpd_extendtdkf2");
18593 set_conv_libfunc (sfix_optab
, SImode
, mode
, "__fixkfsi");
18594 set_conv_libfunc (ufix_optab
, SImode
, mode
, "__fixunskfsi");
18595 set_conv_libfunc (sfix_optab
, DImode
, mode
, "__fixkfdi");
18596 set_conv_libfunc (ufix_optab
, DImode
, mode
, "__fixunskfdi");
18598 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "__floatsikf");
18599 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "__floatunsikf");
18600 set_conv_libfunc (sfloat_optab
, mode
, DImode
, "__floatdikf");
18601 set_conv_libfunc (ufloat_optab
, mode
, DImode
, "__floatundikf");
18603 if (TARGET_POWERPC64
)
18605 set_conv_libfunc (sfix_optab
, TImode
, mode
, "__fixkfti");
18606 set_conv_libfunc (ufix_optab
, TImode
, mode
, "__fixunskfti");
18607 set_conv_libfunc (sfloat_optab
, mode
, TImode
, "__floattikf");
18608 set_conv_libfunc (ufloat_optab
, mode
, TImode
, "__floatuntikf");
18614 set_optab_libfunc (add_optab
, mode
, "_q_add");
18615 set_optab_libfunc (sub_optab
, mode
, "_q_sub");
18616 set_optab_libfunc (neg_optab
, mode
, "_q_neg");
18617 set_optab_libfunc (smul_optab
, mode
, "_q_mul");
18618 set_optab_libfunc (sdiv_optab
, mode
, "_q_div");
18619 if (TARGET_PPC_GPOPT
)
18620 set_optab_libfunc (sqrt_optab
, mode
, "_q_sqrt");
18622 set_optab_libfunc (eq_optab
, mode
, "_q_feq");
18623 set_optab_libfunc (ne_optab
, mode
, "_q_fne");
18624 set_optab_libfunc (gt_optab
, mode
, "_q_fgt");
18625 set_optab_libfunc (ge_optab
, mode
, "_q_fge");
18626 set_optab_libfunc (lt_optab
, mode
, "_q_flt");
18627 set_optab_libfunc (le_optab
, mode
, "_q_fle");
18629 set_conv_libfunc (sext_optab
, mode
, SFmode
, "_q_stoq");
18630 set_conv_libfunc (sext_optab
, mode
, DFmode
, "_q_dtoq");
18631 set_conv_libfunc (trunc_optab
, SFmode
, mode
, "_q_qtos");
18632 set_conv_libfunc (trunc_optab
, DFmode
, mode
, "_q_qtod");
18633 set_conv_libfunc (sfix_optab
, SImode
, mode
, "_q_qtoi");
18634 set_conv_libfunc (ufix_optab
, SImode
, mode
, "_q_qtou");
18635 set_conv_libfunc (sfloat_optab
, mode
, SImode
, "_q_itoq");
18636 set_conv_libfunc (ufloat_optab
, mode
, SImode
, "_q_utoq");
18641 rs6000_init_libfuncs (void)
18643 /* __float128 support. */
18644 if (TARGET_FLOAT128_TYPE
)
18646 init_float128_ibm (IFmode
);
18647 init_float128_ieee (KFmode
);
18650 /* AIX/Darwin/64-bit Linux quad floating point routines. */
18651 if (TARGET_LONG_DOUBLE_128
)
18653 if (!TARGET_IEEEQUAD
)
18654 init_float128_ibm (TFmode
);
18656 /* IEEE 128-bit including 32-bit SVR4 quad floating point routines. */
18658 init_float128_ieee (TFmode
);
18663 /* Expand a block clear operation, and return 1 if successful. Return 0
18664 if we should let the compiler generate normal code.
18666 operands[0] is the destination
18667 operands[1] is the length
18668 operands[3] is the alignment */
18671 expand_block_clear (rtx operands
[])
18673 rtx orig_dest
= operands
[0];
18674 rtx bytes_rtx
= operands
[1];
18675 rtx align_rtx
= operands
[3];
18676 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
18677 HOST_WIDE_INT align
;
18678 HOST_WIDE_INT bytes
;
18683 /* If this is not a fixed size move, just call memcpy */
18687 /* This must be a fixed size alignment */
18688 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
18689 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
18691 /* Anything to clear? */
18692 bytes
= INTVAL (bytes_rtx
);
18696 /* Use the builtin memset after a point, to avoid huge code bloat.
18697 When optimize_size, avoid any significant code bloat; calling
18698 memset is about 4 instructions, so allow for one instruction to
18699 load zero and three to do clearing. */
18700 if (TARGET_ALTIVEC
&& align
>= 128)
18702 else if (TARGET_POWERPC64
&& (align
>= 64 || !STRICT_ALIGNMENT
))
18704 else if (TARGET_SPE
&& align
>= 64)
18709 if (optimize_size
&& bytes
> 3 * clear_step
)
18711 if (! optimize_size
&& bytes
> 8 * clear_step
)
18714 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
18716 machine_mode mode
= BLKmode
;
18719 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
18724 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
18729 else if (bytes
>= 8 && TARGET_POWERPC64
18730 && (align
>= 64 || !STRICT_ALIGNMENT
))
18734 if (offset
== 0 && align
< 64)
18738 /* If the address form is reg+offset with offset not a
18739 multiple of four, reload into reg indirect form here
18740 rather than waiting for reload. This way we get one
18741 reload, not one per store. */
18742 addr
= XEXP (orig_dest
, 0);
18743 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
18744 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
18745 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
18747 addr
= copy_addr_to_reg (addr
);
18748 orig_dest
= replace_equiv_address (orig_dest
, addr
);
18752 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
18753 { /* move 4 bytes */
18757 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
18758 { /* move 2 bytes */
18762 else /* move 1 byte at a time */
18768 dest
= adjust_address (orig_dest
, mode
, offset
);
18770 emit_move_insn (dest
, CONST0_RTX (mode
));
18776 /* Emit a potentially record-form instruction, setting DST from SRC.
18777 If DOT is 0, that is all; otherwise, set CCREG to the result of the
18778 signed comparison of DST with zero. If DOT is 1, the generated RTL
18779 doesn't care about the DST result; if DOT is 2, it does. If CCREG
18780 is CR0 do a single dot insn (as a PARALLEL); otherwise, do a SET and
18781 a separate COMPARE. */
18784 rs6000_emit_dot_insn (rtx dst
, rtx src
, int dot
, rtx ccreg
)
18788 emit_move_insn (dst
, src
);
18792 if (cc_reg_not_cr0_operand (ccreg
, CCmode
))
18794 emit_move_insn (dst
, src
);
18795 emit_move_insn (ccreg
, gen_rtx_COMPARE (CCmode
, dst
, const0_rtx
));
18799 rtx ccset
= gen_rtx_SET (ccreg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
));
18802 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, dst
);
18803 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, clobber
)));
18807 rtx set
= gen_rtx_SET (dst
, src
);
18808 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, ccset
, set
)));
18813 /* Figure out the correct instructions to generate to load data for
18814 block compare. MODE is used for the read from memory, and
18815 data is zero extended if REG is wider than MODE. If LE code
18816 is being generated, bswap loads are used.
18818 REG is the destination register to move the data into.
18819 MEM is the memory block being read.
18820 MODE is the mode of memory to use for the read. */
18822 do_load_for_compare (rtx reg
, rtx mem
, machine_mode mode
)
18824 switch (GET_MODE (reg
))
18830 emit_insn (gen_zero_extendqidi2 (reg
, mem
));
18835 if (!BYTES_BIG_ENDIAN
)
18837 src
= gen_reg_rtx (HImode
);
18838 emit_insn (gen_bswaphi2 (src
, mem
));
18840 emit_insn (gen_zero_extendhidi2 (reg
, src
));
18846 if (!BYTES_BIG_ENDIAN
)
18848 src
= gen_reg_rtx (SImode
);
18849 emit_insn (gen_bswapsi2 (src
, mem
));
18851 emit_insn (gen_zero_extendsidi2 (reg
, src
));
18855 if (!BYTES_BIG_ENDIAN
)
18856 emit_insn (gen_bswapdi2 (reg
, mem
));
18858 emit_insn (gen_movdi (reg
, mem
));
18861 gcc_unreachable ();
18869 emit_insn (gen_zero_extendqisi2 (reg
, mem
));
18874 if (!BYTES_BIG_ENDIAN
)
18876 src
= gen_reg_rtx (HImode
);
18877 emit_insn (gen_bswaphi2 (src
, mem
));
18879 emit_insn (gen_zero_extendhisi2 (reg
, src
));
18883 if (!BYTES_BIG_ENDIAN
)
18884 emit_insn (gen_bswapsi2 (reg
, mem
));
18886 emit_insn (gen_movsi (reg
, mem
));
18889 /* DImode is larger than the destination reg so is not expected. */
18890 gcc_unreachable ();
18893 gcc_unreachable ();
18897 gcc_unreachable ();
18902 /* Select the mode to be used for reading the next chunk of bytes
18905 OFFSET is the current read offset from the beginning of the block.
18906 BYTES is the number of bytes remaining to be read.
18907 ALIGN is the minimum alignment of the memory blocks being compared in bytes.
18908 WORD_MODE_OK indicates using WORD_MODE is allowed, else SImode is
18909 the largest allowable mode. */
18910 static machine_mode
18911 select_block_compare_mode (HOST_WIDE_INT offset
, HOST_WIDE_INT bytes
,
18912 HOST_WIDE_INT align
, bool word_mode_ok
)
18914 /* First see if we can do a whole load unit
18915 as that will be more efficient than a larger load + shift. */
18917 /* If big, use biggest chunk.
18918 If exactly chunk size, use that size.
18919 If remainder can be done in one piece with shifting, do that.
18920 Do largest chunk possible without violating alignment rules. */
18922 /* The most we can read without potential page crossing. */
18923 HOST_WIDE_INT maxread
= ROUND_UP (bytes
, align
);
18925 if (word_mode_ok
&& bytes
>= UNITS_PER_WORD
)
18927 else if (bytes
== GET_MODE_SIZE (SImode
))
18929 else if (bytes
== GET_MODE_SIZE (HImode
))
18931 else if (bytes
== GET_MODE_SIZE (QImode
))
18933 else if (bytes
< GET_MODE_SIZE (SImode
)
18934 && offset
>= GET_MODE_SIZE (SImode
) - bytes
)
18935 /* This matches the case were we have SImode and 3 bytes
18936 and offset >= 1 and permits us to move back one and overlap
18937 with the previous read, thus avoiding having to shift
18938 unwanted bytes off of the input. */
18940 else if (word_mode_ok
&& bytes
< UNITS_PER_WORD
18941 && offset
>= UNITS_PER_WORD
-bytes
)
18942 /* Similarly, if we can use DImode it will get matched here and
18943 can do an overlapping read that ends at the end of the block. */
18945 else if (word_mode_ok
&& maxread
>= UNITS_PER_WORD
)
18946 /* It is safe to do all remaining in one load of largest size,
18947 possibly with a shift to get rid of unwanted bytes. */
18949 else if (maxread
>= GET_MODE_SIZE (SImode
))
18950 /* It is safe to do all remaining in one SImode load,
18951 possibly with a shift to get rid of unwanted bytes. */
18953 else if (bytes
> GET_MODE_SIZE (SImode
))
18955 else if (bytes
> GET_MODE_SIZE (HImode
))
18958 /* final fallback is do one byte */
18962 /* Compute the alignment of pointer+OFFSET where the original alignment
18963 of pointer was BASE_ALIGN. */
18964 static HOST_WIDE_INT
18965 compute_current_alignment (HOST_WIDE_INT base_align
, HOST_WIDE_INT offset
)
18969 return min (base_align
, offset
& -offset
);
18972 /* Expand a block compare operation, and return true if successful.
18973 Return false if we should let the compiler generate normal code,
18974 probably a memcmp call.
18976 OPERANDS[0] is the target (result).
18977 OPERANDS[1] is the first source.
18978 OPERANDS[2] is the second source.
18979 OPERANDS[3] is the length.
18980 OPERANDS[4] is the alignment. */
18982 expand_block_compare (rtx operands
[])
18984 rtx target
= operands
[0];
18985 rtx orig_src1
= operands
[1];
18986 rtx orig_src2
= operands
[2];
18987 rtx bytes_rtx
= operands
[3];
18988 rtx align_rtx
= operands
[4];
18989 HOST_WIDE_INT cmp_bytes
= 0;
18990 rtx src1
= orig_src1
;
18991 rtx src2
= orig_src2
;
18993 /* If this is not a fixed size compare, just call memcmp */
18994 if (!CONST_INT_P (bytes_rtx
))
18997 /* This must be a fixed size alignment */
18998 if (!CONST_INT_P (align_rtx
))
19001 int base_align
= INTVAL (align_rtx
) / BITS_PER_UNIT
;
19003 /* SLOW_UNALIGNED_ACCESS -- don't do unaligned stuff */
19004 if (SLOW_UNALIGNED_ACCESS (word_mode
, MEM_ALIGN (orig_src1
))
19005 || SLOW_UNALIGNED_ACCESS (word_mode
, MEM_ALIGN (orig_src2
)))
19008 gcc_assert (GET_MODE (target
) == SImode
);
19010 /* Anything to move? */
19011 HOST_WIDE_INT bytes
= INTVAL (bytes_rtx
);
19015 /* The code generated for p7 and older is not faster than glibc
19016 memcmp if alignment is small and length is not short, so bail
19017 out to avoid those conditions. */
19018 if (!TARGET_EFFICIENT_OVERLAPPING_UNALIGNED
19019 && ((base_align
== 1 && bytes
> 16)
19020 || (base_align
== 2 && bytes
> 32)))
19023 rtx tmp_reg_src1
= gen_reg_rtx (word_mode
);
19024 rtx tmp_reg_src2
= gen_reg_rtx (word_mode
);
19026 /* If we have an LE target without ldbrx and word_mode is DImode,
19027 then we must avoid using word_mode. */
19028 int word_mode_ok
= !(!BYTES_BIG_ENDIAN
&& !TARGET_LDBRX
19029 && word_mode
== DImode
);
19031 /* Strategy phase. How many ops will this take and should we expand it? */
19034 machine_mode load_mode
=
19035 select_block_compare_mode (offset
, bytes
, base_align
, word_mode_ok
);
19036 int load_mode_size
= GET_MODE_SIZE (load_mode
);
19038 /* We don't want to generate too much code. */
19039 if (ROUND_UP (bytes
, load_mode_size
) / load_mode_size
19040 > rs6000_block_compare_inline_limit
)
19043 bool generate_6432_conversion
= false;
19044 rtx convert_label
= NULL
;
19045 rtx final_label
= NULL
;
19047 /* Example of generated code for 11 bytes aligned 1 byte:
19059 .L8: # convert_label
19065 We start off with DImode and have a compare/branch to something
19066 with a smaller mode then we will need a block with the DI->SI conversion
19067 that may or may not be executed. */
19071 int align
= compute_current_alignment (base_align
, offset
);
19072 if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED
)
19073 load_mode
= select_block_compare_mode (offset
, bytes
, align
,
19076 load_mode
= select_block_compare_mode (0, bytes
, align
, word_mode_ok
);
19077 load_mode_size
= GET_MODE_SIZE (load_mode
);
19078 if (bytes
>= load_mode_size
)
19079 cmp_bytes
= load_mode_size
;
19080 else if (TARGET_EFFICIENT_OVERLAPPING_UNALIGNED
)
19082 /* Move this load back so it doesn't go past the end.
19083 P8/P9 can do this efficiently. */
19084 int extra_bytes
= load_mode_size
- bytes
;
19086 if (extra_bytes
< offset
)
19088 offset
-= extra_bytes
;
19089 cmp_bytes
= load_mode_size
;
19094 /* P7 and earlier can't do the overlapping load trick fast,
19095 so this forces a non-overlapping load and a shift to get
19096 rid of the extra bytes. */
19099 src1
= adjust_address (orig_src1
, load_mode
, offset
);
19100 src2
= adjust_address (orig_src2
, load_mode
, offset
);
19102 if (!REG_P (XEXP (src1
, 0)))
19104 rtx src1_reg
= copy_addr_to_reg (XEXP (src1
, 0));
19105 src1
= replace_equiv_address (src1
, src1_reg
);
19107 set_mem_size (src1
, cmp_bytes
);
19109 if (!REG_P (XEXP (src2
, 0)))
19111 rtx src2_reg
= copy_addr_to_reg (XEXP (src2
, 0));
19112 src2
= replace_equiv_address (src2
, src2_reg
);
19114 set_mem_size (src2
, cmp_bytes
);
19116 do_load_for_compare (tmp_reg_src1
, src1
, load_mode
);
19117 do_load_for_compare (tmp_reg_src2
, src2
, load_mode
);
19119 if (cmp_bytes
< load_mode_size
)
19121 /* Shift unneeded bytes off. */
19122 rtx sh
= GEN_INT (BITS_PER_UNIT
* (load_mode_size
- cmp_bytes
));
19123 if (word_mode
== DImode
)
19125 emit_insn (gen_lshrdi3 (tmp_reg_src1
, tmp_reg_src1
, sh
));
19126 emit_insn (gen_lshrdi3 (tmp_reg_src2
, tmp_reg_src2
, sh
));
19130 emit_insn (gen_lshrsi3 (tmp_reg_src1
, tmp_reg_src1
, sh
));
19131 emit_insn (gen_lshrsi3 (tmp_reg_src2
, tmp_reg_src2
, sh
));
19135 /* We previously did a block that need 64->32 conversion but
19136 the current block does not, so a label is needed to jump
19138 if (generate_6432_conversion
&& !final_label
19139 && GET_MODE_SIZE (GET_MODE (target
)) >= load_mode_size
)
19140 final_label
= gen_label_rtx ();
19142 /* Do we need a 64->32 conversion block? */
19143 int remain
= bytes
- cmp_bytes
;
19144 if (GET_MODE_SIZE (GET_MODE (target
)) < GET_MODE_SIZE (load_mode
))
19146 generate_6432_conversion
= true;
19147 if (remain
> 0 && !convert_label
)
19148 convert_label
= gen_label_rtx ();
19151 if (GET_MODE_SIZE (GET_MODE (target
)) >= GET_MODE_SIZE (load_mode
))
19153 /* Target is larger than load size so we don't need to
19154 reduce result size. */
19157 /* This is not the last block, branch to the end if the result
19158 of this subtract is not zero. */
19160 final_label
= gen_label_rtx ();
19161 rtx fin_ref
= gen_rtx_LABEL_REF (VOIDmode
, final_label
);
19162 rtx cond
= gen_reg_rtx (CCmode
);
19163 rtx tmp
= gen_rtx_MINUS (word_mode
, tmp_reg_src1
, tmp_reg_src2
);
19164 rs6000_emit_dot_insn (tmp_reg_src2
, tmp
, 2, cond
);
19165 emit_insn (gen_movsi (target
, gen_lowpart (SImode
, tmp_reg_src2
)));
19166 rtx ne_rtx
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19167 rtx ifelse
= gen_rtx_IF_THEN_ELSE (VOIDmode
, ne_rtx
,
19169 rtx j
= emit_jump_insn (gen_rtx_SET (pc_rtx
, ifelse
));
19170 JUMP_LABEL (j
) = final_label
;
19171 LABEL_NUSES (final_label
) += 1;
19175 if (word_mode
== DImode
)
19177 emit_insn (gen_subdi3 (tmp_reg_src2
, tmp_reg_src1
,
19179 emit_insn (gen_movsi (target
,
19180 gen_lowpart (SImode
, tmp_reg_src2
)));
19183 emit_insn (gen_subsi3 (target
, tmp_reg_src1
, tmp_reg_src2
));
19187 rtx fin_ref
= gen_rtx_LABEL_REF (VOIDmode
, final_label
);
19188 rtx j
= emit_jump_insn (gen_rtx_SET (pc_rtx
, fin_ref
));
19189 JUMP_LABEL(j
) = final_label
;
19190 LABEL_NUSES (final_label
) += 1;
19197 generate_6432_conversion
= true;
19200 if (!convert_label
)
19201 convert_label
= gen_label_rtx ();
19203 /* Compare to zero and branch to convert_label if not zero. */
19204 rtx cvt_ref
= gen_rtx_LABEL_REF (VOIDmode
, convert_label
);
19205 rtx cond
= gen_reg_rtx (CCmode
);
19206 rtx tmp
= gen_rtx_MINUS (DImode
, tmp_reg_src1
, tmp_reg_src2
);
19207 rs6000_emit_dot_insn (tmp_reg_src2
, tmp
, 2, cond
);
19208 rtx ne_rtx
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19209 rtx ifelse
= gen_rtx_IF_THEN_ELSE (VOIDmode
, ne_rtx
,
19211 rtx j
= emit_jump_insn (gen_rtx_SET (pc_rtx
, ifelse
));
19212 JUMP_LABEL(j
) = convert_label
;
19213 LABEL_NUSES (convert_label
) += 1;
19217 /* Just do the subtract. Since this is the last block the
19218 convert code will be generated immediately following. */
19219 emit_insn (gen_subdi3 (tmp_reg_src2
, tmp_reg_src1
,
19224 offset
+= cmp_bytes
;
19225 bytes
-= cmp_bytes
;
19228 if (generate_6432_conversion
)
19231 emit_label (convert_label
);
19233 /* We need to produce DI result from sub, then convert to target SI
19234 while maintaining <0 / ==0 / >0 properties.
19235 Segher's sequence: cntlzd 3,3 ; addi 3,3,-1 ; xori 3,3,63 */
19236 emit_insn (gen_clzdi2 (tmp_reg_src2
, tmp_reg_src2
));
19237 emit_insn (gen_adddi3 (tmp_reg_src2
, tmp_reg_src2
, GEN_INT (-1)));
19238 emit_insn (gen_xordi3 (tmp_reg_src2
, tmp_reg_src2
, GEN_INT (63)));
19239 emit_insn (gen_movsi (target
, gen_lowpart (SImode
, tmp_reg_src2
)));
19243 emit_label (final_label
);
19245 gcc_assert (bytes
== 0);
19250 /* Expand a block move operation, and return 1 if successful. Return 0
19251 if we should let the compiler generate normal code.
19253 operands[0] is the destination
19254 operands[1] is the source
19255 operands[2] is the length
19256 operands[3] is the alignment */
19258 #define MAX_MOVE_REG 4
19261 expand_block_move (rtx operands
[])
19263 rtx orig_dest
= operands
[0];
19264 rtx orig_src
= operands
[1];
19265 rtx bytes_rtx
= operands
[2];
19266 rtx align_rtx
= operands
[3];
19267 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
19272 rtx stores
[MAX_MOVE_REG
];
19275 /* If this is not a fixed size move, just call memcpy */
19279 /* This must be a fixed size alignment */
19280 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
19281 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
19283 /* Anything to move? */
19284 bytes
= INTVAL (bytes_rtx
);
19288 if (bytes
> rs6000_block_move_inline_limit
)
19291 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
19294 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
19295 rtx (*mov
) (rtx
, rtx
);
19297 machine_mode mode
= BLKmode
;
19300 /* Altivec first, since it will be faster than a string move
19301 when it applies, and usually not significantly larger. */
19302 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
19306 gen_func
.mov
= gen_movv4si
;
19308 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
19312 gen_func
.mov
= gen_movv2si
;
19314 else if (TARGET_STRING
19315 && bytes
> 24 /* move up to 32 bytes at a time */
19321 && ! fixed_regs
[10]
19322 && ! fixed_regs
[11]
19323 && ! fixed_regs
[12])
19325 move_bytes
= (bytes
> 32) ? 32 : bytes
;
19326 gen_func
.movmemsi
= gen_movmemsi_8reg
;
19328 else if (TARGET_STRING
19329 && bytes
> 16 /* move up to 24 bytes at a time */
19335 && ! fixed_regs
[10])
19337 move_bytes
= (bytes
> 24) ? 24 : bytes
;
19338 gen_func
.movmemsi
= gen_movmemsi_6reg
;
19340 else if (TARGET_STRING
19341 && bytes
> 8 /* move up to 16 bytes at a time */
19345 && ! fixed_regs
[8])
19347 move_bytes
= (bytes
> 16) ? 16 : bytes
;
19348 gen_func
.movmemsi
= gen_movmemsi_4reg
;
19350 else if (bytes
>= 8 && TARGET_POWERPC64
19351 && (align
>= 64 || !STRICT_ALIGNMENT
))
19355 gen_func
.mov
= gen_movdi
;
19356 if (offset
== 0 && align
< 64)
19360 /* If the address form is reg+offset with offset not a
19361 multiple of four, reload into reg indirect form here
19362 rather than waiting for reload. This way we get one
19363 reload, not one per load and/or store. */
19364 addr
= XEXP (orig_dest
, 0);
19365 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
19366 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
19367 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
19369 addr
= copy_addr_to_reg (addr
);
19370 orig_dest
= replace_equiv_address (orig_dest
, addr
);
19372 addr
= XEXP (orig_src
, 0);
19373 if ((GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
19374 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
19375 && (INTVAL (XEXP (addr
, 1)) & 3) != 0)
19377 addr
= copy_addr_to_reg (addr
);
19378 orig_src
= replace_equiv_address (orig_src
, addr
);
19382 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
19383 { /* move up to 8 bytes at a time */
19384 move_bytes
= (bytes
> 8) ? 8 : bytes
;
19385 gen_func
.movmemsi
= gen_movmemsi_2reg
;
19387 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
19388 { /* move 4 bytes */
19391 gen_func
.mov
= gen_movsi
;
19393 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
19394 { /* move 2 bytes */
19397 gen_func
.mov
= gen_movhi
;
19399 else if (TARGET_STRING
&& bytes
> 1)
19400 { /* move up to 4 bytes at a time */
19401 move_bytes
= (bytes
> 4) ? 4 : bytes
;
19402 gen_func
.movmemsi
= gen_movmemsi_1reg
;
19404 else /* move 1 byte at a time */
19408 gen_func
.mov
= gen_movqi
;
19411 src
= adjust_address (orig_src
, mode
, offset
);
19412 dest
= adjust_address (orig_dest
, mode
, offset
);
19414 if (mode
!= BLKmode
)
19416 rtx tmp_reg
= gen_reg_rtx (mode
);
19418 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
19419 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
19422 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
19425 for (i
= 0; i
< num_reg
; i
++)
19426 emit_insn (stores
[i
]);
19430 if (mode
== BLKmode
)
19432 /* Move the address into scratch registers. The movmemsi
19433 patterns require zero offset. */
19434 if (!REG_P (XEXP (src
, 0)))
19436 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
19437 src
= replace_equiv_address (src
, src_reg
);
19439 set_mem_size (src
, move_bytes
);
19441 if (!REG_P (XEXP (dest
, 0)))
19443 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
19444 dest
= replace_equiv_address (dest
, dest_reg
);
19446 set_mem_size (dest
, move_bytes
);
19448 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
19449 GEN_INT (move_bytes
& 31),
19458 /* Return a string to perform a load_multiple operation.
19459 operands[0] is the vector.
19460 operands[1] is the source address.
19461 operands[2] is the first destination register. */
19464 rs6000_output_load_multiple (rtx operands
[3])
19466 /* We have to handle the case where the pseudo used to contain the address
19467 is assigned to one of the output registers. */
19469 int words
= XVECLEN (operands
[0], 0);
19472 if (XVECLEN (operands
[0], 0) == 1)
19473 return "lwz %2,0(%1)";
19475 for (i
= 0; i
< words
; i
++)
19476 if (refers_to_regno_p (REGNO (operands
[2]) + i
, operands
[1]))
19480 xop
[0] = GEN_INT (4 * (words
-1));
19481 xop
[1] = operands
[1];
19482 xop
[2] = operands
[2];
19483 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
19488 xop
[0] = GEN_INT (4 * (words
-1));
19489 xop
[1] = operands
[1];
19490 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
19491 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
19496 for (j
= 0; j
< words
; j
++)
19499 xop
[0] = GEN_INT (j
* 4);
19500 xop
[1] = operands
[1];
19501 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
19502 output_asm_insn ("lwz %2,%0(%1)", xop
);
19504 xop
[0] = GEN_INT (i
* 4);
19505 xop
[1] = operands
[1];
19506 output_asm_insn ("lwz %1,%0(%1)", xop
);
19511 return "lswi %2,%1,%N0";
19515 /* A validation routine: say whether CODE, a condition code, and MODE
19516 match. The other alternatives either don't make sense or should
19517 never be generated. */
19520 validate_condition_mode (enum rtx_code code
, machine_mode mode
)
19522 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
19523 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
19524 && GET_MODE_CLASS (mode
) == MODE_CC
);
19526 /* These don't make sense. */
19527 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
19528 || mode
!= CCUNSmode
);
19530 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
19531 || mode
== CCUNSmode
);
19533 gcc_assert (mode
== CCFPmode
19534 || (code
!= ORDERED
&& code
!= UNORDERED
19535 && code
!= UNEQ
&& code
!= LTGT
19536 && code
!= UNGT
&& code
!= UNLT
19537 && code
!= UNGE
&& code
!= UNLE
));
19539 /* These should never be generated except for
19540 flag_finite_math_only. */
19541 gcc_assert (mode
!= CCFPmode
19542 || flag_finite_math_only
19543 || (code
!= LE
&& code
!= GE
19544 && code
!= UNEQ
&& code
!= LTGT
19545 && code
!= UNGT
&& code
!= UNLT
));
19547 /* These are invalid; the information is not there. */
19548 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
19552 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm,
19553 rldicl, rldicr, or rldic instruction in mode MODE. If so, if E is
19554 not zero, store there the bit offset (counted from the right) where
19555 the single stretch of 1 bits begins; and similarly for B, the bit
19556 offset where it ends. */
19559 rs6000_is_valid_mask (rtx mask
, int *b
, int *e
, machine_mode mode
)
19561 unsigned HOST_WIDE_INT val
= INTVAL (mask
);
19562 unsigned HOST_WIDE_INT bit
;
19564 int n
= GET_MODE_PRECISION (mode
);
19566 if (mode
!= DImode
&& mode
!= SImode
)
19569 if (INTVAL (mask
) >= 0)
19572 ne
= exact_log2 (bit
);
19573 nb
= exact_log2 (val
+ bit
);
19575 else if (val
+ 1 == 0)
19584 nb
= exact_log2 (bit
);
19585 ne
= exact_log2 (val
+ bit
);
19590 ne
= exact_log2 (bit
);
19591 if (val
+ bit
== 0)
19599 if (nb
< 0 || ne
< 0 || nb
>= n
|| ne
>= n
)
19610 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwinm, rldicl,
19611 or rldicr instruction, to implement an AND with it in mode MODE. */
19614 rs6000_is_valid_and_mask (rtx mask
, machine_mode mode
)
19618 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
19621 /* For DImode, we need a rldicl, rldicr, or a rlwinm with mask that
19623 if (mode
== DImode
)
19624 return (ne
== 0 || nb
== 63 || (nb
< 32 && ne
<= nb
));
19626 /* For SImode, rlwinm can do everything. */
19627 if (mode
== SImode
)
19628 return (nb
< 32 && ne
< 32);
19633 /* Return the instruction template for an AND with mask in mode MODE, with
19634 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19637 rs6000_insn_for_and_mask (machine_mode mode
, rtx
*operands
, bool dot
)
19641 if (!rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
))
19642 gcc_unreachable ();
19644 if (mode
== DImode
&& ne
== 0)
19646 operands
[3] = GEN_INT (63 - nb
);
19648 return "rldicl. %0,%1,0,%3";
19649 return "rldicl %0,%1,0,%3";
19652 if (mode
== DImode
&& nb
== 63)
19654 operands
[3] = GEN_INT (63 - ne
);
19656 return "rldicr. %0,%1,0,%3";
19657 return "rldicr %0,%1,0,%3";
19660 if (nb
< 32 && ne
< 32)
19662 operands
[3] = GEN_INT (31 - nb
);
19663 operands
[4] = GEN_INT (31 - ne
);
19665 return "rlwinm. %0,%1,0,%3,%4";
19666 return "rlwinm %0,%1,0,%3,%4";
19669 gcc_unreachable ();
19672 /* Return whether MASK (a CONST_INT) is a valid mask for any rlw[i]nm,
19673 rld[i]cl, rld[i]cr, or rld[i]c instruction, to implement an AND with
19674 shift SHIFT (a ROTATE, ASHIFT, or LSHIFTRT) in mode MODE. */
19677 rs6000_is_valid_shift_mask (rtx mask
, rtx shift
, machine_mode mode
)
19681 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
19684 int n
= GET_MODE_PRECISION (mode
);
19687 if (CONST_INT_P (XEXP (shift
, 1)))
19689 sh
= INTVAL (XEXP (shift
, 1));
19690 if (sh
< 0 || sh
>= n
)
19694 rtx_code code
= GET_CODE (shift
);
19696 /* Convert any shift by 0 to a rotate, to simplify below code. */
19700 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19701 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
19703 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
19709 /* DImode rotates need rld*. */
19710 if (mode
== DImode
&& code
== ROTATE
)
19711 return (nb
== 63 || ne
== 0 || ne
== sh
);
19713 /* SImode rotates need rlw*. */
19714 if (mode
== SImode
&& code
== ROTATE
)
19715 return (nb
< 32 && ne
< 32 && sh
< 32);
19717 /* Wrap-around masks are only okay for rotates. */
19721 /* Variable shifts are only okay for rotates. */
19725 /* Don't allow ASHIFT if the mask is wrong for that. */
19726 if (code
== ASHIFT
&& ne
< sh
)
19729 /* If we can do it with an rlw*, we can do it. Don't allow LSHIFTRT
19730 if the mask is wrong for that. */
19731 if (nb
< 32 && ne
< 32 && sh
< 32
19732 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
19735 /* If we can do it with an rld*, we can do it. Don't allow LSHIFTRT
19736 if the mask is wrong for that. */
19737 if (code
== LSHIFTRT
)
19739 if (nb
== 63 || ne
== 0 || ne
== sh
)
19740 return !(code
== LSHIFTRT
&& nb
>= sh
);
19745 /* Return the instruction template for a shift with mask in mode MODE, with
19746 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19749 rs6000_insn_for_shift_mask (machine_mode mode
, rtx
*operands
, bool dot
)
19753 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
19754 gcc_unreachable ();
19756 if (mode
== DImode
&& ne
== 0)
19758 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
19759 operands
[2] = GEN_INT (64 - INTVAL (operands
[2]));
19760 operands
[3] = GEN_INT (63 - nb
);
19762 return "rld%I2cl. %0,%1,%2,%3";
19763 return "rld%I2cl %0,%1,%2,%3";
19766 if (mode
== DImode
&& nb
== 63)
19768 operands
[3] = GEN_INT (63 - ne
);
19770 return "rld%I2cr. %0,%1,%2,%3";
19771 return "rld%I2cr %0,%1,%2,%3";
19775 && GET_CODE (operands
[4]) != LSHIFTRT
19776 && CONST_INT_P (operands
[2])
19777 && ne
== INTVAL (operands
[2]))
19779 operands
[3] = GEN_INT (63 - nb
);
19781 return "rld%I2c. %0,%1,%2,%3";
19782 return "rld%I2c %0,%1,%2,%3";
19785 if (nb
< 32 && ne
< 32)
19787 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
19788 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
19789 operands
[3] = GEN_INT (31 - nb
);
19790 operands
[4] = GEN_INT (31 - ne
);
19791 /* This insn can also be a 64-bit rotate with mask that really makes
19792 it just a shift right (with mask); the %h below are to adjust for
19793 that situation (shift count is >= 32 in that case). */
19795 return "rlw%I2nm. %0,%1,%h2,%3,%4";
19796 return "rlw%I2nm %0,%1,%h2,%3,%4";
19799 gcc_unreachable ();
19802 /* Return whether MASK (a CONST_INT) is a valid mask for any rlwimi or
19803 rldimi instruction, to implement an insert with shift SHIFT (a ROTATE,
19804 ASHIFT, or LSHIFTRT) in mode MODE. */
19807 rs6000_is_valid_insert_mask (rtx mask
, rtx shift
, machine_mode mode
)
19811 if (!rs6000_is_valid_mask (mask
, &nb
, &ne
, mode
))
19814 int n
= GET_MODE_PRECISION (mode
);
19816 int sh
= INTVAL (XEXP (shift
, 1));
19817 if (sh
< 0 || sh
>= n
)
19820 rtx_code code
= GET_CODE (shift
);
19822 /* Convert any shift by 0 to a rotate, to simplify below code. */
19826 /* Convert rotate to simple shift if we can, to make analysis simpler. */
19827 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& ne
>= sh
)
19829 if (code
== ROTATE
&& sh
>= 0 && nb
>= ne
&& nb
< sh
)
19835 /* DImode rotates need rldimi. */
19836 if (mode
== DImode
&& code
== ROTATE
)
19839 /* SImode rotates need rlwimi. */
19840 if (mode
== SImode
&& code
== ROTATE
)
19841 return (nb
< 32 && ne
< 32 && sh
< 32);
19843 /* Wrap-around masks are only okay for rotates. */
19847 /* Don't allow ASHIFT if the mask is wrong for that. */
19848 if (code
== ASHIFT
&& ne
< sh
)
19851 /* If we can do it with an rlwimi, we can do it. Don't allow LSHIFTRT
19852 if the mask is wrong for that. */
19853 if (nb
< 32 && ne
< 32 && sh
< 32
19854 && !(code
== LSHIFTRT
&& nb
>= 32 - sh
))
19857 /* If we can do it with an rldimi, we can do it. Don't allow LSHIFTRT
19858 if the mask is wrong for that. */
19859 if (code
== LSHIFTRT
)
19862 return !(code
== LSHIFTRT
&& nb
>= sh
);
19867 /* Return the instruction template for an insert with mask in mode MODE, with
19868 operands OPERANDS. If DOT is true, make it a record-form instruction. */
19871 rs6000_insn_for_insert_mask (machine_mode mode
, rtx
*operands
, bool dot
)
19875 if (!rs6000_is_valid_mask (operands
[3], &nb
, &ne
, mode
))
19876 gcc_unreachable ();
19878 /* Prefer rldimi because rlwimi is cracked. */
19879 if (TARGET_POWERPC64
19880 && (!dot
|| mode
== DImode
)
19881 && GET_CODE (operands
[4]) != LSHIFTRT
19882 && ne
== INTVAL (operands
[2]))
19884 operands
[3] = GEN_INT (63 - nb
);
19886 return "rldimi. %0,%1,%2,%3";
19887 return "rldimi %0,%1,%2,%3";
19890 if (nb
< 32 && ne
< 32)
19892 if (GET_CODE (operands
[4]) == LSHIFTRT
&& INTVAL (operands
[2]))
19893 operands
[2] = GEN_INT (32 - INTVAL (operands
[2]));
19894 operands
[3] = GEN_INT (31 - nb
);
19895 operands
[4] = GEN_INT (31 - ne
);
19897 return "rlwimi. %0,%1,%2,%3,%4";
19898 return "rlwimi %0,%1,%2,%3,%4";
19901 gcc_unreachable ();
19904 /* Return whether an AND with C (a CONST_INT) in mode MODE can be done
19905 using two machine instructions. */
19908 rs6000_is_valid_2insn_and (rtx c
, machine_mode mode
)
19910 /* There are two kinds of AND we can handle with two insns:
19911 1) those we can do with two rl* insn;
19914 We do not handle that last case yet. */
19916 /* If there is just one stretch of ones, we can do it. */
19917 if (rs6000_is_valid_mask (c
, NULL
, NULL
, mode
))
19920 /* Otherwise, fill in the lowest "hole"; if we can do the result with
19921 one insn, we can do the whole thing with two. */
19922 unsigned HOST_WIDE_INT val
= INTVAL (c
);
19923 unsigned HOST_WIDE_INT bit1
= val
& -val
;
19924 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
19925 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
19926 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
19927 return rs6000_is_valid_and_mask (GEN_INT (val
+ bit3
- bit2
), mode
);
19930 /* Emit the two insns to do an AND in mode MODE, with operands OPERANDS.
19931 If EXPAND is true, split rotate-and-mask instructions we generate to
19932 their constituent parts as well (this is used during expand); if DOT
19933 is 1, make the last insn a record-form instruction clobbering the
19934 destination GPR and setting the CC reg (from operands[3]); if 2, set
19935 that GPR as well as the CC reg. */
19938 rs6000_emit_2insn_and (machine_mode mode
, rtx
*operands
, bool expand
, int dot
)
19940 gcc_assert (!(expand
&& dot
));
19942 unsigned HOST_WIDE_INT val
= INTVAL (operands
[2]);
19944 /* If it is one stretch of ones, it is DImode; shift left, mask, then
19945 shift right. This generates better code than doing the masks without
19946 shifts, or shifting first right and then left. */
19948 if (rs6000_is_valid_mask (operands
[2], &nb
, &ne
, mode
) && nb
>= ne
)
19950 gcc_assert (mode
== DImode
);
19952 int shift
= 63 - nb
;
19955 rtx tmp1
= gen_reg_rtx (DImode
);
19956 rtx tmp2
= gen_reg_rtx (DImode
);
19957 emit_insn (gen_ashldi3 (tmp1
, operands
[1], GEN_INT (shift
)));
19958 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (val
<< shift
)));
19959 emit_insn (gen_lshrdi3 (operands
[0], tmp2
, GEN_INT (shift
)));
19963 rtx tmp
= gen_rtx_ASHIFT (mode
, operands
[1], GEN_INT (shift
));
19964 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (val
<< shift
));
19965 emit_move_insn (operands
[0], tmp
);
19966 tmp
= gen_rtx_LSHIFTRT (mode
, operands
[0], GEN_INT (shift
));
19967 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
19972 /* Otherwise, make a mask2 that cuts out the lowest "hole", and a mask1
19973 that does the rest. */
19974 unsigned HOST_WIDE_INT bit1
= val
& -val
;
19975 unsigned HOST_WIDE_INT bit2
= (val
+ bit1
) & ~val
;
19976 unsigned HOST_WIDE_INT val1
= (val
+ bit1
) & val
;
19977 unsigned HOST_WIDE_INT bit3
= val1
& -val1
;
19979 unsigned HOST_WIDE_INT mask1
= -bit3
+ bit2
- 1;
19980 unsigned HOST_WIDE_INT mask2
= val
+ bit3
- bit2
;
19982 gcc_assert (rs6000_is_valid_and_mask (GEN_INT (mask2
), mode
));
19984 /* Two "no-rotate"-and-mask instructions, for SImode. */
19985 if (rs6000_is_valid_and_mask (GEN_INT (mask1
), mode
))
19987 gcc_assert (mode
== SImode
);
19989 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
19990 rtx tmp
= gen_rtx_AND (mode
, operands
[1], GEN_INT (mask1
));
19991 emit_move_insn (reg
, tmp
);
19992 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
19993 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
19997 gcc_assert (mode
== DImode
);
19999 /* Two "no-rotate"-and-mask instructions, for DImode: both are rlwinm
20000 insns; we have to do the first in SImode, because it wraps. */
20001 if (mask2
<= 0xffffffff
20002 && rs6000_is_valid_and_mask (GEN_INT (mask1
), SImode
))
20004 rtx reg
= expand
? gen_reg_rtx (mode
) : operands
[0];
20005 rtx tmp
= gen_rtx_AND (SImode
, gen_lowpart (SImode
, operands
[1]),
20007 rtx reg_low
= gen_lowpart (SImode
, reg
);
20008 emit_move_insn (reg_low
, tmp
);
20009 tmp
= gen_rtx_AND (mode
, reg
, GEN_INT (mask2
));
20010 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
20014 /* Two rld* insns: rotate, clear the hole in the middle (which now is
20015 at the top end), rotate back and clear the other hole. */
20016 int right
= exact_log2 (bit3
);
20017 int left
= 64 - right
;
20019 /* Rotate the mask too. */
20020 mask1
= (mask1
>> right
) | ((bit2
- 1) << left
);
20024 rtx tmp1
= gen_reg_rtx (DImode
);
20025 rtx tmp2
= gen_reg_rtx (DImode
);
20026 rtx tmp3
= gen_reg_rtx (DImode
);
20027 emit_insn (gen_rotldi3 (tmp1
, operands
[1], GEN_INT (left
)));
20028 emit_insn (gen_anddi3 (tmp2
, tmp1
, GEN_INT (mask1
)));
20029 emit_insn (gen_rotldi3 (tmp3
, tmp2
, GEN_INT (right
)));
20030 emit_insn (gen_anddi3 (operands
[0], tmp3
, GEN_INT (mask2
)));
20034 rtx tmp
= gen_rtx_ROTATE (mode
, operands
[1], GEN_INT (left
));
20035 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask1
));
20036 emit_move_insn (operands
[0], tmp
);
20037 tmp
= gen_rtx_ROTATE (mode
, operands
[0], GEN_INT (right
));
20038 tmp
= gen_rtx_AND (mode
, tmp
, GEN_INT (mask2
));
20039 rs6000_emit_dot_insn (operands
[0], tmp
, dot
, dot
? operands
[3] : 0);
20043 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
20044 for lfq and stfq insns iff the registers are hard registers. */
20047 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
20049 /* We might have been passed a SUBREG. */
20050 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
20053 /* We might have been passed non floating point registers. */
20054 if (!FP_REGNO_P (REGNO (reg1
))
20055 || !FP_REGNO_P (REGNO (reg2
)))
20058 return (REGNO (reg1
) == REGNO (reg2
) - 1);
20061 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
20062 addr1 and addr2 must be in consecutive memory locations
20063 (addr2 == addr1 + 8). */
20066 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
20069 unsigned int reg1
, reg2
;
20070 int offset1
, offset2
;
20072 /* The mems cannot be volatile. */
20073 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
20076 addr1
= XEXP (mem1
, 0);
20077 addr2
= XEXP (mem2
, 0);
20079 /* Extract an offset (if used) from the first addr. */
20080 if (GET_CODE (addr1
) == PLUS
)
20082 /* If not a REG, return zero. */
20083 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
20087 reg1
= REGNO (XEXP (addr1
, 0));
20088 /* The offset must be constant! */
20089 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
20091 offset1
= INTVAL (XEXP (addr1
, 1));
20094 else if (GET_CODE (addr1
) != REG
)
20098 reg1
= REGNO (addr1
);
20099 /* This was a simple (mem (reg)) expression. Offset is 0. */
20103 /* And now for the second addr. */
20104 if (GET_CODE (addr2
) == PLUS
)
20106 /* If not a REG, return zero. */
20107 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
20111 reg2
= REGNO (XEXP (addr2
, 0));
20112 /* The offset must be constant. */
20113 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
20115 offset2
= INTVAL (XEXP (addr2
, 1));
20118 else if (GET_CODE (addr2
) != REG
)
20122 reg2
= REGNO (addr2
);
20123 /* This was a simple (mem (reg)) expression. Offset is 0. */
20127 /* Both of these must have the same base register. */
20131 /* The offset for the second addr must be 8 more than the first addr. */
20132 if (offset2
!= offset1
+ 8)
20135 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
20142 rs6000_secondary_memory_needed_rtx (machine_mode mode
)
20144 static bool eliminated
= false;
20147 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
20148 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
20151 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
20152 gcc_assert (mem
!= NULL_RTX
);
20156 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
20157 cfun
->machine
->sdmode_stack_slot
= mem
;
20163 if (TARGET_DEBUG_ADDR
)
20165 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
20166 GET_MODE_NAME (mode
));
20168 fprintf (stderr
, "\tNULL_RTX\n");
20176 /* Return the mode to be used for memory when a secondary memory
20177 location is needed. For SDmode values we need to use DDmode, in
20178 all other cases we can use the same mode. */
20180 rs6000_secondary_memory_needed_mode (machine_mode mode
)
20182 if (lra_in_progress
&& mode
== SDmode
)
20188 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
20190 /* Don't walk into types. */
20191 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
20193 *walk_subtrees
= 0;
20197 switch (TREE_CODE (*tp
))
20206 case VIEW_CONVERT_EXPR
:
20207 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
20217 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
20218 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
20219 only work on the traditional altivec registers, note if an altivec register
20222 static enum rs6000_reg_type
20223 register_to_reg_type (rtx reg
, bool *is_altivec
)
20225 HOST_WIDE_INT regno
;
20226 enum reg_class rclass
;
20228 if (GET_CODE (reg
) == SUBREG
)
20229 reg
= SUBREG_REG (reg
);
20232 return NO_REG_TYPE
;
20234 regno
= REGNO (reg
);
20235 if (regno
>= FIRST_PSEUDO_REGISTER
)
20237 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
20238 return PSEUDO_REG_TYPE
;
20240 regno
= true_regnum (reg
);
20241 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
20242 return PSEUDO_REG_TYPE
;
20245 gcc_assert (regno
>= 0);
20247 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
20248 *is_altivec
= true;
20250 rclass
= rs6000_regno_regclass
[regno
];
20251 return reg_class_to_reg_type
[(int)rclass
];
20254 /* Helper function to return the cost of adding a TOC entry address. */
20257 rs6000_secondary_reload_toc_costs (addr_mask_type addr_mask
)
20261 if (TARGET_CMODEL
!= CMODEL_SMALL
)
20262 ret
= ((addr_mask
& RELOAD_REG_OFFSET
) == 0) ? 1 : 2;
20265 ret
= (TARGET_MINIMAL_TOC
) ? 6 : 3;
20270 /* Helper function for rs6000_secondary_reload to determine whether the memory
20271 address (ADDR) with a given register class (RCLASS) and machine mode (MODE)
20272 needs reloading. Return negative if the memory is not handled by the memory
20273 helper functions and to try a different reload method, 0 if no additional
20274 instructions are need, and positive to give the extra cost for the
20278 rs6000_secondary_reload_memory (rtx addr
,
20279 enum reg_class rclass
,
20282 int extra_cost
= 0;
20283 rtx reg
, and_arg
, plus_arg0
, plus_arg1
;
20284 addr_mask_type addr_mask
;
20285 const char *type
= NULL
;
20286 const char *fail_msg
= NULL
;
20288 if (GPR_REG_CLASS_P (rclass
))
20289 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
20291 else if (rclass
== FLOAT_REGS
)
20292 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
20294 else if (rclass
== ALTIVEC_REGS
)
20295 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
20297 /* For the combined VSX_REGS, turn off Altivec AND -16. */
20298 else if (rclass
== VSX_REGS
)
20299 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
]
20300 & ~RELOAD_REG_AND_M16
);
20302 /* If the register allocator hasn't made up its mind yet on the register
20303 class to use, settle on defaults to use. */
20304 else if (rclass
== NO_REGS
)
20306 addr_mask
= (reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
]
20307 & ~RELOAD_REG_AND_M16
);
20309 if ((addr_mask
& RELOAD_REG_MULTIPLE
) != 0)
20310 addr_mask
&= ~(RELOAD_REG_INDEXED
20311 | RELOAD_REG_PRE_INCDEC
20312 | RELOAD_REG_PRE_MODIFY
);
20318 /* If the register isn't valid in this register class, just return now. */
20319 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
20321 if (TARGET_DEBUG_ADDR
)
20324 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
20325 "not valid in class\n",
20326 GET_MODE_NAME (mode
), reg_class_names
[rclass
]);
20333 switch (GET_CODE (addr
))
20335 /* Does the register class supports auto update forms for this mode? We
20336 don't need a scratch register, since the powerpc only supports
20337 PRE_INC, PRE_DEC, and PRE_MODIFY. */
20340 reg
= XEXP (addr
, 0);
20341 if (!base_reg_operand (addr
, GET_MODE (reg
)))
20343 fail_msg
= "no base register #1";
20347 else if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
20355 reg
= XEXP (addr
, 0);
20356 plus_arg1
= XEXP (addr
, 1);
20357 if (!base_reg_operand (reg
, GET_MODE (reg
))
20358 || GET_CODE (plus_arg1
) != PLUS
20359 || !rtx_equal_p (reg
, XEXP (plus_arg1
, 0)))
20361 fail_msg
= "bad PRE_MODIFY";
20365 else if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
20372 /* Do we need to simulate AND -16 to clear the bottom address bits used
20373 in VMX load/stores? Only allow the AND for vector sizes. */
20375 and_arg
= XEXP (addr
, 0);
20376 if (GET_MODE_SIZE (mode
) != 16
20377 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
20378 || INTVAL (XEXP (addr
, 1)) != -16)
20380 fail_msg
= "bad Altivec AND #1";
20384 if (rclass
!= ALTIVEC_REGS
)
20386 if (legitimate_indirect_address_p (and_arg
, false))
20389 else if (legitimate_indexed_address_p (and_arg
, false))
20394 fail_msg
= "bad Altivec AND #2";
20402 /* If this is an indirect address, make sure it is a base register. */
20405 if (!legitimate_indirect_address_p (addr
, false))
20412 /* If this is an indexed address, make sure the register class can handle
20413 indexed addresses for this mode. */
20415 plus_arg0
= XEXP (addr
, 0);
20416 plus_arg1
= XEXP (addr
, 1);
20418 /* (plus (plus (reg) (constant)) (constant)) is generated during
20419 push_reload processing, so handle it now. */
20420 if (GET_CODE (plus_arg0
) == PLUS
&& CONST_INT_P (plus_arg1
))
20422 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
20429 /* (plus (plus (reg) (constant)) (reg)) is also generated during
20430 push_reload processing, so handle it now. */
20431 else if (GET_CODE (plus_arg0
) == PLUS
&& REG_P (plus_arg1
))
20433 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
20436 type
= "indexed #2";
20440 else if (!base_reg_operand (plus_arg0
, GET_MODE (plus_arg0
)))
20442 fail_msg
= "no base register #2";
20446 else if (int_reg_operand (plus_arg1
, GET_MODE (plus_arg1
)))
20448 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0
20449 || !legitimate_indexed_address_p (addr
, false))
20456 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0
20457 && CONST_INT_P (plus_arg1
))
20459 if (!quad_address_offset_p (INTVAL (plus_arg1
)))
20462 type
= "vector d-form offset";
20466 /* Make sure the register class can handle offset addresses. */
20467 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
20469 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
20472 type
= "offset #2";
20478 fail_msg
= "bad PLUS";
20485 /* Quad offsets are restricted and can't handle normal addresses. */
20486 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
20489 type
= "vector d-form lo_sum";
20492 else if (!legitimate_lo_sum_address_p (mode
, addr
, false))
20494 fail_msg
= "bad LO_SUM";
20498 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
20505 /* Static addresses need to create a TOC entry. */
20509 if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
20512 type
= "vector d-form lo_sum #2";
20518 extra_cost
= rs6000_secondary_reload_toc_costs (addr_mask
);
20522 /* TOC references look like offsetable memory. */
20524 if (TARGET_CMODEL
== CMODEL_SMALL
|| XINT (addr
, 1) != UNSPEC_TOCREL
)
20526 fail_msg
= "bad UNSPEC";
20530 else if ((addr_mask
& RELOAD_REG_QUAD_OFFSET
) != 0)
20533 type
= "vector d-form lo_sum #3";
20536 else if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
20539 type
= "toc reference";
20545 fail_msg
= "bad address";
20550 if (TARGET_DEBUG_ADDR
/* && extra_cost != 0 */)
20552 if (extra_cost
< 0)
20554 "rs6000_secondary_reload_memory error: mode = %s, "
20555 "class = %s, addr_mask = '%s', %s\n",
20556 GET_MODE_NAME (mode
),
20557 reg_class_names
[rclass
],
20558 rs6000_debug_addr_mask (addr_mask
, false),
20559 (fail_msg
!= NULL
) ? fail_msg
: "<bad address>");
20563 "rs6000_secondary_reload_memory: mode = %s, class = %s, "
20564 "addr_mask = '%s', extra cost = %d, %s\n",
20565 GET_MODE_NAME (mode
),
20566 reg_class_names
[rclass
],
20567 rs6000_debug_addr_mask (addr_mask
, false),
20569 (type
) ? type
: "<none>");
20577 /* Helper function for rs6000_secondary_reload to return true if a move to a
20578 different register classe is really a simple move. */
20581 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
20582 enum rs6000_reg_type from_type
,
20585 int size
= GET_MODE_SIZE (mode
);
20587 /* Add support for various direct moves available. In this function, we only
20588 look at cases where we don't need any extra registers, and one or more
20589 simple move insns are issued. Originally small integers are not allowed
20590 in FPR/VSX registers. Single precision binary floating is not a simple
20591 move because we need to convert to the single precision memory layout.
20592 The 4-byte SDmode can be moved. TDmode values are disallowed since they
20593 need special direct move handling, which we do not support yet. */
20594 if (TARGET_DIRECT_MOVE
20595 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
20596 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
20598 if (TARGET_POWERPC64
)
20600 /* ISA 2.07: MTVSRD or MVFVSRD. */
20604 /* ISA 3.0: MTVSRDD or MFVSRD + MFVSRLD. */
20605 if (size
== 16 && TARGET_P9_VECTOR
&& mode
!= TDmode
)
20609 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
20610 if (TARGET_VSX_SMALL_INTEGER
&& mode
== SImode
)
20613 /* ISA 2.07: MTVSRWZ or MFVSRWZ. */
20614 if (mode
== SDmode
)
20618 /* Power6+: MFTGPR or MFFGPR. */
20619 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
20620 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
20621 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
20624 /* Move to/from SPR. */
20625 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
20626 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
20627 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
20633 /* Direct move helper function for rs6000_secondary_reload, handle all of the
20634 special direct moves that involve allocating an extra register, return the
20635 insn code of the helper function if there is such a function or
20636 CODE_FOR_nothing if not. */
20639 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
20640 enum rs6000_reg_type from_type
,
20642 secondary_reload_info
*sri
,
20646 enum insn_code icode
= CODE_FOR_nothing
;
20648 int size
= GET_MODE_SIZE (mode
);
20650 if (TARGET_POWERPC64
&& size
== 16)
20652 /* Handle moving 128-bit values from GPRs to VSX point registers on
20653 ISA 2.07 (power8, power9) when running in 64-bit mode using
20654 XXPERMDI to glue the two 64-bit values back together. */
20655 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
20657 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
20658 icode
= reg_addr
[mode
].reload_vsx_gpr
;
20661 /* Handle moving 128-bit values from VSX point registers to GPRs on
20662 ISA 2.07 when running in 64-bit mode using XXPERMDI to get access to the
20663 bottom 64-bit value. */
20664 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
20666 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
20667 icode
= reg_addr
[mode
].reload_gpr_vsx
;
20671 else if (TARGET_POWERPC64
&& mode
== SFmode
)
20673 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
20675 cost
= 3; /* xscvdpspn, mfvsrd, and. */
20676 icode
= reg_addr
[mode
].reload_gpr_vsx
;
20679 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
20681 cost
= 2; /* mtvsrz, xscvspdpn. */
20682 icode
= reg_addr
[mode
].reload_vsx_gpr
;
20686 else if (!TARGET_POWERPC64
&& size
== 8)
20688 /* Handle moving 64-bit values from GPRs to floating point registers on
20689 ISA 2.07 when running in 32-bit mode using FMRGOW to glue the two
20690 32-bit values back together. Altivec register classes must be handled
20691 specially since a different instruction is used, and the secondary
20692 reload support requires a single instruction class in the scratch
20693 register constraint. However, right now TFmode is not allowed in
20694 Altivec registers, so the pattern will never match. */
20695 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
20697 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
20698 icode
= reg_addr
[mode
].reload_fpr_gpr
;
20702 if (icode
!= CODE_FOR_nothing
)
20707 sri
->icode
= icode
;
20708 sri
->extra_cost
= cost
;
20715 /* Return whether a move between two register classes can be done either
20716 directly (simple move) or via a pattern that uses a single extra temporary
20717 (using ISA 2.07's direct move in this case. */
20720 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
20721 enum rs6000_reg_type from_type
,
20723 secondary_reload_info
*sri
,
20726 /* Fall back to load/store reloads if either type is not a register. */
20727 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
20730 /* If we haven't allocated registers yet, assume the move can be done for the
20731 standard register types. */
20732 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
20733 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
20734 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
20737 /* Moves to the same set of registers is a simple move for non-specialized
20739 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
20742 /* Check whether a simple move can be done directly. */
20743 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
20747 sri
->icode
= CODE_FOR_nothing
;
20748 sri
->extra_cost
= 0;
20753 /* Now check if we can do it in a few steps. */
20754 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
20758 /* Inform reload about cases where moving X with a mode MODE to a register in
20759 RCLASS requires an extra scratch or immediate register. Return the class
20760 needed for the immediate register.
20762 For VSX and Altivec, we may need a register to convert sp+offset into
20765 For misaligned 64-bit gpr loads and stores we need a register to
20766 convert an offset address to indirect. */
20769 rs6000_secondary_reload (bool in_p
,
20771 reg_class_t rclass_i
,
20773 secondary_reload_info
*sri
)
20775 enum reg_class rclass
= (enum reg_class
) rclass_i
;
20776 reg_class_t ret
= ALL_REGS
;
20777 enum insn_code icode
;
20778 bool default_p
= false;
20779 bool done_p
= false;
20781 /* Allow subreg of memory before/during reload. */
20782 bool memory_p
= (MEM_P (x
)
20783 || (!reload_completed
&& GET_CODE (x
) == SUBREG
20784 && MEM_P (SUBREG_REG (x
))));
20786 sri
->icode
= CODE_FOR_nothing
;
20787 sri
->t_icode
= CODE_FOR_nothing
;
20788 sri
->extra_cost
= 0;
20790 ? reg_addr
[mode
].reload_load
20791 : reg_addr
[mode
].reload_store
);
20793 if (REG_P (x
) || register_operand (x
, mode
))
20795 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
20796 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
20797 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
20800 std::swap (to_type
, from_type
);
20802 /* Can we do a direct move of some sort? */
20803 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
20806 icode
= (enum insn_code
)sri
->icode
;
20813 /* Make sure 0.0 is not reloaded or forced into memory. */
20814 if (x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
20821 /* If this is a scalar floating point value and we want to load it into the
20822 traditional Altivec registers, do it via a move via a traditional floating
20823 point register, unless we have D-form addressing. Also make sure that
20824 non-zero constants use a FPR. */
20825 if (!done_p
&& reg_addr
[mode
].scalar_in_vmx_p
20826 && !mode_supports_vmx_dform (mode
)
20827 && (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
20828 && (memory_p
|| (GET_CODE (x
) == CONST_DOUBLE
)))
20835 /* Handle reload of load/stores if we have reload helper functions. */
20836 if (!done_p
&& icode
!= CODE_FOR_nothing
&& memory_p
)
20838 int extra_cost
= rs6000_secondary_reload_memory (XEXP (x
, 0), rclass
,
20841 if (extra_cost
>= 0)
20845 if (extra_cost
> 0)
20847 sri
->extra_cost
= extra_cost
;
20848 sri
->icode
= icode
;
20853 /* Handle unaligned loads and stores of integer registers. */
20854 if (!done_p
&& TARGET_POWERPC64
20855 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
20857 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
20859 rtx addr
= XEXP (x
, 0);
20860 rtx off
= address_offset (addr
);
20862 if (off
!= NULL_RTX
)
20864 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
20865 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
20867 /* We need a secondary reload when our legitimate_address_p
20868 says the address is good (as otherwise the entire address
20869 will be reloaded), and the offset is not a multiple of
20870 four or we have an address wrap. Address wrap will only
20871 occur for LO_SUMs since legitimate_offset_address_p
20872 rejects addresses for 16-byte mems that will wrap. */
20873 if (GET_CODE (addr
) == LO_SUM
20874 ? (1 /* legitimate_address_p allows any offset for lo_sum */
20875 && ((offset
& 3) != 0
20876 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
20877 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
20878 && (offset
& 3) != 0))
20880 /* -m32 -mpowerpc64 needs to use a 32-bit scratch register. */
20882 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_load
20883 : CODE_FOR_reload_di_load
);
20885 sri
->icode
= ((TARGET_32BIT
) ? CODE_FOR_reload_si_store
20886 : CODE_FOR_reload_di_store
);
20887 sri
->extra_cost
= 2;
20898 if (!done_p
&& !TARGET_POWERPC64
20899 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
20901 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
20903 rtx addr
= XEXP (x
, 0);
20904 rtx off
= address_offset (addr
);
20906 if (off
!= NULL_RTX
)
20908 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
20909 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
20911 /* We need a secondary reload when our legitimate_address_p
20912 says the address is good (as otherwise the entire address
20913 will be reloaded), and we have a wrap.
20915 legitimate_lo_sum_address_p allows LO_SUM addresses to
20916 have any offset so test for wrap in the low 16 bits.
20918 legitimate_offset_address_p checks for the range
20919 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
20920 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
20921 [0x7ff4,0x7fff] respectively, so test for the
20922 intersection of these ranges, [0x7ffc,0x7fff] and
20923 [0x7ff4,0x7ff7] respectively.
20925 Note that the address we see here may have been
20926 manipulated by legitimize_reload_address. */
20927 if (GET_CODE (addr
) == LO_SUM
20928 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
20929 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
20932 sri
->icode
= CODE_FOR_reload_si_load
;
20934 sri
->icode
= CODE_FOR_reload_si_store
;
20935 sri
->extra_cost
= 2;
20950 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
20952 gcc_assert (ret
!= ALL_REGS
);
20954 if (TARGET_DEBUG_ADDR
)
20957 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
20959 reg_class_names
[ret
],
20960 in_p
? "true" : "false",
20961 reg_class_names
[rclass
],
20962 GET_MODE_NAME (mode
));
20964 if (reload_completed
)
20965 fputs (", after reload", stderr
);
20968 fputs (", done_p not set", stderr
);
20971 fputs (", default secondary reload", stderr
);
20973 if (sri
->icode
!= CODE_FOR_nothing
)
20974 fprintf (stderr
, ", reload func = %s, extra cost = %d",
20975 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
20977 else if (sri
->extra_cost
> 0)
20978 fprintf (stderr
, ", extra cost = %d", sri
->extra_cost
);
20980 fputs ("\n", stderr
);
20987 /* Better tracing for rs6000_secondary_reload_inner. */
20990 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
20995 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
20997 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
20998 store_p
? "store" : "load");
21001 set
= gen_rtx_SET (mem
, reg
);
21003 set
= gen_rtx_SET (reg
, mem
);
21005 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
21006 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
21009 static void rs6000_secondary_reload_fail (int, rtx
, rtx
, rtx
, bool)
21010 ATTRIBUTE_NORETURN
;
21013 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
21016 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
21017 gcc_unreachable ();
21020 /* Fixup reload addresses for values in GPR, FPR, and VMX registers that have
21021 reload helper functions. These were identified in
21022 rs6000_secondary_reload_memory, and if reload decided to use the secondary
21023 reload, it calls the insns:
21024 reload_<RELOAD:mode>_<P:mptrsize>_store
21025 reload_<RELOAD:mode>_<P:mptrsize>_load
21027 which in turn calls this function, to do whatever is necessary to create
21028 valid addresses. */
21031 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
21033 int regno
= true_regnum (reg
);
21034 machine_mode mode
= GET_MODE (reg
);
21035 addr_mask_type addr_mask
;
21038 rtx op_reg
, op0
, op1
;
21043 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
|| !MEM_P (mem
)
21044 || !base_reg_operand (scratch
, GET_MODE (scratch
)))
21045 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21047 if (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
))
21048 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_GPR
];
21050 else if (IN_RANGE (regno
, FIRST_FPR_REGNO
, LAST_FPR_REGNO
))
21051 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
];
21053 else if (IN_RANGE (regno
, FIRST_ALTIVEC_REGNO
, LAST_ALTIVEC_REGNO
))
21054 addr_mask
= reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
];
21057 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21059 /* Make sure the mode is valid in this register class. */
21060 if ((addr_mask
& RELOAD_REG_VALID
) == 0)
21061 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21063 if (TARGET_DEBUG_ADDR
)
21064 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
21066 new_addr
= addr
= XEXP (mem
, 0);
21067 switch (GET_CODE (addr
))
21069 /* Does the register class support auto update forms for this mode? If
21070 not, do the update now. We don't need a scratch register, since the
21071 powerpc only supports PRE_INC, PRE_DEC, and PRE_MODIFY. */
21074 op_reg
= XEXP (addr
, 0);
21075 if (!base_reg_operand (op_reg
, Pmode
))
21076 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21078 if ((addr_mask
& RELOAD_REG_PRE_INCDEC
) == 0)
21080 emit_insn (gen_add2_insn (op_reg
, GEN_INT (GET_MODE_SIZE (mode
))));
21086 op0
= XEXP (addr
, 0);
21087 op1
= XEXP (addr
, 1);
21088 if (!base_reg_operand (op0
, Pmode
)
21089 || GET_CODE (op1
) != PLUS
21090 || !rtx_equal_p (op0
, XEXP (op1
, 0)))
21091 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21093 if ((addr_mask
& RELOAD_REG_PRE_MODIFY
) == 0)
21095 emit_insn (gen_rtx_SET (op0
, op1
));
21100 /* Do we need to simulate AND -16 to clear the bottom address bits used
21101 in VMX load/stores? */
21103 op0
= XEXP (addr
, 0);
21104 op1
= XEXP (addr
, 1);
21105 if ((addr_mask
& RELOAD_REG_AND_M16
) == 0)
21107 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
21110 else if (GET_CODE (op1
) == PLUS
)
21112 emit_insn (gen_rtx_SET (scratch
, op1
));
21117 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21119 and_op
= gen_rtx_AND (GET_MODE (scratch
), op_reg
, op1
);
21120 cc_clobber
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (CCmode
));
21121 rv
= gen_rtvec (2, gen_rtx_SET (scratch
, and_op
), cc_clobber
);
21122 emit_insn (gen_rtx_PARALLEL (VOIDmode
, rv
));
21123 new_addr
= scratch
;
21127 /* If this is an indirect address, make sure it is a base register. */
21130 if (!base_reg_operand (addr
, GET_MODE (addr
)))
21132 emit_insn (gen_rtx_SET (scratch
, addr
));
21133 new_addr
= scratch
;
21137 /* If this is an indexed address, make sure the register class can handle
21138 indexed addresses for this mode. */
21140 op0
= XEXP (addr
, 0);
21141 op1
= XEXP (addr
, 1);
21142 if (!base_reg_operand (op0
, Pmode
))
21143 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21145 else if (int_reg_operand (op1
, Pmode
))
21147 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
21149 emit_insn (gen_rtx_SET (scratch
, addr
));
21150 new_addr
= scratch
;
21154 else if (mode_supports_vsx_dform_quad (mode
) && CONST_INT_P (op1
))
21156 if (((addr_mask
& RELOAD_REG_QUAD_OFFSET
) == 0)
21157 || !quad_address_p (addr
, mode
, false))
21159 emit_insn (gen_rtx_SET (scratch
, addr
));
21160 new_addr
= scratch
;
21164 /* Make sure the register class can handle offset addresses. */
21165 else if (rs6000_legitimate_offset_address_p (mode
, addr
, false, true))
21167 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
21169 emit_insn (gen_rtx_SET (scratch
, addr
));
21170 new_addr
= scratch
;
21175 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21180 op0
= XEXP (addr
, 0);
21181 op1
= XEXP (addr
, 1);
21182 if (!base_reg_operand (op0
, Pmode
))
21183 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21185 else if (int_reg_operand (op1
, Pmode
))
21187 if ((addr_mask
& RELOAD_REG_INDEXED
) == 0)
21189 emit_insn (gen_rtx_SET (scratch
, addr
));
21190 new_addr
= scratch
;
21194 /* Quad offsets are restricted and can't handle normal addresses. */
21195 else if (mode_supports_vsx_dform_quad (mode
))
21197 emit_insn (gen_rtx_SET (scratch
, addr
));
21198 new_addr
= scratch
;
21201 /* Make sure the register class can handle offset addresses. */
21202 else if (legitimate_lo_sum_address_p (mode
, addr
, false))
21204 if ((addr_mask
& RELOAD_REG_OFFSET
) == 0)
21206 emit_insn (gen_rtx_SET (scratch
, addr
));
21207 new_addr
= scratch
;
21212 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21219 rs6000_emit_move (scratch
, addr
, Pmode
);
21220 new_addr
= scratch
;
21224 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
21227 /* Adjust the address if it changed. */
21228 if (addr
!= new_addr
)
21230 mem
= replace_equiv_address_nv (mem
, new_addr
);
21231 if (TARGET_DEBUG_ADDR
)
21232 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
21235 /* Now create the move. */
21237 emit_insn (gen_rtx_SET (mem
, reg
));
21239 emit_insn (gen_rtx_SET (reg
, mem
));
21244 /* Convert reloads involving 64-bit gprs and misaligned offset
21245 addressing, or multiple 32-bit gprs and offsets that are too large,
21246 to use indirect addressing. */
21249 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
21251 int regno
= true_regnum (reg
);
21252 enum reg_class rclass
;
21254 rtx scratch_or_premodify
= scratch
;
21256 if (TARGET_DEBUG_ADDR
)
21258 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
21259 store_p
? "store" : "load");
21260 fprintf (stderr
, "reg:\n");
21262 fprintf (stderr
, "mem:\n");
21264 fprintf (stderr
, "scratch:\n");
21265 debug_rtx (scratch
);
21268 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
21269 gcc_assert (GET_CODE (mem
) == MEM
);
21270 rclass
= REGNO_REG_CLASS (regno
);
21271 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
21272 addr
= XEXP (mem
, 0);
21274 if (GET_CODE (addr
) == PRE_MODIFY
)
21276 gcc_assert (REG_P (XEXP (addr
, 0))
21277 && GET_CODE (XEXP (addr
, 1)) == PLUS
21278 && XEXP (XEXP (addr
, 1), 0) == XEXP (addr
, 0));
21279 scratch_or_premodify
= XEXP (addr
, 0);
21280 if (!HARD_REGISTER_P (scratch_or_premodify
))
21281 /* If we have a pseudo here then reload will have arranged
21282 to have it replaced, but only in the original insn.
21283 Use the replacement here too. */
21284 scratch_or_premodify
= find_replacement (&XEXP (addr
, 0));
21286 /* RTL emitted by rs6000_secondary_reload_gpr uses RTL
21287 expressions from the original insn, without unsharing them.
21288 Any RTL that points into the original insn will of course
21289 have register replacements applied. That is why we don't
21290 need to look for replacements under the PLUS. */
21291 addr
= XEXP (addr
, 1);
21293 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
21295 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
21297 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
21299 /* Now create the move. */
21301 emit_insn (gen_rtx_SET (mem
, reg
));
21303 emit_insn (gen_rtx_SET (reg
, mem
));
21308 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
21309 this function has any SDmode references. If we are on a power7 or later, we
21310 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
21311 can load/store the value. */
21314 rs6000_alloc_sdmode_stack_slot (void)
21318 gimple_stmt_iterator gsi
;
21320 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
21321 /* We use a different approach for dealing with the secondary
21326 if (TARGET_NO_SDMODE_STACK
)
21329 FOR_EACH_BB_FN (bb
, cfun
)
21330 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
21332 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
21335 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
21336 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
21342 /* Check for any SDmode parameters of the function. */
21343 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
21345 if (TREE_TYPE (t
) == error_mark_node
)
21348 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
21349 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
21351 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
21352 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
21360 rs6000_instantiate_decls (void)
21362 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
21363 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
21366 /* Given an rtx X being reloaded into a reg required to be
21367 in class CLASS, return the class of reg to actually use.
21368 In general this is just CLASS; but on some machines
21369 in some cases it is preferable to use a more restrictive class.
21371 On the RS/6000, we have to return NO_REGS when we want to reload a
21372 floating-point CONST_DOUBLE to force it to be copied to memory.
21374 We also don't want to reload integer values into floating-point
21375 registers if we can at all help it. In fact, this can
21376 cause reload to die, if it tries to generate a reload of CTR
21377 into a FP register and discovers it doesn't have the memory location
21380 ??? Would it be a good idea to have reload do the converse, that is
21381 try to reload floating modes into FP registers if possible?
21384 static enum reg_class
21385 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
21387 machine_mode mode
= GET_MODE (x
);
21388 bool is_constant
= CONSTANT_P (x
);
21390 /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred
21391 reload class for it. */
21392 if ((rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
21393 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_VMX
] & RELOAD_REG_VALID
) == 0)
21396 if ((rclass
== FLOAT_REGS
|| rclass
== VSX_REGS
)
21397 && (reg_addr
[mode
].addr_mask
[RELOAD_REG_FPR
] & RELOAD_REG_VALID
) == 0)
21400 /* For VSX, see if we should prefer FLOAT_REGS or ALTIVEC_REGS. Do not allow
21401 the reloading of address expressions using PLUS into floating point
21403 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
) && GET_CODE (x
) != PLUS
)
21407 /* Zero is always allowed in all VSX registers. */
21408 if (x
== CONST0_RTX (mode
))
21411 /* If this is a vector constant that can be formed with a few Altivec
21412 instructions, we want altivec registers. */
21413 if (GET_CODE (x
) == CONST_VECTOR
&& easy_vector_constant (x
, mode
))
21414 return ALTIVEC_REGS
;
21416 /* Force constant to memory. */
21420 /* D-form addressing can easily reload the value. */
21421 if (mode_supports_vmx_dform (mode
)
21422 || mode_supports_vsx_dform_quad (mode
))
21425 /* If this is a scalar floating point value and we don't have D-form
21426 addressing, prefer the traditional floating point registers so that we
21427 can use D-form (register+offset) addressing. */
21428 if (rclass
== VSX_REGS
21429 && (mode
== SFmode
|| GET_MODE_SIZE (mode
) == 8))
21432 /* Prefer the Altivec registers if Altivec is handling the vector
21433 operations (i.e. V16QI, V8HI, and V4SI), or if we prefer Altivec
21435 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
)
21436 || mode
== V1TImode
)
21437 return ALTIVEC_REGS
;
21442 if (is_constant
|| GET_CODE (x
) == PLUS
)
21444 if (reg_class_subset_p (GENERAL_REGS
, rclass
))
21445 return GENERAL_REGS
;
21446 if (reg_class_subset_p (BASE_REGS
, rclass
))
21451 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
21452 return GENERAL_REGS
;
21457 /* Debug version of rs6000_preferred_reload_class. */
21458 static enum reg_class
21459 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
21461 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
21464 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
21466 reg_class_names
[ret
], reg_class_names
[rclass
],
21467 GET_MODE_NAME (GET_MODE (x
)));
21473 /* If we are copying between FP or AltiVec registers and anything else, we need
21474 a memory location. The exception is when we are targeting ppc64 and the
21475 move to/from fpr to gpr instructions are available. Also, under VSX, you
21476 can copy vector registers from the FP register set to the Altivec register
21477 set and vice versa. */
21480 rs6000_secondary_memory_needed (enum reg_class from_class
,
21481 enum reg_class to_class
,
21484 enum rs6000_reg_type from_type
, to_type
;
21485 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
21486 || (to_class
== ALTIVEC_REGS
));
21488 /* If a simple/direct move is available, we don't need secondary memory */
21489 from_type
= reg_class_to_reg_type
[(int)from_class
];
21490 to_type
= reg_class_to_reg_type
[(int)to_class
];
21492 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
21493 (secondary_reload_info
*)0, altivec_p
))
21496 /* If we have a floating point or vector register class, we need to use
21497 memory to transfer the data. */
21498 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
21504 /* Debug version of rs6000_secondary_memory_needed. */
21506 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
21507 enum reg_class to_class
,
21510 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
21513 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
21514 "to_class = %s, mode = %s\n",
21515 ret
? "true" : "false",
21516 reg_class_names
[from_class
],
21517 reg_class_names
[to_class
],
21518 GET_MODE_NAME (mode
));
21523 /* Return the register class of a scratch register needed to copy IN into
21524 or out of a register in RCLASS in MODE. If it can be done directly,
21525 NO_REGS is returned. */
21527 static enum reg_class
21528 rs6000_secondary_reload_class (enum reg_class rclass
, machine_mode mode
,
21533 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
21535 && MACHOPIC_INDIRECT
21539 /* We cannot copy a symbolic operand directly into anything
21540 other than BASE_REGS for TARGET_ELF. So indicate that a
21541 register from BASE_REGS is needed as an intermediate
21544 On Darwin, pic addresses require a load from memory, which
21545 needs a base register. */
21546 if (rclass
!= BASE_REGS
21547 && (GET_CODE (in
) == SYMBOL_REF
21548 || GET_CODE (in
) == HIGH
21549 || GET_CODE (in
) == LABEL_REF
21550 || GET_CODE (in
) == CONST
))
21554 if (GET_CODE (in
) == REG
)
21556 regno
= REGNO (in
);
21557 if (regno
>= FIRST_PSEUDO_REGISTER
)
21559 regno
= true_regnum (in
);
21560 if (regno
>= FIRST_PSEUDO_REGISTER
)
21564 else if (GET_CODE (in
) == SUBREG
)
21566 regno
= true_regnum (in
);
21567 if (regno
>= FIRST_PSEUDO_REGISTER
)
21573 /* If we have VSX register moves, prefer moving scalar values between
21574 Altivec registers and GPR by going via an FPR (and then via memory)
21575 instead of reloading the secondary memory address for Altivec moves. */
21577 && GET_MODE_SIZE (mode
) < 16
21578 && !mode_supports_vmx_dform (mode
)
21579 && (((rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
21580 && (regno
>= 0 && ALTIVEC_REGNO_P (regno
)))
21581 || ((rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
)
21582 && (regno
>= 0 && INT_REGNO_P (regno
)))))
21585 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
21587 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
21588 || (regno
>= 0 && INT_REGNO_P (regno
)))
21591 /* Constants, memory, and VSX registers can go into VSX registers (both the
21592 traditional floating point and the altivec registers). */
21593 if (rclass
== VSX_REGS
21594 && (regno
== -1 || VSX_REGNO_P (regno
)))
21597 /* Constants, memory, and FP registers can go into FP registers. */
21598 if ((regno
== -1 || FP_REGNO_P (regno
))
21599 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
21600 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
21602 /* Memory, and AltiVec registers can go into AltiVec registers. */
21603 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
21604 && rclass
== ALTIVEC_REGS
)
21607 /* We can copy among the CR registers. */
21608 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
21609 && regno
>= 0 && CR_REGNO_P (regno
))
21612 /* Otherwise, we need GENERAL_REGS. */
21613 return GENERAL_REGS
;
21616 /* Debug version of rs6000_secondary_reload_class. */
21617 static enum reg_class
21618 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
21619 machine_mode mode
, rtx in
)
21621 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
21623 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
21624 "mode = %s, input rtx:\n",
21625 reg_class_names
[ret
], reg_class_names
[rclass
],
21626 GET_MODE_NAME (mode
));
21632 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
21635 rs6000_cannot_change_mode_class (machine_mode from
,
21637 enum reg_class rclass
)
21639 unsigned from_size
= GET_MODE_SIZE (from
);
21640 unsigned to_size
= GET_MODE_SIZE (to
);
21642 if (from_size
!= to_size
)
21644 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
21646 if (reg_classes_intersect_p (xclass
, rclass
))
21648 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
21649 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
21650 bool to_float128_vector_p
= FLOAT128_VECTOR_P (to
);
21651 bool from_float128_vector_p
= FLOAT128_VECTOR_P (from
);
21653 /* Don't allow 64-bit types to overlap with 128-bit types that take a
21654 single register under VSX because the scalar part of the register
21655 is in the upper 64-bits, and not the lower 64-bits. Types like
21656 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
21657 IEEE floating point can't overlap, and neither can small
21660 if (to_float128_vector_p
&& from_float128_vector_p
)
21663 else if (to_float128_vector_p
|| from_float128_vector_p
)
21666 /* TDmode in floating-mode registers must always go into a register
21667 pair with the most significant word in the even-numbered register
21668 to match ISA requirements. In little-endian mode, this does not
21669 match subreg numbering, so we cannot allow subregs. */
21670 if (!BYTES_BIG_ENDIAN
&& (to
== TDmode
|| from
== TDmode
))
21673 if (from_size
< 8 || to_size
< 8)
21676 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
21679 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
21688 if (TARGET_E500_DOUBLE
21689 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
21690 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
21691 || (((to
) == IFmode
) + ((from
) == IFmode
)) == 1
21692 || (((to
) == KFmode
) + ((from
) == KFmode
)) == 1
21693 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
21694 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
21695 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
21698 /* Since the VSX register set includes traditional floating point registers
21699 and altivec registers, just check for the size being different instead of
21700 trying to check whether the modes are vector modes. Otherwise it won't
21701 allow say DF and DI to change classes. For types like TFmode and TDmode
21702 that take 2 64-bit registers, rather than a single 128-bit register, don't
21703 allow subregs of those types to other 128 bit types. */
21704 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
21706 unsigned num_regs
= (from_size
+ 15) / 16;
21707 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
21708 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
21711 return (from_size
!= 8 && from_size
!= 16);
21714 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
21715 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
21718 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
21719 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
21725 /* Debug version of rs6000_cannot_change_mode_class. */
21727 rs6000_debug_cannot_change_mode_class (machine_mode from
,
21729 enum reg_class rclass
)
21731 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
21734 "rs6000_cannot_change_mode_class, return %s, from = %s, "
21735 "to = %s, rclass = %s\n",
21736 ret
? "true" : "false",
21737 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
21738 reg_class_names
[rclass
]);
21743 /* Return a string to do a move operation of 128 bits of data. */
21746 rs6000_output_move_128bit (rtx operands
[])
21748 rtx dest
= operands
[0];
21749 rtx src
= operands
[1];
21750 machine_mode mode
= GET_MODE (dest
);
21753 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
21754 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
21758 dest_regno
= REGNO (dest
);
21759 dest_gpr_p
= INT_REGNO_P (dest_regno
);
21760 dest_fp_p
= FP_REGNO_P (dest_regno
);
21761 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
21762 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
21767 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
21772 src_regno
= REGNO (src
);
21773 src_gpr_p
= INT_REGNO_P (src_regno
);
21774 src_fp_p
= FP_REGNO_P (src_regno
);
21775 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
21776 src_vsx_p
= src_fp_p
| src_vmx_p
;
21781 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
21784 /* Register moves. */
21785 if (dest_regno
>= 0 && src_regno
>= 0)
21792 if (TARGET_DIRECT_MOVE_128
&& src_vsx_p
)
21793 return (WORDS_BIG_ENDIAN
21794 ? "mfvsrd %0,%x1\n\tmfvsrld %L0,%x1"
21795 : "mfvsrd %L0,%x1\n\tmfvsrld %0,%x1");
21797 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
21801 else if (TARGET_VSX
&& dest_vsx_p
)
21804 return "xxlor %x0,%x1,%x1";
21806 else if (TARGET_DIRECT_MOVE_128
&& src_gpr_p
)
21807 return (WORDS_BIG_ENDIAN
21808 ? "mtvsrdd %x0,%1,%L1"
21809 : "mtvsrdd %x0,%L1,%1");
21811 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
21815 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
21816 return "vor %0,%1,%1";
21818 else if (dest_fp_p
&& src_fp_p
)
21823 else if (dest_regno
>= 0 && MEM_P (src
))
21827 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
21833 else if (TARGET_ALTIVEC
&& dest_vmx_p
21834 && altivec_indexed_or_indirect_operand (src
, mode
))
21835 return "lvx %0,%y1";
21837 else if (TARGET_VSX
&& dest_vsx_p
)
21839 if (mode_supports_vsx_dform_quad (mode
)
21840 && quad_address_p (XEXP (src
, 0), mode
, true))
21841 return "lxv %x0,%1";
21843 else if (TARGET_P9_VECTOR
)
21844 return "lxvx %x0,%y1";
21846 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
21847 return "lxvw4x %x0,%y1";
21850 return "lxvd2x %x0,%y1";
21853 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
21854 return "lvx %0,%y1";
21856 else if (dest_fp_p
)
21861 else if (src_regno
>= 0 && MEM_P (dest
))
21865 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
21866 return "stq %1,%0";
21871 else if (TARGET_ALTIVEC
&& src_vmx_p
21872 && altivec_indexed_or_indirect_operand (src
, mode
))
21873 return "stvx %1,%y0";
21875 else if (TARGET_VSX
&& src_vsx_p
)
21877 if (mode_supports_vsx_dform_quad (mode
)
21878 && quad_address_p (XEXP (dest
, 0), mode
, true))
21879 return "stxv %x1,%0";
21881 else if (TARGET_P9_VECTOR
)
21882 return "stxvx %x1,%y0";
21884 else if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
21885 return "stxvw4x %x1,%y0";
21888 return "stxvd2x %x1,%y0";
21891 else if (TARGET_ALTIVEC
&& src_vmx_p
)
21892 return "stvx %1,%y0";
21899 else if (dest_regno
>= 0
21900 && (GET_CODE (src
) == CONST_INT
21901 || GET_CODE (src
) == CONST_WIDE_INT
21902 || GET_CODE (src
) == CONST_DOUBLE
21903 || GET_CODE (src
) == CONST_VECTOR
))
21908 else if ((dest_vmx_p
&& TARGET_ALTIVEC
)
21909 || (dest_vsx_p
&& TARGET_VSX
))
21910 return output_vec_const_move (operands
);
21913 fatal_insn ("Bad 128-bit move", gen_rtx_SET (dest
, src
));
21916 /* Validate a 128-bit move. */
21918 rs6000_move_128bit_ok_p (rtx operands
[])
21920 machine_mode mode
= GET_MODE (operands
[0]);
21921 return (gpc_reg_operand (operands
[0], mode
)
21922 || gpc_reg_operand (operands
[1], mode
));
21925 /* Return true if a 128-bit move needs to be split. */
21927 rs6000_split_128bit_ok_p (rtx operands
[])
21929 if (!reload_completed
)
21932 if (!gpr_or_gpr_p (operands
[0], operands
[1]))
21935 if (quad_load_store_p (operands
[0], operands
[1]))
21942 /* Given a comparison operation, return the bit number in CCR to test. We
21943 know this is a valid comparison.
21945 SCC_P is 1 if this is for an scc. That means that %D will have been
21946 used instead of %C, so the bits will be in different places.
21948 Return -1 if OP isn't a valid comparison for some reason. */
21951 ccr_bit (rtx op
, int scc_p
)
21953 enum rtx_code code
= GET_CODE (op
);
21954 machine_mode cc_mode
;
21959 if (!COMPARISON_P (op
))
21962 reg
= XEXP (op
, 0);
21964 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
21966 cc_mode
= GET_MODE (reg
);
21967 cc_regnum
= REGNO (reg
);
21968 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
21970 validate_condition_mode (code
, cc_mode
);
21972 /* When generating a sCOND operation, only positive conditions are
21975 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
21976 || code
== GTU
|| code
== LTU
);
21981 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
21983 return base_bit
+ 2;
21984 case GT
: case GTU
: case UNLE
:
21985 return base_bit
+ 1;
21986 case LT
: case LTU
: case UNGE
:
21988 case ORDERED
: case UNORDERED
:
21989 return base_bit
+ 3;
21992 /* If scc, we will have done a cror to put the bit in the
21993 unordered position. So test that bit. For integer, this is ! LT
21994 unless this is an scc insn. */
21995 return scc_p
? base_bit
+ 3 : base_bit
;
21998 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
22001 gcc_unreachable ();
22005 /* Return the GOT register. */
22008 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
22010 /* The second flow pass currently (June 1999) can't update
22011 regs_ever_live without disturbing other parts of the compiler, so
22012 update it here to make the prolog/epilogue code happy. */
22013 if (!can_create_pseudo_p ()
22014 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
22015 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
22017 crtl
->uses_pic_offset_table
= 1;
22019 return pic_offset_table_rtx
;
22022 static rs6000_stack_t stack_info
;
22024 /* Function to init struct machine_function.
22025 This will be called, via a pointer variable,
22026 from push_function_context. */
22028 static struct machine_function
*
22029 rs6000_init_machine_status (void)
22031 stack_info
.reload_completed
= 0;
22032 return ggc_cleared_alloc
<machine_function
> ();
22035 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
22037 /* Write out a function code label. */
22040 rs6000_output_function_entry (FILE *file
, const char *fname
)
22042 if (fname
[0] != '.')
22044 switch (DEFAULT_ABI
)
22047 gcc_unreachable ();
22053 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
22063 RS6000_OUTPUT_BASENAME (file
, fname
);
22066 /* Print an operand. Recognize special options, documented below. */
22069 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
22070 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
22072 #define SMALL_DATA_RELOC "sda21"
22073 #define SMALL_DATA_REG 0
22077 print_operand (FILE *file
, rtx x
, int code
)
22080 unsigned HOST_WIDE_INT uval
;
22084 /* %a is output_address. */
22086 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
22090 /* Like 'J' but get to the GT bit only. */
22091 gcc_assert (REG_P (x
));
22093 /* Bit 1 is GT bit. */
22094 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
22096 /* Add one for shift count in rlinm for scc. */
22097 fprintf (file
, "%d", i
+ 1);
22101 /* If the low 16 bits are 0, but some other bit is set, write 's'. */
22104 output_operand_lossage ("invalid %%e value");
22109 if ((uval
& 0xffff) == 0 && uval
!= 0)
22114 /* X is a CR register. Print the number of the EQ bit of the CR */
22115 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
22116 output_operand_lossage ("invalid %%E value");
22118 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
22122 /* X is a CR register. Print the shift count needed to move it
22123 to the high-order four bits. */
22124 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
22125 output_operand_lossage ("invalid %%f value");
22127 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
22131 /* Similar, but print the count for the rotate in the opposite
22133 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
22134 output_operand_lossage ("invalid %%F value");
22136 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
22140 /* X is a constant integer. If it is negative, print "m",
22141 otherwise print "z". This is to make an aze or ame insn. */
22142 if (GET_CODE (x
) != CONST_INT
)
22143 output_operand_lossage ("invalid %%G value");
22144 else if (INTVAL (x
) >= 0)
22151 /* If constant, output low-order five bits. Otherwise, write
22154 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
22156 print_operand (file
, x
, 0);
22160 /* If constant, output low-order six bits. Otherwise, write
22163 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
22165 print_operand (file
, x
, 0);
22169 /* Print `i' if this is a constant, else nothing. */
22175 /* Write the bit number in CCR for jump. */
22176 i
= ccr_bit (x
, 0);
22178 output_operand_lossage ("invalid %%j code");
22180 fprintf (file
, "%d", i
);
22184 /* Similar, but add one for shift count in rlinm for scc and pass
22185 scc flag to `ccr_bit'. */
22186 i
= ccr_bit (x
, 1);
22188 output_operand_lossage ("invalid %%J code");
22190 /* If we want bit 31, write a shift count of zero, not 32. */
22191 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
22195 /* X must be a constant. Write the 1's complement of the
22198 output_operand_lossage ("invalid %%k value");
22200 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
22204 /* X must be a symbolic constant on ELF. Write an
22205 expression suitable for an 'addi' that adds in the low 16
22206 bits of the MEM. */
22207 if (GET_CODE (x
) == CONST
)
22209 if (GET_CODE (XEXP (x
, 0)) != PLUS
22210 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
22211 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
22212 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
22213 output_operand_lossage ("invalid %%K value");
22215 print_operand_address (file
, x
);
22216 fputs ("@l", file
);
22219 /* %l is output_asm_label. */
22222 /* Write second word of DImode or DFmode reference. Works on register
22223 or non-indexed memory only. */
22225 fputs (reg_names
[REGNO (x
) + 1], file
);
22226 else if (MEM_P (x
))
22228 machine_mode mode
= GET_MODE (x
);
22229 /* Handle possible auto-increment. Since it is pre-increment and
22230 we have already done it, we can just use an offset of word. */
22231 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
22232 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
22233 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
22235 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
22236 output_address (mode
, plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
22239 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
,
22243 if (small_data_operand (x
, GET_MODE (x
)))
22244 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
22245 reg_names
[SMALL_DATA_REG
]);
22250 /* Write the number of elements in the vector times 4. */
22251 if (GET_CODE (x
) != PARALLEL
)
22252 output_operand_lossage ("invalid %%N value");
22254 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
22258 /* Similar, but subtract 1 first. */
22259 if (GET_CODE (x
) != PARALLEL
)
22260 output_operand_lossage ("invalid %%O value");
22262 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
22266 /* X is a CONST_INT that is a power of two. Output the logarithm. */
22269 || (i
= exact_log2 (INTVAL (x
))) < 0)
22270 output_operand_lossage ("invalid %%p value");
22272 fprintf (file
, "%d", i
);
22276 /* The operand must be an indirect memory reference. The result
22277 is the register name. */
22278 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
22279 || REGNO (XEXP (x
, 0)) >= 32)
22280 output_operand_lossage ("invalid %%P value");
22282 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
22286 /* This outputs the logical code corresponding to a boolean
22287 expression. The expression may have one or both operands
22288 negated (if one, only the first one). For condition register
22289 logical operations, it will also treat the negated
22290 CR codes as NOTs, but not handle NOTs of them. */
22292 const char *const *t
= 0;
22294 enum rtx_code code
= GET_CODE (x
);
22295 static const char * const tbl
[3][3] = {
22296 { "and", "andc", "nor" },
22297 { "or", "orc", "nand" },
22298 { "xor", "eqv", "xor" } };
22302 else if (code
== IOR
)
22304 else if (code
== XOR
)
22307 output_operand_lossage ("invalid %%q value");
22309 if (GET_CODE (XEXP (x
, 0)) != NOT
)
22313 if (GET_CODE (XEXP (x
, 1)) == NOT
)
22324 if (! TARGET_MFCRF
)
22330 /* X is a CR register. Print the mask for `mtcrf'. */
22331 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
22332 output_operand_lossage ("invalid %%R value");
22334 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
22338 /* Low 5 bits of 32 - value */
22340 output_operand_lossage ("invalid %%s value");
22342 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
22346 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
22347 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
22349 /* Bit 3 is OV bit. */
22350 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
22352 /* If we want bit 31, write a shift count of zero, not 32. */
22353 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
22357 /* Print the symbolic name of a branch target register. */
22358 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
22359 && REGNO (x
) != CTR_REGNO
))
22360 output_operand_lossage ("invalid %%T value");
22361 else if (REGNO (x
) == LR_REGNO
)
22362 fputs ("lr", file
);
22364 fputs ("ctr", file
);
22368 /* High-order or low-order 16 bits of constant, whichever is non-zero,
22369 for use in unsigned operand. */
22372 output_operand_lossage ("invalid %%u value");
22377 if ((uval
& 0xffff) == 0)
22380 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, uval
& 0xffff);
22384 /* High-order 16 bits of constant for use in signed operand. */
22386 output_operand_lossage ("invalid %%v value");
22388 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
22389 (INTVAL (x
) >> 16) & 0xffff);
22393 /* Print `u' if this has an auto-increment or auto-decrement. */
22395 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
22396 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
22397 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
22402 /* Print the trap code for this operand. */
22403 switch (GET_CODE (x
))
22406 fputs ("eq", file
); /* 4 */
22409 fputs ("ne", file
); /* 24 */
22412 fputs ("lt", file
); /* 16 */
22415 fputs ("le", file
); /* 20 */
22418 fputs ("gt", file
); /* 8 */
22421 fputs ("ge", file
); /* 12 */
22424 fputs ("llt", file
); /* 2 */
22427 fputs ("lle", file
); /* 6 */
22430 fputs ("lgt", file
); /* 1 */
22433 fputs ("lge", file
); /* 5 */
22436 gcc_unreachable ();
22441 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
22444 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
22445 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
22447 print_operand (file
, x
, 0);
22451 /* X is a FPR or Altivec register used in a VSX context. */
22452 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
22453 output_operand_lossage ("invalid %%x value");
22456 int reg
= REGNO (x
);
22457 int vsx_reg
= (FP_REGNO_P (reg
)
22459 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
22461 #ifdef TARGET_REGNAMES
22462 if (TARGET_REGNAMES
)
22463 fprintf (file
, "%%vs%d", vsx_reg
);
22466 fprintf (file
, "%d", vsx_reg
);
22472 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
22473 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
22474 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
22479 /* Like 'L', for third word of TImode/PTImode */
22481 fputs (reg_names
[REGNO (x
) + 2], file
);
22482 else if (MEM_P (x
))
22484 machine_mode mode
= GET_MODE (x
);
22485 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
22486 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
22487 output_address (mode
, plus_constant (Pmode
,
22488 XEXP (XEXP (x
, 0), 0), 8));
22489 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
22490 output_address (mode
, plus_constant (Pmode
,
22491 XEXP (XEXP (x
, 0), 0), 8));
22493 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 8), 0));
22494 if (small_data_operand (x
, GET_MODE (x
)))
22495 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
22496 reg_names
[SMALL_DATA_REG
]);
22501 /* X is a SYMBOL_REF. Write out the name preceded by a
22502 period and without any trailing data in brackets. Used for function
22503 names. If we are configured for System V (or the embedded ABI) on
22504 the PowerPC, do not emit the period, since those systems do not use
22505 TOCs and the like. */
22506 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
22508 /* For macho, check to see if we need a stub. */
22511 const char *name
= XSTR (x
, 0);
22513 if (darwin_emit_branch_islands
22514 && MACHOPIC_INDIRECT
22515 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
22516 name
= machopic_indirection_name (x
, /*stub_p=*/true);
22518 assemble_name (file
, name
);
22520 else if (!DOT_SYMBOLS
)
22521 assemble_name (file
, XSTR (x
, 0));
22523 rs6000_output_function_entry (file
, XSTR (x
, 0));
22527 /* Like 'L', for last word of TImode/PTImode. */
22529 fputs (reg_names
[REGNO (x
) + 3], file
);
22530 else if (MEM_P (x
))
22532 machine_mode mode
= GET_MODE (x
);
22533 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
22534 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
22535 output_address (mode
, plus_constant (Pmode
,
22536 XEXP (XEXP (x
, 0), 0), 12));
22537 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
22538 output_address (mode
, plus_constant (Pmode
,
22539 XEXP (XEXP (x
, 0), 0), 12));
22541 output_address (mode
, XEXP (adjust_address_nv (x
, SImode
, 12), 0));
22542 if (small_data_operand (x
, GET_MODE (x
)))
22543 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
22544 reg_names
[SMALL_DATA_REG
]);
22548 /* Print AltiVec or SPE memory operand. */
22553 gcc_assert (MEM_P (x
));
22557 /* Ugly hack because %y is overloaded. */
22558 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
22559 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
22560 || FLOAT128_2REG_P (GET_MODE (x
))
22561 || GET_MODE (x
) == TImode
22562 || GET_MODE (x
) == PTImode
))
22564 /* Handle [reg]. */
22567 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
22570 /* Handle [reg+UIMM]. */
22571 else if (GET_CODE (tmp
) == PLUS
&&
22572 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
22576 gcc_assert (REG_P (XEXP (tmp
, 0)));
22578 x
= INTVAL (XEXP (tmp
, 1));
22579 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
22583 /* Fall through. Must be [reg+reg]. */
22585 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
22586 && GET_CODE (tmp
) == AND
22587 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
22588 && INTVAL (XEXP (tmp
, 1)) == -16)
22589 tmp
= XEXP (tmp
, 0);
22590 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
22591 && GET_CODE (tmp
) == PRE_MODIFY
)
22592 tmp
= XEXP (tmp
, 1);
22594 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
22597 if (GET_CODE (tmp
) != PLUS
22598 || !REG_P (XEXP (tmp
, 0))
22599 || !REG_P (XEXP (tmp
, 1)))
22601 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
22605 if (REGNO (XEXP (tmp
, 0)) == 0)
22606 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
22607 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
22609 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
22610 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
22617 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
22618 else if (MEM_P (x
))
22620 /* We need to handle PRE_INC and PRE_DEC here, since we need to
22621 know the width from the mode. */
22622 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
22623 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
22624 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
22625 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
22626 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
22627 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
22628 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
22629 output_address (GET_MODE (x
), XEXP (XEXP (x
, 0), 1));
22631 output_address (GET_MODE (x
), XEXP (x
, 0));
22635 if (toc_relative_expr_p (x
, false))
22636 /* This hack along with a corresponding hack in
22637 rs6000_output_addr_const_extra arranges to output addends
22638 where the assembler expects to find them. eg.
22639 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
22640 without this hack would be output as "x@toc+4". We
22642 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
22644 output_addr_const (file
, x
);
22649 if (const char *name
= get_some_local_dynamic_name ())
22650 assemble_name (file
, name
);
22652 output_operand_lossage ("'%%&' used without any "
22653 "local dynamic TLS references");
22657 output_operand_lossage ("invalid %%xn code");
22661 /* Print the address of an operand. */
22664 print_operand_address (FILE *file
, rtx x
)
22667 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
22668 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
22669 || GET_CODE (x
) == LABEL_REF
)
22671 output_addr_const (file
, x
);
22672 if (small_data_operand (x
, GET_MODE (x
)))
22673 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
22674 reg_names
[SMALL_DATA_REG
]);
22676 gcc_assert (!TARGET_TOC
);
22678 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
22679 && REG_P (XEXP (x
, 1)))
22681 if (REGNO (XEXP (x
, 0)) == 0)
22682 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
22683 reg_names
[ REGNO (XEXP (x
, 0)) ]);
22685 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
22686 reg_names
[ REGNO (XEXP (x
, 1)) ]);
22688 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
22689 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
22690 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
22691 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
22693 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
22694 && CONSTANT_P (XEXP (x
, 1)))
22696 fprintf (file
, "lo16(");
22697 output_addr_const (file
, XEXP (x
, 1));
22698 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
22702 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
22703 && CONSTANT_P (XEXP (x
, 1)))
22705 output_addr_const (file
, XEXP (x
, 1));
22706 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
22709 else if (toc_relative_expr_p (x
, false))
22711 /* This hack along with a corresponding hack in
22712 rs6000_output_addr_const_extra arranges to output addends
22713 where the assembler expects to find them. eg.
22715 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
22716 without this hack would be output as "x@toc+8@l(9)". We
22717 want "x+8@toc@l(9)". */
22718 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
22719 if (GET_CODE (x
) == LO_SUM
)
22720 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
22722 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
22725 gcc_unreachable ();
22728 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
22731 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
22733 if (GET_CODE (x
) == UNSPEC
)
22734 switch (XINT (x
, 1))
22736 case UNSPEC_TOCREL
:
22737 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
22738 && REG_P (XVECEXP (x
, 0, 1))
22739 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
22740 output_addr_const (file
, XVECEXP (x
, 0, 0));
22741 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
22743 if (INTVAL (tocrel_offset
) >= 0)
22744 fprintf (file
, "+");
22745 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
22747 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
22750 assemble_name (file
, toc_label_name
);
22753 else if (TARGET_ELF
)
22754 fputs ("@toc", file
);
22758 case UNSPEC_MACHOPIC_OFFSET
:
22759 output_addr_const (file
, XVECEXP (x
, 0, 0));
22761 machopic_output_function_base_name (file
);
22768 /* Target hook for assembling integer objects. The PowerPC version has
22769 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
22770 is defined. It also needs to handle DI-mode objects on 64-bit
22774 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
22776 #ifdef RELOCATABLE_NEEDS_FIXUP
22777 /* Special handling for SI values. */
22778 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
22780 static int recurse
= 0;
22782 /* For -mrelocatable, we mark all addresses that need to be fixed up in
22783 the .fixup section. Since the TOC section is already relocated, we
22784 don't need to mark it here. We used to skip the text section, but it
22785 should never be valid for relocated addresses to be placed in the text
22787 if (DEFAULT_ABI
== ABI_V4
22788 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
22789 && in_section
!= toc_section
22791 && !CONST_SCALAR_INT_P (x
)
22797 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
22799 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
22800 fprintf (asm_out_file
, "\t.long\t(");
22801 output_addr_const (asm_out_file
, x
);
22802 fprintf (asm_out_file
, ")@fixup\n");
22803 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
22804 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
22805 fprintf (asm_out_file
, "\t.long\t");
22806 assemble_name (asm_out_file
, buf
);
22807 fprintf (asm_out_file
, "\n\t.previous\n");
22811 /* Remove initial .'s to turn a -mcall-aixdesc function
22812 address into the address of the descriptor, not the function
22814 else if (GET_CODE (x
) == SYMBOL_REF
22815 && XSTR (x
, 0)[0] == '.'
22816 && DEFAULT_ABI
== ABI_AIX
)
22818 const char *name
= XSTR (x
, 0);
22819 while (*name
== '.')
22822 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
22826 #endif /* RELOCATABLE_NEEDS_FIXUP */
22827 return default_assemble_integer (x
, size
, aligned_p
);
22830 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
22831 /* Emit an assembler directive to set symbol visibility for DECL to
22832 VISIBILITY_TYPE. */
22835 rs6000_assemble_visibility (tree decl
, int vis
)
22840 /* Functions need to have their entry point symbol visibility set as
22841 well as their descriptor symbol visibility. */
22842 if (DEFAULT_ABI
== ABI_AIX
22844 && TREE_CODE (decl
) == FUNCTION_DECL
)
22846 static const char * const visibility_types
[] = {
22847 NULL
, "protected", "hidden", "internal"
22850 const char *name
, *type
;
22852 name
= ((* targetm
.strip_name_encoding
)
22853 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
22854 type
= visibility_types
[vis
];
22856 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
22857 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
22860 default_assemble_visibility (decl
, vis
);
22865 rs6000_reverse_condition (machine_mode mode
, enum rtx_code code
)
22867 /* Reversal of FP compares takes care -- an ordered compare
22868 becomes an unordered compare and vice versa. */
22869 if (mode
== CCFPmode
22870 && (!flag_finite_math_only
22871 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
22872 || code
== UNEQ
|| code
== LTGT
))
22873 return reverse_condition_maybe_unordered (code
);
22875 return reverse_condition (code
);
22878 /* Generate a compare for CODE. Return a brand-new rtx that
22879 represents the result of the compare. */
22882 rs6000_generate_compare (rtx cmp
, machine_mode mode
)
22884 machine_mode comp_mode
;
22885 rtx compare_result
;
22886 enum rtx_code code
= GET_CODE (cmp
);
22887 rtx op0
= XEXP (cmp
, 0);
22888 rtx op1
= XEXP (cmp
, 1);
22890 if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
22891 comp_mode
= CCmode
;
22892 else if (FLOAT_MODE_P (mode
))
22893 comp_mode
= CCFPmode
;
22894 else if (code
== GTU
|| code
== LTU
22895 || code
== GEU
|| code
== LEU
)
22896 comp_mode
= CCUNSmode
;
22897 else if ((code
== EQ
|| code
== NE
)
22898 && unsigned_reg_p (op0
)
22899 && (unsigned_reg_p (op1
)
22900 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
22901 /* These are unsigned values, perhaps there will be a later
22902 ordering compare that can be shared with this one. */
22903 comp_mode
= CCUNSmode
;
22905 comp_mode
= CCmode
;
22907 /* If we have an unsigned compare, make sure we don't have a signed value as
22909 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
22910 && INTVAL (op1
) < 0)
22912 op0
= copy_rtx_if_shared (op0
);
22913 op1
= force_reg (GET_MODE (op0
), op1
);
22914 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
22917 /* First, the compare. */
22918 compare_result
= gen_reg_rtx (comp_mode
);
22920 /* E500 FP compare instructions on the GPRs. Yuck! */
22921 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
22922 && FLOAT_MODE_P (mode
))
22924 rtx cmp
, or_result
, compare_result2
;
22925 machine_mode op_mode
= GET_MODE (op0
);
22928 if (op_mode
== VOIDmode
)
22929 op_mode
= GET_MODE (op1
);
22931 /* First reverse the condition codes that aren't directly supported. */
22939 code
= reverse_condition_maybe_unordered (code
);
22952 gcc_unreachable ();
22955 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
22956 This explains the following mess. */
22964 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
22965 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
22966 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
22970 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
22971 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
22972 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
22978 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
22979 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
22980 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
22984 gcc_unreachable ();
22993 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
22994 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
22995 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
22999 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
23000 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
23001 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
23007 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
23008 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
23009 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
23013 gcc_unreachable ();
23022 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
23023 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
23024 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
23028 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
23029 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
23030 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
23036 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
23037 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
23038 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
23042 gcc_unreachable ();
23047 gcc_unreachable ();
23050 /* Synthesize LE and GE from LT/GT || EQ. */
23051 if (code
== LE
|| code
== GE
)
23055 compare_result2
= gen_reg_rtx (CCFPmode
);
23061 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
23062 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
23063 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
23067 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
23068 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
23069 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
23075 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
23076 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
23077 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
23081 gcc_unreachable ();
23086 /* OR them together. */
23087 or_result
= gen_reg_rtx (CCFPmode
);
23088 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
23090 compare_result
= or_result
;
23093 code
= reverse_p
? NE
: EQ
;
23098 /* IEEE 128-bit support in VSX registers when we do not have hardware
23100 else if (!TARGET_FLOAT128_HW
&& FLOAT128_VECTOR_P (mode
))
23102 rtx libfunc
= NULL_RTX
;
23103 bool check_nan
= false;
23110 libfunc
= optab_libfunc (eq_optab
, mode
);
23115 libfunc
= optab_libfunc (ge_optab
, mode
);
23120 libfunc
= optab_libfunc (le_optab
, mode
);
23125 libfunc
= optab_libfunc (unord_optab
, mode
);
23126 code
= (code
== UNORDERED
) ? NE
: EQ
;
23132 libfunc
= optab_libfunc (ge_optab
, mode
);
23133 code
= (code
== UNGE
) ? GE
: GT
;
23139 libfunc
= optab_libfunc (le_optab
, mode
);
23140 code
= (code
== UNLE
) ? LE
: LT
;
23146 libfunc
= optab_libfunc (eq_optab
, mode
);
23147 code
= (code
= UNEQ
) ? EQ
: NE
;
23151 gcc_unreachable ();
23154 gcc_assert (libfunc
);
23157 dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
23158 SImode
, 2, op0
, mode
, op1
, mode
);
23160 /* The library signals an exception for signalling NaNs, so we need to
23161 handle isgreater, etc. by first checking isordered. */
23164 rtx ne_rtx
, normal_dest
, unord_dest
;
23165 rtx unord_func
= optab_libfunc (unord_optab
, mode
);
23166 rtx join_label
= gen_label_rtx ();
23167 rtx join_ref
= gen_rtx_LABEL_REF (VOIDmode
, join_label
);
23168 rtx unord_cmp
= gen_reg_rtx (comp_mode
);
23171 /* Test for either value being a NaN. */
23172 gcc_assert (unord_func
);
23173 unord_dest
= emit_library_call_value (unord_func
, NULL_RTX
, LCT_CONST
,
23174 SImode
, 2, op0
, mode
, op1
,
23177 /* Set value (0) if either value is a NaN, and jump to the join
23179 dest
= gen_reg_rtx (SImode
);
23180 emit_move_insn (dest
, const1_rtx
);
23181 emit_insn (gen_rtx_SET (unord_cmp
,
23182 gen_rtx_COMPARE (comp_mode
, unord_dest
,
23185 ne_rtx
= gen_rtx_NE (comp_mode
, unord_cmp
, const0_rtx
);
23186 emit_jump_insn (gen_rtx_SET (pc_rtx
,
23187 gen_rtx_IF_THEN_ELSE (VOIDmode
, ne_rtx
,
23191 /* Do the normal comparison, knowing that the values are not
23193 normal_dest
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
23194 SImode
, 2, op0
, mode
, op1
,
23197 emit_insn (gen_cstoresi4 (dest
,
23198 gen_rtx_fmt_ee (code
, SImode
, normal_dest
,
23200 normal_dest
, const0_rtx
));
23202 /* Join NaN and non-Nan paths. Compare dest against 0. */
23203 emit_label (join_label
);
23207 emit_insn (gen_rtx_SET (compare_result
,
23208 gen_rtx_COMPARE (comp_mode
, dest
, const0_rtx
)));
23213 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
23214 CLOBBERs to match cmptf_internal2 pattern. */
23215 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
23216 && FLOAT128_IBM_P (GET_MODE (op0
))
23217 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
23218 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
23220 gen_rtx_SET (compare_result
,
23221 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
23222 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
23223 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
23224 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
23225 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
23226 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
23227 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
23228 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
23229 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
23230 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
23231 else if (GET_CODE (op1
) == UNSPEC
23232 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
23234 rtx op1b
= XVECEXP (op1
, 0, 0);
23235 comp_mode
= CCEQmode
;
23236 compare_result
= gen_reg_rtx (CCEQmode
);
23238 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
23240 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
23243 emit_insn (gen_rtx_SET (compare_result
,
23244 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
23247 /* Some kinds of FP comparisons need an OR operation;
23248 under flag_finite_math_only we don't bother. */
23249 if (FLOAT_MODE_P (mode
)
23250 && (!FLOAT128_IEEE_P (mode
) || TARGET_FLOAT128_HW
)
23251 && !flag_finite_math_only
23252 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
23253 && (code
== LE
|| code
== GE
23254 || code
== UNEQ
|| code
== LTGT
23255 || code
== UNGT
|| code
== UNLT
))
23257 enum rtx_code or1
, or2
;
23258 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
23259 rtx or_result
= gen_reg_rtx (CCEQmode
);
23263 case LE
: or1
= LT
; or2
= EQ
; break;
23264 case GE
: or1
= GT
; or2
= EQ
; break;
23265 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
23266 case LTGT
: or1
= LT
; or2
= GT
; break;
23267 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
23268 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
23269 default: gcc_unreachable ();
23271 validate_condition_mode (or1
, comp_mode
);
23272 validate_condition_mode (or2
, comp_mode
);
23273 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
23274 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
23275 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
23276 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
23278 emit_insn (gen_rtx_SET (or_result
, compare2_rtx
));
23280 compare_result
= or_result
;
23284 validate_condition_mode (code
, GET_MODE (compare_result
));
23286 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
23290 /* Return the diagnostic message string if the binary operation OP is
23291 not permitted on TYPE1 and TYPE2, NULL otherwise. */
23294 rs6000_invalid_binary_op (int op ATTRIBUTE_UNUSED
,
23298 enum machine_mode mode1
= TYPE_MODE (type1
);
23299 enum machine_mode mode2
= TYPE_MODE (type2
);
23301 /* For complex modes, use the inner type. */
23302 if (COMPLEX_MODE_P (mode1
))
23303 mode1
= GET_MODE_INNER (mode1
);
23305 if (COMPLEX_MODE_P (mode2
))
23306 mode2
= GET_MODE_INNER (mode2
);
23308 /* Don't allow IEEE 754R 128-bit binary floating point and IBM extended
23309 double to intermix unless -mfloat128-convert. */
23310 if (mode1
== mode2
)
23313 if (!TARGET_FLOAT128_CVT
)
23315 if ((mode1
== KFmode
&& mode2
== IFmode
)
23316 || (mode1
== IFmode
&& mode2
== KFmode
))
23317 return N_("__float128 and __ibm128 cannot be used in the same "
23320 if (TARGET_IEEEQUAD
23321 && ((mode1
== IFmode
&& mode2
== TFmode
)
23322 || (mode1
== TFmode
&& mode2
== IFmode
)))
23323 return N_("__ibm128 and long double cannot be used in the same "
23326 if (!TARGET_IEEEQUAD
23327 && ((mode1
== KFmode
&& mode2
== TFmode
)
23328 || (mode1
== TFmode
&& mode2
== KFmode
)))
23329 return N_("__float128 and long double cannot be used in the same "
23337 /* Expand floating point conversion to/from __float128 and __ibm128. */
23340 rs6000_expand_float128_convert (rtx dest
, rtx src
, bool unsigned_p
)
23342 machine_mode dest_mode
= GET_MODE (dest
);
23343 machine_mode src_mode
= GET_MODE (src
);
23344 convert_optab cvt
= unknown_optab
;
23345 bool do_move
= false;
23346 rtx libfunc
= NULL_RTX
;
23348 typedef rtx (*rtx_2func_t
) (rtx
, rtx
);
23349 rtx_2func_t hw_convert
= (rtx_2func_t
)0;
23353 rtx_2func_t from_df
;
23354 rtx_2func_t from_sf
;
23355 rtx_2func_t from_si_sign
;
23356 rtx_2func_t from_si_uns
;
23357 rtx_2func_t from_di_sign
;
23358 rtx_2func_t from_di_uns
;
23361 rtx_2func_t to_si_sign
;
23362 rtx_2func_t to_si_uns
;
23363 rtx_2func_t to_di_sign
;
23364 rtx_2func_t to_di_uns
;
23365 } hw_conversions
[2] = {
23366 /* convertions to/from KFmode */
23368 gen_extenddfkf2_hw
, /* KFmode <- DFmode. */
23369 gen_extendsfkf2_hw
, /* KFmode <- SFmode. */
23370 gen_float_kfsi2_hw
, /* KFmode <- SImode (signed). */
23371 gen_floatuns_kfsi2_hw
, /* KFmode <- SImode (unsigned). */
23372 gen_float_kfdi2_hw
, /* KFmode <- DImode (signed). */
23373 gen_floatuns_kfdi2_hw
, /* KFmode <- DImode (unsigned). */
23374 gen_trunckfdf2_hw
, /* DFmode <- KFmode. */
23375 gen_trunckfsf2_hw
, /* SFmode <- KFmode. */
23376 gen_fix_kfsi2_hw
, /* SImode <- KFmode (signed). */
23377 gen_fixuns_kfsi2_hw
, /* SImode <- KFmode (unsigned). */
23378 gen_fix_kfdi2_hw
, /* DImode <- KFmode (signed). */
23379 gen_fixuns_kfdi2_hw
, /* DImode <- KFmode (unsigned). */
23382 /* convertions to/from TFmode */
23384 gen_extenddftf2_hw
, /* TFmode <- DFmode. */
23385 gen_extendsftf2_hw
, /* TFmode <- SFmode. */
23386 gen_float_tfsi2_hw
, /* TFmode <- SImode (signed). */
23387 gen_floatuns_tfsi2_hw
, /* TFmode <- SImode (unsigned). */
23388 gen_float_tfdi2_hw
, /* TFmode <- DImode (signed). */
23389 gen_floatuns_tfdi2_hw
, /* TFmode <- DImode (unsigned). */
23390 gen_trunctfdf2_hw
, /* DFmode <- TFmode. */
23391 gen_trunctfsf2_hw
, /* SFmode <- TFmode. */
23392 gen_fix_tfsi2_hw
, /* SImode <- TFmode (signed). */
23393 gen_fixuns_tfsi2_hw
, /* SImode <- TFmode (unsigned). */
23394 gen_fix_tfdi2_hw
, /* DImode <- TFmode (signed). */
23395 gen_fixuns_tfdi2_hw
, /* DImode <- TFmode (unsigned). */
23399 if (dest_mode
== src_mode
)
23400 gcc_unreachable ();
23402 /* Eliminate memory operations. */
23404 src
= force_reg (src_mode
, src
);
23408 rtx tmp
= gen_reg_rtx (dest_mode
);
23409 rs6000_expand_float128_convert (tmp
, src
, unsigned_p
);
23410 rs6000_emit_move (dest
, tmp
, dest_mode
);
23414 /* Convert to IEEE 128-bit floating point. */
23415 if (FLOAT128_IEEE_P (dest_mode
))
23417 if (dest_mode
== KFmode
)
23419 else if (dest_mode
== TFmode
)
23422 gcc_unreachable ();
23428 hw_convert
= hw_conversions
[kf_or_tf
].from_df
;
23433 hw_convert
= hw_conversions
[kf_or_tf
].from_sf
;
23439 if (FLOAT128_IBM_P (src_mode
))
23448 cvt
= ufloat_optab
;
23449 hw_convert
= hw_conversions
[kf_or_tf
].from_si_uns
;
23453 cvt
= sfloat_optab
;
23454 hw_convert
= hw_conversions
[kf_or_tf
].from_si_sign
;
23461 cvt
= ufloat_optab
;
23462 hw_convert
= hw_conversions
[kf_or_tf
].from_di_uns
;
23466 cvt
= sfloat_optab
;
23467 hw_convert
= hw_conversions
[kf_or_tf
].from_di_sign
;
23472 gcc_unreachable ();
23476 /* Convert from IEEE 128-bit floating point. */
23477 else if (FLOAT128_IEEE_P (src_mode
))
23479 if (src_mode
== KFmode
)
23481 else if (src_mode
== TFmode
)
23484 gcc_unreachable ();
23490 hw_convert
= hw_conversions
[kf_or_tf
].to_df
;
23495 hw_convert
= hw_conversions
[kf_or_tf
].to_sf
;
23501 if (FLOAT128_IBM_P (dest_mode
))
23511 hw_convert
= hw_conversions
[kf_or_tf
].to_si_uns
;
23516 hw_convert
= hw_conversions
[kf_or_tf
].to_si_sign
;
23524 hw_convert
= hw_conversions
[kf_or_tf
].to_di_uns
;
23529 hw_convert
= hw_conversions
[kf_or_tf
].to_di_sign
;
23534 gcc_unreachable ();
23538 /* Both IBM format. */
23539 else if (FLOAT128_IBM_P (dest_mode
) && FLOAT128_IBM_P (src_mode
))
23543 gcc_unreachable ();
23545 /* Handle conversion between TFmode/KFmode. */
23547 emit_move_insn (dest
, gen_lowpart (dest_mode
, src
));
23549 /* Handle conversion if we have hardware support. */
23550 else if (TARGET_FLOAT128_HW
&& hw_convert
)
23551 emit_insn ((hw_convert
) (dest
, src
));
23553 /* Call an external function to do the conversion. */
23554 else if (cvt
!= unknown_optab
)
23556 libfunc
= convert_optab_libfunc (cvt
, dest_mode
, src_mode
);
23557 gcc_assert (libfunc
!= NULL_RTX
);
23559 dest2
= emit_library_call_value (libfunc
, dest
, LCT_CONST
, dest_mode
, 1, src
,
23562 gcc_assert (dest2
!= NULL_RTX
);
23563 if (!rtx_equal_p (dest
, dest2
))
23564 emit_move_insn (dest
, dest2
);
23568 gcc_unreachable ();
23573 /* Split a conversion from __float128 to an integer type into separate insns.
23574 OPERANDS points to the destination, source, and V2DI temporary
23575 register. CODE is either FIX or UNSIGNED_FIX. */
23578 convert_float128_to_int (rtx
*operands
, enum rtx_code code
)
23580 rtx dest
= operands
[0];
23581 rtx src
= operands
[1];
23582 rtx tmp
= operands
[2];
23589 if (GET_CODE (tmp
) == SCRATCH
)
23590 tmp
= gen_reg_rtx (V2DImode
);
23593 dest
= rs6000_address_for_fpconvert (dest
);
23595 /* Generate the actual convert insn of the form:
23596 (set (tmp) (unspec:V2DI [(fix:SI (reg:KF))] UNSPEC_IEEE128_CONVERT)). */
23597 cvt
= gen_rtx_fmt_e (code
, GET_MODE (dest
), src
);
23598 cvt_vec
= gen_rtvec (1, cvt
);
23599 cvt_unspec
= gen_rtx_UNSPEC (V2DImode
, cvt_vec
, UNSPEC_IEEE128_CONVERT
);
23600 emit_insn (gen_rtx_SET (tmp
, cvt_unspec
));
23602 /* Generate the move insn of the form:
23603 (set (dest:SI) (unspec:SI [(tmp:V2DI))] UNSPEC_IEEE128_MOVE)). */
23604 move_vec
= gen_rtvec (1, tmp
);
23605 move_unspec
= gen_rtx_UNSPEC (GET_MODE (dest
), move_vec
, UNSPEC_IEEE128_MOVE
);
23606 emit_insn (gen_rtx_SET (dest
, move_unspec
));
23609 /* Split a conversion from an integer type to __float128 into separate insns.
23610 OPERANDS points to the destination, source, and V2DI temporary
23611 register. CODE is either FLOAT or UNSIGNED_FLOAT. */
23614 convert_int_to_float128 (rtx
*operands
, enum rtx_code code
)
23616 rtx dest
= operands
[0];
23617 rtx src
= operands
[1];
23618 rtx tmp
= operands
[2];
23626 if (GET_CODE (tmp
) == SCRATCH
)
23627 tmp
= gen_reg_rtx (V2DImode
);
23630 src
= rs6000_address_for_fpconvert (src
);
23632 /* Generate the move of the integer into the Altivec register of the form:
23633 (set (tmp:V2DI) (unspec:V2DI [(src:SI)
23634 (const_int 0)] UNSPEC_IEEE128_MOVE)).
23637 (set (tmp:V2DI) (unspec:V2DI [(src:DI)] UNSPEC_IEEE128_MOVE)). */
23639 if (GET_MODE (src
) == SImode
)
23641 unsigned_flag
= (code
== UNSIGNED_FLOAT
) ? const1_rtx
: const0_rtx
;
23642 move_vec
= gen_rtvec (2, src
, unsigned_flag
);
23645 move_vec
= gen_rtvec (1, src
);
23647 move_unspec
= gen_rtx_UNSPEC (V2DImode
, move_vec
, UNSPEC_IEEE128_MOVE
);
23648 emit_insn (gen_rtx_SET (tmp
, move_unspec
));
23650 /* Generate the actual convert insn of the form:
23651 (set (dest:KF) (float:KF (unspec:DI [(tmp:V2DI)]
23652 UNSPEC_IEEE128_CONVERT))). */
23653 cvt_vec
= gen_rtvec (1, tmp
);
23654 cvt_unspec
= gen_rtx_UNSPEC (DImode
, cvt_vec
, UNSPEC_IEEE128_CONVERT
);
23655 cvt
= gen_rtx_fmt_e (code
, GET_MODE (dest
), cvt_unspec
);
23656 emit_insn (gen_rtx_SET (dest
, cvt
));
23660 /* Emit the RTL for an sISEL pattern. */
23663 rs6000_emit_sISEL (machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
23665 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
23668 /* Emit RTL that sets a register to zero if OP1 and OP2 are equal. SCRATCH
23669 can be used as that dest register. Return the dest register. */
23672 rs6000_emit_eqne (machine_mode mode
, rtx op1
, rtx op2
, rtx scratch
)
23674 if (op2
== const0_rtx
)
23677 if (GET_CODE (scratch
) == SCRATCH
)
23678 scratch
= gen_reg_rtx (mode
);
23680 if (logical_operand (op2
, mode
))
23681 emit_insn (gen_rtx_SET (scratch
, gen_rtx_XOR (mode
, op1
, op2
)));
23683 emit_insn (gen_rtx_SET (scratch
,
23684 gen_rtx_PLUS (mode
, op1
, negate_rtx (mode
, op2
))));
23690 rs6000_emit_sCOND (machine_mode mode
, rtx operands
[])
23693 machine_mode op_mode
;
23694 enum rtx_code cond_code
;
23695 rtx result
= operands
[0];
23697 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
23698 cond_code
= GET_CODE (condition_rtx
);
23700 if (FLOAT_MODE_P (mode
)
23701 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
23705 PUT_MODE (condition_rtx
, SImode
);
23706 t
= XEXP (condition_rtx
, 0);
23708 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
23710 if (cond_code
== NE
)
23711 emit_insn (gen_e500_flip_gt_bit (t
, t
));
23713 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
23717 if (cond_code
== NE
23718 || cond_code
== GE
|| cond_code
== LE
23719 || cond_code
== GEU
|| cond_code
== LEU
23720 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
23722 rtx not_result
= gen_reg_rtx (CCEQmode
);
23723 rtx not_op
, rev_cond_rtx
;
23724 machine_mode cc_mode
;
23726 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
23728 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
23729 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
23730 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
23731 emit_insn (gen_rtx_SET (not_result
, not_op
));
23732 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
23735 op_mode
= GET_MODE (XEXP (operands
[1], 0));
23736 if (op_mode
== VOIDmode
)
23737 op_mode
= GET_MODE (XEXP (operands
[1], 1));
23739 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
23741 PUT_MODE (condition_rtx
, DImode
);
23742 convert_move (result
, condition_rtx
, 0);
23746 PUT_MODE (condition_rtx
, SImode
);
23747 emit_insn (gen_rtx_SET (result
, condition_rtx
));
23751 /* Emit a branch of kind CODE to location LOC. */
23754 rs6000_emit_cbranch (machine_mode mode
, rtx operands
[])
23756 rtx condition_rtx
, loc_ref
;
23758 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
23759 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
23760 emit_jump_insn (gen_rtx_SET (pc_rtx
,
23761 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
23762 loc_ref
, pc_rtx
)));
23765 /* Return the string to output a conditional branch to LABEL, which is
23766 the operand template of the label, or NULL if the branch is really a
23767 conditional return.
23769 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
23770 condition code register and its mode specifies what kind of
23771 comparison we made.
23773 REVERSED is nonzero if we should reverse the sense of the comparison.
23775 INSN is the insn. */
23778 output_cbranch (rtx op
, const char *label
, int reversed
, rtx_insn
*insn
)
23780 static char string
[64];
23781 enum rtx_code code
= GET_CODE (op
);
23782 rtx cc_reg
= XEXP (op
, 0);
23783 machine_mode mode
= GET_MODE (cc_reg
);
23784 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
23785 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
23786 int really_reversed
= reversed
^ need_longbranch
;
23792 validate_condition_mode (code
, mode
);
23794 /* Work out which way this really branches. We could use
23795 reverse_condition_maybe_unordered here always but this
23796 makes the resulting assembler clearer. */
23797 if (really_reversed
)
23799 /* Reversal of FP compares takes care -- an ordered compare
23800 becomes an unordered compare and vice versa. */
23801 if (mode
== CCFPmode
)
23802 code
= reverse_condition_maybe_unordered (code
);
23804 code
= reverse_condition (code
);
23807 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
23809 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
23814 /* Opposite of GT. */
23823 gcc_unreachable ();
23829 /* Not all of these are actually distinct opcodes, but
23830 we distinguish them for clarity of the resulting assembler. */
23831 case NE
: case LTGT
:
23832 ccode
= "ne"; break;
23833 case EQ
: case UNEQ
:
23834 ccode
= "eq"; break;
23836 ccode
= "ge"; break;
23837 case GT
: case GTU
: case UNGT
:
23838 ccode
= "gt"; break;
23840 ccode
= "le"; break;
23841 case LT
: case LTU
: case UNLT
:
23842 ccode
= "lt"; break;
23843 case UNORDERED
: ccode
= "un"; break;
23844 case ORDERED
: ccode
= "nu"; break;
23845 case UNGE
: ccode
= "nl"; break;
23846 case UNLE
: ccode
= "ng"; break;
23848 gcc_unreachable ();
23851 /* Maybe we have a guess as to how likely the branch is. */
23853 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
23854 if (note
!= NULL_RTX
)
23856 /* PROB is the difference from 50%. */
23857 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
23859 /* Only hint for highly probable/improbable branches on newer cpus when
23860 we have real profile data, as static prediction overrides processor
23861 dynamic prediction. For older cpus we may as well always hint, but
23862 assume not taken for branches that are very close to 50% as a
23863 mispredicted taken branch is more expensive than a
23864 mispredicted not-taken branch. */
23865 if (rs6000_always_hint
23866 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
23867 && (profile_status_for_fn (cfun
) != PROFILE_GUESSED
)
23868 && br_prob_note_reliable_p (note
)))
23870 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
23871 && ((prob
> 0) ^ need_longbranch
))
23879 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
23881 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
23883 /* We need to escape any '%' characters in the reg_names string.
23884 Assume they'd only be the first character.... */
23885 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
23887 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
23891 /* If the branch distance was too far, we may have to use an
23892 unconditional branch to go the distance. */
23893 if (need_longbranch
)
23894 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
23896 s
+= sprintf (s
, ",%s", label
);
23902 /* Return the string to flip the GT bit on a CR. */
23904 output_e500_flip_gt_bit (rtx dst
, rtx src
)
23906 static char string
[64];
23909 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
23910 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
23913 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
23914 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
23916 sprintf (string
, "crnot %d,%d", a
, b
);
23920 /* Return insn for VSX or Altivec comparisons. */
23923 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
23926 machine_mode mode
= GET_MODE (op0
);
23934 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
23945 mask
= gen_reg_rtx (mode
);
23946 emit_insn (gen_rtx_SET (mask
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
23953 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
23954 DMODE is expected destination mode. This is a recursive function. */
23957 rs6000_emit_vector_compare (enum rtx_code rcode
,
23959 machine_mode dmode
)
23962 bool swap_operands
= false;
23963 bool try_again
= false;
23965 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
23966 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
23968 /* See if the comparison works as is. */
23969 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
23977 swap_operands
= true;
23982 swap_operands
= true;
23990 /* Invert condition and try again.
23991 e.g., A != B becomes ~(A==B). */
23993 enum rtx_code rev_code
;
23994 enum insn_code nor_code
;
23997 rev_code
= reverse_condition_maybe_unordered (rcode
);
23998 if (rev_code
== UNKNOWN
)
24001 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
24002 if (nor_code
== CODE_FOR_nothing
)
24005 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
24009 mask
= gen_reg_rtx (dmode
);
24010 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
24018 /* Try GT/GTU/LT/LTU OR EQ */
24021 enum insn_code ior_code
;
24022 enum rtx_code new_code
;
24043 gcc_unreachable ();
24046 ior_code
= optab_handler (ior_optab
, dmode
);
24047 if (ior_code
== CODE_FOR_nothing
)
24050 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
24054 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
24058 mask
= gen_reg_rtx (dmode
);
24059 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
24070 std::swap (op0
, op1
);
24072 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
24077 /* You only get two chances. */
24081 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
24082 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
24083 operands for the relation operation COND. */
24086 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
24087 rtx cond
, rtx cc_op0
, rtx cc_op1
)
24089 machine_mode dest_mode
= GET_MODE (dest
);
24090 machine_mode mask_mode
= GET_MODE (cc_op0
);
24091 enum rtx_code rcode
= GET_CODE (cond
);
24092 machine_mode cc_mode
= CCmode
;
24096 bool invert_move
= false;
24098 if (VECTOR_UNIT_NONE_P (dest_mode
))
24101 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
24102 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
24106 /* Swap operands if we can, and fall back to doing the operation as
24107 specified, and doing a NOR to invert the test. */
24113 /* Invert condition and try again.
24114 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
24115 invert_move
= true;
24116 rcode
= reverse_condition_maybe_unordered (rcode
);
24117 if (rcode
== UNKNOWN
)
24121 /* Mark unsigned tests with CCUNSmode. */
24126 cc_mode
= CCUNSmode
;
24133 /* Get the vector mask for the given relational operations. */
24134 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
24142 op_true
= op_false
;
24146 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
24147 CONST0_RTX (dest_mode
));
24148 emit_insn (gen_rtx_SET (dest
,
24149 gen_rtx_IF_THEN_ELSE (dest_mode
,
24156 /* ISA 3.0 (power9) minmax subcase to emit a XSMAXCDP or XSMINCDP instruction
24157 for SF/DF scalars. Move TRUE_COND to DEST if OP of the operands of the last
24158 comparison is nonzero/true, FALSE_COND if it is zero/false. Return 0 if the
24159 hardware has no such operation. */
24162 rs6000_emit_p9_fp_minmax (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
24164 enum rtx_code code
= GET_CODE (op
);
24165 rtx op0
= XEXP (op
, 0);
24166 rtx op1
= XEXP (op
, 1);
24167 machine_mode compare_mode
= GET_MODE (op0
);
24168 machine_mode result_mode
= GET_MODE (dest
);
24169 bool max_p
= false;
24171 if (result_mode
!= compare_mode
)
24174 if (code
== GE
|| code
== GT
)
24176 else if (code
== LE
|| code
== LT
)
24181 if (rtx_equal_p (op0
, true_cond
) && rtx_equal_p (op1
, false_cond
))
24184 else if (rtx_equal_p (op1
, true_cond
) && rtx_equal_p (op0
, false_cond
))
24190 rs6000_emit_minmax (dest
, max_p
? SMAX
: SMIN
, op0
, op1
);
24194 /* ISA 3.0 (power9) conditional move subcase to emit XSCMP{EQ,GE,GT,NE}DP and
24195 XXSEL instructions for SF/DF scalars. Move TRUE_COND to DEST if OP of the
24196 operands of the last comparison is nonzero/true, FALSE_COND if it is
24197 zero/false. Return 0 if the hardware has no such operation. */
24200 rs6000_emit_p9_fp_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
24202 enum rtx_code code
= GET_CODE (op
);
24203 rtx op0
= XEXP (op
, 0);
24204 rtx op1
= XEXP (op
, 1);
24205 machine_mode result_mode
= GET_MODE (dest
);
24210 if (!can_create_pseudo_p ())
24223 code
= swap_condition (code
);
24224 std::swap (op0
, op1
);
24231 /* Generate: [(parallel [(set (dest)
24232 (if_then_else (op (cmp1) (cmp2))
24235 (clobber (scratch))])]. */
24237 compare_rtx
= gen_rtx_fmt_ee (code
, CCFPmode
, op0
, op1
);
24238 cmove_rtx
= gen_rtx_SET (dest
,
24239 gen_rtx_IF_THEN_ELSE (result_mode
,
24244 clobber_rtx
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (V2DImode
));
24245 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
24246 gen_rtvec (2, cmove_rtx
, clobber_rtx
)));
24251 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
24252 operands of the last comparison is nonzero/true, FALSE_COND if it
24253 is zero/false. Return 0 if the hardware has no such operation. */
24256 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
24258 enum rtx_code code
= GET_CODE (op
);
24259 rtx op0
= XEXP (op
, 0);
24260 rtx op1
= XEXP (op
, 1);
24261 machine_mode compare_mode
= GET_MODE (op0
);
24262 machine_mode result_mode
= GET_MODE (dest
);
24264 bool is_against_zero
;
24266 /* These modes should always match. */
24267 if (GET_MODE (op1
) != compare_mode
24268 /* In the isel case however, we can use a compare immediate, so
24269 op1 may be a small constant. */
24270 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
24272 if (GET_MODE (true_cond
) != result_mode
)
24274 if (GET_MODE (false_cond
) != result_mode
)
24277 /* See if we can use the ISA 3.0 (power9) min/max/compare functions. */
24278 if (TARGET_P9_MINMAX
24279 && (compare_mode
== SFmode
|| compare_mode
== DFmode
)
24280 && (result_mode
== SFmode
|| result_mode
== DFmode
))
24282 if (rs6000_emit_p9_fp_minmax (dest
, op
, true_cond
, false_cond
))
24285 if (rs6000_emit_p9_fp_cmove (dest
, op
, true_cond
, false_cond
))
24289 /* Don't allow using floating point comparisons for integer results for
24291 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
24294 /* First, work out if the hardware can do this at all, or
24295 if it's too slow.... */
24296 if (!FLOAT_MODE_P (compare_mode
))
24299 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
24302 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
24303 && SCALAR_FLOAT_MODE_P (compare_mode
))
24306 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
24308 /* A floating-point subtract might overflow, underflow, or produce
24309 an inexact result, thus changing the floating-point flags, so it
24310 can't be generated if we care about that. It's safe if one side
24311 of the construct is zero, since then no subtract will be
24313 if (SCALAR_FLOAT_MODE_P (compare_mode
)
24314 && flag_trapping_math
&& ! is_against_zero
)
24317 /* Eliminate half of the comparisons by switching operands, this
24318 makes the remaining code simpler. */
24319 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
24320 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
24322 code
= reverse_condition_maybe_unordered (code
);
24324 true_cond
= false_cond
;
24328 /* UNEQ and LTGT take four instructions for a comparison with zero,
24329 it'll probably be faster to use a branch here too. */
24330 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
24333 /* We're going to try to implement comparisons by performing
24334 a subtract, then comparing against zero. Unfortunately,
24335 Inf - Inf is NaN which is not zero, and so if we don't
24336 know that the operand is finite and the comparison
24337 would treat EQ different to UNORDERED, we can't do it. */
24338 if (HONOR_INFINITIES (compare_mode
)
24339 && code
!= GT
&& code
!= UNGE
24340 && (GET_CODE (op1
) != CONST_DOUBLE
24341 || real_isinf (CONST_DOUBLE_REAL_VALUE (op1
)))
24342 /* Constructs of the form (a OP b ? a : b) are safe. */
24343 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
24344 || (! rtx_equal_p (op0
, true_cond
)
24345 && ! rtx_equal_p (op1
, true_cond
))))
24348 /* At this point we know we can use fsel. */
24350 /* Reduce the comparison to a comparison against zero. */
24351 if (! is_against_zero
)
24353 temp
= gen_reg_rtx (compare_mode
);
24354 emit_insn (gen_rtx_SET (temp
, gen_rtx_MINUS (compare_mode
, op0
, op1
)));
24356 op1
= CONST0_RTX (compare_mode
);
24359 /* If we don't care about NaNs we can reduce some of the comparisons
24360 down to faster ones. */
24361 if (! HONOR_NANS (compare_mode
))
24367 true_cond
= false_cond
;
24380 /* Now, reduce everything down to a GE. */
24387 temp
= gen_reg_rtx (compare_mode
);
24388 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
24393 temp
= gen_reg_rtx (compare_mode
);
24394 emit_insn (gen_rtx_SET (temp
, gen_rtx_ABS (compare_mode
, op0
)));
24399 temp
= gen_reg_rtx (compare_mode
);
24400 emit_insn (gen_rtx_SET (temp
,
24401 gen_rtx_NEG (compare_mode
,
24402 gen_rtx_ABS (compare_mode
, op0
))));
24407 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
24408 temp
= gen_reg_rtx (result_mode
);
24409 emit_insn (gen_rtx_SET (temp
,
24410 gen_rtx_IF_THEN_ELSE (result_mode
,
24411 gen_rtx_GE (VOIDmode
,
24413 true_cond
, false_cond
)));
24414 false_cond
= true_cond
;
24417 temp
= gen_reg_rtx (compare_mode
);
24418 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
24423 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
24424 temp
= gen_reg_rtx (result_mode
);
24425 emit_insn (gen_rtx_SET (temp
,
24426 gen_rtx_IF_THEN_ELSE (result_mode
,
24427 gen_rtx_GE (VOIDmode
,
24429 true_cond
, false_cond
)));
24430 true_cond
= false_cond
;
24433 temp
= gen_reg_rtx (compare_mode
);
24434 emit_insn (gen_rtx_SET (temp
, gen_rtx_NEG (compare_mode
, op0
)));
24439 gcc_unreachable ();
24442 emit_insn (gen_rtx_SET (dest
,
24443 gen_rtx_IF_THEN_ELSE (result_mode
,
24444 gen_rtx_GE (VOIDmode
,
24446 true_cond
, false_cond
)));
24450 /* Same as above, but for ints (isel). */
24453 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
24455 rtx condition_rtx
, cr
;
24456 machine_mode mode
= GET_MODE (dest
);
24457 enum rtx_code cond_code
;
24458 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
24461 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
24464 /* We still have to do the compare, because isel doesn't do a
24465 compare, it just looks at the CRx bits set by a previous compare
24467 condition_rtx
= rs6000_generate_compare (op
, mode
);
24468 cond_code
= GET_CODE (condition_rtx
);
24469 cr
= XEXP (condition_rtx
, 0);
24470 signedp
= GET_MODE (cr
) == CCmode
;
24472 isel_func
= (mode
== SImode
24473 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
24474 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
24478 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
24479 /* isel handles these directly. */
24483 /* We need to swap the sense of the comparison. */
24485 std::swap (false_cond
, true_cond
);
24486 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
24491 false_cond
= force_reg (mode
, false_cond
);
24492 if (true_cond
!= const0_rtx
)
24493 true_cond
= force_reg (mode
, true_cond
);
24495 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
24501 output_isel (rtx
*operands
)
24503 enum rtx_code code
;
24505 code
= GET_CODE (operands
[1]);
24507 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
24509 gcc_assert (GET_CODE (operands
[2]) == REG
24510 && GET_CODE (operands
[3]) == REG
);
24511 PUT_CODE (operands
[1], reverse_condition (code
));
24512 return "isel %0,%3,%2,%j1";
24515 return "isel %0,%2,%3,%j1";
24519 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
24521 machine_mode mode
= GET_MODE (op0
);
24525 /* VSX/altivec have direct min/max insns. */
24526 if ((code
== SMAX
|| code
== SMIN
)
24527 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
24528 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
24530 emit_insn (gen_rtx_SET (dest
, gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
24534 if (code
== SMAX
|| code
== SMIN
)
24539 if (code
== SMAX
|| code
== UMAX
)
24540 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
24541 op0
, op1
, mode
, 0);
24543 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
24544 op1
, op0
, mode
, 0);
24545 gcc_assert (target
);
24546 if (target
!= dest
)
24547 emit_move_insn (dest
, target
);
24550 /* Split a signbit operation on 64-bit machines with direct move. Also allow
24551 for the value to come from memory or if it is already loaded into a GPR. */
24554 rs6000_split_signbit (rtx dest
, rtx src
)
24556 machine_mode d_mode
= GET_MODE (dest
);
24557 machine_mode s_mode
= GET_MODE (src
);
24558 rtx dest_di
= (d_mode
== DImode
) ? dest
: gen_lowpart (DImode
, dest
);
24559 rtx shift_reg
= dest_di
;
24561 gcc_assert (REG_P (dest
));
24562 gcc_assert (REG_P (src
) || MEM_P (src
));
24563 gcc_assert (s_mode
== KFmode
|| s_mode
== TFmode
);
24567 rtx mem
= (WORDS_BIG_ENDIAN
24568 ? adjust_address (src
, DImode
, 0)
24569 : adjust_address (src
, DImode
, 8));
24570 emit_insn (gen_rtx_SET (dest_di
, mem
));
24575 unsigned int r
= REGNO (src
);
24577 /* If this is a VSX register, generate the special mfvsrd instruction
24578 to get it in a GPR. Until we support SF and DF modes, that will
24580 gcc_assert (VSX_REGNO_P (r
));
24582 if (s_mode
== KFmode
)
24583 emit_insn (gen_signbitkf2_dm2 (dest_di
, src
));
24585 emit_insn (gen_signbittf2_dm2 (dest_di
, src
));
24588 emit_insn (gen_lshrdi3 (dest_di
, shift_reg
, GEN_INT (63)));
24592 /* A subroutine of the atomic operation splitters. Jump to LABEL if
24593 COND is true. Mark the jump as unlikely to be taken. */
24596 emit_unlikely_jump (rtx cond
, rtx label
)
24598 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
24601 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
24602 x
= emit_jump_insn (gen_rtx_SET (pc_rtx
, x
));
24603 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
24606 /* A subroutine of the atomic operation splitters. Emit a load-locked
24607 instruction in MODE. For QI/HImode, possibly use a pattern than includes
24608 the zero_extend operation. */
24611 emit_load_locked (machine_mode mode
, rtx reg
, rtx mem
)
24613 rtx (*fn
) (rtx
, rtx
) = NULL
;
24618 fn
= gen_load_lockedqi
;
24621 fn
= gen_load_lockedhi
;
24624 if (GET_MODE (mem
) == QImode
)
24625 fn
= gen_load_lockedqi_si
;
24626 else if (GET_MODE (mem
) == HImode
)
24627 fn
= gen_load_lockedhi_si
;
24629 fn
= gen_load_lockedsi
;
24632 fn
= gen_load_lockeddi
;
24635 fn
= gen_load_lockedti
;
24638 gcc_unreachable ();
24640 emit_insn (fn (reg
, mem
));
24643 /* A subroutine of the atomic operation splitters. Emit a store-conditional
24644 instruction in MODE. */
24647 emit_store_conditional (machine_mode mode
, rtx res
, rtx mem
, rtx val
)
24649 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
24654 fn
= gen_store_conditionalqi
;
24657 fn
= gen_store_conditionalhi
;
24660 fn
= gen_store_conditionalsi
;
24663 fn
= gen_store_conditionaldi
;
24666 fn
= gen_store_conditionalti
;
24669 gcc_unreachable ();
24672 /* Emit sync before stwcx. to address PPC405 Erratum. */
24673 if (PPC405_ERRATUM77
)
24674 emit_insn (gen_hwsync ());
24676 emit_insn (fn (res
, mem
, val
));
24679 /* Expand barriers before and after a load_locked/store_cond sequence. */
24682 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
24684 rtx addr
= XEXP (mem
, 0);
24685 int strict_p
= (reload_in_progress
|| reload_completed
);
24687 if (!legitimate_indirect_address_p (addr
, strict_p
)
24688 && !legitimate_indexed_address_p (addr
, strict_p
))
24690 addr
= force_reg (Pmode
, addr
);
24691 mem
= replace_equiv_address_nv (mem
, addr
);
24696 case MEMMODEL_RELAXED
:
24697 case MEMMODEL_CONSUME
:
24698 case MEMMODEL_ACQUIRE
:
24700 case MEMMODEL_RELEASE
:
24701 case MEMMODEL_ACQ_REL
:
24702 emit_insn (gen_lwsync ());
24704 case MEMMODEL_SEQ_CST
:
24705 emit_insn (gen_hwsync ());
24708 gcc_unreachable ();
24714 rs6000_post_atomic_barrier (enum memmodel model
)
24718 case MEMMODEL_RELAXED
:
24719 case MEMMODEL_CONSUME
:
24720 case MEMMODEL_RELEASE
:
24722 case MEMMODEL_ACQUIRE
:
24723 case MEMMODEL_ACQ_REL
:
24724 case MEMMODEL_SEQ_CST
:
24725 emit_insn (gen_isync ());
24728 gcc_unreachable ();
24732 /* A subroutine of the various atomic expanders. For sub-word operations,
24733 we must adjust things to operate on SImode. Given the original MEM,
24734 return a new aligned memory. Also build and return the quantities by
24735 which to shift and mask. */
24738 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
24740 rtx addr
, align
, shift
, mask
, mem
;
24741 HOST_WIDE_INT shift_mask
;
24742 machine_mode mode
= GET_MODE (orig_mem
);
24744 /* For smaller modes, we have to implement this via SImode. */
24745 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
24747 addr
= XEXP (orig_mem
, 0);
24748 addr
= force_reg (GET_MODE (addr
), addr
);
24750 /* Aligned memory containing subword. Generate a new memory. We
24751 do not want any of the existing MEM_ATTR data, as we're now
24752 accessing memory outside the original object. */
24753 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
24754 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
24755 mem
= gen_rtx_MEM (SImode
, align
);
24756 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
24757 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
24758 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
24760 /* Shift amount for subword relative to aligned word. */
24761 shift
= gen_reg_rtx (SImode
);
24762 addr
= gen_lowpart (SImode
, addr
);
24763 rtx tmp
= gen_reg_rtx (SImode
);
24764 emit_insn (gen_ashlsi3 (tmp
, addr
, GEN_INT (3)));
24765 emit_insn (gen_andsi3 (shift
, tmp
, GEN_INT (shift_mask
)));
24766 if (BYTES_BIG_ENDIAN
)
24767 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
24768 shift
, 1, OPTAB_LIB_WIDEN
);
24771 /* Mask for insertion. */
24772 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
24773 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
24779 /* A subroutine of the various atomic expanders. For sub-word operands,
24780 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
24783 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
24787 x
= gen_reg_rtx (SImode
);
24788 emit_insn (gen_rtx_SET (x
, gen_rtx_AND (SImode
,
24789 gen_rtx_NOT (SImode
, mask
),
24792 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
24797 /* A subroutine of the various atomic expanders. For sub-word operands,
24798 extract WIDE to NARROW via SHIFT. */
24801 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
24803 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
24804 wide
, 1, OPTAB_LIB_WIDEN
);
24805 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
24808 /* Expand an atomic compare and swap operation. */
24811 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
24813 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
24814 rtx label1
, label2
, x
, mask
, shift
;
24815 machine_mode mode
, orig_mode
;
24816 enum memmodel mod_s
, mod_f
;
24819 boolval
= operands
[0];
24820 retval
= operands
[1];
24822 oldval
= operands
[3];
24823 newval
= operands
[4];
24824 is_weak
= (INTVAL (operands
[5]) != 0);
24825 mod_s
= memmodel_base (INTVAL (operands
[6]));
24826 mod_f
= memmodel_base (INTVAL (operands
[7]));
24827 orig_mode
= mode
= GET_MODE (mem
);
24829 mask
= shift
= NULL_RTX
;
24830 if (mode
== QImode
|| mode
== HImode
)
24832 /* Before power8, we didn't have access to lbarx/lharx, so generate a
24833 lwarx and shift/mask operations. With power8, we need to do the
24834 comparison in SImode, but the store is still done in QI/HImode. */
24835 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
24837 if (!TARGET_SYNC_HI_QI
)
24839 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
24841 /* Shift and mask OLDVAL into position with the word. */
24842 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
24843 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
24845 /* Shift and mask NEWVAL into position within the word. */
24846 newval
= convert_modes (SImode
, mode
, newval
, 1);
24847 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
24848 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
24851 /* Prepare to adjust the return value. */
24852 retval
= gen_reg_rtx (SImode
);
24855 else if (reg_overlap_mentioned_p (retval
, oldval
))
24856 oldval
= copy_to_reg (oldval
);
24858 if (mode
!= TImode
&& !reg_or_short_operand (oldval
, mode
))
24859 oldval
= copy_to_mode_reg (mode
, oldval
);
24861 if (reg_overlap_mentioned_p (retval
, newval
))
24862 newval
= copy_to_reg (newval
);
24864 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
24869 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
24870 emit_label (XEXP (label1
, 0));
24872 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
24874 emit_load_locked (mode
, retval
, mem
);
24878 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
24879 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
24881 cond
= gen_reg_rtx (CCmode
);
24882 /* If we have TImode, synthesize a comparison. */
24883 if (mode
!= TImode
)
24884 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
24887 rtx xor1_result
= gen_reg_rtx (DImode
);
24888 rtx xor2_result
= gen_reg_rtx (DImode
);
24889 rtx or_result
= gen_reg_rtx (DImode
);
24890 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
24891 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
24892 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
24893 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
24895 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
24896 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
24897 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
24898 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
24901 emit_insn (gen_rtx_SET (cond
, x
));
24903 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
24904 emit_unlikely_jump (x
, label2
);
24908 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
24910 emit_store_conditional (orig_mode
, cond
, mem
, x
);
24914 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
24915 emit_unlikely_jump (x
, label1
);
24918 if (!is_mm_relaxed (mod_f
))
24919 emit_label (XEXP (label2
, 0));
24921 rs6000_post_atomic_barrier (mod_s
);
24923 if (is_mm_relaxed (mod_f
))
24924 emit_label (XEXP (label2
, 0));
24927 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
24928 else if (mode
!= GET_MODE (operands
[1]))
24929 convert_move (operands
[1], retval
, 1);
24931 /* In all cases, CR0 contains EQ on success, and NE on failure. */
24932 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
24933 emit_insn (gen_rtx_SET (boolval
, x
));
24936 /* Expand an atomic exchange operation. */
24939 rs6000_expand_atomic_exchange (rtx operands
[])
24941 rtx retval
, mem
, val
, cond
;
24943 enum memmodel model
;
24944 rtx label
, x
, mask
, shift
;
24946 retval
= operands
[0];
24949 model
= memmodel_base (INTVAL (operands
[3]));
24950 mode
= GET_MODE (mem
);
24952 mask
= shift
= NULL_RTX
;
24953 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
24955 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
24957 /* Shift and mask VAL into position with the word. */
24958 val
= convert_modes (SImode
, mode
, val
, 1);
24959 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
24960 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
24962 /* Prepare to adjust the return value. */
24963 retval
= gen_reg_rtx (SImode
);
24967 mem
= rs6000_pre_atomic_barrier (mem
, model
);
24969 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
24970 emit_label (XEXP (label
, 0));
24972 emit_load_locked (mode
, retval
, mem
);
24976 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
24978 cond
= gen_reg_rtx (CCmode
);
24979 emit_store_conditional (mode
, cond
, mem
, x
);
24981 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
24982 emit_unlikely_jump (x
, label
);
24984 rs6000_post_atomic_barrier (model
);
24987 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
24990 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
24991 to perform. MEM is the memory on which to operate. VAL is the second
24992 operand of the binary operator. BEFORE and AFTER are optional locations to
24993 return the value of MEM either before of after the operation. MODEL_RTX
24994 is a CONST_INT containing the memory model to use. */
24997 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
24998 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
25000 enum memmodel model
= memmodel_base (INTVAL (model_rtx
));
25001 machine_mode mode
= GET_MODE (mem
);
25002 machine_mode store_mode
= mode
;
25003 rtx label
, x
, cond
, mask
, shift
;
25004 rtx before
= orig_before
, after
= orig_after
;
25006 mask
= shift
= NULL_RTX
;
25007 /* On power8, we want to use SImode for the operation. On previous systems,
25008 use the operation in a subword and shift/mask to get the proper byte or
25010 if (mode
== QImode
|| mode
== HImode
)
25012 if (TARGET_SYNC_HI_QI
)
25014 val
= convert_modes (SImode
, mode
, val
, 1);
25016 /* Prepare to adjust the return value. */
25017 before
= gen_reg_rtx (SImode
);
25019 after
= gen_reg_rtx (SImode
);
25024 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
25026 /* Shift and mask VAL into position with the word. */
25027 val
= convert_modes (SImode
, mode
, val
, 1);
25028 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
25029 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
25035 /* We've already zero-extended VAL. That is sufficient to
25036 make certain that it does not affect other bits. */
25041 /* If we make certain that all of the other bits in VAL are
25042 set, that will be sufficient to not affect other bits. */
25043 x
= gen_rtx_NOT (SImode
, mask
);
25044 x
= gen_rtx_IOR (SImode
, x
, val
);
25045 emit_insn (gen_rtx_SET (val
, x
));
25052 /* These will all affect bits outside the field and need
25053 adjustment via MASK within the loop. */
25057 gcc_unreachable ();
25060 /* Prepare to adjust the return value. */
25061 before
= gen_reg_rtx (SImode
);
25063 after
= gen_reg_rtx (SImode
);
25064 store_mode
= mode
= SImode
;
25068 mem
= rs6000_pre_atomic_barrier (mem
, model
);
25070 label
= gen_label_rtx ();
25071 emit_label (label
);
25072 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
25074 if (before
== NULL_RTX
)
25075 before
= gen_reg_rtx (mode
);
25077 emit_load_locked (mode
, before
, mem
);
25081 x
= expand_simple_binop (mode
, AND
, before
, val
,
25082 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
25083 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
25087 after
= expand_simple_binop (mode
, code
, before
, val
,
25088 after
, 1, OPTAB_LIB_WIDEN
);
25094 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
25095 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
25096 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
25098 else if (store_mode
!= mode
)
25099 x
= convert_modes (store_mode
, mode
, x
, 1);
25101 cond
= gen_reg_rtx (CCmode
);
25102 emit_store_conditional (store_mode
, cond
, mem
, x
);
25104 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
25105 emit_unlikely_jump (x
, label
);
25107 rs6000_post_atomic_barrier (model
);
25111 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
25112 then do the calcuations in a SImode register. */
25114 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
25116 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
25118 else if (store_mode
!= mode
)
25120 /* QImode/HImode on machines with lbarx/lharx where we do the native
25121 operation and then do the calcuations in a SImode register. */
25123 convert_move (orig_before
, before
, 1);
25125 convert_move (orig_after
, after
, 1);
25127 else if (orig_after
&& after
!= orig_after
)
25128 emit_move_insn (orig_after
, after
);
25131 /* Emit instructions to move SRC to DST. Called by splitters for
25132 multi-register moves. It will emit at most one instruction for
25133 each register that is accessed; that is, it won't emit li/lis pairs
25134 (or equivalent for 64-bit code). One of SRC or DST must be a hard
25138 rs6000_split_multireg_move (rtx dst
, rtx src
)
25140 /* The register number of the first register being moved. */
25142 /* The mode that is to be moved. */
25144 /* The mode that the move is being done in, and its size. */
25145 machine_mode reg_mode
;
25147 /* The number of registers that will be moved. */
25150 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
25151 mode
= GET_MODE (dst
);
25152 nregs
= hard_regno_nregs
[reg
][mode
];
25153 if (FP_REGNO_P (reg
))
25154 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
25155 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
25156 else if (ALTIVEC_REGNO_P (reg
))
25157 reg_mode
= V16QImode
;
25158 else if (TARGET_E500_DOUBLE
&& FLOAT128_2REG_P (mode
))
25161 reg_mode
= word_mode
;
25162 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
25164 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
25166 /* TDmode residing in FP registers is special, since the ISA requires that
25167 the lower-numbered word of a register pair is always the most significant
25168 word, even in little-endian mode. This does not match the usual subreg
25169 semantics, so we cannnot use simplify_gen_subreg in those cases. Access
25170 the appropriate constituent registers "by hand" in little-endian mode.
25172 Note we do not need to check for destructive overlap here since TDmode
25173 can only reside in even/odd register pairs. */
25174 if (FP_REGNO_P (reg
) && DECIMAL_FLOAT_MODE_P (mode
) && !BYTES_BIG_ENDIAN
)
25179 for (i
= 0; i
< nregs
; i
++)
25181 if (REG_P (src
) && FP_REGNO_P (REGNO (src
)))
25182 p_src
= gen_rtx_REG (reg_mode
, REGNO (src
) + nregs
- 1 - i
);
25184 p_src
= simplify_gen_subreg (reg_mode
, src
, mode
,
25185 i
* reg_mode_size
);
25187 if (REG_P (dst
) && FP_REGNO_P (REGNO (dst
)))
25188 p_dst
= gen_rtx_REG (reg_mode
, REGNO (dst
) + nregs
- 1 - i
);
25190 p_dst
= simplify_gen_subreg (reg_mode
, dst
, mode
,
25191 i
* reg_mode_size
);
25193 emit_insn (gen_rtx_SET (p_dst
, p_src
));
25199 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
25201 /* Move register range backwards, if we might have destructive
25204 for (i
= nregs
- 1; i
>= 0; i
--)
25205 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
25206 i
* reg_mode_size
),
25207 simplify_gen_subreg (reg_mode
, src
, mode
,
25208 i
* reg_mode_size
)));
25214 bool used_update
= false;
25215 rtx restore_basereg
= NULL_RTX
;
25217 if (MEM_P (src
) && INT_REGNO_P (reg
))
25221 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
25222 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
25225 breg
= XEXP (XEXP (src
, 0), 0);
25226 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
25227 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
25228 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
25229 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
25230 src
= replace_equiv_address (src
, breg
);
25232 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
25234 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
25236 rtx basereg
= XEXP (XEXP (src
, 0), 0);
25239 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
25240 emit_insn (gen_rtx_SET (ndst
,
25241 gen_rtx_MEM (reg_mode
,
25243 used_update
= true;
25246 emit_insn (gen_rtx_SET (basereg
,
25247 XEXP (XEXP (src
, 0), 1)));
25248 src
= replace_equiv_address (src
, basereg
);
25252 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
25253 emit_insn (gen_rtx_SET (basereg
, XEXP (src
, 0)));
25254 src
= replace_equiv_address (src
, basereg
);
25258 breg
= XEXP (src
, 0);
25259 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
25260 breg
= XEXP (breg
, 0);
25262 /* If the base register we are using to address memory is
25263 also a destination reg, then change that register last. */
25265 && REGNO (breg
) >= REGNO (dst
)
25266 && REGNO (breg
) < REGNO (dst
) + nregs
)
25267 j
= REGNO (breg
) - REGNO (dst
);
25269 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
25273 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
25274 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
25277 breg
= XEXP (XEXP (dst
, 0), 0);
25278 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
25279 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
25280 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
25282 /* We have to update the breg before doing the store.
25283 Use store with update, if available. */
25287 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
25288 emit_insn (TARGET_32BIT
25289 ? (TARGET_POWERPC64
25290 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
25291 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
25292 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
25293 used_update
= true;
25296 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
25297 dst
= replace_equiv_address (dst
, breg
);
25299 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
25300 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
25302 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
25304 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
25307 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
25308 emit_insn (gen_rtx_SET (gen_rtx_MEM (reg_mode
,
25311 used_update
= true;
25314 emit_insn (gen_rtx_SET (basereg
,
25315 XEXP (XEXP (dst
, 0), 1)));
25316 dst
= replace_equiv_address (dst
, basereg
);
25320 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
25321 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
25322 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
25324 && REG_P (offsetreg
)
25325 && REGNO (basereg
) != REGNO (offsetreg
));
25326 if (REGNO (basereg
) == 0)
25328 rtx tmp
= offsetreg
;
25329 offsetreg
= basereg
;
25332 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
25333 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
25334 dst
= replace_equiv_address (dst
, basereg
);
25337 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
25338 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
25341 for (i
= 0; i
< nregs
; i
++)
25343 /* Calculate index to next subword. */
25348 /* If compiler already emitted move of first word by
25349 store with update, no need to do anything. */
25350 if (j
== 0 && used_update
)
25353 emit_insn (gen_rtx_SET (simplify_gen_subreg (reg_mode
, dst
, mode
,
25354 j
* reg_mode_size
),
25355 simplify_gen_subreg (reg_mode
, src
, mode
,
25356 j
* reg_mode_size
)));
25358 if (restore_basereg
!= NULL_RTX
)
25359 emit_insn (restore_basereg
);
25364 /* This page contains routines that are used to determine what the
25365 function prologue and epilogue code will do and write them out. */
25370 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
25373 /* Determine whether the gp REG is really used. */
25376 rs6000_reg_live_or_pic_offset_p (int reg
)
25378 /* We need to mark the PIC offset register live for the same conditions
25379 as it is set up, or otherwise it won't be saved before we clobber it. */
25381 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
&& !TARGET_SINGLE_PIC_BASE
)
25383 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
25384 && (crtl
->calls_eh_return
25385 || df_regs_ever_live_p (reg
)
25386 || get_pool_size ()))
25389 if ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
25394 /* If the function calls eh_return, claim used all the registers that would
25395 be checked for liveness otherwise. */
25397 return ((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
25398 && !call_used_regs
[reg
]);
25401 /* Return the first fixed-point register that is required to be
25402 saved. 32 if none. */
25405 first_reg_to_save (void)
25409 /* Find lowest numbered live register. */
25410 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
25411 if (save_reg_p (first_reg
))
25414 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
25415 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
25416 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
25417 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
25418 && rs6000_reg_live_or_pic_offset_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
25419 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
25423 && crtl
->uses_pic_offset_table
25424 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
25425 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
25431 /* Similar, for FP regs. */
25434 first_fp_reg_to_save (void)
25438 /* Find lowest numbered live register. */
25439 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
25440 if (save_reg_p (first_reg
))
25446 /* Similar, for AltiVec regs. */
25449 first_altivec_reg_to_save (void)
25453 /* Stack frame remains as is unless we are in AltiVec ABI. */
25454 if (! TARGET_ALTIVEC_ABI
)
25455 return LAST_ALTIVEC_REGNO
+ 1;
25457 /* On Darwin, the unwind routines are compiled without
25458 TARGET_ALTIVEC, and use save_world to save/restore the
25459 altivec registers when necessary. */
25460 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
25461 && ! TARGET_ALTIVEC
)
25462 return FIRST_ALTIVEC_REGNO
+ 20;
25464 /* Find lowest numbered live register. */
25465 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25466 if (save_reg_p (i
))
25472 /* Return a 32-bit mask of the AltiVec registers we need to set in
25473 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
25474 the 32-bit word is 0. */
25476 static unsigned int
25477 compute_vrsave_mask (void)
25479 unsigned int i
, mask
= 0;
25481 /* On Darwin, the unwind routines are compiled without
25482 TARGET_ALTIVEC, and use save_world to save/restore the
25483 call-saved altivec registers when necessary. */
25484 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
25485 && ! TARGET_ALTIVEC
)
25488 /* First, find out if we use _any_ altivec registers. */
25489 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
25490 if (df_regs_ever_live_p (i
))
25491 mask
|= ALTIVEC_REG_BIT (i
);
25496 /* Next, remove the argument registers from the set. These must
25497 be in the VRSAVE mask set by the caller, so we don't need to add
25498 them in again. More importantly, the mask we compute here is
25499 used to generate CLOBBERs in the set_vrsave insn, and we do not
25500 wish the argument registers to die. */
25501 for (i
= ALTIVEC_ARG_MIN_REG
; i
< (unsigned) crtl
->args
.info
.vregno
; i
++)
25502 mask
&= ~ALTIVEC_REG_BIT (i
);
25504 /* Similarly, remove the return value from the set. */
25507 diddle_return_value (is_altivec_return_reg
, &yes
);
25509 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
25515 /* For a very restricted set of circumstances, we can cut down the
25516 size of prologues/epilogues by calling our own save/restore-the-world
25520 compute_save_world_info (rs6000_stack_t
*info
)
25522 info
->world_save_p
= 1;
25524 = (WORLD_SAVE_P (info
)
25525 && DEFAULT_ABI
== ABI_DARWIN
25526 && !cfun
->has_nonlocal_label
25527 && info
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
25528 && info
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
25529 && info
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
25530 && info
->cr_save_p
);
25532 /* This will not work in conjunction with sibcalls. Make sure there
25533 are none. (This check is expensive, but seldom executed.) */
25534 if (WORLD_SAVE_P (info
))
25537 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
25538 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
25540 info
->world_save_p
= 0;
25545 if (WORLD_SAVE_P (info
))
25547 /* Even if we're not touching VRsave, make sure there's room on the
25548 stack for it, if it looks like we're calling SAVE_WORLD, which
25549 will attempt to save it. */
25550 info
->vrsave_size
= 4;
25552 /* If we are going to save the world, we need to save the link register too. */
25553 info
->lr_save_p
= 1;
25555 /* "Save" the VRsave register too if we're saving the world. */
25556 if (info
->vrsave_mask
== 0)
25557 info
->vrsave_mask
= compute_vrsave_mask ();
25559 /* Because the Darwin register save/restore routines only handle
25560 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
25562 gcc_assert (info
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
25563 && (info
->first_altivec_reg_save
25564 >= FIRST_SAVED_ALTIVEC_REGNO
));
25572 is_altivec_return_reg (rtx reg
, void *xyes
)
25574 bool *yes
= (bool *) xyes
;
25575 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
25580 /* Return whether REG is a global user reg or has been specifed by
25581 -ffixed-REG. We should not restore these, and so cannot use
25582 lmw or out-of-line restore functions if there are any. We also
25583 can't save them (well, emit frame notes for them), because frame
25584 unwinding during exception handling will restore saved registers. */
25587 fixed_reg_p (int reg
)
25589 /* Ignore fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] when the
25590 backend sets it, overriding anything the user might have given. */
25591 if (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
25592 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
)
25593 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
25594 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
25597 return fixed_regs
[reg
];
25600 /* Determine the strategy for savings/restoring registers. */
25603 SAVE_MULTIPLE
= 0x1,
25604 SAVE_INLINE_GPRS
= 0x2,
25605 SAVE_INLINE_FPRS
= 0x4,
25606 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x8,
25607 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x10,
25608 SAVE_INLINE_VRS
= 0x20,
25609 REST_MULTIPLE
= 0x100,
25610 REST_INLINE_GPRS
= 0x200,
25611 REST_INLINE_FPRS
= 0x400,
25612 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x800,
25613 REST_INLINE_VRS
= 0x1000
25617 rs6000_savres_strategy (rs6000_stack_t
*info
,
25618 bool using_static_chain_p
)
25622 /* Select between in-line and out-of-line save and restore of regs.
25623 First, all the obvious cases where we don't use out-of-line. */
25624 if (crtl
->calls_eh_return
25625 || cfun
->machine
->ra_need_lr
)
25626 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
25627 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
25628 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
25630 if (info
->first_gp_reg_save
== 32)
25631 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
25633 if (info
->first_fp_reg_save
== 64
25634 /* The out-of-line FP routines use double-precision stores;
25635 we can't use those routines if we don't have such stores. */
25636 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
))
25637 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
25639 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1)
25640 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
25642 /* Define cutoff for using out-of-line functions to save registers. */
25643 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
25645 if (!optimize_size
)
25647 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
25648 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
25649 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
25653 /* Prefer out-of-line restore if it will exit. */
25654 if (info
->first_fp_reg_save
> 61)
25655 strategy
|= SAVE_INLINE_FPRS
;
25656 if (info
->first_gp_reg_save
> 29)
25658 if (info
->first_fp_reg_save
== 64)
25659 strategy
|= SAVE_INLINE_GPRS
;
25661 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
25663 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
25664 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
25667 else if (DEFAULT_ABI
== ABI_DARWIN
)
25669 if (info
->first_fp_reg_save
> 60)
25670 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
25671 if (info
->first_gp_reg_save
> 29)
25672 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
25673 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
25677 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
25678 if ((flag_shrink_wrap_separate
&& optimize_function_for_speed_p (cfun
))
25679 || info
->first_fp_reg_save
> 61)
25680 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
25681 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
25682 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
25685 /* Don't bother to try to save things out-of-line if r11 is occupied
25686 by the static chain. It would require too much fiddling and the
25687 static chain is rarely used anyway. FPRs are saved w.r.t the stack
25688 pointer on Darwin, and AIX uses r1 or r12. */
25689 if (using_static_chain_p
25690 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
25691 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
25693 | SAVE_INLINE_VRS
);
25695 /* Saving CR interferes with the exit routines used on the SPE, so
25698 && info
->spe_64bit_regs_used
25699 && info
->cr_save_p
)
25700 strategy
|= REST_INLINE_GPRS
;
25702 /* We can only use the out-of-line routines to restore fprs if we've
25703 saved all the registers from first_fp_reg_save in the prologue.
25704 Otherwise, we risk loading garbage. Of course, if we have saved
25705 out-of-line then we know we haven't skipped any fprs. */
25706 if ((strategy
& SAVE_INLINE_FPRS
)
25707 && !(strategy
& REST_INLINE_FPRS
))
25711 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
25712 if (fixed_regs
[i
] || !save_reg_p (i
))
25714 strategy
|= REST_INLINE_FPRS
;
25719 /* Similarly, for altivec regs. */
25720 if ((strategy
& SAVE_INLINE_VRS
)
25721 && !(strategy
& REST_INLINE_VRS
))
25725 for (i
= info
->first_altivec_reg_save
; i
< LAST_ALTIVEC_REGNO
+ 1; i
++)
25726 if (fixed_regs
[i
] || !save_reg_p (i
))
25728 strategy
|= REST_INLINE_VRS
;
25733 /* info->lr_save_p isn't yet set if the only reason lr needs to be
25734 saved is an out-of-line save or restore. Set up the value for
25735 the next test (excluding out-of-line gprs). */
25736 bool lr_save_p
= (info
->lr_save_p
25737 || !(strategy
& SAVE_INLINE_FPRS
)
25738 || !(strategy
& SAVE_INLINE_VRS
)
25739 || !(strategy
& REST_INLINE_FPRS
)
25740 || !(strategy
& REST_INLINE_VRS
));
25742 if (TARGET_MULTIPLE
25743 && !TARGET_POWERPC64
25744 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
25745 && info
->first_gp_reg_save
< 31
25746 && !(flag_shrink_wrap
25747 && flag_shrink_wrap_separate
25748 && optimize_function_for_speed_p (cfun
)))
25750 /* Prefer store multiple for saves over out-of-line routines,
25751 since the store-multiple instruction will always be smaller. */
25752 strategy
|= SAVE_INLINE_GPRS
| SAVE_MULTIPLE
;
25754 /* The situation is more complicated with load multiple. We'd
25755 prefer to use the out-of-line routines for restores, since the
25756 "exit" out-of-line routines can handle the restore of LR and the
25757 frame teardown. However if doesn't make sense to use the
25758 out-of-line routine if that is the only reason we'd need to save
25759 LR, and we can't use the "exit" out-of-line gpr restore if we
25760 have saved some fprs; In those cases it is advantageous to use
25761 load multiple when available. */
25762 if (info
->first_fp_reg_save
!= 64 || !lr_save_p
)
25763 strategy
|= REST_INLINE_GPRS
| REST_MULTIPLE
;
25766 /* Using the "exit" out-of-line routine does not improve code size
25767 if using it would require lr to be saved and if only saving one
25769 else if (!lr_save_p
&& info
->first_gp_reg_save
> 29)
25770 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
25772 /* We can only use load multiple or the out-of-line routines to
25773 restore gprs if we've saved all the registers from
25774 first_gp_reg_save. Otherwise, we risk loading garbage.
25775 Of course, if we have saved out-of-line or used stmw then we know
25776 we haven't skipped any gprs. */
25777 if ((strategy
& (SAVE_INLINE_GPRS
| SAVE_MULTIPLE
)) == SAVE_INLINE_GPRS
25778 && (strategy
& (REST_INLINE_GPRS
| REST_MULTIPLE
)) != REST_INLINE_GPRS
)
25782 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
25783 if (fixed_reg_p (i
) || !save_reg_p (i
))
25785 strategy
|= REST_INLINE_GPRS
;
25786 strategy
&= ~REST_MULTIPLE
;
25791 if (TARGET_ELF
&& TARGET_64BIT
)
25793 if (!(strategy
& SAVE_INLINE_FPRS
))
25794 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
25795 else if (!(strategy
& SAVE_INLINE_GPRS
)
25796 && info
->first_fp_reg_save
== 64)
25797 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
25799 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
25800 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
25802 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
25803 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
25808 /* Calculate the stack information for the current function. This is
25809 complicated by having two separate calling sequences, the AIX calling
25810 sequence and the V.4 calling sequence.
25812 AIX (and Darwin/Mac OS X) stack frames look like:
25814 SP----> +---------------------------------------+
25815 | back chain to caller | 0 0
25816 +---------------------------------------+
25817 | saved CR | 4 8 (8-11)
25818 +---------------------------------------+
25820 +---------------------------------------+
25821 | reserved for compilers | 12 24
25822 +---------------------------------------+
25823 | reserved for binders | 16 32
25824 +---------------------------------------+
25825 | saved TOC pointer | 20 40
25826 +---------------------------------------+
25827 | Parameter save area (P) | 24 48
25828 +---------------------------------------+
25829 | Alloca space (A) | 24+P etc.
25830 +---------------------------------------+
25831 | Local variable space (L) | 24+P+A
25832 +---------------------------------------+
25833 | Float/int conversion temporary (X) | 24+P+A+L
25834 +---------------------------------------+
25835 | Save area for AltiVec registers (W) | 24+P+A+L+X
25836 +---------------------------------------+
25837 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
25838 +---------------------------------------+
25839 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
25840 +---------------------------------------+
25841 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
25842 +---------------------------------------+
25843 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
25844 +---------------------------------------+
25845 old SP->| back chain to caller's caller |
25846 +---------------------------------------+
25848 The required alignment for AIX configurations is two words (i.e., 8
25851 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
25853 SP----> +---------------------------------------+
25854 | Back chain to caller | 0
25855 +---------------------------------------+
25856 | Save area for CR | 8
25857 +---------------------------------------+
25859 +---------------------------------------+
25860 | Saved TOC pointer | 24
25861 +---------------------------------------+
25862 | Parameter save area (P) | 32
25863 +---------------------------------------+
25864 | Alloca space (A) | 32+P
25865 +---------------------------------------+
25866 | Local variable space (L) | 32+P+A
25867 +---------------------------------------+
25868 | Save area for AltiVec registers (W) | 32+P+A+L
25869 +---------------------------------------+
25870 | AltiVec alignment padding (Y) | 32+P+A+L+W
25871 +---------------------------------------+
25872 | Save area for GP registers (G) | 32+P+A+L+W+Y
25873 +---------------------------------------+
25874 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
25875 +---------------------------------------+
25876 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
25877 +---------------------------------------+
25880 V.4 stack frames look like:
25882 SP----> +---------------------------------------+
25883 | back chain to caller | 0
25884 +---------------------------------------+
25885 | caller's saved LR | 4
25886 +---------------------------------------+
25887 | Parameter save area (P) | 8
25888 +---------------------------------------+
25889 | Alloca space (A) | 8+P
25890 +---------------------------------------+
25891 | Varargs save area (V) | 8+P+A
25892 +---------------------------------------+
25893 | Local variable space (L) | 8+P+A+V
25894 +---------------------------------------+
25895 | Float/int conversion temporary (X) | 8+P+A+V+L
25896 +---------------------------------------+
25897 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
25898 +---------------------------------------+
25899 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
25900 +---------------------------------------+
25901 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
25902 +---------------------------------------+
25903 | SPE: area for 64-bit GP registers |
25904 +---------------------------------------+
25905 | SPE alignment padding |
25906 +---------------------------------------+
25907 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
25908 +---------------------------------------+
25909 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
25910 +---------------------------------------+
25911 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
25912 +---------------------------------------+
25913 old SP->| back chain to caller's caller |
25914 +---------------------------------------+
25916 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
25917 given. (But note below and in sysv4.h that we require only 8 and
25918 may round up the size of our stack frame anyways. The historical
25919 reason is early versions of powerpc-linux which didn't properly
25920 align the stack at program startup. A happy side-effect is that
25921 -mno-eabi libraries can be used with -meabi programs.)
25923 The EABI configuration defaults to the V.4 layout. However,
25924 the stack alignment requirements may differ. If -mno-eabi is not
25925 given, the required stack alignment is 8 bytes; if -mno-eabi is
25926 given, the required alignment is 16 bytes. (But see V.4 comment
25929 #ifndef ABI_STACK_BOUNDARY
25930 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
25933 static rs6000_stack_t
*
25934 rs6000_stack_info (void)
25936 /* We should never be called for thunks, we are not set up for that. */
25937 gcc_assert (!cfun
->is_thunk
);
25939 rs6000_stack_t
*info
= &stack_info
;
25940 int reg_size
= TARGET_32BIT
? 4 : 8;
25945 HOST_WIDE_INT non_fixed_size
;
25946 bool using_static_chain_p
;
25948 if (reload_completed
&& info
->reload_completed
)
25951 memset (info
, 0, sizeof (*info
));
25952 info
->reload_completed
= reload_completed
;
25956 /* Cache value so we don't rescan instruction chain over and over. */
25957 if (cfun
->machine
->spe_insn_chain_scanned_p
== 0)
25958 cfun
->machine
->spe_insn_chain_scanned_p
25959 = spe_func_has_64bit_regs_p () + 1;
25960 info
->spe_64bit_regs_used
= cfun
->machine
->spe_insn_chain_scanned_p
- 1;
25963 /* Select which calling sequence. */
25964 info
->abi
= DEFAULT_ABI
;
25966 /* Calculate which registers need to be saved & save area size. */
25967 info
->first_gp_reg_save
= first_reg_to_save ();
25968 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
25969 even if it currently looks like we won't. Reload may need it to
25970 get at a constant; if so, it will have already created a constant
25971 pool entry for it. */
25972 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
25973 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
25974 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
25975 && crtl
->uses_const_pool
25976 && info
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
25977 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
25979 first_gp
= info
->first_gp_reg_save
;
25981 info
->gp_size
= reg_size
* (32 - first_gp
);
25983 /* For the SPE, we have an additional upper 32-bits on each GPR.
25984 Ideally we should save the entire 64-bits only when the upper
25985 half is used in SIMD instructions. Since we only record
25986 registers live (not the size they are used in), this proves
25987 difficult because we'd have to traverse the instruction chain at
25988 the right time, taking reload into account. This is a real pain,
25989 so we opt to save the GPRs in 64-bits always if but one register
25990 gets used in 64-bits. Otherwise, all the registers in the frame
25991 get saved in 32-bits.
25993 So... since when we save all GPRs (except the SP) in 64-bits, the
25994 traditional GP save area will be empty. */
25995 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
25998 info
->first_fp_reg_save
= first_fp_reg_to_save ();
25999 info
->fp_size
= 8 * (64 - info
->first_fp_reg_save
);
26001 info
->first_altivec_reg_save
= first_altivec_reg_to_save ();
26002 info
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
26003 - info
->first_altivec_reg_save
);
26005 /* Does this function call anything? */
26006 info
->calls_p
= (!crtl
->is_leaf
|| cfun
->machine
->ra_needs_full_frame
);
26008 /* Determine if we need to save the condition code registers. */
26009 if (save_reg_p (CR2_REGNO
)
26010 || save_reg_p (CR3_REGNO
)
26011 || save_reg_p (CR4_REGNO
))
26013 info
->cr_save_p
= 1;
26014 if (DEFAULT_ABI
== ABI_V4
)
26015 info
->cr_size
= reg_size
;
26018 /* If the current function calls __builtin_eh_return, then we need
26019 to allocate stack space for registers that will hold data for
26020 the exception handler. */
26021 if (crtl
->calls_eh_return
)
26024 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
26027 /* SPE saves EH registers in 64-bits. */
26028 ehrd_size
= i
* (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0
26029 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
26034 /* In the ELFv2 ABI, we also need to allocate space for separate
26035 CR field save areas if the function calls __builtin_eh_return. */
26036 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
26038 /* This hard-codes that we have three call-saved CR fields. */
26039 ehcr_size
= 3 * reg_size
;
26040 /* We do *not* use the regular CR save mechanism. */
26041 info
->cr_save_p
= 0;
26046 /* Determine various sizes. */
26047 info
->reg_size
= reg_size
;
26048 info
->fixed_size
= RS6000_SAVE_AREA
;
26049 info
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
26050 info
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
26051 TARGET_ALTIVEC
? 16 : 8);
26052 if (FRAME_GROWS_DOWNWARD
)
26054 += RS6000_ALIGN (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
,
26055 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
26056 - (info
->fixed_size
+ info
->vars_size
+ info
->parm_size
);
26058 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
26059 info
->spe_gp_size
= 8 * (32 - first_gp
);
26061 if (TARGET_ALTIVEC_ABI
)
26062 info
->vrsave_mask
= compute_vrsave_mask ();
26064 if (TARGET_ALTIVEC_VRSAVE
&& info
->vrsave_mask
)
26065 info
->vrsave_size
= 4;
26067 compute_save_world_info (info
);
26069 /* Calculate the offsets. */
26070 switch (DEFAULT_ABI
)
26074 gcc_unreachable ();
26079 info
->fp_save_offset
= -info
->fp_size
;
26080 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
26082 if (TARGET_ALTIVEC_ABI
)
26084 info
->vrsave_save_offset
= info
->gp_save_offset
- info
->vrsave_size
;
26086 /* Align stack so vector save area is on a quadword boundary.
26087 The padding goes above the vectors. */
26088 if (info
->altivec_size
!= 0)
26089 info
->altivec_padding_size
= info
->vrsave_save_offset
& 0xF;
26091 info
->altivec_save_offset
= info
->vrsave_save_offset
26092 - info
->altivec_padding_size
26093 - info
->altivec_size
;
26094 gcc_assert (info
->altivec_size
== 0
26095 || info
->altivec_save_offset
% 16 == 0);
26097 /* Adjust for AltiVec case. */
26098 info
->ehrd_offset
= info
->altivec_save_offset
- ehrd_size
;
26101 info
->ehrd_offset
= info
->gp_save_offset
- ehrd_size
;
26103 info
->ehcr_offset
= info
->ehrd_offset
- ehcr_size
;
26104 info
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
26105 info
->lr_save_offset
= 2*reg_size
;
26109 info
->fp_save_offset
= -info
->fp_size
;
26110 info
->gp_save_offset
= info
->fp_save_offset
- info
->gp_size
;
26111 info
->cr_save_offset
= info
->gp_save_offset
- info
->cr_size
;
26113 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
26115 /* Align stack so SPE GPR save area is aligned on a
26116 double-word boundary. */
26117 if (info
->spe_gp_size
!= 0 && info
->cr_save_offset
!= 0)
26118 info
->spe_padding_size
= 8 - (-info
->cr_save_offset
% 8);
26120 info
->spe_padding_size
= 0;
26122 info
->spe_gp_save_offset
= info
->cr_save_offset
26123 - info
->spe_padding_size
26124 - info
->spe_gp_size
;
26126 /* Adjust for SPE case. */
26127 info
->ehrd_offset
= info
->spe_gp_save_offset
;
26129 else if (TARGET_ALTIVEC_ABI
)
26131 info
->vrsave_save_offset
= info
->cr_save_offset
- info
->vrsave_size
;
26133 /* Align stack so vector save area is on a quadword boundary. */
26134 if (info
->altivec_size
!= 0)
26135 info
->altivec_padding_size
= 16 - (-info
->vrsave_save_offset
% 16);
26137 info
->altivec_save_offset
= info
->vrsave_save_offset
26138 - info
->altivec_padding_size
26139 - info
->altivec_size
;
26141 /* Adjust for AltiVec case. */
26142 info
->ehrd_offset
= info
->altivec_save_offset
;
26145 info
->ehrd_offset
= info
->cr_save_offset
;
26147 info
->ehrd_offset
-= ehrd_size
;
26148 info
->lr_save_offset
= reg_size
;
26151 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
26152 info
->save_size
= RS6000_ALIGN (info
->fp_size
26154 + info
->altivec_size
26155 + info
->altivec_padding_size
26156 + info
->spe_gp_size
26157 + info
->spe_padding_size
26161 + info
->vrsave_size
,
26164 non_fixed_size
= info
->vars_size
+ info
->parm_size
+ info
->save_size
;
26166 info
->total_size
= RS6000_ALIGN (non_fixed_size
+ info
->fixed_size
,
26167 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
26169 /* Determine if we need to save the link register. */
26171 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26173 && !TARGET_PROFILE_KERNEL
)
26174 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
26175 #ifdef TARGET_RELOCATABLE
26176 || (DEFAULT_ABI
== ABI_V4
26177 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
26178 && get_pool_size () != 0)
26180 || rs6000_ra_ever_killed ())
26181 info
->lr_save_p
= 1;
26183 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
26184 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
26185 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
26186 info
->savres_strategy
= rs6000_savres_strategy (info
, using_static_chain_p
);
26188 if (!(info
->savres_strategy
& SAVE_INLINE_GPRS
)
26189 || !(info
->savres_strategy
& SAVE_INLINE_FPRS
)
26190 || !(info
->savres_strategy
& SAVE_INLINE_VRS
)
26191 || !(info
->savres_strategy
& REST_INLINE_GPRS
)
26192 || !(info
->savres_strategy
& REST_INLINE_FPRS
)
26193 || !(info
->savres_strategy
& REST_INLINE_VRS
))
26194 info
->lr_save_p
= 1;
26196 if (info
->lr_save_p
)
26197 df_set_regs_ever_live (LR_REGNO
, true);
26199 /* Determine if we need to allocate any stack frame:
26201 For AIX we need to push the stack if a frame pointer is needed
26202 (because the stack might be dynamically adjusted), if we are
26203 debugging, if we make calls, or if the sum of fp_save, gp_save,
26204 and local variables are more than the space needed to save all
26205 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
26206 + 18*8 = 288 (GPR13 reserved).
26208 For V.4 we don't have the stack cushion that AIX uses, but assume
26209 that the debugger can handle stackless frames. */
26214 else if (DEFAULT_ABI
== ABI_V4
)
26215 info
->push_p
= non_fixed_size
!= 0;
26217 else if (frame_pointer_needed
)
26220 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
26224 info
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
26229 /* Return true if the current function uses any GPRs in 64-bit SIMD
26233 spe_func_has_64bit_regs_p (void)
26235 rtx_insn
*insns
, *insn
;
26237 /* Functions that save and restore all the call-saved registers will
26238 need to save/restore the registers in 64-bits. */
26239 if (crtl
->calls_eh_return
26240 || cfun
->calls_setjmp
26241 || crtl
->has_nonlocal_goto
)
26244 insns
= get_insns ();
26246 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
26252 /* FIXME: This should be implemented with attributes...
26254 (set_attr "spe64" "true")....then,
26255 if (get_spe64(insn)) return true;
26257 It's the only reliable way to do the stuff below. */
26259 i
= PATTERN (insn
);
26260 if (GET_CODE (i
) == SET
)
26262 machine_mode mode
= GET_MODE (SET_SRC (i
));
26264 if (SPE_VECTOR_MODE (mode
))
26266 if (TARGET_E500_DOUBLE
26267 && (mode
== DFmode
|| FLOAT128_2REG_P (mode
)))
26277 debug_stack_info (rs6000_stack_t
*info
)
26279 const char *abi_string
;
26282 info
= rs6000_stack_info ();
26284 fprintf (stderr
, "\nStack information for function %s:\n",
26285 ((current_function_decl
&& DECL_NAME (current_function_decl
))
26286 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
26291 default: abi_string
= "Unknown"; break;
26292 case ABI_NONE
: abi_string
= "NONE"; break;
26293 case ABI_AIX
: abi_string
= "AIX"; break;
26294 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
26295 case ABI_DARWIN
: abi_string
= "Darwin"; break;
26296 case ABI_V4
: abi_string
= "V.4"; break;
26299 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
26301 if (TARGET_ALTIVEC_ABI
)
26302 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
26304 if (TARGET_SPE_ABI
)
26305 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
26307 if (info
->first_gp_reg_save
!= 32)
26308 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
26310 if (info
->first_fp_reg_save
!= 64)
26311 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
26313 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
26314 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
26315 info
->first_altivec_reg_save
);
26317 if (info
->lr_save_p
)
26318 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
26320 if (info
->cr_save_p
)
26321 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
26323 if (info
->vrsave_mask
)
26324 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
26327 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
26330 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
26333 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
26336 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
26338 if (info
->altivec_size
)
26339 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
26340 info
->altivec_save_offset
);
26342 if (info
->spe_gp_size
)
26343 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
26344 info
->spe_gp_save_offset
);
26346 if (info
->vrsave_size
)
26347 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
26348 info
->vrsave_save_offset
);
26350 if (info
->lr_save_p
)
26351 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
26353 if (info
->cr_save_p
)
26354 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
26356 if (info
->varargs_save_offset
)
26357 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
26359 if (info
->total_size
)
26360 fprintf (stderr
, "\ttotal_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
26363 if (info
->vars_size
)
26364 fprintf (stderr
, "\tvars_size = " HOST_WIDE_INT_PRINT_DEC
"\n",
26367 if (info
->parm_size
)
26368 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
26370 if (info
->fixed_size
)
26371 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
26374 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
26376 if (info
->spe_gp_size
)
26377 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
26380 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
26382 if (info
->altivec_size
)
26383 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
26385 if (info
->vrsave_size
)
26386 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
26388 if (info
->altivec_padding_size
)
26389 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
26390 info
->altivec_padding_size
);
26392 if (info
->spe_padding_size
)
26393 fprintf (stderr
, "\tspe_padding_size = %5d\n",
26394 info
->spe_padding_size
);
26397 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
26399 if (info
->save_size
)
26400 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
26402 if (info
->reg_size
!= 4)
26403 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
26405 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
26407 fprintf (stderr
, "\n");
26411 rs6000_return_addr (int count
, rtx frame
)
26413 /* Currently we don't optimize very well between prolog and body
26414 code and for PIC code the code can be actually quite bad, so
26415 don't try to be too clever here. */
26417 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
26419 cfun
->machine
->ra_needs_full_frame
= 1;
26426 plus_constant (Pmode
,
26428 (gen_rtx_MEM (Pmode
,
26429 memory_address (Pmode
, frame
))),
26430 RETURN_ADDRESS_OFFSET
)));
26433 cfun
->machine
->ra_need_lr
= 1;
26434 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
26437 /* Say whether a function is a candidate for sibcall handling or not. */
26440 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
26445 fntype
= TREE_TYPE (decl
);
26447 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
26449 /* We can't do it if the called function has more vector parameters
26450 than the current function; there's nowhere to put the VRsave code. */
26451 if (TARGET_ALTIVEC_ABI
26452 && TARGET_ALTIVEC_VRSAVE
26453 && !(decl
&& decl
== current_function_decl
))
26455 function_args_iterator args_iter
;
26459 /* Functions with vector parameters are required to have a
26460 prototype, so the argument type info must be available
26462 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
26463 if (TREE_CODE (type
) == VECTOR_TYPE
26464 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
26467 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
26468 if (TREE_CODE (type
) == VECTOR_TYPE
26469 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
26476 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
26477 functions, because the callee may have a different TOC pointer to
26478 the caller and there's no way to ensure we restore the TOC when
26479 we return. With the secure-plt SYSV ABI we can't make non-local
26480 calls when -fpic/PIC because the plt call stubs use r30. */
26481 if (DEFAULT_ABI
== ABI_DARWIN
26482 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
26484 && !DECL_EXTERNAL (decl
)
26485 && !DECL_WEAK (decl
)
26486 && (*targetm
.binds_local_p
) (decl
))
26487 || (DEFAULT_ABI
== ABI_V4
26488 && (!TARGET_SECURE_PLT
26491 && (*targetm
.binds_local_p
) (decl
)))))
26493 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
26495 if (!lookup_attribute ("longcall", attr_list
)
26496 || lookup_attribute ("shortcall", attr_list
))
26504 rs6000_ra_ever_killed (void)
26510 if (cfun
->is_thunk
)
26513 if (cfun
->machine
->lr_save_state
)
26514 return cfun
->machine
->lr_save_state
- 1;
26516 /* regs_ever_live has LR marked as used if any sibcalls are present,
26517 but this should not force saving and restoring in the
26518 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
26519 clobbers LR, so that is inappropriate. */
26521 /* Also, the prologue can generate a store into LR that
26522 doesn't really count, like this:
26525 bcl to set PIC register
26529 When we're called from the epilogue, we need to avoid counting
26530 this as a store. */
26532 push_topmost_sequence ();
26533 top
= get_insns ();
26534 pop_topmost_sequence ();
26535 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
26537 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
26543 if (!SIBLING_CALL_P (insn
))
26546 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
26548 else if (set_of (reg
, insn
) != NULL_RTX
26549 && !prologue_epilogue_contains (insn
))
26556 /* Emit instructions needed to load the TOC register.
26557 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
26558 a constant pool; or for SVR4 -fpic. */
26561 rs6000_emit_load_toc_table (int fromprolog
)
26564 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
26566 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
26569 rtx lab
, tmp1
, tmp2
, got
;
26571 lab
= gen_label_rtx ();
26572 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
26573 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
26576 got
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
26580 got
= rs6000_got_sym ();
26581 tmp1
= tmp2
= dest
;
26584 tmp1
= gen_reg_rtx (Pmode
);
26585 tmp2
= gen_reg_rtx (Pmode
);
26587 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
26588 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
26589 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
26590 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
26592 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
26594 emit_insn (gen_load_toc_v4_pic_si ());
26595 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
26597 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
26600 rtx temp0
= (fromprolog
26601 ? gen_rtx_REG (Pmode
, 0)
26602 : gen_reg_rtx (Pmode
));
26608 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
26609 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
26611 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
26612 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
26614 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
26615 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
26616 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
26622 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
26624 lab
= gen_label_rtx ();
26625 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
26626 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
26627 if (TARGET_LINK_STACK
)
26628 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
26629 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
26631 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
26633 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
26635 /* This is for AIX code running in non-PIC ELF32. */
26636 rtx realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (toc_label_name
));
26639 emit_insn (gen_elf_high (dest
, realsym
));
26640 emit_insn (gen_elf_low (dest
, dest
, realsym
));
26644 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
26647 emit_insn (gen_load_toc_aix_si (dest
));
26649 emit_insn (gen_load_toc_aix_di (dest
));
26653 /* Emit instructions to restore the link register after determining where
26654 its value has been stored. */
26657 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
26659 rs6000_stack_t
*info
= rs6000_stack_info ();
26662 operands
[0] = source
;
26663 operands
[1] = scratch
;
26665 if (info
->lr_save_p
)
26667 rtx frame_rtx
= stack_pointer_rtx
;
26668 HOST_WIDE_INT sp_offset
= 0;
26671 if (frame_pointer_needed
26672 || cfun
->calls_alloca
26673 || info
->total_size
> 32767)
26675 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
26676 emit_move_insn (operands
[1], tmp
);
26677 frame_rtx
= operands
[1];
26679 else if (info
->push_p
)
26680 sp_offset
= info
->total_size
;
26682 tmp
= plus_constant (Pmode
, frame_rtx
,
26683 info
->lr_save_offset
+ sp_offset
);
26684 tmp
= gen_frame_mem (Pmode
, tmp
);
26685 emit_move_insn (tmp
, operands
[0]);
26688 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
26690 /* Freeze lr_save_p. We've just emitted rtl that depends on the
26691 state of lr_save_p so any change from here on would be a bug. In
26692 particular, stop rs6000_ra_ever_killed from considering the SET
26693 of lr we may have added just above. */
26694 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
26697 static GTY(()) alias_set_type set
= -1;
26700 get_TOC_alias_set (void)
26703 set
= new_alias_set ();
26707 /* This returns nonzero if the current function uses the TOC. This is
26708 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
26709 is generated by the ABI_V4 load_toc_* patterns. */
26716 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
26719 rtx pat
= PATTERN (insn
);
26722 if (GET_CODE (pat
) == PARALLEL
)
26723 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26725 rtx sub
= XVECEXP (pat
, 0, i
);
26726 if (GET_CODE (sub
) == USE
)
26728 sub
= XEXP (sub
, 0);
26729 if (GET_CODE (sub
) == UNSPEC
26730 && XINT (sub
, 1) == UNSPEC_TOC
)
26740 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
26742 rtx tocrel
, tocreg
, hi
;
26744 if (TARGET_DEBUG_ADDR
)
26746 if (GET_CODE (symbol
) == SYMBOL_REF
)
26747 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
26751 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
26752 GET_RTX_NAME (GET_CODE (symbol
)));
26753 debug_rtx (symbol
);
26757 if (!can_create_pseudo_p ())
26758 df_set_regs_ever_live (TOC_REGISTER
, true);
26760 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
26761 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
26762 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
26765 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
26766 if (largetoc_reg
!= NULL
)
26768 emit_move_insn (largetoc_reg
, hi
);
26771 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
26774 /* Issue assembly directives that create a reference to the given DWARF
26775 FRAME_TABLE_LABEL from the current function section. */
26777 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
26779 fprintf (asm_out_file
, "\t.ref %s\n",
26780 (* targetm
.strip_name_encoding
) (frame_table_label
));
26783 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
26784 and the change to the stack pointer. */
26787 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
26794 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26795 if (hard_frame_needed
)
26796 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
26797 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
26798 || (hard_frame_needed
26799 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
26802 p
= rtvec_alloc (i
);
26805 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
26806 RTVEC_ELT (p
, i
) = gen_rtx_SET (mem
, const0_rtx
);
26809 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
26812 /* Emit the correct code for allocating stack space, as insns.
26813 If COPY_REG, make sure a copy of the old frame is left there.
26814 The generated code may use hard register 0 as a temporary. */
26817 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
26820 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
26821 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
26822 rtx todec
= gen_int_mode (-size
, Pmode
);
26825 if (INTVAL (todec
) != -size
)
26827 warning (0, "stack frame too large");
26828 emit_insn (gen_trap ());
26832 if (crtl
->limit_stack
)
26834 if (REG_P (stack_limit_rtx
)
26835 && REGNO (stack_limit_rtx
) > 1
26836 && REGNO (stack_limit_rtx
) <= 31)
26838 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
26839 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
26842 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
26844 && DEFAULT_ABI
== ABI_V4
)
26846 rtx toload
= gen_rtx_CONST (VOIDmode
,
26847 gen_rtx_PLUS (Pmode
,
26851 emit_insn (gen_elf_high (tmp_reg
, toload
));
26852 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
26853 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
26857 warning (0, "stack limit expression is not supported");
26863 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
26865 emit_move_insn (copy_reg
, stack_reg
);
26870 /* Need a note here so that try_split doesn't get confused. */
26871 if (get_last_insn () == NULL_RTX
)
26872 emit_note (NOTE_INSN_DELETED
);
26873 insn
= emit_move_insn (tmp_reg
, todec
);
26874 try_split (PATTERN (insn
), insn
, 0);
26878 insn
= emit_insn (TARGET_32BIT
26879 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
26881 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
26882 todec
, stack_reg
));
26883 /* Since we didn't use gen_frame_mem to generate the MEM, grab
26884 it now and set the alias set/attributes. The above gen_*_update
26885 calls will generate a PARALLEL with the MEM set being the first
26887 par
= PATTERN (insn
);
26888 gcc_assert (GET_CODE (par
) == PARALLEL
);
26889 set
= XVECEXP (par
, 0, 0);
26890 gcc_assert (GET_CODE (set
) == SET
);
26891 mem
= SET_DEST (set
);
26892 gcc_assert (MEM_P (mem
));
26893 MEM_NOTRAP_P (mem
) = 1;
26894 set_mem_alias_set (mem
, get_frame_alias_set ());
26896 RTX_FRAME_RELATED_P (insn
) = 1;
26897 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
26898 gen_rtx_SET (stack_reg
, gen_rtx_PLUS (Pmode
, stack_reg
,
26899 GEN_INT (-size
))));
26903 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
26905 #if PROBE_INTERVAL > 32768
26906 #error Cannot use indexed addressing mode for stack probing
26909 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
26910 inclusive. These are offsets from the current stack pointer. */
26913 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
26915 /* See if we have a constant small number of probes to generate. If so,
26916 that's the easy case. */
26917 if (first
+ size
<= 32768)
26921 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
26922 it exceeds SIZE. If only one probe is needed, this will not
26923 generate any code. Then probe at FIRST + SIZE. */
26924 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
26925 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
26928 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
26932 /* Otherwise, do the same as above, but in a loop. Note that we must be
26933 extra careful with variables wrapping around because we might be at
26934 the very top (or the very bottom) of the address space and we have
26935 to be able to handle this case properly; in particular, we use an
26936 equality test for the loop condition. */
26939 HOST_WIDE_INT rounded_size
;
26940 rtx r12
= gen_rtx_REG (Pmode
, 12);
26941 rtx r0
= gen_rtx_REG (Pmode
, 0);
26943 /* Sanity check for the addressing mode we're going to use. */
26944 gcc_assert (first
<= 32768);
26946 /* Step 1: round SIZE to the previous multiple of the interval. */
26948 rounded_size
= ROUND_DOWN (size
, PROBE_INTERVAL
);
26951 /* Step 2: compute initial and final value of the loop counter. */
26953 /* TEST_ADDR = SP + FIRST. */
26954 emit_insn (gen_rtx_SET (r12
, plus_constant (Pmode
, stack_pointer_rtx
,
26957 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
26958 if (rounded_size
> 32768)
26960 emit_move_insn (r0
, GEN_INT (-rounded_size
));
26961 emit_insn (gen_rtx_SET (r0
, gen_rtx_PLUS (Pmode
, r12
, r0
)));
26964 emit_insn (gen_rtx_SET (r0
, plus_constant (Pmode
, r12
,
26968 /* Step 3: the loop
26972 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
26975 while (TEST_ADDR != LAST_ADDR)
26977 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
26978 until it is equal to ROUNDED_SIZE. */
26981 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
26983 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
26986 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
26987 that SIZE is equal to ROUNDED_SIZE. */
26989 if (size
!= rounded_size
)
26990 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
26994 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
26995 absolute addresses. */
26998 output_probe_stack_range (rtx reg1
, rtx reg2
)
27000 static int labelno
= 0;
27004 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
++);
27007 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
27009 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
27011 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
27012 output_asm_insn ("addi %0,%0,%1", xops
);
27014 /* Probe at TEST_ADDR. */
27015 xops
[1] = gen_rtx_REG (Pmode
, 0);
27016 output_asm_insn ("stw %1,0(%0)", xops
);
27018 /* Test if TEST_ADDR == LAST_ADDR. */
27021 output_asm_insn ("cmpd 0,%0,%1", xops
);
27023 output_asm_insn ("cmpw 0,%0,%1", xops
);
27026 fputs ("\tbne 0,", asm_out_file
);
27027 assemble_name_raw (asm_out_file
, loop_lab
);
27028 fputc ('\n', asm_out_file
);
27033 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
27034 with (plus:P (reg 1) VAL), and with REG2 replaced with REPL2 if REG2
27035 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
27036 deduce these equivalences by itself so it wasn't necessary to hold
27037 its hand so much. Don't be tempted to always supply d2_f_d_e with
27038 the actual cfa register, ie. r31 when we are using a hard frame
27039 pointer. That fails when saving regs off r1, and sched moves the
27040 r31 setup past the reg saves. */
27043 rs6000_frame_related (rtx_insn
*insn
, rtx reg
, HOST_WIDE_INT val
,
27044 rtx reg2
, rtx repl2
)
27048 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
27050 gcc_checking_assert (val
== 0);
27054 repl
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
27057 rtx pat
= PATTERN (insn
);
27058 if (!repl
&& !reg2
)
27060 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
27061 if (GET_CODE (pat
) == PARALLEL
)
27062 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
27063 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
27065 rtx set
= XVECEXP (pat
, 0, i
);
27067 /* If this PARALLEL has been emitted for out-of-line
27068 register save functions, or store multiple, then omit
27069 eh_frame info for any user-defined global regs. If
27070 eh_frame info is supplied, frame unwinding will
27071 restore a user reg. */
27072 if (!REG_P (SET_SRC (set
))
27073 || !fixed_reg_p (REGNO (SET_SRC (set
))))
27074 RTX_FRAME_RELATED_P (set
) = 1;
27076 RTX_FRAME_RELATED_P (insn
) = 1;
27080 /* We expect that 'pat' is either a SET or a PARALLEL containing
27081 SETs (and possibly other stuff). In a PARALLEL, all the SETs
27082 are important so they all have to be marked RTX_FRAME_RELATED_P.
27083 Call simplify_replace_rtx on the SETs rather than the whole insn
27084 so as to leave the other stuff alone (for example USE of r12). */
27086 if (GET_CODE (pat
) == SET
)
27089 pat
= simplify_replace_rtx (pat
, reg
, repl
);
27091 pat
= simplify_replace_rtx (pat
, reg2
, repl2
);
27093 else if (GET_CODE (pat
) == PARALLEL
)
27095 pat
= shallow_copy_rtx (pat
);
27096 XVEC (pat
, 0) = shallow_copy_rtvec (XVEC (pat
, 0));
27098 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
27099 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
27101 rtx set
= XVECEXP (pat
, 0, i
);
27104 set
= simplify_replace_rtx (set
, reg
, repl
);
27106 set
= simplify_replace_rtx (set
, reg2
, repl2
);
27107 XVECEXP (pat
, 0, i
) = set
;
27109 /* Omit eh_frame info for any user-defined global regs. */
27110 if (!REG_P (SET_SRC (set
))
27111 || !fixed_reg_p (REGNO (SET_SRC (set
))))
27112 RTX_FRAME_RELATED_P (set
) = 1;
27116 gcc_unreachable ();
27118 RTX_FRAME_RELATED_P (insn
) = 1;
27120 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, pat
);
27125 /* Returns an insn that has a vrsave set operation with the
27126 appropriate CLOBBERs. */
27129 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
27132 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
27133 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
27136 = gen_rtx_SET (vrsave
,
27137 gen_rtx_UNSPEC_VOLATILE (SImode
,
27138 gen_rtvec (2, reg
, vrsave
),
27139 UNSPECV_SET_VRSAVE
));
27143 /* We need to clobber the registers in the mask so the scheduler
27144 does not move sets to VRSAVE before sets of AltiVec registers.
27146 However, if the function receives nonlocal gotos, reload will set
27147 all call saved registers live. We will end up with:
27149 (set (reg 999) (mem))
27150 (parallel [ (set (reg vrsave) (unspec blah))
27151 (clobber (reg 999))])
27153 The clobber will cause the store into reg 999 to be dead, and
27154 flow will attempt to delete an epilogue insn. In this case, we
27155 need an unspec use/set of the register. */
27157 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
27158 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
27160 if (!epiloguep
|| call_used_regs
[i
])
27161 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
27162 gen_rtx_REG (V4SImode
, i
));
27165 rtx reg
= gen_rtx_REG (V4SImode
, i
);
27168 = gen_rtx_SET (reg
,
27169 gen_rtx_UNSPEC (V4SImode
,
27170 gen_rtvec (1, reg
), 27));
27174 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
27176 for (i
= 0; i
< nclobs
; ++i
)
27177 XVECEXP (insn
, 0, i
) = clobs
[i
];
27183 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
27187 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
27188 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
27189 return gen_rtx_SET (store
? mem
: reg
, store
? reg
: mem
);
27193 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
27195 return gen_frame_set (reg
, frame_reg
, offset
, false);
27199 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
27201 return gen_frame_set (reg
, frame_reg
, offset
, true);
27204 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
27205 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
27208 emit_frame_save (rtx frame_reg
, machine_mode mode
,
27209 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
27213 /* Some cases that need register indexed addressing. */
27214 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
27215 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
27216 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
27218 && SPE_VECTOR_MODE (mode
)
27219 && !SPE_CONST_OFFSET_OK (offset
))));
27221 reg
= gen_rtx_REG (mode
, regno
);
27222 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
27223 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
27224 NULL_RTX
, NULL_RTX
);
27227 /* Emit an offset memory reference suitable for a frame store, while
27228 converting to a valid addressing mode. */
27231 gen_frame_mem_offset (machine_mode mode
, rtx reg
, int offset
)
27233 rtx int_rtx
, offset_rtx
;
27235 int_rtx
= GEN_INT (offset
);
27237 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
27238 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
27240 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
27241 emit_move_insn (offset_rtx
, int_rtx
);
27244 offset_rtx
= int_rtx
;
27246 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
27249 #ifndef TARGET_FIX_AND_CONTINUE
27250 #define TARGET_FIX_AND_CONTINUE 0
27253 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
27254 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
27255 #define LAST_SAVRES_REGISTER 31
27256 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
27267 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
27269 /* Temporary holding space for an out-of-line register save/restore
27271 static char savres_routine_name
[30];
27273 /* Return the name for an out-of-line register save/restore routine.
27274 We are saving/restoring GPRs if GPR is true. */
27277 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
27279 const char *prefix
= "";
27280 const char *suffix
= "";
27282 /* Different targets are supposed to define
27283 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
27284 routine name could be defined with:
27286 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
27288 This is a nice idea in practice, but in reality, things are
27289 complicated in several ways:
27291 - ELF targets have save/restore routines for GPRs.
27293 - SPE targets use different prefixes for 32/64-bit registers, and
27294 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
27296 - PPC64 ELF targets have routines for save/restore of GPRs that
27297 differ in what they do with the link register, so having a set
27298 prefix doesn't work. (We only use one of the save routines at
27299 the moment, though.)
27301 - PPC32 elf targets have "exit" versions of the restore routines
27302 that restore the link register and can save some extra space.
27303 These require an extra suffix. (There are also "tail" versions
27304 of the restore routines and "GOT" versions of the save routines,
27305 but we don't generate those at present. Same problems apply,
27308 We deal with all this by synthesizing our own prefix/suffix and
27309 using that for the simple sprintf call shown above. */
27312 /* No floating point saves on the SPE. */
27313 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
27315 if ((sel
& SAVRES_SAVE
))
27316 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
27318 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
27320 if ((sel
& SAVRES_LR
))
27323 else if (DEFAULT_ABI
== ABI_V4
)
27328 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
27329 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
27330 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
27331 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
27332 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
27333 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
27337 if ((sel
& SAVRES_LR
))
27340 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27342 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
27343 /* No out-of-line save/restore routines for GPRs on AIX. */
27344 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
27348 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
27349 prefix
= ((sel
& SAVRES_SAVE
)
27350 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
27351 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
27352 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
27354 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
27355 if ((sel
& SAVRES_LR
))
27356 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
27360 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
27361 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
27364 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
27365 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
27370 if (DEFAULT_ABI
== ABI_DARWIN
)
27372 /* The Darwin approach is (slightly) different, in order to be
27373 compatible with code generated by the system toolchain. There is a
27374 single symbol for the start of save sequence, and the code here
27375 embeds an offset into that code on the basis of the first register
27377 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
27378 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
27379 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
27380 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
27381 (regno
- 13) * 4, prefix
, regno
);
27382 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
27383 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
27384 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
27385 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
27386 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
27387 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
27392 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
27394 return savres_routine_name
;
27397 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
27398 We are saving/restoring GPRs if GPR is true. */
27401 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
27403 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
27404 ? info
->first_gp_reg_save
27405 : (sel
& SAVRES_REG
) == SAVRES_FPR
27406 ? info
->first_fp_reg_save
- 32
27407 : (sel
& SAVRES_REG
) == SAVRES_VR
27408 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
27413 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
27414 versions of the gpr routines. */
27415 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
27416 && info
->spe_64bit_regs_used
)
27417 select
^= SAVRES_FPR
^ SAVRES_GPR
;
27419 /* Don't generate bogus routine names. */
27420 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
27421 && regno
<= LAST_SAVRES_REGISTER
27422 && select
>= 0 && select
<= 12);
27424 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
27430 name
= rs6000_savres_routine_name (info
, regno
, sel
);
27432 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
27433 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
27434 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
27440 /* Emit a sequence of insns, including a stack tie if needed, for
27441 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
27442 reset the stack pointer, but move the base of the frame into
27443 reg UPDT_REGNO for use by out-of-line register restore routines. */
27446 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
27447 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
27448 unsigned updt_regno
)
27452 /* This blockage is needed so that sched doesn't decide to move
27453 the sp change before the register restores. */
27454 if (DEFAULT_ABI
== ABI_V4
27456 && info
->spe_64bit_regs_used
!= 0
27457 && info
->first_gp_reg_save
!= 32))
27458 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
27460 /* If we are restoring registers out-of-line, we will be using the
27461 "exit" variants of the restore routines, which will reset the
27462 stack for us. But we do need to point updt_reg into the
27463 right place for those routines. */
27464 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
27466 if (frame_off
!= 0)
27467 return emit_insn (gen_add3_insn (updt_reg_rtx
,
27468 frame_reg_rtx
, GEN_INT (frame_off
)));
27469 else if (REGNO (frame_reg_rtx
) != updt_regno
)
27470 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
27475 /* Return the register number used as a pointer by out-of-line
27476 save/restore functions. */
27478 static inline unsigned
27479 ptr_regno_for_savres (int sel
)
27481 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27482 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
27483 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
27486 /* Construct a parallel rtx describing the effect of a call to an
27487 out-of-line register save/restore routine, and emit the insn
27488 or jump_insn as appropriate. */
27491 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
27492 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
27493 machine_mode reg_mode
, int sel
)
27496 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
27497 int reg_size
= GET_MODE_SIZE (reg_mode
);
27504 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
27505 ? info
->first_gp_reg_save
27506 : (sel
& SAVRES_REG
) == SAVRES_FPR
27507 ? info
->first_fp_reg_save
27508 : (sel
& SAVRES_REG
) == SAVRES_VR
27509 ? info
->first_altivec_reg_save
27511 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
27513 : (sel
& SAVRES_REG
) == SAVRES_FPR
27515 : (sel
& SAVRES_REG
) == SAVRES_VR
27516 ? LAST_ALTIVEC_REGNO
+ 1
27518 n_regs
= end_reg
- start_reg
;
27519 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
27520 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
27523 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
27524 RTVEC_ELT (p
, offset
++) = ret_rtx
;
27526 RTVEC_ELT (p
, offset
++)
27527 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
27529 sym
= rs6000_savres_routine_sym (info
, sel
);
27530 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
27532 use_reg
= ptr_regno_for_savres (sel
);
27533 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
27535 /* Vector regs are saved/restored using [reg+reg] addressing. */
27536 RTVEC_ELT (p
, offset
++)
27537 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
27538 RTVEC_ELT (p
, offset
++)
27539 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
27542 RTVEC_ELT (p
, offset
++)
27543 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
27545 for (i
= 0; i
< end_reg
- start_reg
; i
++)
27546 RTVEC_ELT (p
, i
+ offset
)
27547 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
27548 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
27549 (sel
& SAVRES_SAVE
) != 0);
27551 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
27552 RTVEC_ELT (p
, i
+ offset
)
27553 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
27555 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
27557 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
27559 insn
= emit_jump_insn (par
);
27560 JUMP_LABEL (insn
) = ret_rtx
;
27563 insn
= emit_insn (par
);
27567 /* Emit code to store CR fields that need to be saved into REG. */
27570 rs6000_emit_move_from_cr (rtx reg
)
27572 /* Only the ELFv2 ABI allows storing only selected fields. */
27573 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
27575 int i
, cr_reg
[8], count
= 0;
27577 /* Collect CR fields that must be saved. */
27578 for (i
= 0; i
< 8; i
++)
27579 if (save_reg_p (CR0_REGNO
+ i
))
27580 cr_reg
[count
++] = i
;
27582 /* If it's just a single one, use mfcrf. */
27585 rtvec p
= rtvec_alloc (1);
27586 rtvec r
= rtvec_alloc (2);
27587 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
27588 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
27590 = gen_rtx_SET (reg
,
27591 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
27593 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
27597 /* ??? It might be better to handle count == 2 / 3 cases here
27598 as well, using logical operations to combine the values. */
27601 emit_insn (gen_movesi_from_cr (reg
));
27604 /* Return whether the split-stack arg pointer (r12) is used. */
27607 split_stack_arg_pointer_used_p (void)
27609 /* If the pseudo holding the arg pointer is no longer a pseudo,
27610 then the arg pointer is used. */
27611 if (cfun
->machine
->split_stack_arg_pointer
!= NULL_RTX
27612 && (!REG_P (cfun
->machine
->split_stack_arg_pointer
)
27613 || (REGNO (cfun
->machine
->split_stack_arg_pointer
)
27614 < FIRST_PSEUDO_REGISTER
)))
27617 /* Unfortunately we also need to do some code scanning, since
27618 r12 may have been substituted for the pseudo. */
27620 basic_block bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
;
27621 FOR_BB_INSNS (bb
, insn
)
27622 if (NONDEBUG_INSN_P (insn
))
27624 /* A call destroys r12. */
27629 FOR_EACH_INSN_USE (use
, insn
)
27631 rtx x
= DF_REF_REG (use
);
27632 if (REG_P (x
) && REGNO (x
) == 12)
27636 FOR_EACH_INSN_DEF (def
, insn
)
27638 rtx x
= DF_REF_REG (def
);
27639 if (REG_P (x
) && REGNO (x
) == 12)
27643 return bitmap_bit_p (DF_LR_OUT (bb
), 12);
27646 /* Return whether we need to emit an ELFv2 global entry point prologue. */
27649 rs6000_global_entry_point_needed_p (void)
27651 /* Only needed for the ELFv2 ABI. */
27652 if (DEFAULT_ABI
!= ABI_ELFv2
)
27655 /* With -msingle-pic-base, we assume the whole program shares the same
27656 TOC, so no global entry point prologues are needed anywhere. */
27657 if (TARGET_SINGLE_PIC_BASE
)
27660 /* Ensure we have a global entry point for thunks. ??? We could
27661 avoid that if the target routine doesn't need a global entry point,
27662 but we do not know whether this is the case at this point. */
27663 if (cfun
->is_thunk
)
27666 /* For regular functions, rs6000_emit_prologue sets this flag if the
27667 routine ever uses the TOC pointer. */
27668 return cfun
->machine
->r2_setup_needed
;
27671 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
27673 rs6000_get_separate_components (void)
27675 rs6000_stack_t
*info
= rs6000_stack_info ();
27677 if (WORLD_SAVE_P (info
))
27680 if (TARGET_SPE_ABI
)
27683 sbitmap components
= sbitmap_alloc (32);
27684 bitmap_clear (components
);
27686 gcc_assert (!(info
->savres_strategy
& SAVE_MULTIPLE
)
27687 && !(info
->savres_strategy
& REST_MULTIPLE
));
27689 /* The GPRs we need saved to the frame. */
27690 if ((info
->savres_strategy
& SAVE_INLINE_GPRS
)
27691 && (info
->savres_strategy
& REST_INLINE_GPRS
))
27693 int reg_size
= TARGET_32BIT
? 4 : 8;
27694 int offset
= info
->gp_save_offset
;
27696 offset
+= info
->total_size
;
27698 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
27700 if (IN_RANGE (offset
, -0x8000, 0x7fff)
27701 && rs6000_reg_live_or_pic_offset_p (regno
))
27702 bitmap_set_bit (components
, regno
);
27704 offset
+= reg_size
;
27708 /* Don't mess with the hard frame pointer. */
27709 if (frame_pointer_needed
)
27710 bitmap_clear_bit (components
, HARD_FRAME_POINTER_REGNUM
);
27712 /* Don't mess with the fixed TOC register. */
27713 if ((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
27714 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
27715 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
27716 bitmap_clear_bit (components
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
27718 /* Optimize LR save and restore if we can. This is component 0. Any
27719 out-of-line register save/restore routines need LR. */
27720 if (info
->lr_save_p
27721 && !(flag_pic
&& (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
27722 && (info
->savres_strategy
& SAVE_INLINE_GPRS
)
27723 && (info
->savres_strategy
& REST_INLINE_GPRS
)
27724 && (info
->savres_strategy
& SAVE_INLINE_FPRS
)
27725 && (info
->savres_strategy
& REST_INLINE_FPRS
)
27726 && (info
->savres_strategy
& SAVE_INLINE_VRS
)
27727 && (info
->savres_strategy
& REST_INLINE_VRS
))
27729 int offset
= info
->lr_save_offset
;
27731 offset
+= info
->total_size
;
27732 if (IN_RANGE (offset
, -0x8000, 0x7fff))
27733 bitmap_set_bit (components
, 0);
27739 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
27741 rs6000_components_for_bb (basic_block bb
)
27743 rs6000_stack_t
*info
= rs6000_stack_info ();
27745 bitmap in
= DF_LIVE_IN (bb
);
27746 bitmap gen
= &DF_LIVE_BB_INFO (bb
)->gen
;
27747 bitmap kill
= &DF_LIVE_BB_INFO (bb
)->kill
;
27749 sbitmap components
= sbitmap_alloc (32);
27750 bitmap_clear (components
);
27752 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
27753 for (unsigned regno
= info
->first_gp_reg_save
; regno
< 32; regno
++)
27754 if (bitmap_bit_p (in
, regno
)
27755 || bitmap_bit_p (gen
, regno
)
27756 || bitmap_bit_p (kill
, regno
))
27757 bitmap_set_bit (components
, regno
);
27759 /* LR needs to be saved around a bb if it is killed in that bb. */
27760 if (bitmap_bit_p (gen
, LR_REGNO
)
27761 || bitmap_bit_p (kill
, LR_REGNO
))
27762 bitmap_set_bit (components
, 0);
27767 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
27769 rs6000_disqualify_components (sbitmap components
, edge e
,
27770 sbitmap edge_components
, bool /*is_prologue*/)
27772 /* Our LR pro/epilogue code moves LR via R0, so R0 had better not be
27773 live where we want to place that code. */
27774 if (bitmap_bit_p (edge_components
, 0)
27775 && bitmap_bit_p (DF_LIVE_IN (e
->dest
), 0))
27778 fprintf (dump_file
, "Disqualifying LR because GPR0 is live "
27779 "on entry to bb %d\n", e
->dest
->index
);
27780 bitmap_clear_bit (components
, 0);
27784 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
27786 rs6000_emit_prologue_components (sbitmap components
)
27788 rs6000_stack_t
*info
= rs6000_stack_info ();
27789 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
27790 ? HARD_FRAME_POINTER_REGNUM
27791 : STACK_POINTER_REGNUM
);
27792 int reg_size
= TARGET_32BIT
? 4 : 8;
27794 /* Prologue for LR. */
27795 if (bitmap_bit_p (components
, 0))
27797 rtx reg
= gen_rtx_REG (Pmode
, 0);
27798 rtx_insn
*insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
27799 RTX_FRAME_RELATED_P (insn
) = 1;
27800 add_reg_note (insn
, REG_CFA_REGISTER
, NULL
);
27802 int offset
= info
->lr_save_offset
;
27804 offset
+= info
->total_size
;
27806 insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
27807 RTX_FRAME_RELATED_P (insn
) = 1;
27808 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27809 rtx mem
= copy_rtx (SET_DEST (single_set (insn
)));
27810 add_reg_note (insn
, REG_CFA_OFFSET
, gen_rtx_SET (mem
, lr
));
27813 /* Prologue for the GPRs. */
27814 int offset
= info
->gp_save_offset
;
27816 offset
+= info
->total_size
;
27818 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
27820 if (bitmap_bit_p (components
, i
))
27822 rtx reg
= gen_rtx_REG (Pmode
, i
);
27823 rtx_insn
*insn
= emit_insn (gen_frame_store (reg
, ptr_reg
, offset
));
27824 RTX_FRAME_RELATED_P (insn
) = 1;
27825 rtx set
= copy_rtx (single_set (insn
));
27826 add_reg_note (insn
, REG_CFA_OFFSET
, set
);
27829 offset
+= reg_size
;
27833 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
27835 rs6000_emit_epilogue_components (sbitmap components
)
27837 rs6000_stack_t
*info
= rs6000_stack_info ();
27838 rtx ptr_reg
= gen_rtx_REG (Pmode
, frame_pointer_needed
27839 ? HARD_FRAME_POINTER_REGNUM
27840 : STACK_POINTER_REGNUM
);
27841 int reg_size
= TARGET_32BIT
? 4 : 8;
27843 /* Epilogue for the GPRs. */
27844 int offset
= info
->gp_save_offset
;
27846 offset
+= info
->total_size
;
27848 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
27850 if (bitmap_bit_p (components
, i
))
27852 rtx reg
= gen_rtx_REG (Pmode
, i
);
27853 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
27854 RTX_FRAME_RELATED_P (insn
) = 1;
27855 add_reg_note (insn
, REG_CFA_RESTORE
, reg
);
27858 offset
+= reg_size
;
27861 /* Epilogue for LR. */
27862 if (bitmap_bit_p (components
, 0))
27864 int offset
= info
->lr_save_offset
;
27866 offset
+= info
->total_size
;
27868 rtx reg
= gen_rtx_REG (Pmode
, 0);
27869 rtx_insn
*insn
= emit_insn (gen_frame_load (reg
, ptr_reg
, offset
));
27871 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
27872 insn
= emit_move_insn (lr
, reg
);
27873 RTX_FRAME_RELATED_P (insn
) = 1;
27874 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
27878 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
27880 rs6000_set_handled_components (sbitmap components
)
27882 rs6000_stack_t
*info
= rs6000_stack_info ();
27884 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
27885 if (bitmap_bit_p (components
, i
))
27886 cfun
->machine
->gpr_is_wrapped_separately
[i
] = true;
27888 if (bitmap_bit_p (components
, 0))
27889 cfun
->machine
->lr_is_wrapped_separately
= true;
27892 /* Emit function prologue as insns. */
27895 rs6000_emit_prologue (void)
27897 rs6000_stack_t
*info
= rs6000_stack_info ();
27898 machine_mode reg_mode
= Pmode
;
27899 int reg_size
= TARGET_32BIT
? 4 : 8;
27900 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
27901 rtx frame_reg_rtx
= sp_reg_rtx
;
27902 unsigned int cr_save_regno
;
27903 rtx cr_save_rtx
= NULL_RTX
;
27906 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
27907 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
27908 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
27909 int using_split_stack
= (flag_split_stack
27910 && (lookup_attribute ("no_split_stack",
27911 DECL_ATTRIBUTES (cfun
->decl
))
27914 /* Offset to top of frame for frame_reg and sp respectively. */
27915 HOST_WIDE_INT frame_off
= 0;
27916 HOST_WIDE_INT sp_off
= 0;
27917 /* sp_adjust is the stack adjusting instruction, tracked so that the
27918 insn setting up the split-stack arg pointer can be emitted just
27919 prior to it, when r12 is not used here for other purposes. */
27920 rtx_insn
*sp_adjust
= 0;
27923 /* Track and check usage of r0, r11, r12. */
27924 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
27925 #define START_USE(R) do \
27927 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27928 reg_inuse |= 1 << (R); \
27930 #define END_USE(R) do \
27932 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
27933 reg_inuse &= ~(1 << (R)); \
27935 #define NOT_INUSE(R) do \
27937 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
27940 #define START_USE(R) do {} while (0)
27941 #define END_USE(R) do {} while (0)
27942 #define NOT_INUSE(R) do {} while (0)
27945 if (DEFAULT_ABI
== ABI_ELFv2
27946 && !TARGET_SINGLE_PIC_BASE
)
27948 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
27950 /* With -mminimal-toc we may generate an extra use of r2 below. */
27951 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
27952 cfun
->machine
->r2_setup_needed
= true;
27956 if (flag_stack_usage_info
)
27957 current_function_static_stack_size
= info
->total_size
;
27959 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
27961 HOST_WIDE_INT size
= info
->total_size
;
27963 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
27965 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
27966 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
27967 size
- STACK_CHECK_PROTECT
);
27970 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
27973 if (TARGET_FIX_AND_CONTINUE
)
27975 /* gdb on darwin arranges to forward a function from the old
27976 address by modifying the first 5 instructions of the function
27977 to branch to the overriding function. This is necessary to
27978 permit function pointers that point to the old function to
27979 actually forward to the new function. */
27980 emit_insn (gen_nop ());
27981 emit_insn (gen_nop ());
27982 emit_insn (gen_nop ());
27983 emit_insn (gen_nop ());
27984 emit_insn (gen_nop ());
27987 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
27989 reg_mode
= V2SImode
;
27993 /* Handle world saves specially here. */
27994 if (WORLD_SAVE_P (info
))
28001 /* save_world expects lr in r0. */
28002 reg0
= gen_rtx_REG (Pmode
, 0);
28003 if (info
->lr_save_p
)
28005 insn
= emit_move_insn (reg0
,
28006 gen_rtx_REG (Pmode
, LR_REGNO
));
28007 RTX_FRAME_RELATED_P (insn
) = 1;
28010 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
28011 assumptions about the offsets of various bits of the stack
28013 gcc_assert (info
->gp_save_offset
== -220
28014 && info
->fp_save_offset
== -144
28015 && info
->lr_save_offset
== 8
28016 && info
->cr_save_offset
== 4
28019 && (!crtl
->calls_eh_return
28020 || info
->ehrd_offset
== -432)
28021 && info
->vrsave_save_offset
== -224
28022 && info
->altivec_save_offset
== -416);
28024 treg
= gen_rtx_REG (SImode
, 11);
28025 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
28027 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
28028 in R11. It also clobbers R12, so beware! */
28030 /* Preserve CR2 for save_world prologues */
28032 sz
+= 32 - info
->first_gp_reg_save
;
28033 sz
+= 64 - info
->first_fp_reg_save
;
28034 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
28035 p
= rtvec_alloc (sz
);
28037 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
28038 gen_rtx_REG (SImode
,
28040 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
28041 gen_rtx_SYMBOL_REF (Pmode
,
28043 /* We do floats first so that the instruction pattern matches
28045 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
28047 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
28049 info
->first_fp_reg_save
+ i
),
28051 info
->fp_save_offset
+ frame_off
+ 8 * i
);
28052 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
28054 = gen_frame_store (gen_rtx_REG (V4SImode
,
28055 info
->first_altivec_reg_save
+ i
),
28057 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
28058 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28060 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
28062 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
28064 /* CR register traditionally saved as CR2. */
28066 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
28067 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
28068 /* Explain about use of R0. */
28069 if (info
->lr_save_p
)
28071 = gen_frame_store (reg0
,
28072 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
28073 /* Explain what happens to the stack pointer. */
28075 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
28076 RTVEC_ELT (p
, j
++) = gen_rtx_SET (sp_reg_rtx
, newval
);
28079 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28080 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
28081 treg
, GEN_INT (-info
->total_size
));
28082 sp_off
= frame_off
= info
->total_size
;
28085 strategy
= info
->savres_strategy
;
28087 /* For V.4, update stack before we do any saving and set back pointer. */
28088 if (! WORLD_SAVE_P (info
)
28090 && (DEFAULT_ABI
== ABI_V4
28091 || crtl
->calls_eh_return
))
28093 bool need_r11
= (TARGET_SPE
28094 ? (!(strategy
& SAVE_INLINE_GPRS
)
28095 && info
->spe_64bit_regs_used
== 0)
28096 : (!(strategy
& SAVE_INLINE_FPRS
)
28097 || !(strategy
& SAVE_INLINE_GPRS
)
28098 || !(strategy
& SAVE_INLINE_VRS
)));
28099 int ptr_regno
= -1;
28100 rtx ptr_reg
= NULL_RTX
;
28103 if (info
->total_size
< 32767)
28104 frame_off
= info
->total_size
;
28107 else if (info
->cr_save_p
28109 || info
->first_fp_reg_save
< 64
28110 || info
->first_gp_reg_save
< 32
28111 || info
->altivec_size
!= 0
28112 || info
->vrsave_size
!= 0
28113 || crtl
->calls_eh_return
)
28117 /* The prologue won't be saving any regs so there is no need
28118 to set up a frame register to access any frame save area.
28119 We also won't be using frame_off anywhere below, but set
28120 the correct value anyway to protect against future
28121 changes to this function. */
28122 frame_off
= info
->total_size
;
28124 if (ptr_regno
!= -1)
28126 /* Set up the frame offset to that needed by the first
28127 out-of-line save function. */
28128 START_USE (ptr_regno
);
28129 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
28130 frame_reg_rtx
= ptr_reg
;
28131 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
28132 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
28133 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
28134 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
28135 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
28136 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
28137 frame_off
= -ptr_off
;
28139 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
28141 if (REGNO (frame_reg_rtx
) == 12)
28143 sp_off
= info
->total_size
;
28144 if (frame_reg_rtx
!= sp_reg_rtx
)
28145 rs6000_emit_stack_tie (frame_reg_rtx
, false);
28148 /* If we use the link register, get it into r0. */
28149 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
28150 && !cfun
->machine
->lr_is_wrapped_separately
)
28152 rtx addr
, reg
, mem
;
28154 reg
= gen_rtx_REG (Pmode
, 0);
28156 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
28157 RTX_FRAME_RELATED_P (insn
) = 1;
28159 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
28160 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
28162 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28163 GEN_INT (info
->lr_save_offset
+ frame_off
));
28164 mem
= gen_rtx_MEM (Pmode
, addr
);
28165 /* This should not be of rs6000_sr_alias_set, because of
28166 __builtin_return_address. */
28168 insn
= emit_move_insn (mem
, reg
);
28169 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
28170 NULL_RTX
, NULL_RTX
);
28175 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
28176 r12 will be needed by out-of-line gpr restore. */
28177 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28178 && !(strategy
& (SAVE_INLINE_GPRS
28179 | SAVE_NOINLINE_GPRS_SAVES_LR
))
28181 if (!WORLD_SAVE_P (info
)
28183 && REGNO (frame_reg_rtx
) != cr_save_regno
28184 && !(using_static_chain_p
&& cr_save_regno
== 11)
28185 && !(using_split_stack
&& cr_save_regno
== 12 && sp_adjust
))
28187 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
28188 START_USE (cr_save_regno
);
28189 rs6000_emit_move_from_cr (cr_save_rtx
);
28192 /* Do any required saving of fpr's. If only one or two to save, do
28193 it ourselves. Otherwise, call function. */
28194 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
28197 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
28198 if (save_reg_p (info
->first_fp_reg_save
+ i
))
28199 emit_frame_save (frame_reg_rtx
,
28200 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
28201 ? DFmode
: SFmode
),
28202 info
->first_fp_reg_save
+ i
,
28203 info
->fp_save_offset
+ frame_off
+ 8 * i
,
28204 sp_off
- frame_off
);
28206 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
28208 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
28209 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28210 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
28211 rtx ptr_reg
= frame_reg_rtx
;
28213 if (REGNO (frame_reg_rtx
) == ptr_regno
)
28214 gcc_checking_assert (frame_off
== 0);
28217 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
28218 NOT_INUSE (ptr_regno
);
28219 emit_insn (gen_add3_insn (ptr_reg
,
28220 frame_reg_rtx
, GEN_INT (frame_off
)));
28222 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
28223 info
->fp_save_offset
,
28224 info
->lr_save_offset
,
28226 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
28227 NULL_RTX
, NULL_RTX
);
28232 /* Save GPRs. This is done as a PARALLEL if we are using
28233 the store-multiple instructions. */
28234 if (!WORLD_SAVE_P (info
)
28236 && info
->spe_64bit_regs_used
!= 0
28237 && info
->first_gp_reg_save
!= 32)
28240 rtx spe_save_area_ptr
;
28241 HOST_WIDE_INT save_off
;
28242 int ool_adjust
= 0;
28244 /* Determine whether we can address all of the registers that need
28245 to be saved with an offset from frame_reg_rtx that fits in
28246 the small const field for SPE memory instructions. */
28247 int spe_regs_addressable
28248 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
28249 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
28250 && (strategy
& SAVE_INLINE_GPRS
));
28252 if (spe_regs_addressable
)
28254 spe_save_area_ptr
= frame_reg_rtx
;
28255 save_off
= frame_off
;
28259 /* Make r11 point to the start of the SPE save area. We need
28260 to be careful here if r11 is holding the static chain. If
28261 it is, then temporarily save it in r0. */
28262 HOST_WIDE_INT offset
;
28264 if (!(strategy
& SAVE_INLINE_GPRS
))
28265 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
28266 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
28267 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
28268 save_off
= frame_off
- offset
;
28270 if (using_static_chain_p
)
28272 rtx r0
= gen_rtx_REG (Pmode
, 0);
28275 gcc_assert (info
->first_gp_reg_save
> 11);
28277 emit_move_insn (r0
, spe_save_area_ptr
);
28279 else if (REGNO (frame_reg_rtx
) != 11)
28282 emit_insn (gen_addsi3 (spe_save_area_ptr
,
28283 frame_reg_rtx
, GEN_INT (offset
)));
28284 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
28285 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
28288 if ((strategy
& SAVE_INLINE_GPRS
))
28290 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28291 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
28292 emit_frame_save (spe_save_area_ptr
, reg_mode
,
28293 info
->first_gp_reg_save
+ i
,
28294 (info
->spe_gp_save_offset
+ save_off
28296 sp_off
- save_off
);
28300 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
28301 info
->spe_gp_save_offset
+ save_off
,
28303 SAVRES_SAVE
| SAVRES_GPR
);
28305 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
28306 NULL_RTX
, NULL_RTX
);
28309 /* Move the static chain pointer back. */
28310 if (!spe_regs_addressable
)
28312 if (using_static_chain_p
)
28314 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
28317 else if (REGNO (frame_reg_rtx
) != 11)
28321 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
28323 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
28324 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
28325 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
28326 rtx ptr_reg
= frame_reg_rtx
;
28327 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
28328 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
28331 if (ptr_regno
== 12)
28334 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
28336 /* Need to adjust r11 (r12) if we saved any FPRs. */
28337 if (end_save
+ frame_off
!= 0)
28339 rtx offset
= GEN_INT (end_save
+ frame_off
);
28342 frame_off
= -end_save
;
28344 NOT_INUSE (ptr_regno
);
28345 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28347 else if (!ptr_set_up
)
28349 NOT_INUSE (ptr_regno
);
28350 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28352 ptr_off
= -end_save
;
28353 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
28354 info
->gp_save_offset
+ ptr_off
,
28355 info
->lr_save_offset
+ ptr_off
,
28357 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
28358 NULL_RTX
, NULL_RTX
);
28362 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_MULTIPLE
))
28366 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
28367 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
28369 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
28371 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
28372 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28373 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
28374 NULL_RTX
, NULL_RTX
);
28376 else if (!WORLD_SAVE_P (info
))
28378 int offset
= info
->gp_save_offset
+ frame_off
;
28379 for (int i
= info
->first_gp_reg_save
; i
< 32; i
++)
28381 if (rs6000_reg_live_or_pic_offset_p (i
)
28382 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
28383 emit_frame_save (frame_reg_rtx
, reg_mode
, i
, offset
,
28384 sp_off
- frame_off
);
28386 offset
+= reg_size
;
28390 if (crtl
->calls_eh_return
)
28397 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
28398 if (regno
== INVALID_REGNUM
)
28402 p
= rtvec_alloc (i
);
28406 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
28407 if (regno
== INVALID_REGNUM
)
28411 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
28413 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
28414 RTVEC_ELT (p
, i
) = set
;
28415 RTX_FRAME_RELATED_P (set
) = 1;
28418 insn
= emit_insn (gen_blockage ());
28419 RTX_FRAME_RELATED_P (insn
) = 1;
28420 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
28423 /* In AIX ABI we need to make sure r2 is really saved. */
28424 if (TARGET_AIX
&& crtl
->calls_eh_return
)
28426 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
28427 rtx join_insn
, note
;
28428 rtx_insn
*save_insn
;
28429 long toc_restore_insn
;
28431 tmp_reg
= gen_rtx_REG (Pmode
, 11);
28432 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
28433 if (using_static_chain_p
)
28436 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
28440 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
28441 /* Peek at instruction to which this function returns. If it's
28442 restoring r2, then we know we've already saved r2. We can't
28443 unconditionally save r2 because the value we have will already
28444 be updated if we arrived at this function via a plt call or
28445 toc adjusting stub. */
28446 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
28447 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
28448 + RS6000_TOC_SAVE_SLOT
);
28449 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
28450 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
28451 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
28452 validate_condition_mode (EQ
, CCUNSmode
);
28453 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
28454 emit_insn (gen_rtx_SET (compare_result
,
28455 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
28456 toc_save_done
= gen_label_rtx ();
28457 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
28458 gen_rtx_EQ (VOIDmode
, compare_result
,
28460 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
28462 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
28463 JUMP_LABEL (jump
) = toc_save_done
;
28464 LABEL_NUSES (toc_save_done
) += 1;
28466 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
28467 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
28468 sp_off
- frame_off
);
28470 emit_label (toc_save_done
);
28472 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
28473 have a CFG that has different saves along different paths.
28474 Move the note to a dummy blockage insn, which describes that
28475 R2 is unconditionally saved after the label. */
28476 /* ??? An alternate representation might be a special insn pattern
28477 containing both the branch and the store. That might let the
28478 code that minimizes the number of DW_CFA_advance opcodes better
28479 freedom in placing the annotations. */
28480 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
28482 remove_note (save_insn
, note
);
28484 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
28485 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
28486 RTX_FRAME_RELATED_P (save_insn
) = 0;
28488 join_insn
= emit_insn (gen_blockage ());
28489 REG_NOTES (join_insn
) = note
;
28490 RTX_FRAME_RELATED_P (join_insn
) = 1;
28492 if (using_static_chain_p
)
28494 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
28501 /* Save CR if we use any that must be preserved. */
28502 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
28504 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28505 GEN_INT (info
->cr_save_offset
+ frame_off
));
28506 rtx mem
= gen_frame_mem (SImode
, addr
);
28508 /* If we didn't copy cr before, do so now using r0. */
28509 if (cr_save_rtx
== NULL_RTX
)
28512 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
28513 rs6000_emit_move_from_cr (cr_save_rtx
);
28516 /* Saving CR requires a two-instruction sequence: one instruction
28517 to move the CR to a general-purpose register, and a second
28518 instruction that stores the GPR to memory.
28520 We do not emit any DWARF CFI records for the first of these,
28521 because we cannot properly represent the fact that CR is saved in
28522 a register. One reason is that we cannot express that multiple
28523 CR fields are saved; another reason is that on 64-bit, the size
28524 of the CR register in DWARF (4 bytes) differs from the size of
28525 a general-purpose register.
28527 This means if any intervening instruction were to clobber one of
28528 the call-saved CR fields, we'd have incorrect CFI. To prevent
28529 this from happening, we mark the store to memory as a use of
28530 those CR fields, which prevents any such instruction from being
28531 scheduled in between the two instructions. */
28536 crsave_v
[n_crsave
++] = gen_rtx_SET (mem
, cr_save_rtx
);
28537 for (i
= 0; i
< 8; i
++)
28538 if (save_reg_p (CR0_REGNO
+ i
))
28539 crsave_v
[n_crsave
++]
28540 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
28542 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
28543 gen_rtvec_v (n_crsave
, crsave_v
)));
28544 END_USE (REGNO (cr_save_rtx
));
28546 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
28547 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
28548 so we need to construct a frame expression manually. */
28549 RTX_FRAME_RELATED_P (insn
) = 1;
28551 /* Update address to be stack-pointer relative, like
28552 rs6000_frame_related would do. */
28553 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
28554 GEN_INT (info
->cr_save_offset
+ sp_off
));
28555 mem
= gen_frame_mem (SImode
, addr
);
28557 if (DEFAULT_ABI
== ABI_ELFv2
)
28559 /* In the ELFv2 ABI we generate separate CFI records for each
28560 CR field that was actually saved. They all point to the
28561 same 32-bit stack slot. */
28565 for (i
= 0; i
< 8; i
++)
28566 if (save_reg_p (CR0_REGNO
+ i
))
28569 = gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
28571 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
28575 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
28576 gen_rtx_PARALLEL (VOIDmode
,
28577 gen_rtvec_v (n_crframe
, crframe
)));
28581 /* In other ABIs, by convention, we use a single CR regnum to
28582 represent the fact that all call-saved CR fields are saved.
28583 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
28584 rtx set
= gen_rtx_SET (mem
, gen_rtx_REG (SImode
, CR2_REGNO
));
28585 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
28589 /* In the ELFv2 ABI we need to save all call-saved CR fields into
28590 *separate* slots if the routine calls __builtin_eh_return, so
28591 that they can be independently restored by the unwinder. */
28592 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
28594 int i
, cr_off
= info
->ehcr_offset
;
28597 /* ??? We might get better performance by using multiple mfocrf
28599 crsave
= gen_rtx_REG (SImode
, 0);
28600 emit_insn (gen_movesi_from_cr (crsave
));
28602 for (i
= 0; i
< 8; i
++)
28603 if (!call_used_regs
[CR0_REGNO
+ i
])
28605 rtvec p
= rtvec_alloc (2);
28607 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
28609 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
28611 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
28613 RTX_FRAME_RELATED_P (insn
) = 1;
28614 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
28615 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
28616 sp_reg_rtx
, cr_off
+ sp_off
));
28618 cr_off
+= reg_size
;
28622 /* Update stack and set back pointer unless this is V.4,
28623 for which it was done previously. */
28624 if (!WORLD_SAVE_P (info
) && info
->push_p
28625 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
28627 rtx ptr_reg
= NULL
;
28630 /* If saving altivec regs we need to be able to address all save
28631 locations using a 16-bit offset. */
28632 if ((strategy
& SAVE_INLINE_VRS
) == 0
28633 || (info
->altivec_size
!= 0
28634 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
28635 + info
->total_size
- frame_off
) > 32767)
28636 || (info
->vrsave_size
!= 0
28637 && (info
->vrsave_save_offset
28638 + info
->total_size
- frame_off
) > 32767))
28640 int sel
= SAVRES_SAVE
| SAVRES_VR
;
28641 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
28643 if (using_static_chain_p
28644 && ptr_regno
== STATIC_CHAIN_REGNUM
)
28646 if (REGNO (frame_reg_rtx
) != ptr_regno
)
28647 START_USE (ptr_regno
);
28648 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
28649 frame_reg_rtx
= ptr_reg
;
28650 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
28651 frame_off
= -ptr_off
;
28653 else if (REGNO (frame_reg_rtx
) == 1)
28654 frame_off
= info
->total_size
;
28655 sp_adjust
= rs6000_emit_allocate_stack (info
->total_size
,
28657 if (REGNO (frame_reg_rtx
) == 12)
28659 sp_off
= info
->total_size
;
28660 if (frame_reg_rtx
!= sp_reg_rtx
)
28661 rs6000_emit_stack_tie (frame_reg_rtx
, false);
28664 /* Set frame pointer, if needed. */
28665 if (frame_pointer_needed
)
28667 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
28669 RTX_FRAME_RELATED_P (insn
) = 1;
28672 /* Save AltiVec registers if needed. Save here because the red zone does
28673 not always include AltiVec registers. */
28674 if (!WORLD_SAVE_P (info
)
28675 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
28677 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
28679 /* Oddly, the vector save/restore functions point r0 at the end
28680 of the save area, then use r11 or r12 to load offsets for
28681 [reg+reg] addressing. */
28682 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
28683 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
28684 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
28686 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
28688 if (scratch_regno
== 12)
28690 if (end_save
+ frame_off
!= 0)
28692 rtx offset
= GEN_INT (end_save
+ frame_off
);
28694 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
28697 emit_move_insn (ptr_reg
, frame_reg_rtx
);
28699 ptr_off
= -end_save
;
28700 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
28701 info
->altivec_save_offset
+ ptr_off
,
28702 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
28703 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
28704 NULL_RTX
, NULL_RTX
);
28705 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
28707 /* The oddity mentioned above clobbered our frame reg. */
28708 emit_move_insn (frame_reg_rtx
, ptr_reg
);
28709 frame_off
= ptr_off
;
28712 else if (!WORLD_SAVE_P (info
)
28713 && info
->altivec_size
!= 0)
28717 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
28718 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
28720 rtx areg
, savereg
, mem
;
28721 HOST_WIDE_INT offset
;
28723 offset
= (info
->altivec_save_offset
+ frame_off
28724 + 16 * (i
- info
->first_altivec_reg_save
));
28726 savereg
= gen_rtx_REG (V4SImode
, i
);
28728 if (TARGET_P9_DFORM_VECTOR
&& quad_address_offset_p (offset
))
28730 mem
= gen_frame_mem (V4SImode
,
28731 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
28732 GEN_INT (offset
)));
28733 insn
= emit_insn (gen_rtx_SET (mem
, savereg
));
28739 areg
= gen_rtx_REG (Pmode
, 0);
28740 emit_move_insn (areg
, GEN_INT (offset
));
28742 /* AltiVec addressing mode is [reg+reg]. */
28743 mem
= gen_frame_mem (V4SImode
,
28744 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
28746 /* Rather than emitting a generic move, force use of the stvx
28747 instruction, which we always want on ISA 2.07 (power8) systems.
28748 In particular we don't want xxpermdi/stxvd2x for little
28750 insn
= emit_insn (gen_altivec_stvx_v4si_internal (mem
, savereg
));
28753 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
28754 areg
, GEN_INT (offset
));
28758 /* VRSAVE is a bit vector representing which AltiVec registers
28759 are used. The OS uses this to determine which vector
28760 registers to save on a context switch. We need to save
28761 VRSAVE on the stack frame, add whatever AltiVec registers we
28762 used in this function, and do the corresponding magic in the
28765 if (!WORLD_SAVE_P (info
)
28766 && info
->vrsave_size
!= 0)
28772 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
28773 be using r12 as frame_reg_rtx and r11 as the static chain
28774 pointer for nested functions. */
28776 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28777 && !using_static_chain_p
)
28779 else if (using_split_stack
|| REGNO (frame_reg_rtx
) == 12)
28782 if (using_static_chain_p
)
28786 NOT_INUSE (save_regno
);
28787 reg
= gen_rtx_REG (SImode
, save_regno
);
28788 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
28790 emit_insn (gen_get_vrsave_internal (reg
));
28792 emit_insn (gen_rtx_SET (reg
, vrsave
));
28795 offset
= info
->vrsave_save_offset
+ frame_off
;
28796 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
28798 /* Include the registers in the mask. */
28799 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
28801 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
28804 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
28805 if (!TARGET_SINGLE_PIC_BASE
28806 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
28807 || (DEFAULT_ABI
== ABI_V4
28808 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
28809 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
28811 /* If emit_load_toc_table will use the link register, we need to save
28812 it. We use R12 for this purpose because emit_load_toc_table
28813 can use register 0. This allows us to use a plain 'blr' to return
28814 from the procedure more often. */
28815 int save_LR_around_toc_setup
= (TARGET_ELF
28816 && DEFAULT_ABI
== ABI_V4
28818 && ! info
->lr_save_p
28819 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
28820 if (save_LR_around_toc_setup
)
28822 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
28823 rtx tmp
= gen_rtx_REG (Pmode
, 12);
28826 insn
= emit_move_insn (tmp
, lr
);
28827 RTX_FRAME_RELATED_P (insn
) = 1;
28829 rs6000_emit_load_toc_table (TRUE
);
28831 insn
= emit_move_insn (lr
, tmp
);
28832 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
28833 RTX_FRAME_RELATED_P (insn
) = 1;
28836 rs6000_emit_load_toc_table (TRUE
);
28840 if (!TARGET_SINGLE_PIC_BASE
28841 && DEFAULT_ABI
== ABI_DARWIN
28842 && flag_pic
&& crtl
->uses_pic_offset_table
)
28844 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
28845 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
28847 /* Save and restore LR locally around this call (in R0). */
28848 if (!info
->lr_save_p
)
28849 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
28851 emit_insn (gen_load_macho_picbase (src
));
28853 emit_move_insn (gen_rtx_REG (Pmode
,
28854 RS6000_PIC_OFFSET_TABLE_REGNUM
),
28857 if (!info
->lr_save_p
)
28858 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
28862 /* If we need to, save the TOC register after doing the stack setup.
28863 Do not emit eh frame info for this save. The unwinder wants info,
28864 conceptually attached to instructions in this function, about
28865 register values in the caller of this function. This R2 may have
28866 already been changed from the value in the caller.
28867 We don't attempt to write accurate DWARF EH frame info for R2
28868 because code emitted by gcc for a (non-pointer) function call
28869 doesn't save and restore R2. Instead, R2 is managed out-of-line
28870 by a linker generated plt call stub when the function resides in
28871 a shared library. This behavior is costly to describe in DWARF,
28872 both in terms of the size of DWARF info and the time taken in the
28873 unwinder to interpret it. R2 changes, apart from the
28874 calls_eh_return case earlier in this function, are handled by
28875 linux-unwind.h frob_update_context. */
28876 if (rs6000_save_toc_in_prologue_p ())
28878 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
28879 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
28882 if (using_split_stack
&& split_stack_arg_pointer_used_p ())
28884 /* Set up the arg pointer (r12) for -fsplit-stack code. If
28885 __morestack was called, it left the arg pointer to the old
28886 stack in r29. Otherwise, the arg pointer is the top of the
28888 cfun
->machine
->split_stack_argp_used
= true;
28891 rtx r12
= gen_rtx_REG (Pmode
, 12);
28892 rtx set_r12
= gen_rtx_SET (r12
, sp_reg_rtx
);
28893 emit_insn_before (set_r12
, sp_adjust
);
28895 else if (frame_off
!= 0 || REGNO (frame_reg_rtx
) != 12)
28897 rtx r12
= gen_rtx_REG (Pmode
, 12);
28898 if (frame_off
== 0)
28899 emit_move_insn (r12
, frame_reg_rtx
);
28901 emit_insn (gen_add3_insn (r12
, frame_reg_rtx
, GEN_INT (frame_off
)));
28905 rtx r12
= gen_rtx_REG (Pmode
, 12);
28906 rtx r29
= gen_rtx_REG (Pmode
, 29);
28907 rtx cr7
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
28908 rtx not_more
= gen_label_rtx ();
28911 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
28912 gen_rtx_GEU (VOIDmode
, cr7
, const0_rtx
),
28913 gen_rtx_LABEL_REF (VOIDmode
, not_more
),
28915 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
28916 JUMP_LABEL (jump
) = not_more
;
28917 LABEL_NUSES (not_more
) += 1;
28918 emit_move_insn (r12
, r29
);
28919 emit_label (not_more
);
28924 /* Output .extern statements for the save/restore routines we use. */
28927 rs6000_output_savres_externs (FILE *file
)
28929 rs6000_stack_t
*info
= rs6000_stack_info ();
28931 if (TARGET_DEBUG_STACK
)
28932 debug_stack_info (info
);
28934 /* Write .extern for any function we will call to save and restore
28936 if (info
->first_fp_reg_save
< 64
28941 int regno
= info
->first_fp_reg_save
- 32;
28943 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
28945 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
28946 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28947 name
= rs6000_savres_routine_name (info
, regno
, sel
);
28948 fprintf (file
, "\t.extern %s\n", name
);
28950 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
28952 bool lr
= (info
->savres_strategy
28953 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
28954 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
28955 name
= rs6000_savres_routine_name (info
, regno
, sel
);
28956 fprintf (file
, "\t.extern %s\n", name
);
28961 /* Write function prologue. */
28964 rs6000_output_function_prologue (FILE *file
,
28965 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
28967 if (!cfun
->is_thunk
)
28968 rs6000_output_savres_externs (file
);
28970 /* ELFv2 ABI r2 setup code and local entry point. This must follow
28971 immediately after the global entry point label. */
28972 if (rs6000_global_entry_point_needed_p ())
28974 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
28976 (*targetm
.asm_out
.internal_label
) (file
, "LCF", rs6000_pic_labelno
);
28978 if (TARGET_CMODEL
!= CMODEL_LARGE
)
28980 /* In the small and medium code models, we assume the TOC is less
28981 2 GB away from the text section, so it can be computed via the
28982 following two-instruction sequence. */
28985 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
28986 fprintf (file
, "0:\taddis 2,12,.TOC.-");
28987 assemble_name (file
, buf
);
28988 fprintf (file
, "@ha\n");
28989 fprintf (file
, "\taddi 2,2,.TOC.-");
28990 assemble_name (file
, buf
);
28991 fprintf (file
, "@l\n");
28995 /* In the large code model, we allow arbitrary offsets between the
28996 TOC and the text section, so we have to load the offset from
28997 memory. The data field is emitted directly before the global
28998 entry point in rs6000_elf_declare_function_name. */
29001 #ifdef HAVE_AS_ENTRY_MARKERS
29002 /* If supported by the linker, emit a marker relocation. If the
29003 total code size of the final executable or shared library
29004 happens to fit into 2 GB after all, the linker will replace
29005 this code sequence with the sequence for the small or medium
29007 fprintf (file
, "\t.reloc .,R_PPC64_ENTRY\n");
29009 fprintf (file
, "\tld 2,");
29010 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
29011 assemble_name (file
, buf
);
29012 fprintf (file
, "-");
29013 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
29014 assemble_name (file
, buf
);
29015 fprintf (file
, "(12)\n");
29016 fprintf (file
, "\tadd 2,2,12\n");
29019 fputs ("\t.localentry\t", file
);
29020 assemble_name (file
, name
);
29021 fputs (",.-", file
);
29022 assemble_name (file
, name
);
29023 fputs ("\n", file
);
29026 /* Output -mprofile-kernel code. This needs to be done here instead of
29027 in output_function_profile since it must go after the ELFv2 ABI
29028 local entry point. */
29029 if (TARGET_PROFILE_KERNEL
&& crtl
->profile
)
29031 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
29032 gcc_assert (!TARGET_32BIT
);
29034 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
29036 /* In the ELFv2 ABI we have no compiler stack word. It must be
29037 the resposibility of _mcount to preserve the static chain
29038 register if required. */
29039 if (DEFAULT_ABI
!= ABI_ELFv2
29040 && cfun
->static_chain_decl
!= NULL
)
29042 asm_fprintf (file
, "\tstd %s,24(%s)\n",
29043 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
29044 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
29045 asm_fprintf (file
, "\tld %s,24(%s)\n",
29046 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
29049 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
29052 rs6000_pic_labelno
++;
29055 /* -mprofile-kernel code calls mcount before the function prolog,
29056 so a profiled leaf function should stay a leaf function. */
29058 rs6000_keep_leaf_when_profiled ()
29060 return TARGET_PROFILE_KERNEL
;
29063 /* Non-zero if vmx regs are restored before the frame pop, zero if
29064 we restore after the pop when possible. */
29065 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
29067 /* Restoring cr is a two step process: loading a reg from the frame
29068 save, then moving the reg to cr. For ABI_V4 we must let the
29069 unwinder know that the stack location is no longer valid at or
29070 before the stack deallocation, but we can't emit a cfa_restore for
29071 cr at the stack deallocation like we do for other registers.
29072 The trouble is that it is possible for the move to cr to be
29073 scheduled after the stack deallocation. So say exactly where cr
29074 is located on each of the two insns. */
29077 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
29079 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
29080 rtx reg
= gen_rtx_REG (SImode
, regno
);
29081 rtx_insn
*insn
= emit_move_insn (reg
, mem
);
29083 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
29085 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
29086 rtx set
= gen_rtx_SET (reg
, cr
);
29088 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
29089 RTX_FRAME_RELATED_P (insn
) = 1;
29094 /* Reload CR from REG. */
29097 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
29102 if (using_mfcr_multiple
)
29104 for (i
= 0; i
< 8; i
++)
29105 if (save_reg_p (CR0_REGNO
+ i
))
29107 gcc_assert (count
);
29110 if (using_mfcr_multiple
&& count
> 1)
29116 p
= rtvec_alloc (count
);
29119 for (i
= 0; i
< 8; i
++)
29120 if (save_reg_p (CR0_REGNO
+ i
))
29122 rtvec r
= rtvec_alloc (2);
29123 RTVEC_ELT (r
, 0) = reg
;
29124 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
29125 RTVEC_ELT (p
, ndx
) =
29126 gen_rtx_SET (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
29127 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
29130 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
29131 gcc_assert (ndx
== count
);
29133 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
29134 CR field separately. */
29135 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
29137 for (i
= 0; i
< 8; i
++)
29138 if (save_reg_p (CR0_REGNO
+ i
))
29139 add_reg_note (insn
, REG_CFA_RESTORE
,
29140 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
29142 RTX_FRAME_RELATED_P (insn
) = 1;
29146 for (i
= 0; i
< 8; i
++)
29147 if (save_reg_p (CR0_REGNO
+ i
))
29149 rtx insn
= emit_insn (gen_movsi_to_cr_one
29150 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
29152 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
29153 CR field separately, attached to the insn that in fact
29154 restores this particular CR field. */
29155 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
29157 add_reg_note (insn
, REG_CFA_RESTORE
,
29158 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
29160 RTX_FRAME_RELATED_P (insn
) = 1;
29164 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
29165 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
29166 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
29168 rtx_insn
*insn
= get_last_insn ();
29169 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
29171 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
29172 RTX_FRAME_RELATED_P (insn
) = 1;
29176 /* Like cr, the move to lr instruction can be scheduled after the
29177 stack deallocation, but unlike cr, its stack frame save is still
29178 valid. So we only need to emit the cfa_restore on the correct
29182 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
29184 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
29185 rtx reg
= gen_rtx_REG (Pmode
, regno
);
29187 emit_move_insn (reg
, mem
);
29191 restore_saved_lr (int regno
, bool exit_func
)
29193 rtx reg
= gen_rtx_REG (Pmode
, regno
);
29194 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
29195 rtx_insn
*insn
= emit_move_insn (lr
, reg
);
29197 if (!exit_func
&& flag_shrink_wrap
)
29199 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
29200 RTX_FRAME_RELATED_P (insn
) = 1;
29205 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
29207 if (DEFAULT_ABI
== ABI_ELFv2
)
29210 for (i
= 0; i
< 8; i
++)
29211 if (save_reg_p (CR0_REGNO
+ i
))
29213 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
29214 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
29218 else if (info
->cr_save_p
)
29219 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
29220 gen_rtx_REG (SImode
, CR2_REGNO
),
29223 if (info
->lr_save_p
)
29224 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
29225 gen_rtx_REG (Pmode
, LR_REGNO
),
29227 return cfa_restores
;
29230 /* Return true if OFFSET from stack pointer can be clobbered by signals.
29231 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
29232 below stack pointer not cloberred by signals. */
29235 offset_below_red_zone_p (HOST_WIDE_INT offset
)
29237 return offset
< (DEFAULT_ABI
== ABI_V4
29239 : TARGET_32BIT
? -220 : -288);
29242 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
29245 emit_cfa_restores (rtx cfa_restores
)
29247 rtx_insn
*insn
= get_last_insn ();
29248 rtx
*loc
= ®_NOTES (insn
);
29251 loc
= &XEXP (*loc
, 1);
29252 *loc
= cfa_restores
;
29253 RTX_FRAME_RELATED_P (insn
) = 1;
29256 /* Emit function epilogue as insns. */
29259 rs6000_emit_epilogue (int sibcall
)
29261 rs6000_stack_t
*info
;
29262 int restoring_GPRs_inline
;
29263 int restoring_FPRs_inline
;
29264 int using_load_multiple
;
29265 int using_mtcr_multiple
;
29266 int use_backchain_to_restore_sp
;
29269 HOST_WIDE_INT frame_off
= 0;
29270 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
29271 rtx frame_reg_rtx
= sp_reg_rtx
;
29272 rtx cfa_restores
= NULL_RTX
;
29274 rtx cr_save_reg
= NULL_RTX
;
29275 machine_mode reg_mode
= Pmode
;
29276 int reg_size
= TARGET_32BIT
? 4 : 8;
29279 unsigned ptr_regno
;
29281 info
= rs6000_stack_info ();
29283 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
29285 reg_mode
= V2SImode
;
29289 strategy
= info
->savres_strategy
;
29290 using_load_multiple
= strategy
& REST_MULTIPLE
;
29291 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
29292 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
29293 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
29294 || rs6000_cpu
== PROCESSOR_PPC603
29295 || rs6000_cpu
== PROCESSOR_PPC750
29297 /* Restore via the backchain when we have a large frame, since this
29298 is more efficient than an addis, addi pair. The second condition
29299 here will not trigger at the moment; We don't actually need a
29300 frame pointer for alloca, but the generic parts of the compiler
29301 give us one anyway. */
29302 use_backchain_to_restore_sp
= (info
->total_size
+ (info
->lr_save_p
29303 ? info
->lr_save_offset
29305 || (cfun
->calls_alloca
29306 && !frame_pointer_needed
));
29307 restore_lr
= (info
->lr_save_p
29308 && (restoring_FPRs_inline
29309 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
29310 && (restoring_GPRs_inline
29311 || info
->first_fp_reg_save
< 64)
29312 && !cfun
->machine
->lr_is_wrapped_separately
);
29315 if (WORLD_SAVE_P (info
))
29319 const char *alloc_rname
;
29322 /* eh_rest_world_r10 will return to the location saved in the LR
29323 stack slot (which is not likely to be our caller.)
29324 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
29325 rest_world is similar, except any R10 parameter is ignored.
29326 The exception-handling stuff that was here in 2.95 is no
29327 longer necessary. */
29330 + 32 - info
->first_gp_reg_save
29331 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
29332 + 63 + 1 - info
->first_fp_reg_save
);
29334 strcpy (rname
, ((crtl
->calls_eh_return
) ?
29335 "*eh_rest_world_r10" : "*rest_world"));
29336 alloc_rname
= ggc_strdup (rname
);
29339 RTVEC_ELT (p
, j
++) = ret_rtx
;
29341 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
29342 /* The instruction pattern requires a clobber here;
29343 it is shared with the restVEC helper. */
29345 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
29348 /* CR register traditionally saved as CR2. */
29349 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
29351 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
29352 if (flag_shrink_wrap
)
29354 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
29355 gen_rtx_REG (Pmode
, LR_REGNO
),
29357 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
29361 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
29363 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
29365 = gen_frame_load (reg
,
29366 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
29367 if (flag_shrink_wrap
)
29368 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
29370 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
29372 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
29374 = gen_frame_load (reg
,
29375 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
29376 if (flag_shrink_wrap
)
29377 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
29379 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
29381 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
29382 ? DFmode
: SFmode
),
29383 info
->first_fp_reg_save
+ i
);
29385 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
29386 if (flag_shrink_wrap
)
29387 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
29390 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
29392 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
29394 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
29396 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
29398 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
29399 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
29401 if (flag_shrink_wrap
)
29403 REG_NOTES (insn
) = cfa_restores
;
29404 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
29405 RTX_FRAME_RELATED_P (insn
) = 1;
29410 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
29412 frame_off
= info
->total_size
;
29414 /* Restore AltiVec registers if we must do so before adjusting the
29416 if (info
->altivec_size
!= 0
29417 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
29418 || (DEFAULT_ABI
!= ABI_V4
29419 && offset_below_red_zone_p (info
->altivec_save_offset
))))
29422 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
29424 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
29425 if (use_backchain_to_restore_sp
)
29427 int frame_regno
= 11;
29429 if ((strategy
& REST_INLINE_VRS
) == 0)
29431 /* Of r11 and r12, select the one not clobbered by an
29432 out-of-line restore function for the frame register. */
29433 frame_regno
= 11 + 12 - scratch_regno
;
29435 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
29436 emit_move_insn (frame_reg_rtx
,
29437 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
29440 else if (frame_pointer_needed
)
29441 frame_reg_rtx
= hard_frame_pointer_rtx
;
29443 if ((strategy
& REST_INLINE_VRS
) == 0)
29445 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
29447 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
29448 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
29450 if (end_save
+ frame_off
!= 0)
29452 rtx offset
= GEN_INT (end_save
+ frame_off
);
29454 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
29457 emit_move_insn (ptr_reg
, frame_reg_rtx
);
29459 ptr_off
= -end_save
;
29460 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
29461 info
->altivec_save_offset
+ ptr_off
,
29462 0, V4SImode
, SAVRES_VR
);
29466 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
29467 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
29469 rtx addr
, areg
, mem
, insn
;
29470 rtx reg
= gen_rtx_REG (V4SImode
, i
);
29471 HOST_WIDE_INT offset
29472 = (info
->altivec_save_offset
+ frame_off
29473 + 16 * (i
- info
->first_altivec_reg_save
));
29475 if (TARGET_P9_DFORM_VECTOR
&& quad_address_offset_p (offset
))
29477 mem
= gen_frame_mem (V4SImode
,
29478 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
29479 GEN_INT (offset
)));
29480 insn
= gen_rtx_SET (reg
, mem
);
29484 areg
= gen_rtx_REG (Pmode
, 0);
29485 emit_move_insn (areg
, GEN_INT (offset
));
29487 /* AltiVec addressing mode is [reg+reg]. */
29488 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
29489 mem
= gen_frame_mem (V4SImode
, addr
);
29491 /* Rather than emitting a generic move, force use of the
29492 lvx instruction, which we always want. In particular we
29493 don't want lxvd2x/xxpermdi for little endian. */
29494 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
29497 (void) emit_insn (insn
);
29501 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
29502 if (((strategy
& REST_INLINE_VRS
) == 0
29503 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
29504 && (flag_shrink_wrap
29505 || (offset_below_red_zone_p
29506 (info
->altivec_save_offset
29507 + 16 * (i
- info
->first_altivec_reg_save
)))))
29509 rtx reg
= gen_rtx_REG (V4SImode
, i
);
29510 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
29514 /* Restore VRSAVE if we must do so before adjusting the stack. */
29515 if (info
->vrsave_size
!= 0
29516 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
29517 || (DEFAULT_ABI
!= ABI_V4
29518 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
29522 if (frame_reg_rtx
== sp_reg_rtx
)
29524 if (use_backchain_to_restore_sp
)
29526 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
29527 emit_move_insn (frame_reg_rtx
,
29528 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
29531 else if (frame_pointer_needed
)
29532 frame_reg_rtx
= hard_frame_pointer_rtx
;
29535 reg
= gen_rtx_REG (SImode
, 12);
29536 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
29537 info
->vrsave_save_offset
+ frame_off
));
29539 emit_insn (generate_set_vrsave (reg
, info
, 1));
29543 /* If we have a large stack frame, restore the old stack pointer
29544 using the backchain. */
29545 if (use_backchain_to_restore_sp
)
29547 if (frame_reg_rtx
== sp_reg_rtx
)
29549 /* Under V.4, don't reset the stack pointer until after we're done
29550 loading the saved registers. */
29551 if (DEFAULT_ABI
== ABI_V4
)
29552 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
29554 insn
= emit_move_insn (frame_reg_rtx
,
29555 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
29558 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
29559 && DEFAULT_ABI
== ABI_V4
)
29560 /* frame_reg_rtx has been set up by the altivec restore. */
29564 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
29565 frame_reg_rtx
= sp_reg_rtx
;
29568 /* If we have a frame pointer, we can restore the old stack pointer
29570 else if (frame_pointer_needed
)
29572 frame_reg_rtx
= sp_reg_rtx
;
29573 if (DEFAULT_ABI
== ABI_V4
)
29574 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
29575 /* Prevent reordering memory accesses against stack pointer restore. */
29576 else if (cfun
->calls_alloca
29577 || offset_below_red_zone_p (-info
->total_size
))
29578 rs6000_emit_stack_tie (frame_reg_rtx
, true);
29580 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
29581 GEN_INT (info
->total_size
)));
29584 else if (info
->push_p
29585 && DEFAULT_ABI
!= ABI_V4
29586 && !crtl
->calls_eh_return
)
29588 /* Prevent reordering memory accesses against stack pointer restore. */
29589 if (cfun
->calls_alloca
29590 || offset_below_red_zone_p (-info
->total_size
))
29591 rs6000_emit_stack_tie (frame_reg_rtx
, false);
29592 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
29593 GEN_INT (info
->total_size
)));
29596 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
29600 REG_NOTES (insn
) = cfa_restores
;
29601 cfa_restores
= NULL_RTX
;
29603 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
29604 RTX_FRAME_RELATED_P (insn
) = 1;
29607 /* Restore AltiVec registers if we have not done so already. */
29608 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
29609 && info
->altivec_size
!= 0
29610 && (DEFAULT_ABI
== ABI_V4
29611 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
29615 if ((strategy
& REST_INLINE_VRS
) == 0)
29617 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
29619 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
29620 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
29621 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
29623 if (end_save
+ frame_off
!= 0)
29625 rtx offset
= GEN_INT (end_save
+ frame_off
);
29627 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
29630 emit_move_insn (ptr_reg
, frame_reg_rtx
);
29632 ptr_off
= -end_save
;
29633 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
29634 info
->altivec_save_offset
+ ptr_off
,
29635 0, V4SImode
, SAVRES_VR
);
29636 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
29638 /* Frame reg was clobbered by out-of-line save. Restore it
29639 from ptr_reg, and if we are calling out-of-line gpr or
29640 fpr restore set up the correct pointer and offset. */
29641 unsigned newptr_regno
= 1;
29642 if (!restoring_GPRs_inline
)
29644 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
29645 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
29646 newptr_regno
= ptr_regno_for_savres (sel
);
29647 end_save
= info
->gp_save_offset
+ info
->gp_size
;
29649 else if (!restoring_FPRs_inline
)
29651 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
29652 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
29653 newptr_regno
= ptr_regno_for_savres (sel
);
29654 end_save
= info
->fp_save_offset
+ info
->fp_size
;
29657 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
29658 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
29660 if (end_save
+ ptr_off
!= 0)
29662 rtx offset
= GEN_INT (end_save
+ ptr_off
);
29664 frame_off
= -end_save
;
29666 emit_insn (gen_addsi3_carry (frame_reg_rtx
,
29669 emit_insn (gen_adddi3_carry (frame_reg_rtx
,
29674 frame_off
= ptr_off
;
29675 emit_move_insn (frame_reg_rtx
, ptr_reg
);
29681 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
29682 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
29684 rtx addr
, areg
, mem
, insn
;
29685 rtx reg
= gen_rtx_REG (V4SImode
, i
);
29686 HOST_WIDE_INT offset
29687 = (info
->altivec_save_offset
+ frame_off
29688 + 16 * (i
- info
->first_altivec_reg_save
));
29690 if (TARGET_P9_DFORM_VECTOR
&& quad_address_offset_p (offset
))
29692 mem
= gen_frame_mem (V4SImode
,
29693 gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
29694 GEN_INT (offset
)));
29695 insn
= gen_rtx_SET (reg
, mem
);
29699 areg
= gen_rtx_REG (Pmode
, 0);
29700 emit_move_insn (areg
, GEN_INT (offset
));
29702 /* AltiVec addressing mode is [reg+reg]. */
29703 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
29704 mem
= gen_frame_mem (V4SImode
, addr
);
29706 /* Rather than emitting a generic move, force use of the
29707 lvx instruction, which we always want. In particular we
29708 don't want lxvd2x/xxpermdi for little endian. */
29709 insn
= gen_altivec_lvx_v4si_internal (reg
, mem
);
29712 (void) emit_insn (insn
);
29716 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
29717 if (((strategy
& REST_INLINE_VRS
) == 0
29718 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
29719 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
29721 rtx reg
= gen_rtx_REG (V4SImode
, i
);
29722 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
29726 /* Restore VRSAVE if we have not done so already. */
29727 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
29728 && info
->vrsave_size
!= 0
29729 && (DEFAULT_ABI
== ABI_V4
29730 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
29734 reg
= gen_rtx_REG (SImode
, 12);
29735 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
29736 info
->vrsave_save_offset
+ frame_off
));
29738 emit_insn (generate_set_vrsave (reg
, info
, 1));
29741 /* If we exit by an out-of-line restore function on ABI_V4 then that
29742 function will deallocate the stack, so we don't need to worry
29743 about the unwinder restoring cr from an invalid stack frame
29745 exit_func
= (!restoring_FPRs_inline
29746 || (!restoring_GPRs_inline
29747 && info
->first_fp_reg_save
== 64));
29749 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
29750 *separate* slots if the routine calls __builtin_eh_return, so
29751 that they can be independently restored by the unwinder. */
29752 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
29754 int i
, cr_off
= info
->ehcr_offset
;
29756 for (i
= 0; i
< 8; i
++)
29757 if (!call_used_regs
[CR0_REGNO
+ i
])
29759 rtx reg
= gen_rtx_REG (SImode
, 0);
29760 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
29761 cr_off
+ frame_off
));
29763 insn
= emit_insn (gen_movsi_to_cr_one
29764 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
29766 if (!exit_func
&& flag_shrink_wrap
)
29768 add_reg_note (insn
, REG_CFA_RESTORE
,
29769 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
29771 RTX_FRAME_RELATED_P (insn
) = 1;
29774 cr_off
+= reg_size
;
29778 /* Get the old lr if we saved it. If we are restoring registers
29779 out-of-line, then the out-of-line routines can do this for us. */
29780 if (restore_lr
&& restoring_GPRs_inline
)
29781 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
29783 /* Get the old cr if we saved it. */
29784 if (info
->cr_save_p
)
29786 unsigned cr_save_regno
= 12;
29788 if (!restoring_GPRs_inline
)
29790 /* Ensure we don't use the register used by the out-of-line
29791 gpr register restore below. */
29792 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
29793 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
29794 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
29796 if (gpr_ptr_regno
== 12)
29797 cr_save_regno
= 11;
29798 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
29800 else if (REGNO (frame_reg_rtx
) == 12)
29801 cr_save_regno
= 11;
29803 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
29804 info
->cr_save_offset
+ frame_off
,
29808 /* Set LR here to try to overlap restores below. */
29809 if (restore_lr
&& restoring_GPRs_inline
)
29810 restore_saved_lr (0, exit_func
);
29812 /* Load exception handler data registers, if needed. */
29813 if (crtl
->calls_eh_return
)
29815 unsigned int i
, regno
;
29819 rtx reg
= gen_rtx_REG (reg_mode
, 2);
29820 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
29821 frame_off
+ RS6000_TOC_SAVE_SLOT
));
29828 regno
= EH_RETURN_DATA_REGNO (i
);
29829 if (regno
== INVALID_REGNUM
)
29832 /* Note: possible use of r0 here to address SPE regs. */
29833 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
29834 info
->ehrd_offset
+ frame_off
29835 + reg_size
* (int) i
);
29837 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
29841 /* Restore GPRs. This is done as a PARALLEL if we are using
29842 the load-multiple instructions. */
29844 && info
->spe_64bit_regs_used
29845 && info
->first_gp_reg_save
!= 32)
29847 /* Determine whether we can address all of the registers that need
29848 to be saved with an offset from frame_reg_rtx that fits in
29849 the small const field for SPE memory instructions. */
29850 int spe_regs_addressable
29851 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
29852 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
29853 && restoring_GPRs_inline
);
29855 if (!spe_regs_addressable
)
29857 int ool_adjust
= 0;
29858 rtx old_frame_reg_rtx
= frame_reg_rtx
;
29859 /* Make r11 point to the start of the SPE save area. We worried about
29860 not clobbering it when we were saving registers in the prologue.
29861 There's no need to worry here because the static chain is passed
29862 anew to every function. */
29864 if (!restoring_GPRs_inline
)
29865 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
29866 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
29867 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
29868 GEN_INT (info
->spe_gp_save_offset
29871 /* Keep the invariant that frame_reg_rtx + frame_off points
29872 at the top of the stack frame. */
29873 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
29876 if (restoring_GPRs_inline
)
29878 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
29880 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
29881 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
29883 rtx offset
, addr
, mem
, reg
;
29885 /* We're doing all this to ensure that the immediate offset
29886 fits into the immediate field of 'evldd'. */
29887 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
29889 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
29890 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
29891 mem
= gen_rtx_MEM (V2SImode
, addr
);
29892 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
29894 emit_move_insn (reg
, mem
);
29898 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
29899 info
->spe_gp_save_offset
+ frame_off
,
29900 info
->lr_save_offset
+ frame_off
,
29902 SAVRES_GPR
| SAVRES_LR
);
29904 else if (!restoring_GPRs_inline
)
29906 /* We are jumping to an out-of-line function. */
29908 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
29909 bool can_use_exit
= end_save
== 0;
29910 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
29913 /* Emit stack reset code if we need it. */
29914 ptr_regno
= ptr_regno_for_savres (sel
);
29915 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
29917 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
29918 else if (end_save
+ frame_off
!= 0)
29919 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
29920 GEN_INT (end_save
+ frame_off
)));
29921 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
29922 emit_move_insn (ptr_reg
, frame_reg_rtx
);
29923 if (REGNO (frame_reg_rtx
) == ptr_regno
)
29924 frame_off
= -end_save
;
29926 if (can_use_exit
&& info
->cr_save_p
)
29927 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
29929 ptr_off
= -end_save
;
29930 rs6000_emit_savres_rtx (info
, ptr_reg
,
29931 info
->gp_save_offset
+ ptr_off
,
29932 info
->lr_save_offset
+ ptr_off
,
29935 else if (using_load_multiple
)
29938 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
29939 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
29941 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
29943 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
29944 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
29948 int offset
= info
->gp_save_offset
+ frame_off
;
29949 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
29951 if (rs6000_reg_live_or_pic_offset_p (i
)
29952 && !cfun
->machine
->gpr_is_wrapped_separately
[i
])
29954 rtx reg
= gen_rtx_REG (reg_mode
, i
);
29955 emit_insn (gen_frame_load (reg
, frame_reg_rtx
, offset
));
29958 offset
+= reg_size
;
29962 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
29964 /* If the frame pointer was used then we can't delay emitting
29965 a REG_CFA_DEF_CFA note. This must happen on the insn that
29966 restores the frame pointer, r31. We may have already emitted
29967 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
29968 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
29969 be harmless if emitted. */
29970 if (frame_pointer_needed
)
29972 insn
= get_last_insn ();
29973 add_reg_note (insn
, REG_CFA_DEF_CFA
,
29974 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
29975 RTX_FRAME_RELATED_P (insn
) = 1;
29978 /* Set up cfa_restores. We always need these when
29979 shrink-wrapping. If not shrink-wrapping then we only need
29980 the cfa_restore when the stack location is no longer valid.
29981 The cfa_restores must be emitted on or before the insn that
29982 invalidates the stack, and of course must not be emitted
29983 before the insn that actually does the restore. The latter
29984 is why it is a bad idea to emit the cfa_restores as a group
29985 on the last instruction here that actually does a restore:
29986 That insn may be reordered with respect to others doing
29988 if (flag_shrink_wrap
29989 && !restoring_GPRs_inline
29990 && info
->first_fp_reg_save
== 64)
29991 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
29993 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
29994 if (!restoring_GPRs_inline
29995 || using_load_multiple
29996 || rs6000_reg_live_or_pic_offset_p (i
))
29998 if (cfun
->machine
->gpr_is_wrapped_separately
[i
])
30001 rtx reg
= gen_rtx_REG (reg_mode
, i
);
30002 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
30006 if (!restoring_GPRs_inline
30007 && info
->first_fp_reg_save
== 64)
30009 /* We are jumping to an out-of-line function. */
30011 emit_cfa_restores (cfa_restores
);
30015 if (restore_lr
&& !restoring_GPRs_inline
)
30017 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
30018 restore_saved_lr (0, exit_func
);
30021 /* Restore fpr's if we need to do it without calling a function. */
30022 if (restoring_FPRs_inline
)
30023 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
30024 if (save_reg_p (info
->first_fp_reg_save
+ i
))
30026 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
30027 ? DFmode
: SFmode
),
30028 info
->first_fp_reg_save
+ i
);
30029 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
30030 info
->fp_save_offset
+ frame_off
+ 8 * i
));
30031 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
30032 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
30035 /* If we saved cr, restore it here. Just those that were used. */
30036 if (info
->cr_save_p
)
30037 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
30039 /* If this is V.4, unwind the stack pointer after all of the loads
30040 have been done, or set up r11 if we are restoring fp out of line. */
30042 if (!restoring_FPRs_inline
)
30044 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
30045 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
30046 ptr_regno
= ptr_regno_for_savres (sel
);
30049 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
30050 if (REGNO (frame_reg_rtx
) == ptr_regno
)
30053 if (insn
&& restoring_FPRs_inline
)
30057 REG_NOTES (insn
) = cfa_restores
;
30058 cfa_restores
= NULL_RTX
;
30060 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
30061 RTX_FRAME_RELATED_P (insn
) = 1;
30064 if (crtl
->calls_eh_return
)
30066 rtx sa
= EH_RETURN_STACKADJ_RTX
;
30067 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
30070 if (!sibcall
&& restoring_FPRs_inline
)
30074 /* We can't hang the cfa_restores off a simple return,
30075 since the shrink-wrap code sometimes uses an existing
30076 return. This means there might be a path from
30077 pre-prologue code to this return, and dwarf2cfi code
30078 wants the eh_frame unwinder state to be the same on
30079 all paths to any point. So we need to emit the
30080 cfa_restores before the return. For -m64 we really
30081 don't need epilogue cfa_restores at all, except for
30082 this irritating dwarf2cfi with shrink-wrap
30083 requirement; The stack red-zone means eh_frame info
30084 from the prologue telling the unwinder to restore
30085 from the stack is perfectly good right to the end of
30087 emit_insn (gen_blockage ());
30088 emit_cfa_restores (cfa_restores
);
30089 cfa_restores
= NULL_RTX
;
30092 emit_jump_insn (targetm
.gen_simple_return ());
30095 if (!sibcall
&& !restoring_FPRs_inline
)
30097 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
30098 rtvec p
= rtvec_alloc (3 + !!lr
+ 64 - info
->first_fp_reg_save
);
30100 RTVEC_ELT (p
, elt
++) = ret_rtx
;
30102 RTVEC_ELT (p
, elt
++)
30103 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
30105 /* We have to restore more than two FP registers, so branch to the
30106 restore function. It will return to our caller. */
30111 if (flag_shrink_wrap
)
30112 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
30114 sym
= rs6000_savres_routine_sym (info
, SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
30115 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, sym
);
30116 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
30117 RTVEC_ELT (p
, elt
++) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
30119 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
30121 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
30123 RTVEC_ELT (p
, elt
++)
30124 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
30125 if (flag_shrink_wrap
)
30126 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
30129 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
30135 /* Ensure the cfa_restores are hung off an insn that won't
30136 be reordered above other restores. */
30137 emit_insn (gen_blockage ());
30139 emit_cfa_restores (cfa_restores
);
30143 /* Write function epilogue. */
30146 rs6000_output_function_epilogue (FILE *file
,
30147 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
30150 macho_branch_islands ();
30151 /* Mach-O doesn't support labels at the end of objects, so if
30152 it looks like we might want one, insert a NOP. */
30154 rtx_insn
*insn
= get_last_insn ();
30155 rtx_insn
*deleted_debug_label
= NULL
;
30158 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
30160 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
30161 notes only, instead set their CODE_LABEL_NUMBER to -1,
30162 otherwise there would be code generation differences
30163 in between -g and -g0. */
30164 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
30165 deleted_debug_label
= insn
;
30166 insn
= PREV_INSN (insn
);
30171 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
30172 fputs ("\tnop\n", file
);
30173 else if (deleted_debug_label
)
30174 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
30175 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
30176 CODE_LABEL_NUMBER (insn
) = -1;
30180 /* Output a traceback table here. See /usr/include/sys/debug.h for info
30183 We don't output a traceback table if -finhibit-size-directive was
30184 used. The documentation for -finhibit-size-directive reads
30185 ``don't output a @code{.size} assembler directive, or anything
30186 else that would cause trouble if the function is split in the
30187 middle, and the two halves are placed at locations far apart in
30188 memory.'' The traceback table has this property, since it
30189 includes the offset from the start of the function to the
30190 traceback table itself.
30192 System V.4 Powerpc's (and the embedded ABI derived from it) use a
30193 different traceback table. */
30194 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
30195 && ! flag_inhibit_size_directive
30196 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
30198 const char *fname
= NULL
;
30199 const char *language_string
= lang_hooks
.name
;
30200 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
30202 int optional_tbtab
;
30203 rs6000_stack_t
*info
= rs6000_stack_info ();
30205 if (rs6000_traceback
== traceback_full
)
30206 optional_tbtab
= 1;
30207 else if (rs6000_traceback
== traceback_part
)
30208 optional_tbtab
= 0;
30210 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
30212 if (optional_tbtab
)
30214 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
30215 while (*fname
== '.') /* V.4 encodes . in the name */
30218 /* Need label immediately before tbtab, so we can compute
30219 its offset from the function start. */
30220 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
30221 ASM_OUTPUT_LABEL (file
, fname
);
30224 /* The .tbtab pseudo-op can only be used for the first eight
30225 expressions, since it can't handle the possibly variable
30226 length fields that follow. However, if you omit the optional
30227 fields, the assembler outputs zeros for all optional fields
30228 anyways, giving each variable length field is minimum length
30229 (as defined in sys/debug.h). Thus we can not use the .tbtab
30230 pseudo-op at all. */
30232 /* An all-zero word flags the start of the tbtab, for debuggers
30233 that have to find it by searching forward from the entry
30234 point or from the current pc. */
30235 fputs ("\t.long 0\n", file
);
30237 /* Tbtab format type. Use format type 0. */
30238 fputs ("\t.byte 0,", file
);
30240 /* Language type. Unfortunately, there does not seem to be any
30241 official way to discover the language being compiled, so we
30242 use language_string.
30243 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
30244 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
30245 a number, so for now use 9. LTO, Go and JIT aren't assigned numbers
30246 either, so for now use 0. */
30248 || ! strcmp (language_string
, "GNU GIMPLE")
30249 || ! strcmp (language_string
, "GNU Go")
30250 || ! strcmp (language_string
, "libgccjit"))
30252 else if (! strcmp (language_string
, "GNU F77")
30253 || lang_GNU_Fortran ())
30255 else if (! strcmp (language_string
, "GNU Pascal"))
30257 else if (! strcmp (language_string
, "GNU Ada"))
30259 else if (lang_GNU_CXX ()
30260 || ! strcmp (language_string
, "GNU Objective-C++"))
30262 else if (! strcmp (language_string
, "GNU Java"))
30264 else if (! strcmp (language_string
, "GNU Objective-C"))
30267 gcc_unreachable ();
30268 fprintf (file
, "%d,", i
);
30270 /* 8 single bit fields: global linkage (not set for C extern linkage,
30271 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
30272 from start of procedure stored in tbtab, internal function, function
30273 has controlled storage, function has no toc, function uses fp,
30274 function logs/aborts fp operations. */
30275 /* Assume that fp operations are used if any fp reg must be saved. */
30276 fprintf (file
, "%d,",
30277 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
30279 /* 6 bitfields: function is interrupt handler, name present in
30280 proc table, function calls alloca, on condition directives
30281 (controls stack walks, 3 bits), saves condition reg, saves
30283 /* The `function calls alloca' bit seems to be set whenever reg 31 is
30284 set up as a frame pointer, even when there is no alloca call. */
30285 fprintf (file
, "%d,",
30286 ((optional_tbtab
<< 6)
30287 | ((optional_tbtab
& frame_pointer_needed
) << 5)
30288 | (info
->cr_save_p
<< 1)
30289 | (info
->lr_save_p
)));
30291 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
30293 fprintf (file
, "%d,",
30294 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
30296 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
30297 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
30299 if (optional_tbtab
)
30301 /* Compute the parameter info from the function decl argument
30304 int next_parm_info_bit
= 31;
30306 for (decl
= DECL_ARGUMENTS (current_function_decl
);
30307 decl
; decl
= DECL_CHAIN (decl
))
30309 rtx parameter
= DECL_INCOMING_RTL (decl
);
30310 machine_mode mode
= GET_MODE (parameter
);
30312 if (GET_CODE (parameter
) == REG
)
30314 if (SCALAR_FLOAT_MODE_P (mode
))
30337 gcc_unreachable ();
30340 /* If only one bit will fit, don't or in this entry. */
30341 if (next_parm_info_bit
> 0)
30342 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
30343 next_parm_info_bit
-= 2;
30347 fixed_parms
+= ((GET_MODE_SIZE (mode
)
30348 + (UNITS_PER_WORD
- 1))
30350 next_parm_info_bit
-= 1;
30356 /* Number of fixed point parameters. */
30357 /* This is actually the number of words of fixed point parameters; thus
30358 an 8 byte struct counts as 2; and thus the maximum value is 8. */
30359 fprintf (file
, "%d,", fixed_parms
);
30361 /* 2 bitfields: number of floating point parameters (7 bits), parameters
30363 /* This is actually the number of fp registers that hold parameters;
30364 and thus the maximum value is 13. */
30365 /* Set parameters on stack bit if parameters are not in their original
30366 registers, regardless of whether they are on the stack? Xlc
30367 seems to set the bit when not optimizing. */
30368 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
30370 if (! optional_tbtab
)
30373 /* Optional fields follow. Some are variable length. */
30375 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
30376 11 double float. */
30377 /* There is an entry for each parameter in a register, in the order that
30378 they occur in the parameter list. Any intervening arguments on the
30379 stack are ignored. If the list overflows a long (max possible length
30380 34 bits) then completely leave off all elements that don't fit. */
30381 /* Only emit this long if there was at least one parameter. */
30382 if (fixed_parms
|| float_parms
)
30383 fprintf (file
, "\t.long %d\n", parm_info
);
30385 /* Offset from start of code to tb table. */
30386 fputs ("\t.long ", file
);
30387 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
30388 RS6000_OUTPUT_BASENAME (file
, fname
);
30390 rs6000_output_function_entry (file
, fname
);
30393 /* Interrupt handler mask. */
30394 /* Omit this long, since we never set the interrupt handler bit
30397 /* Number of CTL (controlled storage) anchors. */
30398 /* Omit this long, since the has_ctl bit is never set above. */
30400 /* Displacement into stack of each CTL anchor. */
30401 /* Omit this list of longs, because there are no CTL anchors. */
30403 /* Length of function name. */
30406 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
30408 /* Function name. */
30409 assemble_string (fname
, strlen (fname
));
30411 /* Register for alloca automatic storage; this is always reg 31.
30412 Only emit this if the alloca bit was set above. */
30413 if (frame_pointer_needed
)
30414 fputs ("\t.byte 31\n", file
);
30416 fputs ("\t.align 2\n", file
);
30419 /* Arrange to define .LCTOC1 label, if not already done. */
30423 if (!toc_initialized
)
30425 switch_to_section (toc_section
);
30426 switch_to_section (current_function_section ());
30431 /* -fsplit-stack support. */
30433 /* A SYMBOL_REF for __morestack. */
30434 static GTY(()) rtx morestack_ref
;
30437 gen_add3_const (rtx rt
, rtx ra
, long c
)
30440 return gen_adddi3 (rt
, ra
, GEN_INT (c
));
30442 return gen_addsi3 (rt
, ra
, GEN_INT (c
));
30445 /* Emit -fsplit-stack prologue, which goes before the regular function
30446 prologue (at local entry point in the case of ELFv2). */
30449 rs6000_expand_split_stack_prologue (void)
30451 rs6000_stack_t
*info
= rs6000_stack_info ();
30452 unsigned HOST_WIDE_INT allocate
;
30453 long alloc_hi
, alloc_lo
;
30454 rtx r0
, r1
, r12
, lr
, ok_label
, compare
, jump
, call_fusage
;
30457 gcc_assert (flag_split_stack
&& reload_completed
);
30462 if (global_regs
[29])
30464 error ("-fsplit-stack uses register r29");
30465 inform (DECL_SOURCE_LOCATION (global_regs_decl
[29]),
30466 "conflicts with %qD", global_regs_decl
[29]);
30469 allocate
= info
->total_size
;
30470 if (allocate
> (unsigned HOST_WIDE_INT
) 1 << 31)
30472 sorry ("Stack frame larger than 2G is not supported for -fsplit-stack");
30475 if (morestack_ref
== NULL_RTX
)
30477 morestack_ref
= gen_rtx_SYMBOL_REF (Pmode
, "__morestack");
30478 SYMBOL_REF_FLAGS (morestack_ref
) |= (SYMBOL_FLAG_LOCAL
30479 | SYMBOL_FLAG_FUNCTION
);
30482 r0
= gen_rtx_REG (Pmode
, 0);
30483 r1
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
30484 r12
= gen_rtx_REG (Pmode
, 12);
30485 emit_insn (gen_load_split_stack_limit (r0
));
30486 /* Always emit two insns here to calculate the requested stack,
30487 so that the linker can edit them when adjusting size for calling
30488 non-split-stack code. */
30489 alloc_hi
= (-allocate
+ 0x8000) & ~0xffffL
;
30490 alloc_lo
= -allocate
- alloc_hi
;
30493 emit_insn (gen_add3_const (r12
, r1
, alloc_hi
));
30495 emit_insn (gen_add3_const (r12
, r12
, alloc_lo
));
30497 emit_insn (gen_nop ());
30501 emit_insn (gen_add3_const (r12
, r1
, alloc_lo
));
30502 emit_insn (gen_nop ());
30505 compare
= gen_rtx_REG (CCUNSmode
, CR7_REGNO
);
30506 emit_insn (gen_rtx_SET (compare
, gen_rtx_COMPARE (CCUNSmode
, r12
, r0
)));
30507 ok_label
= gen_label_rtx ();
30508 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
30509 gen_rtx_GEU (VOIDmode
, compare
, const0_rtx
),
30510 gen_rtx_LABEL_REF (VOIDmode
, ok_label
),
30512 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
30513 JUMP_LABEL (jump
) = ok_label
;
30514 /* Mark the jump as very likely to be taken. */
30515 add_int_reg_note (jump
, REG_BR_PROB
,
30516 REG_BR_PROB_BASE
- REG_BR_PROB_BASE
/ 100);
30518 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
30519 insn
= emit_move_insn (r0
, lr
);
30520 RTX_FRAME_RELATED_P (insn
) = 1;
30521 insn
= emit_insn (gen_frame_store (r0
, r1
, info
->lr_save_offset
));
30522 RTX_FRAME_RELATED_P (insn
) = 1;
30524 insn
= emit_call_insn (gen_call (gen_rtx_MEM (SImode
, morestack_ref
),
30525 const0_rtx
, const0_rtx
));
30526 call_fusage
= NULL_RTX
;
30527 use_reg (&call_fusage
, r12
);
30528 /* Say the call uses r0, even though it doesn't, to stop regrename
30529 from twiddling with the insns saving lr, trashing args for cfun.
30530 The insns restoring lr are similarly protected by making
30531 split_stack_return use r0. */
30532 use_reg (&call_fusage
, r0
);
30533 add_function_usage_to (insn
, call_fusage
);
30534 emit_insn (gen_frame_load (r0
, r1
, info
->lr_save_offset
));
30535 insn
= emit_move_insn (lr
, r0
);
30536 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
30537 RTX_FRAME_RELATED_P (insn
) = 1;
30538 emit_insn (gen_split_stack_return ());
30540 emit_label (ok_label
);
30541 LABEL_NUSES (ok_label
) = 1;
30544 /* Return the internal arg pointer used for function incoming
30545 arguments. When -fsplit-stack, the arg pointer is r12 so we need
30546 to copy it to a pseudo in order for it to be preserved over calls
30547 and suchlike. We'd really like to use a pseudo here for the
30548 internal arg pointer but data-flow analysis is not prepared to
30549 accept pseudos as live at the beginning of a function. */
30552 rs6000_internal_arg_pointer (void)
30554 if (flag_split_stack
30555 && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun
->decl
))
30559 if (cfun
->machine
->split_stack_arg_pointer
== NULL_RTX
)
30563 cfun
->machine
->split_stack_arg_pointer
= gen_reg_rtx (Pmode
);
30564 REG_POINTER (cfun
->machine
->split_stack_arg_pointer
) = 1;
30566 /* Put the pseudo initialization right after the note at the
30567 beginning of the function. */
30568 pat
= gen_rtx_SET (cfun
->machine
->split_stack_arg_pointer
,
30569 gen_rtx_REG (Pmode
, 12));
30570 push_topmost_sequence ();
30571 emit_insn_after (pat
, get_insns ());
30572 pop_topmost_sequence ();
30574 return plus_constant (Pmode
, cfun
->machine
->split_stack_arg_pointer
,
30575 FIRST_PARM_OFFSET (current_function_decl
));
30577 return virtual_incoming_args_rtx
;
30580 /* We may have to tell the dataflow pass that the split stack prologue
30581 is initializing a register. */
30584 rs6000_live_on_entry (bitmap regs
)
30586 if (flag_split_stack
)
30587 bitmap_set_bit (regs
, 12);
30590 /* Emit -fsplit-stack dynamic stack allocation space check. */
30593 rs6000_split_stack_space_check (rtx size
, rtx label
)
30595 rtx sp
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
30596 rtx limit
= gen_reg_rtx (Pmode
);
30597 rtx requested
= gen_reg_rtx (Pmode
);
30598 rtx cmp
= gen_reg_rtx (CCUNSmode
);
30601 emit_insn (gen_load_split_stack_limit (limit
));
30602 if (CONST_INT_P (size
))
30603 emit_insn (gen_add3_insn (requested
, sp
, GEN_INT (-INTVAL (size
))));
30606 size
= force_reg (Pmode
, size
);
30607 emit_move_insn (requested
, gen_rtx_MINUS (Pmode
, sp
, size
));
30609 emit_insn (gen_rtx_SET (cmp
, gen_rtx_COMPARE (CCUNSmode
, requested
, limit
)));
30610 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
30611 gen_rtx_GEU (VOIDmode
, cmp
, const0_rtx
),
30612 gen_rtx_LABEL_REF (VOIDmode
, label
),
30614 jump
= emit_jump_insn (gen_rtx_SET (pc_rtx
, jump
));
30615 JUMP_LABEL (jump
) = label
;
30618 /* A C compound statement that outputs the assembler code for a thunk
30619 function, used to implement C++ virtual function calls with
30620 multiple inheritance. The thunk acts as a wrapper around a virtual
30621 function, adjusting the implicit object parameter before handing
30622 control off to the real function.
30624 First, emit code to add the integer DELTA to the location that
30625 contains the incoming first argument. Assume that this argument
30626 contains a pointer, and is the one used to pass the `this' pointer
30627 in C++. This is the incoming argument *before* the function
30628 prologue, e.g. `%o0' on a sparc. The addition must preserve the
30629 values of all other incoming arguments.
30631 After the addition, emit code to jump to FUNCTION, which is a
30632 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
30633 not touch the return address. Hence returning from FUNCTION will
30634 return to whoever called the current `thunk'.
30636 The effect must be as if FUNCTION had been called directly with the
30637 adjusted first argument. This macro is responsible for emitting
30638 all of the code for a thunk function; output_function_prologue()
30639 and output_function_epilogue() are not invoked.
30641 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
30642 been extracted from it.) It might possibly be useful on some
30643 targets, but probably not.
30645 If you do not define this macro, the target-independent code in the
30646 C++ frontend will generate a less efficient heavyweight thunk that
30647 calls FUNCTION instead of jumping to it. The generic approach does
30648 not support varargs. */
30651 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
30652 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
30655 rtx this_rtx
, funexp
;
30658 reload_completed
= 1;
30659 epilogue_completed
= 1;
30661 /* Mark the end of the (empty) prologue. */
30662 emit_note (NOTE_INSN_PROLOGUE_END
);
30664 /* Find the "this" pointer. If the function returns a structure,
30665 the structure return pointer is in r3. */
30666 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
30667 this_rtx
= gen_rtx_REG (Pmode
, 4);
30669 this_rtx
= gen_rtx_REG (Pmode
, 3);
30671 /* Apply the constant offset, if required. */
30673 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
30675 /* Apply the offset from the vtable, if required. */
30678 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
30679 rtx tmp
= gen_rtx_REG (Pmode
, 12);
30681 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
30682 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
30684 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
30685 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
30689 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
30691 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
30693 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
30696 /* Generate a tail call to the target function. */
30697 if (!TREE_USED (function
))
30699 assemble_external (function
);
30700 TREE_USED (function
) = 1;
30702 funexp
= XEXP (DECL_RTL (function
), 0);
30703 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
30706 if (MACHOPIC_INDIRECT
)
30707 funexp
= machopic_indirect_call_target (funexp
);
30710 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
30711 generate sibcall RTL explicitly. */
30712 insn
= emit_call_insn (
30713 gen_rtx_PARALLEL (VOIDmode
,
30715 gen_rtx_CALL (VOIDmode
,
30716 funexp
, const0_rtx
),
30717 gen_rtx_USE (VOIDmode
, const0_rtx
),
30718 simple_return_rtx
)));
30719 SIBLING_CALL_P (insn
) = 1;
30722 /* Run just enough of rest_of_compilation to get the insns emitted.
30723 There's not really enough bulk here to make other passes such as
30724 instruction scheduling worth while. Note that use_thunk calls
30725 assemble_start_function and assemble_end_function. */
30726 insn
= get_insns ();
30727 shorten_branches (insn
);
30728 final_start_function (insn
, file
, 1);
30729 final (insn
, file
, 1);
30730 final_end_function ();
30732 reload_completed
= 0;
30733 epilogue_completed
= 0;
30736 /* A quick summary of the various types of 'constant-pool tables'
30739 Target Flags Name One table per
30740 AIX (none) AIX TOC object file
30741 AIX -mfull-toc AIX TOC object file
30742 AIX -mminimal-toc AIX minimal TOC translation unit
30743 SVR4/EABI (none) SVR4 SDATA object file
30744 SVR4/EABI -fpic SVR4 pic object file
30745 SVR4/EABI -fPIC SVR4 PIC translation unit
30746 SVR4/EABI -mrelocatable EABI TOC function
30747 SVR4/EABI -maix AIX TOC object file
30748 SVR4/EABI -maix -mminimal-toc
30749 AIX minimal TOC translation unit
30751 Name Reg. Set by entries contains:
30752 made by addrs? fp? sum?
30754 AIX TOC 2 crt0 as Y option option
30755 AIX minimal TOC 30 prolog gcc Y Y option
30756 SVR4 SDATA 13 crt0 gcc N Y N
30757 SVR4 pic 30 prolog ld Y not yet N
30758 SVR4 PIC 30 prolog gcc Y option option
30759 EABI TOC 30 prolog gcc Y option option
30763 /* Hash functions for the hash table. */
30766 rs6000_hash_constant (rtx k
)
30768 enum rtx_code code
= GET_CODE (k
);
30769 machine_mode mode
= GET_MODE (k
);
30770 unsigned result
= (code
<< 3) ^ mode
;
30771 const char *format
;
30774 format
= GET_RTX_FORMAT (code
);
30775 flen
= strlen (format
);
30781 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
30783 case CONST_WIDE_INT
:
30786 flen
= CONST_WIDE_INT_NUNITS (k
);
30787 for (i
= 0; i
< flen
; i
++)
30788 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
30793 if (mode
!= VOIDmode
)
30794 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
30806 for (; fidx
< flen
; fidx
++)
30807 switch (format
[fidx
])
30812 const char *str
= XSTR (k
, fidx
);
30813 len
= strlen (str
);
30814 result
= result
* 613 + len
;
30815 for (i
= 0; i
< len
; i
++)
30816 result
= result
* 613 + (unsigned) str
[i
];
30821 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
30825 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
30828 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
30829 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
30833 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
30834 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
30841 gcc_unreachable ();
30848 toc_hasher::hash (toc_hash_struct
*thc
)
30850 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
30853 /* Compare H1 and H2 for equivalence. */
30856 toc_hasher::equal (toc_hash_struct
*h1
, toc_hash_struct
*h2
)
30861 if (h1
->key_mode
!= h2
->key_mode
)
30864 return rtx_equal_p (r1
, r2
);
30867 /* These are the names given by the C++ front-end to vtables, and
30868 vtable-like objects. Ideally, this logic should not be here;
30869 instead, there should be some programmatic way of inquiring as
30870 to whether or not an object is a vtable. */
30872 #define VTABLE_NAME_P(NAME) \
30873 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
30874 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
30875 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
30876 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
30877 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
30879 #ifdef NO_DOLLAR_IN_LABEL
30880 /* Return a GGC-allocated character string translating dollar signs in
30881 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
30884 rs6000_xcoff_strip_dollar (const char *name
)
30890 q
= (const char *) strchr (name
, '$');
30892 if (q
== 0 || q
== name
)
30895 len
= strlen (name
);
30896 strip
= XALLOCAVEC (char, len
+ 1);
30897 strcpy (strip
, name
);
30898 p
= strip
+ (q
- name
);
30902 p
= strchr (p
+ 1, '$');
30905 return ggc_alloc_string (strip
, len
);
30910 rs6000_output_symbol_ref (FILE *file
, rtx x
)
30912 const char *name
= XSTR (x
, 0);
30914 /* Currently C++ toc references to vtables can be emitted before it
30915 is decided whether the vtable is public or private. If this is
30916 the case, then the linker will eventually complain that there is
30917 a reference to an unknown section. Thus, for vtables only,
30918 we emit the TOC reference to reference the identifier and not the
30920 if (VTABLE_NAME_P (name
))
30922 RS6000_OUTPUT_BASENAME (file
, name
);
30925 assemble_name (file
, name
);
30928 /* Output a TOC entry. We derive the entry name from what is being
30932 output_toc (FILE *file
, rtx x
, int labelno
, machine_mode mode
)
30935 const char *name
= buf
;
30937 HOST_WIDE_INT offset
= 0;
30939 gcc_assert (!TARGET_NO_TOC
);
30941 /* When the linker won't eliminate them, don't output duplicate
30942 TOC entries (this happens on AIX if there is any kind of TOC,
30943 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
30945 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
30947 struct toc_hash_struct
*h
;
30949 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
30950 time because GGC is not initialized at that point. */
30951 if (toc_hash_table
== NULL
)
30952 toc_hash_table
= hash_table
<toc_hasher
>::create_ggc (1021);
30954 h
= ggc_alloc
<toc_hash_struct
> ();
30956 h
->key_mode
= mode
;
30957 h
->labelno
= labelno
;
30959 toc_hash_struct
**found
= toc_hash_table
->find_slot (h
, INSERT
);
30960 if (*found
== NULL
)
30962 else /* This is indeed a duplicate.
30963 Set this label equal to that label. */
30965 fputs ("\t.set ", file
);
30966 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
30967 fprintf (file
, "%d,", labelno
);
30968 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
30969 fprintf (file
, "%d\n", ((*found
)->labelno
));
30972 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
30973 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
30974 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
30976 fputs ("\t.set ", file
);
30977 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
30978 fprintf (file
, "%d,", labelno
);
30979 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
30980 fprintf (file
, "%d\n", ((*found
)->labelno
));
30987 /* If we're going to put a double constant in the TOC, make sure it's
30988 aligned properly when strict alignment is on. */
30989 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
30990 && STRICT_ALIGNMENT
30991 && GET_MODE_BITSIZE (mode
) >= 64
30992 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
30993 ASM_OUTPUT_ALIGN (file
, 3);
30996 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
30998 /* Handle FP constants specially. Note that if we have a minimal
30999 TOC, things we put here aren't actually in the TOC, so we can allow
31001 if (GET_CODE (x
) == CONST_DOUBLE
&&
31002 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
31003 || GET_MODE (x
) == IFmode
|| GET_MODE (x
) == KFmode
))
31007 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
31008 REAL_VALUE_TO_TARGET_DECIMAL128 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
31010 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
31014 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31015 fputs (DOUBLE_INT_ASM_OP
, file
);
31017 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
31018 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
31019 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
31020 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
31021 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
31022 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
31023 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
31024 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
31029 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31030 fputs ("\t.long ", file
);
31032 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
31033 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
31034 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
31035 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
31036 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
31037 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
31041 else if (GET_CODE (x
) == CONST_DOUBLE
&&
31042 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
31046 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
31047 REAL_VALUE_TO_TARGET_DECIMAL64 (*CONST_DOUBLE_REAL_VALUE (x
), k
);
31049 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), k
);
31053 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31054 fputs (DOUBLE_INT_ASM_OP
, file
);
31056 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
31057 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
31058 fprintf (file
, "0x%lx%08lx\n",
31059 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
31060 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
31065 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31066 fputs ("\t.long ", file
);
31068 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
31069 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
31070 fprintf (file
, "0x%lx,0x%lx\n",
31071 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
31075 else if (GET_CODE (x
) == CONST_DOUBLE
&&
31076 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
31080 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
31081 REAL_VALUE_TO_TARGET_DECIMAL32 (*CONST_DOUBLE_REAL_VALUE (x
), l
);
31083 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x
), l
);
31087 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31088 fputs (DOUBLE_INT_ASM_OP
, file
);
31090 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
31091 if (WORDS_BIG_ENDIAN
)
31092 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
31094 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
31099 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31100 fputs ("\t.long ", file
);
31102 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
31103 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
31107 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
31109 unsigned HOST_WIDE_INT low
;
31110 HOST_WIDE_INT high
;
31112 low
= INTVAL (x
) & 0xffffffff;
31113 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
31115 /* TOC entries are always Pmode-sized, so when big-endian
31116 smaller integer constants in the TOC need to be padded.
31117 (This is still a win over putting the constants in
31118 a separate constant pool, because then we'd have
31119 to have both a TOC entry _and_ the actual constant.)
31121 For a 32-bit target, CONST_INT values are loaded and shifted
31122 entirely within `low' and can be stored in one TOC entry. */
31124 /* It would be easy to make this work, but it doesn't now. */
31125 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
31127 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
31130 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
31131 high
= (HOST_WIDE_INT
) low
>> 32;
31137 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31138 fputs (DOUBLE_INT_ASM_OP
, file
);
31140 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
31141 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
31142 fprintf (file
, "0x%lx%08lx\n",
31143 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
31148 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
31150 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31151 fputs ("\t.long ", file
);
31153 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
31154 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
31155 fprintf (file
, "0x%lx,0x%lx\n",
31156 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
31160 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31161 fputs ("\t.long ", file
);
31163 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
31164 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
31170 if (GET_CODE (x
) == CONST
)
31172 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
31173 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
31175 base
= XEXP (XEXP (x
, 0), 0);
31176 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
31179 switch (GET_CODE (base
))
31182 name
= XSTR (base
, 0);
31186 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
31187 CODE_LABEL_NUMBER (XEXP (base
, 0)));
31191 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
31195 gcc_unreachable ();
31198 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
31199 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
31202 fputs ("\t.tc ", file
);
31203 RS6000_OUTPUT_BASENAME (file
, name
);
31206 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
31208 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
31210 /* Mark large TOC symbols on AIX with [TE] so they are mapped
31211 after other TOC symbols, reducing overflow of small TOC access
31212 to [TC] symbols. */
31213 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
31214 ? "[TE]," : "[TC],", file
);
31217 /* Currently C++ toc references to vtables can be emitted before it
31218 is decided whether the vtable is public or private. If this is
31219 the case, then the linker will eventually complain that there is
31220 a TOC reference to an unknown section. Thus, for vtables only,
31221 we emit the TOC reference to reference the symbol and not the
31223 if (VTABLE_NAME_P (name
))
31225 RS6000_OUTPUT_BASENAME (file
, name
);
31227 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
31228 else if (offset
> 0)
31229 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
31232 output_addr_const (file
, x
);
31235 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
)
31237 switch (SYMBOL_REF_TLS_MODEL (base
))
31241 case TLS_MODEL_LOCAL_EXEC
:
31242 fputs ("@le", file
);
31244 case TLS_MODEL_INITIAL_EXEC
:
31245 fputs ("@ie", file
);
31247 /* Use global-dynamic for local-dynamic. */
31248 case TLS_MODEL_GLOBAL_DYNAMIC
:
31249 case TLS_MODEL_LOCAL_DYNAMIC
:
31251 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
31252 fputs ("\t.tc .", file
);
31253 RS6000_OUTPUT_BASENAME (file
, name
);
31254 fputs ("[TC],", file
);
31255 output_addr_const (file
, x
);
31256 fputs ("@m", file
);
31259 gcc_unreachable ();
31267 /* Output an assembler pseudo-op to write an ASCII string of N characters
31268 starting at P to FILE.
31270 On the RS/6000, we have to do this using the .byte operation and
31271 write out special characters outside the quoted string.
31272 Also, the assembler is broken; very long strings are truncated,
31273 so we must artificially break them up early. */
31276 output_ascii (FILE *file
, const char *p
, int n
)
31279 int i
, count_string
;
31280 const char *for_string
= "\t.byte \"";
31281 const char *for_decimal
= "\t.byte ";
31282 const char *to_close
= NULL
;
31285 for (i
= 0; i
< n
; i
++)
31288 if (c
>= ' ' && c
< 0177)
31291 fputs (for_string
, file
);
31294 /* Write two quotes to get one. */
31302 for_decimal
= "\"\n\t.byte ";
31306 if (count_string
>= 512)
31308 fputs (to_close
, file
);
31310 for_string
= "\t.byte \"";
31311 for_decimal
= "\t.byte ";
31319 fputs (for_decimal
, file
);
31320 fprintf (file
, "%d", c
);
31322 for_string
= "\n\t.byte \"";
31323 for_decimal
= ", ";
31329 /* Now close the string if we have written one. Then end the line. */
31331 fputs (to_close
, file
);
31334 /* Generate a unique section name for FILENAME for a section type
31335 represented by SECTION_DESC. Output goes into BUF.
31337 SECTION_DESC can be any string, as long as it is different for each
31338 possible section type.
31340 We name the section in the same manner as xlc. The name begins with an
31341 underscore followed by the filename (after stripping any leading directory
31342 names) with the last period replaced by the string SECTION_DESC. If
31343 FILENAME does not contain a period, SECTION_DESC is appended to the end of
31347 rs6000_gen_section_name (char **buf
, const char *filename
,
31348 const char *section_desc
)
31350 const char *q
, *after_last_slash
, *last_period
= 0;
31354 after_last_slash
= filename
;
31355 for (q
= filename
; *q
; q
++)
31358 after_last_slash
= q
+ 1;
31359 else if (*q
== '.')
31363 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
31364 *buf
= (char *) xmalloc (len
);
31369 for (q
= after_last_slash
; *q
; q
++)
31371 if (q
== last_period
)
31373 strcpy (p
, section_desc
);
31374 p
+= strlen (section_desc
);
31378 else if (ISALNUM (*q
))
31382 if (last_period
== 0)
31383 strcpy (p
, section_desc
);
31388 /* Emit profile function. */
31391 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
31393 /* Non-standard profiling for kernels, which just saves LR then calls
31394 _mcount without worrying about arg saves. The idea is to change
31395 the function prologue as little as possible as it isn't easy to
31396 account for arg save/restore code added just for _mcount. */
31397 if (TARGET_PROFILE_KERNEL
)
31400 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
31402 #ifndef NO_PROFILE_COUNTERS
31403 # define NO_PROFILE_COUNTERS 0
31405 if (NO_PROFILE_COUNTERS
)
31406 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
31407 LCT_NORMAL
, VOIDmode
, 0);
31411 const char *label_name
;
31414 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
31415 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
31416 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
31418 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
31419 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
31422 else if (DEFAULT_ABI
== ABI_DARWIN
)
31424 const char *mcount_name
= RS6000_MCOUNT
;
31425 int caller_addr_regno
= LR_REGNO
;
31427 /* Be conservative and always set this, at least for now. */
31428 crtl
->uses_pic_offset_table
= 1;
31431 /* For PIC code, set up a stub and collect the caller's address
31432 from r0, which is where the prologue puts it. */
31433 if (MACHOPIC_INDIRECT
31434 && crtl
->uses_pic_offset_table
)
31435 caller_addr_regno
= 0;
31437 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
31438 LCT_NORMAL
, VOIDmode
, 1,
31439 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
31443 /* Write function profiler code. */
31446 output_function_profiler (FILE *file
, int labelno
)
31450 switch (DEFAULT_ABI
)
31453 gcc_unreachable ();
31458 warning (0, "no profiling of 64-bit code for this ABI");
31461 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
31462 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
31463 if (NO_PROFILE_COUNTERS
)
31465 asm_fprintf (file
, "\tstw %s,4(%s)\n",
31466 reg_names
[0], reg_names
[1]);
31468 else if (TARGET_SECURE_PLT
&& flag_pic
)
31470 if (TARGET_LINK_STACK
)
31473 get_ppc476_thunk_name (name
);
31474 asm_fprintf (file
, "\tbl %s\n", name
);
31477 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
31478 asm_fprintf (file
, "\tstw %s,4(%s)\n",
31479 reg_names
[0], reg_names
[1]);
31480 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
31481 asm_fprintf (file
, "\taddis %s,%s,",
31482 reg_names
[12], reg_names
[12]);
31483 assemble_name (file
, buf
);
31484 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
31485 assemble_name (file
, buf
);
31486 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
31488 else if (flag_pic
== 1)
31490 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
31491 asm_fprintf (file
, "\tstw %s,4(%s)\n",
31492 reg_names
[0], reg_names
[1]);
31493 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
31494 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
31495 assemble_name (file
, buf
);
31496 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
31498 else if (flag_pic
> 1)
31500 asm_fprintf (file
, "\tstw %s,4(%s)\n",
31501 reg_names
[0], reg_names
[1]);
31502 /* Now, we need to get the address of the label. */
31503 if (TARGET_LINK_STACK
)
31506 get_ppc476_thunk_name (name
);
31507 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
31508 assemble_name (file
, buf
);
31509 fputs ("-.\n1:", file
);
31510 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
31511 asm_fprintf (file
, "\taddi %s,%s,4\n",
31512 reg_names
[11], reg_names
[11]);
31516 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
31517 assemble_name (file
, buf
);
31518 fputs ("-.\n1:", file
);
31519 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
31521 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
31522 reg_names
[0], reg_names
[11]);
31523 asm_fprintf (file
, "\tadd %s,%s,%s\n",
31524 reg_names
[0], reg_names
[0], reg_names
[11]);
31528 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
31529 assemble_name (file
, buf
);
31530 fputs ("@ha\n", file
);
31531 asm_fprintf (file
, "\tstw %s,4(%s)\n",
31532 reg_names
[0], reg_names
[1]);
31533 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
31534 assemble_name (file
, buf
);
31535 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
31538 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
31539 fprintf (file
, "\tbl %s%s\n",
31540 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
31546 /* Don't do anything, done in output_profile_hook (). */
31553 /* The following variable value is the last issued insn. */
31555 static rtx_insn
*last_scheduled_insn
;
31557 /* The following variable helps to balance issuing of load and
31558 store instructions */
31560 static int load_store_pendulum
;
31562 /* The following variable helps pair divide insns during scheduling. */
31563 static int divide_cnt
;
31564 /* The following variable helps pair and alternate vector and vector load
31565 insns during scheduling. */
31566 static int vec_load_pendulum
;
31569 /* Power4 load update and store update instructions are cracked into a
31570 load or store and an integer insn which are executed in the same cycle.
31571 Branches have their own dispatch slot which does not count against the
31572 GCC issue rate, but it changes the program flow so there are no other
31573 instructions to issue in this cycle. */
31576 rs6000_variable_issue_1 (rtx_insn
*insn
, int more
)
31578 last_scheduled_insn
= insn
;
31579 if (GET_CODE (PATTERN (insn
)) == USE
31580 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31582 cached_can_issue_more
= more
;
31583 return cached_can_issue_more
;
31586 if (insn_terminates_group_p (insn
, current_group
))
31588 cached_can_issue_more
= 0;
31589 return cached_can_issue_more
;
31592 /* If no reservation, but reach here */
31593 if (recog_memoized (insn
) < 0)
31596 if (rs6000_sched_groups
)
31598 if (is_microcoded_insn (insn
))
31599 cached_can_issue_more
= 0;
31600 else if (is_cracked_insn (insn
))
31601 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
31603 cached_can_issue_more
= more
- 1;
31605 return cached_can_issue_more
;
31608 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
31611 cached_can_issue_more
= more
- 1;
31612 return cached_can_issue_more
;
31616 rs6000_variable_issue (FILE *stream
, int verbose
, rtx_insn
*insn
, int more
)
31618 int r
= rs6000_variable_issue_1 (insn
, more
);
31620 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
31624 /* Adjust the cost of a scheduling dependency. Return the new cost of
31625 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
31628 rs6000_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
31631 enum attr_type attr_type
;
31633 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
31640 /* Data dependency; DEP_INSN writes a register that INSN reads
31641 some cycles later. */
31643 /* Separate a load from a narrower, dependent store. */
31644 if ((rs6000_sched_groups
|| rs6000_cpu_attr
== CPU_POWER9
)
31645 && GET_CODE (PATTERN (insn
)) == SET
31646 && GET_CODE (PATTERN (dep_insn
)) == SET
31647 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
31648 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
31649 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
31650 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
31653 attr_type
= get_attr_type (insn
);
31658 /* Tell the first scheduling pass about the latency between
31659 a mtctr and bctr (and mtlr and br/blr). The first
31660 scheduling pass will not know about this latency since
31661 the mtctr instruction, which has the latency associated
31662 to it, will be generated by reload. */
31665 /* Leave some extra cycles between a compare and its
31666 dependent branch, to inhibit expensive mispredicts. */
31667 if ((rs6000_cpu_attr
== CPU_PPC603
31668 || rs6000_cpu_attr
== CPU_PPC604
31669 || rs6000_cpu_attr
== CPU_PPC604E
31670 || rs6000_cpu_attr
== CPU_PPC620
31671 || rs6000_cpu_attr
== CPU_PPC630
31672 || rs6000_cpu_attr
== CPU_PPC750
31673 || rs6000_cpu_attr
== CPU_PPC7400
31674 || rs6000_cpu_attr
== CPU_PPC7450
31675 || rs6000_cpu_attr
== CPU_PPCE5500
31676 || rs6000_cpu_attr
== CPU_PPCE6500
31677 || rs6000_cpu_attr
== CPU_POWER4
31678 || rs6000_cpu_attr
== CPU_POWER5
31679 || rs6000_cpu_attr
== CPU_POWER7
31680 || rs6000_cpu_attr
== CPU_POWER8
31681 || rs6000_cpu_attr
== CPU_POWER9
31682 || rs6000_cpu_attr
== CPU_CELL
)
31683 && recog_memoized (dep_insn
)
31684 && (INSN_CODE (dep_insn
) >= 0))
31686 switch (get_attr_type (dep_insn
))
31689 case TYPE_FPCOMPARE
:
31690 case TYPE_CR_LOGICAL
:
31691 case TYPE_DELAYED_CR
:
31695 if (get_attr_dot (dep_insn
) == DOT_YES
)
31700 if (get_attr_dot (dep_insn
) == DOT_YES
31701 && get_attr_var_shift (dep_insn
) == VAR_SHIFT_NO
)
31712 if ((rs6000_cpu
== PROCESSOR_POWER6
)
31713 && recog_memoized (dep_insn
)
31714 && (INSN_CODE (dep_insn
) >= 0))
31717 if (GET_CODE (PATTERN (insn
)) != SET
)
31718 /* If this happens, we have to extend this to schedule
31719 optimally. Return default for now. */
31722 /* Adjust the cost for the case where the value written
31723 by a fixed point operation is used as the address
31724 gen value on a store. */
31725 switch (get_attr_type (dep_insn
))
31730 if (! store_data_bypass_p (dep_insn
, insn
))
31731 return get_attr_sign_extend (dep_insn
)
31732 == SIGN_EXTEND_YES
? 6 : 4;
31737 if (! store_data_bypass_p (dep_insn
, insn
))
31738 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
31748 if (! store_data_bypass_p (dep_insn
, insn
))
31756 if (get_attr_update (dep_insn
) == UPDATE_YES
31757 && ! store_data_bypass_p (dep_insn
, insn
))
31763 if (! store_data_bypass_p (dep_insn
, insn
))
31769 if (! store_data_bypass_p (dep_insn
, insn
))
31770 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
31780 if ((rs6000_cpu
== PROCESSOR_POWER6
)
31781 && recog_memoized (dep_insn
)
31782 && (INSN_CODE (dep_insn
) >= 0))
31785 /* Adjust the cost for the case where the value written
31786 by a fixed point instruction is used within the address
31787 gen portion of a subsequent load(u)(x) */
31788 switch (get_attr_type (dep_insn
))
31793 if (set_to_load_agen (dep_insn
, insn
))
31794 return get_attr_sign_extend (dep_insn
)
31795 == SIGN_EXTEND_YES
? 6 : 4;
31800 if (set_to_load_agen (dep_insn
, insn
))
31801 return get_attr_var_shift (dep_insn
) == VAR_SHIFT_YES
?
31811 if (set_to_load_agen (dep_insn
, insn
))
31819 if (get_attr_update (dep_insn
) == UPDATE_YES
31820 && set_to_load_agen (dep_insn
, insn
))
31826 if (set_to_load_agen (dep_insn
, insn
))
31832 if (set_to_load_agen (dep_insn
, insn
))
31833 return get_attr_size (dep_insn
) == SIZE_32
? 45 : 57;
31843 if ((rs6000_cpu
== PROCESSOR_POWER6
)
31844 && get_attr_update (insn
) == UPDATE_NO
31845 && recog_memoized (dep_insn
)
31846 && (INSN_CODE (dep_insn
) >= 0)
31847 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
31854 /* Fall out to return default cost. */
31858 case REG_DEP_OUTPUT
:
31859 /* Output dependency; DEP_INSN writes a register that INSN writes some
31861 if ((rs6000_cpu
== PROCESSOR_POWER6
)
31862 && recog_memoized (dep_insn
)
31863 && (INSN_CODE (dep_insn
) >= 0))
31865 attr_type
= get_attr_type (insn
);
31870 case TYPE_FPSIMPLE
:
31871 if (get_attr_type (dep_insn
) == TYPE_FP
31872 || get_attr_type (dep_insn
) == TYPE_FPSIMPLE
)
31876 if (get_attr_update (insn
) == UPDATE_NO
31877 && get_attr_type (dep_insn
) == TYPE_MFFGPR
)
31884 /* Fall through, no cost for output dependency. */
31888 /* Anti dependency; DEP_INSN reads a register that INSN writes some
31893 gcc_unreachable ();
31899 /* Debug version of rs6000_adjust_cost. */
31902 rs6000_debug_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
,
31903 int cost
, unsigned int dw
)
31905 int ret
= rs6000_adjust_cost (insn
, dep_type
, dep_insn
, cost
, dw
);
31913 default: dep
= "unknown depencency"; break;
31914 case REG_DEP_TRUE
: dep
= "data dependency"; break;
31915 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
31916 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
31920 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
31921 "%s, insn:\n", ret
, cost
, dep
);
31929 /* The function returns a true if INSN is microcoded.
31930 Return false otherwise. */
31933 is_microcoded_insn (rtx_insn
*insn
)
31935 if (!insn
|| !NONDEBUG_INSN_P (insn
)
31936 || GET_CODE (PATTERN (insn
)) == USE
31937 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31940 if (rs6000_cpu_attr
== CPU_CELL
)
31941 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
31943 if (rs6000_sched_groups
31944 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
31946 enum attr_type type
= get_attr_type (insn
);
31947 if ((type
== TYPE_LOAD
31948 && get_attr_update (insn
) == UPDATE_YES
31949 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
)
31950 || ((type
== TYPE_LOAD
|| type
== TYPE_STORE
)
31951 && get_attr_update (insn
) == UPDATE_YES
31952 && get_attr_indexed (insn
) == INDEXED_YES
)
31953 || type
== TYPE_MFCR
)
31960 /* The function returns true if INSN is cracked into 2 instructions
31961 by the processor (and therefore occupies 2 issue slots). */
31964 is_cracked_insn (rtx_insn
*insn
)
31966 if (!insn
|| !NONDEBUG_INSN_P (insn
)
31967 || GET_CODE (PATTERN (insn
)) == USE
31968 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
31971 if (rs6000_sched_groups
31972 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
31974 enum attr_type type
= get_attr_type (insn
);
31975 if ((type
== TYPE_LOAD
31976 && get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
31977 && get_attr_update (insn
) == UPDATE_NO
)
31978 || (type
== TYPE_LOAD
31979 && get_attr_sign_extend (insn
) == SIGN_EXTEND_NO
31980 && get_attr_update (insn
) == UPDATE_YES
31981 && get_attr_indexed (insn
) == INDEXED_NO
)
31982 || (type
== TYPE_STORE
31983 && get_attr_update (insn
) == UPDATE_YES
31984 && get_attr_indexed (insn
) == INDEXED_NO
)
31985 || ((type
== TYPE_FPLOAD
|| type
== TYPE_FPSTORE
)
31986 && get_attr_update (insn
) == UPDATE_YES
)
31987 || type
== TYPE_DELAYED_CR
31988 || (type
== TYPE_EXTS
31989 && get_attr_dot (insn
) == DOT_YES
)
31990 || (type
== TYPE_SHIFT
31991 && get_attr_dot (insn
) == DOT_YES
31992 && get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
31993 || (type
== TYPE_MUL
31994 && get_attr_dot (insn
) == DOT_YES
)
31995 || type
== TYPE_DIV
31996 || (type
== TYPE_INSERT
31997 && get_attr_size (insn
) == SIZE_32
))
32004 /* The function returns true if INSN can be issued only from
32005 the branch slot. */
32008 is_branch_slot_insn (rtx_insn
*insn
)
32010 if (!insn
|| !NONDEBUG_INSN_P (insn
)
32011 || GET_CODE (PATTERN (insn
)) == USE
32012 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
32015 if (rs6000_sched_groups
)
32017 enum attr_type type
= get_attr_type (insn
);
32018 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
32026 /* The function returns true if out_inst sets a value that is
32027 used in the address generation computation of in_insn */
32029 set_to_load_agen (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
32031 rtx out_set
, in_set
;
32033 /* For performance reasons, only handle the simple case where
32034 both loads are a single_set. */
32035 out_set
= single_set (out_insn
);
32038 in_set
= single_set (in_insn
);
32040 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
32046 /* Try to determine base/offset/size parts of the given MEM.
32047 Return true if successful, false if all the values couldn't
32050 This function only looks for REG or REG+CONST address forms.
32051 REG+REG address form will return false. */
32054 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
32055 HOST_WIDE_INT
*size
)
32058 if MEM_SIZE_KNOWN_P (mem
)
32059 *size
= MEM_SIZE (mem
);
32063 addr_rtx
= (XEXP (mem
, 0));
32064 if (GET_CODE (addr_rtx
) == PRE_MODIFY
)
32065 addr_rtx
= XEXP (addr_rtx
, 1);
32068 while (GET_CODE (addr_rtx
) == PLUS
32069 && CONST_INT_P (XEXP (addr_rtx
, 1)))
32071 *offset
+= INTVAL (XEXP (addr_rtx
, 1));
32072 addr_rtx
= XEXP (addr_rtx
, 0);
32074 if (!REG_P (addr_rtx
))
32081 /* The function returns true if the target storage location of
32082 mem1 is adjacent to the target storage location of mem2 */
32083 /* Return 1 if memory locations are adjacent. */
32086 adjacent_mem_locations (rtx mem1
, rtx mem2
)
32089 HOST_WIDE_INT off1
, size1
, off2
, size2
;
32091 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
32092 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
32093 return ((REGNO (reg1
) == REGNO (reg2
))
32094 && ((off1
+ size1
== off2
)
32095 || (off2
+ size2
== off1
)));
32100 /* This function returns true if it can be determined that the two MEM
32101 locations overlap by at least 1 byte based on base reg/offset/size. */
32104 mem_locations_overlap (rtx mem1
, rtx mem2
)
32107 HOST_WIDE_INT off1
, size1
, off2
, size2
;
32109 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
32110 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
32111 return ((REGNO (reg1
) == REGNO (reg2
))
32112 && (((off1
<= off2
) && (off1
+ size1
> off2
))
32113 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
32118 /* A C statement (sans semicolon) to update the integer scheduling
32119 priority INSN_PRIORITY (INSN). Increase the priority to execute the
32120 INSN earlier, reduce the priority to execute INSN later. Do not
32121 define this macro if you do not need to adjust the scheduling
32122 priorities of insns. */
32125 rs6000_adjust_priority (rtx_insn
*insn ATTRIBUTE_UNUSED
, int priority
)
32127 rtx load_mem
, str_mem
;
32128 /* On machines (like the 750) which have asymmetric integer units,
32129 where one integer unit can do multiply and divides and the other
32130 can't, reduce the priority of multiply/divide so it is scheduled
32131 before other integer operations. */
32134 if (! INSN_P (insn
))
32137 if (GET_CODE (PATTERN (insn
)) == USE
)
32140 switch (rs6000_cpu_attr
) {
32142 switch (get_attr_type (insn
))
32149 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
32150 priority
, priority
);
32151 if (priority
>= 0 && priority
< 0x01000000)
32158 if (insn_must_be_first_in_group (insn
)
32159 && reload_completed
32160 && current_sched_info
->sched_max_insns_priority
32161 && rs6000_sched_restricted_insns_priority
)
32164 /* Prioritize insns that can be dispatched only in the first
32166 if (rs6000_sched_restricted_insns_priority
== 1)
32167 /* Attach highest priority to insn. This means that in
32168 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
32169 precede 'priority' (critical path) considerations. */
32170 return current_sched_info
->sched_max_insns_priority
;
32171 else if (rs6000_sched_restricted_insns_priority
== 2)
32172 /* Increase priority of insn by a minimal amount. This means that in
32173 haifa-sched.c:ready_sort(), only 'priority' (critical path)
32174 considerations precede dispatch-slot restriction considerations. */
32175 return (priority
+ 1);
32178 if (rs6000_cpu
== PROCESSOR_POWER6
32179 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
32180 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
32181 /* Attach highest priority to insn if the scheduler has just issued two
32182 stores and this instruction is a load, or two loads and this instruction
32183 is a store. Power6 wants loads and stores scheduled alternately
32185 return current_sched_info
->sched_max_insns_priority
;
32190 /* Return true if the instruction is nonpipelined on the Cell. */
32192 is_nonpipeline_insn (rtx_insn
*insn
)
32194 enum attr_type type
;
32195 if (!insn
|| !NONDEBUG_INSN_P (insn
)
32196 || GET_CODE (PATTERN (insn
)) == USE
32197 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
32200 type
= get_attr_type (insn
);
32201 if (type
== TYPE_MUL
32202 || type
== TYPE_DIV
32203 || type
== TYPE_SDIV
32204 || type
== TYPE_DDIV
32205 || type
== TYPE_SSQRT
32206 || type
== TYPE_DSQRT
32207 || type
== TYPE_MFCR
32208 || type
== TYPE_MFCRF
32209 || type
== TYPE_MFJMPR
)
32217 /* Return how many instructions the machine can issue per cycle. */
32220 rs6000_issue_rate (void)
32222 /* Unless scheduling for register pressure, use issue rate of 1 for
32223 first scheduling pass to decrease degradation. */
32224 if (!reload_completed
&& !flag_sched_pressure
)
32227 switch (rs6000_cpu_attr
) {
32229 case CPU_PPC601
: /* ? */
32239 case CPU_PPCE300C2
:
32240 case CPU_PPCE300C3
:
32241 case CPU_PPCE500MC
:
32242 case CPU_PPCE500MC64
:
32267 /* Return how many instructions to look ahead for better insn
32271 rs6000_use_sched_lookahead (void)
32273 switch (rs6000_cpu_attr
)
32280 return (reload_completed
? 8 : 0);
32287 /* We are choosing insn from the ready queue. Return zero if INSN can be
32290 rs6000_use_sched_lookahead_guard (rtx_insn
*insn
, int ready_index
)
32292 if (ready_index
== 0)
32295 if (rs6000_cpu_attr
!= CPU_CELL
)
32298 gcc_assert (insn
!= NULL_RTX
&& INSN_P (insn
));
32300 if (!reload_completed
32301 || is_nonpipeline_insn (insn
)
32302 || is_microcoded_insn (insn
))
32308 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
32309 and return true. */
32312 find_mem_ref (rtx pat
, rtx
*mem_ref
)
32317 /* stack_tie does not produce any real memory traffic. */
32318 if (tie_operand (pat
, VOIDmode
))
32321 if (GET_CODE (pat
) == MEM
)
32327 /* Recursively process the pattern. */
32328 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
32330 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
32334 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
32337 else if (fmt
[i
] == 'E')
32338 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
32340 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
32348 /* Determine if PAT is a PATTERN of a load insn. */
32351 is_load_insn1 (rtx pat
, rtx
*load_mem
)
32353 if (!pat
|| pat
== NULL_RTX
)
32356 if (GET_CODE (pat
) == SET
)
32357 return find_mem_ref (SET_SRC (pat
), load_mem
);
32359 if (GET_CODE (pat
) == PARALLEL
)
32363 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
32364 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
32371 /* Determine if INSN loads from memory. */
32374 is_load_insn (rtx insn
, rtx
*load_mem
)
32376 if (!insn
|| !INSN_P (insn
))
32382 return is_load_insn1 (PATTERN (insn
), load_mem
);
32385 /* Determine if PAT is a PATTERN of a store insn. */
32388 is_store_insn1 (rtx pat
, rtx
*str_mem
)
32390 if (!pat
|| pat
== NULL_RTX
)
32393 if (GET_CODE (pat
) == SET
)
32394 return find_mem_ref (SET_DEST (pat
), str_mem
);
32396 if (GET_CODE (pat
) == PARALLEL
)
32400 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
32401 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
32408 /* Determine if INSN stores to memory. */
32411 is_store_insn (rtx insn
, rtx
*str_mem
)
32413 if (!insn
|| !INSN_P (insn
))
32416 return is_store_insn1 (PATTERN (insn
), str_mem
);
32419 /* Return whether TYPE is a Power9 pairable vector instruction type. */
32422 is_power9_pairable_vec_type (enum attr_type type
)
32426 case TYPE_VECSIMPLE
:
32427 case TYPE_VECCOMPLEX
:
32431 case TYPE_VECFLOAT
:
32433 case TYPE_VECDOUBLE
:
32441 /* Returns whether the dependence between INSN and NEXT is considered
32442 costly by the given target. */
32445 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
32449 rtx load_mem
, str_mem
;
32451 /* If the flag is not enabled - no dependence is considered costly;
32452 allow all dependent insns in the same group.
32453 This is the most aggressive option. */
32454 if (rs6000_sched_costly_dep
== no_dep_costly
)
32457 /* If the flag is set to 1 - a dependence is always considered costly;
32458 do not allow dependent instructions in the same group.
32459 This is the most conservative option. */
32460 if (rs6000_sched_costly_dep
== all_deps_costly
)
32463 insn
= DEP_PRO (dep
);
32464 next
= DEP_CON (dep
);
32466 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
32467 && is_load_insn (next
, &load_mem
)
32468 && is_store_insn (insn
, &str_mem
))
32469 /* Prevent load after store in the same group. */
32472 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
32473 && is_load_insn (next
, &load_mem
)
32474 && is_store_insn (insn
, &str_mem
)
32475 && DEP_TYPE (dep
) == REG_DEP_TRUE
32476 && mem_locations_overlap(str_mem
, load_mem
))
32477 /* Prevent load after store in the same group if it is a true
32481 /* The flag is set to X; dependences with latency >= X are considered costly,
32482 and will not be scheduled in the same group. */
32483 if (rs6000_sched_costly_dep
<= max_dep_latency
32484 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
32490 /* Return the next insn after INSN that is found before TAIL is reached,
32491 skipping any "non-active" insns - insns that will not actually occupy
32492 an issue slot. Return NULL_RTX if such an insn is not found. */
32495 get_next_active_insn (rtx_insn
*insn
, rtx_insn
*tail
)
32497 if (insn
== NULL_RTX
|| insn
== tail
)
32502 insn
= NEXT_INSN (insn
);
32503 if (insn
== NULL_RTX
|| insn
== tail
)
32507 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
32508 || (NONJUMP_INSN_P (insn
)
32509 && GET_CODE (PATTERN (insn
)) != USE
32510 && GET_CODE (PATTERN (insn
)) != CLOBBER
32511 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
32517 /* Do Power9 specific sched_reorder2 reordering of ready list. */
32520 power9_sched_reorder2 (rtx_insn
**ready
, int lastpos
)
32525 enum attr_type type
;
32527 type
= get_attr_type (last_scheduled_insn
);
32529 /* Try to issue fixed point divides back-to-back in pairs so they will be
32530 routed to separate execution units and execute in parallel. */
32531 if (type
== TYPE_DIV
&& divide_cnt
== 0)
32533 /* First divide has been scheduled. */
32536 /* Scan the ready list looking for another divide, if found move it
32537 to the end of the list so it is chosen next. */
32541 if (recog_memoized (ready
[pos
]) >= 0
32542 && get_attr_type (ready
[pos
]) == TYPE_DIV
)
32545 for (i
= pos
; i
< lastpos
; i
++)
32546 ready
[i
] = ready
[i
+ 1];
32547 ready
[lastpos
] = tmp
;
32555 /* Last insn was the 2nd divide or not a divide, reset the counter. */
32558 /* Power9 can execute 2 vector operations and 2 vector loads in a single
32559 cycle. So try to pair up and alternate groups of vector and vector
32562 To aid this formation, a counter is maintained to keep track of
32563 vec/vecload insns issued. The value of vec_load_pendulum maintains
32564 the current state with the following values:
32566 0 : Initial state, no vec/vecload group has been started.
32568 -1 : 1 vector load has been issued and another has been found on
32569 the ready list and moved to the end.
32571 -2 : 2 vector loads have been issued and a vector operation has
32572 been found and moved to the end of the ready list.
32574 -3 : 2 vector loads and a vector insn have been issued and a
32575 vector operation has been found and moved to the end of the
32578 1 : 1 vector insn has been issued and another has been found and
32579 moved to the end of the ready list.
32581 2 : 2 vector insns have been issued and a vector load has been
32582 found and moved to the end of the ready list.
32584 3 : 2 vector insns and a vector load have been issued and another
32585 vector load has been found and moved to the end of the ready
32587 if (type
== TYPE_VECLOAD
)
32589 /* Issued a vecload. */
32590 if (vec_load_pendulum
== 0)
32592 /* We issued a single vecload, look for another and move it to
32593 the end of the ready list so it will be scheduled next.
32594 Set pendulum if found. */
32598 if (recog_memoized (ready
[pos
]) >= 0
32599 && get_attr_type (ready
[pos
]) == TYPE_VECLOAD
)
32602 for (i
= pos
; i
< lastpos
; i
++)
32603 ready
[i
] = ready
[i
+ 1];
32604 ready
[lastpos
] = tmp
;
32605 vec_load_pendulum
= -1;
32606 return cached_can_issue_more
;
32611 else if (vec_load_pendulum
== -1)
32613 /* This is the second vecload we've issued, search the ready
32614 list for a vector operation so we can try to schedule a
32615 pair of those next. If found move to the end of the ready
32616 list so it is scheduled next and set the pendulum. */
32620 if (recog_memoized (ready
[pos
]) >= 0
32621 && is_power9_pairable_vec_type (
32622 get_attr_type (ready
[pos
])))
32625 for (i
= pos
; i
< lastpos
; i
++)
32626 ready
[i
] = ready
[i
+ 1];
32627 ready
[lastpos
] = tmp
;
32628 vec_load_pendulum
= -2;
32629 return cached_can_issue_more
;
32634 else if (vec_load_pendulum
== 2)
32636 /* Two vector ops have been issued and we've just issued a
32637 vecload, look for another vecload and move to end of ready
32642 if (recog_memoized (ready
[pos
]) >= 0
32643 && get_attr_type (ready
[pos
]) == TYPE_VECLOAD
)
32646 for (i
= pos
; i
< lastpos
; i
++)
32647 ready
[i
] = ready
[i
+ 1];
32648 ready
[lastpos
] = tmp
;
32649 /* Set pendulum so that next vecload will be seen as
32650 finishing a group, not start of one. */
32651 vec_load_pendulum
= 3;
32652 return cached_can_issue_more
;
32658 else if (is_power9_pairable_vec_type (type
))
32660 /* Issued a vector operation. */
32661 if (vec_load_pendulum
== 0)
32662 /* We issued a single vec op, look for another and move it
32663 to the end of the ready list so it will be scheduled next.
32664 Set pendulum if found. */
32669 if (recog_memoized (ready
[pos
]) >= 0
32670 && is_power9_pairable_vec_type (
32671 get_attr_type (ready
[pos
])))
32674 for (i
= pos
; i
< lastpos
; i
++)
32675 ready
[i
] = ready
[i
+ 1];
32676 ready
[lastpos
] = tmp
;
32677 vec_load_pendulum
= 1;
32678 return cached_can_issue_more
;
32683 else if (vec_load_pendulum
== 1)
32685 /* This is the second vec op we've issued, search the ready
32686 list for a vecload operation so we can try to schedule a
32687 pair of those next. If found move to the end of the ready
32688 list so it is scheduled next and set the pendulum. */
32692 if (recog_memoized (ready
[pos
]) >= 0
32693 && get_attr_type (ready
[pos
]) == TYPE_VECLOAD
)
32696 for (i
= pos
; i
< lastpos
; i
++)
32697 ready
[i
] = ready
[i
+ 1];
32698 ready
[lastpos
] = tmp
;
32699 vec_load_pendulum
= 2;
32700 return cached_can_issue_more
;
32705 else if (vec_load_pendulum
== -2)
32707 /* Two vecload ops have been issued and we've just issued a
32708 vec op, look for another vec op and move to end of ready
32713 if (recog_memoized (ready
[pos
]) >= 0
32714 && is_power9_pairable_vec_type (
32715 get_attr_type (ready
[pos
])))
32718 for (i
= pos
; i
< lastpos
; i
++)
32719 ready
[i
] = ready
[i
+ 1];
32720 ready
[lastpos
] = tmp
;
32721 /* Set pendulum so that next vec op will be seen as
32722 finishing a group, not start of one. */
32723 vec_load_pendulum
= -3;
32724 return cached_can_issue_more
;
32731 /* We've either finished a vec/vecload group, couldn't find an insn to
32732 continue the current group, or the last insn had nothing to do with
32733 with a group. In any case, reset the pendulum. */
32734 vec_load_pendulum
= 0;
32737 return cached_can_issue_more
;
32740 /* We are about to begin issuing insns for this clock cycle. */
32743 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
32744 rtx_insn
**ready ATTRIBUTE_UNUSED
,
32745 int *pn_ready ATTRIBUTE_UNUSED
,
32746 int clock_var ATTRIBUTE_UNUSED
)
32748 int n_ready
= *pn_ready
;
32751 fprintf (dump
, "// rs6000_sched_reorder :\n");
32753 /* Reorder the ready list, if the second to last ready insn
32754 is a nonepipeline insn. */
32755 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
32757 if (is_nonpipeline_insn (ready
[n_ready
- 1])
32758 && (recog_memoized (ready
[n_ready
- 2]) > 0))
32759 /* Simply swap first two insns. */
32760 std::swap (ready
[n_ready
- 1], ready
[n_ready
- 2]);
32763 if (rs6000_cpu
== PROCESSOR_POWER6
)
32764 load_store_pendulum
= 0;
32766 return rs6000_issue_rate ();
32769 /* Like rs6000_sched_reorder, but called after issuing each insn. */
32772 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx_insn
**ready
,
32773 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
32776 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
32778 /* For Power6, we need to handle some special cases to try and keep the
32779 store queue from overflowing and triggering expensive flushes.
32781 This code monitors how load and store instructions are being issued
32782 and skews the ready list one way or the other to increase the likelihood
32783 that a desired instruction is issued at the proper time.
32785 A couple of things are done. First, we maintain a "load_store_pendulum"
32786 to track the current state of load/store issue.
32788 - If the pendulum is at zero, then no loads or stores have been
32789 issued in the current cycle so we do nothing.
32791 - If the pendulum is 1, then a single load has been issued in this
32792 cycle and we attempt to locate another load in the ready list to
32795 - If the pendulum is -2, then two stores have already been
32796 issued in this cycle, so we increase the priority of the first load
32797 in the ready list to increase it's likelihood of being chosen first
32800 - If the pendulum is -1, then a single store has been issued in this
32801 cycle and we attempt to locate another store in the ready list to
32802 issue with it, preferring a store to an adjacent memory location to
32803 facilitate store pairing in the store queue.
32805 - If the pendulum is 2, then two loads have already been
32806 issued in this cycle, so we increase the priority of the first store
32807 in the ready list to increase it's likelihood of being chosen first
32810 - If the pendulum < -2 or > 2, then do nothing.
32812 Note: This code covers the most common scenarios. There exist non
32813 load/store instructions which make use of the LSU and which
32814 would need to be accounted for to strictly model the behavior
32815 of the machine. Those instructions are currently unaccounted
32816 for to help minimize compile time overhead of this code.
32818 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
32823 rtx load_mem
, str_mem
;
32825 if (is_store_insn (last_scheduled_insn
, &str_mem
))
32826 /* Issuing a store, swing the load_store_pendulum to the left */
32827 load_store_pendulum
--;
32828 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
32829 /* Issuing a load, swing the load_store_pendulum to the right */
32830 load_store_pendulum
++;
32832 return cached_can_issue_more
;
32834 /* If the pendulum is balanced, or there is only one instruction on
32835 the ready list, then all is well, so return. */
32836 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
32837 return cached_can_issue_more
;
32839 if (load_store_pendulum
== 1)
32841 /* A load has been issued in this cycle. Scan the ready list
32842 for another load to issue with it */
32847 if (is_load_insn (ready
[pos
], &load_mem
))
32849 /* Found a load. Move it to the head of the ready list,
32850 and adjust it's priority so that it is more likely to
32853 for (i
=pos
; i
<*pn_ready
-1; i
++)
32854 ready
[i
] = ready
[i
+ 1];
32855 ready
[*pn_ready
-1] = tmp
;
32857 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
32858 INSN_PRIORITY (tmp
)++;
32864 else if (load_store_pendulum
== -2)
32866 /* Two stores have been issued in this cycle. Increase the
32867 priority of the first load in the ready list to favor it for
32868 issuing in the next cycle. */
32873 if (is_load_insn (ready
[pos
], &load_mem
)
32875 && INSN_PRIORITY_KNOWN (ready
[pos
]))
32877 INSN_PRIORITY (ready
[pos
])++;
32879 /* Adjust the pendulum to account for the fact that a load
32880 was found and increased in priority. This is to prevent
32881 increasing the priority of multiple loads */
32882 load_store_pendulum
--;
32889 else if (load_store_pendulum
== -1)
32891 /* A store has been issued in this cycle. Scan the ready list for
32892 another store to issue with it, preferring a store to an adjacent
32894 int first_store_pos
= -1;
32900 if (is_store_insn (ready
[pos
], &str_mem
))
32903 /* Maintain the index of the first store found on the
32905 if (first_store_pos
== -1)
32906 first_store_pos
= pos
;
32908 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
32909 && adjacent_mem_locations (str_mem
, str_mem2
))
32911 /* Found an adjacent store. Move it to the head of the
32912 ready list, and adjust it's priority so that it is
32913 more likely to stay there */
32915 for (i
=pos
; i
<*pn_ready
-1; i
++)
32916 ready
[i
] = ready
[i
+ 1];
32917 ready
[*pn_ready
-1] = tmp
;
32919 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
32920 INSN_PRIORITY (tmp
)++;
32922 first_store_pos
= -1;
32930 if (first_store_pos
>= 0)
32932 /* An adjacent store wasn't found, but a non-adjacent store was,
32933 so move the non-adjacent store to the front of the ready
32934 list, and adjust its priority so that it is more likely to
32936 tmp
= ready
[first_store_pos
];
32937 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
32938 ready
[i
] = ready
[i
+ 1];
32939 ready
[*pn_ready
-1] = tmp
;
32940 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
32941 INSN_PRIORITY (tmp
)++;
32944 else if (load_store_pendulum
== 2)
32946 /* Two loads have been issued in this cycle. Increase the priority
32947 of the first store in the ready list to favor it for issuing in
32953 if (is_store_insn (ready
[pos
], &str_mem
)
32955 && INSN_PRIORITY_KNOWN (ready
[pos
]))
32957 INSN_PRIORITY (ready
[pos
])++;
32959 /* Adjust the pendulum to account for the fact that a store
32960 was found and increased in priority. This is to prevent
32961 increasing the priority of multiple stores */
32962 load_store_pendulum
++;
32971 /* Do Power9 dependent reordering if necessary. */
32972 if (rs6000_cpu
== PROCESSOR_POWER9
&& last_scheduled_insn
32973 && recog_memoized (last_scheduled_insn
) >= 0)
32974 return power9_sched_reorder2 (ready
, *pn_ready
- 1);
32976 return cached_can_issue_more
;
32979 /* Return whether the presence of INSN causes a dispatch group termination
32980 of group WHICH_GROUP.
32982 If WHICH_GROUP == current_group, this function will return true if INSN
32983 causes the termination of the current group (i.e, the dispatch group to
32984 which INSN belongs). This means that INSN will be the last insn in the
32985 group it belongs to.
32987 If WHICH_GROUP == previous_group, this function will return true if INSN
32988 causes the termination of the previous group (i.e, the dispatch group that
32989 precedes the group to which INSN belongs). This means that INSN will be
32990 the first insn in the group it belongs to). */
32993 insn_terminates_group_p (rtx_insn
*insn
, enum group_termination which_group
)
33000 first
= insn_must_be_first_in_group (insn
);
33001 last
= insn_must_be_last_in_group (insn
);
33006 if (which_group
== current_group
)
33008 else if (which_group
== previous_group
)
33016 insn_must_be_first_in_group (rtx_insn
*insn
)
33018 enum attr_type type
;
33022 || DEBUG_INSN_P (insn
)
33023 || GET_CODE (PATTERN (insn
)) == USE
33024 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
33027 switch (rs6000_cpu
)
33029 case PROCESSOR_POWER5
:
33030 if (is_cracked_insn (insn
))
33033 case PROCESSOR_POWER4
:
33034 if (is_microcoded_insn (insn
))
33037 if (!rs6000_sched_groups
)
33040 type
= get_attr_type (insn
);
33047 case TYPE_DELAYED_CR
:
33048 case TYPE_CR_LOGICAL
:
33061 case PROCESSOR_POWER6
:
33062 type
= get_attr_type (insn
);
33071 case TYPE_FPCOMPARE
:
33082 if (get_attr_dot (insn
) == DOT_NO
33083 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
33088 if (get_attr_size (insn
) == SIZE_32
)
33096 if (get_attr_update (insn
) == UPDATE_YES
)
33104 case PROCESSOR_POWER7
:
33105 type
= get_attr_type (insn
);
33109 case TYPE_CR_LOGICAL
:
33123 if (get_attr_dot (insn
) == DOT_YES
)
33128 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
33129 || get_attr_update (insn
) == UPDATE_YES
)
33136 if (get_attr_update (insn
) == UPDATE_YES
)
33144 case PROCESSOR_POWER8
:
33145 type
= get_attr_type (insn
);
33149 case TYPE_CR_LOGICAL
:
33150 case TYPE_DELAYED_CR
:
33158 case TYPE_VECSTORE
:
33165 if (get_attr_dot (insn
) == DOT_YES
)
33170 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
33171 || get_attr_update (insn
) == UPDATE_YES
)
33176 if (get_attr_update (insn
) == UPDATE_YES
33177 && get_attr_indexed (insn
) == INDEXED_YES
)
33193 insn_must_be_last_in_group (rtx_insn
*insn
)
33195 enum attr_type type
;
33199 || DEBUG_INSN_P (insn
)
33200 || GET_CODE (PATTERN (insn
)) == USE
33201 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
33204 switch (rs6000_cpu
) {
33205 case PROCESSOR_POWER4
:
33206 case PROCESSOR_POWER5
:
33207 if (is_microcoded_insn (insn
))
33210 if (is_branch_slot_insn (insn
))
33214 case PROCESSOR_POWER6
:
33215 type
= get_attr_type (insn
);
33223 case TYPE_FPCOMPARE
:
33234 if (get_attr_dot (insn
) == DOT_NO
33235 || get_attr_var_shift (insn
) == VAR_SHIFT_NO
)
33240 if (get_attr_size (insn
) == SIZE_32
)
33248 case PROCESSOR_POWER7
:
33249 type
= get_attr_type (insn
);
33259 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
33260 && get_attr_update (insn
) == UPDATE_YES
)
33265 if (get_attr_update (insn
) == UPDATE_YES
33266 && get_attr_indexed (insn
) == INDEXED_YES
)
33274 case PROCESSOR_POWER8
:
33275 type
= get_attr_type (insn
);
33287 if (get_attr_sign_extend (insn
) == SIGN_EXTEND_YES
33288 && get_attr_update (insn
) == UPDATE_YES
)
33293 if (get_attr_update (insn
) == UPDATE_YES
33294 && get_attr_indexed (insn
) == INDEXED_YES
)
33309 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
33310 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
33313 is_costly_group (rtx
*group_insns
, rtx next_insn
)
33316 int issue_rate
= rs6000_issue_rate ();
33318 for (i
= 0; i
< issue_rate
; i
++)
33320 sd_iterator_def sd_it
;
33322 rtx insn
= group_insns
[i
];
33327 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
33329 rtx next
= DEP_CON (dep
);
33331 if (next
== next_insn
33332 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
33340 /* Utility of the function redefine_groups.
33341 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
33342 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
33343 to keep it "far" (in a separate group) from GROUP_INSNS, following
33344 one of the following schemes, depending on the value of the flag
33345 -minsert_sched_nops = X:
33346 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
33347 in order to force NEXT_INSN into a separate group.
33348 (2) X < sched_finish_regroup_exact: insert exactly X nops.
33349 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
33350 insertion (has a group just ended, how many vacant issue slots remain in the
33351 last group, and how many dispatch groups were encountered so far). */
33354 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
33355 rtx_insn
*next_insn
, bool *group_end
, int can_issue_more
,
33360 int issue_rate
= rs6000_issue_rate ();
33361 bool end
= *group_end
;
33364 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
33365 return can_issue_more
;
33367 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
33368 return can_issue_more
;
33370 force
= is_costly_group (group_insns
, next_insn
);
33372 return can_issue_more
;
33374 if (sched_verbose
> 6)
33375 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
33376 *group_count
,can_issue_more
);
33378 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
33381 can_issue_more
= 0;
33383 /* Since only a branch can be issued in the last issue_slot, it is
33384 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
33385 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
33386 in this case the last nop will start a new group and the branch
33387 will be forced to the new group. */
33388 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
33391 /* Do we have a special group ending nop? */
33392 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
33393 || rs6000_cpu_attr
== CPU_POWER8
)
33395 nop
= gen_group_ending_nop ();
33396 emit_insn_before (nop
, next_insn
);
33397 can_issue_more
= 0;
33400 while (can_issue_more
> 0)
33403 emit_insn_before (nop
, next_insn
);
33411 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
33413 int n_nops
= rs6000_sched_insert_nops
;
33415 /* Nops can't be issued from the branch slot, so the effective
33416 issue_rate for nops is 'issue_rate - 1'. */
33417 if (can_issue_more
== 0)
33418 can_issue_more
= issue_rate
;
33420 if (can_issue_more
== 0)
33422 can_issue_more
= issue_rate
- 1;
33425 for (i
= 0; i
< issue_rate
; i
++)
33427 group_insns
[i
] = 0;
33434 emit_insn_before (nop
, next_insn
);
33435 if (can_issue_more
== issue_rate
- 1) /* new group begins */
33438 if (can_issue_more
== 0)
33440 can_issue_more
= issue_rate
- 1;
33443 for (i
= 0; i
< issue_rate
; i
++)
33445 group_insns
[i
] = 0;
33451 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
33454 /* Is next_insn going to start a new group? */
33457 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
33458 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
33459 || (can_issue_more
< issue_rate
&&
33460 insn_terminates_group_p (next_insn
, previous_group
)));
33461 if (*group_end
&& end
)
33464 if (sched_verbose
> 6)
33465 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
33466 *group_count
, can_issue_more
);
33467 return can_issue_more
;
33470 return can_issue_more
;
33473 /* This function tries to synch the dispatch groups that the compiler "sees"
33474 with the dispatch groups that the processor dispatcher is expected to
33475 form in practice. It tries to achieve this synchronization by forcing the
33476 estimated processor grouping on the compiler (as opposed to the function
33477 'pad_goups' which tries to force the scheduler's grouping on the processor).
33479 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
33480 examines the (estimated) dispatch groups that will be formed by the processor
33481 dispatcher. It marks these group boundaries to reflect the estimated
33482 processor grouping, overriding the grouping that the scheduler had marked.
33483 Depending on the value of the flag '-minsert-sched-nops' this function can
33484 force certain insns into separate groups or force a certain distance between
33485 them by inserting nops, for example, if there exists a "costly dependence"
33488 The function estimates the group boundaries that the processor will form as
33489 follows: It keeps track of how many vacant issue slots are available after
33490 each insn. A subsequent insn will start a new group if one of the following
33492 - no more vacant issue slots remain in the current dispatch group.
33493 - only the last issue slot, which is the branch slot, is vacant, but the next
33494 insn is not a branch.
33495 - only the last 2 or less issue slots, including the branch slot, are vacant,
33496 which means that a cracked insn (which occupies two issue slots) can't be
33497 issued in this group.
33498 - less than 'issue_rate' slots are vacant, and the next insn always needs to
33499 start a new group. */
33502 redefine_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
33505 rtx_insn
*insn
, *next_insn
;
33507 int can_issue_more
;
33510 int group_count
= 0;
33514 issue_rate
= rs6000_issue_rate ();
33515 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
33516 for (i
= 0; i
< issue_rate
; i
++)
33518 group_insns
[i
] = 0;
33520 can_issue_more
= issue_rate
;
33522 insn
= get_next_active_insn (prev_head_insn
, tail
);
33525 while (insn
!= NULL_RTX
)
33527 slot
= (issue_rate
- can_issue_more
);
33528 group_insns
[slot
] = insn
;
33530 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
33531 if (insn_terminates_group_p (insn
, current_group
))
33532 can_issue_more
= 0;
33534 next_insn
= get_next_active_insn (insn
, tail
);
33535 if (next_insn
== NULL_RTX
)
33536 return group_count
+ 1;
33538 /* Is next_insn going to start a new group? */
33540 = (can_issue_more
== 0
33541 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
33542 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
33543 || (can_issue_more
< issue_rate
&&
33544 insn_terminates_group_p (next_insn
, previous_group
)));
33546 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
33547 next_insn
, &group_end
, can_issue_more
,
33553 can_issue_more
= 0;
33554 for (i
= 0; i
< issue_rate
; i
++)
33556 group_insns
[i
] = 0;
33560 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
33561 PUT_MODE (next_insn
, VOIDmode
);
33562 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
33563 PUT_MODE (next_insn
, TImode
);
33566 if (can_issue_more
== 0)
33567 can_issue_more
= issue_rate
;
33570 return group_count
;
33573 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
33574 dispatch group boundaries that the scheduler had marked. Pad with nops
33575 any dispatch groups which have vacant issue slots, in order to force the
33576 scheduler's grouping on the processor dispatcher. The function
33577 returns the number of dispatch groups found. */
33580 pad_groups (FILE *dump
, int sched_verbose
, rtx_insn
*prev_head_insn
,
33583 rtx_insn
*insn
, *next_insn
;
33586 int can_issue_more
;
33588 int group_count
= 0;
33590 /* Initialize issue_rate. */
33591 issue_rate
= rs6000_issue_rate ();
33592 can_issue_more
= issue_rate
;
33594 insn
= get_next_active_insn (prev_head_insn
, tail
);
33595 next_insn
= get_next_active_insn (insn
, tail
);
33597 while (insn
!= NULL_RTX
)
33600 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
33602 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
33604 if (next_insn
== NULL_RTX
)
33609 /* If the scheduler had marked group termination at this location
33610 (between insn and next_insn), and neither insn nor next_insn will
33611 force group termination, pad the group with nops to force group
33614 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
33615 && !insn_terminates_group_p (insn
, current_group
)
33616 && !insn_terminates_group_p (next_insn
, previous_group
))
33618 if (!is_branch_slot_insn (next_insn
))
33621 while (can_issue_more
)
33624 emit_insn_before (nop
, next_insn
);
33629 can_issue_more
= issue_rate
;
33634 next_insn
= get_next_active_insn (insn
, tail
);
33637 return group_count
;
33640 /* We're beginning a new block. Initialize data structures as necessary. */
33643 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
33644 int sched_verbose ATTRIBUTE_UNUSED
,
33645 int max_ready ATTRIBUTE_UNUSED
)
33647 last_scheduled_insn
= NULL
;
33648 load_store_pendulum
= 0;
33650 vec_load_pendulum
= 0;
33653 /* The following function is called at the end of scheduling BB.
33654 After reload, it inserts nops at insn group bundling. */
33657 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
33662 fprintf (dump
, "=== Finishing schedule.\n");
33664 if (reload_completed
&& rs6000_sched_groups
)
33666 /* Do not run sched_finish hook when selective scheduling enabled. */
33667 if (sel_sched_p ())
33670 if (rs6000_sched_insert_nops
== sched_finish_none
)
33673 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
33674 n_groups
= pad_groups (dump
, sched_verbose
,
33675 current_sched_info
->prev_head
,
33676 current_sched_info
->next_tail
);
33678 n_groups
= redefine_groups (dump
, sched_verbose
,
33679 current_sched_info
->prev_head
,
33680 current_sched_info
->next_tail
);
33682 if (sched_verbose
>= 6)
33684 fprintf (dump
, "ngroups = %d\n", n_groups
);
33685 print_rtl (dump
, current_sched_info
->prev_head
);
33686 fprintf (dump
, "Done finish_sched\n");
33691 struct rs6000_sched_context
33693 short cached_can_issue_more
;
33694 rtx_insn
*last_scheduled_insn
;
33695 int load_store_pendulum
;
33697 int vec_load_pendulum
;
33700 typedef struct rs6000_sched_context rs6000_sched_context_def
;
33701 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
33703 /* Allocate store for new scheduling context. */
33705 rs6000_alloc_sched_context (void)
33707 return xmalloc (sizeof (rs6000_sched_context_def
));
33710 /* If CLEAN_P is true then initializes _SC with clean data,
33711 and from the global context otherwise. */
33713 rs6000_init_sched_context (void *_sc
, bool clean_p
)
33715 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
33719 sc
->cached_can_issue_more
= 0;
33720 sc
->last_scheduled_insn
= NULL
;
33721 sc
->load_store_pendulum
= 0;
33722 sc
->divide_cnt
= 0;
33723 sc
->vec_load_pendulum
= 0;
33727 sc
->cached_can_issue_more
= cached_can_issue_more
;
33728 sc
->last_scheduled_insn
= last_scheduled_insn
;
33729 sc
->load_store_pendulum
= load_store_pendulum
;
33730 sc
->divide_cnt
= divide_cnt
;
33731 sc
->vec_load_pendulum
= vec_load_pendulum
;
33735 /* Sets the global scheduling context to the one pointed to by _SC. */
33737 rs6000_set_sched_context (void *_sc
)
33739 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
33741 gcc_assert (sc
!= NULL
);
33743 cached_can_issue_more
= sc
->cached_can_issue_more
;
33744 last_scheduled_insn
= sc
->last_scheduled_insn
;
33745 load_store_pendulum
= sc
->load_store_pendulum
;
33746 divide_cnt
= sc
->divide_cnt
;
33747 vec_load_pendulum
= sc
->vec_load_pendulum
;
33752 rs6000_free_sched_context (void *_sc
)
33754 gcc_assert (_sc
!= NULL
);
33760 /* Length in units of the trampoline for entering a nested function. */
33763 rs6000_trampoline_size (void)
33767 switch (DEFAULT_ABI
)
33770 gcc_unreachable ();
33773 ret
= (TARGET_32BIT
) ? 12 : 24;
33777 gcc_assert (!TARGET_32BIT
);
33783 ret
= (TARGET_32BIT
) ? 40 : 48;
33790 /* Emit RTL insns to initialize the variable parts of a trampoline.
33791 FNADDR is an RTX for the address of the function's pure code.
33792 CXT is an RTX for the static chain value for the function. */
33795 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
33797 int regsize
= (TARGET_32BIT
) ? 4 : 8;
33798 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
33799 rtx ctx_reg
= force_reg (Pmode
, cxt
);
33800 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
33802 switch (DEFAULT_ABI
)
33805 gcc_unreachable ();
33807 /* Under AIX, just build the 3 word function descriptor */
33810 rtx fnmem
, fn_reg
, toc_reg
;
33812 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
33813 error ("You cannot take the address of a nested function if you use "
33814 "the -mno-pointers-to-nested-functions option.");
33816 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
33817 fn_reg
= gen_reg_rtx (Pmode
);
33818 toc_reg
= gen_reg_rtx (Pmode
);
33820 /* Macro to shorten the code expansions below. */
33821 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
33823 m_tramp
= replace_equiv_address (m_tramp
, addr
);
33825 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
33826 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
33827 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
33828 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
33829 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
33835 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
33839 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
33840 LCT_NORMAL
, VOIDmode
, 4,
33842 GEN_INT (rs6000_trampoline_size ()), SImode
,
33850 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
33851 identifier as an argument, so the front end shouldn't look it up. */
33854 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
33856 return is_attribute_p ("altivec", attr_id
);
33859 /* Handle the "altivec" attribute. The attribute may have
33860 arguments as follows:
33862 __attribute__((altivec(vector__)))
33863 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
33864 __attribute__((altivec(bool__))) (always followed by 'unsigned')
33866 and may appear more than once (e.g., 'vector bool char') in a
33867 given declaration. */
33870 rs6000_handle_altivec_attribute (tree
*node
,
33871 tree name ATTRIBUTE_UNUSED
,
33873 int flags ATTRIBUTE_UNUSED
,
33874 bool *no_add_attrs
)
33876 tree type
= *node
, result
= NULL_TREE
;
33880 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
33881 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
33882 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
33885 while (POINTER_TYPE_P (type
)
33886 || TREE_CODE (type
) == FUNCTION_TYPE
33887 || TREE_CODE (type
) == METHOD_TYPE
33888 || TREE_CODE (type
) == ARRAY_TYPE
)
33889 type
= TREE_TYPE (type
);
33891 mode
= TYPE_MODE (type
);
33893 /* Check for invalid AltiVec type qualifiers. */
33894 if (type
== long_double_type_node
)
33895 error ("use of %<long double%> in AltiVec types is invalid");
33896 else if (type
== boolean_type_node
)
33897 error ("use of boolean types in AltiVec types is invalid");
33898 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
33899 error ("use of %<complex%> in AltiVec types is invalid");
33900 else if (DECIMAL_FLOAT_MODE_P (mode
))
33901 error ("use of decimal floating point types in AltiVec types is invalid");
33902 else if (!TARGET_VSX
)
33904 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
33907 error ("use of %<long%> in AltiVec types is invalid for "
33908 "64-bit code without -mvsx");
33909 else if (rs6000_warn_altivec_long
)
33910 warning (0, "use of %<long%> in AltiVec types is deprecated; "
33913 else if (type
== long_long_unsigned_type_node
33914 || type
== long_long_integer_type_node
)
33915 error ("use of %<long long%> in AltiVec types is invalid without "
33917 else if (type
== double_type_node
)
33918 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
33921 switch (altivec_type
)
33924 unsigned_p
= TYPE_UNSIGNED (type
);
33928 result
= (unsigned_p
? unsigned_V1TI_type_node
: V1TI_type_node
);
33931 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
33934 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
33937 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
33940 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
33942 case SFmode
: result
= V4SF_type_node
; break;
33943 case DFmode
: result
= V2DF_type_node
; break;
33944 /* If the user says 'vector int bool', we may be handed the 'bool'
33945 attribute _before_ the 'vector' attribute, and so select the
33946 proper type in the 'b' case below. */
33947 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
33948 case V2DImode
: case V2DFmode
:
33956 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
33957 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
33958 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
33959 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
33966 case V8HImode
: result
= pixel_V8HI_type_node
;
33972 /* Propagate qualifiers attached to the element type
33973 onto the vector type. */
33974 if (result
&& result
!= type
&& TYPE_QUALS (type
))
33975 result
= build_qualified_type (result
, TYPE_QUALS (type
));
33977 *no_add_attrs
= true; /* No need to hang on to the attribute. */
33980 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
33985 /* AltiVec defines four built-in scalar types that serve as vector
33986 elements; we must teach the compiler how to mangle them. */
33988 static const char *
33989 rs6000_mangle_type (const_tree type
)
33991 type
= TYPE_MAIN_VARIANT (type
);
33993 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
33994 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
33997 if (type
== bool_char_type_node
) return "U6__boolc";
33998 if (type
== bool_short_type_node
) return "U6__bools";
33999 if (type
== pixel_type_node
) return "u7__pixel";
34000 if (type
== bool_int_type_node
) return "U6__booli";
34001 if (type
== bool_long_type_node
) return "U6__booll";
34003 /* Use a unique name for __float128 rather than trying to use "e" or "g". Use
34004 "g" for IBM extended double, no matter whether it is long double (using
34005 -mabi=ibmlongdouble) or the distinct __ibm128 type. */
34006 if (TARGET_FLOAT128_TYPE
)
34008 if (type
== ieee128_float_type_node
)
34009 return "U10__float128";
34011 if (type
== ibm128_float_type_node
)
34014 if (type
== long_double_type_node
&& TARGET_LONG_DOUBLE_128
)
34015 return (TARGET_IEEEQUAD
) ? "U10__float128" : "g";
34018 /* Mangle IBM extended float long double as `g' (__float128) on
34019 powerpc*-linux where long-double-64 previously was the default. */
34020 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
34022 && TARGET_LONG_DOUBLE_128
34023 && !TARGET_IEEEQUAD
)
34026 /* For all other types, use normal C++ mangling. */
34030 /* Handle a "longcall" or "shortcall" attribute; arguments as in
34031 struct attribute_spec.handler. */
34034 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
34035 tree args ATTRIBUTE_UNUSED
,
34036 int flags ATTRIBUTE_UNUSED
,
34037 bool *no_add_attrs
)
34039 if (TREE_CODE (*node
) != FUNCTION_TYPE
34040 && TREE_CODE (*node
) != FIELD_DECL
34041 && TREE_CODE (*node
) != TYPE_DECL
)
34043 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
34045 *no_add_attrs
= true;
34051 /* Set longcall attributes on all functions declared when
34052 rs6000_default_long_calls is true. */
34054 rs6000_set_default_type_attributes (tree type
)
34056 if (rs6000_default_long_calls
34057 && (TREE_CODE (type
) == FUNCTION_TYPE
34058 || TREE_CODE (type
) == METHOD_TYPE
))
34059 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
34061 TYPE_ATTRIBUTES (type
));
34064 darwin_set_default_type_attributes (type
);
34068 /* Return a reference suitable for calling a function with the
34069 longcall attribute. */
34072 rs6000_longcall_ref (rtx call_ref
)
34074 const char *call_name
;
34077 if (GET_CODE (call_ref
) != SYMBOL_REF
)
34080 /* System V adds '.' to the internal name, so skip them. */
34081 call_name
= XSTR (call_ref
, 0);
34082 if (*call_name
== '.')
34084 while (*call_name
== '.')
34087 node
= get_identifier (call_name
);
34088 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
34091 return force_reg (Pmode
, call_ref
);
34094 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
34095 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
34098 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34099 struct attribute_spec.handler. */
34101 rs6000_handle_struct_attribute (tree
*node
, tree name
,
34102 tree args ATTRIBUTE_UNUSED
,
34103 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
34106 if (DECL_P (*node
))
34108 if (TREE_CODE (*node
) == TYPE_DECL
)
34109 type
= &TREE_TYPE (*node
);
34114 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
34115 || TREE_CODE (*type
) == UNION_TYPE
)))
34117 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
34118 *no_add_attrs
= true;
34121 else if ((is_attribute_p ("ms_struct", name
)
34122 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
34123 || ((is_attribute_p ("gcc_struct", name
)
34124 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
34126 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
34128 *no_add_attrs
= true;
34135 rs6000_ms_bitfield_layout_p (const_tree record_type
)
34137 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
34138 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
34139 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
34142 #ifdef USING_ELFOS_H
34144 /* A get_unnamed_section callback, used for switching to toc_section. */
34147 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
34149 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
34150 && TARGET_MINIMAL_TOC
)
34152 if (!toc_initialized
)
34154 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
34155 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
34156 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
34157 fprintf (asm_out_file
, "\t.tc ");
34158 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
34159 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
34160 fprintf (asm_out_file
, "\n");
34162 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
34163 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
34164 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
34165 fprintf (asm_out_file
, " = .+32768\n");
34166 toc_initialized
= 1;
34169 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
34171 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
34173 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
34174 if (!toc_initialized
)
34176 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
34177 toc_initialized
= 1;
34182 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
34183 if (!toc_initialized
)
34185 ASM_OUTPUT_ALIGN (asm_out_file
, TARGET_64BIT
? 3 : 2);
34186 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
34187 fprintf (asm_out_file
, " = .+32768\n");
34188 toc_initialized
= 1;
34193 /* Implement TARGET_ASM_INIT_SECTIONS. */
34196 rs6000_elf_asm_init_sections (void)
34199 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
34202 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
34203 SDATA2_SECTION_ASM_OP
);
34206 /* Implement TARGET_SELECT_RTX_SECTION. */
34209 rs6000_elf_select_rtx_section (machine_mode mode
, rtx x
,
34210 unsigned HOST_WIDE_INT align
)
34212 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
34213 return toc_section
;
34215 return default_elf_select_rtx_section (mode
, x
, align
);
34218 /* For a SYMBOL_REF, set generic flags and then perform some
34219 target-specific processing.
34221 When the AIX ABI is requested on a non-AIX system, replace the
34222 function name with the real name (with a leading .) rather than the
34223 function descriptor name. This saves a lot of overriding code to
34224 read the prefixes. */
34226 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
34228 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
34230 default_encode_section_info (decl
, rtl
, first
);
34233 && TREE_CODE (decl
) == FUNCTION_DECL
34235 && DEFAULT_ABI
== ABI_AIX
)
34237 rtx sym_ref
= XEXP (rtl
, 0);
34238 size_t len
= strlen (XSTR (sym_ref
, 0));
34239 char *str
= XALLOCAVEC (char, len
+ 2);
34241 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
34242 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
34247 compare_section_name (const char *section
, const char *templ
)
34251 len
= strlen (templ
);
34252 return (strncmp (section
, templ
, len
) == 0
34253 && (section
[len
] == 0 || section
[len
] == '.'));
34257 rs6000_elf_in_small_data_p (const_tree decl
)
34259 if (rs6000_sdata
== SDATA_NONE
)
34262 /* We want to merge strings, so we never consider them small data. */
34263 if (TREE_CODE (decl
) == STRING_CST
)
34266 /* Functions are never in the small data area. */
34267 if (TREE_CODE (decl
) == FUNCTION_DECL
)
34270 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
34272 const char *section
= DECL_SECTION_NAME (decl
);
34273 if (compare_section_name (section
, ".sdata")
34274 || compare_section_name (section
, ".sdata2")
34275 || compare_section_name (section
, ".gnu.linkonce.s")
34276 || compare_section_name (section
, ".sbss")
34277 || compare_section_name (section
, ".sbss2")
34278 || compare_section_name (section
, ".gnu.linkonce.sb")
34279 || strcmp (section
, ".PPC.EMB.sdata0") == 0
34280 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
34285 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
34288 && size
<= g_switch_value
34289 /* If it's not public, and we're not going to reference it there,
34290 there's no need to put it in the small data section. */
34291 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
34298 #endif /* USING_ELFOS_H */
34300 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
34303 rs6000_use_blocks_for_constant_p (machine_mode mode
, const_rtx x
)
34305 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
34308 /* Do not place thread-local symbols refs in the object blocks. */
34311 rs6000_use_blocks_for_decl_p (const_tree decl
)
34313 return !DECL_THREAD_LOCAL_P (decl
);
34316 /* Return a REG that occurs in ADDR with coefficient 1.
34317 ADDR can be effectively incremented by incrementing REG.
34319 r0 is special and we must not select it as an address
34320 register by this routine since our caller will try to
34321 increment the returned register via an "la" instruction. */
34324 find_addr_reg (rtx addr
)
34326 while (GET_CODE (addr
) == PLUS
)
34328 if (GET_CODE (XEXP (addr
, 0)) == REG
34329 && REGNO (XEXP (addr
, 0)) != 0)
34330 addr
= XEXP (addr
, 0);
34331 else if (GET_CODE (XEXP (addr
, 1)) == REG
34332 && REGNO (XEXP (addr
, 1)) != 0)
34333 addr
= XEXP (addr
, 1);
34334 else if (CONSTANT_P (XEXP (addr
, 0)))
34335 addr
= XEXP (addr
, 1);
34336 else if (CONSTANT_P (XEXP (addr
, 1)))
34337 addr
= XEXP (addr
, 0);
34339 gcc_unreachable ();
34341 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
34346 rs6000_fatal_bad_address (rtx op
)
34348 fatal_insn ("bad address", op
);
34353 typedef struct branch_island_d
{
34354 tree function_name
;
34360 static vec
<branch_island
, va_gc
> *branch_islands
;
34362 /* Remember to generate a branch island for far calls to the given
34366 add_compiler_branch_island (tree label_name
, tree function_name
,
34369 branch_island bi
= {function_name
, label_name
, line_number
};
34370 vec_safe_push (branch_islands
, bi
);
34373 /* Generate far-jump branch islands for everything recorded in
34374 branch_islands. Invoked immediately after the last instruction of
34375 the epilogue has been emitted; the branch islands must be appended
34376 to, and contiguous with, the function body. Mach-O stubs are
34377 generated in machopic_output_stub(). */
34380 macho_branch_islands (void)
34384 while (!vec_safe_is_empty (branch_islands
))
34386 branch_island
*bi
= &branch_islands
->last ();
34387 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
34388 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
34389 char name_buf
[512];
34390 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
34391 if (name
[0] == '*' || name
[0] == '&')
34392 strcpy (name_buf
, name
+1);
34396 strcpy (name_buf
+1, name
);
34398 strcpy (tmp_buf
, "\n");
34399 strcat (tmp_buf
, label
);
34400 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
34401 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
34402 dbxout_stabd (N_SLINE
, bi
->line_number
);
34403 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
34406 if (TARGET_LINK_STACK
)
34409 get_ppc476_thunk_name (name
);
34410 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
34411 strcat (tmp_buf
, name
);
34412 strcat (tmp_buf
, "\n");
34413 strcat (tmp_buf
, label
);
34414 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
34418 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
34419 strcat (tmp_buf
, label
);
34420 strcat (tmp_buf
, "_pic\n");
34421 strcat (tmp_buf
, label
);
34422 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
34425 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
34426 strcat (tmp_buf
, name_buf
);
34427 strcat (tmp_buf
, " - ");
34428 strcat (tmp_buf
, label
);
34429 strcat (tmp_buf
, "_pic)\n");
34431 strcat (tmp_buf
, "\tmtlr r0\n");
34433 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
34434 strcat (tmp_buf
, name_buf
);
34435 strcat (tmp_buf
, " - ");
34436 strcat (tmp_buf
, label
);
34437 strcat (tmp_buf
, "_pic)\n");
34439 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
34443 strcat (tmp_buf
, ":\nlis r12,hi16(");
34444 strcat (tmp_buf
, name_buf
);
34445 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
34446 strcat (tmp_buf
, name_buf
);
34447 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
34449 output_asm_insn (tmp_buf
, 0);
34450 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
34451 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
34452 dbxout_stabd (N_SLINE
, bi
->line_number
);
34453 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
34454 branch_islands
->pop ();
34458 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
34459 already there or not. */
34462 no_previous_def (tree function_name
)
34467 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
34468 if (function_name
== bi
->function_name
)
34473 /* GET_PREV_LABEL gets the label name from the previous definition of
34477 get_prev_label (tree function_name
)
34482 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
34483 if (function_name
== bi
->function_name
)
34484 return bi
->label_name
;
34488 /* INSN is either a function call or a millicode call. It may have an
34489 unconditional jump in its delay slot.
34491 CALL_DEST is the routine we are calling. */
34494 output_call (rtx_insn
*insn
, rtx
*operands
, int dest_operand_number
,
34495 int cookie_operand_number
)
34497 static char buf
[256];
34498 if (darwin_emit_branch_islands
34499 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
34500 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
34503 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
34505 if (no_previous_def (funname
))
34507 rtx label_rtx
= gen_label_rtx ();
34508 char *label_buf
, temp_buf
[256];
34509 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
34510 CODE_LABEL_NUMBER (label_rtx
));
34511 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
34512 labelname
= get_identifier (label_buf
);
34513 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
34516 labelname
= get_prev_label (funname
);
34518 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
34519 instruction will reach 'foo', otherwise link as 'bl L42'".
34520 "L42" should be a 'branch island', that will do a far jump to
34521 'foo'. Branch islands are generated in
34522 macho_branch_islands(). */
34523 sprintf (buf
, "jbsr %%z%d,%.246s",
34524 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
34527 sprintf (buf
, "bl %%z%d", dest_operand_number
);
34531 /* Generate PIC and indirect symbol stubs. */
34534 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
34536 unsigned int length
;
34537 char *symbol_name
, *lazy_ptr_name
;
34538 char *local_label_0
;
34539 static int label
= 0;
34541 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34542 symb
= (*targetm
.strip_name_encoding
) (symb
);
34545 length
= strlen (symb
);
34546 symbol_name
= XALLOCAVEC (char, length
+ 32);
34547 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
34549 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
34550 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
34553 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
34555 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
34559 fprintf (file
, "\t.align 5\n");
34561 fprintf (file
, "%s:\n", stub
);
34562 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
34565 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
34566 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
34568 fprintf (file
, "\tmflr r0\n");
34569 if (TARGET_LINK_STACK
)
34572 get_ppc476_thunk_name (name
);
34573 fprintf (file
, "\tbl %s\n", name
);
34574 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
34578 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
34579 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
34581 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
34582 lazy_ptr_name
, local_label_0
);
34583 fprintf (file
, "\tmtlr r0\n");
34584 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
34585 (TARGET_64BIT
? "ldu" : "lwzu"),
34586 lazy_ptr_name
, local_label_0
);
34587 fprintf (file
, "\tmtctr r12\n");
34588 fprintf (file
, "\tbctr\n");
34592 fprintf (file
, "\t.align 4\n");
34594 fprintf (file
, "%s:\n", stub
);
34595 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
34597 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
34598 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
34599 (TARGET_64BIT
? "ldu" : "lwzu"),
34601 fprintf (file
, "\tmtctr r12\n");
34602 fprintf (file
, "\tbctr\n");
34605 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
34606 fprintf (file
, "%s:\n", lazy_ptr_name
);
34607 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
34608 fprintf (file
, "%sdyld_stub_binding_helper\n",
34609 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
34612 /* Legitimize PIC addresses. If the address is already
34613 position-independent, we return ORIG. Newly generated
34614 position-independent addresses go into a reg. This is REG if non
34615 zero, otherwise we allocate register(s) as necessary. */
34617 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
34620 rs6000_machopic_legitimize_pic_address (rtx orig
, machine_mode mode
,
34625 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
34626 reg
= gen_reg_rtx (Pmode
);
34628 if (GET_CODE (orig
) == CONST
)
34632 if (GET_CODE (XEXP (orig
, 0)) == PLUS
34633 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
34636 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
34638 /* Use a different reg for the intermediate value, as
34639 it will be marked UNCHANGING. */
34640 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
34641 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
34644 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
34647 if (GET_CODE (offset
) == CONST_INT
)
34649 if (SMALL_INT (offset
))
34650 return plus_constant (Pmode
, base
, INTVAL (offset
));
34651 else if (! reload_in_progress
&& ! reload_completed
)
34652 offset
= force_reg (Pmode
, offset
);
34655 rtx mem
= force_const_mem (Pmode
, orig
);
34656 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
34659 return gen_rtx_PLUS (Pmode
, base
, offset
);
34662 /* Fall back on generic machopic code. */
34663 return machopic_legitimize_pic_address (orig
, mode
, reg
);
34666 /* Output a .machine directive for the Darwin assembler, and call
34667 the generic start_file routine. */
34670 rs6000_darwin_file_start (void)
34672 static const struct
34676 HOST_WIDE_INT if_set
;
34678 { "ppc64", "ppc64", MASK_64BIT
},
34679 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
34680 { "power4", "ppc970", 0 },
34681 { "G5", "ppc970", 0 },
34682 { "7450", "ppc7450", 0 },
34683 { "7400", "ppc7400", MASK_ALTIVEC
},
34684 { "G4", "ppc7400", 0 },
34685 { "750", "ppc750", 0 },
34686 { "740", "ppc750", 0 },
34687 { "G3", "ppc750", 0 },
34688 { "604e", "ppc604e", 0 },
34689 { "604", "ppc604", 0 },
34690 { "603e", "ppc603", 0 },
34691 { "603", "ppc603", 0 },
34692 { "601", "ppc601", 0 },
34693 { NULL
, "ppc", 0 } };
34694 const char *cpu_id
= "";
34697 rs6000_file_start ();
34698 darwin_file_start ();
34700 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
34702 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
34703 cpu_id
= rs6000_default_cpu
;
34705 if (global_options_set
.x_rs6000_cpu_index
)
34706 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
34708 /* Look through the mapping array. Pick the first name that either
34709 matches the argument, has a bit set in IF_SET that is also set
34710 in the target flags, or has a NULL name. */
34713 while (mapping
[i
].arg
!= NULL
34714 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
34715 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
34718 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
34721 #endif /* TARGET_MACHO */
34725 rs6000_elf_reloc_rw_mask (void)
34729 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
34735 /* Record an element in the table of global constructors. SYMBOL is
34736 a SYMBOL_REF of the function to be called; PRIORITY is a number
34737 between 0 and MAX_INIT_PRIORITY.
34739 This differs from default_named_section_asm_out_constructor in
34740 that we have special handling for -mrelocatable. */
34742 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
34744 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
34746 const char *section
= ".ctors";
34749 if (priority
!= DEFAULT_INIT_PRIORITY
)
34751 sprintf (buf
, ".ctors.%.5u",
34752 /* Invert the numbering so the linker puts us in the proper
34753 order; constructors are run from right to left, and the
34754 linker sorts in increasing order. */
34755 MAX_INIT_PRIORITY
- priority
);
34759 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
34760 assemble_align (POINTER_SIZE
);
34762 if (DEFAULT_ABI
== ABI_V4
34763 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
34765 fputs ("\t.long (", asm_out_file
);
34766 output_addr_const (asm_out_file
, symbol
);
34767 fputs (")@fixup\n", asm_out_file
);
34770 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
34773 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
34775 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
34777 const char *section
= ".dtors";
34780 if (priority
!= DEFAULT_INIT_PRIORITY
)
34782 sprintf (buf
, ".dtors.%.5u",
34783 /* Invert the numbering so the linker puts us in the proper
34784 order; constructors are run from right to left, and the
34785 linker sorts in increasing order. */
34786 MAX_INIT_PRIORITY
- priority
);
34790 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
34791 assemble_align (POINTER_SIZE
);
34793 if (DEFAULT_ABI
== ABI_V4
34794 && (TARGET_RELOCATABLE
|| flag_pic
> 1))
34796 fputs ("\t.long (", asm_out_file
);
34797 output_addr_const (asm_out_file
, symbol
);
34798 fputs (")@fixup\n", asm_out_file
);
34801 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
34805 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
34807 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
34809 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
34810 ASM_OUTPUT_LABEL (file
, name
);
34811 fputs (DOUBLE_INT_ASM_OP
, file
);
34812 rs6000_output_function_entry (file
, name
);
34813 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
34816 fputs ("\t.size\t", file
);
34817 assemble_name (file
, name
);
34818 fputs (",24\n\t.type\t.", file
);
34819 assemble_name (file
, name
);
34820 fputs (",@function\n", file
);
34821 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
34823 fputs ("\t.globl\t.", file
);
34824 assemble_name (file
, name
);
34829 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
34830 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
34831 rs6000_output_function_entry (file
, name
);
34832 fputs (":\n", file
);
34836 if (DEFAULT_ABI
== ABI_V4
34837 && (TARGET_RELOCATABLE
|| flag_pic
> 1)
34838 && !TARGET_SECURE_PLT
34839 && (get_pool_size () != 0 || crtl
->profile
)
34844 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
34846 fprintf (file
, "\t.long ");
34847 assemble_name (file
, toc_label_name
);
34850 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
34851 assemble_name (file
, buf
);
34855 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
34856 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
34858 if (TARGET_CMODEL
== CMODEL_LARGE
&& rs6000_global_entry_point_needed_p ())
34862 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
34864 fprintf (file
, "\t.quad .TOC.-");
34865 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
34866 assemble_name (file
, buf
);
34870 if (DEFAULT_ABI
== ABI_AIX
)
34872 const char *desc_name
, *orig_name
;
34874 orig_name
= (*targetm
.strip_name_encoding
) (name
);
34875 desc_name
= orig_name
;
34876 while (*desc_name
== '.')
34879 if (TREE_PUBLIC (decl
))
34880 fprintf (file
, "\t.globl %s\n", desc_name
);
34882 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
34883 fprintf (file
, "%s:\n", desc_name
);
34884 fprintf (file
, "\t.long %s\n", orig_name
);
34885 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
34886 fputs ("\t.long 0\n", file
);
34887 fprintf (file
, "\t.previous\n");
34889 ASM_OUTPUT_LABEL (file
, name
);
34892 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
34894 rs6000_elf_file_end (void)
34896 #ifdef HAVE_AS_GNU_ATTRIBUTE
34897 /* ??? The value emitted depends on options active at file end.
34898 Assume anyone using #pragma or attributes that might change
34899 options knows what they are doing. */
34900 if ((TARGET_64BIT
|| DEFAULT_ABI
== ABI_V4
)
34901 && rs6000_passes_float
)
34905 if (TARGET_DF_FPR
| TARGET_DF_SPE
)
34907 else if (TARGET_SF_FPR
| TARGET_SF_SPE
)
34911 if (rs6000_passes_long_double
)
34913 if (!TARGET_LONG_DOUBLE_128
)
34915 else if (TARGET_IEEEQUAD
)
34920 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n", fp
);
34922 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
34924 if (rs6000_passes_vector
)
34925 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
34926 (TARGET_ALTIVEC_ABI
? 2
34927 : TARGET_SPE_ABI
? 3
34929 if (rs6000_returns_struct
)
34930 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
34931 aix_struct_return
? 2 : 1);
34934 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
34935 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
34936 file_end_indicate_exec_stack ();
34939 if (flag_split_stack
)
34940 file_end_indicate_split_stack ();
34944 /* We have expanded a CPU builtin, so we need to emit a reference to
34945 the special symbol that LIBC uses to declare it supports the
34946 AT_PLATFORM and AT_HWCAP/AT_HWCAP2 in the TCB feature. */
34947 switch_to_section (data_section
);
34948 fprintf (asm_out_file
, "\t.align %u\n", TARGET_32BIT
? 2 : 3);
34949 fprintf (asm_out_file
, "\t%s %s\n",
34950 TARGET_32BIT
? ".long" : ".quad", tcb_verification_symbol
);
34957 #ifndef HAVE_XCOFF_DWARF_EXTRAS
34958 #define HAVE_XCOFF_DWARF_EXTRAS 0
34961 static enum unwind_info_type
34962 rs6000_xcoff_debug_unwind_info (void)
34968 rs6000_xcoff_asm_output_anchor (rtx symbol
)
34972 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
34973 SYMBOL_REF_BLOCK_OFFSET (symbol
));
34974 fprintf (asm_out_file
, "%s", SET_ASM_OP
);
34975 RS6000_OUTPUT_BASENAME (asm_out_file
, XSTR (symbol
, 0));
34976 fprintf (asm_out_file
, ",");
34977 RS6000_OUTPUT_BASENAME (asm_out_file
, buffer
);
34978 fprintf (asm_out_file
, "\n");
34982 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
34984 fputs (GLOBAL_ASM_OP
, stream
);
34985 RS6000_OUTPUT_BASENAME (stream
, name
);
34986 putc ('\n', stream
);
34989 /* A get_unnamed_decl callback, used for read-only sections. PTR
34990 points to the section string variable. */
34993 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
34995 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
34996 *(const char *const *) directive
,
34997 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
35000 /* Likewise for read-write sections. */
35003 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
35005 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
35006 *(const char *const *) directive
,
35007 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
35011 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
35013 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
35014 *(const char *const *) directive
,
35015 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
35018 /* A get_unnamed_section callback, used for switching to toc_section. */
35021 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
35023 if (TARGET_MINIMAL_TOC
)
35025 /* toc_section is always selected at least once from
35026 rs6000_xcoff_file_start, so this is guaranteed to
35027 always be defined once and only once in each file. */
35028 if (!toc_initialized
)
35030 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
35031 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
35032 toc_initialized
= 1;
35034 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
35035 (TARGET_32BIT
? "" : ",3"));
35038 fputs ("\t.toc\n", asm_out_file
);
35041 /* Implement TARGET_ASM_INIT_SECTIONS. */
35044 rs6000_xcoff_asm_init_sections (void)
35046 read_only_data_section
35047 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
35048 &xcoff_read_only_section_name
);
35050 private_data_section
35051 = get_unnamed_section (SECTION_WRITE
,
35052 rs6000_xcoff_output_readwrite_section_asm_op
,
35053 &xcoff_private_data_section_name
);
35056 = get_unnamed_section (SECTION_TLS
,
35057 rs6000_xcoff_output_tls_section_asm_op
,
35058 &xcoff_tls_data_section_name
);
35060 tls_private_data_section
35061 = get_unnamed_section (SECTION_TLS
,
35062 rs6000_xcoff_output_tls_section_asm_op
,
35063 &xcoff_private_data_section_name
);
35065 read_only_private_data_section
35066 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
35067 &xcoff_private_data_section_name
);
35070 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
35072 readonly_data_section
= read_only_data_section
;
35076 rs6000_xcoff_reloc_rw_mask (void)
35082 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
35083 tree decl ATTRIBUTE_UNUSED
)
35086 static const char * const suffix
[5] = { "PR", "RO", "RW", "TL", "XO" };
35088 if (flags
& SECTION_EXCLUDE
)
35090 else if (flags
& SECTION_DEBUG
)
35092 fprintf (asm_out_file
, "\t.dwsect %s\n", name
);
35095 else if (flags
& SECTION_CODE
)
35097 else if (flags
& SECTION_TLS
)
35099 else if (flags
& SECTION_WRITE
)
35104 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
35105 (flags
& SECTION_CODE
) ? "." : "",
35106 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
35109 #define IN_NAMED_SECTION(DECL) \
35110 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
35111 && DECL_SECTION_NAME (DECL) != NULL)
35114 rs6000_xcoff_select_section (tree decl
, int reloc
,
35115 unsigned HOST_WIDE_INT align
)
35117 /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into
35119 if (align
> BIGGEST_ALIGNMENT
)
35121 resolve_unique_section (decl
, reloc
, true);
35122 if (IN_NAMED_SECTION (decl
))
35123 return get_named_section (decl
, NULL
, reloc
);
35126 if (decl_readonly_section (decl
, reloc
))
35128 if (TREE_PUBLIC (decl
))
35129 return read_only_data_section
;
35131 return read_only_private_data_section
;
35136 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
35138 if (TREE_PUBLIC (decl
))
35139 return tls_data_section
;
35140 else if (bss_initializer_p (decl
))
35142 /* Convert to COMMON to emit in BSS. */
35143 DECL_COMMON (decl
) = 1;
35144 return tls_comm_section
;
35147 return tls_private_data_section
;
35151 if (TREE_PUBLIC (decl
))
35152 return data_section
;
35154 return private_data_section
;
35159 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
35163 /* Use select_section for private data and uninitialized data with
35164 alignment <= BIGGEST_ALIGNMENT. */
35165 if (!TREE_PUBLIC (decl
)
35166 || DECL_COMMON (decl
)
35167 || (DECL_INITIAL (decl
) == NULL_TREE
35168 && DECL_ALIGN (decl
) <= BIGGEST_ALIGNMENT
)
35169 || DECL_INITIAL (decl
) == error_mark_node
35170 || (flag_zero_initialized_in_bss
35171 && initializer_zerop (DECL_INITIAL (decl
))))
35174 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
35175 name
= (*targetm
.strip_name_encoding
) (name
);
35176 set_decl_section_name (decl
, name
);
35179 /* Select section for constant in constant pool.
35181 On RS/6000, all constants are in the private read-only data area.
35182 However, if this is being placed in the TOC it must be output as a
35186 rs6000_xcoff_select_rtx_section (machine_mode mode
, rtx x
,
35187 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
35189 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
35190 return toc_section
;
35192 return read_only_private_data_section
;
35195 /* Remove any trailing [DS] or the like from the symbol name. */
35197 static const char *
35198 rs6000_xcoff_strip_name_encoding (const char *name
)
35203 len
= strlen (name
);
35204 if (name
[len
- 1] == ']')
35205 return ggc_alloc_string (name
, len
- 4);
35210 /* Section attributes. AIX is always PIC. */
35212 static unsigned int
35213 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
35215 unsigned int align
;
35216 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
35218 /* Align to at least UNIT size. */
35219 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
35220 align
= MIN_UNITS_PER_WORD
;
35222 /* Increase alignment of large objects if not already stricter. */
35223 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
35224 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
35225 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
35227 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
35230 /* Output at beginning of assembler file.
35232 Initialize the section names for the RS/6000 at this point.
35234 Specify filename, including full path, to assembler.
35236 We want to go into the TOC section so at least one .toc will be emitted.
35237 Also, in order to output proper .bs/.es pairs, we need at least one static
35238 [RW] section emitted.
35240 Finally, declare mcount when profiling to make the assembler happy. */
35243 rs6000_xcoff_file_start (void)
35245 rs6000_gen_section_name (&xcoff_bss_section_name
,
35246 main_input_filename
, ".bss_");
35247 rs6000_gen_section_name (&xcoff_private_data_section_name
,
35248 main_input_filename
, ".rw_");
35249 rs6000_gen_section_name (&xcoff_read_only_section_name
,
35250 main_input_filename
, ".ro_");
35251 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
35252 main_input_filename
, ".tls_");
35253 rs6000_gen_section_name (&xcoff_tbss_section_name
,
35254 main_input_filename
, ".tbss_[UL]");
35256 fputs ("\t.file\t", asm_out_file
);
35257 output_quoted_string (asm_out_file
, main_input_filename
);
35258 fputc ('\n', asm_out_file
);
35259 if (write_symbols
!= NO_DEBUG
)
35260 switch_to_section (private_data_section
);
35261 switch_to_section (toc_section
);
35262 switch_to_section (text_section
);
35264 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
35265 rs6000_file_start ();
35268 /* Output at end of assembler file.
35269 On the RS/6000, referencing data should automatically pull in text. */
35272 rs6000_xcoff_file_end (void)
35274 switch_to_section (text_section
);
35275 fputs ("_section_.text:\n", asm_out_file
);
35276 switch_to_section (data_section
);
35277 fputs (TARGET_32BIT
35278 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
35282 struct declare_alias_data
35285 bool function_descriptor
;
35288 /* Declare alias N. A helper function for for_node_and_aliases. */
35291 rs6000_declare_alias (struct symtab_node
*n
, void *d
)
35293 struct declare_alias_data
*data
= (struct declare_alias_data
*)d
;
35294 /* Main symbol is output specially, because varasm machinery does part of
35295 the job for us - we do not need to declare .globl/lglobs and such. */
35296 if (!n
->alias
|| n
->weakref
)
35299 if (lookup_attribute ("ifunc", DECL_ATTRIBUTES (n
->decl
)))
35302 /* Prevent assemble_alias from trying to use .set pseudo operation
35303 that does not behave as expected by the middle-end. */
35304 TREE_ASM_WRITTEN (n
->decl
) = true;
35306 const char *name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (n
->decl
));
35307 char *buffer
= (char *) alloca (strlen (name
) + 2);
35309 int dollar_inside
= 0;
35311 strcpy (buffer
, name
);
35312 p
= strchr (buffer
, '$');
35316 p
= strchr (p
+ 1, '$');
35318 if (TREE_PUBLIC (n
->decl
))
35320 if (!RS6000_WEAK
|| !DECL_WEAK (n
->decl
))
35322 if (dollar_inside
) {
35323 if (data
->function_descriptor
)
35324 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
35325 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
35327 if (data
->function_descriptor
)
35329 fputs ("\t.globl .", data
->file
);
35330 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
35331 putc ('\n', data
->file
);
35333 fputs ("\t.globl ", data
->file
);
35334 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
35335 putc ('\n', data
->file
);
35337 #ifdef ASM_WEAKEN_DECL
35338 else if (DECL_WEAK (n
->decl
) && !data
->function_descriptor
)
35339 ASM_WEAKEN_DECL (data
->file
, n
->decl
, name
, NULL
);
35346 if (data
->function_descriptor
)
35347 fprintf(data
->file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
35348 fprintf(data
->file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
35350 if (data
->function_descriptor
)
35352 fputs ("\t.lglobl .", data
->file
);
35353 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
35354 putc ('\n', data
->file
);
35356 fputs ("\t.lglobl ", data
->file
);
35357 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
35358 putc ('\n', data
->file
);
35360 if (data
->function_descriptor
)
35361 fputs (".", data
->file
);
35362 RS6000_OUTPUT_BASENAME (data
->file
, buffer
);
35363 fputs (":\n", data
->file
);
35367 /* This macro produces the initial definition of a function name.
35368 On the RS/6000, we need to place an extra '.' in the function name and
35369 output the function descriptor.
35370 Dollar signs are converted to underscores.
35372 The csect for the function will have already been created when
35373 text_section was selected. We do have to go back to that csect, however.
35375 The third and fourth parameters to the .function pseudo-op (16 and 044)
35376 are placeholders which no longer have any use.
35378 Because AIX assembler's .set command has unexpected semantics, we output
35379 all aliases as alternative labels in front of the definition. */
35382 rs6000_xcoff_declare_function_name (FILE *file
, const char *name
, tree decl
)
35384 char *buffer
= (char *) alloca (strlen (name
) + 1);
35386 int dollar_inside
= 0;
35387 struct declare_alias_data data
= {file
, false};
35389 strcpy (buffer
, name
);
35390 p
= strchr (buffer
, '$');
35394 p
= strchr (p
+ 1, '$');
35396 if (TREE_PUBLIC (decl
))
35398 if (!RS6000_WEAK
|| !DECL_WEAK (decl
))
35400 if (dollar_inside
) {
35401 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
35402 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
35404 fputs ("\t.globl .", file
);
35405 RS6000_OUTPUT_BASENAME (file
, buffer
);
35411 if (dollar_inside
) {
35412 fprintf(file
, "\t.rename .%s,\".%s\"\n", buffer
, name
);
35413 fprintf(file
, "\t.rename %s,\"%s\"\n", buffer
, name
);
35415 fputs ("\t.lglobl .", file
);
35416 RS6000_OUTPUT_BASENAME (file
, buffer
);
35419 fputs ("\t.csect ", file
);
35420 RS6000_OUTPUT_BASENAME (file
, buffer
);
35421 fputs (TARGET_32BIT
? "[DS]\n" : "[DS],3\n", file
);
35422 RS6000_OUTPUT_BASENAME (file
, buffer
);
35423 fputs (":\n", file
);
35424 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
35426 fputs (TARGET_32BIT
? "\t.long ." : "\t.llong .", file
);
35427 RS6000_OUTPUT_BASENAME (file
, buffer
);
35428 fputs (", TOC[tc0], 0\n", file
);
35430 switch_to_section (function_section (decl
));
35432 RS6000_OUTPUT_BASENAME (file
, buffer
);
35433 fputs (":\n", file
);
35434 data
.function_descriptor
= true;
35435 symtab_node::get (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
35437 if (!DECL_IGNORED_P (decl
))
35439 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
35440 xcoffout_declare_function (file
, decl
, buffer
);
35441 else if (write_symbols
== DWARF2_DEBUG
)
35443 name
= (*targetm
.strip_name_encoding
) (name
);
35444 fprintf (file
, "\t.function .%s,.%s,2,0\n", name
, name
);
35450 /* This macro produces the initial definition of a object (variable) name.
35451 Because AIX assembler's .set command has unexpected semantics, we output
35452 all aliases as alternative labels in front of the definition. */
35455 rs6000_xcoff_declare_object_name (FILE *file
, const char *name
, tree decl
)
35457 struct declare_alias_data data
= {file
, false};
35458 RS6000_OUTPUT_BASENAME (file
, name
);
35459 fputs (":\n", file
);
35460 symtab_node::get_create (decl
)->call_for_symbol_and_aliases (rs6000_declare_alias
,
35464 /* Overide the default 'SYMBOL-.' syntax with AIX compatible 'SYMBOL-$'. */
35467 rs6000_asm_output_dwarf_pcrel (FILE *file
, int size
, const char *label
)
35469 fputs (integer_asm_op (size
, FALSE
), file
);
35470 assemble_name (file
, label
);
35471 fputs ("-$", file
);
35474 /* Output a symbol offset relative to the dbase for the current object.
35475 We use __gcc_unwind_dbase as an arbitrary base for dbase and assume
35478 __gcc_unwind_dbase is embedded in all executables/libraries through
35479 libgcc/config/rs6000/crtdbase.S. */
35482 rs6000_asm_output_dwarf_datarel (FILE *file
, int size
, const char *label
)
35484 fputs (integer_asm_op (size
, FALSE
), file
);
35485 assemble_name (file
, label
);
35486 fputs("-__gcc_unwind_dbase", file
);
35491 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
35495 const char *symname
;
35497 default_encode_section_info (decl
, rtl
, first
);
35499 /* Careful not to prod global register variables. */
35502 symbol
= XEXP (rtl
, 0);
35503 if (GET_CODE (symbol
) != SYMBOL_REF
)
35506 flags
= SYMBOL_REF_FLAGS (symbol
);
35508 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
35509 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
35511 SYMBOL_REF_FLAGS (symbol
) = flags
;
35513 /* Append mapping class to extern decls. */
35514 symname
= XSTR (symbol
, 0);
35515 if (decl
/* sync condition with assemble_external () */
35516 && DECL_P (decl
) && DECL_EXTERNAL (decl
) && TREE_PUBLIC (decl
)
35517 && ((TREE_CODE (decl
) == VAR_DECL
&& !DECL_THREAD_LOCAL_P (decl
))
35518 || TREE_CODE (decl
) == FUNCTION_DECL
)
35519 && symname
[strlen (symname
) - 1] != ']')
35521 char *newname
= (char *) alloca (strlen (symname
) + 5);
35522 strcpy (newname
, symname
);
35523 strcat (newname
, (TREE_CODE (decl
) == FUNCTION_DECL
35524 ? "[DS]" : "[UA]"));
35525 XSTR (symbol
, 0) = ggc_strdup (newname
);
35528 #endif /* HAVE_AS_TLS */
35529 #endif /* TARGET_XCOFF */
35531 /* Return true if INSN should not be copied. */
35534 rs6000_cannot_copy_insn_p (rtx_insn
*insn
)
35536 return recog_memoized (insn
) >= 0
35537 && get_attr_cannot_copy (insn
);
35540 /* Compute a (partial) cost for rtx X. Return true if the complete
35541 cost has been computed, and false if subexpressions should be
35542 scanned. In either case, *TOTAL contains the cost result. */
35545 rs6000_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
35546 int opno ATTRIBUTE_UNUSED
, int *total
, bool speed
)
35548 int code
= GET_CODE (x
);
35552 /* On the RS/6000, if it is valid in the insn, it is free. */
35554 if (((outer_code
== SET
35555 || outer_code
== PLUS
35556 || outer_code
== MINUS
)
35557 && (satisfies_constraint_I (x
)
35558 || satisfies_constraint_L (x
)))
35559 || (outer_code
== AND
35560 && (satisfies_constraint_K (x
)
35562 ? satisfies_constraint_L (x
)
35563 : satisfies_constraint_J (x
))))
35564 || ((outer_code
== IOR
|| outer_code
== XOR
)
35565 && (satisfies_constraint_K (x
)
35567 ? satisfies_constraint_L (x
)
35568 : satisfies_constraint_J (x
))))
35569 || outer_code
== ASHIFT
35570 || outer_code
== ASHIFTRT
35571 || outer_code
== LSHIFTRT
35572 || outer_code
== ROTATE
35573 || outer_code
== ROTATERT
35574 || outer_code
== ZERO_EXTRACT
35575 || (outer_code
== MULT
35576 && satisfies_constraint_I (x
))
35577 || ((outer_code
== DIV
|| outer_code
== UDIV
35578 || outer_code
== MOD
|| outer_code
== UMOD
)
35579 && exact_log2 (INTVAL (x
)) >= 0)
35580 || (outer_code
== COMPARE
35581 && (satisfies_constraint_I (x
)
35582 || satisfies_constraint_K (x
)))
35583 || ((outer_code
== EQ
|| outer_code
== NE
)
35584 && (satisfies_constraint_I (x
)
35585 || satisfies_constraint_K (x
)
35587 ? satisfies_constraint_L (x
)
35588 : satisfies_constraint_J (x
))))
35589 || (outer_code
== GTU
35590 && satisfies_constraint_I (x
))
35591 || (outer_code
== LTU
35592 && satisfies_constraint_P (x
)))
35597 else if ((outer_code
== PLUS
35598 && reg_or_add_cint_operand (x
, VOIDmode
))
35599 || (outer_code
== MINUS
35600 && reg_or_sub_cint_operand (x
, VOIDmode
))
35601 || ((outer_code
== SET
35602 || outer_code
== IOR
35603 || outer_code
== XOR
)
35605 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
35607 *total
= COSTS_N_INSNS (1);
35613 case CONST_WIDE_INT
:
35617 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
35621 /* When optimizing for size, MEM should be slightly more expensive
35622 than generating address, e.g., (plus (reg) (const)).
35623 L1 cache latency is about two instructions. */
35624 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
35625 if (SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (x
)))
35626 *total
+= COSTS_N_INSNS (100);
35635 if (FLOAT_MODE_P (mode
))
35636 *total
= rs6000_cost
->fp
;
35638 *total
= COSTS_N_INSNS (1);
35642 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
35643 && satisfies_constraint_I (XEXP (x
, 1)))
35645 if (INTVAL (XEXP (x
, 1)) >= -256
35646 && INTVAL (XEXP (x
, 1)) <= 255)
35647 *total
= rs6000_cost
->mulsi_const9
;
35649 *total
= rs6000_cost
->mulsi_const
;
35651 else if (mode
== SFmode
)
35652 *total
= rs6000_cost
->fp
;
35653 else if (FLOAT_MODE_P (mode
))
35654 *total
= rs6000_cost
->dmul
;
35655 else if (mode
== DImode
)
35656 *total
= rs6000_cost
->muldi
;
35658 *total
= rs6000_cost
->mulsi
;
35662 if (mode
== SFmode
)
35663 *total
= rs6000_cost
->fp
;
35665 *total
= rs6000_cost
->dmul
;
35670 if (FLOAT_MODE_P (mode
))
35672 *total
= mode
== DFmode
? rs6000_cost
->ddiv
35673 : rs6000_cost
->sdiv
;
35680 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
35681 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
35683 if (code
== DIV
|| code
== MOD
)
35685 *total
= COSTS_N_INSNS (2);
35688 *total
= COSTS_N_INSNS (1);
35692 if (GET_MODE (XEXP (x
, 1)) == DImode
)
35693 *total
= rs6000_cost
->divdi
;
35695 *total
= rs6000_cost
->divsi
;
35697 /* Add in shift and subtract for MOD unless we have a mod instruction. */
35698 if (!TARGET_MODULO
&& (code
== MOD
|| code
== UMOD
))
35699 *total
+= COSTS_N_INSNS (2);
35703 *total
= COSTS_N_INSNS (TARGET_CTZ
? 1 : 4);
35707 *total
= COSTS_N_INSNS (4);
35711 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
35715 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
35719 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
35722 *total
= COSTS_N_INSNS (1);
35726 if (CONST_INT_P (XEXP (x
, 1)))
35728 rtx left
= XEXP (x
, 0);
35729 rtx_code left_code
= GET_CODE (left
);
35731 /* rotate-and-mask: 1 insn. */
35732 if ((left_code
== ROTATE
35733 || left_code
== ASHIFT
35734 || left_code
== LSHIFTRT
)
35735 && rs6000_is_valid_shift_mask (XEXP (x
, 1), left
, mode
))
35737 *total
= rtx_cost (XEXP (left
, 0), mode
, left_code
, 0, speed
);
35738 if (!CONST_INT_P (XEXP (left
, 1)))
35739 *total
+= rtx_cost (XEXP (left
, 1), SImode
, left_code
, 1, speed
);
35740 *total
+= COSTS_N_INSNS (1);
35744 /* rotate-and-mask (no rotate), andi., andis.: 1 insn. */
35745 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
35746 if (rs6000_is_valid_and_mask (XEXP (x
, 1), mode
)
35747 || (val
& 0xffff) == val
35748 || (val
& 0xffff0000) == val
35749 || ((val
& 0xffff) == 0 && mode
== SImode
))
35751 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
35752 *total
+= COSTS_N_INSNS (1);
35757 if (rs6000_is_valid_2insn_and (XEXP (x
, 1), mode
))
35759 *total
= rtx_cost (left
, mode
, AND
, 0, speed
);
35760 *total
+= COSTS_N_INSNS (2);
35765 *total
= COSTS_N_INSNS (1);
35770 *total
= COSTS_N_INSNS (1);
35776 *total
= COSTS_N_INSNS (1);
35780 /* The EXTSWSLI instruction is a combined instruction. Don't count both
35781 the sign extend and shift separately within the insn. */
35782 if (TARGET_EXTSWSLI
&& mode
== DImode
35783 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
35784 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == SImode
)
35795 /* Handle mul_highpart. */
35796 if (outer_code
== TRUNCATE
35797 && GET_CODE (XEXP (x
, 0)) == MULT
)
35799 if (mode
== DImode
)
35800 *total
= rs6000_cost
->muldi
;
35802 *total
= rs6000_cost
->mulsi
;
35805 else if (outer_code
== AND
)
35808 *total
= COSTS_N_INSNS (1);
35813 if (GET_CODE (XEXP (x
, 0)) == MEM
)
35816 *total
= COSTS_N_INSNS (1);
35822 if (!FLOAT_MODE_P (mode
))
35824 *total
= COSTS_N_INSNS (1);
35830 case UNSIGNED_FLOAT
:
35833 case FLOAT_TRUNCATE
:
35834 *total
= rs6000_cost
->fp
;
35838 if (mode
== DFmode
)
35839 *total
= rs6000_cost
->sfdf_convert
;
35841 *total
= rs6000_cost
->fp
;
35845 switch (XINT (x
, 1))
35848 *total
= rs6000_cost
->fp
;
35860 *total
= COSTS_N_INSNS (1);
35863 else if (FLOAT_MODE_P (mode
)
35864 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
35866 *total
= rs6000_cost
->fp
;
35875 /* Carry bit requires mode == Pmode.
35876 NEG or PLUS already counted so only add one. */
35878 && (outer_code
== NEG
|| outer_code
== PLUS
))
35880 *total
= COSTS_N_INSNS (1);
35883 if (outer_code
== SET
)
35885 if (XEXP (x
, 1) == const0_rtx
)
35887 if (TARGET_ISEL
&& !TARGET_MFCRF
)
35888 *total
= COSTS_N_INSNS (8);
35890 *total
= COSTS_N_INSNS (2);
35895 *total
= COSTS_N_INSNS (3);
35904 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
35906 if (TARGET_ISEL
&& !TARGET_MFCRF
)
35907 *total
= COSTS_N_INSNS (8);
35909 *total
= COSTS_N_INSNS (2);
35913 if (outer_code
== COMPARE
)
35927 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
35930 rs6000_debug_rtx_costs (rtx x
, machine_mode mode
, int outer_code
,
35931 int opno
, int *total
, bool speed
)
35933 bool ret
= rs6000_rtx_costs (x
, mode
, outer_code
, opno
, total
, speed
);
35936 "\nrs6000_rtx_costs, return = %s, mode = %s, outer_code = %s, "
35937 "opno = %d, total = %d, speed = %s, x:\n",
35938 ret
? "complete" : "scan inner",
35939 GET_MODE_NAME (mode
),
35940 GET_RTX_NAME (outer_code
),
35943 speed
? "true" : "false");
35950 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
35953 rs6000_debug_address_cost (rtx x
, machine_mode mode
,
35954 addr_space_t as
, bool speed
)
35956 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
35958 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
35959 ret
, speed
? "true" : "false");
35966 /* A C expression returning the cost of moving data from a register of class
35967 CLASS1 to one of CLASS2. */
35970 rs6000_register_move_cost (machine_mode mode
,
35971 reg_class_t from
, reg_class_t to
)
35975 if (TARGET_DEBUG_COST
)
35978 /* Moves from/to GENERAL_REGS. */
35979 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
35980 || reg_classes_intersect_p (from
, GENERAL_REGS
))
35982 reg_class_t rclass
= from
;
35984 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
35987 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
35988 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
35989 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
35991 /* It's more expensive to move CR_REGS than CR0_REGS because of the
35993 else if (rclass
== CR_REGS
)
35996 /* For those processors that have slow LR/CTR moves, make them more
35997 expensive than memory in order to bias spills to memory .*/
35998 else if ((rs6000_cpu
== PROCESSOR_POWER6
35999 || rs6000_cpu
== PROCESSOR_POWER7
36000 || rs6000_cpu
== PROCESSOR_POWER8
36001 || rs6000_cpu
== PROCESSOR_POWER9
)
36002 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
36003 ret
= 6 * hard_regno_nregs
[0][mode
];
36006 /* A move will cost one instruction per GPR moved. */
36007 ret
= 2 * hard_regno_nregs
[0][mode
];
36010 /* If we have VSX, we can easily move between FPR or Altivec registers. */
36011 else if (VECTOR_MEM_VSX_P (mode
)
36012 && reg_classes_intersect_p (to
, VSX_REGS
)
36013 && reg_classes_intersect_p (from
, VSX_REGS
))
36014 ret
= 2 * hard_regno_nregs
[FIRST_FPR_REGNO
][mode
];
36016 /* Moving between two similar registers is just one instruction. */
36017 else if (reg_classes_intersect_p (to
, from
))
36018 ret
= (FLOAT128_2REG_P (mode
)) ? 4 : 2;
36020 /* Everything else has to go through GENERAL_REGS. */
36022 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
36023 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
36025 if (TARGET_DEBUG_COST
)
36027 if (dbg_cost_ctrl
== 1)
36029 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
36030 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
36031 reg_class_names
[to
]);
36038 /* A C expressions returning the cost of moving data of MODE from a register to
36042 rs6000_memory_move_cost (machine_mode mode
, reg_class_t rclass
,
36043 bool in ATTRIBUTE_UNUSED
)
36047 if (TARGET_DEBUG_COST
)
36050 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
36051 ret
= 4 * hard_regno_nregs
[0][mode
];
36052 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
36053 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
36054 ret
= 4 * hard_regno_nregs
[32][mode
];
36055 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
36056 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
36058 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
36060 if (TARGET_DEBUG_COST
)
36062 if (dbg_cost_ctrl
== 1)
36064 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
36065 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
36072 /* Returns a code for a target-specific builtin that implements
36073 reciprocal of the function, or NULL_TREE if not available. */
36076 rs6000_builtin_reciprocal (tree fndecl
)
36078 switch (DECL_FUNCTION_CODE (fndecl
))
36080 case VSX_BUILTIN_XVSQRTDP
:
36081 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
36084 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
36086 case VSX_BUILTIN_XVSQRTSP
:
36087 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
36090 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
36097 /* Load up a constant. If the mode is a vector mode, splat the value across
36098 all of the vector elements. */
36101 rs6000_load_constant_and_splat (machine_mode mode
, REAL_VALUE_TYPE dconst
)
36105 if (mode
== SFmode
|| mode
== DFmode
)
36107 rtx d
= const_double_from_real_value (dconst
, mode
);
36108 reg
= force_reg (mode
, d
);
36110 else if (mode
== V4SFmode
)
36112 rtx d
= const_double_from_real_value (dconst
, SFmode
);
36113 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
36114 reg
= gen_reg_rtx (mode
);
36115 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
36117 else if (mode
== V2DFmode
)
36119 rtx d
= const_double_from_real_value (dconst
, DFmode
);
36120 rtvec v
= gen_rtvec (2, d
, d
);
36121 reg
= gen_reg_rtx (mode
);
36122 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
36125 gcc_unreachable ();
36130 /* Generate an FMA instruction. */
36133 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
36135 machine_mode mode
= GET_MODE (target
);
36138 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
36139 gcc_assert (dst
!= NULL
);
36142 emit_move_insn (target
, dst
);
36145 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
36148 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
36150 machine_mode mode
= GET_MODE (dst
);
36153 /* This is a tad more complicated, since the fnma_optab is for
36154 a different expression: fma(-m1, m2, a), which is the same
36155 thing except in the case of signed zeros.
36157 Fortunately we know that if FMA is supported that FNMSUB is
36158 also supported in the ISA. Just expand it directly. */
36160 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
36162 r
= gen_rtx_NEG (mode
, a
);
36163 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
36164 r
= gen_rtx_NEG (mode
, r
);
36165 emit_insn (gen_rtx_SET (dst
, r
));
36168 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
36169 add a reg_note saying that this was a division. Support both scalar and
36170 vector divide. Assumes no trapping math and finite arguments. */
36173 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
36175 machine_mode mode
= GET_MODE (dst
);
36176 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
36179 /* Low precision estimates guarantee 5 bits of accuracy. High
36180 precision estimates guarantee 14 bits of accuracy. SFmode
36181 requires 23 bits of accuracy. DFmode requires 52 bits of
36182 accuracy. Each pass at least doubles the accuracy, leading
36183 to the following. */
36184 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
36185 if (mode
== DFmode
|| mode
== V2DFmode
)
36188 enum insn_code code
= optab_handler (smul_optab
, mode
);
36189 insn_gen_fn gen_mul
= GEN_FCN (code
);
36191 gcc_assert (code
!= CODE_FOR_nothing
);
36193 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
36195 /* x0 = 1./d estimate */
36196 x0
= gen_reg_rtx (mode
);
36197 emit_insn (gen_rtx_SET (x0
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
36200 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
36203 /* e0 = 1. - d * x0 */
36204 e0
= gen_reg_rtx (mode
);
36205 rs6000_emit_nmsub (e0
, d
, x0
, one
);
36207 /* x1 = x0 + e0 * x0 */
36208 x1
= gen_reg_rtx (mode
);
36209 rs6000_emit_madd (x1
, e0
, x0
, x0
);
36211 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
36212 ++i
, xprev
= xnext
, eprev
= enext
) {
36214 /* enext = eprev * eprev */
36215 enext
= gen_reg_rtx (mode
);
36216 emit_insn (gen_mul (enext
, eprev
, eprev
));
36218 /* xnext = xprev + enext * xprev */
36219 xnext
= gen_reg_rtx (mode
);
36220 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
36226 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
36228 /* u = n * xprev */
36229 u
= gen_reg_rtx (mode
);
36230 emit_insn (gen_mul (u
, n
, xprev
));
36232 /* v = n - (d * u) */
36233 v
= gen_reg_rtx (mode
);
36234 rs6000_emit_nmsub (v
, d
, u
, n
);
36236 /* dst = (v * xprev) + u */
36237 rs6000_emit_madd (dst
, v
, xprev
, u
);
36240 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
36243 /* Goldschmidt's Algorithm for single/double-precision floating point
36244 sqrt and rsqrt. Assumes no trapping math and finite arguments. */
36247 rs6000_emit_swsqrt (rtx dst
, rtx src
, bool recip
)
36249 machine_mode mode
= GET_MODE (src
);
36250 rtx e
= gen_reg_rtx (mode
);
36251 rtx g
= gen_reg_rtx (mode
);
36252 rtx h
= gen_reg_rtx (mode
);
36254 /* Low precision estimates guarantee 5 bits of accuracy. High
36255 precision estimates guarantee 14 bits of accuracy. SFmode
36256 requires 23 bits of accuracy. DFmode requires 52 bits of
36257 accuracy. Each pass at least doubles the accuracy, leading
36258 to the following. */
36259 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
36260 if (mode
== DFmode
|| mode
== V2DFmode
)
36265 enum insn_code code
= optab_handler (smul_optab
, mode
);
36266 insn_gen_fn gen_mul
= GEN_FCN (code
);
36268 gcc_assert (code
!= CODE_FOR_nothing
);
36270 mhalf
= rs6000_load_constant_and_splat (mode
, dconsthalf
);
36272 /* e = rsqrt estimate */
36273 emit_insn (gen_rtx_SET (e
, gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
36276 /* If (src == 0.0) filter infinity to prevent NaN for sqrt(0.0). */
36279 rtx zero
= force_reg (mode
, CONST0_RTX (mode
));
36281 if (mode
== SFmode
)
36283 rtx target
= emit_conditional_move (e
, GT
, src
, zero
, mode
,
36286 emit_move_insn (e
, target
);
36290 rtx cond
= gen_rtx_GT (VOIDmode
, e
, zero
);
36291 rs6000_emit_vector_cond_expr (e
, e
, zero
, cond
, src
, zero
);
36295 /* g = sqrt estimate. */
36296 emit_insn (gen_mul (g
, e
, src
));
36297 /* h = 1/(2*sqrt) estimate. */
36298 emit_insn (gen_mul (h
, e
, mhalf
));
36304 rtx t
= gen_reg_rtx (mode
);
36305 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
36306 /* Apply correction directly to 1/rsqrt estimate. */
36307 rs6000_emit_madd (dst
, e
, t
, e
);
36311 for (i
= 0; i
< passes
; i
++)
36313 rtx t1
= gen_reg_rtx (mode
);
36314 rtx g1
= gen_reg_rtx (mode
);
36315 rtx h1
= gen_reg_rtx (mode
);
36317 rs6000_emit_nmsub (t1
, g
, h
, mhalf
);
36318 rs6000_emit_madd (g1
, g
, t1
, g
);
36319 rs6000_emit_madd (h1
, h
, t1
, h
);
36324 /* Multiply by 2 for 1/rsqrt. */
36325 emit_insn (gen_add3_insn (dst
, h
, h
));
36330 rtx t
= gen_reg_rtx (mode
);
36331 rs6000_emit_nmsub (t
, g
, h
, mhalf
);
36332 rs6000_emit_madd (dst
, g
, t
, g
);
36338 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
36339 (Power7) targets. DST is the target, and SRC is the argument operand. */
36342 rs6000_emit_popcount (rtx dst
, rtx src
)
36344 machine_mode mode
= GET_MODE (dst
);
36347 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
36348 if (TARGET_POPCNTD
)
36350 if (mode
== SImode
)
36351 emit_insn (gen_popcntdsi2 (dst
, src
));
36353 emit_insn (gen_popcntddi2 (dst
, src
));
36357 tmp1
= gen_reg_rtx (mode
);
36359 if (mode
== SImode
)
36361 emit_insn (gen_popcntbsi2 (tmp1
, src
));
36362 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
36364 tmp2
= force_reg (SImode
, tmp2
);
36365 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
36369 emit_insn (gen_popcntbdi2 (tmp1
, src
));
36370 tmp2
= expand_mult (DImode
, tmp1
,
36371 GEN_INT ((HOST_WIDE_INT
)
36372 0x01010101 << 32 | 0x01010101),
36374 tmp2
= force_reg (DImode
, tmp2
);
36375 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
36380 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
36381 target, and SRC is the argument operand. */
36384 rs6000_emit_parity (rtx dst
, rtx src
)
36386 machine_mode mode
= GET_MODE (dst
);
36389 tmp
= gen_reg_rtx (mode
);
36391 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
36394 if (mode
== SImode
)
36396 emit_insn (gen_popcntbsi2 (tmp
, src
));
36397 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
36401 emit_insn (gen_popcntbdi2 (tmp
, src
));
36402 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
36407 if (mode
== SImode
)
36409 /* Is mult+shift >= shift+xor+shift+xor? */
36410 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
36412 rtx tmp1
, tmp2
, tmp3
, tmp4
;
36414 tmp1
= gen_reg_rtx (SImode
);
36415 emit_insn (gen_popcntbsi2 (tmp1
, src
));
36417 tmp2
= gen_reg_rtx (SImode
);
36418 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
36419 tmp3
= gen_reg_rtx (SImode
);
36420 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
36422 tmp4
= gen_reg_rtx (SImode
);
36423 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
36424 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
36427 rs6000_emit_popcount (tmp
, src
);
36428 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
36432 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
36433 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
36435 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
36437 tmp1
= gen_reg_rtx (DImode
);
36438 emit_insn (gen_popcntbdi2 (tmp1
, src
));
36440 tmp2
= gen_reg_rtx (DImode
);
36441 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
36442 tmp3
= gen_reg_rtx (DImode
);
36443 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
36445 tmp4
= gen_reg_rtx (DImode
);
36446 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
36447 tmp5
= gen_reg_rtx (DImode
);
36448 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
36450 tmp6
= gen_reg_rtx (DImode
);
36451 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
36452 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
36455 rs6000_emit_popcount (tmp
, src
);
36456 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
36460 /* Expand an Altivec constant permutation for little endian mode.
36461 There are two issues: First, the two input operands must be
36462 swapped so that together they form a double-wide array in LE
36463 order. Second, the vperm instruction has surprising behavior
36464 in LE mode: it interprets the elements of the source vectors
36465 in BE mode ("left to right") and interprets the elements of
36466 the destination vector in LE mode ("right to left"). To
36467 correct for this, we must subtract each element of the permute
36468 control vector from 31.
36470 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
36471 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
36472 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
36473 serve as the permute control vector. Then, in BE mode,
36477 places the desired result in vr9. However, in LE mode the
36478 vector contents will be
36480 vr10 = 00000003 00000002 00000001 00000000
36481 vr11 = 00000007 00000006 00000005 00000004
36483 The result of the vperm using the same permute control vector is
36485 vr9 = 05000000 07000000 01000000 03000000
36487 That is, the leftmost 4 bytes of vr10 are interpreted as the
36488 source for the rightmost 4 bytes of vr9, and so on.
36490 If we change the permute control vector to
36492 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
36500 vr9 = 00000006 00000004 00000002 00000000. */
36503 altivec_expand_vec_perm_const_le (rtx operands
[4])
36507 rtx constv
, unspec
;
36508 rtx target
= operands
[0];
36509 rtx op0
= operands
[1];
36510 rtx op1
= operands
[2];
36511 rtx sel
= operands
[3];
36513 /* Unpack and adjust the constant selector. */
36514 for (i
= 0; i
< 16; ++i
)
36516 rtx e
= XVECEXP (sel
, 0, i
);
36517 unsigned int elt
= 31 - (INTVAL (e
) & 31);
36518 perm
[i
] = GEN_INT (elt
);
36521 /* Expand to a permute, swapping the inputs and using the
36522 adjusted selector. */
36524 op0
= force_reg (V16QImode
, op0
);
36526 op1
= force_reg (V16QImode
, op1
);
36528 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
36529 constv
= force_reg (V16QImode
, constv
);
36530 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
36532 if (!REG_P (target
))
36534 rtx tmp
= gen_reg_rtx (V16QImode
);
36535 emit_move_insn (tmp
, unspec
);
36539 emit_move_insn (target
, unspec
);
36542 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
36543 permute control vector. But here it's not a constant, so we must
36544 generate a vector NAND or NOR to do the adjustment. */
36547 altivec_expand_vec_perm_le (rtx operands
[4])
36549 rtx notx
, iorx
, unspec
;
36550 rtx target
= operands
[0];
36551 rtx op0
= operands
[1];
36552 rtx op1
= operands
[2];
36553 rtx sel
= operands
[3];
36555 rtx norreg
= gen_reg_rtx (V16QImode
);
36556 machine_mode mode
= GET_MODE (target
);
36558 /* Get everything in regs so the pattern matches. */
36560 op0
= force_reg (mode
, op0
);
36562 op1
= force_reg (mode
, op1
);
36564 sel
= force_reg (V16QImode
, sel
);
36565 if (!REG_P (target
))
36566 tmp
= gen_reg_rtx (mode
);
36568 if (TARGET_P9_VECTOR
)
36570 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op0
, op1
, sel
),
36575 /* Invert the selector with a VNAND if available, else a VNOR.
36576 The VNAND is preferred for future fusion opportunities. */
36577 notx
= gen_rtx_NOT (V16QImode
, sel
);
36578 iorx
= (TARGET_P8_VECTOR
36579 ? gen_rtx_IOR (V16QImode
, notx
, notx
)
36580 : gen_rtx_AND (V16QImode
, notx
, notx
));
36581 emit_insn (gen_rtx_SET (norreg
, iorx
));
36583 /* Permute with operands reversed and adjusted selector. */
36584 unspec
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, op1
, op0
, norreg
),
36588 /* Copy into target, possibly by way of a register. */
36589 if (!REG_P (target
))
36591 emit_move_insn (tmp
, unspec
);
36595 emit_move_insn (target
, unspec
);
36598 /* Expand an Altivec constant permutation. Return true if we match
36599 an efficient implementation; false to fall back to VPERM. */
36602 altivec_expand_vec_perm_const (rtx operands
[4])
36604 struct altivec_perm_insn
{
36605 HOST_WIDE_INT mask
;
36606 enum insn_code impl
;
36607 unsigned char perm
[16];
36609 static const struct altivec_perm_insn patterns
[] = {
36610 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum_direct
,
36611 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
36612 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum_direct
,
36613 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
36614 { OPTION_MASK_ALTIVEC
,
36615 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb_direct
36616 : CODE_FOR_altivec_vmrglb_direct
),
36617 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
36618 { OPTION_MASK_ALTIVEC
,
36619 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh_direct
36620 : CODE_FOR_altivec_vmrglh_direct
),
36621 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
36622 { OPTION_MASK_ALTIVEC
,
36623 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw_direct
36624 : CODE_FOR_altivec_vmrglw_direct
),
36625 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
36626 { OPTION_MASK_ALTIVEC
,
36627 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb_direct
36628 : CODE_FOR_altivec_vmrghb_direct
),
36629 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
36630 { OPTION_MASK_ALTIVEC
,
36631 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh_direct
36632 : CODE_FOR_altivec_vmrghh_direct
),
36633 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
36634 { OPTION_MASK_ALTIVEC
,
36635 (BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw_direct
36636 : CODE_FOR_altivec_vmrghw_direct
),
36637 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
36638 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
36639 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
36640 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
36641 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
36644 unsigned int i
, j
, elt
, which
;
36645 unsigned char perm
[16];
36646 rtx target
, op0
, op1
, sel
, x
;
36649 target
= operands
[0];
36654 /* Unpack the constant selector. */
36655 for (i
= which
= 0; i
< 16; ++i
)
36657 rtx e
= XVECEXP (sel
, 0, i
);
36658 elt
= INTVAL (e
) & 31;
36659 which
|= (elt
< 16 ? 1 : 2);
36663 /* Simplify the constant selector based on operands. */
36667 gcc_unreachable ();
36671 if (!rtx_equal_p (op0
, op1
))
36676 for (i
= 0; i
< 16; ++i
)
36688 /* Look for splat patterns. */
36693 for (i
= 0; i
< 16; ++i
)
36694 if (perm
[i
] != elt
)
36698 if (!BYTES_BIG_ENDIAN
)
36700 emit_insn (gen_altivec_vspltb_direct (target
, op0
, GEN_INT (elt
)));
36706 for (i
= 0; i
< 16; i
+= 2)
36707 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
36711 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
36712 x
= gen_reg_rtx (V8HImode
);
36713 emit_insn (gen_altivec_vsplth_direct (x
, gen_lowpart (V8HImode
, op0
),
36715 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
36722 for (i
= 0; i
< 16; i
+= 4)
36724 || perm
[i
+ 1] != elt
+ 1
36725 || perm
[i
+ 2] != elt
+ 2
36726 || perm
[i
+ 3] != elt
+ 3)
36730 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
36731 x
= gen_reg_rtx (V4SImode
);
36732 emit_insn (gen_altivec_vspltw_direct (x
, gen_lowpart (V4SImode
, op0
),
36734 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
36740 /* Look for merge and pack patterns. */
36741 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
36745 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
36748 elt
= patterns
[j
].perm
[0];
36749 if (perm
[0] == elt
)
36751 else if (perm
[0] == elt
+ 16)
36755 for (i
= 1; i
< 16; ++i
)
36757 elt
= patterns
[j
].perm
[i
];
36759 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
36760 else if (one_vec
&& elt
>= 16)
36762 if (perm
[i
] != elt
)
36767 enum insn_code icode
= patterns
[j
].impl
;
36768 machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
36769 machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
36771 /* For little-endian, don't use vpkuwum and vpkuhum if the
36772 underlying vector type is not V4SI and V8HI, respectively.
36773 For example, using vpkuwum with a V8HI picks up the even
36774 halfwords (BE numbering) when the even halfwords (LE
36775 numbering) are what we need. */
36776 if (!BYTES_BIG_ENDIAN
36777 && icode
== CODE_FOR_altivec_vpkuwum_direct
36778 && ((GET_CODE (op0
) == REG
36779 && GET_MODE (op0
) != V4SImode
)
36780 || (GET_CODE (op0
) == SUBREG
36781 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
36783 if (!BYTES_BIG_ENDIAN
36784 && icode
== CODE_FOR_altivec_vpkuhum_direct
36785 && ((GET_CODE (op0
) == REG
36786 && GET_MODE (op0
) != V8HImode
)
36787 || (GET_CODE (op0
) == SUBREG
36788 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
36791 /* For little-endian, the two input operands must be swapped
36792 (or swapped back) to ensure proper right-to-left numbering
36794 if (swapped
^ !BYTES_BIG_ENDIAN
)
36795 std::swap (op0
, op1
);
36796 if (imode
!= V16QImode
)
36798 op0
= gen_lowpart (imode
, op0
);
36799 op1
= gen_lowpart (imode
, op1
);
36801 if (omode
== V16QImode
)
36804 x
= gen_reg_rtx (omode
);
36805 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
36806 if (omode
!= V16QImode
)
36807 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
36812 if (!BYTES_BIG_ENDIAN
)
36814 altivec_expand_vec_perm_const_le (operands
);
36821 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
36822 Return true if we match an efficient implementation. */
36825 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
36826 unsigned char perm0
, unsigned char perm1
)
36830 /* If both selectors come from the same operand, fold to single op. */
36831 if ((perm0
& 2) == (perm1
& 2))
36838 /* If both operands are equal, fold to simpler permutation. */
36839 if (rtx_equal_p (op0
, op1
))
36842 perm1
= (perm1
& 1) + 2;
36844 /* If the first selector comes from the second operand, swap. */
36845 else if (perm0
& 2)
36851 std::swap (op0
, op1
);
36853 /* If the second selector does not come from the second operand, fail. */
36854 else if ((perm1
& 2) == 0)
36858 if (target
!= NULL
)
36860 machine_mode vmode
, dmode
;
36863 vmode
= GET_MODE (target
);
36864 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
36865 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
36866 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
36867 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
36868 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
36869 emit_insn (gen_rtx_SET (target
, x
));
36875 rs6000_expand_vec_perm_const (rtx operands
[4])
36877 rtx target
, op0
, op1
, sel
;
36878 unsigned char perm0
, perm1
;
36880 target
= operands
[0];
36885 /* Unpack the constant selector. */
36886 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
36887 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
36889 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
36892 /* Test whether a constant permutation is supported. */
36895 rs6000_vectorize_vec_perm_const_ok (machine_mode vmode
,
36896 const unsigned char *sel
)
36898 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
36899 if (TARGET_ALTIVEC
)
36902 /* Check for ps_merge* or evmerge* insns. */
36903 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
36904 || (TARGET_SPE
&& vmode
== V2SImode
))
36906 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
36907 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
36908 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
36914 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
36917 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
36918 machine_mode vmode
, unsigned nelt
, rtx perm
[])
36920 machine_mode imode
;
36924 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
36926 imode
= mode_for_size (GET_MODE_UNIT_BITSIZE (vmode
), MODE_INT
, 0);
36927 imode
= mode_for_vector (imode
, nelt
);
36930 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
36931 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
36933 emit_move_insn (target
, x
);
36936 /* Expand an extract even operation. */
36939 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
36941 machine_mode vmode
= GET_MODE (target
);
36942 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
36945 for (i
= 0; i
< nelt
; i
++)
36946 perm
[i
] = GEN_INT (i
* 2);
36948 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
36951 /* Expand a vector interleave operation. */
36954 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
36956 machine_mode vmode
= GET_MODE (target
);
36957 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
36960 high
= (highp
? 0 : nelt
/ 2);
36961 for (i
= 0; i
< nelt
/ 2; i
++)
36963 perm
[i
* 2] = GEN_INT (i
+ high
);
36964 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
36967 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
36970 /* Scale a V2DF vector SRC by two to the SCALE and place in TGT. */
36972 rs6000_scale_v2df (rtx tgt
, rtx src
, int scale
)
36974 HOST_WIDE_INT
hwi_scale (scale
);
36975 REAL_VALUE_TYPE r_pow
;
36976 rtvec v
= rtvec_alloc (2);
36978 rtx scale_vec
= gen_reg_rtx (V2DFmode
);
36979 (void)real_powi (&r_pow
, DFmode
, &dconst2
, hwi_scale
);
36980 elt
= const_double_from_real_value (r_pow
, DFmode
);
36981 RTVEC_ELT (v
, 0) = elt
;
36982 RTVEC_ELT (v
, 1) = elt
;
36983 rs6000_expand_vector_init (scale_vec
, gen_rtx_PARALLEL (V2DFmode
, v
));
36984 emit_insn (gen_mulv2df3 (tgt
, src
, scale_vec
));
36987 /* Return an RTX representing where to find the function value of a
36988 function returning MODE. */
36990 rs6000_complex_function_value (machine_mode mode
)
36992 unsigned int regno
;
36994 machine_mode inner
= GET_MODE_INNER (mode
);
36995 unsigned int inner_bytes
= GET_MODE_UNIT_SIZE (mode
);
36997 if (TARGET_FLOAT128_TYPE
36999 || (mode
== TCmode
&& TARGET_IEEEQUAD
)))
37000 regno
= ALTIVEC_ARG_RETURN
;
37002 else if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
37003 regno
= FP_ARG_RETURN
;
37007 regno
= GP_ARG_RETURN
;
37009 /* 32-bit is OK since it'll go in r3/r4. */
37010 if (TARGET_32BIT
&& inner_bytes
>= 4)
37011 return gen_rtx_REG (mode
, regno
);
37014 if (inner_bytes
>= 8)
37015 return gen_rtx_REG (mode
, regno
);
37017 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
37019 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
37020 GEN_INT (inner_bytes
));
37021 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
37024 /* Return an rtx describing a return value of MODE as a PARALLEL
37025 in N_ELTS registers, each of mode ELT_MODE, starting at REGNO,
37026 stride REG_STRIDE. */
37029 rs6000_parallel_return (machine_mode mode
,
37030 int n_elts
, machine_mode elt_mode
,
37031 unsigned int regno
, unsigned int reg_stride
)
37033 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
37036 for (i
= 0; i
< n_elts
; i
++)
37038 rtx r
= gen_rtx_REG (elt_mode
, regno
);
37039 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
37040 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
37041 regno
+= reg_stride
;
37047 /* Target hook for TARGET_FUNCTION_VALUE.
37049 On the SPE, both FPs and vectors are returned in r3.
37051 On RS/6000 an integer value is in r3 and a floating-point value is in
37052 fp1, unless -msoft-float. */
37055 rs6000_function_value (const_tree valtype
,
37056 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
37057 bool outgoing ATTRIBUTE_UNUSED
)
37060 unsigned int regno
;
37061 machine_mode elt_mode
;
37064 /* Special handling for structs in darwin64. */
37066 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
37068 CUMULATIVE_ARGS valcum
;
37072 valcum
.fregno
= FP_ARG_MIN_REG
;
37073 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
37074 /* Do a trial code generation as if this were going to be passed as
37075 an argument; if any part goes in memory, we return NULL. */
37076 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
37079 /* Otherwise fall through to standard ABI rules. */
37082 mode
= TYPE_MODE (valtype
);
37084 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
37085 if (rs6000_discover_homogeneous_aggregate (mode
, valtype
, &elt_mode
, &n_elts
))
37087 int first_reg
, n_regs
;
37089 if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (elt_mode
))
37091 /* _Decimal128 must use even/odd register pairs. */
37092 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
37093 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
37097 first_reg
= ALTIVEC_ARG_RETURN
;
37101 return rs6000_parallel_return (mode
, n_elts
, elt_mode
, first_reg
, n_regs
);
37104 /* Some return value types need be split in -mpowerpc64, 32bit ABI. */
37105 if (TARGET_32BIT
&& TARGET_POWERPC64
)
37114 int count
= GET_MODE_SIZE (mode
) / 4;
37115 return rs6000_parallel_return (mode
, count
, SImode
, GP_ARG_RETURN
, 1);
37118 if ((INTEGRAL_TYPE_P (valtype
)
37119 && GET_MODE_BITSIZE (mode
) < (TARGET_32BIT
? 32 : 64))
37120 || POINTER_TYPE_P (valtype
))
37121 mode
= TARGET_32BIT
? SImode
: DImode
;
37123 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
37124 /* _Decimal128 must use an even/odd register pair. */
37125 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
37126 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
37127 && !FLOAT128_VECTOR_P (mode
)
37128 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
37129 regno
= FP_ARG_RETURN
;
37130 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
37131 && targetm
.calls
.split_complex_arg
)
37132 return rs6000_complex_function_value (mode
);
37133 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
37134 return register is used in both cases, and we won't see V2DImode/V2DFmode
37135 for pure altivec, combine the two cases. */
37136 else if ((TREE_CODE (valtype
) == VECTOR_TYPE
|| FLOAT128_VECTOR_P (mode
))
37137 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
37138 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
37139 regno
= ALTIVEC_ARG_RETURN
;
37140 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
37141 && (mode
== DFmode
|| mode
== DCmode
37142 || FLOAT128_IBM_P (mode
) || mode
== TCmode
))
37143 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
37145 regno
= GP_ARG_RETURN
;
37147 return gen_rtx_REG (mode
, regno
);
37150 /* Define how to find the value returned by a library function
37151 assuming the value has mode MODE. */
37153 rs6000_libcall_value (machine_mode mode
)
37155 unsigned int regno
;
37157 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
37158 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
37159 return rs6000_parallel_return (mode
, 2, SImode
, GP_ARG_RETURN
, 1);
37161 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
37162 /* _Decimal128 must use an even/odd register pair. */
37163 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
37164 else if (SCALAR_FLOAT_MODE_NOT_VECTOR_P (mode
)
37165 && TARGET_HARD_FLOAT
&& TARGET_FPRS
37166 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
37167 regno
= FP_ARG_RETURN
;
37168 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
37169 return register is used in both cases, and we won't see V2DImode/V2DFmode
37170 for pure altivec, combine the two cases. */
37171 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
37172 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
37173 regno
= ALTIVEC_ARG_RETURN
;
37174 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
37175 return rs6000_complex_function_value (mode
);
37176 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
37177 && (mode
== DFmode
|| mode
== DCmode
37178 || FLOAT128_IBM_P (mode
) || mode
== TCmode
))
37179 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
37181 regno
= GP_ARG_RETURN
;
37183 return gen_rtx_REG (mode
, regno
);
37187 /* Return true if we use LRA instead of reload pass. */
37189 rs6000_lra_p (void)
37194 /* Given FROM and TO register numbers, say whether this elimination is allowed.
37195 Frame pointer elimination is automatically handled.
37197 For the RS/6000, if frame pointer elimination is being done, we would like
37198 to convert ap into fp, not sp.
37200 We need r30 if -mminimal-toc was specified, and there are constant pool
37204 rs6000_can_eliminate (const int from
, const int to
)
37206 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
37207 ? ! frame_pointer_needed
37208 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
37209 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
37213 /* Define the offset between two registers, FROM to be eliminated and its
37214 replacement TO, at the start of a routine. */
37216 rs6000_initial_elimination_offset (int from
, int to
)
37218 rs6000_stack_t
*info
= rs6000_stack_info ();
37219 HOST_WIDE_INT offset
;
37221 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
37222 offset
= info
->push_p
? 0 : -info
->total_size
;
37223 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
37225 offset
= info
->push_p
? 0 : -info
->total_size
;
37226 if (FRAME_GROWS_DOWNWARD
)
37227 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
37229 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
37230 offset
= FRAME_GROWS_DOWNWARD
37231 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
37233 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
37234 offset
= info
->total_size
;
37235 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
37236 offset
= info
->push_p
? info
->total_size
: 0;
37237 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
37240 gcc_unreachable ();
37246 rs6000_dwarf_register_span (rtx reg
)
37250 unsigned regno
= REGNO (reg
);
37251 machine_mode mode
= GET_MODE (reg
);
37255 && (SPE_VECTOR_MODE (GET_MODE (reg
))
37256 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
37257 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
37262 regno
= REGNO (reg
);
37264 /* The duality of the SPE register size wreaks all kinds of havoc.
37265 This is a way of distinguishing r0 in 32-bits from r0 in
37267 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
37268 gcc_assert (words
<= 4);
37269 for (i
= 0; i
< words
; i
++, regno
++)
37271 if (BYTES_BIG_ENDIAN
)
37273 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
37274 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
37278 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
37279 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ FIRST_SPE_HIGH_REGNO
);
37283 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
37286 /* Fill in sizes for SPE register high parts in table used by unwinder. */
37289 rs6000_init_dwarf_reg_sizes_extra (tree address
)
37294 machine_mode mode
= TYPE_MODE (char_type_node
);
37295 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
37296 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
37297 rtx value
= gen_int_mode (4, mode
);
37299 for (i
= FIRST_SPE_HIGH_REGNO
; i
< LAST_SPE_HIGH_REGNO
+1; i
++)
37301 int column
= DWARF_REG_TO_UNWIND_COLUMN
37302 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
37303 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
37305 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
37309 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
37312 machine_mode mode
= TYPE_MODE (char_type_node
);
37313 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
37314 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
37315 rtx value
= gen_int_mode (16, mode
);
37317 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
37318 The unwinder still needs to know the size of Altivec registers. */
37320 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
37322 int column
= DWARF_REG_TO_UNWIND_COLUMN
37323 (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i
), true));
37324 HOST_WIDE_INT offset
= column
* GET_MODE_SIZE (mode
);
37326 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
37331 /* Map internal gcc register numbers to debug format register numbers.
37332 FORMAT specifies the type of debug register number to use:
37333 0 -- debug information, except for frame-related sections
37334 1 -- DWARF .debug_frame section
37335 2 -- DWARF .eh_frame section */
37338 rs6000_dbx_register_number (unsigned int regno
, unsigned int format
)
37340 /* We never use the GCC internal number for SPE high registers.
37341 Those are mapped to the 1200..1231 range for all debug formats. */
37342 if (SPE_HIGH_REGNO_P (regno
))
37343 return regno
- FIRST_SPE_HIGH_REGNO
+ 1200;
37345 /* Except for the above, we use the internal number for non-DWARF
37346 debug information, and also for .eh_frame. */
37347 if ((format
== 0 && write_symbols
!= DWARF2_DEBUG
) || format
== 2)
37350 /* On some platforms, we use the standard DWARF register
37351 numbering for .debug_info and .debug_frame. */
37352 #ifdef RS6000_USE_DWARF_NUMBERING
37355 if (regno
== LR_REGNO
)
37357 if (regno
== CTR_REGNO
)
37359 /* Special handling for CR for .debug_frame: rs6000_emit_prologue has
37360 translated any combination of CR2, CR3, CR4 saves to a save of CR2.
37361 The actual code emitted saves the whole of CR, so we map CR2_REGNO
37362 to the DWARF reg for CR. */
37363 if (format
== 1 && regno
== CR2_REGNO
)
37365 if (CR_REGNO_P (regno
))
37366 return regno
- CR0_REGNO
+ 86;
37367 if (regno
== CA_REGNO
)
37368 return 101; /* XER */
37369 if (ALTIVEC_REGNO_P (regno
))
37370 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
37371 if (regno
== VRSAVE_REGNO
)
37373 if (regno
== VSCR_REGNO
)
37375 if (regno
== SPE_ACC_REGNO
)
37377 if (regno
== SPEFSCR_REGNO
)
37383 /* target hook eh_return_filter_mode */
37384 static machine_mode
37385 rs6000_eh_return_filter_mode (void)
37387 return TARGET_32BIT
? SImode
: word_mode
;
37390 /* Target hook for scalar_mode_supported_p. */
37392 rs6000_scalar_mode_supported_p (machine_mode mode
)
37394 /* -m32 does not support TImode. This is the default, from
37395 default_scalar_mode_supported_p. For -m32 -mpowerpc64 we want the
37396 same ABI as for -m32. But default_scalar_mode_supported_p allows
37397 integer modes of precision 2 * BITS_PER_WORD, which matches TImode
37398 for -mpowerpc64. */
37399 if (TARGET_32BIT
&& mode
== TImode
)
37402 if (DECIMAL_FLOAT_MODE_P (mode
))
37403 return default_decimal_float_supported_p ();
37404 else if (TARGET_FLOAT128_TYPE
&& (mode
== KFmode
|| mode
== IFmode
))
37407 return default_scalar_mode_supported_p (mode
);
37410 /* Target hook for vector_mode_supported_p. */
37412 rs6000_vector_mode_supported_p (machine_mode mode
)
37415 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
37418 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
37421 /* There is no vector form for IEEE 128-bit. If we return true for IEEE
37422 128-bit, the compiler might try to widen IEEE 128-bit to IBM
37424 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
) && !FLOAT128_IEEE_P (mode
))
37431 /* Target hook for floatn_mode. */
37432 static machine_mode
37433 rs6000_floatn_mode (int n
, bool extended
)
37443 if (TARGET_FLOAT128_KEYWORD
)
37444 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
37452 /* Those are the only valid _FloatNx types. */
37453 gcc_unreachable ();
37467 if (TARGET_FLOAT128_KEYWORD
)
37468 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
37479 /* Target hook for c_mode_for_suffix. */
37480 static machine_mode
37481 rs6000_c_mode_for_suffix (char suffix
)
37483 if (TARGET_FLOAT128_TYPE
)
37485 if (suffix
== 'q' || suffix
== 'Q')
37486 return (FLOAT128_IEEE_P (TFmode
)) ? TFmode
: KFmode
;
37488 /* At the moment, we are not defining a suffix for IBM extended double.
37489 If/when the default for -mabi=ieeelongdouble is changed, and we want
37490 to support __ibm128 constants in legacy library code, we may need to
37491 re-evalaute this decision. Currently, c-lex.c only supports 'w' and
37492 'q' as machine dependent suffixes. The x86_64 port uses 'w' for
37493 __float80 constants. */
37499 /* Target hook for invalid_arg_for_unprototyped_fn. */
37500 static const char *
37501 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
37503 return (!rs6000_darwin64_abi
37505 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
37506 && (funcdecl
== NULL_TREE
37507 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
37508 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
37509 ? N_("AltiVec argument passed to unprototyped function")
37513 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
37514 setup by using __stack_chk_fail_local hidden function instead of
37515 calling __stack_chk_fail directly. Otherwise it is better to call
37516 __stack_chk_fail directly. */
37518 static tree ATTRIBUTE_UNUSED
37519 rs6000_stack_protect_fail (void)
37521 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
37522 ? default_hidden_stack_protect_fail ()
37523 : default_external_stack_protect_fail ();
37527 rs6000_final_prescan_insn (rtx_insn
*insn
, rtx
*operand ATTRIBUTE_UNUSED
,
37528 int num_operands ATTRIBUTE_UNUSED
)
37530 if (rs6000_warn_cell_microcode
)
37533 int insn_code_number
= recog_memoized (insn
);
37534 location_t location
= INSN_LOCATION (insn
);
37536 /* Punt on insns we cannot recognize. */
37537 if (insn_code_number
< 0)
37540 temp
= get_insn_template (insn_code_number
, insn
);
37542 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
37543 warning_at (location
, OPT_mwarn_cell_microcode
,
37544 "emitting microcode insn %s\t[%s] #%d",
37545 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
37546 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
37547 warning_at (location
, OPT_mwarn_cell_microcode
,
37548 "emitting conditional microcode insn %s\t[%s] #%d",
37549 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
37553 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
37556 static unsigned HOST_WIDE_INT
37557 rs6000_asan_shadow_offset (void)
37559 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
37563 /* Mask options that we want to support inside of attribute((target)) and
37564 #pragma GCC target operations. Note, we do not include things like
37565 64/32-bit, endianess, hard/soft floating point, etc. that would have
37566 different calling sequences. */
37568 struct rs6000_opt_mask
{
37569 const char *name
; /* option name */
37570 HOST_WIDE_INT mask
; /* mask to set */
37571 bool invert
; /* invert sense of mask */
37572 bool valid_target
; /* option is a target option */
37575 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
37577 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
37578 { "cmpb", OPTION_MASK_CMPB
, false, true },
37579 { "crypto", OPTION_MASK_CRYPTO
, false, true },
37580 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
37581 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
37582 { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX
,
37584 { "float128", OPTION_MASK_FLOAT128_KEYWORD
, false, false },
37585 { "float128-type", OPTION_MASK_FLOAT128_TYPE
, false, false },
37586 { "float128-hardware", OPTION_MASK_FLOAT128_HW
, false, false },
37587 { "fprnd", OPTION_MASK_FPRND
, false, true },
37588 { "hard-dfp", OPTION_MASK_DFP
, false, true },
37589 { "htm", OPTION_MASK_HTM
, false, true },
37590 { "isel", OPTION_MASK_ISEL
, false, true },
37591 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
37592 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
37593 { "modulo", OPTION_MASK_MODULO
, false, true },
37594 { "mulhw", OPTION_MASK_MULHW
, false, true },
37595 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
37596 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
37597 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
37598 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
37599 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
37600 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
37601 { "power9-dform-scalar", OPTION_MASK_P9_DFORM_SCALAR
, false, true },
37602 { "power9-dform-vector", OPTION_MASK_P9_DFORM_VECTOR
, false, true },
37603 { "power9-fusion", OPTION_MASK_P9_FUSION
, false, true },
37604 { "power9-minmax", OPTION_MASK_P9_MINMAX
, false, true },
37605 { "power9-misc", OPTION_MASK_P9_MISC
, false, true },
37606 { "power9-vector", OPTION_MASK_P9_VECTOR
, false, true },
37607 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
37608 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
37609 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
37610 { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC
, false, true },
37611 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
37612 { "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT
, false, true },
37613 { "string", OPTION_MASK_STRING
, false, true },
37614 { "toc-fusion", OPTION_MASK_TOC_FUSION
, false, true },
37615 { "update", OPTION_MASK_NO_UPDATE
, true , true },
37616 { "upper-regs-di", OPTION_MASK_UPPER_REGS_DI
, false, true },
37617 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, true },
37618 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, true },
37619 { "vsx", OPTION_MASK_VSX
, false, true },
37620 { "vsx-small-integer", OPTION_MASK_VSX_SMALL_INTEGER
, false, true },
37621 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
37622 #ifdef OPTION_MASK_64BIT
37624 { "aix64", OPTION_MASK_64BIT
, false, false },
37625 { "aix32", OPTION_MASK_64BIT
, true, false },
37627 { "64", OPTION_MASK_64BIT
, false, false },
37628 { "32", OPTION_MASK_64BIT
, true, false },
37631 #ifdef OPTION_MASK_EABI
37632 { "eabi", OPTION_MASK_EABI
, false, false },
37634 #ifdef OPTION_MASK_LITTLE_ENDIAN
37635 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
37636 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
37638 #ifdef OPTION_MASK_RELOCATABLE
37639 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
37641 #ifdef OPTION_MASK_STRICT_ALIGN
37642 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
37644 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
37645 { "string", OPTION_MASK_STRING
, false, false },
37648 /* Builtin mask mapping for printing the flags. */
37649 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
37651 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
37652 { "vsx", RS6000_BTM_VSX
, false, false },
37653 { "spe", RS6000_BTM_SPE
, false, false },
37654 { "paired", RS6000_BTM_PAIRED
, false, false },
37655 { "fre", RS6000_BTM_FRE
, false, false },
37656 { "fres", RS6000_BTM_FRES
, false, false },
37657 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
37658 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
37659 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
37660 { "cell", RS6000_BTM_CELL
, false, false },
37661 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
37662 { "power9-vector", RS6000_BTM_P9_VECTOR
, false, false },
37663 { "power9-misc", RS6000_BTM_P9_MISC
, false, false },
37664 { "crypto", RS6000_BTM_CRYPTO
, false, false },
37665 { "htm", RS6000_BTM_HTM
, false, false },
37666 { "hard-dfp", RS6000_BTM_DFP
, false, false },
37667 { "hard-float", RS6000_BTM_HARD_FLOAT
, false, false },
37668 { "long-double-128", RS6000_BTM_LDBL128
, false, false },
37669 { "float128", RS6000_BTM_FLOAT128
, false, false },
37672 /* Option variables that we want to support inside attribute((target)) and
37673 #pragma GCC target operations. */
37675 struct rs6000_opt_var
{
37676 const char *name
; /* option name */
37677 size_t global_offset
; /* offset of the option in global_options. */
37678 size_t target_offset
; /* offset of the option in target options. */
37681 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
37684 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
37685 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
37686 { "avoid-indexed-addresses",
37687 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
37688 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
37690 offsetof (struct gcc_options
, x_rs6000_paired_float
),
37691 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
37693 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
37694 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
37695 { "optimize-swaps",
37696 offsetof (struct gcc_options
, x_rs6000_optimize_swaps
),
37697 offsetof (struct cl_target_option
, x_rs6000_optimize_swaps
), },
37698 { "allow-movmisalign",
37699 offsetof (struct gcc_options
, x_TARGET_ALLOW_MOVMISALIGN
),
37700 offsetof (struct cl_target_option
, x_TARGET_ALLOW_MOVMISALIGN
), },
37701 { "allow-df-permute",
37702 offsetof (struct gcc_options
, x_TARGET_ALLOW_DF_PERMUTE
),
37703 offsetof (struct cl_target_option
, x_TARGET_ALLOW_DF_PERMUTE
), },
37705 offsetof (struct gcc_options
, x_TARGET_SCHED_GROUPS
),
37706 offsetof (struct cl_target_option
, x_TARGET_SCHED_GROUPS
), },
37708 offsetof (struct gcc_options
, x_TARGET_ALWAYS_HINT
),
37709 offsetof (struct cl_target_option
, x_TARGET_ALWAYS_HINT
), },
37710 { "align-branch-targets",
37711 offsetof (struct gcc_options
, x_TARGET_ALIGN_BRANCH_TARGETS
),
37712 offsetof (struct cl_target_option
, x_TARGET_ALIGN_BRANCH_TARGETS
), },
37713 { "vectorize-builtins",
37714 offsetof (struct gcc_options
, x_TARGET_VECTORIZE_BUILTINS
),
37715 offsetof (struct cl_target_option
, x_TARGET_VECTORIZE_BUILTINS
), },
37717 offsetof (struct gcc_options
, x_tls_markers
),
37718 offsetof (struct cl_target_option
, x_tls_markers
), },
37720 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
37721 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
37723 offsetof (struct gcc_options
, x_TARGET_SCHED_PROLOG
),
37724 offsetof (struct cl_target_option
, x_TARGET_SCHED_PROLOG
), },
37725 { "gen-cell-microcode",
37726 offsetof (struct gcc_options
, x_rs6000_gen_cell_microcode
),
37727 offsetof (struct cl_target_option
, x_rs6000_gen_cell_microcode
), },
37728 { "warn-cell-microcode",
37729 offsetof (struct gcc_options
, x_rs6000_warn_cell_microcode
),
37730 offsetof (struct cl_target_option
, x_rs6000_warn_cell_microcode
), },
37733 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
37734 parsing. Return true if there were no errors. */
37737 rs6000_inner_target_options (tree args
, bool attr_p
)
37741 if (args
== NULL_TREE
)
37744 else if (TREE_CODE (args
) == STRING_CST
)
37746 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
37749 while ((q
= strtok (p
, ",")) != NULL
)
37751 bool error_p
= false;
37752 bool not_valid_p
= false;
37753 const char *cpu_opt
= NULL
;
37756 if (strncmp (q
, "cpu=", 4) == 0)
37758 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
37759 if (cpu_index
>= 0)
37760 rs6000_cpu_index
= cpu_index
;
37767 else if (strncmp (q
, "tune=", 5) == 0)
37769 int tune_index
= rs6000_cpu_name_lookup (q
+5);
37770 if (tune_index
>= 0)
37771 rs6000_tune_index
= tune_index
;
37781 bool invert
= false;
37785 if (strncmp (r
, "no-", 3) == 0)
37791 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
37792 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
37794 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
37796 if (!rs6000_opt_masks
[i
].valid_target
)
37797 not_valid_p
= true;
37801 rs6000_isa_flags_explicit
|= mask
;
37803 /* VSX needs altivec, so -mvsx automagically sets
37804 altivec and disables -mavoid-indexed-addresses. */
37807 if (mask
== OPTION_MASK_VSX
)
37809 mask
|= OPTION_MASK_ALTIVEC
;
37810 TARGET_AVOID_XFORM
= 0;
37814 if (rs6000_opt_masks
[i
].invert
)
37818 rs6000_isa_flags
&= ~mask
;
37820 rs6000_isa_flags
|= mask
;
37825 if (error_p
&& !not_valid_p
)
37827 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
37828 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
37830 size_t j
= rs6000_opt_vars
[i
].global_offset
;
37831 *((int *) ((char *)&global_options
+ j
)) = !invert
;
37833 not_valid_p
= false;
37841 const char *eprefix
, *esuffix
;
37846 eprefix
= "__attribute__((__target__(";
37851 eprefix
= "#pragma GCC target ";
37856 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
37858 else if (not_valid_p
)
37859 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
37861 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
37866 else if (TREE_CODE (args
) == TREE_LIST
)
37870 tree value
= TREE_VALUE (args
);
37873 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
37877 args
= TREE_CHAIN (args
);
37879 while (args
!= NULL_TREE
);
37883 gcc_unreachable ();
37888 /* Print out the target options as a list for -mdebug=target. */
37891 rs6000_debug_target_options (tree args
, const char *prefix
)
37893 if (args
== NULL_TREE
)
37894 fprintf (stderr
, "%s<NULL>", prefix
);
37896 else if (TREE_CODE (args
) == STRING_CST
)
37898 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
37901 while ((q
= strtok (p
, ",")) != NULL
)
37904 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
37909 else if (TREE_CODE (args
) == TREE_LIST
)
37913 tree value
= TREE_VALUE (args
);
37916 rs6000_debug_target_options (value
, prefix
);
37919 args
= TREE_CHAIN (args
);
37921 while (args
!= NULL_TREE
);
37925 gcc_unreachable ();
37931 /* Hook to validate attribute((target("..."))). */
37934 rs6000_valid_attribute_p (tree fndecl
,
37935 tree
ARG_UNUSED (name
),
37939 struct cl_target_option cur_target
;
37941 tree old_optimize
= build_optimization_node (&global_options
);
37942 tree new_target
, new_optimize
;
37943 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
37945 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
37947 if (TARGET_DEBUG_TARGET
)
37949 tree tname
= DECL_NAME (fndecl
);
37950 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
37952 fprintf (stderr
, "function: %.*s\n",
37953 (int) IDENTIFIER_LENGTH (tname
),
37954 IDENTIFIER_POINTER (tname
));
37956 fprintf (stderr
, "function: unknown\n");
37958 fprintf (stderr
, "args:");
37959 rs6000_debug_target_options (args
, " ");
37960 fprintf (stderr
, "\n");
37963 fprintf (stderr
, "flags: 0x%x\n", flags
);
37965 fprintf (stderr
, "--------------------\n");
37968 old_optimize
= build_optimization_node (&global_options
);
37969 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
37971 /* If the function changed the optimization levels as well as setting target
37972 options, start with the optimizations specified. */
37973 if (func_optimize
&& func_optimize
!= old_optimize
)
37974 cl_optimization_restore (&global_options
,
37975 TREE_OPTIMIZATION (func_optimize
));
37977 /* The target attributes may also change some optimization flags, so update
37978 the optimization options if necessary. */
37979 cl_target_option_save (&cur_target
, &global_options
);
37980 rs6000_cpu_index
= rs6000_tune_index
= -1;
37981 ret
= rs6000_inner_target_options (args
, true);
37983 /* Set up any additional state. */
37986 ret
= rs6000_option_override_internal (false);
37987 new_target
= build_target_option_node (&global_options
);
37992 new_optimize
= build_optimization_node (&global_options
);
37999 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
38001 if (old_optimize
!= new_optimize
)
38002 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
38005 cl_target_option_restore (&global_options
, &cur_target
);
38007 if (old_optimize
!= new_optimize
)
38008 cl_optimization_restore (&global_options
,
38009 TREE_OPTIMIZATION (old_optimize
));
38015 /* Hook to validate the current #pragma GCC target and set the state, and
38016 update the macros based on what was changed. If ARGS is NULL, then
38017 POP_TARGET is used to reset the options. */
38020 rs6000_pragma_target_parse (tree args
, tree pop_target
)
38022 tree prev_tree
= build_target_option_node (&global_options
);
38024 struct cl_target_option
*prev_opt
, *cur_opt
;
38025 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
38026 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
38028 if (TARGET_DEBUG_TARGET
)
38030 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
38031 fprintf (stderr
, "args:");
38032 rs6000_debug_target_options (args
, " ");
38033 fprintf (stderr
, "\n");
38037 fprintf (stderr
, "pop_target:\n");
38038 debug_tree (pop_target
);
38041 fprintf (stderr
, "pop_target: <NULL>\n");
38043 fprintf (stderr
, "--------------------\n");
38048 cur_tree
= ((pop_target
)
38050 : target_option_default_node
);
38051 cl_target_option_restore (&global_options
,
38052 TREE_TARGET_OPTION (cur_tree
));
38056 rs6000_cpu_index
= rs6000_tune_index
= -1;
38057 if (!rs6000_inner_target_options (args
, false)
38058 || !rs6000_option_override_internal (false)
38059 || (cur_tree
= build_target_option_node (&global_options
))
38062 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
38063 fprintf (stderr
, "invalid pragma\n");
38069 target_option_current_node
= cur_tree
;
38071 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
38072 change the macros that are defined. */
38073 if (rs6000_target_modify_macros_ptr
)
38075 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
38076 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
38077 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
38079 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
38080 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
38081 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
38083 diff_bumask
= (prev_bumask
^ cur_bumask
);
38084 diff_flags
= (prev_flags
^ cur_flags
);
38086 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
38088 /* Delete old macros. */
38089 rs6000_target_modify_macros_ptr (false,
38090 prev_flags
& diff_flags
,
38091 prev_bumask
& diff_bumask
);
38093 /* Define new macros. */
38094 rs6000_target_modify_macros_ptr (true,
38095 cur_flags
& diff_flags
,
38096 cur_bumask
& diff_bumask
);
38104 /* Remember the last target of rs6000_set_current_function. */
38105 static GTY(()) tree rs6000_previous_fndecl
;
38107 /* Establish appropriate back-end context for processing the function
38108 FNDECL. The argument might be NULL to indicate processing at top
38109 level, outside of any function scope. */
38111 rs6000_set_current_function (tree fndecl
)
38113 tree old_tree
= (rs6000_previous_fndecl
38114 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
38117 tree new_tree
= (fndecl
38118 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
38121 if (TARGET_DEBUG_TARGET
)
38123 bool print_final
= false;
38124 fprintf (stderr
, "\n==================== rs6000_set_current_function");
38127 fprintf (stderr
, ", fndecl %s (%p)",
38128 (DECL_NAME (fndecl
)
38129 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
38130 : "<unknown>"), (void *)fndecl
);
38132 if (rs6000_previous_fndecl
)
38133 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
38135 fprintf (stderr
, "\n");
38138 fprintf (stderr
, "\nnew fndecl target specific options:\n");
38139 debug_tree (new_tree
);
38140 print_final
= true;
38145 fprintf (stderr
, "\nold fndecl target specific options:\n");
38146 debug_tree (old_tree
);
38147 print_final
= true;
38151 fprintf (stderr
, "--------------------\n");
38154 /* Only change the context if the function changes. This hook is called
38155 several times in the course of compiling a function, and we don't want to
38156 slow things down too much or call target_reinit when it isn't safe. */
38157 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
38159 rs6000_previous_fndecl
= fndecl
;
38160 if (old_tree
== new_tree
)
38163 else if (new_tree
&& new_tree
!= target_option_default_node
)
38165 cl_target_option_restore (&global_options
,
38166 TREE_TARGET_OPTION (new_tree
));
38167 if (TREE_TARGET_GLOBALS (new_tree
))
38168 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
38170 TREE_TARGET_GLOBALS (new_tree
)
38171 = save_target_globals_default_opts ();
38174 else if (old_tree
&& old_tree
!= target_option_default_node
)
38176 new_tree
= target_option_current_node
;
38177 cl_target_option_restore (&global_options
,
38178 TREE_TARGET_OPTION (new_tree
));
38179 if (TREE_TARGET_GLOBALS (new_tree
))
38180 restore_target_globals (TREE_TARGET_GLOBALS (new_tree
));
38181 else if (new_tree
== target_option_default_node
)
38182 restore_target_globals (&default_target_globals
);
38184 TREE_TARGET_GLOBALS (new_tree
)
38185 = save_target_globals_default_opts ();
38191 /* Save the current options */
38194 rs6000_function_specific_save (struct cl_target_option
*ptr
,
38195 struct gcc_options
*opts
)
38197 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
38198 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
38201 /* Restore the current options */
38204 rs6000_function_specific_restore (struct gcc_options
*opts
,
38205 struct cl_target_option
*ptr
)
38208 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
38209 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
38210 (void) rs6000_option_override_internal (false);
38213 /* Print the current options */
38216 rs6000_function_specific_print (FILE *file
, int indent
,
38217 struct cl_target_option
*ptr
)
38219 rs6000_print_isa_options (file
, indent
, "Isa options set",
38220 ptr
->x_rs6000_isa_flags
);
38222 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
38223 ptr
->x_rs6000_isa_flags_explicit
);
38226 /* Helper function to print the current isa or misc options on a line. */
38229 rs6000_print_options_internal (FILE *file
,
38231 const char *string
,
38232 HOST_WIDE_INT flags
,
38233 const char *prefix
,
38234 const struct rs6000_opt_mask
*opts
,
38235 size_t num_elements
)
38238 size_t start_column
= 0;
38240 size_t max_column
= 120;
38241 size_t prefix_len
= strlen (prefix
);
38242 size_t comma_len
= 0;
38243 const char *comma
= "";
38246 start_column
+= fprintf (file
, "%*s", indent
, "");
38250 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
38254 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
38256 /* Print the various mask options. */
38257 cur_column
= start_column
;
38258 for (i
= 0; i
< num_elements
; i
++)
38260 bool invert
= opts
[i
].invert
;
38261 const char *name
= opts
[i
].name
;
38262 const char *no_str
= "";
38263 HOST_WIDE_INT mask
= opts
[i
].mask
;
38264 size_t len
= comma_len
+ prefix_len
+ strlen (name
);
38268 if ((flags
& mask
) == 0)
38271 len
+= sizeof ("no-") - 1;
38279 if ((flags
& mask
) != 0)
38282 len
+= sizeof ("no-") - 1;
38289 if (cur_column
> max_column
)
38291 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
38292 cur_column
= start_column
+ len
;
38296 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
, name
);
38298 comma_len
= sizeof (", ") - 1;
38301 fputs ("\n", file
);
38304 /* Helper function to print the current isa options on a line. */
38307 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
38308 HOST_WIDE_INT flags
)
38310 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
38311 &rs6000_opt_masks
[0],
38312 ARRAY_SIZE (rs6000_opt_masks
));
38316 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
38317 HOST_WIDE_INT flags
)
38319 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
38320 &rs6000_builtin_mask_names
[0],
38321 ARRAY_SIZE (rs6000_builtin_mask_names
));
38325 /* Hook to determine if one function can safely inline another. */
38328 rs6000_can_inline_p (tree caller
, tree callee
)
38331 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
38332 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
38334 /* If callee has no option attributes, then it is ok to inline. */
38338 /* If caller has no option attributes, but callee does then it is not ok to
38340 else if (!caller_tree
)
38345 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
38346 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
38348 /* Callee's options should a subset of the caller's, i.e. a vsx function
38349 can inline an altivec function but a non-vsx function can't inline a
38351 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
38352 == callee_opts
->x_rs6000_isa_flags
)
38356 if (TARGET_DEBUG_TARGET
)
38357 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
38358 (DECL_NAME (caller
)
38359 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
38361 (DECL_NAME (callee
)
38362 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
38364 (ret
? "can" : "cannot"));
38369 /* Allocate a stack temp and fixup the address so it meets the particular
38370 memory requirements (either offetable or REG+REG addressing). */
38373 rs6000_allocate_stack_temp (machine_mode mode
,
38374 bool offsettable_p
,
38377 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
38378 rtx addr
= XEXP (stack
, 0);
38379 int strict_p
= (reload_in_progress
|| reload_completed
);
38381 if (!legitimate_indirect_address_p (addr
, strict_p
))
38384 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
38385 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
38387 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
38388 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
38394 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
38395 to such a form to deal with memory reference instructions like STFIWX that
38396 only take reg+reg addressing. */
38399 rs6000_address_for_fpconvert (rtx x
)
38401 int strict_p
= (reload_in_progress
|| reload_completed
);
38404 gcc_assert (MEM_P (x
));
38405 addr
= XEXP (x
, 0);
38406 if (! legitimate_indirect_address_p (addr
, strict_p
)
38407 && ! legitimate_indexed_address_p (addr
, strict_p
))
38409 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
38411 rtx reg
= XEXP (addr
, 0);
38412 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
38413 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
38414 gcc_assert (REG_P (reg
));
38415 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
38418 else if (GET_CODE (addr
) == PRE_MODIFY
)
38420 rtx reg
= XEXP (addr
, 0);
38421 rtx expr
= XEXP (addr
, 1);
38422 gcc_assert (REG_P (reg
));
38423 gcc_assert (GET_CODE (expr
) == PLUS
);
38424 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
38428 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
38434 /* Given a memory reference, if it is not in the form for altivec memory
38435 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
38436 convert to the altivec format. */
38439 rs6000_address_for_altivec (rtx x
)
38441 gcc_assert (MEM_P (x
));
38442 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
38444 rtx addr
= XEXP (x
, 0);
38445 int strict_p
= (reload_in_progress
|| reload_completed
);
38447 if (!legitimate_indexed_address_p (addr
, strict_p
)
38448 && !legitimate_indirect_address_p (addr
, strict_p
))
38449 addr
= copy_to_mode_reg (Pmode
, addr
);
38451 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
38452 x
= change_address (x
, GET_MODE (x
), addr
);
38458 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
38460 On the RS/6000, all integer constants are acceptable, most won't be valid
38461 for particular insns, though. Only easy FP constants are acceptable. */
38464 rs6000_legitimate_constant_p (machine_mode mode
, rtx x
)
38466 if (TARGET_ELF
&& tls_referenced_p (x
))
38469 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
38470 || GET_MODE (x
) == VOIDmode
38471 || (TARGET_POWERPC64
&& mode
== DImode
)
38472 || easy_fp_constant (x
, mode
)
38473 || easy_vector_constant (x
, mode
));
38477 /* Return TRUE iff the sequence ending in LAST sets the static chain. */
38480 chain_already_loaded (rtx_insn
*last
)
38482 for (; last
!= NULL
; last
= PREV_INSN (last
))
38484 if (NONJUMP_INSN_P (last
))
38486 rtx patt
= PATTERN (last
);
38488 if (GET_CODE (patt
) == SET
)
38490 rtx lhs
= XEXP (patt
, 0);
38492 if (REG_P (lhs
) && REGNO (lhs
) == STATIC_CHAIN_REGNUM
)
38500 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
38503 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
38505 const bool direct_call_p
38506 = GET_CODE (func_desc
) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (func_desc
);
38507 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
38508 rtx toc_load
= NULL_RTX
;
38509 rtx toc_restore
= NULL_RTX
;
38511 rtx abi_reg
= NULL_RTX
;
38516 /* Handle longcall attributes. */
38517 if (INTVAL (cookie
) & CALL_LONG
)
38518 func_desc
= rs6000_longcall_ref (func_desc
);
38520 /* Handle indirect calls. */
38521 if (GET_CODE (func_desc
) != SYMBOL_REF
38522 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
38524 /* Save the TOC into its reserved slot before the call,
38525 and prepare to restore it after the call. */
38526 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
38527 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
38528 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
38529 gen_rtx_PLUS (Pmode
, stack_ptr
,
38530 stack_toc_offset
));
38531 rtx stack_toc_unspec
= gen_rtx_UNSPEC (Pmode
,
38532 gen_rtvec (1, stack_toc_offset
),
38534 toc_restore
= gen_rtx_SET (toc_reg
, stack_toc_unspec
);
38536 /* Can we optimize saving the TOC in the prologue or
38537 do we need to do it at every call? */
38538 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
38539 cfun
->machine
->save_toc_in_prologue
= true;
38542 MEM_VOLATILE_P (stack_toc_mem
) = 1;
38543 emit_move_insn (stack_toc_mem
, toc_reg
);
38546 if (DEFAULT_ABI
== ABI_ELFv2
)
38548 /* A function pointer in the ELFv2 ABI is just a plain address, but
38549 the ABI requires it to be loaded into r12 before the call. */
38550 func_addr
= gen_rtx_REG (Pmode
, 12);
38551 emit_move_insn (func_addr
, func_desc
);
38552 abi_reg
= func_addr
;
38556 /* A function pointer under AIX is a pointer to a data area whose
38557 first word contains the actual address of the function, whose
38558 second word contains a pointer to its TOC, and whose third word
38559 contains a value to place in the static chain register (r11).
38560 Note that if we load the static chain, our "trampoline" need
38561 not have any executable code. */
38563 /* Load up address of the actual function. */
38564 func_desc
= force_reg (Pmode
, func_desc
);
38565 func_addr
= gen_reg_rtx (Pmode
);
38566 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
38568 /* Prepare to load the TOC of the called function. Note that the
38569 TOC load must happen immediately before the actual call so
38570 that unwinding the TOC registers works correctly. See the
38571 comment in frob_update_context. */
38572 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
38573 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
38574 gen_rtx_PLUS (Pmode
, func_desc
,
38576 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
38578 /* If we have a static chain, load it up. But, if the call was
38579 originally direct, the 3rd word has not been written since no
38580 trampoline has been built, so we ought not to load it, lest we
38581 override a static chain value. */
38583 && TARGET_POINTERS_TO_NESTED_FUNCTIONS
38584 && !chain_already_loaded (get_current_sequence ()->next
->last
))
38586 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
38587 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
38588 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
38589 gen_rtx_PLUS (Pmode
, func_desc
,
38591 emit_move_insn (sc_reg
, func_sc_mem
);
38598 /* Direct calls use the TOC: for local calls, the callee will
38599 assume the TOC register is set; for non-local calls, the
38600 PLT stub needs the TOC register. */
38602 func_addr
= func_desc
;
38605 /* Create the call. */
38606 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
38607 if (value
!= NULL_RTX
)
38608 call
[0] = gen_rtx_SET (value
, call
[0]);
38612 call
[n_call
++] = toc_load
;
38614 call
[n_call
++] = toc_restore
;
38616 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
38618 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
38619 insn
= emit_call_insn (insn
);
38621 /* Mention all registers defined by the ABI to hold information
38622 as uses in CALL_INSN_FUNCTION_USAGE. */
38624 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
38627 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
38630 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
38635 gcc_assert (INTVAL (cookie
) == 0);
38637 /* Create the call. */
38638 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
38639 if (value
!= NULL_RTX
)
38640 call
[0] = gen_rtx_SET (value
, call
[0]);
38642 call
[1] = simple_return_rtx
;
38644 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
38645 insn
= emit_call_insn (insn
);
38647 /* Note use of the TOC register. */
38648 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
38651 /* Return whether we need to always update the saved TOC pointer when we update
38652 the stack pointer. */
38655 rs6000_save_toc_in_prologue_p (void)
38657 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
38660 #ifdef HAVE_GAS_HIDDEN
38661 # define USE_HIDDEN_LINKONCE 1
38663 # define USE_HIDDEN_LINKONCE 0
38666 /* Fills in the label name that should be used for a 476 link stack thunk. */
38669 get_ppc476_thunk_name (char name
[32])
38671 gcc_assert (TARGET_LINK_STACK
);
38673 if (USE_HIDDEN_LINKONCE
)
38674 sprintf (name
, "__ppc476.get_thunk");
38676 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
38679 /* This function emits the simple thunk routine that is used to preserve
38680 the link stack on the 476 cpu. */
38682 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
38684 rs6000_code_end (void)
38689 if (!TARGET_LINK_STACK
)
38692 get_ppc476_thunk_name (name
);
38694 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
38695 build_function_type_list (void_type_node
, NULL_TREE
));
38696 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
38697 NULL_TREE
, void_type_node
);
38698 TREE_PUBLIC (decl
) = 1;
38699 TREE_STATIC (decl
) = 1;
38702 if (USE_HIDDEN_LINKONCE
)
38704 cgraph_node::create (decl
)->set_comdat_group (DECL_ASSEMBLER_NAME (decl
));
38705 targetm
.asm_out
.unique_section (decl
, 0);
38706 switch_to_section (get_named_section (decl
, NULL
, 0));
38707 DECL_WEAK (decl
) = 1;
38708 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
38709 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
38710 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
38711 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
38716 switch_to_section (text_section
);
38717 ASM_OUTPUT_LABEL (asm_out_file
, name
);
38720 DECL_INITIAL (decl
) = make_node (BLOCK
);
38721 current_function_decl
= decl
;
38722 allocate_struct_function (decl
, false);
38723 init_function_start (decl
);
38724 first_function_block_is_cold
= false;
38725 /* Make sure unwind info is emitted for the thunk if needed. */
38726 final_start_function (emit_barrier (), asm_out_file
, 1);
38728 fputs ("\tblr\n", asm_out_file
);
38730 final_end_function ();
38731 init_insn_lengths ();
38732 free_after_compilation (cfun
);
38734 current_function_decl
= NULL
;
38737 /* Add r30 to hard reg set if the prologue sets it up and it is not
38738 pic_offset_table_rtx. */
38741 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
38743 if (!TARGET_SINGLE_PIC_BASE
38745 && TARGET_MINIMAL_TOC
38746 && get_pool_size () != 0)
38747 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
38748 if (cfun
->machine
->split_stack_argp_used
)
38749 add_to_hard_reg_set (&set
->set
, Pmode
, 12);
38753 /* Helper function for rs6000_split_logical to emit a logical instruction after
38754 spliting the operation to single GPR registers.
38756 DEST is the destination register.
38757 OP1 and OP2 are the input source registers.
38758 CODE is the base operation (AND, IOR, XOR, NOT).
38759 MODE is the machine mode.
38760 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38761 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38762 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38765 rs6000_split_logical_inner (rtx dest
,
38768 enum rtx_code code
,
38770 bool complement_final_p
,
38771 bool complement_op1_p
,
38772 bool complement_op2_p
)
38776 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
38777 if (op2
&& GET_CODE (op2
) == CONST_INT
38778 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
38779 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
38781 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
38782 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
38784 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
38789 emit_insn (gen_rtx_SET (dest
, const0_rtx
));
38793 else if (value
== mask
)
38795 if (!rtx_equal_p (dest
, op1
))
38796 emit_insn (gen_rtx_SET (dest
, op1
));
38801 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
38802 into separate ORI/ORIS or XORI/XORIS instrucitons. */
38803 else if (code
== IOR
|| code
== XOR
)
38807 if (!rtx_equal_p (dest
, op1
))
38808 emit_insn (gen_rtx_SET (dest
, op1
));
38814 if (code
== AND
&& mode
== SImode
38815 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
38817 emit_insn (gen_andsi3 (dest
, op1
, op2
));
38821 if (complement_op1_p
)
38822 op1
= gen_rtx_NOT (mode
, op1
);
38824 if (complement_op2_p
)
38825 op2
= gen_rtx_NOT (mode
, op2
);
38827 /* For canonical RTL, if only one arm is inverted it is the first. */
38828 if (!complement_op1_p
&& complement_op2_p
)
38829 std::swap (op1
, op2
);
38831 bool_rtx
= ((code
== NOT
)
38832 ? gen_rtx_NOT (mode
, op1
)
38833 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
38835 if (complement_final_p
)
38836 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
38838 emit_insn (gen_rtx_SET (dest
, bool_rtx
));
38841 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
38842 operations are split immediately during RTL generation to allow for more
38843 optimizations of the AND/IOR/XOR.
38845 OPERANDS is an array containing the destination and two input operands.
38846 CODE is the base operation (AND, IOR, XOR, NOT).
38847 MODE is the machine mode.
38848 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38849 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38850 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
38851 CLOBBER_REG is either NULL or a scratch register of type CC to allow
38852 formation of the AND instructions. */
38855 rs6000_split_logical_di (rtx operands
[3],
38856 enum rtx_code code
,
38857 bool complement_final_p
,
38858 bool complement_op1_p
,
38859 bool complement_op2_p
)
38861 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
38862 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
38863 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
38864 enum hi_lo
{ hi
= 0, lo
= 1 };
38865 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
38868 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
38869 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
38870 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
38871 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
38874 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
38877 if (GET_CODE (operands
[2]) != CONST_INT
)
38879 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
38880 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
38884 HOST_WIDE_INT value
= INTVAL (operands
[2]);
38885 HOST_WIDE_INT value_hi_lo
[2];
38887 gcc_assert (!complement_final_p
);
38888 gcc_assert (!complement_op1_p
);
38889 gcc_assert (!complement_op2_p
);
38891 value_hi_lo
[hi
] = value
>> 32;
38892 value_hi_lo
[lo
] = value
& lower_32bits
;
38894 for (i
= 0; i
< 2; i
++)
38896 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
38898 if (sub_value
& sign_bit
)
38899 sub_value
|= upper_32bits
;
38901 op2_hi_lo
[i
] = GEN_INT (sub_value
);
38903 /* If this is an AND instruction, check to see if we need to load
38904 the value in a register. */
38905 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
38906 && !and_operand (op2_hi_lo
[i
], SImode
))
38907 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
38912 for (i
= 0; i
< 2; i
++)
38914 /* Split large IOR/XOR operations. */
38915 if ((code
== IOR
|| code
== XOR
)
38916 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
38917 && !complement_final_p
38918 && !complement_op1_p
38919 && !complement_op2_p
38920 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
38922 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
38923 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
38924 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
38925 rtx tmp
= gen_reg_rtx (SImode
);
38927 /* Make sure the constant is sign extended. */
38928 if ((hi_16bits
& sign_bit
) != 0)
38929 hi_16bits
|= upper_32bits
;
38931 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
38932 code
, SImode
, false, false, false);
38934 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
38935 code
, SImode
, false, false, false);
38938 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
38939 code
, SImode
, complement_final_p
,
38940 complement_op1_p
, complement_op2_p
);
38946 /* Split the insns that make up boolean operations operating on multiple GPR
38947 registers. The boolean MD patterns ensure that the inputs either are
38948 exactly the same as the output registers, or there is no overlap.
38950 OPERANDS is an array containing the destination and two input operands.
38951 CODE is the base operation (AND, IOR, XOR, NOT).
38952 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
38953 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
38954 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. */
38957 rs6000_split_logical (rtx operands
[3],
38958 enum rtx_code code
,
38959 bool complement_final_p
,
38960 bool complement_op1_p
,
38961 bool complement_op2_p
)
38963 machine_mode mode
= GET_MODE (operands
[0]);
38964 machine_mode sub_mode
;
38966 int sub_size
, regno0
, regno1
, nregs
, i
;
38968 /* If this is DImode, use the specialized version that can run before
38969 register allocation. */
38970 if (mode
== DImode
&& !TARGET_POWERPC64
)
38972 rs6000_split_logical_di (operands
, code
, complement_final_p
,
38973 complement_op1_p
, complement_op2_p
);
38979 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
38980 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
38981 sub_size
= GET_MODE_SIZE (sub_mode
);
38982 regno0
= REGNO (op0
);
38983 regno1
= REGNO (op1
);
38985 gcc_assert (reload_completed
);
38986 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38987 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38989 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
38990 gcc_assert (nregs
> 1);
38992 if (op2
&& REG_P (op2
))
38993 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
38995 for (i
= 0; i
< nregs
; i
++)
38997 int offset
= i
* sub_size
;
38998 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
38999 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
39000 rtx sub_op2
= ((code
== NOT
)
39002 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
39004 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
39005 complement_final_p
, complement_op1_p
,
39013 /* Return true if the peephole2 can combine a load involving a combination of
39014 an addis instruction and a load with an offset that can be fused together on
39018 fusion_gpr_load_p (rtx addis_reg
, /* register set via addis. */
39019 rtx addis_value
, /* addis value. */
39020 rtx target
, /* target register that is loaded. */
39021 rtx mem
) /* bottom part of the memory addr. */
39026 /* Validate arguments. */
39027 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
39030 if (!base_reg_operand (target
, GET_MODE (target
)))
39033 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
39036 /* Allow sign/zero extension. */
39037 if (GET_CODE (mem
) == ZERO_EXTEND
39038 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
39039 mem
= XEXP (mem
, 0);
39044 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
39047 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
39048 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
39051 /* Validate that the register used to load the high value is either the
39052 register being loaded, or we can safely replace its use.
39054 This function is only called from the peephole2 pass and we assume that
39055 there are 2 instructions in the peephole (addis and load), so we want to
39056 check if the target register was not used in the memory address and the
39057 register to hold the addis result is dead after the peephole. */
39058 if (REGNO (addis_reg
) != REGNO (target
))
39060 if (reg_mentioned_p (target
, mem
))
39063 if (!peep2_reg_dead_p (2, addis_reg
))
39066 /* If the target register being loaded is the stack pointer, we must
39067 avoid loading any other value into it, even temporarily. */
39068 if (REG_P (target
) && REGNO (target
) == STACK_POINTER_REGNUM
)
39072 base_reg
= XEXP (addr
, 0);
39073 return REGNO (addis_reg
) == REGNO (base_reg
);
39076 /* During the peephole2 pass, adjust and expand the insns for a load fusion
39077 sequence. We adjust the addis register to use the target register. If the
39078 load sign extends, we adjust the code to do the zero extending load, and an
39079 explicit sign extension later since the fusion only covers zero extending
39083 operands[0] register set with addis (to be replaced with target)
39084 operands[1] value set via addis
39085 operands[2] target register being loaded
39086 operands[3] D-form memory reference using operands[0]. */
39089 expand_fusion_gpr_load (rtx
*operands
)
39091 rtx addis_value
= operands
[1];
39092 rtx target
= operands
[2];
39093 rtx orig_mem
= operands
[3];
39094 rtx new_addr
, new_mem
, orig_addr
, offset
;
39095 enum rtx_code plus_or_lo_sum
;
39096 machine_mode target_mode
= GET_MODE (target
);
39097 machine_mode extend_mode
= target_mode
;
39098 machine_mode ptr_mode
= Pmode
;
39099 enum rtx_code extend
= UNKNOWN
;
39101 if (GET_CODE (orig_mem
) == ZERO_EXTEND
39102 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
39104 extend
= GET_CODE (orig_mem
);
39105 orig_mem
= XEXP (orig_mem
, 0);
39106 target_mode
= GET_MODE (orig_mem
);
39109 gcc_assert (MEM_P (orig_mem
));
39111 orig_addr
= XEXP (orig_mem
, 0);
39112 plus_or_lo_sum
= GET_CODE (orig_addr
);
39113 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
39115 offset
= XEXP (orig_addr
, 1);
39116 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
39117 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
39119 if (extend
!= UNKNOWN
)
39120 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
39122 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
39123 UNSPEC_FUSION_GPR
);
39124 emit_insn (gen_rtx_SET (target
, new_mem
));
39126 if (extend
== SIGN_EXTEND
)
39128 int sub_off
= ((BYTES_BIG_ENDIAN
)
39129 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
39132 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
39134 emit_insn (gen_rtx_SET (target
,
39135 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
39141 /* Emit the addis instruction that will be part of a fused instruction
39145 emit_fusion_addis (rtx target
, rtx addis_value
, const char *comment
,
39146 const char *mode_name
)
39149 char insn_template
[80];
39150 const char *addis_str
= NULL
;
39151 const char *comment_str
= ASM_COMMENT_START
;
39153 if (*comment_str
== ' ')
39156 /* Emit the addis instruction. */
39157 fuse_ops
[0] = target
;
39158 if (satisfies_constraint_L (addis_value
))
39160 fuse_ops
[1] = addis_value
;
39161 addis_str
= "lis %0,%v1";
39164 else if (GET_CODE (addis_value
) == PLUS
)
39166 rtx op0
= XEXP (addis_value
, 0);
39167 rtx op1
= XEXP (addis_value
, 1);
39169 if (REG_P (op0
) && CONST_INT_P (op1
)
39170 && satisfies_constraint_L (op1
))
39174 addis_str
= "addis %0,%1,%v2";
39178 else if (GET_CODE (addis_value
) == HIGH
)
39180 rtx value
= XEXP (addis_value
, 0);
39181 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
39183 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
39184 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
39186 addis_str
= "addis %0,%2,%1@toc@ha";
39188 else if (TARGET_XCOFF
)
39189 addis_str
= "addis %0,%1@u(%2)";
39192 gcc_unreachable ();
39195 else if (GET_CODE (value
) == PLUS
)
39197 rtx op0
= XEXP (value
, 0);
39198 rtx op1
= XEXP (value
, 1);
39200 if (GET_CODE (op0
) == UNSPEC
39201 && XINT (op0
, 1) == UNSPEC_TOCREL
39202 && CONST_INT_P (op1
))
39204 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
39205 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
39208 addis_str
= "addis %0,%2,%1+%3@toc@ha";
39210 else if (TARGET_XCOFF
)
39211 addis_str
= "addis %0,%1+%3@u(%2)";
39214 gcc_unreachable ();
39218 else if (satisfies_constraint_L (value
))
39220 fuse_ops
[1] = value
;
39221 addis_str
= "lis %0,%v1";
39224 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
39226 fuse_ops
[1] = value
;
39227 addis_str
= "lis %0,%1@ha";
39232 fatal_insn ("Could not generate addis value for fusion", addis_value
);
39234 sprintf (insn_template
, "%s\t\t%s %s, type %s", addis_str
, comment_str
,
39235 comment
, mode_name
);
39236 output_asm_insn (insn_template
, fuse_ops
);
39239 /* Emit a D-form load or store instruction that is the second instruction
39240 of a fusion sequence. */
39243 emit_fusion_load_store (rtx load_store_reg
, rtx addis_reg
, rtx offset
,
39244 const char *insn_str
)
39247 char insn_template
[80];
39249 fuse_ops
[0] = load_store_reg
;
39250 fuse_ops
[1] = addis_reg
;
39252 if (CONST_INT_P (offset
) && satisfies_constraint_I (offset
))
39254 sprintf (insn_template
, "%s %%0,%%2(%%1)", insn_str
);
39255 fuse_ops
[2] = offset
;
39256 output_asm_insn (insn_template
, fuse_ops
);
39259 else if (GET_CODE (offset
) == UNSPEC
39260 && XINT (offset
, 1) == UNSPEC_TOCREL
)
39263 sprintf (insn_template
, "%s %%0,%%2@toc@l(%%1)", insn_str
);
39265 else if (TARGET_XCOFF
)
39266 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
39269 gcc_unreachable ();
39271 fuse_ops
[2] = XVECEXP (offset
, 0, 0);
39272 output_asm_insn (insn_template
, fuse_ops
);
39275 else if (GET_CODE (offset
) == PLUS
39276 && GET_CODE (XEXP (offset
, 0)) == UNSPEC
39277 && XINT (XEXP (offset
, 0), 1) == UNSPEC_TOCREL
39278 && CONST_INT_P (XEXP (offset
, 1)))
39280 rtx tocrel_unspec
= XEXP (offset
, 0);
39282 sprintf (insn_template
, "%s %%0,%%2+%%3@toc@l(%%1)", insn_str
);
39284 else if (TARGET_XCOFF
)
39285 sprintf (insn_template
, "%s %%0,%%2+%%3@l(%%1)", insn_str
);
39288 gcc_unreachable ();
39290 fuse_ops
[2] = XVECEXP (tocrel_unspec
, 0, 0);
39291 fuse_ops
[3] = XEXP (offset
, 1);
39292 output_asm_insn (insn_template
, fuse_ops
);
39295 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (offset
))
39297 sprintf (insn_template
, "%s %%0,%%2@l(%%1)", insn_str
);
39299 fuse_ops
[2] = offset
;
39300 output_asm_insn (insn_template
, fuse_ops
);
39304 fatal_insn ("Unable to generate load/store offset for fusion", offset
);
39309 /* Wrap a TOC address that can be fused to indicate that special fusion
39310 processing is needed. */
39313 fusion_wrap_memory_address (rtx old_mem
)
39315 rtx old_addr
= XEXP (old_mem
, 0);
39316 rtvec v
= gen_rtvec (1, old_addr
);
39317 rtx new_addr
= gen_rtx_UNSPEC (Pmode
, v
, UNSPEC_FUSION_ADDIS
);
39318 return replace_equiv_address_nv (old_mem
, new_addr
, false);
39321 /* Given an address, convert it into the addis and load offset parts. Addresses
39322 created during the peephole2 process look like:
39323 (lo_sum (high (unspec [(sym)] UNSPEC_TOCREL))
39324 (unspec [(...)] UNSPEC_TOCREL))
39326 Addresses created via toc fusion look like:
39327 (unspec [(unspec [(...)] UNSPEC_TOCREL)] UNSPEC_FUSION_ADDIS)) */
39330 fusion_split_address (rtx addr
, rtx
*p_hi
, rtx
*p_lo
)
39334 if (GET_CODE (addr
) == UNSPEC
&& XINT (addr
, 1) == UNSPEC_FUSION_ADDIS
)
39336 lo
= XVECEXP (addr
, 0, 0);
39337 hi
= gen_rtx_HIGH (Pmode
, lo
);
39339 else if (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
)
39341 hi
= XEXP (addr
, 0);
39342 lo
= XEXP (addr
, 1);
39345 gcc_unreachable ();
39351 /* Return a string to fuse an addis instruction with a gpr load to the same
39352 register that we loaded up the addis instruction. The address that is used
39353 is the logical address that was formed during peephole2:
39354 (lo_sum (high) (low-part))
39356 Or the address is the TOC address that is wrapped before register allocation:
39357 (unspec [(addr) (toc-reg)] UNSPEC_FUSION_ADDIS)
39359 The code is complicated, so we call output_asm_insn directly, and just
39363 emit_fusion_gpr_load (rtx target
, rtx mem
)
39368 const char *load_str
= NULL
;
39369 const char *mode_name
= NULL
;
39372 if (GET_CODE (mem
) == ZERO_EXTEND
)
39373 mem
= XEXP (mem
, 0);
39375 gcc_assert (REG_P (target
) && MEM_P (mem
));
39377 addr
= XEXP (mem
, 0);
39378 fusion_split_address (addr
, &addis_value
, &load_offset
);
39380 /* Now emit the load instruction to the same register. */
39381 mode
= GET_MODE (mem
);
39385 mode_name
= "char";
39390 mode_name
= "short";
39396 mode_name
= (mode
== SFmode
) ? "float" : "int";
39402 gcc_assert (TARGET_POWERPC64
);
39403 mode_name
= (mode
== DFmode
) ? "double" : "long";
39408 fatal_insn ("Bad GPR fusion", gen_rtx_SET (target
, mem
));
39411 /* Emit the addis instruction. */
39412 emit_fusion_addis (target
, addis_value
, "gpr load fusion", mode_name
);
39414 /* Emit the D-form load instruction. */
39415 emit_fusion_load_store (target
, target
, load_offset
, load_str
);
39421 /* Return true if the peephole2 can combine a load/store involving a
39422 combination of an addis instruction and the memory operation. This was
39423 added to the ISA 3.0 (power9) hardware. */
39426 fusion_p9_p (rtx addis_reg
, /* register set via addis. */
39427 rtx addis_value
, /* addis value. */
39428 rtx dest
, /* destination (memory or register). */
39429 rtx src
) /* source (register or memory). */
39431 rtx addr
, mem
, offset
;
39432 enum machine_mode mode
= GET_MODE (src
);
39434 /* Validate arguments. */
39435 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
39438 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
39441 /* Ignore extend operations that are part of the load. */
39442 if (GET_CODE (src
) == FLOAT_EXTEND
|| GET_CODE (src
) == ZERO_EXTEND
)
39443 src
= XEXP (src
, 0);
39445 /* Test for memory<-register or register<-memory. */
39446 if (fpr_reg_operand (src
, mode
) || int_reg_operand (src
, mode
))
39454 else if (MEM_P (src
))
39456 if (!fpr_reg_operand (dest
, mode
) && !int_reg_operand (dest
, mode
))
39465 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
39466 if (GET_CODE (addr
) == PLUS
)
39468 if (!rtx_equal_p (addis_reg
, XEXP (addr
, 0)))
39471 return satisfies_constraint_I (XEXP (addr
, 1));
39474 else if (GET_CODE (addr
) == LO_SUM
)
39476 if (!rtx_equal_p (addis_reg
, XEXP (addr
, 0)))
39479 offset
= XEXP (addr
, 1);
39480 if (TARGET_XCOFF
|| (TARGET_ELF
&& TARGET_POWERPC64
))
39481 return small_toc_ref (offset
, GET_MODE (offset
));
39483 else if (TARGET_ELF
&& !TARGET_POWERPC64
)
39484 return CONSTANT_P (offset
);
39490 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39494 operands[0] register set with addis
39495 operands[1] value set via addis
39496 operands[2] target register being loaded
39497 operands[3] D-form memory reference using operands[0].
39499 This is similar to the fusion introduced with power8, except it scales to
39500 both loads/stores and does not require the result register to be the same as
39501 the base register. At the moment, we only do this if register set with addis
39505 expand_fusion_p9_load (rtx
*operands
)
39507 rtx tmp_reg
= operands
[0];
39508 rtx addis_value
= operands
[1];
39509 rtx target
= operands
[2];
39510 rtx orig_mem
= operands
[3];
39511 rtx new_addr
, new_mem
, orig_addr
, offset
, set
, clobber
, insn
;
39512 enum rtx_code plus_or_lo_sum
;
39513 machine_mode target_mode
= GET_MODE (target
);
39514 machine_mode extend_mode
= target_mode
;
39515 machine_mode ptr_mode
= Pmode
;
39516 enum rtx_code extend
= UNKNOWN
;
39518 if (GET_CODE (orig_mem
) == FLOAT_EXTEND
|| GET_CODE (orig_mem
) == ZERO_EXTEND
)
39520 extend
= GET_CODE (orig_mem
);
39521 orig_mem
= XEXP (orig_mem
, 0);
39522 target_mode
= GET_MODE (orig_mem
);
39525 gcc_assert (MEM_P (orig_mem
));
39527 orig_addr
= XEXP (orig_mem
, 0);
39528 plus_or_lo_sum
= GET_CODE (orig_addr
);
39529 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
39531 offset
= XEXP (orig_addr
, 1);
39532 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
39533 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
39535 if (extend
!= UNKNOWN
)
39536 new_mem
= gen_rtx_fmt_e (extend
, extend_mode
, new_mem
);
39538 new_mem
= gen_rtx_UNSPEC (extend_mode
, gen_rtvec (1, new_mem
),
39541 set
= gen_rtx_SET (target
, new_mem
);
39542 clobber
= gen_rtx_CLOBBER (VOIDmode
, tmp_reg
);
39543 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
));
39549 /* During the peephole2 pass, adjust and expand the insns for an extended fusion
39553 operands[0] register set with addis
39554 operands[1] value set via addis
39555 operands[2] target D-form memory being stored to
39556 operands[3] register being stored
39558 This is similar to the fusion introduced with power8, except it scales to
39559 both loads/stores and does not require the result register to be the same as
39560 the base register. At the moment, we only do this if register set with addis
39564 expand_fusion_p9_store (rtx
*operands
)
39566 rtx tmp_reg
= operands
[0];
39567 rtx addis_value
= operands
[1];
39568 rtx orig_mem
= operands
[2];
39569 rtx src
= operands
[3];
39570 rtx new_addr
, new_mem
, orig_addr
, offset
, set
, clobber
, insn
, new_src
;
39571 enum rtx_code plus_or_lo_sum
;
39572 machine_mode target_mode
= GET_MODE (orig_mem
);
39573 machine_mode ptr_mode
= Pmode
;
39575 gcc_assert (MEM_P (orig_mem
));
39577 orig_addr
= XEXP (orig_mem
, 0);
39578 plus_or_lo_sum
= GET_CODE (orig_addr
);
39579 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
39581 offset
= XEXP (orig_addr
, 1);
39582 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_value
, offset
);
39583 new_mem
= replace_equiv_address_nv (orig_mem
, new_addr
, false);
39585 new_src
= gen_rtx_UNSPEC (target_mode
, gen_rtvec (1, src
),
39588 set
= gen_rtx_SET (new_mem
, new_src
);
39589 clobber
= gen_rtx_CLOBBER (VOIDmode
, tmp_reg
);
39590 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
));
39596 /* Return a string to fuse an addis instruction with a load using extended
39597 fusion. The address that is used is the logical address that was formed
39598 during peephole2: (lo_sum (high) (low-part))
39600 The code is complicated, so we call output_asm_insn directly, and just
39604 emit_fusion_p9_load (rtx reg
, rtx mem
, rtx tmp_reg
)
39606 enum machine_mode mode
= GET_MODE (reg
);
39610 const char *load_string
;
39613 if (GET_CODE (mem
) == FLOAT_EXTEND
|| GET_CODE (mem
) == ZERO_EXTEND
)
39615 mem
= XEXP (mem
, 0);
39616 mode
= GET_MODE (mem
);
39619 if (GET_CODE (reg
) == SUBREG
)
39621 gcc_assert (SUBREG_BYTE (reg
) == 0);
39622 reg
= SUBREG_REG (reg
);
39626 fatal_insn ("emit_fusion_p9_load, bad reg #1", reg
);
39629 if (FP_REGNO_P (r
))
39631 if (mode
== SFmode
)
39632 load_string
= "lfs";
39633 else if (mode
== DFmode
|| mode
== DImode
)
39634 load_string
= "lfd";
39636 gcc_unreachable ();
39638 else if (INT_REGNO_P (r
))
39643 load_string
= "lbz";
39646 load_string
= "lhz";
39650 load_string
= "lwz";
39654 if (!TARGET_POWERPC64
)
39655 gcc_unreachable ();
39656 load_string
= "ld";
39659 gcc_unreachable ();
39663 fatal_insn ("emit_fusion_p9_load, bad reg #2", reg
);
39666 fatal_insn ("emit_fusion_p9_load not MEM", mem
);
39668 addr
= XEXP (mem
, 0);
39669 fusion_split_address (addr
, &hi
, &lo
);
39671 /* Emit the addis instruction. */
39672 emit_fusion_addis (tmp_reg
, hi
, "power9 load fusion", GET_MODE_NAME (mode
));
39674 /* Emit the D-form load instruction. */
39675 emit_fusion_load_store (reg
, tmp_reg
, lo
, load_string
);
39680 /* Return a string to fuse an addis instruction with a store using extended
39681 fusion. The address that is used is the logical address that was formed
39682 during peephole2: (lo_sum (high) (low-part))
39684 The code is complicated, so we call output_asm_insn directly, and just
39688 emit_fusion_p9_store (rtx mem
, rtx reg
, rtx tmp_reg
)
39690 enum machine_mode mode
= GET_MODE (reg
);
39694 const char *store_string
;
39697 if (GET_CODE (reg
) == SUBREG
)
39699 gcc_assert (SUBREG_BYTE (reg
) == 0);
39700 reg
= SUBREG_REG (reg
);
39704 fatal_insn ("emit_fusion_p9_store, bad reg #1", reg
);
39707 if (FP_REGNO_P (r
))
39709 if (mode
== SFmode
)
39710 store_string
= "stfs";
39711 else if (mode
== DFmode
)
39712 store_string
= "stfd";
39714 gcc_unreachable ();
39716 else if (INT_REGNO_P (r
))
39721 store_string
= "stb";
39724 store_string
= "sth";
39728 store_string
= "stw";
39732 if (!TARGET_POWERPC64
)
39733 gcc_unreachable ();
39734 store_string
= "std";
39737 gcc_unreachable ();
39741 fatal_insn ("emit_fusion_p9_store, bad reg #2", reg
);
39744 fatal_insn ("emit_fusion_p9_store not MEM", mem
);
39746 addr
= XEXP (mem
, 0);
39747 fusion_split_address (addr
, &hi
, &lo
);
39749 /* Emit the addis instruction. */
39750 emit_fusion_addis (tmp_reg
, hi
, "power9 store fusion", GET_MODE_NAME (mode
));
39752 /* Emit the D-form load instruction. */
39753 emit_fusion_load_store (reg
, tmp_reg
, lo
, store_string
);
39759 /* Analyze vector computations and remove unnecessary doubleword
39760 swaps (xxswapdi instructions). This pass is performed only
39761 for little-endian VSX code generation.
39763 For this specific case, loads and stores of 4x32 and 2x64 vectors
39764 are inefficient. These are implemented using the lvx2dx and
39765 stvx2dx instructions, which invert the order of doublewords in
39766 a vector register. Thus the code generation inserts an xxswapdi
39767 after each such load, and prior to each such store. (For spill
39768 code after register assignment, an additional xxswapdi is inserted
39769 following each store in order to return a hard register to its
39772 The extra xxswapdi instructions reduce performance. This can be
39773 particularly bad for vectorized code. The purpose of this pass
39774 is to reduce the number of xxswapdi instructions required for
39777 The primary insight is that much code that operates on vectors
39778 does not care about the relative order of elements in a register,
39779 so long as the correct memory order is preserved. If we have
39780 a computation where all input values are provided by lvxd2x/xxswapdi
39781 sequences, all outputs are stored using xxswapdi/stvxd2x sequences,
39782 and all intermediate computations are pure SIMD (independent of
39783 element order), then all the xxswapdi's associated with the loads
39784 and stores may be removed.
39786 This pass uses some of the infrastructure and logical ideas from
39787 the "web" pass in web.c. We create maximal webs of computations
39788 fitting the description above using union-find. Each such web is
39789 then optimized by removing its unnecessary xxswapdi instructions.
39791 The pass is placed prior to global optimization so that we can
39792 perform the optimization in the safest and simplest way possible;
39793 that is, by replacing each xxswapdi insn with a register copy insn.
39794 Subsequent forward propagation will remove copies where possible.
39796 There are some operations sensitive to element order for which we
39797 can still allow the operation, provided we modify those operations.
39798 These include CONST_VECTORs, for which we must swap the first and
39799 second halves of the constant vector; and SUBREGs, for which we
39800 must adjust the byte offset to account for the swapped doublewords.
39801 A remaining opportunity would be non-immediate-form splats, for
39802 which we should adjust the selected lane of the input. We should
39803 also make code generation adjustments for sum-across operations,
39804 since this is a common vectorizer reduction.
39806 Because we run prior to the first split, we can see loads and stores
39807 here that match *vsx_le_perm_{load,store}_<mode>. These are vanilla
39808 vector loads and stores that have not yet been split into a permuting
39809 load/store and a swap. (One way this can happen is with a builtin
39810 call to vec_vsx_{ld,st}.) We can handle these as well, but rather
39811 than deleting a swap, we convert the load/store into a permuting
39812 load/store (which effectively removes the swap). */
39814 /* Notes on Permutes
39816 We do not currently handle computations that contain permutes. There
39817 is a general transformation that can be performed correctly, but it
39818 may introduce more expensive code than it replaces. To handle these
39819 would require a cost model to determine when to perform the optimization.
39820 This commentary records how this could be done if desired.
39822 The most general permute is something like this (example for V16QI):
39824 (vec_select:V16QI (vec_concat:V32QI (op1:V16QI) (op2:V16QI))
39825 (parallel [(const_int a0) (const_int a1)
39827 (const_int a14) (const_int a15)]))
39829 where a0,...,a15 are in [0,31] and select elements from op1 and op2
39830 to produce in the result.
39832 Regardless of mode, we can convert the PARALLEL to a mask of 16
39833 byte-element selectors. Let's call this M, with M[i] representing
39834 the ith byte-element selector value. Then if we swap doublewords
39835 throughout the computation, we can get correct behavior by replacing
39836 M with M' as follows:
39838 M'[i] = { (M[i]+8)%16 : M[i] in [0,15]
39839 { ((M[i]+8)%16)+16 : M[i] in [16,31]
39841 This seems promising at first, since we are just replacing one mask
39842 with another. But certain masks are preferable to others. If M
39843 is a mask that matches a vmrghh pattern, for example, M' certainly
39844 will not. Instead of a single vmrghh, we would generate a load of
39845 M' and a vperm. So we would need to know how many xxswapd's we can
39846 remove as a result of this transformation to determine if it's
39847 profitable; and preferably the logic would need to be aware of all
39848 the special preferable masks.
39850 Another form of permute is an UNSPEC_VPERM, in which the mask is
39851 already in a register. In some cases, this mask may be a constant
39852 that we can discover with ud-chains, in which case the above
39853 transformation is ok. However, the common usage here is for the
39854 mask to be produced by an UNSPEC_LVSL, in which case the mask
39855 cannot be known at compile time. In such a case we would have to
39856 generate several instructions to compute M' as above at run time,
39857 and a cost model is needed again.
39859 However, when the mask M for an UNSPEC_VPERM is loaded from the
39860 constant pool, we can replace M with M' as above at no cost
39861 beyond adding a constant pool entry. */
39863 /* This is based on the union-find logic in web.c. web_entry_base is
39864 defined in df.h. */
39865 class swap_web_entry
: public web_entry_base
39868 /* Pointer to the insn. */
39870 /* Set if insn contains a mention of a vector register. All other
39871 fields are undefined if this field is unset. */
39872 unsigned int is_relevant
: 1;
39873 /* Set if insn is a load. */
39874 unsigned int is_load
: 1;
39875 /* Set if insn is a store. */
39876 unsigned int is_store
: 1;
39877 /* Set if insn is a doubleword swap. This can either be a register swap
39878 or a permuting load or store (test is_load and is_store for this). */
39879 unsigned int is_swap
: 1;
39880 /* Set if the insn has a live-in use of a parameter register. */
39881 unsigned int is_live_in
: 1;
39882 /* Set if the insn has a live-out def of a return register. */
39883 unsigned int is_live_out
: 1;
39884 /* Set if the insn contains a subreg reference of a vector register. */
39885 unsigned int contains_subreg
: 1;
39886 /* Set if the insn contains a 128-bit integer operand. */
39887 unsigned int is_128_int
: 1;
39888 /* Set if this is a call-insn. */
39889 unsigned int is_call
: 1;
39890 /* Set if this insn does not perform a vector operation for which
39891 element order matters, or if we know how to fix it up if it does.
39892 Undefined if is_swap is set. */
39893 unsigned int is_swappable
: 1;
39894 /* A nonzero value indicates what kind of special handling for this
39895 insn is required if doublewords are swapped. Undefined if
39896 is_swappable is not set. */
39897 unsigned int special_handling
: 4;
39898 /* Set if the web represented by this entry cannot be optimized. */
39899 unsigned int web_not_optimizable
: 1;
39900 /* Set if this insn should be deleted. */
39901 unsigned int will_delete
: 1;
39904 enum special_handling_values
{
39917 /* Union INSN with all insns containing definitions that reach USE.
39918 Detect whether USE is live-in to the current function. */
39920 union_defs (swap_web_entry
*insn_entry
, rtx insn
, df_ref use
)
39922 struct df_link
*link
= DF_REF_CHAIN (use
);
39925 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
39929 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
39930 insn_entry
[INSN_UID (insn
)].is_live_in
= 1;
39932 if (DF_REF_INSN_INFO (link
->ref
))
39934 rtx def_insn
= DF_REF_INSN (link
->ref
);
39935 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
39936 insn_entry
+ INSN_UID (def_insn
));
39943 /* Union INSN with all insns containing uses reached from DEF.
39944 Detect whether DEF is live-out from the current function. */
39946 union_uses (swap_web_entry
*insn_entry
, rtx insn
, df_ref def
)
39948 struct df_link
*link
= DF_REF_CHAIN (def
);
39951 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
39955 /* This could be an eh use or some other artificial use;
39956 we treat these all the same (killing the optimization). */
39957 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
39958 insn_entry
[INSN_UID (insn
)].is_live_out
= 1;
39960 if (DF_REF_INSN_INFO (link
->ref
))
39962 rtx use_insn
= DF_REF_INSN (link
->ref
);
39963 (void)unionfind_union (insn_entry
+ INSN_UID (insn
),
39964 insn_entry
+ INSN_UID (use_insn
));
39971 /* Return 1 iff INSN is a load insn, including permuting loads that
39972 represent an lvxd2x instruction; else return 0. */
39973 static unsigned int
39974 insn_is_load_p (rtx insn
)
39976 rtx body
= PATTERN (insn
);
39978 if (GET_CODE (body
) == SET
)
39980 if (GET_CODE (SET_SRC (body
)) == MEM
)
39983 if (GET_CODE (SET_SRC (body
)) == VEC_SELECT
39984 && GET_CODE (XEXP (SET_SRC (body
), 0)) == MEM
)
39990 if (GET_CODE (body
) != PARALLEL
)
39993 rtx set
= XVECEXP (body
, 0, 0);
39995 if (GET_CODE (set
) == SET
&& GET_CODE (SET_SRC (set
)) == MEM
)
40001 /* Return 1 iff INSN is a store insn, including permuting stores that
40002 represent an stvxd2x instruction; else return 0. */
40003 static unsigned int
40004 insn_is_store_p (rtx insn
)
40006 rtx body
= PATTERN (insn
);
40007 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == MEM
)
40009 if (GET_CODE (body
) != PARALLEL
)
40011 rtx set
= XVECEXP (body
, 0, 0);
40012 if (GET_CODE (set
) == SET
&& GET_CODE (SET_DEST (set
)) == MEM
)
40017 /* Return 1 iff INSN swaps doublewords. This may be a reg-reg swap,
40018 a permuting load, or a permuting store. */
40019 static unsigned int
40020 insn_is_swap_p (rtx insn
)
40022 rtx body
= PATTERN (insn
);
40023 if (GET_CODE (body
) != SET
)
40025 rtx rhs
= SET_SRC (body
);
40026 if (GET_CODE (rhs
) != VEC_SELECT
)
40028 rtx parallel
= XEXP (rhs
, 1);
40029 if (GET_CODE (parallel
) != PARALLEL
)
40031 unsigned int len
= XVECLEN (parallel
, 0);
40032 if (len
!= 2 && len
!= 4 && len
!= 8 && len
!= 16)
40034 for (unsigned int i
= 0; i
< len
/ 2; ++i
)
40036 rtx op
= XVECEXP (parallel
, 0, i
);
40037 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != len
/ 2 + i
)
40040 for (unsigned int i
= len
/ 2; i
< len
; ++i
)
40042 rtx op
= XVECEXP (parallel
, 0, i
);
40043 if (GET_CODE (op
) != CONST_INT
|| INTVAL (op
) != i
- len
/ 2)
40049 /* Return TRUE if insn is a swap fed by a load from the constant pool. */
40051 const_load_sequence_p (swap_web_entry
*insn_entry
, rtx insn
)
40053 unsigned uid
= INSN_UID (insn
);
40054 if (!insn_entry
[uid
].is_swap
|| insn_entry
[uid
].is_load
)
40057 /* Find the unique use in the swap and locate its def. If the def
40058 isn't unique, punt. */
40059 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
40061 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
40063 struct df_link
*def_link
= DF_REF_CHAIN (use
);
40064 if (!def_link
|| def_link
->next
)
40067 rtx def_insn
= DF_REF_INSN (def_link
->ref
);
40068 unsigned uid2
= INSN_UID (def_insn
);
40069 if (!insn_entry
[uid2
].is_load
|| !insn_entry
[uid2
].is_swap
)
40072 rtx body
= PATTERN (def_insn
);
40073 if (GET_CODE (body
) != SET
40074 || GET_CODE (SET_SRC (body
)) != VEC_SELECT
40075 || GET_CODE (XEXP (SET_SRC (body
), 0)) != MEM
)
40078 rtx mem
= XEXP (SET_SRC (body
), 0);
40079 rtx base_reg
= XEXP (mem
, 0);
40082 insn_info
= DF_INSN_INFO_GET (def_insn
);
40083 FOR_EACH_INSN_INFO_USE (base_use
, insn_info
)
40085 if (!rtx_equal_p (DF_REF_REG (base_use
), base_reg
))
40088 struct df_link
*base_def_link
= DF_REF_CHAIN (base_use
);
40089 if (!base_def_link
|| base_def_link
->next
)
40092 rtx tocrel_insn
= DF_REF_INSN (base_def_link
->ref
);
40093 rtx tocrel_body
= PATTERN (tocrel_insn
);
40095 if (GET_CODE (tocrel_body
) != SET
)
40097 /* There is an extra level of indirection for small/large
40099 rtx tocrel_expr
= SET_SRC (tocrel_body
);
40100 if (GET_CODE (tocrel_expr
) == MEM
)
40101 tocrel_expr
= XEXP (tocrel_expr
, 0);
40102 if (!toc_relative_expr_p (tocrel_expr
, false))
40104 split_const (XVECEXP (tocrel_base
, 0, 0), &base
, &offset
);
40105 if (GET_CODE (base
) != SYMBOL_REF
|| !CONSTANT_POOL_ADDRESS_P (base
))
40112 /* Return TRUE iff OP matches a V2DF reduction pattern. See the
40113 definition of vsx_reduc_<VEC_reduc_name>_v2df in vsx.md. */
40115 v2df_reduction_p (rtx op
)
40117 if (GET_MODE (op
) != V2DFmode
)
40120 enum rtx_code code
= GET_CODE (op
);
40121 if (code
!= PLUS
&& code
!= SMIN
&& code
!= SMAX
)
40124 rtx concat
= XEXP (op
, 0);
40125 if (GET_CODE (concat
) != VEC_CONCAT
)
40128 rtx select0
= XEXP (concat
, 0);
40129 rtx select1
= XEXP (concat
, 1);
40130 if (GET_CODE (select0
) != VEC_SELECT
|| GET_CODE (select1
) != VEC_SELECT
)
40133 rtx reg0
= XEXP (select0
, 0);
40134 rtx reg1
= XEXP (select1
, 0);
40135 if (!rtx_equal_p (reg0
, reg1
) || !REG_P (reg0
))
40138 rtx parallel0
= XEXP (select0
, 1);
40139 rtx parallel1
= XEXP (select1
, 1);
40140 if (GET_CODE (parallel0
) != PARALLEL
|| GET_CODE (parallel1
) != PARALLEL
)
40143 if (!rtx_equal_p (XVECEXP (parallel0
, 0, 0), const1_rtx
)
40144 || !rtx_equal_p (XVECEXP (parallel1
, 0, 0), const0_rtx
))
40150 /* Return 1 iff OP is an operand that will not be affected by having
40151 vector doublewords swapped in memory. */
40152 static unsigned int
40153 rtx_is_swappable_p (rtx op
, unsigned int *special
)
40155 enum rtx_code code
= GET_CODE (op
);
40174 *special
= SH_CONST_VECTOR
;
40178 case VEC_DUPLICATE
:
40179 /* Opportunity: If XEXP (op, 0) has the same mode as the result,
40180 and XEXP (op, 1) is a PARALLEL with a single QImode const int,
40181 it represents a vector splat for which we can do special
40183 if (GET_CODE (XEXP (op
, 0)) == CONST_INT
)
40185 else if (REG_P (XEXP (op
, 0))
40186 && GET_MODE_INNER (GET_MODE (op
)) == GET_MODE (XEXP (op
, 0)))
40187 /* This catches V2DF and V2DI splat, at a minimum. */
40189 else if (GET_CODE (XEXP (op
, 0)) == TRUNCATE
40190 && REG_P (XEXP (XEXP (op
, 0), 0))
40191 && GET_MODE_INNER (GET_MODE (op
)) == GET_MODE (XEXP (op
, 0)))
40192 /* This catches splat of a truncated value. */
40194 else if (GET_CODE (XEXP (op
, 0)) == VEC_SELECT
)
40195 /* If the duplicated item is from a select, defer to the select
40196 processing to see if we can change the lane for the splat. */
40197 return rtx_is_swappable_p (XEXP (op
, 0), special
);
40202 /* A vec_extract operation is ok if we change the lane. */
40203 if (GET_CODE (XEXP (op
, 0)) == REG
40204 && GET_MODE_INNER (GET_MODE (XEXP (op
, 0))) == GET_MODE (op
)
40205 && GET_CODE ((parallel
= XEXP (op
, 1))) == PARALLEL
40206 && XVECLEN (parallel
, 0) == 1
40207 && GET_CODE (XVECEXP (parallel
, 0, 0)) == CONST_INT
)
40209 *special
= SH_EXTRACT
;
40212 /* An XXPERMDI is ok if we adjust the lanes. Note that if the
40213 XXPERMDI is a swap operation, it will be identified by
40214 insn_is_swap_p and therefore we won't get here. */
40215 else if (GET_CODE (XEXP (op
, 0)) == VEC_CONCAT
40216 && (GET_MODE (XEXP (op
, 0)) == V4DFmode
40217 || GET_MODE (XEXP (op
, 0)) == V4DImode
)
40218 && GET_CODE ((parallel
= XEXP (op
, 1))) == PARALLEL
40219 && XVECLEN (parallel
, 0) == 2
40220 && GET_CODE (XVECEXP (parallel
, 0, 0)) == CONST_INT
40221 && GET_CODE (XVECEXP (parallel
, 0, 1)) == CONST_INT
)
40223 *special
= SH_XXPERMDI
;
40226 else if (v2df_reduction_p (op
))
40233 /* Various operations are unsafe for this optimization, at least
40234 without significant additional work. Permutes are obviously
40235 problematic, as both the permute control vector and the ordering
40236 of the target values are invalidated by doubleword swapping.
40237 Vector pack and unpack modify the number of vector lanes.
40238 Merge-high/low will not operate correctly on swapped operands.
40239 Vector shifts across element boundaries are clearly uncool,
40240 as are vector select and concatenate operations. Vector
40241 sum-across instructions define one operand with a specific
40242 order-dependent element, so additional fixup code would be
40243 needed to make those work. Vector set and non-immediate-form
40244 vector splat are element-order sensitive. A few of these
40245 cases might be workable with special handling if required.
40246 Adding cost modeling would be appropriate in some cases. */
40247 int val
= XINT (op
, 1);
40252 case UNSPEC_VMRGH_DIRECT
:
40253 case UNSPEC_VMRGL_DIRECT
:
40254 case UNSPEC_VPACK_SIGN_SIGN_SAT
:
40255 case UNSPEC_VPACK_SIGN_UNS_SAT
:
40256 case UNSPEC_VPACK_UNS_UNS_MOD
:
40257 case UNSPEC_VPACK_UNS_UNS_MOD_DIRECT
:
40258 case UNSPEC_VPACK_UNS_UNS_SAT
:
40260 case UNSPEC_VPERM_UNS
:
40261 case UNSPEC_VPERMHI
:
40262 case UNSPEC_VPERMSI
:
40264 case UNSPEC_VSLDOI
:
40267 case UNSPEC_VSUM2SWS
:
40268 case UNSPEC_VSUM4S
:
40269 case UNSPEC_VSUM4UBS
:
40270 case UNSPEC_VSUMSWS
:
40271 case UNSPEC_VSUMSWS_DIRECT
:
40272 case UNSPEC_VSX_CONCAT
:
40273 case UNSPEC_VSX_SET
:
40274 case UNSPEC_VSX_SLDWI
:
40275 case UNSPEC_VUNPACK_HI_SIGN
:
40276 case UNSPEC_VUNPACK_HI_SIGN_DIRECT
:
40277 case UNSPEC_VUNPACK_LO_SIGN
:
40278 case UNSPEC_VUNPACK_LO_SIGN_DIRECT
:
40279 case UNSPEC_VUPKHPX
:
40280 case UNSPEC_VUPKHS_V4SF
:
40281 case UNSPEC_VUPKHU_V4SF
:
40282 case UNSPEC_VUPKLPX
:
40283 case UNSPEC_VUPKLS_V4SF
:
40284 case UNSPEC_VUPKLU_V4SF
:
40285 case UNSPEC_VSX_CVDPSPN
:
40286 case UNSPEC_VSX_CVSPDP
:
40287 case UNSPEC_VSX_CVSPDPN
:
40288 case UNSPEC_VSX_EXTRACT
:
40289 case UNSPEC_VSX_VSLO
:
40290 case UNSPEC_VSX_VEC_INIT
:
40292 case UNSPEC_VSPLT_DIRECT
:
40293 *special
= SH_SPLAT
;
40295 case UNSPEC_REDUC_PLUS
:
40305 const char *fmt
= GET_RTX_FORMAT (code
);
40308 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
40309 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
40311 unsigned int special_op
= SH_NONE
;
40312 ok
&= rtx_is_swappable_p (XEXP (op
, i
), &special_op
);
40313 if (special_op
== SH_NONE
)
40315 /* Ensure we never have two kinds of special handling
40316 for the same insn. */
40317 if (*special
!= SH_NONE
&& *special
!= special_op
)
40319 *special
= special_op
;
40321 else if (fmt
[i
] == 'E')
40322 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
40324 unsigned int special_op
= SH_NONE
;
40325 ok
&= rtx_is_swappable_p (XVECEXP (op
, i
, j
), &special_op
);
40326 if (special_op
== SH_NONE
)
40328 /* Ensure we never have two kinds of special handling
40329 for the same insn. */
40330 if (*special
!= SH_NONE
&& *special
!= special_op
)
40332 *special
= special_op
;
40338 /* Return 1 iff INSN is an operand that will not be affected by
40339 having vector doublewords swapped in memory (in which case
40340 *SPECIAL is unchanged), or that can be modified to be correct
40341 if vector doublewords are swapped in memory (in which case
40342 *SPECIAL is changed to a value indicating how). */
40343 static unsigned int
40344 insn_is_swappable_p (swap_web_entry
*insn_entry
, rtx insn
,
40345 unsigned int *special
)
40347 /* Calls are always bad. */
40348 if (GET_CODE (insn
) == CALL_INSN
)
40351 /* Loads and stores seen here are not permuting, but we can still
40352 fix them up by converting them to permuting ones. Exceptions:
40353 UNSPEC_LVE, UNSPEC_LVX, and UNSPEC_STVX, which have a PARALLEL
40354 body instead of a SET; and UNSPEC_STVE, which has an UNSPEC
40355 for the SET source. Also we must now make an exception for lvx
40356 and stvx when they are not in the UNSPEC_LVX/STVX form (with the
40357 explicit "& -16") since this leads to unrecognizable insns. */
40358 rtx body
= PATTERN (insn
);
40359 int i
= INSN_UID (insn
);
40361 if (insn_entry
[i
].is_load
)
40363 if (GET_CODE (body
) == SET
)
40365 rtx rhs
= SET_SRC (body
);
40366 gcc_assert (GET_CODE (rhs
) == MEM
);
40367 if (GET_CODE (XEXP (rhs
, 0)) == AND
)
40370 *special
= SH_NOSWAP_LD
;
40377 if (insn_entry
[i
].is_store
)
40379 if (GET_CODE (body
) == SET
40380 && GET_CODE (SET_SRC (body
)) != UNSPEC
)
40382 rtx lhs
= SET_DEST (body
);
40383 gcc_assert (GET_CODE (lhs
) == MEM
);
40384 if (GET_CODE (XEXP (lhs
, 0)) == AND
)
40387 *special
= SH_NOSWAP_ST
;
40394 /* A convert to single precision can be left as is provided that
40395 all of its uses are in xxspltw instructions that splat BE element
40397 if (GET_CODE (body
) == SET
40398 && GET_CODE (SET_SRC (body
)) == UNSPEC
40399 && XINT (SET_SRC (body
), 1) == UNSPEC_VSX_CVDPSPN
)
40402 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
40404 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
40406 struct df_link
*link
= DF_REF_CHAIN (def
);
40410 for (; link
; link
= link
->next
) {
40411 rtx use_insn
= DF_REF_INSN (link
->ref
);
40412 rtx use_body
= PATTERN (use_insn
);
40413 if (GET_CODE (use_body
) != SET
40414 || GET_CODE (SET_SRC (use_body
)) != UNSPEC
40415 || XINT (SET_SRC (use_body
), 1) != UNSPEC_VSX_XXSPLTW
40416 || XEXP (XEXP (SET_SRC (use_body
), 0), 1) != const0_rtx
)
40424 /* A concatenation of two doublewords is ok if we reverse the
40425 order of the inputs. */
40426 if (GET_CODE (body
) == SET
40427 && GET_CODE (SET_SRC (body
)) == VEC_CONCAT
40428 && (GET_MODE (SET_SRC (body
)) == V2DFmode
40429 || GET_MODE (SET_SRC (body
)) == V2DImode
))
40431 *special
= SH_CONCAT
;
40435 /* V2DF reductions are always swappable. */
40436 if (GET_CODE (body
) == PARALLEL
)
40438 rtx expr
= XVECEXP (body
, 0, 0);
40439 if (GET_CODE (expr
) == SET
40440 && v2df_reduction_p (SET_SRC (expr
)))
40444 /* An UNSPEC_VPERM is ok if the mask operand is loaded from the
40446 if (GET_CODE (body
) == SET
40447 && GET_CODE (SET_SRC (body
)) == UNSPEC
40448 && XINT (SET_SRC (body
), 1) == UNSPEC_VPERM
40449 && XVECLEN (SET_SRC (body
), 0) == 3
40450 && GET_CODE (XVECEXP (SET_SRC (body
), 0, 2)) == REG
)
40452 rtx mask_reg
= XVECEXP (SET_SRC (body
), 0, 2);
40453 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
40455 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
40456 if (rtx_equal_p (DF_REF_REG (use
), mask_reg
))
40458 struct df_link
*def_link
= DF_REF_CHAIN (use
);
40459 /* Punt if multiple definitions for this reg. */
40460 if (def_link
&& !def_link
->next
&&
40461 const_load_sequence_p (insn_entry
,
40462 DF_REF_INSN (def_link
->ref
)))
40464 *special
= SH_VPERM
;
40470 /* Otherwise check the operands for vector lane violations. */
40471 return rtx_is_swappable_p (body
, special
);
40474 enum chain_purpose
{ FOR_LOADS
, FOR_STORES
};
40476 /* Return true if the UD or DU chain headed by LINK is non-empty,
40477 and every entry on the chain references an insn that is a
40478 register swap. Furthermore, if PURPOSE is FOR_LOADS, each such
40479 register swap must have only permuting loads as reaching defs.
40480 If PURPOSE is FOR_STORES, each such register swap must have only
40481 register swaps or permuting stores as reached uses. */
40483 chain_contains_only_swaps (swap_web_entry
*insn_entry
, struct df_link
*link
,
40484 enum chain_purpose purpose
)
40489 for (; link
; link
= link
->next
)
40491 if (!ALTIVEC_OR_VSX_VECTOR_MODE (GET_MODE (DF_REF_REG (link
->ref
))))
40494 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
40497 rtx reached_insn
= DF_REF_INSN (link
->ref
);
40498 unsigned uid
= INSN_UID (reached_insn
);
40499 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (reached_insn
);
40501 if (!insn_entry
[uid
].is_swap
|| insn_entry
[uid
].is_load
40502 || insn_entry
[uid
].is_store
)
40505 if (purpose
== FOR_LOADS
)
40508 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
40510 struct df_link
*swap_link
= DF_REF_CHAIN (use
);
40514 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
40517 rtx swap_def_insn
= DF_REF_INSN (swap_link
->ref
);
40518 unsigned uid2
= INSN_UID (swap_def_insn
);
40520 /* Only permuting loads are allowed. */
40521 if (!insn_entry
[uid2
].is_swap
|| !insn_entry
[uid2
].is_load
)
40524 swap_link
= swap_link
->next
;
40528 else if (purpose
== FOR_STORES
)
40531 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
40533 struct df_link
*swap_link
= DF_REF_CHAIN (def
);
40537 if (DF_REF_IS_ARTIFICIAL (link
->ref
))
40540 rtx swap_use_insn
= DF_REF_INSN (swap_link
->ref
);
40541 unsigned uid2
= INSN_UID (swap_use_insn
);
40543 /* Permuting stores or register swaps are allowed. */
40544 if (!insn_entry
[uid2
].is_swap
|| insn_entry
[uid2
].is_load
)
40547 swap_link
= swap_link
->next
;
40556 /* Mark the xxswapdi instructions associated with permuting loads and
40557 stores for removal. Note that we only flag them for deletion here,
40558 as there is a possibility of a swap being reached from multiple
40561 mark_swaps_for_removal (swap_web_entry
*insn_entry
, unsigned int i
)
40563 rtx insn
= insn_entry
[i
].insn
;
40564 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
40566 if (insn_entry
[i
].is_load
)
40569 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
40571 struct df_link
*link
= DF_REF_CHAIN (def
);
40573 /* We know by now that these are swaps, so we can delete
40574 them confidently. */
40577 rtx use_insn
= DF_REF_INSN (link
->ref
);
40578 insn_entry
[INSN_UID (use_insn
)].will_delete
= 1;
40583 else if (insn_entry
[i
].is_store
)
40586 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
40588 /* Ignore uses for addressability. */
40589 machine_mode mode
= GET_MODE (DF_REF_REG (use
));
40590 if (!ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
40593 struct df_link
*link
= DF_REF_CHAIN (use
);
40595 /* We know by now that these are swaps, so we can delete
40596 them confidently. */
40599 rtx def_insn
= DF_REF_INSN (link
->ref
);
40600 insn_entry
[INSN_UID (def_insn
)].will_delete
= 1;
40607 /* OP is either a CONST_VECTOR or an expression containing one.
40608 Swap the first half of the vector with the second in the first
40609 case. Recurse to find it in the second. */
40611 swap_const_vector_halves (rtx op
)
40614 enum rtx_code code
= GET_CODE (op
);
40615 if (GET_CODE (op
) == CONST_VECTOR
)
40617 int half_units
= GET_MODE_NUNITS (GET_MODE (op
)) / 2;
40618 for (i
= 0; i
< half_units
; ++i
)
40620 rtx temp
= CONST_VECTOR_ELT (op
, i
);
40621 CONST_VECTOR_ELT (op
, i
) = CONST_VECTOR_ELT (op
, i
+ half_units
);
40622 CONST_VECTOR_ELT (op
, i
+ half_units
) = temp
;
40628 const char *fmt
= GET_RTX_FORMAT (code
);
40629 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
40630 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
40631 swap_const_vector_halves (XEXP (op
, i
));
40632 else if (fmt
[i
] == 'E')
40633 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
40634 swap_const_vector_halves (XVECEXP (op
, i
, j
));
40638 /* Find all subregs of a vector expression that perform a narrowing,
40639 and adjust the subreg index to account for doubleword swapping. */
40641 adjust_subreg_index (rtx op
)
40643 enum rtx_code code
= GET_CODE (op
);
40645 && (GET_MODE_SIZE (GET_MODE (op
))
40646 < GET_MODE_SIZE (GET_MODE (XEXP (op
, 0)))))
40648 unsigned int index
= SUBREG_BYTE (op
);
40653 SUBREG_BYTE (op
) = index
;
40656 const char *fmt
= GET_RTX_FORMAT (code
);
40658 for (i
= 0; i
< GET_RTX_LENGTH (code
); ++i
)
40659 if (fmt
[i
] == 'e' || fmt
[i
] == 'u')
40660 adjust_subreg_index (XEXP (op
, i
));
40661 else if (fmt
[i
] == 'E')
40662 for (j
= 0; j
< XVECLEN (op
, i
); ++j
)
40663 adjust_subreg_index (XVECEXP (op
, i
, j
));
40666 /* Convert the non-permuting load INSN to a permuting one. */
40668 permute_load (rtx_insn
*insn
)
40670 rtx body
= PATTERN (insn
);
40671 rtx mem_op
= SET_SRC (body
);
40672 rtx tgt_reg
= SET_DEST (body
);
40673 machine_mode mode
= GET_MODE (tgt_reg
);
40674 int n_elts
= GET_MODE_NUNITS (mode
);
40675 int half_elts
= n_elts
/ 2;
40676 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
40678 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
40679 XVECEXP (par
, 0, i
) = GEN_INT (j
);
40680 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
40681 XVECEXP (par
, 0, i
) = GEN_INT (j
);
40682 rtx sel
= gen_rtx_VEC_SELECT (mode
, mem_op
, par
);
40683 SET_SRC (body
) = sel
;
40684 INSN_CODE (insn
) = -1; /* Force re-recognition. */
40685 df_insn_rescan (insn
);
40688 fprintf (dump_file
, "Replacing load %d with permuted load\n",
40692 /* Convert the non-permuting store INSN to a permuting one. */
40694 permute_store (rtx_insn
*insn
)
40696 rtx body
= PATTERN (insn
);
40697 rtx src_reg
= SET_SRC (body
);
40698 machine_mode mode
= GET_MODE (src_reg
);
40699 int n_elts
= GET_MODE_NUNITS (mode
);
40700 int half_elts
= n_elts
/ 2;
40701 rtx par
= gen_rtx_PARALLEL (mode
, rtvec_alloc (n_elts
));
40703 for (i
= 0, j
= half_elts
; i
< half_elts
; ++i
, ++j
)
40704 XVECEXP (par
, 0, i
) = GEN_INT (j
);
40705 for (i
= half_elts
, j
= 0; j
< half_elts
; ++i
, ++j
)
40706 XVECEXP (par
, 0, i
) = GEN_INT (j
);
40707 rtx sel
= gen_rtx_VEC_SELECT (mode
, src_reg
, par
);
40708 SET_SRC (body
) = sel
;
40709 INSN_CODE (insn
) = -1; /* Force re-recognition. */
40710 df_insn_rescan (insn
);
40713 fprintf (dump_file
, "Replacing store %d with permuted store\n",
40717 /* Given OP that contains a vector extract operation, adjust the index
40718 of the extracted lane to account for the doubleword swap. */
40720 adjust_extract (rtx_insn
*insn
)
40722 rtx pattern
= PATTERN (insn
);
40723 if (GET_CODE (pattern
) == PARALLEL
)
40724 pattern
= XVECEXP (pattern
, 0, 0);
40725 rtx src
= SET_SRC (pattern
);
40726 /* The vec_select may be wrapped in a vec_duplicate for a splat, so
40727 account for that. */
40728 rtx sel
= GET_CODE (src
) == VEC_DUPLICATE
? XEXP (src
, 0) : src
;
40729 rtx par
= XEXP (sel
, 1);
40730 int half_elts
= GET_MODE_NUNITS (GET_MODE (XEXP (sel
, 0))) >> 1;
40731 int lane
= INTVAL (XVECEXP (par
, 0, 0));
40732 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
40733 XVECEXP (par
, 0, 0) = GEN_INT (lane
);
40734 INSN_CODE (insn
) = -1; /* Force re-recognition. */
40735 df_insn_rescan (insn
);
40738 fprintf (dump_file
, "Changing lane for extract %d\n", INSN_UID (insn
));
40741 /* Given OP that contains a vector direct-splat operation, adjust the index
40742 of the source lane to account for the doubleword swap. */
40744 adjust_splat (rtx_insn
*insn
)
40746 rtx body
= PATTERN (insn
);
40747 rtx unspec
= XEXP (body
, 1);
40748 int half_elts
= GET_MODE_NUNITS (GET_MODE (unspec
)) >> 1;
40749 int lane
= INTVAL (XVECEXP (unspec
, 0, 1));
40750 lane
= lane
>= half_elts
? lane
- half_elts
: lane
+ half_elts
;
40751 XVECEXP (unspec
, 0, 1) = GEN_INT (lane
);
40752 INSN_CODE (insn
) = -1; /* Force re-recognition. */
40753 df_insn_rescan (insn
);
40756 fprintf (dump_file
, "Changing lane for splat %d\n", INSN_UID (insn
));
40759 /* Given OP that contains an XXPERMDI operation (that is not a doubleword
40760 swap), reverse the order of the source operands and adjust the indices
40761 of the source lanes to account for doubleword reversal. */
40763 adjust_xxpermdi (rtx_insn
*insn
)
40765 rtx set
= PATTERN (insn
);
40766 rtx select
= XEXP (set
, 1);
40767 rtx concat
= XEXP (select
, 0);
40768 rtx src0
= XEXP (concat
, 0);
40769 XEXP (concat
, 0) = XEXP (concat
, 1);
40770 XEXP (concat
, 1) = src0
;
40771 rtx parallel
= XEXP (select
, 1);
40772 int lane0
= INTVAL (XVECEXP (parallel
, 0, 0));
40773 int lane1
= INTVAL (XVECEXP (parallel
, 0, 1));
40774 int new_lane0
= 3 - lane1
;
40775 int new_lane1
= 3 - lane0
;
40776 XVECEXP (parallel
, 0, 0) = GEN_INT (new_lane0
);
40777 XVECEXP (parallel
, 0, 1) = GEN_INT (new_lane1
);
40778 INSN_CODE (insn
) = -1; /* Force re-recognition. */
40779 df_insn_rescan (insn
);
40782 fprintf (dump_file
, "Changing lanes for xxpermdi %d\n", INSN_UID (insn
));
40785 /* Given OP that contains a VEC_CONCAT operation of two doublewords,
40786 reverse the order of those inputs. */
40788 adjust_concat (rtx_insn
*insn
)
40790 rtx set
= PATTERN (insn
);
40791 rtx concat
= XEXP (set
, 1);
40792 rtx src0
= XEXP (concat
, 0);
40793 XEXP (concat
, 0) = XEXP (concat
, 1);
40794 XEXP (concat
, 1) = src0
;
40795 INSN_CODE (insn
) = -1; /* Force re-recognition. */
40796 df_insn_rescan (insn
);
40799 fprintf (dump_file
, "Reversing inputs for concat %d\n", INSN_UID (insn
));
40802 /* Given an UNSPEC_VPERM insn, modify the mask loaded from the
40803 constant pool to reflect swapped doublewords. */
40805 adjust_vperm (rtx_insn
*insn
)
40807 /* We previously determined that the UNSPEC_VPERM was fed by a
40808 swap of a swapping load of a TOC-relative constant pool symbol.
40809 Find the MEM in the swapping load and replace it with a MEM for
40810 the adjusted mask constant. */
40811 rtx set
= PATTERN (insn
);
40812 rtx mask_reg
= XVECEXP (SET_SRC (set
), 0, 2);
40814 /* Find the swap. */
40815 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
40817 rtx_insn
*swap_insn
= 0;
40818 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
40819 if (rtx_equal_p (DF_REF_REG (use
), mask_reg
))
40821 struct df_link
*def_link
= DF_REF_CHAIN (use
);
40822 gcc_assert (def_link
&& !def_link
->next
);
40823 swap_insn
= DF_REF_INSN (def_link
->ref
);
40826 gcc_assert (swap_insn
);
40828 /* Find the load. */
40829 insn_info
= DF_INSN_INFO_GET (swap_insn
);
40830 rtx_insn
*load_insn
= 0;
40831 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
40833 struct df_link
*def_link
= DF_REF_CHAIN (use
);
40834 gcc_assert (def_link
&& !def_link
->next
);
40835 load_insn
= DF_REF_INSN (def_link
->ref
);
40838 gcc_assert (load_insn
);
40840 /* Find the TOC-relative symbol access. */
40841 insn_info
= DF_INSN_INFO_GET (load_insn
);
40842 rtx_insn
*tocrel_insn
= 0;
40843 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
40845 struct df_link
*def_link
= DF_REF_CHAIN (use
);
40846 gcc_assert (def_link
&& !def_link
->next
);
40847 tocrel_insn
= DF_REF_INSN (def_link
->ref
);
40850 gcc_assert (tocrel_insn
);
40852 /* Find the embedded CONST_VECTOR. We have to call toc_relative_expr_p
40853 to set tocrel_base; otherwise it would be unnecessary as we've
40854 already established it will return true. */
40856 rtx tocrel_expr
= SET_SRC (PATTERN (tocrel_insn
));
40857 /* There is an extra level of indirection for small/large code models. */
40858 if (GET_CODE (tocrel_expr
) == MEM
)
40859 tocrel_expr
= XEXP (tocrel_expr
, 0);
40860 if (!toc_relative_expr_p (tocrel_expr
, false))
40861 gcc_unreachable ();
40862 split_const (XVECEXP (tocrel_base
, 0, 0), &base
, &offset
);
40863 rtx const_vector
= get_pool_constant (base
);
40864 /* With the extra indirection, get_pool_constant will produce the
40865 real constant from the reg_equal expression, so get the real
40867 if (GET_CODE (const_vector
) == SYMBOL_REF
)
40868 const_vector
= get_pool_constant (const_vector
);
40869 gcc_assert (GET_CODE (const_vector
) == CONST_VECTOR
);
40871 /* Create an adjusted mask from the initial mask. */
40872 unsigned int new_mask
[16], i
, val
;
40873 for (i
= 0; i
< 16; ++i
) {
40874 val
= INTVAL (XVECEXP (const_vector
, 0, i
));
40876 new_mask
[i
] = (val
+ 8) % 16;
40878 new_mask
[i
] = ((val
+ 8) % 16) + 16;
40881 /* Create a new CONST_VECTOR and a MEM that references it. */
40882 rtx vals
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
40883 for (i
= 0; i
< 16; ++i
)
40884 XVECEXP (vals
, 0, i
) = GEN_INT (new_mask
[i
]);
40885 rtx new_const_vector
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (vals
, 0));
40886 rtx new_mem
= force_const_mem (V16QImode
, new_const_vector
);
40887 /* This gives us a MEM whose base operand is a SYMBOL_REF, which we
40888 can't recognize. Force the SYMBOL_REF into a register. */
40889 if (!REG_P (XEXP (new_mem
, 0))) {
40890 rtx base_reg
= force_reg (Pmode
, XEXP (new_mem
, 0));
40891 XEXP (new_mem
, 0) = base_reg
;
40892 /* Move the newly created insn ahead of the load insn. */
40893 rtx_insn
*force_insn
= get_last_insn ();
40894 remove_insn (force_insn
);
40895 rtx_insn
*before_load_insn
= PREV_INSN (load_insn
);
40896 add_insn_after (force_insn
, before_load_insn
, BLOCK_FOR_INSN (load_insn
));
40897 df_insn_rescan (before_load_insn
);
40898 df_insn_rescan (force_insn
);
40901 /* Replace the MEM in the load instruction and rescan it. */
40902 XEXP (SET_SRC (PATTERN (load_insn
)), 0) = new_mem
;
40903 INSN_CODE (load_insn
) = -1; /* Force re-recognition. */
40904 df_insn_rescan (load_insn
);
40907 fprintf (dump_file
, "Adjusting mask for vperm %d\n", INSN_UID (insn
));
40910 /* The insn described by INSN_ENTRY[I] can be swapped, but only
40911 with special handling. Take care of that here. */
40913 handle_special_swappables (swap_web_entry
*insn_entry
, unsigned i
)
40915 rtx_insn
*insn
= insn_entry
[i
].insn
;
40916 rtx body
= PATTERN (insn
);
40918 switch (insn_entry
[i
].special_handling
)
40921 gcc_unreachable ();
40922 case SH_CONST_VECTOR
:
40924 /* A CONST_VECTOR will only show up somewhere in the RHS of a SET. */
40925 gcc_assert (GET_CODE (body
) == SET
);
40926 rtx rhs
= SET_SRC (body
);
40927 swap_const_vector_halves (rhs
);
40929 fprintf (dump_file
, "Swapping constant halves in insn %d\n", i
);
40933 /* A subreg of the same size is already safe. For subregs that
40934 select a smaller portion of a reg, adjust the index for
40935 swapped doublewords. */
40936 adjust_subreg_index (body
);
40938 fprintf (dump_file
, "Adjusting subreg in insn %d\n", i
);
40941 /* Convert a non-permuting load to a permuting one. */
40942 permute_load (insn
);
40945 /* Convert a non-permuting store to a permuting one. */
40946 permute_store (insn
);
40949 /* Change the lane on an extract operation. */
40950 adjust_extract (insn
);
40953 /* Change the lane on a direct-splat operation. */
40954 adjust_splat (insn
);
40957 /* Change the lanes on an XXPERMDI operation. */
40958 adjust_xxpermdi (insn
);
40961 /* Reverse the order of a concatenation operation. */
40962 adjust_concat (insn
);
40965 /* Change the mask loaded from the constant pool for a VPERM. */
40966 adjust_vperm (insn
);
40971 /* Find the insn from the Ith table entry, which is known to be a
40972 register swap Y = SWAP(X). Replace it with a copy Y = X. */
40974 replace_swap_with_copy (swap_web_entry
*insn_entry
, unsigned i
)
40976 rtx_insn
*insn
= insn_entry
[i
].insn
;
40977 rtx body
= PATTERN (insn
);
40978 rtx src_reg
= XEXP (SET_SRC (body
), 0);
40979 rtx copy
= gen_rtx_SET (SET_DEST (body
), src_reg
);
40980 rtx_insn
*new_insn
= emit_insn_before (copy
, insn
);
40981 set_block_for_insn (new_insn
, BLOCK_FOR_INSN (insn
));
40982 df_insn_rescan (new_insn
);
40986 unsigned int new_uid
= INSN_UID (new_insn
);
40987 fprintf (dump_file
, "Replacing swap %d with copy %d\n", i
, new_uid
);
40990 df_insn_delete (insn
);
40991 remove_insn (insn
);
40992 insn
->set_deleted ();
40995 /* Dump the swap table to DUMP_FILE. */
40997 dump_swap_insn_table (swap_web_entry
*insn_entry
)
40999 int e
= get_max_uid ();
41000 fprintf (dump_file
, "\nRelevant insns with their flag settings\n\n");
41002 for (int i
= 0; i
< e
; ++i
)
41003 if (insn_entry
[i
].is_relevant
)
41005 swap_web_entry
*pred_entry
= (swap_web_entry
*)insn_entry
[i
].pred ();
41006 fprintf (dump_file
, "%6d %6d ", i
,
41007 pred_entry
&& pred_entry
->insn
41008 ? INSN_UID (pred_entry
->insn
) : 0);
41009 if (insn_entry
[i
].is_load
)
41010 fputs ("load ", dump_file
);
41011 if (insn_entry
[i
].is_store
)
41012 fputs ("store ", dump_file
);
41013 if (insn_entry
[i
].is_swap
)
41014 fputs ("swap ", dump_file
);
41015 if (insn_entry
[i
].is_live_in
)
41016 fputs ("live-in ", dump_file
);
41017 if (insn_entry
[i
].is_live_out
)
41018 fputs ("live-out ", dump_file
);
41019 if (insn_entry
[i
].contains_subreg
)
41020 fputs ("subreg ", dump_file
);
41021 if (insn_entry
[i
].is_128_int
)
41022 fputs ("int128 ", dump_file
);
41023 if (insn_entry
[i
].is_call
)
41024 fputs ("call ", dump_file
);
41025 if (insn_entry
[i
].is_swappable
)
41027 fputs ("swappable ", dump_file
);
41028 if (insn_entry
[i
].special_handling
== SH_CONST_VECTOR
)
41029 fputs ("special:constvec ", dump_file
);
41030 else if (insn_entry
[i
].special_handling
== SH_SUBREG
)
41031 fputs ("special:subreg ", dump_file
);
41032 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_LD
)
41033 fputs ("special:load ", dump_file
);
41034 else if (insn_entry
[i
].special_handling
== SH_NOSWAP_ST
)
41035 fputs ("special:store ", dump_file
);
41036 else if (insn_entry
[i
].special_handling
== SH_EXTRACT
)
41037 fputs ("special:extract ", dump_file
);
41038 else if (insn_entry
[i
].special_handling
== SH_SPLAT
)
41039 fputs ("special:splat ", dump_file
);
41040 else if (insn_entry
[i
].special_handling
== SH_XXPERMDI
)
41041 fputs ("special:xxpermdi ", dump_file
);
41042 else if (insn_entry
[i
].special_handling
== SH_CONCAT
)
41043 fputs ("special:concat ", dump_file
);
41044 else if (insn_entry
[i
].special_handling
== SH_VPERM
)
41045 fputs ("special:vperm ", dump_file
);
41047 if (insn_entry
[i
].web_not_optimizable
)
41048 fputs ("unoptimizable ", dump_file
);
41049 if (insn_entry
[i
].will_delete
)
41050 fputs ("delete ", dump_file
);
41051 fputs ("\n", dump_file
);
41053 fputs ("\n", dump_file
);
41056 /* Return RTX with its address canonicalized to (reg) or (+ reg reg).
41057 Here RTX is an (& addr (const_int -16)). Always return a new copy
41058 to avoid problems with combine. */
41060 alignment_with_canonical_addr (rtx align
)
41063 rtx addr
= XEXP (align
, 0);
41068 else if (GET_CODE (addr
) == PLUS
)
41070 rtx addrop0
= XEXP (addr
, 0);
41071 rtx addrop1
= XEXP (addr
, 1);
41073 if (!REG_P (addrop0
))
41074 addrop0
= force_reg (GET_MODE (addrop0
), addrop0
);
41076 if (!REG_P (addrop1
))
41077 addrop1
= force_reg (GET_MODE (addrop1
), addrop1
);
41079 canon
= gen_rtx_PLUS (GET_MODE (addr
), addrop0
, addrop1
);
41083 canon
= force_reg (GET_MODE (addr
), addr
);
41085 return gen_rtx_AND (GET_MODE (align
), canon
, GEN_INT (-16));
41088 /* Check whether an rtx is an alignment mask, and if so, return
41089 a fully-expanded rtx for the masking operation. */
41091 alignment_mask (rtx_insn
*insn
)
41093 rtx body
= PATTERN (insn
);
41095 if (GET_CODE (body
) != SET
41096 || GET_CODE (SET_SRC (body
)) != AND
41097 || !REG_P (XEXP (SET_SRC (body
), 0)))
41100 rtx mask
= XEXP (SET_SRC (body
), 1);
41102 if (GET_CODE (mask
) == CONST_INT
)
41104 if (INTVAL (mask
) == -16)
41105 return alignment_with_canonical_addr (SET_SRC (body
));
41113 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
41117 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
41119 if (!rtx_equal_p (DF_REF_REG (use
), mask
))
41122 struct df_link
*def_link
= DF_REF_CHAIN (use
);
41123 if (!def_link
|| def_link
->next
)
41126 rtx_insn
*const_insn
= DF_REF_INSN (def_link
->ref
);
41127 rtx const_body
= PATTERN (const_insn
);
41128 if (GET_CODE (const_body
) != SET
)
41131 real_mask
= SET_SRC (const_body
);
41133 if (GET_CODE (real_mask
) != CONST_INT
41134 || INTVAL (real_mask
) != -16)
41138 if (real_mask
== 0)
41141 return alignment_with_canonical_addr (SET_SRC (body
));
41144 /* Given INSN that's a load or store based at BASE_REG, look for a
41145 feeding computation that aligns its address on a 16-byte boundary. */
41147 find_alignment_op (rtx_insn
*insn
, rtx base_reg
)
41150 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
41151 rtx and_operation
= 0;
41153 FOR_EACH_INSN_INFO_USE (base_use
, insn_info
)
41155 if (!rtx_equal_p (DF_REF_REG (base_use
), base_reg
))
41158 struct df_link
*base_def_link
= DF_REF_CHAIN (base_use
);
41159 if (!base_def_link
|| base_def_link
->next
)
41162 rtx_insn
*and_insn
= DF_REF_INSN (base_def_link
->ref
);
41163 and_operation
= alignment_mask (and_insn
);
41164 if (and_operation
!= 0)
41168 return and_operation
;
41171 struct del_info
{ bool replace
; rtx_insn
*replace_insn
; };
41173 /* If INSN is the load for an lvx pattern, put it in canonical form. */
41175 recombine_lvx_pattern (rtx_insn
*insn
, del_info
*to_delete
)
41177 rtx body
= PATTERN (insn
);
41178 gcc_assert (GET_CODE (body
) == SET
41179 && GET_CODE (SET_SRC (body
)) == VEC_SELECT
41180 && GET_CODE (XEXP (SET_SRC (body
), 0)) == MEM
);
41182 rtx mem
= XEXP (SET_SRC (body
), 0);
41183 rtx base_reg
= XEXP (mem
, 0);
41185 rtx and_operation
= find_alignment_op (insn
, base_reg
);
41187 if (and_operation
!= 0)
41190 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
41191 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
41193 struct df_link
*link
= DF_REF_CHAIN (def
);
41194 if (!link
|| link
->next
)
41197 rtx_insn
*swap_insn
= DF_REF_INSN (link
->ref
);
41198 if (!insn_is_swap_p (swap_insn
)
41199 || insn_is_load_p (swap_insn
)
41200 || insn_is_store_p (swap_insn
))
41203 /* Expected lvx pattern found. Change the swap to
41204 a copy, and propagate the AND operation into the
41206 to_delete
[INSN_UID (swap_insn
)].replace
= true;
41207 to_delete
[INSN_UID (swap_insn
)].replace_insn
= swap_insn
;
41209 XEXP (mem
, 0) = and_operation
;
41210 SET_SRC (body
) = mem
;
41211 INSN_CODE (insn
) = -1; /* Force re-recognition. */
41212 df_insn_rescan (insn
);
41215 fprintf (dump_file
, "lvx opportunity found at %d\n",
41221 /* If INSN is the store for an stvx pattern, put it in canonical form. */
41223 recombine_stvx_pattern (rtx_insn
*insn
, del_info
*to_delete
)
41225 rtx body
= PATTERN (insn
);
41226 gcc_assert (GET_CODE (body
) == SET
41227 && GET_CODE (SET_DEST (body
)) == MEM
41228 && GET_CODE (SET_SRC (body
)) == VEC_SELECT
);
41229 rtx mem
= SET_DEST (body
);
41230 rtx base_reg
= XEXP (mem
, 0);
41232 rtx and_operation
= find_alignment_op (insn
, base_reg
);
41234 if (and_operation
!= 0)
41236 rtx src_reg
= XEXP (SET_SRC (body
), 0);
41238 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
41239 FOR_EACH_INSN_INFO_USE (src_use
, insn_info
)
41241 if (!rtx_equal_p (DF_REF_REG (src_use
), src_reg
))
41244 struct df_link
*link
= DF_REF_CHAIN (src_use
);
41245 if (!link
|| link
->next
)
41248 rtx_insn
*swap_insn
= DF_REF_INSN (link
->ref
);
41249 if (!insn_is_swap_p (swap_insn
)
41250 || insn_is_load_p (swap_insn
)
41251 || insn_is_store_p (swap_insn
))
41254 /* Expected stvx pattern found. Change the swap to
41255 a copy, and propagate the AND operation into the
41257 to_delete
[INSN_UID (swap_insn
)].replace
= true;
41258 to_delete
[INSN_UID (swap_insn
)].replace_insn
= swap_insn
;
41260 XEXP (mem
, 0) = and_operation
;
41261 SET_SRC (body
) = src_reg
;
41262 INSN_CODE (insn
) = -1; /* Force re-recognition. */
41263 df_insn_rescan (insn
);
41266 fprintf (dump_file
, "stvx opportunity found at %d\n",
41272 /* Look for patterns created from builtin lvx and stvx calls, and
41273 canonicalize them to be properly recognized as such. */
41275 recombine_lvx_stvx_patterns (function
*fun
)
41281 int num_insns
= get_max_uid ();
41282 del_info
*to_delete
= XCNEWVEC (del_info
, num_insns
);
41284 FOR_ALL_BB_FN (bb
, fun
)
41285 FOR_BB_INSNS (bb
, insn
)
41287 if (!NONDEBUG_INSN_P (insn
))
41290 if (insn_is_load_p (insn
) && insn_is_swap_p (insn
))
41291 recombine_lvx_pattern (insn
, to_delete
);
41292 else if (insn_is_store_p (insn
) && insn_is_swap_p (insn
))
41293 recombine_stvx_pattern (insn
, to_delete
);
41296 /* Turning swaps into copies is delayed until now, to avoid problems
41297 with deleting instructions during the insn walk. */
41298 for (i
= 0; i
< num_insns
; i
++)
41299 if (to_delete
[i
].replace
)
41301 rtx swap_body
= PATTERN (to_delete
[i
].replace_insn
);
41302 rtx src_reg
= XEXP (SET_SRC (swap_body
), 0);
41303 rtx copy
= gen_rtx_SET (SET_DEST (swap_body
), src_reg
);
41304 rtx_insn
*new_insn
= emit_insn_before (copy
,
41305 to_delete
[i
].replace_insn
);
41306 set_block_for_insn (new_insn
,
41307 BLOCK_FOR_INSN (to_delete
[i
].replace_insn
));
41308 df_insn_rescan (new_insn
);
41309 df_insn_delete (to_delete
[i
].replace_insn
);
41310 remove_insn (to_delete
[i
].replace_insn
);
41311 to_delete
[i
].replace_insn
->set_deleted ();
41317 /* Main entry point for this pass. */
41319 rs6000_analyze_swaps (function
*fun
)
41321 swap_web_entry
*insn_entry
;
41323 rtx_insn
*insn
, *curr_insn
= 0;
41325 /* Dataflow analysis for use-def chains. */
41326 df_set_flags (DF_RD_PRUNE_DEAD_DEFS
);
41327 df_chain_add_problem (DF_DU_CHAIN
| DF_UD_CHAIN
);
41329 df_set_flags (DF_DEFER_INSN_RESCAN
);
41331 /* Pre-pass to recombine lvx and stvx patterns so we don't lose info. */
41332 recombine_lvx_stvx_patterns (fun
);
41334 /* Allocate structure to represent webs of insns. */
41335 insn_entry
= XCNEWVEC (swap_web_entry
, get_max_uid ());
41337 /* Walk the insns to gather basic data. */
41338 FOR_ALL_BB_FN (bb
, fun
)
41339 FOR_BB_INSNS_SAFE (bb
, insn
, curr_insn
)
41341 unsigned int uid
= INSN_UID (insn
);
41342 if (NONDEBUG_INSN_P (insn
))
41344 insn_entry
[uid
].insn
= insn
;
41346 if (GET_CODE (insn
) == CALL_INSN
)
41347 insn_entry
[uid
].is_call
= 1;
41349 /* Walk the uses and defs to see if we mention vector regs.
41350 Record any constraints on optimization of such mentions. */
41351 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
41353 FOR_EACH_INSN_INFO_USE (mention
, insn_info
)
41355 /* We use DF_REF_REAL_REG here to get inside any subregs. */
41356 machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
41358 /* If a use gets its value from a call insn, it will be
41359 a hard register and will look like (reg:V4SI 3 3).
41360 The df analysis creates two mentions for GPR3 and GPR4,
41361 both DImode. We must recognize this and treat it as a
41362 vector mention to ensure the call is unioned with this
41364 if (mode
== DImode
&& DF_REF_INSN_INFO (mention
))
41366 rtx feeder
= DF_REF_INSN (mention
);
41367 /* FIXME: It is pretty hard to get from the df mention
41368 to the mode of the use in the insn. We arbitrarily
41369 pick a vector mode here, even though the use might
41370 be a real DImode. We can be too conservative
41371 (create a web larger than necessary) because of
41372 this, so consider eventually fixing this. */
41373 if (GET_CODE (feeder
) == CALL_INSN
)
41377 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
) || mode
== TImode
)
41379 insn_entry
[uid
].is_relevant
= 1;
41380 if (mode
== TImode
|| mode
== V1TImode
41381 || FLOAT128_VECTOR_P (mode
))
41382 insn_entry
[uid
].is_128_int
= 1;
41383 if (DF_REF_INSN_INFO (mention
))
41384 insn_entry
[uid
].contains_subreg
41385 = !rtx_equal_p (DF_REF_REG (mention
),
41386 DF_REF_REAL_REG (mention
));
41387 union_defs (insn_entry
, insn
, mention
);
41390 FOR_EACH_INSN_INFO_DEF (mention
, insn_info
)
41392 /* We use DF_REF_REAL_REG here to get inside any subregs. */
41393 machine_mode mode
= GET_MODE (DF_REF_REAL_REG (mention
));
41395 /* If we're loading up a hard vector register for a call,
41396 it looks like (set (reg:V4SI 9 9) (...)). The df
41397 analysis creates two mentions for GPR9 and GPR10, both
41398 DImode. So relying on the mode from the mentions
41399 isn't sufficient to ensure we union the call into the
41400 web with the parameter setup code. */
41401 if (mode
== DImode
&& GET_CODE (insn
) == SET
41402 && ALTIVEC_OR_VSX_VECTOR_MODE (GET_MODE (SET_DEST (insn
))))
41403 mode
= GET_MODE (SET_DEST (insn
));
41405 if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
) || mode
== TImode
)
41407 insn_entry
[uid
].is_relevant
= 1;
41408 if (mode
== TImode
|| mode
== V1TImode
41409 || FLOAT128_VECTOR_P (mode
))
41410 insn_entry
[uid
].is_128_int
= 1;
41411 if (DF_REF_INSN_INFO (mention
))
41412 insn_entry
[uid
].contains_subreg
41413 = !rtx_equal_p (DF_REF_REG (mention
),
41414 DF_REF_REAL_REG (mention
));
41415 /* REG_FUNCTION_VALUE_P is not valid for subregs. */
41416 else if (REG_FUNCTION_VALUE_P (DF_REF_REG (mention
)))
41417 insn_entry
[uid
].is_live_out
= 1;
41418 union_uses (insn_entry
, insn
, mention
);
41422 if (insn_entry
[uid
].is_relevant
)
41424 /* Determine if this is a load or store. */
41425 insn_entry
[uid
].is_load
= insn_is_load_p (insn
);
41426 insn_entry
[uid
].is_store
= insn_is_store_p (insn
);
41428 /* Determine if this is a doubleword swap. If not,
41429 determine whether it can legally be swapped. */
41430 if (insn_is_swap_p (insn
))
41431 insn_entry
[uid
].is_swap
= 1;
41434 unsigned int special
= SH_NONE
;
41435 insn_entry
[uid
].is_swappable
41436 = insn_is_swappable_p (insn_entry
, insn
, &special
);
41437 if (special
!= SH_NONE
&& insn_entry
[uid
].contains_subreg
)
41438 insn_entry
[uid
].is_swappable
= 0;
41439 else if (special
!= SH_NONE
)
41440 insn_entry
[uid
].special_handling
= special
;
41441 else if (insn_entry
[uid
].contains_subreg
)
41442 insn_entry
[uid
].special_handling
= SH_SUBREG
;
41450 fprintf (dump_file
, "\nSwap insn entry table when first built\n");
41451 dump_swap_insn_table (insn_entry
);
41454 /* Record unoptimizable webs. */
41455 unsigned e
= get_max_uid (), i
;
41456 for (i
= 0; i
< e
; ++i
)
41458 if (!insn_entry
[i
].is_relevant
)
41461 swap_web_entry
*root
41462 = (swap_web_entry
*)(&insn_entry
[i
])->unionfind_root ();
41464 if (insn_entry
[i
].is_live_in
|| insn_entry
[i
].is_live_out
41465 || (insn_entry
[i
].contains_subreg
41466 && insn_entry
[i
].special_handling
!= SH_SUBREG
)
41467 || insn_entry
[i
].is_128_int
|| insn_entry
[i
].is_call
41468 || !(insn_entry
[i
].is_swappable
|| insn_entry
[i
].is_swap
))
41469 root
->web_not_optimizable
= 1;
41471 /* If we have loads or stores that aren't permuting then the
41472 optimization isn't appropriate. */
41473 else if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
41474 && !insn_entry
[i
].is_swap
&& !insn_entry
[i
].is_swappable
)
41475 root
->web_not_optimizable
= 1;
41477 /* If we have permuting loads or stores that are not accompanied
41478 by a register swap, the optimization isn't appropriate. */
41479 else if (insn_entry
[i
].is_load
&& insn_entry
[i
].is_swap
)
41481 rtx insn
= insn_entry
[i
].insn
;
41482 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
41485 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
41487 struct df_link
*link
= DF_REF_CHAIN (def
);
41489 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_LOADS
))
41491 root
->web_not_optimizable
= 1;
41496 else if (insn_entry
[i
].is_store
&& insn_entry
[i
].is_swap
)
41498 rtx insn
= insn_entry
[i
].insn
;
41499 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
41502 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
41504 struct df_link
*link
= DF_REF_CHAIN (use
);
41506 if (!chain_contains_only_swaps (insn_entry
, link
, FOR_STORES
))
41508 root
->web_not_optimizable
= 1;
41517 fprintf (dump_file
, "\nSwap insn entry table after web analysis\n");
41518 dump_swap_insn_table (insn_entry
);
41521 /* For each load and store in an optimizable web (which implies
41522 the loads and stores are permuting), find the associated
41523 register swaps and mark them for removal. Due to various
41524 optimizations we may mark the same swap more than once. Also
41525 perform special handling for swappable insns that require it. */
41526 for (i
= 0; i
< e
; ++i
)
41527 if ((insn_entry
[i
].is_load
|| insn_entry
[i
].is_store
)
41528 && insn_entry
[i
].is_swap
)
41530 swap_web_entry
* root_entry
41531 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
41532 if (!root_entry
->web_not_optimizable
)
41533 mark_swaps_for_removal (insn_entry
, i
);
41535 else if (insn_entry
[i
].is_swappable
&& insn_entry
[i
].special_handling
)
41537 swap_web_entry
* root_entry
41538 = (swap_web_entry
*)((&insn_entry
[i
])->unionfind_root ());
41539 if (!root_entry
->web_not_optimizable
)
41540 handle_special_swappables (insn_entry
, i
);
41543 /* Now delete the swaps marked for removal. */
41544 for (i
= 0; i
< e
; ++i
)
41545 if (insn_entry
[i
].will_delete
)
41546 replace_swap_with_copy (insn_entry
, i
);
41553 const pass_data pass_data_analyze_swaps
=
41555 RTL_PASS
, /* type */
41556 "swaps", /* name */
41557 OPTGROUP_NONE
, /* optinfo_flags */
41558 TV_NONE
, /* tv_id */
41559 0, /* properties_required */
41560 0, /* properties_provided */
41561 0, /* properties_destroyed */
41562 0, /* todo_flags_start */
41563 TODO_df_finish
, /* todo_flags_finish */
41566 class pass_analyze_swaps
: public rtl_opt_pass
41569 pass_analyze_swaps(gcc::context
*ctxt
)
41570 : rtl_opt_pass(pass_data_analyze_swaps
, ctxt
)
41573 /* opt_pass methods: */
41574 virtual bool gate (function
*)
41576 return (optimize
> 0 && !BYTES_BIG_ENDIAN
&& TARGET_VSX
41577 && !TARGET_P9_VECTOR
&& rs6000_optimize_swaps
);
41580 virtual unsigned int execute (function
*fun
)
41582 return rs6000_analyze_swaps (fun
);
41585 }; // class pass_analyze_swaps
41588 make_pass_analyze_swaps (gcc::context
*ctxt
)
41590 return new pass_analyze_swaps (ctxt
);
41593 #ifdef RS6000_GLIBC_ATOMIC_FENV
41594 /* Function declarations for rs6000_atomic_assign_expand_fenv. */
41595 static tree atomic_hold_decl
, atomic_clear_decl
, atomic_update_decl
;
41598 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
41601 rs6000_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
41603 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
)
41605 #ifdef RS6000_GLIBC_ATOMIC_FENV
41606 if (atomic_hold_decl
== NULL_TREE
)
41609 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
41610 get_identifier ("__atomic_feholdexcept"),
41611 build_function_type_list (void_type_node
,
41612 double_ptr_type_node
,
41614 TREE_PUBLIC (atomic_hold_decl
) = 1;
41615 DECL_EXTERNAL (atomic_hold_decl
) = 1;
41618 if (atomic_clear_decl
== NULL_TREE
)
41621 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
41622 get_identifier ("__atomic_feclearexcept"),
41623 build_function_type_list (void_type_node
,
41625 TREE_PUBLIC (atomic_clear_decl
) = 1;
41626 DECL_EXTERNAL (atomic_clear_decl
) = 1;
41629 tree const_double
= build_qualified_type (double_type_node
,
41631 tree const_double_ptr
= build_pointer_type (const_double
);
41632 if (atomic_update_decl
== NULL_TREE
)
41635 = build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
41636 get_identifier ("__atomic_feupdateenv"),
41637 build_function_type_list (void_type_node
,
41640 TREE_PUBLIC (atomic_update_decl
) = 1;
41641 DECL_EXTERNAL (atomic_update_decl
) = 1;
41644 tree fenv_var
= create_tmp_var_raw (double_type_node
);
41645 TREE_ADDRESSABLE (fenv_var
) = 1;
41646 tree fenv_addr
= build1 (ADDR_EXPR
, double_ptr_type_node
, fenv_var
);
41648 *hold
= build_call_expr (atomic_hold_decl
, 1, fenv_addr
);
41649 *clear
= build_call_expr (atomic_clear_decl
, 0);
41650 *update
= build_call_expr (atomic_update_decl
, 1,
41651 fold_convert (const_double_ptr
, fenv_addr
));
41656 tree mffs
= rs6000_builtin_decls
[RS6000_BUILTIN_MFFS
];
41657 tree mtfsf
= rs6000_builtin_decls
[RS6000_BUILTIN_MTFSF
];
41658 tree call_mffs
= build_call_expr (mffs
, 0);
41660 /* Generates the equivalent of feholdexcept (&fenv_var)
41662 *fenv_var = __builtin_mffs ();
41664 *(uint64_t*)&fenv_hold = *(uint64_t*)fenv_var & 0xffffffff00000007LL;
41665 __builtin_mtfsf (0xff, fenv_hold); */
41667 /* Mask to clear everything except for the rounding modes and non-IEEE
41668 arithmetic flag. */
41669 const unsigned HOST_WIDE_INT hold_exception_mask
=
41670 HOST_WIDE_INT_C (0xffffffff00000007);
41672 tree fenv_var
= create_tmp_var_raw (double_type_node
);
41674 tree hold_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_var
, call_mffs
);
41676 tree fenv_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_var
);
41677 tree fenv_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
41678 build_int_cst (uint64_type_node
,
41679 hold_exception_mask
));
41681 tree fenv_hold_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
41684 tree hold_mtfsf
= build_call_expr (mtfsf
, 2,
41685 build_int_cst (unsigned_type_node
, 0xff),
41688 *hold
= build2 (COMPOUND_EXPR
, void_type_node
, hold_mffs
, hold_mtfsf
);
41690 /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT):
41692 double fenv_clear = __builtin_mffs ();
41693 *(uint64_t)&fenv_clear &= 0xffffffff00000000LL;
41694 __builtin_mtfsf (0xff, fenv_clear); */
41696 /* Mask to clear everything except for the rounding modes and non-IEEE
41697 arithmetic flag. */
41698 const unsigned HOST_WIDE_INT clear_exception_mask
=
41699 HOST_WIDE_INT_C (0xffffffff00000000);
41701 tree fenv_clear
= create_tmp_var_raw (double_type_node
);
41703 tree clear_mffs
= build2 (MODIFY_EXPR
, void_type_node
, fenv_clear
, call_mffs
);
41705 tree fenv_clean_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, fenv_clear
);
41706 tree fenv_clear_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
,
41708 build_int_cst (uint64_type_node
,
41709 clear_exception_mask
));
41711 tree fenv_clear_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
41712 fenv_clear_llu_and
);
41714 tree clear_mtfsf
= build_call_expr (mtfsf
, 2,
41715 build_int_cst (unsigned_type_node
, 0xff),
41718 *clear
= build2 (COMPOUND_EXPR
, void_type_node
, clear_mffs
, clear_mtfsf
);
41720 /* Generates the equivalent of feupdateenv (&fenv_var)
41722 double old_fenv = __builtin_mffs ();
41723 double fenv_update;
41724 *(uint64_t*)&fenv_update = (*(uint64_t*)&old & 0xffffffff1fffff00LL) |
41725 (*(uint64_t*)fenv_var 0x1ff80fff);
41726 __builtin_mtfsf (0xff, fenv_update); */
41728 const unsigned HOST_WIDE_INT update_exception_mask
=
41729 HOST_WIDE_INT_C (0xffffffff1fffff00);
41730 const unsigned HOST_WIDE_INT new_exception_mask
=
41731 HOST_WIDE_INT_C (0x1ff80fff);
41733 tree old_fenv
= create_tmp_var_raw (double_type_node
);
41734 tree update_mffs
= build2 (MODIFY_EXPR
, void_type_node
, old_fenv
, call_mffs
);
41736 tree old_llu
= build1 (VIEW_CONVERT_EXPR
, uint64_type_node
, old_fenv
);
41737 tree old_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, old_llu
,
41738 build_int_cst (uint64_type_node
,
41739 update_exception_mask
));
41741 tree new_llu_and
= build2 (BIT_AND_EXPR
, uint64_type_node
, fenv_llu
,
41742 build_int_cst (uint64_type_node
,
41743 new_exception_mask
));
41745 tree new_llu_mask
= build2 (BIT_IOR_EXPR
, uint64_type_node
,
41746 old_llu_and
, new_llu_and
);
41748 tree fenv_update_mtfsf
= build1 (VIEW_CONVERT_EXPR
, double_type_node
,
41751 tree update_mtfsf
= build_call_expr (mtfsf
, 2,
41752 build_int_cst (unsigned_type_node
, 0xff),
41753 fenv_update_mtfsf
);
41755 *update
= build2 (COMPOUND_EXPR
, void_type_node
, update_mffs
, update_mtfsf
);
41758 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
41761 rs6000_optab_supported_p (int op
, machine_mode mode1
, machine_mode
,
41762 optimization_type opt_type
)
41767 return (opt_type
== OPTIMIZE_FOR_SPEED
41768 && RS6000_RECIP_AUTO_RSQRTE_P (mode1
));
41775 struct gcc_target targetm
= TARGET_INITIALIZER
;
41777 #include "gt-rs6000.h"