1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
35 #include "stringpool.h"
36 #include "stor-layout.h"
38 #include "print-tree.h"
46 #include "basic-block.h"
47 #include "diagnostic-core.h"
53 #include "target-def.h"
54 #include "common/common-target.h"
55 #include "langhooks.h"
58 #include "sched-int.h"
61 #include "gimple-iterator.h"
62 #include "gimple-walk.h"
65 #include "tm-constrs.h"
68 #include "tree-vectorizer.h"
72 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
75 #include "gstab.h" /* for N_SLINE */
78 #ifndef TARGET_NO_PROTOTYPE
79 #define TARGET_NO_PROTOTYPE 0
82 #define min(A,B) ((A) < (B) ? (A) : (B))
83 #define max(A,B) ((A) > (B) ? (A) : (B))
85 /* Structure used to define the rs6000 stack */
86 typedef struct rs6000_stack
{
87 int reload_completed
; /* stack info won't change from here on */
88 int first_gp_reg_save
; /* first callee saved GP register used */
89 int first_fp_reg_save
; /* first callee saved FP register used */
90 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
91 int lr_save_p
; /* true if the link reg needs to be saved */
92 int cr_save_p
; /* true if the CR reg needs to be saved */
93 unsigned int vrsave_mask
; /* mask of vec registers to save */
94 int push_p
; /* true if we need to allocate stack space */
95 int calls_p
; /* true if the function makes any calls */
96 int world_save_p
; /* true if we're saving *everything*:
97 r13-r31, cr, f14-f31, vrsave, v20-v31 */
98 enum rs6000_abi abi
; /* which ABI to use */
99 int gp_save_offset
; /* offset to save GP regs from initial SP */
100 int fp_save_offset
; /* offset to save FP regs from initial SP */
101 int altivec_save_offset
; /* offset to save AltiVec regs from initial SP */
102 int lr_save_offset
; /* offset to save LR from initial SP */
103 int cr_save_offset
; /* offset to save CR from initial SP */
104 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
105 int spe_gp_save_offset
; /* offset to save spe 64-bit gprs */
106 int varargs_save_offset
; /* offset to save the varargs registers */
107 int ehrd_offset
; /* offset to EH return data */
108 int ehcr_offset
; /* offset to EH CR field data */
109 int reg_size
; /* register size (4 or 8) */
110 HOST_WIDE_INT vars_size
; /* variable save area size */
111 int parm_size
; /* outgoing parameter size */
112 int save_size
; /* save area size */
113 int fixed_size
; /* fixed size of stack frame */
114 int gp_size
; /* size of saved GP registers */
115 int fp_size
; /* size of saved FP registers */
116 int altivec_size
; /* size of saved AltiVec registers */
117 int cr_size
; /* size to hold CR if not in save_size */
118 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
119 int altivec_padding_size
; /* size of altivec alignment padding if
121 int spe_gp_size
; /* size of 64-bit GPR save size for SPE */
122 int spe_padding_size
;
123 HOST_WIDE_INT total_size
; /* total bytes allocated for stack */
124 int spe_64bit_regs_used
;
128 /* A C structure for machine-specific, per-function data.
129 This is added to the cfun structure. */
130 typedef struct GTY(()) machine_function
132 /* Some local-dynamic symbol. */
133 const char *some_ld_name
;
134 /* Whether the instruction chain has been scanned already. */
135 int insn_chain_scanned_p
;
136 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
137 int ra_needs_full_frame
;
138 /* Flags if __builtin_return_address (0) was used. */
140 /* Cache lr_save_p after expansion of builtin_eh_return. */
142 /* Whether we need to save the TOC to the reserved stack location in the
143 function prologue. */
144 bool save_toc_in_prologue
;
145 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
146 varargs save area. */
147 HOST_WIDE_INT varargs_save_offset
;
148 /* Temporary stack slot to use for SDmode copies. This slot is
149 64-bits wide and is allocated early enough so that the offset
150 does not overflow the 16-bit load/store offset field. */
151 rtx sdmode_stack_slot
;
152 /* Flag if r2 setup is needed with ELFv2 ABI. */
153 bool r2_setup_needed
;
156 /* Support targetm.vectorize.builtin_mask_for_load. */
157 static GTY(()) tree altivec_builtin_mask_for_load
;
159 /* Set to nonzero once AIX common-mode calls have been defined. */
160 static GTY(()) int common_mode_defined
;
162 /* Label number of label created for -mrelocatable, to call to so we can
163 get the address of the GOT section */
164 static int rs6000_pic_labelno
;
167 /* Counter for labels which are to be placed in .fixup. */
168 int fixuplabelno
= 0;
171 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
174 /* Specify the machine mode that pointers have. After generation of rtl, the
175 compiler makes no further distinction between pointers and any other objects
176 of this machine mode. The type is unsigned since not all things that
177 include rs6000.h also include machmode.h. */
178 unsigned rs6000_pmode
;
180 /* Width in bits of a pointer. */
181 unsigned rs6000_pointer_size
;
183 #ifdef HAVE_AS_GNU_ATTRIBUTE
184 /* Flag whether floating point values have been passed/returned. */
185 static bool rs6000_passes_float
;
186 /* Flag whether vector values have been passed/returned. */
187 static bool rs6000_passes_vector
;
188 /* Flag whether small (<= 8 byte) structures have been returned. */
189 static bool rs6000_returns_struct
;
192 /* Value is TRUE if register/mode pair is acceptable. */
193 bool rs6000_hard_regno_mode_ok_p
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
195 /* Maximum number of registers needed for a given register class and mode. */
196 unsigned char rs6000_class_max_nregs
[NUM_MACHINE_MODES
][LIM_REG_CLASSES
];
198 /* How many registers are needed for a given register and mode. */
199 unsigned char rs6000_hard_regno_nregs
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
201 /* Map register number to register class. */
202 enum reg_class rs6000_regno_regclass
[FIRST_PSEUDO_REGISTER
];
204 static int dbg_cost_ctrl
;
206 /* Built in types. */
207 tree rs6000_builtin_types
[RS6000_BTI_MAX
];
208 tree rs6000_builtin_decls
[RS6000_BUILTIN_COUNT
];
210 /* Flag to say the TOC is initialized */
212 char toc_label_name
[10];
214 /* Cached value of rs6000_variable_issue. This is cached in
215 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
216 static short cached_can_issue_more
;
218 static GTY(()) section
*read_only_data_section
;
219 static GTY(()) section
*private_data_section
;
220 static GTY(()) section
*tls_data_section
;
221 static GTY(()) section
*tls_private_data_section
;
222 static GTY(()) section
*read_only_private_data_section
;
223 static GTY(()) section
*sdata2_section
;
224 static GTY(()) section
*toc_section
;
226 struct builtin_description
228 const HOST_WIDE_INT mask
;
229 const enum insn_code icode
;
230 const char *const name
;
231 const enum rs6000_builtins code
;
234 /* Describe the vector unit used for modes. */
235 enum rs6000_vector rs6000_vector_unit
[NUM_MACHINE_MODES
];
236 enum rs6000_vector rs6000_vector_mem
[NUM_MACHINE_MODES
];
238 /* Register classes for various constraints that are based on the target
240 enum reg_class rs6000_constraints
[RS6000_CONSTRAINT_MAX
];
242 /* Describe the alignment of a vector. */
243 int rs6000_vector_align
[NUM_MACHINE_MODES
];
245 /* Map selected modes to types for builtins. */
246 static GTY(()) tree builtin_mode_to_type
[MAX_MACHINE_MODE
][2];
248 /* What modes to automatically generate reciprocal divide estimate (fre) and
249 reciprocal sqrt (frsqrte) for. */
250 unsigned char rs6000_recip_bits
[MAX_MACHINE_MODE
];
252 /* Masks to determine which reciprocal esitmate instructions to generate
254 enum rs6000_recip_mask
{
255 RECIP_SF_DIV
= 0x001, /* Use divide estimate */
256 RECIP_DF_DIV
= 0x002,
257 RECIP_V4SF_DIV
= 0x004,
258 RECIP_V2DF_DIV
= 0x008,
260 RECIP_SF_RSQRT
= 0x010, /* Use reciprocal sqrt estimate. */
261 RECIP_DF_RSQRT
= 0x020,
262 RECIP_V4SF_RSQRT
= 0x040,
263 RECIP_V2DF_RSQRT
= 0x080,
265 /* Various combination of flags for -mrecip=xxx. */
267 RECIP_ALL
= (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
268 | RECIP_V2DF_DIV
| RECIP_SF_RSQRT
| RECIP_DF_RSQRT
269 | RECIP_V4SF_RSQRT
| RECIP_V2DF_RSQRT
),
271 RECIP_HIGH_PRECISION
= RECIP_ALL
,
273 /* On low precision machines like the power5, don't enable double precision
274 reciprocal square root estimate, since it isn't accurate enough. */
275 RECIP_LOW_PRECISION
= (RECIP_ALL
& ~(RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
))
278 /* -mrecip options. */
281 const char *string
; /* option name */
282 unsigned int mask
; /* mask bits to set */
283 } recip_options
[] = {
284 { "all", RECIP_ALL
},
285 { "none", RECIP_NONE
},
286 { "div", (RECIP_SF_DIV
| RECIP_DF_DIV
| RECIP_V4SF_DIV
288 { "divf", (RECIP_SF_DIV
| RECIP_V4SF_DIV
) },
289 { "divd", (RECIP_DF_DIV
| RECIP_V2DF_DIV
) },
290 { "rsqrt", (RECIP_SF_RSQRT
| RECIP_DF_RSQRT
| RECIP_V4SF_RSQRT
291 | RECIP_V2DF_RSQRT
) },
292 { "rsqrtf", (RECIP_SF_RSQRT
| RECIP_V4SF_RSQRT
) },
293 { "rsqrtd", (RECIP_DF_RSQRT
| RECIP_V2DF_RSQRT
) },
296 /* Pointer to function (in rs6000-c.c) that can define or undefine target
297 macros that have changed. Languages that don't support the preprocessor
298 don't link in rs6000-c.c, so we can't call it directly. */
299 void (*rs6000_target_modify_macros_ptr
) (bool, HOST_WIDE_INT
, HOST_WIDE_INT
);
301 /* Simplfy register classes into simpler classifications. We assume
302 GPR_REG_TYPE - FPR_REG_TYPE are ordered so that we can use a simple range
303 check for standard register classes (gpr/floating/altivec/vsx) and
304 floating/vector classes (float/altivec/vsx). */
306 enum rs6000_reg_type
{
319 /* Map register class to register type. */
320 static enum rs6000_reg_type reg_class_to_reg_type
[N_REG_CLASSES
];
322 /* First/last register type for the 'normal' register types (i.e. general
323 purpose, floating point, altivec, and VSX registers). */
324 #define IS_STD_REG_TYPE(RTYPE) IN_RANGE(RTYPE, GPR_REG_TYPE, FPR_REG_TYPE)
326 #define IS_FP_VECT_REG_TYPE(RTYPE) IN_RANGE(RTYPE, VSX_REG_TYPE, FPR_REG_TYPE)
329 /* Register classes we care about in secondary reload or go if legitimate
330 address. We only need to worry about GPR, FPR, and Altivec registers here,
331 along an ANY field that is the OR of the 3 register classes. */
333 enum rs6000_reload_reg_type
{
334 RELOAD_REG_GPR
, /* General purpose registers. */
335 RELOAD_REG_FPR
, /* Traditional floating point regs. */
336 RELOAD_REG_VMX
, /* Altivec (VMX) registers. */
337 RELOAD_REG_ANY
, /* OR of GPR, FPR, Altivec masks. */
341 /* For setting up register classes, loop through the 3 register classes mapping
342 into real registers, and skip the ANY class, which is just an OR of the
344 #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR
345 #define LAST_RELOAD_REG_CLASS RELOAD_REG_VMX
347 /* Map reload register type to a register in the register class. */
348 struct reload_reg_map_type
{
349 const char *name
; /* Register class name. */
350 int reg
; /* Register in the register class. */
353 static const struct reload_reg_map_type reload_reg_map
[N_RELOAD_REG
] = {
354 { "Gpr", FIRST_GPR_REGNO
}, /* RELOAD_REG_GPR. */
355 { "Fpr", FIRST_FPR_REGNO
}, /* RELOAD_REG_FPR. */
356 { "VMX", FIRST_ALTIVEC_REGNO
}, /* RELOAD_REG_VMX. */
357 { "Any", -1 }, /* RELOAD_REG_ANY. */
360 /* Mask bits for each register class, indexed per mode. Historically the
361 compiler has been more restrictive which types can do PRE_MODIFY instead of
362 PRE_INC and PRE_DEC, so keep track of sepaate bits for these two. */
363 typedef unsigned char addr_mask_type
;
365 #define RELOAD_REG_VALID 0x01 /* Mode valid in register.. */
366 #define RELOAD_REG_MULTIPLE 0x02 /* Mode takes multiple registers. */
367 #define RELOAD_REG_INDEXED 0x04 /* Reg+reg addressing. */
368 #define RELOAD_REG_OFFSET 0x08 /* Reg+offset addressing. */
369 #define RELOAD_REG_PRE_INCDEC 0x10 /* PRE_INC/PRE_DEC valid. */
370 #define RELOAD_REG_PRE_MODIFY 0x20 /* PRE_MODIFY valid. */
372 /* Register type masks based on the type, of valid addressing modes. */
373 struct rs6000_reg_addr
{
374 enum insn_code reload_load
; /* INSN to reload for loading. */
375 enum insn_code reload_store
; /* INSN to reload for storing. */
376 enum insn_code reload_fpr_gpr
; /* INSN to move from FPR to GPR. */
377 enum insn_code reload_gpr_vsx
; /* INSN to move from GPR to VSX. */
378 enum insn_code reload_vsx_gpr
; /* INSN to move from VSX to GPR. */
379 addr_mask_type addr_mask
[(int)N_RELOAD_REG
]; /* Valid address masks. */
382 static struct rs6000_reg_addr reg_addr
[NUM_MACHINE_MODES
];
384 /* Helper function to say whether a mode supports PRE_INC or PRE_DEC. */
386 mode_supports_pre_incdec_p (enum machine_mode mode
)
388 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_INCDEC
)
392 /* Helper function to say whether a mode supports PRE_MODIFY. */
394 mode_supports_pre_modify_p (enum machine_mode mode
)
396 return ((reg_addr
[mode
].addr_mask
[RELOAD_REG_ANY
] & RELOAD_REG_PRE_MODIFY
)
401 /* Target cpu costs. */
403 struct processor_costs
{
404 const int mulsi
; /* cost of SImode multiplication. */
405 const int mulsi_const
; /* cost of SImode multiplication by constant. */
406 const int mulsi_const9
; /* cost of SImode mult by short constant. */
407 const int muldi
; /* cost of DImode multiplication. */
408 const int divsi
; /* cost of SImode division. */
409 const int divdi
; /* cost of DImode division. */
410 const int fp
; /* cost of simple SFmode and DFmode insns. */
411 const int dmul
; /* cost of DFmode multiplication (and fmadd). */
412 const int sdiv
; /* cost of SFmode division (fdivs). */
413 const int ddiv
; /* cost of DFmode division (fdiv). */
414 const int cache_line_size
; /* cache line size in bytes. */
415 const int l1_cache_size
; /* size of l1 cache, in kilobytes. */
416 const int l2_cache_size
; /* size of l2 cache, in kilobytes. */
417 const int simultaneous_prefetches
; /* number of parallel prefetch
421 const struct processor_costs
*rs6000_cost
;
423 /* Processor costs (relative to an add) */
425 /* Instruction size costs on 32bit processors. */
427 struct processor_costs size32_cost
= {
428 COSTS_N_INSNS (1), /* mulsi */
429 COSTS_N_INSNS (1), /* mulsi_const */
430 COSTS_N_INSNS (1), /* mulsi_const9 */
431 COSTS_N_INSNS (1), /* muldi */
432 COSTS_N_INSNS (1), /* divsi */
433 COSTS_N_INSNS (1), /* divdi */
434 COSTS_N_INSNS (1), /* fp */
435 COSTS_N_INSNS (1), /* dmul */
436 COSTS_N_INSNS (1), /* sdiv */
437 COSTS_N_INSNS (1), /* ddiv */
444 /* Instruction size costs on 64bit processors. */
446 struct processor_costs size64_cost
= {
447 COSTS_N_INSNS (1), /* mulsi */
448 COSTS_N_INSNS (1), /* mulsi_const */
449 COSTS_N_INSNS (1), /* mulsi_const9 */
450 COSTS_N_INSNS (1), /* muldi */
451 COSTS_N_INSNS (1), /* divsi */
452 COSTS_N_INSNS (1), /* divdi */
453 COSTS_N_INSNS (1), /* fp */
454 COSTS_N_INSNS (1), /* dmul */
455 COSTS_N_INSNS (1), /* sdiv */
456 COSTS_N_INSNS (1), /* ddiv */
463 /* Instruction costs on RS64A processors. */
465 struct processor_costs rs64a_cost
= {
466 COSTS_N_INSNS (20), /* mulsi */
467 COSTS_N_INSNS (12), /* mulsi_const */
468 COSTS_N_INSNS (8), /* mulsi_const9 */
469 COSTS_N_INSNS (34), /* muldi */
470 COSTS_N_INSNS (65), /* divsi */
471 COSTS_N_INSNS (67), /* divdi */
472 COSTS_N_INSNS (4), /* fp */
473 COSTS_N_INSNS (4), /* dmul */
474 COSTS_N_INSNS (31), /* sdiv */
475 COSTS_N_INSNS (31), /* ddiv */
476 128, /* cache line size */
482 /* Instruction costs on MPCCORE processors. */
484 struct processor_costs mpccore_cost
= {
485 COSTS_N_INSNS (2), /* mulsi */
486 COSTS_N_INSNS (2), /* mulsi_const */
487 COSTS_N_INSNS (2), /* mulsi_const9 */
488 COSTS_N_INSNS (2), /* muldi */
489 COSTS_N_INSNS (6), /* divsi */
490 COSTS_N_INSNS (6), /* divdi */
491 COSTS_N_INSNS (4), /* fp */
492 COSTS_N_INSNS (5), /* dmul */
493 COSTS_N_INSNS (10), /* sdiv */
494 COSTS_N_INSNS (17), /* ddiv */
495 32, /* cache line size */
501 /* Instruction costs on PPC403 processors. */
503 struct processor_costs ppc403_cost
= {
504 COSTS_N_INSNS (4), /* mulsi */
505 COSTS_N_INSNS (4), /* mulsi_const */
506 COSTS_N_INSNS (4), /* mulsi_const9 */
507 COSTS_N_INSNS (4), /* muldi */
508 COSTS_N_INSNS (33), /* divsi */
509 COSTS_N_INSNS (33), /* divdi */
510 COSTS_N_INSNS (11), /* fp */
511 COSTS_N_INSNS (11), /* dmul */
512 COSTS_N_INSNS (11), /* sdiv */
513 COSTS_N_INSNS (11), /* ddiv */
514 32, /* cache line size */
520 /* Instruction costs on PPC405 processors. */
522 struct processor_costs ppc405_cost
= {
523 COSTS_N_INSNS (5), /* mulsi */
524 COSTS_N_INSNS (4), /* mulsi_const */
525 COSTS_N_INSNS (3), /* mulsi_const9 */
526 COSTS_N_INSNS (5), /* muldi */
527 COSTS_N_INSNS (35), /* divsi */
528 COSTS_N_INSNS (35), /* divdi */
529 COSTS_N_INSNS (11), /* fp */
530 COSTS_N_INSNS (11), /* dmul */
531 COSTS_N_INSNS (11), /* sdiv */
532 COSTS_N_INSNS (11), /* ddiv */
533 32, /* cache line size */
539 /* Instruction costs on PPC440 processors. */
541 struct processor_costs ppc440_cost
= {
542 COSTS_N_INSNS (3), /* mulsi */
543 COSTS_N_INSNS (2), /* mulsi_const */
544 COSTS_N_INSNS (2), /* mulsi_const9 */
545 COSTS_N_INSNS (3), /* muldi */
546 COSTS_N_INSNS (34), /* divsi */
547 COSTS_N_INSNS (34), /* divdi */
548 COSTS_N_INSNS (5), /* fp */
549 COSTS_N_INSNS (5), /* dmul */
550 COSTS_N_INSNS (19), /* sdiv */
551 COSTS_N_INSNS (33), /* ddiv */
552 32, /* cache line size */
558 /* Instruction costs on PPC476 processors. */
560 struct processor_costs ppc476_cost
= {
561 COSTS_N_INSNS (4), /* mulsi */
562 COSTS_N_INSNS (4), /* mulsi_const */
563 COSTS_N_INSNS (4), /* mulsi_const9 */
564 COSTS_N_INSNS (4), /* muldi */
565 COSTS_N_INSNS (11), /* divsi */
566 COSTS_N_INSNS (11), /* divdi */
567 COSTS_N_INSNS (6), /* fp */
568 COSTS_N_INSNS (6), /* dmul */
569 COSTS_N_INSNS (19), /* sdiv */
570 COSTS_N_INSNS (33), /* ddiv */
571 32, /* l1 cache line size */
577 /* Instruction costs on PPC601 processors. */
579 struct processor_costs ppc601_cost
= {
580 COSTS_N_INSNS (5), /* mulsi */
581 COSTS_N_INSNS (5), /* mulsi_const */
582 COSTS_N_INSNS (5), /* mulsi_const9 */
583 COSTS_N_INSNS (5), /* muldi */
584 COSTS_N_INSNS (36), /* divsi */
585 COSTS_N_INSNS (36), /* divdi */
586 COSTS_N_INSNS (4), /* fp */
587 COSTS_N_INSNS (5), /* dmul */
588 COSTS_N_INSNS (17), /* sdiv */
589 COSTS_N_INSNS (31), /* ddiv */
590 32, /* cache line size */
596 /* Instruction costs on PPC603 processors. */
598 struct processor_costs ppc603_cost
= {
599 COSTS_N_INSNS (5), /* mulsi */
600 COSTS_N_INSNS (3), /* mulsi_const */
601 COSTS_N_INSNS (2), /* mulsi_const9 */
602 COSTS_N_INSNS (5), /* muldi */
603 COSTS_N_INSNS (37), /* divsi */
604 COSTS_N_INSNS (37), /* divdi */
605 COSTS_N_INSNS (3), /* fp */
606 COSTS_N_INSNS (4), /* dmul */
607 COSTS_N_INSNS (18), /* sdiv */
608 COSTS_N_INSNS (33), /* ddiv */
609 32, /* cache line size */
615 /* Instruction costs on PPC604 processors. */
617 struct processor_costs ppc604_cost
= {
618 COSTS_N_INSNS (4), /* mulsi */
619 COSTS_N_INSNS (4), /* mulsi_const */
620 COSTS_N_INSNS (4), /* mulsi_const9 */
621 COSTS_N_INSNS (4), /* muldi */
622 COSTS_N_INSNS (20), /* divsi */
623 COSTS_N_INSNS (20), /* divdi */
624 COSTS_N_INSNS (3), /* fp */
625 COSTS_N_INSNS (3), /* dmul */
626 COSTS_N_INSNS (18), /* sdiv */
627 COSTS_N_INSNS (32), /* ddiv */
628 32, /* cache line size */
634 /* Instruction costs on PPC604e processors. */
636 struct processor_costs ppc604e_cost
= {
637 COSTS_N_INSNS (2), /* mulsi */
638 COSTS_N_INSNS (2), /* mulsi_const */
639 COSTS_N_INSNS (2), /* mulsi_const9 */
640 COSTS_N_INSNS (2), /* muldi */
641 COSTS_N_INSNS (20), /* divsi */
642 COSTS_N_INSNS (20), /* divdi */
643 COSTS_N_INSNS (3), /* fp */
644 COSTS_N_INSNS (3), /* dmul */
645 COSTS_N_INSNS (18), /* sdiv */
646 COSTS_N_INSNS (32), /* ddiv */
647 32, /* cache line size */
653 /* Instruction costs on PPC620 processors. */
655 struct processor_costs ppc620_cost
= {
656 COSTS_N_INSNS (5), /* mulsi */
657 COSTS_N_INSNS (4), /* mulsi_const */
658 COSTS_N_INSNS (3), /* mulsi_const9 */
659 COSTS_N_INSNS (7), /* muldi */
660 COSTS_N_INSNS (21), /* divsi */
661 COSTS_N_INSNS (37), /* divdi */
662 COSTS_N_INSNS (3), /* fp */
663 COSTS_N_INSNS (3), /* dmul */
664 COSTS_N_INSNS (18), /* sdiv */
665 COSTS_N_INSNS (32), /* ddiv */
666 128, /* cache line size */
672 /* Instruction costs on PPC630 processors. */
674 struct processor_costs ppc630_cost
= {
675 COSTS_N_INSNS (5), /* mulsi */
676 COSTS_N_INSNS (4), /* mulsi_const */
677 COSTS_N_INSNS (3), /* mulsi_const9 */
678 COSTS_N_INSNS (7), /* muldi */
679 COSTS_N_INSNS (21), /* divsi */
680 COSTS_N_INSNS (37), /* divdi */
681 COSTS_N_INSNS (3), /* fp */
682 COSTS_N_INSNS (3), /* dmul */
683 COSTS_N_INSNS (17), /* sdiv */
684 COSTS_N_INSNS (21), /* ddiv */
685 128, /* cache line size */
691 /* Instruction costs on Cell processor. */
692 /* COSTS_N_INSNS (1) ~ one add. */
694 struct processor_costs ppccell_cost
= {
695 COSTS_N_INSNS (9/2)+2, /* mulsi */
696 COSTS_N_INSNS (6/2), /* mulsi_const */
697 COSTS_N_INSNS (6/2), /* mulsi_const9 */
698 COSTS_N_INSNS (15/2)+2, /* muldi */
699 COSTS_N_INSNS (38/2), /* divsi */
700 COSTS_N_INSNS (70/2), /* divdi */
701 COSTS_N_INSNS (10/2), /* fp */
702 COSTS_N_INSNS (10/2), /* dmul */
703 COSTS_N_INSNS (74/2), /* sdiv */
704 COSTS_N_INSNS (74/2), /* ddiv */
705 128, /* cache line size */
711 /* Instruction costs on PPC750 and PPC7400 processors. */
713 struct processor_costs ppc750_cost
= {
714 COSTS_N_INSNS (5), /* mulsi */
715 COSTS_N_INSNS (3), /* mulsi_const */
716 COSTS_N_INSNS (2), /* mulsi_const9 */
717 COSTS_N_INSNS (5), /* muldi */
718 COSTS_N_INSNS (17), /* divsi */
719 COSTS_N_INSNS (17), /* divdi */
720 COSTS_N_INSNS (3), /* fp */
721 COSTS_N_INSNS (3), /* dmul */
722 COSTS_N_INSNS (17), /* sdiv */
723 COSTS_N_INSNS (31), /* ddiv */
724 32, /* cache line size */
730 /* Instruction costs on PPC7450 processors. */
732 struct processor_costs ppc7450_cost
= {
733 COSTS_N_INSNS (4), /* mulsi */
734 COSTS_N_INSNS (3), /* mulsi_const */
735 COSTS_N_INSNS (3), /* mulsi_const9 */
736 COSTS_N_INSNS (4), /* muldi */
737 COSTS_N_INSNS (23), /* divsi */
738 COSTS_N_INSNS (23), /* divdi */
739 COSTS_N_INSNS (5), /* fp */
740 COSTS_N_INSNS (5), /* dmul */
741 COSTS_N_INSNS (21), /* sdiv */
742 COSTS_N_INSNS (35), /* ddiv */
743 32, /* cache line size */
749 /* Instruction costs on PPC8540 processors. */
751 struct processor_costs ppc8540_cost
= {
752 COSTS_N_INSNS (4), /* mulsi */
753 COSTS_N_INSNS (4), /* mulsi_const */
754 COSTS_N_INSNS (4), /* mulsi_const9 */
755 COSTS_N_INSNS (4), /* muldi */
756 COSTS_N_INSNS (19), /* divsi */
757 COSTS_N_INSNS (19), /* divdi */
758 COSTS_N_INSNS (4), /* fp */
759 COSTS_N_INSNS (4), /* dmul */
760 COSTS_N_INSNS (29), /* sdiv */
761 COSTS_N_INSNS (29), /* ddiv */
762 32, /* cache line size */
765 1, /* prefetch streams /*/
768 /* Instruction costs on E300C2 and E300C3 cores. */
770 struct processor_costs ppce300c2c3_cost
= {
771 COSTS_N_INSNS (4), /* mulsi */
772 COSTS_N_INSNS (4), /* mulsi_const */
773 COSTS_N_INSNS (4), /* mulsi_const9 */
774 COSTS_N_INSNS (4), /* muldi */
775 COSTS_N_INSNS (19), /* divsi */
776 COSTS_N_INSNS (19), /* divdi */
777 COSTS_N_INSNS (3), /* fp */
778 COSTS_N_INSNS (4), /* dmul */
779 COSTS_N_INSNS (18), /* sdiv */
780 COSTS_N_INSNS (33), /* ddiv */
784 1, /* prefetch streams /*/
787 /* Instruction costs on PPCE500MC processors. */
789 struct processor_costs ppce500mc_cost
= {
790 COSTS_N_INSNS (4), /* mulsi */
791 COSTS_N_INSNS (4), /* mulsi_const */
792 COSTS_N_INSNS (4), /* mulsi_const9 */
793 COSTS_N_INSNS (4), /* muldi */
794 COSTS_N_INSNS (14), /* divsi */
795 COSTS_N_INSNS (14), /* divdi */
796 COSTS_N_INSNS (8), /* fp */
797 COSTS_N_INSNS (10), /* dmul */
798 COSTS_N_INSNS (36), /* sdiv */
799 COSTS_N_INSNS (66), /* ddiv */
800 64, /* cache line size */
803 1, /* prefetch streams /*/
806 /* Instruction costs on PPCE500MC64 processors. */
808 struct processor_costs ppce500mc64_cost
= {
809 COSTS_N_INSNS (4), /* mulsi */
810 COSTS_N_INSNS (4), /* mulsi_const */
811 COSTS_N_INSNS (4), /* mulsi_const9 */
812 COSTS_N_INSNS (4), /* muldi */
813 COSTS_N_INSNS (14), /* divsi */
814 COSTS_N_INSNS (14), /* divdi */
815 COSTS_N_INSNS (4), /* fp */
816 COSTS_N_INSNS (10), /* dmul */
817 COSTS_N_INSNS (36), /* sdiv */
818 COSTS_N_INSNS (66), /* ddiv */
819 64, /* cache line size */
822 1, /* prefetch streams /*/
825 /* Instruction costs on PPCE5500 processors. */
827 struct processor_costs ppce5500_cost
= {
828 COSTS_N_INSNS (5), /* mulsi */
829 COSTS_N_INSNS (5), /* mulsi_const */
830 COSTS_N_INSNS (4), /* mulsi_const9 */
831 COSTS_N_INSNS (5), /* muldi */
832 COSTS_N_INSNS (14), /* divsi */
833 COSTS_N_INSNS (14), /* divdi */
834 COSTS_N_INSNS (7), /* fp */
835 COSTS_N_INSNS (10), /* dmul */
836 COSTS_N_INSNS (36), /* sdiv */
837 COSTS_N_INSNS (66), /* ddiv */
838 64, /* cache line size */
841 1, /* prefetch streams /*/
844 /* Instruction costs on PPCE6500 processors. */
846 struct processor_costs ppce6500_cost
= {
847 COSTS_N_INSNS (5), /* mulsi */
848 COSTS_N_INSNS (5), /* mulsi_const */
849 COSTS_N_INSNS (4), /* mulsi_const9 */
850 COSTS_N_INSNS (5), /* muldi */
851 COSTS_N_INSNS (14), /* divsi */
852 COSTS_N_INSNS (14), /* divdi */
853 COSTS_N_INSNS (7), /* fp */
854 COSTS_N_INSNS (10), /* dmul */
855 COSTS_N_INSNS (36), /* sdiv */
856 COSTS_N_INSNS (66), /* ddiv */
857 64, /* cache line size */
860 1, /* prefetch streams /*/
863 /* Instruction costs on AppliedMicro Titan processors. */
865 struct processor_costs titan_cost
= {
866 COSTS_N_INSNS (5), /* mulsi */
867 COSTS_N_INSNS (5), /* mulsi_const */
868 COSTS_N_INSNS (5), /* mulsi_const9 */
869 COSTS_N_INSNS (5), /* muldi */
870 COSTS_N_INSNS (18), /* divsi */
871 COSTS_N_INSNS (18), /* divdi */
872 COSTS_N_INSNS (10), /* fp */
873 COSTS_N_INSNS (10), /* dmul */
874 COSTS_N_INSNS (46), /* sdiv */
875 COSTS_N_INSNS (72), /* ddiv */
876 32, /* cache line size */
879 1, /* prefetch streams /*/
882 /* Instruction costs on POWER4 and POWER5 processors. */
884 struct processor_costs power4_cost
= {
885 COSTS_N_INSNS (3), /* mulsi */
886 COSTS_N_INSNS (2), /* mulsi_const */
887 COSTS_N_INSNS (2), /* mulsi_const9 */
888 COSTS_N_INSNS (4), /* muldi */
889 COSTS_N_INSNS (18), /* divsi */
890 COSTS_N_INSNS (34), /* divdi */
891 COSTS_N_INSNS (3), /* fp */
892 COSTS_N_INSNS (3), /* dmul */
893 COSTS_N_INSNS (17), /* sdiv */
894 COSTS_N_INSNS (17), /* ddiv */
895 128, /* cache line size */
898 8, /* prefetch streams /*/
901 /* Instruction costs on POWER6 processors. */
903 struct processor_costs power6_cost
= {
904 COSTS_N_INSNS (8), /* mulsi */
905 COSTS_N_INSNS (8), /* mulsi_const */
906 COSTS_N_INSNS (8), /* mulsi_const9 */
907 COSTS_N_INSNS (8), /* muldi */
908 COSTS_N_INSNS (22), /* divsi */
909 COSTS_N_INSNS (28), /* divdi */
910 COSTS_N_INSNS (3), /* fp */
911 COSTS_N_INSNS (3), /* dmul */
912 COSTS_N_INSNS (13), /* sdiv */
913 COSTS_N_INSNS (16), /* ddiv */
914 128, /* cache line size */
917 16, /* prefetch streams */
920 /* Instruction costs on POWER7 processors. */
922 struct processor_costs power7_cost
= {
923 COSTS_N_INSNS (2), /* mulsi */
924 COSTS_N_INSNS (2), /* mulsi_const */
925 COSTS_N_INSNS (2), /* mulsi_const9 */
926 COSTS_N_INSNS (2), /* muldi */
927 COSTS_N_INSNS (18), /* divsi */
928 COSTS_N_INSNS (34), /* divdi */
929 COSTS_N_INSNS (3), /* fp */
930 COSTS_N_INSNS (3), /* dmul */
931 COSTS_N_INSNS (13), /* sdiv */
932 COSTS_N_INSNS (16), /* ddiv */
933 128, /* cache line size */
936 12, /* prefetch streams */
939 /* Instruction costs on POWER8 processors. */
941 struct processor_costs power8_cost
= {
942 COSTS_N_INSNS (3), /* mulsi */
943 COSTS_N_INSNS (3), /* mulsi_const */
944 COSTS_N_INSNS (3), /* mulsi_const9 */
945 COSTS_N_INSNS (3), /* muldi */
946 COSTS_N_INSNS (19), /* divsi */
947 COSTS_N_INSNS (35), /* divdi */
948 COSTS_N_INSNS (3), /* fp */
949 COSTS_N_INSNS (3), /* dmul */
950 COSTS_N_INSNS (14), /* sdiv */
951 COSTS_N_INSNS (17), /* ddiv */
952 128, /* cache line size */
955 12, /* prefetch streams */
958 /* Instruction costs on POWER A2 processors. */
960 struct processor_costs ppca2_cost
= {
961 COSTS_N_INSNS (16), /* mulsi */
962 COSTS_N_INSNS (16), /* mulsi_const */
963 COSTS_N_INSNS (16), /* mulsi_const9 */
964 COSTS_N_INSNS (16), /* muldi */
965 COSTS_N_INSNS (22), /* divsi */
966 COSTS_N_INSNS (28), /* divdi */
967 COSTS_N_INSNS (3), /* fp */
968 COSTS_N_INSNS (3), /* dmul */
969 COSTS_N_INSNS (59), /* sdiv */
970 COSTS_N_INSNS (72), /* ddiv */
974 16, /* prefetch streams */
978 /* Table that classifies rs6000 builtin functions (pure, const, etc.). */
979 #undef RS6000_BUILTIN_1
980 #undef RS6000_BUILTIN_2
981 #undef RS6000_BUILTIN_3
982 #undef RS6000_BUILTIN_A
983 #undef RS6000_BUILTIN_D
984 #undef RS6000_BUILTIN_E
985 #undef RS6000_BUILTIN_H
986 #undef RS6000_BUILTIN_P
987 #undef RS6000_BUILTIN_Q
988 #undef RS6000_BUILTIN_S
989 #undef RS6000_BUILTIN_X
991 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
992 { NAME, ICODE, MASK, ATTR },
994 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
995 { NAME, ICODE, MASK, ATTR },
997 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
998 { NAME, ICODE, MASK, ATTR },
1000 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
1001 { NAME, ICODE, MASK, ATTR },
1003 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
1004 { NAME, ICODE, MASK, ATTR },
1006 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
1007 { NAME, ICODE, MASK, ATTR },
1009 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
1010 { NAME, ICODE, MASK, ATTR },
1012 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
1013 { NAME, ICODE, MASK, ATTR },
1015 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
1016 { NAME, ICODE, MASK, ATTR },
1018 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
1019 { NAME, ICODE, MASK, ATTR },
1021 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE) \
1022 { NAME, ICODE, MASK, ATTR },
1024 struct rs6000_builtin_info_type
{
1026 const enum insn_code icode
;
1027 const HOST_WIDE_INT mask
;
1028 const unsigned attr
;
1031 static const struct rs6000_builtin_info_type rs6000_builtin_info
[] =
1033 #include "rs6000-builtin.def"
1036 #undef RS6000_BUILTIN_1
1037 #undef RS6000_BUILTIN_2
1038 #undef RS6000_BUILTIN_3
1039 #undef RS6000_BUILTIN_A
1040 #undef RS6000_BUILTIN_D
1041 #undef RS6000_BUILTIN_E
1042 #undef RS6000_BUILTIN_H
1043 #undef RS6000_BUILTIN_P
1044 #undef RS6000_BUILTIN_Q
1045 #undef RS6000_BUILTIN_S
1046 #undef RS6000_BUILTIN_X
1048 /* Support for -mveclibabi=<xxx> to control which vector library to use. */
1049 static tree (*rs6000_veclib_handler
) (tree
, tree
, tree
);
1052 static bool rs6000_debug_legitimate_address_p (enum machine_mode
, rtx
, bool);
1053 static bool spe_func_has_64bit_regs_p (void);
1054 static struct machine_function
* rs6000_init_machine_status (void);
1055 static int rs6000_ra_ever_killed (void);
1056 static tree
rs6000_handle_longcall_attribute (tree
*, tree
, tree
, int, bool *);
1057 static tree
rs6000_handle_altivec_attribute (tree
*, tree
, tree
, int, bool *);
1058 static tree
rs6000_handle_struct_attribute (tree
*, tree
, tree
, int, bool *);
1059 static tree
rs6000_builtin_vectorized_libmass (tree
, tree
, tree
);
1060 static rtx
rs6000_emit_set_long_const (rtx
, HOST_WIDE_INT
, HOST_WIDE_INT
);
1061 static int rs6000_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
1062 static bool rs6000_debug_rtx_costs (rtx
, int, int, int, int *, bool);
1063 static int rs6000_debug_address_cost (rtx
, enum machine_mode
, addr_space_t
,
1065 static int rs6000_debug_adjust_cost (rtx
, rtx
, rtx
, int);
1066 static bool is_microcoded_insn (rtx
);
1067 static bool is_nonpipeline_insn (rtx
);
1068 static bool is_cracked_insn (rtx
);
1069 static bool is_load_insn (rtx
, rtx
*);
1070 static bool is_store_insn (rtx
, rtx
*);
1071 static bool set_to_load_agen (rtx
,rtx
);
1072 static bool insn_terminates_group_p (rtx
, enum group_termination
);
1073 static bool insn_must_be_first_in_group (rtx
);
1074 static bool insn_must_be_last_in_group (rtx
);
1075 static void altivec_init_builtins (void);
1076 static tree
builtin_function_type (enum machine_mode
, enum machine_mode
,
1077 enum machine_mode
, enum machine_mode
,
1078 enum rs6000_builtins
, const char *name
);
1079 static void rs6000_common_init_builtins (void);
1080 static void paired_init_builtins (void);
1081 static rtx
paired_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1082 static void spe_init_builtins (void);
1083 static void htm_init_builtins (void);
1084 static rtx
spe_expand_predicate_builtin (enum insn_code
, tree
, rtx
);
1085 static rtx
spe_expand_evsel_builtin (enum insn_code
, tree
, rtx
);
1086 static int rs6000_emit_int_cmove (rtx
, rtx
, rtx
, rtx
);
1087 static rs6000_stack_t
*rs6000_stack_info (void);
1088 static void is_altivec_return_reg (rtx
, void *);
1089 int easy_vector_constant (rtx
, enum machine_mode
);
1090 static rtx
rs6000_debug_legitimize_address (rtx
, rtx
, enum machine_mode
);
1091 static rtx
rs6000_legitimize_tls_address (rtx
, enum tls_model
);
1092 static int rs6000_tls_symbol_ref_1 (rtx
*, void *);
1093 static int rs6000_get_some_local_dynamic_name_1 (rtx
*, void *);
1094 static rtx
rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*, const_tree
,
1097 static void macho_branch_islands (void);
1099 static rtx
rs6000_legitimize_reload_address (rtx
, enum machine_mode
, int, int,
1101 static rtx
rs6000_debug_legitimize_reload_address (rtx
, enum machine_mode
, int,
1103 static bool rs6000_mode_dependent_address (const_rtx
);
1104 static bool rs6000_debug_mode_dependent_address (const_rtx
);
1105 static enum reg_class
rs6000_secondary_reload_class (enum reg_class
,
1106 enum machine_mode
, rtx
);
1107 static enum reg_class
rs6000_debug_secondary_reload_class (enum reg_class
,
1110 static enum reg_class
rs6000_preferred_reload_class (rtx
, enum reg_class
);
1111 static enum reg_class
rs6000_debug_preferred_reload_class (rtx
,
1113 static bool rs6000_secondary_memory_needed (enum reg_class
, enum reg_class
,
1115 static bool rs6000_debug_secondary_memory_needed (enum reg_class
,
1118 static bool rs6000_cannot_change_mode_class (enum machine_mode
,
1121 static bool rs6000_debug_cannot_change_mode_class (enum machine_mode
,
1124 static bool rs6000_save_toc_in_prologue_p (void);
1126 rtx (*rs6000_legitimize_reload_address_ptr
) (rtx
, enum machine_mode
, int, int,
1128 = rs6000_legitimize_reload_address
;
1130 static bool (*rs6000_mode_dependent_address_ptr
) (const_rtx
)
1131 = rs6000_mode_dependent_address
;
1133 enum reg_class (*rs6000_secondary_reload_class_ptr
) (enum reg_class
,
1134 enum machine_mode
, rtx
)
1135 = rs6000_secondary_reload_class
;
1137 enum reg_class (*rs6000_preferred_reload_class_ptr
) (rtx
, enum reg_class
)
1138 = rs6000_preferred_reload_class
;
1140 bool (*rs6000_secondary_memory_needed_ptr
) (enum reg_class
, enum reg_class
,
1142 = rs6000_secondary_memory_needed
;
1144 bool (*rs6000_cannot_change_mode_class_ptr
) (enum machine_mode
,
1147 = rs6000_cannot_change_mode_class
;
1149 const int INSN_NOT_AVAILABLE
= -1;
1151 static void rs6000_print_isa_options (FILE *, int, const char *,
1153 static void rs6000_print_builtin_options (FILE *, int, const char *,
1156 static enum rs6000_reg_type
register_to_reg_type (rtx
, bool *);
1157 static bool rs6000_secondary_reload_move (enum rs6000_reg_type
,
1158 enum rs6000_reg_type
,
1160 secondary_reload_info
*,
1163 /* Hash table stuff for keeping track of TOC entries. */
1165 struct GTY(()) toc_hash_struct
1167 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
1168 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
1170 enum machine_mode key_mode
;
1174 static GTY ((param_is (struct toc_hash_struct
))) htab_t toc_hash_table
;
1176 /* Hash table to keep track of the argument types for builtin functions. */
1178 struct GTY(()) builtin_hash_struct
1181 enum machine_mode mode
[4]; /* return value + 3 arguments. */
1182 unsigned char uns_p
[4]; /* and whether the types are unsigned. */
1185 static GTY ((param_is (struct builtin_hash_struct
))) htab_t builtin_hash_table
;
1188 /* Default register names. */
1189 char rs6000_reg_names
[][8] =
1191 "0", "1", "2", "3", "4", "5", "6", "7",
1192 "8", "9", "10", "11", "12", "13", "14", "15",
1193 "16", "17", "18", "19", "20", "21", "22", "23",
1194 "24", "25", "26", "27", "28", "29", "30", "31",
1195 "0", "1", "2", "3", "4", "5", "6", "7",
1196 "8", "9", "10", "11", "12", "13", "14", "15",
1197 "16", "17", "18", "19", "20", "21", "22", "23",
1198 "24", "25", "26", "27", "28", "29", "30", "31",
1199 "mq", "lr", "ctr","ap",
1200 "0", "1", "2", "3", "4", "5", "6", "7",
1202 /* AltiVec registers. */
1203 "0", "1", "2", "3", "4", "5", "6", "7",
1204 "8", "9", "10", "11", "12", "13", "14", "15",
1205 "16", "17", "18", "19", "20", "21", "22", "23",
1206 "24", "25", "26", "27", "28", "29", "30", "31",
1208 /* SPE registers. */
1209 "spe_acc", "spefscr",
1210 /* Soft frame pointer. */
1212 /* HTM SPR registers. */
1213 "tfhar", "tfiar", "texasr"
1216 #ifdef TARGET_REGNAMES
1217 static const char alt_reg_names
[][8] =
1219 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
1220 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
1221 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
1222 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
1223 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
1224 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
1225 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
1226 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
1227 "mq", "lr", "ctr", "ap",
1228 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
1230 /* AltiVec registers. */
1231 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
1232 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
1233 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
1234 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
1236 /* SPE registers. */
1237 "spe_acc", "spefscr",
1238 /* Soft frame pointer. */
1240 /* HTM SPR registers. */
1241 "tfhar", "tfiar", "texasr"
1245 /* Table of valid machine attributes. */
1247 static const struct attribute_spec rs6000_attribute_table
[] =
1249 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
1250 affects_type_identity } */
1251 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute
,
1253 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1255 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute
,
1257 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1259 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute
,
1261 #ifdef SUBTARGET_ATTRIBUTE_TABLE
1262 SUBTARGET_ATTRIBUTE_TABLE
,
1264 { NULL
, 0, 0, false, false, false, NULL
, false }
1267 #ifndef TARGET_PROFILE_KERNEL
1268 #define TARGET_PROFILE_KERNEL 0
1271 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
1272 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
1274 /* Initialize the GCC target structure. */
1275 #undef TARGET_ATTRIBUTE_TABLE
1276 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
1277 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
1278 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
1279 #undef TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P
1280 #define TARGET_ATTRIBUTE_TAKES_IDENTIFIER_P rs6000_attribute_takes_identifier_p
1282 #undef TARGET_ASM_ALIGNED_DI_OP
1283 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1285 /* Default unaligned ops are only provided for ELF. Find the ops needed
1286 for non-ELF systems. */
1287 #ifndef OBJECT_FORMAT_ELF
1289 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1291 #undef TARGET_ASM_UNALIGNED_HI_OP
1292 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1293 #undef TARGET_ASM_UNALIGNED_SI_OP
1294 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1295 #undef TARGET_ASM_UNALIGNED_DI_OP
1296 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1299 #undef TARGET_ASM_UNALIGNED_HI_OP
1300 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1301 #undef TARGET_ASM_UNALIGNED_SI_OP
1302 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1303 #undef TARGET_ASM_UNALIGNED_DI_OP
1304 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1305 #undef TARGET_ASM_ALIGNED_DI_OP
1306 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1310 /* This hook deals with fixups for relocatable code and DI-mode objects
1312 #undef TARGET_ASM_INTEGER
1313 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1315 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
1316 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1317 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1320 #undef TARGET_SET_UP_BY_PROLOGUE
1321 #define TARGET_SET_UP_BY_PROLOGUE rs6000_set_up_by_prologue
1323 #undef TARGET_HAVE_TLS
1324 #define TARGET_HAVE_TLS HAVE_AS_TLS
1326 #undef TARGET_CANNOT_FORCE_CONST_MEM
1327 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_cannot_force_const_mem
1329 #undef TARGET_DELEGITIMIZE_ADDRESS
1330 #define TARGET_DELEGITIMIZE_ADDRESS rs6000_delegitimize_address
1332 #undef TARGET_CONST_NOT_OK_FOR_DEBUG_P
1333 #define TARGET_CONST_NOT_OK_FOR_DEBUG_P rs6000_const_not_ok_for_debug_p
1335 #undef TARGET_ASM_FUNCTION_PROLOGUE
1336 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1337 #undef TARGET_ASM_FUNCTION_EPILOGUE
1338 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1340 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
1341 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA rs6000_output_addr_const_extra
1343 #undef TARGET_LEGITIMIZE_ADDRESS
1344 #define TARGET_LEGITIMIZE_ADDRESS rs6000_legitimize_address
1346 #undef TARGET_SCHED_VARIABLE_ISSUE
1347 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1349 #undef TARGET_SCHED_ISSUE_RATE
1350 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1351 #undef TARGET_SCHED_ADJUST_COST
1352 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1353 #undef TARGET_SCHED_ADJUST_PRIORITY
1354 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1355 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1356 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1357 #undef TARGET_SCHED_INIT
1358 #define TARGET_SCHED_INIT rs6000_sched_init
1359 #undef TARGET_SCHED_FINISH
1360 #define TARGET_SCHED_FINISH rs6000_sched_finish
1361 #undef TARGET_SCHED_REORDER
1362 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1363 #undef TARGET_SCHED_REORDER2
1364 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1366 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1367 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1369 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1370 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1372 #undef TARGET_SCHED_ALLOC_SCHED_CONTEXT
1373 #define TARGET_SCHED_ALLOC_SCHED_CONTEXT rs6000_alloc_sched_context
1374 #undef TARGET_SCHED_INIT_SCHED_CONTEXT
1375 #define TARGET_SCHED_INIT_SCHED_CONTEXT rs6000_init_sched_context
1376 #undef TARGET_SCHED_SET_SCHED_CONTEXT
1377 #define TARGET_SCHED_SET_SCHED_CONTEXT rs6000_set_sched_context
1378 #undef TARGET_SCHED_FREE_SCHED_CONTEXT
1379 #define TARGET_SCHED_FREE_SCHED_CONTEXT rs6000_free_sched_context
1381 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1382 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1383 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
1384 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
1385 rs6000_builtin_support_vector_misalignment
1386 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
1387 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1388 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
1389 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
1390 rs6000_builtin_vectorization_cost
1391 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
1392 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
1393 rs6000_preferred_simd_mode
1394 #undef TARGET_VECTORIZE_INIT_COST
1395 #define TARGET_VECTORIZE_INIT_COST rs6000_init_cost
1396 #undef TARGET_VECTORIZE_ADD_STMT_COST
1397 #define TARGET_VECTORIZE_ADD_STMT_COST rs6000_add_stmt_cost
1398 #undef TARGET_VECTORIZE_FINISH_COST
1399 #define TARGET_VECTORIZE_FINISH_COST rs6000_finish_cost
1400 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
1401 #define TARGET_VECTORIZE_DESTROY_COST_DATA rs6000_destroy_cost_data
1403 #undef TARGET_INIT_BUILTINS
1404 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1405 #undef TARGET_BUILTIN_DECL
1406 #define TARGET_BUILTIN_DECL rs6000_builtin_decl
1408 #undef TARGET_EXPAND_BUILTIN
1409 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1411 #undef TARGET_MANGLE_TYPE
1412 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1414 #undef TARGET_INIT_LIBFUNCS
1415 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1418 #undef TARGET_BINDS_LOCAL_P
1419 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1422 #undef TARGET_MS_BITFIELD_LAYOUT_P
1423 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1425 #undef TARGET_ASM_OUTPUT_MI_THUNK
1426 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1428 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1429 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1431 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1432 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1434 #undef TARGET_REGISTER_MOVE_COST
1435 #define TARGET_REGISTER_MOVE_COST rs6000_register_move_cost
1436 #undef TARGET_MEMORY_MOVE_COST
1437 #define TARGET_MEMORY_MOVE_COST rs6000_memory_move_cost
1438 #undef TARGET_RTX_COSTS
1439 #define TARGET_RTX_COSTS rs6000_rtx_costs
1440 #undef TARGET_ADDRESS_COST
1441 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
1443 #undef TARGET_DWARF_REGISTER_SPAN
1444 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1446 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1447 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1449 #undef TARGET_MEMBER_TYPE_FORCES_BLK
1450 #define TARGET_MEMBER_TYPE_FORCES_BLK rs6000_member_type_forces_blk
1452 /* On rs6000, function arguments are promoted, as are function return
1454 #undef TARGET_PROMOTE_FUNCTION_MODE
1455 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
1457 #undef TARGET_RETURN_IN_MEMORY
1458 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1460 #undef TARGET_RETURN_IN_MSB
1461 #define TARGET_RETURN_IN_MSB rs6000_return_in_msb
1463 #undef TARGET_SETUP_INCOMING_VARARGS
1464 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1466 /* Always strict argument naming on rs6000. */
1467 #undef TARGET_STRICT_ARGUMENT_NAMING
1468 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1469 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1470 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1471 #undef TARGET_SPLIT_COMPLEX_ARG
1472 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1473 #undef TARGET_MUST_PASS_IN_STACK
1474 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1475 #undef TARGET_PASS_BY_REFERENCE
1476 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1477 #undef TARGET_ARG_PARTIAL_BYTES
1478 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1479 #undef TARGET_FUNCTION_ARG_ADVANCE
1480 #define TARGET_FUNCTION_ARG_ADVANCE rs6000_function_arg_advance
1481 #undef TARGET_FUNCTION_ARG
1482 #define TARGET_FUNCTION_ARG rs6000_function_arg
1483 #undef TARGET_FUNCTION_ARG_BOUNDARY
1484 #define TARGET_FUNCTION_ARG_BOUNDARY rs6000_function_arg_boundary
1486 #undef TARGET_BUILD_BUILTIN_VA_LIST
1487 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1489 #undef TARGET_EXPAND_BUILTIN_VA_START
1490 #define TARGET_EXPAND_BUILTIN_VA_START rs6000_va_start
1492 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1493 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1495 #undef TARGET_EH_RETURN_FILTER_MODE
1496 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1498 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1499 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1501 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1502 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1504 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1505 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1507 #undef TARGET_ASM_LOOP_ALIGN_MAX_SKIP
1508 #define TARGET_ASM_LOOP_ALIGN_MAX_SKIP rs6000_loop_align_max_skip
1510 #undef TARGET_OPTION_OVERRIDE
1511 #define TARGET_OPTION_OVERRIDE rs6000_option_override
1513 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
1514 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
1515 rs6000_builtin_vectorized_function
1518 #undef TARGET_STACK_PROTECT_FAIL
1519 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1522 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1523 The PowerPC architecture requires only weak consistency among
1524 processors--that is, memory accesses between processors need not be
1525 sequentially consistent and memory accesses among processors can occur
1526 in any order. The ability to order memory accesses weakly provides
1527 opportunities for more efficient use of the system bus. Unless a
1528 dependency exists, the 604e allows read operations to precede store
1530 #undef TARGET_RELAXED_ORDERING
1531 #define TARGET_RELAXED_ORDERING true
1534 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1535 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1538 /* Use a 32-bit anchor range. This leads to sequences like:
1540 addis tmp,anchor,high
1543 where tmp itself acts as an anchor, and can be shared between
1544 accesses to the same 64k page. */
1545 #undef TARGET_MIN_ANCHOR_OFFSET
1546 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1547 #undef TARGET_MAX_ANCHOR_OFFSET
1548 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1549 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1550 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1551 #undef TARGET_USE_BLOCKS_FOR_DECL_P
1552 #define TARGET_USE_BLOCKS_FOR_DECL_P rs6000_use_blocks_for_decl_p
1554 #undef TARGET_BUILTIN_RECIPROCAL
1555 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1557 #undef TARGET_EXPAND_TO_RTL_HOOK
1558 #define TARGET_EXPAND_TO_RTL_HOOK rs6000_alloc_sdmode_stack_slot
1560 #undef TARGET_INSTANTIATE_DECLS
1561 #define TARGET_INSTANTIATE_DECLS rs6000_instantiate_decls
1563 #undef TARGET_SECONDARY_RELOAD
1564 #define TARGET_SECONDARY_RELOAD rs6000_secondary_reload
1566 #undef TARGET_LEGITIMATE_ADDRESS_P
1567 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
1569 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
1570 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
1573 #define TARGET_LRA_P rs6000_lra_p
1575 #undef TARGET_CAN_ELIMINATE
1576 #define TARGET_CAN_ELIMINATE rs6000_can_eliminate
1578 #undef TARGET_CONDITIONAL_REGISTER_USAGE
1579 #define TARGET_CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage
1581 #undef TARGET_TRAMPOLINE_INIT
1582 #define TARGET_TRAMPOLINE_INIT rs6000_trampoline_init
1584 #undef TARGET_FUNCTION_VALUE
1585 #define TARGET_FUNCTION_VALUE rs6000_function_value
1587 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
1588 #define TARGET_OPTION_VALID_ATTRIBUTE_P rs6000_valid_attribute_p
1590 #undef TARGET_OPTION_SAVE
1591 #define TARGET_OPTION_SAVE rs6000_function_specific_save
1593 #undef TARGET_OPTION_RESTORE
1594 #define TARGET_OPTION_RESTORE rs6000_function_specific_restore
1596 #undef TARGET_OPTION_PRINT
1597 #define TARGET_OPTION_PRINT rs6000_function_specific_print
1599 #undef TARGET_CAN_INLINE_P
1600 #define TARGET_CAN_INLINE_P rs6000_can_inline_p
1602 #undef TARGET_SET_CURRENT_FUNCTION
1603 #define TARGET_SET_CURRENT_FUNCTION rs6000_set_current_function
1605 #undef TARGET_LEGITIMATE_CONSTANT_P
1606 #define TARGET_LEGITIMATE_CONSTANT_P rs6000_legitimate_constant_p
1608 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
1609 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK rs6000_vectorize_vec_perm_const_ok
1611 #undef TARGET_CAN_USE_DOLOOP_P
1612 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
1615 /* Processor table. */
1618 const char *const name
; /* Canonical processor name. */
1619 const enum processor_type processor
; /* Processor type enum value. */
1620 const HOST_WIDE_INT target_enable
; /* Target flags to enable. */
1623 static struct rs6000_ptt
const processor_target_table
[] =
1625 #define RS6000_CPU(NAME, CPU, FLAGS) { NAME, CPU, FLAGS },
1626 #include "rs6000-cpus.def"
1630 /* Look up a processor name for -mcpu=xxx and -mtune=xxx. Return -1 if the
1634 rs6000_cpu_name_lookup (const char *name
)
1640 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
1641 if (! strcmp (name
, processor_target_table
[i
].name
))
1649 /* Return number of consecutive hard regs needed starting at reg REGNO
1650 to hold something of mode MODE.
1651 This is ordinarily the length in words of a value of mode MODE
1652 but can be less for certain modes in special long registers.
1654 For the SPE, GPRs are 64 bits but only 32 bits are visible in
1655 scalar instructions. The upper 32 bits are only available to the
1658 POWER and PowerPC GPRs hold 32 bits worth;
1659 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
1662 rs6000_hard_regno_nregs_internal (int regno
, enum machine_mode mode
)
1664 unsigned HOST_WIDE_INT reg_size
;
1666 /* TF/TD modes are special in that they always take 2 registers. */
1667 if (FP_REGNO_P (regno
))
1668 reg_size
= ((VECTOR_MEM_VSX_P (mode
) && mode
!= TDmode
&& mode
!= TFmode
)
1669 ? UNITS_PER_VSX_WORD
1670 : UNITS_PER_FP_WORD
);
1672 else if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1673 reg_size
= UNITS_PER_SPE_WORD
;
1675 else if (ALTIVEC_REGNO_P (regno
))
1676 reg_size
= UNITS_PER_ALTIVEC_WORD
;
1678 /* The value returned for SCmode in the E500 double case is 2 for
1679 ABI compatibility; storing an SCmode value in a single register
1680 would require function_arg and rs6000_spe_function_arg to handle
1681 SCmode so as to pass the value correctly in a pair of
1683 else if (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
) && mode
!= SCmode
1684 && !DECIMAL_FLOAT_MODE_P (mode
))
1685 reg_size
= UNITS_PER_FP_WORD
;
1688 reg_size
= UNITS_PER_WORD
;
1690 return (GET_MODE_SIZE (mode
) + reg_size
- 1) / reg_size
;
1693 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1696 rs6000_hard_regno_mode_ok (int regno
, enum machine_mode mode
)
1698 int last_regno
= regno
+ rs6000_hard_regno_nregs
[mode
][regno
] - 1;
1700 /* PTImode can only go in GPRs. Quad word memory operations require even/odd
1701 register combinations, and use PTImode where we need to deal with quad
1702 word memory operations. Don't allow quad words in the argument or frame
1703 pointer registers, just registers 0..31. */
1704 if (mode
== PTImode
)
1705 return (IN_RANGE (regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1706 && IN_RANGE (last_regno
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
)
1707 && ((regno
& 1) == 0));
1709 /* VSX registers that overlap the FPR registers are larger than for non-VSX
1710 implementations. Don't allow an item to be split between a FP register
1711 and an Altivec register. Allow TImode in all VSX registers if the user
1713 if (TARGET_VSX
&& VSX_REGNO_P (regno
)
1714 && (VECTOR_MEM_VSX_P (mode
)
1715 || (TARGET_VSX_SCALAR_FLOAT
&& mode
== SFmode
)
1716 || (TARGET_VSX_SCALAR_DOUBLE
&& (mode
== DFmode
|| mode
== DImode
))
1717 || (TARGET_VSX_TIMODE
&& mode
== TImode
)))
1719 if (FP_REGNO_P (regno
))
1720 return FP_REGNO_P (last_regno
);
1722 if (ALTIVEC_REGNO_P (regno
))
1724 if (mode
== SFmode
&& !TARGET_UPPER_REGS_SF
)
1727 if ((mode
== DFmode
|| mode
== DImode
) && !TARGET_UPPER_REGS_DF
)
1730 return ALTIVEC_REGNO_P (last_regno
);
1734 /* The GPRs can hold any mode, but values bigger than one register
1735 cannot go past R31. */
1736 if (INT_REGNO_P (regno
))
1737 return INT_REGNO_P (last_regno
);
1739 /* The float registers (except for VSX vector modes) can only hold floating
1740 modes and DImode. */
1741 if (FP_REGNO_P (regno
))
1743 if (SCALAR_FLOAT_MODE_P (mode
)
1744 && (mode
!= TDmode
|| (regno
% 2) == 0)
1745 && FP_REGNO_P (last_regno
))
1748 if (GET_MODE_CLASS (mode
) == MODE_INT
1749 && GET_MODE_SIZE (mode
) == UNITS_PER_FP_WORD
)
1752 if (PAIRED_SIMD_REGNO_P (regno
) && TARGET_PAIRED_FLOAT
1753 && PAIRED_VECTOR_MODE (mode
))
1759 /* The CR register can only hold CC modes. */
1760 if (CR_REGNO_P (regno
))
1761 return GET_MODE_CLASS (mode
) == MODE_CC
;
1763 if (CA_REGNO_P (regno
))
1764 return mode
== BImode
;
1766 /* AltiVec only in AldyVec registers. */
1767 if (ALTIVEC_REGNO_P (regno
))
1768 return VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
);
1770 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1771 if (SPE_SIMD_REGNO_P (regno
) && TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
1774 /* We cannot put non-VSX TImode or PTImode anywhere except general register
1775 and it must be able to fit within the register set. */
1777 return GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
;
1780 /* Print interesting facts about registers. */
1782 rs6000_debug_reg_print (int first_regno
, int last_regno
, const char *reg_name
)
1786 for (r
= first_regno
; r
<= last_regno
; ++r
)
1788 const char *comma
= "";
1791 if (first_regno
== last_regno
)
1792 fprintf (stderr
, "%s:\t", reg_name
);
1794 fprintf (stderr
, "%s%d:\t", reg_name
, r
- first_regno
);
1797 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
1798 if (rs6000_hard_regno_mode_ok_p
[m
][r
] && rs6000_hard_regno_nregs
[m
][r
])
1802 fprintf (stderr
, ",\n\t");
1807 if (rs6000_hard_regno_nregs
[m
][r
] > 1)
1808 len
+= fprintf (stderr
, "%s%s/%d", comma
, GET_MODE_NAME (m
),
1809 rs6000_hard_regno_nregs
[m
][r
]);
1811 len
+= fprintf (stderr
, "%s%s", comma
, GET_MODE_NAME (m
));
1816 if (call_used_regs
[r
])
1820 fprintf (stderr
, ",\n\t");
1825 len
+= fprintf (stderr
, "%s%s", comma
, "call-used");
1833 fprintf (stderr
, ",\n\t");
1838 len
+= fprintf (stderr
, "%s%s", comma
, "fixed");
1844 fprintf (stderr
, ",\n\t");
1848 len
+= fprintf (stderr
, "%sreg-class = %s", comma
,
1849 reg_class_names
[(int)rs6000_regno_regclass
[r
]]);
1854 fprintf (stderr
, ",\n\t");
1858 fprintf (stderr
, "%sregno = %d\n", comma
, r
);
1863 rs6000_debug_vector_unit (enum rs6000_vector v
)
1869 case VECTOR_NONE
: ret
= "none"; break;
1870 case VECTOR_ALTIVEC
: ret
= "altivec"; break;
1871 case VECTOR_VSX
: ret
= "vsx"; break;
1872 case VECTOR_P8_VECTOR
: ret
= "p8_vector"; break;
1873 case VECTOR_PAIRED
: ret
= "paired"; break;
1874 case VECTOR_SPE
: ret
= "spe"; break;
1875 case VECTOR_OTHER
: ret
= "other"; break;
1876 default: ret
= "unknown"; break;
1882 /* Print the address masks in a human readble fashion. */
1884 rs6000_debug_print_mode (ssize_t m
)
1888 fprintf (stderr
, "Mode: %-5s", GET_MODE_NAME (m
));
1889 for (rc
= 0; rc
< N_RELOAD_REG
; rc
++)
1891 addr_mask_type mask
= reg_addr
[m
].addr_mask
[rc
];
1893 " %s: %c%c%c%c%c%c",
1894 reload_reg_map
[rc
].name
,
1895 (mask
& RELOAD_REG_VALID
) != 0 ? 'v' : ' ',
1896 (mask
& RELOAD_REG_MULTIPLE
) != 0 ? 'm' : ' ',
1897 (mask
& RELOAD_REG_INDEXED
) != 0 ? 'i' : ' ',
1898 (mask
& RELOAD_REG_OFFSET
) != 0 ? 'o' : ' ',
1899 (mask
& RELOAD_REG_PRE_INCDEC
) != 0 ? '+' : ' ',
1900 (mask
& RELOAD_REG_PRE_MODIFY
) != 0 ? '+' : ' ');
1903 if (rs6000_vector_unit
[m
] != VECTOR_NONE
1904 || rs6000_vector_mem
[m
] != VECTOR_NONE
1905 || (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
)
1906 || (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
))
1909 " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c",
1910 rs6000_debug_vector_unit (rs6000_vector_unit
[m
]),
1911 rs6000_debug_vector_unit (rs6000_vector_mem
[m
]),
1912 (reg_addr
[m
].reload_store
!= CODE_FOR_nothing
) ? 's' : '*',
1913 (reg_addr
[m
].reload_load
!= CODE_FOR_nothing
) ? 'l' : '*');
1916 fputs ("\n", stderr
);
1919 #define DEBUG_FMT_ID "%-32s= "
1920 #define DEBUG_FMT_D DEBUG_FMT_ID "%d\n"
1921 #define DEBUG_FMT_WX DEBUG_FMT_ID "%#.12" HOST_WIDE_INT_PRINT "x: "
1922 #define DEBUG_FMT_S DEBUG_FMT_ID "%s\n"
1924 /* Print various interesting information with -mdebug=reg. */
1926 rs6000_debug_reg_global (void)
1928 static const char *const tf
[2] = { "false", "true" };
1929 const char *nl
= (const char *)0;
1932 char costly_num
[20];
1934 char flags_buffer
[40];
1935 const char *costly_str
;
1936 const char *nop_str
;
1937 const char *trace_str
;
1938 const char *abi_str
;
1939 const char *cmodel_str
;
1940 struct cl_target_option cl_opts
;
1942 /* Modes we want tieable information on. */
1943 static const enum machine_mode print_tieable_modes
[] = {
1977 /* Virtual regs we are interested in. */
1978 const static struct {
1979 int regno
; /* register number. */
1980 const char *name
; /* register name. */
1981 } virtual_regs
[] = {
1982 { STACK_POINTER_REGNUM
, "stack pointer:" },
1983 { TOC_REGNUM
, "toc: " },
1984 { STATIC_CHAIN_REGNUM
, "static chain: " },
1985 { RS6000_PIC_OFFSET_TABLE_REGNUM
, "pic offset: " },
1986 { HARD_FRAME_POINTER_REGNUM
, "hard frame: " },
1987 { ARG_POINTER_REGNUM
, "arg pointer: " },
1988 { FRAME_POINTER_REGNUM
, "frame pointer:" },
1989 { FIRST_PSEUDO_REGISTER
, "first pseudo: " },
1990 { FIRST_VIRTUAL_REGISTER
, "first virtual:" },
1991 { VIRTUAL_INCOMING_ARGS_REGNUM
, "incoming_args:" },
1992 { VIRTUAL_STACK_VARS_REGNUM
, "stack_vars: " },
1993 { VIRTUAL_STACK_DYNAMIC_REGNUM
, "stack_dynamic:" },
1994 { VIRTUAL_OUTGOING_ARGS_REGNUM
, "outgoing_args:" },
1995 { VIRTUAL_CFA_REGNUM
, "cfa (frame): " },
1996 { VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
, "stack boundry:" },
1997 { LAST_VIRTUAL_REGISTER
, "last virtual: " },
2000 fputs ("\nHard register information:\n", stderr
);
2001 rs6000_debug_reg_print (FIRST_GPR_REGNO
, LAST_GPR_REGNO
, "gr");
2002 rs6000_debug_reg_print (FIRST_FPR_REGNO
, LAST_FPR_REGNO
, "fp");
2003 rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO
,
2006 rs6000_debug_reg_print (LR_REGNO
, LR_REGNO
, "lr");
2007 rs6000_debug_reg_print (CTR_REGNO
, CTR_REGNO
, "ctr");
2008 rs6000_debug_reg_print (CR0_REGNO
, CR7_REGNO
, "cr");
2009 rs6000_debug_reg_print (CA_REGNO
, CA_REGNO
, "ca");
2010 rs6000_debug_reg_print (VRSAVE_REGNO
, VRSAVE_REGNO
, "vrsave");
2011 rs6000_debug_reg_print (VSCR_REGNO
, VSCR_REGNO
, "vscr");
2012 rs6000_debug_reg_print (SPE_ACC_REGNO
, SPE_ACC_REGNO
, "spe_a");
2013 rs6000_debug_reg_print (SPEFSCR_REGNO
, SPEFSCR_REGNO
, "spe_f");
2015 fputs ("\nVirtual/stack/frame registers:\n", stderr
);
2016 for (v
= 0; v
< ARRAY_SIZE (virtual_regs
); v
++)
2017 fprintf (stderr
, "%s regno = %3d\n", virtual_regs
[v
].name
, virtual_regs
[v
].regno
);
2021 "d reg_class = %s\n"
2022 "f reg_class = %s\n"
2023 "v reg_class = %s\n"
2024 "wa reg_class = %s\n"
2025 "wd reg_class = %s\n"
2026 "wf reg_class = %s\n"
2027 "wg reg_class = %s\n"
2028 "wl reg_class = %s\n"
2029 "wm reg_class = %s\n"
2030 "wr reg_class = %s\n"
2031 "ws reg_class = %s\n"
2032 "wt reg_class = %s\n"
2033 "wu reg_class = %s\n"
2034 "wv reg_class = %s\n"
2035 "ww reg_class = %s\n"
2036 "wx reg_class = %s\n"
2037 "wy reg_class = %s\n"
2038 "wz reg_class = %s\n"
2040 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_d
]],
2041 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_f
]],
2042 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_v
]],
2043 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wa
]],
2044 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wd
]],
2045 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wf
]],
2046 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wg
]],
2047 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wl
]],
2048 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wm
]],
2049 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wr
]],
2050 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ws
]],
2051 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wt
]],
2052 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wu
]],
2053 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wv
]],
2054 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_ww
]],
2055 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wx
]],
2056 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wy
]],
2057 reg_class_names
[rs6000_constraints
[RS6000_CONSTRAINT_wz
]]);
2060 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2061 rs6000_debug_print_mode (m
);
2063 fputs ("\n", stderr
);
2065 for (m1
= 0; m1
< ARRAY_SIZE (print_tieable_modes
); m1
++)
2067 enum machine_mode mode1
= print_tieable_modes
[m1
];
2068 bool first_time
= true;
2070 nl
= (const char *)0;
2071 for (m2
= 0; m2
< ARRAY_SIZE (print_tieable_modes
); m2
++)
2073 enum machine_mode mode2
= print_tieable_modes
[m2
];
2074 if (mode1
!= mode2
&& MODES_TIEABLE_P (mode1
, mode2
))
2078 fprintf (stderr
, "Tieable modes %s:", GET_MODE_NAME (mode1
));
2083 fprintf (stderr
, " %s", GET_MODE_NAME (mode2
));
2088 fputs ("\n", stderr
);
2094 if (rs6000_recip_control
)
2096 fprintf (stderr
, "\nReciprocal mask = 0x%x\n", rs6000_recip_control
);
2098 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2099 if (rs6000_recip_bits
[m
])
2102 "Reciprocal estimate mode: %-5s divide: %s rsqrt: %s\n",
2104 (RS6000_RECIP_AUTO_RE_P (m
)
2106 : (RS6000_RECIP_HAVE_RE_P (m
) ? "have" : "none")),
2107 (RS6000_RECIP_AUTO_RSQRTE_P (m
)
2109 : (RS6000_RECIP_HAVE_RSQRTE_P (m
) ? "have" : "none")));
2112 fputs ("\n", stderr
);
2115 if (rs6000_cpu_index
>= 0)
2117 const char *name
= processor_target_table
[rs6000_cpu_index
].name
;
2119 = processor_target_table
[rs6000_cpu_index
].target_enable
;
2121 sprintf (flags_buffer
, "-mcpu=%s flags", name
);
2122 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2125 fprintf (stderr
, DEBUG_FMT_S
, "cpu", "<none>");
2127 if (rs6000_tune_index
>= 0)
2129 const char *name
= processor_target_table
[rs6000_tune_index
].name
;
2131 = processor_target_table
[rs6000_tune_index
].target_enable
;
2133 sprintf (flags_buffer
, "-mtune=%s flags", name
);
2134 rs6000_print_isa_options (stderr
, 0, flags_buffer
, flags
);
2137 fprintf (stderr
, DEBUG_FMT_S
, "tune", "<none>");
2139 cl_target_option_save (&cl_opts
, &global_options
);
2140 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags",
2143 rs6000_print_isa_options (stderr
, 0, "rs6000_isa_flags_explicit",
2144 rs6000_isa_flags_explicit
);
2146 rs6000_print_builtin_options (stderr
, 0, "rs6000_builtin_mask",
2147 rs6000_builtin_mask
);
2149 rs6000_print_isa_options (stderr
, 0, "TARGET_DEFAULT", TARGET_DEFAULT
);
2151 fprintf (stderr
, DEBUG_FMT_S
, "--with-cpu default",
2152 OPTION_TARGET_CPU_DEFAULT
? OPTION_TARGET_CPU_DEFAULT
: "<none>");
2154 switch (rs6000_sched_costly_dep
)
2156 case max_dep_latency
:
2157 costly_str
= "max_dep_latency";
2161 costly_str
= "no_dep_costly";
2164 case all_deps_costly
:
2165 costly_str
= "all_deps_costly";
2168 case true_store_to_load_dep_costly
:
2169 costly_str
= "true_store_to_load_dep_costly";
2172 case store_to_load_dep_costly
:
2173 costly_str
= "store_to_load_dep_costly";
2177 costly_str
= costly_num
;
2178 sprintf (costly_num
, "%d", (int)rs6000_sched_costly_dep
);
2182 fprintf (stderr
, DEBUG_FMT_S
, "sched_costly_dep", costly_str
);
2184 switch (rs6000_sched_insert_nops
)
2186 case sched_finish_regroup_exact
:
2187 nop_str
= "sched_finish_regroup_exact";
2190 case sched_finish_pad_groups
:
2191 nop_str
= "sched_finish_pad_groups";
2194 case sched_finish_none
:
2195 nop_str
= "sched_finish_none";
2200 sprintf (nop_num
, "%d", (int)rs6000_sched_insert_nops
);
2204 fprintf (stderr
, DEBUG_FMT_S
, "sched_insert_nops", nop_str
);
2206 switch (rs6000_sdata
)
2213 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "data");
2217 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "sysv");
2221 fprintf (stderr
, DEBUG_FMT_S
, "sdata", "eabi");
2226 switch (rs6000_traceback
)
2228 case traceback_default
: trace_str
= "default"; break;
2229 case traceback_none
: trace_str
= "none"; break;
2230 case traceback_part
: trace_str
= "part"; break;
2231 case traceback_full
: trace_str
= "full"; break;
2232 default: trace_str
= "unknown"; break;
2235 fprintf (stderr
, DEBUG_FMT_S
, "traceback", trace_str
);
2237 switch (rs6000_current_cmodel
)
2239 case CMODEL_SMALL
: cmodel_str
= "small"; break;
2240 case CMODEL_MEDIUM
: cmodel_str
= "medium"; break;
2241 case CMODEL_LARGE
: cmodel_str
= "large"; break;
2242 default: cmodel_str
= "unknown"; break;
2245 fprintf (stderr
, DEBUG_FMT_S
, "cmodel", cmodel_str
);
2247 switch (rs6000_current_abi
)
2249 case ABI_NONE
: abi_str
= "none"; break;
2250 case ABI_AIX
: abi_str
= "aix"; break;
2251 case ABI_ELFv2
: abi_str
= "ELFv2"; break;
2252 case ABI_V4
: abi_str
= "V4"; break;
2253 case ABI_DARWIN
: abi_str
= "darwin"; break;
2254 default: abi_str
= "unknown"; break;
2257 fprintf (stderr
, DEBUG_FMT_S
, "abi", abi_str
);
2259 if (rs6000_altivec_abi
)
2260 fprintf (stderr
, DEBUG_FMT_S
, "altivec_abi", "true");
2263 fprintf (stderr
, DEBUG_FMT_S
, "spe_abi", "true");
2265 if (rs6000_darwin64_abi
)
2266 fprintf (stderr
, DEBUG_FMT_S
, "darwin64_abi", "true");
2268 if (rs6000_float_gprs
)
2269 fprintf (stderr
, DEBUG_FMT_S
, "float_gprs", "true");
2271 if (TARGET_LINK_STACK
)
2272 fprintf (stderr
, DEBUG_FMT_S
, "link_stack", "true");
2274 if (targetm
.lra_p ())
2275 fprintf (stderr
, DEBUG_FMT_S
, "lra", "true");
2277 if (TARGET_P8_FUSION
)
2278 fprintf (stderr
, DEBUG_FMT_S
, "p8 fusion",
2279 (TARGET_P8_FUSION_SIGN
) ? "zero+sign" : "zero");
2281 fprintf (stderr
, DEBUG_FMT_S
, "plt-format",
2282 TARGET_SECURE_PLT
? "secure" : "bss");
2283 fprintf (stderr
, DEBUG_FMT_S
, "struct-return",
2284 aix_struct_return
? "aix" : "sysv");
2285 fprintf (stderr
, DEBUG_FMT_S
, "always_hint", tf
[!!rs6000_always_hint
]);
2286 fprintf (stderr
, DEBUG_FMT_S
, "sched_groups", tf
[!!rs6000_sched_groups
]);
2287 fprintf (stderr
, DEBUG_FMT_S
, "align_branch",
2288 tf
[!!rs6000_align_branch_targets
]);
2289 fprintf (stderr
, DEBUG_FMT_D
, "tls_size", rs6000_tls_size
);
2290 fprintf (stderr
, DEBUG_FMT_D
, "long_double_size",
2291 rs6000_long_double_type_size
);
2292 fprintf (stderr
, DEBUG_FMT_D
, "sched_restricted_insns_priority",
2293 (int)rs6000_sched_restricted_insns_priority
);
2294 fprintf (stderr
, DEBUG_FMT_D
, "Number of standard builtins",
2296 fprintf (stderr
, DEBUG_FMT_D
, "Number of rs6000 builtins",
2297 (int)RS6000_BUILTIN_COUNT
);
2301 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2302 legitimate address support to figure out the appropriate addressing to
2306 rs6000_setup_reg_addr_masks (void)
2308 ssize_t rc
, reg
, m
, nregs
;
2309 addr_mask_type any_addr_mask
, addr_mask
;
2311 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2313 /* SDmode is special in that we want to access it only via REG+REG
2314 addressing on power7 and above, since we want to use the LFIWZX and
2315 STFIWZX instructions to load it. */
2316 bool indexed_only_p
= (m
== SDmode
&& TARGET_NO_SDMODE_STACK
);
2319 for (rc
= FIRST_RELOAD_REG_CLASS
; rc
<= LAST_RELOAD_REG_CLASS
; rc
++)
2322 reg
= reload_reg_map
[rc
].reg
;
2324 /* Can mode values go in the GPR/FPR/Altivec registers? */
2325 if (reg
>= 0 && rs6000_hard_regno_mode_ok_p
[m
][reg
])
2327 nregs
= rs6000_hard_regno_nregs
[m
][reg
];
2328 addr_mask
|= RELOAD_REG_VALID
;
2330 /* Indicate if the mode takes more than 1 physical register. If
2331 it takes a single register, indicate it can do REG+REG
2333 if (nregs
> 1 || m
== BLKmode
)
2334 addr_mask
|= RELOAD_REG_MULTIPLE
;
2336 addr_mask
|= RELOAD_REG_INDEXED
;
2338 /* Figure out if we can do PRE_INC, PRE_DEC, or PRE_MODIFY
2339 addressing. Restrict addressing on SPE for 64-bit types
2340 because of the SUBREG hackery used to address 64-bit floats in
2341 '32-bit' GPRs. To simplify secondary reload, don't allow
2342 update forms on scalar floating point types that can go in the
2346 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
)
2347 && GET_MODE_SIZE (m
) <= 8
2348 && !VECTOR_MODE_P (m
)
2349 && !COMPLEX_MODE_P (m
)
2351 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (m
) == 8)
2352 && !(m
== DFmode
&& TARGET_UPPER_REGS_DF
)
2353 && !(m
== SFmode
&& TARGET_UPPER_REGS_SF
))
2355 addr_mask
|= RELOAD_REG_PRE_INCDEC
;
2357 /* PRE_MODIFY is more restricted than PRE_INC/PRE_DEC in that
2358 we don't allow PRE_MODIFY for some multi-register
2363 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2367 if (TARGET_POWERPC64
)
2368 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2374 addr_mask
|= RELOAD_REG_PRE_MODIFY
;
2380 /* GPR and FPR registers can do REG+OFFSET addressing, except
2381 possibly for SDmode. */
2382 if ((addr_mask
!= 0) && !indexed_only_p
2383 && (rc
== RELOAD_REG_GPR
|| rc
== RELOAD_REG_FPR
))
2384 addr_mask
|= RELOAD_REG_OFFSET
;
2386 reg_addr
[m
].addr_mask
[rc
] = addr_mask
;
2387 any_addr_mask
|= addr_mask
;
2390 reg_addr
[m
].addr_mask
[RELOAD_REG_ANY
] = any_addr_mask
;
2395 /* Initialize the various global tables that are based on register size. */
2397 rs6000_init_hard_regno_mode_ok (bool global_init_p
)
2403 /* Precalculate REGNO_REG_CLASS. */
2404 rs6000_regno_regclass
[0] = GENERAL_REGS
;
2405 for (r
= 1; r
< 32; ++r
)
2406 rs6000_regno_regclass
[r
] = BASE_REGS
;
2408 for (r
= 32; r
< 64; ++r
)
2409 rs6000_regno_regclass
[r
] = FLOAT_REGS
;
2411 for (r
= 64; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2412 rs6000_regno_regclass
[r
] = NO_REGS
;
2414 for (r
= FIRST_ALTIVEC_REGNO
; r
<= LAST_ALTIVEC_REGNO
; ++r
)
2415 rs6000_regno_regclass
[r
] = ALTIVEC_REGS
;
2417 rs6000_regno_regclass
[CR0_REGNO
] = CR0_REGS
;
2418 for (r
= CR1_REGNO
; r
<= CR7_REGNO
; ++r
)
2419 rs6000_regno_regclass
[r
] = CR_REGS
;
2421 rs6000_regno_regclass
[LR_REGNO
] = LINK_REGS
;
2422 rs6000_regno_regclass
[CTR_REGNO
] = CTR_REGS
;
2423 rs6000_regno_regclass
[CA_REGNO
] = CA_REGS
;
2424 rs6000_regno_regclass
[VRSAVE_REGNO
] = VRSAVE_REGS
;
2425 rs6000_regno_regclass
[VSCR_REGNO
] = VRSAVE_REGS
;
2426 rs6000_regno_regclass
[SPE_ACC_REGNO
] = SPE_ACC_REGS
;
2427 rs6000_regno_regclass
[SPEFSCR_REGNO
] = SPEFSCR_REGS
;
2428 rs6000_regno_regclass
[TFHAR_REGNO
] = SPR_REGS
;
2429 rs6000_regno_regclass
[TFIAR_REGNO
] = SPR_REGS
;
2430 rs6000_regno_regclass
[TEXASR_REGNO
] = SPR_REGS
;
2431 rs6000_regno_regclass
[ARG_POINTER_REGNUM
] = BASE_REGS
;
2432 rs6000_regno_regclass
[FRAME_POINTER_REGNUM
] = BASE_REGS
;
2434 /* Precalculate register class to simpler reload register class. We don't
2435 need all of the register classes that are combinations of different
2436 classes, just the simple ones that have constraint letters. */
2437 for (c
= 0; c
< N_REG_CLASSES
; c
++)
2438 reg_class_to_reg_type
[c
] = NO_REG_TYPE
;
2440 reg_class_to_reg_type
[(int)GENERAL_REGS
] = GPR_REG_TYPE
;
2441 reg_class_to_reg_type
[(int)BASE_REGS
] = GPR_REG_TYPE
;
2442 reg_class_to_reg_type
[(int)VSX_REGS
] = VSX_REG_TYPE
;
2443 reg_class_to_reg_type
[(int)VRSAVE_REGS
] = SPR_REG_TYPE
;
2444 reg_class_to_reg_type
[(int)VSCR_REGS
] = SPR_REG_TYPE
;
2445 reg_class_to_reg_type
[(int)LINK_REGS
] = SPR_REG_TYPE
;
2446 reg_class_to_reg_type
[(int)CTR_REGS
] = SPR_REG_TYPE
;
2447 reg_class_to_reg_type
[(int)LINK_OR_CTR_REGS
] = SPR_REG_TYPE
;
2448 reg_class_to_reg_type
[(int)CR_REGS
] = CR_REG_TYPE
;
2449 reg_class_to_reg_type
[(int)CR0_REGS
] = CR_REG_TYPE
;
2450 reg_class_to_reg_type
[(int)SPE_ACC_REGS
] = SPE_ACC_TYPE
;
2451 reg_class_to_reg_type
[(int)SPEFSCR_REGS
] = SPEFSCR_REG_TYPE
;
2455 reg_class_to_reg_type
[(int)FLOAT_REGS
] = VSX_REG_TYPE
;
2456 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = VSX_REG_TYPE
;
2460 reg_class_to_reg_type
[(int)FLOAT_REGS
] = FPR_REG_TYPE
;
2461 reg_class_to_reg_type
[(int)ALTIVEC_REGS
] = ALTIVEC_REG_TYPE
;
2464 /* Precalculate the valid memory formats as well as the vector information,
2465 this must be set up before the rs6000_hard_regno_nregs_internal calls
2467 gcc_assert ((int)VECTOR_NONE
== 0);
2468 memset ((void *) &rs6000_vector_unit
[0], '\0', sizeof (rs6000_vector_unit
));
2469 memset ((void *) &rs6000_vector_mem
[0], '\0', sizeof (rs6000_vector_unit
));
2471 gcc_assert ((int)CODE_FOR_nothing
== 0);
2472 memset ((void *) ®_addr
[0], '\0', sizeof (reg_addr
));
2474 gcc_assert ((int)NO_REGS
== 0);
2475 memset ((void *) &rs6000_constraints
[0], '\0', sizeof (rs6000_constraints
));
2477 /* The VSX hardware allows native alignment for vectors, but control whether the compiler
2478 believes it can use native alignment or still uses 128-bit alignment. */
2479 if (TARGET_VSX
&& !TARGET_VSX_ALIGN_128
)
2490 /* V2DF mode, VSX only. */
2493 rs6000_vector_unit
[V2DFmode
] = VECTOR_VSX
;
2494 rs6000_vector_mem
[V2DFmode
] = VECTOR_VSX
;
2495 rs6000_vector_align
[V2DFmode
] = align64
;
2498 /* V4SF mode, either VSX or Altivec. */
2501 rs6000_vector_unit
[V4SFmode
] = VECTOR_VSX
;
2502 rs6000_vector_mem
[V4SFmode
] = VECTOR_VSX
;
2503 rs6000_vector_align
[V4SFmode
] = align32
;
2505 else if (TARGET_ALTIVEC
)
2507 rs6000_vector_unit
[V4SFmode
] = VECTOR_ALTIVEC
;
2508 rs6000_vector_mem
[V4SFmode
] = VECTOR_ALTIVEC
;
2509 rs6000_vector_align
[V4SFmode
] = align32
;
2512 /* V16QImode, V8HImode, V4SImode are Altivec only, but possibly do VSX loads
2516 rs6000_vector_unit
[V4SImode
] = VECTOR_ALTIVEC
;
2517 rs6000_vector_unit
[V8HImode
] = VECTOR_ALTIVEC
;
2518 rs6000_vector_unit
[V16QImode
] = VECTOR_ALTIVEC
;
2519 rs6000_vector_align
[V4SImode
] = align32
;
2520 rs6000_vector_align
[V8HImode
] = align32
;
2521 rs6000_vector_align
[V16QImode
] = align32
;
2525 rs6000_vector_mem
[V4SImode
] = VECTOR_VSX
;
2526 rs6000_vector_mem
[V8HImode
] = VECTOR_VSX
;
2527 rs6000_vector_mem
[V16QImode
] = VECTOR_VSX
;
2531 rs6000_vector_mem
[V4SImode
] = VECTOR_ALTIVEC
;
2532 rs6000_vector_mem
[V8HImode
] = VECTOR_ALTIVEC
;
2533 rs6000_vector_mem
[V16QImode
] = VECTOR_ALTIVEC
;
2537 /* V2DImode, full mode depends on ISA 2.07 vector mode. Allow under VSX to
2538 do insert/splat/extract. Altivec doesn't have 64-bit integer support. */
2541 rs6000_vector_mem
[V2DImode
] = VECTOR_VSX
;
2542 rs6000_vector_unit
[V2DImode
]
2543 = (TARGET_P8_VECTOR
) ? VECTOR_P8_VECTOR
: VECTOR_NONE
;
2544 rs6000_vector_align
[V2DImode
] = align64
;
2547 /* DFmode, see if we want to use the VSX unit. */
2548 if (TARGET_VSX
&& TARGET_VSX_SCALAR_DOUBLE
)
2550 rs6000_vector_unit
[DFmode
] = VECTOR_VSX
;
2551 rs6000_vector_mem
[DFmode
]
2552 = (TARGET_UPPER_REGS_DF
? VECTOR_VSX
: VECTOR_NONE
);
2553 rs6000_vector_align
[DFmode
] = align64
;
2556 /* Allow TImode in VSX register and set the VSX memory macros. */
2557 if (TARGET_VSX
&& TARGET_VSX_TIMODE
)
2559 rs6000_vector_mem
[TImode
] = VECTOR_VSX
;
2560 rs6000_vector_align
[TImode
] = align64
;
2563 /* TODO add SPE and paired floating point vector support. */
2565 /* Register class constraints for the constraints that depend on compile
2566 switches. When the VSX code was added, different constraints were added
2567 based on the type (DFmode, V2DFmode, V4SFmode). For the vector types, all
2568 of the VSX registers are used. The register classes for scalar floating
2569 point types is set, based on whether we allow that type into the upper
2570 (Altivec) registers. GCC has register classes to target the Altivec
2571 registers for load/store operations, to select using a VSX memory
2572 operation instead of the traditional floating point operation. The
2575 d - Register class to use with traditional DFmode instructions.
2576 f - Register class to use with traditional SFmode instructions.
2577 v - Altivec register.
2578 wa - Any VSX register.
2579 wd - Preferred register class for V2DFmode.
2580 wf - Preferred register class for V4SFmode.
2581 wg - Float register for power6x move insns.
2582 wl - Float register if we can do 32-bit signed int loads.
2583 wm - VSX register for ISA 2.07 direct move operations.
2584 wr - GPR if 64-bit mode is permitted.
2585 ws - Register class to do ISA 2.06 DF operations.
2586 wu - Altivec register for ISA 2.07 VSX SF/SI load/stores.
2587 wv - Altivec register for ISA 2.06 VSX DF/DI load/stores.
2588 wt - VSX register for TImode in VSX registers.
2589 ww - Register class to do SF conversions in with VSX operations.
2590 wx - Float register if we can do 32-bit int stores.
2591 wy - Register class to do ISA 2.07 SF operations.
2592 wz - Float register if we can do 32-bit unsigned int loads. */
2594 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
2595 rs6000_constraints
[RS6000_CONSTRAINT_f
] = FLOAT_REGS
;
2597 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
2598 rs6000_constraints
[RS6000_CONSTRAINT_d
] = FLOAT_REGS
;
2602 rs6000_constraints
[RS6000_CONSTRAINT_wa
] = VSX_REGS
;
2603 rs6000_constraints
[RS6000_CONSTRAINT_wd
] = VSX_REGS
;
2604 rs6000_constraints
[RS6000_CONSTRAINT_wf
] = VSX_REGS
;
2606 if (TARGET_VSX_TIMODE
)
2607 rs6000_constraints
[RS6000_CONSTRAINT_wt
] = VSX_REGS
;
2609 if (TARGET_UPPER_REGS_DF
)
2611 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = VSX_REGS
;
2612 rs6000_constraints
[RS6000_CONSTRAINT_wv
] = ALTIVEC_REGS
;
2615 rs6000_constraints
[RS6000_CONSTRAINT_ws
] = FLOAT_REGS
;
2618 /* Add conditional constraints based on various options, to allow us to
2619 collapse multiple insn patterns. */
2621 rs6000_constraints
[RS6000_CONSTRAINT_v
] = ALTIVEC_REGS
;
2624 rs6000_constraints
[RS6000_CONSTRAINT_wg
] = FLOAT_REGS
;
2627 rs6000_constraints
[RS6000_CONSTRAINT_wl
] = FLOAT_REGS
;
2629 if (TARGET_DIRECT_MOVE
)
2630 rs6000_constraints
[RS6000_CONSTRAINT_wm
] = VSX_REGS
;
2632 if (TARGET_POWERPC64
)
2633 rs6000_constraints
[RS6000_CONSTRAINT_wr
] = GENERAL_REGS
;
2635 if (TARGET_P8_VECTOR
&& TARGET_UPPER_REGS_SF
)
2637 rs6000_constraints
[RS6000_CONSTRAINT_wu
] = ALTIVEC_REGS
;
2638 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = VSX_REGS
;
2639 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = VSX_REGS
;
2641 else if (TARGET_P8_VECTOR
)
2643 rs6000_constraints
[RS6000_CONSTRAINT_wy
] = FLOAT_REGS
;
2644 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2646 else if (TARGET_VSX
)
2647 rs6000_constraints
[RS6000_CONSTRAINT_ww
] = FLOAT_REGS
;
2650 rs6000_constraints
[RS6000_CONSTRAINT_wx
] = FLOAT_REGS
;
2653 rs6000_constraints
[RS6000_CONSTRAINT_wz
] = FLOAT_REGS
;
2655 /* Set up the reload helper and direct move functions. */
2656 if (TARGET_VSX
|| TARGET_ALTIVEC
)
2660 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_di_store
;
2661 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_di_load
;
2662 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_di_store
;
2663 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_di_load
;
2664 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_di_store
;
2665 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_di_load
;
2666 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_di_store
;
2667 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_di_load
;
2668 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_di_store
;
2669 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_di_load
;
2670 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_di_store
;
2671 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_di_load
;
2672 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2674 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_di_store
;
2675 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_di_load
;
2676 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_di_store
;
2677 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_di_load
;
2679 if (TARGET_P8_VECTOR
)
2681 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_di_store
;
2682 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_di_load
;
2683 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_di_store
;
2684 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_di_load
;
2686 if (TARGET_VSX_TIMODE
)
2688 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_di_store
;
2689 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_di_load
;
2691 if (TARGET_DIRECT_MOVE
)
2693 if (TARGET_POWERPC64
)
2695 reg_addr
[TImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxti
;
2696 reg_addr
[V2DFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2df
;
2697 reg_addr
[V2DImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv2di
;
2698 reg_addr
[V4SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4sf
;
2699 reg_addr
[V4SImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv4si
;
2700 reg_addr
[V8HImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv8hi
;
2701 reg_addr
[V16QImode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxv16qi
;
2702 reg_addr
[SFmode
].reload_gpr_vsx
= CODE_FOR_reload_gpr_from_vsxsf
;
2704 reg_addr
[TImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprti
;
2705 reg_addr
[V2DFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2df
;
2706 reg_addr
[V2DImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv2di
;
2707 reg_addr
[V4SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4sf
;
2708 reg_addr
[V4SImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv4si
;
2709 reg_addr
[V8HImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv8hi
;
2710 reg_addr
[V16QImode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprv16qi
;
2711 reg_addr
[SFmode
].reload_vsx_gpr
= CODE_FOR_reload_vsx_from_gprsf
;
2715 reg_addr
[DImode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdi
;
2716 reg_addr
[DDmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdd
;
2717 reg_addr
[DFmode
].reload_fpr_gpr
= CODE_FOR_reload_fpr_from_gprdf
;
2723 reg_addr
[V16QImode
].reload_store
= CODE_FOR_reload_v16qi_si_store
;
2724 reg_addr
[V16QImode
].reload_load
= CODE_FOR_reload_v16qi_si_load
;
2725 reg_addr
[V8HImode
].reload_store
= CODE_FOR_reload_v8hi_si_store
;
2726 reg_addr
[V8HImode
].reload_load
= CODE_FOR_reload_v8hi_si_load
;
2727 reg_addr
[V4SImode
].reload_store
= CODE_FOR_reload_v4si_si_store
;
2728 reg_addr
[V4SImode
].reload_load
= CODE_FOR_reload_v4si_si_load
;
2729 reg_addr
[V2DImode
].reload_store
= CODE_FOR_reload_v2di_si_store
;
2730 reg_addr
[V2DImode
].reload_load
= CODE_FOR_reload_v2di_si_load
;
2731 reg_addr
[V4SFmode
].reload_store
= CODE_FOR_reload_v4sf_si_store
;
2732 reg_addr
[V4SFmode
].reload_load
= CODE_FOR_reload_v4sf_si_load
;
2733 reg_addr
[V2DFmode
].reload_store
= CODE_FOR_reload_v2df_si_store
;
2734 reg_addr
[V2DFmode
].reload_load
= CODE_FOR_reload_v2df_si_load
;
2735 if (TARGET_VSX
&& TARGET_UPPER_REGS_DF
)
2737 reg_addr
[DFmode
].reload_store
= CODE_FOR_reload_df_si_store
;
2738 reg_addr
[DFmode
].reload_load
= CODE_FOR_reload_df_si_load
;
2739 reg_addr
[DDmode
].reload_store
= CODE_FOR_reload_dd_si_store
;
2740 reg_addr
[DDmode
].reload_load
= CODE_FOR_reload_dd_si_load
;
2742 if (TARGET_P8_VECTOR
)
2744 reg_addr
[SFmode
].reload_store
= CODE_FOR_reload_sf_si_store
;
2745 reg_addr
[SFmode
].reload_load
= CODE_FOR_reload_sf_si_load
;
2746 reg_addr
[SDmode
].reload_store
= CODE_FOR_reload_sd_si_store
;
2747 reg_addr
[SDmode
].reload_load
= CODE_FOR_reload_sd_si_load
;
2749 if (TARGET_VSX_TIMODE
)
2751 reg_addr
[TImode
].reload_store
= CODE_FOR_reload_ti_si_store
;
2752 reg_addr
[TImode
].reload_load
= CODE_FOR_reload_ti_si_load
;
2757 /* Precalculate HARD_REGNO_NREGS. */
2758 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2759 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2760 rs6000_hard_regno_nregs
[m
][r
]
2761 = rs6000_hard_regno_nregs_internal (r
, (enum machine_mode
)m
);
2763 /* Precalculate HARD_REGNO_MODE_OK. */
2764 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; ++r
)
2765 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2766 if (rs6000_hard_regno_mode_ok (r
, (enum machine_mode
)m
))
2767 rs6000_hard_regno_mode_ok_p
[m
][r
] = true;
2769 /* Precalculate CLASS_MAX_NREGS sizes. */
2770 for (c
= 0; c
< LIM_REG_CLASSES
; ++c
)
2774 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
))
2775 reg_size
= UNITS_PER_VSX_WORD
;
2777 else if (c
== ALTIVEC_REGS
)
2778 reg_size
= UNITS_PER_ALTIVEC_WORD
;
2780 else if (c
== FLOAT_REGS
)
2781 reg_size
= UNITS_PER_FP_WORD
;
2784 reg_size
= UNITS_PER_WORD
;
2786 for (m
= 0; m
< NUM_MACHINE_MODES
; ++m
)
2788 int reg_size2
= reg_size
;
2790 /* TFmode/TDmode always takes 2 registers, even in VSX. */
2791 if (TARGET_VSX
&& VSX_REG_CLASS_P (c
)
2792 && (m
== TDmode
|| m
== TFmode
))
2793 reg_size2
= UNITS_PER_FP_WORD
;
2795 rs6000_class_max_nregs
[m
][c
]
2796 = (GET_MODE_SIZE (m
) + reg_size2
- 1) / reg_size2
;
2800 if (TARGET_E500_DOUBLE
)
2801 rs6000_class_max_nregs
[DFmode
][GENERAL_REGS
] = 1;
2803 /* Calculate which modes to automatically generate code to use a the
2804 reciprocal divide and square root instructions. In the future, possibly
2805 automatically generate the instructions even if the user did not specify
2806 -mrecip. The older machines double precision reciprocal sqrt estimate is
2807 not accurate enough. */
2808 memset (rs6000_recip_bits
, 0, sizeof (rs6000_recip_bits
));
2810 rs6000_recip_bits
[SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2812 rs6000_recip_bits
[DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2813 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2814 rs6000_recip_bits
[V4SFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2815 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2816 rs6000_recip_bits
[V2DFmode
] = RS6000_RECIP_MASK_HAVE_RE
;
2818 if (TARGET_FRSQRTES
)
2819 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2821 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2822 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
))
2823 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2824 if (VECTOR_UNIT_VSX_P (V2DFmode
))
2825 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_HAVE_RSQRTE
;
2827 if (rs6000_recip_control
)
2829 if (!flag_finite_math_only
)
2830 warning (0, "-mrecip requires -ffinite-math or -ffast-math");
2831 if (flag_trapping_math
)
2832 warning (0, "-mrecip requires -fno-trapping-math or -ffast-math");
2833 if (!flag_reciprocal_math
)
2834 warning (0, "-mrecip requires -freciprocal-math or -ffast-math");
2835 if (flag_finite_math_only
&& !flag_trapping_math
&& flag_reciprocal_math
)
2837 if (RS6000_RECIP_HAVE_RE_P (SFmode
)
2838 && (rs6000_recip_control
& RECIP_SF_DIV
) != 0)
2839 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2841 if (RS6000_RECIP_HAVE_RE_P (DFmode
)
2842 && (rs6000_recip_control
& RECIP_DF_DIV
) != 0)
2843 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2845 if (RS6000_RECIP_HAVE_RE_P (V4SFmode
)
2846 && (rs6000_recip_control
& RECIP_V4SF_DIV
) != 0)
2847 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2849 if (RS6000_RECIP_HAVE_RE_P (V2DFmode
)
2850 && (rs6000_recip_control
& RECIP_V2DF_DIV
) != 0)
2851 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RE
;
2853 if (RS6000_RECIP_HAVE_RSQRTE_P (SFmode
)
2854 && (rs6000_recip_control
& RECIP_SF_RSQRT
) != 0)
2855 rs6000_recip_bits
[SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2857 if (RS6000_RECIP_HAVE_RSQRTE_P (DFmode
)
2858 && (rs6000_recip_control
& RECIP_DF_RSQRT
) != 0)
2859 rs6000_recip_bits
[DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2861 if (RS6000_RECIP_HAVE_RSQRTE_P (V4SFmode
)
2862 && (rs6000_recip_control
& RECIP_V4SF_RSQRT
) != 0)
2863 rs6000_recip_bits
[V4SFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2865 if (RS6000_RECIP_HAVE_RSQRTE_P (V2DFmode
)
2866 && (rs6000_recip_control
& RECIP_V2DF_RSQRT
) != 0)
2867 rs6000_recip_bits
[V2DFmode
] |= RS6000_RECIP_MASK_AUTO_RSQRTE
;
2871 /* Update the addr mask bits in reg_addr to help secondary reload and go if
2872 legitimate address support to figure out the appropriate addressing to
2874 rs6000_setup_reg_addr_masks ();
2876 if (global_init_p
|| TARGET_DEBUG_TARGET
)
2878 if (TARGET_DEBUG_REG
)
2879 rs6000_debug_reg_global ();
2881 if (TARGET_DEBUG_COST
|| TARGET_DEBUG_REG
)
2883 "SImode variable mult cost = %d\n"
2884 "SImode constant mult cost = %d\n"
2885 "SImode short constant mult cost = %d\n"
2886 "DImode multipliciation cost = %d\n"
2887 "SImode division cost = %d\n"
2888 "DImode division cost = %d\n"
2889 "Simple fp operation cost = %d\n"
2890 "DFmode multiplication cost = %d\n"
2891 "SFmode division cost = %d\n"
2892 "DFmode division cost = %d\n"
2893 "cache line size = %d\n"
2894 "l1 cache size = %d\n"
2895 "l2 cache size = %d\n"
2896 "simultaneous prefetches = %d\n"
2899 rs6000_cost
->mulsi_const
,
2900 rs6000_cost
->mulsi_const9
,
2908 rs6000_cost
->cache_line_size
,
2909 rs6000_cost
->l1_cache_size
,
2910 rs6000_cost
->l2_cache_size
,
2911 rs6000_cost
->simultaneous_prefetches
);
2916 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
2919 darwin_rs6000_override_options (void)
2921 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
2923 rs6000_altivec_abi
= 1;
2924 TARGET_ALTIVEC_VRSAVE
= 1;
2925 rs6000_current_abi
= ABI_DARWIN
;
2927 if (DEFAULT_ABI
== ABI_DARWIN
2929 darwin_one_byte_bool
= 1;
2931 if (TARGET_64BIT
&& ! TARGET_POWERPC64
)
2933 rs6000_isa_flags
|= OPTION_MASK_POWERPC64
;
2934 warning (0, "-m64 requires PowerPC64 architecture, enabling");
2938 rs6000_default_long_calls
= 1;
2939 rs6000_isa_flags
|= OPTION_MASK_SOFT_FLOAT
;
2942 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
2944 if (!flag_mkernel
&& !flag_apple_kext
2946 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
))
2947 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2949 /* Unless the user (not the configurer) has explicitly overridden
2950 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
2951 G4 unless targeting the kernel. */
2954 && strverscmp (darwin_macosx_version_min
, "10.5") >= 0
2955 && ! (rs6000_isa_flags_explicit
& OPTION_MASK_ALTIVEC
)
2956 && ! global_options_set
.x_rs6000_cpu_index
)
2958 rs6000_isa_flags
|= OPTION_MASK_ALTIVEC
;
2963 /* If not otherwise specified by a target, make 'long double' equivalent to
2966 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
2967 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
2970 /* Return the builtin mask of the various options used that could affect which
2971 builtins were used. In the past we used target_flags, but we've run out of
2972 bits, and some options like SPE and PAIRED are no longer in
2976 rs6000_builtin_mask_calculate (void)
2978 return (((TARGET_ALTIVEC
) ? RS6000_BTM_ALTIVEC
: 0)
2979 | ((TARGET_VSX
) ? RS6000_BTM_VSX
: 0)
2980 | ((TARGET_SPE
) ? RS6000_BTM_SPE
: 0)
2981 | ((TARGET_PAIRED_FLOAT
) ? RS6000_BTM_PAIRED
: 0)
2982 | ((TARGET_FRE
) ? RS6000_BTM_FRE
: 0)
2983 | ((TARGET_FRES
) ? RS6000_BTM_FRES
: 0)
2984 | ((TARGET_FRSQRTE
) ? RS6000_BTM_FRSQRTE
: 0)
2985 | ((TARGET_FRSQRTES
) ? RS6000_BTM_FRSQRTES
: 0)
2986 | ((TARGET_POPCNTD
) ? RS6000_BTM_POPCNTD
: 0)
2987 | ((rs6000_cpu
== PROCESSOR_CELL
) ? RS6000_BTM_CELL
: 0)
2988 | ((TARGET_P8_VECTOR
) ? RS6000_BTM_P8_VECTOR
: 0)
2989 | ((TARGET_CRYPTO
) ? RS6000_BTM_CRYPTO
: 0)
2990 | ((TARGET_HTM
) ? RS6000_BTM_HTM
: 0));
2993 /* Override command line options. Mostly we process the processor type and
2994 sometimes adjust other TARGET_ options. */
2997 rs6000_option_override_internal (bool global_init_p
)
3000 bool have_cpu
= false;
3002 /* The default cpu requested at configure time, if any. */
3003 const char *implicit_cpu
= OPTION_TARGET_CPU_DEFAULT
;
3005 HOST_WIDE_INT set_masks
;
3008 struct cl_target_option
*main_target_opt
3009 = ((global_init_p
|| target_option_default_node
== NULL
)
3010 ? NULL
: TREE_TARGET_OPTION (target_option_default_node
));
3012 /* Remember the explicit arguments. */
3014 rs6000_isa_flags_explicit
= global_options_set
.x_rs6000_isa_flags
;
3016 /* On 64-bit Darwin, power alignment is ABI-incompatible with some C
3017 library functions, so warn about it. The flag may be useful for
3018 performance studies from time to time though, so don't disable it
3020 if (global_options_set
.x_rs6000_alignment_flags
3021 && rs6000_alignment_flags
== MASK_ALIGN_POWER
3022 && DEFAULT_ABI
== ABI_DARWIN
3024 warning (0, "-malign-power is not supported for 64-bit Darwin;"
3025 " it is incompatible with the installed C and C++ libraries");
3027 /* Numerous experiment shows that IRA based loop pressure
3028 calculation works better for RTL loop invariant motion on targets
3029 with enough (>= 32) registers. It is an expensive optimization.
3030 So it is on only for peak performance. */
3031 if (optimize
>= 3 && global_init_p
)
3032 flag_ira_loop_pressure
= 1;
3034 /* Set the pointer size. */
3037 rs6000_pmode
= (int)DImode
;
3038 rs6000_pointer_size
= 64;
3042 rs6000_pmode
= (int)SImode
;
3043 rs6000_pointer_size
= 32;
3046 /* Some OSs don't support saving the high part of 64-bit registers on context
3047 switch. Other OSs don't support saving Altivec registers. On those OSs,
3048 we don't touch the OPTION_MASK_POWERPC64 or OPTION_MASK_ALTIVEC settings;
3049 if the user wants either, the user must explicitly specify them and we
3050 won't interfere with the user's specification. */
3052 set_masks
= POWERPC_MASKS
;
3053 #ifdef OS_MISSING_POWERPC64
3054 if (OS_MISSING_POWERPC64
)
3055 set_masks
&= ~OPTION_MASK_POWERPC64
;
3057 #ifdef OS_MISSING_ALTIVEC
3058 if (OS_MISSING_ALTIVEC
)
3059 set_masks
&= ~(OPTION_MASK_ALTIVEC
| OPTION_MASK_VSX
);
3062 /* Don't override by the processor default if given explicitly. */
3063 set_masks
&= ~rs6000_isa_flags_explicit
;
3065 /* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
3066 the cpu in a target attribute or pragma, but did not specify a tuning
3067 option, use the cpu for the tuning option rather than the option specified
3068 with -mtune on the command line. Process a '--with-cpu' configuration
3069 request as an implicit --cpu. */
3070 if (rs6000_cpu_index
>= 0)
3072 cpu_index
= rs6000_cpu_index
;
3075 else if (main_target_opt
!= NULL
&& main_target_opt
->x_rs6000_cpu_index
>= 0)
3077 rs6000_cpu_index
= cpu_index
= main_target_opt
->x_rs6000_cpu_index
;
3080 else if (implicit_cpu
)
3082 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (implicit_cpu
);
3087 const char *default_cpu
= (TARGET_POWERPC64
? "powerpc64" : "powerpc");
3088 rs6000_cpu_index
= cpu_index
= rs6000_cpu_name_lookup (default_cpu
);
3092 gcc_assert (cpu_index
>= 0);
3094 /* If we have a cpu, either through an explicit -mcpu=<xxx> or if the
3095 compiler was configured with --with-cpu=<xxx>, replace all of the ISA bits
3096 with those from the cpu, except for options that were explicitly set. If
3097 we don't have a cpu, do not override the target bits set in
3101 rs6000_isa_flags
&= ~set_masks
;
3102 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3106 rs6000_isa_flags
|= (processor_target_table
[cpu_index
].target_enable
3107 & ~rs6000_isa_flags_explicit
);
3109 /* If no -mcpu=<xxx>, inherit any default options that were cleared via
3110 POWERPC_MASKS. Originally, TARGET_DEFAULT was used to initialize
3111 target_flags via the TARGET_DEFAULT_TARGET_FLAGS hook. When we switched
3112 to using rs6000_isa_flags, we need to do the initialization here. */
3114 rs6000_isa_flags
|= (TARGET_DEFAULT
& ~rs6000_isa_flags_explicit
);
3116 if (rs6000_tune_index
>= 0)
3117 tune_index
= rs6000_tune_index
;
3119 rs6000_tune_index
= tune_index
= cpu_index
;
3123 enum processor_type tune_proc
3124 = (TARGET_POWERPC64
? PROCESSOR_DEFAULT64
: PROCESSOR_DEFAULT
);
3127 for (i
= 0; i
< ARRAY_SIZE (processor_target_table
); i
++)
3128 if (processor_target_table
[i
].processor
== tune_proc
)
3130 rs6000_tune_index
= tune_index
= i
;
3135 gcc_assert (tune_index
>= 0);
3136 rs6000_cpu
= processor_target_table
[tune_index
].processor
;
3138 /* Pick defaults for SPE related control flags. Do this early to make sure
3139 that the TARGET_ macros are representative ASAP. */
3141 int spe_capable_cpu
=
3142 (rs6000_cpu
== PROCESSOR_PPC8540
3143 || rs6000_cpu
== PROCESSOR_PPC8548
);
3145 if (!global_options_set
.x_rs6000_spe_abi
)
3146 rs6000_spe_abi
= spe_capable_cpu
;
3148 if (!global_options_set
.x_rs6000_spe
)
3149 rs6000_spe
= spe_capable_cpu
;
3151 if (!global_options_set
.x_rs6000_float_gprs
)
3153 (rs6000_cpu
== PROCESSOR_PPC8540
? 1
3154 : rs6000_cpu
== PROCESSOR_PPC8548
? 2
3158 if (global_options_set
.x_rs6000_spe_abi
3161 error ("not configured for SPE ABI");
3163 if (global_options_set
.x_rs6000_spe
3166 error ("not configured for SPE instruction set");
3168 if (main_target_opt
!= NULL
3169 && ((main_target_opt
->x_rs6000_spe_abi
!= rs6000_spe_abi
)
3170 || (main_target_opt
->x_rs6000_spe
!= rs6000_spe
)
3171 || (main_target_opt
->x_rs6000_float_gprs
!= rs6000_float_gprs
)))
3172 error ("target attribute or pragma changes SPE ABI");
3174 if (rs6000_cpu
== PROCESSOR_PPCE300C2
|| rs6000_cpu
== PROCESSOR_PPCE300C3
3175 || rs6000_cpu
== PROCESSOR_PPCE500MC
|| rs6000_cpu
== PROCESSOR_PPCE500MC64
3176 || rs6000_cpu
== PROCESSOR_PPCE5500
)
3179 error ("AltiVec not supported in this target");
3181 error ("SPE not supported in this target");
3183 if (rs6000_cpu
== PROCESSOR_PPCE6500
)
3186 error ("SPE not supported in this target");
3189 /* Disable Cell microcode if we are optimizing for the Cell
3190 and not optimizing for size. */
3191 if (rs6000_gen_cell_microcode
== -1)
3192 rs6000_gen_cell_microcode
= !(rs6000_cpu
== PROCESSOR_CELL
3195 /* If we are optimizing big endian systems for space and it's OK to
3196 use instructions that would be microcoded on the Cell, use the
3197 load/store multiple and string instructions. */
3198 if (BYTES_BIG_ENDIAN
&& optimize_size
&& rs6000_gen_cell_microcode
)
3199 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& (OPTION_MASK_MULTIPLE
3200 | OPTION_MASK_STRING
);
3202 /* Don't allow -mmultiple or -mstring on little endian systems
3203 unless the cpu is a 750, because the hardware doesn't support the
3204 instructions used in little endian mode, and causes an alignment
3205 trap. The 750 does not cause an alignment trap (except when the
3206 target is unaligned). */
3208 if (!BYTES_BIG_ENDIAN
&& rs6000_cpu
!= PROCESSOR_PPC750
)
3210 if (TARGET_MULTIPLE
)
3212 rs6000_isa_flags
&= ~OPTION_MASK_MULTIPLE
;
3213 if ((rs6000_isa_flags_explicit
& OPTION_MASK_MULTIPLE
) != 0)
3214 warning (0, "-mmultiple is not supported on little endian systems");
3219 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3220 if ((rs6000_isa_flags_explicit
& OPTION_MASK_STRING
) != 0)
3221 warning (0, "-mstring is not supported on little endian systems");
3225 /* If little-endian, default to -mstrict-align on older processors.
3226 Testing for htm matches power8 and later. */
3227 if (!BYTES_BIG_ENDIAN
3228 && !(processor_target_table
[tune_index
].target_enable
& OPTION_MASK_HTM
))
3229 rs6000_isa_flags
|= ~rs6000_isa_flags_explicit
& OPTION_MASK_STRICT_ALIGN
;
3231 /* Add some warnings for VSX. */
3234 const char *msg
= NULL
;
3235 if (!TARGET_HARD_FLOAT
|| !TARGET_FPRS
3236 || !TARGET_SINGLE_FLOAT
|| !TARGET_DOUBLE_FLOAT
)
3238 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3239 msg
= N_("-mvsx requires hardware floating point");
3242 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3243 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3246 else if (TARGET_PAIRED_FLOAT
)
3247 msg
= N_("-mvsx and -mpaired are incompatible");
3248 else if (TARGET_AVOID_XFORM
> 0)
3249 msg
= N_("-mvsx needs indexed addressing");
3250 else if (!TARGET_ALTIVEC
&& (rs6000_isa_flags_explicit
3251 & OPTION_MASK_ALTIVEC
))
3253 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX
)
3254 msg
= N_("-mvsx and -mno-altivec are incompatible");
3256 msg
= N_("-mno-altivec disables vsx");
3262 rs6000_isa_flags
&= ~ OPTION_MASK_VSX
;
3263 rs6000_isa_flags_explicit
|= OPTION_MASK_VSX
;
3267 /* If hard-float/altivec/vsx were explicitly turned off then don't allow
3268 the -mcpu setting to enable options that conflict. */
3269 if ((!TARGET_HARD_FLOAT
|| !TARGET_ALTIVEC
|| !TARGET_VSX
)
3270 && (rs6000_isa_flags_explicit
& (OPTION_MASK_SOFT_FLOAT
3271 | OPTION_MASK_ALTIVEC
3272 | OPTION_MASK_VSX
)) != 0)
3273 rs6000_isa_flags
&= ~((OPTION_MASK_P8_VECTOR
| OPTION_MASK_CRYPTO
3274 | OPTION_MASK_DIRECT_MOVE
)
3275 & ~rs6000_isa_flags_explicit
);
3277 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3278 rs6000_print_isa_options (stderr
, 0, "before defaults", rs6000_isa_flags
);
3280 /* For the newer switches (vsx, dfp, etc.) set some of the older options,
3281 unless the user explicitly used the -mno-<option> to disable the code. */
3282 if (TARGET_P8_VECTOR
|| TARGET_DIRECT_MOVE
|| TARGET_CRYPTO
)
3283 rs6000_isa_flags
|= (ISA_2_7_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3284 else if (TARGET_VSX
)
3285 rs6000_isa_flags
|= (ISA_2_6_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3286 else if (TARGET_POPCNTD
)
3287 rs6000_isa_flags
|= (ISA_2_6_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3288 else if (TARGET_DFP
)
3289 rs6000_isa_flags
|= (ISA_2_5_MASKS_SERVER
& ~rs6000_isa_flags_explicit
);
3290 else if (TARGET_CMPB
)
3291 rs6000_isa_flags
|= (ISA_2_5_MASKS_EMBEDDED
& ~rs6000_isa_flags_explicit
);
3292 else if (TARGET_FPRND
)
3293 rs6000_isa_flags
|= (ISA_2_4_MASKS
& ~rs6000_isa_flags_explicit
);
3294 else if (TARGET_POPCNTB
)
3295 rs6000_isa_flags
|= (ISA_2_2_MASKS
& ~rs6000_isa_flags_explicit
);
3296 else if (TARGET_ALTIVEC
)
3297 rs6000_isa_flags
|= (OPTION_MASK_PPC_GFXOPT
& ~rs6000_isa_flags_explicit
);
3299 if (TARGET_CRYPTO
&& !TARGET_ALTIVEC
)
3301 if (rs6000_isa_flags_explicit
& OPTION_MASK_CRYPTO
)
3302 error ("-mcrypto requires -maltivec");
3303 rs6000_isa_flags
&= ~OPTION_MASK_CRYPTO
;
3306 if (TARGET_DIRECT_MOVE
&& !TARGET_VSX
)
3308 if (rs6000_isa_flags_explicit
& OPTION_MASK_DIRECT_MOVE
)
3309 error ("-mdirect-move requires -mvsx");
3310 rs6000_isa_flags
&= ~OPTION_MASK_DIRECT_MOVE
;
3313 if (TARGET_P8_VECTOR
&& !TARGET_ALTIVEC
)
3315 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3316 error ("-mpower8-vector requires -maltivec");
3317 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3320 if (TARGET_P8_VECTOR
&& !TARGET_VSX
)
3322 if (rs6000_isa_flags_explicit
& OPTION_MASK_P8_VECTOR
)
3323 error ("-mpower8-vector requires -mvsx");
3324 rs6000_isa_flags
&= ~OPTION_MASK_P8_VECTOR
;
3327 if (TARGET_VSX_TIMODE
&& !TARGET_VSX
)
3329 if (rs6000_isa_flags_explicit
& OPTION_MASK_VSX_TIMODE
)
3330 error ("-mvsx-timode requires -mvsx");
3331 rs6000_isa_flags
&= ~OPTION_MASK_VSX_TIMODE
;
3334 /* The quad memory instructions only works in 64-bit mode. In 32-bit mode,
3335 silently turn off quad memory mode. */
3336 if (TARGET_QUAD_MEMORY
&& !TARGET_POWERPC64
)
3338 if ((rs6000_isa_flags_explicit
& OPTION_MASK_QUAD_MEMORY
) != 0)
3339 warning (0, N_("-mquad-memory requires 64-bit mode"));
3341 rs6000_isa_flags
&= ~OPTION_MASK_QUAD_MEMORY
;
3344 /* Enable power8 fusion if we are tuning for power8, even if we aren't
3345 generating power8 instructions. */
3346 if (!(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION
))
3347 rs6000_isa_flags
|= (processor_target_table
[tune_index
].target_enable
3348 & OPTION_MASK_P8_FUSION
);
3350 /* Power8 does not fuse sign extended loads with the addis. If we are
3351 optimizing at high levels for speed, convert a sign extended load into a
3352 zero extending load, and an explicit sign extension. */
3353 if (TARGET_P8_FUSION
3354 && !(rs6000_isa_flags_explicit
& OPTION_MASK_P8_FUSION_SIGN
)
3355 && optimize_function_for_speed_p (cfun
)
3357 rs6000_isa_flags
|= OPTION_MASK_P8_FUSION_SIGN
;
3359 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3360 rs6000_print_isa_options (stderr
, 0, "after defaults", rs6000_isa_flags
);
3362 /* E500mc does "better" if we inline more aggressively. Respect the
3363 user's opinion, though. */
3364 if (rs6000_block_move_inline_limit
== 0
3365 && (rs6000_cpu
== PROCESSOR_PPCE500MC
3366 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3367 || rs6000_cpu
== PROCESSOR_PPCE5500
3368 || rs6000_cpu
== PROCESSOR_PPCE6500
))
3369 rs6000_block_move_inline_limit
= 128;
3371 /* store_one_arg depends on expand_block_move to handle at least the
3372 size of reg_parm_stack_space. */
3373 if (rs6000_block_move_inline_limit
< (TARGET_POWERPC64
? 64 : 32))
3374 rs6000_block_move_inline_limit
= (TARGET_POWERPC64
? 64 : 32);
3378 /* If the appropriate debug option is enabled, replace the target hooks
3379 with debug versions that call the real version and then prints
3380 debugging information. */
3381 if (TARGET_DEBUG_COST
)
3383 targetm
.rtx_costs
= rs6000_debug_rtx_costs
;
3384 targetm
.address_cost
= rs6000_debug_address_cost
;
3385 targetm
.sched
.adjust_cost
= rs6000_debug_adjust_cost
;
3388 if (TARGET_DEBUG_ADDR
)
3390 targetm
.legitimate_address_p
= rs6000_debug_legitimate_address_p
;
3391 targetm
.legitimize_address
= rs6000_debug_legitimize_address
;
3392 rs6000_secondary_reload_class_ptr
3393 = rs6000_debug_secondary_reload_class
;
3394 rs6000_secondary_memory_needed_ptr
3395 = rs6000_debug_secondary_memory_needed
;
3396 rs6000_cannot_change_mode_class_ptr
3397 = rs6000_debug_cannot_change_mode_class
;
3398 rs6000_preferred_reload_class_ptr
3399 = rs6000_debug_preferred_reload_class
;
3400 rs6000_legitimize_reload_address_ptr
3401 = rs6000_debug_legitimize_reload_address
;
3402 rs6000_mode_dependent_address_ptr
3403 = rs6000_debug_mode_dependent_address
;
3406 if (rs6000_veclibabi_name
)
3408 if (strcmp (rs6000_veclibabi_name
, "mass") == 0)
3409 rs6000_veclib_handler
= rs6000_builtin_vectorized_libmass
;
3412 error ("unknown vectorization library ABI type (%s) for "
3413 "-mveclibabi= switch", rs6000_veclibabi_name
);
3419 if (!global_options_set
.x_rs6000_long_double_type_size
)
3421 if (main_target_opt
!= NULL
3422 && (main_target_opt
->x_rs6000_long_double_type_size
3423 != RS6000_DEFAULT_LONG_DOUBLE_SIZE
))
3424 error ("target attribute or pragma changes long double size");
3426 rs6000_long_double_type_size
= RS6000_DEFAULT_LONG_DOUBLE_SIZE
;
3429 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
3430 if (!global_options_set
.x_rs6000_ieeequad
)
3431 rs6000_ieeequad
= 1;
3434 /* Disable VSX and Altivec silently if the user switched cpus to power7 in a
3435 target attribute or pragma which automatically enables both options,
3436 unless the altivec ABI was set. This is set by default for 64-bit, but
3438 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3439 rs6000_isa_flags
&= ~((OPTION_MASK_VSX
| OPTION_MASK_ALTIVEC
)
3440 & ~rs6000_isa_flags_explicit
);
3442 /* Enable Altivec ABI for AIX -maltivec. */
3443 if (TARGET_XCOFF
&& (TARGET_ALTIVEC
|| TARGET_VSX
))
3445 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_altivec_abi
)
3446 error ("target attribute or pragma changes AltiVec ABI");
3448 rs6000_altivec_abi
= 1;
3451 /* The AltiVec ABI is the default for PowerPC-64 GNU/Linux. For
3452 PowerPC-32 GNU/Linux, -maltivec implies the AltiVec ABI. It can
3453 be explicitly overridden in either case. */
3456 if (!global_options_set
.x_rs6000_altivec_abi
3457 && (TARGET_64BIT
|| TARGET_ALTIVEC
|| TARGET_VSX
))
3459 if (main_target_opt
!= NULL
&&
3460 !main_target_opt
->x_rs6000_altivec_abi
)
3461 error ("target attribute or pragma changes AltiVec ABI");
3463 rs6000_altivec_abi
= 1;
3467 /* Set the Darwin64 ABI as default for 64-bit Darwin.
3468 So far, the only darwin64 targets are also MACH-O. */
3470 && DEFAULT_ABI
== ABI_DARWIN
3473 if (main_target_opt
!= NULL
&& !main_target_opt
->x_rs6000_darwin64_abi
)
3474 error ("target attribute or pragma changes darwin64 ABI");
3477 rs6000_darwin64_abi
= 1;
3478 /* Default to natural alignment, for better performance. */
3479 rs6000_alignment_flags
= MASK_ALIGN_NATURAL
;
3483 /* Place FP constants in the constant pool instead of TOC
3484 if section anchors enabled. */
3485 if (flag_section_anchors
3486 && !global_options_set
.x_TARGET_NO_FP_IN_TOC
)
3487 TARGET_NO_FP_IN_TOC
= 1;
3489 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3490 rs6000_print_isa_options (stderr
, 0, "before subtarget", rs6000_isa_flags
);
3492 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3493 SUBTARGET_OVERRIDE_OPTIONS
;
3495 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3496 SUBSUBTARGET_OVERRIDE_OPTIONS
;
3498 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
3499 SUB3TARGET_OVERRIDE_OPTIONS
;
3502 if (TARGET_DEBUG_REG
|| TARGET_DEBUG_TARGET
)
3503 rs6000_print_isa_options (stderr
, 0, "after subtarget", rs6000_isa_flags
);
3505 /* For the E500 family of cores, reset the single/double FP flags to let us
3506 check that they remain constant across attributes or pragmas. Also,
3507 clear a possible request for string instructions, not supported and which
3508 we might have silently queried above for -Os.
3510 For other families, clear ISEL in case it was set implicitly.
3515 case PROCESSOR_PPC8540
:
3516 case PROCESSOR_PPC8548
:
3517 case PROCESSOR_PPCE500MC
:
3518 case PROCESSOR_PPCE500MC64
:
3519 case PROCESSOR_PPCE5500
:
3520 case PROCESSOR_PPCE6500
:
3522 rs6000_single_float
= TARGET_E500_SINGLE
|| TARGET_E500_DOUBLE
;
3523 rs6000_double_float
= TARGET_E500_DOUBLE
;
3525 rs6000_isa_flags
&= ~OPTION_MASK_STRING
;
3531 if (have_cpu
&& !(rs6000_isa_flags_explicit
& OPTION_MASK_ISEL
))
3532 rs6000_isa_flags
&= ~OPTION_MASK_ISEL
;
3537 if (main_target_opt
)
3539 if (main_target_opt
->x_rs6000_single_float
!= rs6000_single_float
)
3540 error ("target attribute or pragma changes single precision floating "
3542 if (main_target_opt
->x_rs6000_double_float
!= rs6000_double_float
)
3543 error ("target attribute or pragma changes double precision floating "
3547 /* Detect invalid option combinations with E500. */
3550 rs6000_always_hint
= (rs6000_cpu
!= PROCESSOR_POWER4
3551 && rs6000_cpu
!= PROCESSOR_POWER5
3552 && rs6000_cpu
!= PROCESSOR_POWER6
3553 && rs6000_cpu
!= PROCESSOR_POWER7
3554 && rs6000_cpu
!= PROCESSOR_POWER8
3555 && rs6000_cpu
!= PROCESSOR_PPCA2
3556 && rs6000_cpu
!= PROCESSOR_CELL
3557 && rs6000_cpu
!= PROCESSOR_PPC476
);
3558 rs6000_sched_groups
= (rs6000_cpu
== PROCESSOR_POWER4
3559 || rs6000_cpu
== PROCESSOR_POWER5
3560 || rs6000_cpu
== PROCESSOR_POWER7
3561 || rs6000_cpu
== PROCESSOR_POWER8
);
3562 rs6000_align_branch_targets
= (rs6000_cpu
== PROCESSOR_POWER4
3563 || rs6000_cpu
== PROCESSOR_POWER5
3564 || rs6000_cpu
== PROCESSOR_POWER6
3565 || rs6000_cpu
== PROCESSOR_POWER7
3566 || rs6000_cpu
== PROCESSOR_POWER8
3567 || rs6000_cpu
== PROCESSOR_PPCE500MC
3568 || rs6000_cpu
== PROCESSOR_PPCE500MC64
3569 || rs6000_cpu
== PROCESSOR_PPCE5500
3570 || rs6000_cpu
== PROCESSOR_PPCE6500
);
3572 /* Allow debug switches to override the above settings. These are set to -1
3573 in rs6000.opt to indicate the user hasn't directly set the switch. */
3574 if (TARGET_ALWAYS_HINT
>= 0)
3575 rs6000_always_hint
= TARGET_ALWAYS_HINT
;
3577 if (TARGET_SCHED_GROUPS
>= 0)
3578 rs6000_sched_groups
= TARGET_SCHED_GROUPS
;
3580 if (TARGET_ALIGN_BRANCH_TARGETS
>= 0)
3581 rs6000_align_branch_targets
= TARGET_ALIGN_BRANCH_TARGETS
;
3583 rs6000_sched_restricted_insns_priority
3584 = (rs6000_sched_groups
? 1 : 0);
3586 /* Handle -msched-costly-dep option. */
3587 rs6000_sched_costly_dep
3588 = (rs6000_sched_groups
? true_store_to_load_dep_costly
: no_dep_costly
);
3590 if (rs6000_sched_costly_dep_str
)
3592 if (! strcmp (rs6000_sched_costly_dep_str
, "no"))
3593 rs6000_sched_costly_dep
= no_dep_costly
;
3594 else if (! strcmp (rs6000_sched_costly_dep_str
, "all"))
3595 rs6000_sched_costly_dep
= all_deps_costly
;
3596 else if (! strcmp (rs6000_sched_costly_dep_str
, "true_store_to_load"))
3597 rs6000_sched_costly_dep
= true_store_to_load_dep_costly
;
3598 else if (! strcmp (rs6000_sched_costly_dep_str
, "store_to_load"))
3599 rs6000_sched_costly_dep
= store_to_load_dep_costly
;
3601 rs6000_sched_costly_dep
= ((enum rs6000_dependence_cost
)
3602 atoi (rs6000_sched_costly_dep_str
));
3605 /* Handle -minsert-sched-nops option. */
3606 rs6000_sched_insert_nops
3607 = (rs6000_sched_groups
? sched_finish_regroup_exact
: sched_finish_none
);
3609 if (rs6000_sched_insert_nops_str
)
3611 if (! strcmp (rs6000_sched_insert_nops_str
, "no"))
3612 rs6000_sched_insert_nops
= sched_finish_none
;
3613 else if (! strcmp (rs6000_sched_insert_nops_str
, "pad"))
3614 rs6000_sched_insert_nops
= sched_finish_pad_groups
;
3615 else if (! strcmp (rs6000_sched_insert_nops_str
, "regroup_exact"))
3616 rs6000_sched_insert_nops
= sched_finish_regroup_exact
;
3618 rs6000_sched_insert_nops
= ((enum rs6000_nop_insertion
)
3619 atoi (rs6000_sched_insert_nops_str
));
3624 #ifdef TARGET_REGNAMES
3625 /* If the user desires alternate register names, copy in the
3626 alternate names now. */
3627 if (TARGET_REGNAMES
)
3628 memcpy (rs6000_reg_names
, alt_reg_names
, sizeof (rs6000_reg_names
));
3631 /* Set aix_struct_return last, after the ABI is determined.
3632 If -maix-struct-return or -msvr4-struct-return was explicitly
3633 used, don't override with the ABI default. */
3634 if (!global_options_set
.x_aix_struct_return
)
3635 aix_struct_return
= (DEFAULT_ABI
!= ABI_V4
|| DRAFT_V4_STRUCT_RET
);
3638 /* IBM XL compiler defaults to unsigned bitfields. */
3639 if (TARGET_XL_COMPAT
)
3640 flag_signed_bitfields
= 0;
3643 if (TARGET_LONG_DOUBLE_128
&& !TARGET_IEEEQUAD
)
3644 REAL_MODE_FORMAT (TFmode
) = &ibm_extended_format
;
3647 ASM_GENERATE_INTERNAL_LABEL (toc_label_name
, "LCTOC", 1);
3649 /* We can only guarantee the availability of DI pseudo-ops when
3650 assembling for 64-bit targets. */
3653 targetm
.asm_out
.aligned_op
.di
= NULL
;
3654 targetm
.asm_out
.unaligned_op
.di
= NULL
;
3658 /* Set branch target alignment, if not optimizing for size. */
3661 /* Cell wants to be aligned 8byte for dual issue. Titan wants to be
3662 aligned 8byte to avoid misprediction by the branch predictor. */
3663 if (rs6000_cpu
== PROCESSOR_TITAN
3664 || rs6000_cpu
== PROCESSOR_CELL
)
3666 if (align_functions
<= 0)
3667 align_functions
= 8;
3668 if (align_jumps
<= 0)
3670 if (align_loops
<= 0)
3673 if (rs6000_align_branch_targets
)
3675 if (align_functions
<= 0)
3676 align_functions
= 16;
3677 if (align_jumps
<= 0)
3679 if (align_loops
<= 0)
3681 can_override_loop_align
= 1;
3685 if (align_jumps_max_skip
<= 0)
3686 align_jumps_max_skip
= 15;
3687 if (align_loops_max_skip
<= 0)
3688 align_loops_max_skip
= 15;
3691 /* Arrange to save and restore machine status around nested functions. */
3692 init_machine_status
= rs6000_init_machine_status
;
3694 /* We should always be splitting complex arguments, but we can't break
3695 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
3696 if (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
)
3697 targetm
.calls
.split_complex_arg
= NULL
;
3700 /* Initialize rs6000_cost with the appropriate target costs. */
3702 rs6000_cost
= TARGET_POWERPC64
? &size64_cost
: &size32_cost
;
3706 case PROCESSOR_RS64A
:
3707 rs6000_cost
= &rs64a_cost
;
3710 case PROCESSOR_MPCCORE
:
3711 rs6000_cost
= &mpccore_cost
;
3714 case PROCESSOR_PPC403
:
3715 rs6000_cost
= &ppc403_cost
;
3718 case PROCESSOR_PPC405
:
3719 rs6000_cost
= &ppc405_cost
;
3722 case PROCESSOR_PPC440
:
3723 rs6000_cost
= &ppc440_cost
;
3726 case PROCESSOR_PPC476
:
3727 rs6000_cost
= &ppc476_cost
;
3730 case PROCESSOR_PPC601
:
3731 rs6000_cost
= &ppc601_cost
;
3734 case PROCESSOR_PPC603
:
3735 rs6000_cost
= &ppc603_cost
;
3738 case PROCESSOR_PPC604
:
3739 rs6000_cost
= &ppc604_cost
;
3742 case PROCESSOR_PPC604e
:
3743 rs6000_cost
= &ppc604e_cost
;
3746 case PROCESSOR_PPC620
:
3747 rs6000_cost
= &ppc620_cost
;
3750 case PROCESSOR_PPC630
:
3751 rs6000_cost
= &ppc630_cost
;
3754 case PROCESSOR_CELL
:
3755 rs6000_cost
= &ppccell_cost
;
3758 case PROCESSOR_PPC750
:
3759 case PROCESSOR_PPC7400
:
3760 rs6000_cost
= &ppc750_cost
;
3763 case PROCESSOR_PPC7450
:
3764 rs6000_cost
= &ppc7450_cost
;
3767 case PROCESSOR_PPC8540
:
3768 case PROCESSOR_PPC8548
:
3769 rs6000_cost
= &ppc8540_cost
;
3772 case PROCESSOR_PPCE300C2
:
3773 case PROCESSOR_PPCE300C3
:
3774 rs6000_cost
= &ppce300c2c3_cost
;
3777 case PROCESSOR_PPCE500MC
:
3778 rs6000_cost
= &ppce500mc_cost
;
3781 case PROCESSOR_PPCE500MC64
:
3782 rs6000_cost
= &ppce500mc64_cost
;
3785 case PROCESSOR_PPCE5500
:
3786 rs6000_cost
= &ppce5500_cost
;
3789 case PROCESSOR_PPCE6500
:
3790 rs6000_cost
= &ppce6500_cost
;
3793 case PROCESSOR_TITAN
:
3794 rs6000_cost
= &titan_cost
;
3797 case PROCESSOR_POWER4
:
3798 case PROCESSOR_POWER5
:
3799 rs6000_cost
= &power4_cost
;
3802 case PROCESSOR_POWER6
:
3803 rs6000_cost
= &power6_cost
;
3806 case PROCESSOR_POWER7
:
3807 rs6000_cost
= &power7_cost
;
3810 case PROCESSOR_POWER8
:
3811 rs6000_cost
= &power8_cost
;
3814 case PROCESSOR_PPCA2
:
3815 rs6000_cost
= &ppca2_cost
;
3824 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
3825 rs6000_cost
->simultaneous_prefetches
,
3826 global_options
.x_param_values
,
3827 global_options_set
.x_param_values
);
3828 maybe_set_param_value (PARAM_L1_CACHE_SIZE
, rs6000_cost
->l1_cache_size
,
3829 global_options
.x_param_values
,
3830 global_options_set
.x_param_values
);
3831 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
3832 rs6000_cost
->cache_line_size
,
3833 global_options
.x_param_values
,
3834 global_options_set
.x_param_values
);
3835 maybe_set_param_value (PARAM_L2_CACHE_SIZE
, rs6000_cost
->l2_cache_size
,
3836 global_options
.x_param_values
,
3837 global_options_set
.x_param_values
);
3839 /* Increase loop peeling limits based on performance analysis. */
3840 maybe_set_param_value (PARAM_MAX_PEELED_INSNS
, 400,
3841 global_options
.x_param_values
,
3842 global_options_set
.x_param_values
);
3843 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS
, 400,
3844 global_options
.x_param_values
,
3845 global_options_set
.x_param_values
);
3847 /* If using typedef char *va_list, signal that
3848 __builtin_va_start (&ap, 0) can be optimized to
3849 ap = __builtin_next_arg (0). */
3850 if (DEFAULT_ABI
!= ABI_V4
)
3851 targetm
.expand_builtin_va_start
= NULL
;
3854 /* Set up single/double float flags.
3855 If TARGET_HARD_FLOAT is set, but neither single or double is set,
3856 then set both flags. */
3857 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
3858 && rs6000_single_float
== 0 && rs6000_double_float
== 0)
3859 rs6000_single_float
= rs6000_double_float
= 1;
3861 /* If not explicitly specified via option, decide whether to generate indexed
3862 load/store instructions. */
3863 if (TARGET_AVOID_XFORM
== -1)
3864 /* Avoid indexed addressing when targeting Power6 in order to avoid the
3865 DERAT mispredict penalty. However the LVE and STVE altivec instructions
3866 need indexed accesses and the type used is the scalar type of the element
3867 being loaded or stored. */
3868 TARGET_AVOID_XFORM
= (rs6000_cpu
== PROCESSOR_POWER6
&& TARGET_CMPB
3869 && !TARGET_ALTIVEC
);
3871 /* Set the -mrecip options. */
3872 if (rs6000_recip_name
)
3874 char *p
= ASTRDUP (rs6000_recip_name
);
3876 unsigned int mask
, i
;
3879 while ((q
= strtok (p
, ",")) != NULL
)
3890 if (!strcmp (q
, "default"))
3891 mask
= ((TARGET_RECIP_PRECISION
)
3892 ? RECIP_HIGH_PRECISION
: RECIP_LOW_PRECISION
);
3895 for (i
= 0; i
< ARRAY_SIZE (recip_options
); i
++)
3896 if (!strcmp (q
, recip_options
[i
].string
))
3898 mask
= recip_options
[i
].mask
;
3902 if (i
== ARRAY_SIZE (recip_options
))
3904 error ("unknown option for -mrecip=%s", q
);
3912 rs6000_recip_control
&= ~mask
;
3914 rs6000_recip_control
|= mask
;
3918 /* Set the builtin mask of the various options used that could affect which
3919 builtins were used. In the past we used target_flags, but we've run out
3920 of bits, and some options like SPE and PAIRED are no longer in
3922 rs6000_builtin_mask
= rs6000_builtin_mask_calculate ();
3923 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
3926 "new builtin mask = " HOST_WIDE_INT_PRINT_HEX
", ",
3927 rs6000_builtin_mask
);
3928 rs6000_print_builtin_options (stderr
, 0, NULL
, rs6000_builtin_mask
);
3931 /* Initialize all of the registers. */
3932 rs6000_init_hard_regno_mode_ok (global_init_p
);
3934 /* Save the initial options in case the user does function specific options */
3936 target_option_default_node
= target_option_current_node
3937 = build_target_option_node (&global_options
);
3939 /* If not explicitly specified via option, decide whether to generate the
3940 extra blr's required to preserve the link stack on some cpus (eg, 476). */
3941 if (TARGET_LINK_STACK
== -1)
3942 SET_TARGET_LINK_STACK (rs6000_cpu
== PROCESSOR_PPC476
&& flag_pic
);
3947 /* Implement TARGET_OPTION_OVERRIDE. On the RS/6000 this is used to
3948 define the target cpu type. */
3951 rs6000_option_override (void)
3953 (void) rs6000_option_override_internal (true);
3957 /* Implement targetm.vectorize.builtin_mask_for_load. */
3959 rs6000_builtin_mask_for_load (void)
3961 if (TARGET_ALTIVEC
|| TARGET_VSX
)
3962 return altivec_builtin_mask_for_load
;
3967 /* Implement LOOP_ALIGN. */
3969 rs6000_loop_align (rtx label
)
3974 /* Don't override loop alignment if -falign-loops was specified. */
3975 if (!can_override_loop_align
)
3976 return align_loops_log
;
3978 bb
= BLOCK_FOR_INSN (label
);
3979 ninsns
= num_loop_insns(bb
->loop_father
);
3981 /* Align small loops to 32 bytes to fit in an icache sector, otherwise return default. */
3982 if (ninsns
> 4 && ninsns
<= 8
3983 && (rs6000_cpu
== PROCESSOR_POWER4
3984 || rs6000_cpu
== PROCESSOR_POWER5
3985 || rs6000_cpu
== PROCESSOR_POWER6
3986 || rs6000_cpu
== PROCESSOR_POWER7
3987 || rs6000_cpu
== PROCESSOR_POWER8
))
3990 return align_loops_log
;
3993 /* Implement TARGET_LOOP_ALIGN_MAX_SKIP. */
3995 rs6000_loop_align_max_skip (rtx label
)
3997 return (1 << rs6000_loop_align (label
)) - 1;
4000 /* Return true iff, data reference of TYPE can reach vector alignment (16)
4001 after applying N number of iterations. This routine does not determine
4002 how may iterations are required to reach desired alignment. */
4005 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED
, bool is_packed
)
4012 if (rs6000_alignment_flags
== MASK_ALIGN_NATURAL
)
4015 if (rs6000_alignment_flags
== MASK_ALIGN_POWER
)
4025 /* Assuming that all other types are naturally aligned. CHECKME! */
4030 /* Return true if the vector misalignment factor is supported by the
4033 rs6000_builtin_support_vector_misalignment (enum machine_mode mode
,
4040 /* Return if movmisalign pattern is not supported for this mode. */
4041 if (optab_handler (movmisalign_optab
, mode
) == CODE_FOR_nothing
)
4044 if (misalignment
== -1)
4046 /* Misalignment factor is unknown at compile time but we know
4047 it's word aligned. */
4048 if (rs6000_vector_alignment_reachable (type
, is_packed
))
4050 int element_size
= TREE_INT_CST_LOW (TYPE_SIZE (type
));
4052 if (element_size
== 64 || element_size
== 32)
4059 /* VSX supports word-aligned vector. */
4060 if (misalignment
% 4 == 0)
4066 /* Implement targetm.vectorize.builtin_vectorization_cost. */
4068 rs6000_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost
,
4069 tree vectype
, int misalign
)
4074 switch (type_of_cost
)
4084 case cond_branch_not_taken
:
4093 case vec_promote_demote
:
4099 case cond_branch_taken
:
4102 case unaligned_load
:
4103 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4105 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4107 /* Double word aligned. */
4115 /* Double word aligned. */
4119 /* Unknown misalignment. */
4132 /* Misaligned loads are not supported. */
4137 case unaligned_store
:
4138 if (TARGET_VSX
&& TARGET_ALLOW_MOVMISALIGN
)
4140 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4142 /* Double word aligned. */
4150 /* Double word aligned. */
4154 /* Unknown misalignment. */
4167 /* Misaligned stores are not supported. */
4173 elements
= TYPE_VECTOR_SUBPARTS (vectype
);
4174 elem_type
= TREE_TYPE (vectype
);
4175 /* 32-bit vectors loaded into registers are stored as double
4176 precision, so we need n/2 converts in addition to the usual
4177 n/2 merges to construct a vector of short floats from them. */
4178 if (SCALAR_FLOAT_TYPE_P (elem_type
)
4179 && TYPE_PRECISION (elem_type
) == 32)
4180 return elements
+ 1;
4182 return elements
/ 2 + 1;
4189 /* Implement targetm.vectorize.preferred_simd_mode. */
4191 static enum machine_mode
4192 rs6000_preferred_simd_mode (enum machine_mode mode
)
4201 if (TARGET_ALTIVEC
|| TARGET_VSX
)
4225 if (TARGET_PAIRED_FLOAT
4231 typedef struct _rs6000_cost_data
4233 struct loop
*loop_info
;
4237 /* Test for likely overcommitment of vector hardware resources. If a
4238 loop iteration is relatively large, and too large a percentage of
4239 instructions in the loop are vectorized, the cost model may not
4240 adequately reflect delays from unavailable vector resources.
4241 Penalize the loop body cost for this case. */
4244 rs6000_density_test (rs6000_cost_data
*data
)
4246 const int DENSITY_PCT_THRESHOLD
= 85;
4247 const int DENSITY_SIZE_THRESHOLD
= 70;
4248 const int DENSITY_PENALTY
= 10;
4249 struct loop
*loop
= data
->loop_info
;
4250 basic_block
*bbs
= get_loop_body (loop
);
4251 int nbbs
= loop
->num_nodes
;
4252 int vec_cost
= data
->cost
[vect_body
], not_vec_cost
= 0;
4255 for (i
= 0; i
< nbbs
; i
++)
4257 basic_block bb
= bbs
[i
];
4258 gimple_stmt_iterator gsi
;
4260 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
4262 gimple stmt
= gsi_stmt (gsi
);
4263 stmt_vec_info stmt_info
= vinfo_for_stmt (stmt
);
4265 if (!STMT_VINFO_RELEVANT_P (stmt_info
)
4266 && !STMT_VINFO_IN_PATTERN_P (stmt_info
))
4272 density_pct
= (vec_cost
* 100) / (vec_cost
+ not_vec_cost
);
4274 if (density_pct
> DENSITY_PCT_THRESHOLD
4275 && vec_cost
+ not_vec_cost
> DENSITY_SIZE_THRESHOLD
)
4277 data
->cost
[vect_body
] = vec_cost
* (100 + DENSITY_PENALTY
) / 100;
4278 if (dump_enabled_p ())
4279 dump_printf_loc (MSG_NOTE
, vect_location
,
4280 "density %d%%, cost %d exceeds threshold, penalizing "
4281 "loop body cost by %d%%", density_pct
,
4282 vec_cost
+ not_vec_cost
, DENSITY_PENALTY
);
4286 /* Implement targetm.vectorize.init_cost. */
4289 rs6000_init_cost (struct loop
*loop_info
)
4291 rs6000_cost_data
*data
= XNEW (struct _rs6000_cost_data
);
4292 data
->loop_info
= loop_info
;
4293 data
->cost
[vect_prologue
] = 0;
4294 data
->cost
[vect_body
] = 0;
4295 data
->cost
[vect_epilogue
] = 0;
4299 /* Implement targetm.vectorize.add_stmt_cost. */
4302 rs6000_add_stmt_cost (void *data
, int count
, enum vect_cost_for_stmt kind
,
4303 struct _stmt_vec_info
*stmt_info
, int misalign
,
4304 enum vect_cost_model_location where
)
4306 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4307 unsigned retval
= 0;
4309 if (flag_vect_cost_model
)
4311 tree vectype
= stmt_info
? stmt_vectype (stmt_info
) : NULL_TREE
;
4312 int stmt_cost
= rs6000_builtin_vectorization_cost (kind
, vectype
,
4314 /* Statements in an inner loop relative to the loop being
4315 vectorized are weighted more heavily. The value here is
4316 arbitrary and could potentially be improved with analysis. */
4317 if (where
== vect_body
&& stmt_info
&& stmt_in_inner_loop_p (stmt_info
))
4318 count
*= 50; /* FIXME. */
4320 retval
= (unsigned) (count
* stmt_cost
);
4321 cost_data
->cost
[where
] += retval
;
4327 /* Implement targetm.vectorize.finish_cost. */
4330 rs6000_finish_cost (void *data
, unsigned *prologue_cost
,
4331 unsigned *body_cost
, unsigned *epilogue_cost
)
4333 rs6000_cost_data
*cost_data
= (rs6000_cost_data
*) data
;
4335 if (cost_data
->loop_info
)
4336 rs6000_density_test (cost_data
);
4338 *prologue_cost
= cost_data
->cost
[vect_prologue
];
4339 *body_cost
= cost_data
->cost
[vect_body
];
4340 *epilogue_cost
= cost_data
->cost
[vect_epilogue
];
4343 /* Implement targetm.vectorize.destroy_cost_data. */
4346 rs6000_destroy_cost_data (void *data
)
4351 /* Handler for the Mathematical Acceleration Subsystem (mass) interface to a
4352 library with vectorized intrinsics. */
4355 rs6000_builtin_vectorized_libmass (tree fndecl
, tree type_out
, tree type_in
)
4358 const char *suffix
= NULL
;
4359 tree fntype
, new_fndecl
, bdecl
= NULL_TREE
;
4362 enum machine_mode el_mode
, in_mode
;
4365 /* Libmass is suitable for unsafe math only as it does not correctly support
4366 parts of IEEE with the required precision such as denormals. Only support
4367 it if we have VSX to use the simd d2 or f4 functions.
4368 XXX: Add variable length support. */
4369 if (!flag_unsafe_math_optimizations
|| !TARGET_VSX
)
4372 el_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4373 n
= TYPE_VECTOR_SUBPARTS (type_out
);
4374 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4375 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4376 if (el_mode
!= in_mode
4380 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4382 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4385 case BUILT_IN_ATAN2
:
4386 case BUILT_IN_HYPOT
:
4392 case BUILT_IN_ACOSH
:
4394 case BUILT_IN_ASINH
:
4396 case BUILT_IN_ATANH
:
4404 case BUILT_IN_EXPM1
:
4405 case BUILT_IN_LGAMMA
:
4406 case BUILT_IN_LOG10
:
4407 case BUILT_IN_LOG1P
:
4415 bdecl
= builtin_decl_implicit (fn
);
4416 suffix
= "d2"; /* pow -> powd2 */
4417 if (el_mode
!= DFmode
4423 case BUILT_IN_ATAN2F
:
4424 case BUILT_IN_HYPOTF
:
4429 case BUILT_IN_ACOSF
:
4430 case BUILT_IN_ACOSHF
:
4431 case BUILT_IN_ASINF
:
4432 case BUILT_IN_ASINHF
:
4433 case BUILT_IN_ATANF
:
4434 case BUILT_IN_ATANHF
:
4435 case BUILT_IN_CBRTF
:
4437 case BUILT_IN_COSHF
:
4439 case BUILT_IN_ERFCF
:
4440 case BUILT_IN_EXP2F
:
4442 case BUILT_IN_EXPM1F
:
4443 case BUILT_IN_LGAMMAF
:
4444 case BUILT_IN_LOG10F
:
4445 case BUILT_IN_LOG1PF
:
4446 case BUILT_IN_LOG2F
:
4449 case BUILT_IN_SINHF
:
4450 case BUILT_IN_SQRTF
:
4452 case BUILT_IN_TANHF
:
4453 bdecl
= builtin_decl_implicit (fn
);
4454 suffix
= "4"; /* powf -> powf4 */
4455 if (el_mode
!= SFmode
4468 gcc_assert (suffix
!= NULL
);
4469 bname
= IDENTIFIER_POINTER (DECL_NAME (bdecl
));
4473 strcpy (name
, bname
+ sizeof ("__builtin_") - 1);
4474 strcat (name
, suffix
);
4477 fntype
= build_function_type_list (type_out
, type_in
, NULL
);
4478 else if (n_args
== 2)
4479 fntype
= build_function_type_list (type_out
, type_in
, type_in
, NULL
);
4483 /* Build a function declaration for the vectorized function. */
4484 new_fndecl
= build_decl (BUILTINS_LOCATION
,
4485 FUNCTION_DECL
, get_identifier (name
), fntype
);
4486 TREE_PUBLIC (new_fndecl
) = 1;
4487 DECL_EXTERNAL (new_fndecl
) = 1;
4488 DECL_IS_NOVOPS (new_fndecl
) = 1;
4489 TREE_READONLY (new_fndecl
) = 1;
4494 /* Returns a function decl for a vectorized version of the builtin function
4495 with builtin function code FN and the result vector type TYPE, or NULL_TREE
4496 if it is not available. */
4499 rs6000_builtin_vectorized_function (tree fndecl
, tree type_out
,
4502 enum machine_mode in_mode
, out_mode
;
4505 if (TARGET_DEBUG_BUILTIN
)
4506 fprintf (stderr
, "rs6000_builtin_vectorized_function (%s, %s, %s)\n",
4507 IDENTIFIER_POINTER (DECL_NAME (fndecl
)),
4508 GET_MODE_NAME (TYPE_MODE (type_out
)),
4509 GET_MODE_NAME (TYPE_MODE (type_in
)));
4511 if (TREE_CODE (type_out
) != VECTOR_TYPE
4512 || TREE_CODE (type_in
) != VECTOR_TYPE
4513 || !TARGET_VECTORIZE_BUILTINS
)
4516 out_mode
= TYPE_MODE (TREE_TYPE (type_out
));
4517 out_n
= TYPE_VECTOR_SUBPARTS (type_out
);
4518 in_mode
= TYPE_MODE (TREE_TYPE (type_in
));
4519 in_n
= TYPE_VECTOR_SUBPARTS (type_in
);
4521 if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_NORMAL
)
4523 enum built_in_function fn
= DECL_FUNCTION_CODE (fndecl
);
4526 case BUILT_IN_CLZIMAX
:
4527 case BUILT_IN_CLZLL
:
4530 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4532 if (out_mode
== QImode
&& out_n
== 16)
4533 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZB
];
4534 else if (out_mode
== HImode
&& out_n
== 8)
4535 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZH
];
4536 else if (out_mode
== SImode
&& out_n
== 4)
4537 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZW
];
4538 else if (out_mode
== DImode
&& out_n
== 2)
4539 return rs6000_builtin_decls
[P8V_BUILTIN_VCLZD
];
4542 case BUILT_IN_COPYSIGN
:
4543 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4544 && out_mode
== DFmode
&& out_n
== 2
4545 && in_mode
== DFmode
&& in_n
== 2)
4546 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNDP
];
4548 case BUILT_IN_COPYSIGNF
:
4549 if (out_mode
!= SFmode
|| out_n
!= 4
4550 || in_mode
!= SFmode
|| in_n
!= 4)
4552 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4553 return rs6000_builtin_decls
[VSX_BUILTIN_CPSGNSP
];
4554 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4555 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_COPYSIGN_V4SF
];
4557 case BUILT_IN_POPCOUNTIMAX
:
4558 case BUILT_IN_POPCOUNTLL
:
4559 case BUILT_IN_POPCOUNTL
:
4560 case BUILT_IN_POPCOUNT
:
4561 if (TARGET_P8_VECTOR
&& in_mode
== out_mode
&& out_n
== in_n
)
4563 if (out_mode
== QImode
&& out_n
== 16)
4564 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTB
];
4565 else if (out_mode
== HImode
&& out_n
== 8)
4566 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTH
];
4567 else if (out_mode
== SImode
&& out_n
== 4)
4568 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTW
];
4569 else if (out_mode
== DImode
&& out_n
== 2)
4570 return rs6000_builtin_decls
[P8V_BUILTIN_VPOPCNTD
];
4574 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4575 && out_mode
== DFmode
&& out_n
== 2
4576 && in_mode
== DFmode
&& in_n
== 2)
4577 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTDP
];
4579 case BUILT_IN_SQRTF
:
4580 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4581 && out_mode
== SFmode
&& out_n
== 4
4582 && in_mode
== SFmode
&& in_n
== 4)
4583 return rs6000_builtin_decls
[VSX_BUILTIN_XVSQRTSP
];
4586 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4587 && out_mode
== DFmode
&& out_n
== 2
4588 && in_mode
== DFmode
&& in_n
== 2)
4589 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIP
];
4591 case BUILT_IN_CEILF
:
4592 if (out_mode
!= SFmode
|| out_n
!= 4
4593 || in_mode
!= SFmode
|| in_n
!= 4)
4595 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4596 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIP
];
4597 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4598 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIP
];
4600 case BUILT_IN_FLOOR
:
4601 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4602 && out_mode
== DFmode
&& out_n
== 2
4603 && in_mode
== DFmode
&& in_n
== 2)
4604 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIM
];
4606 case BUILT_IN_FLOORF
:
4607 if (out_mode
!= SFmode
|| out_n
!= 4
4608 || in_mode
!= SFmode
|| in_n
!= 4)
4610 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4611 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIM
];
4612 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4613 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIM
];
4616 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4617 && out_mode
== DFmode
&& out_n
== 2
4618 && in_mode
== DFmode
&& in_n
== 2)
4619 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDDP
];
4622 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4623 && out_mode
== SFmode
&& out_n
== 4
4624 && in_mode
== SFmode
&& in_n
== 4)
4625 return rs6000_builtin_decls
[VSX_BUILTIN_XVMADDSP
];
4626 else if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
)
4627 && out_mode
== SFmode
&& out_n
== 4
4628 && in_mode
== SFmode
&& in_n
== 4)
4629 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VMADDFP
];
4631 case BUILT_IN_TRUNC
:
4632 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4633 && out_mode
== DFmode
&& out_n
== 2
4634 && in_mode
== DFmode
&& in_n
== 2)
4635 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIZ
];
4637 case BUILT_IN_TRUNCF
:
4638 if (out_mode
!= SFmode
|| out_n
!= 4
4639 || in_mode
!= SFmode
|| in_n
!= 4)
4641 if (VECTOR_UNIT_VSX_P (V4SFmode
))
4642 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIZ
];
4643 if (VECTOR_UNIT_ALTIVEC_P (V4SFmode
))
4644 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRFIZ
];
4646 case BUILT_IN_NEARBYINT
:
4647 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4648 && flag_unsafe_math_optimizations
4649 && out_mode
== DFmode
&& out_n
== 2
4650 && in_mode
== DFmode
&& in_n
== 2)
4651 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPI
];
4653 case BUILT_IN_NEARBYINTF
:
4654 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4655 && flag_unsafe_math_optimizations
4656 && out_mode
== SFmode
&& out_n
== 4
4657 && in_mode
== SFmode
&& in_n
== 4)
4658 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPI
];
4661 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4662 && !flag_trapping_math
4663 && out_mode
== DFmode
&& out_n
== 2
4664 && in_mode
== DFmode
&& in_n
== 2)
4665 return rs6000_builtin_decls
[VSX_BUILTIN_XVRDPIC
];
4667 case BUILT_IN_RINTF
:
4668 if (VECTOR_UNIT_VSX_P (V4SFmode
)
4669 && !flag_trapping_math
4670 && out_mode
== SFmode
&& out_n
== 4
4671 && in_mode
== SFmode
&& in_n
== 4)
4672 return rs6000_builtin_decls
[VSX_BUILTIN_XVRSPIC
];
4679 else if (DECL_BUILT_IN_CLASS (fndecl
) == BUILT_IN_MD
)
4681 enum rs6000_builtins fn
4682 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
4685 case RS6000_BUILTIN_RSQRTF
:
4686 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4687 && out_mode
== SFmode
&& out_n
== 4
4688 && in_mode
== SFmode
&& in_n
== 4)
4689 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRSQRTFP
];
4691 case RS6000_BUILTIN_RSQRT
:
4692 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4693 && out_mode
== DFmode
&& out_n
== 2
4694 && in_mode
== DFmode
&& in_n
== 2)
4695 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
4697 case RS6000_BUILTIN_RECIPF
:
4698 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode
)
4699 && out_mode
== SFmode
&& out_n
== 4
4700 && in_mode
== SFmode
&& in_n
== 4)
4701 return rs6000_builtin_decls
[ALTIVEC_BUILTIN_VRECIPFP
];
4703 case RS6000_BUILTIN_RECIP
:
4704 if (VECTOR_UNIT_VSX_P (V2DFmode
)
4705 && out_mode
== DFmode
&& out_n
== 2
4706 && in_mode
== DFmode
&& in_n
== 2)
4707 return rs6000_builtin_decls
[VSX_BUILTIN_RECIP_V2DF
];
4714 /* Generate calls to libmass if appropriate. */
4715 if (rs6000_veclib_handler
)
4716 return rs6000_veclib_handler (fndecl
, type_out
, type_in
);
4721 /* Default CPU string for rs6000*_file_start functions. */
4722 static const char *rs6000_default_cpu
;
4724 /* Do anything needed at the start of the asm file. */
4727 rs6000_file_start (void)
4730 const char *start
= buffer
;
4731 FILE *file
= asm_out_file
;
4733 rs6000_default_cpu
= TARGET_CPU_DEFAULT
;
4735 default_file_start ();
4737 if (flag_verbose_asm
)
4739 sprintf (buffer
, "\n%s rs6000/powerpc options:", ASM_COMMENT_START
);
4741 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
4743 fprintf (file
, "%s --with-cpu=%s", start
, rs6000_default_cpu
);
4747 if (global_options_set
.x_rs6000_cpu_index
)
4749 fprintf (file
, "%s -mcpu=%s", start
,
4750 processor_target_table
[rs6000_cpu_index
].name
);
4754 if (global_options_set
.x_rs6000_tune_index
)
4756 fprintf (file
, "%s -mtune=%s", start
,
4757 processor_target_table
[rs6000_tune_index
].name
);
4761 if (PPC405_ERRATUM77
)
4763 fprintf (file
, "%s PPC405CR_ERRATUM77", start
);
4767 #ifdef USING_ELFOS_H
4768 switch (rs6000_sdata
)
4770 case SDATA_NONE
: fprintf (file
, "%s -msdata=none", start
); start
= ""; break;
4771 case SDATA_DATA
: fprintf (file
, "%s -msdata=data", start
); start
= ""; break;
4772 case SDATA_SYSV
: fprintf (file
, "%s -msdata=sysv", start
); start
= ""; break;
4773 case SDATA_EABI
: fprintf (file
, "%s -msdata=eabi", start
); start
= ""; break;
4776 if (rs6000_sdata
&& g_switch_value
)
4778 fprintf (file
, "%s -G %d", start
,
4788 if (DEFAULT_ABI
== ABI_ELFv2
)
4789 fprintf (file
, "\t.abiversion 2\n");
4791 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
4792 || (TARGET_ELF
&& flag_pic
== 2))
4794 switch_to_section (toc_section
);
4795 switch_to_section (text_section
);
4800 /* Return nonzero if this function is known to have a null epilogue. */
4803 direct_return (void)
4805 if (reload_completed
)
4807 rs6000_stack_t
*info
= rs6000_stack_info ();
4809 if (info
->first_gp_reg_save
== 32
4810 && info
->first_fp_reg_save
== 64
4811 && info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
4812 && ! info
->lr_save_p
4813 && ! info
->cr_save_p
4814 && info
->vrsave_mask
== 0
4822 /* Return the number of instructions it takes to form a constant in an
4823 integer register. */
4826 num_insns_constant_wide (HOST_WIDE_INT value
)
4828 /* signed constant loadable with addi */
4829 if ((unsigned HOST_WIDE_INT
) (value
+ 0x8000) < 0x10000)
4832 /* constant loadable with addis */
4833 else if ((value
& 0xffff) == 0
4834 && (value
>> 31 == -1 || value
>> 31 == 0))
4837 else if (TARGET_POWERPC64
)
4839 HOST_WIDE_INT low
= ((value
& 0xffffffff) ^ 0x80000000) - 0x80000000;
4840 HOST_WIDE_INT high
= value
>> 31;
4842 if (high
== 0 || high
== -1)
4848 return num_insns_constant_wide (high
) + 1;
4850 return num_insns_constant_wide (low
) + 1;
4852 return (num_insns_constant_wide (high
)
4853 + num_insns_constant_wide (low
) + 1);
4861 num_insns_constant (rtx op
, enum machine_mode mode
)
4863 HOST_WIDE_INT low
, high
;
4865 switch (GET_CODE (op
))
4868 if ((INTVAL (op
) >> 31) != 0 && (INTVAL (op
) >> 31) != -1
4869 && mask64_operand (op
, mode
))
4872 return num_insns_constant_wide (INTVAL (op
));
4874 case CONST_WIDE_INT
:
4877 int ins
= CONST_WIDE_INT_NUNITS (op
) - 1;
4878 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (op
); i
++)
4879 ins
+= num_insns_constant_wide (CONST_WIDE_INT_ELT (op
, i
));
4884 if (mode
== SFmode
|| mode
== SDmode
)
4889 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4890 if (DECIMAL_FLOAT_MODE_P (mode
))
4891 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
4893 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4894 return num_insns_constant_wide ((HOST_WIDE_INT
) l
);
4900 REAL_VALUE_FROM_CONST_DOUBLE (rv
, op
);
4901 if (DECIMAL_FLOAT_MODE_P (mode
))
4902 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, l
);
4904 REAL_VALUE_TO_TARGET_DOUBLE (rv
, l
);
4905 high
= l
[WORDS_BIG_ENDIAN
== 0];
4906 low
= l
[WORDS_BIG_ENDIAN
!= 0];
4909 return (num_insns_constant_wide (low
)
4910 + num_insns_constant_wide (high
));
4913 if ((high
== 0 && low
>= 0)
4914 || (high
== -1 && low
< 0))
4915 return num_insns_constant_wide (low
);
4917 else if (mask64_operand (op
, mode
))
4921 return num_insns_constant_wide (high
) + 1;
4924 return (num_insns_constant_wide (high
)
4925 + num_insns_constant_wide (low
) + 1);
4933 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
4934 If the mode of OP is MODE_VECTOR_INT, this simply returns the
4935 corresponding element of the vector, but for V4SFmode and V2SFmode,
4936 the corresponding "float" is interpreted as an SImode integer. */
4939 const_vector_elt_as_int (rtx op
, unsigned int elt
)
4943 /* We can't handle V2DImode and V2DFmode vector constants here yet. */
4944 gcc_assert (GET_MODE (op
) != V2DImode
4945 && GET_MODE (op
) != V2DFmode
);
4947 tmp
= CONST_VECTOR_ELT (op
, elt
);
4948 if (GET_MODE (op
) == V4SFmode
4949 || GET_MODE (op
) == V2SFmode
)
4950 tmp
= gen_lowpart (SImode
, tmp
);
4951 return INTVAL (tmp
);
4954 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
4955 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
4956 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
4957 all items are set to the same value and contain COPIES replicas of the
4958 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
4959 operand and the others are set to the value of the operand's msb. */
4962 vspltis_constant (rtx op
, unsigned step
, unsigned copies
)
4964 enum machine_mode mode
= GET_MODE (op
);
4965 enum machine_mode inner
= GET_MODE_INNER (mode
);
4973 HOST_WIDE_INT splat_val
;
4974 HOST_WIDE_INT msb_val
;
4976 if (mode
== V2DImode
|| mode
== V2DFmode
)
4979 nunits
= GET_MODE_NUNITS (mode
);
4980 bitsize
= GET_MODE_BITSIZE (inner
);
4981 mask
= GET_MODE_MASK (inner
);
4983 val
= const_vector_elt_as_int (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
4985 msb_val
= val
> 0 ? 0 : -1;
4987 /* Construct the value to be splatted, if possible. If not, return 0. */
4988 for (i
= 2; i
<= copies
; i
*= 2)
4990 HOST_WIDE_INT small_val
;
4992 small_val
= splat_val
>> bitsize
;
4994 if (splat_val
!= ((small_val
<< bitsize
) | (small_val
& mask
)))
4996 splat_val
= small_val
;
4999 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
5000 if (EASY_VECTOR_15 (splat_val
))
5003 /* Also check if we can splat, and then add the result to itself. Do so if
5004 the value is positive, of if the splat instruction is using OP's mode;
5005 for splat_val < 0, the splat and the add should use the same mode. */
5006 else if (EASY_VECTOR_15_ADD_SELF (splat_val
)
5007 && (splat_val
>= 0 || (step
== 1 && copies
== 1)))
5010 /* Also check if are loading up the most significant bit which can be done by
5011 loading up -1 and shifting the value left by -1. */
5012 else if (EASY_VECTOR_MSB (splat_val
, inner
))
5018 /* Check if VAL is present in every STEP-th element, and the
5019 other elements are filled with its most significant bit. */
5020 for (i
= 1; i
< nunits
; ++i
)
5022 HOST_WIDE_INT desired_val
;
5023 unsigned elt
= BYTES_BIG_ENDIAN
? nunits
- 1 - i
: i
;
5024 if ((i
& (step
- 1)) == 0)
5027 desired_val
= msb_val
;
5029 if (desired_val
!= const_vector_elt_as_int (op
, elt
))
5037 /* Return true if OP is of the given MODE and can be synthesized
5038 with a vspltisb, vspltish or vspltisw. */
5041 easy_altivec_constant (rtx op
, enum machine_mode mode
)
5043 unsigned step
, copies
;
5045 if (mode
== VOIDmode
)
5046 mode
= GET_MODE (op
);
5047 else if (mode
!= GET_MODE (op
))
5050 /* V2DI/V2DF was added with VSX. Only allow 0 and all 1's as easy
5052 if (mode
== V2DFmode
)
5053 return zero_constant (op
, mode
);
5055 if (mode
== V2DImode
)
5057 /* In case the compiler is built 32-bit, CONST_WIDE_INT
5058 constants are not easy. */
5059 if (GET_CODE (CONST_VECTOR_ELT (op
, 0)) != CONST_INT
5060 || GET_CODE (CONST_VECTOR_ELT (op
, 1)) != CONST_INT
)
5063 if (zero_constant (op
, mode
))
5066 if (INTVAL (CONST_VECTOR_ELT (op
, 0)) == -1
5067 && INTVAL (CONST_VECTOR_ELT (op
, 1)) == -1)
5073 /* Start with a vspltisw. */
5074 step
= GET_MODE_NUNITS (mode
) / 4;
5077 if (vspltis_constant (op
, step
, copies
))
5080 /* Then try with a vspltish. */
5086 if (vspltis_constant (op
, step
, copies
))
5089 /* And finally a vspltisb. */
5095 if (vspltis_constant (op
, step
, copies
))
5101 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
5102 result is OP. Abort if it is not possible. */
5105 gen_easy_altivec_constant (rtx op
)
5107 enum machine_mode mode
= GET_MODE (op
);
5108 int nunits
= GET_MODE_NUNITS (mode
);
5109 rtx val
= CONST_VECTOR_ELT (op
, BYTES_BIG_ENDIAN
? nunits
- 1 : 0);
5110 unsigned step
= nunits
/ 4;
5111 unsigned copies
= 1;
5113 /* Start with a vspltisw. */
5114 if (vspltis_constant (op
, step
, copies
))
5115 return gen_rtx_VEC_DUPLICATE (V4SImode
, gen_lowpart (SImode
, val
));
5117 /* Then try with a vspltish. */
5123 if (vspltis_constant (op
, step
, copies
))
5124 return gen_rtx_VEC_DUPLICATE (V8HImode
, gen_lowpart (HImode
, val
));
5126 /* And finally a vspltisb. */
5132 if (vspltis_constant (op
, step
, copies
))
5133 return gen_rtx_VEC_DUPLICATE (V16QImode
, gen_lowpart (QImode
, val
));
5139 output_vec_const_move (rtx
*operands
)
5142 enum machine_mode mode
;
5147 mode
= GET_MODE (dest
);
5151 if (zero_constant (vec
, mode
))
5152 return "xxlxor %x0,%x0,%x0";
5154 if (mode
== V2DImode
5155 && INTVAL (CONST_VECTOR_ELT (vec
, 0)) == -1
5156 && INTVAL (CONST_VECTOR_ELT (vec
, 1)) == -1)
5157 return "vspltisw %0,-1";
5163 if (zero_constant (vec
, mode
))
5164 return "vxor %0,%0,%0";
5166 splat_vec
= gen_easy_altivec_constant (vec
);
5167 gcc_assert (GET_CODE (splat_vec
) == VEC_DUPLICATE
);
5168 operands
[1] = XEXP (splat_vec
, 0);
5169 if (!EASY_VECTOR_15 (INTVAL (operands
[1])))
5172 switch (GET_MODE (splat_vec
))
5175 return "vspltisw %0,%1";
5178 return "vspltish %0,%1";
5181 return "vspltisb %0,%1";
5188 gcc_assert (TARGET_SPE
);
5190 /* Vector constant 0 is handled as a splitter of V2SI, and in the
5191 pattern of V1DI, V4HI, and V2SF.
5193 FIXME: We should probably return # and add post reload
5194 splitters for these, but this way is so easy ;-). */
5195 cst
= INTVAL (CONST_VECTOR_ELT (vec
, 0));
5196 cst2
= INTVAL (CONST_VECTOR_ELT (vec
, 1));
5197 operands
[1] = CONST_VECTOR_ELT (vec
, 0);
5198 operands
[2] = CONST_VECTOR_ELT (vec
, 1);
5200 return "li %0,%1\n\tevmergelo %0,%0,%0";
5202 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
5205 /* Initialize TARGET of vector PAIRED to VALS. */
5208 paired_expand_vector_init (rtx target
, rtx vals
)
5210 enum machine_mode mode
= GET_MODE (target
);
5211 int n_elts
= GET_MODE_NUNITS (mode
);
5213 rtx x
, new_rtx
, tmp
, constant_op
, op1
, op2
;
5216 for (i
= 0; i
< n_elts
; ++i
)
5218 x
= XVECEXP (vals
, 0, i
);
5219 if (!CONSTANT_P (x
))
5224 /* Load from constant pool. */
5225 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
5231 /* The vector is initialized only with non-constants. */
5232 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, XVECEXP (vals
, 0, 0),
5233 XVECEXP (vals
, 0, 1));
5235 emit_move_insn (target
, new_rtx
);
5239 /* One field is non-constant and the other one is a constant. Load the
5240 constant from the constant pool and use ps_merge instruction to
5241 construct the whole vector. */
5242 op1
= XVECEXP (vals
, 0, 0);
5243 op2
= XVECEXP (vals
, 0, 1);
5245 constant_op
= (CONSTANT_P (op1
)) ? op1
: op2
;
5247 tmp
= gen_reg_rtx (GET_MODE (constant_op
));
5248 emit_move_insn (tmp
, constant_op
);
5250 if (CONSTANT_P (op1
))
5251 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, tmp
, op2
);
5253 new_rtx
= gen_rtx_VEC_CONCAT (V2SFmode
, op1
, tmp
);
5255 emit_move_insn (target
, new_rtx
);
5259 paired_expand_vector_move (rtx operands
[])
5261 rtx op0
= operands
[0], op1
= operands
[1];
5263 emit_move_insn (op0
, op1
);
5266 /* Emit vector compare for code RCODE. DEST is destination, OP1 and
5267 OP2 are two VEC_COND_EXPR operands, CC_OP0 and CC_OP1 are the two
5268 operands for the relation operation COND. This is a recursive
5272 paired_emit_vector_compare (enum rtx_code rcode
,
5273 rtx dest
, rtx op0
, rtx op1
,
5274 rtx cc_op0
, rtx cc_op1
)
5276 rtx tmp
= gen_reg_rtx (V2SFmode
);
5279 gcc_assert (TARGET_PAIRED_FLOAT
);
5280 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
5286 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5290 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5291 emit_insn (gen_selv2sf4 (dest
, tmp
, op0
, op1
, CONST0_RTX (SFmode
)));
5295 paired_emit_vector_compare (GE
, dest
, op0
, op1
, cc_op1
, cc_op0
);
5298 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5301 tmp1
= gen_reg_rtx (V2SFmode
);
5302 max
= gen_reg_rtx (V2SFmode
);
5303 min
= gen_reg_rtx (V2SFmode
);
5304 gen_reg_rtx (V2SFmode
);
5306 emit_insn (gen_subv2sf3 (tmp
, cc_op0
, cc_op1
));
5307 emit_insn (gen_selv2sf4
5308 (max
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5309 emit_insn (gen_subv2sf3 (tmp
, cc_op1
, cc_op0
));
5310 emit_insn (gen_selv2sf4
5311 (min
, tmp
, cc_op0
, cc_op1
, CONST0_RTX (SFmode
)));
5312 emit_insn (gen_subv2sf3 (tmp1
, min
, max
));
5313 emit_insn (gen_selv2sf4 (dest
, tmp1
, op0
, op1
, CONST0_RTX (SFmode
)));
5316 paired_emit_vector_compare (EQ
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5319 paired_emit_vector_compare (LE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5322 paired_emit_vector_compare (LT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5325 paired_emit_vector_compare (GE
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5328 paired_emit_vector_compare (GT
, dest
, op1
, op0
, cc_op0
, cc_op1
);
5337 /* Emit vector conditional expression.
5338 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
5339 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
5342 paired_emit_vector_cond_expr (rtx dest
, rtx op1
, rtx op2
,
5343 rtx cond
, rtx cc_op0
, rtx cc_op1
)
5345 enum rtx_code rcode
= GET_CODE (cond
);
5347 if (!TARGET_PAIRED_FLOAT
)
5350 paired_emit_vector_compare (rcode
, dest
, op1
, op2
, cc_op0
, cc_op1
);
5355 /* Initialize vector TARGET to VALS. */
5358 rs6000_expand_vector_init (rtx target
, rtx vals
)
5360 enum machine_mode mode
= GET_MODE (target
);
5361 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5362 int n_elts
= GET_MODE_NUNITS (mode
);
5363 int n_var
= 0, one_var
= -1;
5364 bool all_same
= true, all_const_zero
= true;
5368 for (i
= 0; i
< n_elts
; ++i
)
5370 x
= XVECEXP (vals
, 0, i
);
5371 if (!CONSTANT_P (x
))
5372 ++n_var
, one_var
= i
;
5373 else if (x
!= CONST0_RTX (inner_mode
))
5374 all_const_zero
= false;
5376 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
5382 rtx const_vec
= gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0));
5383 bool int_vector_p
= (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
);
5384 if ((int_vector_p
|| TARGET_VSX
) && all_const_zero
)
5386 /* Zero register. */
5387 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5388 gen_rtx_XOR (mode
, target
, target
)));
5391 else if (int_vector_p
&& easy_vector_constant (const_vec
, mode
))
5393 /* Splat immediate. */
5394 emit_insn (gen_rtx_SET (VOIDmode
, target
, const_vec
));
5399 /* Load from constant pool. */
5400 emit_move_insn (target
, const_vec
);
5405 /* Double word values on VSX can use xxpermdi or lxvdsx. */
5406 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5408 rtx op0
= XVECEXP (vals
, 0, 0);
5409 rtx op1
= XVECEXP (vals
, 0, 1);
5412 if (!MEM_P (op0
) && !REG_P (op0
))
5413 op0
= force_reg (inner_mode
, op0
);
5414 if (mode
== V2DFmode
)
5415 emit_insn (gen_vsx_splat_v2df (target
, op0
));
5417 emit_insn (gen_vsx_splat_v2di (target
, op0
));
5421 op0
= force_reg (inner_mode
, op0
);
5422 op1
= force_reg (inner_mode
, op1
);
5423 if (mode
== V2DFmode
)
5424 emit_insn (gen_vsx_concat_v2df (target
, op0
, op1
));
5426 emit_insn (gen_vsx_concat_v2di (target
, op0
, op1
));
5431 /* With single precision floating point on VSX, know that internally single
5432 precision is actually represented as a double, and either make 2 V2DF
5433 vectors, and convert these vectors to single precision, or do one
5434 conversion, and splat the result to the other elements. */
5435 if (mode
== V4SFmode
&& VECTOR_MEM_VSX_P (mode
))
5439 rtx freg
= gen_reg_rtx (V4SFmode
);
5440 rtx sreg
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5441 rtx cvt
= ((TARGET_XSCVDPSPN
)
5442 ? gen_vsx_xscvdpspn_scalar (freg
, sreg
)
5443 : gen_vsx_xscvdpsp_scalar (freg
, sreg
));
5446 emit_insn (gen_vsx_xxspltw_v4sf (target
, freg
, const0_rtx
));
5450 rtx dbl_even
= gen_reg_rtx (V2DFmode
);
5451 rtx dbl_odd
= gen_reg_rtx (V2DFmode
);
5452 rtx flt_even
= gen_reg_rtx (V4SFmode
);
5453 rtx flt_odd
= gen_reg_rtx (V4SFmode
);
5454 rtx op0
= force_reg (SFmode
, XVECEXP (vals
, 0, 0));
5455 rtx op1
= force_reg (SFmode
, XVECEXP (vals
, 0, 1));
5456 rtx op2
= force_reg (SFmode
, XVECEXP (vals
, 0, 2));
5457 rtx op3
= force_reg (SFmode
, XVECEXP (vals
, 0, 3));
5459 emit_insn (gen_vsx_concat_v2sf (dbl_even
, op0
, op1
));
5460 emit_insn (gen_vsx_concat_v2sf (dbl_odd
, op2
, op3
));
5461 emit_insn (gen_vsx_xvcvdpsp (flt_even
, dbl_even
));
5462 emit_insn (gen_vsx_xvcvdpsp (flt_odd
, dbl_odd
));
5463 rs6000_expand_extract_even (target
, flt_even
, flt_odd
);
5468 /* Store value to stack temp. Load vector element. Splat. However, splat
5469 of 64-bit items is not supported on Altivec. */
5470 if (all_same
&& GET_MODE_SIZE (inner_mode
) <= 4)
5473 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5474 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0),
5475 XVECEXP (vals
, 0, 0));
5476 x
= gen_rtx_UNSPEC (VOIDmode
,
5477 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5478 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5480 gen_rtx_SET (VOIDmode
,
5483 field
= (BYTES_BIG_ENDIAN
? const0_rtx
5484 : GEN_INT (GET_MODE_NUNITS (mode
) - 1));
5485 x
= gen_rtx_VEC_SELECT (inner_mode
, target
,
5486 gen_rtx_PARALLEL (VOIDmode
,
5487 gen_rtvec (1, field
)));
5488 emit_insn (gen_rtx_SET (VOIDmode
, target
,
5489 gen_rtx_VEC_DUPLICATE (mode
, x
)));
5493 /* One field is non-constant. Load constant then overwrite
5497 rtx copy
= copy_rtx (vals
);
5499 /* Load constant part of vector, substitute neighboring value for
5501 XVECEXP (copy
, 0, one_var
) = XVECEXP (vals
, 0, (one_var
+ 1) % n_elts
);
5502 rs6000_expand_vector_init (target
, copy
);
5504 /* Insert variable. */
5505 rs6000_expand_vector_set (target
, XVECEXP (vals
, 0, one_var
), one_var
);
5509 /* Construct the vector in memory one field at a time
5510 and load the whole vector. */
5511 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5512 for (i
= 0; i
< n_elts
; i
++)
5513 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
5514 i
* GET_MODE_SIZE (inner_mode
)),
5515 XVECEXP (vals
, 0, i
));
5516 emit_move_insn (target
, mem
);
5519 /* Set field ELT of TARGET to VAL. */
5522 rs6000_expand_vector_set (rtx target
, rtx val
, int elt
)
5524 enum machine_mode mode
= GET_MODE (target
);
5525 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5526 rtx reg
= gen_reg_rtx (mode
);
5528 int width
= GET_MODE_SIZE (inner_mode
);
5531 if (VECTOR_MEM_VSX_P (mode
) && (mode
== V2DFmode
|| mode
== V2DImode
))
5533 rtx (*set_func
) (rtx
, rtx
, rtx
, rtx
)
5534 = ((mode
== V2DFmode
) ? gen_vsx_set_v2df
: gen_vsx_set_v2di
);
5535 emit_insn (set_func (target
, target
, val
, GEN_INT (elt
)));
5539 /* Load single variable value. */
5540 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (inner_mode
));
5541 emit_move_insn (adjust_address_nv (mem
, inner_mode
, 0), val
);
5542 x
= gen_rtx_UNSPEC (VOIDmode
,
5543 gen_rtvec (1, const0_rtx
), UNSPEC_LVE
);
5544 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
5546 gen_rtx_SET (VOIDmode
,
5550 /* Linear sequence. */
5551 mask
= gen_rtx_PARALLEL (V16QImode
, rtvec_alloc (16));
5552 for (i
= 0; i
< 16; ++i
)
5553 XVECEXP (mask
, 0, i
) = GEN_INT (i
);
5555 /* Set permute mask to insert element into target. */
5556 for (i
= 0; i
< width
; ++i
)
5557 XVECEXP (mask
, 0, elt
*width
+ i
)
5558 = GEN_INT (i
+ 0x10);
5559 x
= gen_rtx_CONST_VECTOR (V16QImode
, XVEC (mask
, 0));
5561 if (BYTES_BIG_ENDIAN
)
5562 x
= gen_rtx_UNSPEC (mode
,
5563 gen_rtvec (3, target
, reg
,
5564 force_reg (V16QImode
, x
)),
5568 /* Invert selector. */
5569 rtx splat
= gen_rtx_VEC_DUPLICATE (V16QImode
,
5570 gen_rtx_CONST_INT (QImode
, -1));
5571 rtx tmp
= gen_reg_rtx (V16QImode
);
5572 emit_move_insn (tmp
, splat
);
5573 x
= gen_rtx_MINUS (V16QImode
, tmp
, force_reg (V16QImode
, x
));
5574 emit_move_insn (tmp
, x
);
5576 /* Permute with operands reversed and adjusted selector. */
5577 x
= gen_rtx_UNSPEC (mode
, gen_rtvec (3, reg
, target
, tmp
),
5581 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
5584 /* Extract field ELT from VEC into TARGET. */
5587 rs6000_expand_vector_extract (rtx target
, rtx vec
, int elt
)
5589 enum machine_mode mode
= GET_MODE (vec
);
5590 enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
5593 if (VECTOR_MEM_VSX_P (mode
))
5600 emit_insn (gen_vsx_extract_v2df (target
, vec
, GEN_INT (elt
)));
5603 emit_insn (gen_vsx_extract_v2di (target
, vec
, GEN_INT (elt
)));
5606 emit_insn (gen_vsx_extract_v4sf (target
, vec
, GEN_INT (elt
)));
5611 /* Allocate mode-sized buffer. */
5612 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
5614 emit_move_insn (mem
, vec
);
5616 /* Add offset to field within buffer matching vector element. */
5617 mem
= adjust_address_nv (mem
, inner_mode
, elt
* GET_MODE_SIZE (inner_mode
));
5619 emit_move_insn (target
, adjust_address_nv (mem
, inner_mode
, 0));
5622 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
5623 implement ANDing by the mask IN. */
5625 build_mask64_2_operands (rtx in
, rtx
*out
)
5627 unsigned HOST_WIDE_INT c
, lsb
, m1
, m2
;
5630 gcc_assert (GET_CODE (in
) == CONST_INT
);
5635 /* Assume c initially something like 0x00fff000000fffff. The idea
5636 is to rotate the word so that the middle ^^^^^^ group of zeros
5637 is at the MS end and can be cleared with an rldicl mask. We then
5638 rotate back and clear off the MS ^^ group of zeros with a
5640 c
= ~c
; /* c == 0xff000ffffff00000 */
5641 lsb
= c
& -c
; /* lsb == 0x0000000000100000 */
5642 m1
= -lsb
; /* m1 == 0xfffffffffff00000 */
5643 c
= ~c
; /* c == 0x00fff000000fffff */
5644 c
&= -lsb
; /* c == 0x00fff00000000000 */
5645 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5646 c
= ~c
; /* c == 0xff000fffffffffff */
5647 c
&= -lsb
; /* c == 0xff00000000000000 */
5649 while ((lsb
>>= 1) != 0)
5650 shift
++; /* shift == 44 on exit from loop */
5651 m1
<<= 64 - shift
; /* m1 == 0xffffff0000000000 */
5652 m1
= ~m1
; /* m1 == 0x000000ffffffffff */
5653 m2
= ~c
; /* m2 == 0x00ffffffffffffff */
5657 /* Assume c initially something like 0xff000f0000000000. The idea
5658 is to rotate the word so that the ^^^ middle group of zeros
5659 is at the LS end and can be cleared with an rldicr mask. We then
5660 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
5662 lsb
= c
& -c
; /* lsb == 0x0000010000000000 */
5663 m2
= -lsb
; /* m2 == 0xffffff0000000000 */
5664 c
= ~c
; /* c == 0x00fff0ffffffffff */
5665 c
&= -lsb
; /* c == 0x00fff00000000000 */
5666 lsb
= c
& -c
; /* lsb == 0x0000100000000000 */
5667 c
= ~c
; /* c == 0xff000fffffffffff */
5668 c
&= -lsb
; /* c == 0xff00000000000000 */
5670 while ((lsb
>>= 1) != 0)
5671 shift
++; /* shift == 44 on exit from loop */
5672 m1
= ~c
; /* m1 == 0x00ffffffffffffff */
5673 m1
>>= shift
; /* m1 == 0x0000000000000fff */
5674 m1
= ~m1
; /* m1 == 0xfffffffffffff000 */
5677 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
5678 masks will be all 1's. We are guaranteed more than one transition. */
5679 out
[0] = GEN_INT (64 - shift
);
5680 out
[1] = GEN_INT (m1
);
5681 out
[2] = GEN_INT (shift
);
5682 out
[3] = GEN_INT (m2
);
5685 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
5688 invalid_e500_subreg (rtx op
, enum machine_mode mode
)
5690 if (TARGET_E500_DOUBLE
)
5692 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
5693 subreg:TI and reg:TF. Decimal float modes are like integer
5694 modes (only low part of each register used) for this
5696 if (GET_CODE (op
) == SUBREG
5697 && (mode
== SImode
|| mode
== DImode
|| mode
== TImode
5698 || mode
== DDmode
|| mode
== TDmode
|| mode
== PTImode
)
5699 && REG_P (SUBREG_REG (op
))
5700 && (GET_MODE (SUBREG_REG (op
)) == DFmode
5701 || GET_MODE (SUBREG_REG (op
)) == TFmode
))
5704 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
5706 if (GET_CODE (op
) == SUBREG
5707 && (mode
== DFmode
|| mode
== TFmode
)
5708 && REG_P (SUBREG_REG (op
))
5709 && (GET_MODE (SUBREG_REG (op
)) == DImode
5710 || GET_MODE (SUBREG_REG (op
)) == TImode
5711 || GET_MODE (SUBREG_REG (op
)) == PTImode
5712 || GET_MODE (SUBREG_REG (op
)) == DDmode
5713 || GET_MODE (SUBREG_REG (op
)) == TDmode
))
5718 && GET_CODE (op
) == SUBREG
5720 && REG_P (SUBREG_REG (op
))
5721 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op
))))
5727 /* Return alignment of TYPE. Existing alignment is ALIGN. HOW
5728 selects whether the alignment is abi mandated, optional, or
5729 both abi and optional alignment. */
5732 rs6000_data_alignment (tree type
, unsigned int align
, enum data_align how
)
5734 if (how
!= align_opt
)
5736 if (TREE_CODE (type
) == VECTOR_TYPE
)
5738 if ((TARGET_SPE
&& SPE_VECTOR_MODE (TYPE_MODE (type
)))
5739 || (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (TYPE_MODE (type
))))
5744 else if (align
< 128)
5747 else if (TARGET_E500_DOUBLE
5748 && TREE_CODE (type
) == REAL_TYPE
5749 && TYPE_MODE (type
) == DFmode
)
5756 if (how
!= align_abi
)
5758 if (TREE_CODE (type
) == ARRAY_TYPE
5759 && TYPE_MODE (TREE_TYPE (type
)) == QImode
)
5761 if (align
< BITS_PER_WORD
)
5762 align
= BITS_PER_WORD
;
5769 /* AIX increases natural record alignment to doubleword if the first
5770 field is an FP double while the FP fields remain word aligned. */
5773 rs6000_special_round_type_align (tree type
, unsigned int computed
,
5774 unsigned int specified
)
5776 unsigned int align
= MAX (computed
, specified
);
5777 tree field
= TYPE_FIELDS (type
);
5779 /* Skip all non field decls */
5780 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5781 field
= DECL_CHAIN (field
);
5783 if (field
!= NULL
&& field
!= type
)
5785 type
= TREE_TYPE (field
);
5786 while (TREE_CODE (type
) == ARRAY_TYPE
)
5787 type
= TREE_TYPE (type
);
5789 if (type
!= error_mark_node
&& TYPE_MODE (type
) == DFmode
)
5790 align
= MAX (align
, 64);
5796 /* Darwin increases record alignment to the natural alignment of
5800 darwin_rs6000_special_round_type_align (tree type
, unsigned int computed
,
5801 unsigned int specified
)
5803 unsigned int align
= MAX (computed
, specified
);
5805 if (TYPE_PACKED (type
))
5808 /* Find the first field, looking down into aggregates. */
5810 tree field
= TYPE_FIELDS (type
);
5811 /* Skip all non field decls */
5812 while (field
!= NULL
&& TREE_CODE (field
) != FIELD_DECL
)
5813 field
= DECL_CHAIN (field
);
5816 /* A packed field does not contribute any extra alignment. */
5817 if (DECL_PACKED (field
))
5819 type
= TREE_TYPE (field
);
5820 while (TREE_CODE (type
) == ARRAY_TYPE
)
5821 type
= TREE_TYPE (type
);
5822 } while (AGGREGATE_TYPE_P (type
));
5824 if (! AGGREGATE_TYPE_P (type
) && type
!= error_mark_node
)
5825 align
= MAX (align
, TYPE_ALIGN (type
));
5830 /* Return 1 for an operand in small memory on V.4/eabi. */
5833 small_data_operand (rtx op ATTRIBUTE_UNUSED
,
5834 enum machine_mode mode ATTRIBUTE_UNUSED
)
5839 if (rs6000_sdata
== SDATA_NONE
|| rs6000_sdata
== SDATA_DATA
)
5842 if (DEFAULT_ABI
!= ABI_V4
)
5845 /* Vector and float memory instructions have a limited offset on the
5846 SPE, so using a vector or float variable directly as an operand is
5849 && (SPE_VECTOR_MODE (mode
) || FLOAT_MODE_P (mode
)))
5852 if (GET_CODE (op
) == SYMBOL_REF
)
5855 else if (GET_CODE (op
) != CONST
5856 || GET_CODE (XEXP (op
, 0)) != PLUS
5857 || GET_CODE (XEXP (XEXP (op
, 0), 0)) != SYMBOL_REF
5858 || GET_CODE (XEXP (XEXP (op
, 0), 1)) != CONST_INT
)
5863 rtx sum
= XEXP (op
, 0);
5864 HOST_WIDE_INT summand
;
5866 /* We have to be careful here, because it is the referenced address
5867 that must be 32k from _SDA_BASE_, not just the symbol. */
5868 summand
= INTVAL (XEXP (sum
, 1));
5869 if (summand
< 0 || summand
> g_switch_value
)
5872 sym_ref
= XEXP (sum
, 0);
5875 return SYMBOL_REF_SMALL_P (sym_ref
);
5881 /* Return true if either operand is a general purpose register. */
5884 gpr_or_gpr_p (rtx op0
, rtx op1
)
5886 return ((REG_P (op0
) && INT_REGNO_P (REGNO (op0
)))
5887 || (REG_P (op1
) && INT_REGNO_P (REGNO (op1
))));
5890 /* Return true if this is a move direct operation between GPR registers and
5891 floating point/VSX registers. */
5894 direct_move_p (rtx op0
, rtx op1
)
5898 if (!REG_P (op0
) || !REG_P (op1
))
5901 if (!TARGET_DIRECT_MOVE
&& !TARGET_MFPGPR
)
5904 regno0
= REGNO (op0
);
5905 regno1
= REGNO (op1
);
5906 if (regno0
>= FIRST_PSEUDO_REGISTER
|| regno1
>= FIRST_PSEUDO_REGISTER
)
5909 if (INT_REGNO_P (regno0
))
5910 return (TARGET_DIRECT_MOVE
) ? VSX_REGNO_P (regno1
) : FP_REGNO_P (regno1
);
5912 else if (INT_REGNO_P (regno1
))
5914 if (TARGET_MFPGPR
&& FP_REGNO_P (regno0
))
5917 else if (TARGET_DIRECT_MOVE
&& VSX_REGNO_P (regno0
))
5924 /* Return true if this is a load or store quad operation. */
5927 quad_load_store_p (rtx op0
, rtx op1
)
5931 if (!TARGET_QUAD_MEMORY
)
5934 else if (REG_P (op0
) && MEM_P (op1
))
5935 ret
= (quad_int_reg_operand (op0
, GET_MODE (op0
))
5936 && quad_memory_operand (op1
, GET_MODE (op1
))
5937 && !reg_overlap_mentioned_p (op0
, op1
));
5939 else if (MEM_P (op0
) && REG_P (op1
))
5940 ret
= (quad_memory_operand (op0
, GET_MODE (op0
))
5941 && quad_int_reg_operand (op1
, GET_MODE (op1
)));
5946 if (TARGET_DEBUG_ADDR
)
5948 fprintf (stderr
, "\n========== quad_load_store, return %s\n",
5949 ret
? "true" : "false");
5950 debug_rtx (gen_rtx_SET (VOIDmode
, op0
, op1
));
5956 /* Given an address, return a constant offset term if one exists. */
5959 address_offset (rtx op
)
5961 if (GET_CODE (op
) == PRE_INC
5962 || GET_CODE (op
) == PRE_DEC
)
5964 else if (GET_CODE (op
) == PRE_MODIFY
5965 || GET_CODE (op
) == LO_SUM
)
5968 if (GET_CODE (op
) == CONST
)
5971 if (GET_CODE (op
) == PLUS
)
5974 if (CONST_INT_P (op
))
5980 /* Return true if the MEM operand is a memory operand suitable for use
5981 with a (full width, possibly multiple) gpr load/store. On
5982 powerpc64 this means the offset must be divisible by 4.
5983 Implements 'Y' constraint.
5985 Accept direct, indexed, offset, lo_sum and tocref. Since this is
5986 a constraint function we know the operand has satisfied a suitable
5987 memory predicate. Also accept some odd rtl generated by reload
5988 (see rs6000_legitimize_reload_address for various forms). It is
5989 important that reload rtl be accepted by appropriate constraints
5990 but not by the operand predicate.
5992 Offsetting a lo_sum should not be allowed, except where we know by
5993 alignment that a 32k boundary is not crossed, but see the ???
5994 comment in rs6000_legitimize_reload_address. Note that by
5995 "offsetting" here we mean a further offset to access parts of the
5996 MEM. It's fine to have a lo_sum where the inner address is offset
5997 from a sym, since the same sym+offset will appear in the high part
5998 of the address calculation. */
6001 mem_operand_gpr (rtx op
, enum machine_mode mode
)
6003 unsigned HOST_WIDE_INT offset
;
6005 rtx addr
= XEXP (op
, 0);
6007 op
= address_offset (addr
);
6011 offset
= INTVAL (op
);
6012 if (TARGET_POWERPC64
&& (offset
& 3) != 0)
6015 extra
= GET_MODE_SIZE (mode
) - UNITS_PER_WORD
;
6016 gcc_assert (extra
>= 0);
6018 if (GET_CODE (addr
) == LO_SUM
)
6019 /* For lo_sum addresses, we must allow any offset except one that
6020 causes a wrap, so test only the low 16 bits. */
6021 offset
= ((offset
& 0xffff) ^ 0x8000) - 0x8000;
6023 return offset
+ 0x8000 < 0x10000u
- extra
;
6026 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address_p. */
6029 reg_offset_addressing_ok_p (enum machine_mode mode
)
6040 /* AltiVec/VSX vector modes. Only reg+reg addressing is valid. While
6041 TImode is not a vector mode, if we want to use the VSX registers to
6042 move it around, we need to restrict ourselves to reg+reg
6044 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
6052 /* Paired vector modes. Only reg+reg addressing is valid. */
6053 if (TARGET_PAIRED_FLOAT
)
6058 /* If we can do direct load/stores of SDmode, restrict it to reg+reg
6059 addressing for the LFIWZX and STFIWX instructions. */
6060 if (TARGET_NO_SDMODE_STACK
)
6072 virtual_stack_registers_memory_p (rtx op
)
6076 if (GET_CODE (op
) == REG
)
6077 regnum
= REGNO (op
);
6079 else if (GET_CODE (op
) == PLUS
6080 && GET_CODE (XEXP (op
, 0)) == REG
6081 && GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6082 regnum
= REGNO (XEXP (op
, 0));
6087 return (regnum
>= FIRST_VIRTUAL_REGISTER
6088 && regnum
<= LAST_VIRTUAL_POINTER_REGISTER
);
6091 /* Return true if a MODE sized memory accesses to OP plus OFFSET
6092 is known to not straddle a 32k boundary. */
6095 offsettable_ok_by_alignment (rtx op
, HOST_WIDE_INT offset
,
6096 enum machine_mode mode
)
6099 unsigned HOST_WIDE_INT dsize
, dalign
, lsb
, mask
;
6101 if (GET_CODE (op
) != SYMBOL_REF
)
6104 dsize
= GET_MODE_SIZE (mode
);
6105 decl
= SYMBOL_REF_DECL (op
);
6111 /* -fsection-anchors loses the original SYMBOL_REF_DECL when
6112 replacing memory addresses with an anchor plus offset. We
6113 could find the decl by rummaging around in the block->objects
6114 VEC for the given offset but that seems like too much work. */
6115 dalign
= BITS_PER_UNIT
;
6116 if (SYMBOL_REF_HAS_BLOCK_INFO_P (op
)
6117 && SYMBOL_REF_ANCHOR_P (op
)
6118 && SYMBOL_REF_BLOCK (op
) != NULL
)
6120 struct object_block
*block
= SYMBOL_REF_BLOCK (op
);
6122 dalign
= block
->alignment
;
6123 offset
+= SYMBOL_REF_BLOCK_OFFSET (op
);
6125 else if (CONSTANT_POOL_ADDRESS_P (op
))
6127 /* It would be nice to have get_pool_align().. */
6128 enum machine_mode cmode
= get_pool_mode (op
);
6130 dalign
= GET_MODE_ALIGNMENT (cmode
);
6133 else if (DECL_P (decl
))
6135 dalign
= DECL_ALIGN (decl
);
6139 /* Allow BLKmode when the entire object is known to not
6140 cross a 32k boundary. */
6141 if (!DECL_SIZE_UNIT (decl
))
6144 if (!tree_fits_uhwi_p (DECL_SIZE_UNIT (decl
)))
6147 dsize
= tree_to_uhwi (DECL_SIZE_UNIT (decl
));
6151 return dalign
/ BITS_PER_UNIT
>= dsize
;
6156 type
= TREE_TYPE (decl
);
6158 dalign
= TYPE_ALIGN (type
);
6159 if (CONSTANT_CLASS_P (decl
))
6160 dalign
= CONSTANT_ALIGNMENT (decl
, dalign
);
6162 dalign
= DATA_ALIGNMENT (decl
, dalign
);
6166 /* BLKmode, check the entire object. */
6167 if (TREE_CODE (decl
) == STRING_CST
)
6168 dsize
= TREE_STRING_LENGTH (decl
);
6169 else if (TYPE_SIZE_UNIT (type
)
6170 && tree_fits_uhwi_p (TYPE_SIZE_UNIT (type
)))
6171 dsize
= tree_to_uhwi (TYPE_SIZE_UNIT (type
));
6177 return dalign
/ BITS_PER_UNIT
>= dsize
;
6181 /* Find how many bits of the alignment we know for this access. */
6182 mask
= dalign
/ BITS_PER_UNIT
- 1;
6183 lsb
= offset
& -offset
;
6187 return dalign
>= dsize
;
6191 constant_pool_expr_p (rtx op
)
6195 split_const (op
, &base
, &offset
);
6196 return (GET_CODE (base
) == SYMBOL_REF
6197 && CONSTANT_POOL_ADDRESS_P (base
)
6198 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (base
), Pmode
));
6201 static const_rtx tocrel_base
, tocrel_offset
;
6203 /* Return true if OP is a toc pointer relative address (the output
6204 of create_TOC_reference). If STRICT, do not match high part or
6205 non-split -mcmodel=large/medium toc pointer relative addresses. */
6208 toc_relative_expr_p (const_rtx op
, bool strict
)
6213 if (TARGET_CMODEL
!= CMODEL_SMALL
)
6215 /* Only match the low part. */
6216 if (GET_CODE (op
) == LO_SUM
6217 && REG_P (XEXP (op
, 0))
6218 && INT_REG_OK_FOR_BASE_P (XEXP (op
, 0), strict
))
6225 tocrel_offset
= const0_rtx
;
6226 if (GET_CODE (op
) == PLUS
&& add_cint_operand (XEXP (op
, 1), GET_MODE (op
)))
6228 tocrel_base
= XEXP (op
, 0);
6229 tocrel_offset
= XEXP (op
, 1);
6232 return (GET_CODE (tocrel_base
) == UNSPEC
6233 && XINT (tocrel_base
, 1) == UNSPEC_TOCREL
);
6236 /* Return true if X is a constant pool address, and also for cmodel=medium
6237 if X is a toc-relative address known to be offsettable within MODE. */
6240 legitimate_constant_pool_address_p (const_rtx x
, enum machine_mode mode
,
6243 return (toc_relative_expr_p (x
, strict
)
6244 && (TARGET_CMODEL
!= CMODEL_MEDIUM
6245 || constant_pool_expr_p (XVECEXP (tocrel_base
, 0, 0))
6247 || offsettable_ok_by_alignment (XVECEXP (tocrel_base
, 0, 0),
6248 INTVAL (tocrel_offset
), mode
)));
6252 legitimate_small_data_p (enum machine_mode mode
, rtx x
)
6254 return (DEFAULT_ABI
== ABI_V4
6255 && !flag_pic
&& !TARGET_TOC
6256 && (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
)
6257 && small_data_operand (x
, mode
));
6260 /* SPE offset addressing is limited to 5-bits worth of double words. */
6261 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
6264 rs6000_legitimate_offset_address_p (enum machine_mode mode
, rtx x
,
6265 bool strict
, bool worst_case
)
6267 unsigned HOST_WIDE_INT offset
;
6270 if (GET_CODE (x
) != PLUS
)
6272 if (!REG_P (XEXP (x
, 0)))
6274 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6276 if (!reg_offset_addressing_ok_p (mode
))
6277 return virtual_stack_registers_memory_p (x
);
6278 if (legitimate_constant_pool_address_p (x
, mode
, strict
|| lra_in_progress
))
6280 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6283 offset
= INTVAL (XEXP (x
, 1));
6291 /* SPE vector modes. */
6292 return SPE_CONST_OFFSET_OK (offset
);
6297 /* On e500v2, we may have:
6299 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
6301 Which gets addressed with evldd instructions. */
6302 if (TARGET_E500_DOUBLE
)
6303 return SPE_CONST_OFFSET_OK (offset
);
6305 /* If we are using VSX scalar loads, restrict ourselves to reg+reg
6307 if (VECTOR_MEM_VSX_P (mode
))
6312 if (!TARGET_POWERPC64
)
6314 else if (offset
& 3)
6322 if (TARGET_E500_DOUBLE
)
6323 return (SPE_CONST_OFFSET_OK (offset
)
6324 && SPE_CONST_OFFSET_OK (offset
+ 8));
6329 if (!TARGET_POWERPC64
)
6331 else if (offset
& 3)
6340 return offset
< 0x10000 - extra
;
6344 legitimate_indexed_address_p (rtx x
, int strict
)
6348 if (GET_CODE (x
) != PLUS
)
6354 /* Recognize the rtl generated by reload which we know will later be
6355 replaced with proper base and index regs. */
6357 && reload_in_progress
6358 && (REG_P (op0
) || GET_CODE (op0
) == PLUS
)
6362 return (REG_P (op0
) && REG_P (op1
)
6363 && ((INT_REG_OK_FOR_BASE_P (op0
, strict
)
6364 && INT_REG_OK_FOR_INDEX_P (op1
, strict
))
6365 || (INT_REG_OK_FOR_BASE_P (op1
, strict
)
6366 && INT_REG_OK_FOR_INDEX_P (op0
, strict
))));
6370 avoiding_indexed_address_p (enum machine_mode mode
)
6372 /* Avoid indexed addressing for modes that have non-indexed
6373 load/store instruction forms. */
6374 return (TARGET_AVOID_XFORM
&& VECTOR_MEM_NONE_P (mode
));
6378 legitimate_indirect_address_p (rtx x
, int strict
)
6380 return GET_CODE (x
) == REG
&& INT_REG_OK_FOR_BASE_P (x
, strict
);
6384 macho_lo_sum_memory_operand (rtx x
, enum machine_mode mode
)
6386 if (!TARGET_MACHO
|| !flag_pic
6387 || mode
!= SImode
|| GET_CODE (x
) != MEM
)
6391 if (GET_CODE (x
) != LO_SUM
)
6393 if (GET_CODE (XEXP (x
, 0)) != REG
)
6395 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 0))
6399 return CONSTANT_P (x
);
6403 legitimate_lo_sum_address_p (enum machine_mode mode
, rtx x
, int strict
)
6405 if (GET_CODE (x
) != LO_SUM
)
6407 if (GET_CODE (XEXP (x
, 0)) != REG
)
6409 if (!INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), strict
))
6411 /* Restrict addressing for DI because of our SUBREG hackery. */
6412 if (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
6416 if (TARGET_ELF
|| TARGET_MACHO
)
6420 if (DEFAULT_ABI
== ABI_V4
&& flag_pic
)
6422 /* LRA don't use LEGITIMIZE_RELOAD_ADDRESS as it usually calls
6423 push_reload from reload pass code. LEGITIMIZE_RELOAD_ADDRESS
6424 recognizes some LO_SUM addresses as valid although this
6425 function says opposite. In most cases, LRA through different
6426 transformations can generate correct code for address reloads.
6427 It can not manage only some LO_SUM cases. So we need to add
6428 code analogous to one in rs6000_legitimize_reload_address for
6429 LOW_SUM here saying that some addresses are still valid. */
6430 large_toc_ok
= (lra_in_progress
&& TARGET_CMODEL
!= CMODEL_SMALL
6431 && small_toc_ref (x
, VOIDmode
));
6432 if (TARGET_TOC
&& ! large_toc_ok
)
6434 if (GET_MODE_NUNITS (mode
) != 1)
6436 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
6437 && !(/* ??? Assume floating point reg based on mode? */
6438 TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
6439 && (mode
== DFmode
|| mode
== DDmode
)))
6442 return CONSTANT_P (x
) || large_toc_ok
;
6449 /* Try machine-dependent ways of modifying an illegitimate address
6450 to be legitimate. If we find one, return the new, valid address.
6451 This is used from only one place: `memory_address' in explow.c.
6453 OLDX is the address as it was before break_out_memory_refs was
6454 called. In some cases it is useful to look at this to decide what
6457 It is always safe for this function to do nothing. It exists to
6458 recognize opportunities to optimize the output.
6460 On RS/6000, first check for the sum of a register with a constant
6461 integer that is out of range. If so, generate code to add the
6462 constant with the low-order 16 bits masked to the register and force
6463 this result into another register (this can be done with `cau').
6464 Then generate an address of REG+(CONST&0xffff), allowing for the
6465 possibility of bit 16 being a one.
6467 Then check for the sum of a register and something not constant, try to
6468 load the other things into a register and return the sum. */
6471 rs6000_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
6472 enum machine_mode mode
)
6476 if (!reg_offset_addressing_ok_p (mode
))
6478 if (virtual_stack_registers_memory_p (x
))
6481 /* In theory we should not be seeing addresses of the form reg+0,
6482 but just in case it is generated, optimize it away. */
6483 if (GET_CODE (x
) == PLUS
&& XEXP (x
, 1) == const0_rtx
)
6484 return force_reg (Pmode
, XEXP (x
, 0));
6486 /* For TImode with load/store quad, restrict addresses to just a single
6487 pointer, so it works with both GPRs and VSX registers. */
6488 /* Make sure both operands are registers. */
6489 else if (GET_CODE (x
) == PLUS
6490 && (mode
!= TImode
|| !TARGET_QUAD_MEMORY
))
6491 return gen_rtx_PLUS (Pmode
,
6492 force_reg (Pmode
, XEXP (x
, 0)),
6493 force_reg (Pmode
, XEXP (x
, 1)));
6495 return force_reg (Pmode
, x
);
6497 if (GET_CODE (x
) == SYMBOL_REF
)
6499 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
6501 return rs6000_legitimize_tls_address (x
, model
);
6511 /* As in legitimate_offset_address_p we do not assume
6512 worst-case. The mode here is just a hint as to the registers
6513 used. A TImode is usually in gprs, but may actually be in
6514 fprs. Leave worst-case scenario for reload to handle via
6515 insn constraints. PTImode is only GPRs. */
6522 if (GET_CODE (x
) == PLUS
6523 && GET_CODE (XEXP (x
, 0)) == REG
6524 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6525 && ((unsigned HOST_WIDE_INT
) (INTVAL (XEXP (x
, 1)) + 0x8000)
6527 && !(SPE_VECTOR_MODE (mode
)
6528 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)))
6530 HOST_WIDE_INT high_int
, low_int
;
6532 low_int
= ((INTVAL (XEXP (x
, 1)) & 0xffff) ^ 0x8000) - 0x8000;
6533 if (low_int
>= 0x8000 - extra
)
6535 high_int
= INTVAL (XEXP (x
, 1)) - low_int
;
6536 sum
= force_operand (gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6537 GEN_INT (high_int
)), 0);
6538 return plus_constant (Pmode
, sum
, low_int
);
6540 else if (GET_CODE (x
) == PLUS
6541 && GET_CODE (XEXP (x
, 0)) == REG
6542 && GET_CODE (XEXP (x
, 1)) != CONST_INT
6543 && GET_MODE_NUNITS (mode
) == 1
6544 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6545 || (/* ??? Assume floating point reg based on mode? */
6546 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6547 && (mode
== DFmode
|| mode
== DDmode
)))
6548 && !avoiding_indexed_address_p (mode
))
6550 return gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
6551 force_reg (Pmode
, force_operand (XEXP (x
, 1), 0)));
6553 else if (SPE_VECTOR_MODE (mode
)
6554 || (TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
))
6558 /* We accept [reg + reg] and [reg + OFFSET]. */
6560 if (GET_CODE (x
) == PLUS
)
6562 rtx op1
= XEXP (x
, 0);
6563 rtx op2
= XEXP (x
, 1);
6566 op1
= force_reg (Pmode
, op1
);
6568 if (GET_CODE (op2
) != REG
6569 && (GET_CODE (op2
) != CONST_INT
6570 || !SPE_CONST_OFFSET_OK (INTVAL (op2
))
6571 || (GET_MODE_SIZE (mode
) > 8
6572 && !SPE_CONST_OFFSET_OK (INTVAL (op2
) + 8))))
6573 op2
= force_reg (Pmode
, op2
);
6575 /* We can't always do [reg + reg] for these, because [reg +
6576 reg + offset] is not a legitimate addressing mode. */
6577 y
= gen_rtx_PLUS (Pmode
, op1
, op2
);
6579 if ((GET_MODE_SIZE (mode
) > 8 || mode
== DDmode
) && REG_P (op2
))
6580 return force_reg (Pmode
, y
);
6585 return force_reg (Pmode
, x
);
6587 else if ((TARGET_ELF
6589 || !MACHO_DYNAMIC_NO_PIC_P
6595 && GET_CODE (x
) != CONST_INT
6596 && GET_CODE (x
) != CONST_WIDE_INT
6597 && GET_CODE (x
) != CONST_DOUBLE
6599 && GET_MODE_NUNITS (mode
) == 1
6600 && (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
6601 || (/* ??? Assume floating point reg based on mode? */
6602 (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
6603 && (mode
== DFmode
|| mode
== DDmode
))))
6605 rtx reg
= gen_reg_rtx (Pmode
);
6607 emit_insn (gen_elf_high (reg
, x
));
6609 emit_insn (gen_macho_high (reg
, x
));
6610 return gen_rtx_LO_SUM (Pmode
, reg
, x
);
6613 && GET_CODE (x
) == SYMBOL_REF
6614 && constant_pool_expr_p (x
)
6615 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x
), Pmode
))
6616 return create_TOC_reference (x
, NULL_RTX
);
6621 /* Debug version of rs6000_legitimize_address. */
6623 rs6000_debug_legitimize_address (rtx x
, rtx oldx
, enum machine_mode mode
)
6629 ret
= rs6000_legitimize_address (x
, oldx
, mode
);
6630 insns
= get_insns ();
6636 "\nrs6000_legitimize_address: mode %s, old code %s, "
6637 "new code %s, modified\n",
6638 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)),
6639 GET_RTX_NAME (GET_CODE (ret
)));
6641 fprintf (stderr
, "Original address:\n");
6644 fprintf (stderr
, "oldx:\n");
6647 fprintf (stderr
, "New address:\n");
6652 fprintf (stderr
, "Insns added:\n");
6653 debug_rtx_list (insns
, 20);
6659 "\nrs6000_legitimize_address: mode %s, code %s, no change:\n",
6660 GET_MODE_NAME (mode
), GET_RTX_NAME (GET_CODE (x
)));
6671 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6672 We need to emit DTP-relative relocations. */
6674 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
6676 rs6000_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
6681 fputs ("\t.long\t", file
);
6684 fputs (DOUBLE_INT_ASM_OP
, file
);
6689 output_addr_const (file
, x
);
6690 fputs ("@dtprel+0x8000", file
);
6693 /* In the name of slightly smaller debug output, and to cater to
6694 general assembler lossage, recognize various UNSPEC sequences
6695 and turn them back into a direct symbol reference. */
6698 rs6000_delegitimize_address (rtx orig_x
)
6702 orig_x
= delegitimize_mem_from_attrs (orig_x
);
6708 if (TARGET_CMODEL
!= CMODEL_SMALL
6709 && GET_CODE (y
) == LO_SUM
)
6713 if (GET_CODE (y
) == PLUS
6714 && GET_MODE (y
) == Pmode
6715 && CONST_INT_P (XEXP (y
, 1)))
6717 offset
= XEXP (y
, 1);
6721 if (GET_CODE (y
) == UNSPEC
6722 && XINT (y
, 1) == UNSPEC_TOCREL
)
6724 #ifdef ENABLE_CHECKING
6725 if (REG_P (XVECEXP (y
, 0, 1))
6726 && REGNO (XVECEXP (y
, 0, 1)) == TOC_REGISTER
)
6730 else if (GET_CODE (XVECEXP (y
, 0, 1)) == DEBUG_EXPR
)
6732 /* Weirdness alert. df_note_compute can replace r2 with a
6733 debug_expr when this unspec is in a debug_insn.
6734 Seen in gcc.dg/pr51957-1.c */
6742 y
= XVECEXP (y
, 0, 0);
6745 /* Do not associate thread-local symbols with the original
6746 constant pool symbol. */
6748 && GET_CODE (y
) == SYMBOL_REF
6749 && CONSTANT_POOL_ADDRESS_P (y
)
6750 && SYMBOL_REF_TLS_MODEL (get_pool_constant (y
)) >= TLS_MODEL_REAL
)
6754 if (offset
!= NULL_RTX
)
6755 y
= gen_rtx_PLUS (Pmode
, y
, offset
);
6756 if (!MEM_P (orig_x
))
6759 return replace_equiv_address_nv (orig_x
, y
);
6763 && GET_CODE (orig_x
) == LO_SUM
6764 && GET_CODE (XEXP (orig_x
, 1)) == CONST
)
6766 y
= XEXP (XEXP (orig_x
, 1), 0);
6767 if (GET_CODE (y
) == UNSPEC
6768 && XINT (y
, 1) == UNSPEC_MACHOPIC_OFFSET
)
6769 return XVECEXP (y
, 0, 0);
6775 /* Return true if X shouldn't be emitted into the debug info.
6776 The linker doesn't like .toc section references from
6777 .debug_* sections, so reject .toc section symbols. */
6780 rs6000_const_not_ok_for_debug_p (rtx x
)
6782 if (GET_CODE (x
) == SYMBOL_REF
6783 && CONSTANT_POOL_ADDRESS_P (x
))
6785 rtx c
= get_pool_constant (x
);
6786 enum machine_mode cmode
= get_pool_mode (x
);
6787 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (c
, cmode
))
6794 /* Construct the SYMBOL_REF for the tls_get_addr function. */
6796 static GTY(()) rtx rs6000_tls_symbol
;
6798 rs6000_tls_get_addr (void)
6800 if (!rs6000_tls_symbol
)
6801 rs6000_tls_symbol
= init_one_libfunc ("__tls_get_addr");
6803 return rs6000_tls_symbol
;
6806 /* Construct the SYMBOL_REF for TLS GOT references. */
6808 static GTY(()) rtx rs6000_got_symbol
;
6810 rs6000_got_sym (void)
6812 if (!rs6000_got_symbol
)
6814 rs6000_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
6815 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_LOCAL
;
6816 SYMBOL_REF_FLAGS (rs6000_got_symbol
) |= SYMBOL_FLAG_EXTERNAL
;
6819 return rs6000_got_symbol
;
6822 /* AIX Thread-Local Address support. */
6825 rs6000_legitimize_tls_address_aix (rtx addr
, enum tls_model model
)
6827 rtx sym
, mem
, tocref
, tlsreg
, tmpreg
, dest
, tlsaddr
;
6831 name
= XSTR (addr
, 0);
6832 /* Append TLS CSECT qualifier, unless the symbol already is qualified
6833 or the symbol will be in TLS private data section. */
6834 if (name
[strlen (name
) - 1] != ']'
6835 && (TREE_PUBLIC (SYMBOL_REF_DECL (addr
))
6836 || bss_initializer_p (SYMBOL_REF_DECL (addr
))))
6838 tlsname
= XALLOCAVEC (char, strlen (name
) + 4);
6839 strcpy (tlsname
, name
);
6841 bss_initializer_p (SYMBOL_REF_DECL (addr
)) ? "[UL]" : "[TL]");
6842 tlsaddr
= copy_rtx (addr
);
6843 XSTR (tlsaddr
, 0) = ggc_strdup (tlsname
);
6848 /* Place addr into TOC constant pool. */
6849 sym
= force_const_mem (GET_MODE (tlsaddr
), tlsaddr
);
6851 /* Output the TOC entry and create the MEM referencing the value. */
6852 if (constant_pool_expr_p (XEXP (sym
, 0))
6853 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (XEXP (sym
, 0)), Pmode
))
6855 tocref
= create_TOC_reference (XEXP (sym
, 0), NULL_RTX
);
6856 mem
= gen_const_mem (Pmode
, tocref
);
6857 set_mem_alias_set (mem
, get_TOC_alias_set ());
6862 /* Use global-dynamic for local-dynamic. */
6863 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
6864 || model
== TLS_MODEL_LOCAL_DYNAMIC
)
6866 /* Create new TOC reference for @m symbol. */
6867 name
= XSTR (XVECEXP (XEXP (mem
, 0), 0, 0), 0);
6868 tlsname
= XALLOCAVEC (char, strlen (name
) + 1);
6869 strcpy (tlsname
, "*LCM");
6870 strcat (tlsname
, name
+ 3);
6871 rtx modaddr
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (tlsname
));
6872 SYMBOL_REF_FLAGS (modaddr
) |= SYMBOL_FLAG_LOCAL
;
6873 tocref
= create_TOC_reference (modaddr
, NULL_RTX
);
6874 rtx modmem
= gen_const_mem (Pmode
, tocref
);
6875 set_mem_alias_set (modmem
, get_TOC_alias_set ());
6877 rtx modreg
= gen_reg_rtx (Pmode
);
6878 emit_insn (gen_rtx_SET (VOIDmode
, modreg
, modmem
));
6880 tmpreg
= gen_reg_rtx (Pmode
);
6881 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6883 dest
= gen_reg_rtx (Pmode
);
6885 emit_insn (gen_tls_get_addrsi (dest
, modreg
, tmpreg
));
6887 emit_insn (gen_tls_get_addrdi (dest
, modreg
, tmpreg
));
6890 /* Obtain TLS pointer: 32 bit call or 64 bit GPR 13. */
6891 else if (TARGET_32BIT
)
6893 tlsreg
= gen_reg_rtx (SImode
);
6894 emit_insn (gen_tls_get_tpointer (tlsreg
));
6897 tlsreg
= gen_rtx_REG (DImode
, 13);
6899 /* Load the TOC value into temporary register. */
6900 tmpreg
= gen_reg_rtx (Pmode
);
6901 emit_insn (gen_rtx_SET (VOIDmode
, tmpreg
, mem
));
6902 set_unique_reg_note (get_last_insn (), REG_EQUAL
,
6903 gen_rtx_MINUS (Pmode
, addr
, tlsreg
));
6905 /* Add TOC symbol value to TLS pointer. */
6906 dest
= force_reg (Pmode
, gen_rtx_PLUS (Pmode
, tmpreg
, tlsreg
));
6911 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
6912 this (thread-local) address. */
6915 rs6000_legitimize_tls_address (rtx addr
, enum tls_model model
)
6920 return rs6000_legitimize_tls_address_aix (addr
, model
);
6922 dest
= gen_reg_rtx (Pmode
);
6923 if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 16)
6929 tlsreg
= gen_rtx_REG (Pmode
, 13);
6930 insn
= gen_tls_tprel_64 (dest
, tlsreg
, addr
);
6934 tlsreg
= gen_rtx_REG (Pmode
, 2);
6935 insn
= gen_tls_tprel_32 (dest
, tlsreg
, addr
);
6939 else if (model
== TLS_MODEL_LOCAL_EXEC
&& rs6000_tls_size
== 32)
6943 tmp
= gen_reg_rtx (Pmode
);
6946 tlsreg
= gen_rtx_REG (Pmode
, 13);
6947 insn
= gen_tls_tprel_ha_64 (tmp
, tlsreg
, addr
);
6951 tlsreg
= gen_rtx_REG (Pmode
, 2);
6952 insn
= gen_tls_tprel_ha_32 (tmp
, tlsreg
, addr
);
6956 insn
= gen_tls_tprel_lo_64 (dest
, tmp
, addr
);
6958 insn
= gen_tls_tprel_lo_32 (dest
, tmp
, addr
);
6963 rtx r3
, got
, tga
, tmp1
, tmp2
, call_insn
;
6965 /* We currently use relocations like @got@tlsgd for tls, which
6966 means the linker will handle allocation of tls entries, placing
6967 them in the .got section. So use a pointer to the .got section,
6968 not one to secondary TOC sections used by 64-bit -mminimal-toc,
6969 or to secondary GOT sections used by 32-bit -fPIC. */
6971 got
= gen_rtx_REG (Pmode
, 2);
6975 got
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
6978 rtx gsym
= rs6000_got_sym ();
6979 got
= gen_reg_rtx (Pmode
);
6981 rs6000_emit_move (got
, gsym
, Pmode
);
6986 tmp1
= gen_reg_rtx (Pmode
);
6987 tmp2
= gen_reg_rtx (Pmode
);
6988 mem
= gen_const_mem (Pmode
, tmp1
);
6989 lab
= gen_label_rtx ();
6990 emit_insn (gen_load_toc_v4_PIC_1b (gsym
, lab
));
6991 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
6992 if (TARGET_LINK_STACK
)
6993 emit_insn (gen_addsi3 (tmp1
, tmp1
, GEN_INT (4)));
6994 emit_move_insn (tmp2
, mem
);
6995 last
= emit_insn (gen_addsi3 (got
, tmp1
, tmp2
));
6996 set_unique_reg_note (last
, REG_EQUAL
, gsym
);
7001 if (model
== TLS_MODEL_GLOBAL_DYNAMIC
)
7003 tga
= rs6000_tls_get_addr ();
7004 emit_library_call_value (tga
, dest
, LCT_CONST
, Pmode
,
7005 1, const0_rtx
, Pmode
);
7007 r3
= gen_rtx_REG (Pmode
, 3);
7008 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7011 insn
= gen_tls_gd_aix64 (r3
, got
, addr
, tga
, const0_rtx
);
7013 insn
= gen_tls_gd_aix32 (r3
, got
, addr
, tga
, const0_rtx
);
7015 else if (DEFAULT_ABI
== ABI_V4
)
7016 insn
= gen_tls_gd_sysvsi (r3
, got
, addr
, tga
, const0_rtx
);
7019 call_insn
= last_call_insn ();
7020 PATTERN (call_insn
) = insn
;
7021 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7022 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7023 pic_offset_table_rtx
);
7025 else if (model
== TLS_MODEL_LOCAL_DYNAMIC
)
7027 tga
= rs6000_tls_get_addr ();
7028 tmp1
= gen_reg_rtx (Pmode
);
7029 emit_library_call_value (tga
, tmp1
, LCT_CONST
, Pmode
,
7030 1, const0_rtx
, Pmode
);
7032 r3
= gen_rtx_REG (Pmode
, 3);
7033 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7036 insn
= gen_tls_ld_aix64 (r3
, got
, tga
, const0_rtx
);
7038 insn
= gen_tls_ld_aix32 (r3
, got
, tga
, const0_rtx
);
7040 else if (DEFAULT_ABI
== ABI_V4
)
7041 insn
= gen_tls_ld_sysvsi (r3
, got
, tga
, const0_rtx
);
7044 call_insn
= last_call_insn ();
7045 PATTERN (call_insn
) = insn
;
7046 if (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
7047 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn
),
7048 pic_offset_table_rtx
);
7050 if (rs6000_tls_size
== 16)
7053 insn
= gen_tls_dtprel_64 (dest
, tmp1
, addr
);
7055 insn
= gen_tls_dtprel_32 (dest
, tmp1
, addr
);
7057 else if (rs6000_tls_size
== 32)
7059 tmp2
= gen_reg_rtx (Pmode
);
7061 insn
= gen_tls_dtprel_ha_64 (tmp2
, tmp1
, addr
);
7063 insn
= gen_tls_dtprel_ha_32 (tmp2
, tmp1
, addr
);
7066 insn
= gen_tls_dtprel_lo_64 (dest
, tmp2
, addr
);
7068 insn
= gen_tls_dtprel_lo_32 (dest
, tmp2
, addr
);
7072 tmp2
= gen_reg_rtx (Pmode
);
7074 insn
= gen_tls_got_dtprel_64 (tmp2
, got
, addr
);
7076 insn
= gen_tls_got_dtprel_32 (tmp2
, got
, addr
);
7078 insn
= gen_rtx_SET (Pmode
, dest
,
7079 gen_rtx_PLUS (Pmode
, tmp2
, tmp1
));
7085 /* IE, or 64-bit offset LE. */
7086 tmp2
= gen_reg_rtx (Pmode
);
7088 insn
= gen_tls_got_tprel_64 (tmp2
, got
, addr
);
7090 insn
= gen_tls_got_tprel_32 (tmp2
, got
, addr
);
7093 insn
= gen_tls_tls_64 (dest
, tmp2
, addr
);
7095 insn
= gen_tls_tls_32 (dest
, tmp2
, addr
);
7103 /* Return 1 if X contains a thread-local symbol. */
7106 rs6000_tls_referenced_p (rtx x
)
7108 if (! TARGET_HAVE_TLS
)
7111 return for_each_rtx (&x
, &rs6000_tls_symbol_ref_1
, 0);
7114 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
7117 rs6000_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
7119 if (GET_CODE (x
) == HIGH
7120 && GET_CODE (XEXP (x
, 0)) == UNSPEC
)
7123 /* A TLS symbol in the TOC cannot contain a sum. */
7124 if (GET_CODE (x
) == CONST
7125 && GET_CODE (XEXP (x
, 0)) == PLUS
7126 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
7127 && SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x
, 0), 0)) != 0)
7130 /* Do not place an ELF TLS symbol in the constant pool. */
7131 return TARGET_ELF
&& rs6000_tls_referenced_p (x
);
7134 /* Return 1 if *X is a thread-local symbol. This is the same as
7135 rs6000_tls_symbol_ref except for the type of the unused argument. */
7138 rs6000_tls_symbol_ref_1 (rtx
*x
, void *data ATTRIBUTE_UNUSED
)
7140 return RS6000_SYMBOL_REF_TLS_P (*x
);
7143 /* Return true iff the given SYMBOL_REF refers to a constant pool entry
7144 that we have put in the TOC, or for cmodel=medium, if the SYMBOL_REF
7145 can be addressed relative to the toc pointer. */
7148 use_toc_relative_ref (rtx sym
)
7150 return ((constant_pool_expr_p (sym
)
7151 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (sym
),
7152 get_pool_mode (sym
)))
7153 || (TARGET_CMODEL
== CMODEL_MEDIUM
7154 && SYMBOL_REF_LOCAL_P (sym
)));
7157 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
7158 replace the input X, or the original X if no replacement is called for.
7159 The output parameter *WIN is 1 if the calling macro should goto WIN,
7162 For RS/6000, we wish to handle large displacements off a base
7163 register by splitting the addend across an addiu/addis and the mem insn.
7164 This cuts number of extra insns needed from 3 to 1.
7166 On Darwin, we use this to generate code for floating point constants.
7167 A movsf_low is generated so we wind up with 2 instructions rather than 3.
7168 The Darwin code is inside #if TARGET_MACHO because only then are the
7169 machopic_* functions defined. */
7171 rs6000_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7172 int opnum
, int type
,
7173 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
7175 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7177 /* Nasty hack for vsx_splat_V2DF/V2DI load from mem, which takes a
7178 DFmode/DImode MEM. */
7181 && ((mode
== DFmode
&& recog_data
.operand_mode
[0] == V2DFmode
)
7182 || (mode
== DImode
&& recog_data
.operand_mode
[0] == V2DImode
)))
7183 reg_offset_p
= false;
7185 /* We must recognize output that we have already generated ourselves. */
7186 if (GET_CODE (x
) == PLUS
7187 && GET_CODE (XEXP (x
, 0)) == PLUS
7188 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7189 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7190 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7192 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7193 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7194 opnum
, (enum reload_type
) type
);
7199 /* Likewise for (lo_sum (high ...) ...) output we have generated. */
7200 if (GET_CODE (x
) == LO_SUM
7201 && GET_CODE (XEXP (x
, 0)) == HIGH
)
7203 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7204 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7205 opnum
, (enum reload_type
) type
);
7211 if (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
7212 && GET_CODE (x
) == LO_SUM
7213 && GET_CODE (XEXP (x
, 0)) == PLUS
7214 && XEXP (XEXP (x
, 0), 0) == pic_offset_table_rtx
7215 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == HIGH
7216 && XEXP (XEXP (XEXP (x
, 0), 1), 0) == XEXP (x
, 1)
7217 && machopic_operand_p (XEXP (x
, 1)))
7219 /* Result of previous invocation of this function on Darwin
7220 floating point constant. */
7221 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7222 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7223 opnum
, (enum reload_type
) type
);
7229 if (TARGET_CMODEL
!= CMODEL_SMALL
7231 && small_toc_ref (x
, VOIDmode
))
7233 rtx hi
= gen_rtx_HIGH (Pmode
, copy_rtx (x
));
7234 x
= gen_rtx_LO_SUM (Pmode
, hi
, x
);
7235 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7236 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7237 opnum
, (enum reload_type
) type
);
7242 if (GET_CODE (x
) == PLUS
7243 && GET_CODE (XEXP (x
, 0)) == REG
7244 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
7245 && INT_REG_OK_FOR_BASE_P (XEXP (x
, 0), 1)
7246 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7248 && !SPE_VECTOR_MODE (mode
)
7249 && !(TARGET_E500_DOUBLE
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
7250 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
)))
7252 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1));
7253 HOST_WIDE_INT low
= ((val
& 0xffff) ^ 0x8000) - 0x8000;
7255 = (((val
- low
) & 0xffffffff) ^ 0x80000000) - 0x80000000;
7257 /* Check for 32-bit overflow. */
7258 if (high
+ low
!= val
)
7264 /* Reload the high part into a base reg; leave the low part
7265 in the mem directly. */
7267 x
= gen_rtx_PLUS (GET_MODE (x
),
7268 gen_rtx_PLUS (GET_MODE (x
), XEXP (x
, 0),
7272 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7273 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
7274 opnum
, (enum reload_type
) type
);
7279 if (GET_CODE (x
) == SYMBOL_REF
7281 && (!VECTOR_MODE_P (mode
) || VECTOR_MEM_NONE_P (mode
))
7282 && !SPE_VECTOR_MODE (mode
)
7284 && DEFAULT_ABI
== ABI_DARWIN
7285 && (flag_pic
|| MACHO_DYNAMIC_NO_PIC_P
)
7286 && machopic_symbol_defined_p (x
)
7288 && DEFAULT_ABI
== ABI_V4
7291 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
7292 The same goes for DImode without 64-bit gprs and DFmode and DDmode
7294 ??? Assume floating point reg based on mode? This assumption is
7295 violated by eg. powerpc-linux -m32 compile of gcc.dg/pr28796-2.c
7296 where reload ends up doing a DFmode load of a constant from
7297 mem using two gprs. Unfortunately, at this point reload
7298 hasn't yet selected regs so poking around in reload data
7299 won't help and even if we could figure out the regs reliably,
7300 we'd still want to allow this transformation when the mem is
7301 naturally aligned. Since we say the address is good here, we
7302 can't disable offsets from LO_SUMs in mem_operand_gpr.
7303 FIXME: Allow offset from lo_sum for other modes too, when
7304 mem is sufficiently aligned. */
7307 && (mode
!= TImode
|| !TARGET_VSX_TIMODE
)
7309 && (mode
!= DImode
|| TARGET_POWERPC64
)
7310 && ((mode
!= DFmode
&& mode
!= DDmode
) || TARGET_POWERPC64
7311 || (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)))
7316 rtx offset
= machopic_gen_offset (x
);
7317 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7318 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
7319 gen_rtx_HIGH (Pmode
, offset
)), offset
);
7323 x
= gen_rtx_LO_SUM (GET_MODE (x
),
7324 gen_rtx_HIGH (Pmode
, x
), x
);
7326 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7327 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7328 opnum
, (enum reload_type
) type
);
7333 /* Reload an offset address wrapped by an AND that represents the
7334 masking of the lower bits. Strip the outer AND and let reload
7335 convert the offset address into an indirect address. For VSX,
7336 force reload to create the address with an AND in a separate
7337 register, because we can't guarantee an altivec register will
7339 if (VECTOR_MEM_ALTIVEC_P (mode
)
7340 && GET_CODE (x
) == AND
7341 && GET_CODE (XEXP (x
, 0)) == PLUS
7342 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == REG
7343 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7344 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7345 && INTVAL (XEXP (x
, 1)) == -16)
7354 && GET_CODE (x
) == SYMBOL_REF
7355 && use_toc_relative_ref (x
))
7357 x
= create_TOC_reference (x
, NULL_RTX
);
7358 if (TARGET_CMODEL
!= CMODEL_SMALL
)
7359 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
7360 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
7361 opnum
, (enum reload_type
) type
);
7369 /* Debug version of rs6000_legitimize_reload_address. */
7371 rs6000_debug_legitimize_reload_address (rtx x
, enum machine_mode mode
,
7372 int opnum
, int type
,
7373 int ind_levels
, int *win
)
7375 rtx ret
= rs6000_legitimize_reload_address (x
, mode
, opnum
, type
,
7378 "\nrs6000_legitimize_reload_address: mode = %s, opnum = %d, "
7379 "type = %d, ind_levels = %d, win = %d, original addr:\n",
7380 GET_MODE_NAME (mode
), opnum
, type
, ind_levels
, *win
);
7384 fprintf (stderr
, "Same address returned\n");
7386 fprintf (stderr
, "NULL returned\n");
7389 fprintf (stderr
, "New address:\n");
7396 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
7397 that is a valid memory address for an instruction.
7398 The MODE argument is the machine mode for the MEM expression
7399 that wants to use this address.
7401 On the RS/6000, there are four valid address: a SYMBOL_REF that
7402 refers to a constant pool entry of an address (or the sum of it
7403 plus a constant), a short (16-bit signed) constant plus a register,
7404 the sum of two registers, or a register indirect, possibly with an
7405 auto-increment. For DFmode, DDmode and DImode with a constant plus
7406 register, we must ensure that both words are addressable or PowerPC64
7407 with offset word aligned.
7409 For modes spanning multiple registers (DFmode and DDmode in 32-bit GPRs,
7410 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
7411 because adjacent memory cells are accessed by adding word-sized offsets
7412 during assembly output. */
7414 rs6000_legitimate_address_p (enum machine_mode mode
, rtx x
, bool reg_ok_strict
)
7416 bool reg_offset_p
= reg_offset_addressing_ok_p (mode
);
7418 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
7419 if (VECTOR_MEM_ALTIVEC_P (mode
)
7420 && GET_CODE (x
) == AND
7421 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7422 && INTVAL (XEXP (x
, 1)) == -16)
7425 if (TARGET_ELF
&& RS6000_SYMBOL_REF_TLS_P (x
))
7427 if (legitimate_indirect_address_p (x
, reg_ok_strict
))
7430 && (GET_CODE (x
) == PRE_INC
|| GET_CODE (x
) == PRE_DEC
)
7431 && mode_supports_pre_incdec_p (mode
)
7432 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
))
7434 if (virtual_stack_registers_memory_p (x
))
7436 if (reg_offset_p
&& legitimate_small_data_p (mode
, x
))
7439 && legitimate_constant_pool_address_p (x
, mode
,
7440 reg_ok_strict
|| lra_in_progress
))
7442 /* For TImode, if we have load/store quad and TImode in VSX registers, only
7443 allow register indirect addresses. This will allow the values to go in
7444 either GPRs or VSX registers without reloading. The vector types would
7445 tend to go into VSX registers, so we allow REG+REG, while TImode seems
7446 somewhat split, in that some uses are GPR based, and some VSX based. */
7447 if (mode
== TImode
&& TARGET_QUAD_MEMORY
&& TARGET_VSX_TIMODE
)
7449 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
7452 && GET_CODE (x
) == PLUS
7453 && GET_CODE (XEXP (x
, 0)) == REG
7454 && (XEXP (x
, 0) == virtual_stack_vars_rtx
7455 || XEXP (x
, 0) == arg_pointer_rtx
)
7456 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
7458 if (rs6000_legitimate_offset_address_p (mode
, x
, reg_ok_strict
, false))
7462 && ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
)
7464 || (mode
!= DFmode
&& mode
!= DDmode
)
7465 || (TARGET_E500_DOUBLE
&& mode
!= DDmode
))
7466 && (TARGET_POWERPC64
|| mode
!= DImode
)
7467 && (mode
!= TImode
|| VECTOR_MEM_VSX_P (TImode
))
7469 && !avoiding_indexed_address_p (mode
)
7470 && legitimate_indexed_address_p (x
, reg_ok_strict
))
7472 if (TARGET_UPDATE
&& GET_CODE (x
) == PRE_MODIFY
7473 && mode_supports_pre_modify_p (mode
)
7474 && legitimate_indirect_address_p (XEXP (x
, 0), reg_ok_strict
)
7475 && (rs6000_legitimate_offset_address_p (mode
, XEXP (x
, 1),
7476 reg_ok_strict
, false)
7477 || (!avoiding_indexed_address_p (mode
)
7478 && legitimate_indexed_address_p (XEXP (x
, 1), reg_ok_strict
)))
7479 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
7481 if (reg_offset_p
&& legitimate_lo_sum_address_p (mode
, x
, reg_ok_strict
))
7486 /* Debug version of rs6000_legitimate_address_p. */
7488 rs6000_debug_legitimate_address_p (enum machine_mode mode
, rtx x
,
7491 bool ret
= rs6000_legitimate_address_p (mode
, x
, reg_ok_strict
);
7493 "\nrs6000_legitimate_address_p: return = %s, mode = %s, "
7494 "strict = %d, reload = %s, code = %s\n",
7495 ret
? "true" : "false",
7496 GET_MODE_NAME (mode
),
7500 : (reload_in_progress
? "progress" : "before")),
7501 GET_RTX_NAME (GET_CODE (x
)));
7507 /* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
7510 rs6000_mode_dependent_address_p (const_rtx addr
,
7511 addr_space_t as ATTRIBUTE_UNUSED
)
7513 return rs6000_mode_dependent_address_ptr (addr
);
7516 /* Go to LABEL if ADDR (a legitimate address expression)
7517 has an effect that depends on the machine mode it is used for.
7519 On the RS/6000 this is true of all integral offsets (since AltiVec
7520 and VSX modes don't allow them) or is a pre-increment or decrement.
7522 ??? Except that due to conceptual problems in offsettable_address_p
7523 we can't really report the problems of integral offsets. So leave
7524 this assuming that the adjustable offset must be valid for the
7525 sub-words of a TFmode operand, which is what we had before. */
7528 rs6000_mode_dependent_address (const_rtx addr
)
7530 switch (GET_CODE (addr
))
7533 /* Any offset from virtual_stack_vars_rtx and arg_pointer_rtx
7534 is considered a legitimate address before reload, so there
7535 are no offset restrictions in that case. Note that this
7536 condition is safe in strict mode because any address involving
7537 virtual_stack_vars_rtx or arg_pointer_rtx would already have
7538 been rejected as illegitimate. */
7539 if (XEXP (addr
, 0) != virtual_stack_vars_rtx
7540 && XEXP (addr
, 0) != arg_pointer_rtx
7541 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
7543 unsigned HOST_WIDE_INT val
= INTVAL (XEXP (addr
, 1));
7544 return val
+ 0x8000 >= 0x10000 - (TARGET_POWERPC64
? 8 : 12);
7549 /* Anything in the constant pool is sufficiently aligned that
7550 all bytes have the same high part address. */
7551 return !legitimate_constant_pool_address_p (addr
, QImode
, false);
7553 /* Auto-increment cases are now treated generically in recog.c. */
7555 return TARGET_UPDATE
;
7557 /* AND is only allowed in Altivec loads. */
7568 /* Debug version of rs6000_mode_dependent_address. */
7570 rs6000_debug_mode_dependent_address (const_rtx addr
)
7572 bool ret
= rs6000_mode_dependent_address (addr
);
7574 fprintf (stderr
, "\nrs6000_mode_dependent_address: ret = %s\n",
7575 ret
? "true" : "false");
7581 /* Implement FIND_BASE_TERM. */
7584 rs6000_find_base_term (rtx op
)
7589 if (GET_CODE (base
) == CONST
)
7590 base
= XEXP (base
, 0);
7591 if (GET_CODE (base
) == PLUS
)
7592 base
= XEXP (base
, 0);
7593 if (GET_CODE (base
) == UNSPEC
)
7594 switch (XINT (base
, 1))
7597 case UNSPEC_MACHOPIC_OFFSET
:
7598 /* OP represents SYM [+ OFFSET] - ANCHOR. SYM is the base term
7599 for aliasing purposes. */
7600 return XVECEXP (base
, 0, 0);
7606 /* More elaborate version of recog's offsettable_memref_p predicate
7607 that works around the ??? note of rs6000_mode_dependent_address.
7608 In particular it accepts
7610 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
7612 in 32-bit mode, that the recog predicate rejects. */
7615 rs6000_offsettable_memref_p (rtx op
, enum machine_mode reg_mode
)
7622 /* First mimic offsettable_memref_p. */
7623 if (offsettable_address_p (true, GET_MODE (op
), XEXP (op
, 0)))
7626 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
7627 the latter predicate knows nothing about the mode of the memory
7628 reference and, therefore, assumes that it is the largest supported
7629 mode (TFmode). As a consequence, legitimate offsettable memory
7630 references are rejected. rs6000_legitimate_offset_address_p contains
7631 the correct logic for the PLUS case of rs6000_mode_dependent_address,
7632 at least with a little bit of help here given that we know the
7633 actual registers used. */
7634 worst_case
= ((TARGET_POWERPC64
&& GET_MODE_CLASS (reg_mode
) == MODE_INT
)
7635 || GET_MODE_SIZE (reg_mode
) == 4);
7636 return rs6000_legitimate_offset_address_p (GET_MODE (op
), XEXP (op
, 0),
7640 /* Change register usage conditional on target flags. */
7642 rs6000_conditional_register_usage (void)
7646 if (TARGET_DEBUG_TARGET
)
7647 fprintf (stderr
, "rs6000_conditional_register_usage called\n");
7649 /* Set MQ register fixed (already call_used) so that it will not be
7653 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
7655 fixed_regs
[13] = call_used_regs
[13]
7656 = call_really_used_regs
[13] = 1;
7658 /* Conditionally disable FPRs. */
7659 if (TARGET_SOFT_FLOAT
|| !TARGET_FPRS
)
7660 for (i
= 32; i
< 64; i
++)
7661 fixed_regs
[i
] = call_used_regs
[i
]
7662 = call_really_used_regs
[i
] = 1;
7664 /* The TOC register is not killed across calls in a way that is
7665 visible to the compiler. */
7666 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
7667 call_really_used_regs
[2] = 0;
7669 if (DEFAULT_ABI
== ABI_V4
7670 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7672 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7674 if (DEFAULT_ABI
== ABI_V4
7675 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
7677 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7678 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7679 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7681 if (DEFAULT_ABI
== ABI_DARWIN
7682 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
7683 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7684 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7685 = call_really_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7687 if (TARGET_TOC
&& TARGET_MINIMAL_TOC
)
7688 fixed_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
]
7689 = call_used_regs
[RS6000_PIC_OFFSET_TABLE_REGNUM
] = 1;
7693 global_regs
[SPEFSCR_REGNO
] = 1;
7694 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
7695 registers in prologues and epilogues. We no longer use r14
7696 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
7697 pool for link-compatibility with older versions of GCC. Once
7698 "old" code has died out, we can return r14 to the allocation
7701 = call_used_regs
[14]
7702 = call_really_used_regs
[14] = 1;
7705 if (!TARGET_ALTIVEC
&& !TARGET_VSX
)
7707 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
7708 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7709 call_really_used_regs
[VRSAVE_REGNO
] = 1;
7712 if (TARGET_ALTIVEC
|| TARGET_VSX
)
7713 global_regs
[VSCR_REGNO
] = 1;
7715 if (TARGET_ALTIVEC_ABI
)
7717 for (i
= FIRST_ALTIVEC_REGNO
; i
< FIRST_ALTIVEC_REGNO
+ 20; ++i
)
7718 call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7720 /* AIX reserves VR20:31 in non-extended ABI mode. */
7722 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
< FIRST_ALTIVEC_REGNO
+ 32; ++i
)
7723 fixed_regs
[i
] = call_used_regs
[i
] = call_really_used_regs
[i
] = 1;
7728 /* Try to output insns to set TARGET equal to the constant C if it can
7729 be done in less than N insns. Do all computations in MODE.
7730 Returns the place where the output has been placed if it can be
7731 done and the insns have been emitted. If it would take more than N
7732 insns, zero is returned and no insns and emitted. */
7735 rs6000_emit_set_const (rtx dest
, enum machine_mode mode
,
7736 rtx source
, int n ATTRIBUTE_UNUSED
)
7738 rtx result
, insn
, set
;
7739 HOST_WIDE_INT c0
, c1
;
7746 dest
= gen_reg_rtx (mode
);
7747 emit_insn (gen_rtx_SET (VOIDmode
, dest
, source
));
7751 result
= !can_create_pseudo_p () ? dest
: gen_reg_rtx (SImode
);
7753 emit_insn (gen_rtx_SET (VOIDmode
, copy_rtx (result
),
7754 GEN_INT (INTVAL (source
)
7755 & (~ (HOST_WIDE_INT
) 0xffff))));
7756 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
7757 gen_rtx_IOR (SImode
, copy_rtx (result
),
7758 GEN_INT (INTVAL (source
) & 0xffff))));
7763 switch (GET_CODE (source
))
7766 c0
= INTVAL (source
);
7774 result
= rs6000_emit_set_long_const (dest
, c0
, c1
);
7781 insn
= get_last_insn ();
7782 set
= single_set (insn
);
7783 if (! CONSTANT_P (SET_SRC (set
)))
7784 set_unique_reg_note (insn
, REG_EQUAL
, source
);
7789 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
7790 fall back to a straight forward decomposition. We do this to avoid
7791 exponential run times encountered when looking for longer sequences
7792 with rs6000_emit_set_const. */
7794 rs6000_emit_set_long_const (rtx dest
, HOST_WIDE_INT c1
, HOST_WIDE_INT c2
)
7796 if (!TARGET_POWERPC64
)
7798 rtx operand1
, operand2
;
7800 operand1
= operand_subword_force (dest
, WORDS_BIG_ENDIAN
== 0,
7802 operand2
= operand_subword_force (copy_rtx (dest
), WORDS_BIG_ENDIAN
!= 0,
7804 emit_move_insn (operand1
, GEN_INT (c1
));
7805 emit_move_insn (operand2
, GEN_INT (c2
));
7809 HOST_WIDE_INT ud1
, ud2
, ud3
, ud4
;
7812 ud2
= (c1
& 0xffff0000) >> 16;
7815 ud4
= (c2
& 0xffff0000) >> 16;
7817 if ((ud4
== 0xffff && ud3
== 0xffff && ud2
== 0xffff && (ud1
& 0x8000))
7818 || (ud4
== 0 && ud3
== 0 && ud2
== 0 && ! (ud1
& 0x8000)))
7819 emit_move_insn (dest
, GEN_INT ((ud1
^ 0x8000) - 0x8000));
7821 else if ((ud4
== 0xffff && ud3
== 0xffff && (ud2
& 0x8000))
7822 || (ud4
== 0 && ud3
== 0 && ! (ud2
& 0x8000)))
7824 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7827 emit_move_insn (copy_rtx (dest
),
7828 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7831 else if (ud3
== 0 && ud4
== 0)
7833 gcc_assert (ud2
& 0x8000);
7834 emit_move_insn (dest
, GEN_INT (((ud2
<< 16) ^ 0x80000000)
7837 emit_move_insn (copy_rtx (dest
),
7838 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7840 emit_move_insn (copy_rtx (dest
),
7841 gen_rtx_ZERO_EXTEND (DImode
,
7842 gen_lowpart (SImode
,
7845 else if ((ud4
== 0xffff && (ud3
& 0x8000))
7846 || (ud4
== 0 && ! (ud3
& 0x8000)))
7848 emit_move_insn (dest
, GEN_INT (((ud3
<< 16) ^ 0x80000000)
7851 emit_move_insn (copy_rtx (dest
),
7852 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7854 emit_move_insn (copy_rtx (dest
),
7855 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7858 emit_move_insn (copy_rtx (dest
),
7859 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7864 emit_move_insn (dest
, GEN_INT (((ud4
<< 16) ^ 0x80000000)
7867 emit_move_insn (copy_rtx (dest
),
7868 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7871 emit_move_insn (copy_rtx (dest
),
7872 gen_rtx_ASHIFT (DImode
, copy_rtx (dest
),
7875 emit_move_insn (copy_rtx (dest
),
7876 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7877 GEN_INT (ud2
<< 16)));
7879 emit_move_insn (copy_rtx (dest
),
7880 gen_rtx_IOR (DImode
, copy_rtx (dest
),
7887 /* Helper for the following. Get rid of [r+r] memory refs
7888 in cases where it won't work (TImode, TFmode, TDmode, PTImode). */
7891 rs6000_eliminate_indexed_memrefs (rtx operands
[2])
7893 if (reload_in_progress
)
7896 if (GET_CODE (operands
[0]) == MEM
7897 && GET_CODE (XEXP (operands
[0], 0)) != REG
7898 && ! legitimate_constant_pool_address_p (XEXP (operands
[0], 0),
7899 GET_MODE (operands
[0]), false))
7901 = replace_equiv_address (operands
[0],
7902 copy_addr_to_reg (XEXP (operands
[0], 0)));
7904 if (GET_CODE (operands
[1]) == MEM
7905 && GET_CODE (XEXP (operands
[1], 0)) != REG
7906 && ! legitimate_constant_pool_address_p (XEXP (operands
[1], 0),
7907 GET_MODE (operands
[1]), false))
7909 = replace_equiv_address (operands
[1],
7910 copy_addr_to_reg (XEXP (operands
[1], 0)));
7913 /* Generate a vector of constants to permute MODE for a little-endian
7914 storage operation by swapping the two halves of a vector. */
7916 rs6000_const_vec (enum machine_mode mode
)
7941 v
= rtvec_alloc (subparts
);
7943 for (i
= 0; i
< subparts
/ 2; ++i
)
7944 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
+ subparts
/ 2);
7945 for (i
= subparts
/ 2; i
< subparts
; ++i
)
7946 RTVEC_ELT (v
, i
) = gen_rtx_CONST_INT (DImode
, i
- subparts
/ 2);
7951 /* Generate a permute rtx that represents an lxvd2x, stxvd2x, or xxpermdi
7952 for a VSX load or store operation. */
7954 rs6000_gen_le_vsx_permute (rtx source
, enum machine_mode mode
)
7956 rtx par
= gen_rtx_PARALLEL (VOIDmode
, rs6000_const_vec (mode
));
7957 return gen_rtx_VEC_SELECT (mode
, source
, par
);
7960 /* Emit a little-endian load from vector memory location SOURCE to VSX
7961 register DEST in mode MODE. The load is done with two permuting
7962 insn's that represent an lxvd2x and xxpermdi. */
7964 rs6000_emit_le_vsx_load (rtx dest
, rtx source
, enum machine_mode mode
)
7966 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (dest
) : dest
;
7967 rtx permute_mem
= rs6000_gen_le_vsx_permute (source
, mode
);
7968 rtx permute_reg
= rs6000_gen_le_vsx_permute (tmp
, mode
);
7969 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_mem
));
7970 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_reg
));
7973 /* Emit a little-endian store to vector memory location DEST from VSX
7974 register SOURCE in mode MODE. The store is done with two permuting
7975 insn's that represent an xxpermdi and an stxvd2x. */
7977 rs6000_emit_le_vsx_store (rtx dest
, rtx source
, enum machine_mode mode
)
7979 rtx tmp
= can_create_pseudo_p () ? gen_reg_rtx_and_attrs (source
) : source
;
7980 rtx permute_src
= rs6000_gen_le_vsx_permute (source
, mode
);
7981 rtx permute_tmp
= rs6000_gen_le_vsx_permute (tmp
, mode
);
7982 emit_insn (gen_rtx_SET (VOIDmode
, tmp
, permute_src
));
7983 emit_insn (gen_rtx_SET (VOIDmode
, dest
, permute_tmp
));
7986 /* Emit a sequence representing a little-endian VSX load or store,
7987 moving data from SOURCE to DEST in mode MODE. This is done
7988 separately from rs6000_emit_move to ensure it is called only
7989 during expand. LE VSX loads and stores introduced later are
7990 handled with a split. The expand-time RTL generation allows
7991 us to optimize away redundant pairs of register-permutes. */
7993 rs6000_emit_le_vsx_move (rtx dest
, rtx source
, enum machine_mode mode
)
7995 gcc_assert (!BYTES_BIG_ENDIAN
7996 && VECTOR_MEM_VSX_P (mode
)
7998 && !gpr_or_gpr_p (dest
, source
)
7999 && (MEM_P (source
) ^ MEM_P (dest
)));
8003 gcc_assert (REG_P (dest
));
8004 rs6000_emit_le_vsx_load (dest
, source
, mode
);
8008 if (!REG_P (source
))
8009 source
= force_reg (mode
, source
);
8010 rs6000_emit_le_vsx_store (dest
, source
, mode
);
8014 /* Emit a move from SOURCE to DEST in mode MODE. */
8016 rs6000_emit_move (rtx dest
, rtx source
, enum machine_mode mode
)
8020 operands
[1] = source
;
8022 if (TARGET_DEBUG_ADDR
)
8025 "\nrs6000_emit_move: mode = %s, reload_in_progress = %d, "
8026 "reload_completed = %d, can_create_pseudos = %d.\ndest:\n",
8027 GET_MODE_NAME (mode
),
8030 can_create_pseudo_p ());
8032 fprintf (stderr
, "source:\n");
8036 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
8037 if (CONST_WIDE_INT_P (operands
[1])
8038 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8040 /* This should be fixed with the introduction of CONST_WIDE_INT. */
8044 /* Check if GCC is setting up a block move that will end up using FP
8045 registers as temporaries. We must make sure this is acceptable. */
8046 if (GET_CODE (operands
[0]) == MEM
8047 && GET_CODE (operands
[1]) == MEM
8049 && (SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[0]))
8050 || SLOW_UNALIGNED_ACCESS (DImode
, MEM_ALIGN (operands
[1])))
8051 && ! (SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[0]) > 32
8052 ? 32 : MEM_ALIGN (operands
[0])))
8053 || SLOW_UNALIGNED_ACCESS (SImode
, (MEM_ALIGN (operands
[1]) > 32
8055 : MEM_ALIGN (operands
[1]))))
8056 && ! MEM_VOLATILE_P (operands
[0])
8057 && ! MEM_VOLATILE_P (operands
[1]))
8059 emit_move_insn (adjust_address (operands
[0], SImode
, 0),
8060 adjust_address (operands
[1], SImode
, 0));
8061 emit_move_insn (adjust_address (copy_rtx (operands
[0]), SImode
, 4),
8062 adjust_address (copy_rtx (operands
[1]), SImode
, 4));
8066 if (can_create_pseudo_p () && GET_CODE (operands
[0]) == MEM
8067 && !gpc_reg_operand (operands
[1], mode
))
8068 operands
[1] = force_reg (mode
, operands
[1]);
8070 /* Recognize the case where operand[1] is a reference to thread-local
8071 data and load its address to a register. */
8072 if (rs6000_tls_referenced_p (operands
[1]))
8074 enum tls_model model
;
8075 rtx tmp
= operands
[1];
8078 if (GET_CODE (tmp
) == CONST
&& GET_CODE (XEXP (tmp
, 0)) == PLUS
)
8080 addend
= XEXP (XEXP (tmp
, 0), 1);
8081 tmp
= XEXP (XEXP (tmp
, 0), 0);
8084 gcc_assert (GET_CODE (tmp
) == SYMBOL_REF
);
8085 model
= SYMBOL_REF_TLS_MODEL (tmp
);
8086 gcc_assert (model
!= 0);
8088 tmp
= rs6000_legitimize_tls_address (tmp
, model
);
8091 tmp
= gen_rtx_PLUS (mode
, tmp
, addend
);
8092 tmp
= force_operand (tmp
, operands
[0]);
8097 /* Handle the case where reload calls us with an invalid address. */
8098 if (reload_in_progress
&& mode
== Pmode
8099 && (! general_operand (operands
[1], mode
)
8100 || ! nonimmediate_operand (operands
[0], mode
)))
8103 /* 128-bit constant floating-point values on Darwin should really be
8104 loaded as two parts. */
8105 if (!TARGET_IEEEQUAD
&& TARGET_LONG_DOUBLE_128
8106 && mode
== TFmode
&& GET_CODE (operands
[1]) == CONST_DOUBLE
)
8108 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
, 0),
8109 simplify_gen_subreg (DFmode
, operands
[1], mode
, 0),
8111 rs6000_emit_move (simplify_gen_subreg (DFmode
, operands
[0], mode
,
8112 GET_MODE_SIZE (DFmode
)),
8113 simplify_gen_subreg (DFmode
, operands
[1], mode
,
8114 GET_MODE_SIZE (DFmode
)),
8119 if (reload_in_progress
&& cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
8120 cfun
->machine
->sdmode_stack_slot
=
8121 eliminate_regs (cfun
->machine
->sdmode_stack_slot
, VOIDmode
, NULL_RTX
);
8126 && REG_P (operands
[0]) && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
8127 && reg_preferred_class (REGNO (operands
[0])) == NO_REGS
8128 && (REG_P (operands
[1])
8129 || (GET_CODE (operands
[1]) == SUBREG
8130 && REG_P (SUBREG_REG (operands
[1])))))
8132 int regno
= REGNO (GET_CODE (operands
[1]) == SUBREG
8133 ? SUBREG_REG (operands
[1]) : operands
[1]);
8136 if (regno
>= FIRST_PSEUDO_REGISTER
)
8138 cl
= reg_preferred_class (regno
);
8139 gcc_assert (cl
!= NO_REGS
);
8140 regno
= ira_class_hard_regs
[cl
][0];
8142 if (FP_REGNO_P (regno
))
8144 if (GET_MODE (operands
[0]) != DDmode
)
8145 operands
[0] = gen_rtx_SUBREG (DDmode
, operands
[0], 0);
8146 emit_insn (gen_movsd_store (operands
[0], operands
[1]));
8148 else if (INT_REGNO_P (regno
))
8149 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8156 && (REG_P (operands
[0])
8157 || (GET_CODE (operands
[0]) == SUBREG
8158 && REG_P (SUBREG_REG (operands
[0]))))
8159 && REG_P (operands
[1]) && REGNO (operands
[1]) >= FIRST_PSEUDO_REGISTER
8160 && reg_preferred_class (REGNO (operands
[1])) == NO_REGS
)
8162 int regno
= REGNO (GET_CODE (operands
[0]) == SUBREG
8163 ? SUBREG_REG (operands
[0]) : operands
[0]);
8166 if (regno
>= FIRST_PSEUDO_REGISTER
)
8168 cl
= reg_preferred_class (regno
);
8169 gcc_assert (cl
!= NO_REGS
);
8170 regno
= ira_class_hard_regs
[cl
][0];
8172 if (FP_REGNO_P (regno
))
8174 if (GET_MODE (operands
[1]) != DDmode
)
8175 operands
[1] = gen_rtx_SUBREG (DDmode
, operands
[1], 0);
8176 emit_insn (gen_movsd_load (operands
[0], operands
[1]));
8178 else if (INT_REGNO_P (regno
))
8179 emit_insn (gen_movsd_hardfloat (operands
[0], operands
[1]));
8185 if (reload_in_progress
8187 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8188 && MEM_P (operands
[0])
8189 && rtx_equal_p (operands
[0], cfun
->machine
->sdmode_stack_slot
)
8190 && REG_P (operands
[1]))
8192 if (FP_REGNO_P (REGNO (operands
[1])))
8194 rtx mem
= adjust_address_nv (operands
[0], DDmode
, 0);
8195 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8196 emit_insn (gen_movsd_store (mem
, operands
[1]));
8198 else if (INT_REGNO_P (REGNO (operands
[1])))
8200 rtx mem
= operands
[0];
8201 if (BYTES_BIG_ENDIAN
)
8202 mem
= adjust_address_nv (mem
, mode
, 4);
8203 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8204 emit_insn (gen_movsd_hardfloat (mem
, operands
[1]));
8210 if (reload_in_progress
8212 && REG_P (operands
[0])
8213 && MEM_P (operands
[1])
8214 && cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
8215 && rtx_equal_p (operands
[1], cfun
->machine
->sdmode_stack_slot
))
8217 if (FP_REGNO_P (REGNO (operands
[0])))
8219 rtx mem
= adjust_address_nv (operands
[1], DDmode
, 0);
8220 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8221 emit_insn (gen_movsd_load (operands
[0], mem
));
8223 else if (INT_REGNO_P (REGNO (operands
[0])))
8225 rtx mem
= operands
[1];
8226 if (BYTES_BIG_ENDIAN
)
8227 mem
= adjust_address_nv (mem
, mode
, 4);
8228 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
8229 emit_insn (gen_movsd_hardfloat (operands
[0], mem
));
8236 /* FIXME: In the long term, this switch statement should go away
8237 and be replaced by a sequence of tests based on things like
8243 if (CONSTANT_P (operands
[1])
8244 && GET_CODE (operands
[1]) != CONST_INT
)
8245 operands
[1] = force_const_mem (mode
, operands
[1]);
8250 rs6000_eliminate_indexed_memrefs (operands
);
8257 if (CONSTANT_P (operands
[1])
8258 && ! easy_fp_constant (operands
[1], mode
))
8259 operands
[1] = force_const_mem (mode
, operands
[1]);
8272 if (CONSTANT_P (operands
[1])
8273 && !easy_vector_constant (operands
[1], mode
))
8274 operands
[1] = force_const_mem (mode
, operands
[1]);
8279 /* Use default pattern for address of ELF small data */
8282 && DEFAULT_ABI
== ABI_V4
8283 && (GET_CODE (operands
[1]) == SYMBOL_REF
8284 || GET_CODE (operands
[1]) == CONST
)
8285 && small_data_operand (operands
[1], mode
))
8287 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8291 if (DEFAULT_ABI
== ABI_V4
8292 && mode
== Pmode
&& mode
== SImode
8293 && flag_pic
== 1 && got_operand (operands
[1], mode
))
8295 emit_insn (gen_movsi_got (operands
[0], operands
[1]));
8299 if ((TARGET_ELF
|| DEFAULT_ABI
== ABI_DARWIN
)
8303 && CONSTANT_P (operands
[1])
8304 && GET_CODE (operands
[1]) != HIGH
8305 && GET_CODE (operands
[1]) != CONST_INT
)
8307 rtx target
= (!can_create_pseudo_p ()
8309 : gen_reg_rtx (mode
));
8311 /* If this is a function address on -mcall-aixdesc,
8312 convert it to the address of the descriptor. */
8313 if (DEFAULT_ABI
== ABI_AIX
8314 && GET_CODE (operands
[1]) == SYMBOL_REF
8315 && XSTR (operands
[1], 0)[0] == '.')
8317 const char *name
= XSTR (operands
[1], 0);
8319 while (*name
== '.')
8321 new_ref
= gen_rtx_SYMBOL_REF (Pmode
, name
);
8322 CONSTANT_POOL_ADDRESS_P (new_ref
)
8323 = CONSTANT_POOL_ADDRESS_P (operands
[1]);
8324 SYMBOL_REF_FLAGS (new_ref
) = SYMBOL_REF_FLAGS (operands
[1]);
8325 SYMBOL_REF_USED (new_ref
) = SYMBOL_REF_USED (operands
[1]);
8326 SYMBOL_REF_DATA (new_ref
) = SYMBOL_REF_DATA (operands
[1]);
8327 operands
[1] = new_ref
;
8330 if (DEFAULT_ABI
== ABI_DARWIN
)
8333 if (MACHO_DYNAMIC_NO_PIC_P
)
8335 /* Take care of any required data indirection. */
8336 operands
[1] = rs6000_machopic_legitimize_pic_address (
8337 operands
[1], mode
, operands
[0]);
8338 if (operands
[0] != operands
[1])
8339 emit_insn (gen_rtx_SET (VOIDmode
,
8340 operands
[0], operands
[1]));
8344 emit_insn (gen_macho_high (target
, operands
[1]));
8345 emit_insn (gen_macho_low (operands
[0], target
, operands
[1]));
8349 emit_insn (gen_elf_high (target
, operands
[1]));
8350 emit_insn (gen_elf_low (operands
[0], target
, operands
[1]));
8354 /* If this is a SYMBOL_REF that refers to a constant pool entry,
8355 and we have put it in the TOC, we just need to make a TOC-relative
8358 && GET_CODE (operands
[1]) == SYMBOL_REF
8359 && use_toc_relative_ref (operands
[1]))
8360 operands
[1] = create_TOC_reference (operands
[1], operands
[0]);
8361 else if (mode
== Pmode
8362 && CONSTANT_P (operands
[1])
8363 && GET_CODE (operands
[1]) != HIGH
8364 && ((GET_CODE (operands
[1]) != CONST_INT
8365 && ! easy_fp_constant (operands
[1], mode
))
8366 || (GET_CODE (operands
[1]) == CONST_INT
8367 && (num_insns_constant (operands
[1], mode
)
8368 > (TARGET_CMODEL
!= CMODEL_SMALL
? 3 : 2)))
8369 || (GET_CODE (operands
[0]) == REG
8370 && FP_REGNO_P (REGNO (operands
[0]))))
8371 && !toc_relative_expr_p (operands
[1], false)
8372 && (TARGET_CMODEL
== CMODEL_SMALL
8373 || can_create_pseudo_p ()
8374 || (REG_P (operands
[0])
8375 && INT_REG_OK_FOR_BASE_P (operands
[0], true))))
8379 /* Darwin uses a special PIC legitimizer. */
8380 if (DEFAULT_ABI
== ABI_DARWIN
&& MACHOPIC_INDIRECT
)
8383 rs6000_machopic_legitimize_pic_address (operands
[1], mode
,
8385 if (operands
[0] != operands
[1])
8386 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8391 /* If we are to limit the number of things we put in the TOC and
8392 this is a symbol plus a constant we can add in one insn,
8393 just put the symbol in the TOC and add the constant. Don't do
8394 this if reload is in progress. */
8395 if (GET_CODE (operands
[1]) == CONST
8396 && TARGET_NO_SUM_IN_TOC
&& ! reload_in_progress
8397 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
8398 && add_operand (XEXP (XEXP (operands
[1], 0), 1), mode
)
8399 && (GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == LABEL_REF
8400 || GET_CODE (XEXP (XEXP (operands
[1], 0), 0)) == SYMBOL_REF
)
8401 && ! side_effects_p (operands
[0]))
8404 force_const_mem (mode
, XEXP (XEXP (operands
[1], 0), 0));
8405 rtx other
= XEXP (XEXP (operands
[1], 0), 1);
8407 sym
= force_reg (mode
, sym
);
8408 emit_insn (gen_add3_insn (operands
[0], sym
, other
));
8412 operands
[1] = force_const_mem (mode
, operands
[1]);
8415 && GET_CODE (XEXP (operands
[1], 0)) == SYMBOL_REF
8416 && constant_pool_expr_p (XEXP (operands
[1], 0))
8417 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
8418 get_pool_constant (XEXP (operands
[1], 0)),
8419 get_pool_mode (XEXP (operands
[1], 0))))
8421 rtx tocref
= create_TOC_reference (XEXP (operands
[1], 0),
8423 operands
[1] = gen_const_mem (mode
, tocref
);
8424 set_mem_alias_set (operands
[1], get_TOC_alias_set ());
8430 if (!VECTOR_MEM_VSX_P (TImode
))
8431 rs6000_eliminate_indexed_memrefs (operands
);
8435 rs6000_eliminate_indexed_memrefs (operands
);
8439 fatal_insn ("bad move", gen_rtx_SET (VOIDmode
, dest
, source
));
8442 /* Above, we may have called force_const_mem which may have returned
8443 an invalid address. If we can, fix this up; otherwise, reload will
8444 have to deal with it. */
8445 if (GET_CODE (operands
[1]) == MEM
&& ! reload_in_progress
)
8446 operands
[1] = validize_mem (operands
[1]);
8449 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]));
8452 /* Return true if a structure, union or array containing FIELD should be
8453 accessed using `BLKMODE'.
8455 For the SPE, simd types are V2SI, and gcc can be tempted to put the
8456 entire thing in a DI and use subregs to access the internals.
8457 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the
8458 back-end. Because a single GPR can hold a V2SI, but not a DI, the
8459 best thing to do is set structs to BLKmode and avoid Severe Tire
8462 On e500 v2, DF and DI modes suffer from the same anomaly. DF can
8463 fit into 1, whereas DI still needs two. */
8466 rs6000_member_type_forces_blk (const_tree field
, enum machine_mode mode
)
8468 return ((TARGET_SPE
&& TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
8469 || (TARGET_E500_DOUBLE
&& mode
== DFmode
));
8472 /* Nonzero if we can use a floating-point register to pass this arg. */
8473 #define USE_FP_FOR_ARG_P(CUM,MODE) \
8474 (SCALAR_FLOAT_MODE_P (MODE) \
8475 && (CUM)->fregno <= FP_ARG_MAX_REG \
8476 && TARGET_HARD_FLOAT && TARGET_FPRS)
8478 /* Nonzero if we can use an AltiVec register to pass this arg. */
8479 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,NAMED) \
8480 (ALTIVEC_OR_VSX_VECTOR_MODE (MODE) \
8481 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
8482 && TARGET_ALTIVEC_ABI \
8485 /* Walk down the type tree of TYPE counting consecutive base elements.
8486 If *MODEP is VOIDmode, then set it to the first valid floating point
8487 or vector type. If a non-floating point or vector type is found, or
8488 if a floating point or vector type that doesn't match a non-VOIDmode
8489 *MODEP is found, then return -1, otherwise return the count in the
8493 rs6000_aggregate_candidate (const_tree type
, enum machine_mode
*modep
)
8495 enum machine_mode mode
;
8498 switch (TREE_CODE (type
))
8501 mode
= TYPE_MODE (type
);
8502 if (!SCALAR_FLOAT_MODE_P (mode
))
8505 if (*modep
== VOIDmode
)
8514 mode
= TYPE_MODE (TREE_TYPE (type
));
8515 if (!SCALAR_FLOAT_MODE_P (mode
))
8518 if (*modep
== VOIDmode
)
8527 if (!TARGET_ALTIVEC_ABI
|| !TARGET_ALTIVEC
)
8530 /* Use V4SImode as representative of all 128-bit vector types. */
8531 size
= int_size_in_bytes (type
);
8541 if (*modep
== VOIDmode
)
8544 /* Vector modes are considered to be opaque: two vectors are
8545 equivalent for the purposes of being homogeneous aggregates
8546 if they are the same size. */
8555 tree index
= TYPE_DOMAIN (type
);
8557 /* Can't handle incomplete types. */
8558 if (!COMPLETE_TYPE_P (type
))
8561 count
= rs6000_aggregate_candidate (TREE_TYPE (type
), modep
);
8564 || !TYPE_MAX_VALUE (index
)
8565 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index
))
8566 || !TYPE_MIN_VALUE (index
)
8567 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index
))
8571 count
*= (1 + tree_to_uhwi (TYPE_MAX_VALUE (index
))
8572 - tree_to_uhwi (TYPE_MIN_VALUE (index
)));
8574 /* There must be no padding. */
8575 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8587 /* Can't handle incomplete types. */
8588 if (!COMPLETE_TYPE_P (type
))
8591 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8593 if (TREE_CODE (field
) != FIELD_DECL
)
8596 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8602 /* There must be no padding. */
8603 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8610 case QUAL_UNION_TYPE
:
8612 /* These aren't very interesting except in a degenerate case. */
8617 /* Can't handle incomplete types. */
8618 if (!COMPLETE_TYPE_P (type
))
8621 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
8623 if (TREE_CODE (field
) != FIELD_DECL
)
8626 sub_count
= rs6000_aggregate_candidate (TREE_TYPE (field
), modep
);
8629 count
= count
> sub_count
? count
: sub_count
;
8632 /* There must be no padding. */
8633 if (wi::ne_p (TYPE_SIZE (type
), count
* GET_MODE_BITSIZE (*modep
)))
8646 /* If an argument, whose type is described by TYPE and MODE, is a homogeneous
8647 float or vector aggregate that shall be passed in FP/vector registers
8648 according to the ELFv2 ABI, return the homogeneous element mode in
8649 *ELT_MODE and the number of elements in *N_ELTS, and return TRUE.
8651 Otherwise, set *ELT_MODE to MODE and *N_ELTS to 1, and return FALSE. */
8654 rs6000_discover_homogeneous_aggregate (enum machine_mode mode
, const_tree type
,
8655 enum machine_mode
*elt_mode
,
8658 /* Note that we do not accept complex types at the top level as
8659 homogeneous aggregates; these types are handled via the
8660 targetm.calls.split_complex_arg mechanism. Complex types
8661 can be elements of homogeneous aggregates, however. */
8662 if (DEFAULT_ABI
== ABI_ELFv2
&& type
&& AGGREGATE_TYPE_P (type
))
8664 enum machine_mode field_mode
= VOIDmode
;
8665 int field_count
= rs6000_aggregate_candidate (type
, &field_mode
);
8667 if (field_count
> 0)
8669 int n_regs
= (SCALAR_FLOAT_MODE_P (field_mode
)?
8670 (GET_MODE_SIZE (field_mode
) + 7) >> 3 : 1);
8672 /* The ELFv2 ABI allows homogeneous aggregates to occupy
8673 up to AGGR_ARG_NUM_REG registers. */
8674 if (field_count
* n_regs
<= AGGR_ARG_NUM_REG
)
8677 *elt_mode
= field_mode
;
8679 *n_elts
= field_count
;
8692 /* Return a nonzero value to say to return the function value in
8693 memory, just as large structures are always returned. TYPE will be
8694 the data type of the value, and FNTYPE will be the type of the
8695 function doing the returning, or @code{NULL} for libcalls.
8697 The AIX ABI for the RS/6000 specifies that all structures are
8698 returned in memory. The Darwin ABI does the same.
8700 For the Darwin 64 Bit ABI, a function result can be returned in
8701 registers or in memory, depending on the size of the return data
8702 type. If it is returned in registers, the value occupies the same
8703 registers as it would if it were the first and only function
8704 argument. Otherwise, the function places its result in memory at
8705 the location pointed to by GPR3.
8707 The SVR4 ABI specifies that structures <= 8 bytes are returned in r3/r4,
8708 but a draft put them in memory, and GCC used to implement the draft
8709 instead of the final standard. Therefore, aix_struct_return
8710 controls this instead of DEFAULT_ABI; V.4 targets needing backward
8711 compatibility can change DRAFT_V4_STRUCT_RET to override the
8712 default, and -m switches get the final word. See
8713 rs6000_option_override_internal for more details.
8715 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
8716 long double support is enabled. These values are returned in memory.
8718 int_size_in_bytes returns -1 for variable size objects, which go in
8719 memory always. The cast to unsigned makes -1 > 8. */
8722 rs6000_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
8724 /* For the Darwin64 ABI, test if we can fit the return value in regs. */
8726 && rs6000_darwin64_abi
8727 && TREE_CODE (type
) == RECORD_TYPE
8728 && int_size_in_bytes (type
) > 0)
8730 CUMULATIVE_ARGS valcum
;
8734 valcum
.fregno
= FP_ARG_MIN_REG
;
8735 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
8736 /* Do a trial code generation as if this were going to be passed
8737 as an argument; if any part goes in memory, we return NULL. */
8738 valret
= rs6000_darwin64_record_arg (&valcum
, type
, true, true);
8741 /* Otherwise fall through to more conventional ABI rules. */
8744 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers */
8745 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (type
), type
,
8749 /* The ELFv2 ABI returns aggregates up to 16B in registers */
8750 if (DEFAULT_ABI
== ABI_ELFv2
&& AGGREGATE_TYPE_P (type
)
8751 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) <= 16)
8754 if (AGGREGATE_TYPE_P (type
)
8755 && (aix_struct_return
8756 || (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8))
8759 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
8760 modes only exist for GCC vector types if -maltivec. */
8761 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
8762 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
8765 /* Return synthetic vectors in memory. */
8766 if (TREE_CODE (type
) == VECTOR_TYPE
8767 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
8769 static bool warned_for_return_big_vectors
= false;
8770 if (!warned_for_return_big_vectors
)
8772 warning (0, "GCC vector returned by reference: "
8773 "non-standard ABI extension with no compatibility guarantee");
8774 warned_for_return_big_vectors
= true;
8779 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& TYPE_MODE (type
) == TFmode
)
8785 /* Specify whether values returned in registers should be at the most
8786 significant end of a register. We want aggregates returned by
8787 value to match the way aggregates are passed to functions. */
8790 rs6000_return_in_msb (const_tree valtype
)
8792 return (DEFAULT_ABI
== ABI_ELFv2
8794 && AGGREGATE_TYPE_P (valtype
)
8795 && FUNCTION_ARG_PADDING (TYPE_MODE (valtype
), valtype
) == upward
);
8798 #ifdef HAVE_AS_GNU_ATTRIBUTE
8799 /* Return TRUE if a call to function FNDECL may be one that
8800 potentially affects the function calling ABI of the object file. */
8803 call_ABI_of_interest (tree fndecl
)
8805 if (cgraph_state
== CGRAPH_STATE_EXPANSION
)
8807 struct cgraph_node
*c_node
;
8809 /* Libcalls are always interesting. */
8810 if (fndecl
== NULL_TREE
)
8813 /* Any call to an external function is interesting. */
8814 if (DECL_EXTERNAL (fndecl
))
8817 /* Interesting functions that we are emitting in this object file. */
8818 c_node
= cgraph_get_node (fndecl
);
8819 c_node
= cgraph_function_or_thunk_node (c_node
, NULL
);
8820 return !cgraph_only_called_directly_p (c_node
);
8826 /* Initialize a variable CUM of type CUMULATIVE_ARGS
8827 for a call to a function whose data type is FNTYPE.
8828 For a library call, FNTYPE is 0 and RETURN_MODE the return value mode.
8830 For incoming args we set the number of arguments in the prototype large
8831 so we never return a PARALLEL. */
8834 init_cumulative_args (CUMULATIVE_ARGS
*cum
, tree fntype
,
8835 rtx libname ATTRIBUTE_UNUSED
, int incoming
,
8836 int libcall
, int n_named_args
,
8837 tree fndecl ATTRIBUTE_UNUSED
,
8838 enum machine_mode return_mode ATTRIBUTE_UNUSED
)
8840 static CUMULATIVE_ARGS zero_cumulative
;
8842 *cum
= zero_cumulative
;
8844 cum
->fregno
= FP_ARG_MIN_REG
;
8845 cum
->vregno
= ALTIVEC_ARG_MIN_REG
;
8846 cum
->prototype
= (fntype
&& prototype_p (fntype
));
8847 cum
->call_cookie
= ((DEFAULT_ABI
== ABI_V4
&& libcall
)
8848 ? CALL_LIBCALL
: CALL_NORMAL
);
8849 cum
->sysv_gregno
= GP_ARG_MIN_REG
;
8850 cum
->stdarg
= stdarg_p (fntype
);
8852 cum
->nargs_prototype
= 0;
8853 if (incoming
|| cum
->prototype
)
8854 cum
->nargs_prototype
= n_named_args
;
8856 /* Check for a longcall attribute. */
8857 if ((!fntype
&& rs6000_default_long_calls
)
8859 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype
))
8860 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype
))))
8861 cum
->call_cookie
|= CALL_LONG
;
8863 if (TARGET_DEBUG_ARG
)
8865 fprintf (stderr
, "\ninit_cumulative_args:");
8868 tree ret_type
= TREE_TYPE (fntype
);
8869 fprintf (stderr
, " ret code = %s,",
8870 get_tree_code_name (TREE_CODE (ret_type
)));
8873 if (cum
->call_cookie
& CALL_LONG
)
8874 fprintf (stderr
, " longcall,");
8876 fprintf (stderr
, " proto = %d, nargs = %d\n",
8877 cum
->prototype
, cum
->nargs_prototype
);
8880 #ifdef HAVE_AS_GNU_ATTRIBUTE
8881 if (DEFAULT_ABI
== ABI_V4
)
8883 cum
->escapes
= call_ABI_of_interest (fndecl
);
8890 return_type
= TREE_TYPE (fntype
);
8891 return_mode
= TYPE_MODE (return_type
);
8894 return_type
= lang_hooks
.types
.type_for_mode (return_mode
, 0);
8896 if (return_type
!= NULL
)
8898 if (TREE_CODE (return_type
) == RECORD_TYPE
8899 && TYPE_TRANSPARENT_AGGR (return_type
))
8901 return_type
= TREE_TYPE (first_field (return_type
));
8902 return_mode
= TYPE_MODE (return_type
);
8904 if (AGGREGATE_TYPE_P (return_type
)
8905 && ((unsigned HOST_WIDE_INT
) int_size_in_bytes (return_type
)
8907 rs6000_returns_struct
= true;
8909 if (SCALAR_FLOAT_MODE_P (return_mode
))
8910 rs6000_passes_float
= true;
8911 else if (ALTIVEC_OR_VSX_VECTOR_MODE (return_mode
)
8912 || SPE_VECTOR_MODE (return_mode
))
8913 rs6000_passes_vector
= true;
8920 && TARGET_ALTIVEC_ABI
8921 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype
))))
8923 error ("cannot return value in vector register because"
8924 " altivec instructions are disabled, use -maltivec"
8929 /* Return true if TYPE must be passed on the stack and not in registers. */
8932 rs6000_must_pass_in_stack (enum machine_mode mode
, const_tree type
)
8934 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
|| TARGET_64BIT
)
8935 return must_pass_in_stack_var_size (mode
, type
);
8937 return must_pass_in_stack_var_size_or_pad (mode
, type
);
8940 /* If defined, a C expression which determines whether, and in which
8941 direction, to pad out an argument with extra space. The value
8942 should be of type `enum direction': either `upward' to pad above
8943 the argument, `downward' to pad below, or `none' to inhibit
8946 For the AIX ABI structs are always stored left shifted in their
8950 function_arg_padding (enum machine_mode mode
, const_tree type
)
8952 #ifndef AGGREGATE_PADDING_FIXED
8953 #define AGGREGATE_PADDING_FIXED 0
8955 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
8956 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
8959 if (!AGGREGATE_PADDING_FIXED
)
8961 /* GCC used to pass structures of the same size as integer types as
8962 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
8963 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
8964 passed padded downward, except that -mstrict-align further
8965 muddied the water in that multi-component structures of 2 and 4
8966 bytes in size were passed padded upward.
8968 The following arranges for best compatibility with previous
8969 versions of gcc, but removes the -mstrict-align dependency. */
8970 if (BYTES_BIG_ENDIAN
)
8972 HOST_WIDE_INT size
= 0;
8974 if (mode
== BLKmode
)
8976 if (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
)
8977 size
= int_size_in_bytes (type
);
8980 size
= GET_MODE_SIZE (mode
);
8982 if (size
== 1 || size
== 2 || size
== 4)
8988 if (AGGREGATES_PAD_UPWARD_ALWAYS
)
8990 if (type
!= 0 && AGGREGATE_TYPE_P (type
))
8994 /* Fall back to the default. */
8995 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
8998 /* If defined, a C expression that gives the alignment boundary, in bits,
8999 of an argument with the specified mode and type. If it is not defined,
9000 PARM_BOUNDARY is used for all arguments.
9002 V.4 wants long longs and doubles to be double word aligned. Just
9003 testing the mode size is a boneheaded way to do this as it means
9004 that other types such as complex int are also double word aligned.
9005 However, we're stuck with this because changing the ABI might break
9006 existing library interfaces.
9008 Doubleword align SPE vectors.
9009 Quadword align Altivec/VSX vectors.
9010 Quadword align large synthetic vector types. */
9013 rs6000_function_arg_boundary (enum machine_mode mode
, const_tree type
)
9015 enum machine_mode elt_mode
;
9018 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9020 if (DEFAULT_ABI
== ABI_V4
9021 && (GET_MODE_SIZE (mode
) == 8
9022 || (TARGET_HARD_FLOAT
9024 && (mode
== TFmode
|| mode
== TDmode
))))
9026 else if (SPE_VECTOR_MODE (mode
)
9027 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9028 && int_size_in_bytes (type
) >= 8
9029 && int_size_in_bytes (type
) < 16))
9031 else if (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9032 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9033 && int_size_in_bytes (type
) >= 16))
9035 else if (((TARGET_MACHO
&& rs6000_darwin64_abi
)
9036 || DEFAULT_ABI
== ABI_ELFv2
9037 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
9039 && type
&& TYPE_ALIGN (type
) > 64)
9042 return PARM_BOUNDARY
;
9045 /* The offset in words to the start of the parameter save area. */
9048 rs6000_parm_offset (void)
9050 return (DEFAULT_ABI
== ABI_V4
? 2
9051 : DEFAULT_ABI
== ABI_ELFv2
? 4
9055 /* For a function parm of MODE and TYPE, return the starting word in
9056 the parameter area. NWORDS of the parameter area are already used. */
9059 rs6000_parm_start (enum machine_mode mode
, const_tree type
,
9060 unsigned int nwords
)
9064 align
= rs6000_function_arg_boundary (mode
, type
) / PARM_BOUNDARY
- 1;
9065 return nwords
+ (-(rs6000_parm_offset () + nwords
) & align
);
9068 /* Compute the size (in words) of a function argument. */
9070 static unsigned long
9071 rs6000_arg_size (enum machine_mode mode
, const_tree type
)
9075 if (mode
!= BLKmode
)
9076 size
= GET_MODE_SIZE (mode
);
9078 size
= int_size_in_bytes (type
);
9081 return (size
+ 3) >> 2;
9083 return (size
+ 7) >> 3;
9086 /* Use this to flush pending int fields. */
9089 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS
*cum
,
9090 HOST_WIDE_INT bitpos
, int final
)
9092 unsigned int startbit
, endbit
;
9093 int intregs
, intoffset
;
9094 enum machine_mode mode
;
9096 /* Handle the situations where a float is taking up the first half
9097 of the GPR, and the other half is empty (typically due to
9098 alignment restrictions). We can detect this by a 8-byte-aligned
9099 int field, or by seeing that this is the final flush for this
9100 argument. Count the word and continue on. */
9101 if (cum
->floats_in_gpr
== 1
9102 && (cum
->intoffset
% 64 == 0
9103 || (cum
->intoffset
== -1 && final
)))
9106 cum
->floats_in_gpr
= 0;
9109 if (cum
->intoffset
== -1)
9112 intoffset
= cum
->intoffset
;
9113 cum
->intoffset
= -1;
9114 cum
->floats_in_gpr
= 0;
9116 if (intoffset
% BITS_PER_WORD
!= 0)
9118 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9120 if (mode
== BLKmode
)
9122 /* We couldn't find an appropriate mode, which happens,
9123 e.g., in packed structs when there are 3 bytes to load.
9124 Back intoffset back to the beginning of the word in this
9126 intoffset
= intoffset
& -BITS_PER_WORD
;
9130 startbit
= intoffset
& -BITS_PER_WORD
;
9131 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9132 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9133 cum
->words
+= intregs
;
9134 /* words should be unsigned. */
9135 if ((unsigned)cum
->words
< (endbit
/BITS_PER_WORD
))
9137 int pad
= (endbit
/BITS_PER_WORD
) - cum
->words
;
9142 /* The darwin64 ABI calls for us to recurse down through structs,
9143 looking for elements passed in registers. Unfortunately, we have
9144 to track int register count here also because of misalignments
9145 in powerpc alignment mode. */
9148 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS
*cum
,
9150 HOST_WIDE_INT startbitpos
)
9154 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9155 if (TREE_CODE (f
) == FIELD_DECL
)
9157 HOST_WIDE_INT bitpos
= startbitpos
;
9158 tree ftype
= TREE_TYPE (f
);
9159 enum machine_mode mode
;
9160 if (ftype
== error_mark_node
)
9162 mode
= TYPE_MODE (ftype
);
9164 if (DECL_SIZE (f
) != 0
9165 && tree_fits_uhwi_p (bit_position (f
)))
9166 bitpos
+= int_bit_position (f
);
9168 /* ??? FIXME: else assume zero offset. */
9170 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9171 rs6000_darwin64_record_arg_advance_recurse (cum
, ftype
, bitpos
);
9172 else if (USE_FP_FOR_ARG_P (cum
, mode
))
9174 unsigned n_fpregs
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9175 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9176 cum
->fregno
+= n_fpregs
;
9177 /* Single-precision floats present a special problem for
9178 us, because they are smaller than an 8-byte GPR, and so
9179 the structure-packing rules combined with the standard
9180 varargs behavior mean that we want to pack float/float
9181 and float/int combinations into a single register's
9182 space. This is complicated by the arg advance flushing,
9183 which works on arbitrarily large groups of int-type
9187 if (cum
->floats_in_gpr
== 1)
9189 /* Two floats in a word; count the word and reset
9192 cum
->floats_in_gpr
= 0;
9194 else if (bitpos
% 64 == 0)
9196 /* A float at the beginning of an 8-byte word;
9197 count it and put off adjusting cum->words until
9198 we see if a arg advance flush is going to do it
9200 cum
->floats_in_gpr
++;
9204 /* The float is at the end of a word, preceded
9205 by integer fields, so the arg advance flush
9206 just above has already set cum->words and
9207 everything is taken care of. */
9211 cum
->words
+= n_fpregs
;
9213 else if (USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9215 rs6000_darwin64_record_arg_advance_flush (cum
, bitpos
, 0);
9219 else if (cum
->intoffset
== -1)
9220 cum
->intoffset
= bitpos
;
9224 /* Check for an item that needs to be considered specially under the darwin 64
9225 bit ABI. These are record types where the mode is BLK or the structure is
9228 rs6000_darwin64_struct_check_p (enum machine_mode mode
, const_tree type
)
9230 return rs6000_darwin64_abi
9231 && ((mode
== BLKmode
9232 && TREE_CODE (type
) == RECORD_TYPE
9233 && int_size_in_bytes (type
) > 0)
9234 || (type
&& TREE_CODE (type
) == RECORD_TYPE
9235 && int_size_in_bytes (type
) == 8)) ? 1 : 0;
9238 /* Update the data in CUM to advance over an argument
9239 of mode MODE and data type TYPE.
9240 (TYPE is null for libcalls where that information may not be available.)
9242 Note that for args passed by reference, function_arg will be called
9243 with MODE and TYPE set to that of the pointer to the arg, not the arg
9247 rs6000_function_arg_advance_1 (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9248 const_tree type
, bool named
, int depth
)
9250 enum machine_mode elt_mode
;
9253 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9255 /* Only tick off an argument if we're not recursing. */
9257 cum
->nargs_prototype
--;
9259 #ifdef HAVE_AS_GNU_ATTRIBUTE
9260 if (DEFAULT_ABI
== ABI_V4
9263 if (SCALAR_FLOAT_MODE_P (mode
))
9264 rs6000_passes_float
= true;
9265 else if (named
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
9266 rs6000_passes_vector
= true;
9267 else if (SPE_VECTOR_MODE (mode
)
9269 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9270 rs6000_passes_vector
= true;
9274 if (TARGET_ALTIVEC_ABI
9275 && (ALTIVEC_OR_VSX_VECTOR_MODE (elt_mode
)
9276 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9277 && int_size_in_bytes (type
) == 16)))
9281 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9283 cum
->vregno
+= n_elts
;
9285 if (!TARGET_ALTIVEC
)
9286 error ("cannot pass argument in vector register because"
9287 " altivec instructions are disabled, use -maltivec"
9290 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
9291 even if it is going to be passed in a vector register.
9292 Darwin does the same for variable-argument functions. */
9293 if (((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
9295 || (cum
->stdarg
&& DEFAULT_ABI
!= ABI_V4
))
9305 /* Vector parameters must be 16-byte aligned. In 32-bit
9306 mode this means we need to take into account the offset
9307 to the parameter save area. In 64-bit mode, they just
9308 have to start on an even word, since the parameter save
9309 area is 16-byte aligned. */
9311 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9313 align
= cum
->words
& 1;
9314 cum
->words
+= align
+ rs6000_arg_size (mode
, type
);
9316 if (TARGET_DEBUG_ARG
)
9318 fprintf (stderr
, "function_adv: words = %2d, align=%d, ",
9320 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s\n",
9321 cum
->nargs_prototype
, cum
->prototype
,
9322 GET_MODE_NAME (mode
));
9326 else if (TARGET_SPE_ABI
&& TARGET_SPE
&& SPE_VECTOR_MODE (mode
)
9328 && cum
->sysv_gregno
<= GP_ARG_MAX_REG
)
9331 else if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9333 int size
= int_size_in_bytes (type
);
9334 /* Variable sized types have size == -1 and are
9335 treated as if consisting entirely of ints.
9336 Pad to 16 byte boundary if needed. */
9337 if (TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9338 && (cum
->words
% 2) != 0)
9340 /* For varargs, we can just go up by the size of the struct. */
9342 cum
->words
+= (size
+ 7) / 8;
9345 /* It is tempting to say int register count just goes up by
9346 sizeof(type)/8, but this is wrong in a case such as
9347 { int; double; int; } [powerpc alignment]. We have to
9348 grovel through the fields for these too. */
9350 cum
->floats_in_gpr
= 0;
9351 rs6000_darwin64_record_arg_advance_recurse (cum
, type
, 0);
9352 rs6000_darwin64_record_arg_advance_flush (cum
,
9353 size
* BITS_PER_UNIT
, 1);
9355 if (TARGET_DEBUG_ARG
)
9357 fprintf (stderr
, "function_adv: words = %2d, align=%d, size=%d",
9358 cum
->words
, TYPE_ALIGN (type
), size
);
9360 "nargs = %4d, proto = %d, mode = %4s (darwin64 abi)\n",
9361 cum
->nargs_prototype
, cum
->prototype
,
9362 GET_MODE_NAME (mode
));
9365 else if (DEFAULT_ABI
== ABI_V4
)
9367 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
9368 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
9369 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
9370 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
9371 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
9373 /* _Decimal128 must use an even/odd register pair. This assumes
9374 that the register number is odd when fregno is odd. */
9375 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9378 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
9379 <= FP_ARG_V4_MAX_REG
)
9380 cum
->fregno
+= (GET_MODE_SIZE (mode
) + 7) >> 3;
9383 cum
->fregno
= FP_ARG_V4_MAX_REG
+ 1;
9384 if (mode
== DFmode
|| mode
== TFmode
9385 || mode
== DDmode
|| mode
== TDmode
)
9386 cum
->words
+= cum
->words
& 1;
9387 cum
->words
+= rs6000_arg_size (mode
, type
);
9392 int n_words
= rs6000_arg_size (mode
, type
);
9393 int gregno
= cum
->sysv_gregno
;
9395 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
9396 (r7,r8) or (r9,r10). As does any other 2 word item such
9397 as complex int due to a historical mistake. */
9399 gregno
+= (1 - gregno
) & 1;
9401 /* Multi-reg args are not split between registers and stack. */
9402 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9404 /* Long long and SPE vectors are aligned on the stack.
9405 So are other 2 word items such as complex int due to
9406 a historical mistake. */
9408 cum
->words
+= cum
->words
& 1;
9409 cum
->words
+= n_words
;
9412 /* Note: continuing to accumulate gregno past when we've started
9413 spilling to the stack indicates the fact that we've started
9414 spilling to the stack to expand_builtin_saveregs. */
9415 cum
->sysv_gregno
= gregno
+ n_words
;
9418 if (TARGET_DEBUG_ARG
)
9420 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9421 cum
->words
, cum
->fregno
);
9422 fprintf (stderr
, "gregno = %2d, nargs = %4d, proto = %d, ",
9423 cum
->sysv_gregno
, cum
->nargs_prototype
, cum
->prototype
);
9424 fprintf (stderr
, "mode = %4s, named = %d\n",
9425 GET_MODE_NAME (mode
), named
);
9430 int n_words
= rs6000_arg_size (mode
, type
);
9431 int start_words
= cum
->words
;
9432 int align_words
= rs6000_parm_start (mode
, type
, start_words
);
9434 cum
->words
= align_words
+ n_words
;
9436 if (SCALAR_FLOAT_MODE_P (elt_mode
)
9437 && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9439 /* _Decimal128 must be passed in an even/odd float register pair.
9440 This assumes that the register number is odd when fregno is
9442 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
9444 cum
->fregno
+= n_elts
* ((GET_MODE_SIZE (elt_mode
) + 7) >> 3);
9447 if (TARGET_DEBUG_ARG
)
9449 fprintf (stderr
, "function_adv: words = %2d, fregno = %2d, ",
9450 cum
->words
, cum
->fregno
);
9451 fprintf (stderr
, "nargs = %4d, proto = %d, mode = %4s, ",
9452 cum
->nargs_prototype
, cum
->prototype
, GET_MODE_NAME (mode
));
9453 fprintf (stderr
, "named = %d, align = %d, depth = %d\n",
9454 named
, align_words
- start_words
, depth
);
9460 rs6000_function_arg_advance (cumulative_args_t cum
, enum machine_mode mode
,
9461 const_tree type
, bool named
)
9463 rs6000_function_arg_advance_1 (get_cumulative_args (cum
), mode
, type
, named
,
9468 spe_build_register_parallel (enum machine_mode mode
, int gregno
)
9475 r1
= gen_rtx_REG (DImode
, gregno
);
9476 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9477 return gen_rtx_PARALLEL (mode
, gen_rtvec (1, r1
));
9481 r1
= gen_rtx_REG (DImode
, gregno
);
9482 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9483 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9484 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9485 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r3
));
9488 r1
= gen_rtx_REG (DImode
, gregno
);
9489 r1
= gen_rtx_EXPR_LIST (VOIDmode
, r1
, const0_rtx
);
9490 r3
= gen_rtx_REG (DImode
, gregno
+ 2);
9491 r3
= gen_rtx_EXPR_LIST (VOIDmode
, r3
, GEN_INT (8));
9492 r5
= gen_rtx_REG (DImode
, gregno
+ 4);
9493 r5
= gen_rtx_EXPR_LIST (VOIDmode
, r5
, GEN_INT (16));
9494 r7
= gen_rtx_REG (DImode
, gregno
+ 6);
9495 r7
= gen_rtx_EXPR_LIST (VOIDmode
, r7
, GEN_INT (24));
9496 return gen_rtx_PARALLEL (mode
, gen_rtvec (4, r1
, r3
, r5
, r7
));
9503 /* Determine where to put a SIMD argument on the SPE. */
9505 rs6000_spe_function_arg (const CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
9508 int gregno
= cum
->sysv_gregno
;
9510 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
9511 are passed and returned in a pair of GPRs for ABI compatibility. */
9512 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
9513 || mode
== DCmode
|| mode
== TCmode
))
9515 int n_words
= rs6000_arg_size (mode
, type
);
9517 /* Doubles go in an odd/even register pair (r5/r6, etc). */
9519 gregno
+= (1 - gregno
) & 1;
9521 /* Multi-reg args are not split between registers and stack. */
9522 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
9525 return spe_build_register_parallel (mode
, gregno
);
9529 int n_words
= rs6000_arg_size (mode
, type
);
9531 /* SPE vectors are put in odd registers. */
9532 if (n_words
== 2 && (gregno
& 1) == 0)
9535 if (gregno
+ n_words
- 1 <= GP_ARG_MAX_REG
)
9538 enum machine_mode m
= SImode
;
9540 r1
= gen_rtx_REG (m
, gregno
);
9541 r1
= gen_rtx_EXPR_LIST (m
, r1
, const0_rtx
);
9542 r2
= gen_rtx_REG (m
, gregno
+ 1);
9543 r2
= gen_rtx_EXPR_LIST (m
, r2
, GEN_INT (4));
9544 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
9551 if (gregno
<= GP_ARG_MAX_REG
)
9552 return gen_rtx_REG (mode
, gregno
);
9558 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
9559 structure between cum->intoffset and bitpos to integer registers. */
9562 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS
*cum
,
9563 HOST_WIDE_INT bitpos
, rtx rvec
[], int *k
)
9565 enum machine_mode mode
;
9567 unsigned int startbit
, endbit
;
9568 int this_regno
, intregs
, intoffset
;
9571 if (cum
->intoffset
== -1)
9574 intoffset
= cum
->intoffset
;
9575 cum
->intoffset
= -1;
9577 /* If this is the trailing part of a word, try to only load that
9578 much into the register. Otherwise load the whole register. Note
9579 that in the latter case we may pick up unwanted bits. It's not a
9580 problem at the moment but may wish to revisit. */
9582 if (intoffset
% BITS_PER_WORD
!= 0)
9584 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
9586 if (mode
== BLKmode
)
9588 /* We couldn't find an appropriate mode, which happens,
9589 e.g., in packed structs when there are 3 bytes to load.
9590 Back intoffset back to the beginning of the word in this
9592 intoffset
= intoffset
& -BITS_PER_WORD
;
9599 startbit
= intoffset
& -BITS_PER_WORD
;
9600 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
9601 intregs
= (endbit
- startbit
) / BITS_PER_WORD
;
9602 this_regno
= cum
->words
+ intoffset
/ BITS_PER_WORD
;
9604 if (intregs
> 0 && intregs
> GP_ARG_NUM_REG
- this_regno
)
9607 intregs
= MIN (intregs
, GP_ARG_NUM_REG
- this_regno
);
9611 intoffset
/= BITS_PER_UNIT
;
9614 regno
= GP_ARG_MIN_REG
+ this_regno
;
9615 reg
= gen_rtx_REG (mode
, regno
);
9617 gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
9620 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
9624 while (intregs
> 0);
9627 /* Recursive workhorse for the following. */
9630 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS
*cum
, const_tree type
,
9631 HOST_WIDE_INT startbitpos
, rtx rvec
[],
9636 for (f
= TYPE_FIELDS (type
); f
; f
= DECL_CHAIN (f
))
9637 if (TREE_CODE (f
) == FIELD_DECL
)
9639 HOST_WIDE_INT bitpos
= startbitpos
;
9640 tree ftype
= TREE_TYPE (f
);
9641 enum machine_mode mode
;
9642 if (ftype
== error_mark_node
)
9644 mode
= TYPE_MODE (ftype
);
9646 if (DECL_SIZE (f
) != 0
9647 && tree_fits_uhwi_p (bit_position (f
)))
9648 bitpos
+= int_bit_position (f
);
9650 /* ??? FIXME: else assume zero offset. */
9652 if (TREE_CODE (ftype
) == RECORD_TYPE
)
9653 rs6000_darwin64_record_arg_recurse (cum
, ftype
, bitpos
, rvec
, k
);
9654 else if (cum
->named
&& USE_FP_FOR_ARG_P (cum
, mode
))
9656 unsigned n_fpreg
= (GET_MODE_SIZE (mode
) + 7) >> 3;
9660 case SCmode
: mode
= SFmode
; break;
9661 case DCmode
: mode
= DFmode
; break;
9662 case TCmode
: mode
= TFmode
; break;
9666 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9667 if (cum
->fregno
+ n_fpreg
> FP_ARG_MAX_REG
+ 1)
9669 gcc_assert (cum
->fregno
== FP_ARG_MAX_REG
9670 && (mode
== TFmode
|| mode
== TDmode
));
9671 /* Long double or _Decimal128 split over regs and memory. */
9672 mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
: DFmode
;
9676 = gen_rtx_EXPR_LIST (VOIDmode
,
9677 gen_rtx_REG (mode
, cum
->fregno
++),
9678 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9679 if (mode
== TFmode
|| mode
== TDmode
)
9682 else if (cum
->named
&& USE_ALTIVEC_FOR_ARG_P (cum
, mode
, 1))
9684 rs6000_darwin64_record_arg_flush (cum
, bitpos
, rvec
, k
);
9686 = gen_rtx_EXPR_LIST (VOIDmode
,
9687 gen_rtx_REG (mode
, cum
->vregno
++),
9688 GEN_INT (bitpos
/ BITS_PER_UNIT
));
9690 else if (cum
->intoffset
== -1)
9691 cum
->intoffset
= bitpos
;
9695 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
9696 the register(s) to be used for each field and subfield of a struct
9697 being passed by value, along with the offset of where the
9698 register's value may be found in the block. FP fields go in FP
9699 register, vector fields go in vector registers, and everything
9700 else goes in int registers, packed as in memory.
9702 This code is also used for function return values. RETVAL indicates
9703 whether this is the case.
9705 Much of this is taken from the SPARC V9 port, which has a similar
9706 calling convention. */
9709 rs6000_darwin64_record_arg (CUMULATIVE_ARGS
*orig_cum
, const_tree type
,
9710 bool named
, bool retval
)
9712 rtx rvec
[FIRST_PSEUDO_REGISTER
];
9713 int k
= 1, kbase
= 1;
9714 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
9715 /* This is a copy; modifications are not visible to our caller. */
9716 CUMULATIVE_ARGS copy_cum
= *orig_cum
;
9717 CUMULATIVE_ARGS
*cum
= ©_cum
;
9719 /* Pad to 16 byte boundary if needed. */
9720 if (!retval
&& TYPE_ALIGN (type
) >= 2 * BITS_PER_WORD
9721 && (cum
->words
% 2) != 0)
9728 /* Put entries into rvec[] for individual FP and vector fields, and
9729 for the chunks of memory that go in int regs. Note we start at
9730 element 1; 0 is reserved for an indication of using memory, and
9731 may or may not be filled in below. */
9732 rs6000_darwin64_record_arg_recurse (cum
, type
, /* startbit pos= */ 0, rvec
, &k
);
9733 rs6000_darwin64_record_arg_flush (cum
, typesize
* BITS_PER_UNIT
, rvec
, &k
);
9735 /* If any part of the struct went on the stack put all of it there.
9736 This hack is because the generic code for
9737 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
9738 parts of the struct are not at the beginning. */
9742 return NULL_RTX
; /* doesn't go in registers at all */
9744 rvec
[0] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9746 if (k
> 1 || cum
->use_stack
)
9747 return gen_rtx_PARALLEL (BLKmode
, gen_rtvec_v (k
- kbase
, &rvec
[kbase
]));
9752 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
9755 rs6000_mixed_function_arg (enum machine_mode mode
, const_tree type
,
9760 rtx rvec
[GP_ARG_NUM_REG
+ 1];
9762 if (align_words
>= GP_ARG_NUM_REG
)
9765 n_units
= rs6000_arg_size (mode
, type
);
9767 /* Optimize the simple case where the arg fits in one gpr, except in
9768 the case of BLKmode due to assign_parms assuming that registers are
9769 BITS_PER_WORD wide. */
9771 || (n_units
== 1 && mode
!= BLKmode
))
9772 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9775 if (align_words
+ n_units
> GP_ARG_NUM_REG
)
9776 /* Not all of the arg fits in gprs. Say that it goes in memory too,
9777 using a magic NULL_RTX component.
9778 This is not strictly correct. Only some of the arg belongs in
9779 memory, not all of it. However, the normal scheme using
9780 function_arg_partial_nregs can result in unusual subregs, eg.
9781 (subreg:SI (reg:DF) 4), which are not handled well. The code to
9782 store the whole arg to memory is often more efficient than code
9783 to store pieces, and we know that space is available in the right
9784 place for the whole arg. */
9785 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9790 rtx r
= gen_rtx_REG (SImode
, GP_ARG_MIN_REG
+ align_words
);
9791 rtx off
= GEN_INT (i
++ * 4);
9792 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9794 while (++align_words
< GP_ARG_NUM_REG
&& --n_units
!= 0);
9796 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9799 /* We have an argument of MODE and TYPE that goes into FPRs or VRs,
9800 but must also be copied into the parameter save area starting at
9801 offset ALIGN_WORDS. Fill in RVEC with the elements corresponding
9802 to the GPRs and/or memory. Return the number of elements used. */
9805 rs6000_psave_function_arg (enum machine_mode mode
, const_tree type
,
9806 int align_words
, rtx
*rvec
)
9810 if (align_words
< GP_ARG_NUM_REG
)
9812 int n_words
= rs6000_arg_size (mode
, type
);
9814 if (align_words
+ n_words
> GP_ARG_NUM_REG
9816 || (TARGET_32BIT
&& TARGET_POWERPC64
))
9818 /* If this is partially on the stack, then we only
9819 include the portion actually in registers here. */
9820 enum machine_mode rmode
= TARGET_32BIT
? SImode
: DImode
;
9823 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
9825 /* Not all of the arg fits in gprs. Say that it goes in memory
9826 too, using a magic NULL_RTX component. Also see comment in
9827 rs6000_mixed_function_arg for why the normal
9828 function_arg_partial_nregs scheme doesn't work in this case. */
9829 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9834 rtx r
= gen_rtx_REG (rmode
, GP_ARG_MIN_REG
+ align_words
);
9835 rtx off
= GEN_INT (i
++ * GET_MODE_SIZE (rmode
));
9836 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9838 while (++align_words
< GP_ARG_NUM_REG
&& --n_words
!= 0);
9842 /* The whole arg fits in gprs. */
9843 rtx r
= gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
9844 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, const0_rtx
);
9849 /* It's entirely in memory. */
9850 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
9856 /* RVEC is a vector of K components of an argument of mode MODE.
9857 Construct the final function_arg return value from it. */
9860 rs6000_finish_function_arg (enum machine_mode mode
, rtx
*rvec
, int k
)
9862 gcc_assert (k
>= 1);
9864 /* Avoid returning a PARALLEL in the trivial cases. */
9867 if (XEXP (rvec
[0], 0) == NULL_RTX
)
9870 if (GET_MODE (XEXP (rvec
[0], 0)) == mode
)
9871 return XEXP (rvec
[0], 0);
9874 return gen_rtx_PARALLEL (mode
, gen_rtvec_v (k
, rvec
));
9877 /* Determine where to put an argument to a function.
9878 Value is zero to push the argument on the stack,
9879 or a hard register in which to store the argument.
9881 MODE is the argument's machine mode.
9882 TYPE is the data type of the argument (as a tree).
9883 This is null for libcalls where that information may
9885 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9886 the preceding args and about the function being called. It is
9887 not modified in this routine.
9888 NAMED is nonzero if this argument is a named parameter
9889 (otherwise it is an extra parameter matching an ellipsis).
9891 On RS/6000 the first eight words of non-FP are normally in registers
9892 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
9893 Under V.4, the first 8 FP args are in registers.
9895 If this is floating-point and no prototype is specified, we use
9896 both an FP and integer register (or possibly FP reg and stack). Library
9897 functions (when CALL_LIBCALL is set) always have the proper types for args,
9898 so we can pass the FP value just in one register. emit_library_function
9899 doesn't support PARALLEL anyway.
9901 Note that for args passed by reference, function_arg will be called
9902 with MODE and TYPE set to that of the pointer to the arg, not the arg
9906 rs6000_function_arg (cumulative_args_t cum_v
, enum machine_mode mode
,
9907 const_tree type
, bool named
)
9909 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
9910 enum rs6000_abi abi
= DEFAULT_ABI
;
9911 enum machine_mode elt_mode
;
9914 /* Return a marker to indicate whether CR1 needs to set or clear the
9915 bit that V.4 uses to say fp args were passed in registers.
9916 Assume that we don't need the marker for software floating point,
9917 or compiler generated library calls. */
9918 if (mode
== VOIDmode
)
9921 && (cum
->call_cookie
& CALL_LIBCALL
) == 0
9923 || (cum
->nargs_prototype
< 0
9924 && (cum
->prototype
|| TARGET_NO_PROTOTYPE
))))
9926 /* For the SPE, we need to crxor CR6 always. */
9928 return GEN_INT (cum
->call_cookie
| CALL_V4_SET_FP_ARGS
);
9929 else if (TARGET_HARD_FLOAT
&& TARGET_FPRS
)
9930 return GEN_INT (cum
->call_cookie
9931 | ((cum
->fregno
== FP_ARG_MIN_REG
)
9932 ? CALL_V4_SET_FP_ARGS
9933 : CALL_V4_CLEAR_FP_ARGS
));
9936 return GEN_INT (cum
->call_cookie
& ~CALL_LIBCALL
);
9939 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
9941 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
9943 rtx rslt
= rs6000_darwin64_record_arg (cum
, type
, named
, /*retval= */false);
9944 if (rslt
!= NULL_RTX
)
9946 /* Else fall through to usual handling. */
9949 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
9951 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
9955 /* Do we also need to pass this argument in the parameter
9957 if (TARGET_64BIT
&& ! cum
->prototype
)
9959 int align_words
= (cum
->words
+ 1) & ~1;
9960 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
9963 /* Describe where this argument goes in the vector registers. */
9964 for (i
= 0; i
< n_elts
&& cum
->vregno
+ i
<= ALTIVEC_ARG_MAX_REG
; i
++)
9966 r
= gen_rtx_REG (elt_mode
, cum
->vregno
+ i
);
9967 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
9968 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
9971 return rs6000_finish_function_arg (mode
, rvec
, k
);
9973 else if (TARGET_ALTIVEC_ABI
9974 && (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
9975 || (type
&& TREE_CODE (type
) == VECTOR_TYPE
9976 && int_size_in_bytes (type
) == 16)))
9978 if (named
|| abi
== ABI_V4
)
9982 /* Vector parameters to varargs functions under AIX or Darwin
9983 get passed in memory and possibly also in GPRs. */
9984 int align
, align_words
, n_words
;
9985 enum machine_mode part_mode
;
9987 /* Vector parameters must be 16-byte aligned. In 32-bit
9988 mode this means we need to take into account the offset
9989 to the parameter save area. In 64-bit mode, they just
9990 have to start on an even word, since the parameter save
9991 area is 16-byte aligned. */
9993 align
= -(rs6000_parm_offset () + cum
->words
) & 3;
9995 align
= cum
->words
& 1;
9996 align_words
= cum
->words
+ align
;
9998 /* Out of registers? Memory, then. */
9999 if (align_words
>= GP_ARG_NUM_REG
)
10002 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10003 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10005 /* The vector value goes in GPRs. Only the part of the
10006 value in GPRs is reported here. */
10008 n_words
= rs6000_arg_size (mode
, type
);
10009 if (align_words
+ n_words
> GP_ARG_NUM_REG
)
10010 /* Fortunately, there are only two possibilities, the value
10011 is either wholly in GPRs or half in GPRs and half not. */
10012 part_mode
= DImode
;
10014 return gen_rtx_REG (part_mode
, GP_ARG_MIN_REG
+ align_words
);
10017 else if (TARGET_SPE_ABI
&& TARGET_SPE
10018 && (SPE_VECTOR_MODE (mode
)
10019 || (TARGET_E500_DOUBLE
&& (mode
== DFmode
10022 || mode
== TCmode
))))
10023 return rs6000_spe_function_arg (cum
, mode
, type
);
10025 else if (abi
== ABI_V4
)
10027 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10028 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
)
10029 || (TARGET_DOUBLE_FLOAT
&& mode
== DFmode
)
10030 || (mode
== TFmode
&& !TARGET_IEEEQUAD
)
10031 || mode
== SDmode
|| mode
== DDmode
|| mode
== TDmode
))
10033 /* _Decimal128 must use an even/odd register pair. This assumes
10034 that the register number is odd when fregno is odd. */
10035 if (mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10038 if (cum
->fregno
+ (mode
== TFmode
|| mode
== TDmode
? 1 : 0)
10039 <= FP_ARG_V4_MAX_REG
)
10040 return gen_rtx_REG (mode
, cum
->fregno
);
10046 int n_words
= rs6000_arg_size (mode
, type
);
10047 int gregno
= cum
->sysv_gregno
;
10049 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
10050 (r7,r8) or (r9,r10). As does any other 2 word item such
10051 as complex int due to a historical mistake. */
10053 gregno
+= (1 - gregno
) & 1;
10055 /* Multi-reg args are not split between registers and stack. */
10056 if (gregno
+ n_words
- 1 > GP_ARG_MAX_REG
)
10059 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10060 return rs6000_mixed_function_arg (mode
, type
,
10061 gregno
- GP_ARG_MIN_REG
);
10062 return gen_rtx_REG (mode
, gregno
);
10067 int align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10069 /* _Decimal128 must be passed in an even/odd float register pair.
10070 This assumes that the register number is odd when fregno is odd. */
10071 if (elt_mode
== TDmode
&& (cum
->fregno
% 2) == 1)
10074 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10076 rtx rvec
[GP_ARG_NUM_REG
+ AGGR_ARG_NUM_REG
+ 1];
10079 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10081 /* Do we also need to pass this argument in the parameter
10083 if (type
&& (cum
->nargs_prototype
<= 0
10084 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10085 && TARGET_XL_COMPAT
10086 && align_words
>= GP_ARG_NUM_REG
)))
10087 k
= rs6000_psave_function_arg (mode
, type
, align_words
, rvec
);
10089 /* Describe where this argument goes in the fprs. */
10090 for (i
= 0; i
< n_elts
10091 && cum
->fregno
+ i
* n_fpreg
<= FP_ARG_MAX_REG
; i
++)
10093 /* Check if the argument is split over registers and memory.
10094 This can only ever happen for long double or _Decimal128;
10095 complex types are handled via split_complex_arg. */
10096 enum machine_mode fmode
= elt_mode
;
10097 if (cum
->fregno
+ (i
+ 1) * n_fpreg
> FP_ARG_MAX_REG
+ 1)
10099 gcc_assert (fmode
== TFmode
|| fmode
== TDmode
);
10100 fmode
= DECIMAL_FLOAT_MODE_P (fmode
) ? DDmode
: DFmode
;
10103 r
= gen_rtx_REG (fmode
, cum
->fregno
+ i
* n_fpreg
);
10104 off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
10105 rvec
[k
++] = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
10108 return rs6000_finish_function_arg (mode
, rvec
, k
);
10110 else if (align_words
< GP_ARG_NUM_REG
)
10112 if (TARGET_32BIT
&& TARGET_POWERPC64
)
10113 return rs6000_mixed_function_arg (mode
, type
, align_words
);
10115 return gen_rtx_REG (mode
, GP_ARG_MIN_REG
+ align_words
);
10122 /* For an arg passed partly in registers and partly in memory, this is
10123 the number of bytes passed in registers. For args passed entirely in
10124 registers or entirely in memory, zero. When an arg is described by a
10125 PARALLEL, perhaps using more than one register type, this function
10126 returns the number of bytes used by the first element of the PARALLEL. */
10129 rs6000_arg_partial_bytes (cumulative_args_t cum_v
, enum machine_mode mode
,
10130 tree type
, bool named
)
10132 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
10133 bool passed_in_gprs
= true;
10136 enum machine_mode elt_mode
;
10139 rs6000_discover_homogeneous_aggregate (mode
, type
, &elt_mode
, &n_elts
);
10141 if (DEFAULT_ABI
== ABI_V4
)
10144 if (USE_ALTIVEC_FOR_ARG_P (cum
, elt_mode
, named
))
10146 /* If we are passing this arg in the fixed parameter save area
10147 (gprs or memory) as well as VRs, we do not use the partial
10148 bytes mechanism; instead, rs6000_function_arg will return a
10149 PARALLEL including a memory element as necessary. */
10150 if (TARGET_64BIT
&& ! cum
->prototype
)
10153 /* Otherwise, we pass in VRs only. Check for partial copies. */
10154 passed_in_gprs
= false;
10155 if (cum
->vregno
+ n_elts
> ALTIVEC_ARG_MAX_REG
+ 1)
10156 ret
= (ALTIVEC_ARG_MAX_REG
+ 1 - cum
->vregno
) * 16;
10159 /* In this complicated case we just disable the partial_nregs code. */
10160 if (TARGET_MACHO
&& rs6000_darwin64_struct_check_p (mode
, type
))
10163 align_words
= rs6000_parm_start (mode
, type
, cum
->words
);
10165 if (USE_FP_FOR_ARG_P (cum
, elt_mode
))
10167 unsigned long n_fpreg
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
10169 /* If we are passing this arg in the fixed parameter save area
10170 (gprs or memory) as well as FPRs, we do not use the partial
10171 bytes mechanism; instead, rs6000_function_arg will return a
10172 PARALLEL including a memory element as necessary. */
10174 && (cum
->nargs_prototype
<= 0
10175 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
10176 && TARGET_XL_COMPAT
10177 && align_words
>= GP_ARG_NUM_REG
)))
10180 /* Otherwise, we pass in FPRs only. Check for partial copies. */
10181 passed_in_gprs
= false;
10182 if (cum
->fregno
+ n_elts
* n_fpreg
> FP_ARG_MAX_REG
+ 1)
10183 ret
= ((FP_ARG_MAX_REG
+ 1 - cum
->fregno
)
10184 * MIN (8, GET_MODE_SIZE (elt_mode
)));
10188 && align_words
< GP_ARG_NUM_REG
10189 && GP_ARG_NUM_REG
< align_words
+ rs6000_arg_size (mode
, type
))
10190 ret
= (GP_ARG_NUM_REG
- align_words
) * (TARGET_32BIT
? 4 : 8);
10192 if (ret
!= 0 && TARGET_DEBUG_ARG
)
10193 fprintf (stderr
, "rs6000_arg_partial_bytes: %d\n", ret
);
10198 /* A C expression that indicates when an argument must be passed by
10199 reference. If nonzero for an argument, a copy of that argument is
10200 made in memory and a pointer to the argument is passed instead of
10201 the argument itself. The pointer is passed in whatever way is
10202 appropriate for passing a pointer to that type.
10204 Under V.4, aggregates and long double are passed by reference.
10206 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
10207 reference unless the AltiVec vector extension ABI is in force.
10209 As an extension to all ABIs, variable sized types are passed by
10213 rs6000_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
10214 enum machine_mode mode
, const_tree type
,
10215 bool named ATTRIBUTE_UNUSED
)
10217 if (DEFAULT_ABI
== ABI_V4
&& TARGET_IEEEQUAD
&& mode
== TFmode
)
10219 if (TARGET_DEBUG_ARG
)
10220 fprintf (stderr
, "function_arg_pass_by_reference: V4 long double\n");
10227 if (DEFAULT_ABI
== ABI_V4
&& AGGREGATE_TYPE_P (type
))
10229 if (TARGET_DEBUG_ARG
)
10230 fprintf (stderr
, "function_arg_pass_by_reference: V4 aggregate\n");
10234 if (int_size_in_bytes (type
) < 0)
10236 if (TARGET_DEBUG_ARG
)
10237 fprintf (stderr
, "function_arg_pass_by_reference: variable size\n");
10241 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
10242 modes only exist for GCC vector types if -maltivec. */
10243 if (TARGET_32BIT
&& !TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
10245 if (TARGET_DEBUG_ARG
)
10246 fprintf (stderr
, "function_arg_pass_by_reference: AltiVec\n");
10250 /* Pass synthetic vectors in memory. */
10251 if (TREE_CODE (type
) == VECTOR_TYPE
10252 && int_size_in_bytes (type
) > (TARGET_ALTIVEC_ABI
? 16 : 8))
10254 static bool warned_for_pass_big_vectors
= false;
10255 if (TARGET_DEBUG_ARG
)
10256 fprintf (stderr
, "function_arg_pass_by_reference: synthetic vector\n");
10257 if (!warned_for_pass_big_vectors
)
10259 warning (0, "GCC vector passed by reference: "
10260 "non-standard ABI extension with no compatibility guarantee");
10261 warned_for_pass_big_vectors
= true;
10269 /* Process parameter of type TYPE after ARGS_SO_FAR parameters were
10270 already processes. Return true if the parameter must be passed
10271 (fully or partially) on the stack. */
10274 rs6000_parm_needs_stack (cumulative_args_t args_so_far
, tree type
)
10276 enum machine_mode mode
;
10280 /* Catch errors. */
10281 if (type
== NULL
|| type
== error_mark_node
)
10284 /* Handle types with no storage requirement. */
10285 if (TYPE_MODE (type
) == VOIDmode
)
10288 /* Handle complex types. */
10289 if (TREE_CODE (type
) == COMPLEX_TYPE
)
10290 return (rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
))
10291 || rs6000_parm_needs_stack (args_so_far
, TREE_TYPE (type
)));
10293 /* Handle transparent aggregates. */
10294 if ((TREE_CODE (type
) == UNION_TYPE
|| TREE_CODE (type
) == RECORD_TYPE
)
10295 && TYPE_TRANSPARENT_AGGR (type
))
10296 type
= TREE_TYPE (first_field (type
));
10298 /* See if this arg was passed by invisible reference. */
10299 if (pass_by_reference (get_cumulative_args (args_so_far
),
10300 TYPE_MODE (type
), type
, true))
10301 type
= build_pointer_type (type
);
10303 /* Find mode as it is passed by the ABI. */
10304 unsignedp
= TYPE_UNSIGNED (type
);
10305 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
);
10307 /* If we must pass in stack, we need a stack. */
10308 if (rs6000_must_pass_in_stack (mode
, type
))
10311 /* If there is no incoming register, we need a stack. */
10312 entry_parm
= rs6000_function_arg (args_so_far
, mode
, type
, true);
10313 if (entry_parm
== NULL
)
10316 /* Likewise if we need to pass both in registers and on the stack. */
10317 if (GET_CODE (entry_parm
) == PARALLEL
10318 && XEXP (XVECEXP (entry_parm
, 0, 0), 0) == NULL_RTX
)
10321 /* Also true if we're partially in registers and partially not. */
10322 if (rs6000_arg_partial_bytes (args_so_far
, mode
, type
, true) != 0)
10325 /* Update info on where next arg arrives in registers. */
10326 rs6000_function_arg_advance (args_so_far
, mode
, type
, true);
10330 /* Return true if FUN has no prototype, has a variable argument
10331 list, or passes any parameter in memory. */
10334 rs6000_function_parms_need_stack (tree fun
)
10336 function_args_iterator args_iter
;
10338 CUMULATIVE_ARGS args_so_far_v
;
10339 cumulative_args_t args_so_far
;
10342 /* Must be a libcall, all of which only use reg parms. */
10345 fun
= TREE_TYPE (fun
);
10347 /* Varargs functions need the parameter save area. */
10348 if (!prototype_p (fun
) || stdarg_p (fun
))
10351 INIT_CUMULATIVE_INCOMING_ARGS (args_so_far_v
, fun
, NULL_RTX
);
10352 args_so_far
= pack_cumulative_args (&args_so_far_v
);
10354 if (aggregate_value_p (TREE_TYPE (fun
), fun
))
10356 tree type
= build_pointer_type (TREE_TYPE (fun
));
10357 rs6000_parm_needs_stack (args_so_far
, type
);
10360 FOREACH_FUNCTION_ARGS (fun
, arg_type
, args_iter
)
10361 if (rs6000_parm_needs_stack (args_so_far
, arg_type
))
10367 /* Return the size of the REG_PARM_STACK_SPACE are for FUN. This is
10368 usually a constant depending on the ABI. However, in the ELFv2 ABI
10369 the register parameter area is optional when calling a function that
10370 has a prototype is scope, has no variable argument list, and passes
10371 all parameters in registers. */
10374 rs6000_reg_parm_stack_space (tree fun
)
10376 int reg_parm_stack_space
;
10378 switch (DEFAULT_ABI
)
10381 reg_parm_stack_space
= 0;
10386 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10390 /* ??? Recomputing this every time is a bit expensive. Is there
10391 a place to cache this information? */
10392 if (rs6000_function_parms_need_stack (fun
))
10393 reg_parm_stack_space
= TARGET_64BIT
? 64 : 32;
10395 reg_parm_stack_space
= 0;
10399 return reg_parm_stack_space
;
10403 rs6000_move_block_from_reg (int regno
, rtx x
, int nregs
)
10406 enum machine_mode reg_mode
= TARGET_32BIT
? SImode
: DImode
;
10411 for (i
= 0; i
< nregs
; i
++)
10413 rtx tem
= adjust_address_nv (x
, reg_mode
, i
* GET_MODE_SIZE (reg_mode
));
10414 if (reload_completed
)
10416 if (! strict_memory_address_p (reg_mode
, XEXP (tem
, 0)))
10419 tem
= simplify_gen_subreg (reg_mode
, x
, BLKmode
,
10420 i
* GET_MODE_SIZE (reg_mode
));
10423 tem
= replace_equiv_address (tem
, XEXP (tem
, 0));
10427 emit_move_insn (tem
, gen_rtx_REG (reg_mode
, regno
+ i
));
10431 /* Perform any needed actions needed for a function that is receiving a
10432 variable number of arguments.
10436 MODE and TYPE are the mode and type of the current parameter.
10438 PRETEND_SIZE is a variable that should be set to the amount of stack
10439 that must be pushed by the prolog to pretend that our caller pushed
10442 Normally, this macro will push all remaining incoming registers on the
10443 stack and set PRETEND_SIZE to the length of the registers pushed. */
10446 setup_incoming_varargs (cumulative_args_t cum
, enum machine_mode mode
,
10447 tree type
, int *pretend_size ATTRIBUTE_UNUSED
,
10450 CUMULATIVE_ARGS next_cum
;
10451 int reg_size
= TARGET_32BIT
? 4 : 8;
10452 rtx save_area
= NULL_RTX
, mem
;
10453 int first_reg_offset
;
10454 alias_set_type set
;
10456 /* Skip the last named argument. */
10457 next_cum
= *get_cumulative_args (cum
);
10458 rs6000_function_arg_advance_1 (&next_cum
, mode
, type
, true, 0);
10460 if (DEFAULT_ABI
== ABI_V4
)
10462 first_reg_offset
= next_cum
.sysv_gregno
- GP_ARG_MIN_REG
;
10466 int gpr_reg_num
= 0, gpr_size
= 0, fpr_size
= 0;
10467 HOST_WIDE_INT offset
= 0;
10469 /* Try to optimize the size of the varargs save area.
10470 The ABI requires that ap.reg_save_area is doubleword
10471 aligned, but we don't need to allocate space for all
10472 the bytes, only those to which we actually will save
10474 if (cfun
->va_list_gpr_size
&& first_reg_offset
< GP_ARG_NUM_REG
)
10475 gpr_reg_num
= GP_ARG_NUM_REG
- first_reg_offset
;
10476 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10477 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10478 && cfun
->va_list_fpr_size
)
10481 fpr_size
= (next_cum
.fregno
- FP_ARG_MIN_REG
)
10482 * UNITS_PER_FP_WORD
;
10483 if (cfun
->va_list_fpr_size
10484 < FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10485 fpr_size
+= cfun
->va_list_fpr_size
* UNITS_PER_FP_WORD
;
10487 fpr_size
+= (FP_ARG_V4_MAX_REG
+ 1 - next_cum
.fregno
)
10488 * UNITS_PER_FP_WORD
;
10492 offset
= -((first_reg_offset
* reg_size
) & ~7);
10493 if (!fpr_size
&& gpr_reg_num
> cfun
->va_list_gpr_size
)
10495 gpr_reg_num
= cfun
->va_list_gpr_size
;
10496 if (reg_size
== 4 && (first_reg_offset
& 1))
10499 gpr_size
= (gpr_reg_num
* reg_size
+ 7) & ~7;
10502 offset
= - (int) (next_cum
.fregno
- FP_ARG_MIN_REG
)
10503 * UNITS_PER_FP_WORD
10504 - (int) (GP_ARG_NUM_REG
* reg_size
);
10506 if (gpr_size
+ fpr_size
)
10509 = assign_stack_local (BLKmode
, gpr_size
+ fpr_size
, 64);
10510 gcc_assert (GET_CODE (reg_save_area
) == MEM
);
10511 reg_save_area
= XEXP (reg_save_area
, 0);
10512 if (GET_CODE (reg_save_area
) == PLUS
)
10514 gcc_assert (XEXP (reg_save_area
, 0)
10515 == virtual_stack_vars_rtx
);
10516 gcc_assert (GET_CODE (XEXP (reg_save_area
, 1)) == CONST_INT
);
10517 offset
+= INTVAL (XEXP (reg_save_area
, 1));
10520 gcc_assert (reg_save_area
== virtual_stack_vars_rtx
);
10523 cfun
->machine
->varargs_save_offset
= offset
;
10524 save_area
= plus_constant (Pmode
, virtual_stack_vars_rtx
, offset
);
10529 first_reg_offset
= next_cum
.words
;
10530 save_area
= virtual_incoming_args_rtx
;
10532 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
10533 first_reg_offset
+= rs6000_arg_size (TYPE_MODE (type
), type
);
10536 set
= get_varargs_alias_set ();
10537 if (! no_rtl
&& first_reg_offset
< GP_ARG_NUM_REG
10538 && cfun
->va_list_gpr_size
)
10540 int n_gpr
, nregs
= GP_ARG_NUM_REG
- first_reg_offset
;
10542 if (va_list_gpr_counter_field
)
10543 /* V4 va_list_gpr_size counts number of registers needed. */
10544 n_gpr
= cfun
->va_list_gpr_size
;
10546 /* char * va_list instead counts number of bytes needed. */
10547 n_gpr
= (cfun
->va_list_gpr_size
+ reg_size
- 1) / reg_size
;
10552 mem
= gen_rtx_MEM (BLKmode
,
10553 plus_constant (Pmode
, save_area
,
10554 first_reg_offset
* reg_size
));
10555 MEM_NOTRAP_P (mem
) = 1;
10556 set_mem_alias_set (mem
, set
);
10557 set_mem_align (mem
, BITS_PER_WORD
);
10559 rs6000_move_block_from_reg (GP_ARG_MIN_REG
+ first_reg_offset
, mem
,
10563 /* Save FP registers if needed. */
10564 if (DEFAULT_ABI
== ABI_V4
10565 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10567 && next_cum
.fregno
<= FP_ARG_V4_MAX_REG
10568 && cfun
->va_list_fpr_size
)
10570 int fregno
= next_cum
.fregno
, nregs
;
10571 rtx cr1
= gen_rtx_REG (CCmode
, CR1_REGNO
);
10572 rtx lab
= gen_label_rtx ();
10573 int off
= (GP_ARG_NUM_REG
* reg_size
) + ((fregno
- FP_ARG_MIN_REG
)
10574 * UNITS_PER_FP_WORD
);
10577 (gen_rtx_SET (VOIDmode
,
10579 gen_rtx_IF_THEN_ELSE (VOIDmode
,
10580 gen_rtx_NE (VOIDmode
, cr1
,
10582 gen_rtx_LABEL_REF (VOIDmode
, lab
),
10586 fregno
<= FP_ARG_V4_MAX_REG
&& nregs
< cfun
->va_list_fpr_size
;
10587 fregno
++, off
+= UNITS_PER_FP_WORD
, nregs
++)
10589 mem
= gen_rtx_MEM ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10591 plus_constant (Pmode
, save_area
, off
));
10592 MEM_NOTRAP_P (mem
) = 1;
10593 set_mem_alias_set (mem
, set
);
10594 set_mem_align (mem
, GET_MODE_ALIGNMENT (
10595 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10596 ? DFmode
: SFmode
));
10597 emit_move_insn (mem
, gen_rtx_REG (
10598 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
)
10599 ? DFmode
: SFmode
, fregno
));
10606 /* Create the va_list data type. */
10609 rs6000_build_builtin_va_list (void)
10611 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
, record
, type_decl
;
10613 /* For AIX, prefer 'char *' because that's what the system
10614 header files like. */
10615 if (DEFAULT_ABI
!= ABI_V4
)
10616 return build_pointer_type (char_type_node
);
10618 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
10619 type_decl
= build_decl (BUILTINS_LOCATION
, TYPE_DECL
,
10620 get_identifier ("__va_list_tag"), record
);
10622 f_gpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("gpr"),
10623 unsigned_char_type_node
);
10624 f_fpr
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
, get_identifier ("fpr"),
10625 unsigned_char_type_node
);
10626 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
10627 every user file. */
10628 f_res
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10629 get_identifier ("reserved"), short_unsigned_type_node
);
10630 f_ovf
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10631 get_identifier ("overflow_arg_area"),
10633 f_sav
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
10634 get_identifier ("reg_save_area"),
10637 va_list_gpr_counter_field
= f_gpr
;
10638 va_list_fpr_counter_field
= f_fpr
;
10640 DECL_FIELD_CONTEXT (f_gpr
) = record
;
10641 DECL_FIELD_CONTEXT (f_fpr
) = record
;
10642 DECL_FIELD_CONTEXT (f_res
) = record
;
10643 DECL_FIELD_CONTEXT (f_ovf
) = record
;
10644 DECL_FIELD_CONTEXT (f_sav
) = record
;
10646 TYPE_STUB_DECL (record
) = type_decl
;
10647 TYPE_NAME (record
) = type_decl
;
10648 TYPE_FIELDS (record
) = f_gpr
;
10649 DECL_CHAIN (f_gpr
) = f_fpr
;
10650 DECL_CHAIN (f_fpr
) = f_res
;
10651 DECL_CHAIN (f_res
) = f_ovf
;
10652 DECL_CHAIN (f_ovf
) = f_sav
;
10654 layout_type (record
);
10656 /* The correct type is an array type of one element. */
10657 return build_array_type (record
, build_index_type (size_zero_node
));
10660 /* Implement va_start. */
10663 rs6000_va_start (tree valist
, rtx nextarg
)
10665 HOST_WIDE_INT words
, n_gpr
, n_fpr
;
10666 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10667 tree gpr
, fpr
, ovf
, sav
, t
;
10669 /* Only SVR4 needs something special. */
10670 if (DEFAULT_ABI
!= ABI_V4
)
10672 std_expand_builtin_va_start (valist
, nextarg
);
10676 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10677 f_fpr
= DECL_CHAIN (f_gpr
);
10678 f_res
= DECL_CHAIN (f_fpr
);
10679 f_ovf
= DECL_CHAIN (f_res
);
10680 f_sav
= DECL_CHAIN (f_ovf
);
10682 valist
= build_simple_mem_ref (valist
);
10683 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10684 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10686 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10688 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10691 /* Count number of gp and fp argument registers used. */
10692 words
= crtl
->args
.info
.words
;
10693 n_gpr
= MIN (crtl
->args
.info
.sysv_gregno
- GP_ARG_MIN_REG
,
10695 n_fpr
= MIN (crtl
->args
.info
.fregno
- FP_ARG_MIN_REG
,
10698 if (TARGET_DEBUG_ARG
)
10699 fprintf (stderr
, "va_start: words = "HOST_WIDE_INT_PRINT_DEC
", n_gpr = "
10700 HOST_WIDE_INT_PRINT_DEC
", n_fpr = "HOST_WIDE_INT_PRINT_DEC
"\n",
10701 words
, n_gpr
, n_fpr
);
10703 if (cfun
->va_list_gpr_size
)
10705 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gpr
), gpr
,
10706 build_int_cst (NULL_TREE
, n_gpr
));
10707 TREE_SIDE_EFFECTS (t
) = 1;
10708 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10711 if (cfun
->va_list_fpr_size
)
10713 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fpr
), fpr
,
10714 build_int_cst (NULL_TREE
, n_fpr
));
10715 TREE_SIDE_EFFECTS (t
) = 1;
10716 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10718 #ifdef HAVE_AS_GNU_ATTRIBUTE
10719 if (call_ABI_of_interest (cfun
->decl
))
10720 rs6000_passes_float
= true;
10724 /* Find the overflow area. */
10725 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
10727 t
= fold_build_pointer_plus_hwi (t
, words
* UNITS_PER_WORD
);
10728 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovf
), ovf
, t
);
10729 TREE_SIDE_EFFECTS (t
) = 1;
10730 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10732 /* If there were no va_arg invocations, don't set up the register
10734 if (!cfun
->va_list_gpr_size
10735 && !cfun
->va_list_fpr_size
10736 && n_gpr
< GP_ARG_NUM_REG
10737 && n_fpr
< FP_ARG_V4_MAX_REG
)
10740 /* Find the register save area. */
10741 t
= make_tree (TREE_TYPE (sav
), virtual_stack_vars_rtx
);
10742 if (cfun
->machine
->varargs_save_offset
)
10743 t
= fold_build_pointer_plus_hwi (t
, cfun
->machine
->varargs_save_offset
);
10744 t
= build2 (MODIFY_EXPR
, TREE_TYPE (sav
), sav
, t
);
10745 TREE_SIDE_EFFECTS (t
) = 1;
10746 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
10749 /* Implement va_arg. */
10752 rs6000_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
10753 gimple_seq
*post_p
)
10755 tree f_gpr
, f_fpr
, f_res
, f_ovf
, f_sav
;
10756 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
10757 int size
, rsize
, n_reg
, sav_ofs
, sav_scale
;
10758 tree lab_false
, lab_over
, addr
;
10760 tree ptrtype
= build_pointer_type_for_mode (type
, ptr_mode
, true);
10764 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
10766 t
= rs6000_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
10767 return build_va_arg_indirect_ref (t
);
10770 /* We need to deal with the fact that the darwin ppc64 ABI is defined by an
10771 earlier version of gcc, with the property that it always applied alignment
10772 adjustments to the va-args (even for zero-sized types). The cheapest way
10773 to deal with this is to replicate the effect of the part of
10774 std_gimplify_va_arg_expr that carries out the align adjust, for the case
10776 We don't need to check for pass-by-reference because of the test above.
10777 We can return a simplifed answer, since we know there's no offset to add. */
10780 && rs6000_darwin64_abi
)
10781 || DEFAULT_ABI
== ABI_ELFv2
10782 || (DEFAULT_ABI
== ABI_AIX
&& !rs6000_compat_align_parm
))
10783 && integer_zerop (TYPE_SIZE (type
)))
10785 unsigned HOST_WIDE_INT align
, boundary
;
10786 tree valist_tmp
= get_initialized_tmp_var (valist
, pre_p
, NULL
);
10787 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
10788 boundary
= rs6000_function_arg_boundary (TYPE_MODE (type
), type
);
10789 if (boundary
> MAX_SUPPORTED_STACK_ALIGNMENT
)
10790 boundary
= MAX_SUPPORTED_STACK_ALIGNMENT
;
10791 boundary
/= BITS_PER_UNIT
;
10792 if (boundary
> align
)
10795 /* This updates arg ptr by the amount that would be necessary
10796 to align the zero-sized (but not zero-alignment) item. */
10797 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10798 fold_build_pointer_plus_hwi (valist_tmp
, boundary
- 1));
10799 gimplify_and_add (t
, pre_p
);
10801 t
= fold_convert (sizetype
, valist_tmp
);
10802 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist_tmp
,
10803 fold_convert (TREE_TYPE (valist
),
10804 fold_build2 (BIT_AND_EXPR
, sizetype
, t
,
10805 size_int (-boundary
))));
10806 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
, t
);
10807 gimplify_and_add (t
, pre_p
);
10809 /* Since it is zero-sized there's no increment for the item itself. */
10810 valist_tmp
= fold_convert (build_pointer_type (type
), valist_tmp
);
10811 return build_va_arg_indirect_ref (valist_tmp
);
10814 if (DEFAULT_ABI
!= ABI_V4
)
10816 if (targetm
.calls
.split_complex_arg
&& TREE_CODE (type
) == COMPLEX_TYPE
)
10818 tree elem_type
= TREE_TYPE (type
);
10819 enum machine_mode elem_mode
= TYPE_MODE (elem_type
);
10820 int elem_size
= GET_MODE_SIZE (elem_mode
);
10822 if (elem_size
< UNITS_PER_WORD
)
10824 tree real_part
, imag_part
;
10825 gimple_seq post
= NULL
;
10827 real_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10829 /* Copy the value into a temporary, lest the formal temporary
10830 be reused out from under us. */
10831 real_part
= get_initialized_tmp_var (real_part
, pre_p
, &post
);
10832 gimple_seq_add_seq (pre_p
, post
);
10834 imag_part
= rs6000_gimplify_va_arg (valist
, elem_type
, pre_p
,
10837 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
10841 return std_gimplify_va_arg_expr (valist
, type
, pre_p
, post_p
);
10844 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
10845 f_fpr
= DECL_CHAIN (f_gpr
);
10846 f_res
= DECL_CHAIN (f_fpr
);
10847 f_ovf
= DECL_CHAIN (f_res
);
10848 f_sav
= DECL_CHAIN (f_ovf
);
10850 valist
= build_va_arg_indirect_ref (valist
);
10851 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
10852 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), unshare_expr (valist
),
10854 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), unshare_expr (valist
),
10856 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), unshare_expr (valist
),
10859 size
= int_size_in_bytes (type
);
10860 rsize
= (size
+ 3) / 4;
10863 if (TARGET_HARD_FLOAT
&& TARGET_FPRS
10864 && ((TARGET_SINGLE_FLOAT
&& TYPE_MODE (type
) == SFmode
)
10865 || (TARGET_DOUBLE_FLOAT
10866 && (TYPE_MODE (type
) == DFmode
10867 || TYPE_MODE (type
) == TFmode
10868 || TYPE_MODE (type
) == SDmode
10869 || TYPE_MODE (type
) == DDmode
10870 || TYPE_MODE (type
) == TDmode
))))
10872 /* FP args go in FP registers, if present. */
10874 n_reg
= (size
+ 7) / 8;
10875 sav_ofs
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4) * 4;
10876 sav_scale
= ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? 8 : 4);
10877 if (TYPE_MODE (type
) != SFmode
&& TYPE_MODE (type
) != SDmode
)
10882 /* Otherwise into GP registers. */
10891 /* Pull the value out of the saved registers.... */
10894 addr
= create_tmp_var (ptr_type_node
, "addr");
10896 /* AltiVec vectors never go in registers when -mabi=altivec. */
10897 if (TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (TYPE_MODE (type
)))
10901 lab_false
= create_artificial_label (input_location
);
10902 lab_over
= create_artificial_label (input_location
);
10904 /* Long long and SPE vectors are aligned in the registers.
10905 As are any other 2 gpr item such as complex int due to a
10906 historical mistake. */
10908 if (n_reg
== 2 && reg
== gpr
)
10911 u
= build2 (BIT_AND_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10912 build_int_cst (TREE_TYPE (reg
), n_reg
- 1));
10913 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
),
10914 unshare_expr (reg
), u
);
10916 /* _Decimal128 is passed in even/odd fpr pairs; the stored
10917 reg number is 0 for f1, so we want to make it odd. */
10918 else if (reg
== fpr
&& TYPE_MODE (type
) == TDmode
)
10920 t
= build2 (BIT_IOR_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10921 build_int_cst (TREE_TYPE (reg
), 1));
10922 u
= build2 (MODIFY_EXPR
, void_type_node
, unshare_expr (reg
), t
);
10925 t
= fold_convert (TREE_TYPE (reg
), size_int (8 - n_reg
+ 1));
10926 t
= build2 (GE_EXPR
, boolean_type_node
, u
, t
);
10927 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
10928 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
10929 gimplify_and_add (t
, pre_p
);
10933 t
= fold_build_pointer_plus_hwi (sav
, sav_ofs
);
10935 u
= build2 (POSTINCREMENT_EXPR
, TREE_TYPE (reg
), unshare_expr (reg
),
10936 build_int_cst (TREE_TYPE (reg
), n_reg
));
10937 u
= fold_convert (sizetype
, u
);
10938 u
= build2 (MULT_EXPR
, sizetype
, u
, size_int (sav_scale
));
10939 t
= fold_build_pointer_plus (t
, u
);
10941 /* _Decimal32 varargs are located in the second word of the 64-bit
10942 FP register for 32-bit binaries. */
10943 if (!TARGET_POWERPC64
10944 && TARGET_HARD_FLOAT
&& TARGET_FPRS
10945 && TYPE_MODE (type
) == SDmode
)
10946 t
= fold_build_pointer_plus_hwi (t
, size
);
10948 gimplify_assign (addr
, t
, pre_p
);
10950 gimple_seq_add_stmt (pre_p
, gimple_build_goto (lab_over
));
10952 stmt
= gimple_build_label (lab_false
);
10953 gimple_seq_add_stmt (pre_p
, stmt
);
10955 if ((n_reg
== 2 && !regalign
) || n_reg
> 2)
10957 /* Ensure that we don't find any more args in regs.
10958 Alignment has taken care of for special cases. */
10959 gimplify_assign (reg
, build_int_cst (TREE_TYPE (reg
), 8), pre_p
);
10963 /* ... otherwise out of the overflow area. */
10965 /* Care for on-stack alignment if needed. */
10969 t
= fold_build_pointer_plus_hwi (t
, align
- 1);
10970 t
= build2 (BIT_AND_EXPR
, TREE_TYPE (t
), t
,
10971 build_int_cst (TREE_TYPE (t
), -align
));
10973 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
10975 gimplify_assign (unshare_expr (addr
), t
, pre_p
);
10977 t
= fold_build_pointer_plus_hwi (t
, size
);
10978 gimplify_assign (unshare_expr (ovf
), t
, pre_p
);
10982 stmt
= gimple_build_label (lab_over
);
10983 gimple_seq_add_stmt (pre_p
, stmt
);
10986 if (STRICT_ALIGNMENT
10987 && (TYPE_ALIGN (type
)
10988 > (unsigned) BITS_PER_UNIT
* (align
< 4 ? 4 : align
)))
10990 /* The value (of type complex double, for example) may not be
10991 aligned in memory in the saved registers, so copy via a
10992 temporary. (This is the same code as used for SPARC.) */
10993 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
10994 tree dest_addr
= build_fold_addr_expr (tmp
);
10996 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
10997 3, dest_addr
, addr
, size_int (rsize
* 4));
10999 gimplify_and_add (copy
, pre_p
);
11003 addr
= fold_convert (ptrtype
, addr
);
11004 return build_va_arg_indirect_ref (addr
);
11010 def_builtin (const char *name
, tree type
, enum rs6000_builtins code
)
11013 unsigned classify
= rs6000_builtin_info
[(int)code
].attr
;
11014 const char *attr_string
= "";
11016 gcc_assert (name
!= NULL
);
11017 gcc_assert (IN_RANGE ((int)code
, 0, (int)RS6000_BUILTIN_COUNT
));
11019 if (rs6000_builtin_decls
[(int)code
])
11020 fatal_error ("internal error: builtin function %s already processed", name
);
11022 rs6000_builtin_decls
[(int)code
] = t
=
11023 add_builtin_function (name
, type
, (int)code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
11025 /* Set any special attributes. */
11026 if ((classify
& RS6000_BTC_CONST
) != 0)
11028 /* const function, function only depends on the inputs. */
11029 TREE_READONLY (t
) = 1;
11030 TREE_NOTHROW (t
) = 1;
11031 attr_string
= ", pure";
11033 else if ((classify
& RS6000_BTC_PURE
) != 0)
11035 /* pure function, function can read global memory, but does not set any
11037 DECL_PURE_P (t
) = 1;
11038 TREE_NOTHROW (t
) = 1;
11039 attr_string
= ", const";
11041 else if ((classify
& RS6000_BTC_FP
) != 0)
11043 /* Function is a math function. If rounding mode is on, then treat the
11044 function as not reading global memory, but it can have arbitrary side
11045 effects. If it is off, then assume the function is a const function.
11046 This mimics the ATTR_MATHFN_FPROUNDING attribute in
11047 builtin-attribute.def that is used for the math functions. */
11048 TREE_NOTHROW (t
) = 1;
11049 if (flag_rounding_math
)
11051 DECL_PURE_P (t
) = 1;
11052 DECL_IS_NOVOPS (t
) = 1;
11053 attr_string
= ", fp, pure";
11057 TREE_READONLY (t
) = 1;
11058 attr_string
= ", fp, const";
11061 else if ((classify
& RS6000_BTC_ATTR_MASK
) != 0)
11062 gcc_unreachable ();
11064 if (TARGET_DEBUG_BUILTIN
)
11065 fprintf (stderr
, "rs6000_builtin, code = %4d, %s%s\n",
11066 (int)code
, name
, attr_string
);
11069 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
11071 #undef RS6000_BUILTIN_1
11072 #undef RS6000_BUILTIN_2
11073 #undef RS6000_BUILTIN_3
11074 #undef RS6000_BUILTIN_A
11075 #undef RS6000_BUILTIN_D
11076 #undef RS6000_BUILTIN_E
11077 #undef RS6000_BUILTIN_H
11078 #undef RS6000_BUILTIN_P
11079 #undef RS6000_BUILTIN_Q
11080 #undef RS6000_BUILTIN_S
11081 #undef RS6000_BUILTIN_X
11083 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11084 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11085 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE) \
11086 { MASK, ICODE, NAME, ENUM },
11088 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11089 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11090 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11091 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11092 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11093 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11094 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11095 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11097 static const struct builtin_description bdesc_3arg
[] =
11099 #include "rs6000-builtin.def"
11102 /* DST operations: void foo (void *, const int, const char). */
11104 #undef RS6000_BUILTIN_1
11105 #undef RS6000_BUILTIN_2
11106 #undef RS6000_BUILTIN_3
11107 #undef RS6000_BUILTIN_A
11108 #undef RS6000_BUILTIN_D
11109 #undef RS6000_BUILTIN_E
11110 #undef RS6000_BUILTIN_H
11111 #undef RS6000_BUILTIN_P
11112 #undef RS6000_BUILTIN_Q
11113 #undef RS6000_BUILTIN_S
11114 #undef RS6000_BUILTIN_X
11116 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11117 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11118 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11119 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11120 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) \
11121 { MASK, ICODE, NAME, ENUM },
11123 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11124 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11125 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11126 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11127 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11128 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11130 static const struct builtin_description bdesc_dst
[] =
11132 #include "rs6000-builtin.def"
11135 /* Simple binary operations: VECc = foo (VECa, VECb). */
11137 #undef RS6000_BUILTIN_1
11138 #undef RS6000_BUILTIN_2
11139 #undef RS6000_BUILTIN_3
11140 #undef RS6000_BUILTIN_A
11141 #undef RS6000_BUILTIN_D
11142 #undef RS6000_BUILTIN_E
11143 #undef RS6000_BUILTIN_H
11144 #undef RS6000_BUILTIN_P
11145 #undef RS6000_BUILTIN_Q
11146 #undef RS6000_BUILTIN_S
11147 #undef RS6000_BUILTIN_X
11149 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11150 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE) \
11151 { MASK, ICODE, NAME, ENUM },
11153 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11154 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11155 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11156 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11157 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11158 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11159 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11160 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11161 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11163 static const struct builtin_description bdesc_2arg
[] =
11165 #include "rs6000-builtin.def"
11168 #undef RS6000_BUILTIN_1
11169 #undef RS6000_BUILTIN_2
11170 #undef RS6000_BUILTIN_3
11171 #undef RS6000_BUILTIN_A
11172 #undef RS6000_BUILTIN_D
11173 #undef RS6000_BUILTIN_E
11174 #undef RS6000_BUILTIN_H
11175 #undef RS6000_BUILTIN_P
11176 #undef RS6000_BUILTIN_Q
11177 #undef RS6000_BUILTIN_S
11178 #undef RS6000_BUILTIN_X
11180 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11181 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11182 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11183 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11184 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11185 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11186 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11187 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) \
11188 { MASK, ICODE, NAME, ENUM },
11190 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11191 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11192 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11194 /* AltiVec predicates. */
11196 static const struct builtin_description bdesc_altivec_preds
[] =
11198 #include "rs6000-builtin.def"
11201 /* SPE predicates. */
11202 #undef RS6000_BUILTIN_1
11203 #undef RS6000_BUILTIN_2
11204 #undef RS6000_BUILTIN_3
11205 #undef RS6000_BUILTIN_A
11206 #undef RS6000_BUILTIN_D
11207 #undef RS6000_BUILTIN_E
11208 #undef RS6000_BUILTIN_H
11209 #undef RS6000_BUILTIN_P
11210 #undef RS6000_BUILTIN_Q
11211 #undef RS6000_BUILTIN_S
11212 #undef RS6000_BUILTIN_X
11214 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11215 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11216 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11217 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11218 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11219 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11220 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11221 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11222 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11223 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) \
11224 { MASK, ICODE, NAME, ENUM },
11226 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11228 static const struct builtin_description bdesc_spe_predicates
[] =
11230 #include "rs6000-builtin.def"
11233 /* SPE evsel predicates. */
11234 #undef RS6000_BUILTIN_1
11235 #undef RS6000_BUILTIN_2
11236 #undef RS6000_BUILTIN_3
11237 #undef RS6000_BUILTIN_A
11238 #undef RS6000_BUILTIN_D
11239 #undef RS6000_BUILTIN_E
11240 #undef RS6000_BUILTIN_H
11241 #undef RS6000_BUILTIN_P
11242 #undef RS6000_BUILTIN_Q
11243 #undef RS6000_BUILTIN_S
11244 #undef RS6000_BUILTIN_X
11246 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11247 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11248 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11249 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11250 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11251 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) \
11252 { MASK, ICODE, NAME, ENUM },
11254 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11255 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11256 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11257 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11258 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11260 static const struct builtin_description bdesc_spe_evsel
[] =
11262 #include "rs6000-builtin.def"
11265 /* PAIRED predicates. */
11266 #undef RS6000_BUILTIN_1
11267 #undef RS6000_BUILTIN_2
11268 #undef RS6000_BUILTIN_3
11269 #undef RS6000_BUILTIN_A
11270 #undef RS6000_BUILTIN_D
11271 #undef RS6000_BUILTIN_E
11272 #undef RS6000_BUILTIN_H
11273 #undef RS6000_BUILTIN_P
11274 #undef RS6000_BUILTIN_Q
11275 #undef RS6000_BUILTIN_S
11276 #undef RS6000_BUILTIN_X
11278 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11279 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11280 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11281 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11282 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11283 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11284 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11285 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11286 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) \
11287 { MASK, ICODE, NAME, ENUM },
11289 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11290 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11292 static const struct builtin_description bdesc_paired_preds
[] =
11294 #include "rs6000-builtin.def"
11297 /* ABS* operations. */
11299 #undef RS6000_BUILTIN_1
11300 #undef RS6000_BUILTIN_2
11301 #undef RS6000_BUILTIN_3
11302 #undef RS6000_BUILTIN_A
11303 #undef RS6000_BUILTIN_D
11304 #undef RS6000_BUILTIN_E
11305 #undef RS6000_BUILTIN_H
11306 #undef RS6000_BUILTIN_P
11307 #undef RS6000_BUILTIN_Q
11308 #undef RS6000_BUILTIN_S
11309 #undef RS6000_BUILTIN_X
11311 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11312 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11313 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11314 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) \
11315 { MASK, ICODE, NAME, ENUM },
11317 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11318 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11319 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11320 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11321 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11322 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11323 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11325 static const struct builtin_description bdesc_abs
[] =
11327 #include "rs6000-builtin.def"
11330 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
11333 #undef RS6000_BUILTIN_1
11334 #undef RS6000_BUILTIN_2
11335 #undef RS6000_BUILTIN_3
11336 #undef RS6000_BUILTIN_A
11337 #undef RS6000_BUILTIN_D
11338 #undef RS6000_BUILTIN_E
11339 #undef RS6000_BUILTIN_H
11340 #undef RS6000_BUILTIN_P
11341 #undef RS6000_BUILTIN_Q
11342 #undef RS6000_BUILTIN_S
11343 #undef RS6000_BUILTIN_X
11345 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE) \
11346 { MASK, ICODE, NAME, ENUM },
11348 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11349 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11350 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11351 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11352 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11353 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE)
11354 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11355 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11356 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11357 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11359 static const struct builtin_description bdesc_1arg
[] =
11361 #include "rs6000-builtin.def"
11364 /* HTM builtins. */
11365 #undef RS6000_BUILTIN_1
11366 #undef RS6000_BUILTIN_2
11367 #undef RS6000_BUILTIN_3
11368 #undef RS6000_BUILTIN_A
11369 #undef RS6000_BUILTIN_D
11370 #undef RS6000_BUILTIN_E
11371 #undef RS6000_BUILTIN_H
11372 #undef RS6000_BUILTIN_P
11373 #undef RS6000_BUILTIN_Q
11374 #undef RS6000_BUILTIN_S
11375 #undef RS6000_BUILTIN_X
11377 #define RS6000_BUILTIN_1(ENUM, NAME, MASK, ATTR, ICODE)
11378 #define RS6000_BUILTIN_2(ENUM, NAME, MASK, ATTR, ICODE)
11379 #define RS6000_BUILTIN_3(ENUM, NAME, MASK, ATTR, ICODE)
11380 #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE)
11381 #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE)
11382 #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE)
11383 #define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) \
11384 { MASK, ICODE, NAME, ENUM },
11386 #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE)
11387 #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE)
11388 #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE)
11389 #define RS6000_BUILTIN_X(ENUM, NAME, MASK, ATTR, ICODE)
11391 static const struct builtin_description bdesc_htm
[] =
11393 #include "rs6000-builtin.def"
11396 #undef RS6000_BUILTIN_1
11397 #undef RS6000_BUILTIN_2
11398 #undef RS6000_BUILTIN_3
11399 #undef RS6000_BUILTIN_A
11400 #undef RS6000_BUILTIN_D
11401 #undef RS6000_BUILTIN_E
11402 #undef RS6000_BUILTIN_H
11403 #undef RS6000_BUILTIN_P
11404 #undef RS6000_BUILTIN_Q
11405 #undef RS6000_BUILTIN_S
11407 /* Return true if a builtin function is overloaded. */
11409 rs6000_overloaded_builtin_p (enum rs6000_builtins fncode
)
11411 return (rs6000_builtin_info
[(int)fncode
].attr
& RS6000_BTC_OVERLOADED
) != 0;
11414 /* Expand an expression EXP that calls a builtin without arguments. */
11416 rs6000_expand_zeroop_builtin (enum insn_code icode
, rtx target
)
11419 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11421 if (icode
== CODE_FOR_nothing
)
11422 /* Builtin not supported on this processor. */
11426 || GET_MODE (target
) != tmode
11427 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11428 target
= gen_reg_rtx (tmode
);
11430 pat
= GEN_FCN (icode
) (target
);
11440 rs6000_expand_unop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11443 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11444 rtx op0
= expand_normal (arg0
);
11445 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11446 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11448 if (icode
== CODE_FOR_nothing
)
11449 /* Builtin not supported on this processor. */
11452 /* If we got invalid arguments bail out before generating bad rtl. */
11453 if (arg0
== error_mark_node
)
11456 if (icode
== CODE_FOR_altivec_vspltisb
11457 || icode
== CODE_FOR_altivec_vspltish
11458 || icode
== CODE_FOR_altivec_vspltisw
11459 || icode
== CODE_FOR_spe_evsplatfi
11460 || icode
== CODE_FOR_spe_evsplati
)
11462 /* Only allow 5-bit *signed* literals. */
11463 if (GET_CODE (op0
) != CONST_INT
11464 || INTVAL (op0
) > 15
11465 || INTVAL (op0
) < -16)
11467 error ("argument 1 must be a 5-bit signed literal");
11473 || GET_MODE (target
) != tmode
11474 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11475 target
= gen_reg_rtx (tmode
);
11477 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11478 op0
= copy_to_mode_reg (mode0
, op0
);
11480 pat
= GEN_FCN (icode
) (target
, op0
);
11489 altivec_expand_abs_builtin (enum insn_code icode
, tree exp
, rtx target
)
11491 rtx pat
, scratch1
, scratch2
;
11492 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11493 rtx op0
= expand_normal (arg0
);
11494 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11495 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11497 /* If we have invalid arguments, bail out before generating bad rtl. */
11498 if (arg0
== error_mark_node
)
11502 || GET_MODE (target
) != tmode
11503 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11504 target
= gen_reg_rtx (tmode
);
11506 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11507 op0
= copy_to_mode_reg (mode0
, op0
);
11509 scratch1
= gen_reg_rtx (mode0
);
11510 scratch2
= gen_reg_rtx (mode0
);
11512 pat
= GEN_FCN (icode
) (target
, op0
, scratch1
, scratch2
);
11521 rs6000_expand_binop_builtin (enum insn_code icode
, tree exp
, rtx target
)
11524 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11525 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11526 rtx op0
= expand_normal (arg0
);
11527 rtx op1
= expand_normal (arg1
);
11528 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11529 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11530 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11532 if (icode
== CODE_FOR_nothing
)
11533 /* Builtin not supported on this processor. */
11536 /* If we got invalid arguments bail out before generating bad rtl. */
11537 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11540 if (icode
== CODE_FOR_altivec_vcfux
11541 || icode
== CODE_FOR_altivec_vcfsx
11542 || icode
== CODE_FOR_altivec_vctsxs
11543 || icode
== CODE_FOR_altivec_vctuxs
11544 || icode
== CODE_FOR_altivec_vspltb
11545 || icode
== CODE_FOR_altivec_vsplth
11546 || icode
== CODE_FOR_altivec_vspltw
11547 || icode
== CODE_FOR_spe_evaddiw
11548 || icode
== CODE_FOR_spe_evldd
11549 || icode
== CODE_FOR_spe_evldh
11550 || icode
== CODE_FOR_spe_evldw
11551 || icode
== CODE_FOR_spe_evlhhesplat
11552 || icode
== CODE_FOR_spe_evlhhossplat
11553 || icode
== CODE_FOR_spe_evlhhousplat
11554 || icode
== CODE_FOR_spe_evlwhe
11555 || icode
== CODE_FOR_spe_evlwhos
11556 || icode
== CODE_FOR_spe_evlwhou
11557 || icode
== CODE_FOR_spe_evlwhsplat
11558 || icode
== CODE_FOR_spe_evlwwsplat
11559 || icode
== CODE_FOR_spe_evrlwi
11560 || icode
== CODE_FOR_spe_evslwi
11561 || icode
== CODE_FOR_spe_evsrwis
11562 || icode
== CODE_FOR_spe_evsubifw
11563 || icode
== CODE_FOR_spe_evsrwiu
)
11565 /* Only allow 5-bit unsigned literals. */
11567 if (TREE_CODE (arg1
) != INTEGER_CST
11568 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
11570 error ("argument 2 must be a 5-bit unsigned literal");
11576 || GET_MODE (target
) != tmode
11577 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11578 target
= gen_reg_rtx (tmode
);
11580 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11581 op0
= copy_to_mode_reg (mode0
, op0
);
11582 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11583 op1
= copy_to_mode_reg (mode1
, op1
);
11585 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
11594 altivec_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
11597 tree cr6_form
= CALL_EXPR_ARG (exp
, 0);
11598 tree arg0
= CALL_EXPR_ARG (exp
, 1);
11599 tree arg1
= CALL_EXPR_ARG (exp
, 2);
11600 rtx op0
= expand_normal (arg0
);
11601 rtx op1
= expand_normal (arg1
);
11602 enum machine_mode tmode
= SImode
;
11603 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
11604 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
11607 if (TREE_CODE (cr6_form
) != INTEGER_CST
)
11609 error ("argument 1 of __builtin_altivec_predicate must be a constant");
11613 cr6_form_int
= TREE_INT_CST_LOW (cr6_form
);
11615 gcc_assert (mode0
== mode1
);
11617 /* If we have invalid arguments, bail out before generating bad rtl. */
11618 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11622 || GET_MODE (target
) != tmode
11623 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11624 target
= gen_reg_rtx (tmode
);
11626 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
11627 op0
= copy_to_mode_reg (mode0
, op0
);
11628 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
11629 op1
= copy_to_mode_reg (mode1
, op1
);
11631 scratch
= gen_reg_rtx (mode0
);
11633 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
11638 /* The vec_any* and vec_all* predicates use the same opcodes for two
11639 different operations, but the bits in CR6 will be different
11640 depending on what information we want. So we have to play tricks
11641 with CR6 to get the right bits out.
11643 If you think this is disgusting, look at the specs for the
11644 AltiVec predicates. */
11646 switch (cr6_form_int
)
11649 emit_insn (gen_cr6_test_for_zero (target
));
11652 emit_insn (gen_cr6_test_for_zero_reverse (target
));
11655 emit_insn (gen_cr6_test_for_lt (target
));
11658 emit_insn (gen_cr6_test_for_lt_reverse (target
));
11661 error ("argument 1 of __builtin_altivec_predicate is out of range");
11669 paired_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
)
11672 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11673 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11674 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11675 enum machine_mode mode0
= Pmode
;
11676 enum machine_mode mode1
= Pmode
;
11677 rtx op0
= expand_normal (arg0
);
11678 rtx op1
= expand_normal (arg1
);
11680 if (icode
== CODE_FOR_nothing
)
11681 /* Builtin not supported on this processor. */
11684 /* If we got invalid arguments bail out before generating bad rtl. */
11685 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11689 || GET_MODE (target
) != tmode
11690 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11691 target
= gen_reg_rtx (tmode
);
11693 op1
= copy_to_mode_reg (mode1
, op1
);
11695 if (op0
== const0_rtx
)
11697 addr
= gen_rtx_MEM (tmode
, op1
);
11701 op0
= copy_to_mode_reg (mode0
, op0
);
11702 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11705 pat
= GEN_FCN (icode
) (target
, addr
);
11715 altivec_expand_lv_builtin (enum insn_code icode
, tree exp
, rtx target
, bool blk
)
11718 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11719 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11720 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11721 enum machine_mode mode0
= Pmode
;
11722 enum machine_mode mode1
= Pmode
;
11723 rtx op0
= expand_normal (arg0
);
11724 rtx op1
= expand_normal (arg1
);
11726 if (icode
== CODE_FOR_nothing
)
11727 /* Builtin not supported on this processor. */
11730 /* If we got invalid arguments bail out before generating bad rtl. */
11731 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
11735 || GET_MODE (target
) != tmode
11736 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11737 target
= gen_reg_rtx (tmode
);
11739 op1
= copy_to_mode_reg (mode1
, op1
);
11741 if (op0
== const0_rtx
)
11743 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, op1
);
11747 op0
= copy_to_mode_reg (mode0
, op0
);
11748 addr
= gen_rtx_MEM (blk
? BLKmode
: tmode
, gen_rtx_PLUS (Pmode
, op0
, op1
));
11751 pat
= GEN_FCN (icode
) (target
, addr
);
11761 spe_expand_stv_builtin (enum insn_code icode
, tree exp
)
11763 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11764 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11765 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11766 rtx op0
= expand_normal (arg0
);
11767 rtx op1
= expand_normal (arg1
);
11768 rtx op2
= expand_normal (arg2
);
11770 enum machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
11771 enum machine_mode mode1
= insn_data
[icode
].operand
[1].mode
;
11772 enum machine_mode mode2
= insn_data
[icode
].operand
[2].mode
;
11774 /* Invalid arguments. Bail before doing anything stoopid! */
11775 if (arg0
== error_mark_node
11776 || arg1
== error_mark_node
11777 || arg2
== error_mark_node
)
11780 if (! (*insn_data
[icode
].operand
[2].predicate
) (op0
, mode2
))
11781 op0
= copy_to_mode_reg (mode2
, op0
);
11782 if (! (*insn_data
[icode
].operand
[0].predicate
) (op1
, mode0
))
11783 op1
= copy_to_mode_reg (mode0
, op1
);
11784 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
11785 op2
= copy_to_mode_reg (mode1
, op2
);
11787 pat
= GEN_FCN (icode
) (op1
, op2
, op0
);
11794 paired_expand_stv_builtin (enum insn_code icode
, tree exp
)
11796 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11797 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11798 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11799 rtx op0
= expand_normal (arg0
);
11800 rtx op1
= expand_normal (arg1
);
11801 rtx op2
= expand_normal (arg2
);
11803 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11804 enum machine_mode mode1
= Pmode
;
11805 enum machine_mode mode2
= Pmode
;
11807 /* Invalid arguments. Bail before doing anything stoopid! */
11808 if (arg0
== error_mark_node
11809 || arg1
== error_mark_node
11810 || arg2
== error_mark_node
)
11813 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, tmode
))
11814 op0
= copy_to_mode_reg (tmode
, op0
);
11816 op2
= copy_to_mode_reg (mode2
, op2
);
11818 if (op1
== const0_rtx
)
11820 addr
= gen_rtx_MEM (tmode
, op2
);
11824 op1
= copy_to_mode_reg (mode1
, op1
);
11825 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
11828 pat
= GEN_FCN (icode
) (addr
, op0
);
11835 altivec_expand_stv_builtin (enum insn_code icode
, tree exp
)
11837 tree arg0
= CALL_EXPR_ARG (exp
, 0);
11838 tree arg1
= CALL_EXPR_ARG (exp
, 1);
11839 tree arg2
= CALL_EXPR_ARG (exp
, 2);
11840 rtx op0
= expand_normal (arg0
);
11841 rtx op1
= expand_normal (arg1
);
11842 rtx op2
= expand_normal (arg2
);
11844 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11845 enum machine_mode smode
= insn_data
[icode
].operand
[1].mode
;
11846 enum machine_mode mode1
= Pmode
;
11847 enum machine_mode mode2
= Pmode
;
11849 /* Invalid arguments. Bail before doing anything stoopid! */
11850 if (arg0
== error_mark_node
11851 || arg1
== error_mark_node
11852 || arg2
== error_mark_node
)
11855 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, smode
))
11856 op0
= copy_to_mode_reg (smode
, op0
);
11858 op2
= copy_to_mode_reg (mode2
, op2
);
11860 if (op1
== const0_rtx
)
11862 addr
= gen_rtx_MEM (tmode
, op2
);
11866 op1
= copy_to_mode_reg (mode1
, op1
);
11867 addr
= gen_rtx_MEM (tmode
, gen_rtx_PLUS (Pmode
, op1
, op2
));
11870 pat
= GEN_FCN (icode
) (addr
, op0
);
11876 /* Return the appropriate SPR number associated with the given builtin. */
11877 static inline HOST_WIDE_INT
11878 htm_spr_num (enum rs6000_builtins code
)
11880 if (code
== HTM_BUILTIN_GET_TFHAR
11881 || code
== HTM_BUILTIN_SET_TFHAR
)
11883 else if (code
== HTM_BUILTIN_GET_TFIAR
11884 || code
== HTM_BUILTIN_SET_TFIAR
)
11886 else if (code
== HTM_BUILTIN_GET_TEXASR
11887 || code
== HTM_BUILTIN_SET_TEXASR
)
11889 gcc_assert (code
== HTM_BUILTIN_GET_TEXASRU
11890 || code
== HTM_BUILTIN_SET_TEXASRU
);
11891 return TEXASRU_SPR
;
11894 /* Return the appropriate SPR regno associated with the given builtin. */
11895 static inline HOST_WIDE_INT
11896 htm_spr_regno (enum rs6000_builtins code
)
11898 if (code
== HTM_BUILTIN_GET_TFHAR
11899 || code
== HTM_BUILTIN_SET_TFHAR
)
11900 return TFHAR_REGNO
;
11901 else if (code
== HTM_BUILTIN_GET_TFIAR
11902 || code
== HTM_BUILTIN_SET_TFIAR
)
11903 return TFIAR_REGNO
;
11904 gcc_assert (code
== HTM_BUILTIN_GET_TEXASR
11905 || code
== HTM_BUILTIN_SET_TEXASR
11906 || code
== HTM_BUILTIN_GET_TEXASRU
11907 || code
== HTM_BUILTIN_SET_TEXASRU
);
11908 return TEXASR_REGNO
;
11911 /* Return the correct ICODE value depending on whether we are
11912 setting or reading the HTM SPRs. */
11913 static inline enum insn_code
11914 rs6000_htm_spr_icode (bool nonvoid
)
11917 return (TARGET_64BIT
) ? CODE_FOR_htm_mfspr_di
: CODE_FOR_htm_mfspr_si
;
11919 return (TARGET_64BIT
) ? CODE_FOR_htm_mtspr_di
: CODE_FOR_htm_mtspr_si
;
11922 /* Expand the HTM builtin in EXP and store the result in TARGET.
11923 Store true in *EXPANDEDP if we found a builtin to expand. */
11925 htm_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
11927 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
11928 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
11929 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
11930 const struct builtin_description
*d
;
11933 *expandedp
= false;
11935 /* Expand the HTM builtins. */
11937 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
11938 if (d
->code
== fcode
)
11940 rtx op
[MAX_HTM_OPERANDS
], pat
;
11943 call_expr_arg_iterator iter
;
11944 unsigned attr
= rs6000_builtin_info
[fcode
].attr
;
11945 enum insn_code icode
= d
->icode
;
11947 if (attr
& RS6000_BTC_SPR
)
11948 icode
= rs6000_htm_spr_icode (nonvoid
);
11952 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
11954 || GET_MODE (target
) != tmode
11955 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
11956 target
= gen_reg_rtx (tmode
);
11957 op
[nopnds
++] = target
;
11960 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
11962 const struct insn_operand_data
*insn_op
;
11964 if (arg
== error_mark_node
|| nopnds
>= MAX_HTM_OPERANDS
)
11967 insn_op
= &insn_data
[icode
].operand
[nopnds
];
11969 op
[nopnds
] = expand_normal (arg
);
11971 if (!(*insn_op
->predicate
) (op
[nopnds
], insn_op
->mode
))
11973 if (!strcmp (insn_op
->constraint
, "n"))
11975 int arg_num
= (nonvoid
) ? nopnds
: nopnds
+ 1;
11976 if (!CONST_INT_P (op
[nopnds
]))
11977 error ("argument %d must be an unsigned literal", arg_num
);
11979 error ("argument %d is an unsigned literal that is "
11980 "out of range", arg_num
);
11983 op
[nopnds
] = copy_to_mode_reg (insn_op
->mode
, op
[nopnds
]);
11989 /* Handle the builtins for extended mnemonics. These accept
11990 no arguments, but map to builtins that take arguments. */
11993 case HTM_BUILTIN_TENDALL
: /* Alias for: tend. 1 */
11994 case HTM_BUILTIN_TRESUME
: /* Alias for: tsr. 1 */
11995 op
[nopnds
++] = GEN_INT (1);
11996 #ifdef ENABLE_CHECKING
11997 attr
|= RS6000_BTC_UNARY
;
12000 case HTM_BUILTIN_TSUSPEND
: /* Alias for: tsr. 0 */
12001 op
[nopnds
++] = GEN_INT (0);
12002 #ifdef ENABLE_CHECKING
12003 attr
|= RS6000_BTC_UNARY
;
12010 /* If this builtin accesses SPRs, then pass in the appropriate
12011 SPR number and SPR regno as the last two operands. */
12012 if (attr
& RS6000_BTC_SPR
)
12014 op
[nopnds
++] = gen_rtx_CONST_INT (Pmode
, htm_spr_num (fcode
));
12015 op
[nopnds
++] = gen_rtx_REG (Pmode
, htm_spr_regno (fcode
));
12018 #ifdef ENABLE_CHECKING
12019 int expected_nopnds
= 0;
12020 if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_UNARY
)
12021 expected_nopnds
= 1;
12022 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_BINARY
)
12023 expected_nopnds
= 2;
12024 else if ((attr
& RS6000_BTC_TYPE_MASK
) == RS6000_BTC_TERNARY
)
12025 expected_nopnds
= 3;
12026 if (!(attr
& RS6000_BTC_VOID
))
12027 expected_nopnds
+= 1;
12028 if (attr
& RS6000_BTC_SPR
)
12029 expected_nopnds
+= 2;
12031 gcc_assert (nopnds
== expected_nopnds
&& nopnds
<= MAX_HTM_OPERANDS
);
12037 pat
= GEN_FCN (icode
) (op
[0]);
12040 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
12043 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
12046 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
12049 gcc_unreachable ();
12065 rs6000_expand_ternop_builtin (enum insn_code icode
, tree exp
, rtx target
)
12068 tree arg0
= CALL_EXPR_ARG (exp
, 0);
12069 tree arg1
= CALL_EXPR_ARG (exp
, 1);
12070 tree arg2
= CALL_EXPR_ARG (exp
, 2);
12071 rtx op0
= expand_normal (arg0
);
12072 rtx op1
= expand_normal (arg1
);
12073 rtx op2
= expand_normal (arg2
);
12074 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
12075 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12076 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12077 enum machine_mode mode2
= insn_data
[icode
].operand
[3].mode
;
12079 if (icode
== CODE_FOR_nothing
)
12080 /* Builtin not supported on this processor. */
12083 /* If we got invalid arguments bail out before generating bad rtl. */
12084 if (arg0
== error_mark_node
12085 || arg1
== error_mark_node
12086 || arg2
== error_mark_node
)
12089 /* Check and prepare argument depending on the instruction code.
12091 Note that a switch statement instead of the sequence of tests
12092 would be incorrect as many of the CODE_FOR values could be
12093 CODE_FOR_nothing and that would yield multiple alternatives
12094 with identical values. We'd never reach here at runtime in
12096 if (icode
== CODE_FOR_altivec_vsldoi_v4sf
12097 || icode
== CODE_FOR_altivec_vsldoi_v4si
12098 || icode
== CODE_FOR_altivec_vsldoi_v8hi
12099 || icode
== CODE_FOR_altivec_vsldoi_v16qi
)
12101 /* Only allow 4-bit unsigned literals. */
12103 if (TREE_CODE (arg2
) != INTEGER_CST
12104 || TREE_INT_CST_LOW (arg2
) & ~0xf)
12106 error ("argument 3 must be a 4-bit unsigned literal");
12110 else if (icode
== CODE_FOR_vsx_xxpermdi_v2df
12111 || icode
== CODE_FOR_vsx_xxpermdi_v2di
12112 || icode
== CODE_FOR_vsx_xxsldwi_v16qi
12113 || icode
== CODE_FOR_vsx_xxsldwi_v8hi
12114 || icode
== CODE_FOR_vsx_xxsldwi_v4si
12115 || icode
== CODE_FOR_vsx_xxsldwi_v4sf
12116 || icode
== CODE_FOR_vsx_xxsldwi_v2di
12117 || icode
== CODE_FOR_vsx_xxsldwi_v2df
)
12119 /* Only allow 2-bit unsigned literals. */
12121 if (TREE_CODE (arg2
) != INTEGER_CST
12122 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12124 error ("argument 3 must be a 2-bit unsigned literal");
12128 else if (icode
== CODE_FOR_vsx_set_v2df
12129 || icode
== CODE_FOR_vsx_set_v2di
)
12131 /* Only allow 1-bit unsigned literals. */
12133 if (TREE_CODE (arg2
) != INTEGER_CST
12134 || TREE_INT_CST_LOW (arg2
) & ~0x1)
12136 error ("argument 3 must be a 1-bit unsigned literal");
12140 else if (icode
== CODE_FOR_crypto_vshasigmaw
12141 || icode
== CODE_FOR_crypto_vshasigmad
)
12143 /* Check whether the 2nd and 3rd arguments are integer constants and in
12144 range and prepare arguments. */
12146 if (TREE_CODE (arg1
) != INTEGER_CST
12147 || !IN_RANGE (TREE_INT_CST_ELT (arg1
, 0), 0, 1))
12149 error ("argument 2 must be 0 or 1");
12154 if (TREE_CODE (arg2
) != INTEGER_CST
12155 || !IN_RANGE (TREE_INT_CST_ELT (arg2
, 0), 0, 15))
12157 error ("argument 3 must be in the range 0..15");
12163 || GET_MODE (target
) != tmode
12164 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12165 target
= gen_reg_rtx (tmode
);
12167 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12168 op0
= copy_to_mode_reg (mode0
, op0
);
12169 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12170 op1
= copy_to_mode_reg (mode1
, op1
);
12171 if (! (*insn_data
[icode
].operand
[3].predicate
) (op2
, mode2
))
12172 op2
= copy_to_mode_reg (mode2
, op2
);
12174 if (TARGET_PAIRED_FLOAT
&& icode
== CODE_FOR_selv2sf4
)
12175 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
, CONST0_RTX (SFmode
));
12177 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
12185 /* Expand the lvx builtins. */
12187 altivec_expand_ld_builtin (tree exp
, rtx target
, bool *expandedp
)
12189 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12190 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12192 enum machine_mode tmode
, mode0
;
12194 enum insn_code icode
;
12198 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi
:
12199 icode
= CODE_FOR_vector_altivec_load_v16qi
;
12201 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi
:
12202 icode
= CODE_FOR_vector_altivec_load_v8hi
;
12204 case ALTIVEC_BUILTIN_LD_INTERNAL_4si
:
12205 icode
= CODE_FOR_vector_altivec_load_v4si
;
12207 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf
:
12208 icode
= CODE_FOR_vector_altivec_load_v4sf
;
12210 case ALTIVEC_BUILTIN_LD_INTERNAL_2df
:
12211 icode
= CODE_FOR_vector_altivec_load_v2df
;
12213 case ALTIVEC_BUILTIN_LD_INTERNAL_2di
:
12214 icode
= CODE_FOR_vector_altivec_load_v2di
;
12217 *expandedp
= false;
12223 arg0
= CALL_EXPR_ARG (exp
, 0);
12224 op0
= expand_normal (arg0
);
12225 tmode
= insn_data
[icode
].operand
[0].mode
;
12226 mode0
= insn_data
[icode
].operand
[1].mode
;
12229 || GET_MODE (target
) != tmode
12230 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12231 target
= gen_reg_rtx (tmode
);
12233 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12234 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12236 pat
= GEN_FCN (icode
) (target
, op0
);
12243 /* Expand the stvx builtins. */
12245 altivec_expand_st_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12248 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12249 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
12251 enum machine_mode mode0
, mode1
;
12253 enum insn_code icode
;
12257 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi
:
12258 icode
= CODE_FOR_vector_altivec_store_v16qi
;
12260 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi
:
12261 icode
= CODE_FOR_vector_altivec_store_v8hi
;
12263 case ALTIVEC_BUILTIN_ST_INTERNAL_4si
:
12264 icode
= CODE_FOR_vector_altivec_store_v4si
;
12266 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf
:
12267 icode
= CODE_FOR_vector_altivec_store_v4sf
;
12269 case ALTIVEC_BUILTIN_ST_INTERNAL_2df
:
12270 icode
= CODE_FOR_vector_altivec_store_v2df
;
12272 case ALTIVEC_BUILTIN_ST_INTERNAL_2di
:
12273 icode
= CODE_FOR_vector_altivec_store_v2di
;
12276 *expandedp
= false;
12280 arg0
= CALL_EXPR_ARG (exp
, 0);
12281 arg1
= CALL_EXPR_ARG (exp
, 1);
12282 op0
= expand_normal (arg0
);
12283 op1
= expand_normal (arg1
);
12284 mode0
= insn_data
[icode
].operand
[0].mode
;
12285 mode1
= insn_data
[icode
].operand
[1].mode
;
12287 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12288 op0
= gen_rtx_MEM (mode0
, copy_to_mode_reg (Pmode
, op0
));
12289 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
12290 op1
= copy_to_mode_reg (mode1
, op1
);
12292 pat
= GEN_FCN (icode
) (op0
, op1
);
12300 /* Expand the dst builtins. */
12302 altivec_expand_dst_builtin (tree exp
, rtx target ATTRIBUTE_UNUSED
,
12305 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12306 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12307 tree arg0
, arg1
, arg2
;
12308 enum machine_mode mode0
, mode1
;
12309 rtx pat
, op0
, op1
, op2
;
12310 const struct builtin_description
*d
;
12313 *expandedp
= false;
12315 /* Handle DST variants. */
12317 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
12318 if (d
->code
== fcode
)
12320 arg0
= CALL_EXPR_ARG (exp
, 0);
12321 arg1
= CALL_EXPR_ARG (exp
, 1);
12322 arg2
= CALL_EXPR_ARG (exp
, 2);
12323 op0
= expand_normal (arg0
);
12324 op1
= expand_normal (arg1
);
12325 op2
= expand_normal (arg2
);
12326 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
12327 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
12329 /* Invalid arguments, bail out before generating bad rtl. */
12330 if (arg0
== error_mark_node
12331 || arg1
== error_mark_node
12332 || arg2
== error_mark_node
)
12337 if (TREE_CODE (arg2
) != INTEGER_CST
12338 || TREE_INT_CST_LOW (arg2
) & ~0x3)
12340 error ("argument to %qs must be a 2-bit unsigned literal", d
->name
);
12344 if (! (*insn_data
[d
->icode
].operand
[0].predicate
) (op0
, mode0
))
12345 op0
= copy_to_mode_reg (Pmode
, op0
);
12346 if (! (*insn_data
[d
->icode
].operand
[1].predicate
) (op1
, mode1
))
12347 op1
= copy_to_mode_reg (mode1
, op1
);
12349 pat
= GEN_FCN (d
->icode
) (op0
, op1
, op2
);
12359 /* Expand vec_init builtin. */
12361 altivec_expand_vec_init_builtin (tree type
, tree exp
, rtx target
)
12363 enum machine_mode tmode
= TYPE_MODE (type
);
12364 enum machine_mode inner_mode
= GET_MODE_INNER (tmode
);
12365 int i
, n_elt
= GET_MODE_NUNITS (tmode
);
12366 rtvec v
= rtvec_alloc (n_elt
);
12368 gcc_assert (VECTOR_MODE_P (tmode
));
12369 gcc_assert (n_elt
== call_expr_nargs (exp
));
12371 for (i
= 0; i
< n_elt
; ++i
)
12373 rtx x
= expand_normal (CALL_EXPR_ARG (exp
, i
));
12374 RTVEC_ELT (v
, i
) = gen_lowpart (inner_mode
, x
);
12377 if (!target
|| !register_operand (target
, tmode
))
12378 target
= gen_reg_rtx (tmode
);
12380 rs6000_expand_vector_init (target
, gen_rtx_PARALLEL (tmode
, v
));
12384 /* Return the integer constant in ARG. Constrain it to be in the range
12385 of the subparts of VEC_TYPE; issue an error if not. */
12388 get_element_number (tree vec_type
, tree arg
)
12390 unsigned HOST_WIDE_INT elt
, max
= TYPE_VECTOR_SUBPARTS (vec_type
) - 1;
12392 if (!tree_fits_uhwi_p (arg
)
12393 || (elt
= tree_to_uhwi (arg
), elt
> max
))
12395 error ("selector must be an integer constant in the range 0..%wi", max
);
12402 /* Expand vec_set builtin. */
12404 altivec_expand_vec_set_builtin (tree exp
)
12406 enum machine_mode tmode
, mode1
;
12407 tree arg0
, arg1
, arg2
;
12411 arg0
= CALL_EXPR_ARG (exp
, 0);
12412 arg1
= CALL_EXPR_ARG (exp
, 1);
12413 arg2
= CALL_EXPR_ARG (exp
, 2);
12415 tmode
= TYPE_MODE (TREE_TYPE (arg0
));
12416 mode1
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12417 gcc_assert (VECTOR_MODE_P (tmode
));
12419 op0
= expand_expr (arg0
, NULL_RTX
, tmode
, EXPAND_NORMAL
);
12420 op1
= expand_expr (arg1
, NULL_RTX
, mode1
, EXPAND_NORMAL
);
12421 elt
= get_element_number (TREE_TYPE (arg0
), arg2
);
12423 if (GET_MODE (op1
) != mode1
&& GET_MODE (op1
) != VOIDmode
)
12424 op1
= convert_modes (mode1
, GET_MODE (op1
), op1
, true);
12426 op0
= force_reg (tmode
, op0
);
12427 op1
= force_reg (mode1
, op1
);
12429 rs6000_expand_vector_set (op0
, op1
, elt
);
12434 /* Expand vec_ext builtin. */
12436 altivec_expand_vec_ext_builtin (tree exp
, rtx target
)
12438 enum machine_mode tmode
, mode0
;
12443 arg0
= CALL_EXPR_ARG (exp
, 0);
12444 arg1
= CALL_EXPR_ARG (exp
, 1);
12446 op0
= expand_normal (arg0
);
12447 elt
= get_element_number (TREE_TYPE (arg0
), arg1
);
12449 tmode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0
)));
12450 mode0
= TYPE_MODE (TREE_TYPE (arg0
));
12451 gcc_assert (VECTOR_MODE_P (mode0
));
12453 op0
= force_reg (mode0
, op0
);
12455 if (optimize
|| !target
|| !register_operand (target
, tmode
))
12456 target
= gen_reg_rtx (tmode
);
12458 rs6000_expand_vector_extract (target
, op0
, elt
);
12463 /* Expand the builtin in EXP and store the result in TARGET. Store
12464 true in *EXPANDEDP if we found a builtin to expand. */
12466 altivec_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12468 const struct builtin_description
*d
;
12470 enum insn_code icode
;
12471 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12474 enum machine_mode tmode
, mode0
;
12475 enum rs6000_builtins fcode
12476 = (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12478 if (rs6000_overloaded_builtin_p (fcode
))
12481 error ("unresolved overload for Altivec builtin %qF", fndecl
);
12483 /* Given it is invalid, just generate a normal call. */
12484 return expand_call (exp
, target
, false);
12487 target
= altivec_expand_ld_builtin (exp
, target
, expandedp
);
12491 target
= altivec_expand_st_builtin (exp
, target
, expandedp
);
12495 target
= altivec_expand_dst_builtin (exp
, target
, expandedp
);
12503 case ALTIVEC_BUILTIN_STVX
:
12504 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx_v4si
, exp
);
12505 case ALTIVEC_BUILTIN_STVEBX
:
12506 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx
, exp
);
12507 case ALTIVEC_BUILTIN_STVEHX
:
12508 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx
, exp
);
12509 case ALTIVEC_BUILTIN_STVEWX
:
12510 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx
, exp
);
12511 case ALTIVEC_BUILTIN_STVXL
:
12512 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl
, exp
);
12514 case ALTIVEC_BUILTIN_STVLX
:
12515 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlx
, exp
);
12516 case ALTIVEC_BUILTIN_STVLXL
:
12517 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvlxl
, exp
);
12518 case ALTIVEC_BUILTIN_STVRX
:
12519 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrx
, exp
);
12520 case ALTIVEC_BUILTIN_STVRXL
:
12521 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvrxl
, exp
);
12523 case VSX_BUILTIN_STXVD2X_V2DF
:
12524 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2df
, exp
);
12525 case VSX_BUILTIN_STXVD2X_V2DI
:
12526 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v2di
, exp
);
12527 case VSX_BUILTIN_STXVW4X_V4SF
:
12528 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4sf
, exp
);
12529 case VSX_BUILTIN_STXVW4X_V4SI
:
12530 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v4si
, exp
);
12531 case VSX_BUILTIN_STXVW4X_V8HI
:
12532 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v8hi
, exp
);
12533 case VSX_BUILTIN_STXVW4X_V16QI
:
12534 return altivec_expand_stv_builtin (CODE_FOR_vsx_store_v16qi
, exp
);
12536 case ALTIVEC_BUILTIN_MFVSCR
:
12537 icode
= CODE_FOR_altivec_mfvscr
;
12538 tmode
= insn_data
[icode
].operand
[0].mode
;
12541 || GET_MODE (target
) != tmode
12542 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12543 target
= gen_reg_rtx (tmode
);
12545 pat
= GEN_FCN (icode
) (target
);
12551 case ALTIVEC_BUILTIN_MTVSCR
:
12552 icode
= CODE_FOR_altivec_mtvscr
;
12553 arg0
= CALL_EXPR_ARG (exp
, 0);
12554 op0
= expand_normal (arg0
);
12555 mode0
= insn_data
[icode
].operand
[0].mode
;
12557 /* If we got invalid arguments bail out before generating bad rtl. */
12558 if (arg0
== error_mark_node
)
12561 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12562 op0
= copy_to_mode_reg (mode0
, op0
);
12564 pat
= GEN_FCN (icode
) (op0
);
12569 case ALTIVEC_BUILTIN_DSSALL
:
12570 emit_insn (gen_altivec_dssall ());
12573 case ALTIVEC_BUILTIN_DSS
:
12574 icode
= CODE_FOR_altivec_dss
;
12575 arg0
= CALL_EXPR_ARG (exp
, 0);
12577 op0
= expand_normal (arg0
);
12578 mode0
= insn_data
[icode
].operand
[0].mode
;
12580 /* If we got invalid arguments bail out before generating bad rtl. */
12581 if (arg0
== error_mark_node
)
12584 if (TREE_CODE (arg0
) != INTEGER_CST
12585 || TREE_INT_CST_LOW (arg0
) & ~0x3)
12587 error ("argument to dss must be a 2-bit unsigned literal");
12591 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12592 op0
= copy_to_mode_reg (mode0
, op0
);
12594 emit_insn (gen_altivec_dss (op0
));
12597 case ALTIVEC_BUILTIN_VEC_INIT_V4SI
:
12598 case ALTIVEC_BUILTIN_VEC_INIT_V8HI
:
12599 case ALTIVEC_BUILTIN_VEC_INIT_V16QI
:
12600 case ALTIVEC_BUILTIN_VEC_INIT_V4SF
:
12601 case VSX_BUILTIN_VEC_INIT_V2DF
:
12602 case VSX_BUILTIN_VEC_INIT_V2DI
:
12603 return altivec_expand_vec_init_builtin (TREE_TYPE (exp
), exp
, target
);
12605 case ALTIVEC_BUILTIN_VEC_SET_V4SI
:
12606 case ALTIVEC_BUILTIN_VEC_SET_V8HI
:
12607 case ALTIVEC_BUILTIN_VEC_SET_V16QI
:
12608 case ALTIVEC_BUILTIN_VEC_SET_V4SF
:
12609 case VSX_BUILTIN_VEC_SET_V2DF
:
12610 case VSX_BUILTIN_VEC_SET_V2DI
:
12611 return altivec_expand_vec_set_builtin (exp
);
12613 case ALTIVEC_BUILTIN_VEC_EXT_V4SI
:
12614 case ALTIVEC_BUILTIN_VEC_EXT_V8HI
:
12615 case ALTIVEC_BUILTIN_VEC_EXT_V16QI
:
12616 case ALTIVEC_BUILTIN_VEC_EXT_V4SF
:
12617 case VSX_BUILTIN_VEC_EXT_V2DF
:
12618 case VSX_BUILTIN_VEC_EXT_V2DI
:
12619 return altivec_expand_vec_ext_builtin (exp
, target
);
12623 /* Fall through. */
12626 /* Expand abs* operations. */
12628 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
12629 if (d
->code
== fcode
)
12630 return altivec_expand_abs_builtin (d
->icode
, exp
, target
);
12632 /* Expand the AltiVec predicates. */
12633 d
= bdesc_altivec_preds
;
12634 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
12635 if (d
->code
== fcode
)
12636 return altivec_expand_predicate_builtin (d
->icode
, exp
, target
);
12638 /* LV* are funky. We initialized them differently. */
12641 case ALTIVEC_BUILTIN_LVSL
:
12642 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl
,
12643 exp
, target
, false);
12644 case ALTIVEC_BUILTIN_LVSR
:
12645 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr
,
12646 exp
, target
, false);
12647 case ALTIVEC_BUILTIN_LVEBX
:
12648 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx
,
12649 exp
, target
, false);
12650 case ALTIVEC_BUILTIN_LVEHX
:
12651 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx
,
12652 exp
, target
, false);
12653 case ALTIVEC_BUILTIN_LVEWX
:
12654 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx
,
12655 exp
, target
, false);
12656 case ALTIVEC_BUILTIN_LVXL
:
12657 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl
,
12658 exp
, target
, false);
12659 case ALTIVEC_BUILTIN_LVX
:
12660 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx_v4si
,
12661 exp
, target
, false);
12662 case ALTIVEC_BUILTIN_LVLX
:
12663 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlx
,
12664 exp
, target
, true);
12665 case ALTIVEC_BUILTIN_LVLXL
:
12666 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvlxl
,
12667 exp
, target
, true);
12668 case ALTIVEC_BUILTIN_LVRX
:
12669 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrx
,
12670 exp
, target
, true);
12671 case ALTIVEC_BUILTIN_LVRXL
:
12672 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvrxl
,
12673 exp
, target
, true);
12674 case VSX_BUILTIN_LXVD2X_V2DF
:
12675 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2df
,
12676 exp
, target
, false);
12677 case VSX_BUILTIN_LXVD2X_V2DI
:
12678 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v2di
,
12679 exp
, target
, false);
12680 case VSX_BUILTIN_LXVW4X_V4SF
:
12681 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4sf
,
12682 exp
, target
, false);
12683 case VSX_BUILTIN_LXVW4X_V4SI
:
12684 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v4si
,
12685 exp
, target
, false);
12686 case VSX_BUILTIN_LXVW4X_V8HI
:
12687 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v8hi
,
12688 exp
, target
, false);
12689 case VSX_BUILTIN_LXVW4X_V16QI
:
12690 return altivec_expand_lv_builtin (CODE_FOR_vsx_load_v16qi
,
12691 exp
, target
, false);
12695 /* Fall through. */
12698 *expandedp
= false;
12702 /* Expand the builtin in EXP and store the result in TARGET. Store
12703 true in *EXPANDEDP if we found a builtin to expand. */
12705 paired_expand_builtin (tree exp
, rtx target
, bool * expandedp
)
12707 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12708 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12709 const struct builtin_description
*d
;
12716 case PAIRED_BUILTIN_STX
:
12717 return paired_expand_stv_builtin (CODE_FOR_paired_stx
, exp
);
12718 case PAIRED_BUILTIN_LX
:
12719 return paired_expand_lv_builtin (CODE_FOR_paired_lx
, exp
, target
);
12722 /* Fall through. */
12725 /* Expand the paired predicates. */
12726 d
= bdesc_paired_preds
;
12727 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); i
++, d
++)
12728 if (d
->code
== fcode
)
12729 return paired_expand_predicate_builtin (d
->icode
, exp
, target
);
12731 *expandedp
= false;
12735 /* Binops that need to be initialized manually, but can be expanded
12736 automagically by rs6000_expand_binop_builtin. */
12737 static const struct builtin_description bdesc_2arg_spe
[] =
12739 { RS6000_BTM_SPE
, CODE_FOR_spe_evlddx
, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX
},
12740 { RS6000_BTM_SPE
, CODE_FOR_spe_evldwx
, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX
},
12741 { RS6000_BTM_SPE
, CODE_FOR_spe_evldhx
, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX
},
12742 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhex
, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX
},
12743 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhoux
, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX
},
12744 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhosx
, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX
},
12745 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplatx
, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX
},
12746 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplatx
, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX
},
12747 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplatx
, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX
},
12748 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplatx
, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX
},
12749 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplatx
, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX
},
12750 { RS6000_BTM_SPE
, CODE_FOR_spe_evldd
, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD
},
12751 { RS6000_BTM_SPE
, CODE_FOR_spe_evldw
, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW
},
12752 { RS6000_BTM_SPE
, CODE_FOR_spe_evldh
, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH
},
12753 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhe
, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE
},
12754 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhou
, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU
},
12755 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhos
, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS
},
12756 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwwsplat
, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT
},
12757 { RS6000_BTM_SPE
, CODE_FOR_spe_evlwhsplat
, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT
},
12758 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhesplat
, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT
},
12759 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhousplat
, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT
},
12760 { RS6000_BTM_SPE
, CODE_FOR_spe_evlhhossplat
, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT
}
12763 /* Expand the builtin in EXP and store the result in TARGET. Store
12764 true in *EXPANDEDP if we found a builtin to expand.
12766 This expands the SPE builtins that are not simple unary and binary
12769 spe_expand_builtin (tree exp
, rtx target
, bool *expandedp
)
12771 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
12773 enum rs6000_builtins fcode
= (enum rs6000_builtins
) DECL_FUNCTION_CODE (fndecl
);
12774 enum insn_code icode
;
12775 enum machine_mode tmode
, mode0
;
12777 const struct builtin_description
*d
;
12782 /* Syntax check for a 5-bit unsigned immediate. */
12785 case SPE_BUILTIN_EVSTDD
:
12786 case SPE_BUILTIN_EVSTDH
:
12787 case SPE_BUILTIN_EVSTDW
:
12788 case SPE_BUILTIN_EVSTWHE
:
12789 case SPE_BUILTIN_EVSTWHO
:
12790 case SPE_BUILTIN_EVSTWWE
:
12791 case SPE_BUILTIN_EVSTWWO
:
12792 arg1
= CALL_EXPR_ARG (exp
, 2);
12793 if (TREE_CODE (arg1
) != INTEGER_CST
12794 || TREE_INT_CST_LOW (arg1
) & ~0x1f)
12796 error ("argument 2 must be a 5-bit unsigned literal");
12804 /* The evsplat*i instructions are not quite generic. */
12807 case SPE_BUILTIN_EVSPLATFI
:
12808 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi
,
12810 case SPE_BUILTIN_EVSPLATI
:
12811 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati
,
12817 d
= bdesc_2arg_spe
;
12818 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg_spe
); ++i
, ++d
)
12819 if (d
->code
== fcode
)
12820 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
12822 d
= bdesc_spe_predicates
;
12823 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, ++d
)
12824 if (d
->code
== fcode
)
12825 return spe_expand_predicate_builtin (d
->icode
, exp
, target
);
12827 d
= bdesc_spe_evsel
;
12828 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, ++d
)
12829 if (d
->code
== fcode
)
12830 return spe_expand_evsel_builtin (d
->icode
, exp
, target
);
12834 case SPE_BUILTIN_EVSTDDX
:
12835 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx
, exp
);
12836 case SPE_BUILTIN_EVSTDHX
:
12837 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx
, exp
);
12838 case SPE_BUILTIN_EVSTDWX
:
12839 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx
, exp
);
12840 case SPE_BUILTIN_EVSTWHEX
:
12841 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex
, exp
);
12842 case SPE_BUILTIN_EVSTWHOX
:
12843 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox
, exp
);
12844 case SPE_BUILTIN_EVSTWWEX
:
12845 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex
, exp
);
12846 case SPE_BUILTIN_EVSTWWOX
:
12847 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox
, exp
);
12848 case SPE_BUILTIN_EVSTDD
:
12849 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd
, exp
);
12850 case SPE_BUILTIN_EVSTDH
:
12851 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh
, exp
);
12852 case SPE_BUILTIN_EVSTDW
:
12853 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw
, exp
);
12854 case SPE_BUILTIN_EVSTWHE
:
12855 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe
, exp
);
12856 case SPE_BUILTIN_EVSTWHO
:
12857 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho
, exp
);
12858 case SPE_BUILTIN_EVSTWWE
:
12859 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe
, exp
);
12860 case SPE_BUILTIN_EVSTWWO
:
12861 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo
, exp
);
12862 case SPE_BUILTIN_MFSPEFSCR
:
12863 icode
= CODE_FOR_spe_mfspefscr
;
12864 tmode
= insn_data
[icode
].operand
[0].mode
;
12867 || GET_MODE (target
) != tmode
12868 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
12869 target
= gen_reg_rtx (tmode
);
12871 pat
= GEN_FCN (icode
) (target
);
12876 case SPE_BUILTIN_MTSPEFSCR
:
12877 icode
= CODE_FOR_spe_mtspefscr
;
12878 arg0
= CALL_EXPR_ARG (exp
, 0);
12879 op0
= expand_normal (arg0
);
12880 mode0
= insn_data
[icode
].operand
[0].mode
;
12882 if (arg0
== error_mark_node
)
12885 if (! (*insn_data
[icode
].operand
[0].predicate
) (op0
, mode0
))
12886 op0
= copy_to_mode_reg (mode0
, op0
);
12888 pat
= GEN_FCN (icode
) (op0
);
12896 *expandedp
= false;
12901 paired_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12903 rtx pat
, scratch
, tmp
;
12904 tree form
= CALL_EXPR_ARG (exp
, 0);
12905 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12906 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12907 rtx op0
= expand_normal (arg0
);
12908 rtx op1
= expand_normal (arg1
);
12909 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12910 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12912 enum rtx_code code
;
12914 if (TREE_CODE (form
) != INTEGER_CST
)
12916 error ("argument 1 of __builtin_paired_predicate must be a constant");
12920 form_int
= TREE_INT_CST_LOW (form
);
12922 gcc_assert (mode0
== mode1
);
12924 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
12928 || GET_MODE (target
) != SImode
12929 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
12930 target
= gen_reg_rtx (SImode
);
12931 if (!(*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
12932 op0
= copy_to_mode_reg (mode0
, op0
);
12933 if (!(*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
12934 op1
= copy_to_mode_reg (mode1
, op1
);
12936 scratch
= gen_reg_rtx (CCFPmode
);
12938 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
12960 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
12963 error ("argument 1 of __builtin_paired_predicate is out of range");
12967 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
12968 emit_move_insn (target
, tmp
);
12973 spe_expand_predicate_builtin (enum insn_code icode
, tree exp
, rtx target
)
12975 rtx pat
, scratch
, tmp
;
12976 tree form
= CALL_EXPR_ARG (exp
, 0);
12977 tree arg0
= CALL_EXPR_ARG (exp
, 1);
12978 tree arg1
= CALL_EXPR_ARG (exp
, 2);
12979 rtx op0
= expand_normal (arg0
);
12980 rtx op1
= expand_normal (arg1
);
12981 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
12982 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
12984 enum rtx_code code
;
12986 if (TREE_CODE (form
) != INTEGER_CST
)
12988 error ("argument 1 of __builtin_spe_predicate must be a constant");
12992 form_int
= TREE_INT_CST_LOW (form
);
12994 gcc_assert (mode0
== mode1
);
12996 if (arg0
== error_mark_node
|| arg1
== error_mark_node
)
13000 || GET_MODE (target
) != SImode
13001 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, SImode
))
13002 target
= gen_reg_rtx (SImode
);
13004 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13005 op0
= copy_to_mode_reg (mode0
, op0
);
13006 if (! (*insn_data
[icode
].operand
[2].predicate
) (op1
, mode1
))
13007 op1
= copy_to_mode_reg (mode1
, op1
);
13009 scratch
= gen_reg_rtx (CCmode
);
13011 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13016 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
13017 _lower_. We use one compare, but look in different bits of the
13018 CR for each variant.
13020 There are 2 elements in each SPE simd type (upper/lower). The CR
13021 bits are set as follows:
13023 BIT0 | BIT 1 | BIT 2 | BIT 3
13024 U | L | (U | L) | (U & L)
13026 So, for an "all" relationship, BIT 3 would be set.
13027 For an "any" relationship, BIT 2 would be set. Etc.
13029 Following traditional nomenclature, these bits map to:
13031 BIT0 | BIT 1 | BIT 2 | BIT 3
13034 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
13039 /* All variant. OV bit. */
13041 /* We need to get to the OV bit, which is the ORDERED bit. We
13042 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
13043 that's ugly and will make validate_condition_mode die.
13044 So let's just use another pattern. */
13045 emit_insn (gen_move_from_CR_ov_bit (target
, scratch
));
13047 /* Any variant. EQ bit. */
13051 /* Upper variant. LT bit. */
13055 /* Lower variant. GT bit. */
13060 error ("argument 1 of __builtin_spe_predicate is out of range");
13064 tmp
= gen_rtx_fmt_ee (code
, SImode
, scratch
, const0_rtx
);
13065 emit_move_insn (target
, tmp
);
13070 /* The evsel builtins look like this:
13072 e = __builtin_spe_evsel_OP (a, b, c, d);
13074 and work like this:
13076 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
13077 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
13081 spe_expand_evsel_builtin (enum insn_code icode
, tree exp
, rtx target
)
13084 tree arg0
= CALL_EXPR_ARG (exp
, 0);
13085 tree arg1
= CALL_EXPR_ARG (exp
, 1);
13086 tree arg2
= CALL_EXPR_ARG (exp
, 2);
13087 tree arg3
= CALL_EXPR_ARG (exp
, 3);
13088 rtx op0
= expand_normal (arg0
);
13089 rtx op1
= expand_normal (arg1
);
13090 rtx op2
= expand_normal (arg2
);
13091 rtx op3
= expand_normal (arg3
);
13092 enum machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
13093 enum machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
13095 gcc_assert (mode0
== mode1
);
13097 if (arg0
== error_mark_node
|| arg1
== error_mark_node
13098 || arg2
== error_mark_node
|| arg3
== error_mark_node
)
13102 || GET_MODE (target
) != mode0
13103 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode0
))
13104 target
= gen_reg_rtx (mode0
);
13106 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
13107 op0
= copy_to_mode_reg (mode0
, op0
);
13108 if (! (*insn_data
[icode
].operand
[1].predicate
) (op1
, mode1
))
13109 op1
= copy_to_mode_reg (mode0
, op1
);
13110 if (! (*insn_data
[icode
].operand
[1].predicate
) (op2
, mode1
))
13111 op2
= copy_to_mode_reg (mode0
, op2
);
13112 if (! (*insn_data
[icode
].operand
[1].predicate
) (op3
, mode1
))
13113 op3
= copy_to_mode_reg (mode0
, op3
);
13115 /* Generate the compare. */
13116 scratch
= gen_reg_rtx (CCmode
);
13117 pat
= GEN_FCN (icode
) (scratch
, op0
, op1
);
13122 if (mode0
== V2SImode
)
13123 emit_insn (gen_spe_evsel (target
, op2
, op3
, scratch
));
13125 emit_insn (gen_spe_evsel_fs (target
, op2
, op3
, scratch
));
13130 /* Raise an error message for a builtin function that is called without the
13131 appropriate target options being set. */
13134 rs6000_invalid_builtin (enum rs6000_builtins fncode
)
13136 size_t uns_fncode
= (size_t)fncode
;
13137 const char *name
= rs6000_builtin_info
[uns_fncode
].name
;
13138 HOST_WIDE_INT fnmask
= rs6000_builtin_info
[uns_fncode
].mask
;
13140 gcc_assert (name
!= NULL
);
13141 if ((fnmask
& RS6000_BTM_CELL
) != 0)
13142 error ("Builtin function %s is only valid for the cell processor", name
);
13143 else if ((fnmask
& RS6000_BTM_VSX
) != 0)
13144 error ("Builtin function %s requires the -mvsx option", name
);
13145 else if ((fnmask
& RS6000_BTM_HTM
) != 0)
13146 error ("Builtin function %s requires the -mhtm option", name
);
13147 else if ((fnmask
& RS6000_BTM_ALTIVEC
) != 0)
13148 error ("Builtin function %s requires the -maltivec option", name
);
13149 else if ((fnmask
& RS6000_BTM_PAIRED
) != 0)
13150 error ("Builtin function %s requires the -mpaired option", name
);
13151 else if ((fnmask
& RS6000_BTM_SPE
) != 0)
13152 error ("Builtin function %s requires the -mspe option", name
);
13154 error ("Builtin function %s is not supported with the current options",
13158 /* Expand an expression EXP that calls a built-in function,
13159 with result going to TARGET if that's convenient
13160 (and in mode MODE if that's convenient).
13161 SUBTARGET may be used as the target for computing one of EXP's operands.
13162 IGNORE is nonzero if the value is to be ignored. */
13165 rs6000_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
13166 enum machine_mode mode ATTRIBUTE_UNUSED
,
13167 int ignore ATTRIBUTE_UNUSED
)
13169 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
13170 enum rs6000_builtins fcode
13171 = (enum rs6000_builtins
)DECL_FUNCTION_CODE (fndecl
);
13172 size_t uns_fcode
= (size_t)fcode
;
13173 const struct builtin_description
*d
;
13177 HOST_WIDE_INT mask
= rs6000_builtin_info
[uns_fcode
].mask
;
13178 bool func_valid_p
= ((rs6000_builtin_mask
& mask
) == mask
);
13180 if (TARGET_DEBUG_BUILTIN
)
13182 enum insn_code icode
= rs6000_builtin_info
[uns_fcode
].icode
;
13183 const char *name1
= rs6000_builtin_info
[uns_fcode
].name
;
13184 const char *name2
= ((icode
!= CODE_FOR_nothing
)
13185 ? get_insn_name ((int)icode
)
13189 switch (rs6000_builtin_info
[uns_fcode
].attr
& RS6000_BTC_TYPE_MASK
)
13191 default: name3
= "unknown"; break;
13192 case RS6000_BTC_SPECIAL
: name3
= "special"; break;
13193 case RS6000_BTC_UNARY
: name3
= "unary"; break;
13194 case RS6000_BTC_BINARY
: name3
= "binary"; break;
13195 case RS6000_BTC_TERNARY
: name3
= "ternary"; break;
13196 case RS6000_BTC_PREDICATE
: name3
= "predicate"; break;
13197 case RS6000_BTC_ABS
: name3
= "abs"; break;
13198 case RS6000_BTC_EVSEL
: name3
= "evsel"; break;
13199 case RS6000_BTC_DST
: name3
= "dst"; break;
13204 "rs6000_expand_builtin, %s (%d), insn = %s (%d), type=%s%s\n",
13205 (name1
) ? name1
: "---", fcode
,
13206 (name2
) ? name2
: "---", (int)icode
,
13208 func_valid_p
? "" : ", not valid");
13213 rs6000_invalid_builtin (fcode
);
13215 /* Given it is invalid, just generate a normal call. */
13216 return expand_call (exp
, target
, ignore
);
13221 case RS6000_BUILTIN_RECIP
:
13222 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3
, exp
, target
);
13224 case RS6000_BUILTIN_RECIPF
:
13225 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3
, exp
, target
);
13227 case RS6000_BUILTIN_RSQRTF
:
13228 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2
, exp
, target
);
13230 case RS6000_BUILTIN_RSQRT
:
13231 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtdf2
, exp
, target
);
13233 case POWER7_BUILTIN_BPERMD
:
13234 return rs6000_expand_binop_builtin (((TARGET_64BIT
)
13235 ? CODE_FOR_bpermd_di
13236 : CODE_FOR_bpermd_si
), exp
, target
);
13238 case RS6000_BUILTIN_GET_TB
:
13239 return rs6000_expand_zeroop_builtin (CODE_FOR_rs6000_get_timebase
,
13242 case RS6000_BUILTIN_MFTB
:
13243 return rs6000_expand_zeroop_builtin (((TARGET_64BIT
)
13244 ? CODE_FOR_rs6000_mftb_di
13245 : CODE_FOR_rs6000_mftb_si
),
13248 case ALTIVEC_BUILTIN_MASK_FOR_LOAD
:
13249 case ALTIVEC_BUILTIN_MASK_FOR_STORE
:
13251 int icode
= (BYTES_BIG_ENDIAN
? (int) CODE_FOR_altivec_lvsr
13252 : (int) CODE_FOR_altivec_lvsl
);
13253 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
13254 enum machine_mode mode
= insn_data
[icode
].operand
[1].mode
;
13258 gcc_assert (TARGET_ALTIVEC
);
13260 arg
= CALL_EXPR_ARG (exp
, 0);
13261 gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg
)));
13262 op
= expand_expr (arg
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
13263 addr
= memory_address (mode
, op
);
13264 if (fcode
== ALTIVEC_BUILTIN_MASK_FOR_STORE
)
13268 /* For the load case need to negate the address. */
13269 op
= gen_reg_rtx (GET_MODE (addr
));
13270 emit_insn (gen_rtx_SET (VOIDmode
, op
,
13271 gen_rtx_NEG (GET_MODE (addr
), addr
)));
13273 op
= gen_rtx_MEM (mode
, op
);
13276 || GET_MODE (target
) != tmode
13277 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
13278 target
= gen_reg_rtx (tmode
);
13280 /*pat = gen_altivec_lvsr (target, op);*/
13281 pat
= GEN_FCN (icode
) (target
, op
);
13289 case ALTIVEC_BUILTIN_VCFUX
:
13290 case ALTIVEC_BUILTIN_VCFSX
:
13291 case ALTIVEC_BUILTIN_VCTUXS
:
13292 case ALTIVEC_BUILTIN_VCTSXS
:
13293 /* FIXME: There's got to be a nicer way to handle this case than
13294 constructing a new CALL_EXPR. */
13295 if (call_expr_nargs (exp
) == 1)
13297 exp
= build_call_nary (TREE_TYPE (exp
), CALL_EXPR_FN (exp
),
13298 2, CALL_EXPR_ARG (exp
, 0), integer_zero_node
);
13306 if (TARGET_ALTIVEC
)
13308 ret
= altivec_expand_builtin (exp
, target
, &success
);
13315 ret
= spe_expand_builtin (exp
, target
, &success
);
13320 if (TARGET_PAIRED_FLOAT
)
13322 ret
= paired_expand_builtin (exp
, target
, &success
);
13329 ret
= htm_expand_builtin (exp
, target
, &success
);
13335 gcc_assert (TARGET_ALTIVEC
|| TARGET_VSX
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
);
13337 /* Handle simple unary operations. */
13339 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
13340 if (d
->code
== fcode
)
13341 return rs6000_expand_unop_builtin (d
->icode
, exp
, target
);
13343 /* Handle simple binary operations. */
13345 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
13346 if (d
->code
== fcode
)
13347 return rs6000_expand_binop_builtin (d
->icode
, exp
, target
);
13349 /* Handle simple ternary operations. */
13351 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
13352 if (d
->code
== fcode
)
13353 return rs6000_expand_ternop_builtin (d
->icode
, exp
, target
);
13355 gcc_unreachable ();
13359 rs6000_init_builtins (void)
13363 enum machine_mode mode
;
13365 if (TARGET_DEBUG_BUILTIN
)
13366 fprintf (stderr
, "rs6000_init_builtins%s%s%s%s\n",
13367 (TARGET_PAIRED_FLOAT
) ? ", paired" : "",
13368 (TARGET_SPE
) ? ", spe" : "",
13369 (TARGET_ALTIVEC
) ? ", altivec" : "",
13370 (TARGET_VSX
) ? ", vsx" : "");
13372 V2SI_type_node
= build_vector_type (intSI_type_node
, 2);
13373 V2SF_type_node
= build_vector_type (float_type_node
, 2);
13374 V2DI_type_node
= build_vector_type (intDI_type_node
, 2);
13375 V2DF_type_node
= build_vector_type (double_type_node
, 2);
13376 V4HI_type_node
= build_vector_type (intHI_type_node
, 4);
13377 V4SI_type_node
= build_vector_type (intSI_type_node
, 4);
13378 V4SF_type_node
= build_vector_type (float_type_node
, 4);
13379 V8HI_type_node
= build_vector_type (intHI_type_node
, 8);
13380 V16QI_type_node
= build_vector_type (intQI_type_node
, 16);
13382 unsigned_V16QI_type_node
= build_vector_type (unsigned_intQI_type_node
, 16);
13383 unsigned_V8HI_type_node
= build_vector_type (unsigned_intHI_type_node
, 8);
13384 unsigned_V4SI_type_node
= build_vector_type (unsigned_intSI_type_node
, 4);
13385 unsigned_V2DI_type_node
= build_vector_type (unsigned_intDI_type_node
, 2);
13387 opaque_V2SF_type_node
= build_opaque_vector_type (float_type_node
, 2);
13388 opaque_V2SI_type_node
= build_opaque_vector_type (intSI_type_node
, 2);
13389 opaque_p_V2SI_type_node
= build_pointer_type (opaque_V2SI_type_node
);
13390 opaque_V4SI_type_node
= build_opaque_vector_type (intSI_type_node
, 4);
13392 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
13393 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
13394 'vector unsigned short'. */
13396 bool_char_type_node
= build_distinct_type_copy (unsigned_intQI_type_node
);
13397 bool_short_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13398 bool_int_type_node
= build_distinct_type_copy (unsigned_intSI_type_node
);
13399 bool_long_type_node
= build_distinct_type_copy (unsigned_intDI_type_node
);
13400 pixel_type_node
= build_distinct_type_copy (unsigned_intHI_type_node
);
13402 long_integer_type_internal_node
= long_integer_type_node
;
13403 long_unsigned_type_internal_node
= long_unsigned_type_node
;
13404 long_long_integer_type_internal_node
= long_long_integer_type_node
;
13405 long_long_unsigned_type_internal_node
= long_long_unsigned_type_node
;
13406 intQI_type_internal_node
= intQI_type_node
;
13407 uintQI_type_internal_node
= unsigned_intQI_type_node
;
13408 intHI_type_internal_node
= intHI_type_node
;
13409 uintHI_type_internal_node
= unsigned_intHI_type_node
;
13410 intSI_type_internal_node
= intSI_type_node
;
13411 uintSI_type_internal_node
= unsigned_intSI_type_node
;
13412 intDI_type_internal_node
= intDI_type_node
;
13413 uintDI_type_internal_node
= unsigned_intDI_type_node
;
13414 float_type_internal_node
= float_type_node
;
13415 double_type_internal_node
= double_type_node
;
13416 void_type_internal_node
= void_type_node
;
13418 /* Initialize the modes for builtin_function_type, mapping a machine mode to
13420 builtin_mode_to_type
[QImode
][0] = integer_type_node
;
13421 builtin_mode_to_type
[HImode
][0] = integer_type_node
;
13422 builtin_mode_to_type
[SImode
][0] = intSI_type_node
;
13423 builtin_mode_to_type
[SImode
][1] = unsigned_intSI_type_node
;
13424 builtin_mode_to_type
[DImode
][0] = intDI_type_node
;
13425 builtin_mode_to_type
[DImode
][1] = unsigned_intDI_type_node
;
13426 builtin_mode_to_type
[SFmode
][0] = float_type_node
;
13427 builtin_mode_to_type
[DFmode
][0] = double_type_node
;
13428 builtin_mode_to_type
[V2SImode
][0] = V2SI_type_node
;
13429 builtin_mode_to_type
[V2SFmode
][0] = V2SF_type_node
;
13430 builtin_mode_to_type
[V2DImode
][0] = V2DI_type_node
;
13431 builtin_mode_to_type
[V2DImode
][1] = unsigned_V2DI_type_node
;
13432 builtin_mode_to_type
[V2DFmode
][0] = V2DF_type_node
;
13433 builtin_mode_to_type
[V4HImode
][0] = V4HI_type_node
;
13434 builtin_mode_to_type
[V4SImode
][0] = V4SI_type_node
;
13435 builtin_mode_to_type
[V4SImode
][1] = unsigned_V4SI_type_node
;
13436 builtin_mode_to_type
[V4SFmode
][0] = V4SF_type_node
;
13437 builtin_mode_to_type
[V8HImode
][0] = V8HI_type_node
;
13438 builtin_mode_to_type
[V8HImode
][1] = unsigned_V8HI_type_node
;
13439 builtin_mode_to_type
[V16QImode
][0] = V16QI_type_node
;
13440 builtin_mode_to_type
[V16QImode
][1] = unsigned_V16QI_type_node
;
13442 tdecl
= add_builtin_type ("__bool char", bool_char_type_node
);
13443 TYPE_NAME (bool_char_type_node
) = tdecl
;
13445 tdecl
= add_builtin_type ("__bool short", bool_short_type_node
);
13446 TYPE_NAME (bool_short_type_node
) = tdecl
;
13448 tdecl
= add_builtin_type ("__bool int", bool_int_type_node
);
13449 TYPE_NAME (bool_int_type_node
) = tdecl
;
13451 tdecl
= add_builtin_type ("__pixel", pixel_type_node
);
13452 TYPE_NAME (pixel_type_node
) = tdecl
;
13454 bool_V16QI_type_node
= build_vector_type (bool_char_type_node
, 16);
13455 bool_V8HI_type_node
= build_vector_type (bool_short_type_node
, 8);
13456 bool_V4SI_type_node
= build_vector_type (bool_int_type_node
, 4);
13457 bool_V2DI_type_node
= build_vector_type (bool_long_type_node
, 2);
13458 pixel_V8HI_type_node
= build_vector_type (pixel_type_node
, 8);
13460 tdecl
= add_builtin_type ("__vector unsigned char", unsigned_V16QI_type_node
);
13461 TYPE_NAME (unsigned_V16QI_type_node
) = tdecl
;
13463 tdecl
= add_builtin_type ("__vector signed char", V16QI_type_node
);
13464 TYPE_NAME (V16QI_type_node
) = tdecl
;
13466 tdecl
= add_builtin_type ("__vector __bool char", bool_V16QI_type_node
);
13467 TYPE_NAME ( bool_V16QI_type_node
) = tdecl
;
13469 tdecl
= add_builtin_type ("__vector unsigned short", unsigned_V8HI_type_node
);
13470 TYPE_NAME (unsigned_V8HI_type_node
) = tdecl
;
13472 tdecl
= add_builtin_type ("__vector signed short", V8HI_type_node
);
13473 TYPE_NAME (V8HI_type_node
) = tdecl
;
13475 tdecl
= add_builtin_type ("__vector __bool short", bool_V8HI_type_node
);
13476 TYPE_NAME (bool_V8HI_type_node
) = tdecl
;
13478 tdecl
= add_builtin_type ("__vector unsigned int", unsigned_V4SI_type_node
);
13479 TYPE_NAME (unsigned_V4SI_type_node
) = tdecl
;
13481 tdecl
= add_builtin_type ("__vector signed int", V4SI_type_node
);
13482 TYPE_NAME (V4SI_type_node
) = tdecl
;
13484 tdecl
= add_builtin_type ("__vector __bool int", bool_V4SI_type_node
);
13485 TYPE_NAME (bool_V4SI_type_node
) = tdecl
;
13487 tdecl
= add_builtin_type ("__vector float", V4SF_type_node
);
13488 TYPE_NAME (V4SF_type_node
) = tdecl
;
13490 tdecl
= add_builtin_type ("__vector __pixel", pixel_V8HI_type_node
);
13491 TYPE_NAME (pixel_V8HI_type_node
) = tdecl
;
13493 tdecl
= add_builtin_type ("__vector double", V2DF_type_node
);
13494 TYPE_NAME (V2DF_type_node
) = tdecl
;
13496 tdecl
= add_builtin_type ("__vector long", V2DI_type_node
);
13497 TYPE_NAME (V2DI_type_node
) = tdecl
;
13499 tdecl
= add_builtin_type ("__vector unsigned long", unsigned_V2DI_type_node
);
13500 TYPE_NAME (unsigned_V2DI_type_node
) = tdecl
;
13502 tdecl
= add_builtin_type ("__vector __bool long", bool_V2DI_type_node
);
13503 TYPE_NAME (bool_V2DI_type_node
) = tdecl
;
13505 /* Paired and SPE builtins are only available if you build a compiler with
13506 the appropriate options, so only create those builtins with the
13507 appropriate compiler option. Create Altivec and VSX builtins on machines
13508 with at least the general purpose extensions (970 and newer) to allow the
13509 use of the target attribute. */
13510 if (TARGET_PAIRED_FLOAT
)
13511 paired_init_builtins ();
13513 spe_init_builtins ();
13514 if (TARGET_EXTRA_BUILTINS
)
13515 altivec_init_builtins ();
13517 htm_init_builtins ();
13519 if (TARGET_EXTRA_BUILTINS
|| TARGET_SPE
|| TARGET_PAIRED_FLOAT
)
13520 rs6000_common_init_builtins ();
13522 ftype
= builtin_function_type (DFmode
, DFmode
, DFmode
, VOIDmode
,
13523 RS6000_BUILTIN_RECIP
, "__builtin_recipdiv");
13524 def_builtin ("__builtin_recipdiv", ftype
, RS6000_BUILTIN_RECIP
);
13526 ftype
= builtin_function_type (SFmode
, SFmode
, SFmode
, VOIDmode
,
13527 RS6000_BUILTIN_RECIPF
, "__builtin_recipdivf");
13528 def_builtin ("__builtin_recipdivf", ftype
, RS6000_BUILTIN_RECIPF
);
13530 ftype
= builtin_function_type (DFmode
, DFmode
, VOIDmode
, VOIDmode
,
13531 RS6000_BUILTIN_RSQRT
, "__builtin_rsqrt");
13532 def_builtin ("__builtin_rsqrt", ftype
, RS6000_BUILTIN_RSQRT
);
13534 ftype
= builtin_function_type (SFmode
, SFmode
, VOIDmode
, VOIDmode
,
13535 RS6000_BUILTIN_RSQRTF
, "__builtin_rsqrtf");
13536 def_builtin ("__builtin_rsqrtf", ftype
, RS6000_BUILTIN_RSQRTF
);
13538 mode
= (TARGET_64BIT
) ? DImode
: SImode
;
13539 ftype
= builtin_function_type (mode
, mode
, mode
, VOIDmode
,
13540 POWER7_BUILTIN_BPERMD
, "__builtin_bpermd");
13541 def_builtin ("__builtin_bpermd", ftype
, POWER7_BUILTIN_BPERMD
);
13543 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13545 def_builtin ("__builtin_ppc_get_timebase", ftype
, RS6000_BUILTIN_GET_TB
);
13548 ftype
= build_function_type_list (unsigned_intDI_type_node
,
13551 ftype
= build_function_type_list (unsigned_intSI_type_node
,
13553 def_builtin ("__builtin_ppc_mftb", ftype
, RS6000_BUILTIN_MFTB
);
13556 /* AIX libm provides clog as __clog. */
13557 if ((tdecl
= builtin_decl_explicit (BUILT_IN_CLOG
)) != NULL_TREE
)
13558 set_user_assembler_name (tdecl
, "__clog");
13561 #ifdef SUBTARGET_INIT_BUILTINS
13562 SUBTARGET_INIT_BUILTINS
;
13566 /* Returns the rs6000 builtin decl for CODE. */
13569 rs6000_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
13571 HOST_WIDE_INT fnmask
;
13573 if (code
>= RS6000_BUILTIN_COUNT
)
13574 return error_mark_node
;
13576 fnmask
= rs6000_builtin_info
[code
].mask
;
13577 if ((fnmask
& rs6000_builtin_mask
) != fnmask
)
13579 rs6000_invalid_builtin ((enum rs6000_builtins
)code
);
13580 return error_mark_node
;
13583 return rs6000_builtin_decls
[code
];
13587 spe_init_builtins (void)
13589 tree puint_type_node
= build_pointer_type (unsigned_type_node
);
13590 tree pushort_type_node
= build_pointer_type (short_unsigned_type_node
);
13591 const struct builtin_description
*d
;
13594 tree v2si_ftype_4_v2si
13595 = build_function_type_list (opaque_V2SI_type_node
,
13596 opaque_V2SI_type_node
,
13597 opaque_V2SI_type_node
,
13598 opaque_V2SI_type_node
,
13599 opaque_V2SI_type_node
,
13602 tree v2sf_ftype_4_v2sf
13603 = build_function_type_list (opaque_V2SF_type_node
,
13604 opaque_V2SF_type_node
,
13605 opaque_V2SF_type_node
,
13606 opaque_V2SF_type_node
,
13607 opaque_V2SF_type_node
,
13610 tree int_ftype_int_v2si_v2si
13611 = build_function_type_list (integer_type_node
,
13613 opaque_V2SI_type_node
,
13614 opaque_V2SI_type_node
,
13617 tree int_ftype_int_v2sf_v2sf
13618 = build_function_type_list (integer_type_node
,
13620 opaque_V2SF_type_node
,
13621 opaque_V2SF_type_node
,
13624 tree void_ftype_v2si_puint_int
13625 = build_function_type_list (void_type_node
,
13626 opaque_V2SI_type_node
,
13631 tree void_ftype_v2si_puint_char
13632 = build_function_type_list (void_type_node
,
13633 opaque_V2SI_type_node
,
13638 tree void_ftype_v2si_pv2si_int
13639 = build_function_type_list (void_type_node
,
13640 opaque_V2SI_type_node
,
13641 opaque_p_V2SI_type_node
,
13645 tree void_ftype_v2si_pv2si_char
13646 = build_function_type_list (void_type_node
,
13647 opaque_V2SI_type_node
,
13648 opaque_p_V2SI_type_node
,
13652 tree void_ftype_int
13653 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
13655 tree int_ftype_void
13656 = build_function_type_list (integer_type_node
, NULL_TREE
);
13658 tree v2si_ftype_pv2si_int
13659 = build_function_type_list (opaque_V2SI_type_node
,
13660 opaque_p_V2SI_type_node
,
13664 tree v2si_ftype_puint_int
13665 = build_function_type_list (opaque_V2SI_type_node
,
13670 tree v2si_ftype_pushort_int
13671 = build_function_type_list (opaque_V2SI_type_node
,
13676 tree v2si_ftype_signed_char
13677 = build_function_type_list (opaque_V2SI_type_node
,
13678 signed_char_type_node
,
13681 add_builtin_type ("__ev64_opaque__", opaque_V2SI_type_node
);
13683 /* Initialize irregular SPE builtins. */
13685 def_builtin ("__builtin_spe_mtspefscr", void_ftype_int
, SPE_BUILTIN_MTSPEFSCR
);
13686 def_builtin ("__builtin_spe_mfspefscr", int_ftype_void
, SPE_BUILTIN_MFSPEFSCR
);
13687 def_builtin ("__builtin_spe_evstddx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDDX
);
13688 def_builtin ("__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDHX
);
13689 def_builtin ("__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int
, SPE_BUILTIN_EVSTDWX
);
13690 def_builtin ("__builtin_spe_evstwhex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHEX
);
13691 def_builtin ("__builtin_spe_evstwhox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWHOX
);
13692 def_builtin ("__builtin_spe_evstwwex", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWEX
);
13693 def_builtin ("__builtin_spe_evstwwox", void_ftype_v2si_puint_int
, SPE_BUILTIN_EVSTWWOX
);
13694 def_builtin ("__builtin_spe_evstdd", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDD
);
13695 def_builtin ("__builtin_spe_evstdh", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDH
);
13696 def_builtin ("__builtin_spe_evstdw", void_ftype_v2si_pv2si_char
, SPE_BUILTIN_EVSTDW
);
13697 def_builtin ("__builtin_spe_evstwhe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHE
);
13698 def_builtin ("__builtin_spe_evstwho", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWHO
);
13699 def_builtin ("__builtin_spe_evstwwe", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWE
);
13700 def_builtin ("__builtin_spe_evstwwo", void_ftype_v2si_puint_char
, SPE_BUILTIN_EVSTWWO
);
13701 def_builtin ("__builtin_spe_evsplatfi", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATFI
);
13702 def_builtin ("__builtin_spe_evsplati", v2si_ftype_signed_char
, SPE_BUILTIN_EVSPLATI
);
13705 def_builtin ("__builtin_spe_evlddx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDDX
);
13706 def_builtin ("__builtin_spe_evldwx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDWX
);
13707 def_builtin ("__builtin_spe_evldhx", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDHX
);
13708 def_builtin ("__builtin_spe_evlwhex", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHEX
);
13709 def_builtin ("__builtin_spe_evlwhoux", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOUX
);
13710 def_builtin ("__builtin_spe_evlwhosx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOSX
);
13711 def_builtin ("__builtin_spe_evlwwsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLATX
);
13712 def_builtin ("__builtin_spe_evlwhsplatx", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLATX
);
13713 def_builtin ("__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLATX
);
13714 def_builtin ("__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLATX
);
13715 def_builtin ("__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLATX
);
13716 def_builtin ("__builtin_spe_evldd", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDD
);
13717 def_builtin ("__builtin_spe_evldw", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDW
);
13718 def_builtin ("__builtin_spe_evldh", v2si_ftype_pv2si_int
, SPE_BUILTIN_EVLDH
);
13719 def_builtin ("__builtin_spe_evlhhesplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHESPLAT
);
13720 def_builtin ("__builtin_spe_evlhhossplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOSSPLAT
);
13721 def_builtin ("__builtin_spe_evlhhousplat", v2si_ftype_pushort_int
, SPE_BUILTIN_EVLHHOUSPLAT
);
13722 def_builtin ("__builtin_spe_evlwhe", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHE
);
13723 def_builtin ("__builtin_spe_evlwhos", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOS
);
13724 def_builtin ("__builtin_spe_evlwhou", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHOU
);
13725 def_builtin ("__builtin_spe_evlwhsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWHSPLAT
);
13726 def_builtin ("__builtin_spe_evlwwsplat", v2si_ftype_puint_int
, SPE_BUILTIN_EVLWWSPLAT
);
13729 d
= bdesc_spe_predicates
;
13730 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_predicates
); ++i
, d
++)
13734 switch (insn_data
[d
->icode
].operand
[1].mode
)
13737 type
= int_ftype_int_v2si_v2si
;
13740 type
= int_ftype_int_v2sf_v2sf
;
13743 gcc_unreachable ();
13746 def_builtin (d
->name
, type
, d
->code
);
13749 /* Evsel predicates. */
13750 d
= bdesc_spe_evsel
;
13751 for (i
= 0; i
< ARRAY_SIZE (bdesc_spe_evsel
); ++i
, d
++)
13755 switch (insn_data
[d
->icode
].operand
[1].mode
)
13758 type
= v2si_ftype_4_v2si
;
13761 type
= v2sf_ftype_4_v2sf
;
13764 gcc_unreachable ();
13767 def_builtin (d
->name
, type
, d
->code
);
13772 paired_init_builtins (void)
13774 const struct builtin_description
*d
;
13777 tree int_ftype_int_v2sf_v2sf
13778 = build_function_type_list (integer_type_node
,
13783 tree pcfloat_type_node
=
13784 build_pointer_type (build_qualified_type
13785 (float_type_node
, TYPE_QUAL_CONST
));
13787 tree v2sf_ftype_long_pcfloat
= build_function_type_list (V2SF_type_node
,
13788 long_integer_type_node
,
13791 tree void_ftype_v2sf_long_pcfloat
=
13792 build_function_type_list (void_type_node
,
13794 long_integer_type_node
,
13799 def_builtin ("__builtin_paired_lx", v2sf_ftype_long_pcfloat
,
13800 PAIRED_BUILTIN_LX
);
13803 def_builtin ("__builtin_paired_stx", void_ftype_v2sf_long_pcfloat
,
13804 PAIRED_BUILTIN_STX
);
13807 d
= bdesc_paired_preds
;
13808 for (i
= 0; i
< ARRAY_SIZE (bdesc_paired_preds
); ++i
, d
++)
13812 if (TARGET_DEBUG_BUILTIN
)
13813 fprintf (stderr
, "paired pred #%d, insn = %s [%d], mode = %s\n",
13814 (int)i
, get_insn_name (d
->icode
), (int)d
->icode
,
13815 GET_MODE_NAME (insn_data
[d
->icode
].operand
[1].mode
));
13817 switch (insn_data
[d
->icode
].operand
[1].mode
)
13820 type
= int_ftype_int_v2sf_v2sf
;
13823 gcc_unreachable ();
13826 def_builtin (d
->name
, type
, d
->code
);
13831 altivec_init_builtins (void)
13833 const struct builtin_description
*d
;
13838 tree pvoid_type_node
= build_pointer_type (void_type_node
);
13840 tree pcvoid_type_node
13841 = build_pointer_type (build_qualified_type (void_type_node
,
13844 tree int_ftype_opaque
13845 = build_function_type_list (integer_type_node
,
13846 opaque_V4SI_type_node
, NULL_TREE
);
13847 tree opaque_ftype_opaque
13848 = build_function_type_list (integer_type_node
, NULL_TREE
);
13849 tree opaque_ftype_opaque_int
13850 = build_function_type_list (opaque_V4SI_type_node
,
13851 opaque_V4SI_type_node
, integer_type_node
, NULL_TREE
);
13852 tree opaque_ftype_opaque_opaque_int
13853 = build_function_type_list (opaque_V4SI_type_node
,
13854 opaque_V4SI_type_node
, opaque_V4SI_type_node
,
13855 integer_type_node
, NULL_TREE
);
13856 tree int_ftype_int_opaque_opaque
13857 = build_function_type_list (integer_type_node
,
13858 integer_type_node
, opaque_V4SI_type_node
,
13859 opaque_V4SI_type_node
, NULL_TREE
);
13860 tree int_ftype_int_v4si_v4si
13861 = build_function_type_list (integer_type_node
,
13862 integer_type_node
, V4SI_type_node
,
13863 V4SI_type_node
, NULL_TREE
);
13864 tree int_ftype_int_v2di_v2di
13865 = build_function_type_list (integer_type_node
,
13866 integer_type_node
, V2DI_type_node
,
13867 V2DI_type_node
, NULL_TREE
);
13868 tree void_ftype_v4si
13869 = build_function_type_list (void_type_node
, V4SI_type_node
, NULL_TREE
);
13870 tree v8hi_ftype_void
13871 = build_function_type_list (V8HI_type_node
, NULL_TREE
);
13872 tree void_ftype_void
13873 = build_function_type_list (void_type_node
, NULL_TREE
);
13874 tree void_ftype_int
13875 = build_function_type_list (void_type_node
, integer_type_node
, NULL_TREE
);
13877 tree opaque_ftype_long_pcvoid
13878 = build_function_type_list (opaque_V4SI_type_node
,
13879 long_integer_type_node
, pcvoid_type_node
,
13881 tree v16qi_ftype_long_pcvoid
13882 = build_function_type_list (V16QI_type_node
,
13883 long_integer_type_node
, pcvoid_type_node
,
13885 tree v8hi_ftype_long_pcvoid
13886 = build_function_type_list (V8HI_type_node
,
13887 long_integer_type_node
, pcvoid_type_node
,
13889 tree v4si_ftype_long_pcvoid
13890 = build_function_type_list (V4SI_type_node
,
13891 long_integer_type_node
, pcvoid_type_node
,
13893 tree v4sf_ftype_long_pcvoid
13894 = build_function_type_list (V4SF_type_node
,
13895 long_integer_type_node
, pcvoid_type_node
,
13897 tree v2df_ftype_long_pcvoid
13898 = build_function_type_list (V2DF_type_node
,
13899 long_integer_type_node
, pcvoid_type_node
,
13901 tree v2di_ftype_long_pcvoid
13902 = build_function_type_list (V2DI_type_node
,
13903 long_integer_type_node
, pcvoid_type_node
,
13906 tree void_ftype_opaque_long_pvoid
13907 = build_function_type_list (void_type_node
,
13908 opaque_V4SI_type_node
, long_integer_type_node
,
13909 pvoid_type_node
, NULL_TREE
);
13910 tree void_ftype_v4si_long_pvoid
13911 = build_function_type_list (void_type_node
,
13912 V4SI_type_node
, long_integer_type_node
,
13913 pvoid_type_node
, NULL_TREE
);
13914 tree void_ftype_v16qi_long_pvoid
13915 = build_function_type_list (void_type_node
,
13916 V16QI_type_node
, long_integer_type_node
,
13917 pvoid_type_node
, NULL_TREE
);
13918 tree void_ftype_v8hi_long_pvoid
13919 = build_function_type_list (void_type_node
,
13920 V8HI_type_node
, long_integer_type_node
,
13921 pvoid_type_node
, NULL_TREE
);
13922 tree void_ftype_v4sf_long_pvoid
13923 = build_function_type_list (void_type_node
,
13924 V4SF_type_node
, long_integer_type_node
,
13925 pvoid_type_node
, NULL_TREE
);
13926 tree void_ftype_v2df_long_pvoid
13927 = build_function_type_list (void_type_node
,
13928 V2DF_type_node
, long_integer_type_node
,
13929 pvoid_type_node
, NULL_TREE
);
13930 tree void_ftype_v2di_long_pvoid
13931 = build_function_type_list (void_type_node
,
13932 V2DI_type_node
, long_integer_type_node
,
13933 pvoid_type_node
, NULL_TREE
);
13934 tree int_ftype_int_v8hi_v8hi
13935 = build_function_type_list (integer_type_node
,
13936 integer_type_node
, V8HI_type_node
,
13937 V8HI_type_node
, NULL_TREE
);
13938 tree int_ftype_int_v16qi_v16qi
13939 = build_function_type_list (integer_type_node
,
13940 integer_type_node
, V16QI_type_node
,
13941 V16QI_type_node
, NULL_TREE
);
13942 tree int_ftype_int_v4sf_v4sf
13943 = build_function_type_list (integer_type_node
,
13944 integer_type_node
, V4SF_type_node
,
13945 V4SF_type_node
, NULL_TREE
);
13946 tree int_ftype_int_v2df_v2df
13947 = build_function_type_list (integer_type_node
,
13948 integer_type_node
, V2DF_type_node
,
13949 V2DF_type_node
, NULL_TREE
);
13950 tree v2di_ftype_v2di
13951 = build_function_type_list (V2DI_type_node
, V2DI_type_node
, NULL_TREE
);
13952 tree v4si_ftype_v4si
13953 = build_function_type_list (V4SI_type_node
, V4SI_type_node
, NULL_TREE
);
13954 tree v8hi_ftype_v8hi
13955 = build_function_type_list (V8HI_type_node
, V8HI_type_node
, NULL_TREE
);
13956 tree v16qi_ftype_v16qi
13957 = build_function_type_list (V16QI_type_node
, V16QI_type_node
, NULL_TREE
);
13958 tree v4sf_ftype_v4sf
13959 = build_function_type_list (V4SF_type_node
, V4SF_type_node
, NULL_TREE
);
13960 tree v2df_ftype_v2df
13961 = build_function_type_list (V2DF_type_node
, V2DF_type_node
, NULL_TREE
);
13962 tree void_ftype_pcvoid_int_int
13963 = build_function_type_list (void_type_node
,
13964 pcvoid_type_node
, integer_type_node
,
13965 integer_type_node
, NULL_TREE
);
13967 def_builtin ("__builtin_altivec_mtvscr", void_ftype_v4si
, ALTIVEC_BUILTIN_MTVSCR
);
13968 def_builtin ("__builtin_altivec_mfvscr", v8hi_ftype_void
, ALTIVEC_BUILTIN_MFVSCR
);
13969 def_builtin ("__builtin_altivec_dssall", void_ftype_void
, ALTIVEC_BUILTIN_DSSALL
);
13970 def_builtin ("__builtin_altivec_dss", void_ftype_int
, ALTIVEC_BUILTIN_DSS
);
13971 def_builtin ("__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSL
);
13972 def_builtin ("__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVSR
);
13973 def_builtin ("__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEBX
);
13974 def_builtin ("__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEHX
);
13975 def_builtin ("__builtin_altivec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVEWX
);
13976 def_builtin ("__builtin_altivec_lvxl", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVXL
);
13977 def_builtin ("__builtin_altivec_lvx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVX
);
13978 def_builtin ("__builtin_altivec_stvx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVX
);
13979 def_builtin ("__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVEWX
);
13980 def_builtin ("__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid
, ALTIVEC_BUILTIN_STVXL
);
13981 def_builtin ("__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVEBX
);
13982 def_builtin ("__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid
, ALTIVEC_BUILTIN_STVEHX
);
13983 def_builtin ("__builtin_vec_ld", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LD
);
13984 def_builtin ("__builtin_vec_lde", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDE
);
13985 def_builtin ("__builtin_vec_ldl", opaque_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LDL
);
13986 def_builtin ("__builtin_vec_lvsl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSL
);
13987 def_builtin ("__builtin_vec_lvsr", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVSR
);
13988 def_builtin ("__builtin_vec_lvebx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEBX
);
13989 def_builtin ("__builtin_vec_lvehx", v8hi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEHX
);
13990 def_builtin ("__builtin_vec_lvewx", v4si_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVEWX
);
13991 def_builtin ("__builtin_vec_st", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_ST
);
13992 def_builtin ("__builtin_vec_ste", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STE
);
13993 def_builtin ("__builtin_vec_stl", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STL
);
13994 def_builtin ("__builtin_vec_stvewx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEWX
);
13995 def_builtin ("__builtin_vec_stvebx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEBX
);
13996 def_builtin ("__builtin_vec_stvehx", void_ftype_opaque_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVEHX
);
13998 def_builtin ("__builtin_vsx_lxvd2x_v2df", v2df_ftype_long_pcvoid
,
13999 VSX_BUILTIN_LXVD2X_V2DF
);
14000 def_builtin ("__builtin_vsx_lxvd2x_v2di", v2di_ftype_long_pcvoid
,
14001 VSX_BUILTIN_LXVD2X_V2DI
);
14002 def_builtin ("__builtin_vsx_lxvw4x_v4sf", v4sf_ftype_long_pcvoid
,
14003 VSX_BUILTIN_LXVW4X_V4SF
);
14004 def_builtin ("__builtin_vsx_lxvw4x_v4si", v4si_ftype_long_pcvoid
,
14005 VSX_BUILTIN_LXVW4X_V4SI
);
14006 def_builtin ("__builtin_vsx_lxvw4x_v8hi", v8hi_ftype_long_pcvoid
,
14007 VSX_BUILTIN_LXVW4X_V8HI
);
14008 def_builtin ("__builtin_vsx_lxvw4x_v16qi", v16qi_ftype_long_pcvoid
,
14009 VSX_BUILTIN_LXVW4X_V16QI
);
14010 def_builtin ("__builtin_vsx_stxvd2x_v2df", void_ftype_v2df_long_pvoid
,
14011 VSX_BUILTIN_STXVD2X_V2DF
);
14012 def_builtin ("__builtin_vsx_stxvd2x_v2di", void_ftype_v2di_long_pvoid
,
14013 VSX_BUILTIN_STXVD2X_V2DI
);
14014 def_builtin ("__builtin_vsx_stxvw4x_v4sf", void_ftype_v4sf_long_pvoid
,
14015 VSX_BUILTIN_STXVW4X_V4SF
);
14016 def_builtin ("__builtin_vsx_stxvw4x_v4si", void_ftype_v4si_long_pvoid
,
14017 VSX_BUILTIN_STXVW4X_V4SI
);
14018 def_builtin ("__builtin_vsx_stxvw4x_v8hi", void_ftype_v8hi_long_pvoid
,
14019 VSX_BUILTIN_STXVW4X_V8HI
);
14020 def_builtin ("__builtin_vsx_stxvw4x_v16qi", void_ftype_v16qi_long_pvoid
,
14021 VSX_BUILTIN_STXVW4X_V16QI
);
14022 def_builtin ("__builtin_vec_vsx_ld", opaque_ftype_long_pcvoid
,
14023 VSX_BUILTIN_VEC_LD
);
14024 def_builtin ("__builtin_vec_vsx_st", void_ftype_opaque_long_pvoid
,
14025 VSX_BUILTIN_VEC_ST
);
14027 def_builtin ("__builtin_vec_step", int_ftype_opaque
, ALTIVEC_BUILTIN_VEC_STEP
);
14028 def_builtin ("__builtin_vec_splats", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_SPLATS
);
14029 def_builtin ("__builtin_vec_promote", opaque_ftype_opaque
, ALTIVEC_BUILTIN_VEC_PROMOTE
);
14031 def_builtin ("__builtin_vec_sld", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_SLD
);
14032 def_builtin ("__builtin_vec_splat", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_SPLAT
);
14033 def_builtin ("__builtin_vec_extract", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_EXTRACT
);
14034 def_builtin ("__builtin_vec_insert", opaque_ftype_opaque_opaque_int
, ALTIVEC_BUILTIN_VEC_INSERT
);
14035 def_builtin ("__builtin_vec_vspltw", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTW
);
14036 def_builtin ("__builtin_vec_vsplth", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTH
);
14037 def_builtin ("__builtin_vec_vspltb", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VSPLTB
);
14038 def_builtin ("__builtin_vec_ctf", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTF
);
14039 def_builtin ("__builtin_vec_vcfsx", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFSX
);
14040 def_builtin ("__builtin_vec_vcfux", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_VCFUX
);
14041 def_builtin ("__builtin_vec_cts", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTS
);
14042 def_builtin ("__builtin_vec_ctu", opaque_ftype_opaque_int
, ALTIVEC_BUILTIN_VEC_CTU
);
14044 /* Cell builtins. */
14045 def_builtin ("__builtin_altivec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLX
);
14046 def_builtin ("__builtin_altivec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVLXL
);
14047 def_builtin ("__builtin_altivec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRX
);
14048 def_builtin ("__builtin_altivec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_LVRXL
);
14050 def_builtin ("__builtin_vec_lvlx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLX
);
14051 def_builtin ("__builtin_vec_lvlxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVLXL
);
14052 def_builtin ("__builtin_vec_lvrx", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRX
);
14053 def_builtin ("__builtin_vec_lvrxl", v16qi_ftype_long_pcvoid
, ALTIVEC_BUILTIN_VEC_LVRXL
);
14055 def_builtin ("__builtin_altivec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLX
);
14056 def_builtin ("__builtin_altivec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVLXL
);
14057 def_builtin ("__builtin_altivec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRX
);
14058 def_builtin ("__builtin_altivec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_STVRXL
);
14060 def_builtin ("__builtin_vec_stvlx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLX
);
14061 def_builtin ("__builtin_vec_stvlxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVLXL
);
14062 def_builtin ("__builtin_vec_stvrx", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRX
);
14063 def_builtin ("__builtin_vec_stvrxl", void_ftype_v16qi_long_pvoid
, ALTIVEC_BUILTIN_VEC_STVRXL
);
14065 /* Add the DST variants. */
14067 for (i
= 0; i
< ARRAY_SIZE (bdesc_dst
); i
++, d
++)
14068 def_builtin (d
->name
, void_ftype_pcvoid_int_int
, d
->code
);
14070 /* Initialize the predicates. */
14071 d
= bdesc_altivec_preds
;
14072 for (i
= 0; i
< ARRAY_SIZE (bdesc_altivec_preds
); i
++, d
++)
14074 enum machine_mode mode1
;
14077 if (rs6000_overloaded_builtin_p (d
->code
))
14080 mode1
= insn_data
[d
->icode
].operand
[1].mode
;
14085 type
= int_ftype_int_opaque_opaque
;
14088 type
= int_ftype_int_v2di_v2di
;
14091 type
= int_ftype_int_v4si_v4si
;
14094 type
= int_ftype_int_v8hi_v8hi
;
14097 type
= int_ftype_int_v16qi_v16qi
;
14100 type
= int_ftype_int_v4sf_v4sf
;
14103 type
= int_ftype_int_v2df_v2df
;
14106 gcc_unreachable ();
14109 def_builtin (d
->name
, type
, d
->code
);
14112 /* Initialize the abs* operators. */
14114 for (i
= 0; i
< ARRAY_SIZE (bdesc_abs
); i
++, d
++)
14116 enum machine_mode mode0
;
14119 mode0
= insn_data
[d
->icode
].operand
[0].mode
;
14124 type
= v2di_ftype_v2di
;
14127 type
= v4si_ftype_v4si
;
14130 type
= v8hi_ftype_v8hi
;
14133 type
= v16qi_ftype_v16qi
;
14136 type
= v4sf_ftype_v4sf
;
14139 type
= v2df_ftype_v2df
;
14142 gcc_unreachable ();
14145 def_builtin (d
->name
, type
, d
->code
);
14148 /* Initialize target builtin that implements
14149 targetm.vectorize.builtin_mask_for_load. */
14151 decl
= add_builtin_function ("__builtin_altivec_mask_for_load",
14152 v16qi_ftype_long_pcvoid
,
14153 ALTIVEC_BUILTIN_MASK_FOR_LOAD
,
14154 BUILT_IN_MD
, NULL
, NULL_TREE
);
14155 TREE_READONLY (decl
) = 1;
14156 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
14157 altivec_builtin_mask_for_load
= decl
;
14159 /* Access to the vec_init patterns. */
14160 ftype
= build_function_type_list (V4SI_type_node
, integer_type_node
,
14161 integer_type_node
, integer_type_node
,
14162 integer_type_node
, NULL_TREE
);
14163 def_builtin ("__builtin_vec_init_v4si", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SI
);
14165 ftype
= build_function_type_list (V8HI_type_node
, short_integer_type_node
,
14166 short_integer_type_node
,
14167 short_integer_type_node
,
14168 short_integer_type_node
,
14169 short_integer_type_node
,
14170 short_integer_type_node
,
14171 short_integer_type_node
,
14172 short_integer_type_node
, NULL_TREE
);
14173 def_builtin ("__builtin_vec_init_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V8HI
);
14175 ftype
= build_function_type_list (V16QI_type_node
, char_type_node
,
14176 char_type_node
, char_type_node
,
14177 char_type_node
, char_type_node
,
14178 char_type_node
, char_type_node
,
14179 char_type_node
, char_type_node
,
14180 char_type_node
, char_type_node
,
14181 char_type_node
, char_type_node
,
14182 char_type_node
, char_type_node
,
14183 char_type_node
, NULL_TREE
);
14184 def_builtin ("__builtin_vec_init_v16qi", ftype
,
14185 ALTIVEC_BUILTIN_VEC_INIT_V16QI
);
14187 ftype
= build_function_type_list (V4SF_type_node
, float_type_node
,
14188 float_type_node
, float_type_node
,
14189 float_type_node
, NULL_TREE
);
14190 def_builtin ("__builtin_vec_init_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_INIT_V4SF
);
14192 /* VSX builtins. */
14193 ftype
= build_function_type_list (V2DF_type_node
, double_type_node
,
14194 double_type_node
, NULL_TREE
);
14195 def_builtin ("__builtin_vec_init_v2df", ftype
, VSX_BUILTIN_VEC_INIT_V2DF
);
14197 ftype
= build_function_type_list (V2DI_type_node
, intDI_type_node
,
14198 intDI_type_node
, NULL_TREE
);
14199 def_builtin ("__builtin_vec_init_v2di", ftype
, VSX_BUILTIN_VEC_INIT_V2DI
);
14201 /* Access to the vec_set patterns. */
14202 ftype
= build_function_type_list (V4SI_type_node
, V4SI_type_node
,
14204 integer_type_node
, NULL_TREE
);
14205 def_builtin ("__builtin_vec_set_v4si", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SI
);
14207 ftype
= build_function_type_list (V8HI_type_node
, V8HI_type_node
,
14209 integer_type_node
, NULL_TREE
);
14210 def_builtin ("__builtin_vec_set_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V8HI
);
14212 ftype
= build_function_type_list (V16QI_type_node
, V16QI_type_node
,
14214 integer_type_node
, NULL_TREE
);
14215 def_builtin ("__builtin_vec_set_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_SET_V16QI
);
14217 ftype
= build_function_type_list (V4SF_type_node
, V4SF_type_node
,
14219 integer_type_node
, NULL_TREE
);
14220 def_builtin ("__builtin_vec_set_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_SET_V4SF
);
14222 ftype
= build_function_type_list (V2DF_type_node
, V2DF_type_node
,
14224 integer_type_node
, NULL_TREE
);
14225 def_builtin ("__builtin_vec_set_v2df", ftype
, VSX_BUILTIN_VEC_SET_V2DF
);
14227 ftype
= build_function_type_list (V2DI_type_node
, V2DI_type_node
,
14229 integer_type_node
, NULL_TREE
);
14230 def_builtin ("__builtin_vec_set_v2di", ftype
, VSX_BUILTIN_VEC_SET_V2DI
);
14232 /* Access to the vec_extract patterns. */
14233 ftype
= build_function_type_list (intSI_type_node
, V4SI_type_node
,
14234 integer_type_node
, NULL_TREE
);
14235 def_builtin ("__builtin_vec_ext_v4si", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SI
);
14237 ftype
= build_function_type_list (intHI_type_node
, V8HI_type_node
,
14238 integer_type_node
, NULL_TREE
);
14239 def_builtin ("__builtin_vec_ext_v8hi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V8HI
);
14241 ftype
= build_function_type_list (intQI_type_node
, V16QI_type_node
,
14242 integer_type_node
, NULL_TREE
);
14243 def_builtin ("__builtin_vec_ext_v16qi", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V16QI
);
14245 ftype
= build_function_type_list (float_type_node
, V4SF_type_node
,
14246 integer_type_node
, NULL_TREE
);
14247 def_builtin ("__builtin_vec_ext_v4sf", ftype
, ALTIVEC_BUILTIN_VEC_EXT_V4SF
);
14249 ftype
= build_function_type_list (double_type_node
, V2DF_type_node
,
14250 integer_type_node
, NULL_TREE
);
14251 def_builtin ("__builtin_vec_ext_v2df", ftype
, VSX_BUILTIN_VEC_EXT_V2DF
);
14253 ftype
= build_function_type_list (intDI_type_node
, V2DI_type_node
,
14254 integer_type_node
, NULL_TREE
);
14255 def_builtin ("__builtin_vec_ext_v2di", ftype
, VSX_BUILTIN_VEC_EXT_V2DI
);
14259 htm_init_builtins (void)
14261 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14262 const struct builtin_description
*d
;
14266 for (i
= 0; i
< ARRAY_SIZE (bdesc_htm
); i
++, d
++)
14268 tree op
[MAX_HTM_OPERANDS
], type
;
14269 HOST_WIDE_INT mask
= d
->mask
;
14270 unsigned attr
= rs6000_builtin_info
[d
->code
].attr
;
14271 bool void_func
= (attr
& RS6000_BTC_VOID
);
14272 int attr_args
= (attr
& RS6000_BTC_TYPE_MASK
);
14274 tree argtype
= (attr
& RS6000_BTC_SPR
) ? long_unsigned_type_node
14275 : unsigned_type_node
;
14277 if ((mask
& builtin_mask
) != mask
)
14279 if (TARGET_DEBUG_BUILTIN
)
14280 fprintf (stderr
, "htm_builtin, skip binary %s\n", d
->name
);
14286 if (TARGET_DEBUG_BUILTIN
)
14287 fprintf (stderr
, "htm_builtin, bdesc_htm[%ld] no name\n",
14288 (long unsigned) i
);
14292 op
[nopnds
++] = (void_func
) ? void_type_node
: argtype
;
14294 if (attr_args
== RS6000_BTC_UNARY
)
14295 op
[nopnds
++] = argtype
;
14296 else if (attr_args
== RS6000_BTC_BINARY
)
14298 op
[nopnds
++] = argtype
;
14299 op
[nopnds
++] = argtype
;
14301 else if (attr_args
== RS6000_BTC_TERNARY
)
14303 op
[nopnds
++] = argtype
;
14304 op
[nopnds
++] = argtype
;
14305 op
[nopnds
++] = argtype
;
14311 type
= build_function_type_list (op
[0], NULL_TREE
);
14314 type
= build_function_type_list (op
[0], op
[1], NULL_TREE
);
14317 type
= build_function_type_list (op
[0], op
[1], op
[2], NULL_TREE
);
14320 type
= build_function_type_list (op
[0], op
[1], op
[2], op
[3],
14324 gcc_unreachable ();
14327 def_builtin (d
->name
, type
, d
->code
);
14331 /* Hash function for builtin functions with up to 3 arguments and a return
14334 builtin_hash_function (const void *hash_entry
)
14338 const struct builtin_hash_struct
*bh
=
14339 (const struct builtin_hash_struct
*) hash_entry
;
14341 for (i
= 0; i
< 4; i
++)
14343 ret
= (ret
* (unsigned)MAX_MACHINE_MODE
) + ((unsigned)bh
->mode
[i
]);
14344 ret
= (ret
* 2) + bh
->uns_p
[i
];
14350 /* Compare builtin hash entries H1 and H2 for equivalence. */
14352 builtin_hash_eq (const void *h1
, const void *h2
)
14354 const struct builtin_hash_struct
*p1
= (const struct builtin_hash_struct
*) h1
;
14355 const struct builtin_hash_struct
*p2
= (const struct builtin_hash_struct
*) h2
;
14357 return ((p1
->mode
[0] == p2
->mode
[0])
14358 && (p1
->mode
[1] == p2
->mode
[1])
14359 && (p1
->mode
[2] == p2
->mode
[2])
14360 && (p1
->mode
[3] == p2
->mode
[3])
14361 && (p1
->uns_p
[0] == p2
->uns_p
[0])
14362 && (p1
->uns_p
[1] == p2
->uns_p
[1])
14363 && (p1
->uns_p
[2] == p2
->uns_p
[2])
14364 && (p1
->uns_p
[3] == p2
->uns_p
[3]));
14367 /* Map types for builtin functions with an explicit return type and up to 3
14368 arguments. Functions with fewer than 3 arguments use VOIDmode as the type
14369 of the argument. */
14371 builtin_function_type (enum machine_mode mode_ret
, enum machine_mode mode_arg0
,
14372 enum machine_mode mode_arg1
, enum machine_mode mode_arg2
,
14373 enum rs6000_builtins builtin
, const char *name
)
14375 struct builtin_hash_struct h
;
14376 struct builtin_hash_struct
*h2
;
14380 tree ret_type
= NULL_TREE
;
14381 tree arg_type
[3] = { NULL_TREE
, NULL_TREE
, NULL_TREE
};
14383 /* Create builtin_hash_table. */
14384 if (builtin_hash_table
== NULL
)
14385 builtin_hash_table
= htab_create_ggc (1500, builtin_hash_function
,
14386 builtin_hash_eq
, NULL
);
14388 h
.type
= NULL_TREE
;
14389 h
.mode
[0] = mode_ret
;
14390 h
.mode
[1] = mode_arg0
;
14391 h
.mode
[2] = mode_arg1
;
14392 h
.mode
[3] = mode_arg2
;
14398 /* If the builtin is a type that produces unsigned results or takes unsigned
14399 arguments, and it is returned as a decl for the vectorizer (such as
14400 widening multiplies, permute), make sure the arguments and return value
14401 are type correct. */
14404 /* unsigned 1 argument functions. */
14405 case CRYPTO_BUILTIN_VSBOX
:
14406 case P8V_BUILTIN_VGBBD
:
14411 /* unsigned 2 argument functions. */
14412 case ALTIVEC_BUILTIN_VMULEUB_UNS
:
14413 case ALTIVEC_BUILTIN_VMULEUH_UNS
:
14414 case ALTIVEC_BUILTIN_VMULOUB_UNS
:
14415 case ALTIVEC_BUILTIN_VMULOUH_UNS
:
14416 case CRYPTO_BUILTIN_VCIPHER
:
14417 case CRYPTO_BUILTIN_VCIPHERLAST
:
14418 case CRYPTO_BUILTIN_VNCIPHER
:
14419 case CRYPTO_BUILTIN_VNCIPHERLAST
:
14420 case CRYPTO_BUILTIN_VPMSUMB
:
14421 case CRYPTO_BUILTIN_VPMSUMH
:
14422 case CRYPTO_BUILTIN_VPMSUMW
:
14423 case CRYPTO_BUILTIN_VPMSUMD
:
14424 case CRYPTO_BUILTIN_VPMSUM
:
14430 /* unsigned 3 argument functions. */
14431 case ALTIVEC_BUILTIN_VPERM_16QI_UNS
:
14432 case ALTIVEC_BUILTIN_VPERM_8HI_UNS
:
14433 case ALTIVEC_BUILTIN_VPERM_4SI_UNS
:
14434 case ALTIVEC_BUILTIN_VPERM_2DI_UNS
:
14435 case ALTIVEC_BUILTIN_VSEL_16QI_UNS
:
14436 case ALTIVEC_BUILTIN_VSEL_8HI_UNS
:
14437 case ALTIVEC_BUILTIN_VSEL_4SI_UNS
:
14438 case ALTIVEC_BUILTIN_VSEL_2DI_UNS
:
14439 case VSX_BUILTIN_VPERM_16QI_UNS
:
14440 case VSX_BUILTIN_VPERM_8HI_UNS
:
14441 case VSX_BUILTIN_VPERM_4SI_UNS
:
14442 case VSX_BUILTIN_VPERM_2DI_UNS
:
14443 case VSX_BUILTIN_XXSEL_16QI_UNS
:
14444 case VSX_BUILTIN_XXSEL_8HI_UNS
:
14445 case VSX_BUILTIN_XXSEL_4SI_UNS
:
14446 case VSX_BUILTIN_XXSEL_2DI_UNS
:
14447 case CRYPTO_BUILTIN_VPERMXOR
:
14448 case CRYPTO_BUILTIN_VPERMXOR_V2DI
:
14449 case CRYPTO_BUILTIN_VPERMXOR_V4SI
:
14450 case CRYPTO_BUILTIN_VPERMXOR_V8HI
:
14451 case CRYPTO_BUILTIN_VPERMXOR_V16QI
:
14452 case CRYPTO_BUILTIN_VSHASIGMAW
:
14453 case CRYPTO_BUILTIN_VSHASIGMAD
:
14454 case CRYPTO_BUILTIN_VSHASIGMA
:
14461 /* signed permute functions with unsigned char mask. */
14462 case ALTIVEC_BUILTIN_VPERM_16QI
:
14463 case ALTIVEC_BUILTIN_VPERM_8HI
:
14464 case ALTIVEC_BUILTIN_VPERM_4SI
:
14465 case ALTIVEC_BUILTIN_VPERM_4SF
:
14466 case ALTIVEC_BUILTIN_VPERM_2DI
:
14467 case ALTIVEC_BUILTIN_VPERM_2DF
:
14468 case VSX_BUILTIN_VPERM_16QI
:
14469 case VSX_BUILTIN_VPERM_8HI
:
14470 case VSX_BUILTIN_VPERM_4SI
:
14471 case VSX_BUILTIN_VPERM_4SF
:
14472 case VSX_BUILTIN_VPERM_2DI
:
14473 case VSX_BUILTIN_VPERM_2DF
:
14477 /* unsigned args, signed return. */
14478 case VSX_BUILTIN_XVCVUXDDP_UNS
:
14479 case ALTIVEC_BUILTIN_UNSFLOAT_V4SI_V4SF
:
14483 /* signed args, unsigned return. */
14484 case VSX_BUILTIN_XVCVDPUXDS_UNS
:
14485 case ALTIVEC_BUILTIN_FIXUNS_V4SF_V4SI
:
14493 /* Figure out how many args are present. */
14494 while (num_args
> 0 && h
.mode
[num_args
] == VOIDmode
)
14498 fatal_error ("internal error: builtin function %s had no type", name
);
14500 ret_type
= builtin_mode_to_type
[h
.mode
[0]][h
.uns_p
[0]];
14501 if (!ret_type
&& h
.uns_p
[0])
14502 ret_type
= builtin_mode_to_type
[h
.mode
[0]][0];
14505 fatal_error ("internal error: builtin function %s had an unexpected "
14506 "return type %s", name
, GET_MODE_NAME (h
.mode
[0]));
14508 for (i
= 0; i
< (int) ARRAY_SIZE (arg_type
); i
++)
14509 arg_type
[i
] = NULL_TREE
;
14511 for (i
= 0; i
< num_args
; i
++)
14513 int m
= (int) h
.mode
[i
+1];
14514 int uns_p
= h
.uns_p
[i
+1];
14516 arg_type
[i
] = builtin_mode_to_type
[m
][uns_p
];
14517 if (!arg_type
[i
] && uns_p
)
14518 arg_type
[i
] = builtin_mode_to_type
[m
][0];
14521 fatal_error ("internal error: builtin function %s, argument %d "
14522 "had unexpected argument type %s", name
, i
,
14523 GET_MODE_NAME (m
));
14526 found
= htab_find_slot (builtin_hash_table
, &h
, INSERT
);
14527 if (*found
== NULL
)
14529 h2
= ggc_alloc_builtin_hash_struct ();
14531 *found
= (void *)h2
;
14533 h2
->type
= build_function_type_list (ret_type
, arg_type
[0], arg_type
[1],
14534 arg_type
[2], NULL_TREE
);
14537 return ((struct builtin_hash_struct
*)(*found
))->type
;
14541 rs6000_common_init_builtins (void)
14543 const struct builtin_description
*d
;
14546 tree opaque_ftype_opaque
= NULL_TREE
;
14547 tree opaque_ftype_opaque_opaque
= NULL_TREE
;
14548 tree opaque_ftype_opaque_opaque_opaque
= NULL_TREE
;
14549 tree v2si_ftype_qi
= NULL_TREE
;
14550 tree v2si_ftype_v2si_qi
= NULL_TREE
;
14551 tree v2si_ftype_int_qi
= NULL_TREE
;
14552 HOST_WIDE_INT builtin_mask
= rs6000_builtin_mask
;
14554 if (!TARGET_PAIRED_FLOAT
)
14556 builtin_mode_to_type
[V2SImode
][0] = opaque_V2SI_type_node
;
14557 builtin_mode_to_type
[V2SFmode
][0] = opaque_V2SF_type_node
;
14560 /* Paired and SPE builtins are only available if you build a compiler with
14561 the appropriate options, so only create those builtins with the
14562 appropriate compiler option. Create Altivec and VSX builtins on machines
14563 with at least the general purpose extensions (970 and newer) to allow the
14564 use of the target attribute.. */
14566 if (TARGET_EXTRA_BUILTINS
)
14567 builtin_mask
|= RS6000_BTM_COMMON
;
14569 /* Add the ternary operators. */
14571 for (i
= 0; i
< ARRAY_SIZE (bdesc_3arg
); i
++, d
++)
14574 HOST_WIDE_INT mask
= d
->mask
;
14576 if ((mask
& builtin_mask
) != mask
)
14578 if (TARGET_DEBUG_BUILTIN
)
14579 fprintf (stderr
, "rs6000_builtin, skip ternary %s\n", d
->name
);
14583 if (rs6000_overloaded_builtin_p (d
->code
))
14585 if (! (type
= opaque_ftype_opaque_opaque_opaque
))
14586 type
= opaque_ftype_opaque_opaque_opaque
14587 = build_function_type_list (opaque_V4SI_type_node
,
14588 opaque_V4SI_type_node
,
14589 opaque_V4SI_type_node
,
14590 opaque_V4SI_type_node
,
14595 enum insn_code icode
= d
->icode
;
14598 if (TARGET_DEBUG_BUILTIN
)
14599 fprintf (stderr
, "rs6000_builtin, bdesc_3arg[%ld] no name\n",
14605 if (icode
== CODE_FOR_nothing
)
14607 if (TARGET_DEBUG_BUILTIN
)
14608 fprintf (stderr
, "rs6000_builtin, skip ternary %s (no code)\n",
14614 type
= builtin_function_type (insn_data
[icode
].operand
[0].mode
,
14615 insn_data
[icode
].operand
[1].mode
,
14616 insn_data
[icode
].operand
[2].mode
,
14617 insn_data
[icode
].operand
[3].mode
,
14621 def_builtin (d
->name
, type
, d
->code
);
14624 /* Add the binary operators. */
14626 for (i
= 0; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
14628 enum machine_mode mode0
, mode1
, mode2
;
14630 HOST_WIDE_INT mask
= d
->mask
;
14632 if ((mask
& builtin_mask
) != mask
)
14634 if (TARGET_DEBUG_BUILTIN
)
14635 fprintf (stderr
, "rs6000_builtin, skip binary %s\n", d
->name
);
14639 if (rs6000_overloaded_builtin_p (d
->code
))
14641 if (! (type
= opaque_ftype_opaque_opaque
))
14642 type
= opaque_ftype_opaque_opaque
14643 = build_function_type_list (opaque_V4SI_type_node
,
14644 opaque_V4SI_type_node
,
14645 opaque_V4SI_type_node
,
14650 enum insn_code icode
= d
->icode
;
14653 if (TARGET_DEBUG_BUILTIN
)
14654 fprintf (stderr
, "rs6000_builtin, bdesc_2arg[%ld] no name\n",
14660 if (icode
== CODE_FOR_nothing
)
14662 if (TARGET_DEBUG_BUILTIN
)
14663 fprintf (stderr
, "rs6000_builtin, skip binary %s (no code)\n",
14669 mode0
= insn_data
[icode
].operand
[0].mode
;
14670 mode1
= insn_data
[icode
].operand
[1].mode
;
14671 mode2
= insn_data
[icode
].operand
[2].mode
;
14673 if (mode0
== V2SImode
&& mode1
== V2SImode
&& mode2
== QImode
)
14675 if (! (type
= v2si_ftype_v2si_qi
))
14676 type
= v2si_ftype_v2si_qi
14677 = build_function_type_list (opaque_V2SI_type_node
,
14678 opaque_V2SI_type_node
,
14683 else if (mode0
== V2SImode
&& GET_MODE_CLASS (mode1
) == MODE_INT
14684 && mode2
== QImode
)
14686 if (! (type
= v2si_ftype_int_qi
))
14687 type
= v2si_ftype_int_qi
14688 = build_function_type_list (opaque_V2SI_type_node
,
14695 type
= builtin_function_type (mode0
, mode1
, mode2
, VOIDmode
,
14699 def_builtin (d
->name
, type
, d
->code
);
14702 /* Add the simple unary operators. */
14704 for (i
= 0; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
14706 enum machine_mode mode0
, mode1
;
14708 HOST_WIDE_INT mask
= d
->mask
;
14710 if ((mask
& builtin_mask
) != mask
)
14712 if (TARGET_DEBUG_BUILTIN
)
14713 fprintf (stderr
, "rs6000_builtin, skip unary %s\n", d
->name
);
14717 if (rs6000_overloaded_builtin_p (d
->code
))
14719 if (! (type
= opaque_ftype_opaque
))
14720 type
= opaque_ftype_opaque
14721 = build_function_type_list (opaque_V4SI_type_node
,
14722 opaque_V4SI_type_node
,
14727 enum insn_code icode
= d
->icode
;
14730 if (TARGET_DEBUG_BUILTIN
)
14731 fprintf (stderr
, "rs6000_builtin, bdesc_1arg[%ld] no name\n",
14737 if (icode
== CODE_FOR_nothing
)
14739 if (TARGET_DEBUG_BUILTIN
)
14740 fprintf (stderr
, "rs6000_builtin, skip unary %s (no code)\n",
14746 mode0
= insn_data
[icode
].operand
[0].mode
;
14747 mode1
= insn_data
[icode
].operand
[1].mode
;
14749 if (mode0
== V2SImode
&& mode1
== QImode
)
14751 if (! (type
= v2si_ftype_qi
))
14752 type
= v2si_ftype_qi
14753 = build_function_type_list (opaque_V2SI_type_node
,
14759 type
= builtin_function_type (mode0
, mode1
, VOIDmode
, VOIDmode
,
14763 def_builtin (d
->name
, type
, d
->code
);
14768 rs6000_init_libfuncs (void)
14770 if (!TARGET_IEEEQUAD
)
14771 /* AIX/Darwin/64-bit Linux quad floating point routines. */
14772 if (!TARGET_XL_COMPAT
)
14774 set_optab_libfunc (add_optab
, TFmode
, "__gcc_qadd");
14775 set_optab_libfunc (sub_optab
, TFmode
, "__gcc_qsub");
14776 set_optab_libfunc (smul_optab
, TFmode
, "__gcc_qmul");
14777 set_optab_libfunc (sdiv_optab
, TFmode
, "__gcc_qdiv");
14779 if (!(TARGET_HARD_FLOAT
&& (TARGET_FPRS
|| TARGET_E500_DOUBLE
)))
14781 set_optab_libfunc (neg_optab
, TFmode
, "__gcc_qneg");
14782 set_optab_libfunc (eq_optab
, TFmode
, "__gcc_qeq");
14783 set_optab_libfunc (ne_optab
, TFmode
, "__gcc_qne");
14784 set_optab_libfunc (gt_optab
, TFmode
, "__gcc_qgt");
14785 set_optab_libfunc (ge_optab
, TFmode
, "__gcc_qge");
14786 set_optab_libfunc (lt_optab
, TFmode
, "__gcc_qlt");
14787 set_optab_libfunc (le_optab
, TFmode
, "__gcc_qle");
14789 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "__gcc_stoq");
14790 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "__gcc_dtoq");
14791 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "__gcc_qtos");
14792 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "__gcc_qtod");
14793 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "__gcc_qtoi");
14794 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "__gcc_qtou");
14795 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "__gcc_itoq");
14796 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "__gcc_utoq");
14799 if (!(TARGET_HARD_FLOAT
&& TARGET_FPRS
))
14800 set_optab_libfunc (unord_optab
, TFmode
, "__gcc_qunord");
14804 set_optab_libfunc (add_optab
, TFmode
, "_xlqadd");
14805 set_optab_libfunc (sub_optab
, TFmode
, "_xlqsub");
14806 set_optab_libfunc (smul_optab
, TFmode
, "_xlqmul");
14807 set_optab_libfunc (sdiv_optab
, TFmode
, "_xlqdiv");
14811 /* 32-bit SVR4 quad floating point routines. */
14813 set_optab_libfunc (add_optab
, TFmode
, "_q_add");
14814 set_optab_libfunc (sub_optab
, TFmode
, "_q_sub");
14815 set_optab_libfunc (neg_optab
, TFmode
, "_q_neg");
14816 set_optab_libfunc (smul_optab
, TFmode
, "_q_mul");
14817 set_optab_libfunc (sdiv_optab
, TFmode
, "_q_div");
14818 if (TARGET_PPC_GPOPT
)
14819 set_optab_libfunc (sqrt_optab
, TFmode
, "_q_sqrt");
14821 set_optab_libfunc (eq_optab
, TFmode
, "_q_feq");
14822 set_optab_libfunc (ne_optab
, TFmode
, "_q_fne");
14823 set_optab_libfunc (gt_optab
, TFmode
, "_q_fgt");
14824 set_optab_libfunc (ge_optab
, TFmode
, "_q_fge");
14825 set_optab_libfunc (lt_optab
, TFmode
, "_q_flt");
14826 set_optab_libfunc (le_optab
, TFmode
, "_q_fle");
14828 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_q_stoq");
14829 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_q_dtoq");
14830 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_q_qtos");
14831 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_q_qtod");
14832 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_q_qtoi");
14833 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_q_qtou");
14834 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_q_itoq");
14835 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_q_utoq");
14840 /* Expand a block clear operation, and return 1 if successful. Return 0
14841 if we should let the compiler generate normal code.
14843 operands[0] is the destination
14844 operands[1] is the length
14845 operands[3] is the alignment */
14848 expand_block_clear (rtx operands
[])
14850 rtx orig_dest
= operands
[0];
14851 rtx bytes_rtx
= operands
[1];
14852 rtx align_rtx
= operands
[3];
14853 bool constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14854 HOST_WIDE_INT align
;
14855 HOST_WIDE_INT bytes
;
14860 /* If this is not a fixed size move, just call memcpy */
14864 /* This must be a fixed size alignment */
14865 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14866 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14868 /* Anything to clear? */
14869 bytes
= INTVAL (bytes_rtx
);
14873 /* Use the builtin memset after a point, to avoid huge code bloat.
14874 When optimize_size, avoid any significant code bloat; calling
14875 memset is about 4 instructions, so allow for one instruction to
14876 load zero and three to do clearing. */
14877 if (TARGET_ALTIVEC
&& align
>= 128)
14879 else if (TARGET_POWERPC64
&& align
>= 32)
14881 else if (TARGET_SPE
&& align
>= 64)
14886 if (optimize_size
&& bytes
> 3 * clear_step
)
14888 if (! optimize_size
&& bytes
> 8 * clear_step
)
14891 for (offset
= 0; bytes
> 0; offset
+= clear_bytes
, bytes
-= clear_bytes
)
14893 enum machine_mode mode
= BLKmode
;
14896 if (bytes
>= 16 && TARGET_ALTIVEC
&& align
>= 128)
14901 else if (bytes
>= 8 && TARGET_SPE
&& align
>= 64)
14906 else if (bytes
>= 8 && TARGET_POWERPC64
14907 /* 64-bit loads and stores require word-aligned
14909 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
14914 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
14915 { /* move 4 bytes */
14919 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
14920 { /* move 2 bytes */
14924 else /* move 1 byte at a time */
14930 dest
= adjust_address (orig_dest
, mode
, offset
);
14932 emit_move_insn (dest
, CONST0_RTX (mode
));
14939 /* Expand a block move operation, and return 1 if successful. Return 0
14940 if we should let the compiler generate normal code.
14942 operands[0] is the destination
14943 operands[1] is the source
14944 operands[2] is the length
14945 operands[3] is the alignment */
14947 #define MAX_MOVE_REG 4
14950 expand_block_move (rtx operands
[])
14952 rtx orig_dest
= operands
[0];
14953 rtx orig_src
= operands
[1];
14954 rtx bytes_rtx
= operands
[2];
14955 rtx align_rtx
= operands
[3];
14956 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
14961 rtx stores
[MAX_MOVE_REG
];
14964 /* If this is not a fixed size move, just call memcpy */
14968 /* This must be a fixed size alignment */
14969 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
14970 align
= INTVAL (align_rtx
) * BITS_PER_UNIT
;
14972 /* Anything to move? */
14973 bytes
= INTVAL (bytes_rtx
);
14977 if (bytes
> rs6000_block_move_inline_limit
)
14980 for (offset
= 0; bytes
> 0; offset
+= move_bytes
, bytes
-= move_bytes
)
14983 rtx (*movmemsi
) (rtx
, rtx
, rtx
, rtx
);
14984 rtx (*mov
) (rtx
, rtx
);
14986 enum machine_mode mode
= BLKmode
;
14989 /* Altivec first, since it will be faster than a string move
14990 when it applies, and usually not significantly larger. */
14991 if (TARGET_ALTIVEC
&& bytes
>= 16 && align
>= 128)
14995 gen_func
.mov
= gen_movv4si
;
14997 else if (TARGET_SPE
&& bytes
>= 8 && align
>= 64)
15001 gen_func
.mov
= gen_movv2si
;
15003 else if (TARGET_STRING
15004 && bytes
> 24 /* move up to 32 bytes at a time */
15010 && ! fixed_regs
[10]
15011 && ! fixed_regs
[11]
15012 && ! fixed_regs
[12])
15014 move_bytes
= (bytes
> 32) ? 32 : bytes
;
15015 gen_func
.movmemsi
= gen_movmemsi_8reg
;
15017 else if (TARGET_STRING
15018 && bytes
> 16 /* move up to 24 bytes at a time */
15024 && ! fixed_regs
[10])
15026 move_bytes
= (bytes
> 24) ? 24 : bytes
;
15027 gen_func
.movmemsi
= gen_movmemsi_6reg
;
15029 else if (TARGET_STRING
15030 && bytes
> 8 /* move up to 16 bytes at a time */
15034 && ! fixed_regs
[8])
15036 move_bytes
= (bytes
> 16) ? 16 : bytes
;
15037 gen_func
.movmemsi
= gen_movmemsi_4reg
;
15039 else if (bytes
>= 8 && TARGET_POWERPC64
15040 /* 64-bit loads and stores require word-aligned
15042 && (align
>= 64 || (!STRICT_ALIGNMENT
&& align
>= 32)))
15046 gen_func
.mov
= gen_movdi
;
15048 else if (TARGET_STRING
&& bytes
> 4 && !TARGET_POWERPC64
)
15049 { /* move up to 8 bytes at a time */
15050 move_bytes
= (bytes
> 8) ? 8 : bytes
;
15051 gen_func
.movmemsi
= gen_movmemsi_2reg
;
15053 else if (bytes
>= 4 && (align
>= 32 || !STRICT_ALIGNMENT
))
15054 { /* move 4 bytes */
15057 gen_func
.mov
= gen_movsi
;
15059 else if (bytes
>= 2 && (align
>= 16 || !STRICT_ALIGNMENT
))
15060 { /* move 2 bytes */
15063 gen_func
.mov
= gen_movhi
;
15065 else if (TARGET_STRING
&& bytes
> 1)
15066 { /* move up to 4 bytes at a time */
15067 move_bytes
= (bytes
> 4) ? 4 : bytes
;
15068 gen_func
.movmemsi
= gen_movmemsi_1reg
;
15070 else /* move 1 byte at a time */
15074 gen_func
.mov
= gen_movqi
;
15077 src
= adjust_address (orig_src
, mode
, offset
);
15078 dest
= adjust_address (orig_dest
, mode
, offset
);
15080 if (mode
!= BLKmode
)
15082 rtx tmp_reg
= gen_reg_rtx (mode
);
15084 emit_insn ((*gen_func
.mov
) (tmp_reg
, src
));
15085 stores
[num_reg
++] = (*gen_func
.mov
) (dest
, tmp_reg
);
15088 if (mode
== BLKmode
|| num_reg
>= MAX_MOVE_REG
|| bytes
== move_bytes
)
15091 for (i
= 0; i
< num_reg
; i
++)
15092 emit_insn (stores
[i
]);
15096 if (mode
== BLKmode
)
15098 /* Move the address into scratch registers. The movmemsi
15099 patterns require zero offset. */
15100 if (!REG_P (XEXP (src
, 0)))
15102 rtx src_reg
= copy_addr_to_reg (XEXP (src
, 0));
15103 src
= replace_equiv_address (src
, src_reg
);
15105 set_mem_size (src
, move_bytes
);
15107 if (!REG_P (XEXP (dest
, 0)))
15109 rtx dest_reg
= copy_addr_to_reg (XEXP (dest
, 0));
15110 dest
= replace_equiv_address (dest
, dest_reg
);
15112 set_mem_size (dest
, move_bytes
);
15114 emit_insn ((*gen_func
.movmemsi
) (dest
, src
,
15115 GEN_INT (move_bytes
& 31),
15124 /* Return a string to perform a load_multiple operation.
15125 operands[0] is the vector.
15126 operands[1] is the source address.
15127 operands[2] is the first destination register. */
15130 rs6000_output_load_multiple (rtx operands
[3])
15132 /* We have to handle the case where the pseudo used to contain the address
15133 is assigned to one of the output registers. */
15135 int words
= XVECLEN (operands
[0], 0);
15138 if (XVECLEN (operands
[0], 0) == 1)
15139 return "lwz %2,0(%1)";
15141 for (i
= 0; i
< words
; i
++)
15142 if (refers_to_regno_p (REGNO (operands
[2]) + i
,
15143 REGNO (operands
[2]) + i
+ 1, operands
[1], 0))
15147 xop
[0] = GEN_INT (4 * (words
-1));
15148 xop
[1] = operands
[1];
15149 xop
[2] = operands
[2];
15150 output_asm_insn ("lswi %2,%1,%0\n\tlwz %1,%0(%1)", xop
);
15155 xop
[0] = GEN_INT (4 * (words
-1));
15156 xop
[1] = operands
[1];
15157 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
15158 output_asm_insn ("addi %1,%1,4\n\tlswi %2,%1,%0\n\tlwz %1,-4(%1)", xop
);
15163 for (j
= 0; j
< words
; j
++)
15166 xop
[0] = GEN_INT (j
* 4);
15167 xop
[1] = operands
[1];
15168 xop
[2] = gen_rtx_REG (SImode
, REGNO (operands
[2]) + j
);
15169 output_asm_insn ("lwz %2,%0(%1)", xop
);
15171 xop
[0] = GEN_INT (i
* 4);
15172 xop
[1] = operands
[1];
15173 output_asm_insn ("lwz %1,%0(%1)", xop
);
15178 return "lswi %2,%1,%N0";
15182 /* A validation routine: say whether CODE, a condition code, and MODE
15183 match. The other alternatives either don't make sense or should
15184 never be generated. */
15187 validate_condition_mode (enum rtx_code code
, enum machine_mode mode
)
15189 gcc_assert ((GET_RTX_CLASS (code
) == RTX_COMPARE
15190 || GET_RTX_CLASS (code
) == RTX_COMM_COMPARE
)
15191 && GET_MODE_CLASS (mode
) == MODE_CC
);
15193 /* These don't make sense. */
15194 gcc_assert ((code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
)
15195 || mode
!= CCUNSmode
);
15197 gcc_assert ((code
!= GTU
&& code
!= LTU
&& code
!= GEU
&& code
!= LEU
)
15198 || mode
== CCUNSmode
);
15200 gcc_assert (mode
== CCFPmode
15201 || (code
!= ORDERED
&& code
!= UNORDERED
15202 && code
!= UNEQ
&& code
!= LTGT
15203 && code
!= UNGT
&& code
!= UNLT
15204 && code
!= UNGE
&& code
!= UNLE
));
15206 /* These should never be generated except for
15207 flag_finite_math_only. */
15208 gcc_assert (mode
!= CCFPmode
15209 || flag_finite_math_only
15210 || (code
!= LE
&& code
!= GE
15211 && code
!= UNEQ
&& code
!= LTGT
15212 && code
!= UNGT
&& code
!= UNLT
));
15214 /* These are invalid; the information is not there. */
15215 gcc_assert (mode
!= CCEQmode
|| code
== EQ
|| code
== NE
);
15219 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
15220 mask required to convert the result of a rotate insn into a shift
15221 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
15224 includes_lshift_p (rtx shiftop
, rtx andop
)
15226 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15228 shift_mask
<<= INTVAL (shiftop
);
15230 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15233 /* Similar, but for right shift. */
15236 includes_rshift_p (rtx shiftop
, rtx andop
)
15238 unsigned HOST_WIDE_INT shift_mask
= ~(unsigned HOST_WIDE_INT
) 0;
15240 shift_mask
>>= INTVAL (shiftop
);
15242 return (INTVAL (andop
) & 0xffffffff & ~shift_mask
) == 0;
15245 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
15246 to perform a left shift. It must have exactly SHIFTOP least
15247 significant 0's, then one or more 1's, then zero or more 0's. */
15250 includes_rldic_lshift_p (rtx shiftop
, rtx andop
)
15252 if (GET_CODE (andop
) == CONST_INT
)
15254 HOST_WIDE_INT c
, lsb
, shift_mask
;
15256 c
= INTVAL (andop
);
15257 if (c
== 0 || c
== ~0)
15261 shift_mask
<<= INTVAL (shiftop
);
15263 /* Find the least significant one bit. */
15266 /* It must coincide with the LSB of the shift mask. */
15267 if (-lsb
!= shift_mask
)
15270 /* Invert to look for the next transition (if any). */
15273 /* Remove the low group of ones (originally low group of zeros). */
15276 /* Again find the lsb, and check we have all 1's above. */
15284 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
15285 to perform a left shift. It must have SHIFTOP or more least
15286 significant 0's, with the remainder of the word 1's. */
15289 includes_rldicr_lshift_p (rtx shiftop
, rtx andop
)
15291 if (GET_CODE (andop
) == CONST_INT
)
15293 HOST_WIDE_INT c
, lsb
, shift_mask
;
15296 shift_mask
<<= INTVAL (shiftop
);
15297 c
= INTVAL (andop
);
15299 /* Find the least significant one bit. */
15302 /* It must be covered by the shift mask.
15303 This test also rejects c == 0. */
15304 if ((lsb
& shift_mask
) == 0)
15307 /* Check we have all 1's above the transition, and reject all 1's. */
15308 return c
== -lsb
&& lsb
!= 1;
15314 /* Return 1 if operands will generate a valid arguments to rlwimi
15315 instruction for insert with right shift in 64-bit mode. The mask may
15316 not start on the first bit or stop on the last bit because wrap-around
15317 effects of instruction do not correspond to semantics of RTL insn. */
15320 insvdi_rshift_rlwimi_p (rtx sizeop
, rtx startop
, rtx shiftop
)
15322 if (INTVAL (startop
) > 32
15323 && INTVAL (startop
) < 64
15324 && INTVAL (sizeop
) > 1
15325 && INTVAL (sizeop
) + INTVAL (startop
) < 64
15326 && INTVAL (shiftop
) > 0
15327 && INTVAL (sizeop
) + INTVAL (shiftop
) < 32
15328 && (64 - (INTVAL (shiftop
) & 63)) >= INTVAL (sizeop
))
15334 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
15335 for lfq and stfq insns iff the registers are hard registers. */
15338 registers_ok_for_quad_peep (rtx reg1
, rtx reg2
)
15340 /* We might have been passed a SUBREG. */
15341 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
15344 /* We might have been passed non floating point registers. */
15345 if (!FP_REGNO_P (REGNO (reg1
))
15346 || !FP_REGNO_P (REGNO (reg2
)))
15349 return (REGNO (reg1
) == REGNO (reg2
) - 1);
15352 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
15353 addr1 and addr2 must be in consecutive memory locations
15354 (addr2 == addr1 + 8). */
15357 mems_ok_for_quad_peep (rtx mem1
, rtx mem2
)
15360 unsigned int reg1
, reg2
;
15361 int offset1
, offset2
;
15363 /* The mems cannot be volatile. */
15364 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
15367 addr1
= XEXP (mem1
, 0);
15368 addr2
= XEXP (mem2
, 0);
15370 /* Extract an offset (if used) from the first addr. */
15371 if (GET_CODE (addr1
) == PLUS
)
15373 /* If not a REG, return zero. */
15374 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
15378 reg1
= REGNO (XEXP (addr1
, 0));
15379 /* The offset must be constant! */
15380 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
15382 offset1
= INTVAL (XEXP (addr1
, 1));
15385 else if (GET_CODE (addr1
) != REG
)
15389 reg1
= REGNO (addr1
);
15390 /* This was a simple (mem (reg)) expression. Offset is 0. */
15394 /* And now for the second addr. */
15395 if (GET_CODE (addr2
) == PLUS
)
15397 /* If not a REG, return zero. */
15398 if (GET_CODE (XEXP (addr2
, 0)) != REG
)
15402 reg2
= REGNO (XEXP (addr2
, 0));
15403 /* The offset must be constant. */
15404 if (GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
15406 offset2
= INTVAL (XEXP (addr2
, 1));
15409 else if (GET_CODE (addr2
) != REG
)
15413 reg2
= REGNO (addr2
);
15414 /* This was a simple (mem (reg)) expression. Offset is 0. */
15418 /* Both of these must have the same base register. */
15422 /* The offset for the second addr must be 8 more than the first addr. */
15423 if (offset2
!= offset1
+ 8)
15426 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
15433 rs6000_secondary_memory_needed_rtx (enum machine_mode mode
)
15435 static bool eliminated
= false;
15438 if (mode
!= SDmode
|| TARGET_NO_SDMODE_STACK
)
15439 ret
= assign_stack_local (mode
, GET_MODE_SIZE (mode
), 0);
15442 rtx mem
= cfun
->machine
->sdmode_stack_slot
;
15443 gcc_assert (mem
!= NULL_RTX
);
15447 mem
= eliminate_regs (mem
, VOIDmode
, NULL_RTX
);
15448 cfun
->machine
->sdmode_stack_slot
= mem
;
15454 if (TARGET_DEBUG_ADDR
)
15456 fprintf (stderr
, "\nrs6000_secondary_memory_needed_rtx, mode %s, rtx:\n",
15457 GET_MODE_NAME (mode
));
15459 fprintf (stderr
, "\tNULL_RTX\n");
15467 /* Return the mode to be used for memory when a secondary memory
15468 location is needed. For SDmode values we need to use DDmode, in
15469 all other cases we can use the same mode. */
15471 rs6000_secondary_memory_needed_mode (enum machine_mode mode
)
15473 if (mode
== SDmode
)
15479 rs6000_check_sdmode (tree
*tp
, int *walk_subtrees
, void *data ATTRIBUTE_UNUSED
)
15481 /* Don't walk into types. */
15482 if (*tp
== NULL_TREE
|| *tp
== error_mark_node
|| TYPE_P (*tp
))
15484 *walk_subtrees
= 0;
15488 switch (TREE_CODE (*tp
))
15497 case VIEW_CONVERT_EXPR
:
15498 if (TYPE_MODE (TREE_TYPE (*tp
)) == SDmode
)
15508 /* Classify a register type. Because the FMRGOW/FMRGEW instructions only work
15509 on traditional floating point registers, and the VMRGOW/VMRGEW instructions
15510 only work on the traditional altivec registers, note if an altivec register
15513 static enum rs6000_reg_type
15514 register_to_reg_type (rtx reg
, bool *is_altivec
)
15516 HOST_WIDE_INT regno
;
15517 enum reg_class rclass
;
15519 if (GET_CODE (reg
) == SUBREG
)
15520 reg
= SUBREG_REG (reg
);
15523 return NO_REG_TYPE
;
15525 regno
= REGNO (reg
);
15526 if (regno
>= FIRST_PSEUDO_REGISTER
)
15528 if (!lra_in_progress
&& !reload_in_progress
&& !reload_completed
)
15529 return PSEUDO_REG_TYPE
;
15531 regno
= true_regnum (reg
);
15532 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15533 return PSEUDO_REG_TYPE
;
15536 gcc_assert (regno
>= 0);
15538 if (is_altivec
&& ALTIVEC_REGNO_P (regno
))
15539 *is_altivec
= true;
15541 rclass
= rs6000_regno_regclass
[regno
];
15542 return reg_class_to_reg_type
[(int)rclass
];
15545 /* Helper function for rs6000_secondary_reload to return true if a move to a
15546 different register classe is really a simple move. */
15549 rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type
,
15550 enum rs6000_reg_type from_type
,
15551 enum machine_mode mode
)
15555 /* Add support for various direct moves available. In this function, we only
15556 look at cases where we don't need any extra registers, and one or more
15557 simple move insns are issued. At present, 32-bit integers are not allowed
15558 in FPR/VSX registers. Single precision binary floating is not a simple
15559 move because we need to convert to the single precision memory layout.
15560 The 4-byte SDmode can be moved. */
15561 size
= GET_MODE_SIZE (mode
);
15562 if (TARGET_DIRECT_MOVE
15563 && ((mode
== SDmode
) || (TARGET_POWERPC64
&& size
== 8))
15564 && ((to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15565 || (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15568 else if (TARGET_MFPGPR
&& TARGET_POWERPC64
&& size
== 8
15569 && ((to_type
== GPR_REG_TYPE
&& from_type
== FPR_REG_TYPE
)
15570 || (to_type
== FPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15573 else if ((size
== 4 || (TARGET_POWERPC64
&& size
== 8))
15574 && ((to_type
== GPR_REG_TYPE
&& from_type
== SPR_REG_TYPE
)
15575 || (to_type
== SPR_REG_TYPE
&& from_type
== GPR_REG_TYPE
)))
15581 /* Power8 helper function for rs6000_secondary_reload, handle all of the
15582 special direct moves that involve allocating an extra register, return the
15583 insn code of the helper function if there is such a function or
15584 CODE_FOR_nothing if not. */
15587 rs6000_secondary_reload_direct_move (enum rs6000_reg_type to_type
,
15588 enum rs6000_reg_type from_type
,
15589 enum machine_mode mode
,
15590 secondary_reload_info
*sri
,
15594 enum insn_code icode
= CODE_FOR_nothing
;
15596 int size
= GET_MODE_SIZE (mode
);
15598 if (TARGET_POWERPC64
)
15602 /* Handle moving 128-bit values from GPRs to VSX point registers on
15603 power8 when running in 64-bit mode using XXPERMDI to glue the two
15604 64-bit values back together. */
15605 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15607 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
15608 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15611 /* Handle moving 128-bit values from VSX point registers to GPRs on
15612 power8 when running in 64-bit mode using XXPERMDI to get access to the
15613 bottom 64-bit value. */
15614 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15616 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
15617 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15621 else if (mode
== SFmode
)
15623 if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15625 cost
= 3; /* xscvdpspn, mfvsrd, and. */
15626 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15629 else if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15631 cost
= 2; /* mtvsrz, xscvspdpn. */
15632 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15637 if (TARGET_POWERPC64
&& size
== 16)
15639 /* Handle moving 128-bit values from GPRs to VSX point registers on
15640 power8 when running in 64-bit mode using XXPERMDI to glue the two
15641 64-bit values back together. */
15642 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
)
15644 cost
= 3; /* 2 mtvsrd's, 1 xxpermdi. */
15645 icode
= reg_addr
[mode
].reload_vsx_gpr
;
15648 /* Handle moving 128-bit values from VSX point registers to GPRs on
15649 power8 when running in 64-bit mode using XXPERMDI to get access to the
15650 bottom 64-bit value. */
15651 else if (to_type
== GPR_REG_TYPE
&& from_type
== VSX_REG_TYPE
)
15653 cost
= 3; /* 2 mfvsrd's, 1 xxpermdi. */
15654 icode
= reg_addr
[mode
].reload_gpr_vsx
;
15658 else if (!TARGET_POWERPC64
&& size
== 8)
15660 /* Handle moving 64-bit values from GPRs to floating point registers on
15661 power8 when running in 32-bit mode using FMRGOW to glue the two 32-bit
15662 values back together. Altivec register classes must be handled
15663 specially since a different instruction is used, and the secondary
15664 reload support requires a single instruction class in the scratch
15665 register constraint. However, right now TFmode is not allowed in
15666 Altivec registers, so the pattern will never match. */
15667 if (to_type
== VSX_REG_TYPE
&& from_type
== GPR_REG_TYPE
&& !altivec_p
)
15669 cost
= 3; /* 2 mtvsrwz's, 1 fmrgow. */
15670 icode
= reg_addr
[mode
].reload_fpr_gpr
;
15674 if (icode
!= CODE_FOR_nothing
)
15679 sri
->icode
= icode
;
15680 sri
->extra_cost
= cost
;
15687 /* Return whether a move between two register classes can be done either
15688 directly (simple move) or via a pattern that uses a single extra temporary
15689 (using power8's direct move in this case. */
15692 rs6000_secondary_reload_move (enum rs6000_reg_type to_type
,
15693 enum rs6000_reg_type from_type
,
15694 enum machine_mode mode
,
15695 secondary_reload_info
*sri
,
15698 /* Fall back to load/store reloads if either type is not a register. */
15699 if (to_type
== NO_REG_TYPE
|| from_type
== NO_REG_TYPE
)
15702 /* If we haven't allocated registers yet, assume the move can be done for the
15703 standard register types. */
15704 if ((to_type
== PSEUDO_REG_TYPE
&& from_type
== PSEUDO_REG_TYPE
)
15705 || (to_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (from_type
))
15706 || (from_type
== PSEUDO_REG_TYPE
&& IS_STD_REG_TYPE (to_type
)))
15709 /* Moves to the same set of registers is a simple move for non-specialized
15711 if (to_type
== from_type
&& IS_STD_REG_TYPE (to_type
))
15714 /* Check whether a simple move can be done directly. */
15715 if (rs6000_secondary_reload_simple_move (to_type
, from_type
, mode
))
15719 sri
->icode
= CODE_FOR_nothing
;
15720 sri
->extra_cost
= 0;
15725 /* Now check if we can do it in a few steps. */
15726 return rs6000_secondary_reload_direct_move (to_type
, from_type
, mode
, sri
,
15730 /* Inform reload about cases where moving X with a mode MODE to a register in
15731 RCLASS requires an extra scratch or immediate register. Return the class
15732 needed for the immediate register.
15734 For VSX and Altivec, we may need a register to convert sp+offset into
15737 For misaligned 64-bit gpr loads and stores we need a register to
15738 convert an offset address to indirect. */
15741 rs6000_secondary_reload (bool in_p
,
15743 reg_class_t rclass_i
,
15744 enum machine_mode mode
,
15745 secondary_reload_info
*sri
)
15747 enum reg_class rclass
= (enum reg_class
) rclass_i
;
15748 reg_class_t ret
= ALL_REGS
;
15749 enum insn_code icode
;
15750 bool default_p
= false;
15752 sri
->icode
= CODE_FOR_nothing
;
15754 ? reg_addr
[mode
].reload_load
15755 : reg_addr
[mode
].reload_store
);
15757 if (REG_P (x
) || register_operand (x
, mode
))
15759 enum rs6000_reg_type to_type
= reg_class_to_reg_type
[(int)rclass
];
15760 bool altivec_p
= (rclass
== ALTIVEC_REGS
);
15761 enum rs6000_reg_type from_type
= register_to_reg_type (x
, &altivec_p
);
15765 enum rs6000_reg_type exchange
= to_type
;
15766 to_type
= from_type
;
15767 from_type
= exchange
;
15770 /* Can we do a direct move of some sort? */
15771 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
, sri
,
15774 icode
= (enum insn_code
)sri
->icode
;
15780 /* Handle vector moves with reload helper functions. */
15781 if (ret
== ALL_REGS
&& icode
!= CODE_FOR_nothing
)
15784 sri
->icode
= CODE_FOR_nothing
;
15785 sri
->extra_cost
= 0;
15787 if (GET_CODE (x
) == MEM
)
15789 rtx addr
= XEXP (x
, 0);
15791 /* Loads to and stores from gprs can do reg+offset, and wouldn't need
15792 an extra register in that case, but it would need an extra
15793 register if the addressing is reg+reg or (reg+reg)&(-16). Special
15794 case load/store quad. */
15795 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
)
15797 if (TARGET_POWERPC64
&& TARGET_QUAD_MEMORY
15798 && GET_MODE_SIZE (mode
) == 16
15799 && quad_memory_operand (x
, mode
))
15801 sri
->icode
= icode
;
15802 sri
->extra_cost
= 2;
15805 else if (!legitimate_indirect_address_p (addr
, false)
15806 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
15809 sri
->icode
= icode
;
15810 /* account for splitting the loads, and converting the
15811 address from reg+reg to reg. */
15812 sri
->extra_cost
= (((TARGET_64BIT
) ? 3 : 5)
15813 + ((GET_CODE (addr
) == AND
) ? 1 : 0));
15816 /* Allow scalar loads to/from the traditional floating point
15817 registers, even if VSX memory is set. */
15818 else if ((rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
15819 && (GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
15820 && (legitimate_indirect_address_p (addr
, false)
15821 || legitimate_indirect_address_p (addr
, false)
15822 || rs6000_legitimate_offset_address_p (mode
, addr
,
15826 /* Loads to and stores from vector registers can only do reg+reg
15827 addressing. Altivec registers can also do (reg+reg)&(-16). Allow
15828 scalar modes loading up the traditional floating point registers
15829 to use offset addresses. */
15830 else if (rclass
== VSX_REGS
|| rclass
== ALTIVEC_REGS
15831 || rclass
== FLOAT_REGS
|| rclass
== NO_REGS
)
15833 if (!VECTOR_MEM_ALTIVEC_P (mode
)
15834 && GET_CODE (addr
) == AND
15835 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
15836 && INTVAL (XEXP (addr
, 1)) == -16
15837 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
15838 || legitimate_indexed_address_p (XEXP (addr
, 0), false)))
15840 sri
->icode
= icode
;
15841 sri
->extra_cost
= ((GET_CODE (XEXP (addr
, 0)) == PLUS
)
15844 else if (!legitimate_indirect_address_p (addr
, false)
15845 && (rclass
== NO_REGS
15846 || !legitimate_indexed_address_p (addr
, false)))
15848 sri
->icode
= icode
;
15849 sri
->extra_cost
= 1;
15852 icode
= CODE_FOR_nothing
;
15854 /* Any other loads, including to pseudo registers which haven't been
15855 assigned to a register yet, default to require a scratch
15859 sri
->icode
= icode
;
15860 sri
->extra_cost
= 2;
15863 else if (REG_P (x
))
15865 int regno
= true_regnum (x
);
15867 icode
= CODE_FOR_nothing
;
15868 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
15872 enum reg_class xclass
= REGNO_REG_CLASS (regno
);
15873 enum rs6000_reg_type rtype1
= reg_class_to_reg_type
[(int)rclass
];
15874 enum rs6000_reg_type rtype2
= reg_class_to_reg_type
[(int)xclass
];
15876 /* If memory is needed, use default_secondary_reload to create the
15878 if (rtype1
!= rtype2
|| !IS_STD_REG_TYPE (rtype1
))
15887 else if (TARGET_POWERPC64
15888 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15890 && GET_MODE_SIZE (GET_MODE (x
)) >= UNITS_PER_WORD
)
15892 rtx addr
= XEXP (x
, 0);
15893 rtx off
= address_offset (addr
);
15895 if (off
!= NULL_RTX
)
15897 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15898 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15900 /* We need a secondary reload when our legitimate_address_p
15901 says the address is good (as otherwise the entire address
15902 will be reloaded), and the offset is not a multiple of
15903 four or we have an address wrap. Address wrap will only
15904 occur for LO_SUMs since legitimate_offset_address_p
15905 rejects addresses for 16-byte mems that will wrap. */
15906 if (GET_CODE (addr
) == LO_SUM
15907 ? (1 /* legitimate_address_p allows any offset for lo_sum */
15908 && ((offset
& 3) != 0
15909 || ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
))
15910 : (offset
+ 0x8000 < 0x10000 - extra
/* legitimate_address_p */
15911 && (offset
& 3) != 0))
15914 sri
->icode
= CODE_FOR_reload_di_load
;
15916 sri
->icode
= CODE_FOR_reload_di_store
;
15917 sri
->extra_cost
= 2;
15926 else if (!TARGET_POWERPC64
15927 && reg_class_to_reg_type
[(int)rclass
] == GPR_REG_TYPE
15929 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
15931 rtx addr
= XEXP (x
, 0);
15932 rtx off
= address_offset (addr
);
15934 if (off
!= NULL_RTX
)
15936 unsigned int extra
= GET_MODE_SIZE (GET_MODE (x
)) - UNITS_PER_WORD
;
15937 unsigned HOST_WIDE_INT offset
= INTVAL (off
);
15939 /* We need a secondary reload when our legitimate_address_p
15940 says the address is good (as otherwise the entire address
15941 will be reloaded), and we have a wrap.
15943 legitimate_lo_sum_address_p allows LO_SUM addresses to
15944 have any offset so test for wrap in the low 16 bits.
15946 legitimate_offset_address_p checks for the range
15947 [-0x8000,0x7fff] for mode size of 8 and [-0x8000,0x7ff7]
15948 for mode size of 16. We wrap at [0x7ffc,0x7fff] and
15949 [0x7ff4,0x7fff] respectively, so test for the
15950 intersection of these ranges, [0x7ffc,0x7fff] and
15951 [0x7ff4,0x7ff7] respectively.
15953 Note that the address we see here may have been
15954 manipulated by legitimize_reload_address. */
15955 if (GET_CODE (addr
) == LO_SUM
15956 ? ((offset
& 0xffff) ^ 0x8000) >= 0x10000 - extra
15957 : offset
- (0x8000 - extra
) < UNITS_PER_WORD
)
15960 sri
->icode
= CODE_FOR_reload_si_load
;
15962 sri
->icode
= CODE_FOR_reload_si_store
;
15963 sri
->extra_cost
= 2;
15976 ret
= default_secondary_reload (in_p
, x
, rclass
, mode
, sri
);
15978 gcc_assert (ret
!= ALL_REGS
);
15980 if (TARGET_DEBUG_ADDR
)
15983 "\nrs6000_secondary_reload, return %s, in_p = %s, rclass = %s, "
15985 reg_class_names
[ret
],
15986 in_p
? "true" : "false",
15987 reg_class_names
[rclass
],
15988 GET_MODE_NAME (mode
));
15991 fprintf (stderr
, ", default secondary reload");
15993 if (sri
->icode
!= CODE_FOR_nothing
)
15994 fprintf (stderr
, ", reload func = %s, extra cost = %d\n",
15995 insn_data
[sri
->icode
].name
, sri
->extra_cost
);
15997 fprintf (stderr
, "\n");
16005 /* Better tracing for rs6000_secondary_reload_inner. */
16008 rs6000_secondary_reload_trace (int line
, rtx reg
, rtx mem
, rtx scratch
,
16013 gcc_assert (reg
!= NULL_RTX
&& mem
!= NULL_RTX
&& scratch
!= NULL_RTX
);
16015 fprintf (stderr
, "rs6000_secondary_reload_inner:%d, type = %s\n", line
,
16016 store_p
? "store" : "load");
16019 set
= gen_rtx_SET (VOIDmode
, mem
, reg
);
16021 set
= gen_rtx_SET (VOIDmode
, reg
, mem
);
16023 clobber
= gen_rtx_CLOBBER (VOIDmode
, scratch
);
16024 debug_rtx (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
16028 rs6000_secondary_reload_fail (int line
, rtx reg
, rtx mem
, rtx scratch
,
16031 rs6000_secondary_reload_trace (line
, reg
, mem
, scratch
, store_p
);
16032 gcc_unreachable ();
16035 /* Fixup reload addresses for Altivec or VSX loads/stores to change SP+offset
16036 to SP+reg addressing. */
16039 rs6000_secondary_reload_inner (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16041 int regno
= true_regnum (reg
);
16042 enum machine_mode mode
= GET_MODE (reg
);
16043 enum reg_class rclass
;
16045 rtx and_op2
= NULL_RTX
;
16048 rtx scratch_or_premodify
= scratch
;
16052 if (TARGET_DEBUG_ADDR
)
16053 rs6000_secondary_reload_trace (__LINE__
, reg
, mem
, scratch
, store_p
);
16055 if (regno
< 0 || regno
>= FIRST_PSEUDO_REGISTER
)
16056 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16058 if (GET_CODE (mem
) != MEM
)
16059 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16061 rclass
= REGNO_REG_CLASS (regno
);
16062 addr
= XEXP (mem
, 0);
16066 /* GPRs can handle reg + small constant, all other addresses need to use
16067 the scratch register. */
16070 if (GET_CODE (addr
) == AND
)
16072 and_op2
= XEXP (addr
, 1);
16073 addr
= XEXP (addr
, 0);
16076 if (GET_CODE (addr
) == PRE_MODIFY
)
16078 scratch_or_premodify
= XEXP (addr
, 0);
16079 if (!REG_P (scratch_or_premodify
))
16080 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16082 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
16083 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16085 addr
= XEXP (addr
, 1);
16088 if (GET_CODE (addr
) == PLUS
16089 && (and_op2
!= NULL_RTX
16090 || !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16093 addr_op1
= XEXP (addr
, 0);
16094 addr_op2
= XEXP (addr
, 1);
16095 if (!legitimate_indirect_address_p (addr_op1
, false))
16096 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16098 if (!REG_P (addr_op2
)
16099 && (GET_CODE (addr_op2
) != CONST_INT
16100 || !satisfies_constraint_I (addr_op2
)))
16102 if (TARGET_DEBUG_ADDR
)
16105 "\nMove plus addr to register %s, mode = %s: ",
16106 rs6000_reg_names
[REGNO (scratch
)],
16107 GET_MODE_NAME (mode
));
16108 debug_rtx (addr_op2
);
16110 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16111 addr_op2
= scratch
;
16114 emit_insn (gen_rtx_SET (VOIDmode
,
16115 scratch_or_premodify
,
16116 gen_rtx_PLUS (Pmode
,
16120 addr
= scratch_or_premodify
;
16121 scratch_or_premodify
= scratch
;
16123 else if (!legitimate_indirect_address_p (addr
, false)
16124 && !rs6000_legitimate_offset_address_p (PTImode
, addr
,
16127 if (TARGET_DEBUG_ADDR
)
16129 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16130 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16131 GET_MODE_NAME (mode
));
16134 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16135 addr
= scratch_or_premodify
;
16136 scratch_or_premodify
= scratch
;
16140 /* Float registers can do offset+reg addressing for scalar types. */
16142 if (legitimate_indirect_address_p (addr
, false) /* reg */
16143 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16144 || ((GET_MODE_SIZE (mode
) == 4 || GET_MODE_SIZE (mode
) == 8)
16145 && and_op2
== NULL_RTX
16146 && scratch_or_premodify
== scratch
16147 && rs6000_legitimate_offset_address_p (mode
, addr
, false, false)))
16150 /* If this isn't a legacy floating point load/store, fall through to the
16153 /* VSX/Altivec registers can only handle reg+reg addressing. Move other
16154 addresses into a scratch register. */
16158 /* With float regs, we need to handle the AND ourselves, since we can't
16159 use the Altivec instruction with an implicit AND -16. Allow scalar
16160 loads to float registers to use reg+offset even if VSX. */
16161 if (GET_CODE (addr
) == AND
16162 && (rclass
!= ALTIVEC_REGS
|| GET_MODE_SIZE (mode
) != 16
16163 || GET_CODE (XEXP (addr
, 1)) != CONST_INT
16164 || INTVAL (XEXP (addr
, 1)) != -16
16165 || !VECTOR_MEM_ALTIVEC_P (mode
)))
16167 and_op2
= XEXP (addr
, 1);
16168 addr
= XEXP (addr
, 0);
16171 /* If we aren't using a VSX load, save the PRE_MODIFY register and use it
16172 as the address later. */
16173 if (GET_CODE (addr
) == PRE_MODIFY
16174 && ((ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
16175 && (rclass
!= FLOAT_REGS
16176 || (GET_MODE_SIZE (mode
) != 4 && GET_MODE_SIZE (mode
) != 8)))
16177 || and_op2
!= NULL_RTX
16178 || !legitimate_indexed_address_p (XEXP (addr
, 1), false)))
16180 scratch_or_premodify
= XEXP (addr
, 0);
16181 if (!legitimate_indirect_address_p (scratch_or_premodify
, false))
16182 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16184 if (GET_CODE (XEXP (addr
, 1)) != PLUS
)
16185 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16187 addr
= XEXP (addr
, 1);
16190 if (legitimate_indirect_address_p (addr
, false) /* reg */
16191 || legitimate_indexed_address_p (addr
, false) /* reg+reg */
16192 || (GET_CODE (addr
) == AND
/* Altivec memory */
16193 && rclass
== ALTIVEC_REGS
16194 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
16195 && INTVAL (XEXP (addr
, 1)) == -16
16196 && (legitimate_indirect_address_p (XEXP (addr
, 0), false)
16197 || legitimate_indexed_address_p (XEXP (addr
, 0), false))))
16200 else if (GET_CODE (addr
) == PLUS
)
16202 addr_op1
= XEXP (addr
, 0);
16203 addr_op2
= XEXP (addr
, 1);
16204 if (!REG_P (addr_op1
))
16205 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16207 if (TARGET_DEBUG_ADDR
)
16209 fprintf (stderr
, "\nMove plus addr to register %s, mode = %s: ",
16210 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16211 debug_rtx (addr_op2
);
16213 rs6000_emit_move (scratch
, addr_op2
, Pmode
);
16214 emit_insn (gen_rtx_SET (VOIDmode
,
16215 scratch_or_premodify
,
16216 gen_rtx_PLUS (Pmode
,
16219 addr
= scratch_or_premodify
;
16220 scratch_or_premodify
= scratch
;
16223 else if (GET_CODE (addr
) == SYMBOL_REF
|| GET_CODE (addr
) == CONST
16224 || GET_CODE (addr
) == CONST_INT
|| GET_CODE (addr
) == LO_SUM
16227 if (TARGET_DEBUG_ADDR
)
16229 fprintf (stderr
, "\nMove addr to register %s, mode = %s: ",
16230 rs6000_reg_names
[REGNO (scratch_or_premodify
)],
16231 GET_MODE_NAME (mode
));
16235 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16236 addr
= scratch_or_premodify
;
16237 scratch_or_premodify
= scratch
;
16241 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16246 rs6000_secondary_reload_fail (__LINE__
, reg
, mem
, scratch
, store_p
);
16249 /* If the original address involved a pre-modify that we couldn't use the VSX
16250 memory instruction with update, and we haven't taken care of already,
16251 store the address in the pre-modify register and use that as the
16253 if (scratch_or_premodify
!= scratch
&& scratch_or_premodify
!= addr
)
16255 emit_insn (gen_rtx_SET (VOIDmode
, scratch_or_premodify
, addr
));
16256 addr
= scratch_or_premodify
;
16259 /* If the original address involved an AND -16 and we couldn't use an ALTIVEC
16260 memory instruction, recreate the AND now, including the clobber which is
16261 generated by the general ANDSI3/ANDDI3 patterns for the
16262 andi. instruction. */
16263 if (and_op2
!= NULL_RTX
)
16265 if (! legitimate_indirect_address_p (addr
, false))
16267 emit_insn (gen_rtx_SET (VOIDmode
, scratch
, addr
));
16271 if (TARGET_DEBUG_ADDR
)
16273 fprintf (stderr
, "\nAnd addr to register %s, mode = %s: ",
16274 rs6000_reg_names
[REGNO (scratch
)], GET_MODE_NAME (mode
));
16275 debug_rtx (and_op2
);
16278 and_rtx
= gen_rtx_SET (VOIDmode
,
16280 gen_rtx_AND (Pmode
,
16284 cc_clobber
= gen_rtx_CLOBBER (CCmode
, gen_rtx_SCRATCH (CCmode
));
16285 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
16286 gen_rtvec (2, and_rtx
, cc_clobber
)));
16290 /* Adjust the address if it changed. */
16291 if (addr
!= XEXP (mem
, 0))
16293 mem
= replace_equiv_address_nv (mem
, addr
);
16294 if (TARGET_DEBUG_ADDR
)
16295 fprintf (stderr
, "\nrs6000_secondary_reload_inner, mem adjusted.\n");
16298 /* Now create the move. */
16300 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16302 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16307 /* Convert reloads involving 64-bit gprs and misaligned offset
16308 addressing, or multiple 32-bit gprs and offsets that are too large,
16309 to use indirect addressing. */
16312 rs6000_secondary_reload_gpr (rtx reg
, rtx mem
, rtx scratch
, bool store_p
)
16314 int regno
= true_regnum (reg
);
16315 enum reg_class rclass
;
16317 rtx scratch_or_premodify
= scratch
;
16319 if (TARGET_DEBUG_ADDR
)
16321 fprintf (stderr
, "\nrs6000_secondary_reload_gpr, type = %s\n",
16322 store_p
? "store" : "load");
16323 fprintf (stderr
, "reg:\n");
16325 fprintf (stderr
, "mem:\n");
16327 fprintf (stderr
, "scratch:\n");
16328 debug_rtx (scratch
);
16331 gcc_assert (regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
);
16332 gcc_assert (GET_CODE (mem
) == MEM
);
16333 rclass
= REGNO_REG_CLASS (regno
);
16334 gcc_assert (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
);
16335 addr
= XEXP (mem
, 0);
16337 if (GET_CODE (addr
) == PRE_MODIFY
)
16339 scratch_or_premodify
= XEXP (addr
, 0);
16340 gcc_assert (REG_P (scratch_or_premodify
));
16341 addr
= XEXP (addr
, 1);
16343 gcc_assert (GET_CODE (addr
) == PLUS
|| GET_CODE (addr
) == LO_SUM
);
16345 rs6000_emit_move (scratch_or_premodify
, addr
, Pmode
);
16347 mem
= replace_equiv_address_nv (mem
, scratch_or_premodify
);
16349 /* Now create the move. */
16351 emit_insn (gen_rtx_SET (VOIDmode
, mem
, reg
));
16353 emit_insn (gen_rtx_SET (VOIDmode
, reg
, mem
));
16358 /* Allocate a 64-bit stack slot to be used for copying SDmode values through if
16359 this function has any SDmode references. If we are on a power7 or later, we
16360 don't need the 64-bit stack slot since the LFIWZX and STIFWX instructions
16361 can load/store the value. */
16364 rs6000_alloc_sdmode_stack_slot (void)
16368 gimple_stmt_iterator gsi
;
16370 gcc_assert (cfun
->machine
->sdmode_stack_slot
== NULL_RTX
);
16371 /* We use a different approach for dealing with the secondary
16376 if (TARGET_NO_SDMODE_STACK
)
16380 for (gsi
= gsi_start_bb (bb
); !gsi_end_p (gsi
); gsi_next (&gsi
))
16382 tree ret
= walk_gimple_op (gsi_stmt (gsi
), rs6000_check_sdmode
, NULL
);
16385 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
16386 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
16392 /* Check for any SDmode parameters of the function. */
16393 for (t
= DECL_ARGUMENTS (cfun
->decl
); t
; t
= DECL_CHAIN (t
))
16395 if (TREE_TYPE (t
) == error_mark_node
)
16398 if (TYPE_MODE (TREE_TYPE (t
)) == SDmode
16399 || TYPE_MODE (DECL_ARG_TYPE (t
)) == SDmode
)
16401 rtx stack
= assign_stack_local (DDmode
, GET_MODE_SIZE (DDmode
), 0);
16402 cfun
->machine
->sdmode_stack_slot
= adjust_address_nv (stack
,
16410 rs6000_instantiate_decls (void)
16412 if (cfun
->machine
->sdmode_stack_slot
!= NULL_RTX
)
16413 instantiate_decl_rtl (cfun
->machine
->sdmode_stack_slot
);
16416 /* Given an rtx X being reloaded into a reg required to be
16417 in class CLASS, return the class of reg to actually use.
16418 In general this is just CLASS; but on some machines
16419 in some cases it is preferable to use a more restrictive class.
16421 On the RS/6000, we have to return NO_REGS when we want to reload a
16422 floating-point CONST_DOUBLE to force it to be copied to memory.
16424 We also don't want to reload integer values into floating-point
16425 registers if we can at all help it. In fact, this can
16426 cause reload to die, if it tries to generate a reload of CTR
16427 into a FP register and discovers it doesn't have the memory location
16430 ??? Would it be a good idea to have reload do the converse, that is
16431 try to reload floating modes into FP registers if possible?
16434 static enum reg_class
16435 rs6000_preferred_reload_class (rtx x
, enum reg_class rclass
)
16437 enum machine_mode mode
= GET_MODE (x
);
16439 if (TARGET_VSX
&& x
== CONST0_RTX (mode
) && VSX_REG_CLASS_P (rclass
))
16442 if (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
16443 && (rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
16444 && easy_vector_constant (x
, mode
))
16445 return ALTIVEC_REGS
;
16447 if (CONSTANT_P (x
) && reg_classes_intersect_p (rclass
, FLOAT_REGS
))
16450 if (GET_MODE_CLASS (mode
) == MODE_INT
&& rclass
== NON_SPECIAL_REGS
)
16451 return GENERAL_REGS
;
16453 /* For VSX, prefer the traditional registers for 64-bit values because we can
16454 use the non-VSX loads. Prefer the Altivec registers if Altivec is
16455 handling the vector operations (i.e. V16QI, V8HI, and V4SI), or if we
16456 prefer Altivec loads.. */
16457 if (rclass
== VSX_REGS
)
16459 if (GET_MODE_SIZE (mode
) <= 8)
16462 if (VECTOR_UNIT_ALTIVEC_P (mode
) || VECTOR_MEM_ALTIVEC_P (mode
))
16463 return ALTIVEC_REGS
;
16471 /* Debug version of rs6000_preferred_reload_class. */
16472 static enum reg_class
16473 rs6000_debug_preferred_reload_class (rtx x
, enum reg_class rclass
)
16475 enum reg_class ret
= rs6000_preferred_reload_class (x
, rclass
);
16478 "\nrs6000_preferred_reload_class, return %s, rclass = %s, "
16480 reg_class_names
[ret
], reg_class_names
[rclass
],
16481 GET_MODE_NAME (GET_MODE (x
)));
16487 /* If we are copying between FP or AltiVec registers and anything else, we need
16488 a memory location. The exception is when we are targeting ppc64 and the
16489 move to/from fpr to gpr instructions are available. Also, under VSX, you
16490 can copy vector registers from the FP register set to the Altivec register
16491 set and vice versa. */
16494 rs6000_secondary_memory_needed (enum reg_class from_class
,
16495 enum reg_class to_class
,
16496 enum machine_mode mode
)
16498 enum rs6000_reg_type from_type
, to_type
;
16499 bool altivec_p
= ((from_class
== ALTIVEC_REGS
)
16500 || (to_class
== ALTIVEC_REGS
));
16502 /* If a simple/direct move is available, we don't need secondary memory */
16503 from_type
= reg_class_to_reg_type
[(int)from_class
];
16504 to_type
= reg_class_to_reg_type
[(int)to_class
];
16506 if (rs6000_secondary_reload_move (to_type
, from_type
, mode
,
16507 (secondary_reload_info
*)0, altivec_p
))
16510 /* If we have a floating point or vector register class, we need to use
16511 memory to transfer the data. */
16512 if (IS_FP_VECT_REG_TYPE (from_type
) || IS_FP_VECT_REG_TYPE (to_type
))
16518 /* Debug version of rs6000_secondary_memory_needed. */
16520 rs6000_debug_secondary_memory_needed (enum reg_class from_class
,
16521 enum reg_class to_class
,
16522 enum machine_mode mode
)
16524 bool ret
= rs6000_secondary_memory_needed (from_class
, to_class
, mode
);
16527 "rs6000_secondary_memory_needed, return: %s, from_class = %s, "
16528 "to_class = %s, mode = %s\n",
16529 ret
? "true" : "false",
16530 reg_class_names
[from_class
],
16531 reg_class_names
[to_class
],
16532 GET_MODE_NAME (mode
));
16537 /* Return the register class of a scratch register needed to copy IN into
16538 or out of a register in RCLASS in MODE. If it can be done directly,
16539 NO_REGS is returned. */
16541 static enum reg_class
16542 rs6000_secondary_reload_class (enum reg_class rclass
, enum machine_mode mode
,
16547 if (TARGET_ELF
|| (DEFAULT_ABI
== ABI_DARWIN
16549 && MACHOPIC_INDIRECT
16553 /* We cannot copy a symbolic operand directly into anything
16554 other than BASE_REGS for TARGET_ELF. So indicate that a
16555 register from BASE_REGS is needed as an intermediate
16558 On Darwin, pic addresses require a load from memory, which
16559 needs a base register. */
16560 if (rclass
!= BASE_REGS
16561 && (GET_CODE (in
) == SYMBOL_REF
16562 || GET_CODE (in
) == HIGH
16563 || GET_CODE (in
) == LABEL_REF
16564 || GET_CODE (in
) == CONST
))
16568 if (GET_CODE (in
) == REG
)
16570 regno
= REGNO (in
);
16571 if (regno
>= FIRST_PSEUDO_REGISTER
)
16573 regno
= true_regnum (in
);
16574 if (regno
>= FIRST_PSEUDO_REGISTER
)
16578 else if (GET_CODE (in
) == SUBREG
)
16580 regno
= true_regnum (in
);
16581 if (regno
>= FIRST_PSEUDO_REGISTER
)
16587 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
16589 if (rclass
== GENERAL_REGS
|| rclass
== BASE_REGS
16590 || (regno
>= 0 && INT_REGNO_P (regno
)))
16593 /* Constants, memory, and FP registers can go into FP registers. */
16594 if ((regno
== -1 || FP_REGNO_P (regno
))
16595 && (rclass
== FLOAT_REGS
|| rclass
== NON_SPECIAL_REGS
))
16596 return (mode
!= SDmode
|| lra_in_progress
) ? NO_REGS
: GENERAL_REGS
;
16598 /* Memory, and FP/altivec registers can go into fp/altivec registers under
16599 VSX. However, for scalar variables, use the traditional floating point
16600 registers so that we can use offset+register addressing. */
16602 && (regno
== -1 || VSX_REGNO_P (regno
))
16603 && VSX_REG_CLASS_P (rclass
))
16605 if (GET_MODE_SIZE (mode
) < 16)
16611 /* Memory, and AltiVec registers can go into AltiVec registers. */
16612 if ((regno
== -1 || ALTIVEC_REGNO_P (regno
))
16613 && rclass
== ALTIVEC_REGS
)
16616 /* We can copy among the CR registers. */
16617 if ((rclass
== CR_REGS
|| rclass
== CR0_REGS
)
16618 && regno
>= 0 && CR_REGNO_P (regno
))
16621 /* Otherwise, we need GENERAL_REGS. */
16622 return GENERAL_REGS
;
16625 /* Debug version of rs6000_secondary_reload_class. */
16626 static enum reg_class
16627 rs6000_debug_secondary_reload_class (enum reg_class rclass
,
16628 enum machine_mode mode
, rtx in
)
16630 enum reg_class ret
= rs6000_secondary_reload_class (rclass
, mode
, in
);
16632 "\nrs6000_secondary_reload_class, return %s, rclass = %s, "
16633 "mode = %s, input rtx:\n",
16634 reg_class_names
[ret
], reg_class_names
[rclass
],
16635 GET_MODE_NAME (mode
));
16641 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */
16644 rs6000_cannot_change_mode_class (enum machine_mode from
,
16645 enum machine_mode to
,
16646 enum reg_class rclass
)
16648 unsigned from_size
= GET_MODE_SIZE (from
);
16649 unsigned to_size
= GET_MODE_SIZE (to
);
16651 if (from_size
!= to_size
)
16653 enum reg_class xclass
= (TARGET_VSX
) ? VSX_REGS
: FLOAT_REGS
;
16655 if (reg_classes_intersect_p (xclass
, rclass
))
16657 unsigned to_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][to
];
16658 unsigned from_nregs
= hard_regno_nregs
[FIRST_FPR_REGNO
][from
];
16660 /* Don't allow 64-bit types to overlap with 128-bit types that take a
16661 single register under VSX because the scalar part of the register
16662 is in the upper 64-bits, and not the lower 64-bits. Types like
16663 TFmode/TDmode that take 2 scalar register can overlap. 128-bit
16664 IEEE floating point can't overlap, and neither can small
16667 if (TARGET_IEEEQUAD
&& (to
== TFmode
|| from
== TFmode
))
16670 if (from_size
< 8 || to_size
< 8)
16673 if (from_size
== 8 && (8 * to_nregs
) != to_size
)
16676 if (to_size
== 8 && (8 * from_nregs
) != from_size
)
16685 if (TARGET_E500_DOUBLE
16686 && ((((to
) == DFmode
) + ((from
) == DFmode
)) == 1
16687 || (((to
) == TFmode
) + ((from
) == TFmode
)) == 1
16688 || (((to
) == DDmode
) + ((from
) == DDmode
)) == 1
16689 || (((to
) == TDmode
) + ((from
) == TDmode
)) == 1
16690 || (((to
) == DImode
) + ((from
) == DImode
)) == 1))
16693 /* Since the VSX register set includes traditional floating point registers
16694 and altivec registers, just check for the size being different instead of
16695 trying to check whether the modes are vector modes. Otherwise it won't
16696 allow say DF and DI to change classes. For types like TFmode and TDmode
16697 that take 2 64-bit registers, rather than a single 128-bit register, don't
16698 allow subregs of those types to other 128 bit types. */
16699 if (TARGET_VSX
&& VSX_REG_CLASS_P (rclass
))
16701 unsigned num_regs
= (from_size
+ 15) / 16;
16702 if (hard_regno_nregs
[FIRST_FPR_REGNO
][to
] > num_regs
16703 || hard_regno_nregs
[FIRST_FPR_REGNO
][from
] > num_regs
)
16706 return (from_size
!= 8 && from_size
!= 16);
16709 if (TARGET_ALTIVEC
&& rclass
== ALTIVEC_REGS
16710 && (ALTIVEC_VECTOR_MODE (from
) + ALTIVEC_VECTOR_MODE (to
)) == 1)
16713 if (TARGET_SPE
&& (SPE_VECTOR_MODE (from
) + SPE_VECTOR_MODE (to
)) == 1
16714 && reg_classes_intersect_p (GENERAL_REGS
, rclass
))
16720 /* Debug version of rs6000_cannot_change_mode_class. */
16722 rs6000_debug_cannot_change_mode_class (enum machine_mode from
,
16723 enum machine_mode to
,
16724 enum reg_class rclass
)
16726 bool ret
= rs6000_cannot_change_mode_class (from
, to
, rclass
);
16729 "rs6000_cannot_change_mode_class, return %s, from = %s, "
16730 "to = %s, rclass = %s\n",
16731 ret
? "true" : "false",
16732 GET_MODE_NAME (from
), GET_MODE_NAME (to
),
16733 reg_class_names
[rclass
]);
16738 /* Return a string to do a move operation of 128 bits of data. */
16741 rs6000_output_move_128bit (rtx operands
[])
16743 rtx dest
= operands
[0];
16744 rtx src
= operands
[1];
16745 enum machine_mode mode
= GET_MODE (dest
);
16748 bool dest_gpr_p
, dest_fp_p
, dest_vmx_p
, dest_vsx_p
;
16749 bool src_gpr_p
, src_fp_p
, src_vmx_p
, src_vsx_p
;
16753 dest_regno
= REGNO (dest
);
16754 dest_gpr_p
= INT_REGNO_P (dest_regno
);
16755 dest_fp_p
= FP_REGNO_P (dest_regno
);
16756 dest_vmx_p
= ALTIVEC_REGNO_P (dest_regno
);
16757 dest_vsx_p
= dest_fp_p
| dest_vmx_p
;
16762 dest_gpr_p
= dest_fp_p
= dest_vmx_p
= dest_vsx_p
= false;
16767 src_regno
= REGNO (src
);
16768 src_gpr_p
= INT_REGNO_P (src_regno
);
16769 src_fp_p
= FP_REGNO_P (src_regno
);
16770 src_vmx_p
= ALTIVEC_REGNO_P (src_regno
);
16771 src_vsx_p
= src_fp_p
| src_vmx_p
;
16776 src_gpr_p
= src_fp_p
= src_vmx_p
= src_vsx_p
= false;
16779 /* Register moves. */
16780 if (dest_regno
>= 0 && src_regno
>= 0)
16787 else if (TARGET_VSX
&& TARGET_DIRECT_MOVE
&& src_vsx_p
)
16791 else if (TARGET_VSX
&& dest_vsx_p
)
16794 return "xxlor %x0,%x1,%x1";
16796 else if (TARGET_DIRECT_MOVE
&& src_gpr_p
)
16800 else if (TARGET_ALTIVEC
&& dest_vmx_p
&& src_vmx_p
)
16801 return "vor %0,%1,%1";
16803 else if (dest_fp_p
&& src_fp_p
)
16808 else if (dest_regno
>= 0 && MEM_P (src
))
16812 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
16818 else if (TARGET_ALTIVEC
&& dest_vmx_p
16819 && altivec_indexed_or_indirect_operand (src
, mode
))
16820 return "lvx %0,%y1";
16822 else if (TARGET_VSX
&& dest_vsx_p
)
16824 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
16825 return "lxvw4x %x0,%y1";
16827 return "lxvd2x %x0,%y1";
16830 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
16831 return "lvx %0,%y1";
16833 else if (dest_fp_p
)
16838 else if (src_regno
>= 0 && MEM_P (dest
))
16842 if (TARGET_QUAD_MEMORY
&& quad_load_store_p (dest
, src
))
16843 return "stq %1,%0";
16848 else if (TARGET_ALTIVEC
&& src_vmx_p
16849 && altivec_indexed_or_indirect_operand (src
, mode
))
16850 return "stvx %1,%y0";
16852 else if (TARGET_VSX
&& src_vsx_p
)
16854 if (mode
== V16QImode
|| mode
== V8HImode
|| mode
== V4SImode
)
16855 return "stxvw4x %x1,%y0";
16857 return "stxvd2x %x1,%y0";
16860 else if (TARGET_ALTIVEC
&& src_vmx_p
)
16861 return "stvx %1,%y0";
16868 else if (dest_regno
>= 0
16869 && (GET_CODE (src
) == CONST_INT
16870 || GET_CODE (src
) == CONST_WIDE_INT
16871 || GET_CODE (src
) == CONST_DOUBLE
16872 || GET_CODE (src
) == CONST_VECTOR
))
16877 else if (TARGET_VSX
&& dest_vsx_p
&& zero_constant (src
, mode
))
16878 return "xxlxor %x0,%x0,%x0";
16880 else if (TARGET_ALTIVEC
&& dest_vmx_p
)
16881 return output_vec_const_move (operands
);
16884 if (TARGET_DEBUG_ADDR
)
16886 fprintf (stderr
, "\n===== Bad 128 bit move:\n");
16887 debug_rtx (gen_rtx_SET (VOIDmode
, dest
, src
));
16890 gcc_unreachable ();
16894 /* Given a comparison operation, return the bit number in CCR to test. We
16895 know this is a valid comparison.
16897 SCC_P is 1 if this is for an scc. That means that %D will have been
16898 used instead of %C, so the bits will be in different places.
16900 Return -1 if OP isn't a valid comparison for some reason. */
16903 ccr_bit (rtx op
, int scc_p
)
16905 enum rtx_code code
= GET_CODE (op
);
16906 enum machine_mode cc_mode
;
16911 if (!COMPARISON_P (op
))
16914 reg
= XEXP (op
, 0);
16916 gcc_assert (GET_CODE (reg
) == REG
&& CR_REGNO_P (REGNO (reg
)));
16918 cc_mode
= GET_MODE (reg
);
16919 cc_regnum
= REGNO (reg
);
16920 base_bit
= 4 * (cc_regnum
- CR0_REGNO
);
16922 validate_condition_mode (code
, cc_mode
);
16924 /* When generating a sCOND operation, only positive conditions are
16927 || code
== EQ
|| code
== GT
|| code
== LT
|| code
== UNORDERED
16928 || code
== GTU
|| code
== LTU
);
16933 return scc_p
? base_bit
+ 3 : base_bit
+ 2;
16935 return base_bit
+ 2;
16936 case GT
: case GTU
: case UNLE
:
16937 return base_bit
+ 1;
16938 case LT
: case LTU
: case UNGE
:
16940 case ORDERED
: case UNORDERED
:
16941 return base_bit
+ 3;
16944 /* If scc, we will have done a cror to put the bit in the
16945 unordered position. So test that bit. For integer, this is ! LT
16946 unless this is an scc insn. */
16947 return scc_p
? base_bit
+ 3 : base_bit
;
16950 return scc_p
? base_bit
+ 3 : base_bit
+ 1;
16953 gcc_unreachable ();
16957 /* Return the GOT register. */
16960 rs6000_got_register (rtx value ATTRIBUTE_UNUSED
)
16962 /* The second flow pass currently (June 1999) can't update
16963 regs_ever_live without disturbing other parts of the compiler, so
16964 update it here to make the prolog/epilogue code happy. */
16965 if (!can_create_pseudo_p ()
16966 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
16967 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM
, true);
16969 crtl
->uses_pic_offset_table
= 1;
16971 return pic_offset_table_rtx
;
16974 static rs6000_stack_t stack_info
;
16976 /* Function to init struct machine_function.
16977 This will be called, via a pointer variable,
16978 from push_function_context. */
16980 static struct machine_function
*
16981 rs6000_init_machine_status (void)
16983 stack_info
.reload_completed
= 0;
16984 return ggc_alloc_cleared_machine_function ();
16987 #define INT_P(X) (GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode)
16990 extract_MB (rtx op
)
16993 unsigned long val
= INTVAL (op
);
16995 /* If the high bit is zero, the value is the first 1 bit we find
16997 if ((val
& 0x80000000) == 0)
16999 gcc_assert (val
& 0xffffffff);
17002 while (((val
<<= 1) & 0x80000000) == 0)
17007 /* If the high bit is set and the low bit is not, or the mask is all
17008 1's, the value is zero. */
17009 if ((val
& 1) == 0 || (val
& 0xffffffff) == 0xffffffff)
17012 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17015 while (((val
>>= 1) & 1) != 0)
17022 extract_ME (rtx op
)
17025 unsigned long val
= INTVAL (op
);
17027 /* If the low bit is zero, the value is the first 1 bit we find from
17029 if ((val
& 1) == 0)
17031 gcc_assert (val
& 0xffffffff);
17034 while (((val
>>= 1) & 1) == 0)
17040 /* If the low bit is set and the high bit is not, or the mask is all
17041 1's, the value is 31. */
17042 if ((val
& 0x80000000) == 0 || (val
& 0xffffffff) == 0xffffffff)
17045 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
17048 while (((val
<<= 1) & 0x80000000) != 0)
17054 /* Locate some local-dynamic symbol still in use by this function
17055 so that we can print its name in some tls_ld pattern. */
17057 static const char *
17058 rs6000_get_some_local_dynamic_name (void)
17062 if (cfun
->machine
->some_ld_name
)
17063 return cfun
->machine
->some_ld_name
;
17065 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
17067 && for_each_rtx (&PATTERN (insn
),
17068 rs6000_get_some_local_dynamic_name_1
, 0))
17069 return cfun
->machine
->some_ld_name
;
17071 gcc_unreachable ();
17074 /* Helper function for rs6000_get_some_local_dynamic_name. */
17077 rs6000_get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
17081 if (GET_CODE (x
) == SYMBOL_REF
)
17083 const char *str
= XSTR (x
, 0);
17084 if (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
17086 cfun
->machine
->some_ld_name
= str
;
17094 /* Write out a function code label. */
17097 rs6000_output_function_entry (FILE *file
, const char *fname
)
17099 if (fname
[0] != '.')
17101 switch (DEFAULT_ABI
)
17104 gcc_unreachable ();
17110 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "L.");
17120 RS6000_OUTPUT_BASENAME (file
, fname
);
17123 /* Print an operand. Recognize special options, documented below. */
17126 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
17127 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
17129 #define SMALL_DATA_RELOC "sda21"
17130 #define SMALL_DATA_REG 0
17134 print_operand (FILE *file
, rtx x
, int code
)
17137 unsigned HOST_WIDE_INT uval
;
17141 /* %a is output_address. */
17144 /* If constant, low-order 16 bits of constant, unsigned.
17145 Otherwise, write normally. */
17147 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
17149 print_operand (file
, x
, 0);
17153 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
17154 for 64-bit mask direction. */
17155 putc (((INTVAL (x
) & 1) == 0 ? 'r' : 'l'), file
);
17158 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
17162 /* Like 'J' but get to the GT bit only. */
17163 gcc_assert (REG_P (x
));
17165 /* Bit 1 is GT bit. */
17166 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 1;
17168 /* Add one for shift count in rlinm for scc. */
17169 fprintf (file
, "%d", i
+ 1);
17173 /* X is a CR register. Print the number of the EQ bit of the CR */
17174 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17175 output_operand_lossage ("invalid %%E value");
17177 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
) + 2);
17181 /* X is a CR register. Print the shift count needed to move it
17182 to the high-order four bits. */
17183 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17184 output_operand_lossage ("invalid %%f value");
17186 fprintf (file
, "%d", 4 * (REGNO (x
) - CR0_REGNO
));
17190 /* Similar, but print the count for the rotate in the opposite
17192 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17193 output_operand_lossage ("invalid %%F value");
17195 fprintf (file
, "%d", 32 - 4 * (REGNO (x
) - CR0_REGNO
));
17199 /* X is a constant integer. If it is negative, print "m",
17200 otherwise print "z". This is to make an aze or ame insn. */
17201 if (GET_CODE (x
) != CONST_INT
)
17202 output_operand_lossage ("invalid %%G value");
17203 else if (INTVAL (x
) >= 0)
17210 /* If constant, output low-order five bits. Otherwise, write
17213 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 31);
17215 print_operand (file
, x
, 0);
17219 /* If constant, output low-order six bits. Otherwise, write
17222 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 63);
17224 print_operand (file
, x
, 0);
17228 /* Print `i' if this is a constant, else nothing. */
17234 /* Write the bit number in CCR for jump. */
17235 i
= ccr_bit (x
, 0);
17237 output_operand_lossage ("invalid %%j code");
17239 fprintf (file
, "%d", i
);
17243 /* Similar, but add one for shift count in rlinm for scc and pass
17244 scc flag to `ccr_bit'. */
17245 i
= ccr_bit (x
, 1);
17247 output_operand_lossage ("invalid %%J code");
17249 /* If we want bit 31, write a shift count of zero, not 32. */
17250 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17254 /* X must be a constant. Write the 1's complement of the
17257 output_operand_lossage ("invalid %%k value");
17259 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
17263 /* X must be a symbolic constant on ELF. Write an
17264 expression suitable for an 'addi' that adds in the low 16
17265 bits of the MEM. */
17266 if (GET_CODE (x
) == CONST
)
17268 if (GET_CODE (XEXP (x
, 0)) != PLUS
17269 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
17270 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
17271 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
17272 output_operand_lossage ("invalid %%K value");
17274 print_operand_address (file
, x
);
17275 fputs ("@l", file
);
17278 /* %l is output_asm_label. */
17281 /* Write second word of DImode or DFmode reference. Works on register
17282 or non-indexed memory only. */
17284 fputs (reg_names
[REGNO (x
) + 1], file
);
17285 else if (MEM_P (x
))
17287 /* Handle possible auto-increment. Since it is pre-increment and
17288 we have already done it, we can just use an offset of word. */
17289 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17290 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17291 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17293 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17294 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0),
17297 output_address (XEXP (adjust_address_nv (x
, SImode
,
17301 if (small_data_operand (x
, GET_MODE (x
)))
17302 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17303 reg_names
[SMALL_DATA_REG
]);
17308 /* MB value for a mask operand. */
17309 if (! mask_operand (x
, SImode
))
17310 output_operand_lossage ("invalid %%m value");
17312 fprintf (file
, "%d", extract_MB (x
));
17316 /* ME value for a mask operand. */
17317 if (! mask_operand (x
, SImode
))
17318 output_operand_lossage ("invalid %%M value");
17320 fprintf (file
, "%d", extract_ME (x
));
17323 /* %n outputs the negative of its operand. */
17326 /* Write the number of elements in the vector times 4. */
17327 if (GET_CODE (x
) != PARALLEL
)
17328 output_operand_lossage ("invalid %%N value");
17330 fprintf (file
, "%d", XVECLEN (x
, 0) * 4);
17334 /* Similar, but subtract 1 first. */
17335 if (GET_CODE (x
) != PARALLEL
)
17336 output_operand_lossage ("invalid %%O value");
17338 fprintf (file
, "%d", (XVECLEN (x
, 0) - 1) * 4);
17342 /* X is a CONST_INT that is a power of two. Output the logarithm. */
17345 || (i
= exact_log2 (INTVAL (x
))) < 0)
17346 output_operand_lossage ("invalid %%p value");
17348 fprintf (file
, "%d", i
);
17352 /* The operand must be an indirect memory reference. The result
17353 is the register name. */
17354 if (GET_CODE (x
) != MEM
|| GET_CODE (XEXP (x
, 0)) != REG
17355 || REGNO (XEXP (x
, 0)) >= 32)
17356 output_operand_lossage ("invalid %%P value");
17358 fputs (reg_names
[REGNO (XEXP (x
, 0))], file
);
17362 /* This outputs the logical code corresponding to a boolean
17363 expression. The expression may have one or both operands
17364 negated (if one, only the first one). For condition register
17365 logical operations, it will also treat the negated
17366 CR codes as NOTs, but not handle NOTs of them. */
17368 const char *const *t
= 0;
17370 enum rtx_code code
= GET_CODE (x
);
17371 static const char * const tbl
[3][3] = {
17372 { "and", "andc", "nor" },
17373 { "or", "orc", "nand" },
17374 { "xor", "eqv", "xor" } };
17378 else if (code
== IOR
)
17380 else if (code
== XOR
)
17383 output_operand_lossage ("invalid %%q value");
17385 if (GET_CODE (XEXP (x
, 0)) != NOT
)
17389 if (GET_CODE (XEXP (x
, 1)) == NOT
)
17400 if (! TARGET_MFCRF
)
17406 /* X is a CR register. Print the mask for `mtcrf'. */
17407 if (GET_CODE (x
) != REG
|| ! CR_REGNO_P (REGNO (x
)))
17408 output_operand_lossage ("invalid %%R value");
17410 fprintf (file
, "%d", 128 >> (REGNO (x
) - CR0_REGNO
));
17414 /* Low 5 bits of 32 - value */
17416 output_operand_lossage ("invalid %%s value");
17418 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (32 - INTVAL (x
)) & 31);
17422 /* PowerPC64 mask position. All 0's is excluded.
17423 CONST_INT 32-bit mask is considered sign-extended so any
17424 transition must occur within the CONST_INT, not on the boundary. */
17425 if (! mask64_operand (x
, DImode
))
17426 output_operand_lossage ("invalid %%S value");
17430 if (uval
& 1) /* Clear Left */
17432 #if HOST_BITS_PER_WIDE_INT > 64
17433 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
17437 else /* Clear Right */
17440 #if HOST_BITS_PER_WIDE_INT > 64
17441 uval
&= ((unsigned HOST_WIDE_INT
) 1 << 64) - 1;
17447 gcc_assert (i
>= 0);
17448 fprintf (file
, "%d", i
);
17452 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
17453 gcc_assert (REG_P (x
) && GET_MODE (x
) == CCmode
);
17455 /* Bit 3 is OV bit. */
17456 i
= 4 * (REGNO (x
) - CR0_REGNO
) + 3;
17458 /* If we want bit 31, write a shift count of zero, not 32. */
17459 fprintf (file
, "%d", i
== 31 ? 0 : i
+ 1);
17463 /* Print the symbolic name of a branch target register. */
17464 if (GET_CODE (x
) != REG
|| (REGNO (x
) != LR_REGNO
17465 && REGNO (x
) != CTR_REGNO
))
17466 output_operand_lossage ("invalid %%T value");
17467 else if (REGNO (x
) == LR_REGNO
)
17468 fputs ("lr", file
);
17470 fputs ("ctr", file
);
17474 /* High-order 16 bits of constant for use in unsigned operand. */
17476 output_operand_lossage ("invalid %%u value");
17478 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17479 (INTVAL (x
) >> 16) & 0xffff);
17483 /* High-order 16 bits of constant for use in signed operand. */
17485 output_operand_lossage ("invalid %%v value");
17487 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
17488 (INTVAL (x
) >> 16) & 0xffff);
17492 /* Print `u' if this has an auto-increment or auto-decrement. */
17494 && (GET_CODE (XEXP (x
, 0)) == PRE_INC
17495 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
17496 || GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
))
17501 /* Print the trap code for this operand. */
17502 switch (GET_CODE (x
))
17505 fputs ("eq", file
); /* 4 */
17508 fputs ("ne", file
); /* 24 */
17511 fputs ("lt", file
); /* 16 */
17514 fputs ("le", file
); /* 20 */
17517 fputs ("gt", file
); /* 8 */
17520 fputs ("ge", file
); /* 12 */
17523 fputs ("llt", file
); /* 2 */
17526 fputs ("lle", file
); /* 6 */
17529 fputs ("lgt", file
); /* 1 */
17532 fputs ("lge", file
); /* 5 */
17535 gcc_unreachable ();
17540 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
17543 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
17544 ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
17546 print_operand (file
, x
, 0);
17550 /* MB value for a PowerPC64 rldic operand. */
17551 i
= clz_hwi (INTVAL (x
));
17553 fprintf (file
, "%d", i
);
17557 /* X is a FPR or Altivec register used in a VSX context. */
17558 if (GET_CODE (x
) != REG
|| !VSX_REGNO_P (REGNO (x
)))
17559 output_operand_lossage ("invalid %%x value");
17562 int reg
= REGNO (x
);
17563 int vsx_reg
= (FP_REGNO_P (reg
)
17565 : reg
- FIRST_ALTIVEC_REGNO
+ 32);
17567 #ifdef TARGET_REGNAMES
17568 if (TARGET_REGNAMES
)
17569 fprintf (file
, "%%vs%d", vsx_reg
);
17572 fprintf (file
, "%d", vsx_reg
);
17578 && (legitimate_indexed_address_p (XEXP (x
, 0), 0)
17579 || (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
17580 && legitimate_indexed_address_p (XEXP (XEXP (x
, 0), 1), 0))))
17585 /* Like 'L', for third word of TImode/PTImode */
17587 fputs (reg_names
[REGNO (x
) + 2], file
);
17588 else if (MEM_P (x
))
17590 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17591 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17592 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
17593 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17594 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 8));
17596 output_address (XEXP (adjust_address_nv (x
, SImode
, 8), 0));
17597 if (small_data_operand (x
, GET_MODE (x
)))
17598 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17599 reg_names
[SMALL_DATA_REG
]);
17604 /* X is a SYMBOL_REF. Write out the name preceded by a
17605 period and without any trailing data in brackets. Used for function
17606 names. If we are configured for System V (or the embedded ABI) on
17607 the PowerPC, do not emit the period, since those systems do not use
17608 TOCs and the like. */
17609 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
17611 /* For macho, check to see if we need a stub. */
17614 const char *name
= XSTR (x
, 0);
17616 if (darwin_emit_branch_islands
17617 && MACHOPIC_INDIRECT
17618 && machopic_classify_symbol (x
) == MACHOPIC_UNDEFINED_FUNCTION
)
17619 name
= machopic_indirection_name (x
, /*stub_p=*/true);
17621 assemble_name (file
, name
);
17623 else if (!DOT_SYMBOLS
)
17624 assemble_name (file
, XSTR (x
, 0));
17626 rs6000_output_function_entry (file
, XSTR (x
, 0));
17630 /* Like 'L', for last word of TImode/PTImode. */
17632 fputs (reg_names
[REGNO (x
) + 3], file
);
17633 else if (MEM_P (x
))
17635 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
17636 || GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17637 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
17638 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17639 output_address (plus_constant (Pmode
, XEXP (XEXP (x
, 0), 0), 12));
17641 output_address (XEXP (adjust_address_nv (x
, SImode
, 12), 0));
17642 if (small_data_operand (x
, GET_MODE (x
)))
17643 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17644 reg_names
[SMALL_DATA_REG
]);
17648 /* Print AltiVec or SPE memory operand. */
17653 gcc_assert (MEM_P (x
));
17657 /* Ugly hack because %y is overloaded. */
17658 if ((TARGET_SPE
|| TARGET_E500_DOUBLE
)
17659 && (GET_MODE_SIZE (GET_MODE (x
)) == 8
17660 || GET_MODE (x
) == TFmode
17661 || GET_MODE (x
) == TImode
17662 || GET_MODE (x
) == PTImode
))
17664 /* Handle [reg]. */
17667 fprintf (file
, "0(%s)", reg_names
[REGNO (tmp
)]);
17670 /* Handle [reg+UIMM]. */
17671 else if (GET_CODE (tmp
) == PLUS
&&
17672 GET_CODE (XEXP (tmp
, 1)) == CONST_INT
)
17676 gcc_assert (REG_P (XEXP (tmp
, 0)));
17678 x
= INTVAL (XEXP (tmp
, 1));
17679 fprintf (file
, "%d(%s)", x
, reg_names
[REGNO (XEXP (tmp
, 0))]);
17683 /* Fall through. Must be [reg+reg]. */
17685 if (VECTOR_MEM_ALTIVEC_P (GET_MODE (x
))
17686 && GET_CODE (tmp
) == AND
17687 && GET_CODE (XEXP (tmp
, 1)) == CONST_INT
17688 && INTVAL (XEXP (tmp
, 1)) == -16)
17689 tmp
= XEXP (tmp
, 0);
17690 else if (VECTOR_MEM_VSX_P (GET_MODE (x
))
17691 && GET_CODE (tmp
) == PRE_MODIFY
)
17692 tmp
= XEXP (tmp
, 1);
17694 fprintf (file
, "0,%s", reg_names
[REGNO (tmp
)]);
17697 if (!GET_CODE (tmp
) == PLUS
17698 || !REG_P (XEXP (tmp
, 0))
17699 || !REG_P (XEXP (tmp
, 1)))
17701 output_operand_lossage ("invalid %%y value, try using the 'Z' constraint");
17705 if (REGNO (XEXP (tmp
, 0)) == 0)
17706 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 1)) ],
17707 reg_names
[ REGNO (XEXP (tmp
, 0)) ]);
17709 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (tmp
, 0)) ],
17710 reg_names
[ REGNO (XEXP (tmp
, 1)) ]);
17717 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
17718 else if (MEM_P (x
))
17720 /* We need to handle PRE_INC and PRE_DEC here, since we need to
17721 know the width from the mode. */
17722 if (GET_CODE (XEXP (x
, 0)) == PRE_INC
)
17723 fprintf (file
, "%d(%s)", GET_MODE_SIZE (GET_MODE (x
)),
17724 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
17725 else if (GET_CODE (XEXP (x
, 0)) == PRE_DEC
)
17726 fprintf (file
, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x
)),
17727 reg_names
[REGNO (XEXP (XEXP (x
, 0), 0))]);
17728 else if (GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
17729 output_address (XEXP (XEXP (x
, 0), 1));
17731 output_address (XEXP (x
, 0));
17735 if (toc_relative_expr_p (x
, false))
17736 /* This hack along with a corresponding hack in
17737 rs6000_output_addr_const_extra arranges to output addends
17738 where the assembler expects to find them. eg.
17739 (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 4)
17740 without this hack would be output as "x@toc+4". We
17742 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
17744 output_addr_const (file
, x
);
17749 assemble_name (file
, rs6000_get_some_local_dynamic_name ());
17753 output_operand_lossage ("invalid %%xn code");
17757 /* Print the address of an operand. */
17760 print_operand_address (FILE *file
, rtx x
)
17763 fprintf (file
, "0(%s)", reg_names
[ REGNO (x
) ]);
17764 else if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == CONST
17765 || GET_CODE (x
) == LABEL_REF
)
17767 output_addr_const (file
, x
);
17768 if (small_data_operand (x
, GET_MODE (x
)))
17769 fprintf (file
, "@%s(%s)", SMALL_DATA_RELOC
,
17770 reg_names
[SMALL_DATA_REG
]);
17772 gcc_assert (!TARGET_TOC
);
17774 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
17775 && REG_P (XEXP (x
, 1)))
17777 if (REGNO (XEXP (x
, 0)) == 0)
17778 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 1)) ],
17779 reg_names
[ REGNO (XEXP (x
, 0)) ]);
17781 fprintf (file
, "%s,%s", reg_names
[ REGNO (XEXP (x
, 0)) ],
17782 reg_names
[ REGNO (XEXP (x
, 1)) ]);
17784 else if (GET_CODE (x
) == PLUS
&& REG_P (XEXP (x
, 0))
17785 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
17786 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)",
17787 INTVAL (XEXP (x
, 1)), reg_names
[ REGNO (XEXP (x
, 0)) ]);
17789 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
17790 && CONSTANT_P (XEXP (x
, 1)))
17792 fprintf (file
, "lo16(");
17793 output_addr_const (file
, XEXP (x
, 1));
17794 fprintf (file
, ")(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
17798 else if (GET_CODE (x
) == LO_SUM
&& REG_P (XEXP (x
, 0))
17799 && CONSTANT_P (XEXP (x
, 1)))
17801 output_addr_const (file
, XEXP (x
, 1));
17802 fprintf (file
, "@l(%s)", reg_names
[ REGNO (XEXP (x
, 0)) ]);
17805 else if (toc_relative_expr_p (x
, false))
17807 /* This hack along with a corresponding hack in
17808 rs6000_output_addr_const_extra arranges to output addends
17809 where the assembler expects to find them. eg.
17811 . (plus (unspec [(symbol_ref ("x")) (reg 2)] tocrel) 8))
17812 without this hack would be output as "x@toc+8@l(9)". We
17813 want "x+8@toc@l(9)". */
17814 output_addr_const (file
, CONST_CAST_RTX (tocrel_base
));
17815 if (GET_CODE (x
) == LO_SUM
)
17816 fprintf (file
, "@l(%s)", reg_names
[REGNO (XEXP (x
, 0))]);
17818 fprintf (file
, "(%s)", reg_names
[REGNO (XVECEXP (tocrel_base
, 0, 1))]);
17821 gcc_unreachable ();
17824 /* Implement TARGET_OUTPUT_ADDR_CONST_EXTRA. */
17827 rs6000_output_addr_const_extra (FILE *file
, rtx x
)
17829 if (GET_CODE (x
) == UNSPEC
)
17830 switch (XINT (x
, 1))
17832 case UNSPEC_TOCREL
:
17833 gcc_checking_assert (GET_CODE (XVECEXP (x
, 0, 0)) == SYMBOL_REF
17834 && REG_P (XVECEXP (x
, 0, 1))
17835 && REGNO (XVECEXP (x
, 0, 1)) == TOC_REGISTER
);
17836 output_addr_const (file
, XVECEXP (x
, 0, 0));
17837 if (x
== tocrel_base
&& tocrel_offset
!= const0_rtx
)
17839 if (INTVAL (tocrel_offset
) >= 0)
17840 fprintf (file
, "+");
17841 output_addr_const (file
, CONST_CAST_RTX (tocrel_offset
));
17843 if (!TARGET_AIX
|| (TARGET_ELF
&& TARGET_MINIMAL_TOC
))
17846 assemble_name (file
, toc_label_name
);
17848 else if (TARGET_ELF
)
17849 fputs ("@toc", file
);
17853 case UNSPEC_MACHOPIC_OFFSET
:
17854 output_addr_const (file
, XVECEXP (x
, 0, 0));
17856 machopic_output_function_base_name (file
);
17863 /* Target hook for assembling integer objects. The PowerPC version has
17864 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
17865 is defined. It also needs to handle DI-mode objects on 64-bit
17869 rs6000_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
17871 #ifdef RELOCATABLE_NEEDS_FIXUP
17872 /* Special handling for SI values. */
17873 if (RELOCATABLE_NEEDS_FIXUP
&& size
== 4 && aligned_p
)
17875 static int recurse
= 0;
17877 /* For -mrelocatable, we mark all addresses that need to be fixed up in
17878 the .fixup section. Since the TOC section is already relocated, we
17879 don't need to mark it here. We used to skip the text section, but it
17880 should never be valid for relocated addresses to be placed in the text
17882 if (TARGET_RELOCATABLE
17883 && in_section
!= toc_section
17885 && !CONST_SCALAR_INT_P (x
)
17891 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", fixuplabelno
);
17893 ASM_OUTPUT_LABEL (asm_out_file
, buf
);
17894 fprintf (asm_out_file
, "\t.long\t(");
17895 output_addr_const (asm_out_file
, x
);
17896 fprintf (asm_out_file
, ")@fixup\n");
17897 fprintf (asm_out_file
, "\t.section\t\".fixup\",\"aw\"\n");
17898 ASM_OUTPUT_ALIGN (asm_out_file
, 2);
17899 fprintf (asm_out_file
, "\t.long\t");
17900 assemble_name (asm_out_file
, buf
);
17901 fprintf (asm_out_file
, "\n\t.previous\n");
17905 /* Remove initial .'s to turn a -mcall-aixdesc function
17906 address into the address of the descriptor, not the function
17908 else if (GET_CODE (x
) == SYMBOL_REF
17909 && XSTR (x
, 0)[0] == '.'
17910 && DEFAULT_ABI
== ABI_AIX
)
17912 const char *name
= XSTR (x
, 0);
17913 while (*name
== '.')
17916 fprintf (asm_out_file
, "\t.long\t%s\n", name
);
17920 #endif /* RELOCATABLE_NEEDS_FIXUP */
17921 return default_assemble_integer (x
, size
, aligned_p
);
17924 #if defined (HAVE_GAS_HIDDEN) && !TARGET_MACHO
17925 /* Emit an assembler directive to set symbol visibility for DECL to
17926 VISIBILITY_TYPE. */
17929 rs6000_assemble_visibility (tree decl
, int vis
)
17934 /* Functions need to have their entry point symbol visibility set as
17935 well as their descriptor symbol visibility. */
17936 if (DEFAULT_ABI
== ABI_AIX
17938 && TREE_CODE (decl
) == FUNCTION_DECL
)
17940 static const char * const visibility_types
[] = {
17941 NULL
, "internal", "hidden", "protected"
17944 const char *name
, *type
;
17946 name
= ((* targetm
.strip_name_encoding
)
17947 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
))));
17948 type
= visibility_types
[vis
];
17950 fprintf (asm_out_file
, "\t.%s\t%s\n", type
, name
);
17951 fprintf (asm_out_file
, "\t.%s\t.%s\n", type
, name
);
17954 default_assemble_visibility (decl
, vis
);
17959 rs6000_reverse_condition (enum machine_mode mode
, enum rtx_code code
)
17961 /* Reversal of FP compares takes care -- an ordered compare
17962 becomes an unordered compare and vice versa. */
17963 if (mode
== CCFPmode
17964 && (!flag_finite_math_only
17965 || code
== UNLT
|| code
== UNLE
|| code
== UNGT
|| code
== UNGE
17966 || code
== UNEQ
|| code
== LTGT
))
17967 return reverse_condition_maybe_unordered (code
);
17969 return reverse_condition (code
);
17972 /* Generate a compare for CODE. Return a brand-new rtx that
17973 represents the result of the compare. */
17976 rs6000_generate_compare (rtx cmp
, enum machine_mode mode
)
17978 enum machine_mode comp_mode
;
17979 rtx compare_result
;
17980 enum rtx_code code
= GET_CODE (cmp
);
17981 rtx op0
= XEXP (cmp
, 0);
17982 rtx op1
= XEXP (cmp
, 1);
17984 if (FLOAT_MODE_P (mode
))
17985 comp_mode
= CCFPmode
;
17986 else if (code
== GTU
|| code
== LTU
17987 || code
== GEU
|| code
== LEU
)
17988 comp_mode
= CCUNSmode
;
17989 else if ((code
== EQ
|| code
== NE
)
17990 && unsigned_reg_p (op0
)
17991 && (unsigned_reg_p (op1
)
17992 || (CONST_INT_P (op1
) && INTVAL (op1
) != 0)))
17993 /* These are unsigned values, perhaps there will be a later
17994 ordering compare that can be shared with this one. */
17995 comp_mode
= CCUNSmode
;
17997 comp_mode
= CCmode
;
17999 /* If we have an unsigned compare, make sure we don't have a signed value as
18001 if (comp_mode
== CCUNSmode
&& GET_CODE (op1
) == CONST_INT
18002 && INTVAL (op1
) < 0)
18004 op0
= copy_rtx_if_shared (op0
);
18005 op1
= force_reg (GET_MODE (op0
), op1
);
18006 cmp
= gen_rtx_fmt_ee (code
, GET_MODE (cmp
), op0
, op1
);
18009 /* First, the compare. */
18010 compare_result
= gen_reg_rtx (comp_mode
);
18012 /* E500 FP compare instructions on the GPRs. Yuck! */
18013 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18014 && FLOAT_MODE_P (mode
))
18016 rtx cmp
, or_result
, compare_result2
;
18017 enum machine_mode op_mode
= GET_MODE (op0
);
18020 if (op_mode
== VOIDmode
)
18021 op_mode
= GET_MODE (op1
);
18023 /* First reverse the condition codes that aren't directly supported. */
18031 code
= reverse_condition_maybe_unordered (code
);
18044 gcc_unreachable ();
18047 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
18048 This explains the following mess. */
18056 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18057 ? gen_tstsfeq_gpr (compare_result
, op0
, op1
)
18058 : gen_cmpsfeq_gpr (compare_result
, op0
, op1
);
18062 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18063 ? gen_tstdfeq_gpr (compare_result
, op0
, op1
)
18064 : gen_cmpdfeq_gpr (compare_result
, op0
, op1
);
18068 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18069 ? gen_tsttfeq_gpr (compare_result
, op0
, op1
)
18070 : gen_cmptfeq_gpr (compare_result
, op0
, op1
);
18074 gcc_unreachable ();
18083 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18084 ? gen_tstsfgt_gpr (compare_result
, op0
, op1
)
18085 : gen_cmpsfgt_gpr (compare_result
, op0
, op1
);
18089 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18090 ? gen_tstdfgt_gpr (compare_result
, op0
, op1
)
18091 : gen_cmpdfgt_gpr (compare_result
, op0
, op1
);
18095 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18096 ? gen_tsttfgt_gpr (compare_result
, op0
, op1
)
18097 : gen_cmptfgt_gpr (compare_result
, op0
, op1
);
18101 gcc_unreachable ();
18110 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18111 ? gen_tstsflt_gpr (compare_result
, op0
, op1
)
18112 : gen_cmpsflt_gpr (compare_result
, op0
, op1
);
18116 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18117 ? gen_tstdflt_gpr (compare_result
, op0
, op1
)
18118 : gen_cmpdflt_gpr (compare_result
, op0
, op1
);
18122 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18123 ? gen_tsttflt_gpr (compare_result
, op0
, op1
)
18124 : gen_cmptflt_gpr (compare_result
, op0
, op1
);
18128 gcc_unreachable ();
18133 gcc_unreachable ();
18136 /* Synthesize LE and GE from LT/GT || EQ. */
18137 if (code
== LE
|| code
== GE
)
18141 compare_result2
= gen_reg_rtx (CCFPmode
);
18147 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18148 ? gen_tstsfeq_gpr (compare_result2
, op0
, op1
)
18149 : gen_cmpsfeq_gpr (compare_result2
, op0
, op1
);
18153 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18154 ? gen_tstdfeq_gpr (compare_result2
, op0
, op1
)
18155 : gen_cmpdfeq_gpr (compare_result2
, op0
, op1
);
18159 cmp
= (flag_finite_math_only
&& !flag_trapping_math
)
18160 ? gen_tsttfeq_gpr (compare_result2
, op0
, op1
)
18161 : gen_cmptfeq_gpr (compare_result2
, op0
, op1
);
18165 gcc_unreachable ();
18170 /* OR them together. */
18171 or_result
= gen_reg_rtx (CCFPmode
);
18172 cmp
= gen_e500_cr_ior_compare (or_result
, compare_result
,
18174 compare_result
= or_result
;
18177 code
= reverse_p
? NE
: EQ
;
18183 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
18184 CLOBBERs to match cmptf_internal2 pattern. */
18185 if (comp_mode
== CCFPmode
&& TARGET_XL_COMPAT
18186 && GET_MODE (op0
) == TFmode
18187 && !TARGET_IEEEQUAD
18188 && TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_LONG_DOUBLE_128
)
18189 emit_insn (gen_rtx_PARALLEL (VOIDmode
,
18191 gen_rtx_SET (VOIDmode
,
18193 gen_rtx_COMPARE (comp_mode
, op0
, op1
)),
18194 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18195 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18196 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18197 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18198 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18199 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18200 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18201 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (DFmode
)),
18202 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_SCRATCH (Pmode
)))));
18203 else if (GET_CODE (op1
) == UNSPEC
18204 && XINT (op1
, 1) == UNSPEC_SP_TEST
)
18206 rtx op1b
= XVECEXP (op1
, 0, 0);
18207 comp_mode
= CCEQmode
;
18208 compare_result
= gen_reg_rtx (CCEQmode
);
18210 emit_insn (gen_stack_protect_testdi (compare_result
, op0
, op1b
));
18212 emit_insn (gen_stack_protect_testsi (compare_result
, op0
, op1b
));
18215 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
18216 gen_rtx_COMPARE (comp_mode
, op0
, op1
)));
18219 /* Some kinds of FP comparisons need an OR operation;
18220 under flag_finite_math_only we don't bother. */
18221 if (FLOAT_MODE_P (mode
)
18222 && !flag_finite_math_only
18223 && !(TARGET_HARD_FLOAT
&& !TARGET_FPRS
)
18224 && (code
== LE
|| code
== GE
18225 || code
== UNEQ
|| code
== LTGT
18226 || code
== UNGT
|| code
== UNLT
))
18228 enum rtx_code or1
, or2
;
18229 rtx or1_rtx
, or2_rtx
, compare2_rtx
;
18230 rtx or_result
= gen_reg_rtx (CCEQmode
);
18234 case LE
: or1
= LT
; or2
= EQ
; break;
18235 case GE
: or1
= GT
; or2
= EQ
; break;
18236 case UNEQ
: or1
= UNORDERED
; or2
= EQ
; break;
18237 case LTGT
: or1
= LT
; or2
= GT
; break;
18238 case UNGT
: or1
= UNORDERED
; or2
= GT
; break;
18239 case UNLT
: or1
= UNORDERED
; or2
= LT
; break;
18240 default: gcc_unreachable ();
18242 validate_condition_mode (or1
, comp_mode
);
18243 validate_condition_mode (or2
, comp_mode
);
18244 or1_rtx
= gen_rtx_fmt_ee (or1
, SImode
, compare_result
, const0_rtx
);
18245 or2_rtx
= gen_rtx_fmt_ee (or2
, SImode
, compare_result
, const0_rtx
);
18246 compare2_rtx
= gen_rtx_COMPARE (CCEQmode
,
18247 gen_rtx_IOR (SImode
, or1_rtx
, or2_rtx
),
18249 emit_insn (gen_rtx_SET (VOIDmode
, or_result
, compare2_rtx
));
18251 compare_result
= or_result
;
18255 validate_condition_mode (code
, GET_MODE (compare_result
));
18257 return gen_rtx_fmt_ee (code
, VOIDmode
, compare_result
, const0_rtx
);
18261 /* Emit the RTL for an sISEL pattern. */
18264 rs6000_emit_sISEL (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx operands
[])
18266 rs6000_emit_int_cmove (operands
[0], operands
[1], const1_rtx
, const0_rtx
);
18270 rs6000_emit_sCOND (enum machine_mode mode
, rtx operands
[])
18273 enum machine_mode op_mode
;
18274 enum rtx_code cond_code
;
18275 rtx result
= operands
[0];
18277 if (TARGET_ISEL
&& (mode
== SImode
|| mode
== DImode
))
18279 rs6000_emit_sISEL (mode
, operands
);
18283 condition_rtx
= rs6000_generate_compare (operands
[1], mode
);
18284 cond_code
= GET_CODE (condition_rtx
);
18286 if (FLOAT_MODE_P (mode
)
18287 && !TARGET_FPRS
&& TARGET_HARD_FLOAT
)
18291 PUT_MODE (condition_rtx
, SImode
);
18292 t
= XEXP (condition_rtx
, 0);
18294 gcc_assert (cond_code
== NE
|| cond_code
== EQ
);
18296 if (cond_code
== NE
)
18297 emit_insn (gen_e500_flip_gt_bit (t
, t
));
18299 emit_insn (gen_move_from_CR_gt_bit (result
, t
));
18303 if (cond_code
== NE
18304 || cond_code
== GE
|| cond_code
== LE
18305 || cond_code
== GEU
|| cond_code
== LEU
18306 || cond_code
== ORDERED
|| cond_code
== UNGE
|| cond_code
== UNLE
)
18308 rtx not_result
= gen_reg_rtx (CCEQmode
);
18309 rtx not_op
, rev_cond_rtx
;
18310 enum machine_mode cc_mode
;
18312 cc_mode
= GET_MODE (XEXP (condition_rtx
, 0));
18314 rev_cond_rtx
= gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode
, cond_code
),
18315 SImode
, XEXP (condition_rtx
, 0), const0_rtx
);
18316 not_op
= gen_rtx_COMPARE (CCEQmode
, rev_cond_rtx
, const0_rtx
);
18317 emit_insn (gen_rtx_SET (VOIDmode
, not_result
, not_op
));
18318 condition_rtx
= gen_rtx_EQ (VOIDmode
, not_result
, const0_rtx
);
18321 op_mode
= GET_MODE (XEXP (operands
[1], 0));
18322 if (op_mode
== VOIDmode
)
18323 op_mode
= GET_MODE (XEXP (operands
[1], 1));
18325 if (TARGET_POWERPC64
&& (op_mode
== DImode
|| FLOAT_MODE_P (mode
)))
18327 PUT_MODE (condition_rtx
, DImode
);
18328 convert_move (result
, condition_rtx
, 0);
18332 PUT_MODE (condition_rtx
, SImode
);
18333 emit_insn (gen_rtx_SET (VOIDmode
, result
, condition_rtx
));
18337 /* Emit a branch of kind CODE to location LOC. */
18340 rs6000_emit_cbranch (enum machine_mode mode
, rtx operands
[])
18342 rtx condition_rtx
, loc_ref
;
18344 condition_rtx
= rs6000_generate_compare (operands
[0], mode
);
18345 loc_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
18346 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
18347 gen_rtx_IF_THEN_ELSE (VOIDmode
, condition_rtx
,
18348 loc_ref
, pc_rtx
)));
18351 /* Return the string to output a conditional branch to LABEL, which is
18352 the operand template of the label, or NULL if the branch is really a
18353 conditional return.
18355 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
18356 condition code register and its mode specifies what kind of
18357 comparison we made.
18359 REVERSED is nonzero if we should reverse the sense of the comparison.
18361 INSN is the insn. */
18364 output_cbranch (rtx op
, const char *label
, int reversed
, rtx insn
)
18366 static char string
[64];
18367 enum rtx_code code
= GET_CODE (op
);
18368 rtx cc_reg
= XEXP (op
, 0);
18369 enum machine_mode mode
= GET_MODE (cc_reg
);
18370 int cc_regno
= REGNO (cc_reg
) - CR0_REGNO
;
18371 int need_longbranch
= label
!= NULL
&& get_attr_length (insn
) == 8;
18372 int really_reversed
= reversed
^ need_longbranch
;
18378 validate_condition_mode (code
, mode
);
18380 /* Work out which way this really branches. We could use
18381 reverse_condition_maybe_unordered here always but this
18382 makes the resulting assembler clearer. */
18383 if (really_reversed
)
18385 /* Reversal of FP compares takes care -- an ordered compare
18386 becomes an unordered compare and vice versa. */
18387 if (mode
== CCFPmode
)
18388 code
= reverse_condition_maybe_unordered (code
);
18390 code
= reverse_condition (code
);
18393 if ((!TARGET_FPRS
&& TARGET_HARD_FLOAT
) && mode
== CCFPmode
)
18395 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
18400 /* Opposite of GT. */
18409 gcc_unreachable ();
18415 /* Not all of these are actually distinct opcodes, but
18416 we distinguish them for clarity of the resulting assembler. */
18417 case NE
: case LTGT
:
18418 ccode
= "ne"; break;
18419 case EQ
: case UNEQ
:
18420 ccode
= "eq"; break;
18422 ccode
= "ge"; break;
18423 case GT
: case GTU
: case UNGT
:
18424 ccode
= "gt"; break;
18426 ccode
= "le"; break;
18427 case LT
: case LTU
: case UNLT
:
18428 ccode
= "lt"; break;
18429 case UNORDERED
: ccode
= "un"; break;
18430 case ORDERED
: ccode
= "nu"; break;
18431 case UNGE
: ccode
= "nl"; break;
18432 case UNLE
: ccode
= "ng"; break;
18434 gcc_unreachable ();
18437 /* Maybe we have a guess as to how likely the branch is. */
18439 note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
);
18440 if (note
!= NULL_RTX
)
18442 /* PROB is the difference from 50%. */
18443 int prob
= XINT (note
, 0) - REG_BR_PROB_BASE
/ 2;
18445 /* Only hint for highly probable/improbable branches on newer
18446 cpus as static prediction overrides processor dynamic
18447 prediction. For older cpus we may as well always hint, but
18448 assume not taken for branches that are very close to 50% as a
18449 mispredicted taken branch is more expensive than a
18450 mispredicted not-taken branch. */
18451 if (rs6000_always_hint
18452 || (abs (prob
) > REG_BR_PROB_BASE
/ 100 * 48
18453 && br_prob_note_reliable_p (note
)))
18455 if (abs (prob
) > REG_BR_PROB_BASE
/ 20
18456 && ((prob
> 0) ^ need_longbranch
))
18464 s
+= sprintf (s
, "b%slr%s ", ccode
, pred
);
18466 s
+= sprintf (s
, "b%s%s ", ccode
, pred
);
18468 /* We need to escape any '%' characters in the reg_names string.
18469 Assume they'd only be the first character.... */
18470 if (reg_names
[cc_regno
+ CR0_REGNO
][0] == '%')
18472 s
+= sprintf (s
, "%s", reg_names
[cc_regno
+ CR0_REGNO
]);
18476 /* If the branch distance was too far, we may have to use an
18477 unconditional branch to go the distance. */
18478 if (need_longbranch
)
18479 s
+= sprintf (s
, ",$+8\n\tb %s", label
);
18481 s
+= sprintf (s
, ",%s", label
);
18487 /* Return the string to flip the GT bit on a CR. */
18489 output_e500_flip_gt_bit (rtx dst
, rtx src
)
18491 static char string
[64];
18494 gcc_assert (GET_CODE (dst
) == REG
&& CR_REGNO_P (REGNO (dst
))
18495 && GET_CODE (src
) == REG
&& CR_REGNO_P (REGNO (src
)));
18498 a
= 4 * (REGNO (dst
) - CR0_REGNO
) + 1;
18499 b
= 4 * (REGNO (src
) - CR0_REGNO
) + 1;
18501 sprintf (string
, "crnot %d,%d", a
, b
);
18505 /* Return insn for VSX or Altivec comparisons. */
18508 rs6000_emit_vector_compare_inner (enum rtx_code code
, rtx op0
, rtx op1
)
18511 enum machine_mode mode
= GET_MODE (op0
);
18519 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
18529 mask
= gen_reg_rtx (mode
);
18530 emit_insn (gen_rtx_SET (VOIDmode
,
18532 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
18539 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
18540 DMODE is expected destination mode. This is a recursive function. */
18543 rs6000_emit_vector_compare (enum rtx_code rcode
,
18545 enum machine_mode dmode
)
18548 bool swap_operands
= false;
18549 bool try_again
= false;
18551 gcc_assert (VECTOR_UNIT_ALTIVEC_OR_VSX_P (dmode
));
18552 gcc_assert (GET_MODE (op0
) == GET_MODE (op1
));
18554 /* See if the comparison works as is. */
18555 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
18563 swap_operands
= true;
18568 swap_operands
= true;
18576 /* Invert condition and try again.
18577 e.g., A != B becomes ~(A==B). */
18579 enum rtx_code rev_code
;
18580 enum insn_code nor_code
;
18583 rev_code
= reverse_condition_maybe_unordered (rcode
);
18584 if (rev_code
== UNKNOWN
)
18587 nor_code
= optab_handler (one_cmpl_optab
, dmode
);
18588 if (nor_code
== CODE_FOR_nothing
)
18591 mask2
= rs6000_emit_vector_compare (rev_code
, op0
, op1
, dmode
);
18595 mask
= gen_reg_rtx (dmode
);
18596 emit_insn (GEN_FCN (nor_code
) (mask
, mask2
));
18604 /* Try GT/GTU/LT/LTU OR EQ */
18607 enum insn_code ior_code
;
18608 enum rtx_code new_code
;
18629 gcc_unreachable ();
18632 ior_code
= optab_handler (ior_optab
, dmode
);
18633 if (ior_code
== CODE_FOR_nothing
)
18636 c_rtx
= rs6000_emit_vector_compare (new_code
, op0
, op1
, dmode
);
18640 eq_rtx
= rs6000_emit_vector_compare (EQ
, op0
, op1
, dmode
);
18644 mask
= gen_reg_rtx (dmode
);
18645 emit_insn (GEN_FCN (ior_code
) (mask
, c_rtx
, eq_rtx
));
18663 mask
= rs6000_emit_vector_compare_inner (rcode
, op0
, op1
);
18668 /* You only get two chances. */
18672 /* Emit vector conditional expression. DEST is destination. OP_TRUE and
18673 OP_FALSE are two VEC_COND_EXPR operands. CC_OP0 and CC_OP1 are the two
18674 operands for the relation operation COND. */
18677 rs6000_emit_vector_cond_expr (rtx dest
, rtx op_true
, rtx op_false
,
18678 rtx cond
, rtx cc_op0
, rtx cc_op1
)
18680 enum machine_mode dest_mode
= GET_MODE (dest
);
18681 enum machine_mode mask_mode
= GET_MODE (cc_op0
);
18682 enum rtx_code rcode
= GET_CODE (cond
);
18683 enum machine_mode cc_mode
= CCmode
;
18687 bool invert_move
= false;
18689 if (VECTOR_UNIT_NONE_P (dest_mode
))
18692 gcc_assert (GET_MODE_SIZE (dest_mode
) == GET_MODE_SIZE (mask_mode
)
18693 && GET_MODE_NUNITS (dest_mode
) == GET_MODE_NUNITS (mask_mode
));
18697 /* Swap operands if we can, and fall back to doing the operation as
18698 specified, and doing a NOR to invert the test. */
18704 /* Invert condition and try again.
18705 e.g., A = (B != C) ? D : E becomes A = (B == C) ? E : D. */
18706 invert_move
= true;
18707 rcode
= reverse_condition_maybe_unordered (rcode
);
18708 if (rcode
== UNKNOWN
)
18712 /* Mark unsigned tests with CCUNSmode. */
18717 cc_mode
= CCUNSmode
;
18724 /* Get the vector mask for the given relational operations. */
18725 mask
= rs6000_emit_vector_compare (rcode
, cc_op0
, cc_op1
, mask_mode
);
18733 op_true
= op_false
;
18737 cond2
= gen_rtx_fmt_ee (NE
, cc_mode
, gen_lowpart (dest_mode
, mask
),
18738 CONST0_RTX (dest_mode
));
18739 emit_insn (gen_rtx_SET (VOIDmode
,
18741 gen_rtx_IF_THEN_ELSE (dest_mode
,
18748 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
18749 operands of the last comparison is nonzero/true, FALSE_COND if it
18750 is zero/false. Return 0 if the hardware has no such operation. */
18753 rs6000_emit_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18755 enum rtx_code code
= GET_CODE (op
);
18756 rtx op0
= XEXP (op
, 0);
18757 rtx op1
= XEXP (op
, 1);
18758 REAL_VALUE_TYPE c1
;
18759 enum machine_mode compare_mode
= GET_MODE (op0
);
18760 enum machine_mode result_mode
= GET_MODE (dest
);
18762 bool is_against_zero
;
18764 /* These modes should always match. */
18765 if (GET_MODE (op1
) != compare_mode
18766 /* In the isel case however, we can use a compare immediate, so
18767 op1 may be a small constant. */
18768 && (!TARGET_ISEL
|| !short_cint_operand (op1
, VOIDmode
)))
18770 if (GET_MODE (true_cond
) != result_mode
)
18772 if (GET_MODE (false_cond
) != result_mode
)
18775 /* Don't allow using floating point comparisons for integer results for
18777 if (FLOAT_MODE_P (compare_mode
) && !FLOAT_MODE_P (result_mode
))
18780 /* First, work out if the hardware can do this at all, or
18781 if it's too slow.... */
18782 if (!FLOAT_MODE_P (compare_mode
))
18785 return rs6000_emit_int_cmove (dest
, op
, true_cond
, false_cond
);
18788 else if (TARGET_HARD_FLOAT
&& !TARGET_FPRS
18789 && SCALAR_FLOAT_MODE_P (compare_mode
))
18792 is_against_zero
= op1
== CONST0_RTX (compare_mode
);
18794 /* A floating-point subtract might overflow, underflow, or produce
18795 an inexact result, thus changing the floating-point flags, so it
18796 can't be generated if we care about that. It's safe if one side
18797 of the construct is zero, since then no subtract will be
18799 if (SCALAR_FLOAT_MODE_P (compare_mode
)
18800 && flag_trapping_math
&& ! is_against_zero
)
18803 /* Eliminate half of the comparisons by switching operands, this
18804 makes the remaining code simpler. */
18805 if (code
== UNLT
|| code
== UNGT
|| code
== UNORDERED
|| code
== NE
18806 || code
== LTGT
|| code
== LT
|| code
== UNLE
)
18808 code
= reverse_condition_maybe_unordered (code
);
18810 true_cond
= false_cond
;
18814 /* UNEQ and LTGT take four instructions for a comparison with zero,
18815 it'll probably be faster to use a branch here too. */
18816 if (code
== UNEQ
&& HONOR_NANS (compare_mode
))
18819 if (GET_CODE (op1
) == CONST_DOUBLE
)
18820 REAL_VALUE_FROM_CONST_DOUBLE (c1
, op1
);
18822 /* We're going to try to implement comparisons by performing
18823 a subtract, then comparing against zero. Unfortunately,
18824 Inf - Inf is NaN which is not zero, and so if we don't
18825 know that the operand is finite and the comparison
18826 would treat EQ different to UNORDERED, we can't do it. */
18827 if (HONOR_INFINITIES (compare_mode
)
18828 && code
!= GT
&& code
!= UNGE
18829 && (GET_CODE (op1
) != CONST_DOUBLE
|| real_isinf (&c1
))
18830 /* Constructs of the form (a OP b ? a : b) are safe. */
18831 && ((! rtx_equal_p (op0
, false_cond
) && ! rtx_equal_p (op1
, false_cond
))
18832 || (! rtx_equal_p (op0
, true_cond
)
18833 && ! rtx_equal_p (op1
, true_cond
))))
18836 /* At this point we know we can use fsel. */
18838 /* Reduce the comparison to a comparison against zero. */
18839 if (! is_against_zero
)
18841 temp
= gen_reg_rtx (compare_mode
);
18842 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18843 gen_rtx_MINUS (compare_mode
, op0
, op1
)));
18845 op1
= CONST0_RTX (compare_mode
);
18848 /* If we don't care about NaNs we can reduce some of the comparisons
18849 down to faster ones. */
18850 if (! HONOR_NANS (compare_mode
))
18856 true_cond
= false_cond
;
18869 /* Now, reduce everything down to a GE. */
18876 temp
= gen_reg_rtx (compare_mode
);
18877 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18882 temp
= gen_reg_rtx (compare_mode
);
18883 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_ABS (compare_mode
, op0
)));
18888 temp
= gen_reg_rtx (compare_mode
);
18889 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18890 gen_rtx_NEG (compare_mode
,
18891 gen_rtx_ABS (compare_mode
, op0
))));
18896 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
18897 temp
= gen_reg_rtx (result_mode
);
18898 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18899 gen_rtx_IF_THEN_ELSE (result_mode
,
18900 gen_rtx_GE (VOIDmode
,
18902 true_cond
, false_cond
)));
18903 false_cond
= true_cond
;
18906 temp
= gen_reg_rtx (compare_mode
);
18907 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18912 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
18913 temp
= gen_reg_rtx (result_mode
);
18914 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
18915 gen_rtx_IF_THEN_ELSE (result_mode
,
18916 gen_rtx_GE (VOIDmode
,
18918 true_cond
, false_cond
)));
18919 true_cond
= false_cond
;
18922 temp
= gen_reg_rtx (compare_mode
);
18923 emit_insn (gen_rtx_SET (VOIDmode
, temp
, gen_rtx_NEG (compare_mode
, op0
)));
18928 gcc_unreachable ();
18931 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
18932 gen_rtx_IF_THEN_ELSE (result_mode
,
18933 gen_rtx_GE (VOIDmode
,
18935 true_cond
, false_cond
)));
18939 /* Same as above, but for ints (isel). */
18942 rs6000_emit_int_cmove (rtx dest
, rtx op
, rtx true_cond
, rtx false_cond
)
18944 rtx condition_rtx
, cr
;
18945 enum machine_mode mode
= GET_MODE (dest
);
18946 enum rtx_code cond_code
;
18947 rtx (*isel_func
) (rtx
, rtx
, rtx
, rtx
, rtx
);
18950 if (mode
!= SImode
&& (!TARGET_POWERPC64
|| mode
!= DImode
))
18953 /* We still have to do the compare, because isel doesn't do a
18954 compare, it just looks at the CRx bits set by a previous compare
18956 condition_rtx
= rs6000_generate_compare (op
, mode
);
18957 cond_code
= GET_CODE (condition_rtx
);
18958 cr
= XEXP (condition_rtx
, 0);
18959 signedp
= GET_MODE (cr
) == CCmode
;
18961 isel_func
= (mode
== SImode
18962 ? (signedp
? gen_isel_signed_si
: gen_isel_unsigned_si
)
18963 : (signedp
? gen_isel_signed_di
: gen_isel_unsigned_di
));
18967 case LT
: case GT
: case LTU
: case GTU
: case EQ
:
18968 /* isel handles these directly. */
18972 /* We need to swap the sense of the comparison. */
18975 true_cond
= false_cond
;
18977 PUT_CODE (condition_rtx
, reverse_condition (cond_code
));
18982 false_cond
= force_reg (mode
, false_cond
);
18983 if (true_cond
!= const0_rtx
)
18984 true_cond
= force_reg (mode
, true_cond
);
18986 emit_insn (isel_func (dest
, condition_rtx
, true_cond
, false_cond
, cr
));
18992 output_isel (rtx
*operands
)
18994 enum rtx_code code
;
18996 code
= GET_CODE (operands
[1]);
18998 if (code
== GE
|| code
== GEU
|| code
== LE
|| code
== LEU
|| code
== NE
)
19000 gcc_assert (GET_CODE (operands
[2]) == REG
19001 && GET_CODE (operands
[3]) == REG
);
19002 PUT_CODE (operands
[1], reverse_condition (code
));
19003 return "isel %0,%3,%2,%j1";
19006 return "isel %0,%2,%3,%j1";
19010 rs6000_emit_minmax (rtx dest
, enum rtx_code code
, rtx op0
, rtx op1
)
19012 enum machine_mode mode
= GET_MODE (op0
);
19016 /* VSX/altivec have direct min/max insns. */
19017 if ((code
== SMAX
|| code
== SMIN
)
19018 && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode
)
19019 || (mode
== SFmode
&& VECTOR_UNIT_VSX_P (DFmode
))))
19021 emit_insn (gen_rtx_SET (VOIDmode
,
19023 gen_rtx_fmt_ee (code
, mode
, op0
, op1
)));
19027 if (code
== SMAX
|| code
== SMIN
)
19032 if (code
== SMAX
|| code
== UMAX
)
19033 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19034 op0
, op1
, mode
, 0);
19036 target
= emit_conditional_move (dest
, c
, op0
, op1
, mode
,
19037 op1
, op0
, mode
, 0);
19038 gcc_assert (target
);
19039 if (target
!= dest
)
19040 emit_move_insn (dest
, target
);
19043 /* A subroutine of the atomic operation splitters. Jump to LABEL if
19044 COND is true. Mark the jump as unlikely to be taken. */
19047 emit_unlikely_jump (rtx cond
, rtx label
)
19049 int very_unlikely
= REG_BR_PROB_BASE
/ 100 - 1;
19052 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, label
, pc_rtx
);
19053 x
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, x
));
19054 add_int_reg_note (x
, REG_BR_PROB
, very_unlikely
);
19057 /* A subroutine of the atomic operation splitters. Emit a load-locked
19058 instruction in MODE. For QI/HImode, possibly use a pattern than includes
19059 the zero_extend operation. */
19062 emit_load_locked (enum machine_mode mode
, rtx reg
, rtx mem
)
19064 rtx (*fn
) (rtx
, rtx
) = NULL
;
19069 fn
= gen_load_lockedqi
;
19072 fn
= gen_load_lockedhi
;
19075 if (GET_MODE (mem
) == QImode
)
19076 fn
= gen_load_lockedqi_si
;
19077 else if (GET_MODE (mem
) == HImode
)
19078 fn
= gen_load_lockedhi_si
;
19080 fn
= gen_load_lockedsi
;
19083 fn
= gen_load_lockeddi
;
19086 fn
= gen_load_lockedti
;
19089 gcc_unreachable ();
19091 emit_insn (fn (reg
, mem
));
19094 /* A subroutine of the atomic operation splitters. Emit a store-conditional
19095 instruction in MODE. */
19098 emit_store_conditional (enum machine_mode mode
, rtx res
, rtx mem
, rtx val
)
19100 rtx (*fn
) (rtx
, rtx
, rtx
) = NULL
;
19105 fn
= gen_store_conditionalqi
;
19108 fn
= gen_store_conditionalhi
;
19111 fn
= gen_store_conditionalsi
;
19114 fn
= gen_store_conditionaldi
;
19117 fn
= gen_store_conditionalti
;
19120 gcc_unreachable ();
19123 /* Emit sync before stwcx. to address PPC405 Erratum. */
19124 if (PPC405_ERRATUM77
)
19125 emit_insn (gen_hwsync ());
19127 emit_insn (fn (res
, mem
, val
));
19130 /* Expand barriers before and after a load_locked/store_cond sequence. */
19133 rs6000_pre_atomic_barrier (rtx mem
, enum memmodel model
)
19135 rtx addr
= XEXP (mem
, 0);
19136 int strict_p
= (reload_in_progress
|| reload_completed
);
19138 if (!legitimate_indirect_address_p (addr
, strict_p
)
19139 && !legitimate_indexed_address_p (addr
, strict_p
))
19141 addr
= force_reg (Pmode
, addr
);
19142 mem
= replace_equiv_address_nv (mem
, addr
);
19147 case MEMMODEL_RELAXED
:
19148 case MEMMODEL_CONSUME
:
19149 case MEMMODEL_ACQUIRE
:
19151 case MEMMODEL_RELEASE
:
19152 case MEMMODEL_ACQ_REL
:
19153 emit_insn (gen_lwsync ());
19155 case MEMMODEL_SEQ_CST
:
19156 emit_insn (gen_hwsync ());
19159 gcc_unreachable ();
19165 rs6000_post_atomic_barrier (enum memmodel model
)
19169 case MEMMODEL_RELAXED
:
19170 case MEMMODEL_CONSUME
:
19171 case MEMMODEL_RELEASE
:
19173 case MEMMODEL_ACQUIRE
:
19174 case MEMMODEL_ACQ_REL
:
19175 case MEMMODEL_SEQ_CST
:
19176 emit_insn (gen_isync ());
19179 gcc_unreachable ();
19183 /* A subroutine of the various atomic expanders. For sub-word operations,
19184 we must adjust things to operate on SImode. Given the original MEM,
19185 return a new aligned memory. Also build and return the quantities by
19186 which to shift and mask. */
19189 rs6000_adjust_atomic_subword (rtx orig_mem
, rtx
*pshift
, rtx
*pmask
)
19191 rtx addr
, align
, shift
, mask
, mem
;
19192 HOST_WIDE_INT shift_mask
;
19193 enum machine_mode mode
= GET_MODE (orig_mem
);
19195 /* For smaller modes, we have to implement this via SImode. */
19196 shift_mask
= (mode
== QImode
? 0x18 : 0x10);
19198 addr
= XEXP (orig_mem
, 0);
19199 addr
= force_reg (GET_MODE (addr
), addr
);
19201 /* Aligned memory containing subword. Generate a new memory. We
19202 do not want any of the existing MEM_ATTR data, as we're now
19203 accessing memory outside the original object. */
19204 align
= expand_simple_binop (Pmode
, AND
, addr
, GEN_INT (-4),
19205 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19206 mem
= gen_rtx_MEM (SImode
, align
);
19207 MEM_VOLATILE_P (mem
) = MEM_VOLATILE_P (orig_mem
);
19208 if (MEM_ALIAS_SET (orig_mem
) == ALIAS_SET_MEMORY_BARRIER
)
19209 set_mem_alias_set (mem
, ALIAS_SET_MEMORY_BARRIER
);
19211 /* Shift amount for subword relative to aligned word. */
19212 shift
= gen_reg_rtx (SImode
);
19213 addr
= gen_lowpart (SImode
, addr
);
19214 emit_insn (gen_rlwinm (shift
, addr
, GEN_INT (3), GEN_INT (shift_mask
)));
19215 if (WORDS_BIG_ENDIAN
)
19216 shift
= expand_simple_binop (SImode
, XOR
, shift
, GEN_INT (shift_mask
),
19217 shift
, 1, OPTAB_LIB_WIDEN
);
19220 /* Mask for insertion. */
19221 mask
= expand_simple_binop (SImode
, ASHIFT
, GEN_INT (GET_MODE_MASK (mode
)),
19222 shift
, NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19228 /* A subroutine of the various atomic expanders. For sub-word operands,
19229 combine OLDVAL and NEWVAL via MASK. Returns a new pseduo. */
19232 rs6000_mask_atomic_subword (rtx oldval
, rtx newval
, rtx mask
)
19236 x
= gen_reg_rtx (SImode
);
19237 emit_insn (gen_rtx_SET (VOIDmode
, x
,
19238 gen_rtx_AND (SImode
,
19239 gen_rtx_NOT (SImode
, mask
),
19242 x
= expand_simple_binop (SImode
, IOR
, newval
, x
, x
, 1, OPTAB_LIB_WIDEN
);
19247 /* A subroutine of the various atomic expanders. For sub-word operands,
19248 extract WIDE to NARROW via SHIFT. */
19251 rs6000_finish_atomic_subword (rtx narrow
, rtx wide
, rtx shift
)
19253 wide
= expand_simple_binop (SImode
, LSHIFTRT
, wide
, shift
,
19254 wide
, 1, OPTAB_LIB_WIDEN
);
19255 emit_move_insn (narrow
, gen_lowpart (GET_MODE (narrow
), wide
));
19258 /* Expand an atomic compare and swap operation. */
19261 rs6000_expand_atomic_compare_and_swap (rtx operands
[])
19263 rtx boolval
, retval
, mem
, oldval
, newval
, cond
;
19264 rtx label1
, label2
, x
, mask
, shift
;
19265 enum machine_mode mode
, orig_mode
;
19266 enum memmodel mod_s
, mod_f
;
19269 boolval
= operands
[0];
19270 retval
= operands
[1];
19272 oldval
= operands
[3];
19273 newval
= operands
[4];
19274 is_weak
= (INTVAL (operands
[5]) != 0);
19275 mod_s
= (enum memmodel
) INTVAL (operands
[6]);
19276 mod_f
= (enum memmodel
) INTVAL (operands
[7]);
19277 orig_mode
= mode
= GET_MODE (mem
);
19279 mask
= shift
= NULL_RTX
;
19280 if (mode
== QImode
|| mode
== HImode
)
19282 /* Before power8, we didn't have access to lbarx/lharx, so generate a
19283 lwarx and shift/mask operations. With power8, we need to do the
19284 comparison in SImode, but the store is still done in QI/HImode. */
19285 oldval
= convert_modes (SImode
, mode
, oldval
, 1);
19287 if (!TARGET_SYNC_HI_QI
)
19289 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19291 /* Shift and mask OLDVAL into position with the word. */
19292 oldval
= expand_simple_binop (SImode
, ASHIFT
, oldval
, shift
,
19293 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19295 /* Shift and mask NEWVAL into position within the word. */
19296 newval
= convert_modes (SImode
, mode
, newval
, 1);
19297 newval
= expand_simple_binop (SImode
, ASHIFT
, newval
, shift
,
19298 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19301 /* Prepare to adjust the return value. */
19302 retval
= gen_reg_rtx (SImode
);
19305 else if (reg_overlap_mentioned_p (retval
, oldval
))
19306 oldval
= copy_to_reg (oldval
);
19308 mem
= rs6000_pre_atomic_barrier (mem
, mod_s
);
19313 label1
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19314 emit_label (XEXP (label1
, 0));
19316 label2
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19318 emit_load_locked (mode
, retval
, mem
);
19323 x
= expand_simple_binop (SImode
, AND
, retval
, mask
,
19324 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19327 cond
= gen_reg_rtx (CCmode
);
19328 /* If we have TImode, synthesize a comparison. */
19329 if (mode
!= TImode
)
19330 x
= gen_rtx_COMPARE (CCmode
, x
, oldval
);
19333 rtx xor1_result
= gen_reg_rtx (DImode
);
19334 rtx xor2_result
= gen_reg_rtx (DImode
);
19335 rtx or_result
= gen_reg_rtx (DImode
);
19336 rtx new_word0
= simplify_gen_subreg (DImode
, x
, TImode
, 0);
19337 rtx new_word1
= simplify_gen_subreg (DImode
, x
, TImode
, 8);
19338 rtx old_word0
= simplify_gen_subreg (DImode
, oldval
, TImode
, 0);
19339 rtx old_word1
= simplify_gen_subreg (DImode
, oldval
, TImode
, 8);
19341 emit_insn (gen_xordi3 (xor1_result
, new_word0
, old_word0
));
19342 emit_insn (gen_xordi3 (xor2_result
, new_word1
, old_word1
));
19343 emit_insn (gen_iordi3 (or_result
, xor1_result
, xor2_result
));
19344 x
= gen_rtx_COMPARE (CCmode
, or_result
, const0_rtx
);
19347 emit_insn (gen_rtx_SET (VOIDmode
, cond
, x
));
19349 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19350 emit_unlikely_jump (x
, label2
);
19354 x
= rs6000_mask_atomic_subword (retval
, newval
, mask
);
19356 emit_store_conditional (orig_mode
, cond
, mem
, x
);
19360 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19361 emit_unlikely_jump (x
, label1
);
19364 if (mod_f
!= MEMMODEL_RELAXED
)
19365 emit_label (XEXP (label2
, 0));
19367 rs6000_post_atomic_barrier (mod_s
);
19369 if (mod_f
== MEMMODEL_RELAXED
)
19370 emit_label (XEXP (label2
, 0));
19373 rs6000_finish_atomic_subword (operands
[1], retval
, shift
);
19374 else if (mode
!= GET_MODE (operands
[1]))
19375 convert_move (operands
[1], retval
, 1);
19377 /* In all cases, CR0 contains EQ on success, and NE on failure. */
19378 x
= gen_rtx_EQ (SImode
, cond
, const0_rtx
);
19379 emit_insn (gen_rtx_SET (VOIDmode
, boolval
, x
));
19382 /* Expand an atomic exchange operation. */
19385 rs6000_expand_atomic_exchange (rtx operands
[])
19387 rtx retval
, mem
, val
, cond
;
19388 enum machine_mode mode
;
19389 enum memmodel model
;
19390 rtx label
, x
, mask
, shift
;
19392 retval
= operands
[0];
19395 model
= (enum memmodel
) INTVAL (operands
[3]);
19396 mode
= GET_MODE (mem
);
19398 mask
= shift
= NULL_RTX
;
19399 if (!TARGET_SYNC_HI_QI
&& (mode
== QImode
|| mode
== HImode
))
19401 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19403 /* Shift and mask VAL into position with the word. */
19404 val
= convert_modes (SImode
, mode
, val
, 1);
19405 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19406 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19408 /* Prepare to adjust the return value. */
19409 retval
= gen_reg_rtx (SImode
);
19413 mem
= rs6000_pre_atomic_barrier (mem
, model
);
19415 label
= gen_rtx_LABEL_REF (VOIDmode
, gen_label_rtx ());
19416 emit_label (XEXP (label
, 0));
19418 emit_load_locked (mode
, retval
, mem
);
19422 x
= rs6000_mask_atomic_subword (retval
, val
, mask
);
19424 cond
= gen_reg_rtx (CCmode
);
19425 emit_store_conditional (mode
, cond
, mem
, x
);
19427 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19428 emit_unlikely_jump (x
, label
);
19430 rs6000_post_atomic_barrier (model
);
19433 rs6000_finish_atomic_subword (operands
[0], retval
, shift
);
19436 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
19437 to perform. MEM is the memory on which to operate. VAL is the second
19438 operand of the binary operator. BEFORE and AFTER are optional locations to
19439 return the value of MEM either before of after the operation. MODEL_RTX
19440 is a CONST_INT containing the memory model to use. */
19443 rs6000_expand_atomic_op (enum rtx_code code
, rtx mem
, rtx val
,
19444 rtx orig_before
, rtx orig_after
, rtx model_rtx
)
19446 enum memmodel model
= (enum memmodel
) INTVAL (model_rtx
);
19447 enum machine_mode mode
= GET_MODE (mem
);
19448 enum machine_mode store_mode
= mode
;
19449 rtx label
, x
, cond
, mask
, shift
;
19450 rtx before
= orig_before
, after
= orig_after
;
19452 mask
= shift
= NULL_RTX
;
19453 /* On power8, we want to use SImode for the operation. On previous systems,
19454 use the operation in a subword and shift/mask to get the proper byte or
19456 if (mode
== QImode
|| mode
== HImode
)
19458 if (TARGET_SYNC_HI_QI
)
19460 val
= convert_modes (SImode
, mode
, val
, 1);
19462 /* Prepare to adjust the return value. */
19463 before
= gen_reg_rtx (SImode
);
19465 after
= gen_reg_rtx (SImode
);
19470 mem
= rs6000_adjust_atomic_subword (mem
, &shift
, &mask
);
19472 /* Shift and mask VAL into position with the word. */
19473 val
= convert_modes (SImode
, mode
, val
, 1);
19474 val
= expand_simple_binop (SImode
, ASHIFT
, val
, shift
,
19475 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19481 /* We've already zero-extended VAL. That is sufficient to
19482 make certain that it does not affect other bits. */
19487 /* If we make certain that all of the other bits in VAL are
19488 set, that will be sufficient to not affect other bits. */
19489 x
= gen_rtx_NOT (SImode
, mask
);
19490 x
= gen_rtx_IOR (SImode
, x
, val
);
19491 emit_insn (gen_rtx_SET (VOIDmode
, val
, x
));
19498 /* These will all affect bits outside the field and need
19499 adjustment via MASK within the loop. */
19503 gcc_unreachable ();
19506 /* Prepare to adjust the return value. */
19507 before
= gen_reg_rtx (SImode
);
19509 after
= gen_reg_rtx (SImode
);
19510 store_mode
= mode
= SImode
;
19514 mem
= rs6000_pre_atomic_barrier (mem
, model
);
19516 label
= gen_label_rtx ();
19517 emit_label (label
);
19518 label
= gen_rtx_LABEL_REF (VOIDmode
, label
);
19520 if (before
== NULL_RTX
)
19521 before
= gen_reg_rtx (mode
);
19523 emit_load_locked (mode
, before
, mem
);
19527 x
= expand_simple_binop (mode
, AND
, before
, val
,
19528 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19529 after
= expand_simple_unop (mode
, NOT
, x
, after
, 1);
19533 after
= expand_simple_binop (mode
, code
, before
, val
,
19534 after
, 1, OPTAB_LIB_WIDEN
);
19540 x
= expand_simple_binop (SImode
, AND
, after
, mask
,
19541 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
19542 x
= rs6000_mask_atomic_subword (before
, x
, mask
);
19544 else if (store_mode
!= mode
)
19545 x
= convert_modes (store_mode
, mode
, x
, 1);
19547 cond
= gen_reg_rtx (CCmode
);
19548 emit_store_conditional (store_mode
, cond
, mem
, x
);
19550 x
= gen_rtx_NE (VOIDmode
, cond
, const0_rtx
);
19551 emit_unlikely_jump (x
, label
);
19553 rs6000_post_atomic_barrier (model
);
19557 /* QImode/HImode on machines without lbarx/lharx where we do a lwarx and
19558 then do the calcuations in a SImode register. */
19560 rs6000_finish_atomic_subword (orig_before
, before
, shift
);
19562 rs6000_finish_atomic_subword (orig_after
, after
, shift
);
19564 else if (store_mode
!= mode
)
19566 /* QImode/HImode on machines with lbarx/lharx where we do the native
19567 operation and then do the calcuations in a SImode register. */
19569 convert_move (orig_before
, before
, 1);
19571 convert_move (orig_after
, after
, 1);
19573 else if (orig_after
&& after
!= orig_after
)
19574 emit_move_insn (orig_after
, after
);
19577 /* Emit instructions to move SRC to DST. Called by splitters for
19578 multi-register moves. It will emit at most one instruction for
19579 each register that is accessed; that is, it won't emit li/lis pairs
19580 (or equivalent for 64-bit code). One of SRC or DST must be a hard
19584 rs6000_split_multireg_move (rtx dst
, rtx src
)
19586 /* The register number of the first register being moved. */
19588 /* The mode that is to be moved. */
19589 enum machine_mode mode
;
19590 /* The mode that the move is being done in, and its size. */
19591 enum machine_mode reg_mode
;
19593 /* The number of registers that will be moved. */
19596 reg
= REG_P (dst
) ? REGNO (dst
) : REGNO (src
);
19597 mode
= GET_MODE (dst
);
19598 nregs
= hard_regno_nregs
[reg
][mode
];
19599 if (FP_REGNO_P (reg
))
19600 reg_mode
= DECIMAL_FLOAT_MODE_P (mode
) ? DDmode
:
19601 ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
) ? DFmode
: SFmode
);
19602 else if (ALTIVEC_REGNO_P (reg
))
19603 reg_mode
= V16QImode
;
19604 else if (TARGET_E500_DOUBLE
&& mode
== TFmode
)
19607 reg_mode
= word_mode
;
19608 reg_mode_size
= GET_MODE_SIZE (reg_mode
);
19610 gcc_assert (reg_mode_size
* nregs
== GET_MODE_SIZE (mode
));
19612 if (REG_P (src
) && REG_P (dst
) && (REGNO (src
) < REGNO (dst
)))
19614 /* Move register range backwards, if we might have destructive
19617 for (i
= nregs
- 1; i
>= 0; i
--)
19618 emit_insn (gen_rtx_SET (VOIDmode
,
19619 simplify_gen_subreg (reg_mode
, dst
, mode
,
19620 i
* reg_mode_size
),
19621 simplify_gen_subreg (reg_mode
, src
, mode
,
19622 i
* reg_mode_size
)));
19628 bool used_update
= false;
19629 rtx restore_basereg
= NULL_RTX
;
19631 if (MEM_P (src
) && INT_REGNO_P (reg
))
19635 if (GET_CODE (XEXP (src
, 0)) == PRE_INC
19636 || GET_CODE (XEXP (src
, 0)) == PRE_DEC
)
19639 breg
= XEXP (XEXP (src
, 0), 0);
19640 delta_rtx
= (GET_CODE (XEXP (src
, 0)) == PRE_INC
19641 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src
)))
19642 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src
))));
19643 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
19644 src
= replace_equiv_address (src
, breg
);
19646 else if (! rs6000_offsettable_memref_p (src
, reg_mode
))
19648 if (GET_CODE (XEXP (src
, 0)) == PRE_MODIFY
)
19650 rtx basereg
= XEXP (XEXP (src
, 0), 0);
19653 rtx ndst
= simplify_gen_subreg (reg_mode
, dst
, mode
, 0);
19654 emit_insn (gen_rtx_SET (VOIDmode
, ndst
,
19655 gen_rtx_MEM (reg_mode
, XEXP (src
, 0))));
19656 used_update
= true;
19659 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
19660 XEXP (XEXP (src
, 0), 1)));
19661 src
= replace_equiv_address (src
, basereg
);
19665 rtx basereg
= gen_rtx_REG (Pmode
, reg
);
19666 emit_insn (gen_rtx_SET (VOIDmode
, basereg
, XEXP (src
, 0)));
19667 src
= replace_equiv_address (src
, basereg
);
19671 breg
= XEXP (src
, 0);
19672 if (GET_CODE (breg
) == PLUS
|| GET_CODE (breg
) == LO_SUM
)
19673 breg
= XEXP (breg
, 0);
19675 /* If the base register we are using to address memory is
19676 also a destination reg, then change that register last. */
19678 && REGNO (breg
) >= REGNO (dst
)
19679 && REGNO (breg
) < REGNO (dst
) + nregs
)
19680 j
= REGNO (breg
) - REGNO (dst
);
19682 else if (MEM_P (dst
) && INT_REGNO_P (reg
))
19686 if (GET_CODE (XEXP (dst
, 0)) == PRE_INC
19687 || GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
19690 breg
= XEXP (XEXP (dst
, 0), 0);
19691 delta_rtx
= (GET_CODE (XEXP (dst
, 0)) == PRE_INC
19692 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst
)))
19693 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst
))));
19695 /* We have to update the breg before doing the store.
19696 Use store with update, if available. */
19700 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
19701 emit_insn (TARGET_32BIT
19702 ? (TARGET_POWERPC64
19703 ? gen_movdi_si_update (breg
, breg
, delta_rtx
, nsrc
)
19704 : gen_movsi_update (breg
, breg
, delta_rtx
, nsrc
))
19705 : gen_movdi_di_update (breg
, breg
, delta_rtx
, nsrc
));
19706 used_update
= true;
19709 emit_insn (gen_add3_insn (breg
, breg
, delta_rtx
));
19710 dst
= replace_equiv_address (dst
, breg
);
19712 else if (!rs6000_offsettable_memref_p (dst
, reg_mode
)
19713 && GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
19715 if (GET_CODE (XEXP (dst
, 0)) == PRE_MODIFY
)
19717 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
19720 rtx nsrc
= simplify_gen_subreg (reg_mode
, src
, mode
, 0);
19721 emit_insn (gen_rtx_SET (VOIDmode
,
19722 gen_rtx_MEM (reg_mode
, XEXP (dst
, 0)), nsrc
));
19723 used_update
= true;
19726 emit_insn (gen_rtx_SET (VOIDmode
, basereg
,
19727 XEXP (XEXP (dst
, 0), 1)));
19728 dst
= replace_equiv_address (dst
, basereg
);
19732 rtx basereg
= XEXP (XEXP (dst
, 0), 0);
19733 rtx offsetreg
= XEXP (XEXP (dst
, 0), 1);
19734 gcc_assert (GET_CODE (XEXP (dst
, 0)) == PLUS
19736 && REG_P (offsetreg
)
19737 && REGNO (basereg
) != REGNO (offsetreg
));
19738 if (REGNO (basereg
) == 0)
19740 rtx tmp
= offsetreg
;
19741 offsetreg
= basereg
;
19744 emit_insn (gen_add3_insn (basereg
, basereg
, offsetreg
));
19745 restore_basereg
= gen_sub3_insn (basereg
, basereg
, offsetreg
);
19746 dst
= replace_equiv_address (dst
, basereg
);
19749 else if (GET_CODE (XEXP (dst
, 0)) != LO_SUM
)
19750 gcc_assert (rs6000_offsettable_memref_p (dst
, reg_mode
));
19753 for (i
= 0; i
< nregs
; i
++)
19755 /* Calculate index to next subword. */
19760 /* If compiler already emitted move of first word by
19761 store with update, no need to do anything. */
19762 if (j
== 0 && used_update
)
19765 emit_insn (gen_rtx_SET (VOIDmode
,
19766 simplify_gen_subreg (reg_mode
, dst
, mode
,
19767 j
* reg_mode_size
),
19768 simplify_gen_subreg (reg_mode
, src
, mode
,
19769 j
* reg_mode_size
)));
19771 if (restore_basereg
!= NULL_RTX
)
19772 emit_insn (restore_basereg
);
19777 /* This page contains routines that are used to determine what the
19778 function prologue and epilogue code will do and write them out. */
19783 return !call_used_regs
[r
] && df_regs_ever_live_p (r
);
19786 /* Return the first fixed-point register that is required to be
19787 saved. 32 if none. */
19790 first_reg_to_save (void)
19794 /* Find lowest numbered live register. */
19795 for (first_reg
= 13; first_reg
<= 31; first_reg
++)
19796 if (save_reg_p (first_reg
))
19799 if (first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
19800 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
19801 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
)
19802 || (TARGET_TOC
&& TARGET_MINIMAL_TOC
))
19803 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))
19804 first_reg
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
19808 && crtl
->uses_pic_offset_table
19809 && first_reg
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
19810 return RS6000_PIC_OFFSET_TABLE_REGNUM
;
19816 /* Similar, for FP regs. */
19819 first_fp_reg_to_save (void)
19823 /* Find lowest numbered live register. */
19824 for (first_reg
= 14 + 32; first_reg
<= 63; first_reg
++)
19825 if (save_reg_p (first_reg
))
19831 /* Similar, for AltiVec regs. */
19834 first_altivec_reg_to_save (void)
19838 /* Stack frame remains as is unless we are in AltiVec ABI. */
19839 if (! TARGET_ALTIVEC_ABI
)
19840 return LAST_ALTIVEC_REGNO
+ 1;
19842 /* On Darwin, the unwind routines are compiled without
19843 TARGET_ALTIVEC, and use save_world to save/restore the
19844 altivec registers when necessary. */
19845 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
19846 && ! TARGET_ALTIVEC
)
19847 return FIRST_ALTIVEC_REGNO
+ 20;
19849 /* Find lowest numbered live register. */
19850 for (i
= FIRST_ALTIVEC_REGNO
+ 20; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19851 if (save_reg_p (i
))
19857 /* Return a 32-bit mask of the AltiVec registers we need to set in
19858 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
19859 the 32-bit word is 0. */
19861 static unsigned int
19862 compute_vrsave_mask (void)
19864 unsigned int i
, mask
= 0;
19866 /* On Darwin, the unwind routines are compiled without
19867 TARGET_ALTIVEC, and use save_world to save/restore the
19868 call-saved altivec registers when necessary. */
19869 if (DEFAULT_ABI
== ABI_DARWIN
&& crtl
->calls_eh_return
19870 && ! TARGET_ALTIVEC
)
19873 /* First, find out if we use _any_ altivec registers. */
19874 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
19875 if (df_regs_ever_live_p (i
))
19876 mask
|= ALTIVEC_REG_BIT (i
);
19881 /* Next, remove the argument registers from the set. These must
19882 be in the VRSAVE mask set by the caller, so we don't need to add
19883 them in again. More importantly, the mask we compute here is
19884 used to generate CLOBBERs in the set_vrsave insn, and we do not
19885 wish the argument registers to die. */
19886 for (i
= crtl
->args
.info
.vregno
- 1; i
>= ALTIVEC_ARG_MIN_REG
; --i
)
19887 mask
&= ~ALTIVEC_REG_BIT (i
);
19889 /* Similarly, remove the return value from the set. */
19892 diddle_return_value (is_altivec_return_reg
, &yes
);
19894 mask
&= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN
);
19900 /* For a very restricted set of circumstances, we can cut down the
19901 size of prologues/epilogues by calling our own save/restore-the-world
19905 compute_save_world_info (rs6000_stack_t
*info_ptr
)
19907 info_ptr
->world_save_p
= 1;
19908 info_ptr
->world_save_p
19909 = (WORLD_SAVE_P (info_ptr
)
19910 && DEFAULT_ABI
== ABI_DARWIN
19911 && !cfun
->has_nonlocal_label
19912 && info_ptr
->first_fp_reg_save
== FIRST_SAVED_FP_REGNO
19913 && info_ptr
->first_gp_reg_save
== FIRST_SAVED_GP_REGNO
19914 && info_ptr
->first_altivec_reg_save
== FIRST_SAVED_ALTIVEC_REGNO
19915 && info_ptr
->cr_save_p
);
19917 /* This will not work in conjunction with sibcalls. Make sure there
19918 are none. (This check is expensive, but seldom executed.) */
19919 if (WORLD_SAVE_P (info_ptr
))
19922 for (insn
= get_last_insn_anywhere (); insn
; insn
= PREV_INSN (insn
))
19923 if (CALL_P (insn
) && SIBLING_CALL_P (insn
))
19925 info_ptr
->world_save_p
= 0;
19930 if (WORLD_SAVE_P (info_ptr
))
19932 /* Even if we're not touching VRsave, make sure there's room on the
19933 stack for it, if it looks like we're calling SAVE_WORLD, which
19934 will attempt to save it. */
19935 info_ptr
->vrsave_size
= 4;
19937 /* If we are going to save the world, we need to save the link register too. */
19938 info_ptr
->lr_save_p
= 1;
19940 /* "Save" the VRsave register too if we're saving the world. */
19941 if (info_ptr
->vrsave_mask
== 0)
19942 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
19944 /* Because the Darwin register save/restore routines only handle
19945 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
19947 gcc_assert (info_ptr
->first_fp_reg_save
>= FIRST_SAVED_FP_REGNO
19948 && (info_ptr
->first_altivec_reg_save
19949 >= FIRST_SAVED_ALTIVEC_REGNO
));
19956 is_altivec_return_reg (rtx reg
, void *xyes
)
19958 bool *yes
= (bool *) xyes
;
19959 if (REGNO (reg
) == ALTIVEC_ARG_RETURN
)
19964 /* Look for user-defined global regs in the range FIRST to LAST-1.
19965 We should not restore these, and so cannot use lmw or out-of-line
19966 restore functions if there are any. We also can't save them
19967 (well, emit frame notes for them), because frame unwinding during
19968 exception handling will restore saved registers. */
19971 global_regs_p (unsigned first
, unsigned last
)
19973 while (first
< last
)
19974 if (global_regs
[first
++])
19979 /* Determine the strategy for savings/restoring registers. */
19982 SAVRES_MULTIPLE
= 0x1,
19983 SAVE_INLINE_FPRS
= 0x2,
19984 SAVE_INLINE_GPRS
= 0x4,
19985 REST_INLINE_FPRS
= 0x8,
19986 REST_INLINE_GPRS
= 0x10,
19987 SAVE_NOINLINE_GPRS_SAVES_LR
= 0x20,
19988 SAVE_NOINLINE_FPRS_SAVES_LR
= 0x40,
19989 REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
= 0x80,
19990 SAVE_INLINE_VRS
= 0x100,
19991 REST_INLINE_VRS
= 0x200
19995 rs6000_savres_strategy (rs6000_stack_t
*info
,
19996 bool using_static_chain_p
)
20001 if (TARGET_MULTIPLE
20002 && !TARGET_POWERPC64
20003 && !(TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
)
20004 && info
->first_gp_reg_save
< 31
20005 && !global_regs_p (info
->first_gp_reg_save
, 32))
20006 strategy
|= SAVRES_MULTIPLE
;
20008 if (crtl
->calls_eh_return
20009 || cfun
->machine
->ra_need_lr
)
20010 strategy
|= (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
20011 | SAVE_INLINE_GPRS
| REST_INLINE_GPRS
20012 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20014 if (info
->first_fp_reg_save
== 64
20015 /* The out-of-line FP routines use double-precision stores;
20016 we can't use those routines if we don't have such stores. */
20017 || (TARGET_HARD_FLOAT
&& !TARGET_DOUBLE_FLOAT
)
20018 || global_regs_p (info
->first_fp_reg_save
, 64))
20019 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20021 if (info
->first_gp_reg_save
== 32
20022 || (!(strategy
& SAVRES_MULTIPLE
)
20023 && global_regs_p (info
->first_gp_reg_save
, 32)))
20024 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20026 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
+ 1
20027 || global_regs_p (info
->first_altivec_reg_save
, LAST_ALTIVEC_REGNO
+ 1))
20028 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20030 /* Define cutoff for using out-of-line functions to save registers. */
20031 if (DEFAULT_ABI
== ABI_V4
|| TARGET_ELF
)
20033 if (!optimize_size
)
20035 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20036 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20037 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20041 /* Prefer out-of-line restore if it will exit. */
20042 if (info
->first_fp_reg_save
> 61)
20043 strategy
|= SAVE_INLINE_FPRS
;
20044 if (info
->first_gp_reg_save
> 29)
20046 if (info
->first_fp_reg_save
== 64)
20047 strategy
|= SAVE_INLINE_GPRS
;
20049 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20051 if (info
->first_altivec_reg_save
== LAST_ALTIVEC_REGNO
)
20052 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20055 else if (DEFAULT_ABI
== ABI_DARWIN
)
20057 if (info
->first_fp_reg_save
> 60)
20058 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20059 if (info
->first_gp_reg_save
> 29)
20060 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20061 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20065 gcc_checking_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
20066 if (info
->first_fp_reg_save
> 61)
20067 strategy
|= SAVE_INLINE_FPRS
| REST_INLINE_FPRS
;
20068 strategy
|= SAVE_INLINE_GPRS
| REST_INLINE_GPRS
;
20069 strategy
|= SAVE_INLINE_VRS
| REST_INLINE_VRS
;
20072 /* Don't bother to try to save things out-of-line if r11 is occupied
20073 by the static chain. It would require too much fiddling and the
20074 static chain is rarely used anyway. FPRs are saved w.r.t the stack
20075 pointer on Darwin, and AIX uses r1 or r12. */
20076 if (using_static_chain_p
20077 && (DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
))
20078 strategy
|= ((DEFAULT_ABI
== ABI_DARWIN
? 0 : SAVE_INLINE_FPRS
)
20080 | SAVE_INLINE_VRS
| REST_INLINE_VRS
);
20082 /* We can only use the out-of-line routines to restore if we've
20083 saved all the registers from first_fp_reg_save in the prologue.
20084 Otherwise, we risk loading garbage. */
20085 if ((strategy
& (SAVE_INLINE_FPRS
| REST_INLINE_FPRS
)) == SAVE_INLINE_FPRS
)
20089 for (i
= info
->first_fp_reg_save
; i
< 64; i
++)
20090 if (!save_reg_p (i
))
20092 strategy
|= REST_INLINE_FPRS
;
20097 /* If we are going to use store multiple, then don't even bother
20098 with the out-of-line routines, since the store-multiple
20099 instruction will always be smaller. */
20100 if ((strategy
& SAVRES_MULTIPLE
))
20101 strategy
|= SAVE_INLINE_GPRS
;
20103 /* info->lr_save_p isn't yet set if the only reason lr needs to be
20104 saved is an out-of-line save or restore. Set up the value for
20105 the next test (excluding out-of-line gpr restore). */
20106 lr_save_p
= (info
->lr_save_p
20107 || !(strategy
& SAVE_INLINE_GPRS
)
20108 || !(strategy
& SAVE_INLINE_FPRS
)
20109 || !(strategy
& SAVE_INLINE_VRS
)
20110 || !(strategy
& REST_INLINE_FPRS
)
20111 || !(strategy
& REST_INLINE_VRS
));
20113 /* The situation is more complicated with load multiple. We'd
20114 prefer to use the out-of-line routines for restores, since the
20115 "exit" out-of-line routines can handle the restore of LR and the
20116 frame teardown. However if doesn't make sense to use the
20117 out-of-line routine if that is the only reason we'd need to save
20118 LR, and we can't use the "exit" out-of-line gpr restore if we
20119 have saved some fprs; In those cases it is advantageous to use
20120 load multiple when available. */
20121 if ((strategy
& SAVRES_MULTIPLE
)
20123 || info
->first_fp_reg_save
!= 64))
20124 strategy
|= REST_INLINE_GPRS
;
20126 /* Saving CR interferes with the exit routines used on the SPE, so
20129 && info
->spe_64bit_regs_used
20130 && info
->cr_save_p
)
20131 strategy
|= REST_INLINE_GPRS
;
20133 /* We can only use load multiple or the out-of-line routines to
20134 restore if we've used store multiple or out-of-line routines
20135 in the prologue, i.e. if we've saved all the registers from
20136 first_gp_reg_save. Otherwise, we risk loading garbage. */
20137 if ((strategy
& (SAVE_INLINE_GPRS
| REST_INLINE_GPRS
| SAVRES_MULTIPLE
))
20138 == SAVE_INLINE_GPRS
)
20142 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
20143 if (!save_reg_p (i
))
20145 strategy
|= REST_INLINE_GPRS
;
20150 if (TARGET_ELF
&& TARGET_64BIT
)
20152 if (!(strategy
& SAVE_INLINE_FPRS
))
20153 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20154 else if (!(strategy
& SAVE_INLINE_GPRS
)
20155 && info
->first_fp_reg_save
== 64)
20156 strategy
|= SAVE_NOINLINE_GPRS_SAVES_LR
;
20158 else if (TARGET_AIX
&& !(strategy
& REST_INLINE_FPRS
))
20159 strategy
|= REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
;
20161 if (TARGET_MACHO
&& !(strategy
& SAVE_INLINE_FPRS
))
20162 strategy
|= SAVE_NOINLINE_FPRS_SAVES_LR
;
20167 /* Calculate the stack information for the current function. This is
20168 complicated by having two separate calling sequences, the AIX calling
20169 sequence and the V.4 calling sequence.
20171 AIX (and Darwin/Mac OS X) stack frames look like:
20173 SP----> +---------------------------------------+
20174 | back chain to caller | 0 0
20175 +---------------------------------------+
20176 | saved CR | 4 8 (8-11)
20177 +---------------------------------------+
20179 +---------------------------------------+
20180 | reserved for compilers | 12 24
20181 +---------------------------------------+
20182 | reserved for binders | 16 32
20183 +---------------------------------------+
20184 | saved TOC pointer | 20 40
20185 +---------------------------------------+
20186 | Parameter save area (P) | 24 48
20187 +---------------------------------------+
20188 | Alloca space (A) | 24+P etc.
20189 +---------------------------------------+
20190 | Local variable space (L) | 24+P+A
20191 +---------------------------------------+
20192 | Float/int conversion temporary (X) | 24+P+A+L
20193 +---------------------------------------+
20194 | Save area for AltiVec registers (W) | 24+P+A+L+X
20195 +---------------------------------------+
20196 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
20197 +---------------------------------------+
20198 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
20199 +---------------------------------------+
20200 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
20201 +---------------------------------------+
20202 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
20203 +---------------------------------------+
20204 old SP->| back chain to caller's caller |
20205 +---------------------------------------+
20207 The required alignment for AIX configurations is two words (i.e., 8
20210 The ELFv2 ABI is a variant of the AIX ABI. Stack frames look like:
20212 SP----> +---------------------------------------+
20213 | Back chain to caller | 0
20214 +---------------------------------------+
20215 | Save area for CR | 8
20216 +---------------------------------------+
20218 +---------------------------------------+
20219 | Saved TOC pointer | 24
20220 +---------------------------------------+
20221 | Parameter save area (P) | 32
20222 +---------------------------------------+
20223 | Alloca space (A) | 32+P
20224 +---------------------------------------+
20225 | Local variable space (L) | 32+P+A
20226 +---------------------------------------+
20227 | Save area for AltiVec registers (W) | 32+P+A+L
20228 +---------------------------------------+
20229 | AltiVec alignment padding (Y) | 32+P+A+L+W
20230 +---------------------------------------+
20231 | Save area for GP registers (G) | 32+P+A+L+W+Y
20232 +---------------------------------------+
20233 | Save area for FP registers (F) | 32+P+A+L+W+Y+G
20234 +---------------------------------------+
20235 old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F
20236 +---------------------------------------+
20239 V.4 stack frames look like:
20241 SP----> +---------------------------------------+
20242 | back chain to caller | 0
20243 +---------------------------------------+
20244 | caller's saved LR | 4
20245 +---------------------------------------+
20246 | Parameter save area (P) | 8
20247 +---------------------------------------+
20248 | Alloca space (A) | 8+P
20249 +---------------------------------------+
20250 | Varargs save area (V) | 8+P+A
20251 +---------------------------------------+
20252 | Local variable space (L) | 8+P+A+V
20253 +---------------------------------------+
20254 | Float/int conversion temporary (X) | 8+P+A+V+L
20255 +---------------------------------------+
20256 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
20257 +---------------------------------------+
20258 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
20259 +---------------------------------------+
20260 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
20261 +---------------------------------------+
20262 | SPE: area for 64-bit GP registers |
20263 +---------------------------------------+
20264 | SPE alignment padding |
20265 +---------------------------------------+
20266 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
20267 +---------------------------------------+
20268 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
20269 +---------------------------------------+
20270 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
20271 +---------------------------------------+
20272 old SP->| back chain to caller's caller |
20273 +---------------------------------------+
20275 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
20276 given. (But note below and in sysv4.h that we require only 8 and
20277 may round up the size of our stack frame anyways. The historical
20278 reason is early versions of powerpc-linux which didn't properly
20279 align the stack at program startup. A happy side-effect is that
20280 -mno-eabi libraries can be used with -meabi programs.)
20282 The EABI configuration defaults to the V.4 layout. However,
20283 the stack alignment requirements may differ. If -mno-eabi is not
20284 given, the required stack alignment is 8 bytes; if -mno-eabi is
20285 given, the required alignment is 16 bytes. (But see V.4 comment
20288 #ifndef ABI_STACK_BOUNDARY
20289 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
20292 static rs6000_stack_t
*
20293 rs6000_stack_info (void)
20295 rs6000_stack_t
*info_ptr
= &stack_info
;
20296 int reg_size
= TARGET_32BIT
? 4 : 8;
20301 HOST_WIDE_INT non_fixed_size
;
20302 bool using_static_chain_p
;
20304 if (reload_completed
&& info_ptr
->reload_completed
)
20307 memset (info_ptr
, 0, sizeof (*info_ptr
));
20308 info_ptr
->reload_completed
= reload_completed
;
20312 /* Cache value so we don't rescan instruction chain over and over. */
20313 if (cfun
->machine
->insn_chain_scanned_p
== 0)
20314 cfun
->machine
->insn_chain_scanned_p
20315 = spe_func_has_64bit_regs_p () + 1;
20316 info_ptr
->spe_64bit_regs_used
= cfun
->machine
->insn_chain_scanned_p
- 1;
20319 /* Select which calling sequence. */
20320 info_ptr
->abi
= DEFAULT_ABI
;
20322 /* Calculate which registers need to be saved & save area size. */
20323 info_ptr
->first_gp_reg_save
= first_reg_to_save ();
20324 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
20325 even if it currently looks like we won't. Reload may need it to
20326 get at a constant; if so, it will have already created a constant
20327 pool entry for it. */
20328 if (((TARGET_TOC
&& TARGET_MINIMAL_TOC
)
20329 || (flag_pic
== 1 && DEFAULT_ABI
== ABI_V4
)
20330 || (flag_pic
&& DEFAULT_ABI
== ABI_DARWIN
))
20331 && crtl
->uses_const_pool
20332 && info_ptr
->first_gp_reg_save
> RS6000_PIC_OFFSET_TABLE_REGNUM
)
20333 first_gp
= RS6000_PIC_OFFSET_TABLE_REGNUM
;
20335 first_gp
= info_ptr
->first_gp_reg_save
;
20337 info_ptr
->gp_size
= reg_size
* (32 - first_gp
);
20339 /* For the SPE, we have an additional upper 32-bits on each GPR.
20340 Ideally we should save the entire 64-bits only when the upper
20341 half is used in SIMD instructions. Since we only record
20342 registers live (not the size they are used in), this proves
20343 difficult because we'd have to traverse the instruction chain at
20344 the right time, taking reload into account. This is a real pain,
20345 so we opt to save the GPRs in 64-bits always if but one register
20346 gets used in 64-bits. Otherwise, all the registers in the frame
20347 get saved in 32-bits.
20349 So... since when we save all GPRs (except the SP) in 64-bits, the
20350 traditional GP save area will be empty. */
20351 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20352 info_ptr
->gp_size
= 0;
20354 info_ptr
->first_fp_reg_save
= first_fp_reg_to_save ();
20355 info_ptr
->fp_size
= 8 * (64 - info_ptr
->first_fp_reg_save
);
20357 info_ptr
->first_altivec_reg_save
= first_altivec_reg_to_save ();
20358 info_ptr
->altivec_size
= 16 * (LAST_ALTIVEC_REGNO
+ 1
20359 - info_ptr
->first_altivec_reg_save
);
20361 /* Does this function call anything? */
20362 info_ptr
->calls_p
= (! crtl
->is_leaf
20363 || cfun
->machine
->ra_needs_full_frame
);
20365 /* Determine if we need to save the condition code registers. */
20366 if (df_regs_ever_live_p (CR2_REGNO
)
20367 || df_regs_ever_live_p (CR3_REGNO
)
20368 || df_regs_ever_live_p (CR4_REGNO
))
20370 info_ptr
->cr_save_p
= 1;
20371 if (DEFAULT_ABI
== ABI_V4
)
20372 info_ptr
->cr_size
= reg_size
;
20375 /* If the current function calls __builtin_eh_return, then we need
20376 to allocate stack space for registers that will hold data for
20377 the exception handler. */
20378 if (crtl
->calls_eh_return
)
20381 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; ++i
)
20384 /* SPE saves EH registers in 64-bits. */
20385 ehrd_size
= i
* (TARGET_SPE_ABI
20386 && info_ptr
->spe_64bit_regs_used
!= 0
20387 ? UNITS_PER_SPE_WORD
: UNITS_PER_WORD
);
20392 /* In the ELFv2 ABI, we also need to allocate space for separate
20393 CR field save areas if the function calls __builtin_eh_return. */
20394 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
20396 /* This hard-codes that we have three call-saved CR fields. */
20397 ehcr_size
= 3 * reg_size
;
20398 /* We do *not* use the regular CR save mechanism. */
20399 info_ptr
->cr_save_p
= 0;
20404 /* Determine various sizes. */
20405 info_ptr
->reg_size
= reg_size
;
20406 info_ptr
->fixed_size
= RS6000_SAVE_AREA
;
20407 info_ptr
->vars_size
= RS6000_ALIGN (get_frame_size (), 8);
20408 info_ptr
->parm_size
= RS6000_ALIGN (crtl
->outgoing_args_size
,
20409 TARGET_ALTIVEC
? 16 : 8);
20410 if (FRAME_GROWS_DOWNWARD
)
20411 info_ptr
->vars_size
20412 += RS6000_ALIGN (info_ptr
->fixed_size
+ info_ptr
->vars_size
20413 + info_ptr
->parm_size
,
20414 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
)
20415 - (info_ptr
->fixed_size
+ info_ptr
->vars_size
20416 + info_ptr
->parm_size
);
20418 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20419 info_ptr
->spe_gp_size
= 8 * (32 - first_gp
);
20421 info_ptr
->spe_gp_size
= 0;
20423 if (TARGET_ALTIVEC_ABI
)
20424 info_ptr
->vrsave_mask
= compute_vrsave_mask ();
20426 info_ptr
->vrsave_mask
= 0;
20428 if (TARGET_ALTIVEC_VRSAVE
&& info_ptr
->vrsave_mask
)
20429 info_ptr
->vrsave_size
= 4;
20431 info_ptr
->vrsave_size
= 0;
20433 compute_save_world_info (info_ptr
);
20435 /* Calculate the offsets. */
20436 switch (DEFAULT_ABI
)
20440 gcc_unreachable ();
20445 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
20446 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
20448 if (TARGET_ALTIVEC_ABI
)
20450 info_ptr
->vrsave_save_offset
20451 = info_ptr
->gp_save_offset
- info_ptr
->vrsave_size
;
20453 /* Align stack so vector save area is on a quadword boundary.
20454 The padding goes above the vectors. */
20455 if (info_ptr
->altivec_size
!= 0)
20456 info_ptr
->altivec_padding_size
20457 = info_ptr
->vrsave_save_offset
& 0xF;
20459 info_ptr
->altivec_padding_size
= 0;
20461 info_ptr
->altivec_save_offset
20462 = info_ptr
->vrsave_save_offset
20463 - info_ptr
->altivec_padding_size
20464 - info_ptr
->altivec_size
;
20465 gcc_assert (info_ptr
->altivec_size
== 0
20466 || info_ptr
->altivec_save_offset
% 16 == 0);
20468 /* Adjust for AltiVec case. */
20469 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
- ehrd_size
;
20472 info_ptr
->ehrd_offset
= info_ptr
->gp_save_offset
- ehrd_size
;
20474 info_ptr
->ehcr_offset
= info_ptr
->ehrd_offset
- ehcr_size
;
20475 info_ptr
->cr_save_offset
= reg_size
; /* first word when 64-bit. */
20476 info_ptr
->lr_save_offset
= 2*reg_size
;
20480 info_ptr
->fp_save_offset
= - info_ptr
->fp_size
;
20481 info_ptr
->gp_save_offset
= info_ptr
->fp_save_offset
- info_ptr
->gp_size
;
20482 info_ptr
->cr_save_offset
= info_ptr
->gp_save_offset
- info_ptr
->cr_size
;
20484 if (TARGET_SPE_ABI
&& info_ptr
->spe_64bit_regs_used
!= 0)
20486 /* Align stack so SPE GPR save area is aligned on a
20487 double-word boundary. */
20488 if (info_ptr
->spe_gp_size
!= 0 && info_ptr
->cr_save_offset
!= 0)
20489 info_ptr
->spe_padding_size
20490 = 8 - (-info_ptr
->cr_save_offset
% 8);
20492 info_ptr
->spe_padding_size
= 0;
20494 info_ptr
->spe_gp_save_offset
20495 = info_ptr
->cr_save_offset
20496 - info_ptr
->spe_padding_size
20497 - info_ptr
->spe_gp_size
;
20499 /* Adjust for SPE case. */
20500 info_ptr
->ehrd_offset
= info_ptr
->spe_gp_save_offset
;
20502 else if (TARGET_ALTIVEC_ABI
)
20504 info_ptr
->vrsave_save_offset
20505 = info_ptr
->cr_save_offset
- info_ptr
->vrsave_size
;
20507 /* Align stack so vector save area is on a quadword boundary. */
20508 if (info_ptr
->altivec_size
!= 0)
20509 info_ptr
->altivec_padding_size
20510 = 16 - (-info_ptr
->vrsave_save_offset
% 16);
20512 info_ptr
->altivec_padding_size
= 0;
20514 info_ptr
->altivec_save_offset
20515 = info_ptr
->vrsave_save_offset
20516 - info_ptr
->altivec_padding_size
20517 - info_ptr
->altivec_size
;
20519 /* Adjust for AltiVec case. */
20520 info_ptr
->ehrd_offset
= info_ptr
->altivec_save_offset
;
20523 info_ptr
->ehrd_offset
= info_ptr
->cr_save_offset
;
20524 info_ptr
->ehrd_offset
-= ehrd_size
;
20525 info_ptr
->lr_save_offset
= reg_size
;
20529 save_align
= (TARGET_ALTIVEC_ABI
|| DEFAULT_ABI
== ABI_DARWIN
) ? 16 : 8;
20530 info_ptr
->save_size
= RS6000_ALIGN (info_ptr
->fp_size
20531 + info_ptr
->gp_size
20532 + info_ptr
->altivec_size
20533 + info_ptr
->altivec_padding_size
20534 + info_ptr
->spe_gp_size
20535 + info_ptr
->spe_padding_size
20538 + info_ptr
->cr_size
20539 + info_ptr
->vrsave_size
,
20542 non_fixed_size
= (info_ptr
->vars_size
20543 + info_ptr
->parm_size
20544 + info_ptr
->save_size
);
20546 info_ptr
->total_size
= RS6000_ALIGN (non_fixed_size
+ info_ptr
->fixed_size
,
20547 ABI_STACK_BOUNDARY
/ BITS_PER_UNIT
);
20549 /* Determine if we need to save the link register. */
20550 if (info_ptr
->calls_p
20551 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
20553 && !TARGET_PROFILE_KERNEL
)
20554 || (DEFAULT_ABI
== ABI_V4
&& cfun
->calls_alloca
)
20555 #ifdef TARGET_RELOCATABLE
20556 || (TARGET_RELOCATABLE
&& (get_pool_size () != 0))
20558 || rs6000_ra_ever_killed ())
20559 info_ptr
->lr_save_p
= 1;
20561 using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
20562 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
20563 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
20564 info_ptr
->savres_strategy
= rs6000_savres_strategy (info_ptr
,
20565 using_static_chain_p
);
20567 if (!(info_ptr
->savres_strategy
& SAVE_INLINE_GPRS
)
20568 || !(info_ptr
->savres_strategy
& SAVE_INLINE_FPRS
)
20569 || !(info_ptr
->savres_strategy
& SAVE_INLINE_VRS
)
20570 || !(info_ptr
->savres_strategy
& REST_INLINE_GPRS
)
20571 || !(info_ptr
->savres_strategy
& REST_INLINE_FPRS
)
20572 || !(info_ptr
->savres_strategy
& REST_INLINE_VRS
))
20573 info_ptr
->lr_save_p
= 1;
20575 if (info_ptr
->lr_save_p
)
20576 df_set_regs_ever_live (LR_REGNO
, true);
20578 /* Determine if we need to allocate any stack frame:
20580 For AIX we need to push the stack if a frame pointer is needed
20581 (because the stack might be dynamically adjusted), if we are
20582 debugging, if we make calls, or if the sum of fp_save, gp_save,
20583 and local variables are more than the space needed to save all
20584 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
20585 + 18*8 = 288 (GPR13 reserved).
20587 For V.4 we don't have the stack cushion that AIX uses, but assume
20588 that the debugger can handle stackless frames. */
20590 if (info_ptr
->calls_p
)
20591 info_ptr
->push_p
= 1;
20593 else if (DEFAULT_ABI
== ABI_V4
)
20594 info_ptr
->push_p
= non_fixed_size
!= 0;
20596 else if (frame_pointer_needed
)
20597 info_ptr
->push_p
= 1;
20599 else if (TARGET_XCOFF
&& write_symbols
!= NO_DEBUG
)
20600 info_ptr
->push_p
= 1;
20603 info_ptr
->push_p
= non_fixed_size
> (TARGET_32BIT
? 220 : 288);
20605 /* Zero offsets if we're not saving those registers. */
20606 if (info_ptr
->fp_size
== 0)
20607 info_ptr
->fp_save_offset
= 0;
20609 if (info_ptr
->gp_size
== 0)
20610 info_ptr
->gp_save_offset
= 0;
20612 if (! TARGET_ALTIVEC_ABI
|| info_ptr
->altivec_size
== 0)
20613 info_ptr
->altivec_save_offset
= 0;
20615 /* Zero VRSAVE offset if not saved and restored. */
20616 if (! TARGET_ALTIVEC_VRSAVE
|| info_ptr
->vrsave_mask
== 0)
20617 info_ptr
->vrsave_save_offset
= 0;
20619 if (! TARGET_SPE_ABI
20620 || info_ptr
->spe_64bit_regs_used
== 0
20621 || info_ptr
->spe_gp_size
== 0)
20622 info_ptr
->spe_gp_save_offset
= 0;
20624 if (! info_ptr
->lr_save_p
)
20625 info_ptr
->lr_save_offset
= 0;
20627 if (! info_ptr
->cr_save_p
)
20628 info_ptr
->cr_save_offset
= 0;
20633 /* Return true if the current function uses any GPRs in 64-bit SIMD
20637 spe_func_has_64bit_regs_p (void)
20641 /* Functions that save and restore all the call-saved registers will
20642 need to save/restore the registers in 64-bits. */
20643 if (crtl
->calls_eh_return
20644 || cfun
->calls_setjmp
20645 || crtl
->has_nonlocal_goto
)
20648 insns
= get_insns ();
20650 for (insn
= NEXT_INSN (insns
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
20656 /* FIXME: This should be implemented with attributes...
20658 (set_attr "spe64" "true")....then,
20659 if (get_spe64(insn)) return true;
20661 It's the only reliable way to do the stuff below. */
20663 i
= PATTERN (insn
);
20664 if (GET_CODE (i
) == SET
)
20666 enum machine_mode mode
= GET_MODE (SET_SRC (i
));
20668 if (SPE_VECTOR_MODE (mode
))
20670 if (TARGET_E500_DOUBLE
&& (mode
== DFmode
|| mode
== TFmode
))
20680 debug_stack_info (rs6000_stack_t
*info
)
20682 const char *abi_string
;
20685 info
= rs6000_stack_info ();
20687 fprintf (stderr
, "\nStack information for function %s:\n",
20688 ((current_function_decl
&& DECL_NAME (current_function_decl
))
20689 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
20694 default: abi_string
= "Unknown"; break;
20695 case ABI_NONE
: abi_string
= "NONE"; break;
20696 case ABI_AIX
: abi_string
= "AIX"; break;
20697 case ABI_ELFv2
: abi_string
= "ELFv2"; break;
20698 case ABI_DARWIN
: abi_string
= "Darwin"; break;
20699 case ABI_V4
: abi_string
= "V.4"; break;
20702 fprintf (stderr
, "\tABI = %5s\n", abi_string
);
20704 if (TARGET_ALTIVEC_ABI
)
20705 fprintf (stderr
, "\tALTIVEC ABI extensions enabled.\n");
20707 if (TARGET_SPE_ABI
)
20708 fprintf (stderr
, "\tSPE ABI extensions enabled.\n");
20710 if (info
->first_gp_reg_save
!= 32)
20711 fprintf (stderr
, "\tfirst_gp_reg_save = %5d\n", info
->first_gp_reg_save
);
20713 if (info
->first_fp_reg_save
!= 64)
20714 fprintf (stderr
, "\tfirst_fp_reg_save = %5d\n", info
->first_fp_reg_save
);
20716 if (info
->first_altivec_reg_save
<= LAST_ALTIVEC_REGNO
)
20717 fprintf (stderr
, "\tfirst_altivec_reg_save = %5d\n",
20718 info
->first_altivec_reg_save
);
20720 if (info
->lr_save_p
)
20721 fprintf (stderr
, "\tlr_save_p = %5d\n", info
->lr_save_p
);
20723 if (info
->cr_save_p
)
20724 fprintf (stderr
, "\tcr_save_p = %5d\n", info
->cr_save_p
);
20726 if (info
->vrsave_mask
)
20727 fprintf (stderr
, "\tvrsave_mask = 0x%x\n", info
->vrsave_mask
);
20730 fprintf (stderr
, "\tpush_p = %5d\n", info
->push_p
);
20733 fprintf (stderr
, "\tcalls_p = %5d\n", info
->calls_p
);
20735 if (info
->gp_save_offset
)
20736 fprintf (stderr
, "\tgp_save_offset = %5d\n", info
->gp_save_offset
);
20738 if (info
->fp_save_offset
)
20739 fprintf (stderr
, "\tfp_save_offset = %5d\n", info
->fp_save_offset
);
20741 if (info
->altivec_save_offset
)
20742 fprintf (stderr
, "\taltivec_save_offset = %5d\n",
20743 info
->altivec_save_offset
);
20745 if (info
->spe_gp_save_offset
)
20746 fprintf (stderr
, "\tspe_gp_save_offset = %5d\n",
20747 info
->spe_gp_save_offset
);
20749 if (info
->vrsave_save_offset
)
20750 fprintf (stderr
, "\tvrsave_save_offset = %5d\n",
20751 info
->vrsave_save_offset
);
20753 if (info
->lr_save_offset
)
20754 fprintf (stderr
, "\tlr_save_offset = %5d\n", info
->lr_save_offset
);
20756 if (info
->cr_save_offset
)
20757 fprintf (stderr
, "\tcr_save_offset = %5d\n", info
->cr_save_offset
);
20759 if (info
->varargs_save_offset
)
20760 fprintf (stderr
, "\tvarargs_save_offset = %5d\n", info
->varargs_save_offset
);
20762 if (info
->total_size
)
20763 fprintf (stderr
, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
20766 if (info
->vars_size
)
20767 fprintf (stderr
, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC
"\n",
20770 if (info
->parm_size
)
20771 fprintf (stderr
, "\tparm_size = %5d\n", info
->parm_size
);
20773 if (info
->fixed_size
)
20774 fprintf (stderr
, "\tfixed_size = %5d\n", info
->fixed_size
);
20777 fprintf (stderr
, "\tgp_size = %5d\n", info
->gp_size
);
20779 if (info
->spe_gp_size
)
20780 fprintf (stderr
, "\tspe_gp_size = %5d\n", info
->spe_gp_size
);
20783 fprintf (stderr
, "\tfp_size = %5d\n", info
->fp_size
);
20785 if (info
->altivec_size
)
20786 fprintf (stderr
, "\taltivec_size = %5d\n", info
->altivec_size
);
20788 if (info
->vrsave_size
)
20789 fprintf (stderr
, "\tvrsave_size = %5d\n", info
->vrsave_size
);
20791 if (info
->altivec_padding_size
)
20792 fprintf (stderr
, "\taltivec_padding_size= %5d\n",
20793 info
->altivec_padding_size
);
20795 if (info
->spe_padding_size
)
20796 fprintf (stderr
, "\tspe_padding_size = %5d\n",
20797 info
->spe_padding_size
);
20800 fprintf (stderr
, "\tcr_size = %5d\n", info
->cr_size
);
20802 if (info
->save_size
)
20803 fprintf (stderr
, "\tsave_size = %5d\n", info
->save_size
);
20805 if (info
->reg_size
!= 4)
20806 fprintf (stderr
, "\treg_size = %5d\n", info
->reg_size
);
20808 fprintf (stderr
, "\tsave-strategy = %04x\n", info
->savres_strategy
);
20810 fprintf (stderr
, "\n");
20814 rs6000_return_addr (int count
, rtx frame
)
20816 /* Currently we don't optimize very well between prolog and body
20817 code and for PIC code the code can be actually quite bad, so
20818 don't try to be too clever here. */
20820 || ((DEFAULT_ABI
== ABI_V4
|| DEFAULT_ABI
== ABI_DARWIN
) && flag_pic
))
20822 cfun
->machine
->ra_needs_full_frame
= 1;
20829 plus_constant (Pmode
,
20831 (gen_rtx_MEM (Pmode
,
20832 memory_address (Pmode
, frame
))),
20833 RETURN_ADDRESS_OFFSET
)));
20836 cfun
->machine
->ra_need_lr
= 1;
20837 return get_hard_reg_initial_val (Pmode
, LR_REGNO
);
20840 /* Say whether a function is a candidate for sibcall handling or not. */
20843 rs6000_function_ok_for_sibcall (tree decl
, tree exp
)
20848 fntype
= TREE_TYPE (decl
);
20850 fntype
= TREE_TYPE (TREE_TYPE (CALL_EXPR_FN (exp
)));
20852 /* We can't do it if the called function has more vector parameters
20853 than the current function; there's nowhere to put the VRsave code. */
20854 if (TARGET_ALTIVEC_ABI
20855 && TARGET_ALTIVEC_VRSAVE
20856 && !(decl
&& decl
== current_function_decl
))
20858 function_args_iterator args_iter
;
20862 /* Functions with vector parameters are required to have a
20863 prototype, so the argument type info must be available
20865 FOREACH_FUNCTION_ARGS(fntype
, type
, args_iter
)
20866 if (TREE_CODE (type
) == VECTOR_TYPE
20867 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
20870 FOREACH_FUNCTION_ARGS(TREE_TYPE (current_function_decl
), type
, args_iter
)
20871 if (TREE_CODE (type
) == VECTOR_TYPE
20872 && ALTIVEC_OR_VSX_VECTOR_MODE (TYPE_MODE (type
)))
20879 /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local
20880 functions, because the callee may have a different TOC pointer to
20881 the caller and there's no way to ensure we restore the TOC when
20882 we return. With the secure-plt SYSV ABI we can't make non-local
20883 calls when -fpic/PIC because the plt call stubs use r30. */
20884 if (DEFAULT_ABI
== ABI_DARWIN
20885 || ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
20887 && !DECL_EXTERNAL (decl
)
20888 && (*targetm
.binds_local_p
) (decl
))
20889 || (DEFAULT_ABI
== ABI_V4
20890 && (!TARGET_SECURE_PLT
20893 && (*targetm
.binds_local_p
) (decl
)))))
20895 tree attr_list
= TYPE_ATTRIBUTES (fntype
);
20897 if (!lookup_attribute ("longcall", attr_list
)
20898 || lookup_attribute ("shortcall", attr_list
))
20906 rs6000_ra_ever_killed (void)
20912 if (cfun
->is_thunk
)
20915 if (cfun
->machine
->lr_save_state
)
20916 return cfun
->machine
->lr_save_state
- 1;
20918 /* regs_ever_live has LR marked as used if any sibcalls are present,
20919 but this should not force saving and restoring in the
20920 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
20921 clobbers LR, so that is inappropriate. */
20923 /* Also, the prologue can generate a store into LR that
20924 doesn't really count, like this:
20927 bcl to set PIC register
20931 When we're called from the epilogue, we need to avoid counting
20932 this as a store. */
20934 push_topmost_sequence ();
20935 top
= get_insns ();
20936 pop_topmost_sequence ();
20937 reg
= gen_rtx_REG (Pmode
, LR_REGNO
);
20939 for (insn
= NEXT_INSN (top
); insn
!= NULL_RTX
; insn
= NEXT_INSN (insn
))
20945 if (!SIBLING_CALL_P (insn
))
20948 else if (find_regno_note (insn
, REG_INC
, LR_REGNO
))
20950 else if (set_of (reg
, insn
) != NULL_RTX
20951 && !prologue_epilogue_contains (insn
))
20958 /* Emit instructions needed to load the TOC register.
20959 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
20960 a constant pool; or for SVR4 -fpic. */
20963 rs6000_emit_load_toc_table (int fromprolog
)
20966 dest
= gen_rtx_REG (Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
20968 if (TARGET_ELF
&& TARGET_SECURE_PLT
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
)
20971 rtx lab
, tmp1
, tmp2
, got
;
20973 lab
= gen_label_rtx ();
20974 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (lab
));
20975 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
20977 got
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
20979 got
= rs6000_got_sym ();
20980 tmp1
= tmp2
= dest
;
20983 tmp1
= gen_reg_rtx (Pmode
);
20984 tmp2
= gen_reg_rtx (Pmode
);
20986 emit_insn (gen_load_toc_v4_PIC_1 (lab
));
20987 emit_move_insn (tmp1
, gen_rtx_REG (Pmode
, LR_REGNO
));
20988 emit_insn (gen_load_toc_v4_PIC_3b (tmp2
, tmp1
, got
, lab
));
20989 emit_insn (gen_load_toc_v4_PIC_3c (dest
, tmp2
, got
, lab
));
20991 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 1)
20993 emit_insn (gen_load_toc_v4_pic_si ());
20994 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
20996 else if (TARGET_ELF
&& DEFAULT_ABI
== ABI_V4
&& flag_pic
== 2)
20999 rtx temp0
= (fromprolog
21000 ? gen_rtx_REG (Pmode
, 0)
21001 : gen_reg_rtx (Pmode
));
21007 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
21008 symF
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21010 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCL", rs6000_pic_labelno
);
21011 symL
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21013 emit_insn (gen_load_toc_v4_PIC_1 (symF
));
21014 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21015 emit_insn (gen_load_toc_v4_PIC_2 (temp0
, dest
, symL
, symF
));
21021 tocsym
= gen_rtx_SYMBOL_REF (Pmode
, toc_label_name
);
21022 lab
= gen_label_rtx ();
21023 emit_insn (gen_load_toc_v4_PIC_1b (tocsym
, lab
));
21024 emit_move_insn (dest
, gen_rtx_REG (Pmode
, LR_REGNO
));
21025 if (TARGET_LINK_STACK
)
21026 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (4)));
21027 emit_move_insn (temp0
, gen_rtx_MEM (Pmode
, dest
));
21029 emit_insn (gen_addsi3 (dest
, temp0
, dest
));
21031 else if (TARGET_ELF
&& !TARGET_AIX
&& flag_pic
== 0 && TARGET_MINIMAL_TOC
)
21033 /* This is for AIX code running in non-PIC ELF32. */
21036 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
21037 realsym
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
21039 emit_insn (gen_elf_high (dest
, realsym
));
21040 emit_insn (gen_elf_low (dest
, dest
, realsym
));
21044 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
21047 emit_insn (gen_load_toc_aix_si (dest
));
21049 emit_insn (gen_load_toc_aix_di (dest
));
21053 /* Emit instructions to restore the link register after determining where
21054 its value has been stored. */
21057 rs6000_emit_eh_reg_restore (rtx source
, rtx scratch
)
21059 rs6000_stack_t
*info
= rs6000_stack_info ();
21062 operands
[0] = source
;
21063 operands
[1] = scratch
;
21065 if (info
->lr_save_p
)
21067 rtx frame_rtx
= stack_pointer_rtx
;
21068 HOST_WIDE_INT sp_offset
= 0;
21071 if (frame_pointer_needed
21072 || cfun
->calls_alloca
21073 || info
->total_size
> 32767)
21075 tmp
= gen_frame_mem (Pmode
, frame_rtx
);
21076 emit_move_insn (operands
[1], tmp
);
21077 frame_rtx
= operands
[1];
21079 else if (info
->push_p
)
21080 sp_offset
= info
->total_size
;
21082 tmp
= plus_constant (Pmode
, frame_rtx
,
21083 info
->lr_save_offset
+ sp_offset
);
21084 tmp
= gen_frame_mem (Pmode
, tmp
);
21085 emit_move_insn (tmp
, operands
[0]);
21088 emit_move_insn (gen_rtx_REG (Pmode
, LR_REGNO
), operands
[0]);
21090 /* Freeze lr_save_p. We've just emitted rtl that depends on the
21091 state of lr_save_p so any change from here on would be a bug. In
21092 particular, stop rs6000_ra_ever_killed from considering the SET
21093 of lr we may have added just above. */
21094 cfun
->machine
->lr_save_state
= info
->lr_save_p
+ 1;
21097 static GTY(()) alias_set_type set
= -1;
21100 get_TOC_alias_set (void)
21103 set
= new_alias_set ();
21107 /* This returns nonzero if the current function uses the TOC. This is
21108 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
21109 is generated by the ABI_V4 load_toc_* patterns. */
21116 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
21119 rtx pat
= PATTERN (insn
);
21122 if (GET_CODE (pat
) == PARALLEL
)
21123 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
21125 rtx sub
= XVECEXP (pat
, 0, i
);
21126 if (GET_CODE (sub
) == USE
)
21128 sub
= XEXP (sub
, 0);
21129 if (GET_CODE (sub
) == UNSPEC
21130 && XINT (sub
, 1) == UNSPEC_TOC
)
21140 create_TOC_reference (rtx symbol
, rtx largetoc_reg
)
21142 rtx tocrel
, tocreg
, hi
;
21144 if (TARGET_DEBUG_ADDR
)
21146 if (GET_CODE (symbol
) == SYMBOL_REF
)
21147 fprintf (stderr
, "\ncreate_TOC_reference, (symbol_ref %s)\n",
21151 fprintf (stderr
, "\ncreate_TOC_reference, code %s:\n",
21152 GET_RTX_NAME (GET_CODE (symbol
)));
21153 debug_rtx (symbol
);
21157 if (!can_create_pseudo_p ())
21158 df_set_regs_ever_live (TOC_REGISTER
, true);
21160 tocreg
= gen_rtx_REG (Pmode
, TOC_REGISTER
);
21161 tocrel
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, symbol
, tocreg
), UNSPEC_TOCREL
);
21162 if (TARGET_CMODEL
== CMODEL_SMALL
|| can_create_pseudo_p ())
21165 hi
= gen_rtx_HIGH (Pmode
, copy_rtx (tocrel
));
21166 if (largetoc_reg
!= NULL
)
21168 emit_move_insn (largetoc_reg
, hi
);
21171 return gen_rtx_LO_SUM (Pmode
, hi
, tocrel
);
21174 /* Issue assembly directives that create a reference to the given DWARF
21175 FRAME_TABLE_LABEL from the current function section. */
21177 rs6000_aix_asm_output_dwarf_table_ref (char * frame_table_label
)
21179 fprintf (asm_out_file
, "\t.ref %s\n",
21180 (* targetm
.strip_name_encoding
) (frame_table_label
));
21183 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
21184 and the change to the stack pointer. */
21187 rs6000_emit_stack_tie (rtx fp
, bool hard_frame_needed
)
21194 regs
[i
++] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21195 if (hard_frame_needed
)
21196 regs
[i
++] = gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
21197 if (!(REGNO (fp
) == STACK_POINTER_REGNUM
21198 || (hard_frame_needed
21199 && REGNO (fp
) == HARD_FRAME_POINTER_REGNUM
)))
21202 p
= rtvec_alloc (i
);
21205 rtx mem
= gen_frame_mem (BLKmode
, regs
[i
]);
21206 RTVEC_ELT (p
, i
) = gen_rtx_SET (VOIDmode
, mem
, const0_rtx
);
21209 emit_insn (gen_stack_tie (gen_rtx_PARALLEL (VOIDmode
, p
)));
21212 /* Emit the correct code for allocating stack space, as insns.
21213 If COPY_REG, make sure a copy of the old frame is left there.
21214 The generated code may use hard register 0 as a temporary. */
21217 rs6000_emit_allocate_stack (HOST_WIDE_INT size
, rtx copy_reg
, int copy_off
)
21220 rtx stack_reg
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
21221 rtx tmp_reg
= gen_rtx_REG (Pmode
, 0);
21222 rtx todec
= gen_int_mode (-size
, Pmode
);
21225 if (INTVAL (todec
) != -size
)
21227 warning (0, "stack frame too large");
21228 emit_insn (gen_trap ());
21232 if (crtl
->limit_stack
)
21234 if (REG_P (stack_limit_rtx
)
21235 && REGNO (stack_limit_rtx
) > 1
21236 && REGNO (stack_limit_rtx
) <= 31)
21238 emit_insn (gen_add3_insn (tmp_reg
, stack_limit_rtx
, GEN_INT (size
)));
21239 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21242 else if (GET_CODE (stack_limit_rtx
) == SYMBOL_REF
21244 && DEFAULT_ABI
== ABI_V4
)
21246 rtx toload
= gen_rtx_CONST (VOIDmode
,
21247 gen_rtx_PLUS (Pmode
,
21251 emit_insn (gen_elf_high (tmp_reg
, toload
));
21252 emit_insn (gen_elf_low (tmp_reg
, tmp_reg
, toload
));
21253 emit_insn (gen_cond_trap (LTU
, stack_reg
, tmp_reg
,
21257 warning (0, "stack limit expression is not supported");
21263 emit_insn (gen_add3_insn (copy_reg
, stack_reg
, GEN_INT (copy_off
)));
21265 emit_move_insn (copy_reg
, stack_reg
);
21270 /* Need a note here so that try_split doesn't get confused. */
21271 if (get_last_insn () == NULL_RTX
)
21272 emit_note (NOTE_INSN_DELETED
);
21273 insn
= emit_move_insn (tmp_reg
, todec
);
21274 try_split (PATTERN (insn
), insn
, 0);
21278 insn
= emit_insn (TARGET_32BIT
21279 ? gen_movsi_update_stack (stack_reg
, stack_reg
,
21281 : gen_movdi_di_update_stack (stack_reg
, stack_reg
,
21282 todec
, stack_reg
));
21283 /* Since we didn't use gen_frame_mem to generate the MEM, grab
21284 it now and set the alias set/attributes. The above gen_*_update
21285 calls will generate a PARALLEL with the MEM set being the first
21287 par
= PATTERN (insn
);
21288 gcc_assert (GET_CODE (par
) == PARALLEL
);
21289 set
= XVECEXP (par
, 0, 0);
21290 gcc_assert (GET_CODE (set
) == SET
);
21291 mem
= SET_DEST (set
);
21292 gcc_assert (MEM_P (mem
));
21293 MEM_NOTRAP_P (mem
) = 1;
21294 set_mem_alias_set (mem
, get_frame_alias_set ());
21296 RTX_FRAME_RELATED_P (insn
) = 1;
21297 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
21298 gen_rtx_SET (VOIDmode
, stack_reg
,
21299 gen_rtx_PLUS (Pmode
, stack_reg
,
21300 GEN_INT (-size
))));
21303 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
21305 #if PROBE_INTERVAL > 32768
21306 #error Cannot use indexed addressing mode for stack probing
21309 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
21310 inclusive. These are offsets from the current stack pointer. */
21313 rs6000_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
21315 /* See if we have a constant small number of probes to generate. If so,
21316 that's the easy case. */
21317 if (first
+ size
<= 32768)
21321 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
21322 it exceeds SIZE. If only one probe is needed, this will not
21323 generate any code. Then probe at FIRST + SIZE. */
21324 for (i
= PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
21325 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
21328 emit_stack_probe (plus_constant (Pmode
, stack_pointer_rtx
,
21332 /* Otherwise, do the same as above, but in a loop. Note that we must be
21333 extra careful with variables wrapping around because we might be at
21334 the very top (or the very bottom) of the address space and we have
21335 to be able to handle this case properly; in particular, we use an
21336 equality test for the loop condition. */
21339 HOST_WIDE_INT rounded_size
;
21340 rtx r12
= gen_rtx_REG (Pmode
, 12);
21341 rtx r0
= gen_rtx_REG (Pmode
, 0);
21343 /* Sanity check for the addressing mode we're going to use. */
21344 gcc_assert (first
<= 32768);
21346 /* Step 1: round SIZE to the previous multiple of the interval. */
21348 rounded_size
= size
& -PROBE_INTERVAL
;
21351 /* Step 2: compute initial and final value of the loop counter. */
21353 /* TEST_ADDR = SP + FIRST. */
21354 emit_insn (gen_rtx_SET (VOIDmode
, r12
,
21355 plus_constant (Pmode
, stack_pointer_rtx
,
21358 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
21359 if (rounded_size
> 32768)
21361 emit_move_insn (r0
, GEN_INT (-rounded_size
));
21362 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
21363 gen_rtx_PLUS (Pmode
, r12
, r0
)));
21366 emit_insn (gen_rtx_SET (VOIDmode
, r0
,
21367 plus_constant (Pmode
, r12
, -rounded_size
)));
21370 /* Step 3: the loop
21372 while (TEST_ADDR != LAST_ADDR)
21374 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
21378 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
21379 until it is equal to ROUNDED_SIZE. */
21382 emit_insn (gen_probe_stack_rangedi (r12
, r12
, r0
));
21384 emit_insn (gen_probe_stack_rangesi (r12
, r12
, r0
));
21387 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
21388 that SIZE is equal to ROUNDED_SIZE. */
21390 if (size
!= rounded_size
)
21391 emit_stack_probe (plus_constant (Pmode
, r12
, rounded_size
- size
));
21395 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
21396 absolute addresses. */
21399 output_probe_stack_range (rtx reg1
, rtx reg2
)
21401 static int labelno
= 0;
21402 char loop_lab
[32], end_lab
[32];
21405 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
21406 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
21408 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
21410 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
21414 output_asm_insn ("cmpd 0,%0,%1", xops
);
21416 output_asm_insn ("cmpw 0,%0,%1", xops
);
21418 fputs ("\tbeq 0,", asm_out_file
);
21419 assemble_name_raw (asm_out_file
, end_lab
);
21420 fputc ('\n', asm_out_file
);
21422 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
21423 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
21424 output_asm_insn ("addi %0,%0,%1", xops
);
21426 /* Probe at TEST_ADDR and branch. */
21427 xops
[1] = gen_rtx_REG (Pmode
, 0);
21428 output_asm_insn ("stw %1,0(%0)", xops
);
21429 fprintf (asm_out_file
, "\tb ");
21430 assemble_name_raw (asm_out_file
, loop_lab
);
21431 fputc ('\n', asm_out_file
);
21433 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
21438 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
21439 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
21440 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
21441 deduce these equivalences by itself so it wasn't necessary to hold
21442 its hand so much. Don't be tempted to always supply d2_f_d_e with
21443 the actual cfa register, ie. r31 when we are using a hard frame
21444 pointer. That fails when saving regs off r1, and sched moves the
21445 r31 setup past the reg saves. */
21448 rs6000_frame_related (rtx insn
, rtx reg
, HOST_WIDE_INT val
,
21449 rtx reg2
, rtx rreg
, rtx split_reg
)
21453 if (REGNO (reg
) == STACK_POINTER_REGNUM
&& reg2
== NULL_RTX
)
21455 /* No need for any replacement. Just set RTX_FRAME_RELATED_P. */
21458 gcc_checking_assert (val
== 0);
21459 real
= PATTERN (insn
);
21460 if (GET_CODE (real
) == PARALLEL
)
21461 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
21462 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
21464 rtx set
= XVECEXP (real
, 0, i
);
21466 RTX_FRAME_RELATED_P (set
) = 1;
21468 RTX_FRAME_RELATED_P (insn
) = 1;
21472 /* copy_rtx will not make unique copies of registers, so we need to
21473 ensure we don't have unwanted sharing here. */
21475 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
21478 reg
= gen_raw_REG (GET_MODE (reg
), REGNO (reg
));
21480 real
= copy_rtx (PATTERN (insn
));
21482 if (reg2
!= NULL_RTX
)
21483 real
= replace_rtx (real
, reg2
, rreg
);
21485 if (REGNO (reg
) == STACK_POINTER_REGNUM
)
21486 gcc_checking_assert (val
== 0);
21488 real
= replace_rtx (real
, reg
,
21489 gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
,
21490 STACK_POINTER_REGNUM
),
21493 /* We expect that 'real' is either a SET or a PARALLEL containing
21494 SETs (and possibly other stuff). In a PARALLEL, all the SETs
21495 are important so they all have to be marked RTX_FRAME_RELATED_P. */
21497 if (GET_CODE (real
) == SET
)
21501 temp
= simplify_rtx (SET_SRC (set
));
21503 SET_SRC (set
) = temp
;
21504 temp
= simplify_rtx (SET_DEST (set
));
21506 SET_DEST (set
) = temp
;
21507 if (GET_CODE (SET_DEST (set
)) == MEM
)
21509 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
21511 XEXP (SET_DEST (set
), 0) = temp
;
21518 gcc_assert (GET_CODE (real
) == PARALLEL
);
21519 for (i
= 0; i
< XVECLEN (real
, 0); i
++)
21520 if (GET_CODE (XVECEXP (real
, 0, i
)) == SET
)
21522 rtx set
= XVECEXP (real
, 0, i
);
21524 temp
= simplify_rtx (SET_SRC (set
));
21526 SET_SRC (set
) = temp
;
21527 temp
= simplify_rtx (SET_DEST (set
));
21529 SET_DEST (set
) = temp
;
21530 if (GET_CODE (SET_DEST (set
)) == MEM
)
21532 temp
= simplify_rtx (XEXP (SET_DEST (set
), 0));
21534 XEXP (SET_DEST (set
), 0) = temp
;
21536 RTX_FRAME_RELATED_P (set
) = 1;
21540 /* If a store insn has been split into multiple insns, the
21541 true source register is given by split_reg. */
21542 if (split_reg
!= NULL_RTX
)
21543 real
= gen_rtx_SET (VOIDmode
, SET_DEST (real
), split_reg
);
21545 RTX_FRAME_RELATED_P (insn
) = 1;
21546 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, real
);
21551 /* Returns an insn that has a vrsave set operation with the
21552 appropriate CLOBBERs. */
21555 generate_set_vrsave (rtx reg
, rs6000_stack_t
*info
, int epiloguep
)
21558 rtx insn
, clobs
[TOTAL_ALTIVEC_REGS
+ 1];
21559 rtx vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
21562 = gen_rtx_SET (VOIDmode
,
21564 gen_rtx_UNSPEC_VOLATILE (SImode
,
21565 gen_rtvec (2, reg
, vrsave
),
21566 UNSPECV_SET_VRSAVE
));
21570 /* We need to clobber the registers in the mask so the scheduler
21571 does not move sets to VRSAVE before sets of AltiVec registers.
21573 However, if the function receives nonlocal gotos, reload will set
21574 all call saved registers live. We will end up with:
21576 (set (reg 999) (mem))
21577 (parallel [ (set (reg vrsave) (unspec blah))
21578 (clobber (reg 999))])
21580 The clobber will cause the store into reg 999 to be dead, and
21581 flow will attempt to delete an epilogue insn. In this case, we
21582 need an unspec use/set of the register. */
21584 for (i
= FIRST_ALTIVEC_REGNO
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
21585 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
21587 if (!epiloguep
|| call_used_regs
[i
])
21588 clobs
[nclobs
++] = gen_rtx_CLOBBER (VOIDmode
,
21589 gen_rtx_REG (V4SImode
, i
));
21592 rtx reg
= gen_rtx_REG (V4SImode
, i
);
21595 = gen_rtx_SET (VOIDmode
,
21597 gen_rtx_UNSPEC (V4SImode
,
21598 gen_rtvec (1, reg
), 27));
21602 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (nclobs
));
21604 for (i
= 0; i
< nclobs
; ++i
)
21605 XVECEXP (insn
, 0, i
) = clobs
[i
];
21611 gen_frame_set (rtx reg
, rtx frame_reg
, int offset
, bool store
)
21615 addr
= gen_rtx_PLUS (Pmode
, frame_reg
, GEN_INT (offset
));
21616 mem
= gen_frame_mem (GET_MODE (reg
), addr
);
21617 return gen_rtx_SET (VOIDmode
, store
? mem
: reg
, store
? reg
: mem
);
21621 gen_frame_load (rtx reg
, rtx frame_reg
, int offset
)
21623 return gen_frame_set (reg
, frame_reg
, offset
, false);
21627 gen_frame_store (rtx reg
, rtx frame_reg
, int offset
)
21629 return gen_frame_set (reg
, frame_reg
, offset
, true);
21632 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
21633 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
21636 emit_frame_save (rtx frame_reg
, enum machine_mode mode
,
21637 unsigned int regno
, int offset
, HOST_WIDE_INT frame_reg_to_sp
)
21641 /* Some cases that need register indexed addressing. */
21642 gcc_checking_assert (!((TARGET_ALTIVEC_ABI
&& ALTIVEC_VECTOR_MODE (mode
))
21643 || (TARGET_VSX
&& ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
21644 || (TARGET_E500_DOUBLE
&& mode
== DFmode
)
21646 && SPE_VECTOR_MODE (mode
)
21647 && !SPE_CONST_OFFSET_OK (offset
))));
21649 reg
= gen_rtx_REG (mode
, regno
);
21650 insn
= emit_insn (gen_frame_store (reg
, frame_reg
, offset
));
21651 return rs6000_frame_related (insn
, frame_reg
, frame_reg_to_sp
,
21652 NULL_RTX
, NULL_RTX
, NULL_RTX
);
21655 /* Emit an offset memory reference suitable for a frame store, while
21656 converting to a valid addressing mode. */
21659 gen_frame_mem_offset (enum machine_mode mode
, rtx reg
, int offset
)
21661 rtx int_rtx
, offset_rtx
;
21663 int_rtx
= GEN_INT (offset
);
21665 if ((TARGET_SPE_ABI
&& SPE_VECTOR_MODE (mode
) && !SPE_CONST_OFFSET_OK (offset
))
21666 || (TARGET_E500_DOUBLE
&& mode
== DFmode
))
21668 offset_rtx
= gen_rtx_REG (Pmode
, FIXED_SCRATCH
);
21669 emit_move_insn (offset_rtx
, int_rtx
);
21672 offset_rtx
= int_rtx
;
21674 return gen_frame_mem (mode
, gen_rtx_PLUS (Pmode
, reg
, offset_rtx
));
21677 #ifndef TARGET_FIX_AND_CONTINUE
21678 #define TARGET_FIX_AND_CONTINUE 0
21681 /* It's really GPR 13 or 14, FPR 14 and VR 20. We need the smallest. */
21682 #define FIRST_SAVRES_REGISTER FIRST_SAVED_GP_REGNO
21683 #define LAST_SAVRES_REGISTER 31
21684 #define N_SAVRES_REGISTERS (LAST_SAVRES_REGISTER - FIRST_SAVRES_REGISTER + 1)
21695 static GTY(()) rtx savres_routine_syms
[N_SAVRES_REGISTERS
][12];
21697 /* Temporary holding space for an out-of-line register save/restore
21699 static char savres_routine_name
[30];
21701 /* Return the name for an out-of-line register save/restore routine.
21702 We are saving/restoring GPRs if GPR is true. */
21705 rs6000_savres_routine_name (rs6000_stack_t
*info
, int regno
, int sel
)
21707 const char *prefix
= "";
21708 const char *suffix
= "";
21710 /* Different targets are supposed to define
21711 {SAVE,RESTORE}_FP_{PREFIX,SUFFIX} with the idea that the needed
21712 routine name could be defined with:
21714 sprintf (name, "%s%d%s", SAVE_FP_PREFIX, regno, SAVE_FP_SUFFIX)
21716 This is a nice idea in practice, but in reality, things are
21717 complicated in several ways:
21719 - ELF targets have save/restore routines for GPRs.
21721 - SPE targets use different prefixes for 32/64-bit registers, and
21722 neither of them fit neatly in the FOO_{PREFIX,SUFFIX} regimen.
21724 - PPC64 ELF targets have routines for save/restore of GPRs that
21725 differ in what they do with the link register, so having a set
21726 prefix doesn't work. (We only use one of the save routines at
21727 the moment, though.)
21729 - PPC32 elf targets have "exit" versions of the restore routines
21730 that restore the link register and can save some extra space.
21731 These require an extra suffix. (There are also "tail" versions
21732 of the restore routines and "GOT" versions of the save routines,
21733 but we don't generate those at present. Same problems apply,
21736 We deal with all this by synthesizing our own prefix/suffix and
21737 using that for the simple sprintf call shown above. */
21740 /* No floating point saves on the SPE. */
21741 gcc_assert ((sel
& SAVRES_REG
) == SAVRES_GPR
);
21743 if ((sel
& SAVRES_SAVE
))
21744 prefix
= info
->spe_64bit_regs_used
? "_save64gpr_" : "_save32gpr_";
21746 prefix
= info
->spe_64bit_regs_used
? "_rest64gpr_" : "_rest32gpr_";
21748 if ((sel
& SAVRES_LR
))
21751 else if (DEFAULT_ABI
== ABI_V4
)
21756 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21757 prefix
= (sel
& SAVRES_SAVE
) ? "_savegpr_" : "_restgpr_";
21758 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21759 prefix
= (sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_";
21760 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21761 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
21765 if ((sel
& SAVRES_LR
))
21768 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21770 #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD)
21771 /* No out-of-line save/restore routines for GPRs on AIX. */
21772 gcc_assert (!TARGET_AIX
|| (sel
& SAVRES_REG
) != SAVRES_GPR
);
21776 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21777 prefix
= ((sel
& SAVRES_SAVE
)
21778 ? ((sel
& SAVRES_LR
) ? "_savegpr0_" : "_savegpr1_")
21779 : ((sel
& SAVRES_LR
) ? "_restgpr0_" : "_restgpr1_"));
21780 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21782 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
21783 if ((sel
& SAVRES_LR
))
21784 prefix
= ((sel
& SAVRES_SAVE
) ? "_savefpr_" : "_restfpr_");
21788 prefix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_PREFIX
: RESTORE_FP_PREFIX
;
21789 suffix
= (sel
& SAVRES_SAVE
) ? SAVE_FP_SUFFIX
: RESTORE_FP_SUFFIX
;
21792 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21793 prefix
= (sel
& SAVRES_SAVE
) ? "_savevr_" : "_restvr_";
21798 if (DEFAULT_ABI
== ABI_DARWIN
)
21800 /* The Darwin approach is (slightly) different, in order to be
21801 compatible with code generated by the system toolchain. There is a
21802 single symbol for the start of save sequence, and the code here
21803 embeds an offset into that code on the basis of the first register
21805 prefix
= (sel
& SAVRES_SAVE
) ? "save" : "rest" ;
21806 if ((sel
& SAVRES_REG
) == SAVRES_GPR
)
21807 sprintf (savres_routine_name
, "*%sGPR%s%s%.0d ; %s r%d-r31", prefix
,
21808 ((sel
& SAVRES_LR
) ? "x" : ""), (regno
== 13 ? "" : "+"),
21809 (regno
- 13) * 4, prefix
, regno
);
21810 else if ((sel
& SAVRES_REG
) == SAVRES_FPR
)
21811 sprintf (savres_routine_name
, "*%sFP%s%.0d ; %s f%d-f31", prefix
,
21812 (regno
== 14 ? "" : "+"), (regno
- 14) * 4, prefix
, regno
);
21813 else if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21814 sprintf (savres_routine_name
, "*%sVEC%s%.0d ; %s v%d-v31", prefix
,
21815 (regno
== 20 ? "" : "+"), (regno
- 20) * 8, prefix
, regno
);
21820 sprintf (savres_routine_name
, "%s%d%s", prefix
, regno
, suffix
);
21822 return savres_routine_name
;
21825 /* Return an RTL SYMBOL_REF for an out-of-line register save/restore routine.
21826 We are saving/restoring GPRs if GPR is true. */
21829 rs6000_savres_routine_sym (rs6000_stack_t
*info
, int sel
)
21831 int regno
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21832 ? info
->first_gp_reg_save
21833 : (sel
& SAVRES_REG
) == SAVRES_FPR
21834 ? info
->first_fp_reg_save
- 32
21835 : (sel
& SAVRES_REG
) == SAVRES_VR
21836 ? info
->first_altivec_reg_save
- FIRST_ALTIVEC_REGNO
21841 /* On the SPE, we never have any FPRs, but we do have 32/64-bit
21842 versions of the gpr routines. */
21843 if (TARGET_SPE_ABI
&& (sel
& SAVRES_REG
) == SAVRES_GPR
21844 && info
->spe_64bit_regs_used
)
21845 select
^= SAVRES_FPR
^ SAVRES_GPR
;
21847 /* Don't generate bogus routine names. */
21848 gcc_assert (FIRST_SAVRES_REGISTER
<= regno
21849 && regno
<= LAST_SAVRES_REGISTER
21850 && select
>= 0 && select
<= 12);
21852 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
];
21858 name
= rs6000_savres_routine_name (info
, regno
, sel
);
21860 sym
= savres_routine_syms
[regno
-FIRST_SAVRES_REGISTER
][select
]
21861 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
21862 SYMBOL_REF_FLAGS (sym
) |= SYMBOL_FLAG_FUNCTION
;
21868 /* Emit a sequence of insns, including a stack tie if needed, for
21869 resetting the stack pointer. If UPDT_REGNO is not 1, then don't
21870 reset the stack pointer, but move the base of the frame into
21871 reg UPDT_REGNO for use by out-of-line register restore routines. */
21874 rs6000_emit_stack_reset (rs6000_stack_t
*info
,
21875 rtx frame_reg_rtx
, HOST_WIDE_INT frame_off
,
21876 unsigned updt_regno
)
21880 /* This blockage is needed so that sched doesn't decide to move
21881 the sp change before the register restores. */
21882 if (DEFAULT_ABI
== ABI_V4
21884 && info
->spe_64bit_regs_used
!= 0
21885 && info
->first_gp_reg_save
!= 32))
21886 rs6000_emit_stack_tie (frame_reg_rtx
, frame_pointer_needed
);
21888 /* If we are restoring registers out-of-line, we will be using the
21889 "exit" variants of the restore routines, which will reset the
21890 stack for us. But we do need to point updt_reg into the
21891 right place for those routines. */
21892 updt_reg_rtx
= gen_rtx_REG (Pmode
, updt_regno
);
21894 if (frame_off
!= 0)
21895 return emit_insn (gen_add3_insn (updt_reg_rtx
,
21896 frame_reg_rtx
, GEN_INT (frame_off
)));
21897 else if (REGNO (frame_reg_rtx
) != updt_regno
)
21898 return emit_move_insn (updt_reg_rtx
, frame_reg_rtx
);
21903 /* Return the register number used as a pointer by out-of-line
21904 save/restore functions. */
21906 static inline unsigned
21907 ptr_regno_for_savres (int sel
)
21909 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
21910 return (sel
& SAVRES_REG
) == SAVRES_FPR
|| (sel
& SAVRES_LR
) ? 1 : 12;
21911 return DEFAULT_ABI
== ABI_DARWIN
&& (sel
& SAVRES_REG
) == SAVRES_FPR
? 1 : 11;
21914 /* Construct a parallel rtx describing the effect of a call to an
21915 out-of-line register save/restore routine, and emit the insn
21916 or jump_insn as appropriate. */
21919 rs6000_emit_savres_rtx (rs6000_stack_t
*info
,
21920 rtx frame_reg_rtx
, int save_area_offset
, int lr_offset
,
21921 enum machine_mode reg_mode
, int sel
)
21924 int offset
, start_reg
, end_reg
, n_regs
, use_reg
;
21925 int reg_size
= GET_MODE_SIZE (reg_mode
);
21931 start_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21932 ? info
->first_gp_reg_save
21933 : (sel
& SAVRES_REG
) == SAVRES_FPR
21934 ? info
->first_fp_reg_save
21935 : (sel
& SAVRES_REG
) == SAVRES_VR
21936 ? info
->first_altivec_reg_save
21938 end_reg
= ((sel
& SAVRES_REG
) == SAVRES_GPR
21940 : (sel
& SAVRES_REG
) == SAVRES_FPR
21942 : (sel
& SAVRES_REG
) == SAVRES_VR
21943 ? LAST_ALTIVEC_REGNO
+ 1
21945 n_regs
= end_reg
- start_reg
;
21946 p
= rtvec_alloc (3 + ((sel
& SAVRES_LR
) ? 1 : 0)
21947 + ((sel
& SAVRES_REG
) == SAVRES_VR
? 1 : 0)
21950 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21951 RTVEC_ELT (p
, offset
++) = ret_rtx
;
21953 RTVEC_ELT (p
, offset
++)
21954 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
21956 sym
= rs6000_savres_routine_sym (info
, sel
);
21957 RTVEC_ELT (p
, offset
++) = gen_rtx_USE (VOIDmode
, sym
);
21959 use_reg
= ptr_regno_for_savres (sel
);
21960 if ((sel
& SAVRES_REG
) == SAVRES_VR
)
21962 /* Vector regs are saved/restored using [reg+reg] addressing. */
21963 RTVEC_ELT (p
, offset
++)
21964 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
21965 RTVEC_ELT (p
, offset
++)
21966 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, 0));
21969 RTVEC_ELT (p
, offset
++)
21970 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, use_reg
));
21972 for (i
= 0; i
< end_reg
- start_reg
; i
++)
21973 RTVEC_ELT (p
, i
+ offset
)
21974 = gen_frame_set (gen_rtx_REG (reg_mode
, start_reg
+ i
),
21975 frame_reg_rtx
, save_area_offset
+ reg_size
* i
,
21976 (sel
& SAVRES_SAVE
) != 0);
21978 if ((sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21979 RTVEC_ELT (p
, i
+ offset
)
21980 = gen_frame_store (gen_rtx_REG (Pmode
, 0), frame_reg_rtx
, lr_offset
);
21982 par
= gen_rtx_PARALLEL (VOIDmode
, p
);
21984 if (!(sel
& SAVRES_SAVE
) && (sel
& SAVRES_LR
))
21986 insn
= emit_jump_insn (par
);
21987 JUMP_LABEL (insn
) = ret_rtx
;
21990 insn
= emit_insn (par
);
21994 /* Emit code to store CR fields that need to be saved into REG. */
21997 rs6000_emit_move_from_cr (rtx reg
)
21999 /* Only the ELFv2 ABI allows storing only selected fields. */
22000 if (DEFAULT_ABI
== ABI_ELFv2
&& TARGET_MFCRF
)
22002 int i
, cr_reg
[8], count
= 0;
22004 /* Collect CR fields that must be saved. */
22005 for (i
= 0; i
< 8; i
++)
22006 if (save_reg_p (CR0_REGNO
+ i
))
22007 cr_reg
[count
++] = i
;
22009 /* If it's just a single one, use mfcrf. */
22012 rtvec p
= rtvec_alloc (1);
22013 rtvec r
= rtvec_alloc (2);
22014 RTVEC_ELT (r
, 0) = gen_rtx_REG (CCmode
, CR0_REGNO
+ cr_reg
[0]);
22015 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7 - cr_reg
[0]));
22017 = gen_rtx_SET (VOIDmode
, reg
,
22018 gen_rtx_UNSPEC (SImode
, r
, UNSPEC_MOVESI_FROM_CR
));
22020 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22024 /* ??? It might be better to handle count == 2 / 3 cases here
22025 as well, using logical operations to combine the values. */
22028 emit_insn (gen_movesi_from_cr (reg
));
22031 /* Determine whether the gp REG is really used. */
22034 rs6000_reg_live_or_pic_offset_p (int reg
)
22036 /* If the function calls eh_return, claim used all the registers that would
22037 be checked for liveness otherwise. This is required for the PIC offset
22038 register with -mminimal-toc on AIX, as it is advertised as "fixed" for
22039 register allocation purposes in this case. */
22041 return (((crtl
->calls_eh_return
|| df_regs_ever_live_p (reg
))
22042 && (!call_used_regs
[reg
]
22043 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22044 && !TARGET_SINGLE_PIC_BASE
22045 && TARGET_TOC
&& TARGET_MINIMAL_TOC
)))
22046 || (reg
== RS6000_PIC_OFFSET_TABLE_REGNUM
22047 && !TARGET_SINGLE_PIC_BASE
22048 && ((DEFAULT_ABI
== ABI_V4
&& flag_pic
!= 0)
22049 || (DEFAULT_ABI
== ABI_DARWIN
&& flag_pic
))));
22052 /* Emit function prologue as insns. */
22055 rs6000_emit_prologue (void)
22057 rs6000_stack_t
*info
= rs6000_stack_info ();
22058 enum machine_mode reg_mode
= Pmode
;
22059 int reg_size
= TARGET_32BIT
? 4 : 8;
22060 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
22061 rtx frame_reg_rtx
= sp_reg_rtx
;
22062 unsigned int cr_save_regno
;
22063 rtx cr_save_rtx
= NULL_RTX
;
22066 int using_static_chain_p
= (cfun
->static_chain_decl
!= NULL_TREE
22067 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM
)
22068 && call_used_regs
[STATIC_CHAIN_REGNUM
]);
22069 /* Offset to top of frame for frame_reg and sp respectively. */
22070 HOST_WIDE_INT frame_off
= 0;
22071 HOST_WIDE_INT sp_off
= 0;
22073 #ifdef ENABLE_CHECKING
22074 /* Track and check usage of r0, r11, r12. */
22075 int reg_inuse
= using_static_chain_p
? 1 << 11 : 0;
22076 #define START_USE(R) do \
22078 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22079 reg_inuse |= 1 << (R); \
22081 #define END_USE(R) do \
22083 gcc_assert ((reg_inuse & (1 << (R))) != 0); \
22084 reg_inuse &= ~(1 << (R)); \
22086 #define NOT_INUSE(R) do \
22088 gcc_assert ((reg_inuse & (1 << (R))) == 0); \
22091 #define START_USE(R) do {} while (0)
22092 #define END_USE(R) do {} while (0)
22093 #define NOT_INUSE(R) do {} while (0)
22096 if (DEFAULT_ABI
== ABI_ELFv2
)
22098 cfun
->machine
->r2_setup_needed
= df_regs_ever_live_p (TOC_REGNUM
);
22100 /* With -mminimal-toc we may generate an extra use of r2 below. */
22101 if (!TARGET_SINGLE_PIC_BASE
22102 && TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22103 cfun
->machine
->r2_setup_needed
= true;
22107 if (flag_stack_usage_info
)
22108 current_function_static_stack_size
= info
->total_size
;
22110 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
22112 HOST_WIDE_INT size
= info
->total_size
;
22114 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
22116 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
22117 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
,
22118 size
- STACK_CHECK_PROTECT
);
22121 rs6000_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
22124 if (TARGET_FIX_AND_CONTINUE
)
22126 /* gdb on darwin arranges to forward a function from the old
22127 address by modifying the first 5 instructions of the function
22128 to branch to the overriding function. This is necessary to
22129 permit function pointers that point to the old function to
22130 actually forward to the new function. */
22131 emit_insn (gen_nop ());
22132 emit_insn (gen_nop ());
22133 emit_insn (gen_nop ());
22134 emit_insn (gen_nop ());
22135 emit_insn (gen_nop ());
22138 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
22140 reg_mode
= V2SImode
;
22144 /* Handle world saves specially here. */
22145 if (WORLD_SAVE_P (info
))
22152 /* save_world expects lr in r0. */
22153 reg0
= gen_rtx_REG (Pmode
, 0);
22154 if (info
->lr_save_p
)
22156 insn
= emit_move_insn (reg0
,
22157 gen_rtx_REG (Pmode
, LR_REGNO
));
22158 RTX_FRAME_RELATED_P (insn
) = 1;
22161 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
22162 assumptions about the offsets of various bits of the stack
22164 gcc_assert (info
->gp_save_offset
== -220
22165 && info
->fp_save_offset
== -144
22166 && info
->lr_save_offset
== 8
22167 && info
->cr_save_offset
== 4
22170 && (!crtl
->calls_eh_return
22171 || info
->ehrd_offset
== -432)
22172 && info
->vrsave_save_offset
== -224
22173 && info
->altivec_save_offset
== -416);
22175 treg
= gen_rtx_REG (SImode
, 11);
22176 emit_move_insn (treg
, GEN_INT (-info
->total_size
));
22178 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
22179 in R11. It also clobbers R12, so beware! */
22181 /* Preserve CR2 for save_world prologues */
22183 sz
+= 32 - info
->first_gp_reg_save
;
22184 sz
+= 64 - info
->first_fp_reg_save
;
22185 sz
+= LAST_ALTIVEC_REGNO
- info
->first_altivec_reg_save
+ 1;
22186 p
= rtvec_alloc (sz
);
22188 RTVEC_ELT (p
, j
++) = gen_rtx_CLOBBER (VOIDmode
,
22189 gen_rtx_REG (SImode
,
22191 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
22192 gen_rtx_SYMBOL_REF (Pmode
,
22194 /* We do floats first so that the instruction pattern matches
22196 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22198 = gen_frame_store (gen_rtx_REG (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22200 info
->first_fp_reg_save
+ i
),
22202 info
->fp_save_offset
+ frame_off
+ 8 * i
);
22203 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
22205 = gen_frame_store (gen_rtx_REG (V4SImode
,
22206 info
->first_altivec_reg_save
+ i
),
22208 info
->altivec_save_offset
+ frame_off
+ 16 * i
);
22209 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22211 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22213 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22215 /* CR register traditionally saved as CR2. */
22217 = gen_frame_store (gen_rtx_REG (SImode
, CR2_REGNO
),
22218 frame_reg_rtx
, info
->cr_save_offset
+ frame_off
);
22219 /* Explain about use of R0. */
22220 if (info
->lr_save_p
)
22222 = gen_frame_store (reg0
,
22223 frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
22224 /* Explain what happens to the stack pointer. */
22226 rtx newval
= gen_rtx_PLUS (Pmode
, sp_reg_rtx
, treg
);
22227 RTVEC_ELT (p
, j
++) = gen_rtx_SET (VOIDmode
, sp_reg_rtx
, newval
);
22230 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22231 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22232 treg
, GEN_INT (-info
->total_size
), NULL_RTX
);
22233 sp_off
= frame_off
= info
->total_size
;
22236 strategy
= info
->savres_strategy
;
22238 /* For V.4, update stack before we do any saving and set back pointer. */
22239 if (! WORLD_SAVE_P (info
)
22241 && (DEFAULT_ABI
== ABI_V4
22242 || crtl
->calls_eh_return
))
22244 bool need_r11
= (TARGET_SPE
22245 ? (!(strategy
& SAVE_INLINE_GPRS
)
22246 && info
->spe_64bit_regs_used
== 0)
22247 : (!(strategy
& SAVE_INLINE_FPRS
)
22248 || !(strategy
& SAVE_INLINE_GPRS
)
22249 || !(strategy
& SAVE_INLINE_VRS
)));
22250 int ptr_regno
= -1;
22251 rtx ptr_reg
= NULL_RTX
;
22254 if (info
->total_size
< 32767)
22255 frame_off
= info
->total_size
;
22258 else if (info
->cr_save_p
22260 || info
->first_fp_reg_save
< 64
22261 || info
->first_gp_reg_save
< 32
22262 || info
->altivec_size
!= 0
22263 || info
->vrsave_mask
!= 0
22264 || crtl
->calls_eh_return
)
22268 /* The prologue won't be saving any regs so there is no need
22269 to set up a frame register to access any frame save area.
22270 We also won't be using frame_off anywhere below, but set
22271 the correct value anyway to protect against future
22272 changes to this function. */
22273 frame_off
= info
->total_size
;
22275 if (ptr_regno
!= -1)
22277 /* Set up the frame offset to that needed by the first
22278 out-of-line save function. */
22279 START_USE (ptr_regno
);
22280 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22281 frame_reg_rtx
= ptr_reg
;
22282 if (!(strategy
& SAVE_INLINE_FPRS
) && info
->fp_size
!= 0)
22283 gcc_checking_assert (info
->fp_save_offset
+ info
->fp_size
== 0);
22284 else if (!(strategy
& SAVE_INLINE_GPRS
) && info
->first_gp_reg_save
< 32)
22285 ptr_off
= info
->gp_save_offset
+ info
->gp_size
;
22286 else if (!(strategy
& SAVE_INLINE_VRS
) && info
->altivec_size
!= 0)
22287 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22288 frame_off
= -ptr_off
;
22290 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22291 sp_off
= info
->total_size
;
22292 if (frame_reg_rtx
!= sp_reg_rtx
)
22293 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22296 /* If we use the link register, get it into r0. */
22297 if (!WORLD_SAVE_P (info
) && info
->lr_save_p
)
22299 rtx addr
, reg
, mem
;
22301 reg
= gen_rtx_REG (Pmode
, 0);
22303 insn
= emit_move_insn (reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22304 RTX_FRAME_RELATED_P (insn
) = 1;
22306 if (!(strategy
& (SAVE_NOINLINE_GPRS_SAVES_LR
22307 | SAVE_NOINLINE_FPRS_SAVES_LR
)))
22309 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22310 GEN_INT (info
->lr_save_offset
+ frame_off
));
22311 mem
= gen_rtx_MEM (Pmode
, addr
);
22312 /* This should not be of rs6000_sr_alias_set, because of
22313 __builtin_return_address. */
22315 insn
= emit_move_insn (mem
, reg
);
22316 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22317 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22322 /* If we need to save CR, put it into r12 or r11. Choose r12 except when
22323 r12 will be needed by out-of-line gpr restore. */
22324 cr_save_regno
= ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22325 && !(strategy
& (SAVE_INLINE_GPRS
22326 | SAVE_NOINLINE_GPRS_SAVES_LR
))
22328 if (!WORLD_SAVE_P (info
)
22330 && REGNO (frame_reg_rtx
) != cr_save_regno
22331 && !(using_static_chain_p
&& cr_save_regno
== 11))
22333 cr_save_rtx
= gen_rtx_REG (SImode
, cr_save_regno
);
22334 START_USE (cr_save_regno
);
22335 rs6000_emit_move_from_cr (cr_save_rtx
);
22338 /* Do any required saving of fpr's. If only one or two to save, do
22339 it ourselves. Otherwise, call function. */
22340 if (!WORLD_SAVE_P (info
) && (strategy
& SAVE_INLINE_FPRS
))
22343 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
22344 if (save_reg_p (info
->first_fp_reg_save
+ i
))
22345 emit_frame_save (frame_reg_rtx
,
22346 (TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
22347 ? DFmode
: SFmode
),
22348 info
->first_fp_reg_save
+ i
,
22349 info
->fp_save_offset
+ frame_off
+ 8 * i
,
22350 sp_off
- frame_off
);
22352 else if (!WORLD_SAVE_P (info
) && info
->first_fp_reg_save
!= 64)
22354 bool lr
= (strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
22355 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
22356 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22357 rtx ptr_reg
= frame_reg_rtx
;
22359 if (REGNO (frame_reg_rtx
) == ptr_regno
)
22360 gcc_checking_assert (frame_off
== 0);
22363 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22364 NOT_INUSE (ptr_regno
);
22365 emit_insn (gen_add3_insn (ptr_reg
,
22366 frame_reg_rtx
, GEN_INT (frame_off
)));
22368 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
22369 info
->fp_save_offset
,
22370 info
->lr_save_offset
,
22372 rs6000_frame_related (insn
, ptr_reg
, sp_off
,
22373 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22378 /* Save GPRs. This is done as a PARALLEL if we are using
22379 the store-multiple instructions. */
22380 if (!WORLD_SAVE_P (info
)
22382 && info
->spe_64bit_regs_used
!= 0
22383 && info
->first_gp_reg_save
!= 32)
22386 rtx spe_save_area_ptr
;
22387 HOST_WIDE_INT save_off
;
22388 int ool_adjust
= 0;
22390 /* Determine whether we can address all of the registers that need
22391 to be saved with an offset from frame_reg_rtx that fits in
22392 the small const field for SPE memory instructions. */
22393 int spe_regs_addressable
22394 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
22395 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
22396 && (strategy
& SAVE_INLINE_GPRS
));
22398 if (spe_regs_addressable
)
22400 spe_save_area_ptr
= frame_reg_rtx
;
22401 save_off
= frame_off
;
22405 /* Make r11 point to the start of the SPE save area. We need
22406 to be careful here if r11 is holding the static chain. If
22407 it is, then temporarily save it in r0. */
22408 HOST_WIDE_INT offset
;
22410 if (!(strategy
& SAVE_INLINE_GPRS
))
22411 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
22412 offset
= info
->spe_gp_save_offset
+ frame_off
- ool_adjust
;
22413 spe_save_area_ptr
= gen_rtx_REG (Pmode
, 11);
22414 save_off
= frame_off
- offset
;
22416 if (using_static_chain_p
)
22418 rtx r0
= gen_rtx_REG (Pmode
, 0);
22421 gcc_assert (info
->first_gp_reg_save
> 11);
22423 emit_move_insn (r0
, spe_save_area_ptr
);
22425 else if (REGNO (frame_reg_rtx
) != 11)
22428 emit_insn (gen_addsi3 (spe_save_area_ptr
,
22429 frame_reg_rtx
, GEN_INT (offset
)));
22430 if (!using_static_chain_p
&& REGNO (frame_reg_rtx
) == 11)
22431 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
22434 if ((strategy
& SAVE_INLINE_GPRS
))
22436 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22437 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22438 emit_frame_save (spe_save_area_ptr
, reg_mode
,
22439 info
->first_gp_reg_save
+ i
,
22440 (info
->spe_gp_save_offset
+ save_off
22442 sp_off
- save_off
);
22446 insn
= rs6000_emit_savres_rtx (info
, spe_save_area_ptr
,
22447 info
->spe_gp_save_offset
+ save_off
,
22449 SAVRES_SAVE
| SAVRES_GPR
);
22451 rs6000_frame_related (insn
, spe_save_area_ptr
, sp_off
- save_off
,
22452 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22455 /* Move the static chain pointer back. */
22456 if (!spe_regs_addressable
)
22458 if (using_static_chain_p
)
22460 emit_move_insn (spe_save_area_ptr
, gen_rtx_REG (Pmode
, 0));
22463 else if (REGNO (frame_reg_rtx
) != 11)
22467 else if (!WORLD_SAVE_P (info
) && !(strategy
& SAVE_INLINE_GPRS
))
22469 bool lr
= (strategy
& SAVE_NOINLINE_GPRS_SAVES_LR
) != 0;
22470 int sel
= SAVRES_SAVE
| SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
22471 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22472 rtx ptr_reg
= frame_reg_rtx
;
22473 bool ptr_set_up
= REGNO (ptr_reg
) == ptr_regno
;
22474 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
22478 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22480 /* Need to adjust r11 (r12) if we saved any FPRs. */
22481 if (end_save
+ frame_off
!= 0)
22483 rtx offset
= GEN_INT (end_save
+ frame_off
);
22486 frame_off
= -end_save
;
22488 NOT_INUSE (ptr_regno
);
22489 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22491 else if (!ptr_set_up
)
22493 NOT_INUSE (ptr_regno
);
22494 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22496 ptr_off
= -end_save
;
22497 insn
= rs6000_emit_savres_rtx (info
, ptr_reg
,
22498 info
->gp_save_offset
+ ptr_off
,
22499 info
->lr_save_offset
+ ptr_off
,
22501 rs6000_frame_related (insn
, ptr_reg
, sp_off
- ptr_off
,
22502 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22506 else if (!WORLD_SAVE_P (info
) && (strategy
& SAVRES_MULTIPLE
))
22510 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
22511 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22513 = gen_frame_store (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
22515 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
22516 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22517 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22518 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22520 else if (!WORLD_SAVE_P (info
))
22523 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
22524 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
22525 emit_frame_save (frame_reg_rtx
, reg_mode
,
22526 info
->first_gp_reg_save
+ i
,
22527 info
->gp_save_offset
+ frame_off
+ reg_size
* i
,
22528 sp_off
- frame_off
);
22531 if (crtl
->calls_eh_return
)
22538 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
22539 if (regno
== INVALID_REGNUM
)
22543 p
= rtvec_alloc (i
);
22547 unsigned int regno
= EH_RETURN_DATA_REGNO (i
);
22548 if (regno
== INVALID_REGNUM
)
22552 = gen_frame_store (gen_rtx_REG (reg_mode
, regno
),
22554 info
->ehrd_offset
+ sp_off
+ reg_size
* (int) i
);
22555 RTVEC_ELT (p
, i
) = insn
;
22556 RTX_FRAME_RELATED_P (insn
) = 1;
22559 insn
= emit_insn (gen_blockage ());
22560 RTX_FRAME_RELATED_P (insn
) = 1;
22561 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, gen_rtx_PARALLEL (VOIDmode
, p
));
22564 /* In AIX ABI we need to make sure r2 is really saved. */
22565 if (TARGET_AIX
&& crtl
->calls_eh_return
)
22567 rtx tmp_reg
, tmp_reg_si
, hi
, lo
, compare_result
, toc_save_done
, jump
;
22568 rtx save_insn
, join_insn
, note
;
22569 long toc_restore_insn
;
22571 tmp_reg
= gen_rtx_REG (Pmode
, 11);
22572 tmp_reg_si
= gen_rtx_REG (SImode
, 11);
22573 if (using_static_chain_p
)
22576 emit_move_insn (gen_rtx_REG (Pmode
, 0), tmp_reg
);
22580 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, LR_REGNO
));
22581 /* Peek at instruction to which this function returns. If it's
22582 restoring r2, then we know we've already saved r2. We can't
22583 unconditionally save r2 because the value we have will already
22584 be updated if we arrived at this function via a plt call or
22585 toc adjusting stub. */
22586 emit_move_insn (tmp_reg_si
, gen_rtx_MEM (SImode
, tmp_reg
));
22587 toc_restore_insn
= ((TARGET_32BIT
? 0x80410000 : 0xE8410000)
22588 + RS6000_TOC_SAVE_SLOT
);
22589 hi
= gen_int_mode (toc_restore_insn
& ~0xffff, SImode
);
22590 emit_insn (gen_xorsi3 (tmp_reg_si
, tmp_reg_si
, hi
));
22591 compare_result
= gen_rtx_REG (CCUNSmode
, CR0_REGNO
);
22592 validate_condition_mode (EQ
, CCUNSmode
);
22593 lo
= gen_int_mode (toc_restore_insn
& 0xffff, SImode
);
22594 emit_insn (gen_rtx_SET (VOIDmode
, compare_result
,
22595 gen_rtx_COMPARE (CCUNSmode
, tmp_reg_si
, lo
)));
22596 toc_save_done
= gen_label_rtx ();
22597 jump
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
22598 gen_rtx_EQ (VOIDmode
, compare_result
,
22600 gen_rtx_LABEL_REF (VOIDmode
, toc_save_done
),
22602 jump
= emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, jump
));
22603 JUMP_LABEL (jump
) = toc_save_done
;
22604 LABEL_NUSES (toc_save_done
) += 1;
22606 save_insn
= emit_frame_save (frame_reg_rtx
, reg_mode
,
22607 TOC_REGNUM
, frame_off
+ RS6000_TOC_SAVE_SLOT
,
22608 sp_off
- frame_off
);
22610 emit_label (toc_save_done
);
22612 /* ??? If we leave SAVE_INSN as marked as saving R2, then we'll
22613 have a CFG that has different saves along different paths.
22614 Move the note to a dummy blockage insn, which describes that
22615 R2 is unconditionally saved after the label. */
22616 /* ??? An alternate representation might be a special insn pattern
22617 containing both the branch and the store. That might let the
22618 code that minimizes the number of DW_CFA_advance opcodes better
22619 freedom in placing the annotations. */
22620 note
= find_reg_note (save_insn
, REG_FRAME_RELATED_EXPR
, NULL
);
22622 remove_note (save_insn
, note
);
22624 note
= alloc_reg_note (REG_FRAME_RELATED_EXPR
,
22625 copy_rtx (PATTERN (save_insn
)), NULL_RTX
);
22626 RTX_FRAME_RELATED_P (save_insn
) = 0;
22628 join_insn
= emit_insn (gen_blockage ());
22629 REG_NOTES (join_insn
) = note
;
22630 RTX_FRAME_RELATED_P (join_insn
) = 1;
22632 if (using_static_chain_p
)
22634 emit_move_insn (tmp_reg
, gen_rtx_REG (Pmode
, 0));
22641 /* Save CR if we use any that must be preserved. */
22642 if (!WORLD_SAVE_P (info
) && info
->cr_save_p
)
22644 rtx addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
,
22645 GEN_INT (info
->cr_save_offset
+ frame_off
));
22646 rtx mem
= gen_frame_mem (SImode
, addr
);
22648 /* If we didn't copy cr before, do so now using r0. */
22649 if (cr_save_rtx
== NULL_RTX
)
22652 cr_save_rtx
= gen_rtx_REG (SImode
, 0);
22653 rs6000_emit_move_from_cr (cr_save_rtx
);
22656 /* Saving CR requires a two-instruction sequence: one instruction
22657 to move the CR to a general-purpose register, and a second
22658 instruction that stores the GPR to memory.
22660 We do not emit any DWARF CFI records for the first of these,
22661 because we cannot properly represent the fact that CR is saved in
22662 a register. One reason is that we cannot express that multiple
22663 CR fields are saved; another reason is that on 64-bit, the size
22664 of the CR register in DWARF (4 bytes) differs from the size of
22665 a general-purpose register.
22667 This means if any intervening instruction were to clobber one of
22668 the call-saved CR fields, we'd have incorrect CFI. To prevent
22669 this from happening, we mark the store to memory as a use of
22670 those CR fields, which prevents any such instruction from being
22671 scheduled in between the two instructions. */
22676 crsave_v
[n_crsave
++] = gen_rtx_SET (VOIDmode
, mem
, cr_save_rtx
);
22677 for (i
= 0; i
< 8; i
++)
22678 if (save_reg_p (CR0_REGNO
+ i
))
22679 crsave_v
[n_crsave
++]
22680 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
22682 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
,
22683 gen_rtvec_v (n_crsave
, crsave_v
)));
22684 END_USE (REGNO (cr_save_rtx
));
22686 /* Now, there's no way that dwarf2out_frame_debug_expr is going to
22687 understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)',
22688 so we need to construct a frame expression manually. */
22689 RTX_FRAME_RELATED_P (insn
) = 1;
22691 /* Update address to be stack-pointer relative, like
22692 rs6000_frame_related would do. */
22693 addr
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
),
22694 GEN_INT (info
->cr_save_offset
+ sp_off
));
22695 mem
= gen_frame_mem (SImode
, addr
);
22697 if (DEFAULT_ABI
== ABI_ELFv2
)
22699 /* In the ELFv2 ABI we generate separate CFI records for each
22700 CR field that was actually saved. They all point to the
22701 same 32-bit stack slot. */
22705 for (i
= 0; i
< 8; i
++)
22706 if (save_reg_p (CR0_REGNO
+ i
))
22709 = gen_rtx_SET (VOIDmode
, mem
,
22710 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
22712 RTX_FRAME_RELATED_P (crframe
[n_crframe
]) = 1;
22716 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22717 gen_rtx_PARALLEL (VOIDmode
,
22718 gen_rtvec_v (n_crframe
, crframe
)));
22722 /* In other ABIs, by convention, we use a single CR regnum to
22723 represent the fact that all call-saved CR fields are saved.
22724 We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */
22725 rtx set
= gen_rtx_SET (VOIDmode
, mem
,
22726 gen_rtx_REG (SImode
, CR2_REGNO
));
22727 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, set
);
22731 /* In the ELFv2 ABI we need to save all call-saved CR fields into
22732 *separate* slots if the routine calls __builtin_eh_return, so
22733 that they can be independently restored by the unwinder. */
22734 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
22736 int i
, cr_off
= info
->ehcr_offset
;
22739 /* ??? We might get better performance by using multiple mfocrf
22741 crsave
= gen_rtx_REG (SImode
, 0);
22742 emit_insn (gen_movesi_from_cr (crsave
));
22744 for (i
= 0; i
< 8; i
++)
22745 if (!call_used_regs
[CR0_REGNO
+ i
])
22747 rtvec p
= rtvec_alloc (2);
22749 = gen_frame_store (crsave
, frame_reg_rtx
, cr_off
+ frame_off
);
22751 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
));
22753 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
22755 RTX_FRAME_RELATED_P (insn
) = 1;
22756 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
22757 gen_frame_store (gen_rtx_REG (SImode
, CR0_REGNO
+ i
),
22758 sp_reg_rtx
, cr_off
+ sp_off
));
22760 cr_off
+= reg_size
;
22764 /* Update stack and set back pointer unless this is V.4,
22765 for which it was done previously. */
22766 if (!WORLD_SAVE_P (info
) && info
->push_p
22767 && !(DEFAULT_ABI
== ABI_V4
|| crtl
->calls_eh_return
))
22769 rtx ptr_reg
= NULL
;
22772 /* If saving altivec regs we need to be able to address all save
22773 locations using a 16-bit offset. */
22774 if ((strategy
& SAVE_INLINE_VRS
) == 0
22775 || (info
->altivec_size
!= 0
22776 && (info
->altivec_save_offset
+ info
->altivec_size
- 16
22777 + info
->total_size
- frame_off
) > 32767)
22778 || (info
->vrsave_size
!= 0
22779 && (info
->vrsave_save_offset
22780 + info
->total_size
- frame_off
) > 32767))
22782 int sel
= SAVRES_SAVE
| SAVRES_VR
;
22783 unsigned ptr_regno
= ptr_regno_for_savres (sel
);
22785 if (using_static_chain_p
22786 && ptr_regno
== STATIC_CHAIN_REGNUM
)
22788 if (REGNO (frame_reg_rtx
) != ptr_regno
)
22789 START_USE (ptr_regno
);
22790 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
22791 frame_reg_rtx
= ptr_reg
;
22792 ptr_off
= info
->altivec_save_offset
+ info
->altivec_size
;
22793 frame_off
= -ptr_off
;
22795 else if (REGNO (frame_reg_rtx
) == 1)
22796 frame_off
= info
->total_size
;
22797 rs6000_emit_allocate_stack (info
->total_size
, ptr_reg
, ptr_off
);
22798 sp_off
= info
->total_size
;
22799 if (frame_reg_rtx
!= sp_reg_rtx
)
22800 rs6000_emit_stack_tie (frame_reg_rtx
, false);
22803 /* Set frame pointer, if needed. */
22804 if (frame_pointer_needed
)
22806 insn
= emit_move_insn (gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
22808 RTX_FRAME_RELATED_P (insn
) = 1;
22811 /* Save AltiVec registers if needed. Save here because the red zone does
22812 not always include AltiVec registers. */
22813 if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
22814 && info
->altivec_size
!= 0 && (strategy
& SAVE_INLINE_VRS
) == 0)
22816 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
22818 /* Oddly, the vector save/restore functions point r0 at the end
22819 of the save area, then use r11 or r12 to load offsets for
22820 [reg+reg] addressing. */
22821 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
22822 int scratch_regno
= ptr_regno_for_savres (SAVRES_SAVE
| SAVRES_VR
);
22823 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
22825 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
22827 if (end_save
+ frame_off
!= 0)
22829 rtx offset
= GEN_INT (end_save
+ frame_off
);
22831 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
22834 emit_move_insn (ptr_reg
, frame_reg_rtx
);
22836 ptr_off
= -end_save
;
22837 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
22838 info
->altivec_save_offset
+ ptr_off
,
22839 0, V4SImode
, SAVRES_SAVE
| SAVRES_VR
);
22840 rs6000_frame_related (insn
, scratch_reg
, sp_off
- ptr_off
,
22841 NULL_RTX
, NULL_RTX
, NULL_RTX
);
22842 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
22844 /* The oddity mentioned above clobbered our frame reg. */
22845 emit_move_insn (frame_reg_rtx
, ptr_reg
);
22846 frame_off
= ptr_off
;
22849 else if (!WORLD_SAVE_P (info
) && TARGET_ALTIVEC_ABI
22850 && info
->altivec_size
!= 0)
22854 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
22855 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
22857 rtx areg
, savereg
, mem
, split_reg
;
22860 offset
= (info
->altivec_save_offset
+ frame_off
22861 + 16 * (i
- info
->first_altivec_reg_save
));
22863 savereg
= gen_rtx_REG (V4SImode
, i
);
22866 areg
= gen_rtx_REG (Pmode
, 0);
22867 emit_move_insn (areg
, GEN_INT (offset
));
22869 /* AltiVec addressing mode is [reg+reg]. */
22870 mem
= gen_frame_mem (V4SImode
,
22871 gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
));
22873 insn
= emit_move_insn (mem
, savereg
);
22875 /* When we split a VSX store into two insns, we need to make
22876 sure the DWARF info knows which register we are storing.
22877 Pass it in to be used on the appropriate note. */
22878 if (!BYTES_BIG_ENDIAN
22879 && GET_CODE (PATTERN (insn
)) == SET
22880 && GET_CODE (SET_SRC (PATTERN (insn
))) == VEC_SELECT
)
22881 split_reg
= savereg
;
22883 split_reg
= NULL_RTX
;
22885 rs6000_frame_related (insn
, frame_reg_rtx
, sp_off
- frame_off
,
22886 areg
, GEN_INT (offset
), split_reg
);
22890 /* VRSAVE is a bit vector representing which AltiVec registers
22891 are used. The OS uses this to determine which vector
22892 registers to save on a context switch. We need to save
22893 VRSAVE on the stack frame, add whatever AltiVec registers we
22894 used in this function, and do the corresponding magic in the
22897 if (!WORLD_SAVE_P (info
)
22899 && TARGET_ALTIVEC_VRSAVE
22900 && info
->vrsave_mask
!= 0)
22906 /* Get VRSAVE onto a GPR. Note that ABI_V4 and ABI_DARWIN might
22907 be using r12 as frame_reg_rtx and r11 as the static chain
22908 pointer for nested functions. */
22910 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
22911 && !using_static_chain_p
)
22913 else if (REGNO (frame_reg_rtx
) == 12)
22916 if (using_static_chain_p
)
22920 NOT_INUSE (save_regno
);
22921 reg
= gen_rtx_REG (SImode
, save_regno
);
22922 vrsave
= gen_rtx_REG (SImode
, VRSAVE_REGNO
);
22924 emit_insn (gen_get_vrsave_internal (reg
));
22926 emit_insn (gen_rtx_SET (VOIDmode
, reg
, vrsave
));
22929 offset
= info
->vrsave_save_offset
+ frame_off
;
22930 insn
= emit_insn (gen_frame_store (reg
, frame_reg_rtx
, offset
));
22932 /* Include the registers in the mask. */
22933 emit_insn (gen_iorsi3 (reg
, reg
, GEN_INT ((int) info
->vrsave_mask
)));
22935 insn
= emit_insn (generate_set_vrsave (reg
, info
, 0));
22938 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
22939 if (!TARGET_SINGLE_PIC_BASE
22940 && ((TARGET_TOC
&& TARGET_MINIMAL_TOC
&& get_pool_size () != 0)
22941 || (DEFAULT_ABI
== ABI_V4
22942 && (flag_pic
== 1 || (flag_pic
&& TARGET_SECURE_PLT
))
22943 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM
))))
22945 /* If emit_load_toc_table will use the link register, we need to save
22946 it. We use R12 for this purpose because emit_load_toc_table
22947 can use register 0. This allows us to use a plain 'blr' to return
22948 from the procedure more often. */
22949 int save_LR_around_toc_setup
= (TARGET_ELF
22950 && DEFAULT_ABI
== ABI_V4
22952 && ! info
->lr_save_p
22953 && EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun
)->preds
) > 0);
22954 if (save_LR_around_toc_setup
)
22956 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
22957 rtx tmp
= gen_rtx_REG (Pmode
, 12);
22959 insn
= emit_move_insn (tmp
, lr
);
22960 RTX_FRAME_RELATED_P (insn
) = 1;
22962 rs6000_emit_load_toc_table (TRUE
);
22964 insn
= emit_move_insn (lr
, tmp
);
22965 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
22966 RTX_FRAME_RELATED_P (insn
) = 1;
22969 rs6000_emit_load_toc_table (TRUE
);
22973 if (!TARGET_SINGLE_PIC_BASE
22974 && DEFAULT_ABI
== ABI_DARWIN
22975 && flag_pic
&& crtl
->uses_pic_offset_table
)
22977 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
22978 rtx src
= gen_rtx_SYMBOL_REF (Pmode
, MACHOPIC_FUNCTION_BASE_NAME
);
22980 /* Save and restore LR locally around this call (in R0). */
22981 if (!info
->lr_save_p
)
22982 emit_move_insn (gen_rtx_REG (Pmode
, 0), lr
);
22984 emit_insn (gen_load_macho_picbase (src
));
22986 emit_move_insn (gen_rtx_REG (Pmode
,
22987 RS6000_PIC_OFFSET_TABLE_REGNUM
),
22990 if (!info
->lr_save_p
)
22991 emit_move_insn (lr
, gen_rtx_REG (Pmode
, 0));
22995 /* If we need to, save the TOC register after doing the stack setup.
22996 Do not emit eh frame info for this save. The unwinder wants info,
22997 conceptually attached to instructions in this function, about
22998 register values in the caller of this function. This R2 may have
22999 already been changed from the value in the caller.
23000 We don't attempt to write accurate DWARF EH frame info for R2
23001 because code emitted by gcc for a (non-pointer) function call
23002 doesn't save and restore R2. Instead, R2 is managed out-of-line
23003 by a linker generated plt call stub when the function resides in
23004 a shared library. This behaviour is costly to describe in DWARF,
23005 both in terms of the size of DWARF info and the time taken in the
23006 unwinder to interpret it. R2 changes, apart from the
23007 calls_eh_return case earlier in this function, are handled by
23008 linux-unwind.h frob_update_context. */
23009 if (rs6000_save_toc_in_prologue_p ())
23011 rtx reg
= gen_rtx_REG (reg_mode
, TOC_REGNUM
);
23012 emit_insn (gen_frame_store (reg
, sp_reg_rtx
, RS6000_TOC_SAVE_SLOT
));
23016 /* Write function prologue. */
23019 rs6000_output_function_prologue (FILE *file
,
23020 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
23022 rs6000_stack_t
*info
= rs6000_stack_info ();
23024 if (TARGET_DEBUG_STACK
)
23025 debug_stack_info (info
);
23027 /* Write .extern for any function we will call to save and restore
23029 if (info
->first_fp_reg_save
< 64
23034 int regno
= info
->first_fp_reg_save
- 32;
23036 if ((info
->savres_strategy
& SAVE_INLINE_FPRS
) == 0)
23038 bool lr
= (info
->savres_strategy
& SAVE_NOINLINE_FPRS_SAVES_LR
) != 0;
23039 int sel
= SAVRES_SAVE
| SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23040 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23041 fprintf (file
, "\t.extern %s\n", name
);
23043 if ((info
->savres_strategy
& REST_INLINE_FPRS
) == 0)
23045 bool lr
= (info
->savres_strategy
23046 & REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
23047 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23048 name
= rs6000_savres_routine_name (info
, regno
, sel
);
23049 fprintf (file
, "\t.extern %s\n", name
);
23053 /* ELFv2 ABI r2 setup code and local entry point. This must follow
23054 immediately after the global entry point label. */
23055 if (DEFAULT_ABI
== ABI_ELFv2
&& cfun
->machine
->r2_setup_needed
)
23057 const char *name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
23059 fprintf (file
, "0:\taddis 2,12,.TOC.-0b@ha\n");
23060 fprintf (file
, "\taddi 2,2,.TOC.-0b@l\n");
23062 fputs ("\t.localentry\t", file
);
23063 assemble_name (file
, name
);
23064 fputs (",.-", file
);
23065 assemble_name (file
, name
);
23066 fputs ("\n", file
);
23069 /* Output -mprofile-kernel code. This needs to be done here instead of
23070 in output_function_profile since it must go after the ELFv2 ABI
23071 local entry point. */
23072 if (TARGET_PROFILE_KERNEL
)
23074 gcc_assert (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
);
23075 gcc_assert (!TARGET_32BIT
);
23077 asm_fprintf (file
, "\tmflr %s\n", reg_names
[0]);
23078 asm_fprintf (file
, "\tstd %s,16(%s)\n", reg_names
[0], reg_names
[1]);
23080 /* In the ELFv2 ABI we have no compiler stack word. It must be
23081 the resposibility of _mcount to preserve the static chain
23082 register if required. */
23083 if (DEFAULT_ABI
!= ABI_ELFv2
23084 && cfun
->static_chain_decl
!= NULL
)
23086 asm_fprintf (file
, "\tstd %s,24(%s)\n",
23087 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23088 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23089 asm_fprintf (file
, "\tld %s,24(%s)\n",
23090 reg_names
[STATIC_CHAIN_REGNUM
], reg_names
[1]);
23093 fprintf (file
, "\tbl %s\n", RS6000_MCOUNT
);
23096 rs6000_pic_labelno
++;
23099 /* Non-zero if vmx regs are restored before the frame pop, zero if
23100 we restore after the pop when possible. */
23101 #define ALWAYS_RESTORE_ALTIVEC_BEFORE_POP 0
23103 /* Restoring cr is a two step process: loading a reg from the frame
23104 save, then moving the reg to cr. For ABI_V4 we must let the
23105 unwinder know that the stack location is no longer valid at or
23106 before the stack deallocation, but we can't emit a cfa_restore for
23107 cr at the stack deallocation like we do for other registers.
23108 The trouble is that it is possible for the move to cr to be
23109 scheduled after the stack deallocation. So say exactly where cr
23110 is located on each of the two insns. */
23113 load_cr_save (int regno
, rtx frame_reg_rtx
, int offset
, bool exit_func
)
23115 rtx mem
= gen_frame_mem_offset (SImode
, frame_reg_rtx
, offset
);
23116 rtx reg
= gen_rtx_REG (SImode
, regno
);
23117 rtx insn
= emit_move_insn (reg
, mem
);
23119 if (!exit_func
&& DEFAULT_ABI
== ABI_V4
)
23121 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23122 rtx set
= gen_rtx_SET (VOIDmode
, reg
, cr
);
23124 add_reg_note (insn
, REG_CFA_REGISTER
, set
);
23125 RTX_FRAME_RELATED_P (insn
) = 1;
23130 /* Reload CR from REG. */
23133 restore_saved_cr (rtx reg
, int using_mfcr_multiple
, bool exit_func
)
23138 if (using_mfcr_multiple
)
23140 for (i
= 0; i
< 8; i
++)
23141 if (save_reg_p (CR0_REGNO
+ i
))
23143 gcc_assert (count
);
23146 if (using_mfcr_multiple
&& count
> 1)
23152 p
= rtvec_alloc (count
);
23155 for (i
= 0; i
< 8; i
++)
23156 if (save_reg_p (CR0_REGNO
+ i
))
23158 rtvec r
= rtvec_alloc (2);
23159 RTVEC_ELT (r
, 0) = reg
;
23160 RTVEC_ELT (r
, 1) = GEN_INT (1 << (7-i
));
23161 RTVEC_ELT (p
, ndx
) =
23162 gen_rtx_SET (VOIDmode
, gen_rtx_REG (CCmode
, CR0_REGNO
+ i
),
23163 gen_rtx_UNSPEC (CCmode
, r
, UNSPEC_MOVESI_TO_CR
));
23166 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23167 gcc_assert (ndx
== count
);
23169 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23170 CR field separately. */
23171 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23173 for (i
= 0; i
< 8; i
++)
23174 if (save_reg_p (CR0_REGNO
+ i
))
23175 add_reg_note (insn
, REG_CFA_RESTORE
,
23176 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23178 RTX_FRAME_RELATED_P (insn
) = 1;
23182 for (i
= 0; i
< 8; i
++)
23183 if (save_reg_p (CR0_REGNO
+ i
))
23185 rtx insn
= emit_insn (gen_movsi_to_cr_one
23186 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23188 /* For the ELFv2 ABI we generate a CFA_RESTORE for each
23189 CR field separately, attached to the insn that in fact
23190 restores this particular CR field. */
23191 if (!exit_func
&& DEFAULT_ABI
== ABI_ELFv2
&& flag_shrink_wrap
)
23193 add_reg_note (insn
, REG_CFA_RESTORE
,
23194 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23196 RTX_FRAME_RELATED_P (insn
) = 1;
23200 /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */
23201 if (!exit_func
&& DEFAULT_ABI
!= ABI_ELFv2
23202 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23204 rtx insn
= get_last_insn ();
23205 rtx cr
= gen_rtx_REG (SImode
, CR2_REGNO
);
23207 add_reg_note (insn
, REG_CFA_RESTORE
, cr
);
23208 RTX_FRAME_RELATED_P (insn
) = 1;
23212 /* Like cr, the move to lr instruction can be scheduled after the
23213 stack deallocation, but unlike cr, its stack frame save is still
23214 valid. So we only need to emit the cfa_restore on the correct
23218 load_lr_save (int regno
, rtx frame_reg_rtx
, int offset
)
23220 rtx mem
= gen_frame_mem_offset (Pmode
, frame_reg_rtx
, offset
);
23221 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23223 emit_move_insn (reg
, mem
);
23227 restore_saved_lr (int regno
, bool exit_func
)
23229 rtx reg
= gen_rtx_REG (Pmode
, regno
);
23230 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
23231 rtx insn
= emit_move_insn (lr
, reg
);
23233 if (!exit_func
&& flag_shrink_wrap
)
23235 add_reg_note (insn
, REG_CFA_RESTORE
, lr
);
23236 RTX_FRAME_RELATED_P (insn
) = 1;
23241 add_crlr_cfa_restore (const rs6000_stack_t
*info
, rtx cfa_restores
)
23243 if (DEFAULT_ABI
== ABI_ELFv2
)
23246 for (i
= 0; i
< 8; i
++)
23247 if (save_reg_p (CR0_REGNO
+ i
))
23249 rtx cr
= gen_rtx_REG (SImode
, CR0_REGNO
+ i
);
23250 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, cr
,
23254 else if (info
->cr_save_p
)
23255 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23256 gen_rtx_REG (SImode
, CR2_REGNO
),
23259 if (info
->lr_save_p
)
23260 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23261 gen_rtx_REG (Pmode
, LR_REGNO
),
23263 return cfa_restores
;
23266 /* Return true if OFFSET from stack pointer can be clobbered by signals.
23267 V.4 doesn't have any stack cushion, AIX ABIs have 220 or 288 bytes
23268 below stack pointer not cloberred by signals. */
23271 offset_below_red_zone_p (HOST_WIDE_INT offset
)
23273 return offset
< (DEFAULT_ABI
== ABI_V4
23275 : TARGET_32BIT
? -220 : -288);
23278 /* Append CFA_RESTORES to any existing REG_NOTES on the last insn. */
23281 emit_cfa_restores (rtx cfa_restores
)
23283 rtx insn
= get_last_insn ();
23284 rtx
*loc
= ®_NOTES (insn
);
23287 loc
= &XEXP (*loc
, 1);
23288 *loc
= cfa_restores
;
23289 RTX_FRAME_RELATED_P (insn
) = 1;
23292 /* Emit function epilogue as insns. */
23295 rs6000_emit_epilogue (int sibcall
)
23297 rs6000_stack_t
*info
;
23298 int restoring_GPRs_inline
;
23299 int restoring_FPRs_inline
;
23300 int using_load_multiple
;
23301 int using_mtcr_multiple
;
23302 int use_backchain_to_restore_sp
;
23305 HOST_WIDE_INT frame_off
= 0;
23306 rtx sp_reg_rtx
= gen_rtx_REG (Pmode
, 1);
23307 rtx frame_reg_rtx
= sp_reg_rtx
;
23308 rtx cfa_restores
= NULL_RTX
;
23310 rtx cr_save_reg
= NULL_RTX
;
23311 enum machine_mode reg_mode
= Pmode
;
23312 int reg_size
= TARGET_32BIT
? 4 : 8;
23315 unsigned ptr_regno
;
23317 info
= rs6000_stack_info ();
23319 if (TARGET_SPE_ABI
&& info
->spe_64bit_regs_used
!= 0)
23321 reg_mode
= V2SImode
;
23325 strategy
= info
->savres_strategy
;
23326 using_load_multiple
= strategy
& SAVRES_MULTIPLE
;
23327 restoring_FPRs_inline
= sibcall
|| (strategy
& REST_INLINE_FPRS
);
23328 restoring_GPRs_inline
= sibcall
|| (strategy
& REST_INLINE_GPRS
);
23329 using_mtcr_multiple
= (rs6000_cpu
== PROCESSOR_PPC601
23330 || rs6000_cpu
== PROCESSOR_PPC603
23331 || rs6000_cpu
== PROCESSOR_PPC750
23333 /* Restore via the backchain when we have a large frame, since this
23334 is more efficient than an addis, addi pair. The second condition
23335 here will not trigger at the moment; We don't actually need a
23336 frame pointer for alloca, but the generic parts of the compiler
23337 give us one anyway. */
23338 use_backchain_to_restore_sp
= (info
->total_size
> 32767 - info
->lr_save_offset
23339 || (cfun
->calls_alloca
23340 && !frame_pointer_needed
));
23341 restore_lr
= (info
->lr_save_p
23342 && (restoring_FPRs_inline
23343 || (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
))
23344 && (restoring_GPRs_inline
23345 || info
->first_fp_reg_save
< 64));
23347 if (WORLD_SAVE_P (info
))
23351 const char *alloc_rname
;
23354 /* eh_rest_world_r10 will return to the location saved in the LR
23355 stack slot (which is not likely to be our caller.)
23356 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
23357 rest_world is similar, except any R10 parameter is ignored.
23358 The exception-handling stuff that was here in 2.95 is no
23359 longer necessary. */
23363 + 32 - info
->first_gp_reg_save
23364 + LAST_ALTIVEC_REGNO
+ 1 - info
->first_altivec_reg_save
23365 + 63 + 1 - info
->first_fp_reg_save
);
23367 strcpy (rname
, ((crtl
->calls_eh_return
) ?
23368 "*eh_rest_world_r10" : "*rest_world"));
23369 alloc_rname
= ggc_strdup (rname
);
23372 RTVEC_ELT (p
, j
++) = ret_rtx
;
23373 RTVEC_ELT (p
, j
++) = gen_rtx_USE (VOIDmode
,
23374 gen_rtx_REG (Pmode
,
23377 = gen_rtx_USE (VOIDmode
, gen_rtx_SYMBOL_REF (Pmode
, alloc_rname
));
23378 /* The instruction pattern requires a clobber here;
23379 it is shared with the restVEC helper. */
23381 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 11));
23384 /* CR register traditionally saved as CR2. */
23385 rtx reg
= gen_rtx_REG (SImode
, CR2_REGNO
);
23387 = gen_frame_load (reg
, frame_reg_rtx
, info
->cr_save_offset
);
23388 if (flag_shrink_wrap
)
23390 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
,
23391 gen_rtx_REG (Pmode
, LR_REGNO
),
23393 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23397 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23399 rtx reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
23401 = gen_frame_load (reg
,
23402 frame_reg_rtx
, info
->gp_save_offset
+ reg_size
* i
);
23403 if (flag_shrink_wrap
)
23404 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23406 for (i
= 0; info
->first_altivec_reg_save
+ i
<= LAST_ALTIVEC_REGNO
; i
++)
23408 rtx reg
= gen_rtx_REG (V4SImode
, info
->first_altivec_reg_save
+ i
);
23410 = gen_frame_load (reg
,
23411 frame_reg_rtx
, info
->altivec_save_offset
+ 16 * i
);
23412 if (flag_shrink_wrap
)
23413 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23415 for (i
= 0; info
->first_fp_reg_save
+ i
<= 63; i
++)
23417 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
23418 ? DFmode
: SFmode
),
23419 info
->first_fp_reg_save
+ i
);
23421 = gen_frame_load (reg
, frame_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
23422 if (flag_shrink_wrap
)
23423 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23426 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, 0));
23428 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 12));
23430 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 7));
23432 = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (SImode
, 8));
23434 = gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, 10));
23435 insn
= emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23437 if (flag_shrink_wrap
)
23439 REG_NOTES (insn
) = cfa_restores
;
23440 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
23441 RTX_FRAME_RELATED_P (insn
) = 1;
23446 /* frame_reg_rtx + frame_off points to the top of this stack frame. */
23448 frame_off
= info
->total_size
;
23450 /* Restore AltiVec registers if we must do so before adjusting the
23452 if (TARGET_ALTIVEC_ABI
23453 && info
->altivec_size
!= 0
23454 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23455 || (DEFAULT_ABI
!= ABI_V4
23456 && offset_below_red_zone_p (info
->altivec_save_offset
))))
23459 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
23461 gcc_checking_assert (scratch_regno
== 11 || scratch_regno
== 12);
23462 if (use_backchain_to_restore_sp
)
23464 int frame_regno
= 11;
23466 if ((strategy
& REST_INLINE_VRS
) == 0)
23468 /* Of r11 and r12, select the one not clobbered by an
23469 out-of-line restore function for the frame register. */
23470 frame_regno
= 11 + 12 - scratch_regno
;
23472 frame_reg_rtx
= gen_rtx_REG (Pmode
, frame_regno
);
23473 emit_move_insn (frame_reg_rtx
,
23474 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23477 else if (frame_pointer_needed
)
23478 frame_reg_rtx
= hard_frame_pointer_rtx
;
23480 if ((strategy
& REST_INLINE_VRS
) == 0)
23482 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23484 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23485 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23487 if (end_save
+ frame_off
!= 0)
23489 rtx offset
= GEN_INT (end_save
+ frame_off
);
23491 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23494 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23496 ptr_off
= -end_save
;
23497 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23498 info
->altivec_save_offset
+ ptr_off
,
23499 0, V4SImode
, SAVRES_VR
);
23503 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23504 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23506 rtx addr
, areg
, mem
, reg
;
23508 areg
= gen_rtx_REG (Pmode
, 0);
23510 (areg
, GEN_INT (info
->altivec_save_offset
23512 + 16 * (i
- info
->first_altivec_reg_save
)));
23514 /* AltiVec addressing mode is [reg+reg]. */
23515 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
23516 mem
= gen_frame_mem (V4SImode
, addr
);
23518 reg
= gen_rtx_REG (V4SImode
, i
);
23519 emit_move_insn (reg
, mem
);
23523 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23524 if (((strategy
& REST_INLINE_VRS
) == 0
23525 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
23526 && (flag_shrink_wrap
23527 || (offset_below_red_zone_p
23528 (info
->altivec_save_offset
23529 + 16 * (i
- info
->first_altivec_reg_save
)))))
23531 rtx reg
= gen_rtx_REG (V4SImode
, i
);
23532 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23536 /* Restore VRSAVE if we must do so before adjusting the stack. */
23538 && TARGET_ALTIVEC_VRSAVE
23539 && info
->vrsave_mask
!= 0
23540 && (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23541 || (DEFAULT_ABI
!= ABI_V4
23542 && offset_below_red_zone_p (info
->vrsave_save_offset
))))
23546 if (frame_reg_rtx
== sp_reg_rtx
)
23548 if (use_backchain_to_restore_sp
)
23550 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23551 emit_move_insn (frame_reg_rtx
,
23552 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23555 else if (frame_pointer_needed
)
23556 frame_reg_rtx
= hard_frame_pointer_rtx
;
23559 reg
= gen_rtx_REG (SImode
, 12);
23560 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23561 info
->vrsave_save_offset
+ frame_off
));
23563 emit_insn (generate_set_vrsave (reg
, info
, 1));
23567 /* If we have a large stack frame, restore the old stack pointer
23568 using the backchain. */
23569 if (use_backchain_to_restore_sp
)
23571 if (frame_reg_rtx
== sp_reg_rtx
)
23573 /* Under V.4, don't reset the stack pointer until after we're done
23574 loading the saved registers. */
23575 if (DEFAULT_ABI
== ABI_V4
)
23576 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23578 insn
= emit_move_insn (frame_reg_rtx
,
23579 gen_rtx_MEM (Pmode
, sp_reg_rtx
));
23582 else if (ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23583 && DEFAULT_ABI
== ABI_V4
)
23584 /* frame_reg_rtx has been set up by the altivec restore. */
23588 insn
= emit_move_insn (sp_reg_rtx
, frame_reg_rtx
);
23589 frame_reg_rtx
= sp_reg_rtx
;
23592 /* If we have a frame pointer, we can restore the old stack pointer
23594 else if (frame_pointer_needed
)
23596 frame_reg_rtx
= sp_reg_rtx
;
23597 if (DEFAULT_ABI
== ABI_V4
)
23598 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23599 /* Prevent reordering memory accesses against stack pointer restore. */
23600 else if (cfun
->calls_alloca
23601 || offset_below_red_zone_p (-info
->total_size
))
23602 rs6000_emit_stack_tie (frame_reg_rtx
, true);
23604 insn
= emit_insn (gen_add3_insn (frame_reg_rtx
, hard_frame_pointer_rtx
,
23605 GEN_INT (info
->total_size
)));
23608 else if (info
->push_p
23609 && DEFAULT_ABI
!= ABI_V4
23610 && !crtl
->calls_eh_return
)
23612 /* Prevent reordering memory accesses against stack pointer restore. */
23613 if (cfun
->calls_alloca
23614 || offset_below_red_zone_p (-info
->total_size
))
23615 rs6000_emit_stack_tie (frame_reg_rtx
, false);
23616 insn
= emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
,
23617 GEN_INT (info
->total_size
)));
23620 if (insn
&& frame_reg_rtx
== sp_reg_rtx
)
23624 REG_NOTES (insn
) = cfa_restores
;
23625 cfa_restores
= NULL_RTX
;
23627 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
23628 RTX_FRAME_RELATED_P (insn
) = 1;
23631 /* Restore AltiVec registers if we have not done so already. */
23632 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23633 && TARGET_ALTIVEC_ABI
23634 && info
->altivec_size
!= 0
23635 && (DEFAULT_ABI
== ABI_V4
23636 || !offset_below_red_zone_p (info
->altivec_save_offset
)))
23640 if ((strategy
& REST_INLINE_VRS
) == 0)
23642 int end_save
= info
->altivec_save_offset
+ info
->altivec_size
;
23644 rtx ptr_reg
= gen_rtx_REG (Pmode
, 0);
23645 int scratch_regno
= ptr_regno_for_savres (SAVRES_VR
);
23646 rtx scratch_reg
= gen_rtx_REG (Pmode
, scratch_regno
);
23648 if (end_save
+ frame_off
!= 0)
23650 rtx offset
= GEN_INT (end_save
+ frame_off
);
23652 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
, offset
));
23655 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23657 ptr_off
= -end_save
;
23658 insn
= rs6000_emit_savres_rtx (info
, scratch_reg
,
23659 info
->altivec_save_offset
+ ptr_off
,
23660 0, V4SImode
, SAVRES_VR
);
23661 if (REGNO (frame_reg_rtx
) == REGNO (scratch_reg
))
23663 /* Frame reg was clobbered by out-of-line save. Restore it
23664 from ptr_reg, and if we are calling out-of-line gpr or
23665 fpr restore set up the correct pointer and offset. */
23666 unsigned newptr_regno
= 1;
23667 if (!restoring_GPRs_inline
)
23669 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
23670 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23671 newptr_regno
= ptr_regno_for_savres (sel
);
23672 end_save
= info
->gp_save_offset
+ info
->gp_size
;
23674 else if (!restoring_FPRs_inline
)
23676 bool lr
= !(strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
);
23677 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
23678 newptr_regno
= ptr_regno_for_savres (sel
);
23679 end_save
= info
->gp_save_offset
+ info
->gp_size
;
23682 if (newptr_regno
!= 1 && REGNO (frame_reg_rtx
) != newptr_regno
)
23683 frame_reg_rtx
= gen_rtx_REG (Pmode
, newptr_regno
);
23685 if (end_save
+ ptr_off
!= 0)
23687 rtx offset
= GEN_INT (end_save
+ ptr_off
);
23689 frame_off
= -end_save
;
23690 emit_insn (gen_add3_insn (frame_reg_rtx
, ptr_reg
, offset
));
23694 frame_off
= ptr_off
;
23695 emit_move_insn (frame_reg_rtx
, ptr_reg
);
23701 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23702 if (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
))
23704 rtx addr
, areg
, mem
, reg
;
23706 areg
= gen_rtx_REG (Pmode
, 0);
23708 (areg
, GEN_INT (info
->altivec_save_offset
23710 + 16 * (i
- info
->first_altivec_reg_save
)));
23712 /* AltiVec addressing mode is [reg+reg]. */
23713 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, areg
);
23714 mem
= gen_frame_mem (V4SImode
, addr
);
23716 reg
= gen_rtx_REG (V4SImode
, i
);
23717 emit_move_insn (reg
, mem
);
23721 for (i
= info
->first_altivec_reg_save
; i
<= LAST_ALTIVEC_REGNO
; ++i
)
23722 if (((strategy
& REST_INLINE_VRS
) == 0
23723 || (info
->vrsave_mask
& ALTIVEC_REG_BIT (i
)) != 0)
23724 && (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
))
23726 rtx reg
= gen_rtx_REG (V4SImode
, i
);
23727 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
23731 /* Restore VRSAVE if we have not done so already. */
23732 if (!ALWAYS_RESTORE_ALTIVEC_BEFORE_POP
23734 && TARGET_ALTIVEC_VRSAVE
23735 && info
->vrsave_mask
!= 0
23736 && (DEFAULT_ABI
== ABI_V4
23737 || !offset_below_red_zone_p (info
->vrsave_save_offset
)))
23741 reg
= gen_rtx_REG (SImode
, 12);
23742 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23743 info
->vrsave_save_offset
+ frame_off
));
23745 emit_insn (generate_set_vrsave (reg
, info
, 1));
23748 /* If we exit by an out-of-line restore function on ABI_V4 then that
23749 function will deallocate the stack, so we don't need to worry
23750 about the unwinder restoring cr from an invalid stack frame
23752 exit_func
= (!restoring_FPRs_inline
23753 || (!restoring_GPRs_inline
23754 && info
->first_fp_reg_save
== 64));
23756 /* In the ELFv2 ABI we need to restore all call-saved CR fields from
23757 *separate* slots if the routine calls __builtin_eh_return, so
23758 that they can be independently restored by the unwinder. */
23759 if (DEFAULT_ABI
== ABI_ELFv2
&& crtl
->calls_eh_return
)
23761 int i
, cr_off
= info
->ehcr_offset
;
23763 for (i
= 0; i
< 8; i
++)
23764 if (!call_used_regs
[CR0_REGNO
+ i
])
23766 rtx reg
= gen_rtx_REG (SImode
, 0);
23767 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23768 cr_off
+ frame_off
));
23770 insn
= emit_insn (gen_movsi_to_cr_one
23771 (gen_rtx_REG (CCmode
, CR0_REGNO
+ i
), reg
));
23773 if (!exit_func
&& flag_shrink_wrap
)
23775 add_reg_note (insn
, REG_CFA_RESTORE
,
23776 gen_rtx_REG (SImode
, CR0_REGNO
+ i
));
23778 RTX_FRAME_RELATED_P (insn
) = 1;
23781 cr_off
+= reg_size
;
23785 /* Get the old lr if we saved it. If we are restoring registers
23786 out-of-line, then the out-of-line routines can do this for us. */
23787 if (restore_lr
&& restoring_GPRs_inline
)
23788 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
23790 /* Get the old cr if we saved it. */
23791 if (info
->cr_save_p
)
23793 unsigned cr_save_regno
= 12;
23795 if (!restoring_GPRs_inline
)
23797 /* Ensure we don't use the register used by the out-of-line
23798 gpr register restore below. */
23799 bool lr
= info
->gp_save_offset
+ info
->gp_size
== 0;
23800 int sel
= SAVRES_GPR
| (lr
? SAVRES_LR
: 0);
23801 int gpr_ptr_regno
= ptr_regno_for_savres (sel
);
23803 if (gpr_ptr_regno
== 12)
23804 cr_save_regno
= 11;
23805 gcc_checking_assert (REGNO (frame_reg_rtx
) != cr_save_regno
);
23807 else if (REGNO (frame_reg_rtx
) == 12)
23808 cr_save_regno
= 11;
23810 cr_save_reg
= load_cr_save (cr_save_regno
, frame_reg_rtx
,
23811 info
->cr_save_offset
+ frame_off
,
23815 /* Set LR here to try to overlap restores below. */
23816 if (restore_lr
&& restoring_GPRs_inline
)
23817 restore_saved_lr (0, exit_func
);
23819 /* Load exception handler data registers, if needed. */
23820 if (crtl
->calls_eh_return
)
23822 unsigned int i
, regno
;
23826 rtx reg
= gen_rtx_REG (reg_mode
, 2);
23827 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
23828 frame_off
+ RS6000_TOC_SAVE_SLOT
));
23835 regno
= EH_RETURN_DATA_REGNO (i
);
23836 if (regno
== INVALID_REGNUM
)
23839 /* Note: possible use of r0 here to address SPE regs. */
23840 mem
= gen_frame_mem_offset (reg_mode
, frame_reg_rtx
,
23841 info
->ehrd_offset
+ frame_off
23842 + reg_size
* (int) i
);
23844 emit_move_insn (gen_rtx_REG (reg_mode
, regno
), mem
);
23848 /* Restore GPRs. This is done as a PARALLEL if we are using
23849 the load-multiple instructions. */
23851 && info
->spe_64bit_regs_used
23852 && info
->first_gp_reg_save
!= 32)
23854 /* Determine whether we can address all of the registers that need
23855 to be saved with an offset from frame_reg_rtx that fits in
23856 the small const field for SPE memory instructions. */
23857 int spe_regs_addressable
23858 = (SPE_CONST_OFFSET_OK (info
->spe_gp_save_offset
+ frame_off
23859 + reg_size
* (32 - info
->first_gp_reg_save
- 1))
23860 && restoring_GPRs_inline
);
23862 if (!spe_regs_addressable
)
23864 int ool_adjust
= 0;
23865 rtx old_frame_reg_rtx
= frame_reg_rtx
;
23866 /* Make r11 point to the start of the SPE save area. We worried about
23867 not clobbering it when we were saving registers in the prologue.
23868 There's no need to worry here because the static chain is passed
23869 anew to every function. */
23871 if (!restoring_GPRs_inline
)
23872 ool_adjust
= 8 * (info
->first_gp_reg_save
- FIRST_SAVED_GP_REGNO
);
23873 frame_reg_rtx
= gen_rtx_REG (Pmode
, 11);
23874 emit_insn (gen_addsi3 (frame_reg_rtx
, old_frame_reg_rtx
,
23875 GEN_INT (info
->spe_gp_save_offset
23878 /* Keep the invariant that frame_reg_rtx + frame_off points
23879 at the top of the stack frame. */
23880 frame_off
= -info
->spe_gp_save_offset
+ ool_adjust
;
23883 if (restoring_GPRs_inline
)
23885 HOST_WIDE_INT spe_offset
= info
->spe_gp_save_offset
+ frame_off
;
23887 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23888 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23890 rtx offset
, addr
, mem
, reg
;
23892 /* We're doing all this to ensure that the immediate offset
23893 fits into the immediate field of 'evldd'. */
23894 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset
+ reg_size
* i
));
23896 offset
= GEN_INT (spe_offset
+ reg_size
* i
);
23897 addr
= gen_rtx_PLUS (Pmode
, frame_reg_rtx
, offset
);
23898 mem
= gen_rtx_MEM (V2SImode
, addr
);
23899 reg
= gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
);
23901 emit_move_insn (reg
, mem
);
23905 rs6000_emit_savres_rtx (info
, frame_reg_rtx
,
23906 info
->spe_gp_save_offset
+ frame_off
,
23907 info
->lr_save_offset
+ frame_off
,
23909 SAVRES_GPR
| SAVRES_LR
);
23911 else if (!restoring_GPRs_inline
)
23913 /* We are jumping to an out-of-line function. */
23915 int end_save
= info
->gp_save_offset
+ info
->gp_size
;
23916 bool can_use_exit
= end_save
== 0;
23917 int sel
= SAVRES_GPR
| (can_use_exit
? SAVRES_LR
: 0);
23920 /* Emit stack reset code if we need it. */
23921 ptr_regno
= ptr_regno_for_savres (sel
);
23922 ptr_reg
= gen_rtx_REG (Pmode
, ptr_regno
);
23924 rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
23925 else if (end_save
+ frame_off
!= 0)
23926 emit_insn (gen_add3_insn (ptr_reg
, frame_reg_rtx
,
23927 GEN_INT (end_save
+ frame_off
)));
23928 else if (REGNO (frame_reg_rtx
) != ptr_regno
)
23929 emit_move_insn (ptr_reg
, frame_reg_rtx
);
23930 if (REGNO (frame_reg_rtx
) == ptr_regno
)
23931 frame_off
= -end_save
;
23933 if (can_use_exit
&& info
->cr_save_p
)
23934 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, true);
23936 ptr_off
= -end_save
;
23937 rs6000_emit_savres_rtx (info
, ptr_reg
,
23938 info
->gp_save_offset
+ ptr_off
,
23939 info
->lr_save_offset
+ ptr_off
,
23942 else if (using_load_multiple
)
23945 p
= rtvec_alloc (32 - info
->first_gp_reg_save
);
23946 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23948 = gen_frame_load (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23950 info
->gp_save_offset
+ frame_off
+ reg_size
* i
);
23951 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
23955 for (i
= 0; i
< 32 - info
->first_gp_reg_save
; i
++)
23956 if (rs6000_reg_live_or_pic_offset_p (info
->first_gp_reg_save
+ i
))
23957 emit_insn (gen_frame_load
23958 (gen_rtx_REG (reg_mode
, info
->first_gp_reg_save
+ i
),
23960 info
->gp_save_offset
+ frame_off
+ reg_size
* i
));
23963 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
23965 /* If the frame pointer was used then we can't delay emitting
23966 a REG_CFA_DEF_CFA note. This must happen on the insn that
23967 restores the frame pointer, r31. We may have already emitted
23968 a REG_CFA_DEF_CFA note, but that's OK; A duplicate is
23969 discarded by dwarf2cfi.c/dwarf2out.c, and in any case would
23970 be harmless if emitted. */
23971 if (frame_pointer_needed
)
23973 insn
= get_last_insn ();
23974 add_reg_note (insn
, REG_CFA_DEF_CFA
,
23975 plus_constant (Pmode
, frame_reg_rtx
, frame_off
));
23976 RTX_FRAME_RELATED_P (insn
) = 1;
23979 /* Set up cfa_restores. We always need these when
23980 shrink-wrapping. If not shrink-wrapping then we only need
23981 the cfa_restore when the stack location is no longer valid.
23982 The cfa_restores must be emitted on or before the insn that
23983 invalidates the stack, and of course must not be emitted
23984 before the insn that actually does the restore. The latter
23985 is why it is a bad idea to emit the cfa_restores as a group
23986 on the last instruction here that actually does a restore:
23987 That insn may be reordered with respect to others doing
23989 if (flag_shrink_wrap
23990 && !restoring_GPRs_inline
23991 && info
->first_fp_reg_save
== 64)
23992 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
23994 for (i
= info
->first_gp_reg_save
; i
< 32; i
++)
23995 if (!restoring_GPRs_inline
23996 || using_load_multiple
23997 || rs6000_reg_live_or_pic_offset_p (i
))
23999 rtx reg
= gen_rtx_REG (reg_mode
, i
);
24001 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24005 if (!restoring_GPRs_inline
24006 && info
->first_fp_reg_save
== 64)
24008 /* We are jumping to an out-of-line function. */
24010 emit_cfa_restores (cfa_restores
);
24014 if (restore_lr
&& !restoring_GPRs_inline
)
24016 load_lr_save (0, frame_reg_rtx
, info
->lr_save_offset
+ frame_off
);
24017 restore_saved_lr (0, exit_func
);
24020 /* Restore fpr's if we need to do it without calling a function. */
24021 if (restoring_FPRs_inline
)
24022 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24023 if (save_reg_p (info
->first_fp_reg_save
+ i
))
24025 rtx reg
= gen_rtx_REG ((TARGET_HARD_FLOAT
&& TARGET_DOUBLE_FLOAT
24026 ? DFmode
: SFmode
),
24027 info
->first_fp_reg_save
+ i
);
24028 emit_insn (gen_frame_load (reg
, frame_reg_rtx
,
24029 info
->fp_save_offset
+ frame_off
+ 8 * i
));
24030 if (DEFAULT_ABI
== ABI_V4
|| flag_shrink_wrap
)
24031 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
24034 /* If we saved cr, restore it here. Just those that were used. */
24035 if (info
->cr_save_p
)
24036 restore_saved_cr (cr_save_reg
, using_mtcr_multiple
, exit_func
);
24038 /* If this is V.4, unwind the stack pointer after all of the loads
24039 have been done, or set up r11 if we are restoring fp out of line. */
24041 if (!restoring_FPRs_inline
)
24043 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24044 int sel
= SAVRES_FPR
| (lr
? SAVRES_LR
: 0);
24045 ptr_regno
= ptr_regno_for_savres (sel
);
24048 insn
= rs6000_emit_stack_reset (info
, frame_reg_rtx
, frame_off
, ptr_regno
);
24049 if (REGNO (frame_reg_rtx
) == ptr_regno
)
24052 if (insn
&& restoring_FPRs_inline
)
24056 REG_NOTES (insn
) = cfa_restores
;
24057 cfa_restores
= NULL_RTX
;
24059 add_reg_note (insn
, REG_CFA_DEF_CFA
, sp_reg_rtx
);
24060 RTX_FRAME_RELATED_P (insn
) = 1;
24063 if (crtl
->calls_eh_return
)
24065 rtx sa
= EH_RETURN_STACKADJ_RTX
;
24066 emit_insn (gen_add3_insn (sp_reg_rtx
, sp_reg_rtx
, sa
));
24072 bool lr
= (strategy
& REST_NOINLINE_FPRS_DOESNT_RESTORE_LR
) == 0;
24073 if (! restoring_FPRs_inline
)
24075 p
= rtvec_alloc (4 + 64 - info
->first_fp_reg_save
);
24076 RTVEC_ELT (p
, 0) = ret_rtx
;
24082 /* We can't hang the cfa_restores off a simple return,
24083 since the shrink-wrap code sometimes uses an existing
24084 return. This means there might be a path from
24085 pre-prologue code to this return, and dwarf2cfi code
24086 wants the eh_frame unwinder state to be the same on
24087 all paths to any point. So we need to emit the
24088 cfa_restores before the return. For -m64 we really
24089 don't need epilogue cfa_restores at all, except for
24090 this irritating dwarf2cfi with shrink-wrap
24091 requirement; The stack red-zone means eh_frame info
24092 from the prologue telling the unwinder to restore
24093 from the stack is perfectly good right to the end of
24095 emit_insn (gen_blockage ());
24096 emit_cfa_restores (cfa_restores
);
24097 cfa_restores
= NULL_RTX
;
24099 p
= rtvec_alloc (2);
24100 RTVEC_ELT (p
, 0) = simple_return_rtx
;
24103 RTVEC_ELT (p
, 1) = ((restoring_FPRs_inline
|| !lr
)
24104 ? gen_rtx_USE (VOIDmode
,
24105 gen_rtx_REG (Pmode
, LR_REGNO
))
24106 : gen_rtx_CLOBBER (VOIDmode
,
24107 gen_rtx_REG (Pmode
, LR_REGNO
)));
24109 /* If we have to restore more than two FP registers, branch to the
24110 restore function. It will return to our caller. */
24111 if (! restoring_FPRs_inline
)
24117 if (flag_shrink_wrap
)
24118 cfa_restores
= add_crlr_cfa_restore (info
, cfa_restores
);
24120 sym
= rs6000_savres_routine_sym (info
,
24121 SAVRES_FPR
| (lr
? SAVRES_LR
: 0));
24122 RTVEC_ELT (p
, 2) = gen_rtx_USE (VOIDmode
, sym
);
24123 reg
= (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)? 1 : 11;
24124 RTVEC_ELT (p
, 3) = gen_rtx_USE (VOIDmode
, gen_rtx_REG (Pmode
, reg
));
24126 for (i
= 0; i
< 64 - info
->first_fp_reg_save
; i
++)
24128 rtx reg
= gen_rtx_REG (DFmode
, info
->first_fp_reg_save
+ i
);
24130 RTVEC_ELT (p
, i
+ 4)
24131 = gen_frame_load (reg
, sp_reg_rtx
, info
->fp_save_offset
+ 8 * i
);
24132 if (flag_shrink_wrap
)
24133 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
,
24138 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
24144 /* Ensure the cfa_restores are hung off an insn that won't
24145 be reordered above other restores. */
24146 emit_insn (gen_blockage ());
24148 emit_cfa_restores (cfa_restores
);
24152 /* Write function epilogue. */
24155 rs6000_output_function_epilogue (FILE *file
,
24156 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
24159 macho_branch_islands ();
24160 /* Mach-O doesn't support labels at the end of objects, so if
24161 it looks like we might want one, insert a NOP. */
24163 rtx insn
= get_last_insn ();
24164 rtx deleted_debug_label
= NULL_RTX
;
24167 && NOTE_KIND (insn
) != NOTE_INSN_DELETED_LABEL
)
24169 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
24170 notes only, instead set their CODE_LABEL_NUMBER to -1,
24171 otherwise there would be code generation differences
24172 in between -g and -g0. */
24173 if (NOTE_P (insn
) && NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24174 deleted_debug_label
= insn
;
24175 insn
= PREV_INSN (insn
);
24180 && NOTE_KIND (insn
) == NOTE_INSN_DELETED_LABEL
)))
24181 fputs ("\tnop\n", file
);
24182 else if (deleted_debug_label
)
24183 for (insn
= deleted_debug_label
; insn
; insn
= NEXT_INSN (insn
))
24184 if (NOTE_KIND (insn
) == NOTE_INSN_DELETED_DEBUG_LABEL
)
24185 CODE_LABEL_NUMBER (insn
) = -1;
24189 /* Output a traceback table here. See /usr/include/sys/debug.h for info
24192 We don't output a traceback table if -finhibit-size-directive was
24193 used. The documentation for -finhibit-size-directive reads
24194 ``don't output a @code{.size} assembler directive, or anything
24195 else that would cause trouble if the function is split in the
24196 middle, and the two halves are placed at locations far apart in
24197 memory.'' The traceback table has this property, since it
24198 includes the offset from the start of the function to the
24199 traceback table itself.
24201 System V.4 Powerpc's (and the embedded ABI derived from it) use a
24202 different traceback table. */
24203 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
24204 && ! flag_inhibit_size_directive
24205 && rs6000_traceback
!= traceback_none
&& !cfun
->is_thunk
)
24207 const char *fname
= NULL
;
24208 const char *language_string
= lang_hooks
.name
;
24209 int fixed_parms
= 0, float_parms
= 0, parm_info
= 0;
24211 int optional_tbtab
;
24212 rs6000_stack_t
*info
= rs6000_stack_info ();
24214 if (rs6000_traceback
== traceback_full
)
24215 optional_tbtab
= 1;
24216 else if (rs6000_traceback
== traceback_part
)
24217 optional_tbtab
= 0;
24219 optional_tbtab
= !optimize_size
&& !TARGET_ELF
;
24221 if (optional_tbtab
)
24223 fname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
24224 while (*fname
== '.') /* V.4 encodes . in the name */
24227 /* Need label immediately before tbtab, so we can compute
24228 its offset from the function start. */
24229 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24230 ASM_OUTPUT_LABEL (file
, fname
);
24233 /* The .tbtab pseudo-op can only be used for the first eight
24234 expressions, since it can't handle the possibly variable
24235 length fields that follow. However, if you omit the optional
24236 fields, the assembler outputs zeros for all optional fields
24237 anyways, giving each variable length field is minimum length
24238 (as defined in sys/debug.h). Thus we can not use the .tbtab
24239 pseudo-op at all. */
24241 /* An all-zero word flags the start of the tbtab, for debuggers
24242 that have to find it by searching forward from the entry
24243 point or from the current pc. */
24244 fputs ("\t.long 0\n", file
);
24246 /* Tbtab format type. Use format type 0. */
24247 fputs ("\t.byte 0,", file
);
24249 /* Language type. Unfortunately, there does not seem to be any
24250 official way to discover the language being compiled, so we
24251 use language_string.
24252 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
24253 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
24254 a number, so for now use 9. LTO and Go aren't assigned numbers
24255 either, so for now use 0. */
24256 if (! strcmp (language_string
, "GNU C")
24257 || ! strcmp (language_string
, "GNU GIMPLE")
24258 || ! strcmp (language_string
, "GNU Go"))
24260 else if (! strcmp (language_string
, "GNU F77")
24261 || ! strcmp (language_string
, "GNU Fortran"))
24263 else if (! strcmp (language_string
, "GNU Pascal"))
24265 else if (! strcmp (language_string
, "GNU Ada"))
24267 else if (! strcmp (language_string
, "GNU C++")
24268 || ! strcmp (language_string
, "GNU Objective-C++"))
24270 else if (! strcmp (language_string
, "GNU Java"))
24272 else if (! strcmp (language_string
, "GNU Objective-C"))
24275 gcc_unreachable ();
24276 fprintf (file
, "%d,", i
);
24278 /* 8 single bit fields: global linkage (not set for C extern linkage,
24279 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
24280 from start of procedure stored in tbtab, internal function, function
24281 has controlled storage, function has no toc, function uses fp,
24282 function logs/aborts fp operations. */
24283 /* Assume that fp operations are used if any fp reg must be saved. */
24284 fprintf (file
, "%d,",
24285 (optional_tbtab
<< 5) | ((info
->first_fp_reg_save
!= 64) << 1));
24287 /* 6 bitfields: function is interrupt handler, name present in
24288 proc table, function calls alloca, on condition directives
24289 (controls stack walks, 3 bits), saves condition reg, saves
24291 /* The `function calls alloca' bit seems to be set whenever reg 31 is
24292 set up as a frame pointer, even when there is no alloca call. */
24293 fprintf (file
, "%d,",
24294 ((optional_tbtab
<< 6)
24295 | ((optional_tbtab
& frame_pointer_needed
) << 5)
24296 | (info
->cr_save_p
<< 1)
24297 | (info
->lr_save_p
)));
24299 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
24301 fprintf (file
, "%d,",
24302 (info
->push_p
<< 7) | (64 - info
->first_fp_reg_save
));
24304 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
24305 fprintf (file
, "%d,", (32 - first_reg_to_save ()));
24307 if (optional_tbtab
)
24309 /* Compute the parameter info from the function decl argument
24312 int next_parm_info_bit
= 31;
24314 for (decl
= DECL_ARGUMENTS (current_function_decl
);
24315 decl
; decl
= DECL_CHAIN (decl
))
24317 rtx parameter
= DECL_INCOMING_RTL (decl
);
24318 enum machine_mode mode
= GET_MODE (parameter
);
24320 if (GET_CODE (parameter
) == REG
)
24322 if (SCALAR_FLOAT_MODE_P (mode
))
24343 gcc_unreachable ();
24346 /* If only one bit will fit, don't or in this entry. */
24347 if (next_parm_info_bit
> 0)
24348 parm_info
|= (bits
<< (next_parm_info_bit
- 1));
24349 next_parm_info_bit
-= 2;
24353 fixed_parms
+= ((GET_MODE_SIZE (mode
)
24354 + (UNITS_PER_WORD
- 1))
24356 next_parm_info_bit
-= 1;
24362 /* Number of fixed point parameters. */
24363 /* This is actually the number of words of fixed point parameters; thus
24364 an 8 byte struct counts as 2; and thus the maximum value is 8. */
24365 fprintf (file
, "%d,", fixed_parms
);
24367 /* 2 bitfields: number of floating point parameters (7 bits), parameters
24369 /* This is actually the number of fp registers that hold parameters;
24370 and thus the maximum value is 13. */
24371 /* Set parameters on stack bit if parameters are not in their original
24372 registers, regardless of whether they are on the stack? Xlc
24373 seems to set the bit when not optimizing. */
24374 fprintf (file
, "%d\n", ((float_parms
<< 1) | (! optimize
)));
24376 if (! optional_tbtab
)
24379 /* Optional fields follow. Some are variable length. */
24381 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
24382 11 double float. */
24383 /* There is an entry for each parameter in a register, in the order that
24384 they occur in the parameter list. Any intervening arguments on the
24385 stack are ignored. If the list overflows a long (max possible length
24386 34 bits) then completely leave off all elements that don't fit. */
24387 /* Only emit this long if there was at least one parameter. */
24388 if (fixed_parms
|| float_parms
)
24389 fprintf (file
, "\t.long %d\n", parm_info
);
24391 /* Offset from start of code to tb table. */
24392 fputs ("\t.long ", file
);
24393 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LT");
24394 RS6000_OUTPUT_BASENAME (file
, fname
);
24396 rs6000_output_function_entry (file
, fname
);
24399 /* Interrupt handler mask. */
24400 /* Omit this long, since we never set the interrupt handler bit
24403 /* Number of CTL (controlled storage) anchors. */
24404 /* Omit this long, since the has_ctl bit is never set above. */
24406 /* Displacement into stack of each CTL anchor. */
24407 /* Omit this list of longs, because there are no CTL anchors. */
24409 /* Length of function name. */
24412 fprintf (file
, "\t.short %d\n", (int) strlen (fname
));
24414 /* Function name. */
24415 assemble_string (fname
, strlen (fname
));
24417 /* Register for alloca automatic storage; this is always reg 31.
24418 Only emit this if the alloca bit was set above. */
24419 if (frame_pointer_needed
)
24420 fputs ("\t.byte 31\n", file
);
24422 fputs ("\t.align 2\n", file
);
24426 /* A C compound statement that outputs the assembler code for a thunk
24427 function, used to implement C++ virtual function calls with
24428 multiple inheritance. The thunk acts as a wrapper around a virtual
24429 function, adjusting the implicit object parameter before handing
24430 control off to the real function.
24432 First, emit code to add the integer DELTA to the location that
24433 contains the incoming first argument. Assume that this argument
24434 contains a pointer, and is the one used to pass the `this' pointer
24435 in C++. This is the incoming argument *before* the function
24436 prologue, e.g. `%o0' on a sparc. The addition must preserve the
24437 values of all other incoming arguments.
24439 After the addition, emit code to jump to FUNCTION, which is a
24440 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
24441 not touch the return address. Hence returning from FUNCTION will
24442 return to whoever called the current `thunk'.
24444 The effect must be as if FUNCTION had been called directly with the
24445 adjusted first argument. This macro is responsible for emitting
24446 all of the code for a thunk function; output_function_prologue()
24447 and output_function_epilogue() are not invoked.
24449 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
24450 been extracted from it.) It might possibly be useful on some
24451 targets, but probably not.
24453 If you do not define this macro, the target-independent code in the
24454 C++ frontend will generate a less efficient heavyweight thunk that
24455 calls FUNCTION instead of jumping to it. The generic approach does
24456 not support varargs. */
24459 rs6000_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
24460 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
24463 rtx this_rtx
, insn
, funexp
;
24465 reload_completed
= 1;
24466 epilogue_completed
= 1;
24468 /* Mark the end of the (empty) prologue. */
24469 emit_note (NOTE_INSN_PROLOGUE_END
);
24471 /* Find the "this" pointer. If the function returns a structure,
24472 the structure return pointer is in r3. */
24473 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
24474 this_rtx
= gen_rtx_REG (Pmode
, 4);
24476 this_rtx
= gen_rtx_REG (Pmode
, 3);
24478 /* Apply the constant offset, if required. */
24480 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, GEN_INT (delta
)));
24482 /* Apply the offset from the vtable, if required. */
24485 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
24486 rtx tmp
= gen_rtx_REG (Pmode
, 12);
24488 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, this_rtx
));
24489 if (((unsigned HOST_WIDE_INT
) vcall_offset
) + 0x8000 >= 0x10000)
24491 emit_insn (gen_add3_insn (tmp
, tmp
, vcall_offset_rtx
));
24492 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, tmp
));
24496 rtx loc
= gen_rtx_PLUS (Pmode
, tmp
, vcall_offset_rtx
);
24498 emit_move_insn (tmp
, gen_rtx_MEM (Pmode
, loc
));
24500 emit_insn (gen_add3_insn (this_rtx
, this_rtx
, tmp
));
24503 /* Generate a tail call to the target function. */
24504 if (!TREE_USED (function
))
24506 assemble_external (function
);
24507 TREE_USED (function
) = 1;
24509 funexp
= XEXP (DECL_RTL (function
), 0);
24510 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
24513 if (MACHOPIC_INDIRECT
)
24514 funexp
= machopic_indirect_call_target (funexp
);
24517 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
24518 generate sibcall RTL explicitly. */
24519 insn
= emit_call_insn (
24520 gen_rtx_PARALLEL (VOIDmode
,
24522 gen_rtx_CALL (VOIDmode
,
24523 funexp
, const0_rtx
),
24524 gen_rtx_USE (VOIDmode
, const0_rtx
),
24525 gen_rtx_USE (VOIDmode
,
24526 gen_rtx_REG (SImode
,
24528 simple_return_rtx
)));
24529 SIBLING_CALL_P (insn
) = 1;
24532 /* Ensure we have a global entry point for the thunk. ??? We could
24533 avoid that if the target routine doesn't need a global entry point,
24534 but we do not know whether this is the case at this point. */
24535 if (DEFAULT_ABI
== ABI_ELFv2
)
24536 cfun
->machine
->r2_setup_needed
= true;
24538 /* Run just enough of rest_of_compilation to get the insns emitted.
24539 There's not really enough bulk here to make other passes such as
24540 instruction scheduling worth while. Note that use_thunk calls
24541 assemble_start_function and assemble_end_function. */
24542 insn
= get_insns ();
24543 shorten_branches (insn
);
24544 final_start_function (insn
, file
, 1);
24545 final (insn
, file
, 1);
24546 final_end_function ();
24548 reload_completed
= 0;
24549 epilogue_completed
= 0;
24552 /* A quick summary of the various types of 'constant-pool tables'
24555 Target Flags Name One table per
24556 AIX (none) AIX TOC object file
24557 AIX -mfull-toc AIX TOC object file
24558 AIX -mminimal-toc AIX minimal TOC translation unit
24559 SVR4/EABI (none) SVR4 SDATA object file
24560 SVR4/EABI -fpic SVR4 pic object file
24561 SVR4/EABI -fPIC SVR4 PIC translation unit
24562 SVR4/EABI -mrelocatable EABI TOC function
24563 SVR4/EABI -maix AIX TOC object file
24564 SVR4/EABI -maix -mminimal-toc
24565 AIX minimal TOC translation unit
24567 Name Reg. Set by entries contains:
24568 made by addrs? fp? sum?
24570 AIX TOC 2 crt0 as Y option option
24571 AIX minimal TOC 30 prolog gcc Y Y option
24572 SVR4 SDATA 13 crt0 gcc N Y N
24573 SVR4 pic 30 prolog ld Y not yet N
24574 SVR4 PIC 30 prolog gcc Y option option
24575 EABI TOC 30 prolog gcc Y option option
24579 /* Hash functions for the hash table. */
24582 rs6000_hash_constant (rtx k
)
24584 enum rtx_code code
= GET_CODE (k
);
24585 enum machine_mode mode
= GET_MODE (k
);
24586 unsigned result
= (code
<< 3) ^ mode
;
24587 const char *format
;
24590 format
= GET_RTX_FORMAT (code
);
24591 flen
= strlen (format
);
24597 return result
* 1231 + (unsigned) INSN_UID (XEXP (k
, 0));
24599 case CONST_WIDE_INT
:
24602 flen
= CONST_WIDE_INT_NUNITS (k
);
24603 for (i
= 0; i
< flen
; i
++)
24604 result
= result
* 613 + CONST_WIDE_INT_ELT (k
, i
);
24609 if (mode
!= VOIDmode
)
24610 return real_hash (CONST_DOUBLE_REAL_VALUE (k
)) * result
;
24622 for (; fidx
< flen
; fidx
++)
24623 switch (format
[fidx
])
24628 const char *str
= XSTR (k
, fidx
);
24629 len
= strlen (str
);
24630 result
= result
* 613 + len
;
24631 for (i
= 0; i
< len
; i
++)
24632 result
= result
* 613 + (unsigned) str
[i
];
24637 result
= result
* 1231 + rs6000_hash_constant (XEXP (k
, fidx
));
24641 result
= result
* 613 + (unsigned) XINT (k
, fidx
);
24644 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT
))
24645 result
= result
* 613 + (unsigned) XWINT (k
, fidx
);
24649 for (i
= 0; i
< sizeof (HOST_WIDE_INT
) / sizeof (unsigned); i
++)
24650 result
= result
* 613 + (unsigned) (XWINT (k
, fidx
)
24657 gcc_unreachable ();
24664 toc_hash_function (const void *hash_entry
)
24666 const struct toc_hash_struct
*thc
=
24667 (const struct toc_hash_struct
*) hash_entry
;
24668 return rs6000_hash_constant (thc
->key
) ^ thc
->key_mode
;
24671 /* Compare H1 and H2 for equivalence. */
24674 toc_hash_eq (const void *h1
, const void *h2
)
24676 rtx r1
= ((const struct toc_hash_struct
*) h1
)->key
;
24677 rtx r2
= ((const struct toc_hash_struct
*) h2
)->key
;
24679 if (((const struct toc_hash_struct
*) h1
)->key_mode
24680 != ((const struct toc_hash_struct
*) h2
)->key_mode
)
24683 return rtx_equal_p (r1
, r2
);
24686 /* These are the names given by the C++ front-end to vtables, and
24687 vtable-like objects. Ideally, this logic should not be here;
24688 instead, there should be some programmatic way of inquiring as
24689 to whether or not an object is a vtable. */
24691 #define VTABLE_NAME_P(NAME) \
24692 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
24693 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
24694 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
24695 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
24696 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
24698 #ifdef NO_DOLLAR_IN_LABEL
24699 /* Return a GGC-allocated character string translating dollar signs in
24700 input NAME to underscores. Used by XCOFF ASM_OUTPUT_LABELREF. */
24703 rs6000_xcoff_strip_dollar (const char *name
)
24709 q
= (const char *) strchr (name
, '$');
24711 if (q
== 0 || q
== name
)
24714 len
= strlen (name
);
24715 strip
= XALLOCAVEC (char, len
+ 1);
24716 strcpy (strip
, name
);
24717 p
= strip
+ (q
- name
);
24721 p
= strchr (p
+ 1, '$');
24724 return ggc_alloc_string (strip
, len
);
24729 rs6000_output_symbol_ref (FILE *file
, rtx x
)
24731 /* Currently C++ toc references to vtables can be emitted before it
24732 is decided whether the vtable is public or private. If this is
24733 the case, then the linker will eventually complain that there is
24734 a reference to an unknown section. Thus, for vtables only,
24735 we emit the TOC reference to reference the symbol and not the
24737 const char *name
= XSTR (x
, 0);
24739 if (VTABLE_NAME_P (name
))
24741 RS6000_OUTPUT_BASENAME (file
, name
);
24744 assemble_name (file
, name
);
24747 /* Output a TOC entry. We derive the entry name from what is being
24751 output_toc (FILE *file
, rtx x
, int labelno
, enum machine_mode mode
)
24754 const char *name
= buf
;
24756 HOST_WIDE_INT offset
= 0;
24758 gcc_assert (!TARGET_NO_TOC
);
24760 /* When the linker won't eliminate them, don't output duplicate
24761 TOC entries (this happens on AIX if there is any kind of TOC,
24762 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
24764 if (TARGET_TOC
&& GET_CODE (x
) != LABEL_REF
)
24766 struct toc_hash_struct
*h
;
24769 /* Create toc_hash_table. This can't be done at TARGET_OPTION_OVERRIDE
24770 time because GGC is not initialized at that point. */
24771 if (toc_hash_table
== NULL
)
24772 toc_hash_table
= htab_create_ggc (1021, toc_hash_function
,
24773 toc_hash_eq
, NULL
);
24775 h
= ggc_alloc_toc_hash_struct ();
24777 h
->key_mode
= mode
;
24778 h
->labelno
= labelno
;
24780 found
= htab_find_slot (toc_hash_table
, h
, INSERT
);
24781 if (*found
== NULL
)
24783 else /* This is indeed a duplicate.
24784 Set this label equal to that label. */
24786 fputs ("\t.set ", file
);
24787 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
24788 fprintf (file
, "%d,", labelno
);
24789 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LC");
24790 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
24794 if (TARGET_XCOFF
&& GET_CODE (x
) == SYMBOL_REF
24795 && (SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_GLOBAL_DYNAMIC
24796 || SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
))
24798 fputs ("\t.set ", file
);
24799 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
24800 fprintf (file
, "%d,", labelno
);
24801 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file
, "LCM");
24802 fprintf (file
, "%d\n", ((*(const struct toc_hash_struct
**)
24810 /* If we're going to put a double constant in the TOC, make sure it's
24811 aligned properly when strict alignment is on. */
24812 if ((CONST_DOUBLE_P (x
) || CONST_WIDE_INT_P (x
))
24813 && STRICT_ALIGNMENT
24814 && GET_MODE_BITSIZE (mode
) >= 64
24815 && ! (TARGET_NO_FP_IN_TOC
&& ! TARGET_MINIMAL_TOC
)) {
24816 ASM_OUTPUT_ALIGN (file
, 3);
24819 (*targetm
.asm_out
.internal_label
) (file
, "LC", labelno
);
24821 /* Handle FP constants specially. Note that if we have a minimal
24822 TOC, things we put here aren't actually in the TOC, so we can allow
24824 if (GET_CODE (x
) == CONST_DOUBLE
&&
24825 (GET_MODE (x
) == TFmode
|| GET_MODE (x
) == TDmode
))
24827 REAL_VALUE_TYPE rv
;
24830 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24831 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24832 REAL_VALUE_TO_TARGET_DECIMAL128 (rv
, k
);
24834 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv
, k
);
24838 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24839 fputs (DOUBLE_INT_ASM_OP
, file
);
24841 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
24842 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24843 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24844 fprintf (file
, "0x%lx%08lx,0x%lx%08lx\n",
24845 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
24846 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff,
24847 k
[WORDS_BIG_ENDIAN
? 2 : 3] & 0xffffffff,
24848 k
[WORDS_BIG_ENDIAN
? 3 : 2] & 0xffffffff);
24853 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24854 fputs ("\t.long ", file
);
24856 fprintf (file
, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
24857 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24858 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24859 fprintf (file
, "0x%lx,0x%lx,0x%lx,0x%lx\n",
24860 k
[0] & 0xffffffff, k
[1] & 0xffffffff,
24861 k
[2] & 0xffffffff, k
[3] & 0xffffffff);
24865 else if (GET_CODE (x
) == CONST_DOUBLE
&&
24866 (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DDmode
))
24868 REAL_VALUE_TYPE rv
;
24871 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24873 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24874 REAL_VALUE_TO_TARGET_DECIMAL64 (rv
, k
);
24876 REAL_VALUE_TO_TARGET_DOUBLE (rv
, k
);
24880 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24881 fputs (DOUBLE_INT_ASM_OP
, file
);
24883 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
24884 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24885 fprintf (file
, "0x%lx%08lx\n",
24886 k
[WORDS_BIG_ENDIAN
? 0 : 1] & 0xffffffff,
24887 k
[WORDS_BIG_ENDIAN
? 1 : 0] & 0xffffffff);
24892 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24893 fputs ("\t.long ", file
);
24895 fprintf (file
, "\t.tc FD_%lx_%lx[TC],",
24896 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24897 fprintf (file
, "0x%lx,0x%lx\n",
24898 k
[0] & 0xffffffff, k
[1] & 0xffffffff);
24902 else if (GET_CODE (x
) == CONST_DOUBLE
&&
24903 (GET_MODE (x
) == SFmode
|| GET_MODE (x
) == SDmode
))
24905 REAL_VALUE_TYPE rv
;
24908 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
24909 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x
)))
24910 REAL_VALUE_TO_TARGET_DECIMAL32 (rv
, l
);
24912 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
24916 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24917 fputs (DOUBLE_INT_ASM_OP
, file
);
24919 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
24920 if (WORDS_BIG_ENDIAN
)
24921 fprintf (file
, "0x%lx00000000\n", l
& 0xffffffff);
24923 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
24928 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24929 fputs ("\t.long ", file
);
24931 fprintf (file
, "\t.tc FS_%lx[TC],", l
& 0xffffffff);
24932 fprintf (file
, "0x%lx\n", l
& 0xffffffff);
24936 else if (GET_MODE (x
) == VOIDmode
&& GET_CODE (x
) == CONST_INT
)
24938 unsigned HOST_WIDE_INT low
;
24939 HOST_WIDE_INT high
;
24941 low
= INTVAL (x
) & 0xffffffff;
24942 high
= (HOST_WIDE_INT
) INTVAL (x
) >> 32;
24944 /* TOC entries are always Pmode-sized, so when big-endian
24945 smaller integer constants in the TOC need to be padded.
24946 (This is still a win over putting the constants in
24947 a separate constant pool, because then we'd have
24948 to have both a TOC entry _and_ the actual constant.)
24950 For a 32-bit target, CONST_INT values are loaded and shifted
24951 entirely within `low' and can be stored in one TOC entry. */
24953 /* It would be easy to make this work, but it doesn't now. */
24954 gcc_assert (!TARGET_64BIT
|| POINTER_SIZE
>= GET_MODE_BITSIZE (mode
));
24956 if (WORDS_BIG_ENDIAN
&& POINTER_SIZE
> GET_MODE_BITSIZE (mode
))
24959 low
<<= POINTER_SIZE
- GET_MODE_BITSIZE (mode
);
24960 high
= (HOST_WIDE_INT
) low
>> 32;
24966 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24967 fputs (DOUBLE_INT_ASM_OP
, file
);
24969 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
24970 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24971 fprintf (file
, "0x%lx%08lx\n",
24972 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24977 if (POINTER_SIZE
< GET_MODE_BITSIZE (mode
))
24979 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24980 fputs ("\t.long ", file
);
24982 fprintf (file
, "\t.tc ID_%lx_%lx[TC],",
24983 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24984 fprintf (file
, "0x%lx,0x%lx\n",
24985 (long) high
& 0xffffffff, (long) low
& 0xffffffff);
24989 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
24990 fputs ("\t.long ", file
);
24992 fprintf (file
, "\t.tc IS_%lx[TC],", (long) low
& 0xffffffff);
24993 fprintf (file
, "0x%lx\n", (long) low
& 0xffffffff);
24999 if (GET_CODE (x
) == CONST
)
25001 gcc_assert (GET_CODE (XEXP (x
, 0)) == PLUS
25002 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
);
25004 base
= XEXP (XEXP (x
, 0), 0);
25005 offset
= INTVAL (XEXP (XEXP (x
, 0), 1));
25008 switch (GET_CODE (base
))
25011 name
= XSTR (base
, 0);
25015 ASM_GENERATE_INTERNAL_LABEL (buf
, "L",
25016 CODE_LABEL_NUMBER (XEXP (base
, 0)));
25020 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (base
));
25024 gcc_unreachable ();
25027 if (TARGET_ELF
|| TARGET_MINIMAL_TOC
)
25028 fputs (TARGET_32BIT
? "\t.long " : DOUBLE_INT_ASM_OP
, file
);
25031 fputs ("\t.tc ", file
);
25032 RS6000_OUTPUT_BASENAME (file
, name
);
25035 fprintf (file
, ".N" HOST_WIDE_INT_PRINT_UNSIGNED
, - offset
);
25037 fprintf (file
, ".P" HOST_WIDE_INT_PRINT_UNSIGNED
, offset
);
25039 /* Mark large TOC symbols on AIX with [TE] so they are mapped
25040 after other TOC symbols, reducing overflow of small TOC access
25041 to [TC] symbols. */
25042 fputs (TARGET_XCOFF
&& TARGET_CMODEL
!= CMODEL_SMALL
25043 ? "[TE]," : "[TC],", file
);
25046 /* Currently C++ toc references to vtables can be emitted before it
25047 is decided whether the vtable is public or private. If this is
25048 the case, then the linker will eventually complain that there is
25049 a TOC reference to an unknown section. Thus, for vtables only,
25050 we emit the TOC reference to reference the symbol and not the
25052 if (VTABLE_NAME_P (name
))
25054 RS6000_OUTPUT_BASENAME (file
, name
);
25056 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
);
25057 else if (offset
> 0)
25058 fprintf (file
, "+" HOST_WIDE_INT_PRINT_DEC
, offset
);
25061 output_addr_const (file
, x
);
25064 if (TARGET_XCOFF
&& GET_CODE (base
) == SYMBOL_REF
25065 && SYMBOL_REF_TLS_MODEL (base
) != 0)
25067 if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_EXEC
)
25068 fputs ("@le", file
);
25069 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_INITIAL_EXEC
)
25070 fputs ("@ie", file
);
25071 /* Use global-dynamic for local-dynamic. */
25072 else if (SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_GLOBAL_DYNAMIC
25073 || SYMBOL_REF_TLS_MODEL (base
) == TLS_MODEL_LOCAL_DYNAMIC
)
25076 (*targetm
.asm_out
.internal_label
) (file
, "LCM", labelno
);
25077 fputs ("\t.tc .", file
);
25078 RS6000_OUTPUT_BASENAME (file
, name
);
25079 fputs ("[TC],", file
);
25080 output_addr_const (file
, x
);
25081 fputs ("@m", file
);
25089 /* Output an assembler pseudo-op to write an ASCII string of N characters
25090 starting at P to FILE.
25092 On the RS/6000, we have to do this using the .byte operation and
25093 write out special characters outside the quoted string.
25094 Also, the assembler is broken; very long strings are truncated,
25095 so we must artificially break them up early. */
25098 output_ascii (FILE *file
, const char *p
, int n
)
25101 int i
, count_string
;
25102 const char *for_string
= "\t.byte \"";
25103 const char *for_decimal
= "\t.byte ";
25104 const char *to_close
= NULL
;
25107 for (i
= 0; i
< n
; i
++)
25110 if (c
>= ' ' && c
< 0177)
25113 fputs (for_string
, file
);
25116 /* Write two quotes to get one. */
25124 for_decimal
= "\"\n\t.byte ";
25128 if (count_string
>= 512)
25130 fputs (to_close
, file
);
25132 for_string
= "\t.byte \"";
25133 for_decimal
= "\t.byte ";
25141 fputs (for_decimal
, file
);
25142 fprintf (file
, "%d", c
);
25144 for_string
= "\n\t.byte \"";
25145 for_decimal
= ", ";
25151 /* Now close the string if we have written one. Then end the line. */
25153 fputs (to_close
, file
);
25156 /* Generate a unique section name for FILENAME for a section type
25157 represented by SECTION_DESC. Output goes into BUF.
25159 SECTION_DESC can be any string, as long as it is different for each
25160 possible section type.
25162 We name the section in the same manner as xlc. The name begins with an
25163 underscore followed by the filename (after stripping any leading directory
25164 names) with the last period replaced by the string SECTION_DESC. If
25165 FILENAME does not contain a period, SECTION_DESC is appended to the end of
25169 rs6000_gen_section_name (char **buf
, const char *filename
,
25170 const char *section_desc
)
25172 const char *q
, *after_last_slash
, *last_period
= 0;
25176 after_last_slash
= filename
;
25177 for (q
= filename
; *q
; q
++)
25180 after_last_slash
= q
+ 1;
25181 else if (*q
== '.')
25185 len
= strlen (after_last_slash
) + strlen (section_desc
) + 2;
25186 *buf
= (char *) xmalloc (len
);
25191 for (q
= after_last_slash
; *q
; q
++)
25193 if (q
== last_period
)
25195 strcpy (p
, section_desc
);
25196 p
+= strlen (section_desc
);
25200 else if (ISALNUM (*q
))
25204 if (last_period
== 0)
25205 strcpy (p
, section_desc
);
25210 /* Emit profile function. */
25213 output_profile_hook (int labelno ATTRIBUTE_UNUSED
)
25215 /* Non-standard profiling for kernels, which just saves LR then calls
25216 _mcount without worrying about arg saves. The idea is to change
25217 the function prologue as little as possible as it isn't easy to
25218 account for arg save/restore code added just for _mcount. */
25219 if (TARGET_PROFILE_KERNEL
)
25222 if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
25224 #ifndef NO_PROFILE_COUNTERS
25225 # define NO_PROFILE_COUNTERS 0
25227 if (NO_PROFILE_COUNTERS
)
25228 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25229 LCT_NORMAL
, VOIDmode
, 0);
25233 const char *label_name
;
25236 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25237 label_name
= ggc_strdup ((*targetm
.strip_name_encoding
) (buf
));
25238 fun
= gen_rtx_SYMBOL_REF (Pmode
, label_name
);
25240 emit_library_call (init_one_libfunc (RS6000_MCOUNT
),
25241 LCT_NORMAL
, VOIDmode
, 1, fun
, Pmode
);
25244 else if (DEFAULT_ABI
== ABI_DARWIN
)
25246 const char *mcount_name
= RS6000_MCOUNT
;
25247 int caller_addr_regno
= LR_REGNO
;
25249 /* Be conservative and always set this, at least for now. */
25250 crtl
->uses_pic_offset_table
= 1;
25253 /* For PIC code, set up a stub and collect the caller's address
25254 from r0, which is where the prologue puts it. */
25255 if (MACHOPIC_INDIRECT
25256 && crtl
->uses_pic_offset_table
)
25257 caller_addr_regno
= 0;
25259 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, mcount_name
),
25260 LCT_NORMAL
, VOIDmode
, 1,
25261 gen_rtx_REG (Pmode
, caller_addr_regno
), Pmode
);
25265 /* Write function profiler code. */
25268 output_function_profiler (FILE *file
, int labelno
)
25272 switch (DEFAULT_ABI
)
25275 gcc_unreachable ();
25280 warning (0, "no profiling of 64-bit code for this ABI");
25283 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
25284 fprintf (file
, "\tmflr %s\n", reg_names
[0]);
25285 if (NO_PROFILE_COUNTERS
)
25287 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25288 reg_names
[0], reg_names
[1]);
25290 else if (TARGET_SECURE_PLT
&& flag_pic
)
25292 if (TARGET_LINK_STACK
)
25295 get_ppc476_thunk_name (name
);
25296 asm_fprintf (file
, "\tbl %s\n", name
);
25299 asm_fprintf (file
, "\tbcl 20,31,1f\n1:\n");
25300 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25301 reg_names
[0], reg_names
[1]);
25302 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25303 asm_fprintf (file
, "\taddis %s,%s,",
25304 reg_names
[12], reg_names
[12]);
25305 assemble_name (file
, buf
);
25306 asm_fprintf (file
, "-1b@ha\n\tla %s,", reg_names
[0]);
25307 assemble_name (file
, buf
);
25308 asm_fprintf (file
, "-1b@l(%s)\n", reg_names
[12]);
25310 else if (flag_pic
== 1)
25312 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file
);
25313 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25314 reg_names
[0], reg_names
[1]);
25315 asm_fprintf (file
, "\tmflr %s\n", reg_names
[12]);
25316 asm_fprintf (file
, "\tlwz %s,", reg_names
[0]);
25317 assemble_name (file
, buf
);
25318 asm_fprintf (file
, "@got(%s)\n", reg_names
[12]);
25320 else if (flag_pic
> 1)
25322 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25323 reg_names
[0], reg_names
[1]);
25324 /* Now, we need to get the address of the label. */
25325 if (TARGET_LINK_STACK
)
25328 get_ppc476_thunk_name (name
);
25329 asm_fprintf (file
, "\tbl %s\n\tb 1f\n\t.long ", name
);
25330 assemble_name (file
, buf
);
25331 fputs ("-.\n1:", file
);
25332 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
25333 asm_fprintf (file
, "\taddi %s,%s,4\n",
25334 reg_names
[11], reg_names
[11]);
25338 fputs ("\tbcl 20,31,1f\n\t.long ", file
);
25339 assemble_name (file
, buf
);
25340 fputs ("-.\n1:", file
);
25341 asm_fprintf (file
, "\tmflr %s\n", reg_names
[11]);
25343 asm_fprintf (file
, "\tlwz %s,0(%s)\n",
25344 reg_names
[0], reg_names
[11]);
25345 asm_fprintf (file
, "\tadd %s,%s,%s\n",
25346 reg_names
[0], reg_names
[0], reg_names
[11]);
25350 asm_fprintf (file
, "\tlis %s,", reg_names
[12]);
25351 assemble_name (file
, buf
);
25352 fputs ("@ha\n", file
);
25353 asm_fprintf (file
, "\tstw %s,4(%s)\n",
25354 reg_names
[0], reg_names
[1]);
25355 asm_fprintf (file
, "\tla %s,", reg_names
[0]);
25356 assemble_name (file
, buf
);
25357 asm_fprintf (file
, "@l(%s)\n", reg_names
[12]);
25360 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
25361 fprintf (file
, "\tbl %s%s\n",
25362 RS6000_MCOUNT
, flag_pic
? "@plt" : "");
25368 /* Don't do anything, done in output_profile_hook (). */
25375 /* The following variable value is the last issued insn. */
25377 static rtx last_scheduled_insn
;
25379 /* The following variable helps to balance issuing of load and
25380 store instructions */
25382 static int load_store_pendulum
;
25384 /* Power4 load update and store update instructions are cracked into a
25385 load or store and an integer insn which are executed in the same cycle.
25386 Branches have their own dispatch slot which does not count against the
25387 GCC issue rate, but it changes the program flow so there are no other
25388 instructions to issue in this cycle. */
25391 rs6000_variable_issue_1 (rtx insn
, int more
)
25393 last_scheduled_insn
= insn
;
25394 if (GET_CODE (PATTERN (insn
)) == USE
25395 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25397 cached_can_issue_more
= more
;
25398 return cached_can_issue_more
;
25401 if (insn_terminates_group_p (insn
, current_group
))
25403 cached_can_issue_more
= 0;
25404 return cached_can_issue_more
;
25407 /* If no reservation, but reach here */
25408 if (recog_memoized (insn
) < 0)
25411 if (rs6000_sched_groups
)
25413 if (is_microcoded_insn (insn
))
25414 cached_can_issue_more
= 0;
25415 else if (is_cracked_insn (insn
))
25416 cached_can_issue_more
= more
> 2 ? more
- 2 : 0;
25418 cached_can_issue_more
= more
- 1;
25420 return cached_can_issue_more
;
25423 if (rs6000_cpu_attr
== CPU_CELL
&& is_nonpipeline_insn (insn
))
25426 cached_can_issue_more
= more
- 1;
25427 return cached_can_issue_more
;
25431 rs6000_variable_issue (FILE *stream
, int verbose
, rtx insn
, int more
)
25433 int r
= rs6000_variable_issue_1 (insn
, more
);
25435 fprintf (stream
, "// rs6000_variable_issue (more = %d) = %d\n", more
, r
);
25439 /* Adjust the cost of a scheduling dependency. Return the new cost of
25440 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
25443 rs6000_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
25445 enum attr_type attr_type
;
25447 if (! recog_memoized (insn
))
25450 switch (REG_NOTE_KIND (link
))
25454 /* Data dependency; DEP_INSN writes a register that INSN reads
25455 some cycles later. */
25457 /* Separate a load from a narrower, dependent store. */
25458 if (rs6000_sched_groups
25459 && GET_CODE (PATTERN (insn
)) == SET
25460 && GET_CODE (PATTERN (dep_insn
)) == SET
25461 && GET_CODE (XEXP (PATTERN (insn
), 1)) == MEM
25462 && GET_CODE (XEXP (PATTERN (dep_insn
), 0)) == MEM
25463 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn
), 1)))
25464 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn
), 0)))))
25467 attr_type
= get_attr_type (insn
);
25472 /* Tell the first scheduling pass about the latency between
25473 a mtctr and bctr (and mtlr and br/blr). The first
25474 scheduling pass will not know about this latency since
25475 the mtctr instruction, which has the latency associated
25476 to it, will be generated by reload. */
25479 /* Leave some extra cycles between a compare and its
25480 dependent branch, to inhibit expensive mispredicts. */
25481 if ((rs6000_cpu_attr
== CPU_PPC603
25482 || rs6000_cpu_attr
== CPU_PPC604
25483 || rs6000_cpu_attr
== CPU_PPC604E
25484 || rs6000_cpu_attr
== CPU_PPC620
25485 || rs6000_cpu_attr
== CPU_PPC630
25486 || rs6000_cpu_attr
== CPU_PPC750
25487 || rs6000_cpu_attr
== CPU_PPC7400
25488 || rs6000_cpu_attr
== CPU_PPC7450
25489 || rs6000_cpu_attr
== CPU_PPCE5500
25490 || rs6000_cpu_attr
== CPU_PPCE6500
25491 || rs6000_cpu_attr
== CPU_POWER4
25492 || rs6000_cpu_attr
== CPU_POWER5
25493 || rs6000_cpu_attr
== CPU_POWER7
25494 || rs6000_cpu_attr
== CPU_POWER8
25495 || rs6000_cpu_attr
== CPU_CELL
)
25496 && recog_memoized (dep_insn
)
25497 && (INSN_CODE (dep_insn
) >= 0))
25499 switch (get_attr_type (dep_insn
))
25503 case TYPE_DELAYED_COMPARE
:
25504 case TYPE_IMUL_COMPARE
:
25505 case TYPE_LMUL_COMPARE
:
25506 case TYPE_FPCOMPARE
:
25507 case TYPE_CR_LOGICAL
:
25508 case TYPE_DELAYED_CR
:
25517 case TYPE_STORE_UX
:
25519 case TYPE_FPSTORE_U
:
25520 case TYPE_FPSTORE_UX
:
25521 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25522 && recog_memoized (dep_insn
)
25523 && (INSN_CODE (dep_insn
) >= 0))
25526 if (GET_CODE (PATTERN (insn
)) != SET
)
25527 /* If this happens, we have to extend this to schedule
25528 optimally. Return default for now. */
25531 /* Adjust the cost for the case where the value written
25532 by a fixed point operation is used as the address
25533 gen value on a store. */
25534 switch (get_attr_type (dep_insn
))
25541 if (! store_data_bypass_p (dep_insn
, insn
))
25545 case TYPE_LOAD_EXT
:
25546 case TYPE_LOAD_EXT_U
:
25547 case TYPE_LOAD_EXT_UX
:
25548 case TYPE_VAR_SHIFT_ROTATE
:
25549 case TYPE_VAR_DELAYED_COMPARE
:
25551 if (! store_data_bypass_p (dep_insn
, insn
))
25557 case TYPE_FAST_COMPARE
:
25560 case TYPE_INSERT_WORD
:
25561 case TYPE_INSERT_DWORD
:
25562 case TYPE_FPLOAD_U
:
25563 case TYPE_FPLOAD_UX
:
25565 case TYPE_STORE_UX
:
25566 case TYPE_FPSTORE_U
:
25567 case TYPE_FPSTORE_UX
:
25569 if (! store_data_bypass_p (dep_insn
, insn
))
25577 case TYPE_IMUL_COMPARE
:
25578 case TYPE_LMUL_COMPARE
:
25580 if (! store_data_bypass_p (dep_insn
, insn
))
25586 if (! store_data_bypass_p (dep_insn
, insn
))
25592 if (! store_data_bypass_p (dep_insn
, insn
))
25605 case TYPE_LOAD_EXT
:
25606 case TYPE_LOAD_EXT_U
:
25607 case TYPE_LOAD_EXT_UX
:
25608 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25609 && recog_memoized (dep_insn
)
25610 && (INSN_CODE (dep_insn
) >= 0))
25613 /* Adjust the cost for the case where the value written
25614 by a fixed point instruction is used within the address
25615 gen portion of a subsequent load(u)(x) */
25616 switch (get_attr_type (dep_insn
))
25623 if (set_to_load_agen (dep_insn
, insn
))
25627 case TYPE_LOAD_EXT
:
25628 case TYPE_LOAD_EXT_U
:
25629 case TYPE_LOAD_EXT_UX
:
25630 case TYPE_VAR_SHIFT_ROTATE
:
25631 case TYPE_VAR_DELAYED_COMPARE
:
25633 if (set_to_load_agen (dep_insn
, insn
))
25639 case TYPE_FAST_COMPARE
:
25642 case TYPE_INSERT_WORD
:
25643 case TYPE_INSERT_DWORD
:
25644 case TYPE_FPLOAD_U
:
25645 case TYPE_FPLOAD_UX
:
25647 case TYPE_STORE_UX
:
25648 case TYPE_FPSTORE_U
:
25649 case TYPE_FPSTORE_UX
:
25651 if (set_to_load_agen (dep_insn
, insn
))
25659 case TYPE_IMUL_COMPARE
:
25660 case TYPE_LMUL_COMPARE
:
25662 if (set_to_load_agen (dep_insn
, insn
))
25668 if (set_to_load_agen (dep_insn
, insn
))
25674 if (set_to_load_agen (dep_insn
, insn
))
25685 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25686 && recog_memoized (dep_insn
)
25687 && (INSN_CODE (dep_insn
) >= 0)
25688 && (get_attr_type (dep_insn
) == TYPE_MFFGPR
))
25695 /* Fall out to return default cost. */
25699 case REG_DEP_OUTPUT
:
25700 /* Output dependency; DEP_INSN writes a register that INSN writes some
25702 if ((rs6000_cpu
== PROCESSOR_POWER6
)
25703 && recog_memoized (dep_insn
)
25704 && (INSN_CODE (dep_insn
) >= 0))
25706 attr_type
= get_attr_type (insn
);
25711 if (get_attr_type (dep_insn
) == TYPE_FP
)
25715 if (get_attr_type (dep_insn
) == TYPE_MFFGPR
)
25723 /* Anti dependency; DEP_INSN reads a register that INSN writes some
25728 gcc_unreachable ();
25734 /* Debug version of rs6000_adjust_cost. */
25737 rs6000_debug_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
25739 int ret
= rs6000_adjust_cost (insn
, link
, dep_insn
, cost
);
25745 switch (REG_NOTE_KIND (link
))
25747 default: dep
= "unknown depencency"; break;
25748 case REG_DEP_TRUE
: dep
= "data dependency"; break;
25749 case REG_DEP_OUTPUT
: dep
= "output dependency"; break;
25750 case REG_DEP_ANTI
: dep
= "anti depencency"; break;
25754 "\nrs6000_adjust_cost, final cost = %d, orig cost = %d, "
25755 "%s, insn:\n", ret
, cost
, dep
);
25763 /* The function returns a true if INSN is microcoded.
25764 Return false otherwise. */
25767 is_microcoded_insn (rtx insn
)
25769 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25770 || GET_CODE (PATTERN (insn
)) == USE
25771 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25774 if (rs6000_cpu_attr
== CPU_CELL
)
25775 return get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
;
25777 if (rs6000_sched_groups
25778 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
25780 enum attr_type type
= get_attr_type (insn
);
25781 if (type
== TYPE_LOAD_EXT_U
25782 || type
== TYPE_LOAD_EXT_UX
25783 || type
== TYPE_LOAD_UX
25784 || type
== TYPE_STORE_UX
25785 || type
== TYPE_MFCR
)
25792 /* The function returns true if INSN is cracked into 2 instructions
25793 by the processor (and therefore occupies 2 issue slots). */
25796 is_cracked_insn (rtx insn
)
25798 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25799 || GET_CODE (PATTERN (insn
)) == USE
25800 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25803 if (rs6000_sched_groups
25804 && (rs6000_cpu
== PROCESSOR_POWER4
|| rs6000_cpu
== PROCESSOR_POWER5
))
25806 enum attr_type type
= get_attr_type (insn
);
25807 if (type
== TYPE_LOAD_U
|| type
== TYPE_STORE_U
25808 || type
== TYPE_FPLOAD_U
|| type
== TYPE_FPSTORE_U
25809 || type
== TYPE_FPLOAD_UX
|| type
== TYPE_FPSTORE_UX
25810 || type
== TYPE_LOAD_EXT
|| type
== TYPE_DELAYED_CR
25811 || type
== TYPE_COMPARE
|| type
== TYPE_DELAYED_COMPARE
25812 || type
== TYPE_IMUL_COMPARE
|| type
== TYPE_LMUL_COMPARE
25813 || type
== TYPE_IDIV
|| type
== TYPE_LDIV
25814 || type
== TYPE_INSERT_WORD
)
25821 /* The function returns true if INSN can be issued only from
25822 the branch slot. */
25825 is_branch_slot_insn (rtx insn
)
25827 if (!insn
|| !NONDEBUG_INSN_P (insn
)
25828 || GET_CODE (PATTERN (insn
)) == USE
25829 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
25832 if (rs6000_sched_groups
)
25834 enum attr_type type
= get_attr_type (insn
);
25835 if (type
== TYPE_BRANCH
|| type
== TYPE_JMPREG
)
25843 /* The function returns true if out_inst sets a value that is
25844 used in the address generation computation of in_insn */
25846 set_to_load_agen (rtx out_insn
, rtx in_insn
)
25848 rtx out_set
, in_set
;
25850 /* For performance reasons, only handle the simple case where
25851 both loads are a single_set. */
25852 out_set
= single_set (out_insn
);
25855 in_set
= single_set (in_insn
);
25857 return reg_mentioned_p (SET_DEST (out_set
), SET_SRC (in_set
));
25863 /* Try to determine base/offset/size parts of the given MEM.
25864 Return true if successful, false if all the values couldn't
25867 This function only looks for REG or REG+CONST address forms.
25868 REG+REG address form will return false. */
25871 get_memref_parts (rtx mem
, rtx
*base
, HOST_WIDE_INT
*offset
,
25872 HOST_WIDE_INT
*size
)
25875 if MEM_SIZE_KNOWN_P (mem
)
25876 *size
= MEM_SIZE (mem
);
25880 if (GET_CODE (XEXP (mem
, 0)) == PRE_MODIFY
)
25881 addr_rtx
= XEXP (XEXP (mem
, 0), 1);
25883 addr_rtx
= (XEXP (mem
, 0));
25885 if (GET_CODE (addr_rtx
) == REG
)
25890 else if (GET_CODE (addr_rtx
) == PLUS
25891 && CONST_INT_P (XEXP (addr_rtx
, 1)))
25893 *base
= XEXP (addr_rtx
, 0);
25894 *offset
= INTVAL (XEXP (addr_rtx
, 1));
25902 /* The function returns true if the target storage location of
25903 mem1 is adjacent to the target storage location of mem2 */
25904 /* Return 1 if memory locations are adjacent. */
25907 adjacent_mem_locations (rtx mem1
, rtx mem2
)
25910 HOST_WIDE_INT off1
, size1
, off2
, size2
;
25912 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
25913 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
25914 return ((REGNO (reg1
) == REGNO (reg2
))
25915 && ((off1
+ size1
== off2
)
25916 || (off2
+ size2
== off1
)));
25921 /* This function returns true if it can be determined that the two MEM
25922 locations overlap by at least 1 byte based on base reg/offset/size. */
25925 mem_locations_overlap (rtx mem1
, rtx mem2
)
25928 HOST_WIDE_INT off1
, size1
, off2
, size2
;
25930 if (get_memref_parts (mem1
, ®1
, &off1
, &size1
)
25931 && get_memref_parts (mem2
, ®2
, &off2
, &size2
))
25932 return ((REGNO (reg1
) == REGNO (reg2
))
25933 && (((off1
<= off2
) && (off1
+ size1
> off2
))
25934 || ((off2
<= off1
) && (off2
+ size2
> off1
))));
25939 /* A C statement (sans semicolon) to update the integer scheduling
25940 priority INSN_PRIORITY (INSN). Increase the priority to execute the
25941 INSN earlier, reduce the priority to execute INSN later. Do not
25942 define this macro if you do not need to adjust the scheduling
25943 priorities of insns. */
25946 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
25948 rtx load_mem
, str_mem
;
25949 /* On machines (like the 750) which have asymmetric integer units,
25950 where one integer unit can do multiply and divides and the other
25951 can't, reduce the priority of multiply/divide so it is scheduled
25952 before other integer operations. */
25955 if (! INSN_P (insn
))
25958 if (GET_CODE (PATTERN (insn
)) == USE
)
25961 switch (rs6000_cpu_attr
) {
25963 switch (get_attr_type (insn
))
25970 fprintf (stderr
, "priority was %#x (%d) before adjustment\n",
25971 priority
, priority
);
25972 if (priority
>= 0 && priority
< 0x01000000)
25979 if (insn_must_be_first_in_group (insn
)
25980 && reload_completed
25981 && current_sched_info
->sched_max_insns_priority
25982 && rs6000_sched_restricted_insns_priority
)
25985 /* Prioritize insns that can be dispatched only in the first
25987 if (rs6000_sched_restricted_insns_priority
== 1)
25988 /* Attach highest priority to insn. This means that in
25989 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
25990 precede 'priority' (critical path) considerations. */
25991 return current_sched_info
->sched_max_insns_priority
;
25992 else if (rs6000_sched_restricted_insns_priority
== 2)
25993 /* Increase priority of insn by a minimal amount. This means that in
25994 haifa-sched.c:ready_sort(), only 'priority' (critical path)
25995 considerations precede dispatch-slot restriction considerations. */
25996 return (priority
+ 1);
25999 if (rs6000_cpu
== PROCESSOR_POWER6
26000 && ((load_store_pendulum
== -2 && is_load_insn (insn
, &load_mem
))
26001 || (load_store_pendulum
== 2 && is_store_insn (insn
, &str_mem
))))
26002 /* Attach highest priority to insn if the scheduler has just issued two
26003 stores and this instruction is a load, or two loads and this instruction
26004 is a store. Power6 wants loads and stores scheduled alternately
26006 return current_sched_info
->sched_max_insns_priority
;
26011 /* Return true if the instruction is nonpipelined on the Cell. */
26013 is_nonpipeline_insn (rtx insn
)
26015 enum attr_type type
;
26016 if (!insn
|| !NONDEBUG_INSN_P (insn
)
26017 || GET_CODE (PATTERN (insn
)) == USE
26018 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26021 type
= get_attr_type (insn
);
26022 if (type
== TYPE_IMUL
26023 || type
== TYPE_IMUL2
26024 || type
== TYPE_IMUL3
26025 || type
== TYPE_LMUL
26026 || type
== TYPE_IDIV
26027 || type
== TYPE_LDIV
26028 || type
== TYPE_SDIV
26029 || type
== TYPE_DDIV
26030 || type
== TYPE_SSQRT
26031 || type
== TYPE_DSQRT
26032 || type
== TYPE_MFCR
26033 || type
== TYPE_MFCRF
26034 || type
== TYPE_MFJMPR
)
26042 /* Return how many instructions the machine can issue per cycle. */
26045 rs6000_issue_rate (void)
26047 /* Unless scheduling for register pressure, use issue rate of 1 for
26048 first scheduling pass to decrease degradation. */
26049 if (!reload_completed
&& !flag_sched_pressure
)
26052 switch (rs6000_cpu_attr
) {
26054 case CPU_PPC601
: /* ? */
26064 case CPU_PPCE300C2
:
26065 case CPU_PPCE300C3
:
26066 case CPU_PPCE500MC
:
26067 case CPU_PPCE500MC64
:
26090 /* Return how many instructions to look ahead for better insn
26094 rs6000_use_sched_lookahead (void)
26096 switch (rs6000_cpu_attr
)
26103 return (reload_completed
? 8 : 0);
26110 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
26112 rs6000_use_sched_lookahead_guard (rtx insn
)
26114 if (rs6000_cpu_attr
!= CPU_CELL
)
26117 if (insn
== NULL_RTX
|| !INSN_P (insn
))
26120 if (!reload_completed
26121 || is_nonpipeline_insn (insn
)
26122 || is_microcoded_insn (insn
))
26128 /* Determine if PAT refers to memory. If so, set MEM_REF to the MEM rtx
26129 and return true. */
26132 find_mem_ref (rtx pat
, rtx
*mem_ref
)
26137 /* stack_tie does not produce any real memory traffic. */
26138 if (tie_operand (pat
, VOIDmode
))
26141 if (GET_CODE (pat
) == MEM
)
26147 /* Recursively process the pattern. */
26148 fmt
= GET_RTX_FORMAT (GET_CODE (pat
));
26150 for (i
= GET_RTX_LENGTH (GET_CODE (pat
)) - 1; i
>= 0; i
--)
26154 if (find_mem_ref (XEXP (pat
, i
), mem_ref
))
26157 else if (fmt
[i
] == 'E')
26158 for (j
= XVECLEN (pat
, i
) - 1; j
>= 0; j
--)
26160 if (find_mem_ref (XVECEXP (pat
, i
, j
), mem_ref
))
26168 /* Determine if PAT is a PATTERN of a load insn. */
26171 is_load_insn1 (rtx pat
, rtx
*load_mem
)
26173 if (!pat
|| pat
== NULL_RTX
)
26176 if (GET_CODE (pat
) == SET
)
26177 return find_mem_ref (SET_SRC (pat
), load_mem
);
26179 if (GET_CODE (pat
) == PARALLEL
)
26183 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26184 if (is_load_insn1 (XVECEXP (pat
, 0, i
), load_mem
))
26191 /* Determine if INSN loads from memory. */
26194 is_load_insn (rtx insn
, rtx
*load_mem
)
26196 if (!insn
|| !INSN_P (insn
))
26202 return is_load_insn1 (PATTERN (insn
), load_mem
);
26205 /* Determine if PAT is a PATTERN of a store insn. */
26208 is_store_insn1 (rtx pat
, rtx
*str_mem
)
26210 if (!pat
|| pat
== NULL_RTX
)
26213 if (GET_CODE (pat
) == SET
)
26214 return find_mem_ref (SET_DEST (pat
), str_mem
);
26216 if (GET_CODE (pat
) == PARALLEL
)
26220 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
26221 if (is_store_insn1 (XVECEXP (pat
, 0, i
), str_mem
))
26228 /* Determine if INSN stores to memory. */
26231 is_store_insn (rtx insn
, rtx
*str_mem
)
26233 if (!insn
|| !INSN_P (insn
))
26236 return is_store_insn1 (PATTERN (insn
), str_mem
);
26239 /* Returns whether the dependence between INSN and NEXT is considered
26240 costly by the given target. */
26243 rs6000_is_costly_dependence (dep_t dep
, int cost
, int distance
)
26247 rtx load_mem
, str_mem
;
26249 /* If the flag is not enabled - no dependence is considered costly;
26250 allow all dependent insns in the same group.
26251 This is the most aggressive option. */
26252 if (rs6000_sched_costly_dep
== no_dep_costly
)
26255 /* If the flag is set to 1 - a dependence is always considered costly;
26256 do not allow dependent instructions in the same group.
26257 This is the most conservative option. */
26258 if (rs6000_sched_costly_dep
== all_deps_costly
)
26261 insn
= DEP_PRO (dep
);
26262 next
= DEP_CON (dep
);
26264 if (rs6000_sched_costly_dep
== store_to_load_dep_costly
26265 && is_load_insn (next
, &load_mem
)
26266 && is_store_insn (insn
, &str_mem
))
26267 /* Prevent load after store in the same group. */
26270 if (rs6000_sched_costly_dep
== true_store_to_load_dep_costly
26271 && is_load_insn (next
, &load_mem
)
26272 && is_store_insn (insn
, &str_mem
)
26273 && DEP_TYPE (dep
) == REG_DEP_TRUE
26274 && mem_locations_overlap(str_mem
, load_mem
))
26275 /* Prevent load after store in the same group if it is a true
26279 /* The flag is set to X; dependences with latency >= X are considered costly,
26280 and will not be scheduled in the same group. */
26281 if (rs6000_sched_costly_dep
<= max_dep_latency
26282 && ((cost
- distance
) >= (int)rs6000_sched_costly_dep
))
26288 /* Return the next insn after INSN that is found before TAIL is reached,
26289 skipping any "non-active" insns - insns that will not actually occupy
26290 an issue slot. Return NULL_RTX if such an insn is not found. */
26293 get_next_active_insn (rtx insn
, rtx tail
)
26295 if (insn
== NULL_RTX
|| insn
== tail
)
26300 insn
= NEXT_INSN (insn
);
26301 if (insn
== NULL_RTX
|| insn
== tail
)
26305 || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
26306 || (NONJUMP_INSN_P (insn
)
26307 && GET_CODE (PATTERN (insn
)) != USE
26308 && GET_CODE (PATTERN (insn
)) != CLOBBER
26309 && INSN_CODE (insn
) != CODE_FOR_stack_tie
))
26315 /* We are about to begin issuing insns for this clock cycle. */
26318 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED
, int sched_verbose
,
26319 rtx
*ready ATTRIBUTE_UNUSED
,
26320 int *pn_ready ATTRIBUTE_UNUSED
,
26321 int clock_var ATTRIBUTE_UNUSED
)
26323 int n_ready
= *pn_ready
;
26326 fprintf (dump
, "// rs6000_sched_reorder :\n");
26328 /* Reorder the ready list, if the second to last ready insn
26329 is a nonepipeline insn. */
26330 if (rs6000_cpu_attr
== CPU_CELL
&& n_ready
> 1)
26332 if (is_nonpipeline_insn (ready
[n_ready
- 1])
26333 && (recog_memoized (ready
[n_ready
- 2]) > 0))
26334 /* Simply swap first two insns. */
26336 rtx tmp
= ready
[n_ready
- 1];
26337 ready
[n_ready
- 1] = ready
[n_ready
- 2];
26338 ready
[n_ready
- 2] = tmp
;
26342 if (rs6000_cpu
== PROCESSOR_POWER6
)
26343 load_store_pendulum
= 0;
26345 return rs6000_issue_rate ();
26348 /* Like rs6000_sched_reorder, but called after issuing each insn. */
26351 rs6000_sched_reorder2 (FILE *dump
, int sched_verbose
, rtx
*ready
,
26352 int *pn_ready
, int clock_var ATTRIBUTE_UNUSED
)
26355 fprintf (dump
, "// rs6000_sched_reorder2 :\n");
26357 /* For Power6, we need to handle some special cases to try and keep the
26358 store queue from overflowing and triggering expensive flushes.
26360 This code monitors how load and store instructions are being issued
26361 and skews the ready list one way or the other to increase the likelihood
26362 that a desired instruction is issued at the proper time.
26364 A couple of things are done. First, we maintain a "load_store_pendulum"
26365 to track the current state of load/store issue.
26367 - If the pendulum is at zero, then no loads or stores have been
26368 issued in the current cycle so we do nothing.
26370 - If the pendulum is 1, then a single load has been issued in this
26371 cycle and we attempt to locate another load in the ready list to
26374 - If the pendulum is -2, then two stores have already been
26375 issued in this cycle, so we increase the priority of the first load
26376 in the ready list to increase it's likelihood of being chosen first
26379 - If the pendulum is -1, then a single store has been issued in this
26380 cycle and we attempt to locate another store in the ready list to
26381 issue with it, preferring a store to an adjacent memory location to
26382 facilitate store pairing in the store queue.
26384 - If the pendulum is 2, then two loads have already been
26385 issued in this cycle, so we increase the priority of the first store
26386 in the ready list to increase it's likelihood of being chosen first
26389 - If the pendulum < -2 or > 2, then do nothing.
26391 Note: This code covers the most common scenarios. There exist non
26392 load/store instructions which make use of the LSU and which
26393 would need to be accounted for to strictly model the behavior
26394 of the machine. Those instructions are currently unaccounted
26395 for to help minimize compile time overhead of this code.
26397 if (rs6000_cpu
== PROCESSOR_POWER6
&& last_scheduled_insn
)
26401 rtx tmp
, load_mem
, str_mem
;
26403 if (is_store_insn (last_scheduled_insn
, &str_mem
))
26404 /* Issuing a store, swing the load_store_pendulum to the left */
26405 load_store_pendulum
--;
26406 else if (is_load_insn (last_scheduled_insn
, &load_mem
))
26407 /* Issuing a load, swing the load_store_pendulum to the right */
26408 load_store_pendulum
++;
26410 return cached_can_issue_more
;
26412 /* If the pendulum is balanced, or there is only one instruction on
26413 the ready list, then all is well, so return. */
26414 if ((load_store_pendulum
== 0) || (*pn_ready
<= 1))
26415 return cached_can_issue_more
;
26417 if (load_store_pendulum
== 1)
26419 /* A load has been issued in this cycle. Scan the ready list
26420 for another load to issue with it */
26425 if (is_load_insn (ready
[pos
], &load_mem
))
26427 /* Found a load. Move it to the head of the ready list,
26428 and adjust it's priority so that it is more likely to
26431 for (i
=pos
; i
<*pn_ready
-1; i
++)
26432 ready
[i
] = ready
[i
+ 1];
26433 ready
[*pn_ready
-1] = tmp
;
26435 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26436 INSN_PRIORITY (tmp
)++;
26442 else if (load_store_pendulum
== -2)
26444 /* Two stores have been issued in this cycle. Increase the
26445 priority of the first load in the ready list to favor it for
26446 issuing in the next cycle. */
26451 if (is_load_insn (ready
[pos
], &load_mem
)
26453 && INSN_PRIORITY_KNOWN (ready
[pos
]))
26455 INSN_PRIORITY (ready
[pos
])++;
26457 /* Adjust the pendulum to account for the fact that a load
26458 was found and increased in priority. This is to prevent
26459 increasing the priority of multiple loads */
26460 load_store_pendulum
--;
26467 else if (load_store_pendulum
== -1)
26469 /* A store has been issued in this cycle. Scan the ready list for
26470 another store to issue with it, preferring a store to an adjacent
26472 int first_store_pos
= -1;
26478 if (is_store_insn (ready
[pos
], &str_mem
))
26481 /* Maintain the index of the first store found on the
26483 if (first_store_pos
== -1)
26484 first_store_pos
= pos
;
26486 if (is_store_insn (last_scheduled_insn
, &str_mem2
)
26487 && adjacent_mem_locations (str_mem
, str_mem2
))
26489 /* Found an adjacent store. Move it to the head of the
26490 ready list, and adjust it's priority so that it is
26491 more likely to stay there */
26493 for (i
=pos
; i
<*pn_ready
-1; i
++)
26494 ready
[i
] = ready
[i
+ 1];
26495 ready
[*pn_ready
-1] = tmp
;
26497 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26498 INSN_PRIORITY (tmp
)++;
26500 first_store_pos
= -1;
26508 if (first_store_pos
>= 0)
26510 /* An adjacent store wasn't found, but a non-adjacent store was,
26511 so move the non-adjacent store to the front of the ready
26512 list, and adjust its priority so that it is more likely to
26514 tmp
= ready
[first_store_pos
];
26515 for (i
=first_store_pos
; i
<*pn_ready
-1; i
++)
26516 ready
[i
] = ready
[i
+ 1];
26517 ready
[*pn_ready
-1] = tmp
;
26518 if (!sel_sched_p () && INSN_PRIORITY_KNOWN (tmp
))
26519 INSN_PRIORITY (tmp
)++;
26522 else if (load_store_pendulum
== 2)
26524 /* Two loads have been issued in this cycle. Increase the priority
26525 of the first store in the ready list to favor it for issuing in
26531 if (is_store_insn (ready
[pos
], &str_mem
)
26533 && INSN_PRIORITY_KNOWN (ready
[pos
]))
26535 INSN_PRIORITY (ready
[pos
])++;
26537 /* Adjust the pendulum to account for the fact that a store
26538 was found and increased in priority. This is to prevent
26539 increasing the priority of multiple stores */
26540 load_store_pendulum
++;
26549 return cached_can_issue_more
;
26552 /* Return whether the presence of INSN causes a dispatch group termination
26553 of group WHICH_GROUP.
26555 If WHICH_GROUP == current_group, this function will return true if INSN
26556 causes the termination of the current group (i.e, the dispatch group to
26557 which INSN belongs). This means that INSN will be the last insn in the
26558 group it belongs to.
26560 If WHICH_GROUP == previous_group, this function will return true if INSN
26561 causes the termination of the previous group (i.e, the dispatch group that
26562 precedes the group to which INSN belongs). This means that INSN will be
26563 the first insn in the group it belongs to). */
26566 insn_terminates_group_p (rtx insn
, enum group_termination which_group
)
26573 first
= insn_must_be_first_in_group (insn
);
26574 last
= insn_must_be_last_in_group (insn
);
26579 if (which_group
== current_group
)
26581 else if (which_group
== previous_group
)
26589 insn_must_be_first_in_group (rtx insn
)
26591 enum attr_type type
;
26595 || DEBUG_INSN_P (insn
)
26596 || GET_CODE (PATTERN (insn
)) == USE
26597 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26600 switch (rs6000_cpu
)
26602 case PROCESSOR_POWER5
:
26603 if (is_cracked_insn (insn
))
26605 case PROCESSOR_POWER4
:
26606 if (is_microcoded_insn (insn
))
26609 if (!rs6000_sched_groups
)
26612 type
= get_attr_type (insn
);
26619 case TYPE_DELAYED_CR
:
26620 case TYPE_CR_LOGICAL
:
26634 case PROCESSOR_POWER6
:
26635 type
= get_attr_type (insn
);
26639 case TYPE_INSERT_DWORD
:
26643 case TYPE_VAR_SHIFT_ROTATE
:
26650 case TYPE_INSERT_WORD
:
26651 case TYPE_DELAYED_COMPARE
:
26652 case TYPE_IMUL_COMPARE
:
26653 case TYPE_LMUL_COMPARE
:
26654 case TYPE_FPCOMPARE
:
26665 case TYPE_LOAD_EXT_UX
:
26667 case TYPE_STORE_UX
:
26668 case TYPE_FPLOAD_U
:
26669 case TYPE_FPLOAD_UX
:
26670 case TYPE_FPSTORE_U
:
26671 case TYPE_FPSTORE_UX
:
26677 case PROCESSOR_POWER7
:
26678 type
= get_attr_type (insn
);
26682 case TYPE_CR_LOGICAL
:
26689 case TYPE_DELAYED_COMPARE
:
26690 case TYPE_VAR_DELAYED_COMPARE
:
26696 case TYPE_LOAD_EXT
:
26697 case TYPE_LOAD_EXT_U
:
26698 case TYPE_LOAD_EXT_UX
:
26700 case TYPE_STORE_UX
:
26701 case TYPE_FPLOAD_U
:
26702 case TYPE_FPLOAD_UX
:
26703 case TYPE_FPSTORE_U
:
26704 case TYPE_FPSTORE_UX
:
26712 case PROCESSOR_POWER8
:
26713 type
= get_attr_type (insn
);
26717 case TYPE_CR_LOGICAL
:
26718 case TYPE_DELAYED_CR
:
26723 case TYPE_DELAYED_COMPARE
:
26724 case TYPE_VAR_DELAYED_COMPARE
:
26725 case TYPE_IMUL_COMPARE
:
26726 case TYPE_LMUL_COMPARE
:
26733 case TYPE_LOAD_EXT
:
26734 case TYPE_LOAD_EXT_U
:
26735 case TYPE_LOAD_EXT_UX
:
26736 case TYPE_STORE_UX
:
26737 case TYPE_VECSTORE
:
26753 insn_must_be_last_in_group (rtx insn
)
26755 enum attr_type type
;
26759 || DEBUG_INSN_P (insn
)
26760 || GET_CODE (PATTERN (insn
)) == USE
26761 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
26764 switch (rs6000_cpu
) {
26765 case PROCESSOR_POWER4
:
26766 case PROCESSOR_POWER5
:
26767 if (is_microcoded_insn (insn
))
26770 if (is_branch_slot_insn (insn
))
26774 case PROCESSOR_POWER6
:
26775 type
= get_attr_type (insn
);
26782 case TYPE_VAR_SHIFT_ROTATE
:
26789 case TYPE_DELAYED_COMPARE
:
26790 case TYPE_IMUL_COMPARE
:
26791 case TYPE_LMUL_COMPARE
:
26792 case TYPE_FPCOMPARE
:
26806 case PROCESSOR_POWER7
:
26807 type
= get_attr_type (insn
);
26815 case TYPE_LOAD_EXT_U
:
26816 case TYPE_LOAD_EXT_UX
:
26817 case TYPE_STORE_UX
:
26823 case PROCESSOR_POWER8
:
26824 type
= get_attr_type (insn
);
26834 case TYPE_LOAD_EXT_U
:
26835 case TYPE_LOAD_EXT_UX
:
26836 case TYPE_STORE_UX
:
26849 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
26850 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
26853 is_costly_group (rtx
*group_insns
, rtx next_insn
)
26856 int issue_rate
= rs6000_issue_rate ();
26858 for (i
= 0; i
< issue_rate
; i
++)
26860 sd_iterator_def sd_it
;
26862 rtx insn
= group_insns
[i
];
26867 FOR_EACH_DEP (insn
, SD_LIST_RES_FORW
, sd_it
, dep
)
26869 rtx next
= DEP_CON (dep
);
26871 if (next
== next_insn
26872 && rs6000_is_costly_dependence (dep
, dep_cost (dep
), 0))
26880 /* Utility of the function redefine_groups.
26881 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
26882 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
26883 to keep it "far" (in a separate group) from GROUP_INSNS, following
26884 one of the following schemes, depending on the value of the flag
26885 -minsert_sched_nops = X:
26886 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
26887 in order to force NEXT_INSN into a separate group.
26888 (2) X < sched_finish_regroup_exact: insert exactly X nops.
26889 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
26890 insertion (has a group just ended, how many vacant issue slots remain in the
26891 last group, and how many dispatch groups were encountered so far). */
26894 force_new_group (int sched_verbose
, FILE *dump
, rtx
*group_insns
,
26895 rtx next_insn
, bool *group_end
, int can_issue_more
,
26900 int issue_rate
= rs6000_issue_rate ();
26901 bool end
= *group_end
;
26904 if (next_insn
== NULL_RTX
|| DEBUG_INSN_P (next_insn
))
26905 return can_issue_more
;
26907 if (rs6000_sched_insert_nops
> sched_finish_regroup_exact
)
26908 return can_issue_more
;
26910 force
= is_costly_group (group_insns
, next_insn
);
26912 return can_issue_more
;
26914 if (sched_verbose
> 6)
26915 fprintf (dump
,"force: group count = %d, can_issue_more = %d\n",
26916 *group_count
,can_issue_more
);
26918 if (rs6000_sched_insert_nops
== sched_finish_regroup_exact
)
26921 can_issue_more
= 0;
26923 /* Since only a branch can be issued in the last issue_slot, it is
26924 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
26925 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
26926 in this case the last nop will start a new group and the branch
26927 will be forced to the new group. */
26928 if (can_issue_more
&& !is_branch_slot_insn (next_insn
))
26931 /* Do we have a special group ending nop? */
26932 if (rs6000_cpu_attr
== CPU_POWER6
|| rs6000_cpu_attr
== CPU_POWER7
26933 || rs6000_cpu_attr
== CPU_POWER8
)
26935 nop
= gen_group_ending_nop ();
26936 emit_insn_before (nop
, next_insn
);
26937 can_issue_more
= 0;
26940 while (can_issue_more
> 0)
26943 emit_insn_before (nop
, next_insn
);
26951 if (rs6000_sched_insert_nops
< sched_finish_regroup_exact
)
26953 int n_nops
= rs6000_sched_insert_nops
;
26955 /* Nops can't be issued from the branch slot, so the effective
26956 issue_rate for nops is 'issue_rate - 1'. */
26957 if (can_issue_more
== 0)
26958 can_issue_more
= issue_rate
;
26960 if (can_issue_more
== 0)
26962 can_issue_more
= issue_rate
- 1;
26965 for (i
= 0; i
< issue_rate
; i
++)
26967 group_insns
[i
] = 0;
26974 emit_insn_before (nop
, next_insn
);
26975 if (can_issue_more
== issue_rate
- 1) /* new group begins */
26978 if (can_issue_more
== 0)
26980 can_issue_more
= issue_rate
- 1;
26983 for (i
= 0; i
< issue_rate
; i
++)
26985 group_insns
[i
] = 0;
26991 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
26994 /* Is next_insn going to start a new group? */
26997 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
26998 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
26999 || (can_issue_more
< issue_rate
&&
27000 insn_terminates_group_p (next_insn
, previous_group
)));
27001 if (*group_end
&& end
)
27004 if (sched_verbose
> 6)
27005 fprintf (dump
, "done force: group count = %d, can_issue_more = %d\n",
27006 *group_count
, can_issue_more
);
27007 return can_issue_more
;
27010 return can_issue_more
;
27013 /* This function tries to synch the dispatch groups that the compiler "sees"
27014 with the dispatch groups that the processor dispatcher is expected to
27015 form in practice. It tries to achieve this synchronization by forcing the
27016 estimated processor grouping on the compiler (as opposed to the function
27017 'pad_goups' which tries to force the scheduler's grouping on the processor).
27019 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
27020 examines the (estimated) dispatch groups that will be formed by the processor
27021 dispatcher. It marks these group boundaries to reflect the estimated
27022 processor grouping, overriding the grouping that the scheduler had marked.
27023 Depending on the value of the flag '-minsert-sched-nops' this function can
27024 force certain insns into separate groups or force a certain distance between
27025 them by inserting nops, for example, if there exists a "costly dependence"
27028 The function estimates the group boundaries that the processor will form as
27029 follows: It keeps track of how many vacant issue slots are available after
27030 each insn. A subsequent insn will start a new group if one of the following
27032 - no more vacant issue slots remain in the current dispatch group.
27033 - only the last issue slot, which is the branch slot, is vacant, but the next
27034 insn is not a branch.
27035 - only the last 2 or less issue slots, including the branch slot, are vacant,
27036 which means that a cracked insn (which occupies two issue slots) can't be
27037 issued in this group.
27038 - less than 'issue_rate' slots are vacant, and the next insn always needs to
27039 start a new group. */
27042 redefine_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27044 rtx insn
, next_insn
;
27046 int can_issue_more
;
27049 int group_count
= 0;
27053 issue_rate
= rs6000_issue_rate ();
27054 group_insns
= XALLOCAVEC (rtx
, issue_rate
);
27055 for (i
= 0; i
< issue_rate
; i
++)
27057 group_insns
[i
] = 0;
27059 can_issue_more
= issue_rate
;
27061 insn
= get_next_active_insn (prev_head_insn
, tail
);
27064 while (insn
!= NULL_RTX
)
27066 slot
= (issue_rate
- can_issue_more
);
27067 group_insns
[slot
] = insn
;
27069 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27070 if (insn_terminates_group_p (insn
, current_group
))
27071 can_issue_more
= 0;
27073 next_insn
= get_next_active_insn (insn
, tail
);
27074 if (next_insn
== NULL_RTX
)
27075 return group_count
+ 1;
27077 /* Is next_insn going to start a new group? */
27079 = (can_issue_more
== 0
27080 || (can_issue_more
== 1 && !is_branch_slot_insn (next_insn
))
27081 || (can_issue_more
<= 2 && is_cracked_insn (next_insn
))
27082 || (can_issue_more
< issue_rate
&&
27083 insn_terminates_group_p (next_insn
, previous_group
)));
27085 can_issue_more
= force_new_group (sched_verbose
, dump
, group_insns
,
27086 next_insn
, &group_end
, can_issue_more
,
27092 can_issue_more
= 0;
27093 for (i
= 0; i
< issue_rate
; i
++)
27095 group_insns
[i
] = 0;
27099 if (GET_MODE (next_insn
) == TImode
&& can_issue_more
)
27100 PUT_MODE (next_insn
, VOIDmode
);
27101 else if (!can_issue_more
&& GET_MODE (next_insn
) != TImode
)
27102 PUT_MODE (next_insn
, TImode
);
27105 if (can_issue_more
== 0)
27106 can_issue_more
= issue_rate
;
27109 return group_count
;
27112 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
27113 dispatch group boundaries that the scheduler had marked. Pad with nops
27114 any dispatch groups which have vacant issue slots, in order to force the
27115 scheduler's grouping on the processor dispatcher. The function
27116 returns the number of dispatch groups found. */
27119 pad_groups (FILE *dump
, int sched_verbose
, rtx prev_head_insn
, rtx tail
)
27121 rtx insn
, next_insn
;
27124 int can_issue_more
;
27126 int group_count
= 0;
27128 /* Initialize issue_rate. */
27129 issue_rate
= rs6000_issue_rate ();
27130 can_issue_more
= issue_rate
;
27132 insn
= get_next_active_insn (prev_head_insn
, tail
);
27133 next_insn
= get_next_active_insn (insn
, tail
);
27135 while (insn
!= NULL_RTX
)
27138 rs6000_variable_issue (dump
, sched_verbose
, insn
, can_issue_more
);
27140 group_end
= (next_insn
== NULL_RTX
|| GET_MODE (next_insn
) == TImode
);
27142 if (next_insn
== NULL_RTX
)
27147 /* If the scheduler had marked group termination at this location
27148 (between insn and next_insn), and neither insn nor next_insn will
27149 force group termination, pad the group with nops to force group
27152 && (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27153 && !insn_terminates_group_p (insn
, current_group
)
27154 && !insn_terminates_group_p (next_insn
, previous_group
))
27156 if (!is_branch_slot_insn (next_insn
))
27159 while (can_issue_more
)
27162 emit_insn_before (nop
, next_insn
);
27167 can_issue_more
= issue_rate
;
27172 next_insn
= get_next_active_insn (insn
, tail
);
27175 return group_count
;
27178 /* We're beginning a new block. Initialize data structures as necessary. */
27181 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
27182 int sched_verbose ATTRIBUTE_UNUSED
,
27183 int max_ready ATTRIBUTE_UNUSED
)
27185 last_scheduled_insn
= NULL_RTX
;
27186 load_store_pendulum
= 0;
27189 /* The following function is called at the end of scheduling BB.
27190 After reload, it inserts nops at insn group bundling. */
27193 rs6000_sched_finish (FILE *dump
, int sched_verbose
)
27198 fprintf (dump
, "=== Finishing schedule.\n");
27200 if (reload_completed
&& rs6000_sched_groups
)
27202 /* Do not run sched_finish hook when selective scheduling enabled. */
27203 if (sel_sched_p ())
27206 if (rs6000_sched_insert_nops
== sched_finish_none
)
27209 if (rs6000_sched_insert_nops
== sched_finish_pad_groups
)
27210 n_groups
= pad_groups (dump
, sched_verbose
,
27211 current_sched_info
->prev_head
,
27212 current_sched_info
->next_tail
);
27214 n_groups
= redefine_groups (dump
, sched_verbose
,
27215 current_sched_info
->prev_head
,
27216 current_sched_info
->next_tail
);
27218 if (sched_verbose
>= 6)
27220 fprintf (dump
, "ngroups = %d\n", n_groups
);
27221 print_rtl (dump
, current_sched_info
->prev_head
);
27222 fprintf (dump
, "Done finish_sched\n");
27227 struct _rs6000_sched_context
27229 short cached_can_issue_more
;
27230 rtx last_scheduled_insn
;
27231 int load_store_pendulum
;
27234 typedef struct _rs6000_sched_context rs6000_sched_context_def
;
27235 typedef rs6000_sched_context_def
*rs6000_sched_context_t
;
27237 /* Allocate store for new scheduling context. */
27239 rs6000_alloc_sched_context (void)
27241 return xmalloc (sizeof (rs6000_sched_context_def
));
27244 /* If CLEAN_P is true then initializes _SC with clean data,
27245 and from the global context otherwise. */
27247 rs6000_init_sched_context (void *_sc
, bool clean_p
)
27249 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27253 sc
->cached_can_issue_more
= 0;
27254 sc
->last_scheduled_insn
= NULL_RTX
;
27255 sc
->load_store_pendulum
= 0;
27259 sc
->cached_can_issue_more
= cached_can_issue_more
;
27260 sc
->last_scheduled_insn
= last_scheduled_insn
;
27261 sc
->load_store_pendulum
= load_store_pendulum
;
27265 /* Sets the global scheduling context to the one pointed to by _SC. */
27267 rs6000_set_sched_context (void *_sc
)
27269 rs6000_sched_context_t sc
= (rs6000_sched_context_t
) _sc
;
27271 gcc_assert (sc
!= NULL
);
27273 cached_can_issue_more
= sc
->cached_can_issue_more
;
27274 last_scheduled_insn
= sc
->last_scheduled_insn
;
27275 load_store_pendulum
= sc
->load_store_pendulum
;
27280 rs6000_free_sched_context (void *_sc
)
27282 gcc_assert (_sc
!= NULL
);
27288 /* Length in units of the trampoline for entering a nested function. */
27291 rs6000_trampoline_size (void)
27295 switch (DEFAULT_ABI
)
27298 gcc_unreachable ();
27301 ret
= (TARGET_32BIT
) ? 12 : 24;
27305 gcc_assert (!TARGET_32BIT
);
27311 ret
= (TARGET_32BIT
) ? 40 : 48;
27318 /* Emit RTL insns to initialize the variable parts of a trampoline.
27319 FNADDR is an RTX for the address of the function's pure code.
27320 CXT is an RTX for the static chain value for the function. */
27323 rs6000_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
27325 int regsize
= (TARGET_32BIT
) ? 4 : 8;
27326 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
27327 rtx ctx_reg
= force_reg (Pmode
, cxt
);
27328 rtx addr
= force_reg (Pmode
, XEXP (m_tramp
, 0));
27330 switch (DEFAULT_ABI
)
27333 gcc_unreachable ();
27335 /* Under AIX, just build the 3 word function descriptor */
27338 rtx fnmem
, fn_reg
, toc_reg
;
27340 if (!TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
27341 error ("You cannot take the address of a nested function if you use "
27342 "the -mno-pointers-to-nested-functions option.");
27344 fnmem
= gen_const_mem (Pmode
, force_reg (Pmode
, fnaddr
));
27345 fn_reg
= gen_reg_rtx (Pmode
);
27346 toc_reg
= gen_reg_rtx (Pmode
);
27348 /* Macro to shorten the code expansions below. */
27349 # define MEM_PLUS(MEM, OFFSET) adjust_address (MEM, Pmode, OFFSET)
27351 m_tramp
= replace_equiv_address (m_tramp
, addr
);
27353 emit_move_insn (fn_reg
, MEM_PLUS (fnmem
, 0));
27354 emit_move_insn (toc_reg
, MEM_PLUS (fnmem
, regsize
));
27355 emit_move_insn (MEM_PLUS (m_tramp
, 0), fn_reg
);
27356 emit_move_insn (MEM_PLUS (m_tramp
, regsize
), toc_reg
);
27357 emit_move_insn (MEM_PLUS (m_tramp
, 2*regsize
), ctx_reg
);
27363 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
27367 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__trampoline_setup"),
27368 LCT_NORMAL
, VOIDmode
, 4,
27370 GEN_INT (rs6000_trampoline_size ()), SImode
,
27378 /* Returns TRUE iff the target attribute indicated by ATTR_ID takes a plain
27379 identifier as an argument, so the front end shouldn't look it up. */
27382 rs6000_attribute_takes_identifier_p (const_tree attr_id
)
27384 return is_attribute_p ("altivec", attr_id
);
27387 /* Handle the "altivec" attribute. The attribute may have
27388 arguments as follows:
27390 __attribute__((altivec(vector__)))
27391 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
27392 __attribute__((altivec(bool__))) (always followed by 'unsigned')
27394 and may appear more than once (e.g., 'vector bool char') in a
27395 given declaration. */
27398 rs6000_handle_altivec_attribute (tree
*node
,
27399 tree name ATTRIBUTE_UNUSED
,
27401 int flags ATTRIBUTE_UNUSED
,
27402 bool *no_add_attrs
)
27404 tree type
= *node
, result
= NULL_TREE
;
27405 enum machine_mode mode
;
27408 = ((args
&& TREE_CODE (args
) == TREE_LIST
&& TREE_VALUE (args
)
27409 && TREE_CODE (TREE_VALUE (args
)) == IDENTIFIER_NODE
)
27410 ? *IDENTIFIER_POINTER (TREE_VALUE (args
))
27413 while (POINTER_TYPE_P (type
)
27414 || TREE_CODE (type
) == FUNCTION_TYPE
27415 || TREE_CODE (type
) == METHOD_TYPE
27416 || TREE_CODE (type
) == ARRAY_TYPE
)
27417 type
= TREE_TYPE (type
);
27419 mode
= TYPE_MODE (type
);
27421 /* Check for invalid AltiVec type qualifiers. */
27422 if (type
== long_double_type_node
)
27423 error ("use of %<long double%> in AltiVec types is invalid");
27424 else if (type
== boolean_type_node
)
27425 error ("use of boolean types in AltiVec types is invalid");
27426 else if (TREE_CODE (type
) == COMPLEX_TYPE
)
27427 error ("use of %<complex%> in AltiVec types is invalid");
27428 else if (DECIMAL_FLOAT_MODE_P (mode
))
27429 error ("use of decimal floating point types in AltiVec types is invalid");
27430 else if (!TARGET_VSX
)
27432 if (type
== long_unsigned_type_node
|| type
== long_integer_type_node
)
27435 error ("use of %<long%> in AltiVec types is invalid for "
27436 "64-bit code without -mvsx");
27437 else if (rs6000_warn_altivec_long
)
27438 warning (0, "use of %<long%> in AltiVec types is deprecated; "
27441 else if (type
== long_long_unsigned_type_node
27442 || type
== long_long_integer_type_node
)
27443 error ("use of %<long long%> in AltiVec types is invalid without "
27445 else if (type
== double_type_node
)
27446 error ("use of %<double%> in AltiVec types is invalid without -mvsx");
27449 switch (altivec_type
)
27452 unsigned_p
= TYPE_UNSIGNED (type
);
27456 result
= (unsigned_p
? unsigned_V2DI_type_node
: V2DI_type_node
);
27459 result
= (unsigned_p
? unsigned_V4SI_type_node
: V4SI_type_node
);
27462 result
= (unsigned_p
? unsigned_V8HI_type_node
: V8HI_type_node
);
27465 result
= (unsigned_p
? unsigned_V16QI_type_node
: V16QI_type_node
);
27467 case SFmode
: result
= V4SF_type_node
; break;
27468 case DFmode
: result
= V2DF_type_node
; break;
27469 /* If the user says 'vector int bool', we may be handed the 'bool'
27470 attribute _before_ the 'vector' attribute, and so select the
27471 proper type in the 'b' case below. */
27472 case V4SImode
: case V8HImode
: case V16QImode
: case V4SFmode
:
27473 case V2DImode
: case V2DFmode
:
27481 case DImode
: case V2DImode
: result
= bool_V2DI_type_node
; break;
27482 case SImode
: case V4SImode
: result
= bool_V4SI_type_node
; break;
27483 case HImode
: case V8HImode
: result
= bool_V8HI_type_node
; break;
27484 case QImode
: case V16QImode
: result
= bool_V16QI_type_node
;
27491 case V8HImode
: result
= pixel_V8HI_type_node
;
27497 /* Propagate qualifiers attached to the element type
27498 onto the vector type. */
27499 if (result
&& result
!= type
&& TYPE_QUALS (type
))
27500 result
= build_qualified_type (result
, TYPE_QUALS (type
));
27502 *no_add_attrs
= true; /* No need to hang on to the attribute. */
27505 *node
= lang_hooks
.types
.reconstruct_complex_type (*node
, result
);
27510 /* AltiVec defines four built-in scalar types that serve as vector
27511 elements; we must teach the compiler how to mangle them. */
27513 static const char *
27514 rs6000_mangle_type (const_tree type
)
27516 type
= TYPE_MAIN_VARIANT (type
);
27518 if (TREE_CODE (type
) != VOID_TYPE
&& TREE_CODE (type
) != BOOLEAN_TYPE
27519 && TREE_CODE (type
) != INTEGER_TYPE
&& TREE_CODE (type
) != REAL_TYPE
)
27522 if (type
== bool_char_type_node
) return "U6__boolc";
27523 if (type
== bool_short_type_node
) return "U6__bools";
27524 if (type
== pixel_type_node
) return "u7__pixel";
27525 if (type
== bool_int_type_node
) return "U6__booli";
27526 if (type
== bool_long_type_node
) return "U6__booll";
27528 /* Mangle IBM extended float long double as `g' (__float128) on
27529 powerpc*-linux where long-double-64 previously was the default. */
27530 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
27532 && TARGET_LONG_DOUBLE_128
27533 && !TARGET_IEEEQUAD
)
27536 /* For all other types, use normal C++ mangling. */
27540 /* Handle a "longcall" or "shortcall" attribute; arguments as in
27541 struct attribute_spec.handler. */
27544 rs6000_handle_longcall_attribute (tree
*node
, tree name
,
27545 tree args ATTRIBUTE_UNUSED
,
27546 int flags ATTRIBUTE_UNUSED
,
27547 bool *no_add_attrs
)
27549 if (TREE_CODE (*node
) != FUNCTION_TYPE
27550 && TREE_CODE (*node
) != FIELD_DECL
27551 && TREE_CODE (*node
) != TYPE_DECL
)
27553 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
27555 *no_add_attrs
= true;
27561 /* Set longcall attributes on all functions declared when
27562 rs6000_default_long_calls is true. */
27564 rs6000_set_default_type_attributes (tree type
)
27566 if (rs6000_default_long_calls
27567 && (TREE_CODE (type
) == FUNCTION_TYPE
27568 || TREE_CODE (type
) == METHOD_TYPE
))
27569 TYPE_ATTRIBUTES (type
) = tree_cons (get_identifier ("longcall"),
27571 TYPE_ATTRIBUTES (type
));
27574 darwin_set_default_type_attributes (type
);
27578 /* Return a reference suitable for calling a function with the
27579 longcall attribute. */
27582 rs6000_longcall_ref (rtx call_ref
)
27584 const char *call_name
;
27587 if (GET_CODE (call_ref
) != SYMBOL_REF
)
27590 /* System V adds '.' to the internal name, so skip them. */
27591 call_name
= XSTR (call_ref
, 0);
27592 if (*call_name
== '.')
27594 while (*call_name
== '.')
27597 node
= get_identifier (call_name
);
27598 call_ref
= gen_rtx_SYMBOL_REF (VOIDmode
, IDENTIFIER_POINTER (node
));
27601 return force_reg (Pmode
, call_ref
);
27604 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
27605 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
27608 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
27609 struct attribute_spec.handler. */
27611 rs6000_handle_struct_attribute (tree
*node
, tree name
,
27612 tree args ATTRIBUTE_UNUSED
,
27613 int flags ATTRIBUTE_UNUSED
, bool *no_add_attrs
)
27616 if (DECL_P (*node
))
27618 if (TREE_CODE (*node
) == TYPE_DECL
)
27619 type
= &TREE_TYPE (*node
);
27624 if (!(type
&& (TREE_CODE (*type
) == RECORD_TYPE
27625 || TREE_CODE (*type
) == UNION_TYPE
)))
27627 warning (OPT_Wattributes
, "%qE attribute ignored", name
);
27628 *no_add_attrs
= true;
27631 else if ((is_attribute_p ("ms_struct", name
)
27632 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type
)))
27633 || ((is_attribute_p ("gcc_struct", name
)
27634 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type
)))))
27636 warning (OPT_Wattributes
, "%qE incompatible attribute ignored",
27638 *no_add_attrs
= true;
27645 rs6000_ms_bitfield_layout_p (const_tree record_type
)
27647 return (TARGET_USE_MS_BITFIELD_LAYOUT
&&
27648 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type
)))
27649 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type
));
27652 #ifdef USING_ELFOS_H
27654 /* A get_unnamed_section callback, used for switching to toc_section. */
27657 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
27659 if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27660 && TARGET_MINIMAL_TOC
27661 && !TARGET_RELOCATABLE
)
27663 if (!toc_initialized
)
27665 toc_initialized
= 1;
27666 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
27667 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "LCTOC", 0);
27668 fprintf (asm_out_file
, "\t.tc ");
27669 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1[TC],");
27670 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27671 fprintf (asm_out_file
, "\n");
27673 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27674 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27675 fprintf (asm_out_file
, " = .+32768\n");
27678 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27680 else if ((DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
27681 && !TARGET_RELOCATABLE
)
27682 fprintf (asm_out_file
, "%s\n", TOC_SECTION_ASM_OP
);
27685 fprintf (asm_out_file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
27686 if (!toc_initialized
)
27688 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file
, "LCTOC1");
27689 fprintf (asm_out_file
, " = .+32768\n");
27690 toc_initialized
= 1;
27695 /* Implement TARGET_ASM_INIT_SECTIONS. */
27698 rs6000_elf_asm_init_sections (void)
27701 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op
, NULL
);
27704 = get_unnamed_section (SECTION_WRITE
, output_section_asm_op
,
27705 SDATA2_SECTION_ASM_OP
);
27708 /* Implement TARGET_SELECT_RTX_SECTION. */
27711 rs6000_elf_select_rtx_section (enum machine_mode mode
, rtx x
,
27712 unsigned HOST_WIDE_INT align
)
27714 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
27715 return toc_section
;
27717 return default_elf_select_rtx_section (mode
, x
, align
);
27720 /* For a SYMBOL_REF, set generic flags and then perform some
27721 target-specific processing.
27723 When the AIX ABI is requested on a non-AIX system, replace the
27724 function name with the real name (with a leading .) rather than the
27725 function descriptor name. This saves a lot of overriding code to
27726 read the prefixes. */
27728 static void rs6000_elf_encode_section_info (tree
, rtx
, int) ATTRIBUTE_UNUSED
;
27730 rs6000_elf_encode_section_info (tree decl
, rtx rtl
, int first
)
27732 default_encode_section_info (decl
, rtl
, first
);
27735 && TREE_CODE (decl
) == FUNCTION_DECL
27737 && DEFAULT_ABI
== ABI_AIX
)
27739 rtx sym_ref
= XEXP (rtl
, 0);
27740 size_t len
= strlen (XSTR (sym_ref
, 0));
27741 char *str
= XALLOCAVEC (char, len
+ 2);
27743 memcpy (str
+ 1, XSTR (sym_ref
, 0), len
+ 1);
27744 XSTR (sym_ref
, 0) = ggc_alloc_string (str
, len
+ 1);
27749 compare_section_name (const char *section
, const char *templ
)
27753 len
= strlen (templ
);
27754 return (strncmp (section
, templ
, len
) == 0
27755 && (section
[len
] == 0 || section
[len
] == '.'));
27759 rs6000_elf_in_small_data_p (const_tree decl
)
27761 if (rs6000_sdata
== SDATA_NONE
)
27764 /* We want to merge strings, so we never consider them small data. */
27765 if (TREE_CODE (decl
) == STRING_CST
)
27768 /* Functions are never in the small data area. */
27769 if (TREE_CODE (decl
) == FUNCTION_DECL
)
27772 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_SECTION_NAME (decl
))
27774 const char *section
= TREE_STRING_POINTER (DECL_SECTION_NAME (decl
));
27775 if (compare_section_name (section
, ".sdata")
27776 || compare_section_name (section
, ".sdata2")
27777 || compare_section_name (section
, ".gnu.linkonce.s")
27778 || compare_section_name (section
, ".sbss")
27779 || compare_section_name (section
, ".sbss2")
27780 || compare_section_name (section
, ".gnu.linkonce.sb")
27781 || strcmp (section
, ".PPC.EMB.sdata0") == 0
27782 || strcmp (section
, ".PPC.EMB.sbss0") == 0)
27787 HOST_WIDE_INT size
= int_size_in_bytes (TREE_TYPE (decl
));
27790 && size
<= g_switch_value
27791 /* If it's not public, and we're not going to reference it there,
27792 there's no need to put it in the small data section. */
27793 && (rs6000_sdata
!= SDATA_DATA
|| TREE_PUBLIC (decl
)))
27800 #endif /* USING_ELFOS_H */
27802 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
27805 rs6000_use_blocks_for_constant_p (enum machine_mode mode
, const_rtx x
)
27807 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
);
27810 /* Do not place thread-local symbols refs in the object blocks. */
27813 rs6000_use_blocks_for_decl_p (const_tree decl
)
27815 return !DECL_THREAD_LOCAL_P (decl
);
27818 /* Return a REG that occurs in ADDR with coefficient 1.
27819 ADDR can be effectively incremented by incrementing REG.
27821 r0 is special and we must not select it as an address
27822 register by this routine since our caller will try to
27823 increment the returned register via an "la" instruction. */
27826 find_addr_reg (rtx addr
)
27828 while (GET_CODE (addr
) == PLUS
)
27830 if (GET_CODE (XEXP (addr
, 0)) == REG
27831 && REGNO (XEXP (addr
, 0)) != 0)
27832 addr
= XEXP (addr
, 0);
27833 else if (GET_CODE (XEXP (addr
, 1)) == REG
27834 && REGNO (XEXP (addr
, 1)) != 0)
27835 addr
= XEXP (addr
, 1);
27836 else if (CONSTANT_P (XEXP (addr
, 0)))
27837 addr
= XEXP (addr
, 1);
27838 else if (CONSTANT_P (XEXP (addr
, 1)))
27839 addr
= XEXP (addr
, 0);
27841 gcc_unreachable ();
27843 gcc_assert (GET_CODE (addr
) == REG
&& REGNO (addr
) != 0);
27848 rs6000_fatal_bad_address (rtx op
)
27850 fatal_insn ("bad address", op
);
27855 typedef struct branch_island_d
{
27856 tree function_name
;
27862 static vec
<branch_island
, va_gc
> *branch_islands
;
27864 /* Remember to generate a branch island for far calls to the given
27868 add_compiler_branch_island (tree label_name
, tree function_name
,
27871 branch_island bi
= {function_name
, label_name
, line_number
};
27872 vec_safe_push (branch_islands
, bi
);
27875 /* Generate far-jump branch islands for everything recorded in
27876 branch_islands. Invoked immediately after the last instruction of
27877 the epilogue has been emitted; the branch islands must be appended
27878 to, and contiguous with, the function body. Mach-O stubs are
27879 generated in machopic_output_stub(). */
27882 macho_branch_islands (void)
27886 while (!vec_safe_is_empty (branch_islands
))
27888 branch_island
*bi
= &branch_islands
->last ();
27889 const char *label
= IDENTIFIER_POINTER (bi
->label_name
);
27890 const char *name
= IDENTIFIER_POINTER (bi
->function_name
);
27891 char name_buf
[512];
27892 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
27893 if (name
[0] == '*' || name
[0] == '&')
27894 strcpy (name_buf
, name
+1);
27898 strcpy (name_buf
+1, name
);
27900 strcpy (tmp_buf
, "\n");
27901 strcat (tmp_buf
, label
);
27902 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
27903 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
27904 dbxout_stabd (N_SLINE
, bi
->line_number
);
27905 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
27908 if (TARGET_LINK_STACK
)
27911 get_ppc476_thunk_name (name
);
27912 strcat (tmp_buf
, ":\n\tmflr r0\n\tbl ");
27913 strcat (tmp_buf
, name
);
27914 strcat (tmp_buf
, "\n");
27915 strcat (tmp_buf
, label
);
27916 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
27920 strcat (tmp_buf
, ":\n\tmflr r0\n\tbcl 20,31,");
27921 strcat (tmp_buf
, label
);
27922 strcat (tmp_buf
, "_pic\n");
27923 strcat (tmp_buf
, label
);
27924 strcat (tmp_buf
, "_pic:\n\tmflr r11\n");
27927 strcat (tmp_buf
, "\taddis r11,r11,ha16(");
27928 strcat (tmp_buf
, name_buf
);
27929 strcat (tmp_buf
, " - ");
27930 strcat (tmp_buf
, label
);
27931 strcat (tmp_buf
, "_pic)\n");
27933 strcat (tmp_buf
, "\tmtlr r0\n");
27935 strcat (tmp_buf
, "\taddi r12,r11,lo16(");
27936 strcat (tmp_buf
, name_buf
);
27937 strcat (tmp_buf
, " - ");
27938 strcat (tmp_buf
, label
);
27939 strcat (tmp_buf
, "_pic)\n");
27941 strcat (tmp_buf
, "\tmtctr r12\n\tbctr\n");
27945 strcat (tmp_buf
, ":\nlis r12,hi16(");
27946 strcat (tmp_buf
, name_buf
);
27947 strcat (tmp_buf
, ")\n\tori r12,r12,lo16(");
27948 strcat (tmp_buf
, name_buf
);
27949 strcat (tmp_buf
, ")\n\tmtctr r12\n\tbctr");
27951 output_asm_insn (tmp_buf
, 0);
27952 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
27953 if (write_symbols
== DBX_DEBUG
|| write_symbols
== XCOFF_DEBUG
)
27954 dbxout_stabd (N_SLINE
, bi
->line_number
);
27955 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
27956 branch_islands
->pop ();
27960 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
27961 already there or not. */
27964 no_previous_def (tree function_name
)
27969 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
27970 if (function_name
== bi
->function_name
)
27975 /* GET_PREV_LABEL gets the label name from the previous definition of
27979 get_prev_label (tree function_name
)
27984 FOR_EACH_VEC_SAFE_ELT (branch_islands
, ix
, bi
)
27985 if (function_name
== bi
->function_name
)
27986 return bi
->label_name
;
27990 /* INSN is either a function call or a millicode call. It may have an
27991 unconditional jump in its delay slot.
27993 CALL_DEST is the routine we are calling. */
27996 output_call (rtx insn
, rtx
*operands
, int dest_operand_number
,
27997 int cookie_operand_number
)
27999 static char buf
[256];
28000 if (darwin_emit_branch_islands
28001 && GET_CODE (operands
[dest_operand_number
]) == SYMBOL_REF
28002 && (INTVAL (operands
[cookie_operand_number
]) & CALL_LONG
))
28005 tree funname
= get_identifier (XSTR (operands
[dest_operand_number
], 0));
28007 if (no_previous_def (funname
))
28009 rtx label_rtx
= gen_label_rtx ();
28010 char *label_buf
, temp_buf
[256];
28011 ASM_GENERATE_INTERNAL_LABEL (temp_buf
, "L",
28012 CODE_LABEL_NUMBER (label_rtx
));
28013 label_buf
= temp_buf
[0] == '*' ? temp_buf
+ 1 : temp_buf
;
28014 labelname
= get_identifier (label_buf
);
28015 add_compiler_branch_island (labelname
, funname
, insn_line (insn
));
28018 labelname
= get_prev_label (funname
);
28020 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
28021 instruction will reach 'foo', otherwise link as 'bl L42'".
28022 "L42" should be a 'branch island', that will do a far jump to
28023 'foo'. Branch islands are generated in
28024 macho_branch_islands(). */
28025 sprintf (buf
, "jbsr %%z%d,%.246s",
28026 dest_operand_number
, IDENTIFIER_POINTER (labelname
));
28029 sprintf (buf
, "bl %%z%d", dest_operand_number
);
28033 /* Generate PIC and indirect symbol stubs. */
28036 machopic_output_stub (FILE *file
, const char *symb
, const char *stub
)
28038 unsigned int length
;
28039 char *symbol_name
, *lazy_ptr_name
;
28040 char *local_label_0
;
28041 static int label
= 0;
28043 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
28044 symb
= (*targetm
.strip_name_encoding
) (symb
);
28047 length
= strlen (symb
);
28048 symbol_name
= XALLOCAVEC (char, length
+ 32);
28049 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name
, symb
, length
);
28051 lazy_ptr_name
= XALLOCAVEC (char, length
+ 32);
28052 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name
, symb
, length
);
28055 switch_to_section (darwin_sections
[machopic_picsymbol_stub1_section
]);
28057 switch_to_section (darwin_sections
[machopic_symbol_stub1_section
]);
28061 fprintf (file
, "\t.align 5\n");
28063 fprintf (file
, "%s:\n", stub
);
28064 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28067 local_label_0
= XALLOCAVEC (char, sizeof ("\"L00000000000$spb\""));
28068 sprintf (local_label_0
, "\"L%011d$spb\"", label
);
28070 fprintf (file
, "\tmflr r0\n");
28071 if (TARGET_LINK_STACK
)
28074 get_ppc476_thunk_name (name
);
28075 fprintf (file
, "\tbl %s\n", name
);
28076 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28080 fprintf (file
, "\tbcl 20,31,%s\n", local_label_0
);
28081 fprintf (file
, "%s:\n\tmflr r11\n", local_label_0
);
28083 fprintf (file
, "\taddis r11,r11,ha16(%s-%s)\n",
28084 lazy_ptr_name
, local_label_0
);
28085 fprintf (file
, "\tmtlr r0\n");
28086 fprintf (file
, "\t%s r12,lo16(%s-%s)(r11)\n",
28087 (TARGET_64BIT
? "ldu" : "lwzu"),
28088 lazy_ptr_name
, local_label_0
);
28089 fprintf (file
, "\tmtctr r12\n");
28090 fprintf (file
, "\tbctr\n");
28094 fprintf (file
, "\t.align 4\n");
28096 fprintf (file
, "%s:\n", stub
);
28097 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28099 fprintf (file
, "\tlis r11,ha16(%s)\n", lazy_ptr_name
);
28100 fprintf (file
, "\t%s r12,lo16(%s)(r11)\n",
28101 (TARGET_64BIT
? "ldu" : "lwzu"),
28103 fprintf (file
, "\tmtctr r12\n");
28104 fprintf (file
, "\tbctr\n");
28107 switch_to_section (darwin_sections
[machopic_lazy_symbol_ptr_section
]);
28108 fprintf (file
, "%s:\n", lazy_ptr_name
);
28109 fprintf (file
, "\t.indirect_symbol %s\n", symbol_name
);
28110 fprintf (file
, "%sdyld_stub_binding_helper\n",
28111 (TARGET_64BIT
? DOUBLE_INT_ASM_OP
: "\t.long\t"));
28114 /* Legitimize PIC addresses. If the address is already
28115 position-independent, we return ORIG. Newly generated
28116 position-independent addresses go into a reg. This is REG if non
28117 zero, otherwise we allocate register(s) as necessary. */
28119 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
28122 rs6000_machopic_legitimize_pic_address (rtx orig
, enum machine_mode mode
,
28127 if (reg
== NULL
&& ! reload_in_progress
&& ! reload_completed
)
28128 reg
= gen_reg_rtx (Pmode
);
28130 if (GET_CODE (orig
) == CONST
)
28134 if (GET_CODE (XEXP (orig
, 0)) == PLUS
28135 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
28138 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
28140 /* Use a different reg for the intermediate value, as
28141 it will be marked UNCHANGING. */
28142 reg_temp
= !can_create_pseudo_p () ? reg
: gen_reg_rtx (Pmode
);
28143 base
= rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0),
28146 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
28149 if (GET_CODE (offset
) == CONST_INT
)
28151 if (SMALL_INT (offset
))
28152 return plus_constant (Pmode
, base
, INTVAL (offset
));
28153 else if (! reload_in_progress
&& ! reload_completed
)
28154 offset
= force_reg (Pmode
, offset
);
28157 rtx mem
= force_const_mem (Pmode
, orig
);
28158 return machopic_legitimize_pic_address (mem
, Pmode
, reg
);
28161 return gen_rtx_PLUS (Pmode
, base
, offset
);
28164 /* Fall back on generic machopic code. */
28165 return machopic_legitimize_pic_address (orig
, mode
, reg
);
28168 /* Output a .machine directive for the Darwin assembler, and call
28169 the generic start_file routine. */
28172 rs6000_darwin_file_start (void)
28174 static const struct
28178 HOST_WIDE_INT if_set
;
28180 { "ppc64", "ppc64", MASK_64BIT
},
28181 { "970", "ppc970", MASK_PPC_GPOPT
| MASK_MFCRF
| MASK_POWERPC64
},
28182 { "power4", "ppc970", 0 },
28183 { "G5", "ppc970", 0 },
28184 { "7450", "ppc7450", 0 },
28185 { "7400", "ppc7400", MASK_ALTIVEC
},
28186 { "G4", "ppc7400", 0 },
28187 { "750", "ppc750", 0 },
28188 { "740", "ppc750", 0 },
28189 { "G3", "ppc750", 0 },
28190 { "604e", "ppc604e", 0 },
28191 { "604", "ppc604", 0 },
28192 { "603e", "ppc603", 0 },
28193 { "603", "ppc603", 0 },
28194 { "601", "ppc601", 0 },
28195 { NULL
, "ppc", 0 } };
28196 const char *cpu_id
= "";
28199 rs6000_file_start ();
28200 darwin_file_start ();
28202 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
28204 if (rs6000_default_cpu
!= 0 && rs6000_default_cpu
[0] != '\0')
28205 cpu_id
= rs6000_default_cpu
;
28207 if (global_options_set
.x_rs6000_cpu_index
)
28208 cpu_id
= processor_target_table
[rs6000_cpu_index
].name
;
28210 /* Look through the mapping array. Pick the first name that either
28211 matches the argument, has a bit set in IF_SET that is also set
28212 in the target flags, or has a NULL name. */
28215 while (mapping
[i
].arg
!= NULL
28216 && strcmp (mapping
[i
].arg
, cpu_id
) != 0
28217 && (mapping
[i
].if_set
& rs6000_isa_flags
) == 0)
28220 fprintf (asm_out_file
, "\t.machine %s\n", mapping
[i
].name
);
28223 #endif /* TARGET_MACHO */
28227 rs6000_elf_reloc_rw_mask (void)
28231 else if (DEFAULT_ABI
== ABI_AIX
|| DEFAULT_ABI
== ABI_ELFv2
)
28237 /* Record an element in the table of global constructors. SYMBOL is
28238 a SYMBOL_REF of the function to be called; PRIORITY is a number
28239 between 0 and MAX_INIT_PRIORITY.
28241 This differs from default_named_section_asm_out_constructor in
28242 that we have special handling for -mrelocatable. */
28244 static void rs6000_elf_asm_out_constructor (rtx
, int) ATTRIBUTE_UNUSED
;
28246 rs6000_elf_asm_out_constructor (rtx symbol
, int priority
)
28248 const char *section
= ".ctors";
28251 if (priority
!= DEFAULT_INIT_PRIORITY
)
28253 sprintf (buf
, ".ctors.%.5u",
28254 /* Invert the numbering so the linker puts us in the proper
28255 order; constructors are run from right to left, and the
28256 linker sorts in increasing order. */
28257 MAX_INIT_PRIORITY
- priority
);
28261 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28262 assemble_align (POINTER_SIZE
);
28264 if (TARGET_RELOCATABLE
)
28266 fputs ("\t.long (", asm_out_file
);
28267 output_addr_const (asm_out_file
, symbol
);
28268 fputs (")@fixup\n", asm_out_file
);
28271 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28274 static void rs6000_elf_asm_out_destructor (rtx
, int) ATTRIBUTE_UNUSED
;
28276 rs6000_elf_asm_out_destructor (rtx symbol
, int priority
)
28278 const char *section
= ".dtors";
28281 if (priority
!= DEFAULT_INIT_PRIORITY
)
28283 sprintf (buf
, ".dtors.%.5u",
28284 /* Invert the numbering so the linker puts us in the proper
28285 order; constructors are run from right to left, and the
28286 linker sorts in increasing order. */
28287 MAX_INIT_PRIORITY
- priority
);
28291 switch_to_section (get_section (section
, SECTION_WRITE
, NULL
));
28292 assemble_align (POINTER_SIZE
);
28294 if (TARGET_RELOCATABLE
)
28296 fputs ("\t.long (", asm_out_file
);
28297 output_addr_const (asm_out_file
, symbol
);
28298 fputs (")@fixup\n", asm_out_file
);
28301 assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, POINTER_SIZE
, 1);
28305 rs6000_elf_declare_function_name (FILE *file
, const char *name
, tree decl
)
28307 if (TARGET_64BIT
&& DEFAULT_ABI
!= ABI_ELFv2
)
28309 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file
);
28310 ASM_OUTPUT_LABEL (file
, name
);
28311 fputs (DOUBLE_INT_ASM_OP
, file
);
28312 rs6000_output_function_entry (file
, name
);
28313 fputs (",.TOC.@tocbase,0\n\t.previous\n", file
);
28316 fputs ("\t.size\t", file
);
28317 assemble_name (file
, name
);
28318 fputs (",24\n\t.type\t.", file
);
28319 assemble_name (file
, name
);
28320 fputs (",@function\n", file
);
28321 if (TREE_PUBLIC (decl
) && ! DECL_WEAK (decl
))
28323 fputs ("\t.globl\t.", file
);
28324 assemble_name (file
, name
);
28329 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
28330 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
28331 rs6000_output_function_entry (file
, name
);
28332 fputs (":\n", file
);
28336 if (TARGET_RELOCATABLE
28337 && !TARGET_SECURE_PLT
28338 && (get_pool_size () != 0 || crtl
->profile
)
28343 (*targetm
.asm_out
.internal_label
) (file
, "LCL", rs6000_pic_labelno
);
28345 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCTOC", 1);
28346 fprintf (file
, "\t.long ");
28347 assemble_name (file
, buf
);
28349 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCF", rs6000_pic_labelno
);
28350 assemble_name (file
, buf
);
28354 ASM_OUTPUT_TYPE_DIRECTIVE (file
, name
, "function");
28355 ASM_DECLARE_RESULT (file
, DECL_RESULT (decl
));
28357 if (DEFAULT_ABI
== ABI_AIX
)
28359 const char *desc_name
, *orig_name
;
28361 orig_name
= (*targetm
.strip_name_encoding
) (name
);
28362 desc_name
= orig_name
;
28363 while (*desc_name
== '.')
28366 if (TREE_PUBLIC (decl
))
28367 fprintf (file
, "\t.globl %s\n", desc_name
);
28369 fprintf (file
, "%s\n", MINIMAL_TOC_SECTION_ASM_OP
);
28370 fprintf (file
, "%s:\n", desc_name
);
28371 fprintf (file
, "\t.long %s\n", orig_name
);
28372 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file
);
28373 fputs ("\t.long 0\n", file
);
28374 fprintf (file
, "\t.previous\n");
28376 ASM_OUTPUT_LABEL (file
, name
);
28379 static void rs6000_elf_file_end (void) ATTRIBUTE_UNUSED
;
28381 rs6000_elf_file_end (void)
28383 #ifdef HAVE_AS_GNU_ATTRIBUTE
28384 if (TARGET_32BIT
&& DEFAULT_ABI
== ABI_V4
)
28386 if (rs6000_passes_float
)
28387 fprintf (asm_out_file
, "\t.gnu_attribute 4, %d\n",
28388 ((TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_DOUBLE_FLOAT
) ? 1
28389 : (TARGET_HARD_FLOAT
&& TARGET_FPRS
&& TARGET_SINGLE_FLOAT
) ? 3
28391 if (rs6000_passes_vector
)
28392 fprintf (asm_out_file
, "\t.gnu_attribute 8, %d\n",
28393 (TARGET_ALTIVEC_ABI
? 2
28394 : TARGET_SPE_ABI
? 3
28396 if (rs6000_returns_struct
)
28397 fprintf (asm_out_file
, "\t.gnu_attribute 12, %d\n",
28398 aix_struct_return
? 2 : 1);
28401 #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD)
28402 if (TARGET_32BIT
|| DEFAULT_ABI
== ABI_ELFv2
)
28403 file_end_indicate_exec_stack ();
28410 rs6000_xcoff_asm_output_anchor (rtx symbol
)
28414 sprintf (buffer
, "$ + " HOST_WIDE_INT_PRINT_DEC
,
28415 SYMBOL_REF_BLOCK_OFFSET (symbol
));
28416 ASM_OUTPUT_DEF (asm_out_file
, XSTR (symbol
, 0), buffer
);
28420 rs6000_xcoff_asm_globalize_label (FILE *stream
, const char *name
)
28422 fputs (GLOBAL_ASM_OP
, stream
);
28423 RS6000_OUTPUT_BASENAME (stream
, name
);
28424 putc ('\n', stream
);
28427 /* A get_unnamed_decl callback, used for read-only sections. PTR
28428 points to the section string variable. */
28431 rs6000_xcoff_output_readonly_section_asm_op (const void *directive
)
28433 fprintf (asm_out_file
, "\t.csect %s[RO],%s\n",
28434 *(const char *const *) directive
,
28435 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28438 /* Likewise for read-write sections. */
28441 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive
)
28443 fprintf (asm_out_file
, "\t.csect %s[RW],%s\n",
28444 *(const char *const *) directive
,
28445 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28449 rs6000_xcoff_output_tls_section_asm_op (const void *directive
)
28451 fprintf (asm_out_file
, "\t.csect %s[TL],%s\n",
28452 *(const char *const *) directive
,
28453 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR
);
28456 /* A get_unnamed_section callback, used for switching to toc_section. */
28459 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED
)
28461 if (TARGET_MINIMAL_TOC
)
28463 /* toc_section is always selected at least once from
28464 rs6000_xcoff_file_start, so this is guaranteed to
28465 always be defined once and only once in each file. */
28466 if (!toc_initialized
)
28468 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file
);
28469 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file
);
28470 toc_initialized
= 1;
28472 fprintf (asm_out_file
, "\t.csect toc_table[RW]%s\n",
28473 (TARGET_32BIT
? "" : ",3"));
28476 fputs ("\t.toc\n", asm_out_file
);
28479 /* Implement TARGET_ASM_INIT_SECTIONS. */
28482 rs6000_xcoff_asm_init_sections (void)
28484 read_only_data_section
28485 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
28486 &xcoff_read_only_section_name
);
28488 private_data_section
28489 = get_unnamed_section (SECTION_WRITE
,
28490 rs6000_xcoff_output_readwrite_section_asm_op
,
28491 &xcoff_private_data_section_name
);
28494 = get_unnamed_section (SECTION_TLS
,
28495 rs6000_xcoff_output_tls_section_asm_op
,
28496 &xcoff_tls_data_section_name
);
28498 tls_private_data_section
28499 = get_unnamed_section (SECTION_TLS
,
28500 rs6000_xcoff_output_tls_section_asm_op
,
28501 &xcoff_private_data_section_name
);
28503 read_only_private_data_section
28504 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op
,
28505 &xcoff_private_data_section_name
);
28508 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op
, NULL
);
28510 readonly_data_section
= read_only_data_section
;
28511 exception_section
= data_section
;
28515 rs6000_xcoff_reloc_rw_mask (void)
28521 rs6000_xcoff_asm_named_section (const char *name
, unsigned int flags
,
28522 tree decl ATTRIBUTE_UNUSED
)
28525 static const char * const suffix
[4] = { "PR", "RO", "RW", "TL" };
28527 if (flags
& SECTION_CODE
)
28529 else if (flags
& SECTION_TLS
)
28531 else if (flags
& SECTION_WRITE
)
28536 fprintf (asm_out_file
, "\t.csect %s%s[%s],%u\n",
28537 (flags
& SECTION_CODE
) ? "." : "",
28538 name
, suffix
[smclass
], flags
& SECTION_ENTSIZE
);
28542 rs6000_xcoff_select_section (tree decl
, int reloc
,
28543 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
28545 if (decl_readonly_section (decl
, reloc
))
28547 if (TREE_PUBLIC (decl
))
28548 return read_only_data_section
;
28550 return read_only_private_data_section
;
28555 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
28557 if (TREE_PUBLIC (decl
))
28558 return tls_data_section
;
28559 else if (bss_initializer_p (decl
))
28561 /* Convert to COMMON to emit in BSS. */
28562 DECL_COMMON (decl
) = 1;
28563 return tls_comm_section
;
28566 return tls_private_data_section
;
28570 if (TREE_PUBLIC (decl
))
28571 return data_section
;
28573 return private_data_section
;
28578 rs6000_xcoff_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
28582 /* Use select_section for private and uninitialized data. */
28583 if (!TREE_PUBLIC (decl
)
28584 || DECL_COMMON (decl
)
28585 || DECL_INITIAL (decl
) == NULL_TREE
28586 || DECL_INITIAL (decl
) == error_mark_node
28587 || (flag_zero_initialized_in_bss
28588 && initializer_zerop (DECL_INITIAL (decl
))))
28591 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
28592 name
= (*targetm
.strip_name_encoding
) (name
);
28593 DECL_SECTION_NAME (decl
) = build_string (strlen (name
), name
);
28596 /* Select section for constant in constant pool.
28598 On RS/6000, all constants are in the private read-only data area.
28599 However, if this is being placed in the TOC it must be output as a
28603 rs6000_xcoff_select_rtx_section (enum machine_mode mode
, rtx x
,
28604 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
28606 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x
, mode
))
28607 return toc_section
;
28609 return read_only_private_data_section
;
28612 /* Remove any trailing [DS] or the like from the symbol name. */
28614 static const char *
28615 rs6000_xcoff_strip_name_encoding (const char *name
)
28620 len
= strlen (name
);
28621 if (name
[len
- 1] == ']')
28622 return ggc_alloc_string (name
, len
- 4);
28627 /* Section attributes. AIX is always PIC. */
28629 static unsigned int
28630 rs6000_xcoff_section_type_flags (tree decl
, const char *name
, int reloc
)
28632 unsigned int align
;
28633 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
28635 /* Align to at least UNIT size. */
28636 if ((flags
& SECTION_CODE
) != 0 || !decl
|| !DECL_P (decl
))
28637 align
= MIN_UNITS_PER_WORD
;
28639 /* Increase alignment of large objects if not already stricter. */
28640 align
= MAX ((DECL_ALIGN (decl
) / BITS_PER_UNIT
),
28641 int_size_in_bytes (TREE_TYPE (decl
)) > MIN_UNITS_PER_WORD
28642 ? UNITS_PER_FP_WORD
: MIN_UNITS_PER_WORD
);
28644 return flags
| (exact_log2 (align
) & SECTION_ENTSIZE
);
28647 /* Output at beginning of assembler file.
28649 Initialize the section names for the RS/6000 at this point.
28651 Specify filename, including full path, to assembler.
28653 We want to go into the TOC section so at least one .toc will be emitted.
28654 Also, in order to output proper .bs/.es pairs, we need at least one static
28655 [RW] section emitted.
28657 Finally, declare mcount when profiling to make the assembler happy. */
28660 rs6000_xcoff_file_start (void)
28662 rs6000_gen_section_name (&xcoff_bss_section_name
,
28663 main_input_filename
, ".bss_");
28664 rs6000_gen_section_name (&xcoff_private_data_section_name
,
28665 main_input_filename
, ".rw_");
28666 rs6000_gen_section_name (&xcoff_read_only_section_name
,
28667 main_input_filename
, ".ro_");
28668 rs6000_gen_section_name (&xcoff_tls_data_section_name
,
28669 main_input_filename
, ".tls_");
28670 rs6000_gen_section_name (&xcoff_tbss_section_name
,
28671 main_input_filename
, ".tbss_[UL]");
28673 fputs ("\t.file\t", asm_out_file
);
28674 output_quoted_string (asm_out_file
, main_input_filename
);
28675 fputc ('\n', asm_out_file
);
28676 if (write_symbols
!= NO_DEBUG
)
28677 switch_to_section (private_data_section
);
28678 switch_to_section (text_section
);
28680 fprintf (asm_out_file
, "\t.extern %s\n", RS6000_MCOUNT
);
28681 rs6000_file_start ();
28684 /* Output at end of assembler file.
28685 On the RS/6000, referencing data should automatically pull in text. */
28688 rs6000_xcoff_file_end (void)
28690 switch_to_section (text_section
);
28691 fputs ("_section_.text:\n", asm_out_file
);
28692 switch_to_section (data_section
);
28693 fputs (TARGET_32BIT
28694 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
28700 rs6000_xcoff_encode_section_info (tree decl
, rtx rtl
, int first
)
28705 default_encode_section_info (decl
, rtl
, first
);
28707 /* Careful not to prod global register variables. */
28710 symbol
= XEXP (rtl
, 0);
28711 if (GET_CODE (symbol
) != SYMBOL_REF
)
28714 flags
= SYMBOL_REF_FLAGS (symbol
);
28716 if (TREE_CODE (decl
) == VAR_DECL
&& DECL_THREAD_LOCAL_P (decl
))
28717 flags
&= ~SYMBOL_FLAG_HAS_BLOCK_INFO
;
28719 SYMBOL_REF_FLAGS (symbol
) = flags
;
28721 #endif /* HAVE_AS_TLS */
28722 #endif /* TARGET_XCOFF */
28724 /* Compute a (partial) cost for rtx X. Return true if the complete
28725 cost has been computed, and false if subexpressions should be
28726 scanned. In either case, *TOTAL contains the cost result. */
28729 rs6000_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
28730 int *total
, bool speed
)
28732 enum machine_mode mode
= GET_MODE (x
);
28736 /* On the RS/6000, if it is valid in the insn, it is free. */
28738 if (((outer_code
== SET
28739 || outer_code
== PLUS
28740 || outer_code
== MINUS
)
28741 && (satisfies_constraint_I (x
)
28742 || satisfies_constraint_L (x
)))
28743 || (outer_code
== AND
28744 && (satisfies_constraint_K (x
)
28746 ? satisfies_constraint_L (x
)
28747 : satisfies_constraint_J (x
))
28748 || mask_operand (x
, mode
)
28750 && mask64_operand (x
, DImode
))))
28751 || ((outer_code
== IOR
|| outer_code
== XOR
)
28752 && (satisfies_constraint_K (x
)
28754 ? satisfies_constraint_L (x
)
28755 : satisfies_constraint_J (x
))))
28756 || outer_code
== ASHIFT
28757 || outer_code
== ASHIFTRT
28758 || outer_code
== LSHIFTRT
28759 || outer_code
== ROTATE
28760 || outer_code
== ROTATERT
28761 || outer_code
== ZERO_EXTRACT
28762 || (outer_code
== MULT
28763 && satisfies_constraint_I (x
))
28764 || ((outer_code
== DIV
|| outer_code
== UDIV
28765 || outer_code
== MOD
|| outer_code
== UMOD
)
28766 && exact_log2 (INTVAL (x
)) >= 0)
28767 || (outer_code
== COMPARE
28768 && (satisfies_constraint_I (x
)
28769 || satisfies_constraint_K (x
)))
28770 || ((outer_code
== EQ
|| outer_code
== NE
)
28771 && (satisfies_constraint_I (x
)
28772 || satisfies_constraint_K (x
)
28774 ? satisfies_constraint_L (x
)
28775 : satisfies_constraint_J (x
))))
28776 || (outer_code
== GTU
28777 && satisfies_constraint_I (x
))
28778 || (outer_code
== LTU
28779 && satisfies_constraint_P (x
)))
28784 else if ((outer_code
== PLUS
28785 && reg_or_add_cint_operand (x
, VOIDmode
))
28786 || (outer_code
== MINUS
28787 && reg_or_sub_cint_operand (x
, VOIDmode
))
28788 || ((outer_code
== SET
28789 || outer_code
== IOR
28790 || outer_code
== XOR
)
28792 & ~ (unsigned HOST_WIDE_INT
) 0xffffffff) == 0))
28794 *total
= COSTS_N_INSNS (1);
28800 case CONST_WIDE_INT
:
28805 /* When optimizing for size, MEM should be slightly more expensive
28806 than generating address, e.g., (plus (reg) (const)).
28807 L1 cache latency is about two instructions. */
28808 *total
= !speed
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
28817 if (FLOAT_MODE_P (mode
))
28818 *total
= rs6000_cost
->fp
;
28820 *total
= COSTS_N_INSNS (1);
28824 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
28825 && satisfies_constraint_I (XEXP (x
, 1)))
28827 if (INTVAL (XEXP (x
, 1)) >= -256
28828 && INTVAL (XEXP (x
, 1)) <= 255)
28829 *total
= rs6000_cost
->mulsi_const9
;
28831 *total
= rs6000_cost
->mulsi_const
;
28833 else if (mode
== SFmode
)
28834 *total
= rs6000_cost
->fp
;
28835 else if (FLOAT_MODE_P (mode
))
28836 *total
= rs6000_cost
->dmul
;
28837 else if (mode
== DImode
)
28838 *total
= rs6000_cost
->muldi
;
28840 *total
= rs6000_cost
->mulsi
;
28844 if (mode
== SFmode
)
28845 *total
= rs6000_cost
->fp
;
28847 *total
= rs6000_cost
->dmul
;
28852 if (FLOAT_MODE_P (mode
))
28854 *total
= mode
== DFmode
? rs6000_cost
->ddiv
28855 : rs6000_cost
->sdiv
;
28862 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
28863 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0)
28865 if (code
== DIV
|| code
== MOD
)
28867 *total
= COSTS_N_INSNS (2);
28870 *total
= COSTS_N_INSNS (1);
28874 if (GET_MODE (XEXP (x
, 1)) == DImode
)
28875 *total
= rs6000_cost
->divdi
;
28877 *total
= rs6000_cost
->divsi
;
28879 /* Add in shift and subtract for MOD. */
28880 if (code
== MOD
|| code
== UMOD
)
28881 *total
+= COSTS_N_INSNS (2);
28886 *total
= COSTS_N_INSNS (4);
28890 *total
= COSTS_N_INSNS (TARGET_POPCNTD
? 1 : 6);
28894 *total
= COSTS_N_INSNS (TARGET_CMPB
? 2 : 6);
28898 if (outer_code
== AND
|| outer_code
== IOR
|| outer_code
== XOR
)
28910 *total
= COSTS_N_INSNS (1);
28918 /* Handle mul_highpart. */
28919 if (outer_code
== TRUNCATE
28920 && GET_CODE (XEXP (x
, 0)) == MULT
)
28922 if (mode
== DImode
)
28923 *total
= rs6000_cost
->muldi
;
28925 *total
= rs6000_cost
->mulsi
;
28928 else if (outer_code
== AND
)
28931 *total
= COSTS_N_INSNS (1);
28936 if (GET_CODE (XEXP (x
, 0)) == MEM
)
28939 *total
= COSTS_N_INSNS (1);
28945 if (!FLOAT_MODE_P (mode
))
28947 *total
= COSTS_N_INSNS (1);
28953 case UNSIGNED_FLOAT
:
28956 case FLOAT_TRUNCATE
:
28957 *total
= rs6000_cost
->fp
;
28961 if (mode
== DFmode
)
28964 *total
= rs6000_cost
->fp
;
28968 switch (XINT (x
, 1))
28971 *total
= rs6000_cost
->fp
;
28983 *total
= COSTS_N_INSNS (1);
28986 else if (FLOAT_MODE_P (mode
)
28987 && TARGET_PPC_GFXOPT
&& TARGET_HARD_FLOAT
&& TARGET_FPRS
)
28989 *total
= rs6000_cost
->fp
;
28997 /* Carry bit requires mode == Pmode.
28998 NEG or PLUS already counted so only add one. */
29000 && (outer_code
== NEG
|| outer_code
== PLUS
))
29002 *total
= COSTS_N_INSNS (1);
29005 if (outer_code
== SET
)
29007 if (XEXP (x
, 1) == const0_rtx
)
29009 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29010 *total
= COSTS_N_INSNS (8);
29012 *total
= COSTS_N_INSNS (2);
29015 else if (mode
== Pmode
)
29017 *total
= COSTS_N_INSNS (3);
29026 if (outer_code
== SET
&& (XEXP (x
, 1) == const0_rtx
))
29028 if (TARGET_ISEL
&& !TARGET_MFCRF
)
29029 *total
= COSTS_N_INSNS (8);
29031 *total
= COSTS_N_INSNS (2);
29035 if (outer_code
== COMPARE
)
29049 /* Debug form of r6000_rtx_costs that is selected if -mdebug=cost. */
29052 rs6000_debug_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
29055 bool ret
= rs6000_rtx_costs (x
, code
, outer_code
, opno
, total
, speed
);
29058 "\nrs6000_rtx_costs, return = %s, code = %s, outer_code = %s, "
29059 "opno = %d, total = %d, speed = %s, x:\n",
29060 ret
? "complete" : "scan inner",
29061 GET_RTX_NAME (code
),
29062 GET_RTX_NAME (outer_code
),
29065 speed
? "true" : "false");
29072 /* Debug form of ADDRESS_COST that is selected if -mdebug=cost. */
29075 rs6000_debug_address_cost (rtx x
, enum machine_mode mode
,
29076 addr_space_t as
, bool speed
)
29078 int ret
= TARGET_ADDRESS_COST (x
, mode
, as
, speed
);
29080 fprintf (stderr
, "\nrs6000_address_cost, return = %d, speed = %s, x:\n",
29081 ret
, speed
? "true" : "false");
29088 /* A C expression returning the cost of moving data from a register of class
29089 CLASS1 to one of CLASS2. */
29092 rs6000_register_move_cost (enum machine_mode mode
,
29093 reg_class_t from
, reg_class_t to
)
29097 if (TARGET_DEBUG_COST
)
29100 /* Moves from/to GENERAL_REGS. */
29101 if (reg_classes_intersect_p (to
, GENERAL_REGS
)
29102 || reg_classes_intersect_p (from
, GENERAL_REGS
))
29104 reg_class_t rclass
= from
;
29106 if (! reg_classes_intersect_p (to
, GENERAL_REGS
))
29109 if (rclass
== FLOAT_REGS
|| rclass
== ALTIVEC_REGS
|| rclass
== VSX_REGS
)
29110 ret
= (rs6000_memory_move_cost (mode
, rclass
, false)
29111 + rs6000_memory_move_cost (mode
, GENERAL_REGS
, false));
29113 /* It's more expensive to move CR_REGS than CR0_REGS because of the
29115 else if (rclass
== CR_REGS
)
29118 /* For those processors that have slow LR/CTR moves, make them more
29119 expensive than memory in order to bias spills to memory .*/
29120 else if ((rs6000_cpu
== PROCESSOR_POWER6
29121 || rs6000_cpu
== PROCESSOR_POWER7
29122 || rs6000_cpu
== PROCESSOR_POWER8
)
29123 && reg_classes_intersect_p (rclass
, LINK_OR_CTR_REGS
))
29124 ret
= 6 * hard_regno_nregs
[0][mode
];
29127 /* A move will cost one instruction per GPR moved. */
29128 ret
= 2 * hard_regno_nregs
[0][mode
];
29131 /* If we have VSX, we can easily move between FPR or Altivec registers. */
29132 else if (VECTOR_MEM_VSX_P (mode
)
29133 && reg_classes_intersect_p (to
, VSX_REGS
)
29134 && reg_classes_intersect_p (from
, VSX_REGS
))
29135 ret
= 2 * hard_regno_nregs
[32][mode
];
29137 /* Moving between two similar registers is just one instruction. */
29138 else if (reg_classes_intersect_p (to
, from
))
29139 ret
= (mode
== TFmode
|| mode
== TDmode
) ? 4 : 2;
29141 /* Everything else has to go through GENERAL_REGS. */
29143 ret
= (rs6000_register_move_cost (mode
, GENERAL_REGS
, to
)
29144 + rs6000_register_move_cost (mode
, from
, GENERAL_REGS
));
29146 if (TARGET_DEBUG_COST
)
29148 if (dbg_cost_ctrl
== 1)
29150 "rs6000_register_move_cost:, ret=%d, mode=%s, from=%s, to=%s\n",
29151 ret
, GET_MODE_NAME (mode
), reg_class_names
[from
],
29152 reg_class_names
[to
]);
29159 /* A C expressions returning the cost of moving data of MODE from a register to
29163 rs6000_memory_move_cost (enum machine_mode mode
, reg_class_t rclass
,
29164 bool in ATTRIBUTE_UNUSED
)
29168 if (TARGET_DEBUG_COST
)
29171 if (reg_classes_intersect_p (rclass
, GENERAL_REGS
))
29172 ret
= 4 * hard_regno_nregs
[0][mode
];
29173 else if ((reg_classes_intersect_p (rclass
, FLOAT_REGS
)
29174 || reg_classes_intersect_p (rclass
, VSX_REGS
)))
29175 ret
= 4 * hard_regno_nregs
[32][mode
];
29176 else if (reg_classes_intersect_p (rclass
, ALTIVEC_REGS
))
29177 ret
= 4 * hard_regno_nregs
[FIRST_ALTIVEC_REGNO
][mode
];
29179 ret
= 4 + rs6000_register_move_cost (mode
, rclass
, GENERAL_REGS
);
29181 if (TARGET_DEBUG_COST
)
29183 if (dbg_cost_ctrl
== 1)
29185 "rs6000_memory_move_cost: ret=%d, mode=%s, rclass=%s, in=%d\n",
29186 ret
, GET_MODE_NAME (mode
), reg_class_names
[rclass
], in
);
29193 /* Returns a code for a target-specific builtin that implements
29194 reciprocal of the function, or NULL_TREE if not available. */
29197 rs6000_builtin_reciprocal (unsigned int fn
, bool md_fn
,
29198 bool sqrt ATTRIBUTE_UNUSED
)
29200 if (optimize_insn_for_size_p ())
29206 case VSX_BUILTIN_XVSQRTDP
:
29207 if (!RS6000_RECIP_AUTO_RSQRTE_P (V2DFmode
))
29210 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_2DF
];
29212 case VSX_BUILTIN_XVSQRTSP
:
29213 if (!RS6000_RECIP_AUTO_RSQRTE_P (V4SFmode
))
29216 return rs6000_builtin_decls
[VSX_BUILTIN_RSQRT_4SF
];
29225 case BUILT_IN_SQRT
:
29226 if (!RS6000_RECIP_AUTO_RSQRTE_P (DFmode
))
29229 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRT
];
29231 case BUILT_IN_SQRTF
:
29232 if (!RS6000_RECIP_AUTO_RSQRTE_P (SFmode
))
29235 return rs6000_builtin_decls
[RS6000_BUILTIN_RSQRTF
];
29242 /* Load up a constant. If the mode is a vector mode, splat the value across
29243 all of the vector elements. */
29246 rs6000_load_constant_and_splat (enum machine_mode mode
, REAL_VALUE_TYPE dconst
)
29250 if (mode
== SFmode
|| mode
== DFmode
)
29252 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, mode
);
29253 reg
= force_reg (mode
, d
);
29255 else if (mode
== V4SFmode
)
29257 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, SFmode
);
29258 rtvec v
= gen_rtvec (4, d
, d
, d
, d
);
29259 reg
= gen_reg_rtx (mode
);
29260 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29262 else if (mode
== V2DFmode
)
29264 rtx d
= CONST_DOUBLE_FROM_REAL_VALUE (dconst
, DFmode
);
29265 rtvec v
= gen_rtvec (2, d
, d
);
29266 reg
= gen_reg_rtx (mode
);
29267 rs6000_expand_vector_init (reg
, gen_rtx_PARALLEL (mode
, v
));
29270 gcc_unreachable ();
29275 /* Generate an FMA instruction. */
29278 rs6000_emit_madd (rtx target
, rtx m1
, rtx m2
, rtx a
)
29280 enum machine_mode mode
= GET_MODE (target
);
29283 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
29284 gcc_assert (dst
!= NULL
);
29287 emit_move_insn (target
, dst
);
29290 /* Generate a FMSUB instruction: dst = fma(m1, m2, -a). */
29293 rs6000_emit_msub (rtx target
, rtx m1
, rtx m2
, rtx a
)
29295 enum machine_mode mode
= GET_MODE (target
);
29298 /* Altivec does not support fms directly;
29299 generate in terms of fma in that case. */
29300 if (optab_handler (fms_optab
, mode
) != CODE_FOR_nothing
)
29301 dst
= expand_ternary_op (mode
, fms_optab
, m1
, m2
, a
, target
, 0);
29304 a
= expand_unop (mode
, neg_optab
, a
, NULL_RTX
, 0);
29305 dst
= expand_ternary_op (mode
, fma_optab
, m1
, m2
, a
, target
, 0);
29307 gcc_assert (dst
!= NULL
);
29310 emit_move_insn (target
, dst
);
29313 /* Generate a FNMSUB instruction: dst = -fma(m1, m2, -a). */
29316 rs6000_emit_nmsub (rtx dst
, rtx m1
, rtx m2
, rtx a
)
29318 enum machine_mode mode
= GET_MODE (dst
);
29321 /* This is a tad more complicated, since the fnma_optab is for
29322 a different expression: fma(-m1, m2, a), which is the same
29323 thing except in the case of signed zeros.
29325 Fortunately we know that if FMA is supported that FNMSUB is
29326 also supported in the ISA. Just expand it directly. */
29328 gcc_assert (optab_handler (fma_optab
, mode
) != CODE_FOR_nothing
);
29330 r
= gen_rtx_NEG (mode
, a
);
29331 r
= gen_rtx_FMA (mode
, m1
, m2
, r
);
29332 r
= gen_rtx_NEG (mode
, r
);
29333 emit_insn (gen_rtx_SET (VOIDmode
, dst
, r
));
29336 /* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P,
29337 add a reg_note saying that this was a division. Support both scalar and
29338 vector divide. Assumes no trapping math and finite arguments. */
29341 rs6000_emit_swdiv (rtx dst
, rtx n
, rtx d
, bool note_p
)
29343 enum machine_mode mode
= GET_MODE (dst
);
29344 rtx one
, x0
, e0
, x1
, xprev
, eprev
, xnext
, enext
, u
, v
;
29347 /* Low precision estimates guarantee 5 bits of accuracy. High
29348 precision estimates guarantee 14 bits of accuracy. SFmode
29349 requires 23 bits of accuracy. DFmode requires 52 bits of
29350 accuracy. Each pass at least doubles the accuracy, leading
29351 to the following. */
29352 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
29353 if (mode
== DFmode
|| mode
== V2DFmode
)
29356 enum insn_code code
= optab_handler (smul_optab
, mode
);
29357 insn_gen_fn gen_mul
= GEN_FCN (code
);
29359 gcc_assert (code
!= CODE_FOR_nothing
);
29361 one
= rs6000_load_constant_and_splat (mode
, dconst1
);
29363 /* x0 = 1./d estimate */
29364 x0
= gen_reg_rtx (mode
);
29365 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
29366 gen_rtx_UNSPEC (mode
, gen_rtvec (1, d
),
29369 /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */
29372 /* e0 = 1. - d * x0 */
29373 e0
= gen_reg_rtx (mode
);
29374 rs6000_emit_nmsub (e0
, d
, x0
, one
);
29376 /* x1 = x0 + e0 * x0 */
29377 x1
= gen_reg_rtx (mode
);
29378 rs6000_emit_madd (x1
, e0
, x0
, x0
);
29380 for (i
= 0, xprev
= x1
, eprev
= e0
; i
< passes
- 2;
29381 ++i
, xprev
= xnext
, eprev
= enext
) {
29383 /* enext = eprev * eprev */
29384 enext
= gen_reg_rtx (mode
);
29385 emit_insn (gen_mul (enext
, eprev
, eprev
));
29387 /* xnext = xprev + enext * xprev */
29388 xnext
= gen_reg_rtx (mode
);
29389 rs6000_emit_madd (xnext
, enext
, xprev
, xprev
);
29395 /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */
29397 /* u = n * xprev */
29398 u
= gen_reg_rtx (mode
);
29399 emit_insn (gen_mul (u
, n
, xprev
));
29401 /* v = n - (d * u) */
29402 v
= gen_reg_rtx (mode
);
29403 rs6000_emit_nmsub (v
, d
, u
, n
);
29405 /* dst = (v * xprev) + u */
29406 rs6000_emit_madd (dst
, v
, xprev
, u
);
29409 add_reg_note (get_last_insn (), REG_EQUAL
, gen_rtx_DIV (mode
, n
, d
));
29412 /* Newton-Raphson approximation of single/double-precision floating point
29413 rsqrt. Assumes no trapping math and finite arguments. */
29416 rs6000_emit_swrsqrt (rtx dst
, rtx src
)
29418 enum machine_mode mode
= GET_MODE (src
);
29419 rtx x0
= gen_reg_rtx (mode
);
29420 rtx y
= gen_reg_rtx (mode
);
29422 /* Low precision estimates guarantee 5 bits of accuracy. High
29423 precision estimates guarantee 14 bits of accuracy. SFmode
29424 requires 23 bits of accuracy. DFmode requires 52 bits of
29425 accuracy. Each pass at least doubles the accuracy, leading
29426 to the following. */
29427 int passes
= (TARGET_RECIP_PRECISION
) ? 1 : 3;
29428 if (mode
== DFmode
|| mode
== V2DFmode
)
29431 REAL_VALUE_TYPE dconst3_2
;
29434 enum insn_code code
= optab_handler (smul_optab
, mode
);
29435 insn_gen_fn gen_mul
= GEN_FCN (code
);
29437 gcc_assert (code
!= CODE_FOR_nothing
);
29439 /* Load up the constant 1.5 either as a scalar, or as a vector. */
29440 real_from_integer (&dconst3_2
, VOIDmode
, 3, SIGNED
);
29441 SET_REAL_EXP (&dconst3_2
, REAL_EXP (&dconst3_2
) - 1);
29443 halfthree
= rs6000_load_constant_and_splat (mode
, dconst3_2
);
29445 /* x0 = rsqrt estimate */
29446 emit_insn (gen_rtx_SET (VOIDmode
, x0
,
29447 gen_rtx_UNSPEC (mode
, gen_rtvec (1, src
),
29450 /* y = 0.5 * src = 1.5 * src - src -> fewer constants */
29451 rs6000_emit_msub (y
, src
, halfthree
, src
);
29453 for (i
= 0; i
< passes
; i
++)
29455 rtx x1
= gen_reg_rtx (mode
);
29456 rtx u
= gen_reg_rtx (mode
);
29457 rtx v
= gen_reg_rtx (mode
);
29459 /* x1 = x0 * (1.5 - y * (x0 * x0)) */
29460 emit_insn (gen_mul (u
, x0
, x0
));
29461 rs6000_emit_nmsub (v
, y
, u
, halfthree
);
29462 emit_insn (gen_mul (x1
, x0
, v
));
29466 emit_move_insn (dst
, x0
);
29470 /* Emit popcount intrinsic on TARGET_POPCNTB (Power5) and TARGET_POPCNTD
29471 (Power7) targets. DST is the target, and SRC is the argument operand. */
29474 rs6000_emit_popcount (rtx dst
, rtx src
)
29476 enum machine_mode mode
= GET_MODE (dst
);
29479 /* Use the PPC ISA 2.06 popcnt{w,d} instruction if we can. */
29480 if (TARGET_POPCNTD
)
29482 if (mode
== SImode
)
29483 emit_insn (gen_popcntdsi2 (dst
, src
));
29485 emit_insn (gen_popcntddi2 (dst
, src
));
29489 tmp1
= gen_reg_rtx (mode
);
29491 if (mode
== SImode
)
29493 emit_insn (gen_popcntbsi2 (tmp1
, src
));
29494 tmp2
= expand_mult (SImode
, tmp1
, GEN_INT (0x01010101),
29496 tmp2
= force_reg (SImode
, tmp2
);
29497 emit_insn (gen_lshrsi3 (dst
, tmp2
, GEN_INT (24)));
29501 emit_insn (gen_popcntbdi2 (tmp1
, src
));
29502 tmp2
= expand_mult (DImode
, tmp1
,
29503 GEN_INT ((HOST_WIDE_INT
)
29504 0x01010101 << 32 | 0x01010101),
29506 tmp2
= force_reg (DImode
, tmp2
);
29507 emit_insn (gen_lshrdi3 (dst
, tmp2
, GEN_INT (56)));
29512 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
29513 target, and SRC is the argument operand. */
29516 rs6000_emit_parity (rtx dst
, rtx src
)
29518 enum machine_mode mode
= GET_MODE (dst
);
29521 tmp
= gen_reg_rtx (mode
);
29523 /* Use the PPC ISA 2.05 prtyw/prtyd instruction if we can. */
29526 if (mode
== SImode
)
29528 emit_insn (gen_popcntbsi2 (tmp
, src
));
29529 emit_insn (gen_paritysi2_cmpb (dst
, tmp
));
29533 emit_insn (gen_popcntbdi2 (tmp
, src
));
29534 emit_insn (gen_paritydi2_cmpb (dst
, tmp
));
29539 if (mode
== SImode
)
29541 /* Is mult+shift >= shift+xor+shift+xor? */
29542 if (rs6000_cost
->mulsi_const
>= COSTS_N_INSNS (3))
29544 rtx tmp1
, tmp2
, tmp3
, tmp4
;
29546 tmp1
= gen_reg_rtx (SImode
);
29547 emit_insn (gen_popcntbsi2 (tmp1
, src
));
29549 tmp2
= gen_reg_rtx (SImode
);
29550 emit_insn (gen_lshrsi3 (tmp2
, tmp1
, GEN_INT (16)));
29551 tmp3
= gen_reg_rtx (SImode
);
29552 emit_insn (gen_xorsi3 (tmp3
, tmp1
, tmp2
));
29554 tmp4
= gen_reg_rtx (SImode
);
29555 emit_insn (gen_lshrsi3 (tmp4
, tmp3
, GEN_INT (8)));
29556 emit_insn (gen_xorsi3 (tmp
, tmp3
, tmp4
));
29559 rs6000_emit_popcount (tmp
, src
);
29560 emit_insn (gen_andsi3 (dst
, tmp
, const1_rtx
));
29564 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
29565 if (rs6000_cost
->muldi
>= COSTS_N_INSNS (5))
29567 rtx tmp1
, tmp2
, tmp3
, tmp4
, tmp5
, tmp6
;
29569 tmp1
= gen_reg_rtx (DImode
);
29570 emit_insn (gen_popcntbdi2 (tmp1
, src
));
29572 tmp2
= gen_reg_rtx (DImode
);
29573 emit_insn (gen_lshrdi3 (tmp2
, tmp1
, GEN_INT (32)));
29574 tmp3
= gen_reg_rtx (DImode
);
29575 emit_insn (gen_xordi3 (tmp3
, tmp1
, tmp2
));
29577 tmp4
= gen_reg_rtx (DImode
);
29578 emit_insn (gen_lshrdi3 (tmp4
, tmp3
, GEN_INT (16)));
29579 tmp5
= gen_reg_rtx (DImode
);
29580 emit_insn (gen_xordi3 (tmp5
, tmp3
, tmp4
));
29582 tmp6
= gen_reg_rtx (DImode
);
29583 emit_insn (gen_lshrdi3 (tmp6
, tmp5
, GEN_INT (8)));
29584 emit_insn (gen_xordi3 (tmp
, tmp5
, tmp6
));
29587 rs6000_emit_popcount (tmp
, src
);
29588 emit_insn (gen_anddi3 (dst
, tmp
, const1_rtx
));
29592 /* Expand an Altivec constant permutation for little endian mode.
29593 There are two issues: First, the two input operands must be
29594 swapped so that together they form a double-wide array in LE
29595 order. Second, the vperm instruction has surprising behavior
29596 in LE mode: it interprets the elements of the source vectors
29597 in BE mode ("left to right") and interprets the elements of
29598 the destination vector in LE mode ("right to left"). To
29599 correct for this, we must subtract each element of the permute
29600 control vector from 31.
29602 For example, suppose we want to concatenate vr10 = {0, 1, 2, 3}
29603 with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm.
29604 We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to
29605 serve as the permute control vector. Then, in BE mode,
29609 places the desired result in vr9. However, in LE mode the
29610 vector contents will be
29612 vr10 = 00000003 00000002 00000001 00000000
29613 vr11 = 00000007 00000006 00000005 00000004
29615 The result of the vperm using the same permute control vector is
29617 vr9 = 05000000 07000000 01000000 03000000
29619 That is, the leftmost 4 bytes of vr10 are interpreted as the
29620 source for the rightmost 4 bytes of vr9, and so on.
29622 If we change the permute control vector to
29624 vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4}
29632 vr9 = 00000006 00000004 00000002 00000000. */
29635 altivec_expand_vec_perm_const_le (rtx operands
[4])
29639 rtx constv
, unspec
;
29640 rtx target
= operands
[0];
29641 rtx op0
= operands
[1];
29642 rtx op1
= operands
[2];
29643 rtx sel
= operands
[3];
29645 /* Unpack and adjust the constant selector. */
29646 for (i
= 0; i
< 16; ++i
)
29648 rtx e
= XVECEXP (sel
, 0, i
);
29649 unsigned int elt
= 31 - (INTVAL (e
) & 31);
29650 perm
[i
] = GEN_INT (elt
);
29653 /* Expand to a permute, swapping the inputs and using the
29654 adjusted selector. */
29656 op0
= force_reg (V16QImode
, op0
);
29658 op1
= force_reg (V16QImode
, op1
);
29660 constv
= gen_rtx_CONST_VECTOR (V16QImode
, gen_rtvec_v (16, perm
));
29661 constv
= force_reg (V16QImode
, constv
);
29662 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, constv
),
29664 if (!REG_P (target
))
29666 rtx tmp
= gen_reg_rtx (V16QImode
);
29667 emit_move_insn (tmp
, unspec
);
29671 emit_move_insn (target
, unspec
);
29674 /* Similarly to altivec_expand_vec_perm_const_le, we must adjust the
29675 permute control vector. But here it's not a constant, so we must
29676 generate a vector splat/subtract to do the adjustment. */
29679 altivec_expand_vec_perm_le (rtx operands
[4])
29682 rtx target
= operands
[0];
29683 rtx op0
= operands
[1];
29684 rtx op1
= operands
[2];
29685 rtx sel
= operands
[3];
29688 /* Get everything in regs so the pattern matches. */
29690 op0
= force_reg (V16QImode
, op0
);
29692 op1
= force_reg (V16QImode
, op1
);
29694 sel
= force_reg (V16QImode
, sel
);
29695 if (!REG_P (target
))
29696 tmp
= gen_reg_rtx (V16QImode
);
29698 /* SEL = splat(31) - SEL. */
29699 /* We want to subtract from 31, but we can't vspltisb 31 since
29700 it's out of range. -1 works as well because only the low-order
29701 five bits of the permute control vector elements are used. */
29702 splat
= gen_rtx_VEC_DUPLICATE (V16QImode
,
29703 gen_rtx_CONST_INT (QImode
, -1));
29704 emit_move_insn (tmp
, splat
);
29705 sel
= gen_rtx_MINUS (V16QImode
, tmp
, sel
);
29706 emit_move_insn (tmp
, sel
);
29708 /* Permute with operands reversed and adjusted selector. */
29709 unspec
= gen_rtx_UNSPEC (V16QImode
, gen_rtvec (3, op1
, op0
, tmp
),
29712 /* Copy into target, possibly by way of a register. */
29713 if (!REG_P (target
))
29715 emit_move_insn (tmp
, unspec
);
29719 emit_move_insn (target
, unspec
);
29722 /* Expand an Altivec constant permutation. Return true if we match
29723 an efficient implementation; false to fall back to VPERM. */
29726 altivec_expand_vec_perm_const (rtx operands
[4])
29728 struct altivec_perm_insn
{
29729 HOST_WIDE_INT mask
;
29730 enum insn_code impl
;
29731 unsigned char perm
[16];
29733 static const struct altivec_perm_insn patterns
[] = {
29734 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuhum
,
29735 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
29736 { OPTION_MASK_ALTIVEC
, CODE_FOR_altivec_vpkuwum
,
29737 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
29738 { OPTION_MASK_ALTIVEC
,
29739 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghb
: CODE_FOR_altivec_vmrglb
,
29740 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
29741 { OPTION_MASK_ALTIVEC
,
29742 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghh
: CODE_FOR_altivec_vmrglh
,
29743 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
29744 { OPTION_MASK_ALTIVEC
,
29745 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrghw
: CODE_FOR_altivec_vmrglw
,
29746 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
29747 { OPTION_MASK_ALTIVEC
,
29748 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglb
: CODE_FOR_altivec_vmrghb
,
29749 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
29750 { OPTION_MASK_ALTIVEC
,
29751 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglh
: CODE_FOR_altivec_vmrghh
,
29752 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
29753 { OPTION_MASK_ALTIVEC
,
29754 BYTES_BIG_ENDIAN
? CODE_FOR_altivec_vmrglw
: CODE_FOR_altivec_vmrghw
,
29755 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
29756 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgew
,
29757 { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } },
29758 { OPTION_MASK_P8_VECTOR
, CODE_FOR_p8_vmrgow
,
29759 { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } }
29762 unsigned int i
, j
, elt
, which
;
29763 unsigned char perm
[16];
29764 rtx target
, op0
, op1
, sel
, x
;
29767 target
= operands
[0];
29772 /* Unpack the constant selector. */
29773 for (i
= which
= 0; i
< 16; ++i
)
29775 rtx e
= XVECEXP (sel
, 0, i
);
29776 elt
= INTVAL (e
) & 31;
29777 which
|= (elt
< 16 ? 1 : 2);
29781 /* Simplify the constant selector based on operands. */
29785 gcc_unreachable ();
29789 if (!rtx_equal_p (op0
, op1
))
29794 for (i
= 0; i
< 16; ++i
)
29806 /* Look for splat patterns. */
29811 for (i
= 0; i
< 16; ++i
)
29812 if (perm
[i
] != elt
)
29816 if (!BYTES_BIG_ENDIAN
)
29818 emit_insn (gen_altivec_vspltb (target
, op0
, GEN_INT (elt
)));
29824 for (i
= 0; i
< 16; i
+= 2)
29825 if (perm
[i
] != elt
|| perm
[i
+ 1] != elt
+ 1)
29829 int field
= BYTES_BIG_ENDIAN
? elt
/ 2 : 7 - elt
/ 2;
29830 x
= gen_reg_rtx (V8HImode
);
29831 emit_insn (gen_altivec_vsplth (x
, gen_lowpart (V8HImode
, op0
),
29833 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29840 for (i
= 0; i
< 16; i
+= 4)
29842 || perm
[i
+ 1] != elt
+ 1
29843 || perm
[i
+ 2] != elt
+ 2
29844 || perm
[i
+ 3] != elt
+ 3)
29848 int field
= BYTES_BIG_ENDIAN
? elt
/ 4 : 3 - elt
/ 4;
29849 x
= gen_reg_rtx (V4SImode
);
29850 emit_insn (gen_altivec_vspltw (x
, gen_lowpart (V4SImode
, op0
),
29852 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29858 /* Look for merge and pack patterns. */
29859 for (j
= 0; j
< ARRAY_SIZE (patterns
); ++j
)
29863 if ((patterns
[j
].mask
& rs6000_isa_flags
) == 0)
29866 elt
= patterns
[j
].perm
[0];
29867 if (perm
[0] == elt
)
29869 else if (perm
[0] == elt
+ 16)
29873 for (i
= 1; i
< 16; ++i
)
29875 elt
= patterns
[j
].perm
[i
];
29877 elt
= (elt
>= 16 ? elt
- 16 : elt
+ 16);
29878 else if (one_vec
&& elt
>= 16)
29880 if (perm
[i
] != elt
)
29885 enum insn_code icode
= patterns
[j
].impl
;
29886 enum machine_mode omode
= insn_data
[icode
].operand
[0].mode
;
29887 enum machine_mode imode
= insn_data
[icode
].operand
[1].mode
;
29889 /* For little-endian, don't use vpkuwum and vpkuhum if the
29890 underlying vector type is not V4SI and V8HI, respectively.
29891 For example, using vpkuwum with a V8HI picks up the even
29892 halfwords (BE numbering) when the even halfwords (LE
29893 numbering) are what we need. */
29894 if (!BYTES_BIG_ENDIAN
29895 && icode
== CODE_FOR_altivec_vpkuwum
29896 && ((GET_CODE (op0
) == REG
29897 && GET_MODE (op0
) != V4SImode
)
29898 || (GET_CODE (op0
) == SUBREG
29899 && GET_MODE (XEXP (op0
, 0)) != V4SImode
)))
29901 if (!BYTES_BIG_ENDIAN
29902 && icode
== CODE_FOR_altivec_vpkuhum
29903 && ((GET_CODE (op0
) == REG
29904 && GET_MODE (op0
) != V8HImode
)
29905 || (GET_CODE (op0
) == SUBREG
29906 && GET_MODE (XEXP (op0
, 0)) != V8HImode
)))
29909 /* For little-endian, the two input operands must be swapped
29910 (or swapped back) to ensure proper right-to-left numbering
29912 if (swapped
^ !BYTES_BIG_ENDIAN
)
29913 x
= op0
, op0
= op1
, op1
= x
;
29914 if (imode
!= V16QImode
)
29916 op0
= gen_lowpart (imode
, op0
);
29917 op1
= gen_lowpart (imode
, op1
);
29919 if (omode
== V16QImode
)
29922 x
= gen_reg_rtx (omode
);
29923 emit_insn (GEN_FCN (icode
) (x
, op0
, op1
));
29924 if (omode
!= V16QImode
)
29925 emit_move_insn (target
, gen_lowpart (V16QImode
, x
));
29930 if (!BYTES_BIG_ENDIAN
)
29932 altivec_expand_vec_perm_const_le (operands
);
29939 /* Expand a Paired Single, VSX Permute Doubleword, or SPE constant permutation.
29940 Return true if we match an efficient implementation. */
29943 rs6000_expand_vec_perm_const_1 (rtx target
, rtx op0
, rtx op1
,
29944 unsigned char perm0
, unsigned char perm1
)
29948 /* If both selectors come from the same operand, fold to single op. */
29949 if ((perm0
& 2) == (perm1
& 2))
29956 /* If both operands are equal, fold to simpler permutation. */
29957 if (rtx_equal_p (op0
, op1
))
29960 perm1
= (perm1
& 1) + 2;
29962 /* If the first selector comes from the second operand, swap. */
29963 else if (perm0
& 2)
29969 x
= op0
, op0
= op1
, op1
= x
;
29971 /* If the second selector does not come from the second operand, fail. */
29972 else if ((perm1
& 2) == 0)
29976 if (target
!= NULL
)
29978 enum machine_mode vmode
, dmode
;
29981 vmode
= GET_MODE (target
);
29982 gcc_assert (GET_MODE_NUNITS (vmode
) == 2);
29983 dmode
= mode_for_vector (GET_MODE_INNER (vmode
), 4);
29985 x
= gen_rtx_VEC_CONCAT (dmode
, op0
, op1
);
29986 v
= gen_rtvec (2, GEN_INT (perm0
), GEN_INT (perm1
));
29987 x
= gen_rtx_VEC_SELECT (vmode
, x
, gen_rtx_PARALLEL (VOIDmode
, v
));
29988 emit_insn (gen_rtx_SET (VOIDmode
, target
, x
));
29994 rs6000_expand_vec_perm_const (rtx operands
[4])
29996 rtx target
, op0
, op1
, sel
;
29997 unsigned char perm0
, perm1
;
29999 target
= operands
[0];
30004 /* Unpack the constant selector. */
30005 perm0
= INTVAL (XVECEXP (sel
, 0, 0)) & 3;
30006 perm1
= INTVAL (XVECEXP (sel
, 0, 1)) & 3;
30008 return rs6000_expand_vec_perm_const_1 (target
, op0
, op1
, perm0
, perm1
);
30011 /* Test whether a constant permutation is supported. */
30014 rs6000_vectorize_vec_perm_const_ok (enum machine_mode vmode
,
30015 const unsigned char *sel
)
30017 /* AltiVec (and thus VSX) can handle arbitrary permutations. */
30018 if (TARGET_ALTIVEC
)
30021 /* Check for ps_merge* or evmerge* insns. */
30022 if ((TARGET_PAIRED_FLOAT
&& vmode
== V2SFmode
)
30023 || (TARGET_SPE
&& vmode
== V2SImode
))
30025 rtx op0
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 1);
30026 rtx op1
= gen_raw_REG (vmode
, LAST_VIRTUAL_REGISTER
+ 2);
30027 return rs6000_expand_vec_perm_const_1 (NULL
, op0
, op1
, sel
[0], sel
[1]);
30033 /* A subroutine for rs6000_expand_extract_even & rs6000_expand_interleave. */
30036 rs6000_do_expand_vec_perm (rtx target
, rtx op0
, rtx op1
,
30037 enum machine_mode vmode
, unsigned nelt
, rtx perm
[])
30039 enum machine_mode imode
;
30043 if (GET_MODE_CLASS (vmode
) != MODE_VECTOR_INT
)
30045 imode
= GET_MODE_INNER (vmode
);
30046 imode
= mode_for_size (GET_MODE_BITSIZE (imode
), MODE_INT
, 0);
30047 imode
= mode_for_vector (imode
, nelt
);
30050 x
= gen_rtx_CONST_VECTOR (imode
, gen_rtvec_v (nelt
, perm
));
30051 x
= expand_vec_perm (vmode
, op0
, op1
, x
, target
);
30053 emit_move_insn (target
, x
);
30056 /* Expand an extract even operation. */
30059 rs6000_expand_extract_even (rtx target
, rtx op0
, rtx op1
)
30061 enum machine_mode vmode
= GET_MODE (target
);
30062 unsigned i
, nelt
= GET_MODE_NUNITS (vmode
);
30065 for (i
= 0; i
< nelt
; i
++)
30066 perm
[i
] = GEN_INT (i
* 2);
30068 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30071 /* Expand a vector interleave operation. */
30074 rs6000_expand_interleave (rtx target
, rtx op0
, rtx op1
, bool highp
)
30076 enum machine_mode vmode
= GET_MODE (target
);
30077 unsigned i
, high
, nelt
= GET_MODE_NUNITS (vmode
);
30080 high
= (highp
== BYTES_BIG_ENDIAN
? 0 : nelt
/ 2);
30081 for (i
= 0; i
< nelt
/ 2; i
++)
30083 perm
[i
* 2] = GEN_INT (i
+ high
);
30084 perm
[i
* 2 + 1] = GEN_INT (i
+ nelt
+ high
);
30087 rs6000_do_expand_vec_perm (target
, op0
, op1
, vmode
, nelt
, perm
);
30090 /* Return an RTX representing where to find the function value of a
30091 function returning MODE. */
30093 rs6000_complex_function_value (enum machine_mode mode
)
30095 unsigned int regno
;
30097 enum machine_mode inner
= GET_MODE_INNER (mode
);
30098 unsigned int inner_bytes
= GET_MODE_SIZE (inner
);
30100 if (FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30101 regno
= FP_ARG_RETURN
;
30104 regno
= GP_ARG_RETURN
;
30106 /* 32-bit is OK since it'll go in r3/r4. */
30107 if (TARGET_32BIT
&& inner_bytes
>= 4)
30108 return gen_rtx_REG (mode
, regno
);
30111 if (inner_bytes
>= 8)
30112 return gen_rtx_REG (mode
, regno
);
30114 r1
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
),
30116 r2
= gen_rtx_EXPR_LIST (inner
, gen_rtx_REG (inner
, regno
+ 1),
30117 GEN_INT (inner_bytes
));
30118 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, r1
, r2
));
30121 /* Target hook for TARGET_FUNCTION_VALUE.
30123 On the SPE, both FPs and vectors are returned in r3.
30125 On RS/6000 an integer value is in r3 and a floating-point value is in
30126 fp1, unless -msoft-float. */
30129 rs6000_function_value (const_tree valtype
,
30130 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
30131 bool outgoing ATTRIBUTE_UNUSED
)
30133 enum machine_mode mode
;
30134 unsigned int regno
;
30135 enum machine_mode elt_mode
;
30138 /* Special handling for structs in darwin64. */
30140 && rs6000_darwin64_struct_check_p (TYPE_MODE (valtype
), valtype
))
30142 CUMULATIVE_ARGS valcum
;
30146 valcum
.fregno
= FP_ARG_MIN_REG
;
30147 valcum
.vregno
= ALTIVEC_ARG_MIN_REG
;
30148 /* Do a trial code generation as if this were going to be passed as
30149 an argument; if any part goes in memory, we return NULL. */
30150 valret
= rs6000_darwin64_record_arg (&valcum
, valtype
, true, /* retval= */ true);
30153 /* Otherwise fall through to standard ABI rules. */
30156 /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */
30157 if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype
), valtype
,
30158 &elt_mode
, &n_elts
))
30160 int first_reg
, n_regs
, i
;
30163 if (SCALAR_FLOAT_MODE_P (elt_mode
))
30165 /* _Decimal128 must use even/odd register pairs. */
30166 first_reg
= (elt_mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30167 n_regs
= (GET_MODE_SIZE (elt_mode
) + 7) >> 3;
30171 first_reg
= ALTIVEC_ARG_RETURN
;
30175 par
= gen_rtx_PARALLEL (TYPE_MODE (valtype
), rtvec_alloc (n_elts
));
30176 for (i
= 0; i
< n_elts
; i
++)
30178 rtx r
= gen_rtx_REG (elt_mode
, first_reg
+ i
* n_regs
);
30179 rtx off
= GEN_INT (i
* GET_MODE_SIZE (elt_mode
));
30180 XVECEXP (par
, 0, i
) = gen_rtx_EXPR_LIST (VOIDmode
, r
, off
);
30186 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DImode
)
30188 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30189 return gen_rtx_PARALLEL (DImode
,
30191 gen_rtx_EXPR_LIST (VOIDmode
,
30192 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30194 gen_rtx_EXPR_LIST (VOIDmode
,
30195 gen_rtx_REG (SImode
,
30196 GP_ARG_RETURN
+ 1),
30199 if (TARGET_32BIT
&& TARGET_POWERPC64
&& TYPE_MODE (valtype
) == DCmode
)
30201 return gen_rtx_PARALLEL (DCmode
,
30203 gen_rtx_EXPR_LIST (VOIDmode
,
30204 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30206 gen_rtx_EXPR_LIST (VOIDmode
,
30207 gen_rtx_REG (SImode
,
30208 GP_ARG_RETURN
+ 1),
30210 gen_rtx_EXPR_LIST (VOIDmode
,
30211 gen_rtx_REG (SImode
,
30212 GP_ARG_RETURN
+ 2),
30214 gen_rtx_EXPR_LIST (VOIDmode
,
30215 gen_rtx_REG (SImode
,
30216 GP_ARG_RETURN
+ 3),
30220 mode
= TYPE_MODE (valtype
);
30221 if ((INTEGRAL_TYPE_P (valtype
) && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
)
30222 || POINTER_TYPE_P (valtype
))
30223 mode
= TARGET_32BIT
? SImode
: DImode
;
30225 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30226 /* _Decimal128 must use an even/odd register pair. */
30227 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30228 else if (SCALAR_FLOAT_TYPE_P (valtype
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
30229 && ((TARGET_SINGLE_FLOAT
&& (mode
== SFmode
)) || TARGET_DOUBLE_FLOAT
))
30230 regno
= FP_ARG_RETURN
;
30231 else if (TREE_CODE (valtype
) == COMPLEX_TYPE
30232 && targetm
.calls
.split_complex_arg
)
30233 return rs6000_complex_function_value (mode
);
30234 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30235 return register is used in both cases, and we won't see V2DImode/V2DFmode
30236 for pure altivec, combine the two cases. */
30237 else if (TREE_CODE (valtype
) == VECTOR_TYPE
30238 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
30239 && ALTIVEC_OR_VSX_VECTOR_MODE (mode
))
30240 regno
= ALTIVEC_ARG_RETURN
;
30241 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30242 && (mode
== DFmode
|| mode
== DCmode
30243 || mode
== TFmode
|| mode
== TCmode
))
30244 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30246 regno
= GP_ARG_RETURN
;
30248 return gen_rtx_REG (mode
, regno
);
30251 /* Define how to find the value returned by a library function
30252 assuming the value has mode MODE. */
30254 rs6000_libcall_value (enum machine_mode mode
)
30256 unsigned int regno
;
30258 if (TARGET_32BIT
&& TARGET_POWERPC64
&& mode
== DImode
)
30260 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
30261 return gen_rtx_PARALLEL (DImode
,
30263 gen_rtx_EXPR_LIST (VOIDmode
,
30264 gen_rtx_REG (SImode
, GP_ARG_RETURN
),
30266 gen_rtx_EXPR_LIST (VOIDmode
,
30267 gen_rtx_REG (SImode
,
30268 GP_ARG_RETURN
+ 1),
30272 if (DECIMAL_FLOAT_MODE_P (mode
) && TARGET_HARD_FLOAT
&& TARGET_FPRS
)
30273 /* _Decimal128 must use an even/odd register pair. */
30274 regno
= (mode
== TDmode
) ? FP_ARG_RETURN
+ 1 : FP_ARG_RETURN
;
30275 else if (SCALAR_FLOAT_MODE_P (mode
)
30276 && TARGET_HARD_FLOAT
&& TARGET_FPRS
30277 && ((TARGET_SINGLE_FLOAT
&& mode
== SFmode
) || TARGET_DOUBLE_FLOAT
))
30278 regno
= FP_ARG_RETURN
;
30279 /* VSX is a superset of Altivec and adds V2DImode/V2DFmode. Since the same
30280 return register is used in both cases, and we won't see V2DImode/V2DFmode
30281 for pure altivec, combine the two cases. */
30282 else if (ALTIVEC_OR_VSX_VECTOR_MODE (mode
)
30283 && TARGET_ALTIVEC
&& TARGET_ALTIVEC_ABI
)
30284 regno
= ALTIVEC_ARG_RETURN
;
30285 else if (COMPLEX_MODE_P (mode
) && targetm
.calls
.split_complex_arg
)
30286 return rs6000_complex_function_value (mode
);
30287 else if (TARGET_E500_DOUBLE
&& TARGET_HARD_FLOAT
30288 && (mode
== DFmode
|| mode
== DCmode
30289 || mode
== TFmode
|| mode
== TCmode
))
30290 return spe_build_register_parallel (mode
, GP_ARG_RETURN
);
30292 regno
= GP_ARG_RETURN
;
30294 return gen_rtx_REG (mode
, regno
);
30298 /* Return true if we use LRA instead of reload pass. */
30300 rs6000_lra_p (void)
30302 return rs6000_lra_flag
;
30305 /* Given FROM and TO register numbers, say whether this elimination is allowed.
30306 Frame pointer elimination is automatically handled.
30308 For the RS/6000, if frame pointer elimination is being done, we would like
30309 to convert ap into fp, not sp.
30311 We need r30 if -mminimal-toc was specified, and there are constant pool
30315 rs6000_can_eliminate (const int from
, const int to
)
30317 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
30318 ? ! frame_pointer_needed
30319 : from
== RS6000_PIC_OFFSET_TABLE_REGNUM
30320 ? ! TARGET_MINIMAL_TOC
|| TARGET_NO_TOC
|| get_pool_size () == 0
30324 /* Define the offset between two registers, FROM to be eliminated and its
30325 replacement TO, at the start of a routine. */
30327 rs6000_initial_elimination_offset (int from
, int to
)
30329 rs6000_stack_t
*info
= rs6000_stack_info ();
30330 HOST_WIDE_INT offset
;
30332 if (from
== HARD_FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30333 offset
= info
->push_p
? 0 : -info
->total_size
;
30334 else if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30336 offset
= info
->push_p
? 0 : -info
->total_size
;
30337 if (FRAME_GROWS_DOWNWARD
)
30338 offset
+= info
->fixed_size
+ info
->vars_size
+ info
->parm_size
;
30340 else if (from
== FRAME_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
30341 offset
= FRAME_GROWS_DOWNWARD
30342 ? info
->fixed_size
+ info
->vars_size
+ info
->parm_size
30344 else if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
30345 offset
= info
->total_size
;
30346 else if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
30347 offset
= info
->push_p
? info
->total_size
: 0;
30348 else if (from
== RS6000_PIC_OFFSET_TABLE_REGNUM
)
30351 gcc_unreachable ();
30357 rs6000_dwarf_register_span (rtx reg
)
30361 unsigned regno
= REGNO (reg
);
30362 enum machine_mode mode
= GET_MODE (reg
);
30366 && (SPE_VECTOR_MODE (GET_MODE (reg
))
30367 || (TARGET_E500_DOUBLE
&& FLOAT_MODE_P (mode
)
30368 && mode
!= SFmode
&& mode
!= SDmode
&& mode
!= SCmode
)))
30373 regno
= REGNO (reg
);
30375 /* The duality of the SPE register size wreaks all kinds of havoc.
30376 This is a way of distinguishing r0 in 32-bits from r0 in
30378 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_FP_WORD
- 1) / UNITS_PER_FP_WORD
;
30379 gcc_assert (words
<= 4);
30380 for (i
= 0; i
< words
; i
++, regno
++)
30382 if (BYTES_BIG_ENDIAN
)
30384 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
+ 1200);
30385 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
);
30389 parts
[2 * i
] = gen_rtx_REG (SImode
, regno
);
30390 parts
[2 * i
+ 1] = gen_rtx_REG (SImode
, regno
+ 1200);
30394 return gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (words
* 2, parts
));
30397 /* Fill in sizes for SPE register high parts in table used by unwinder. */
30400 rs6000_init_dwarf_reg_sizes_extra (tree address
)
30405 enum machine_mode mode
= TYPE_MODE (char_type_node
);
30406 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
30407 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
30408 rtx value
= gen_int_mode (4, mode
);
30410 for (i
= 1201; i
< 1232; i
++)
30412 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
30413 HOST_WIDE_INT offset
30414 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
30416 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
30420 if (TARGET_MACHO
&& ! TARGET_ALTIVEC
)
30423 enum machine_mode mode
= TYPE_MODE (char_type_node
);
30424 rtx addr
= expand_expr (address
, NULL_RTX
, VOIDmode
, EXPAND_NORMAL
);
30425 rtx mem
= gen_rtx_MEM (BLKmode
, addr
);
30426 rtx value
= gen_int_mode (16, mode
);
30428 /* On Darwin, libgcc may be built to run on both G3 and G4/5.
30429 The unwinder still needs to know the size of Altivec registers. */
30431 for (i
= FIRST_ALTIVEC_REGNO
; i
< LAST_ALTIVEC_REGNO
+1; i
++)
30433 int column
= DWARF_REG_TO_UNWIND_COLUMN (i
);
30434 HOST_WIDE_INT offset
30435 = DWARF_FRAME_REGNUM (column
) * GET_MODE_SIZE (mode
);
30437 emit_move_insn (adjust_address (mem
, mode
, offset
), value
);
30442 /* Map internal gcc register numbers to DWARF2 register numbers. */
30445 rs6000_dbx_register_number (unsigned int regno
)
30447 if (regno
<= 63 || write_symbols
!= DWARF2_DEBUG
)
30449 if (regno
== LR_REGNO
)
30451 if (regno
== CTR_REGNO
)
30453 if (CR_REGNO_P (regno
))
30454 return regno
- CR0_REGNO
+ 86;
30455 if (regno
== CA_REGNO
)
30456 return 101; /* XER */
30457 if (ALTIVEC_REGNO_P (regno
))
30458 return regno
- FIRST_ALTIVEC_REGNO
+ 1124;
30459 if (regno
== VRSAVE_REGNO
)
30461 if (regno
== VSCR_REGNO
)
30463 if (regno
== SPE_ACC_REGNO
)
30465 if (regno
== SPEFSCR_REGNO
)
30467 /* SPE high reg number. We get these values of regno from
30468 rs6000_dwarf_register_span. */
30469 gcc_assert (regno
>= 1200 && regno
< 1232);
30473 /* target hook eh_return_filter_mode */
30474 static enum machine_mode
30475 rs6000_eh_return_filter_mode (void)
30477 return TARGET_32BIT
? SImode
: word_mode
;
30480 /* Target hook for scalar_mode_supported_p. */
30482 rs6000_scalar_mode_supported_p (enum machine_mode mode
)
30484 if (DECIMAL_FLOAT_MODE_P (mode
))
30485 return default_decimal_float_supported_p ();
30487 return default_scalar_mode_supported_p (mode
);
30490 /* Target hook for vector_mode_supported_p. */
30492 rs6000_vector_mode_supported_p (enum machine_mode mode
)
30495 if (TARGET_PAIRED_FLOAT
&& PAIRED_VECTOR_MODE (mode
))
30498 if (TARGET_SPE
&& SPE_VECTOR_MODE (mode
))
30501 else if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode
))
30508 /* Target hook for invalid_arg_for_unprototyped_fn. */
30509 static const char *
30510 invalid_arg_for_unprototyped_fn (const_tree typelist
, const_tree funcdecl
, const_tree val
)
30512 return (!rs6000_darwin64_abi
30514 && TREE_CODE (TREE_TYPE (val
)) == VECTOR_TYPE
30515 && (funcdecl
== NULL_TREE
30516 || (TREE_CODE (funcdecl
) == FUNCTION_DECL
30517 && DECL_BUILT_IN_CLASS (funcdecl
) != BUILT_IN_MD
)))
30518 ? N_("AltiVec argument passed to unprototyped function")
30522 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
30523 setup by using __stack_chk_fail_local hidden function instead of
30524 calling __stack_chk_fail directly. Otherwise it is better to call
30525 __stack_chk_fail directly. */
30527 static tree ATTRIBUTE_UNUSED
30528 rs6000_stack_protect_fail (void)
30530 return (DEFAULT_ABI
== ABI_V4
&& TARGET_SECURE_PLT
&& flag_pic
)
30531 ? default_hidden_stack_protect_fail ()
30532 : default_external_stack_protect_fail ();
30536 rs6000_final_prescan_insn (rtx insn
, rtx
*operand ATTRIBUTE_UNUSED
,
30537 int num_operands ATTRIBUTE_UNUSED
)
30539 if (rs6000_warn_cell_microcode
)
30542 int insn_code_number
= recog_memoized (insn
);
30543 location_t location
= INSN_LOCATION (insn
);
30545 /* Punt on insns we cannot recognize. */
30546 if (insn_code_number
< 0)
30549 temp
= get_insn_template (insn_code_number
, insn
);
30551 if (get_attr_cell_micro (insn
) == CELL_MICRO_ALWAYS
)
30552 warning_at (location
, OPT_mwarn_cell_microcode
,
30553 "emitting microcode insn %s\t[%s] #%d",
30554 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
30555 else if (get_attr_cell_micro (insn
) == CELL_MICRO_CONDITIONAL
)
30556 warning_at (location
, OPT_mwarn_cell_microcode
,
30557 "emitting conditional microcode insn %s\t[%s] #%d",
30558 temp
, insn_data
[INSN_CODE (insn
)].name
, INSN_UID (insn
));
30562 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
30565 static unsigned HOST_WIDE_INT
30566 rs6000_asan_shadow_offset (void)
30568 return (unsigned HOST_WIDE_INT
) 1 << (TARGET_64BIT
? 41 : 29);
30572 /* Mask options that we want to support inside of attribute((target)) and
30573 #pragma GCC target operations. Note, we do not include things like
30574 64/32-bit, endianess, hard/soft floating point, etc. that would have
30575 different calling sequences. */
30577 struct rs6000_opt_mask
{
30578 const char *name
; /* option name */
30579 HOST_WIDE_INT mask
; /* mask to set */
30580 bool invert
; /* invert sense of mask */
30581 bool valid_target
; /* option is a target option */
30584 static struct rs6000_opt_mask
const rs6000_opt_masks
[] =
30586 { "altivec", OPTION_MASK_ALTIVEC
, false, true },
30587 { "cmpb", OPTION_MASK_CMPB
, false, true },
30588 { "crypto", OPTION_MASK_CRYPTO
, false, true },
30589 { "direct-move", OPTION_MASK_DIRECT_MOVE
, false, true },
30590 { "dlmzb", OPTION_MASK_DLMZB
, false, true },
30591 { "fprnd", OPTION_MASK_FPRND
, false, true },
30592 { "hard-dfp", OPTION_MASK_DFP
, false, true },
30593 { "htm", OPTION_MASK_HTM
, false, true },
30594 { "isel", OPTION_MASK_ISEL
, false, true },
30595 { "mfcrf", OPTION_MASK_MFCRF
, false, true },
30596 { "mfpgpr", OPTION_MASK_MFPGPR
, false, true },
30597 { "mulhw", OPTION_MASK_MULHW
, false, true },
30598 { "multiple", OPTION_MASK_MULTIPLE
, false, true },
30599 { "popcntb", OPTION_MASK_POPCNTB
, false, true },
30600 { "popcntd", OPTION_MASK_POPCNTD
, false, true },
30601 { "power8-fusion", OPTION_MASK_P8_FUSION
, false, true },
30602 { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN
, false, true },
30603 { "power8-vector", OPTION_MASK_P8_VECTOR
, false, true },
30604 { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT
, false, true },
30605 { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT
, false, true },
30606 { "quad-memory", OPTION_MASK_QUAD_MEMORY
, false, true },
30607 { "recip-precision", OPTION_MASK_RECIP_PRECISION
, false, true },
30608 { "string", OPTION_MASK_STRING
, false, true },
30609 { "update", OPTION_MASK_NO_UPDATE
, true , true },
30610 { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF
, false, false },
30611 { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF
, false, false },
30612 { "vsx", OPTION_MASK_VSX
, false, true },
30613 { "vsx-timode", OPTION_MASK_VSX_TIMODE
, false, true },
30614 #ifdef OPTION_MASK_64BIT
30616 { "aix64", OPTION_MASK_64BIT
, false, false },
30617 { "aix32", OPTION_MASK_64BIT
, true, false },
30619 { "64", OPTION_MASK_64BIT
, false, false },
30620 { "32", OPTION_MASK_64BIT
, true, false },
30623 #ifdef OPTION_MASK_EABI
30624 { "eabi", OPTION_MASK_EABI
, false, false },
30626 #ifdef OPTION_MASK_LITTLE_ENDIAN
30627 { "little", OPTION_MASK_LITTLE_ENDIAN
, false, false },
30628 { "big", OPTION_MASK_LITTLE_ENDIAN
, true, false },
30630 #ifdef OPTION_MASK_RELOCATABLE
30631 { "relocatable", OPTION_MASK_RELOCATABLE
, false, false },
30633 #ifdef OPTION_MASK_STRICT_ALIGN
30634 { "strict-align", OPTION_MASK_STRICT_ALIGN
, false, false },
30636 { "soft-float", OPTION_MASK_SOFT_FLOAT
, false, false },
30637 { "string", OPTION_MASK_STRING
, false, false },
30640 /* Builtin mask mapping for printing the flags. */
30641 static struct rs6000_opt_mask
const rs6000_builtin_mask_names
[] =
30643 { "altivec", RS6000_BTM_ALTIVEC
, false, false },
30644 { "vsx", RS6000_BTM_VSX
, false, false },
30645 { "spe", RS6000_BTM_SPE
, false, false },
30646 { "paired", RS6000_BTM_PAIRED
, false, false },
30647 { "fre", RS6000_BTM_FRE
, false, false },
30648 { "fres", RS6000_BTM_FRES
, false, false },
30649 { "frsqrte", RS6000_BTM_FRSQRTE
, false, false },
30650 { "frsqrtes", RS6000_BTM_FRSQRTES
, false, false },
30651 { "popcntd", RS6000_BTM_POPCNTD
, false, false },
30652 { "cell", RS6000_BTM_CELL
, false, false },
30653 { "power8-vector", RS6000_BTM_P8_VECTOR
, false, false },
30654 { "crypto", RS6000_BTM_CRYPTO
, false, false },
30655 { "htm", RS6000_BTM_HTM
, false, false },
30658 /* Option variables that we want to support inside attribute((target)) and
30659 #pragma GCC target operations. */
30661 struct rs6000_opt_var
{
30662 const char *name
; /* option name */
30663 size_t global_offset
; /* offset of the option in global_options. */
30664 size_t target_offset
; /* offset of the option in target optiosn. */
30667 static struct rs6000_opt_var
const rs6000_opt_vars
[] =
30670 offsetof (struct gcc_options
, x_TARGET_FRIZ
),
30671 offsetof (struct cl_target_option
, x_TARGET_FRIZ
), },
30672 { "avoid-indexed-addresses",
30673 offsetof (struct gcc_options
, x_TARGET_AVOID_XFORM
),
30674 offsetof (struct cl_target_option
, x_TARGET_AVOID_XFORM
) },
30676 offsetof (struct gcc_options
, x_rs6000_paired_float
),
30677 offsetof (struct cl_target_option
, x_rs6000_paired_float
), },
30679 offsetof (struct gcc_options
, x_rs6000_default_long_calls
),
30680 offsetof (struct cl_target_option
, x_rs6000_default_long_calls
), },
30683 /* Inner function to handle attribute((target("..."))) and #pragma GCC target
30684 parsing. Return true if there were no errors. */
30687 rs6000_inner_target_options (tree args
, bool attr_p
)
30691 if (args
== NULL_TREE
)
30694 else if (TREE_CODE (args
) == STRING_CST
)
30696 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
30699 while ((q
= strtok (p
, ",")) != NULL
)
30701 bool error_p
= false;
30702 bool not_valid_p
= false;
30703 const char *cpu_opt
= NULL
;
30706 if (strncmp (q
, "cpu=", 4) == 0)
30708 int cpu_index
= rs6000_cpu_name_lookup (q
+4);
30709 if (cpu_index
>= 0)
30710 rs6000_cpu_index
= cpu_index
;
30717 else if (strncmp (q
, "tune=", 5) == 0)
30719 int tune_index
= rs6000_cpu_name_lookup (q
+5);
30720 if (tune_index
>= 0)
30721 rs6000_tune_index
= tune_index
;
30731 bool invert
= false;
30735 if (strncmp (r
, "no-", 3) == 0)
30741 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_masks
); i
++)
30742 if (strcmp (r
, rs6000_opt_masks
[i
].name
) == 0)
30744 HOST_WIDE_INT mask
= rs6000_opt_masks
[i
].mask
;
30746 if (!rs6000_opt_masks
[i
].valid_target
)
30747 not_valid_p
= true;
30751 rs6000_isa_flags_explicit
|= mask
;
30753 /* VSX needs altivec, so -mvsx automagically sets
30755 if (mask
== OPTION_MASK_VSX
&& !invert
)
30756 mask
|= OPTION_MASK_ALTIVEC
;
30758 if (rs6000_opt_masks
[i
].invert
)
30762 rs6000_isa_flags
&= ~mask
;
30764 rs6000_isa_flags
|= mask
;
30769 if (error_p
&& !not_valid_p
)
30771 for (i
= 0; i
< ARRAY_SIZE (rs6000_opt_vars
); i
++)
30772 if (strcmp (r
, rs6000_opt_vars
[i
].name
) == 0)
30774 size_t j
= rs6000_opt_vars
[i
].global_offset
;
30775 *((int *) ((char *)&global_options
+ j
)) = !invert
;
30784 const char *eprefix
, *esuffix
;
30789 eprefix
= "__attribute__((__target__(";
30794 eprefix
= "#pragma GCC target ";
30799 error ("invalid cpu \"%s\" for %s\"%s\"%s", cpu_opt
, eprefix
,
30801 else if (not_valid_p
)
30802 error ("%s\"%s\"%s is not allowed", eprefix
, q
, esuffix
);
30804 error ("%s\"%s\"%s is invalid", eprefix
, q
, esuffix
);
30809 else if (TREE_CODE (args
) == TREE_LIST
)
30813 tree value
= TREE_VALUE (args
);
30816 bool ret2
= rs6000_inner_target_options (value
, attr_p
);
30820 args
= TREE_CHAIN (args
);
30822 while (args
!= NULL_TREE
);
30826 gcc_unreachable ();
30831 /* Print out the target options as a list for -mdebug=target. */
30834 rs6000_debug_target_options (tree args
, const char *prefix
)
30836 if (args
== NULL_TREE
)
30837 fprintf (stderr
, "%s<NULL>", prefix
);
30839 else if (TREE_CODE (args
) == STRING_CST
)
30841 char *p
= ASTRDUP (TREE_STRING_POINTER (args
));
30844 while ((q
= strtok (p
, ",")) != NULL
)
30847 fprintf (stderr
, "%s\"%s\"", prefix
, q
);
30852 else if (TREE_CODE (args
) == TREE_LIST
)
30856 tree value
= TREE_VALUE (args
);
30859 rs6000_debug_target_options (value
, prefix
);
30862 args
= TREE_CHAIN (args
);
30864 while (args
!= NULL_TREE
);
30868 gcc_unreachable ();
30874 /* Hook to validate attribute((target("..."))). */
30877 rs6000_valid_attribute_p (tree fndecl
,
30878 tree
ARG_UNUSED (name
),
30882 struct cl_target_option cur_target
;
30884 tree old_optimize
= build_optimization_node (&global_options
);
30885 tree new_target
, new_optimize
;
30886 tree func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
30888 gcc_assert ((fndecl
!= NULL_TREE
) && (args
!= NULL_TREE
));
30890 if (TARGET_DEBUG_TARGET
)
30892 tree tname
= DECL_NAME (fndecl
);
30893 fprintf (stderr
, "\n==================== rs6000_valid_attribute_p:\n");
30895 fprintf (stderr
, "function: %.*s\n",
30896 (int) IDENTIFIER_LENGTH (tname
),
30897 IDENTIFIER_POINTER (tname
));
30899 fprintf (stderr
, "function: unknown\n");
30901 fprintf (stderr
, "args:");
30902 rs6000_debug_target_options (args
, " ");
30903 fprintf (stderr
, "\n");
30906 fprintf (stderr
, "flags: 0x%x\n", flags
);
30908 fprintf (stderr
, "--------------------\n");
30911 old_optimize
= build_optimization_node (&global_options
);
30912 func_optimize
= DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
);
30914 /* If the function changed the optimization levels as well as setting target
30915 options, start with the optimizations specified. */
30916 if (func_optimize
&& func_optimize
!= old_optimize
)
30917 cl_optimization_restore (&global_options
,
30918 TREE_OPTIMIZATION (func_optimize
));
30920 /* The target attributes may also change some optimization flags, so update
30921 the optimization options if necessary. */
30922 cl_target_option_save (&cur_target
, &global_options
);
30923 rs6000_cpu_index
= rs6000_tune_index
= -1;
30924 ret
= rs6000_inner_target_options (args
, true);
30926 /* Set up any additional state. */
30929 ret
= rs6000_option_override_internal (false);
30930 new_target
= build_target_option_node (&global_options
);
30935 new_optimize
= build_optimization_node (&global_options
);
30942 DECL_FUNCTION_SPECIFIC_TARGET (fndecl
) = new_target
;
30944 if (old_optimize
!= new_optimize
)
30945 DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl
) = new_optimize
;
30948 cl_target_option_restore (&global_options
, &cur_target
);
30950 if (old_optimize
!= new_optimize
)
30951 cl_optimization_restore (&global_options
,
30952 TREE_OPTIMIZATION (old_optimize
));
30958 /* Hook to validate the current #pragma GCC target and set the state, and
30959 update the macros based on what was changed. If ARGS is NULL, then
30960 POP_TARGET is used to reset the options. */
30963 rs6000_pragma_target_parse (tree args
, tree pop_target
)
30965 tree prev_tree
= build_target_option_node (&global_options
);
30967 struct cl_target_option
*prev_opt
, *cur_opt
;
30968 HOST_WIDE_INT prev_flags
, cur_flags
, diff_flags
;
30969 HOST_WIDE_INT prev_bumask
, cur_bumask
, diff_bumask
;
30971 if (TARGET_DEBUG_TARGET
)
30973 fprintf (stderr
, "\n==================== rs6000_pragma_target_parse\n");
30974 fprintf (stderr
, "args:");
30975 rs6000_debug_target_options (args
, " ");
30976 fprintf (stderr
, "\n");
30980 fprintf (stderr
, "pop_target:\n");
30981 debug_tree (pop_target
);
30984 fprintf (stderr
, "pop_target: <NULL>\n");
30986 fprintf (stderr
, "--------------------\n");
30991 cur_tree
= ((pop_target
)
30993 : target_option_default_node
);
30994 cl_target_option_restore (&global_options
,
30995 TREE_TARGET_OPTION (cur_tree
));
30999 rs6000_cpu_index
= rs6000_tune_index
= -1;
31000 if (!rs6000_inner_target_options (args
, false)
31001 || !rs6000_option_override_internal (false)
31002 || (cur_tree
= build_target_option_node (&global_options
))
31005 if (TARGET_DEBUG_BUILTIN
|| TARGET_DEBUG_TARGET
)
31006 fprintf (stderr
, "invalid pragma\n");
31012 target_option_current_node
= cur_tree
;
31014 /* If we have the preprocessor linked in (i.e. C or C++ languages), possibly
31015 change the macros that are defined. */
31016 if (rs6000_target_modify_macros_ptr
)
31018 prev_opt
= TREE_TARGET_OPTION (prev_tree
);
31019 prev_bumask
= prev_opt
->x_rs6000_builtin_mask
;
31020 prev_flags
= prev_opt
->x_rs6000_isa_flags
;
31022 cur_opt
= TREE_TARGET_OPTION (cur_tree
);
31023 cur_flags
= cur_opt
->x_rs6000_isa_flags
;
31024 cur_bumask
= cur_opt
->x_rs6000_builtin_mask
;
31026 diff_bumask
= (prev_bumask
^ cur_bumask
);
31027 diff_flags
= (prev_flags
^ cur_flags
);
31029 if ((diff_flags
!= 0) || (diff_bumask
!= 0))
31031 /* Delete old macros. */
31032 rs6000_target_modify_macros_ptr (false,
31033 prev_flags
& diff_flags
,
31034 prev_bumask
& diff_bumask
);
31036 /* Define new macros. */
31037 rs6000_target_modify_macros_ptr (true,
31038 cur_flags
& diff_flags
,
31039 cur_bumask
& diff_bumask
);
31047 /* Remember the last target of rs6000_set_current_function. */
31048 static GTY(()) tree rs6000_previous_fndecl
;
31050 /* Establish appropriate back-end context for processing the function
31051 FNDECL. The argument might be NULL to indicate processing at top
31052 level, outside of any function scope. */
31054 rs6000_set_current_function (tree fndecl
)
31056 tree old_tree
= (rs6000_previous_fndecl
31057 ? DECL_FUNCTION_SPECIFIC_TARGET (rs6000_previous_fndecl
)
31060 tree new_tree
= (fndecl
31061 ? DECL_FUNCTION_SPECIFIC_TARGET (fndecl
)
31064 if (TARGET_DEBUG_TARGET
)
31066 bool print_final
= false;
31067 fprintf (stderr
, "\n==================== rs6000_set_current_function");
31070 fprintf (stderr
, ", fndecl %s (%p)",
31071 (DECL_NAME (fndecl
)
31072 ? IDENTIFIER_POINTER (DECL_NAME (fndecl
))
31073 : "<unknown>"), (void *)fndecl
);
31075 if (rs6000_previous_fndecl
)
31076 fprintf (stderr
, ", prev_fndecl (%p)", (void *)rs6000_previous_fndecl
);
31078 fprintf (stderr
, "\n");
31081 fprintf (stderr
, "\nnew fndecl target specific options:\n");
31082 debug_tree (new_tree
);
31083 print_final
= true;
31088 fprintf (stderr
, "\nold fndecl target specific options:\n");
31089 debug_tree (old_tree
);
31090 print_final
= true;
31094 fprintf (stderr
, "--------------------\n");
31097 /* Only change the context if the function changes. This hook is called
31098 several times in the course of compiling a function, and we don't want to
31099 slow things down too much or call target_reinit when it isn't safe. */
31100 if (fndecl
&& fndecl
!= rs6000_previous_fndecl
)
31102 rs6000_previous_fndecl
= fndecl
;
31103 if (old_tree
== new_tree
)
31108 cl_target_option_restore (&global_options
,
31109 TREE_TARGET_OPTION (new_tree
));
31115 struct cl_target_option
*def
31116 = TREE_TARGET_OPTION (target_option_current_node
);
31118 cl_target_option_restore (&global_options
, def
);
31125 /* Save the current options */
31128 rs6000_function_specific_save (struct cl_target_option
*ptr
,
31129 struct gcc_options
*opts
)
31131 ptr
->x_rs6000_isa_flags
= opts
->x_rs6000_isa_flags
;
31132 ptr
->x_rs6000_isa_flags_explicit
= opts
->x_rs6000_isa_flags_explicit
;
31135 /* Restore the current options */
31138 rs6000_function_specific_restore (struct gcc_options
*opts
,
31139 struct cl_target_option
*ptr
)
31142 opts
->x_rs6000_isa_flags
= ptr
->x_rs6000_isa_flags
;
31143 opts
->x_rs6000_isa_flags_explicit
= ptr
->x_rs6000_isa_flags_explicit
;
31144 (void) rs6000_option_override_internal (false);
31147 /* Print the current options */
31150 rs6000_function_specific_print (FILE *file
, int indent
,
31151 struct cl_target_option
*ptr
)
31153 rs6000_print_isa_options (file
, indent
, "Isa options set",
31154 ptr
->x_rs6000_isa_flags
);
31156 rs6000_print_isa_options (file
, indent
, "Isa options explicit",
31157 ptr
->x_rs6000_isa_flags_explicit
);
31160 /* Helper function to print the current isa or misc options on a line. */
31163 rs6000_print_options_internal (FILE *file
,
31165 const char *string
,
31166 HOST_WIDE_INT flags
,
31167 const char *prefix
,
31168 const struct rs6000_opt_mask
*opts
,
31169 size_t num_elements
)
31172 size_t start_column
= 0;
31174 size_t max_column
= 76;
31175 const char *comma
= "";
31178 start_column
+= fprintf (file
, "%*s", indent
, "");
31182 fprintf (stderr
, DEBUG_FMT_S
, string
, "<none>");
31186 start_column
+= fprintf (stderr
, DEBUG_FMT_WX
, string
, flags
);
31188 /* Print the various mask options. */
31189 cur_column
= start_column
;
31190 for (i
= 0; i
< num_elements
; i
++)
31192 if ((flags
& opts
[i
].mask
) != 0)
31194 const char *no_str
= rs6000_opt_masks
[i
].invert
? "no-" : "";
31195 size_t len
= (strlen (comma
)
31198 + strlen (rs6000_opt_masks
[i
].name
));
31201 if (cur_column
> max_column
)
31203 fprintf (stderr
, ", \\\n%*s", (int)start_column
, "");
31204 cur_column
= start_column
+ len
;
31208 fprintf (file
, "%s%s%s%s", comma
, prefix
, no_str
,
31209 rs6000_opt_masks
[i
].name
);
31210 flags
&= ~ opts
[i
].mask
;
31215 fputs ("\n", file
);
31218 /* Helper function to print the current isa options on a line. */
31221 rs6000_print_isa_options (FILE *file
, int indent
, const char *string
,
31222 HOST_WIDE_INT flags
)
31224 rs6000_print_options_internal (file
, indent
, string
, flags
, "-m",
31225 &rs6000_opt_masks
[0],
31226 ARRAY_SIZE (rs6000_opt_masks
));
31230 rs6000_print_builtin_options (FILE *file
, int indent
, const char *string
,
31231 HOST_WIDE_INT flags
)
31233 rs6000_print_options_internal (file
, indent
, string
, flags
, "",
31234 &rs6000_builtin_mask_names
[0],
31235 ARRAY_SIZE (rs6000_builtin_mask_names
));
31239 /* Hook to determine if one function can safely inline another. */
31242 rs6000_can_inline_p (tree caller
, tree callee
)
31245 tree caller_tree
= DECL_FUNCTION_SPECIFIC_TARGET (caller
);
31246 tree callee_tree
= DECL_FUNCTION_SPECIFIC_TARGET (callee
);
31248 /* If callee has no option attributes, then it is ok to inline. */
31252 /* If caller has no option attributes, but callee does then it is not ok to
31254 else if (!caller_tree
)
31259 struct cl_target_option
*caller_opts
= TREE_TARGET_OPTION (caller_tree
);
31260 struct cl_target_option
*callee_opts
= TREE_TARGET_OPTION (callee_tree
);
31262 /* Callee's options should a subset of the caller's, i.e. a vsx function
31263 can inline an altivec function but a non-vsx function can't inline a
31265 if ((caller_opts
->x_rs6000_isa_flags
& callee_opts
->x_rs6000_isa_flags
)
31266 == callee_opts
->x_rs6000_isa_flags
)
31270 if (TARGET_DEBUG_TARGET
)
31271 fprintf (stderr
, "rs6000_can_inline_p:, caller %s, callee %s, %s inline\n",
31272 (DECL_NAME (caller
)
31273 ? IDENTIFIER_POINTER (DECL_NAME (caller
))
31275 (DECL_NAME (callee
)
31276 ? IDENTIFIER_POINTER (DECL_NAME (callee
))
31278 (ret
? "can" : "cannot"));
31283 /* Allocate a stack temp and fixup the address so it meets the particular
31284 memory requirements (either offetable or REG+REG addressing). */
31287 rs6000_allocate_stack_temp (enum machine_mode mode
,
31288 bool offsettable_p
,
31291 rtx stack
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
31292 rtx addr
= XEXP (stack
, 0);
31293 int strict_p
= (reload_in_progress
|| reload_completed
);
31295 if (!legitimate_indirect_address_p (addr
, strict_p
))
31298 && !rs6000_legitimate_offset_address_p (mode
, addr
, strict_p
, true))
31299 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
31301 else if (reg_reg_p
&& !legitimate_indexed_address_p (addr
, strict_p
))
31302 stack
= replace_equiv_address (stack
, copy_addr_to_reg (addr
));
31308 /* Given a memory reference, if it is not a reg or reg+reg addressing, convert
31309 to such a form to deal with memory reference instructions like STFIWX that
31310 only take reg+reg addressing. */
31313 rs6000_address_for_fpconvert (rtx x
)
31315 int strict_p
= (reload_in_progress
|| reload_completed
);
31318 gcc_assert (MEM_P (x
));
31319 addr
= XEXP (x
, 0);
31320 if (! legitimate_indirect_address_p (addr
, strict_p
)
31321 && ! legitimate_indexed_address_p (addr
, strict_p
))
31323 if (GET_CODE (addr
) == PRE_INC
|| GET_CODE (addr
) == PRE_DEC
)
31325 rtx reg
= XEXP (addr
, 0);
31326 HOST_WIDE_INT size
= GET_MODE_SIZE (GET_MODE (x
));
31327 rtx size_rtx
= GEN_INT ((GET_CODE (addr
) == PRE_DEC
) ? -size
: size
);
31328 gcc_assert (REG_P (reg
));
31329 emit_insn (gen_add3_insn (reg
, reg
, size_rtx
));
31332 else if (GET_CODE (addr
) == PRE_MODIFY
)
31334 rtx reg
= XEXP (addr
, 0);
31335 rtx expr
= XEXP (addr
, 1);
31336 gcc_assert (REG_P (reg
));
31337 gcc_assert (GET_CODE (expr
) == PLUS
);
31338 emit_insn (gen_add3_insn (reg
, XEXP (expr
, 0), XEXP (expr
, 1)));
31342 x
= replace_equiv_address (x
, copy_addr_to_reg (addr
));
31348 /* Given a memory reference, if it is not in the form for altivec memory
31349 reference instructions (i.e. reg or reg+reg addressing with AND of -16),
31350 convert to the altivec format. */
31353 rs6000_address_for_altivec (rtx x
)
31355 gcc_assert (MEM_P (x
));
31356 if (!altivec_indexed_or_indirect_operand (x
, GET_MODE (x
)))
31358 rtx addr
= XEXP (x
, 0);
31359 int strict_p
= (reload_in_progress
|| reload_completed
);
31361 if (!legitimate_indexed_address_p (addr
, strict_p
)
31362 && !legitimate_indirect_address_p (addr
, strict_p
))
31363 addr
= copy_to_mode_reg (Pmode
, addr
);
31365 addr
= gen_rtx_AND (Pmode
, addr
, GEN_INT (-16));
31366 x
= change_address (x
, GET_MODE (x
), addr
);
31372 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
31374 On the RS/6000, all integer constants are acceptable, most won't be valid
31375 for particular insns, though. Only easy FP constants are acceptable. */
31378 rs6000_legitimate_constant_p (enum machine_mode mode
, rtx x
)
31380 if (TARGET_ELF
&& rs6000_tls_referenced_p (x
))
31383 return ((GET_CODE (x
) != CONST_DOUBLE
&& GET_CODE (x
) != CONST_VECTOR
)
31384 || GET_MODE (x
) == VOIDmode
31385 || (TARGET_POWERPC64
&& mode
== DImode
)
31386 || easy_fp_constant (x
, mode
)
31387 || easy_vector_constant (x
, mode
));
31392 /* Expand code to perform a call under the AIX or ELFv2 ABI. */
31395 rs6000_call_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
31397 rtx toc_reg
= gen_rtx_REG (Pmode
, TOC_REGNUM
);
31398 rtx toc_load
= NULL_RTX
;
31399 rtx toc_restore
= NULL_RTX
;
31401 rtx abi_reg
= NULL_RTX
;
31406 /* Handle longcall attributes. */
31407 if (INTVAL (cookie
) & CALL_LONG
)
31408 func_desc
= rs6000_longcall_ref (func_desc
);
31410 /* Handle indirect calls. */
31411 if (GET_CODE (func_desc
) != SYMBOL_REF
31412 || (DEFAULT_ABI
== ABI_AIX
&& !SYMBOL_REF_FUNCTION_P (func_desc
)))
31414 /* Save the TOC into its reserved slot before the call,
31415 and prepare to restore it after the call. */
31416 rtx stack_ptr
= gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
31417 rtx stack_toc_offset
= GEN_INT (RS6000_TOC_SAVE_SLOT
);
31418 rtx stack_toc_mem
= gen_frame_mem (Pmode
,
31419 gen_rtx_PLUS (Pmode
, stack_ptr
,
31420 stack_toc_offset
));
31421 toc_restore
= gen_rtx_SET (VOIDmode
, toc_reg
, stack_toc_mem
);
31423 /* Can we optimize saving the TOC in the prologue or
31424 do we need to do it at every call? */
31425 if (TARGET_SAVE_TOC_INDIRECT
&& !cfun
->calls_alloca
)
31426 cfun
->machine
->save_toc_in_prologue
= true;
31429 MEM_VOLATILE_P (stack_toc_mem
) = 1;
31430 emit_move_insn (stack_toc_mem
, toc_reg
);
31433 if (DEFAULT_ABI
== ABI_ELFv2
)
31435 /* A function pointer in the ELFv2 ABI is just a plain address, but
31436 the ABI requires it to be loaded into r12 before the call. */
31437 func_addr
= gen_rtx_REG (Pmode
, 12);
31438 emit_move_insn (func_addr
, func_desc
);
31439 abi_reg
= func_addr
;
31443 /* A function pointer under AIX is a pointer to a data area whose
31444 first word contains the actual address of the function, whose
31445 second word contains a pointer to its TOC, and whose third word
31446 contains a value to place in the static chain register (r11).
31447 Note that if we load the static chain, our "trampoline" need
31448 not have any executable code. */
31450 /* Load up address of the actual function. */
31451 func_desc
= force_reg (Pmode
, func_desc
);
31452 func_addr
= gen_reg_rtx (Pmode
);
31453 emit_move_insn (func_addr
, gen_rtx_MEM (Pmode
, func_desc
));
31455 /* Prepare to load the TOC of the called function. Note that the
31456 TOC load must happen immediately before the actual call so
31457 that unwinding the TOC registers works correctly. See the
31458 comment in frob_update_context. */
31459 rtx func_toc_offset
= GEN_INT (GET_MODE_SIZE (Pmode
));
31460 rtx func_toc_mem
= gen_rtx_MEM (Pmode
,
31461 gen_rtx_PLUS (Pmode
, func_desc
,
31463 toc_load
= gen_rtx_USE (VOIDmode
, func_toc_mem
);
31465 /* If we have a static chain, load it up. */
31466 if (TARGET_POINTERS_TO_NESTED_FUNCTIONS
)
31468 rtx sc_reg
= gen_rtx_REG (Pmode
, STATIC_CHAIN_REGNUM
);
31469 rtx func_sc_offset
= GEN_INT (2 * GET_MODE_SIZE (Pmode
));
31470 rtx func_sc_mem
= gen_rtx_MEM (Pmode
,
31471 gen_rtx_PLUS (Pmode
, func_desc
,
31473 emit_move_insn (sc_reg
, func_sc_mem
);
31480 /* Direct calls use the TOC: for local calls, the callee will
31481 assume the TOC register is set; for non-local calls, the
31482 PLT stub needs the TOC register. */
31484 func_addr
= func_desc
;
31487 /* Create the call. */
31488 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_addr
), flag
);
31489 if (value
!= NULL_RTX
)
31490 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
31494 call
[n_call
++] = toc_load
;
31496 call
[n_call
++] = toc_restore
;
31498 call
[n_call
++] = gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (Pmode
, LR_REGNO
));
31500 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (n_call
, call
));
31501 insn
= emit_call_insn (insn
);
31503 /* Mention all registers defined by the ABI to hold information
31504 as uses in CALL_INSN_FUNCTION_USAGE. */
31506 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), abi_reg
);
31509 /* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */
31512 rs6000_sibcall_aix (rtx value
, rtx func_desc
, rtx flag
, rtx cookie
)
31517 gcc_assert (INTVAL (cookie
) == 0);
31519 /* Create the call. */
31520 call
[0] = gen_rtx_CALL (VOIDmode
, gen_rtx_MEM (SImode
, func_desc
), flag
);
31521 if (value
!= NULL_RTX
)
31522 call
[0] = gen_rtx_SET (VOIDmode
, value
, call
[0]);
31524 call
[1] = simple_return_rtx
;
31526 insn
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (2, call
));
31527 insn
= emit_call_insn (insn
);
31529 /* Note use of the TOC register. */
31530 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, TOC_REGNUM
));
31531 /* We need to also mark a use of the link register since the function we
31532 sibling-call to will use it to return to our caller. */
31533 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), gen_rtx_REG (Pmode
, LR_REGNO
));
31536 /* Return whether we need to always update the saved TOC pointer when we update
31537 the stack pointer. */
31540 rs6000_save_toc_in_prologue_p (void)
31542 return (cfun
&& cfun
->machine
&& cfun
->machine
->save_toc_in_prologue
);
31545 #ifdef HAVE_GAS_HIDDEN
31546 # define USE_HIDDEN_LINKONCE 1
31548 # define USE_HIDDEN_LINKONCE 0
31551 /* Fills in the label name that should be used for a 476 link stack thunk. */
31554 get_ppc476_thunk_name (char name
[32])
31556 gcc_assert (TARGET_LINK_STACK
);
31558 if (USE_HIDDEN_LINKONCE
)
31559 sprintf (name
, "__ppc476.get_thunk");
31561 ASM_GENERATE_INTERNAL_LABEL (name
, "LPPC476_", 0);
31564 /* This function emits the simple thunk routine that is used to preserve
31565 the link stack on the 476 cpu. */
31567 static void rs6000_code_end (void) ATTRIBUTE_UNUSED
;
31569 rs6000_code_end (void)
31574 if (!TARGET_LINK_STACK
)
31577 get_ppc476_thunk_name (name
);
31579 decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
, get_identifier (name
),
31580 build_function_type_list (void_type_node
, NULL_TREE
));
31581 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
31582 NULL_TREE
, void_type_node
);
31583 TREE_PUBLIC (decl
) = 1;
31584 TREE_STATIC (decl
) = 1;
31587 if (USE_HIDDEN_LINKONCE
)
31589 DECL_COMDAT_GROUP (decl
) = DECL_ASSEMBLER_NAME (decl
);
31590 targetm
.asm_out
.unique_section (decl
, 0);
31591 switch_to_section (get_named_section (decl
, NULL
, 0));
31592 DECL_WEAK (decl
) = 1;
31593 ASM_WEAKEN_DECL (asm_out_file
, decl
, name
, 0);
31594 targetm
.asm_out
.globalize_label (asm_out_file
, name
);
31595 targetm
.asm_out
.assemble_visibility (decl
, VISIBILITY_HIDDEN
);
31596 ASM_DECLARE_FUNCTION_NAME (asm_out_file
, name
, decl
);
31601 switch_to_section (text_section
);
31602 ASM_OUTPUT_LABEL (asm_out_file
, name
);
31605 DECL_INITIAL (decl
) = make_node (BLOCK
);
31606 current_function_decl
= decl
;
31607 init_function_start (decl
);
31608 first_function_block_is_cold
= false;
31609 /* Make sure unwind info is emitted for the thunk if needed. */
31610 final_start_function (emit_barrier (), asm_out_file
, 1);
31612 fputs ("\tblr\n", asm_out_file
);
31614 final_end_function ();
31615 init_insn_lengths ();
31616 free_after_compilation (cfun
);
31618 current_function_decl
= NULL
;
31621 /* Add r30 to hard reg set if the prologue sets it up and it is not
31622 pic_offset_table_rtx. */
31625 rs6000_set_up_by_prologue (struct hard_reg_set_container
*set
)
31627 if (!TARGET_SINGLE_PIC_BASE
31629 && TARGET_MINIMAL_TOC
31630 && get_pool_size () != 0)
31631 add_to_hard_reg_set (&set
->set
, Pmode
, RS6000_PIC_OFFSET_TABLE_REGNUM
);
31635 /* Helper function for rs6000_split_logical to emit a logical instruction after
31636 spliting the operation to single GPR registers.
31638 DEST is the destination register.
31639 OP1 and OP2 are the input source registers.
31640 CODE is the base operation (AND, IOR, XOR, NOT).
31641 MODE is the machine mode.
31642 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31643 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31644 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31645 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31646 formation of the AND instructions. */
31649 rs6000_split_logical_inner (rtx dest
,
31652 enum rtx_code code
,
31653 enum machine_mode mode
,
31654 bool complement_final_p
,
31655 bool complement_op1_p
,
31656 bool complement_op2_p
,
31662 /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */
31663 if (op2
&& GET_CODE (op2
) == CONST_INT
31664 && (mode
== SImode
|| (mode
== DImode
&& TARGET_POWERPC64
))
31665 && !complement_final_p
&& !complement_op1_p
&& !complement_op2_p
)
31667 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
31668 HOST_WIDE_INT value
= INTVAL (op2
) & mask
;
31670 /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */
31675 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
31679 else if (value
== mask
)
31681 if (!rtx_equal_p (dest
, op1
))
31682 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
31687 /* Optimize IOR/XOR of 0 to be a simple move. Split large operations
31688 into separate ORI/ORIS or XORI/XORIS instrucitons. */
31689 else if (code
== IOR
|| code
== XOR
)
31693 if (!rtx_equal_p (dest
, op1
))
31694 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op1
));
31700 if (complement_op1_p
)
31701 op1
= gen_rtx_NOT (mode
, op1
);
31703 if (complement_op2_p
)
31704 op2
= gen_rtx_NOT (mode
, op2
);
31706 bool_rtx
= ((code
== NOT
)
31707 ? gen_rtx_NOT (mode
, op1
)
31708 : gen_rtx_fmt_ee (code
, mode
, op1
, op2
));
31710 if (complement_final_p
)
31711 bool_rtx
= gen_rtx_NOT (mode
, bool_rtx
);
31713 set_rtx
= gen_rtx_SET (VOIDmode
, dest
, bool_rtx
);
31715 /* Is this AND with an explicit clobber? */
31718 rtx clobber
= gen_rtx_CLOBBER (VOIDmode
, clobber_reg
);
31719 set_rtx
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set_rtx
, clobber
));
31722 emit_insn (set_rtx
);
31726 /* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These
31727 operations are split immediately during RTL generation to allow for more
31728 optimizations of the AND/IOR/XOR.
31730 OPERANDS is an array containing the destination and two input operands.
31731 CODE is the base operation (AND, IOR, XOR, NOT).
31732 MODE is the machine mode.
31733 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31734 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31735 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31736 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31737 formation of the AND instructions. */
31740 rs6000_split_logical_di (rtx operands
[3],
31741 enum rtx_code code
,
31742 bool complement_final_p
,
31743 bool complement_op1_p
,
31744 bool complement_op2_p
,
31747 const HOST_WIDE_INT lower_32bits
= HOST_WIDE_INT_C(0xffffffff);
31748 const HOST_WIDE_INT upper_32bits
= ~ lower_32bits
;
31749 const HOST_WIDE_INT sign_bit
= HOST_WIDE_INT_C(0x80000000);
31750 enum hi_lo
{ hi
= 0, lo
= 1 };
31751 rtx op0_hi_lo
[2], op1_hi_lo
[2], op2_hi_lo
[2];
31754 op0_hi_lo
[hi
] = gen_highpart (SImode
, operands
[0]);
31755 op1_hi_lo
[hi
] = gen_highpart (SImode
, operands
[1]);
31756 op0_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[0]);
31757 op1_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[1]);
31760 op2_hi_lo
[hi
] = op2_hi_lo
[lo
] = NULL_RTX
;
31763 if (GET_CODE (operands
[2]) != CONST_INT
)
31765 op2_hi_lo
[hi
] = gen_highpart_mode (SImode
, DImode
, operands
[2]);
31766 op2_hi_lo
[lo
] = gen_lowpart (SImode
, operands
[2]);
31770 HOST_WIDE_INT value
= INTVAL (operands
[2]);
31771 HOST_WIDE_INT value_hi_lo
[2];
31773 gcc_assert (!complement_final_p
);
31774 gcc_assert (!complement_op1_p
);
31775 gcc_assert (!complement_op2_p
);
31777 value_hi_lo
[hi
] = value
>> 32;
31778 value_hi_lo
[lo
] = value
& lower_32bits
;
31780 for (i
= 0; i
< 2; i
++)
31782 HOST_WIDE_INT sub_value
= value_hi_lo
[i
];
31784 if (sub_value
& sign_bit
)
31785 sub_value
|= upper_32bits
;
31787 op2_hi_lo
[i
] = GEN_INT (sub_value
);
31789 /* If this is an AND instruction, check to see if we need to load
31790 the value in a register. */
31791 if (code
== AND
&& sub_value
!= -1 && sub_value
!= 0
31792 && !and_operand (op2_hi_lo
[i
], SImode
))
31793 op2_hi_lo
[i
] = force_reg (SImode
, op2_hi_lo
[i
]);
31798 for (i
= 0; i
< 2; i
++)
31800 /* Split large IOR/XOR operations. */
31801 if ((code
== IOR
|| code
== XOR
)
31802 && GET_CODE (op2_hi_lo
[i
]) == CONST_INT
31803 && !complement_final_p
31804 && !complement_op1_p
31805 && !complement_op2_p
31806 && clobber_reg
== NULL_RTX
31807 && !logical_const_operand (op2_hi_lo
[i
], SImode
))
31809 HOST_WIDE_INT value
= INTVAL (op2_hi_lo
[i
]);
31810 HOST_WIDE_INT hi_16bits
= value
& HOST_WIDE_INT_C(0xffff0000);
31811 HOST_WIDE_INT lo_16bits
= value
& HOST_WIDE_INT_C(0x0000ffff);
31812 rtx tmp
= gen_reg_rtx (SImode
);
31814 /* Make sure the constant is sign extended. */
31815 if ((hi_16bits
& sign_bit
) != 0)
31816 hi_16bits
|= upper_32bits
;
31818 rs6000_split_logical_inner (tmp
, op1_hi_lo
[i
], GEN_INT (hi_16bits
),
31819 code
, SImode
, false, false, false,
31822 rs6000_split_logical_inner (op0_hi_lo
[i
], tmp
, GEN_INT (lo_16bits
),
31823 code
, SImode
, false, false, false,
31827 rs6000_split_logical_inner (op0_hi_lo
[i
], op1_hi_lo
[i
], op2_hi_lo
[i
],
31828 code
, SImode
, complement_final_p
,
31829 complement_op1_p
, complement_op2_p
,
31836 /* Split the insns that make up boolean operations operating on multiple GPR
31837 registers. The boolean MD patterns ensure that the inputs either are
31838 exactly the same as the output registers, or there is no overlap.
31840 OPERANDS is an array containing the destination and two input operands.
31841 CODE is the base operation (AND, IOR, XOR, NOT).
31842 MODE is the machine mode.
31843 If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT.
31844 If COMPLEMENT_OP1_P is true, wrap operand1 with NOT.
31845 If COMPLEMENT_OP2_P is true, wrap operand2 with NOT.
31846 CLOBBER_REG is either NULL or a scratch register of type CC to allow
31847 formation of the AND instructions. */
31850 rs6000_split_logical (rtx operands
[3],
31851 enum rtx_code code
,
31852 bool complement_final_p
,
31853 bool complement_op1_p
,
31854 bool complement_op2_p
,
31857 enum machine_mode mode
= GET_MODE (operands
[0]);
31858 enum machine_mode sub_mode
;
31860 int sub_size
, regno0
, regno1
, nregs
, i
;
31862 /* If this is DImode, use the specialized version that can run before
31863 register allocation. */
31864 if (mode
== DImode
&& !TARGET_POWERPC64
)
31866 rs6000_split_logical_di (operands
, code
, complement_final_p
,
31867 complement_op1_p
, complement_op2_p
,
31874 op2
= (code
== NOT
) ? NULL_RTX
: operands
[2];
31875 sub_mode
= (TARGET_POWERPC64
) ? DImode
: SImode
;
31876 sub_size
= GET_MODE_SIZE (sub_mode
);
31877 regno0
= REGNO (op0
);
31878 regno1
= REGNO (op1
);
31880 gcc_assert (reload_completed
);
31881 gcc_assert (IN_RANGE (regno0
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31882 gcc_assert (IN_RANGE (regno1
, FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31884 nregs
= rs6000_hard_regno_nregs
[(int)mode
][regno0
];
31885 gcc_assert (nregs
> 1);
31887 if (op2
&& REG_P (op2
))
31888 gcc_assert (IN_RANGE (REGNO (op2
), FIRST_GPR_REGNO
, LAST_GPR_REGNO
));
31890 for (i
= 0; i
< nregs
; i
++)
31892 int offset
= i
* sub_size
;
31893 rtx sub_op0
= simplify_subreg (sub_mode
, op0
, mode
, offset
);
31894 rtx sub_op1
= simplify_subreg (sub_mode
, op1
, mode
, offset
);
31895 rtx sub_op2
= ((code
== NOT
)
31897 : simplify_subreg (sub_mode
, op2
, mode
, offset
));
31899 rs6000_split_logical_inner (sub_op0
, sub_op1
, sub_op2
, code
, sub_mode
,
31900 complement_final_p
, complement_op1_p
,
31901 complement_op2_p
, clobber_reg
);
31908 /* Return true if the peephole2 can combine a load involving a combination of
31909 an addis instruction and a load with an offset that can be fused together on
31913 operands[0] register set with addis
31914 operands[1] value set via addis
31915 operands[2] target register being loaded
31916 operands[3] D-form memory reference using operands[0].
31918 In addition, we are passed a boolean that is true if this is a peephole2,
31919 and we can use see if the addis_reg is dead after the insn and can be
31920 replaced by the target register. */
31923 fusion_gpr_load_p (rtx
*operands
, bool peep2_p
)
31925 rtx addis_reg
= operands
[0];
31926 rtx addis_value
= operands
[1];
31927 rtx target
= operands
[2];
31928 rtx mem
= operands
[3];
31932 /* Validate arguments. */
31933 if (!base_reg_operand (addis_reg
, GET_MODE (addis_reg
)))
31936 if (!base_reg_operand (target
, GET_MODE (target
)))
31939 if (!fusion_gpr_addis (addis_value
, GET_MODE (addis_value
)))
31942 if (!fusion_gpr_mem_load (mem
, GET_MODE (mem
)))
31945 /* Allow sign/zero extension. */
31946 if (GET_CODE (mem
) == ZERO_EXTEND
31947 || (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
))
31948 mem
= XEXP (mem
, 0);
31953 addr
= XEXP (mem
, 0); /* either PLUS or LO_SUM. */
31954 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
31957 /* Validate that the register used to load the high value is either the
31958 register being loaded, or we can safely replace its use in a peephole2.
31960 If this is a peephole2, we assume that there are 2 instructions in the
31961 peephole (addis and load), so we want to check if the target register was
31962 not used in the memory address and the register to hold the addis result
31963 is dead after the peephole. */
31964 if (REGNO (addis_reg
) != REGNO (target
))
31969 if (reg_mentioned_p (target
, mem
))
31972 if (!peep2_reg_dead_p (2, addis_reg
))
31976 base_reg
= XEXP (addr
, 0);
31977 return REGNO (addis_reg
) == REGNO (base_reg
);
31980 /* During the peephole2 pass, adjust and expand the insns for a load fusion
31981 sequence. We adjust the addis register to use the target register. If the
31982 load sign extends, we adjust the code to do the zero extending load, and an
31983 explicit sign extension later since the fusion only covers zero extending
31987 operands[0] register set with addis (to be replaced with target)
31988 operands[1] value set via addis
31989 operands[2] target register being loaded
31990 operands[3] D-form memory reference using operands[0]. */
31993 expand_fusion_gpr_load (rtx
*operands
)
31995 rtx addis_value
= operands
[1];
31996 rtx target
= operands
[2];
31997 rtx orig_mem
= operands
[3];
31998 rtx new_addr
, new_mem
, orig_addr
, offset
;
31999 enum rtx_code plus_or_lo_sum
;
32000 enum machine_mode target_mode
= GET_MODE (target
);
32001 enum machine_mode extend_mode
= target_mode
;
32002 enum machine_mode ptr_mode
= Pmode
;
32003 enum rtx_code extend
= UNKNOWN
;
32004 rtx addis_reg
= ((ptr_mode
== target_mode
)
32006 : simplify_subreg (ptr_mode
, target
, target_mode
, 0));
32008 if (GET_CODE (orig_mem
) == ZERO_EXTEND
32009 || (TARGET_P8_FUSION_SIGN
&& GET_CODE (orig_mem
) == SIGN_EXTEND
))
32011 extend
= GET_CODE (orig_mem
);
32012 orig_mem
= XEXP (orig_mem
, 0);
32013 target_mode
= GET_MODE (orig_mem
);
32016 gcc_assert (MEM_P (orig_mem
));
32018 orig_addr
= XEXP (orig_mem
, 0);
32019 plus_or_lo_sum
= GET_CODE (orig_addr
);
32020 gcc_assert (plus_or_lo_sum
== PLUS
|| plus_or_lo_sum
== LO_SUM
);
32022 offset
= XEXP (orig_addr
, 1);
32023 new_addr
= gen_rtx_fmt_ee (plus_or_lo_sum
, ptr_mode
, addis_reg
, offset
);
32024 new_mem
= change_address (orig_mem
, target_mode
, new_addr
);
32026 if (extend
!= UNKNOWN
)
32027 new_mem
= gen_rtx_fmt_e (ZERO_EXTEND
, extend_mode
, new_mem
);
32029 emit_insn (gen_rtx_SET (VOIDmode
, addis_reg
, addis_value
));
32030 emit_insn (gen_rtx_SET (VOIDmode
, target
, new_mem
));
32032 if (extend
== SIGN_EXTEND
)
32034 int sub_off
= ((BYTES_BIG_ENDIAN
)
32035 ? GET_MODE_SIZE (extend_mode
) - GET_MODE_SIZE (target_mode
)
32038 = simplify_subreg (target_mode
, target
, extend_mode
, sub_off
);
32040 emit_insn (gen_rtx_SET (VOIDmode
, target
,
32041 gen_rtx_SIGN_EXTEND (extend_mode
, sign_reg
)));
32047 /* Return a string to fuse an addis instruction with a gpr load to the same
32048 register that we loaded up the addis instruction. The code is complicated,
32049 so we call output_asm_insn directly, and just return "".
32052 operands[0] register set with addis (must be same reg as target).
32053 operands[1] value set via addis
32054 operands[2] target register being loaded
32055 operands[3] D-form memory reference using operands[0]. */
32058 emit_fusion_gpr_load (rtx
*operands
)
32060 rtx addis_reg
= operands
[0];
32061 rtx addis_value
= operands
[1];
32062 rtx target
= operands
[2];
32063 rtx mem
= operands
[3];
32067 const char *addis_str
= NULL
;
32068 const char *load_str
= NULL
;
32069 const char *extend_insn
= NULL
;
32070 const char *mode_name
= NULL
;
32071 char insn_template
[80];
32072 enum machine_mode mode
;
32073 const char *comment_str
= ASM_COMMENT_START
;
32074 bool sign_p
= false;
32076 gcc_assert (REG_P (addis_reg
) && REG_P (target
));
32077 gcc_assert (REGNO (addis_reg
) == REGNO (target
));
32079 if (*comment_str
== ' ')
32082 /* Allow sign/zero extension. */
32083 if (GET_CODE (mem
) == ZERO_EXTEND
)
32084 mem
= XEXP (mem
, 0);
32086 else if (GET_CODE (mem
) == SIGN_EXTEND
&& TARGET_P8_FUSION_SIGN
)
32089 mem
= XEXP (mem
, 0);
32092 gcc_assert (MEM_P (mem
));
32093 addr
= XEXP (mem
, 0);
32094 if (GET_CODE (addr
) != PLUS
&& GET_CODE (addr
) != LO_SUM
)
32095 gcc_unreachable ();
32097 load_offset
= XEXP (addr
, 1);
32099 /* Now emit the load instruction to the same register. */
32100 mode
= GET_MODE (mem
);
32104 mode_name
= "char";
32106 extend_insn
= "extsb %0,%0";
32110 mode_name
= "short";
32112 extend_insn
= "extsh %0,%0";
32118 extend_insn
= "extsw %0,%0";
32122 if (TARGET_POWERPC64
)
32124 mode_name
= "long";
32128 gcc_unreachable ();
32132 gcc_unreachable ();
32135 /* Emit the addis instruction. */
32136 fuse_ops
[0] = target
;
32137 if (satisfies_constraint_L (addis_value
))
32139 fuse_ops
[1] = addis_value
;
32140 addis_str
= "lis %0,%v1";
32143 else if (GET_CODE (addis_value
) == PLUS
)
32145 rtx op0
= XEXP (addis_value
, 0);
32146 rtx op1
= XEXP (addis_value
, 1);
32148 if (REG_P (op0
) && CONST_INT_P (op1
)
32149 && satisfies_constraint_L (op1
))
32153 addis_str
= "addis %0,%1,%v2";
32157 else if (GET_CODE (addis_value
) == HIGH
)
32159 rtx value
= XEXP (addis_value
, 0);
32160 if (GET_CODE (value
) == UNSPEC
&& XINT (value
, 1) == UNSPEC_TOCREL
)
32162 fuse_ops
[1] = XVECEXP (value
, 0, 0); /* symbol ref. */
32163 fuse_ops
[2] = XVECEXP (value
, 0, 1); /* TOC register. */
32165 addis_str
= "addis %0,%2,%1@toc@ha";
32167 else if (TARGET_XCOFF
)
32168 addis_str
= "addis %0,%1@u(%2)";
32171 gcc_unreachable ();
32174 else if (GET_CODE (value
) == PLUS
)
32176 rtx op0
= XEXP (value
, 0);
32177 rtx op1
= XEXP (value
, 1);
32179 if (GET_CODE (op0
) == UNSPEC
32180 && XINT (op0
, 1) == UNSPEC_TOCREL
32181 && CONST_INT_P (op1
))
32183 fuse_ops
[1] = XVECEXP (op0
, 0, 0); /* symbol ref. */
32184 fuse_ops
[2] = XVECEXP (op0
, 0, 1); /* TOC register. */
32187 addis_str
= "addis %0,%2,%1+%3@toc@ha";
32189 else if (TARGET_XCOFF
)
32190 addis_str
= "addis %0,%1+%3@u(%2)";
32193 gcc_unreachable ();
32197 else if (satisfies_constraint_L (value
))
32199 fuse_ops
[1] = value
;
32200 addis_str
= "lis %0,%v1";
32203 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (value
))
32205 fuse_ops
[1] = value
;
32206 addis_str
= "lis %0,%1@ha";
32211 fatal_insn ("Could not generate addis value for fusion", addis_value
);
32213 sprintf (insn_template
, "%s\t\t%s gpr load fusion, type %s", addis_str
,
32214 comment_str
, mode_name
);
32215 output_asm_insn (insn_template
, fuse_ops
);
32217 /* Emit the D-form load instruction. */
32218 if (CONST_INT_P (load_offset
) && satisfies_constraint_I (load_offset
))
32220 sprintf (insn_template
, "%s %%0,%%1(%%0)", load_str
);
32221 fuse_ops
[1] = load_offset
;
32222 output_asm_insn (insn_template
, fuse_ops
);
32225 else if (GET_CODE (load_offset
) == UNSPEC
32226 && XINT (load_offset
, 1) == UNSPEC_TOCREL
)
32229 sprintf (insn_template
, "%s %%0,%%1@toc@l(%%0)", load_str
);
32231 else if (TARGET_XCOFF
)
32232 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32235 gcc_unreachable ();
32237 fuse_ops
[1] = XVECEXP (load_offset
, 0, 0);
32238 output_asm_insn (insn_template
, fuse_ops
);
32241 else if (GET_CODE (load_offset
) == PLUS
32242 && GET_CODE (XEXP (load_offset
, 0)) == UNSPEC
32243 && XINT (XEXP (load_offset
, 0), 1) == UNSPEC_TOCREL
32244 && CONST_INT_P (XEXP (load_offset
, 1)))
32246 rtx tocrel_unspec
= XEXP (load_offset
, 0);
32248 sprintf (insn_template
, "%s %%0,%%1+%%2@toc@l(%%0)", load_str
);
32250 else if (TARGET_XCOFF
)
32251 sprintf (insn_template
, "%s %%0,%%1+%%2@l(%%0)", load_str
);
32254 gcc_unreachable ();
32256 fuse_ops
[1] = XVECEXP (tocrel_unspec
, 0, 0);
32257 fuse_ops
[2] = XEXP (load_offset
, 1);
32258 output_asm_insn (insn_template
, fuse_ops
);
32261 else if (TARGET_ELF
&& !TARGET_POWERPC64
&& CONSTANT_P (load_offset
))
32263 sprintf (insn_template
, "%s %%0,%%1@l(%%0)", load_str
);
32265 fuse_ops
[1] = load_offset
;
32266 output_asm_insn (insn_template
, fuse_ops
);
32270 fatal_insn ("Unable to generate load offset for fusion", load_offset
);
32272 /* Handle sign extension. The peephole2 pass generates this as a separate
32273 insn, but we handle it just in case it got reattached. */
32276 gcc_assert (extend_insn
!= NULL
);
32277 output_asm_insn (extend_insn
, fuse_ops
);
32284 struct gcc_target targetm
= TARGET_INITIALIZER
;
32286 #include "gt-rs6000.h"