1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 /* Note that some other tm.h files include this one and then override
25 many of the definitions. */
27 /* Definitions for the object file format. These are set at
30 #define OBJECT_XCOFF 1
33 #define OBJECT_MACHO 4
35 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF)
36 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF)
37 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF)
38 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO)
44 /* Default string to use for cpu if not specified. */
45 #ifndef TARGET_CPU_DEFAULT
46 #define TARGET_CPU_DEFAULT ((char *)0)
49 /* Common CPP definitions used by CPP_SPEC among the various targets
50 for handling -mcpu=xxx switches. */
51 #define CPP_CPU_SPEC \
53 %{mpower: %{!mpower2: -D_ARCH_PWR}} \
54 %{mpower2: -D_ARCH_PWR2} \
55 %{mpowerpc*: -D_ARCH_PPC} \
56 %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \
57 %{!mno-power: %{!mpower2: %(cpp_default)}}} \
58 %{mcpu=common: -D_ARCH_COM} \
59 %{mcpu=power: -D_ARCH_PWR} \
60 %{mcpu=power2: -D_ARCH_PWR2} \
61 %{mcpu=powerpc: -D_ARCH_PPC} \
62 %{mcpu=rios: -D_ARCH_PWR} \
63 %{mcpu=rios1: -D_ARCH_PWR} \
64 %{mcpu=rios2: -D_ARCH_PWR2} \
65 %{mcpu=rsc: -D_ARCH_PWR} \
66 %{mcpu=rsc1: -D_ARCH_PWR} \
67 %{mcpu=401: -D_ARCH_PPC} \
68 %{mcpu=403: -D_ARCH_PPC} \
69 %{mcpu=405: -D_ARCH_PPC} \
70 %{mcpu=505: -D_ARCH_PPC} \
71 %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \
72 %{mcpu=602: -D_ARCH_PPC} \
73 %{mcpu=603: -D_ARCH_PPC} \
74 %{mcpu=603e: -D_ARCH_PPC} \
75 %{mcpu=ec603e: -D_ARCH_PPC} \
76 %{mcpu=604: -D_ARCH_PPC} \
77 %{mcpu=604e: -D_ARCH_PPC} \
78 %{mcpu=620: -D_ARCH_PPC} \
79 %{mcpu=740: -D_ARCH_PPC} \
80 %{mcpu=7400: -D_ARCH_PPC} \
81 %{mcpu=7450: -D_ARCH_PPC} \
82 %{mcpu=750: -D_ARCH_PPC} \
83 %{mcpu=801: -D_ARCH_PPC} \
84 %{mcpu=821: -D_ARCH_PPC} \
85 %{mcpu=823: -D_ARCH_PPC} \
86 %{mcpu=860: -D_ARCH_PPC} \
87 %{maltivec: -D__ALTIVEC__}"
89 /* Common ASM definitions used by ASM_SPEC among the various targets
90 for handling -mcpu=xxx switches. */
91 #define ASM_CPU_SPEC \
93 %{mpower: %{!mpower2: -mpwr}} \
96 %{mno-power: %{!mpowerpc*: -mcom}} \
97 %{!mno-power: %{!mpower2: %(asm_default)}}} \
98 %{mcpu=common: -mcom} \
99 %{mcpu=power: -mpwr} \
100 %{mcpu=power2: -mpwrx} \
101 %{mcpu=powerpc: -mppc} \
102 %{mcpu=rios: -mpwr} \
103 %{mcpu=rios1: -mpwr} \
104 %{mcpu=rios2: -mpwrx} \
106 %{mcpu=rsc1: -mpwr} \
114 %{mcpu=603e: -mppc} \
115 %{mcpu=ec603e: -mppc} \
117 %{mcpu=604e: -mppc} \
120 %{mcpu=7400: -mppc} \
121 %{mcpu=7450: -mppc} \
127 %{maltivec: -maltivec}"
129 #define CPP_DEFAULT_SPEC ""
131 #define ASM_DEFAULT_SPEC ""
133 /* This macro defines names of additional specifications to put in the specs
134 that can be used in various specifications like CC1_SPEC. Its definition
135 is an initializer with a subgrouping for each command option.
137 Each subgrouping contains a string constant, that defines the
138 specification name, and a string constant that used by the GNU CC driver
141 Do not define this macro if it does not need to do anything. */
143 #define SUBTARGET_EXTRA_SPECS
145 #define EXTRA_SPECS \
146 { "cpp_cpu", CPP_CPU_SPEC }, \
147 { "cpp_default", CPP_DEFAULT_SPEC }, \
148 { "asm_cpu", ASM_CPU_SPEC }, \
149 { "asm_default", ASM_DEFAULT_SPEC }, \
150 SUBTARGET_EXTRA_SPECS
152 /* Architecture type. */
154 extern int target_flags
;
156 /* Use POWER architecture instructions and MQ register. */
157 #define MASK_POWER 0x00000001
159 /* Use POWER2 extensions to POWER architecture. */
160 #define MASK_POWER2 0x00000002
162 /* Use PowerPC architecture instructions. */
163 #define MASK_POWERPC 0x00000004
165 /* Use PowerPC General Purpose group optional instructions, e.g. fsqrt. */
166 #define MASK_PPC_GPOPT 0x00000008
168 /* Use PowerPC Graphics group optional instructions, e.g. fsel. */
169 #define MASK_PPC_GFXOPT 0x00000010
171 /* Use PowerPC-64 architecture instructions. */
172 #define MASK_POWERPC64 0x00000020
174 /* Use revised mnemonic names defined for PowerPC architecture. */
175 #define MASK_NEW_MNEMONICS 0x00000040
177 /* Disable placing fp constants in the TOC; can be turned on when the
179 #define MASK_NO_FP_IN_TOC 0x00000080
181 /* Disable placing symbol+offset constants in the TOC; can be turned on when
182 the TOC overflows. */
183 #define MASK_NO_SUM_IN_TOC 0x00000100
185 /* Output only one TOC entry per module. Normally linking fails if
186 there are more than 16K unique variables/constants in an executable. With
187 this option, linking fails only if there are more than 16K modules, or
188 if there are more than 16K unique variables/constant in a single module.
190 This is at the cost of having 2 extra loads and one extra store per
191 function, and one less allocable register. */
192 #define MASK_MINIMAL_TOC 0x00000200
194 /* Nonzero for the 64bit model: longs and pointers are 64 bits. */
195 #define MASK_64BIT 0x00000400
197 /* Disable use of FPRs. */
198 #define MASK_SOFT_FLOAT 0x00000800
200 /* Enable load/store multiple, even on powerpc */
201 #define MASK_MULTIPLE 0x00001000
202 #define MASK_MULTIPLE_SET 0x00002000
204 /* Use string instructions for block moves */
205 #define MASK_STRING 0x00004000
206 #define MASK_STRING_SET 0x00008000
208 /* Disable update form of load/store */
209 #define MASK_NO_UPDATE 0x00010000
211 /* Disable fused multiply/add operations */
212 #define MASK_NO_FUSED_MADD 0x00020000
214 /* Nonzero if we need to schedule the prolog and epilog. */
215 #define MASK_SCHED_PROLOG 0x00040000
217 /* Use AltiVec instructions. */
218 #define MASK_ALTIVEC 0x00080000
220 /* Return small structures in memory (as the AIX ABI requires). */
221 #define MASK_AIX_STRUCT_RET 0x00100000
222 #define MASK_AIX_STRUCT_RET_SET 0x00200000
224 /* The only remaining free bit is 0x00400000. sysv4.h uses
225 0x00800000 -> 0x40000000, and 0x80000000 is not available
226 because target_flags is signed. */
228 #define TARGET_POWER (target_flags & MASK_POWER)
229 #define TARGET_POWER2 (target_flags & MASK_POWER2)
230 #define TARGET_POWERPC (target_flags & MASK_POWERPC)
231 #define TARGET_PPC_GPOPT (target_flags & MASK_PPC_GPOPT)
232 #define TARGET_PPC_GFXOPT (target_flags & MASK_PPC_GFXOPT)
233 #define TARGET_NEW_MNEMONICS (target_flags & MASK_NEW_MNEMONICS)
234 #define TARGET_NO_FP_IN_TOC (target_flags & MASK_NO_FP_IN_TOC)
235 #define TARGET_NO_SUM_IN_TOC (target_flags & MASK_NO_SUM_IN_TOC)
236 #define TARGET_MINIMAL_TOC (target_flags & MASK_MINIMAL_TOC)
237 #define TARGET_64BIT (target_flags & MASK_64BIT)
238 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
239 #define TARGET_MULTIPLE (target_flags & MASK_MULTIPLE)
240 #define TARGET_MULTIPLE_SET (target_flags & MASK_MULTIPLE_SET)
241 #define TARGET_STRING (target_flags & MASK_STRING)
242 #define TARGET_STRING_SET (target_flags & MASK_STRING_SET)
243 #define TARGET_NO_UPDATE (target_flags & MASK_NO_UPDATE)
244 #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD)
245 #define TARGET_SCHED_PROLOG (target_flags & MASK_SCHED_PROLOG)
246 #define TARGET_ALTIVEC (target_flags & MASK_ALTIVEC)
247 #define TARGET_AIX_STRUCT_RET (target_flags & MASK_AIX_STRUCT_RET)
249 #define TARGET_32BIT (! TARGET_64BIT)
250 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
251 #define TARGET_UPDATE (! TARGET_NO_UPDATE)
252 #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD)
255 /* For libgcc2 we make sure this is a compile time constant */
256 #if defined (__64BIT__) || defined (__powerpc64__)
257 #define TARGET_POWERPC64 1
259 #define TARGET_POWERPC64 0
262 #define TARGET_POWERPC64 (target_flags & MASK_POWERPC64)
265 #define TARGET_XL_CALL 0
267 /* Run-time compilation parameters selecting different hardware subsets.
269 Macro to define tables used to set the flags.
270 This is a list in braces of pairs in braces,
271 each pair being { "NAME", VALUE }
272 where VALUE is the bits to set or minus the bits to clear.
273 An empty string NAME is used to identify the default VALUE. */
275 #define TARGET_SWITCHES \
276 {{"power", MASK_POWER | MASK_MULTIPLE | MASK_STRING, \
277 N_("Use POWER instruction set")}, \
278 {"power2", (MASK_POWER | MASK_MULTIPLE | MASK_STRING \
280 N_("Use POWER2 instruction set")}, \
281 {"no-power2", - MASK_POWER2, \
282 N_("Do not use POWER2 instruction set")}, \
283 {"no-power", - (MASK_POWER | MASK_POWER2 | MASK_MULTIPLE \
285 N_("Do not use POWER instruction set")}, \
286 {"powerpc", MASK_POWERPC, \
287 N_("Use PowerPC instruction set")}, \
288 {"no-powerpc", - (MASK_POWERPC | MASK_PPC_GPOPT \
289 | MASK_PPC_GFXOPT | MASK_POWERPC64), \
290 N_("Do not use PowerPC instruction set")}, \
291 {"powerpc-gpopt", MASK_POWERPC | MASK_PPC_GPOPT, \
292 N_("Use PowerPC General Purpose group optional instructions")},\
293 {"no-powerpc-gpopt", - MASK_PPC_GPOPT, \
294 N_("Don't use PowerPC General Purpose group optional instructions")},\
295 {"powerpc-gfxopt", MASK_POWERPC | MASK_PPC_GFXOPT, \
296 N_("Use PowerPC Graphics group optional instructions")},\
297 {"no-powerpc-gfxopt", - MASK_PPC_GFXOPT, \
298 N_("Don't use PowerPC Graphics group optional instructions")},\
299 {"powerpc64", MASK_POWERPC64, \
300 N_("Use PowerPC-64 instruction set")}, \
301 {"no-powerpc64", - MASK_POWERPC64, \
302 N_("Don't use PowerPC-64 instruction set")}, \
303 {"altivec", MASK_ALTIVEC , \
304 N_("Use AltiVec instructions")}, \
305 {"no-altivec", - MASK_ALTIVEC , \
306 N_("Don't use AltiVec instructions")}, \
307 {"new-mnemonics", MASK_NEW_MNEMONICS, \
308 N_("Use new mnemonics for PowerPC architecture")},\
309 {"old-mnemonics", -MASK_NEW_MNEMONICS, \
310 N_("Use old mnemonics for PowerPC architecture")},\
311 {"full-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC \
312 | MASK_MINIMAL_TOC), \
313 N_("Put everything in the regular TOC")}, \
314 {"fp-in-toc", - MASK_NO_FP_IN_TOC, \
315 N_("Place floating point constants in TOC")}, \
316 {"no-fp-in-toc", MASK_NO_FP_IN_TOC, \
317 N_("Don't place floating point constants in TOC")},\
318 {"sum-in-toc", - MASK_NO_SUM_IN_TOC, \
319 N_("Place symbol+offset constants in TOC")}, \
320 {"no-sum-in-toc", MASK_NO_SUM_IN_TOC, \
321 N_("Don't place symbol+offset constants in TOC")},\
322 {"minimal-toc", MASK_MINIMAL_TOC, \
323 "Use only one TOC entry per procedure"}, \
324 {"minimal-toc", - (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC), \
326 {"no-minimal-toc", - MASK_MINIMAL_TOC, \
327 N_("Place variable addresses in the regular TOC")},\
328 {"hard-float", - MASK_SOFT_FLOAT, \
329 N_("Use hardware fp")}, \
330 {"soft-float", MASK_SOFT_FLOAT, \
331 N_("Do not use hardware fp")}, \
332 {"multiple", MASK_MULTIPLE | MASK_MULTIPLE_SET, \
333 N_("Generate load/store multiple instructions")}, \
334 {"no-multiple", - MASK_MULTIPLE, \
335 N_("Do not generate load/store multiple instructions")},\
336 {"no-multiple", MASK_MULTIPLE_SET, \
338 {"string", MASK_STRING | MASK_STRING_SET, \
339 N_("Generate string instructions for block moves")},\
340 {"no-string", - MASK_STRING, \
341 N_("Do not generate string instructions for block moves")},\
342 {"no-string", MASK_STRING_SET, \
344 {"update", - MASK_NO_UPDATE, \
345 N_("Generate load/store with update instructions")},\
346 {"no-update", MASK_NO_UPDATE, \
347 N_("Do not generate load/store with update instructions")},\
348 {"fused-madd", - MASK_NO_FUSED_MADD, \
349 N_("Generate fused multiply/add instructions")},\
350 {"no-fused-madd", MASK_NO_FUSED_MADD, \
351 N_("Don't generate fused multiply/add instructions")},\
352 {"sched-prolog", MASK_SCHED_PROLOG, \
354 {"no-sched-prolog", -MASK_SCHED_PROLOG, \
355 N_("Don't schedule the start and end of the procedure")},\
356 {"sched-epilog", MASK_SCHED_PROLOG, \
358 {"no-sched-epilog", -MASK_SCHED_PROLOG, \
360 {"aix-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET, \
361 N_("Return all structures in memory (AIX default)")},\
362 {"svr4-struct-return", - MASK_AIX_STRUCT_RET,\
363 N_("Return small structures in registers (SVR4 default)")},\
364 {"svr4-struct-return",MASK_AIX_STRUCT_RET_SET,\
366 {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,\
368 {"no-aix-struct-return", MASK_AIX_STRUCT_RET_SET,\
370 {"no-svr4-struct-return", MASK_AIX_STRUCT_RET | MASK_AIX_STRUCT_RET_SET,\
373 {"", TARGET_DEFAULT | MASK_SCHED_PROLOG, \
376 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING)
378 /* This is meant to be redefined in the host dependent files */
379 #define SUBTARGET_SWITCHES
381 /* Processor type. Order must match cpu attribute in MD file. */
401 extern enum processor_type rs6000_cpu
;
403 /* Recast the processor type to the cpu attribute. */
404 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu)
406 /* Define generic processor types based upon current deployment. */
407 #define PROCESSOR_COMMON PROCESSOR_PPC601
408 #define PROCESSOR_POWER PROCESSOR_RIOS1
409 #define PROCESSOR_POWERPC PROCESSOR_PPC604
410 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A
412 /* Define the default processor. This is overridden by other tm.h files. */
413 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1
414 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A
416 /* Specify the dialect of assembler to use. New mnemonics is dialect one
417 and the old mnemonics are dialect zero. */
418 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0)
420 /* This is meant to be overridden in target specific files. */
421 #define SUBTARGET_OPTIONS
423 #define TARGET_OPTIONS \
425 {"cpu=", &rs6000_select[1].string, \
426 N_("Use features of and schedule code for given CPU") }, \
427 {"tune=", &rs6000_select[2].string, \
428 N_("Schedule code for given CPU") }, \
429 {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \
430 {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \
431 {"long-double-", &rs6000_long_double_size_string, \
432 N_("Specify size of long double (64 or 128 bits)") }, \
433 {"vrsave=", &rs6000_altivec_vrsave_string, \
434 N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \
435 {"longcall", &rs6000_longcall_switch, \
436 N_("Avoid all range limits on call instructions") }, \
437 {"no-longcall", &rs6000_longcall_switch, "" }, \
441 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */
442 struct rs6000_cpu_select
450 extern struct rs6000_cpu_select rs6000_select
[];
453 extern const char *rs6000_debug_name
; /* Name for -mdebug-xxxx option */
454 extern const char *rs6000_abi_string
; /* for -mabi={sysv,darwin,eabi,aix,altivec} */
455 extern int rs6000_debug_stack
; /* debug stack applications */
456 extern int rs6000_debug_arg
; /* debug argument handling */
458 #define TARGET_DEBUG_STACK rs6000_debug_stack
459 #define TARGET_DEBUG_ARG rs6000_debug_arg
461 /* These are separate from target_flags because we've run out of bits
463 extern const char *rs6000_long_double_size_string
;
464 extern int rs6000_long_double_type_size
;
465 extern int rs6000_altivec_abi
;
466 extern const char *rs6000_altivec_vrsave_string
;
467 extern int rs6000_altivec_vrsave
;
468 extern const char *rs6000_longcall_switch
;
469 extern int rs6000_default_long_calls
;
471 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
472 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
473 #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
475 /* Sometimes certain combinations of command options do not make sense
476 on a particular target machine. You can define a macro
477 `OVERRIDE_OPTIONS' to take account of this. This macro, if
478 defined, is executed once just after all the command options have
481 Don't use this macro to turn on various extra optimizations for
482 `-O'. That is what `OPTIMIZATION_OPTIONS' is for.
484 On the RS/6000 this is used to define the target cpu type. */
486 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT)
488 /* Define this to change the optimizations performed by default. */
489 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE)
492 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
493 cpp_register_pragma (PFILE, 0, "longcall", rs6000_pragma_longcall); \
496 /* Show we can debug even without a frame pointer. */
497 #define CAN_DEBUG_WITHOUT_FP
499 /* target machine storage layout */
501 /* Define this macro if it is advisable to hold scalars in registers
502 in a wider mode than that declared by the program. In such cases,
503 the value is constrained to be within the bounds of the declared
504 type, but kept valid in the wider mode. The signedness of the
505 extension may differ from that of the type. */
507 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
508 if (GET_MODE_CLASS (MODE) == MODE_INT \
509 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
512 /* Define this if function arguments should also be promoted using the above
515 #define PROMOTE_FUNCTION_ARGS
517 /* Likewise, if the function return value is promoted. */
519 #define PROMOTE_FUNCTION_RETURN
521 /* Define this if most significant bit is lowest numbered
522 in instructions that operate on numbered bit-fields. */
523 /* That is true on RS/6000. */
524 #define BITS_BIG_ENDIAN 1
526 /* Define this if most significant byte of a word is the lowest numbered. */
527 /* That is true on RS/6000. */
528 #define BYTES_BIG_ENDIAN 1
530 /* Define this if most significant word of a multiword number is lowest
533 For RS/6000 we can decide arbitrarily since there are no machine
534 instructions for them. Might as well be consistent with bits and bytes. */
535 #define WORDS_BIG_ENDIAN 1
537 #define MAX_BITS_PER_WORD 64
539 /* Width of a word, in units (bytes). */
540 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8)
541 #define MIN_UNITS_PER_WORD 4
542 #define UNITS_PER_FP_WORD 8
543 #define UNITS_PER_ALTIVEC_WORD 16
545 /* Type used for ptrdiff_t, as a string used in a declaration. */
546 #define PTRDIFF_TYPE "int"
548 /* Type used for size_t, as a string used in a declaration. */
549 #define SIZE_TYPE "long unsigned int"
551 /* Type used for wchar_t, as a string used in a declaration. */
552 #define WCHAR_TYPE "short unsigned int"
554 /* Width of wchar_t in bits. */
555 #define WCHAR_TYPE_SIZE 16
557 /* A C expression for the size in bits of the type `short' on the
558 target machine. If you don't define this, the default is half a
559 word. (If this would be less than one storage unit, it is
560 rounded up to one unit.) */
561 #define SHORT_TYPE_SIZE 16
563 /* A C expression for the size in bits of the type `int' on the
564 target machine. If you don't define this, the default is one
566 #define INT_TYPE_SIZE 32
568 /* A C expression for the size in bits of the type `long' on the
569 target machine. If you don't define this, the default is one
571 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64)
572 #define MAX_LONG_TYPE_SIZE 64
574 /* A C expression for the size in bits of the type `long long' on the
575 target machine. If you don't define this, the default is two
577 #define LONG_LONG_TYPE_SIZE 64
579 /* A C expression for the size in bits of the type `float' on the
580 target machine. If you don't define this, the default is one
582 #define FLOAT_TYPE_SIZE 32
584 /* A C expression for the size in bits of the type `double' on the
585 target machine. If you don't define this, the default is two
587 #define DOUBLE_TYPE_SIZE 64
589 /* A C expression for the size in bits of the type `long double' on
590 the target machine. If you don't define this, the default is two
592 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size
594 /* Constant which presents upper bound of the above value. */
595 #define MAX_LONG_DOUBLE_TYPE_SIZE 128
597 /* Define this to set long double type size to use in libgcc2.c, which can
598 not depend on target_flags. */
599 #ifdef __LONG_DOUBLE_128__
600 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
602 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
605 /* Width in bits of a pointer.
606 See also the macro `Pmode' defined below. */
607 #define POINTER_SIZE (TARGET_32BIT ? 32 : 64)
609 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
610 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64)
612 /* Boundary (in *bits*) on which stack pointer should be aligned. */
613 #define STACK_BOUNDARY ((TARGET_32BIT && !TARGET_ALTIVEC_ABI) ? 64 : 128)
615 /* Allocation boundary (in *bits*) for the code of a function. */
616 #define FUNCTION_BOUNDARY 32
618 /* No data type wants to be aligned rounder than this. */
619 #define BIGGEST_ALIGNMENT 128
621 /* A C expression to compute the alignment for a variables in the
622 local store. TYPE is the data type, and ALIGN is the alignment
623 that the object would ordinarily have. */
624 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
625 ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : ALIGN)
627 /* Alignment of field after `int : 0' in a structure. */
628 #define EMPTY_FIELD_BOUNDARY 32
630 /* Every structure's size must be a multiple of this. */
631 #define STRUCTURE_SIZE_BOUNDARY 8
633 /* A bitfield declared as `int' forces `int' alignment for the struct. */
634 #define PCC_BITFIELD_TYPE_MATTERS 1
636 /* Make strings word-aligned so strcpy from constants will be faster.
637 Make vector constants quadword aligned. */
638 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
639 (TREE_CODE (EXP) == STRING_CST \
640 && (ALIGN) < BITS_PER_WORD \
644 /* Make arrays of chars word-aligned for the same reasons.
645 Align vectors to 128 bits. */
646 #define DATA_ALIGNMENT(TYPE, ALIGN) \
647 (TREE_CODE (TYPE) == VECTOR_TYPE ? 128 \
648 : TREE_CODE (TYPE) == ARRAY_TYPE \
649 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
650 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
652 /* Non-zero if move instructions will actually fail to work
653 when given unaligned data. */
654 #define STRICT_ALIGNMENT 0
656 /* Define this macro to be the value 1 if unaligned accesses have a cost
657 many times greater than aligned accesses, for example if they are
658 emulated in a trap handler. */
659 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \
661 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \
664 /* Standard register usage. */
666 /* Number of actual hardware registers.
667 The hardware registers are assigned numbers for the compiler
668 from 0 to just below FIRST_PSEUDO_REGISTER.
669 All registers that the compiler knows about must be given numbers,
670 even those that are not normally considered general registers.
672 RS/6000 has 32 fixed-point registers, 32 floating-point registers,
673 an MQ register, a count register, a link register, and 8 condition
674 register fields, which we view here as separate registers.
676 In addition, the difference between the frame and argument pointers is
677 a function of the number of registers saved, so we need to have a
678 register for AP that will later be eliminated in favor of SP or FP.
679 This is a normal register, but it is fixed.
681 We also create a pseudo register for float/int conversions, that will
682 really represent the memory location used. It is represented here as
683 a register, in order to work around problems in allocating stack storage
684 in inline functions. */
686 #define FIRST_PSEUDO_REGISTER 111
688 /* This must be included for pre gcc 3.0 glibc compatibility. */
689 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77
691 /* 1 for registers that have pervasive standard uses
692 and are not available for the register allocator.
694 On RS/6000, r1 is used for the stack. On Darwin, r2 is available
695 as a local register; for all other OS's r2 is the TOC pointer.
697 cr5 is not supposed to be used.
699 On System V implementations, r13 is fixed and not available for use. */
701 #define FIXED_REGISTERS \
702 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \
703 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
704 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
705 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
706 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \
707 /* AltiVec registers. */ \
708 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
709 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
713 /* 1 for registers not available across function calls.
714 These must include the FIXED_REGISTERS and also any
715 registers that can be used without being saved.
716 The latter must include the registers where values are returned
717 and the register where structure-value addresses are passed.
718 Aside from that, you can include as many other registers as you like. */
720 #define CALL_USED_REGISTERS \
721 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
722 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
723 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
724 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
725 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
726 /* AltiVec registers. */ \
727 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
728 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
732 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that
733 the entire set of `FIXED_REGISTERS' be included.
734 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS').
735 This macro is optional. If not specified, it defaults to the value
736 of `CALL_USED_REGISTERS'. */
738 #define CALL_REALLY_USED_REGISTERS \
739 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \
740 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
741 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
742 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
743 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \
744 /* AltiVec registers. */ \
745 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
746 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
756 #define MAX_CR_REGNO 75
758 #define FIRST_ALTIVEC_REGNO 77
759 #define LAST_ALTIVEC_REGNO 108
760 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
761 #define VRSAVE_REGNO 109
762 #define VSCR_REGNO 110
764 /* List the order in which to allocate registers. Each register must be
765 listed once, even those in FIXED_REGISTERS.
767 We allocate in the following order:
768 fp0 (not saved or used for anything)
769 fp13 - fp2 (not saved; incoming fp arg registers)
770 fp1 (not saved; return value)
771 fp31 - fp14 (saved; order given to save least number)
772 cr7, cr6 (not saved or special)
773 cr1 (not saved, but used for FP operations)
774 cr0 (not saved, but used for arithmetic operations)
775 cr4, cr3, cr2 (saved)
776 r0 (not saved; cannot be base reg)
777 r9 (not saved; best for TImode)
778 r11, r10, r8-r4 (not saved; highest used first to make less conflict)
779 r3 (not saved; return value register)
780 r31 - r13 (saved; order given to save least number)
781 r12 (not saved; if used for DImode or DFmode would use r13)
782 mq (not saved; best to use it if we can)
783 ctr (not saved; when we have the choice ctr is better)
785 cr5, r1, r2, ap, xer, vrsave, vscr (fixed)
788 v0 - v1 (not saved or used for anything)
789 v13 - v3 (not saved; incoming vector arg registers)
790 v2 (not saved; incoming vector arg reg; return value)
791 v19 - v14 (not saved or used for anything)
792 v31 - v20 (saved; order given to save least number)
796 #define REG_ALLOC_ORDER \
798 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \
800 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \
801 50, 49, 48, 47, 46, \
802 75, 74, 69, 68, 72, 71, 70, \
804 9, 11, 10, 8, 7, 6, 5, 4, \
806 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
807 18, 17, 16, 15, 14, 13, 12, \
810 /* AltiVec registers. */ \
812 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \
814 96, 95, 94, 93, 92, 91, \
815 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \
819 /* True if register is floating-point. */
820 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)
822 /* True if register is a condition register. */
823 #define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)
825 /* True if register is a condition register, but not cr0. */
826 #define CR_REGNO_NOT_CR0_P(N) ((N) >= 69 && (N) <= 75)
828 /* True if register is an integer register. */
829 #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM)
831 /* True if register is the XER register. */
832 #define XER_REGNO_P(N) ((N) == XER_REGNO)
834 /* True if register is an AltiVec register. */
835 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO)
837 /* Return number of consecutive hard regs needed starting at reg REGNO
838 to hold something of mode MODE.
839 This is ordinarily the length in words of a value of mode MODE
840 but can be less for certain modes in special long registers.
842 POWER and PowerPC GPRs hold 32 bits worth;
843 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
845 #define HARD_REGNO_NREGS(REGNO, MODE) \
846 (FP_REGNO_P (REGNO) \
847 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
848 : ALTIVEC_REGNO_P (REGNO) \
849 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \
850 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
852 #define ALTIVEC_VECTOR_MODE(MODE) \
853 ((MODE) == V16QImode \
854 || (MODE) == V8HImode \
855 || (MODE) == V4SFmode \
856 || (MODE) == V4SImode)
858 /* Define this macro to be nonzero if the port is prepared to handle
859 insns involving vector mode MODE. At the very least, it must have
860 move patterns for this mode. */
862 #define VECTOR_MODE_SUPPORTED_P(MODE) \
863 (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))
865 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
866 For POWER and PowerPC, the GPRs can hold any mode, but the float
867 registers only can hold floating modes and DImode, and CR register only
868 can hold CC modes. We cannot put TImode anywhere except general
869 register and it must be able to fit within the register set. */
871 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
872 (FP_REGNO_P (REGNO) ? \
873 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
874 || (GET_MODE_CLASS (MODE) == MODE_INT \
875 && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \
876 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \
877 : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \
878 : XER_REGNO_P (REGNO) ? (MODE) == PSImode \
879 : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \
880 && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \
883 /* Value is 1 if it is a good idea to tie two pseudo registers
884 when one has mode MODE1 and one has mode MODE2.
885 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
886 for any hard reg, then this must be 0 for correct output. */
887 #define MODES_TIEABLE_P(MODE1, MODE2) \
888 (GET_MODE_CLASS (MODE1) == MODE_FLOAT \
889 ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \
890 : GET_MODE_CLASS (MODE2) == MODE_FLOAT \
891 ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \
892 : GET_MODE_CLASS (MODE1) == MODE_CC \
893 ? GET_MODE_CLASS (MODE2) == MODE_CC \
894 : GET_MODE_CLASS (MODE2) == MODE_CC \
895 ? GET_MODE_CLASS (MODE1) == MODE_CC \
896 : ALTIVEC_VECTOR_MODE (MODE1) \
897 ? ALTIVEC_VECTOR_MODE (MODE2) \
898 : ALTIVEC_VECTOR_MODE (MODE2) \
899 ? ALTIVEC_VECTOR_MODE (MODE1) \
902 /* A C expression returning the cost of moving data from a register of class
903 CLASS1 to one of CLASS2.
905 On the RS/6000, copying between floating-point and fixed-point
906 registers is expensive. */
908 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
909 ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \
910 : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \
911 : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \
912 : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20 \
913 : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20 \
914 : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \
915 || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \
916 || (CLASS1) == LINK_OR_CTR_REGS) \
917 && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \
918 || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \
919 || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \
922 /* A C expressions returning the cost of moving data of MODE from a register to
925 On the RS/6000, bump this up a bit. */
927 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \
928 ((GET_MODE_CLASS (MODE) == MODE_FLOAT \
929 && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \
933 /* Specify the cost of a branch insn; roughly the number of extra insns that
934 should be added to avoid a branch.
936 Set this to 3 on the RS/6000 since that is roughly the average cost of an
937 unscheduled conditional branch. */
939 #define BRANCH_COST 3
941 /* Define this macro to change register usage conditional on target flags.
942 Set MQ register fixed (already call_used) if not POWER architecture
943 (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated.
944 64-bit AIX reserves GPR13 for thread-private data.
945 Conditionally disable FPRs. */
947 #define CONDITIONAL_REGISTER_USAGE \
950 if (! TARGET_POWER) \
951 fixed_regs[64] = 1; \
953 fixed_regs[13] = call_used_regs[13] \
954 = call_really_used_regs[13] = 1; \
955 if (TARGET_SOFT_FLOAT) \
956 for (i = 32; i < 64; i++) \
957 fixed_regs[i] = call_used_regs[i] \
958 = call_really_used_regs[i] = 1; \
959 if (DEFAULT_ABI == ABI_V4 \
960 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \
962 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
963 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
964 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
965 if (DEFAULT_ABI == ABI_DARWIN \
966 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \
967 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
968 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
969 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \
970 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \
971 if (TARGET_ALTIVEC) \
972 global_regs[VSCR_REGNO] = 1; \
973 if (! TARGET_ALTIVEC) \
975 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \
976 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; \
977 call_really_used_regs[VRSAVE_REGNO] = 1; \
979 if (TARGET_ALTIVEC_ABI) \
980 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i) \
981 call_used_regs[i] = call_really_used_regs[i] = 1; \
984 /* Specify the registers used for certain standard purposes.
985 The values of these macros are register numbers. */
987 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */
988 /* #define PC_REGNUM */
990 /* Register to use for pushing function arguments. */
991 #define STACK_POINTER_REGNUM 1
993 /* Base register for access to local variables of the function. */
994 #define FRAME_POINTER_REGNUM 31
996 /* Value should be nonzero if functions must have frame pointers.
997 Zero means the frame pointer need not be set up (and parms
998 may be accessed via the stack pointer) in functions that seem suitable.
999 This is computed in `reload', in reload1.c. */
1000 #define FRAME_POINTER_REQUIRED 0
1002 /* Base register for access to arguments of the function. */
1003 #define ARG_POINTER_REGNUM 67
1005 /* Place to put static chain when calling a function that requires it. */
1006 #define STATIC_CHAIN_REGNUM 11
1008 /* Link register number. */
1009 #define LINK_REGISTER_REGNUM 65
1011 /* Count register number. */
1012 #define COUNT_REGISTER_REGNUM 66
1014 /* Place that structure value return address is placed.
1016 On the RS/6000, it is passed as an extra parameter. */
1017 #define STRUCT_VALUE 0
1019 /* Define the classes of registers for register constraints in the
1020 machine description. Also define ranges of constants.
1022 One of the classes must always be named ALL_REGS and include all hard regs.
1023 If there is more than one class, another class must be named NO_REGS
1024 and contain no registers.
1026 The name GENERAL_REGS must be the name of a class (or an alias for
1027 another name such as ALL_REGS). This is the class of registers
1028 that is allowed by "g" or "r" in a register constraint.
1029 Also, registers outside this class are allocated only when
1030 instructions express preferences for them.
1032 The classes must be numbered in nondecreasing order; that is,
1033 a larger-numbered class must never be contained completely
1034 in a smaller-numbered class.
1036 For any two classes, it is very desirable that there be another
1037 class that represents their union. */
1039 /* The RS/6000 has three types of registers, fixed-point, floating-point,
1040 and condition registers, plus three special registers, MQ, CTR, and the
1043 However, r0 is special in that it cannot be used as a base register.
1044 So make a class for registers valid as base registers.
1046 Also, cr0 is the only condition code register that can be used in
1047 arithmetic insns, so make a separate class for it. */
1073 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1075 /* Give names of register classes as strings for dump file. */
1077 #define REG_CLASS_NAMES \
1086 "NON_SPECIAL_REGS", \
1090 "LINK_OR_CTR_REGS", \
1092 "SPEC_OR_GEN_REGS", \
1100 /* Define which registers fit in which classes.
1101 This is an initializer for a vector of HARD_REG_SET
1102 of length N_REG_CLASSES. */
1104 #define REG_CLASS_CONTENTS \
1106 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \
1107 { 0xfffffffe, 0x00000000, 0x00000008, 0x00000000 }, /* BASE_REGS */ \
1108 { 0xffffffff, 0x00000000, 0x00000008, 0x00000000 }, /* GENERAL_REGS */ \
1109 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \
1110 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \
1111 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \
1112 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \
1113 { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \
1114 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \
1115 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \
1116 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \
1117 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \
1118 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \
1119 { 0xffffffff, 0x00000000, 0x0000000f, 0x00000000 }, /* SPEC_OR_GEN_REGS */ \
1120 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \
1121 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \
1122 { 0xffffffff, 0x00000000, 0x0000efff, 0x00000000 }, /* NON_FLOAT_REGS */ \
1123 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \
1124 { 0xffffffff, 0xffffffff, 0xffffffff, 0x00003fff } /* ALL_REGS */ \
1127 /* The same information, inverted:
1128 Return the class number of the smallest class containing
1129 reg number REGNO. This could be a conditional expression
1130 or could index an array. */
1132 #define REGNO_REG_CLASS(REGNO) \
1133 ((REGNO) == 0 ? GENERAL_REGS \
1134 : (REGNO) < 32 ? BASE_REGS \
1135 : FP_REGNO_P (REGNO) ? FLOAT_REGS \
1136 : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_REGS \
1137 : (REGNO) == CR0_REGNO ? CR0_REGS \
1138 : CR_REGNO_P (REGNO) ? CR_REGS \
1139 : (REGNO) == MQ_REGNO ? MQ_REGS \
1140 : (REGNO) == LINK_REGISTER_REGNUM ? LINK_REGS \
1141 : (REGNO) == COUNT_REGISTER_REGNUM ? CTR_REGS \
1142 : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \
1143 : (REGNO) == XER_REGNO ? XER_REGS \
1144 : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \
1145 : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \
1148 /* The class value for index registers, and the one for base regs. */
1149 #define INDEX_REG_CLASS GENERAL_REGS
1150 #define BASE_REG_CLASS BASE_REGS
1152 /* Get reg_class from a letter such as appears in the machine description. */
1154 #define REG_CLASS_FROM_LETTER(C) \
1155 ((C) == 'f' ? FLOAT_REGS \
1156 : (C) == 'b' ? BASE_REGS \
1157 : (C) == 'h' ? SPECIAL_REGS \
1158 : (C) == 'q' ? MQ_REGS \
1159 : (C) == 'c' ? CTR_REGS \
1160 : (C) == 'l' ? LINK_REGS \
1161 : (C) == 'v' ? ALTIVEC_REGS \
1162 : (C) == 'x' ? CR0_REGS \
1163 : (C) == 'y' ? CR_REGS \
1164 : (C) == 'z' ? XER_REGS \
1167 /* The letters I, J, K, L, M, N, and P in a register constraint string
1168 can be used to stand for particular ranges of immediate operands.
1169 This macro defines what the ranges are.
1170 C is the letter, and VALUE is a constant value.
1171 Return 1 if VALUE is in the range specified by C.
1173 `I' is a signed 16-bit constant
1174 `J' is a constant with only the high-order 16 bits non-zero
1175 `K' is a constant with only the low-order 16 bits non-zero
1176 `L' is a signed 16-bit constant shifted left 16 bits
1177 `M' is a constant that is greater than 31
1178 `N' is a positive constant that is an exact power of two
1179 `O' is the constant zero
1180 `P' is a constant whose negation is a signed 16-bit constant */
1182 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1183 ( (C) == 'I' ? (unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000 \
1184 : (C) == 'J' ? ((VALUE) & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0 \
1185 : (C) == 'K' ? ((VALUE) & (~ (HOST_WIDE_INT) 0xffff)) == 0 \
1186 : (C) == 'L' ? (((VALUE) & 0xffff) == 0 \
1187 && ((VALUE) >> 31 == -1 || (VALUE) >> 31 == 0)) \
1188 : (C) == 'M' ? (VALUE) > 31 \
1189 : (C) == 'N' ? (VALUE) > 0 && exact_log2 (VALUE) >= 0 \
1190 : (C) == 'O' ? (VALUE) == 0 \
1191 : (C) == 'P' ? (unsigned HOST_WIDE_INT) ((- (VALUE)) + 0x8000) < 0x10000 \
1194 /* Similar, but for floating constants, and defining letters G and H.
1195 Here VALUE is the CONST_DOUBLE rtx itself.
1197 We flag for special constants when we can copy the constant into
1198 a general register in two insns for DF/DI and one insn for SF.
1200 'H' is used for DI/DF constants that take 3 insns. */
1202 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1203 ( (C) == 'G' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) \
1204 == ((GET_MODE (VALUE) == SFmode) ? 1 : 2)) \
1205 : (C) == 'H' ? (num_insns_constant (VALUE, GET_MODE (VALUE)) == 3) \
1208 /* Optional extra constraints for this machine.
1210 'Q' means that is a memory operand that is just an offset from a reg.
1211 'R' is for AIX TOC entries.
1212 'S' is a constant that can be placed into a 64-bit mask operand
1213 'T' is a constant that can be placed into a 32-bit mask operand
1214 'U' is for V.4 small data references. */
1216 #define EXTRA_CONSTRAINT(OP, C) \
1217 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \
1218 : (C) == 'R' ? LEGITIMATE_CONSTANT_POOL_ADDRESS_P (OP) \
1219 : (C) == 'S' ? mask64_operand (OP, DImode) \
1220 : (C) == 'T' ? mask_operand (OP, SImode) \
1221 : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \
1222 && small_data_operand (OP, GET_MODE (OP))) \
1225 /* Given an rtx X being reloaded into a reg required to be
1226 in class CLASS, return the class of reg to actually use.
1227 In general this is just CLASS; but on some machines
1228 in some cases it is preferable to use a more restrictive class.
1230 On the RS/6000, we have to return NO_REGS when we want to reload a
1231 floating-point CONST_DOUBLE to force it to be copied to memory.
1233 We also don't want to reload integer values into floating-point
1234 registers if we can at all help it. In fact, this can
1235 cause reload to abort, if it tries to generate a reload of CTR
1236 into a FP register and discovers it doesn't have the memory location
1239 ??? Would it be a good idea to have reload do the converse, that is
1240 try to reload floating modes into FP registers if possible?
1243 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1244 (((GET_CODE (X) == CONST_DOUBLE \
1245 && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1247 : (GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
1248 && (CLASS) == NON_SPECIAL_REGS) \
1252 /* Return the register class of a scratch register needed to copy IN into
1253 or out of a register in CLASS in MODE. If it can be done directly,
1254 NO_REGS is returned. */
1256 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
1257 secondary_reload_class (CLASS, MODE, IN)
1259 /* If we are copying between FP or AltiVec registers and anything
1260 else, we need a memory location. */
1262 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \
1263 ((CLASS1) != (CLASS2) && ((CLASS1) == FLOAT_REGS \
1264 || (CLASS2) == FLOAT_REGS \
1265 || (CLASS1) == ALTIVEC_REGS \
1266 || (CLASS2) == ALTIVEC_REGS))
1268 /* Return the maximum number of consecutive registers
1269 needed to represent mode MODE in a register of class CLASS.
1271 On RS/6000, this is the size of MODE in words,
1272 except in the FP regs, where a single reg is enough for two words. */
1273 #define CLASS_MAX_NREGS(CLASS, MODE) \
1274 (((CLASS) == FLOAT_REGS) \
1275 ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \
1276 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1278 /* If defined, gives a class of registers that cannot be used as the
1279 operand of a SUBREG that changes the mode of the object illegally. */
1281 #define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS
1283 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
1285 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
1286 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
1288 /* Stack layout; function entry, exit and calling. */
1290 /* Enumeration to give which calling sequence to use. */
1293 ABI_AIX
, /* IBM's AIX */
1294 ABI_AIX_NODESC
, /* AIX calling sequence minus
1295 function descriptors */
1296 ABI_V4
, /* System V.4/eabi */
1297 ABI_DARWIN
/* Apple's Darwin (OS X kernel) */
1300 extern enum rs6000_abi rs6000_current_abi
; /* available for use by subtarget */
1302 /* Structure used to define the rs6000 stack */
1303 typedef struct rs6000_stack
{
1304 int first_gp_reg_save
; /* first callee saved GP register used */
1305 int first_fp_reg_save
; /* first callee saved FP register used */
1306 int first_altivec_reg_save
; /* first callee saved AltiVec register used */
1307 int lr_save_p
; /* true if the link reg needs to be saved */
1308 int cr_save_p
; /* true if the CR reg needs to be saved */
1309 unsigned int vrsave_mask
; /* mask of vec registers to save */
1310 int toc_save_p
; /* true if the TOC needs to be saved */
1311 int push_p
; /* true if we need to allocate stack space */
1312 int calls_p
; /* true if the function makes any calls */
1313 enum rs6000_abi abi
; /* which ABI to use */
1314 int gp_save_offset
; /* offset to save GP regs from initial SP */
1315 int fp_save_offset
; /* offset to save FP regs from initial SP */
1316 int altivec_save_offset
; /* offset to save AltiVec regs from inital SP */
1317 int lr_save_offset
; /* offset to save LR from initial SP */
1318 int cr_save_offset
; /* offset to save CR from initial SP */
1319 int vrsave_save_offset
; /* offset to save VRSAVE from initial SP */
1320 int toc_save_offset
; /* offset to save the TOC pointer */
1321 int varargs_save_offset
; /* offset to save the varargs registers */
1322 int ehrd_offset
; /* offset to EH return data */
1323 int reg_size
; /* register size (4 or 8) */
1324 int varargs_size
; /* size to hold V.4 args passed in regs */
1325 int vars_size
; /* variable save area size */
1326 int parm_size
; /* outgoing parameter size */
1327 int save_size
; /* save area size */
1328 int fixed_size
; /* fixed size of stack frame */
1329 int gp_size
; /* size of saved GP registers */
1330 int fp_size
; /* size of saved FP registers */
1331 int altivec_size
; /* size of saved AltiVec registers */
1332 int cr_size
; /* size to hold CR if not in save_size */
1333 int lr_size
; /* size to hold LR if not in save_size */
1334 int vrsave_size
; /* size to hold VRSAVE if not in save_size */
1335 int altivec_padding_size
; /* size of altivec alignment padding if
1337 int toc_size
; /* size to hold TOC if not in save_size */
1338 int total_size
; /* total bytes allocated for stack */
1341 /* Define this if pushing a word on the stack
1342 makes the stack pointer a smaller address. */
1343 #define STACK_GROWS_DOWNWARD
1345 /* Define this if the nominal address of the stack frame
1346 is at the high-address end of the local variables;
1347 that is, each additional local variable allocated
1348 goes at a more negative offset in the frame.
1350 On the RS/6000, we grow upwards, from the area after the outgoing
1352 /* #define FRAME_GROWS_DOWNWARD */
1354 /* Size of the outgoing register save area */
1355 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \
1356 || DEFAULT_ABI == ABI_AIX_NODESC \
1357 || DEFAULT_ABI == ABI_DARWIN) \
1358 ? (TARGET_64BIT ? 64 : 32) \
1361 /* Size of the fixed area on the stack */
1362 #define RS6000_SAVE_AREA \
1363 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \
1364 << (TARGET_64BIT ? 1 : 0))
1366 /* MEM representing address to save the TOC register */
1367 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \
1368 plus_constant (stack_pointer_rtx, \
1369 (TARGET_32BIT ? 20 : 40)))
1371 /* Size of the V.4 varargs area if needed */
1372 #define RS6000_VARARGS_AREA 0
1374 /* Align an address */
1375 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1))
1377 /* Size of V.4 varargs area in bytes */
1378 #define RS6000_VARARGS_SIZE \
1379 ((GP_ARG_NUM_REG * (TARGET_32BIT ? 4 : 8)) + (FP_ARG_NUM_REG * 8) + 8)
1381 /* Offset within stack frame to start allocating local variables at.
1382 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1383 first local allocated. Otherwise, it is the offset to the BEGINNING
1384 of the first local allocated.
1386 On the RS/6000, the frame pointer is the same as the stack pointer,
1387 except for dynamic allocations. So we start after the fixed area and
1388 outgoing parameter area. */
1390 #define STARTING_FRAME_OFFSET \
1391 (RS6000_ALIGN (current_function_outgoing_args_size, \
1392 TARGET_ALTIVEC ? 16 : 8) \
1393 + RS6000_VARARGS_AREA \
1396 /* Offset from the stack pointer register to an item dynamically
1397 allocated on the stack, e.g., by `alloca'.
1399 The default value for this macro is `STACK_POINTER_OFFSET' plus the
1400 length of the outgoing arguments. The default is correct for most
1401 machines. See `function.c' for details. */
1402 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
1403 (RS6000_ALIGN (current_function_outgoing_args_size, \
1404 TARGET_ALTIVEC ? 16 : 8) \
1405 + (STACK_POINTER_OFFSET))
1407 /* If we generate an insn to push BYTES bytes,
1408 this says how many the stack pointer really advances by.
1409 On RS/6000, don't define this because there are no push insns. */
1410 /* #define PUSH_ROUNDING(BYTES) */
1412 /* Offset of first parameter from the argument pointer register value.
1413 On the RS/6000, we define the argument pointer to the start of the fixed
1415 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA
1417 /* Offset from the argument pointer register value to the top of
1418 stack. This is different from FIRST_PARM_OFFSET because of the
1419 register save area. */
1420 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
1422 /* Define this if stack space is still allocated for a parameter passed
1423 in a register. The value is the number of bytes allocated to this
1425 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE
1427 /* Define this if the above stack space is to be considered part of the
1428 space allocated by the caller. */
1429 #define OUTGOING_REG_PARM_STACK_SPACE
1431 /* This is the difference between the logical top of stack and the actual sp.
1433 For the RS/6000, sp points past the fixed area. */
1434 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA
1436 /* Define this if the maximum size of all the outgoing args is to be
1437 accumulated and pushed during the prologue. The amount can be
1438 found in the variable current_function_outgoing_args_size. */
1439 #define ACCUMULATE_OUTGOING_ARGS 1
1441 /* Value is the number of bytes of arguments automatically
1442 popped when returning from a subroutine call.
1443 FUNDECL is the declaration node of the function (as a tree),
1444 FUNTYPE is the data type of the function (as a tree),
1445 or for a library call it is an identifier node for the subroutine name.
1446 SIZE is the number of bytes of arguments passed on the stack. */
1448 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1450 /* Define how to find the value returned by a function.
1451 VALTYPE is the data type of the value (as a tree).
1452 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1453 otherwise, FUNC is 0.
1455 On RS/6000 an integer value is in r3 and a floating-point value is in
1456 fp1, unless -msoft-float. */
1458 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1459 gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \
1460 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
1461 || POINTER_TYPE_P (VALTYPE) \
1462 ? word_mode : TYPE_MODE (VALTYPE), \
1463 TREE_CODE (VALTYPE) == VECTOR_TYPE \
1464 && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \
1465 : TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \
1466 ? FP_ARG_RETURN : GP_ARG_RETURN)
1468 /* Define how to find the value returned by a library function
1469 assuming the value has mode MODE. */
1471 #define LIBCALL_VALUE(MODE) \
1472 gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \
1473 : GET_MODE_CLASS (MODE) == MODE_FLOAT \
1474 && TARGET_HARD_FLOAT \
1475 ? FP_ARG_RETURN : GP_ARG_RETURN)
1477 /* The AIX ABI for the RS/6000 specifies that all structures are
1478 returned in memory. The Darwin ABI does the same. The SVR4 ABI
1479 specifies that structures <= 8 bytes are returned in r3/r4, but a
1480 draft put them in memory, and GCC used to implement the draft
1481 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
1482 controls this instead of DEFAULT_ABI; V.4 targets needing backward
1483 compatibility can change DRAFT_V4_STRUCT_RET to override the
1484 default, and -m switches get the final word. See
1485 rs6000_override_options for more details.
1487 int_size_in_bytes returns -1 for variable size objects, which go in
1488 memory always. The cast to unsigned makes -1 > 8. */
1490 #define RETURN_IN_MEMORY(TYPE) \
1491 (AGGREGATE_TYPE_P (TYPE) && \
1492 (TARGET_AIX_STRUCT_RET || \
1493 (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8))
1495 /* DRAFT_V4_STRUCT_RET defaults off. */
1496 #define DRAFT_V4_STRUCT_RET 0
1498 /* Let RETURN_IN_MEMORY control what happens. */
1499 #define DEFAULT_PCC_STRUCT_RETURN 0
1501 /* Mode of stack savearea.
1502 FUNCTION is VOIDmode because calling convention maintains SP.
1503 BLOCK needs Pmode for SP.
1504 NONLOCAL needs twice Pmode to maintain both backchain and SP. */
1505 #define STACK_SAVEAREA_MODE(LEVEL) \
1506 (LEVEL == SAVE_FUNCTION ? VOIDmode \
1507 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode)
1509 /* Minimum and maximum general purpose registers used to hold arguments. */
1510 #define GP_ARG_MIN_REG 3
1511 #define GP_ARG_MAX_REG 10
1512 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1)
1514 /* Minimum and maximum floating point registers used to hold arguments. */
1515 #define FP_ARG_MIN_REG 33
1516 #define FP_ARG_AIX_MAX_REG 45
1517 #define FP_ARG_V4_MAX_REG 40
1518 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \
1519 || DEFAULT_ABI == ABI_AIX_NODESC \
1520 || DEFAULT_ABI == ABI_DARWIN) \
1521 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG)
1522 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1)
1524 /* Minimum and maximum AltiVec registers used to hold arguments. */
1525 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2)
1526 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11)
1527 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1)
1529 /* Return registers */
1530 #define GP_ARG_RETURN GP_ARG_MIN_REG
1531 #define FP_ARG_RETURN FP_ARG_MIN_REG
1532 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2)
1534 /* Flags for the call/call_value rtl operations set up by function_arg */
1535 #define CALL_NORMAL 0x00000000 /* no special processing */
1536 /* Bits in 0x00000001 are unused. */
1537 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */
1538 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */
1539 #define CALL_LONG 0x00000008 /* always call indirect */
1541 /* 1 if N is a possible register number for a function value
1542 as seen by the caller.
1544 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */
1545 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \
1546 || ((N) == FP_ARG_RETURN) \
1547 || (TARGET_ALTIVEC && \
1548 (N) == ALTIVEC_ARG_RETURN))
1550 /* 1 if N is a possible register number for function argument passing.
1551 On RS/6000, these are r3-r10 and fp1-fp13.
1552 On AltiVec, v2 - v13 are used for passing vectors. */
1553 #define FUNCTION_ARG_REGNO_P(N) \
1554 (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \
1555 || (TARGET_ALTIVEC && \
1556 (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \
1557 || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG)))
1560 /* A C structure for machine-specific, per-function data.
1561 This is added to the cfun structure. */
1562 typedef struct machine_function
GTY(())
1564 /* Whether a System V.4 varargs area was created. */
1566 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
1567 int ra_needs_full_frame
;
1570 /* Define a data type for recording info about an argument list
1571 during the scan of that argument list. This data type should
1572 hold all necessary information about the function itself
1573 and about the args processed so far, enough to enable macros
1574 such as FUNCTION_ARG to determine where the next arg should go.
1576 On the RS/6000, this is a structure. The first element is the number of
1577 total argument words, the second is used to store the next
1578 floating-point register number, and the third says how many more args we
1579 have prototype types for.
1581 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is
1582 the next availible GP register, `fregno' is the next available FP
1583 register, and `words' is the number of words used on the stack.
1585 The varargs/stdarg support requires that this structure's size
1586 be a multiple of sizeof(int). */
1588 typedef struct rs6000_args
1590 int words
; /* # words used for passing GP registers */
1591 int fregno
; /* next available FP register */
1592 int vregno
; /* next available AltiVec register */
1593 int nargs_prototype
; /* # args left in the current prototype */
1594 int orig_nargs
; /* Original value of nargs_prototype */
1595 int prototype
; /* Whether a prototype was defined */
1596 int call_cookie
; /* Do special things for this call */
1597 int sysv_gregno
; /* next available GP register */
1600 /* Define intermediate macro to compute the size (in registers) of an argument
1603 #define RS6000_ARG_SIZE(MODE, TYPE) \
1604 ((MODE) != BLKmode \
1605 ? (GET_MODE_SIZE (MODE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD \
1606 : (int_size_in_bytes (TYPE) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
1608 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1609 for a call to a function whose data type is FNTYPE.
1610 For a library call, FNTYPE is 0. */
1612 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1613 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE)
1615 /* Similar, but when scanning the definition of a procedure. We always
1616 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */
1618 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \
1619 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE)
1621 /* Update the data in CUM to advance over an argument
1622 of mode MODE and data type TYPE.
1623 (TYPE is null for libcalls where that information may not be available.) */
1625 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1626 function_arg_advance (&CUM, MODE, TYPE, NAMED)
1628 /* Non-zero if we can use a floating-point register to pass this arg. */
1629 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
1630 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1631 && (CUM).fregno <= FP_ARG_MAX_REG \
1632 && TARGET_HARD_FLOAT)
1634 /* Non-zero if we can use an AltiVec register to pass this arg. */
1635 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \
1636 (ALTIVEC_VECTOR_MODE (MODE) \
1637 && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \
1638 && TARGET_ALTIVEC_ABI)
1640 /* Determine where to put an argument to a function.
1641 Value is zero to push the argument on the stack,
1642 or a hard register in which to store the argument.
1644 MODE is the argument's machine mode.
1645 TYPE is the data type of the argument (as a tree).
1646 This is null for libcalls where that information may
1648 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1649 the preceding args and about the function being called.
1650 NAMED is nonzero if this argument is a named parameter
1651 (otherwise it is an extra parameter matching an ellipsis).
1653 On RS/6000 the first eight words of non-FP are normally in registers
1654 and the rest are pushed. The first 13 FP args are in registers.
1656 If this is floating-point and no prototype is specified, we use
1657 both an FP and integer register (or possibly FP reg and stack). Library
1658 functions (when TYPE is zero) always have the proper types for args,
1659 so we can pass the FP value just in one register. emit_library_function
1660 doesn't support EXPR_LIST anyway. */
1662 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1663 function_arg (&CUM, MODE, TYPE, NAMED)
1665 /* For an arg passed partly in registers and partly in memory,
1666 this is the number of registers used.
1667 For args passed entirely in registers or entirely in memory, zero. */
1669 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1670 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1672 /* A C expression that indicates when an argument must be passed by
1673 reference. If nonzero for an argument, a copy of that argument is
1674 made in memory and a pointer to the argument is passed instead of
1675 the argument itself. The pointer is passed in whatever way is
1676 appropriate for passing a pointer to that type. */
1678 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
1679 function_arg_pass_by_reference(&CUM, MODE, TYPE, NAMED)
1681 /* If defined, a C expression which determines whether, and in which
1682 direction, to pad out an argument with extra space. The value
1683 should be of type `enum direction': either `upward' to pad above
1684 the argument, `downward' to pad below, or `none' to inhibit
1687 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE)
1689 /* If defined, a C expression that gives the alignment boundary, in bits,
1690 of an argument with the specified mode and type. If it is not defined,
1691 PARM_BOUNDARY is used for all arguments. */
1693 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1694 function_arg_boundary (MODE, TYPE)
1696 /* Perform any needed actions needed for a function that is receiving a
1697 variable number of arguments.
1701 MODE and TYPE are the mode and type of the current parameter.
1703 PRETEND_SIZE is a variable that should be set to the amount of stack
1704 that must be pushed by the prolog to pretend that our caller pushed
1707 Normally, this macro will push all remaining incoming registers on the
1708 stack and set PRETEND_SIZE to the length of the registers pushed. */
1710 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
1711 setup_incoming_varargs (&CUM, MODE, TYPE, &PRETEND_SIZE, NO_RTL)
1713 /* Define the `__builtin_va_list' type for the ABI. */
1714 #define BUILD_VA_LIST_TYPE(VALIST) \
1715 (VALIST) = rs6000_build_va_list ()
1717 /* Implement `va_start' for varargs and stdarg. */
1718 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1719 rs6000_va_start (stdarg, valist, nextarg)
1721 /* Implement `va_arg'. */
1722 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1723 rs6000_va_arg (valist, type)
1725 /* For AIX, the rule is that structures are passed left-aligned in
1726 their stack slot. However, GCC does not presently do this:
1727 structures which are the same size as integer types are passed
1728 right-aligned, as if they were in fact integers. This only
1729 matters for structures of size 1 or 2, or 4 when TARGET_64BIT.
1730 ABI_V4 does not use std_expand_builtin_va_arg. */
1731 #define PAD_VARARGS_DOWN (TYPE_MODE (type) != BLKmode)
1733 /* Define this macro to be a nonzero value if the location where a function
1734 argument is passed depends on whether or not it is a named argument. */
1735 #define STRICT_ARGUMENT_NAMING 1
1737 /* Output assembler code to FILE to increment profiler label # LABELNO
1738 for profiling a function entry. */
1740 #define FUNCTION_PROFILER(FILE, LABELNO) \
1741 output_function_profiler ((FILE), (LABELNO));
1743 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1744 the stack pointer does not matter. No definition is equivalent to
1747 On the RS/6000, this is non-zero because we can restore the stack from
1748 its backpointer, which we maintain. */
1749 #define EXIT_IGNORE_STACK 1
1751 /* Define this macro as a C expression that is nonzero for registers
1752 that are used by the epilogue or the return' pattern. The stack
1753 and frame pointer registers are already be assumed to be used as
1756 #define EPILOGUE_USES(REGNO) \
1757 ((reload_completed && (REGNO) == LINK_REGISTER_REGNUM) \
1758 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \
1759 || (current_function_calls_eh_return \
1761 && (REGNO) == TOC_REGISTER))
1764 /* TRAMPOLINE_TEMPLATE deleted */
1766 /* Length in units of the trampoline for entering a nested function. */
1768 #define TRAMPOLINE_SIZE rs6000_trampoline_size ()
1770 /* Emit RTL insns to initialize the variable parts of a trampoline.
1771 FNADDR is an RTX for the address of the function's pure code.
1772 CXT is an RTX for the static chain value for the function. */
1774 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \
1775 rs6000_initialize_trampoline (ADDR, FNADDR, CXT)
1777 /* Definitions for __builtin_return_address and __builtin_frame_address.
1778 __builtin_return_address (0) should give link register (65), enable
1780 /* This should be uncommented, so that the link register is used, but
1781 currently this would result in unmatched insns and spilling fixed
1782 registers so we'll leave it for another day. When these problems are
1783 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX.
1785 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */
1787 /* Number of bytes into the frame return addresses can be found. See
1788 rs6000_stack_info in rs6000.c for more information on how the different
1789 abi's store the return address. */
1790 #define RETURN_ADDRESS_OFFSET \
1791 ((DEFAULT_ABI == ABI_AIX \
1792 || DEFAULT_ABI == ABI_DARWIN \
1793 || DEFAULT_ABI == ABI_AIX_NODESC) ? (TARGET_32BIT ? 8 : 16) : \
1794 (DEFAULT_ABI == ABI_V4) ? 4 : \
1795 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0))
1797 /* The current return address is in link register (65). The return address
1798 of anything farther back is accessed normally at an offset of 8 from the
1800 #define RETURN_ADDR_RTX(COUNT, FRAME) \
1801 (rs6000_return_addr (COUNT, FRAME))
1804 /* Definitions for register eliminations.
1806 We have two registers that can be eliminated on the RS/6000. First, the
1807 frame pointer register can often be eliminated in favor of the stack
1808 pointer register. Secondly, the argument pointer register can always be
1809 eliminated; it is replaced with either the stack or frame pointer.
1811 In addition, we use the elimination mechanism to see if r30 is needed
1812 Initially we assume that it isn't. If it is, we spill it. This is done
1813 by making it an eliminable register. We replace it with itself so that
1814 if it isn't needed, then existing uses won't be modified. */
1816 /* This is an array of structures. Each structure initializes one pair
1817 of eliminable registers. The "from" register number is given first,
1818 followed by "to". Eliminations of the same "from" register are listed
1819 in order of preference. */
1820 #define ELIMINABLE_REGS \
1821 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1822 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1823 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
1826 /* Given FROM and TO register numbers, say whether this elimination is allowed.
1827 Frame pointer elimination is automatically handled.
1829 For the RS/6000, if frame pointer elimination is being done, we would like
1830 to convert ap into fp, not sp.
1832 We need r30 if -mminimal-toc was specified, and there are constant pool
1835 #define CAN_ELIMINATE(FROM, TO) \
1836 ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \
1837 ? ! frame_pointer_needed \
1838 : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \
1841 /* Define the offset between two registers, one to be eliminated, and the other
1842 its replacement, at the start of a routine. */
1843 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1845 rs6000_stack_t *info = rs6000_stack_info (); \
1847 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1848 (OFFSET) = (info->push_p) ? 0 : - info->total_size; \
1849 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \
1850 (OFFSET) = info->total_size; \
1851 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1852 (OFFSET) = (info->push_p) ? info->total_size : 0; \
1853 else if ((FROM) == 30) \
1859 /* Addressing modes, and classification of registers for them. */
1861 /* #define HAVE_POST_INCREMENT 0 */
1862 /* #define HAVE_POST_DECREMENT 0 */
1864 #define HAVE_PRE_DECREMENT 1
1865 #define HAVE_PRE_INCREMENT 1
1867 /* Macros to check register numbers against specific register classes. */
1869 /* These assume that REGNO is a hard or pseudo reg number.
1870 They give nonzero only if REGNO is a hard reg of the suitable class
1871 or a pseudo reg currently allocated to a suitable hard reg.
1872 Since they use reg_renumber, they are safe only once reg_renumber
1873 has been allocated, which happens in local-alloc.c. */
1875 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1876 ((REGNO) < FIRST_PSEUDO_REGISTER \
1877 ? (REGNO) <= 31 || (REGNO) == 67 \
1878 : (reg_renumber[REGNO] >= 0 \
1879 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1881 #define REGNO_OK_FOR_BASE_P(REGNO) \
1882 ((REGNO) < FIRST_PSEUDO_REGISTER \
1883 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \
1884 : (reg_renumber[REGNO] > 0 \
1885 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67)))
1887 /* Maximum number of registers that can appear in a valid memory address. */
1889 #define MAX_REGS_PER_ADDRESS 2
1891 /* Recognize any constant value that is a valid address. */
1893 #define CONSTANT_ADDRESS_P(X) \
1894 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1895 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1896 || GET_CODE (X) == HIGH)
1898 /* Nonzero if the constant value X is a legitimate general operand.
1899 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1901 On the RS/6000, all integer constants are acceptable, most won't be valid
1902 for particular insns, though. Only easy FP constants are
1905 #define LEGITIMATE_CONSTANT_P(X) \
1906 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \
1907 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \
1908 || easy_fp_constant (X, GET_MODE (X)))
1910 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1911 and check its validity for a certain class.
1912 We have two alternate definitions for each of them.
1913 The usual definition accepts all pseudo regs; the other rejects
1914 them unless they have been allocated suitable hard regs.
1915 The symbol REG_OK_STRICT causes the latter definition to be used.
1917 Most source files want to accept pseudo regs in the hope that
1918 they will get allocated to the class that the insn wants them to be in.
1919 Source files for reload pass need to be strict.
1920 After reload, it makes no difference, since pseudo regs have
1921 been eliminated by then. */
1923 #ifdef REG_OK_STRICT
1924 # define REG_OK_STRICT_FLAG 1
1926 # define REG_OK_STRICT_FLAG 0
1929 /* Nonzero if X is a hard reg that can be used as an index
1930 or if it is a pseudo reg in the non-strict case. */
1931 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \
1933 && (REGNO (X) <= 31 \
1934 || REGNO (X) == ARG_POINTER_REGNUM \
1935 || REGNO (X) >= FIRST_PSEUDO_REGISTER)) \
1936 || ((STRICT) && REGNO_OK_FOR_INDEX_P (REGNO (X))))
1938 /* Nonzero if X is a hard reg that can be used as a base reg
1939 or if it is a pseudo reg in the non-strict case. */
1940 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \
1941 (REGNO (X) > 0 && INT_REG_OK_FOR_INDEX_P (X, (STRICT)))
1943 #define REG_OK_FOR_INDEX_P(X) INT_REG_OK_FOR_INDEX_P (X, REG_OK_STRICT_FLAG)
1944 #define REG_OK_FOR_BASE_P(X) INT_REG_OK_FOR_BASE_P (X, REG_OK_STRICT_FLAG)
1946 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1947 that is a valid memory address for an instruction.
1948 The MODE argument is the machine mode for the MEM expression
1949 that wants to use this address.
1951 On the RS/6000, there are four valid address: a SYMBOL_REF that
1952 refers to a constant pool entry of an address (or the sum of it
1953 plus a constant), a short (16-bit signed) constant plus a register,
1954 the sum of two registers, or a register indirect, possibly with an
1955 auto-increment. For DFmode and DImode with an constant plus register,
1956 we must ensure that both words are addressable or PowerPC64 with offset
1959 For modes spanning multiple registers (DFmode in 32-bit GPRs,
1960 32-bit DImode, TImode), indexed addressing cannot be used because
1961 adjacent memory cells are accessed by adding word-sized offsets
1962 during assembly output. */
1964 #define CONSTANT_POOL_EXPR_P(X) (constant_pool_expr_p (X))
1966 #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X))
1968 #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \
1970 && GET_CODE (X) == PLUS \
1971 && GET_CODE (XEXP (X, 0)) == REG \
1972 && (TARGET_MINIMAL_TOC || REGNO (XEXP (X, 0)) == TOC_REGISTER) \
1973 && CONSTANT_POOL_EXPR_P (XEXP (X, 1)))
1975 #define LEGITIMATE_SMALL_DATA_P(MODE, X) \
1976 (DEFAULT_ABI == ABI_V4 \
1977 && !flag_pic && !TARGET_TOC \
1978 && (GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == CONST) \
1979 && small_data_operand (X, MODE))
1981 #define LEGITIMATE_ADDRESS_INTEGER_P(X, OFFSET) \
1982 (GET_CODE (X) == CONST_INT \
1983 && (unsigned HOST_WIDE_INT) (INTVAL (X) + (OFFSET) + 0x8000) < 0x10000)
1985 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X, STRICT) \
1986 (GET_CODE (X) == PLUS \
1987 && GET_CODE (XEXP (X, 0)) == REG \
1988 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
1989 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \
1990 && (! ALTIVEC_VECTOR_MODE (MODE) \
1991 || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \
1992 && (((MODE) != DFmode && (MODE) != DImode) \
1994 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \
1995 : ! (INTVAL (XEXP (X, 1)) & 3))) \
1996 && ((MODE) != TImode \
1998 ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \
1999 : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \
2000 && ! (INTVAL (XEXP (X, 1)) & 3)))))
2002 #define LEGITIMATE_INDEXED_ADDRESS_P(X, STRICT) \
2003 (GET_CODE (X) == PLUS \
2004 && GET_CODE (XEXP (X, 0)) == REG \
2005 && GET_CODE (XEXP (X, 1)) == REG \
2006 && ((INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2007 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 1), (STRICT))) \
2008 || (INT_REG_OK_FOR_BASE_P (XEXP (X, 1), (STRICT)) \
2009 && INT_REG_OK_FOR_INDEX_P (XEXP (X, 0), (STRICT)))))
2011 #define LEGITIMATE_INDIRECT_ADDRESS_P(X, STRICT) \
2012 (GET_CODE (X) == REG && INT_REG_OK_FOR_BASE_P (X, (STRICT)))
2014 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X, STRICT) \
2016 && ! flag_pic && ! TARGET_TOC \
2017 && GET_MODE_NUNITS (MODE) == 1 \
2018 && (GET_MODE_BITSIZE (MODE) <= 32 \
2019 || (TARGET_HARD_FLOAT && (MODE) == DFmode)) \
2020 && GET_CODE (X) == LO_SUM \
2021 && GET_CODE (XEXP (X, 0)) == REG \
2022 && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \
2023 && CONSTANT_P (XEXP (X, 1)))
2025 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2026 { if (rs6000_legitimate_address (MODE, X, REG_OK_STRICT_FLAG)) \
2030 /* Try machine-dependent ways of modifying an illegitimate address
2031 to be legitimate. If we find one, return the new, valid address.
2032 This macro is used in only one place: `memory_address' in explow.c.
2034 OLDX is the address as it was before break_out_memory_refs was called.
2035 In some cases it is useful to look at this to decide what needs to be done.
2037 MODE and WIN are passed so that this macro can use
2038 GO_IF_LEGITIMATE_ADDRESS.
2040 It is always safe for this macro to do nothing. It exists to recognize
2041 opportunities to optimize the output.
2043 On RS/6000, first check for the sum of a register with a constant
2044 integer that is out of range. If so, generate code to add the
2045 constant with the low-order 16 bits masked to the register and force
2046 this result into another register (this can be done with `cau').
2047 Then generate an address of REG+(CONST&0xffff), allowing for the
2048 possibility of bit 16 being a one.
2050 Then check for the sum of a register and something not constant, try to
2051 load the other things into a register and return the sum. */
2053 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2054 { rtx result = rs6000_legitimize_address (X, OLDX, MODE); \
2055 if (result != NULL_RTX) \
2062 /* Try a machine-dependent way of reloading an illegitimate address
2063 operand. If we find one, push the reload and jump to WIN. This
2064 macro is used in only one place: `find_reloads_address' in reload.c.
2066 Implemented on rs6000 by rs6000_legitimize_reload_address.
2067 Note that (X) is evaluated twice; this is safe in current usage. */
2069 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
2072 (X) = rs6000_legitimize_reload_address ((X), (MODE), (OPNUM), \
2073 (int)(TYPE), (IND_LEVELS), &win); \
2078 /* Go to LABEL if ADDR (a legitimate address expression)
2079 has an effect that depends on the machine mode it is used for.
2081 On the RS/6000 this is true if the address is valid with a zero offset
2082 but not with an offset of four (this means it cannot be used as an
2083 address for DImode or DFmode) or is a pre-increment or decrement. Since
2084 we know it is valid, we just check for an address that is not valid with
2085 an offset of four. */
2087 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
2088 { if (GET_CODE (ADDR) == PLUS \
2089 && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), 0) \
2090 && ! LEGITIMATE_ADDRESS_INTEGER_P (XEXP (ADDR, 1), \
2091 (TARGET_32BIT ? 4 : 8))) \
2093 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_INC) \
2095 if (TARGET_UPDATE && GET_CODE (ADDR) == PRE_DEC) \
2097 if (GET_CODE (ADDR) == LO_SUM) \
2101 /* The register number of the register used to address a table of
2102 static data addresses in memory. In some cases this register is
2103 defined by a processor's "application binary interface" (ABI).
2104 When this macro is defined, RTL is generated for this register
2105 once, as with the stack pointer and frame pointer registers. If
2106 this macro is not defined, it is up to the machine-dependent files
2107 to allocate such a register (if necessary). */
2109 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30
2110 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM)
2112 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2)
2114 /* Define this macro if the register defined by
2115 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define
2116 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */
2118 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */
2120 /* By generating position-independent code, when two different
2121 programs (A and B) share a common library (libC.a), the text of
2122 the library can be shared whether or not the library is linked at
2123 the same address for both programs. In some of these
2124 environments, position-independent code requires not only the use
2125 of different addressing modes, but also special code to enable the
2126 use of these addressing modes.
2128 The `FINALIZE_PIC' macro serves as a hook to emit these special
2129 codes once the function is being compiled into assembly code, but
2130 not before. (It is not done before, because in the case of
2131 compiling an inline function, it would lead to multiple PIC
2132 prologues being included in functions which used inline functions
2133 and were compiled to assembly language.) */
2135 /* #define FINALIZE_PIC */
2137 /* A C expression that is nonzero if X is a legitimate immediate
2138 operand on the target machine when generating position independent
2139 code. You can assume that X satisfies `CONSTANT_P', so you need
2140 not check this. You can also assume FLAG_PIC is true, so you need
2141 not check it either. You need not define this macro if all
2142 constants (including `SYMBOL_REF') can be immediate operands when
2143 generating position independent code. */
2145 /* #define LEGITIMATE_PIC_OPERAND_P (X) */
2147 /* In rare cases, correct code generation requires extra machine
2148 dependent processing between the second jump optimization pass and
2149 delayed branch scheduling. On those machines, define this macro
2150 as a C statement to act on the code starting at INSN. */
2152 /* #define MACHINE_DEPENDENT_REORG(INSN) */
2155 /* Define this if some processing needs to be done immediately before
2156 emitting code for an insn. */
2158 /* #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) */
2160 /* Specify the machine mode that this machine uses
2161 for the index in the tablejump instruction. */
2162 #define CASE_VECTOR_MODE SImode
2164 /* Define as C expression which evaluates to nonzero if the tablejump
2165 instruction expects the table to contain offsets from the address of the
2167 Do not define this if the table should contain absolute addresses. */
2168 #define CASE_VECTOR_PC_RELATIVE 1
2170 /* Define this as 1 if `char' should by default be signed; else as 0. */
2171 #define DEFAULT_SIGNED_CHAR 0
2173 /* This flag, if defined, says the same insns that convert to a signed fixnum
2174 also convert validly to an unsigned one. */
2176 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */
2178 /* Max number of bytes we can move from memory to memory
2179 in one reasonably fast instruction. */
2180 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8)
2181 #define MAX_MOVE_MAX 8
2183 /* Nonzero if access to memory by bytes is no faster than for words.
2184 Also non-zero if doing byte operations (specifically shifts) in registers
2186 #define SLOW_BYTE_ACCESS 1
2188 /* Define if operations between registers always perform the operation
2189 on the full register even if a narrower mode is specified. */
2190 #define WORD_REGISTER_OPERATIONS
2192 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2193 will either zero-extend or sign-extend. The value of this macro should
2194 be the code that says which one of the two operations is implicitly
2195 done, NIL if none. */
2196 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
2198 /* Define if loading short immediate values into registers sign extends. */
2199 #define SHORT_IMMEDIATES_SIGN_EXTEND
2201 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2202 is done just by pretending it is already truncated. */
2203 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2205 /* Specify the machine mode that pointers have.
2206 After generation of rtl, the compiler makes no further distinction
2207 between pointers and any other objects of this machine mode. */
2208 #define Pmode (TARGET_32BIT ? SImode : DImode)
2210 /* Mode of a function address in a call instruction (for indexing purposes).
2211 Doesn't matter on RS/6000. */
2212 #define FUNCTION_MODE (TARGET_32BIT ? SImode : DImode)
2214 /* Define this if addresses of constant functions
2215 shouldn't be put through pseudo regs where they can be cse'd.
2216 Desirable on machines where ordinary constants are expensive
2217 but a CALL with constant address is cheap. */
2218 #define NO_FUNCTION_CSE
2220 /* Define this to be nonzero if shift instructions ignore all but the low-order
2223 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED
2224 have been dropped from the PowerPC architecture. */
2226 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0)
2228 /* Compute the cost of computing a constant rtl expression RTX
2229 whose rtx-code is CODE. The body of this macro is a portion
2230 of a switch statement. If the code is computed here,
2231 return it with a return statement. Otherwise, break from the switch.
2233 On the RS/6000, if it is valid in the insn, it is free. So this
2234 always returns 0. */
2236 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
2241 case CONST_DOUBLE: \
2245 /* Provide the costs of a rtl expression. This is in the body of a
2248 #define RTX_COSTS(X,CODE,OUTER_CODE) \
2250 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2251 && ((unsigned HOST_WIDE_INT) (INTVAL (XEXP (X, 1)) \
2252 + 0x8000) >= 0x10000) \
2253 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2254 ? COSTS_N_INSNS (2) \
2255 : COSTS_N_INSNS (1)); \
2259 return ((GET_CODE (XEXP (X, 1)) == CONST_INT \
2260 && (INTVAL (XEXP (X, 1)) & (~ (HOST_WIDE_INT) 0xffff)) != 0 \
2261 && ((INTVAL (XEXP (X, 1)) & 0xffff) != 0)) \
2262 ? COSTS_N_INSNS (2) \
2263 : COSTS_N_INSNS (1)); \
2265 switch (rs6000_cpu) \
2267 case PROCESSOR_RIOS1: \
2268 case PROCESSOR_PPC405: \
2269 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2270 ? COSTS_N_INSNS (5) \
2271 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2272 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2273 case PROCESSOR_RS64A: \
2274 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2275 ? GET_MODE (XEXP (X, 1)) != DImode \
2276 ? COSTS_N_INSNS (20) : COSTS_N_INSNS (34) \
2277 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2278 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (12)); \
2279 case PROCESSOR_RIOS2: \
2280 case PROCESSOR_MPCCORE: \
2281 case PROCESSOR_PPC604e: \
2282 return COSTS_N_INSNS (2); \
2283 case PROCESSOR_PPC601: \
2284 return COSTS_N_INSNS (5); \
2285 case PROCESSOR_PPC603: \
2286 case PROCESSOR_PPC7400: \
2287 case PROCESSOR_PPC750: \
2288 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2289 ? COSTS_N_INSNS (5) \
2290 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2291 ? COSTS_N_INSNS (2) : COSTS_N_INSNS (3)); \
2292 case PROCESSOR_PPC7450: \
2293 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2294 ? COSTS_N_INSNS (4) \
2295 : COSTS_N_INSNS (3)); \
2296 case PROCESSOR_PPC403: \
2297 case PROCESSOR_PPC604: \
2298 return COSTS_N_INSNS (4); \
2299 case PROCESSOR_PPC620: \
2300 case PROCESSOR_PPC630: \
2301 return (GET_CODE (XEXP (X, 1)) != CONST_INT \
2302 ? GET_MODE (XEXP (X, 1)) != DImode \
2303 ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \
2304 : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \
2305 ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \
2309 if (GET_CODE (XEXP (X, 1)) == CONST_INT \
2310 && exact_log2 (INTVAL (XEXP (X, 1))) >= 0) \
2311 return COSTS_N_INSNS (2); \
2312 /* otherwise fall through to normal divide. */ \
2315 switch (rs6000_cpu) \
2317 case PROCESSOR_RIOS1: \
2318 return COSTS_N_INSNS (19); \
2319 case PROCESSOR_RIOS2: \
2320 return COSTS_N_INSNS (13); \
2321 case PROCESSOR_RS64A: \
2322 return (GET_MODE (XEXP (X, 1)) != DImode \
2323 ? COSTS_N_INSNS (65) \
2324 : COSTS_N_INSNS (67)); \
2325 case PROCESSOR_MPCCORE: \
2326 return COSTS_N_INSNS (6); \
2327 case PROCESSOR_PPC403: \
2328 return COSTS_N_INSNS (33); \
2329 case PROCESSOR_PPC405: \
2330 return COSTS_N_INSNS (35); \
2331 case PROCESSOR_PPC601: \
2332 return COSTS_N_INSNS (36); \
2333 case PROCESSOR_PPC603: \
2334 return COSTS_N_INSNS (37); \
2335 case PROCESSOR_PPC604: \
2336 case PROCESSOR_PPC604e: \
2337 return COSTS_N_INSNS (20); \
2338 case PROCESSOR_PPC620: \
2339 case PROCESSOR_PPC630: \
2340 return (GET_MODE (XEXP (X, 1)) != DImode \
2341 ? COSTS_N_INSNS (21) \
2342 : COSTS_N_INSNS (37)); \
2343 case PROCESSOR_PPC750: \
2344 case PROCESSOR_PPC7400: \
2345 return COSTS_N_INSNS (19); \
2346 case PROCESSOR_PPC7450: \
2347 return COSTS_N_INSNS (23); \
2350 return COSTS_N_INSNS (4); \
2352 /* MEM should be slightly more expensive than (plus (reg) (const)) */ \
2355 /* Compute the cost of an address. This is meant to approximate the size
2356 and/or execution delay of an insn using that address. If the cost is
2357 approximated by the RTL complexity, including CONST_COSTS above, as
2358 is usually the case for CISC machines, this macro should not be defined.
2359 For aggressively RISCy machines, only one insn format is allowed, so
2360 this macro should be a constant. The value of this macro only matters
2361 for valid addresses.
2363 For the RS/6000, everything is cost 0. */
2365 #define ADDRESS_COST(RTX) 0
2367 /* Adjust the length of an INSN. LENGTH is the currently-computed length and
2368 should be adjusted to reflect any required changes. This macro is used when
2369 there is some systematic length adjustment required that would be difficult
2370 to express in the length attribute. */
2372 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */
2374 /* Add any extra modes needed to represent the condition code.
2376 For the RS/6000, we need separate modes when unsigned (logical) comparisons
2377 are being done and we need a separate mode for floating-point. We also
2378 use a mode for the case when we are comparing the results of two
2379 comparisons, as then only the EQ bit is valid in the register. */
2381 #define EXTRA_CC_MODES \
2382 CC(CCUNSmode, "CCUNS") \
2383 CC(CCFPmode, "CCFP") \
2384 CC(CCEQmode, "CCEQ")
2386 /* Given a comparison code (EQ, NE, etc.) and the first operand of a
2387 COMPARE, return the mode to be used for the comparison. For
2388 floating-point, CCFPmode should be used. CCUNSmode should be used
2389 for unsigned comparisons. CCEQmode should be used when we are
2390 doing an inequality comparison on the result of a
2391 comparison. CCmode should be used in all other cases. */
2393 #define SELECT_CC_MODE(OP,X,Y) \
2394 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2395 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \
2396 : (((OP) == EQ || (OP) == NE) && GET_RTX_CLASS (GET_CODE (X)) == '<' \
2397 ? CCEQmode : CCmode))
2399 /* Define the information needed to generate branch and scc insns. This is
2400 stored from the compare operation. Note that we can't use "rtx" here
2401 since it hasn't been defined! */
2403 extern GTY(()) rtx rs6000_compare_op0
;
2404 extern GTY(()) rtx rs6000_compare_op1
;
2405 extern int rs6000_compare_fp_p
;
2407 /* Control the assembler format that we output. */
2409 /* A C string constant describing how to begin a comment in the target
2410 assembler language. The compiler assumes that the comment will end at
2411 the end of the line. */
2412 #define ASM_COMMENT_START " #"
2414 /* Implicit library calls should use memcpy, not bcopy, etc. */
2416 #define TARGET_MEM_FUNCTIONS
2418 /* Flag to say the TOC is initialized */
2419 extern int toc_initialized
;
2421 /* Macro to output a special constant pool entry. Go to WIN if we output
2422 it. Otherwise, it is written the usual way.
2424 On the RS/6000, toc entries are handled this way. */
2426 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \
2427 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \
2429 output_toc (FILE, X, LABELNO, MODE); \
2434 #ifdef HAVE_GAS_WEAK
2435 #define RS6000_WEAK 1
2437 #define RS6000_WEAK 0
2441 /* Used in lieu of ASM_WEAKEN_LABEL. */
2442 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \
2445 fputs ("\t.weak\t", (FILE)); \
2446 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2447 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2448 && DEFAULT_ABI == ABI_AIX) \
2451 fputs ("[DS]", (FILE)); \
2452 fputs ("\n\t.weak\t.", (FILE)); \
2453 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2455 fputc ('\n', (FILE)); \
2458 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \
2459 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \
2460 && DEFAULT_ABI == ABI_AIX) \
2462 fputs ("\t.set\t.", (FILE)); \
2463 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \
2464 fputs (",.", (FILE)); \
2465 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \
2466 fputc ('\n', (FILE)); \
2473 /* This implements the `alias' attribute. */
2474 #undef ASM_OUTPUT_DEF_FROM_DECLS
2475 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \
2478 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
2479 const char *name = IDENTIFIER_POINTER (TARGET); \
2480 if (TREE_CODE (DECL) == FUNCTION_DECL \
2481 && DEFAULT_ABI == ABI_AIX) \
2483 if (TREE_PUBLIC (DECL)) \
2485 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \
2487 fputs ("\t.globl\t.", FILE); \
2488 RS6000_OUTPUT_BASENAME (FILE, alias); \
2489 putc ('\n', FILE); \
2492 else if (TARGET_XCOFF) \
2494 fputs ("\t.lglobl\t.", FILE); \
2495 RS6000_OUTPUT_BASENAME (FILE, alias); \
2496 putc ('\n', FILE); \
2498 fputs ("\t.set\t.", FILE); \
2499 RS6000_OUTPUT_BASENAME (FILE, alias); \
2500 fputs (",.", FILE); \
2501 RS6000_OUTPUT_BASENAME (FILE, name); \
2502 fputc ('\n', FILE); \
2504 ASM_OUTPUT_DEF (FILE, alias, name); \
2508 /* Output to assembler file text saying following lines
2509 may contain character constants, extra white space, comments, etc. */
2511 #define ASM_APP_ON ""
2513 /* Output to assembler file text saying following lines
2514 no longer contain unusual constructs. */
2516 #define ASM_APP_OFF ""
2518 /* How to refer to registers in assembler output.
2519 This sequence is indexed by compiler's hard-register-number (see above). */
2521 extern char rs6000_reg_names
[][8]; /* register names (0 vs. %r0). */
2523 #define REGISTER_NAMES \
2525 &rs6000_reg_names[ 0][0], /* r0 */ \
2526 &rs6000_reg_names[ 1][0], /* r1 */ \
2527 &rs6000_reg_names[ 2][0], /* r2 */ \
2528 &rs6000_reg_names[ 3][0], /* r3 */ \
2529 &rs6000_reg_names[ 4][0], /* r4 */ \
2530 &rs6000_reg_names[ 5][0], /* r5 */ \
2531 &rs6000_reg_names[ 6][0], /* r6 */ \
2532 &rs6000_reg_names[ 7][0], /* r7 */ \
2533 &rs6000_reg_names[ 8][0], /* r8 */ \
2534 &rs6000_reg_names[ 9][0], /* r9 */ \
2535 &rs6000_reg_names[10][0], /* r10 */ \
2536 &rs6000_reg_names[11][0], /* r11 */ \
2537 &rs6000_reg_names[12][0], /* r12 */ \
2538 &rs6000_reg_names[13][0], /* r13 */ \
2539 &rs6000_reg_names[14][0], /* r14 */ \
2540 &rs6000_reg_names[15][0], /* r15 */ \
2541 &rs6000_reg_names[16][0], /* r16 */ \
2542 &rs6000_reg_names[17][0], /* r17 */ \
2543 &rs6000_reg_names[18][0], /* r18 */ \
2544 &rs6000_reg_names[19][0], /* r19 */ \
2545 &rs6000_reg_names[20][0], /* r20 */ \
2546 &rs6000_reg_names[21][0], /* r21 */ \
2547 &rs6000_reg_names[22][0], /* r22 */ \
2548 &rs6000_reg_names[23][0], /* r23 */ \
2549 &rs6000_reg_names[24][0], /* r24 */ \
2550 &rs6000_reg_names[25][0], /* r25 */ \
2551 &rs6000_reg_names[26][0], /* r26 */ \
2552 &rs6000_reg_names[27][0], /* r27 */ \
2553 &rs6000_reg_names[28][0], /* r28 */ \
2554 &rs6000_reg_names[29][0], /* r29 */ \
2555 &rs6000_reg_names[30][0], /* r30 */ \
2556 &rs6000_reg_names[31][0], /* r31 */ \
2558 &rs6000_reg_names[32][0], /* fr0 */ \
2559 &rs6000_reg_names[33][0], /* fr1 */ \
2560 &rs6000_reg_names[34][0], /* fr2 */ \
2561 &rs6000_reg_names[35][0], /* fr3 */ \
2562 &rs6000_reg_names[36][0], /* fr4 */ \
2563 &rs6000_reg_names[37][0], /* fr5 */ \
2564 &rs6000_reg_names[38][0], /* fr6 */ \
2565 &rs6000_reg_names[39][0], /* fr7 */ \
2566 &rs6000_reg_names[40][0], /* fr8 */ \
2567 &rs6000_reg_names[41][0], /* fr9 */ \
2568 &rs6000_reg_names[42][0], /* fr10 */ \
2569 &rs6000_reg_names[43][0], /* fr11 */ \
2570 &rs6000_reg_names[44][0], /* fr12 */ \
2571 &rs6000_reg_names[45][0], /* fr13 */ \
2572 &rs6000_reg_names[46][0], /* fr14 */ \
2573 &rs6000_reg_names[47][0], /* fr15 */ \
2574 &rs6000_reg_names[48][0], /* fr16 */ \
2575 &rs6000_reg_names[49][0], /* fr17 */ \
2576 &rs6000_reg_names[50][0], /* fr18 */ \
2577 &rs6000_reg_names[51][0], /* fr19 */ \
2578 &rs6000_reg_names[52][0], /* fr20 */ \
2579 &rs6000_reg_names[53][0], /* fr21 */ \
2580 &rs6000_reg_names[54][0], /* fr22 */ \
2581 &rs6000_reg_names[55][0], /* fr23 */ \
2582 &rs6000_reg_names[56][0], /* fr24 */ \
2583 &rs6000_reg_names[57][0], /* fr25 */ \
2584 &rs6000_reg_names[58][0], /* fr26 */ \
2585 &rs6000_reg_names[59][0], /* fr27 */ \
2586 &rs6000_reg_names[60][0], /* fr28 */ \
2587 &rs6000_reg_names[61][0], /* fr29 */ \
2588 &rs6000_reg_names[62][0], /* fr30 */ \
2589 &rs6000_reg_names[63][0], /* fr31 */ \
2591 &rs6000_reg_names[64][0], /* mq */ \
2592 &rs6000_reg_names[65][0], /* lr */ \
2593 &rs6000_reg_names[66][0], /* ctr */ \
2594 &rs6000_reg_names[67][0], /* ap */ \
2596 &rs6000_reg_names[68][0], /* cr0 */ \
2597 &rs6000_reg_names[69][0], /* cr1 */ \
2598 &rs6000_reg_names[70][0], /* cr2 */ \
2599 &rs6000_reg_names[71][0], /* cr3 */ \
2600 &rs6000_reg_names[72][0], /* cr4 */ \
2601 &rs6000_reg_names[73][0], /* cr5 */ \
2602 &rs6000_reg_names[74][0], /* cr6 */ \
2603 &rs6000_reg_names[75][0], /* cr7 */ \
2605 &rs6000_reg_names[76][0], /* xer */ \
2607 &rs6000_reg_names[77][0], /* v0 */ \
2608 &rs6000_reg_names[78][0], /* v1 */ \
2609 &rs6000_reg_names[79][0], /* v2 */ \
2610 &rs6000_reg_names[80][0], /* v3 */ \
2611 &rs6000_reg_names[81][0], /* v4 */ \
2612 &rs6000_reg_names[82][0], /* v5 */ \
2613 &rs6000_reg_names[83][0], /* v6 */ \
2614 &rs6000_reg_names[84][0], /* v7 */ \
2615 &rs6000_reg_names[85][0], /* v8 */ \
2616 &rs6000_reg_names[86][0], /* v9 */ \
2617 &rs6000_reg_names[87][0], /* v10 */ \
2618 &rs6000_reg_names[88][0], /* v11 */ \
2619 &rs6000_reg_names[89][0], /* v12 */ \
2620 &rs6000_reg_names[90][0], /* v13 */ \
2621 &rs6000_reg_names[91][0], /* v14 */ \
2622 &rs6000_reg_names[92][0], /* v15 */ \
2623 &rs6000_reg_names[93][0], /* v16 */ \
2624 &rs6000_reg_names[94][0], /* v17 */ \
2625 &rs6000_reg_names[95][0], /* v18 */ \
2626 &rs6000_reg_names[96][0], /* v19 */ \
2627 &rs6000_reg_names[97][0], /* v20 */ \
2628 &rs6000_reg_names[98][0], /* v21 */ \
2629 &rs6000_reg_names[99][0], /* v22 */ \
2630 &rs6000_reg_names[100][0], /* v23 */ \
2631 &rs6000_reg_names[101][0], /* v24 */ \
2632 &rs6000_reg_names[102][0], /* v25 */ \
2633 &rs6000_reg_names[103][0], /* v26 */ \
2634 &rs6000_reg_names[104][0], /* v27 */ \
2635 &rs6000_reg_names[105][0], /* v28 */ \
2636 &rs6000_reg_names[106][0], /* v29 */ \
2637 &rs6000_reg_names[107][0], /* v30 */ \
2638 &rs6000_reg_names[108][0], /* v31 */ \
2639 &rs6000_reg_names[109][0], /* vrsave */ \
2640 &rs6000_reg_names[110][0], /* vscr */ \
2643 /* print-rtl can't handle the above REGISTER_NAMES, so define the
2644 following for it. Switch to use the alternate names since
2645 they are more mnemonic. */
2647 #define DEBUG_REGISTER_NAMES \
2649 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
2650 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
2651 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
2652 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
2653 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
2654 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
2655 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \
2656 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \
2657 "mq", "lr", "ctr", "ap", \
2658 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
2660 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \
2661 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \
2662 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \
2663 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \
2667 /* Table of additional register names to use in user input. */
2669 #define ADDITIONAL_REGISTER_NAMES \
2670 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \
2671 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \
2672 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \
2673 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \
2674 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \
2675 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \
2676 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \
2677 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \
2678 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \
2679 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \
2680 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \
2681 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \
2682 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \
2683 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \
2684 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \
2685 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \
2686 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \
2687 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \
2688 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \
2689 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \
2690 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \
2691 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \
2692 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \
2693 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \
2694 {"vrsave", 109}, {"vscr", 110}, \
2695 /* no additional names for: mq, lr, ctr, ap */ \
2696 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \
2697 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \
2698 {"cc", 68}, {"sp", 1}, {"toc", 2} }
2700 /* Text to write out after a CALL that may be replaced by glue code by
2701 the loader. This depends on the AIX version. */
2702 #define RS6000_CALL_GLUE "cror 31,31,31"
2704 /* This is how to output an element of a case-vector that is relative. */
2706 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
2707 do { char buf[100]; \
2708 fputs ("\t.long ", FILE); \
2709 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
2710 assemble_name (FILE, buf); \
2712 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
2713 assemble_name (FILE, buf); \
2714 putc ('\n', FILE); \
2717 /* This is how to output an assembler line
2718 that says to advance the location counter
2719 to a multiple of 2**LOG bytes. */
2721 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
2723 fprintf (FILE, "\t.align %d\n", (LOG))
2725 /* Store in OUTPUT a string (made with alloca) containing
2726 an assembler-name for a local static variable named NAME.
2727 LABELNO is an integer which is different for each call. */
2729 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
2730 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
2731 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
2733 /* Pick up the return address upon entry to a procedure. Used for
2734 dwarf2 unwind information. This also enables the table driven
2737 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
2738 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LINK_REGISTER_REGNUM)
2740 /* Describe how we implement __builtin_eh_return. */
2741 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM)
2742 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10)
2744 /* Print operand X (an rtx) in assembler syntax to file FILE.
2745 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2746 For `%' followed by punctuation, CODE is the punctuation and X is null. */
2748 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2750 /* Define which CODE values are valid. */
2752 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2755 /* Print a memory address as an operand to reference that memory location. */
2757 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2759 /* Define the codes that are matched by predicates in rs6000.c. */
2761 #define PREDICATE_CODES \
2762 {"any_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2763 LABEL_REF, SUBREG, REG, MEM, PARALLEL}}, \
2764 {"zero_constant", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
2765 LABEL_REF, SUBREG, REG, MEM}}, \
2766 {"short_cint_operand", {CONST_INT}}, \
2767 {"u_short_cint_operand", {CONST_INT}}, \
2768 {"non_short_cint_operand", {CONST_INT}}, \
2769 {"exact_log2_cint_operand", {CONST_INT}}, \
2770 {"gpc_reg_operand", {SUBREG, REG}}, \
2771 {"cc_reg_operand", {SUBREG, REG}}, \
2772 {"cc_reg_not_cr0_operand", {SUBREG, REG}}, \
2773 {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \
2774 {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \
2775 {"reg_or_aligned_short_operand", {SUBREG, REG, CONST_INT}}, \
2776 {"reg_or_u_short_operand", {SUBREG, REG, CONST_INT}}, \
2777 {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \
2778 {"reg_or_arith_cint_operand", {SUBREG, REG, CONST_INT}}, \
2779 {"reg_or_add_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2780 {"reg_or_sub_cint64_operand", {SUBREG, REG, CONST_INT}}, \
2781 {"reg_or_logical_cint_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2782 {"got_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \
2783 {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \
2784 {"easy_fp_constant", {CONST_DOUBLE}}, \
2785 {"zero_fp_constant", {CONST_DOUBLE}}, \
2786 {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \
2787 {"lwa_operand", {SUBREG, MEM, REG}}, \
2788 {"volatile_mem_operand", {MEM}}, \
2789 {"offsettable_mem_operand", {MEM}}, \
2790 {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}}, \
2791 {"add_operand", {SUBREG, REG, CONST_INT}}, \
2792 {"non_add_cint_operand", {CONST_INT}}, \
2793 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2794 {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2795 {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2796 {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \
2797 {"mask_operand", {CONST_INT}}, \
2798 {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \
2799 {"count_register_operand", {REG}}, \
2800 {"xer_operand", {REG}}, \
2801 {"symbol_ref_operand", {SYMBOL_REF}}, \
2802 {"call_operand", {SYMBOL_REF, REG}}, \
2803 {"current_file_function_operand", {SYMBOL_REF}}, \
2804 {"input_operand", {SUBREG, MEM, REG, CONST_INT, \
2805 CONST_DOUBLE, SYMBOL_REF}}, \
2806 {"load_multiple_operation", {PARALLEL}}, \
2807 {"store_multiple_operation", {PARALLEL}}, \
2808 {"vrsave_operation", {PARALLEL}}, \
2809 {"branch_comparison_operator", {EQ, NE, LE, LT, GE, \
2810 GT, LEU, LTU, GEU, GTU, \
2811 UNORDERED, ORDERED, \
2813 {"branch_positive_comparison_operator", {EQ, LT, GT, LTU, GTU, \
2815 {"scc_comparison_operator", {EQ, NE, LE, LT, GE, \
2816 GT, LEU, LTU, GEU, GTU, \
2817 UNORDERED, ORDERED, \
2819 {"trap_comparison_operator", {EQ, NE, LE, LT, GE, \
2820 GT, LEU, LTU, GEU, GTU}}, \
2821 {"boolean_operator", {AND, IOR, XOR}}, \
2822 {"boolean_or_operator", {IOR, XOR}}, \
2823 {"altivec_register_operand", {REG}}, \
2824 {"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
2826 /* uncomment for disabling the corresponding default options */
2827 /* #define MACHINE_no_sched_interblock */
2828 /* #define MACHINE_no_sched_speculative */
2829 /* #define MACHINE_no_sched_speculative_load */
2831 /* General flags. */
2832 extern int flag_pic
;
2833 extern int optimize
;
2834 extern int flag_expensive_optimizations
;
2835 extern int frame_pointer_needed
;
2837 enum rs6000_builtins
2839 /* AltiVec builtins. */
2840 ALTIVEC_BUILTIN_ST_INTERNAL_4si
,
2841 ALTIVEC_BUILTIN_LD_INTERNAL_4si
,
2842 ALTIVEC_BUILTIN_ST_INTERNAL_8hi
,
2843 ALTIVEC_BUILTIN_LD_INTERNAL_8hi
,
2844 ALTIVEC_BUILTIN_ST_INTERNAL_16qi
,
2845 ALTIVEC_BUILTIN_LD_INTERNAL_16qi
,
2846 ALTIVEC_BUILTIN_ST_INTERNAL_4sf
,
2847 ALTIVEC_BUILTIN_LD_INTERNAL_4sf
,
2848 ALTIVEC_BUILTIN_VADDUBM
,
2849 ALTIVEC_BUILTIN_VADDUHM
,
2850 ALTIVEC_BUILTIN_VADDUWM
,
2851 ALTIVEC_BUILTIN_VADDFP
,
2852 ALTIVEC_BUILTIN_VADDCUW
,
2853 ALTIVEC_BUILTIN_VADDUBS
,
2854 ALTIVEC_BUILTIN_VADDSBS
,
2855 ALTIVEC_BUILTIN_VADDUHS
,
2856 ALTIVEC_BUILTIN_VADDSHS
,
2857 ALTIVEC_BUILTIN_VADDUWS
,
2858 ALTIVEC_BUILTIN_VADDSWS
,
2859 ALTIVEC_BUILTIN_VAND
,
2860 ALTIVEC_BUILTIN_VANDC
,
2861 ALTIVEC_BUILTIN_VAVGUB
,
2862 ALTIVEC_BUILTIN_VAVGSB
,
2863 ALTIVEC_BUILTIN_VAVGUH
,
2864 ALTIVEC_BUILTIN_VAVGSH
,
2865 ALTIVEC_BUILTIN_VAVGUW
,
2866 ALTIVEC_BUILTIN_VAVGSW
,
2867 ALTIVEC_BUILTIN_VCFUX
,
2868 ALTIVEC_BUILTIN_VCFSX
,
2869 ALTIVEC_BUILTIN_VCTSXS
,
2870 ALTIVEC_BUILTIN_VCTUXS
,
2871 ALTIVEC_BUILTIN_VCMPBFP
,
2872 ALTIVEC_BUILTIN_VCMPEQUB
,
2873 ALTIVEC_BUILTIN_VCMPEQUH
,
2874 ALTIVEC_BUILTIN_VCMPEQUW
,
2875 ALTIVEC_BUILTIN_VCMPEQFP
,
2876 ALTIVEC_BUILTIN_VCMPGEFP
,
2877 ALTIVEC_BUILTIN_VCMPGTUB
,
2878 ALTIVEC_BUILTIN_VCMPGTSB
,
2879 ALTIVEC_BUILTIN_VCMPGTUH
,
2880 ALTIVEC_BUILTIN_VCMPGTSH
,
2881 ALTIVEC_BUILTIN_VCMPGTUW
,
2882 ALTIVEC_BUILTIN_VCMPGTSW
,
2883 ALTIVEC_BUILTIN_VCMPGTFP
,
2884 ALTIVEC_BUILTIN_VEXPTEFP
,
2885 ALTIVEC_BUILTIN_VLOGEFP
,
2886 ALTIVEC_BUILTIN_VMADDFP
,
2887 ALTIVEC_BUILTIN_VMAXUB
,
2888 ALTIVEC_BUILTIN_VMAXSB
,
2889 ALTIVEC_BUILTIN_VMAXUH
,
2890 ALTIVEC_BUILTIN_VMAXSH
,
2891 ALTIVEC_BUILTIN_VMAXUW
,
2892 ALTIVEC_BUILTIN_VMAXSW
,
2893 ALTIVEC_BUILTIN_VMAXFP
,
2894 ALTIVEC_BUILTIN_VMHADDSHS
,
2895 ALTIVEC_BUILTIN_VMHRADDSHS
,
2896 ALTIVEC_BUILTIN_VMLADDUHM
,
2897 ALTIVEC_BUILTIN_VMRGHB
,
2898 ALTIVEC_BUILTIN_VMRGHH
,
2899 ALTIVEC_BUILTIN_VMRGHW
,
2900 ALTIVEC_BUILTIN_VMRGLB
,
2901 ALTIVEC_BUILTIN_VMRGLH
,
2902 ALTIVEC_BUILTIN_VMRGLW
,
2903 ALTIVEC_BUILTIN_VMSUMUBM
,
2904 ALTIVEC_BUILTIN_VMSUMMBM
,
2905 ALTIVEC_BUILTIN_VMSUMUHM
,
2906 ALTIVEC_BUILTIN_VMSUMSHM
,
2907 ALTIVEC_BUILTIN_VMSUMUHS
,
2908 ALTIVEC_BUILTIN_VMSUMSHS
,
2909 ALTIVEC_BUILTIN_VMINUB
,
2910 ALTIVEC_BUILTIN_VMINSB
,
2911 ALTIVEC_BUILTIN_VMINUH
,
2912 ALTIVEC_BUILTIN_VMINSH
,
2913 ALTIVEC_BUILTIN_VMINUW
,
2914 ALTIVEC_BUILTIN_VMINSW
,
2915 ALTIVEC_BUILTIN_VMINFP
,
2916 ALTIVEC_BUILTIN_VMULEUB
,
2917 ALTIVEC_BUILTIN_VMULESB
,
2918 ALTIVEC_BUILTIN_VMULEUH
,
2919 ALTIVEC_BUILTIN_VMULESH
,
2920 ALTIVEC_BUILTIN_VMULOUB
,
2921 ALTIVEC_BUILTIN_VMULOSB
,
2922 ALTIVEC_BUILTIN_VMULOUH
,
2923 ALTIVEC_BUILTIN_VMULOSH
,
2924 ALTIVEC_BUILTIN_VNMSUBFP
,
2925 ALTIVEC_BUILTIN_VNOR
,
2926 ALTIVEC_BUILTIN_VOR
,
2927 ALTIVEC_BUILTIN_VSEL_4SI
,
2928 ALTIVEC_BUILTIN_VSEL_4SF
,
2929 ALTIVEC_BUILTIN_VSEL_8HI
,
2930 ALTIVEC_BUILTIN_VSEL_16QI
,
2931 ALTIVEC_BUILTIN_VPERM_4SI
,
2932 ALTIVEC_BUILTIN_VPERM_4SF
,
2933 ALTIVEC_BUILTIN_VPERM_8HI
,
2934 ALTIVEC_BUILTIN_VPERM_16QI
,
2935 ALTIVEC_BUILTIN_VPKUHUM
,
2936 ALTIVEC_BUILTIN_VPKUWUM
,
2937 ALTIVEC_BUILTIN_VPKPX
,
2938 ALTIVEC_BUILTIN_VPKUHSS
,
2939 ALTIVEC_BUILTIN_VPKSHSS
,
2940 ALTIVEC_BUILTIN_VPKUWSS
,
2941 ALTIVEC_BUILTIN_VPKSWSS
,
2942 ALTIVEC_BUILTIN_VPKUHUS
,
2943 ALTIVEC_BUILTIN_VPKSHUS
,
2944 ALTIVEC_BUILTIN_VPKUWUS
,
2945 ALTIVEC_BUILTIN_VPKSWUS
,
2946 ALTIVEC_BUILTIN_VREFP
,
2947 ALTIVEC_BUILTIN_VRFIM
,
2948 ALTIVEC_BUILTIN_VRFIN
,
2949 ALTIVEC_BUILTIN_VRFIP
,
2950 ALTIVEC_BUILTIN_VRFIZ
,
2951 ALTIVEC_BUILTIN_VRLB
,
2952 ALTIVEC_BUILTIN_VRLH
,
2953 ALTIVEC_BUILTIN_VRLW
,
2954 ALTIVEC_BUILTIN_VRSQRTEFP
,
2955 ALTIVEC_BUILTIN_VSLB
,
2956 ALTIVEC_BUILTIN_VSLH
,
2957 ALTIVEC_BUILTIN_VSLW
,
2958 ALTIVEC_BUILTIN_VSL
,
2959 ALTIVEC_BUILTIN_VSLO
,
2960 ALTIVEC_BUILTIN_VSPLTB
,
2961 ALTIVEC_BUILTIN_VSPLTH
,
2962 ALTIVEC_BUILTIN_VSPLTW
,
2963 ALTIVEC_BUILTIN_VSPLTISB
,
2964 ALTIVEC_BUILTIN_VSPLTISH
,
2965 ALTIVEC_BUILTIN_VSPLTISW
,
2966 ALTIVEC_BUILTIN_VSRB
,
2967 ALTIVEC_BUILTIN_VSRH
,
2968 ALTIVEC_BUILTIN_VSRW
,
2969 ALTIVEC_BUILTIN_VSRAB
,
2970 ALTIVEC_BUILTIN_VSRAH
,
2971 ALTIVEC_BUILTIN_VSRAW
,
2972 ALTIVEC_BUILTIN_VSR
,
2973 ALTIVEC_BUILTIN_VSRO
,
2974 ALTIVEC_BUILTIN_VSUBUBM
,
2975 ALTIVEC_BUILTIN_VSUBUHM
,
2976 ALTIVEC_BUILTIN_VSUBUWM
,
2977 ALTIVEC_BUILTIN_VSUBFP
,
2978 ALTIVEC_BUILTIN_VSUBCUW
,
2979 ALTIVEC_BUILTIN_VSUBUBS
,
2980 ALTIVEC_BUILTIN_VSUBSBS
,
2981 ALTIVEC_BUILTIN_VSUBUHS
,
2982 ALTIVEC_BUILTIN_VSUBSHS
,
2983 ALTIVEC_BUILTIN_VSUBUWS
,
2984 ALTIVEC_BUILTIN_VSUBSWS
,
2985 ALTIVEC_BUILTIN_VSUM4UBS
,
2986 ALTIVEC_BUILTIN_VSUM4SBS
,
2987 ALTIVEC_BUILTIN_VSUM4SHS
,
2988 ALTIVEC_BUILTIN_VSUM2SWS
,
2989 ALTIVEC_BUILTIN_VSUMSWS
,
2990 ALTIVEC_BUILTIN_VXOR
,
2991 ALTIVEC_BUILTIN_VSLDOI_16QI
,
2992 ALTIVEC_BUILTIN_VSLDOI_8HI
,
2993 ALTIVEC_BUILTIN_VSLDOI_4SI
,
2994 ALTIVEC_BUILTIN_VSLDOI_4SF
,
2995 ALTIVEC_BUILTIN_VUPKHSB
,
2996 ALTIVEC_BUILTIN_VUPKHPX
,
2997 ALTIVEC_BUILTIN_VUPKHSH
,
2998 ALTIVEC_BUILTIN_VUPKLSB
,
2999 ALTIVEC_BUILTIN_VUPKLPX
,
3000 ALTIVEC_BUILTIN_VUPKLSH
,
3001 ALTIVEC_BUILTIN_MTVSCR
,
3002 ALTIVEC_BUILTIN_MFVSCR
,
3003 ALTIVEC_BUILTIN_DSSALL
,
3004 ALTIVEC_BUILTIN_DSS
,
3005 ALTIVEC_BUILTIN_LVSL
,
3006 ALTIVEC_BUILTIN_LVSR
,
3007 ALTIVEC_BUILTIN_DSTT
,
3008 ALTIVEC_BUILTIN_DSTST
,
3009 ALTIVEC_BUILTIN_DSTSTT
,
3010 ALTIVEC_BUILTIN_DST
,
3011 ALTIVEC_BUILTIN_LVEBX
,
3012 ALTIVEC_BUILTIN_LVEHX
,
3013 ALTIVEC_BUILTIN_LVEWX
,
3014 ALTIVEC_BUILTIN_LVXL
,
3015 ALTIVEC_BUILTIN_LVX
,
3016 ALTIVEC_BUILTIN_STVX
,
3017 ALTIVEC_BUILTIN_STVEBX
,
3018 ALTIVEC_BUILTIN_STVEHX
,
3019 ALTIVEC_BUILTIN_STVEWX
,
3020 ALTIVEC_BUILTIN_STVXL
,
3021 ALTIVEC_BUILTIN_VCMPBFP_P
,
3022 ALTIVEC_BUILTIN_VCMPEQFP_P
,
3023 ALTIVEC_BUILTIN_VCMPEQUB_P
,
3024 ALTIVEC_BUILTIN_VCMPEQUH_P
,
3025 ALTIVEC_BUILTIN_VCMPEQUW_P
,
3026 ALTIVEC_BUILTIN_VCMPGEFP_P
,
3027 ALTIVEC_BUILTIN_VCMPGTFP_P
,
3028 ALTIVEC_BUILTIN_VCMPGTSB_P
,
3029 ALTIVEC_BUILTIN_VCMPGTSH_P
,
3030 ALTIVEC_BUILTIN_VCMPGTSW_P
,
3031 ALTIVEC_BUILTIN_VCMPGTUB_P
,
3032 ALTIVEC_BUILTIN_VCMPGTUH_P
,
3033 ALTIVEC_BUILTIN_VCMPGTUW_P
,
3034 ALTIVEC_BUILTIN_ABSS_V4SI
,
3035 ALTIVEC_BUILTIN_ABSS_V8HI
,
3036 ALTIVEC_BUILTIN_ABSS_V16QI
,
3037 ALTIVEC_BUILTIN_ABS_V4SI
,
3038 ALTIVEC_BUILTIN_ABS_V4SF
,
3039 ALTIVEC_BUILTIN_ABS_V8HI
,
3040 ALTIVEC_BUILTIN_ABS_V16QI