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1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6
7 ;; This file is part of GCC.
8
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 2, or (at your
12 ;; option) any later version.
13
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
18
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the
21 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 ;; MA 02110-1301, USA.
23
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25
26 ;;
27 ;; UNSPEC usage
28 ;;
29
30 (define_constants
31 [(UNSPEC_FRSP 0) ; frsp for POWER machines
32 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
33 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
34 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
35 (UNSPEC_MOVSI_GOT 8)
36 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
37 (UNSPEC_FCTIWZ 10)
38 (UNSPEC_FRIM 11)
39 (UNSPEC_FRIN 12)
40 (UNSPEC_FRIP 13)
41 (UNSPEC_FRIZ 14)
42 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
43 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
44 (UNSPEC_TLSGD 17)
45 (UNSPEC_TLSLD 18)
46 (UNSPEC_MOVESI_FROM_CR 19)
47 (UNSPEC_MOVESI_TO_CR 20)
48 (UNSPEC_TLSDTPREL 21)
49 (UNSPEC_TLSDTPRELHA 22)
50 (UNSPEC_TLSDTPRELLO 23)
51 (UNSPEC_TLSGOTDTPREL 24)
52 (UNSPEC_TLSTPREL 25)
53 (UNSPEC_TLSTPRELHA 26)
54 (UNSPEC_TLSTPRELLO 27)
55 (UNSPEC_TLSGOTTPREL 28)
56 (UNSPEC_TLSTLS 29)
57 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
58 (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit
59 (UNSPEC_STFIWX 32)
60 (UNSPEC_POPCNTB 33)
61 (UNSPEC_FRES 34)
62 (UNSPEC_SP_SET 35)
63 (UNSPEC_SP_TEST 36)
64 (UNSPEC_SYNC 37)
65 (UNSPEC_LWSYNC 38)
66 (UNSPEC_ISYNC 39)
67 (UNSPEC_SYNC_OP 40)
68 (UNSPEC_ATOMIC 41)
69 (UNSPEC_CMPXCHG 42)
70 (UNSPEC_XCHG 43)
71 (UNSPEC_AND 44)
72 (UNSPEC_DLMZB 45)
73 (UNSPEC_DLMZB_CR 46)
74 (UNSPEC_DLMZB_STRLEN 47)
75 ])
76
77 ;;
78 ;; UNSPEC_VOLATILE usage
79 ;;
80
81 (define_constants
82 [(UNSPECV_BLOCK 0)
83 (UNSPECV_LL 1) ; load-locked
84 (UNSPECV_SC 2) ; store-conditional
85 (UNSPECV_EH_RR 9) ; eh_reg_restore
86 ])
87 \f
88 ;; Define an insn type attribute. This is used in function unit delay
89 ;; computations.
90 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c"
91 (const_string "integer"))
92
93 ;; Length (in bytes).
94 ; '(pc)' in the following doesn't include the instruction itself; it is
95 ; calculated as if the instruction had zero size.
96 (define_attr "length" ""
97 (if_then_else (eq_attr "type" "branch")
98 (if_then_else (and (ge (minus (match_dup 0) (pc))
99 (const_int -32768))
100 (lt (minus (match_dup 0) (pc))
101 (const_int 32764)))
102 (const_int 4)
103 (const_int 8))
104 (const_int 4)))
105
106 ;; Processor type -- this attribute must exactly match the processor_type
107 ;; enumeration in rs6000.h.
108
109 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5"
110 (const (symbol_ref "rs6000_cpu_attr")))
111
112 (automata_option "ndfa")
113
114 (include "rios1.md")
115 (include "rios2.md")
116 (include "rs64.md")
117 (include "mpc.md")
118 (include "40x.md")
119 (include "440.md")
120 (include "603.md")
121 (include "6xx.md")
122 (include "7xx.md")
123 (include "7450.md")
124 (include "8540.md")
125 (include "power4.md")
126 (include "power5.md")
127
128 (include "predicates.md")
129
130 (include "darwin.md")
131
132 \f
133 ;; Mode macros
134
135 ; This mode macro allows :GPR to be used to indicate the allowable size
136 ; of whole values in GPRs.
137 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
138
139 ; Any supported integer mode.
140 (define_mode_macro INT [QI HI SI DI TI])
141
142 ; Any supported integer mode that fits in one register.
143 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
144
145 ; extend modes for DImode
146 (define_mode_macro QHSI [QI HI SI])
147
148 ; SImode or DImode, even if DImode doesn't fit in GPRs.
149 (define_mode_macro SDI [SI DI])
150
151 ; The size of a pointer. Also, the size of the value that a record-condition
152 ; (one with a '.') will compare.
153 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
154
155 ; Any hardware-supported floating-point mode
156 (define_mode_macro FP [(SF "TARGET_HARD_FLOAT")
157 (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)")
158 (TF "!TARGET_IEEEQUAD
159 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")])
160
161 ; Various instructions that come in SI and DI forms.
162 ; A generic w/d attribute, for things like cmpw/cmpd.
163 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
164
165 ; DImode bits
166 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
167
168 \f
169 ;; Start with fixed-point load and store insns. Here we put only the more
170 ;; complex forms. Basic data transfer is done later.
171
172 (define_expand "zero_extend<mode>di2"
173 [(set (match_operand:DI 0 "gpc_reg_operand" "")
174 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
175 "TARGET_POWERPC64"
176 "")
177
178 (define_insn "*zero_extend<mode>di2_internal1"
179 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
180 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
181 "TARGET_POWERPC64"
182 "@
183 l<wd>z%U1%X1 %0,%1
184 rldicl %0,%1,0,<dbits>"
185 [(set_attr "type" "load,*")])
186
187 (define_insn "*zero_extend<mode>di2_internal2"
188 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
189 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
190 (const_int 0)))
191 (clobber (match_scratch:DI 2 "=r,r"))]
192 "TARGET_64BIT"
193 "@
194 rldicl. %2,%1,0,<dbits>
195 #"
196 [(set_attr "type" "compare")
197 (set_attr "length" "4,8")])
198
199 (define_split
200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
201 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
202 (const_int 0)))
203 (clobber (match_scratch:DI 2 ""))]
204 "TARGET_POWERPC64 && reload_completed"
205 [(set (match_dup 2)
206 (zero_extend:DI (match_dup 1)))
207 (set (match_dup 0)
208 (compare:CC (match_dup 2)
209 (const_int 0)))]
210 "")
211
212 (define_insn "*zero_extend<mode>di2_internal3"
213 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
214 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
215 (const_int 0)))
216 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
217 (zero_extend:DI (match_dup 1)))]
218 "TARGET_64BIT"
219 "@
220 rldicl. %0,%1,0,<dbits>
221 #"
222 [(set_attr "type" "compare")
223 (set_attr "length" "4,8")])
224
225 (define_split
226 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
227 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
228 (const_int 0)))
229 (set (match_operand:DI 0 "gpc_reg_operand" "")
230 (zero_extend:DI (match_dup 1)))]
231 "TARGET_POWERPC64 && reload_completed"
232 [(set (match_dup 0)
233 (zero_extend:DI (match_dup 1)))
234 (set (match_dup 2)
235 (compare:CC (match_dup 0)
236 (const_int 0)))]
237 "")
238
239 (define_insn "extendqidi2"
240 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
241 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
242 "TARGET_POWERPC64"
243 "extsb %0,%1")
244
245 (define_insn ""
246 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
247 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
248 (const_int 0)))
249 (clobber (match_scratch:DI 2 "=r,r"))]
250 "TARGET_64BIT"
251 "@
252 extsb. %2,%1
253 #"
254 [(set_attr "type" "compare")
255 (set_attr "length" "4,8")])
256
257 (define_split
258 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
259 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
260 (const_int 0)))
261 (clobber (match_scratch:DI 2 ""))]
262 "TARGET_POWERPC64 && reload_completed"
263 [(set (match_dup 2)
264 (sign_extend:DI (match_dup 1)))
265 (set (match_dup 0)
266 (compare:CC (match_dup 2)
267 (const_int 0)))]
268 "")
269
270 (define_insn ""
271 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
272 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
273 (const_int 0)))
274 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
275 (sign_extend:DI (match_dup 1)))]
276 "TARGET_64BIT"
277 "@
278 extsb. %0,%1
279 #"
280 [(set_attr "type" "compare")
281 (set_attr "length" "4,8")])
282
283 (define_split
284 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
285 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
286 (const_int 0)))
287 (set (match_operand:DI 0 "gpc_reg_operand" "")
288 (sign_extend:DI (match_dup 1)))]
289 "TARGET_POWERPC64 && reload_completed"
290 [(set (match_dup 0)
291 (sign_extend:DI (match_dup 1)))
292 (set (match_dup 2)
293 (compare:CC (match_dup 0)
294 (const_int 0)))]
295 "")
296
297 (define_expand "extendhidi2"
298 [(set (match_operand:DI 0 "gpc_reg_operand" "")
299 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
300 "TARGET_POWERPC64"
301 "")
302
303 (define_insn ""
304 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
305 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
306 "TARGET_POWERPC64"
307 "@
308 lha%U1%X1 %0,%1
309 extsh %0,%1"
310 [(set_attr "type" "load_ext,*")])
311
312 (define_insn ""
313 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
314 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
315 (const_int 0)))
316 (clobber (match_scratch:DI 2 "=r,r"))]
317 "TARGET_64BIT"
318 "@
319 extsh. %2,%1
320 #"
321 [(set_attr "type" "compare")
322 (set_attr "length" "4,8")])
323
324 (define_split
325 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
326 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
327 (const_int 0)))
328 (clobber (match_scratch:DI 2 ""))]
329 "TARGET_POWERPC64 && reload_completed"
330 [(set (match_dup 2)
331 (sign_extend:DI (match_dup 1)))
332 (set (match_dup 0)
333 (compare:CC (match_dup 2)
334 (const_int 0)))]
335 "")
336
337 (define_insn ""
338 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
339 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
340 (const_int 0)))
341 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
342 (sign_extend:DI (match_dup 1)))]
343 "TARGET_64BIT"
344 "@
345 extsh. %0,%1
346 #"
347 [(set_attr "type" "compare")
348 (set_attr "length" "4,8")])
349
350 (define_split
351 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
352 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
353 (const_int 0)))
354 (set (match_operand:DI 0 "gpc_reg_operand" "")
355 (sign_extend:DI (match_dup 1)))]
356 "TARGET_POWERPC64 && reload_completed"
357 [(set (match_dup 0)
358 (sign_extend:DI (match_dup 1)))
359 (set (match_dup 2)
360 (compare:CC (match_dup 0)
361 (const_int 0)))]
362 "")
363
364 (define_expand "extendsidi2"
365 [(set (match_operand:DI 0 "gpc_reg_operand" "")
366 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
367 "TARGET_POWERPC64"
368 "")
369
370 (define_insn ""
371 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
372 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
373 "TARGET_POWERPC64"
374 "@
375 lwa%U1%X1 %0,%1
376 extsw %0,%1"
377 [(set_attr "type" "load_ext,*")])
378
379 (define_insn ""
380 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
381 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
382 (const_int 0)))
383 (clobber (match_scratch:DI 2 "=r,r"))]
384 "TARGET_64BIT"
385 "@
386 extsw. %2,%1
387 #"
388 [(set_attr "type" "compare")
389 (set_attr "length" "4,8")])
390
391 (define_split
392 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
393 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
394 (const_int 0)))
395 (clobber (match_scratch:DI 2 ""))]
396 "TARGET_POWERPC64 && reload_completed"
397 [(set (match_dup 2)
398 (sign_extend:DI (match_dup 1)))
399 (set (match_dup 0)
400 (compare:CC (match_dup 2)
401 (const_int 0)))]
402 "")
403
404 (define_insn ""
405 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
406 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
407 (const_int 0)))
408 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
409 (sign_extend:DI (match_dup 1)))]
410 "TARGET_64BIT"
411 "@
412 extsw. %0,%1
413 #"
414 [(set_attr "type" "compare")
415 (set_attr "length" "4,8")])
416
417 (define_split
418 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
419 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
420 (const_int 0)))
421 (set (match_operand:DI 0 "gpc_reg_operand" "")
422 (sign_extend:DI (match_dup 1)))]
423 "TARGET_POWERPC64 && reload_completed"
424 [(set (match_dup 0)
425 (sign_extend:DI (match_dup 1)))
426 (set (match_dup 2)
427 (compare:CC (match_dup 0)
428 (const_int 0)))]
429 "")
430
431 (define_expand "zero_extendqisi2"
432 [(set (match_operand:SI 0 "gpc_reg_operand" "")
433 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
434 ""
435 "")
436
437 (define_insn ""
438 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
439 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
440 ""
441 "@
442 lbz%U1%X1 %0,%1
443 {rlinm|rlwinm} %0,%1,0,0xff"
444 [(set_attr "type" "load,*")])
445
446 (define_insn ""
447 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
448 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
449 (const_int 0)))
450 (clobber (match_scratch:SI 2 "=r,r"))]
451 ""
452 "@
453 {andil.|andi.} %2,%1,0xff
454 #"
455 [(set_attr "type" "compare")
456 (set_attr "length" "4,8")])
457
458 (define_split
459 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
460 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
461 (const_int 0)))
462 (clobber (match_scratch:SI 2 ""))]
463 "reload_completed"
464 [(set (match_dup 2)
465 (zero_extend:SI (match_dup 1)))
466 (set (match_dup 0)
467 (compare:CC (match_dup 2)
468 (const_int 0)))]
469 "")
470
471 (define_insn ""
472 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
473 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
474 (const_int 0)))
475 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
476 (zero_extend:SI (match_dup 1)))]
477 ""
478 "@
479 {andil.|andi.} %0,%1,0xff
480 #"
481 [(set_attr "type" "compare")
482 (set_attr "length" "4,8")])
483
484 (define_split
485 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
486 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
487 (const_int 0)))
488 (set (match_operand:SI 0 "gpc_reg_operand" "")
489 (zero_extend:SI (match_dup 1)))]
490 "reload_completed"
491 [(set (match_dup 0)
492 (zero_extend:SI (match_dup 1)))
493 (set (match_dup 2)
494 (compare:CC (match_dup 0)
495 (const_int 0)))]
496 "")
497
498 (define_expand "extendqisi2"
499 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
500 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
501 ""
502 "
503 {
504 if (TARGET_POWERPC)
505 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
506 else if (TARGET_POWER)
507 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
508 else
509 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
510 DONE;
511 }")
512
513 (define_insn "extendqisi2_ppc"
514 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
515 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
516 "TARGET_POWERPC"
517 "extsb %0,%1")
518
519 (define_insn ""
520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
521 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
522 (const_int 0)))
523 (clobber (match_scratch:SI 2 "=r,r"))]
524 "TARGET_POWERPC"
525 "@
526 extsb. %2,%1
527 #"
528 [(set_attr "type" "compare")
529 (set_attr "length" "4,8")])
530
531 (define_split
532 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
533 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
534 (const_int 0)))
535 (clobber (match_scratch:SI 2 ""))]
536 "TARGET_POWERPC && reload_completed"
537 [(set (match_dup 2)
538 (sign_extend:SI (match_dup 1)))
539 (set (match_dup 0)
540 (compare:CC (match_dup 2)
541 (const_int 0)))]
542 "")
543
544 (define_insn ""
545 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
546 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
547 (const_int 0)))
548 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
549 (sign_extend:SI (match_dup 1)))]
550 "TARGET_POWERPC"
551 "@
552 extsb. %0,%1
553 #"
554 [(set_attr "type" "compare")
555 (set_attr "length" "4,8")])
556
557 (define_split
558 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
559 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
560 (const_int 0)))
561 (set (match_operand:SI 0 "gpc_reg_operand" "")
562 (sign_extend:SI (match_dup 1)))]
563 "TARGET_POWERPC && reload_completed"
564 [(set (match_dup 0)
565 (sign_extend:SI (match_dup 1)))
566 (set (match_dup 2)
567 (compare:CC (match_dup 0)
568 (const_int 0)))]
569 "")
570
571 (define_expand "extendqisi2_power"
572 [(parallel [(set (match_dup 2)
573 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
574 (const_int 24)))
575 (clobber (scratch:SI))])
576 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
577 (ashiftrt:SI (match_dup 2)
578 (const_int 24)))
579 (clobber (scratch:SI))])]
580 "TARGET_POWER"
581 "
582 { operands[1] = gen_lowpart (SImode, operands[1]);
583 operands[2] = gen_reg_rtx (SImode); }")
584
585 (define_expand "extendqisi2_no_power"
586 [(set (match_dup 2)
587 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
588 (const_int 24)))
589 (set (match_operand:SI 0 "gpc_reg_operand" "")
590 (ashiftrt:SI (match_dup 2)
591 (const_int 24)))]
592 "! TARGET_POWER && ! TARGET_POWERPC"
593 "
594 { operands[1] = gen_lowpart (SImode, operands[1]);
595 operands[2] = gen_reg_rtx (SImode); }")
596
597 (define_expand "zero_extendqihi2"
598 [(set (match_operand:HI 0 "gpc_reg_operand" "")
599 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
600 ""
601 "")
602
603 (define_insn ""
604 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
605 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
606 ""
607 "@
608 lbz%U1%X1 %0,%1
609 {rlinm|rlwinm} %0,%1,0,0xff"
610 [(set_attr "type" "load,*")])
611
612 (define_insn ""
613 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
614 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
615 (const_int 0)))
616 (clobber (match_scratch:HI 2 "=r,r"))]
617 ""
618 "@
619 {andil.|andi.} %2,%1,0xff
620 #"
621 [(set_attr "type" "compare")
622 (set_attr "length" "4,8")])
623
624 (define_split
625 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
626 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
627 (const_int 0)))
628 (clobber (match_scratch:HI 2 ""))]
629 "reload_completed"
630 [(set (match_dup 2)
631 (zero_extend:HI (match_dup 1)))
632 (set (match_dup 0)
633 (compare:CC (match_dup 2)
634 (const_int 0)))]
635 "")
636
637 (define_insn ""
638 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
639 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
640 (const_int 0)))
641 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
642 (zero_extend:HI (match_dup 1)))]
643 ""
644 "@
645 {andil.|andi.} %0,%1,0xff
646 #"
647 [(set_attr "type" "compare")
648 (set_attr "length" "4,8")])
649
650 (define_split
651 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
652 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
653 (const_int 0)))
654 (set (match_operand:HI 0 "gpc_reg_operand" "")
655 (zero_extend:HI (match_dup 1)))]
656 "reload_completed"
657 [(set (match_dup 0)
658 (zero_extend:HI (match_dup 1)))
659 (set (match_dup 2)
660 (compare:CC (match_dup 0)
661 (const_int 0)))]
662 "")
663
664 (define_expand "extendqihi2"
665 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
666 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
667 ""
668 "
669 {
670 if (TARGET_POWERPC)
671 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
672 else if (TARGET_POWER)
673 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
674 else
675 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
676 DONE;
677 }")
678
679 (define_insn "extendqihi2_ppc"
680 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
681 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
682 "TARGET_POWERPC"
683 "extsb %0,%1")
684
685 (define_insn ""
686 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
687 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
688 (const_int 0)))
689 (clobber (match_scratch:HI 2 "=r,r"))]
690 "TARGET_POWERPC"
691 "@
692 extsb. %2,%1
693 #"
694 [(set_attr "type" "compare")
695 (set_attr "length" "4,8")])
696
697 (define_split
698 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
699 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
700 (const_int 0)))
701 (clobber (match_scratch:HI 2 ""))]
702 "TARGET_POWERPC && reload_completed"
703 [(set (match_dup 2)
704 (sign_extend:HI (match_dup 1)))
705 (set (match_dup 0)
706 (compare:CC (match_dup 2)
707 (const_int 0)))]
708 "")
709
710 (define_insn ""
711 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
712 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
713 (const_int 0)))
714 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
715 (sign_extend:HI (match_dup 1)))]
716 "TARGET_POWERPC"
717 "@
718 extsb. %0,%1
719 #"
720 [(set_attr "type" "compare")
721 (set_attr "length" "4,8")])
722
723 (define_split
724 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
725 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
726 (const_int 0)))
727 (set (match_operand:HI 0 "gpc_reg_operand" "")
728 (sign_extend:HI (match_dup 1)))]
729 "TARGET_POWERPC && reload_completed"
730 [(set (match_dup 0)
731 (sign_extend:HI (match_dup 1)))
732 (set (match_dup 2)
733 (compare:CC (match_dup 0)
734 (const_int 0)))]
735 "")
736
737 (define_expand "extendqihi2_power"
738 [(parallel [(set (match_dup 2)
739 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
740 (const_int 24)))
741 (clobber (scratch:SI))])
742 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
743 (ashiftrt:SI (match_dup 2)
744 (const_int 24)))
745 (clobber (scratch:SI))])]
746 "TARGET_POWER"
747 "
748 { operands[0] = gen_lowpart (SImode, operands[0]);
749 operands[1] = gen_lowpart (SImode, operands[1]);
750 operands[2] = gen_reg_rtx (SImode); }")
751
752 (define_expand "extendqihi2_no_power"
753 [(set (match_dup 2)
754 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
755 (const_int 24)))
756 (set (match_operand:HI 0 "gpc_reg_operand" "")
757 (ashiftrt:SI (match_dup 2)
758 (const_int 24)))]
759 "! TARGET_POWER && ! TARGET_POWERPC"
760 "
761 { operands[0] = gen_lowpart (SImode, operands[0]);
762 operands[1] = gen_lowpart (SImode, operands[1]);
763 operands[2] = gen_reg_rtx (SImode); }")
764
765 (define_expand "zero_extendhisi2"
766 [(set (match_operand:SI 0 "gpc_reg_operand" "")
767 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
768 ""
769 "")
770
771 (define_insn ""
772 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
773 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
774 ""
775 "@
776 lhz%U1%X1 %0,%1
777 {rlinm|rlwinm} %0,%1,0,0xffff"
778 [(set_attr "type" "load,*")])
779
780 (define_insn ""
781 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
782 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
783 (const_int 0)))
784 (clobber (match_scratch:SI 2 "=r,r"))]
785 ""
786 "@
787 {andil.|andi.} %2,%1,0xffff
788 #"
789 [(set_attr "type" "compare")
790 (set_attr "length" "4,8")])
791
792 (define_split
793 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
794 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
795 (const_int 0)))
796 (clobber (match_scratch:SI 2 ""))]
797 "reload_completed"
798 [(set (match_dup 2)
799 (zero_extend:SI (match_dup 1)))
800 (set (match_dup 0)
801 (compare:CC (match_dup 2)
802 (const_int 0)))]
803 "")
804
805 (define_insn ""
806 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
807 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
808 (const_int 0)))
809 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
810 (zero_extend:SI (match_dup 1)))]
811 ""
812 "@
813 {andil.|andi.} %0,%1,0xffff
814 #"
815 [(set_attr "type" "compare")
816 (set_attr "length" "4,8")])
817
818 (define_split
819 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
820 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
821 (const_int 0)))
822 (set (match_operand:SI 0 "gpc_reg_operand" "")
823 (zero_extend:SI (match_dup 1)))]
824 "reload_completed"
825 [(set (match_dup 0)
826 (zero_extend:SI (match_dup 1)))
827 (set (match_dup 2)
828 (compare:CC (match_dup 0)
829 (const_int 0)))]
830 "")
831
832 (define_expand "extendhisi2"
833 [(set (match_operand:SI 0 "gpc_reg_operand" "")
834 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
835 ""
836 "")
837
838 (define_insn ""
839 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
840 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
841 ""
842 "@
843 lha%U1%X1 %0,%1
844 {exts|extsh} %0,%1"
845 [(set_attr "type" "load_ext,*")])
846
847 (define_insn ""
848 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
849 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
850 (const_int 0)))
851 (clobber (match_scratch:SI 2 "=r,r"))]
852 ""
853 "@
854 {exts.|extsh.} %2,%1
855 #"
856 [(set_attr "type" "compare")
857 (set_attr "length" "4,8")])
858
859 (define_split
860 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
861 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
862 (const_int 0)))
863 (clobber (match_scratch:SI 2 ""))]
864 "reload_completed"
865 [(set (match_dup 2)
866 (sign_extend:SI (match_dup 1)))
867 (set (match_dup 0)
868 (compare:CC (match_dup 2)
869 (const_int 0)))]
870 "")
871
872 (define_insn ""
873 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
874 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
875 (const_int 0)))
876 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
877 (sign_extend:SI (match_dup 1)))]
878 ""
879 "@
880 {exts.|extsh.} %0,%1
881 #"
882 [(set_attr "type" "compare")
883 (set_attr "length" "4,8")])
884 \f
885 ;; IBM 405 and 440 half-word multiplication operations.
886
887 (define_insn "*macchwc"
888 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
889 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
890 (match_operand:SI 2 "gpc_reg_operand" "r")
891 (const_int 16))
892 (sign_extend:SI
893 (match_operand:HI 1 "gpc_reg_operand" "r")))
894 (match_operand:SI 4 "gpc_reg_operand" "0"))
895 (const_int 0)))
896 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
897 (plus:SI (mult:SI (ashiftrt:SI
898 (match_dup 2)
899 (const_int 16))
900 (sign_extend:SI
901 (match_dup 1)))
902 (match_dup 4)))]
903 "TARGET_MULHW"
904 "macchw. %0, %1, %2"
905 [(set_attr "type" "imul3")])
906
907 (define_insn "*macchw"
908 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
909 (plus:SI (mult:SI (ashiftrt:SI
910 (match_operand:SI 2 "gpc_reg_operand" "r")
911 (const_int 16))
912 (sign_extend:SI
913 (match_operand:HI 1 "gpc_reg_operand" "r")))
914 (match_operand:SI 3 "gpc_reg_operand" "0")))]
915 "TARGET_MULHW"
916 "macchw %0, %1, %2"
917 [(set_attr "type" "imul3")])
918
919 (define_insn "*macchwuc"
920 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
921 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
922 (match_operand:SI 2 "gpc_reg_operand" "r")
923 (const_int 16))
924 (zero_extend:SI
925 (match_operand:HI 1 "gpc_reg_operand" "r")))
926 (match_operand:SI 4 "gpc_reg_operand" "0"))
927 (const_int 0)))
928 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
929 (plus:SI (mult:SI (lshiftrt:SI
930 (match_dup 2)
931 (const_int 16))
932 (zero_extend:SI
933 (match_dup 1)))
934 (match_dup 4)))]
935 "TARGET_MULHW"
936 "macchwu. %0, %1, %2"
937 [(set_attr "type" "imul3")])
938
939 (define_insn "*macchwu"
940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
941 (plus:SI (mult:SI (lshiftrt:SI
942 (match_operand:SI 2 "gpc_reg_operand" "r")
943 (const_int 16))
944 (zero_extend:SI
945 (match_operand:HI 1 "gpc_reg_operand" "r")))
946 (match_operand:SI 3 "gpc_reg_operand" "0")))]
947 "TARGET_MULHW"
948 "macchwu %0, %1, %2"
949 [(set_attr "type" "imul3")])
950
951 (define_insn "*machhwc"
952 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
953 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
954 (match_operand:SI 1 "gpc_reg_operand" "%r")
955 (const_int 16))
956 (ashiftrt:SI
957 (match_operand:SI 2 "gpc_reg_operand" "r")
958 (const_int 16)))
959 (match_operand:SI 4 "gpc_reg_operand" "0"))
960 (const_int 0)))
961 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
962 (plus:SI (mult:SI (ashiftrt:SI
963 (match_dup 1)
964 (const_int 16))
965 (ashiftrt:SI
966 (match_dup 2)
967 (const_int 16)))
968 (match_dup 4)))]
969 "TARGET_MULHW"
970 "machhw. %0, %1, %2"
971 [(set_attr "type" "imul3")])
972
973 (define_insn "*machhw"
974 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
975 (plus:SI (mult:SI (ashiftrt:SI
976 (match_operand:SI 1 "gpc_reg_operand" "%r")
977 (const_int 16))
978 (ashiftrt:SI
979 (match_operand:SI 2 "gpc_reg_operand" "r")
980 (const_int 16)))
981 (match_operand:SI 3 "gpc_reg_operand" "0")))]
982 "TARGET_MULHW"
983 "machhw %0, %1, %2"
984 [(set_attr "type" "imul3")])
985
986 (define_insn "*machhwuc"
987 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
988 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
989 (match_operand:SI 1 "gpc_reg_operand" "%r")
990 (const_int 16))
991 (lshiftrt:SI
992 (match_operand:SI 2 "gpc_reg_operand" "r")
993 (const_int 16)))
994 (match_operand:SI 4 "gpc_reg_operand" "0"))
995 (const_int 0)))
996 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
997 (plus:SI (mult:SI (lshiftrt:SI
998 (match_dup 1)
999 (const_int 16))
1000 (lshiftrt:SI
1001 (match_dup 2)
1002 (const_int 16)))
1003 (match_dup 4)))]
1004 "TARGET_MULHW"
1005 "machhwu. %0, %1, %2"
1006 [(set_attr "type" "imul3")])
1007
1008 (define_insn "*machhwu"
1009 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1010 (plus:SI (mult:SI (lshiftrt:SI
1011 (match_operand:SI 1 "gpc_reg_operand" "%r")
1012 (const_int 16))
1013 (lshiftrt:SI
1014 (match_operand:SI 2 "gpc_reg_operand" "r")
1015 (const_int 16)))
1016 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1017 "TARGET_MULHW"
1018 "machhwu %0, %1, %2"
1019 [(set_attr "type" "imul3")])
1020
1021 (define_insn "*maclhwc"
1022 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1023 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1024 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1025 (sign_extend:SI
1026 (match_operand:HI 2 "gpc_reg_operand" "r")))
1027 (match_operand:SI 4 "gpc_reg_operand" "0"))
1028 (const_int 0)))
1029 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1030 (plus:SI (mult:SI (sign_extend:SI
1031 (match_dup 1))
1032 (sign_extend:SI
1033 (match_dup 2)))
1034 (match_dup 4)))]
1035 "TARGET_MULHW"
1036 "maclhw. %0, %1, %2"
1037 [(set_attr "type" "imul3")])
1038
1039 (define_insn "*maclhw"
1040 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1041 (plus:SI (mult:SI (sign_extend:SI
1042 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1043 (sign_extend:SI
1044 (match_operand:HI 2 "gpc_reg_operand" "r")))
1045 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1046 "TARGET_MULHW"
1047 "maclhw %0, %1, %2"
1048 [(set_attr "type" "imul3")])
1049
1050 (define_insn "*maclhwuc"
1051 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1052 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1053 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1054 (zero_extend:SI
1055 (match_operand:HI 2 "gpc_reg_operand" "r")))
1056 (match_operand:SI 4 "gpc_reg_operand" "0"))
1057 (const_int 0)))
1058 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1059 (plus:SI (mult:SI (zero_extend:SI
1060 (match_dup 1))
1061 (zero_extend:SI
1062 (match_dup 2)))
1063 (match_dup 4)))]
1064 "TARGET_MULHW"
1065 "maclhwu. %0, %1, %2"
1066 [(set_attr "type" "imul3")])
1067
1068 (define_insn "*maclhwu"
1069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1070 (plus:SI (mult:SI (zero_extend:SI
1071 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1072 (zero_extend:SI
1073 (match_operand:HI 2 "gpc_reg_operand" "r")))
1074 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1075 "TARGET_MULHW"
1076 "maclhwu %0, %1, %2"
1077 [(set_attr "type" "imul3")])
1078
1079 (define_insn "*nmacchwc"
1080 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1081 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1082 (mult:SI (ashiftrt:SI
1083 (match_operand:SI 2 "gpc_reg_operand" "r")
1084 (const_int 16))
1085 (sign_extend:SI
1086 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1087 (const_int 0)))
1088 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1089 (minus:SI (match_dup 4)
1090 (mult:SI (ashiftrt:SI
1091 (match_dup 2)
1092 (const_int 16))
1093 (sign_extend:SI
1094 (match_dup 1)))))]
1095 "TARGET_MULHW"
1096 "nmacchw. %0, %1, %2"
1097 [(set_attr "type" "imul3")])
1098
1099 (define_insn "*nmacchw"
1100 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1101 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1102 (mult:SI (ashiftrt:SI
1103 (match_operand:SI 2 "gpc_reg_operand" "r")
1104 (const_int 16))
1105 (sign_extend:SI
1106 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1107 "TARGET_MULHW"
1108 "nmacchw %0, %1, %2"
1109 [(set_attr "type" "imul3")])
1110
1111 (define_insn "*nmachhwc"
1112 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1113 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1114 (mult:SI (ashiftrt:SI
1115 (match_operand:SI 1 "gpc_reg_operand" "%r")
1116 (const_int 16))
1117 (ashiftrt:SI
1118 (match_operand:SI 2 "gpc_reg_operand" "r")
1119 (const_int 16))))
1120 (const_int 0)))
1121 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1122 (minus:SI (match_dup 4)
1123 (mult:SI (ashiftrt:SI
1124 (match_dup 1)
1125 (const_int 16))
1126 (ashiftrt:SI
1127 (match_dup 2)
1128 (const_int 16)))))]
1129 "TARGET_MULHW"
1130 "nmachhw. %0, %1, %2"
1131 [(set_attr "type" "imul3")])
1132
1133 (define_insn "*nmachhw"
1134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1135 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1136 (mult:SI (ashiftrt:SI
1137 (match_operand:SI 1 "gpc_reg_operand" "%r")
1138 (const_int 16))
1139 (ashiftrt:SI
1140 (match_operand:SI 2 "gpc_reg_operand" "r")
1141 (const_int 16)))))]
1142 "TARGET_MULHW"
1143 "nmachhw %0, %1, %2"
1144 [(set_attr "type" "imul3")])
1145
1146 (define_insn "*nmaclhwc"
1147 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1148 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1149 (mult:SI (sign_extend:SI
1150 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1151 (sign_extend:SI
1152 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1153 (const_int 0)))
1154 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1155 (minus:SI (match_dup 4)
1156 (mult:SI (sign_extend:SI
1157 (match_dup 1))
1158 (sign_extend:SI
1159 (match_dup 2)))))]
1160 "TARGET_MULHW"
1161 "nmaclhw. %0, %1, %2"
1162 [(set_attr "type" "imul3")])
1163
1164 (define_insn "*nmaclhw"
1165 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1166 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1167 (mult:SI (sign_extend:SI
1168 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1169 (sign_extend:SI
1170 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1171 "TARGET_MULHW"
1172 "nmaclhw %0, %1, %2"
1173 [(set_attr "type" "imul3")])
1174
1175 (define_insn "*mulchwc"
1176 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1177 (compare:CC (mult:SI (ashiftrt:SI
1178 (match_operand:SI 2 "gpc_reg_operand" "r")
1179 (const_int 16))
1180 (sign_extend:SI
1181 (match_operand:HI 1 "gpc_reg_operand" "r")))
1182 (const_int 0)))
1183 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1184 (mult:SI (ashiftrt:SI
1185 (match_dup 2)
1186 (const_int 16))
1187 (sign_extend:SI
1188 (match_dup 1))))]
1189 "TARGET_MULHW"
1190 "mulchw. %0, %1, %2"
1191 [(set_attr "type" "imul3")])
1192
1193 (define_insn "*mulchw"
1194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1195 (mult:SI (ashiftrt:SI
1196 (match_operand:SI 2 "gpc_reg_operand" "r")
1197 (const_int 16))
1198 (sign_extend:SI
1199 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1200 "TARGET_MULHW"
1201 "mulchw %0, %1, %2"
1202 [(set_attr "type" "imul3")])
1203
1204 (define_insn "*mulchwuc"
1205 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1206 (compare:CC (mult:SI (lshiftrt:SI
1207 (match_operand:SI 2 "gpc_reg_operand" "r")
1208 (const_int 16))
1209 (zero_extend:SI
1210 (match_operand:HI 1 "gpc_reg_operand" "r")))
1211 (const_int 0)))
1212 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1213 (mult:SI (lshiftrt:SI
1214 (match_dup 2)
1215 (const_int 16))
1216 (zero_extend:SI
1217 (match_dup 1))))]
1218 "TARGET_MULHW"
1219 "mulchwu. %0, %1, %2"
1220 [(set_attr "type" "imul3")])
1221
1222 (define_insn "*mulchwu"
1223 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1224 (mult:SI (lshiftrt:SI
1225 (match_operand:SI 2 "gpc_reg_operand" "r")
1226 (const_int 16))
1227 (zero_extend:SI
1228 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1229 "TARGET_MULHW"
1230 "mulchwu %0, %1, %2"
1231 [(set_attr "type" "imul3")])
1232
1233 (define_insn "*mulhhwc"
1234 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1235 (compare:CC (mult:SI (ashiftrt:SI
1236 (match_operand:SI 1 "gpc_reg_operand" "%r")
1237 (const_int 16))
1238 (ashiftrt:SI
1239 (match_operand:SI 2 "gpc_reg_operand" "r")
1240 (const_int 16)))
1241 (const_int 0)))
1242 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1243 (mult:SI (ashiftrt:SI
1244 (match_dup 1)
1245 (const_int 16))
1246 (ashiftrt:SI
1247 (match_dup 2)
1248 (const_int 16))))]
1249 "TARGET_MULHW"
1250 "mulhhw. %0, %1, %2"
1251 [(set_attr "type" "imul3")])
1252
1253 (define_insn "*mulhhw"
1254 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1255 (mult:SI (ashiftrt:SI
1256 (match_operand:SI 1 "gpc_reg_operand" "%r")
1257 (const_int 16))
1258 (ashiftrt:SI
1259 (match_operand:SI 2 "gpc_reg_operand" "r")
1260 (const_int 16))))]
1261 "TARGET_MULHW"
1262 "mulhhw %0, %1, %2"
1263 [(set_attr "type" "imul3")])
1264
1265 (define_insn "*mulhhwuc"
1266 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1267 (compare:CC (mult:SI (lshiftrt:SI
1268 (match_operand:SI 1 "gpc_reg_operand" "%r")
1269 (const_int 16))
1270 (lshiftrt:SI
1271 (match_operand:SI 2 "gpc_reg_operand" "r")
1272 (const_int 16)))
1273 (const_int 0)))
1274 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1275 (mult:SI (lshiftrt:SI
1276 (match_dup 1)
1277 (const_int 16))
1278 (lshiftrt:SI
1279 (match_dup 2)
1280 (const_int 16))))]
1281 "TARGET_MULHW"
1282 "mulhhwu. %0, %1, %2"
1283 [(set_attr "type" "imul3")])
1284
1285 (define_insn "*mulhhwu"
1286 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1287 (mult:SI (lshiftrt:SI
1288 (match_operand:SI 1 "gpc_reg_operand" "%r")
1289 (const_int 16))
1290 (lshiftrt:SI
1291 (match_operand:SI 2 "gpc_reg_operand" "r")
1292 (const_int 16))))]
1293 "TARGET_MULHW"
1294 "mulhhwu %0, %1, %2"
1295 [(set_attr "type" "imul3")])
1296
1297 (define_insn "*mullhwc"
1298 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1299 (compare:CC (mult:SI (sign_extend:SI
1300 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1301 (sign_extend:SI
1302 (match_operand:HI 2 "gpc_reg_operand" "r")))
1303 (const_int 0)))
1304 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1305 (mult:SI (sign_extend:SI
1306 (match_dup 1))
1307 (sign_extend:SI
1308 (match_dup 2))))]
1309 "TARGET_MULHW"
1310 "mullhw. %0, %1, %2"
1311 [(set_attr "type" "imul3")])
1312
1313 (define_insn "*mullhw"
1314 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1315 (mult:SI (sign_extend:SI
1316 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1317 (sign_extend:SI
1318 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1319 "TARGET_MULHW"
1320 "mullhw %0, %1, %2"
1321 [(set_attr "type" "imul3")])
1322
1323 (define_insn "*mullhwuc"
1324 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1325 (compare:CC (mult:SI (zero_extend:SI
1326 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1327 (zero_extend:SI
1328 (match_operand:HI 2 "gpc_reg_operand" "r")))
1329 (const_int 0)))
1330 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1331 (mult:SI (zero_extend:SI
1332 (match_dup 1))
1333 (zero_extend:SI
1334 (match_dup 2))))]
1335 "TARGET_MULHW"
1336 "mullhwu. %0, %1, %2"
1337 [(set_attr "type" "imul3")])
1338
1339 (define_insn "*mullhwu"
1340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1341 (mult:SI (zero_extend:SI
1342 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1343 (zero_extend:SI
1344 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1345 "TARGET_MULHW"
1346 "mullhwu %0, %1, %2"
1347 [(set_attr "type" "imul3")])
1348 \f
1349 ;; IBM 405 and 440 string-search dlmzb instruction support.
1350 (define_insn "dlmzb"
1351 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1352 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1353 (match_operand:SI 2 "gpc_reg_operand" "r")]
1354 UNSPEC_DLMZB_CR))
1355 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1356 (unspec:SI [(match_dup 1)
1357 (match_dup 2)]
1358 UNSPEC_DLMZB))]
1359 "TARGET_DLMZB"
1360 "dlmzb. %0, %1, %2")
1361
1362 (define_expand "strlensi"
1363 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1364 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1365 (match_operand:QI 2 "const_int_operand" "")
1366 (match_operand 3 "const_int_operand" "")]
1367 UNSPEC_DLMZB_STRLEN))
1368 (clobber (match_scratch:CC 4 "=x"))]
1369 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1370 {
1371 rtx result = operands[0];
1372 rtx src = operands[1];
1373 rtx search_char = operands[2];
1374 rtx align = operands[3];
1375 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1376 rtx loop_label, end_label, mem, cr0, cond;
1377 if (search_char != const0_rtx
1378 || GET_CODE (align) != CONST_INT
1379 || INTVAL (align) < 8)
1380 FAIL;
1381 word1 = gen_reg_rtx (SImode);
1382 word2 = gen_reg_rtx (SImode);
1383 scratch_dlmzb = gen_reg_rtx (SImode);
1384 scratch_string = gen_reg_rtx (Pmode);
1385 loop_label = gen_label_rtx ();
1386 end_label = gen_label_rtx ();
1387 addr = force_reg (Pmode, XEXP (src, 0));
1388 emit_move_insn (scratch_string, addr);
1389 emit_label (loop_label);
1390 mem = change_address (src, SImode, scratch_string);
1391 emit_move_insn (word1, mem);
1392 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1393 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1394 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1395 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1396 emit_jump_insn (gen_rtx_SET (VOIDmode,
1397 pc_rtx,
1398 gen_rtx_IF_THEN_ELSE (VOIDmode,
1399 cond,
1400 gen_rtx_LABEL_REF
1401 (VOIDmode,
1402 end_label),
1403 pc_rtx)));
1404 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1405 emit_jump_insn (gen_rtx_SET (VOIDmode,
1406 pc_rtx,
1407 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1408 emit_barrier ();
1409 emit_label (end_label);
1410 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1411 emit_insn (gen_subsi3 (result, scratch_string, addr));
1412 emit_insn (gen_subsi3 (result, result, const1_rtx));
1413 DONE;
1414 })
1415 \f
1416 (define_split
1417 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1418 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1419 (const_int 0)))
1420 (set (match_operand:SI 0 "gpc_reg_operand" "")
1421 (sign_extend:SI (match_dup 1)))]
1422 "reload_completed"
1423 [(set (match_dup 0)
1424 (sign_extend:SI (match_dup 1)))
1425 (set (match_dup 2)
1426 (compare:CC (match_dup 0)
1427 (const_int 0)))]
1428 "")
1429
1430 ;; Fixed-point arithmetic insns.
1431
1432 (define_expand "add<mode>3"
1433 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1434 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1435 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1436 ""
1437 "
1438 {
1439 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1440 {
1441 if (non_short_cint_operand (operands[2], DImode))
1442 FAIL;
1443 }
1444 else if (GET_CODE (operands[2]) == CONST_INT
1445 && ! add_operand (operands[2], <MODE>mode))
1446 {
1447 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1448 ? operands[0] : gen_reg_rtx (<MODE>mode));
1449
1450 HOST_WIDE_INT val = INTVAL (operands[2]);
1451 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1452 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1453
1454 if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L'))
1455 FAIL;
1456
1457 /* The ordering here is important for the prolog expander.
1458 When space is allocated from the stack, adding 'low' first may
1459 produce a temporary deallocation (which would be bad). */
1460 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1461 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1462 DONE;
1463 }
1464 }")
1465
1466 ;; Discourage ai/addic because of carry but provide it in an alternative
1467 ;; allowing register zero as source.
1468 (define_insn "*add<mode>3_internal1"
1469 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1470 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1471 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1472 ""
1473 "@
1474 {cax|add} %0,%1,%2
1475 {cal %0,%2(%1)|addi %0,%1,%2}
1476 {ai|addic} %0,%1,%2
1477 {cau|addis} %0,%1,%v2"
1478 [(set_attr "length" "4,4,4,4")])
1479
1480 (define_insn "addsi3_high"
1481 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1482 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1483 (high:SI (match_operand 2 "" ""))))]
1484 "TARGET_MACHO && !TARGET_64BIT"
1485 "{cau|addis} %0,%1,ha16(%2)"
1486 [(set_attr "length" "4")])
1487
1488 (define_insn "*add<mode>3_internal2"
1489 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1490 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1491 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1492 (const_int 0)))
1493 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1494 ""
1495 "@
1496 {cax.|add.} %3,%1,%2
1497 {ai.|addic.} %3,%1,%2
1498 #
1499 #"
1500 [(set_attr "type" "fast_compare,compare,compare,compare")
1501 (set_attr "length" "4,4,8,8")])
1502
1503 (define_split
1504 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1505 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1506 (match_operand:GPR 2 "reg_or_short_operand" ""))
1507 (const_int 0)))
1508 (clobber (match_scratch:GPR 3 ""))]
1509 "reload_completed"
1510 [(set (match_dup 3)
1511 (plus:GPR (match_dup 1)
1512 (match_dup 2)))
1513 (set (match_dup 0)
1514 (compare:CC (match_dup 3)
1515 (const_int 0)))]
1516 "")
1517
1518 (define_insn "*add<mode>3_internal3"
1519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1520 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1521 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1522 (const_int 0)))
1523 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1524 (plus:P (match_dup 1)
1525 (match_dup 2)))]
1526 ""
1527 "@
1528 {cax.|add.} %0,%1,%2
1529 {ai.|addic.} %0,%1,%2
1530 #
1531 #"
1532 [(set_attr "type" "fast_compare,compare,compare,compare")
1533 (set_attr "length" "4,4,8,8")])
1534
1535 (define_split
1536 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1537 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1538 (match_operand:P 2 "reg_or_short_operand" ""))
1539 (const_int 0)))
1540 (set (match_operand:P 0 "gpc_reg_operand" "")
1541 (plus:P (match_dup 1) (match_dup 2)))]
1542 "reload_completed"
1543 [(set (match_dup 0)
1544 (plus:P (match_dup 1)
1545 (match_dup 2)))
1546 (set (match_dup 3)
1547 (compare:CC (match_dup 0)
1548 (const_int 0)))]
1549 "")
1550
1551 ;; Split an add that we can't do in one insn into two insns, each of which
1552 ;; does one 16-bit part. This is used by combine. Note that the low-order
1553 ;; add should be last in case the result gets used in an address.
1554
1555 (define_split
1556 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1557 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1558 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1559 ""
1560 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1561 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1562 "
1563 {
1564 HOST_WIDE_INT val = INTVAL (operands[2]);
1565 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1566 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1567
1568 operands[4] = GEN_INT (low);
1569 if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L'))
1570 operands[3] = GEN_INT (rest);
1571 else if (! no_new_pseudos)
1572 {
1573 operands[3] = gen_reg_rtx (DImode);
1574 emit_move_insn (operands[3], operands[2]);
1575 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1576 DONE;
1577 }
1578 else
1579 FAIL;
1580 }")
1581
1582 (define_insn "one_cmpl<mode>2"
1583 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1584 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1585 ""
1586 "nor %0,%1,%1")
1587
1588 (define_insn ""
1589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1590 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1591 (const_int 0)))
1592 (clobber (match_scratch:P 2 "=r,r"))]
1593 ""
1594 "@
1595 nor. %2,%1,%1
1596 #"
1597 [(set_attr "type" "compare")
1598 (set_attr "length" "4,8")])
1599
1600 (define_split
1601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1602 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1603 (const_int 0)))
1604 (clobber (match_scratch:P 2 ""))]
1605 "reload_completed"
1606 [(set (match_dup 2)
1607 (not:P (match_dup 1)))
1608 (set (match_dup 0)
1609 (compare:CC (match_dup 2)
1610 (const_int 0)))]
1611 "")
1612
1613 (define_insn ""
1614 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1615 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1616 (const_int 0)))
1617 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1618 (not:P (match_dup 1)))]
1619 ""
1620 "@
1621 nor. %0,%1,%1
1622 #"
1623 [(set_attr "type" "compare")
1624 (set_attr "length" "4,8")])
1625
1626 (define_split
1627 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1628 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1629 (const_int 0)))
1630 (set (match_operand:P 0 "gpc_reg_operand" "")
1631 (not:P (match_dup 1)))]
1632 "reload_completed"
1633 [(set (match_dup 0)
1634 (not:P (match_dup 1)))
1635 (set (match_dup 2)
1636 (compare:CC (match_dup 0)
1637 (const_int 0)))]
1638 "")
1639
1640 (define_insn ""
1641 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1642 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1643 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1644 "! TARGET_POWERPC"
1645 "{sf%I1|subf%I1c} %0,%2,%1")
1646
1647 (define_insn ""
1648 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1649 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1650 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1651 "TARGET_POWERPC"
1652 "@
1653 subf %0,%2,%1
1654 subfic %0,%2,%1")
1655
1656 (define_insn ""
1657 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1658 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1659 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1660 (const_int 0)))
1661 (clobber (match_scratch:SI 3 "=r,r"))]
1662 "! TARGET_POWERPC"
1663 "@
1664 {sf.|subfc.} %3,%2,%1
1665 #"
1666 [(set_attr "type" "compare")
1667 (set_attr "length" "4,8")])
1668
1669 (define_insn ""
1670 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1671 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1672 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1673 (const_int 0)))
1674 (clobber (match_scratch:P 3 "=r,r"))]
1675 "TARGET_POWERPC"
1676 "@
1677 subf. %3,%2,%1
1678 #"
1679 [(set_attr "type" "fast_compare")
1680 (set_attr "length" "4,8")])
1681
1682 (define_split
1683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1684 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1685 (match_operand:P 2 "gpc_reg_operand" ""))
1686 (const_int 0)))
1687 (clobber (match_scratch:P 3 ""))]
1688 "reload_completed"
1689 [(set (match_dup 3)
1690 (minus:P (match_dup 1)
1691 (match_dup 2)))
1692 (set (match_dup 0)
1693 (compare:CC (match_dup 3)
1694 (const_int 0)))]
1695 "")
1696
1697 (define_insn ""
1698 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1699 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1700 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1701 (const_int 0)))
1702 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1703 (minus:SI (match_dup 1) (match_dup 2)))]
1704 "! TARGET_POWERPC"
1705 "@
1706 {sf.|subfc.} %0,%2,%1
1707 #"
1708 [(set_attr "type" "compare")
1709 (set_attr "length" "4,8")])
1710
1711 (define_insn ""
1712 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1713 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1714 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1715 (const_int 0)))
1716 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1717 (minus:P (match_dup 1)
1718 (match_dup 2)))]
1719 "TARGET_POWERPC"
1720 "@
1721 subf. %0,%2,%1
1722 #"
1723 [(set_attr "type" "fast_compare")
1724 (set_attr "length" "4,8")])
1725
1726 (define_split
1727 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1728 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1729 (match_operand:P 2 "gpc_reg_operand" ""))
1730 (const_int 0)))
1731 (set (match_operand:P 0 "gpc_reg_operand" "")
1732 (minus:P (match_dup 1)
1733 (match_dup 2)))]
1734 "reload_completed"
1735 [(set (match_dup 0)
1736 (minus:P (match_dup 1)
1737 (match_dup 2)))
1738 (set (match_dup 3)
1739 (compare:CC (match_dup 0)
1740 (const_int 0)))]
1741 "")
1742
1743 (define_expand "sub<mode>3"
1744 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1745 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1746 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1747 ""
1748 "
1749 {
1750 if (GET_CODE (operands[2]) == CONST_INT)
1751 {
1752 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1753 negate_rtx (<MODE>mode, operands[2])));
1754 DONE;
1755 }
1756 }")
1757
1758 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1759 ;; instruction and some auxiliary computations. Then we just have a single
1760 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1761 ;; combine.
1762
1763 (define_expand "sminsi3"
1764 [(set (match_dup 3)
1765 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1766 (match_operand:SI 2 "reg_or_short_operand" ""))
1767 (const_int 0)
1768 (minus:SI (match_dup 2) (match_dup 1))))
1769 (set (match_operand:SI 0 "gpc_reg_operand" "")
1770 (minus:SI (match_dup 2) (match_dup 3)))]
1771 "TARGET_POWER || TARGET_ISEL"
1772 "
1773 {
1774 if (TARGET_ISEL)
1775 {
1776 operands[2] = force_reg (SImode, operands[2]);
1777 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1778 DONE;
1779 }
1780
1781 operands[3] = gen_reg_rtx (SImode);
1782 }")
1783
1784 (define_split
1785 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1786 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1787 (match_operand:SI 2 "reg_or_short_operand" "")))
1788 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1789 "TARGET_POWER"
1790 [(set (match_dup 3)
1791 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1792 (const_int 0)
1793 (minus:SI (match_dup 2) (match_dup 1))))
1794 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1795 "")
1796
1797 (define_expand "smaxsi3"
1798 [(set (match_dup 3)
1799 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1800 (match_operand:SI 2 "reg_or_short_operand" ""))
1801 (const_int 0)
1802 (minus:SI (match_dup 2) (match_dup 1))))
1803 (set (match_operand:SI 0 "gpc_reg_operand" "")
1804 (plus:SI (match_dup 3) (match_dup 1)))]
1805 "TARGET_POWER || TARGET_ISEL"
1806 "
1807 {
1808 if (TARGET_ISEL)
1809 {
1810 operands[2] = force_reg (SImode, operands[2]);
1811 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1812 DONE;
1813 }
1814 operands[3] = gen_reg_rtx (SImode);
1815 }")
1816
1817 (define_split
1818 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1819 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1820 (match_operand:SI 2 "reg_or_short_operand" "")))
1821 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1822 "TARGET_POWER"
1823 [(set (match_dup 3)
1824 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1825 (const_int 0)
1826 (minus:SI (match_dup 2) (match_dup 1))))
1827 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1828 "")
1829
1830 (define_expand "uminsi3"
1831 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1832 (match_dup 5)))
1833 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1834 (match_dup 5)))
1835 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1836 (const_int 0)
1837 (minus:SI (match_dup 4) (match_dup 3))))
1838 (set (match_operand:SI 0 "gpc_reg_operand" "")
1839 (minus:SI (match_dup 2) (match_dup 3)))]
1840 "TARGET_POWER || TARGET_ISEL"
1841 "
1842 {
1843 if (TARGET_ISEL)
1844 {
1845 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1846 DONE;
1847 }
1848 operands[3] = gen_reg_rtx (SImode);
1849 operands[4] = gen_reg_rtx (SImode);
1850 operands[5] = GEN_INT (-2147483647 - 1);
1851 }")
1852
1853 (define_expand "umaxsi3"
1854 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1855 (match_dup 5)))
1856 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1857 (match_dup 5)))
1858 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1859 (const_int 0)
1860 (minus:SI (match_dup 4) (match_dup 3))))
1861 (set (match_operand:SI 0 "gpc_reg_operand" "")
1862 (plus:SI (match_dup 3) (match_dup 1)))]
1863 "TARGET_POWER || TARGET_ISEL"
1864 "
1865 {
1866 if (TARGET_ISEL)
1867 {
1868 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1869 DONE;
1870 }
1871 operands[3] = gen_reg_rtx (SImode);
1872 operands[4] = gen_reg_rtx (SImode);
1873 operands[5] = GEN_INT (-2147483647 - 1);
1874 }")
1875
1876 (define_insn ""
1877 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1878 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1879 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1880 (const_int 0)
1881 (minus:SI (match_dup 2) (match_dup 1))))]
1882 "TARGET_POWER"
1883 "doz%I2 %0,%1,%2")
1884
1885 (define_insn ""
1886 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1887 (compare:CC
1888 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1889 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1890 (const_int 0)
1891 (minus:SI (match_dup 2) (match_dup 1)))
1892 (const_int 0)))
1893 (clobber (match_scratch:SI 3 "=r,r"))]
1894 "TARGET_POWER"
1895 "@
1896 doz%I2. %3,%1,%2
1897 #"
1898 [(set_attr "type" "delayed_compare")
1899 (set_attr "length" "4,8")])
1900
1901 (define_split
1902 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1903 (compare:CC
1904 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1905 (match_operand:SI 2 "reg_or_short_operand" ""))
1906 (const_int 0)
1907 (minus:SI (match_dup 2) (match_dup 1)))
1908 (const_int 0)))
1909 (clobber (match_scratch:SI 3 ""))]
1910 "TARGET_POWER && reload_completed"
1911 [(set (match_dup 3)
1912 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1913 (const_int 0)
1914 (minus:SI (match_dup 2) (match_dup 1))))
1915 (set (match_dup 0)
1916 (compare:CC (match_dup 3)
1917 (const_int 0)))]
1918 "")
1919
1920 (define_insn ""
1921 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1922 (compare:CC
1923 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1924 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1925 (const_int 0)
1926 (minus:SI (match_dup 2) (match_dup 1)))
1927 (const_int 0)))
1928 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1929 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1930 (const_int 0)
1931 (minus:SI (match_dup 2) (match_dup 1))))]
1932 "TARGET_POWER"
1933 "@
1934 doz%I2. %0,%1,%2
1935 #"
1936 [(set_attr "type" "delayed_compare")
1937 (set_attr "length" "4,8")])
1938
1939 (define_split
1940 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1941 (compare:CC
1942 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1943 (match_operand:SI 2 "reg_or_short_operand" ""))
1944 (const_int 0)
1945 (minus:SI (match_dup 2) (match_dup 1)))
1946 (const_int 0)))
1947 (set (match_operand:SI 0 "gpc_reg_operand" "")
1948 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1949 (const_int 0)
1950 (minus:SI (match_dup 2) (match_dup 1))))]
1951 "TARGET_POWER && reload_completed"
1952 [(set (match_dup 0)
1953 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1954 (const_int 0)
1955 (minus:SI (match_dup 2) (match_dup 1))))
1956 (set (match_dup 3)
1957 (compare:CC (match_dup 0)
1958 (const_int 0)))]
1959 "")
1960
1961 ;; We don't need abs with condition code because such comparisons should
1962 ;; never be done.
1963 (define_expand "abssi2"
1964 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1965 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1966 ""
1967 "
1968 {
1969 if (TARGET_ISEL)
1970 {
1971 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1972 DONE;
1973 }
1974 else if (! TARGET_POWER)
1975 {
1976 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1977 DONE;
1978 }
1979 }")
1980
1981 (define_insn "*abssi2_power"
1982 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1983 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1984 "TARGET_POWER"
1985 "abs %0,%1")
1986
1987 (define_insn_and_split "abssi2_isel"
1988 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1989 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
1990 (clobber (match_scratch:SI 2 "=&b"))
1991 (clobber (match_scratch:CC 3 "=y"))]
1992 "TARGET_ISEL"
1993 "#"
1994 "&& reload_completed"
1995 [(set (match_dup 2) (neg:SI (match_dup 1)))
1996 (set (match_dup 3)
1997 (compare:CC (match_dup 1)
1998 (const_int 0)))
1999 (set (match_dup 0)
2000 (if_then_else:SI (ge (match_dup 3)
2001 (const_int 0))
2002 (match_dup 1)
2003 (match_dup 2)))]
2004 "")
2005
2006 (define_insn_and_split "abssi2_nopower"
2007 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2008 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2009 (clobber (match_scratch:SI 2 "=&r,&r"))]
2010 "! TARGET_POWER && ! TARGET_ISEL"
2011 "#"
2012 "&& reload_completed"
2013 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2014 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2015 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2016 "")
2017
2018 (define_insn "*nabs_power"
2019 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2020 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2021 "TARGET_POWER"
2022 "nabs %0,%1")
2023
2024 (define_insn_and_split "*nabs_nopower"
2025 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2026 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2027 (clobber (match_scratch:SI 2 "=&r,&r"))]
2028 "! TARGET_POWER"
2029 "#"
2030 "&& reload_completed"
2031 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2032 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2033 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2034 "")
2035
2036 (define_expand "neg<mode>2"
2037 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2038 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2039 ""
2040 "")
2041
2042 (define_insn "*neg<mode>2_internal"
2043 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2044 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2045 ""
2046 "neg %0,%1")
2047
2048 (define_insn ""
2049 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2050 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2051 (const_int 0)))
2052 (clobber (match_scratch:P 2 "=r,r"))]
2053 ""
2054 "@
2055 neg. %2,%1
2056 #"
2057 [(set_attr "type" "fast_compare")
2058 (set_attr "length" "4,8")])
2059
2060 (define_split
2061 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2062 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2063 (const_int 0)))
2064 (clobber (match_scratch:P 2 ""))]
2065 "reload_completed"
2066 [(set (match_dup 2)
2067 (neg:P (match_dup 1)))
2068 (set (match_dup 0)
2069 (compare:CC (match_dup 2)
2070 (const_int 0)))]
2071 "")
2072
2073 (define_insn ""
2074 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2075 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2076 (const_int 0)))
2077 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2078 (neg:P (match_dup 1)))]
2079 ""
2080 "@
2081 neg. %0,%1
2082 #"
2083 [(set_attr "type" "fast_compare")
2084 (set_attr "length" "4,8")])
2085
2086 (define_split
2087 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2088 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2089 (const_int 0)))
2090 (set (match_operand:P 0 "gpc_reg_operand" "")
2091 (neg:P (match_dup 1)))]
2092 "reload_completed"
2093 [(set (match_dup 0)
2094 (neg:P (match_dup 1)))
2095 (set (match_dup 2)
2096 (compare:CC (match_dup 0)
2097 (const_int 0)))]
2098 "")
2099
2100 (define_insn "clz<mode>2"
2101 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2102 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2103 ""
2104 "{cntlz|cntlz<wd>} %0,%1")
2105
2106 (define_expand "ctz<mode>2"
2107 [(set (match_dup 2)
2108 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2109 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2110 (match_dup 2)))
2111 (clobber (scratch:CC))])
2112 (set (match_dup 4) (clz:GPR (match_dup 3)))
2113 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2114 (minus:GPR (match_dup 5) (match_dup 4)))]
2115 ""
2116 {
2117 operands[2] = gen_reg_rtx (<MODE>mode);
2118 operands[3] = gen_reg_rtx (<MODE>mode);
2119 operands[4] = gen_reg_rtx (<MODE>mode);
2120 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2121 })
2122
2123 (define_expand "ffs<mode>2"
2124 [(set (match_dup 2)
2125 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))
2126 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2127 (match_dup 2)))
2128 (clobber (scratch:CC))])
2129 (set (match_dup 4) (clz:GPR (match_dup 3)))
2130 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2131 (minus:GPR (match_dup 5) (match_dup 4)))]
2132 ""
2133 {
2134 operands[2] = gen_reg_rtx (<MODE>mode);
2135 operands[3] = gen_reg_rtx (<MODE>mode);
2136 operands[4] = gen_reg_rtx (<MODE>mode);
2137 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2138 })
2139
2140 (define_expand "popcount<mode>2"
2141 [(set (match_dup 2)
2142 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2143 UNSPEC_POPCNTB))
2144 (set (match_dup 3)
2145 (mult:GPR (match_dup 2) (match_dup 4)))
2146 (set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2147 (lshiftrt:GPR (match_dup 3) (match_dup 5)))]
2148 "TARGET_POPCNTB"
2149 {
2150 operands[2] = gen_reg_rtx (<MODE>mode);
2151 operands[3] = gen_reg_rtx (<MODE>mode);
2152 operands[4] = force_reg (<MODE>mode,
2153 <MODE>mode == SImode
2154 ? GEN_INT (0x01010101)
2155 : GEN_INT ((HOST_WIDE_INT)
2156 0x01010101 << 32 | 0x01010101));
2157 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8);
2158 })
2159
2160 (define_insn "popcntb<mode>2"
2161 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2162 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2163 UNSPEC_POPCNTB))]
2164 "TARGET_POPCNTB"
2165 "popcntb %0,%1")
2166
2167 (define_expand "mulsi3"
2168 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2169 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2170 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2171 ""
2172 "
2173 {
2174 if (TARGET_POWER)
2175 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2176 else
2177 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2178 DONE;
2179 }")
2180
2181 (define_insn "mulsi3_mq"
2182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2183 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2184 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2185 (clobber (match_scratch:SI 3 "=q,q"))]
2186 "TARGET_POWER"
2187 "@
2188 {muls|mullw} %0,%1,%2
2189 {muli|mulli} %0,%1,%2"
2190 [(set (attr "type")
2191 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2192 (const_string "imul3")
2193 (match_operand:SI 2 "short_cint_operand" "")
2194 (const_string "imul2")]
2195 (const_string "imul")))])
2196
2197 (define_insn "mulsi3_no_mq"
2198 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2199 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2200 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2201 "! TARGET_POWER"
2202 "@
2203 {muls|mullw} %0,%1,%2
2204 {muli|mulli} %0,%1,%2"
2205 [(set (attr "type")
2206 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2207 (const_string "imul3")
2208 (match_operand:SI 2 "short_cint_operand" "")
2209 (const_string "imul2")]
2210 (const_string "imul")))])
2211
2212 (define_insn "*mulsi3_mq_internal1"
2213 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2214 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2215 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2216 (const_int 0)))
2217 (clobber (match_scratch:SI 3 "=r,r"))
2218 (clobber (match_scratch:SI 4 "=q,q"))]
2219 "TARGET_POWER"
2220 "@
2221 {muls.|mullw.} %3,%1,%2
2222 #"
2223 [(set_attr "type" "imul_compare")
2224 (set_attr "length" "4,8")])
2225
2226 (define_split
2227 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2228 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2229 (match_operand:SI 2 "gpc_reg_operand" ""))
2230 (const_int 0)))
2231 (clobber (match_scratch:SI 3 ""))
2232 (clobber (match_scratch:SI 4 ""))]
2233 "TARGET_POWER && reload_completed"
2234 [(parallel [(set (match_dup 3)
2235 (mult:SI (match_dup 1) (match_dup 2)))
2236 (clobber (match_dup 4))])
2237 (set (match_dup 0)
2238 (compare:CC (match_dup 3)
2239 (const_int 0)))]
2240 "")
2241
2242 (define_insn "*mulsi3_no_mq_internal1"
2243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2244 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2245 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2246 (const_int 0)))
2247 (clobber (match_scratch:SI 3 "=r,r"))]
2248 "! TARGET_POWER"
2249 "@
2250 {muls.|mullw.} %3,%1,%2
2251 #"
2252 [(set_attr "type" "imul_compare")
2253 (set_attr "length" "4,8")])
2254
2255 (define_split
2256 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2257 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2258 (match_operand:SI 2 "gpc_reg_operand" ""))
2259 (const_int 0)))
2260 (clobber (match_scratch:SI 3 ""))]
2261 "! TARGET_POWER && reload_completed"
2262 [(set (match_dup 3)
2263 (mult:SI (match_dup 1) (match_dup 2)))
2264 (set (match_dup 0)
2265 (compare:CC (match_dup 3)
2266 (const_int 0)))]
2267 "")
2268
2269 (define_insn "*mulsi3_mq_internal2"
2270 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2271 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2272 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2273 (const_int 0)))
2274 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2275 (mult:SI (match_dup 1) (match_dup 2)))
2276 (clobber (match_scratch:SI 4 "=q,q"))]
2277 "TARGET_POWER"
2278 "@
2279 {muls.|mullw.} %0,%1,%2
2280 #"
2281 [(set_attr "type" "imul_compare")
2282 (set_attr "length" "4,8")])
2283
2284 (define_split
2285 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2286 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2287 (match_operand:SI 2 "gpc_reg_operand" ""))
2288 (const_int 0)))
2289 (set (match_operand:SI 0 "gpc_reg_operand" "")
2290 (mult:SI (match_dup 1) (match_dup 2)))
2291 (clobber (match_scratch:SI 4 ""))]
2292 "TARGET_POWER && reload_completed"
2293 [(parallel [(set (match_dup 0)
2294 (mult:SI (match_dup 1) (match_dup 2)))
2295 (clobber (match_dup 4))])
2296 (set (match_dup 3)
2297 (compare:CC (match_dup 0)
2298 (const_int 0)))]
2299 "")
2300
2301 (define_insn "*mulsi3_no_mq_internal2"
2302 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2303 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2304 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2305 (const_int 0)))
2306 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2307 (mult:SI (match_dup 1) (match_dup 2)))]
2308 "! TARGET_POWER"
2309 "@
2310 {muls.|mullw.} %0,%1,%2
2311 #"
2312 [(set_attr "type" "imul_compare")
2313 (set_attr "length" "4,8")])
2314
2315 (define_split
2316 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2317 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2318 (match_operand:SI 2 "gpc_reg_operand" ""))
2319 (const_int 0)))
2320 (set (match_operand:SI 0 "gpc_reg_operand" "")
2321 (mult:SI (match_dup 1) (match_dup 2)))]
2322 "! TARGET_POWER && reload_completed"
2323 [(set (match_dup 0)
2324 (mult:SI (match_dup 1) (match_dup 2)))
2325 (set (match_dup 3)
2326 (compare:CC (match_dup 0)
2327 (const_int 0)))]
2328 "")
2329
2330 ;; Operand 1 is divided by operand 2; quotient goes to operand
2331 ;; 0 and remainder to operand 3.
2332 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2333
2334 (define_expand "divmodsi4"
2335 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2336 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2337 (match_operand:SI 2 "gpc_reg_operand" "")))
2338 (set (match_operand:SI 3 "register_operand" "")
2339 (mod:SI (match_dup 1) (match_dup 2)))])]
2340 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2341 "
2342 {
2343 if (! TARGET_POWER && ! TARGET_POWERPC)
2344 {
2345 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2346 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2347 emit_insn (gen_divss_call ());
2348 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2349 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2350 DONE;
2351 }
2352 }")
2353
2354 (define_insn "*divmodsi4_internal"
2355 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2356 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2357 (match_operand:SI 2 "gpc_reg_operand" "r")))
2358 (set (match_operand:SI 3 "register_operand" "=q")
2359 (mod:SI (match_dup 1) (match_dup 2)))]
2360 "TARGET_POWER"
2361 "divs %0,%1,%2"
2362 [(set_attr "type" "idiv")])
2363
2364 (define_expand "udiv<mode>3"
2365 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2366 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2367 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2368 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2369 "
2370 {
2371 if (! TARGET_POWER && ! TARGET_POWERPC)
2372 {
2373 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2374 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2375 emit_insn (gen_quous_call ());
2376 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2377 DONE;
2378 }
2379 else if (TARGET_POWER)
2380 {
2381 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2382 DONE;
2383 }
2384 }")
2385
2386 (define_insn "udivsi3_mq"
2387 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2388 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2389 (match_operand:SI 2 "gpc_reg_operand" "r")))
2390 (clobber (match_scratch:SI 3 "=q"))]
2391 "TARGET_POWERPC && TARGET_POWER"
2392 "divwu %0,%1,%2"
2393 [(set_attr "type" "idiv")])
2394
2395 (define_insn "*udivsi3_no_mq"
2396 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2397 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2398 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2399 "TARGET_POWERPC && ! TARGET_POWER"
2400 "div<wd>u %0,%1,%2"
2401 [(set_attr "type" "idiv")])
2402
2403 ;; For powers of two we can do srai/aze for divide and then adjust for
2404 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2405 ;; used; for PowerPC, force operands into register and do a normal divide;
2406 ;; for AIX common-mode, use quoss call on register operands.
2407 (define_expand "div<mode>3"
2408 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2409 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2410 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2411 ""
2412 "
2413 {
2414 if (GET_CODE (operands[2]) == CONST_INT
2415 && INTVAL (operands[2]) > 0
2416 && exact_log2 (INTVAL (operands[2])) >= 0)
2417 ;
2418 else if (TARGET_POWERPC)
2419 {
2420 operands[2] = force_reg (SImode, operands[2]);
2421 if (TARGET_POWER)
2422 {
2423 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2424 DONE;
2425 }
2426 }
2427 else if (TARGET_POWER)
2428 FAIL;
2429 else
2430 {
2431 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2432 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2433 emit_insn (gen_quoss_call ());
2434 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2435 DONE;
2436 }
2437 }")
2438
2439 (define_insn "divsi3_mq"
2440 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2441 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2442 (match_operand:SI 2 "gpc_reg_operand" "r")))
2443 (clobber (match_scratch:SI 3 "=q"))]
2444 "TARGET_POWERPC && TARGET_POWER"
2445 "divw %0,%1,%2"
2446 [(set_attr "type" "idiv")])
2447
2448 (define_insn "*div<mode>3_no_mq"
2449 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2450 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2451 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2452 "TARGET_POWERPC && ! TARGET_POWER"
2453 "div<wd> %0,%1,%2"
2454 [(set_attr "type" "idiv")])
2455
2456 (define_expand "mod<mode>3"
2457 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2458 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2459 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2460 ""
2461 "
2462 {
2463 int i;
2464 rtx temp1;
2465 rtx temp2;
2466
2467 if (GET_CODE (operands[2]) != CONST_INT
2468 || INTVAL (operands[2]) <= 0
2469 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2470 FAIL;
2471
2472 temp1 = gen_reg_rtx (<MODE>mode);
2473 temp2 = gen_reg_rtx (<MODE>mode);
2474
2475 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2476 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2477 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2478 DONE;
2479 }")
2480
2481 (define_insn ""
2482 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2483 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2484 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2485 ""
2486 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2487 [(set_attr "type" "two")
2488 (set_attr "length" "8")])
2489
2490 (define_insn ""
2491 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2492 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2493 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2494 (const_int 0)))
2495 (clobber (match_scratch:P 3 "=r,r"))]
2496 ""
2497 "@
2498 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2499 #"
2500 [(set_attr "type" "compare")
2501 (set_attr "length" "8,12")])
2502
2503 (define_split
2504 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2505 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2506 (match_operand:GPR 2 "exact_log2_cint_operand"
2507 ""))
2508 (const_int 0)))
2509 (clobber (match_scratch:GPR 3 ""))]
2510 "reload_completed"
2511 [(set (match_dup 3)
2512 (div:<MODE> (match_dup 1) (match_dup 2)))
2513 (set (match_dup 0)
2514 (compare:CC (match_dup 3)
2515 (const_int 0)))]
2516 "")
2517
2518 (define_insn ""
2519 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2520 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2521 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2522 (const_int 0)))
2523 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2524 (div:P (match_dup 1) (match_dup 2)))]
2525 ""
2526 "@
2527 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2528 #"
2529 [(set_attr "type" "compare")
2530 (set_attr "length" "8,12")])
2531
2532 (define_split
2533 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2534 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2535 (match_operand:GPR 2 "exact_log2_cint_operand"
2536 ""))
2537 (const_int 0)))
2538 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2539 (div:GPR (match_dup 1) (match_dup 2)))]
2540 "reload_completed"
2541 [(set (match_dup 0)
2542 (div:<MODE> (match_dup 1) (match_dup 2)))
2543 (set (match_dup 3)
2544 (compare:CC (match_dup 0)
2545 (const_int 0)))]
2546 "")
2547
2548 (define_insn ""
2549 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2550 (udiv:SI
2551 (plus:DI (ashift:DI
2552 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2553 (const_int 32))
2554 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2555 (match_operand:SI 3 "gpc_reg_operand" "r")))
2556 (set (match_operand:SI 2 "register_operand" "=*q")
2557 (umod:SI
2558 (plus:DI (ashift:DI
2559 (zero_extend:DI (match_dup 1)) (const_int 32))
2560 (zero_extend:DI (match_dup 4)))
2561 (match_dup 3)))]
2562 "TARGET_POWER"
2563 "div %0,%1,%3"
2564 [(set_attr "type" "idiv")])
2565
2566 ;; To do unsigned divide we handle the cases of the divisor looking like a
2567 ;; negative number. If it is a constant that is less than 2**31, we don't
2568 ;; have to worry about the branches. So make a few subroutines here.
2569 ;;
2570 ;; First comes the normal case.
2571 (define_expand "udivmodsi4_normal"
2572 [(set (match_dup 4) (const_int 0))
2573 (parallel [(set (match_operand:SI 0 "" "")
2574 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2575 (const_int 32))
2576 (zero_extend:DI (match_operand:SI 1 "" "")))
2577 (match_operand:SI 2 "" "")))
2578 (set (match_operand:SI 3 "" "")
2579 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2580 (const_int 32))
2581 (zero_extend:DI (match_dup 1)))
2582 (match_dup 2)))])]
2583 "TARGET_POWER"
2584 "
2585 { operands[4] = gen_reg_rtx (SImode); }")
2586
2587 ;; This handles the branches.
2588 (define_expand "udivmodsi4_tests"
2589 [(set (match_operand:SI 0 "" "") (const_int 0))
2590 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2591 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2592 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2593 (label_ref (match_operand:SI 4 "" "")) (pc)))
2594 (set (match_dup 0) (const_int 1))
2595 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2596 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2597 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2598 (label_ref (match_dup 4)) (pc)))]
2599 "TARGET_POWER"
2600 "
2601 { operands[5] = gen_reg_rtx (CCUNSmode);
2602 operands[6] = gen_reg_rtx (CCmode);
2603 }")
2604
2605 (define_expand "udivmodsi4"
2606 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2607 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2608 (match_operand:SI 2 "reg_or_cint_operand" "")))
2609 (set (match_operand:SI 3 "gpc_reg_operand" "")
2610 (umod:SI (match_dup 1) (match_dup 2)))])]
2611 ""
2612 "
2613 {
2614 rtx label = 0;
2615
2616 if (! TARGET_POWER)
2617 {
2618 if (! TARGET_POWERPC)
2619 {
2620 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2621 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2622 emit_insn (gen_divus_call ());
2623 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2624 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2625 DONE;
2626 }
2627 else
2628 FAIL;
2629 }
2630
2631 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2632 {
2633 operands[2] = force_reg (SImode, operands[2]);
2634 label = gen_label_rtx ();
2635 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2636 operands[3], label));
2637 }
2638 else
2639 operands[2] = force_reg (SImode, operands[2]);
2640
2641 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2642 operands[3]));
2643 if (label)
2644 emit_label (label);
2645
2646 DONE;
2647 }")
2648
2649 ;; AIX architecture-independent common-mode multiply (DImode),
2650 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2651 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2652 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2653 ;; assumed unused if generating common-mode, so ignore.
2654 (define_insn "mulh_call"
2655 [(set (reg:SI 3)
2656 (truncate:SI
2657 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2658 (sign_extend:DI (reg:SI 4)))
2659 (const_int 32))))
2660 (clobber (match_scratch:SI 0 "=l"))]
2661 "! TARGET_POWER && ! TARGET_POWERPC"
2662 "bla __mulh"
2663 [(set_attr "type" "imul")])
2664
2665 (define_insn "mull_call"
2666 [(set (reg:DI 3)
2667 (mult:DI (sign_extend:DI (reg:SI 3))
2668 (sign_extend:DI (reg:SI 4))))
2669 (clobber (match_scratch:SI 0 "=l"))
2670 (clobber (reg:SI 0))]
2671 "! TARGET_POWER && ! TARGET_POWERPC"
2672 "bla __mull"
2673 [(set_attr "type" "imul")])
2674
2675 (define_insn "divss_call"
2676 [(set (reg:SI 3)
2677 (div:SI (reg:SI 3) (reg:SI 4)))
2678 (set (reg:SI 4)
2679 (mod:SI (reg:SI 3) (reg:SI 4)))
2680 (clobber (match_scratch:SI 0 "=l"))
2681 (clobber (reg:SI 0))]
2682 "! TARGET_POWER && ! TARGET_POWERPC"
2683 "bla __divss"
2684 [(set_attr "type" "idiv")])
2685
2686 (define_insn "divus_call"
2687 [(set (reg:SI 3)
2688 (udiv:SI (reg:SI 3) (reg:SI 4)))
2689 (set (reg:SI 4)
2690 (umod:SI (reg:SI 3) (reg:SI 4)))
2691 (clobber (match_scratch:SI 0 "=l"))
2692 (clobber (reg:SI 0))
2693 (clobber (match_scratch:CC 1 "=x"))
2694 (clobber (reg:CC 69))]
2695 "! TARGET_POWER && ! TARGET_POWERPC"
2696 "bla __divus"
2697 [(set_attr "type" "idiv")])
2698
2699 (define_insn "quoss_call"
2700 [(set (reg:SI 3)
2701 (div:SI (reg:SI 3) (reg:SI 4)))
2702 (clobber (match_scratch:SI 0 "=l"))]
2703 "! TARGET_POWER && ! TARGET_POWERPC"
2704 "bla __quoss"
2705 [(set_attr "type" "idiv")])
2706
2707 (define_insn "quous_call"
2708 [(set (reg:SI 3)
2709 (udiv:SI (reg:SI 3) (reg:SI 4)))
2710 (clobber (match_scratch:SI 0 "=l"))
2711 (clobber (reg:SI 0))
2712 (clobber (match_scratch:CC 1 "=x"))
2713 (clobber (reg:CC 69))]
2714 "! TARGET_POWER && ! TARGET_POWERPC"
2715 "bla __quous"
2716 [(set_attr "type" "idiv")])
2717 \f
2718 ;; Logical instructions
2719 ;; The logical instructions are mostly combined by using match_operator,
2720 ;; but the plain AND insns are somewhat different because there is no
2721 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2722 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2723
2724 (define_insn "andsi3"
2725 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2726 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2727 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2728 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2729 ""
2730 "@
2731 and %0,%1,%2
2732 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2733 {andil.|andi.} %0,%1,%b2
2734 {andiu.|andis.} %0,%1,%u2"
2735 [(set_attr "type" "*,*,compare,compare")])
2736
2737 ;; Note to set cr's other than cr0 we do the and immediate and then
2738 ;; the test again -- this avoids a mfcr which on the higher end
2739 ;; machines causes an execution serialization
2740
2741 (define_insn "*andsi3_internal2"
2742 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2743 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2744 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2745 (const_int 0)))
2746 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2747 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2748 "TARGET_32BIT"
2749 "@
2750 and. %3,%1,%2
2751 {andil.|andi.} %3,%1,%b2
2752 {andiu.|andis.} %3,%1,%u2
2753 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2754 #
2755 #
2756 #
2757 #"
2758 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2759 (set_attr "length" "4,4,4,4,8,8,8,8")])
2760
2761 (define_insn "*andsi3_internal3"
2762 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2763 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2764 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2765 (const_int 0)))
2766 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2767 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2768 "TARGET_64BIT"
2769 "@
2770 #
2771 {andil.|andi.} %3,%1,%b2
2772 {andiu.|andis.} %3,%1,%u2
2773 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2774 #
2775 #
2776 #
2777 #"
2778 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2779 (set_attr "length" "8,4,4,4,8,8,8,8")])
2780
2781 (define_split
2782 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2783 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2784 (match_operand:GPR 2 "and_operand" ""))
2785 (const_int 0)))
2786 (clobber (match_scratch:GPR 3 ""))
2787 (clobber (match_scratch:CC 4 ""))]
2788 "reload_completed"
2789 [(parallel [(set (match_dup 3)
2790 (and:<MODE> (match_dup 1)
2791 (match_dup 2)))
2792 (clobber (match_dup 4))])
2793 (set (match_dup 0)
2794 (compare:CC (match_dup 3)
2795 (const_int 0)))]
2796 "")
2797
2798 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
2799 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
2800
2801 (define_split
2802 [(set (match_operand:CC 0 "cc_reg_operand" "")
2803 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2804 (match_operand:SI 2 "gpc_reg_operand" ""))
2805 (const_int 0)))
2806 (clobber (match_scratch:SI 3 ""))
2807 (clobber (match_scratch:CC 4 ""))]
2808 "TARGET_POWERPC64 && reload_completed"
2809 [(parallel [(set (match_dup 3)
2810 (and:SI (match_dup 1)
2811 (match_dup 2)))
2812 (clobber (match_dup 4))])
2813 (set (match_dup 0)
2814 (compare:CC (match_dup 3)
2815 (const_int 0)))]
2816 "")
2817
2818 (define_insn "*andsi3_internal4"
2819 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2820 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2821 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2822 (const_int 0)))
2823 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2824 (and:SI (match_dup 1)
2825 (match_dup 2)))
2826 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2827 "TARGET_32BIT"
2828 "@
2829 and. %0,%1,%2
2830 {andil.|andi.} %0,%1,%b2
2831 {andiu.|andis.} %0,%1,%u2
2832 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2833 #
2834 #
2835 #
2836 #"
2837 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2838 (set_attr "length" "4,4,4,4,8,8,8,8")])
2839
2840 (define_insn "*andsi3_internal5"
2841 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2842 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2843 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2844 (const_int 0)))
2845 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2846 (and:SI (match_dup 1)
2847 (match_dup 2)))
2848 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2849 "TARGET_64BIT"
2850 "@
2851 #
2852 {andil.|andi.} %0,%1,%b2
2853 {andiu.|andis.} %0,%1,%u2
2854 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2855 #
2856 #
2857 #
2858 #"
2859 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2860 (set_attr "length" "8,4,4,4,8,8,8,8")])
2861
2862 (define_split
2863 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2864 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2865 (match_operand:SI 2 "and_operand" ""))
2866 (const_int 0)))
2867 (set (match_operand:SI 0 "gpc_reg_operand" "")
2868 (and:SI (match_dup 1)
2869 (match_dup 2)))
2870 (clobber (match_scratch:CC 4 ""))]
2871 "reload_completed"
2872 [(parallel [(set (match_dup 0)
2873 (and:SI (match_dup 1)
2874 (match_dup 2)))
2875 (clobber (match_dup 4))])
2876 (set (match_dup 3)
2877 (compare:CC (match_dup 0)
2878 (const_int 0)))]
2879 "")
2880
2881 (define_split
2882 [(set (match_operand:CC 3 "cc_reg_operand" "")
2883 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2884 (match_operand:SI 2 "gpc_reg_operand" ""))
2885 (const_int 0)))
2886 (set (match_operand:SI 0 "gpc_reg_operand" "")
2887 (and:SI (match_dup 1)
2888 (match_dup 2)))
2889 (clobber (match_scratch:CC 4 ""))]
2890 "TARGET_POWERPC64 && reload_completed"
2891 [(parallel [(set (match_dup 0)
2892 (and:SI (match_dup 1)
2893 (match_dup 2)))
2894 (clobber (match_dup 4))])
2895 (set (match_dup 3)
2896 (compare:CC (match_dup 0)
2897 (const_int 0)))]
2898 "")
2899
2900 ;; Handle the PowerPC64 rlwinm corner case
2901
2902 (define_insn_and_split "*andsi3_internal6"
2903 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2904 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2905 (match_operand:SI 2 "mask_operand_wrap" "i")))]
2906 "TARGET_POWERPC64"
2907 "#"
2908 "TARGET_POWERPC64"
2909 [(set (match_dup 0)
2910 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
2911 (match_dup 4)))
2912 (set (match_dup 0)
2913 (rotate:SI (match_dup 0) (match_dup 5)))]
2914 "
2915 {
2916 int mb = extract_MB (operands[2]);
2917 int me = extract_ME (operands[2]);
2918 operands[3] = GEN_INT (me + 1);
2919 operands[5] = GEN_INT (32 - (me + 1));
2920 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
2921 }"
2922 [(set_attr "length" "8")])
2923
2924 (define_expand "iorsi3"
2925 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2926 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2927 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2928 ""
2929 "
2930 {
2931 if (GET_CODE (operands[2]) == CONST_INT
2932 && ! logical_operand (operands[2], SImode))
2933 {
2934 HOST_WIDE_INT value = INTVAL (operands[2]);
2935 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2936 ? operands[0] : gen_reg_rtx (SImode));
2937
2938 emit_insn (gen_iorsi3 (tmp, operands[1],
2939 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2940 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2941 DONE;
2942 }
2943 }")
2944
2945 (define_expand "xorsi3"
2946 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2947 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2948 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2949 ""
2950 "
2951 {
2952 if (GET_CODE (operands[2]) == CONST_INT
2953 && ! logical_operand (operands[2], SImode))
2954 {
2955 HOST_WIDE_INT value = INTVAL (operands[2]);
2956 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2957 ? operands[0] : gen_reg_rtx (SImode));
2958
2959 emit_insn (gen_xorsi3 (tmp, operands[1],
2960 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2961 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2962 DONE;
2963 }
2964 }")
2965
2966 (define_insn "*boolsi3_internal1"
2967 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2968 (match_operator:SI 3 "boolean_or_operator"
2969 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2970 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2971 ""
2972 "@
2973 %q3 %0,%1,%2
2974 {%q3il|%q3i} %0,%1,%b2
2975 {%q3iu|%q3is} %0,%1,%u2")
2976
2977 (define_insn "*boolsi3_internal2"
2978 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2979 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2980 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2981 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2982 (const_int 0)))
2983 (clobber (match_scratch:SI 3 "=r,r"))]
2984 "TARGET_32BIT"
2985 "@
2986 %q4. %3,%1,%2
2987 #"
2988 [(set_attr "type" "compare")
2989 (set_attr "length" "4,8")])
2990
2991 (define_split
2992 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2993 (compare:CC (match_operator:SI 4 "boolean_operator"
2994 [(match_operand:SI 1 "gpc_reg_operand" "")
2995 (match_operand:SI 2 "gpc_reg_operand" "")])
2996 (const_int 0)))
2997 (clobber (match_scratch:SI 3 ""))]
2998 "TARGET_32BIT && reload_completed"
2999 [(set (match_dup 3) (match_dup 4))
3000 (set (match_dup 0)
3001 (compare:CC (match_dup 3)
3002 (const_int 0)))]
3003 "")
3004
3005 (define_insn "*boolsi3_internal3"
3006 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3007 (compare:CC (match_operator:SI 4 "boolean_operator"
3008 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3009 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3010 (const_int 0)))
3011 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3012 (match_dup 4))]
3013 "TARGET_32BIT"
3014 "@
3015 %q4. %0,%1,%2
3016 #"
3017 [(set_attr "type" "compare")
3018 (set_attr "length" "4,8")])
3019
3020 (define_split
3021 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3022 (compare:CC (match_operator:SI 4 "boolean_operator"
3023 [(match_operand:SI 1 "gpc_reg_operand" "")
3024 (match_operand:SI 2 "gpc_reg_operand" "")])
3025 (const_int 0)))
3026 (set (match_operand:SI 0 "gpc_reg_operand" "")
3027 (match_dup 4))]
3028 "TARGET_32BIT && reload_completed"
3029 [(set (match_dup 0) (match_dup 4))
3030 (set (match_dup 3)
3031 (compare:CC (match_dup 0)
3032 (const_int 0)))]
3033 "")
3034
3035 ;; Split a logical operation that we can't do in one insn into two insns,
3036 ;; each of which does one 16-bit part. This is used by combine.
3037
3038 (define_split
3039 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3040 (match_operator:SI 3 "boolean_or_operator"
3041 [(match_operand:SI 1 "gpc_reg_operand" "")
3042 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3043 ""
3044 [(set (match_dup 0) (match_dup 4))
3045 (set (match_dup 0) (match_dup 5))]
3046 "
3047 {
3048 rtx i;
3049 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3050 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3051 operands[1], i);
3052 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3053 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3054 operands[0], i);
3055 }")
3056
3057 (define_insn "*boolcsi3_internal1"
3058 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3059 (match_operator:SI 3 "boolean_operator"
3060 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3061 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3062 ""
3063 "%q3 %0,%2,%1")
3064
3065 (define_insn "*boolcsi3_internal2"
3066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3067 (compare:CC (match_operator:SI 4 "boolean_operator"
3068 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3069 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3070 (const_int 0)))
3071 (clobber (match_scratch:SI 3 "=r,r"))]
3072 "TARGET_32BIT"
3073 "@
3074 %q4. %3,%2,%1
3075 #"
3076 [(set_attr "type" "compare")
3077 (set_attr "length" "4,8")])
3078
3079 (define_split
3080 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3081 (compare:CC (match_operator:SI 4 "boolean_operator"
3082 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3083 (match_operand:SI 2 "gpc_reg_operand" "")])
3084 (const_int 0)))
3085 (clobber (match_scratch:SI 3 ""))]
3086 "TARGET_32BIT && reload_completed"
3087 [(set (match_dup 3) (match_dup 4))
3088 (set (match_dup 0)
3089 (compare:CC (match_dup 3)
3090 (const_int 0)))]
3091 "")
3092
3093 (define_insn "*boolcsi3_internal3"
3094 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3095 (compare:CC (match_operator:SI 4 "boolean_operator"
3096 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3097 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3098 (const_int 0)))
3099 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3100 (match_dup 4))]
3101 "TARGET_32BIT"
3102 "@
3103 %q4. %0,%2,%1
3104 #"
3105 [(set_attr "type" "compare")
3106 (set_attr "length" "4,8")])
3107
3108 (define_split
3109 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3110 (compare:CC (match_operator:SI 4 "boolean_operator"
3111 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3112 (match_operand:SI 2 "gpc_reg_operand" "")])
3113 (const_int 0)))
3114 (set (match_operand:SI 0 "gpc_reg_operand" "")
3115 (match_dup 4))]
3116 "TARGET_32BIT && reload_completed"
3117 [(set (match_dup 0) (match_dup 4))
3118 (set (match_dup 3)
3119 (compare:CC (match_dup 0)
3120 (const_int 0)))]
3121 "")
3122
3123 (define_insn "*boolccsi3_internal1"
3124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3125 (match_operator:SI 3 "boolean_operator"
3126 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3127 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3128 ""
3129 "%q3 %0,%1,%2")
3130
3131 (define_insn "*boolccsi3_internal2"
3132 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3133 (compare:CC (match_operator:SI 4 "boolean_operator"
3134 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3135 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3136 (const_int 0)))
3137 (clobber (match_scratch:SI 3 "=r,r"))]
3138 "TARGET_32BIT"
3139 "@
3140 %q4. %3,%1,%2
3141 #"
3142 [(set_attr "type" "compare")
3143 (set_attr "length" "4,8")])
3144
3145 (define_split
3146 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3147 (compare:CC (match_operator:SI 4 "boolean_operator"
3148 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3149 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3150 (const_int 0)))
3151 (clobber (match_scratch:SI 3 ""))]
3152 "TARGET_32BIT && reload_completed"
3153 [(set (match_dup 3) (match_dup 4))
3154 (set (match_dup 0)
3155 (compare:CC (match_dup 3)
3156 (const_int 0)))]
3157 "")
3158
3159 (define_insn "*boolccsi3_internal3"
3160 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3161 (compare:CC (match_operator:SI 4 "boolean_operator"
3162 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3163 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3164 (const_int 0)))
3165 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3166 (match_dup 4))]
3167 "TARGET_32BIT"
3168 "@
3169 %q4. %0,%1,%2
3170 #"
3171 [(set_attr "type" "compare")
3172 (set_attr "length" "4,8")])
3173
3174 (define_split
3175 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3176 (compare:CC (match_operator:SI 4 "boolean_operator"
3177 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3178 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3179 (const_int 0)))
3180 (set (match_operand:SI 0 "gpc_reg_operand" "")
3181 (match_dup 4))]
3182 "TARGET_32BIT && reload_completed"
3183 [(set (match_dup 0) (match_dup 4))
3184 (set (match_dup 3)
3185 (compare:CC (match_dup 0)
3186 (const_int 0)))]
3187 "")
3188
3189 ;; maskir insn. We need four forms because things might be in arbitrary
3190 ;; orders. Don't define forms that only set CR fields because these
3191 ;; would modify an input register.
3192
3193 (define_insn "*maskir_internal1"
3194 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3195 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3196 (match_operand:SI 1 "gpc_reg_operand" "0"))
3197 (and:SI (match_dup 2)
3198 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3199 "TARGET_POWER"
3200 "maskir %0,%3,%2")
3201
3202 (define_insn "*maskir_internal2"
3203 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3204 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3205 (match_operand:SI 1 "gpc_reg_operand" "0"))
3206 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3207 (match_dup 2))))]
3208 "TARGET_POWER"
3209 "maskir %0,%3,%2")
3210
3211 (define_insn "*maskir_internal3"
3212 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3213 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3214 (match_operand:SI 3 "gpc_reg_operand" "r"))
3215 (and:SI (not:SI (match_dup 2))
3216 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3217 "TARGET_POWER"
3218 "maskir %0,%3,%2")
3219
3220 (define_insn "*maskir_internal4"
3221 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3222 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3223 (match_operand:SI 2 "gpc_reg_operand" "r"))
3224 (and:SI (not:SI (match_dup 2))
3225 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3226 "TARGET_POWER"
3227 "maskir %0,%3,%2")
3228
3229 (define_insn "*maskir_internal5"
3230 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3231 (compare:CC
3232 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3233 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3234 (and:SI (match_dup 2)
3235 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3236 (const_int 0)))
3237 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3238 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3239 (and:SI (match_dup 2) (match_dup 3))))]
3240 "TARGET_POWER"
3241 "@
3242 maskir. %0,%3,%2
3243 #"
3244 [(set_attr "type" "compare")
3245 (set_attr "length" "4,8")])
3246
3247 (define_split
3248 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3249 (compare:CC
3250 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3251 (match_operand:SI 1 "gpc_reg_operand" ""))
3252 (and:SI (match_dup 2)
3253 (match_operand:SI 3 "gpc_reg_operand" "")))
3254 (const_int 0)))
3255 (set (match_operand:SI 0 "gpc_reg_operand" "")
3256 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3257 (and:SI (match_dup 2) (match_dup 3))))]
3258 "TARGET_POWER && reload_completed"
3259 [(set (match_dup 0)
3260 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3261 (and:SI (match_dup 2) (match_dup 3))))
3262 (set (match_dup 4)
3263 (compare:CC (match_dup 0)
3264 (const_int 0)))]
3265 "")
3266
3267 (define_insn "*maskir_internal6"
3268 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3269 (compare:CC
3270 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3271 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3272 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3273 (match_dup 2)))
3274 (const_int 0)))
3275 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3276 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3277 (and:SI (match_dup 3) (match_dup 2))))]
3278 "TARGET_POWER"
3279 "@
3280 maskir. %0,%3,%2
3281 #"
3282 [(set_attr "type" "compare")
3283 (set_attr "length" "4,8")])
3284
3285 (define_split
3286 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3287 (compare:CC
3288 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3289 (match_operand:SI 1 "gpc_reg_operand" ""))
3290 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3291 (match_dup 2)))
3292 (const_int 0)))
3293 (set (match_operand:SI 0 "gpc_reg_operand" "")
3294 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3295 (and:SI (match_dup 3) (match_dup 2))))]
3296 "TARGET_POWER && reload_completed"
3297 [(set (match_dup 0)
3298 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3299 (and:SI (match_dup 3) (match_dup 2))))
3300 (set (match_dup 4)
3301 (compare:CC (match_dup 0)
3302 (const_int 0)))]
3303 "")
3304
3305 (define_insn "*maskir_internal7"
3306 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3307 (compare:CC
3308 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3309 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3310 (and:SI (not:SI (match_dup 2))
3311 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3312 (const_int 0)))
3313 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3314 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3315 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3316 "TARGET_POWER"
3317 "@
3318 maskir. %0,%3,%2
3319 #"
3320 [(set_attr "type" "compare")
3321 (set_attr "length" "4,8")])
3322
3323 (define_split
3324 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3325 (compare:CC
3326 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3327 (match_operand:SI 3 "gpc_reg_operand" ""))
3328 (and:SI (not:SI (match_dup 2))
3329 (match_operand:SI 1 "gpc_reg_operand" "")))
3330 (const_int 0)))
3331 (set (match_operand:SI 0 "gpc_reg_operand" "")
3332 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3333 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3334 "TARGET_POWER && reload_completed"
3335 [(set (match_dup 0)
3336 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3337 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3338 (set (match_dup 4)
3339 (compare:CC (match_dup 0)
3340 (const_int 0)))]
3341 "")
3342
3343 (define_insn "*maskir_internal8"
3344 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3345 (compare:CC
3346 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3347 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3348 (and:SI (not:SI (match_dup 2))
3349 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3350 (const_int 0)))
3351 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3352 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3353 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3354 "TARGET_POWER"
3355 "@
3356 maskir. %0,%3,%2
3357 #"
3358 [(set_attr "type" "compare")
3359 (set_attr "length" "4,8")])
3360
3361 (define_split
3362 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3363 (compare:CC
3364 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3365 (match_operand:SI 2 "gpc_reg_operand" ""))
3366 (and:SI (not:SI (match_dup 2))
3367 (match_operand:SI 1 "gpc_reg_operand" "")))
3368 (const_int 0)))
3369 (set (match_operand:SI 0 "gpc_reg_operand" "")
3370 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3371 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3372 "TARGET_POWER && reload_completed"
3373 [(set (match_dup 0)
3374 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3375 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3376 (set (match_dup 4)
3377 (compare:CC (match_dup 0)
3378 (const_int 0)))]
3379 "")
3380 \f
3381 ;; Rotate and shift insns, in all their variants. These support shifts,
3382 ;; field inserts and extracts, and various combinations thereof.
3383 (define_expand "insv"
3384 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3385 (match_operand:SI 1 "const_int_operand" "")
3386 (match_operand:SI 2 "const_int_operand" ""))
3387 (match_operand 3 "gpc_reg_operand" ""))]
3388 ""
3389 "
3390 {
3391 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3392 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3393 compiler if the address of the structure is taken later. */
3394 if (GET_CODE (operands[0]) == SUBREG
3395 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3396 FAIL;
3397
3398 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3399 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3400 else
3401 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3402 DONE;
3403 }")
3404
3405 (define_insn "insvsi"
3406 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3407 (match_operand:SI 1 "const_int_operand" "i")
3408 (match_operand:SI 2 "const_int_operand" "i"))
3409 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3410 ""
3411 "*
3412 {
3413 int start = INTVAL (operands[2]) & 31;
3414 int size = INTVAL (operands[1]) & 31;
3415
3416 operands[4] = GEN_INT (32 - start - size);
3417 operands[1] = GEN_INT (start + size - 1);
3418 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3419 }"
3420 [(set_attr "type" "insert_word")])
3421
3422 (define_insn "*insvsi_internal1"
3423 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3424 (match_operand:SI 1 "const_int_operand" "i")
3425 (match_operand:SI 2 "const_int_operand" "i"))
3426 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3427 (match_operand:SI 4 "const_int_operand" "i")))]
3428 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3429 "*
3430 {
3431 int shift = INTVAL (operands[4]) & 31;
3432 int start = INTVAL (operands[2]) & 31;
3433 int size = INTVAL (operands[1]) & 31;
3434
3435 operands[4] = GEN_INT (shift - start - size);
3436 operands[1] = GEN_INT (start + size - 1);
3437 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3438 }"
3439 [(set_attr "type" "insert_word")])
3440
3441 (define_insn "*insvsi_internal2"
3442 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3443 (match_operand:SI 1 "const_int_operand" "i")
3444 (match_operand:SI 2 "const_int_operand" "i"))
3445 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3446 (match_operand:SI 4 "const_int_operand" "i")))]
3447 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3448 "*
3449 {
3450 int shift = INTVAL (operands[4]) & 31;
3451 int start = INTVAL (operands[2]) & 31;
3452 int size = INTVAL (operands[1]) & 31;
3453
3454 operands[4] = GEN_INT (32 - shift - start - size);
3455 operands[1] = GEN_INT (start + size - 1);
3456 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3457 }"
3458 [(set_attr "type" "insert_word")])
3459
3460 (define_insn "*insvsi_internal3"
3461 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3462 (match_operand:SI 1 "const_int_operand" "i")
3463 (match_operand:SI 2 "const_int_operand" "i"))
3464 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3465 (match_operand:SI 4 "const_int_operand" "i")))]
3466 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3467 "*
3468 {
3469 int shift = INTVAL (operands[4]) & 31;
3470 int start = INTVAL (operands[2]) & 31;
3471 int size = INTVAL (operands[1]) & 31;
3472
3473 operands[4] = GEN_INT (32 - shift - start - size);
3474 operands[1] = GEN_INT (start + size - 1);
3475 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3476 }"
3477 [(set_attr "type" "insert_word")])
3478
3479 (define_insn "*insvsi_internal4"
3480 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3481 (match_operand:SI 1 "const_int_operand" "i")
3482 (match_operand:SI 2 "const_int_operand" "i"))
3483 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3484 (match_operand:SI 4 "const_int_operand" "i")
3485 (match_operand:SI 5 "const_int_operand" "i")))]
3486 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3487 "*
3488 {
3489 int extract_start = INTVAL (operands[5]) & 31;
3490 int extract_size = INTVAL (operands[4]) & 31;
3491 int insert_start = INTVAL (operands[2]) & 31;
3492 int insert_size = INTVAL (operands[1]) & 31;
3493
3494 /* Align extract field with insert field */
3495 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3496 operands[1] = GEN_INT (insert_start + insert_size - 1);
3497 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3498 }"
3499 [(set_attr "type" "insert_word")])
3500
3501 ;; combine patterns for rlwimi
3502 (define_insn "*insvsi_internal5"
3503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3504 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3505 (match_operand:SI 1 "mask_operand" "i"))
3506 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3507 (match_operand:SI 2 "const_int_operand" "i"))
3508 (match_operand:SI 5 "mask_operand" "i"))))]
3509 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3510 "*
3511 {
3512 int me = extract_ME(operands[5]);
3513 int mb = extract_MB(operands[5]);
3514 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3515 operands[2] = GEN_INT(mb);
3516 operands[1] = GEN_INT(me);
3517 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3518 }"
3519 [(set_attr "type" "insert_word")])
3520
3521 (define_insn "*insvsi_internal6"
3522 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3523 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3524 (match_operand:SI 2 "const_int_operand" "i"))
3525 (match_operand:SI 5 "mask_operand" "i"))
3526 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3527 (match_operand:SI 1 "mask_operand" "i"))))]
3528 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3529 "*
3530 {
3531 int me = extract_ME(operands[5]);
3532 int mb = extract_MB(operands[5]);
3533 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3534 operands[2] = GEN_INT(mb);
3535 operands[1] = GEN_INT(me);
3536 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3537 }"
3538 [(set_attr "type" "insert_word")])
3539
3540 (define_insn "insvdi"
3541 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3542 (match_operand:SI 1 "const_int_operand" "i")
3543 (match_operand:SI 2 "const_int_operand" "i"))
3544 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3545 "TARGET_POWERPC64"
3546 "*
3547 {
3548 int start = INTVAL (operands[2]) & 63;
3549 int size = INTVAL (operands[1]) & 63;
3550
3551 operands[1] = GEN_INT (64 - start - size);
3552 return \"rldimi %0,%3,%H1,%H2\";
3553 }")
3554
3555 (define_insn "*insvdi_internal2"
3556 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3557 (match_operand:SI 1 "const_int_operand" "i")
3558 (match_operand:SI 2 "const_int_operand" "i"))
3559 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3560 (match_operand:SI 4 "const_int_operand" "i")))]
3561 "TARGET_POWERPC64
3562 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3563 "*
3564 {
3565 int shift = INTVAL (operands[4]) & 63;
3566 int start = (INTVAL (operands[2]) & 63) - 32;
3567 int size = INTVAL (operands[1]) & 63;
3568
3569 operands[4] = GEN_INT (64 - shift - start - size);
3570 operands[2] = GEN_INT (start);
3571 operands[1] = GEN_INT (start + size - 1);
3572 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3573 }")
3574
3575 (define_insn "*insvdi_internal3"
3576 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3577 (match_operand:SI 1 "const_int_operand" "i")
3578 (match_operand:SI 2 "const_int_operand" "i"))
3579 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3580 (match_operand:SI 4 "const_int_operand" "i")))]
3581 "TARGET_POWERPC64
3582 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3583 "*
3584 {
3585 int shift = INTVAL (operands[4]) & 63;
3586 int start = (INTVAL (operands[2]) & 63) - 32;
3587 int size = INTVAL (operands[1]) & 63;
3588
3589 operands[4] = GEN_INT (64 - shift - start - size);
3590 operands[2] = GEN_INT (start);
3591 operands[1] = GEN_INT (start + size - 1);
3592 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3593 }")
3594
3595 (define_expand "extzv"
3596 [(set (match_operand 0 "gpc_reg_operand" "")
3597 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3598 (match_operand:SI 2 "const_int_operand" "")
3599 (match_operand:SI 3 "const_int_operand" "")))]
3600 ""
3601 "
3602 {
3603 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3604 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3605 compiler if the address of the structure is taken later. */
3606 if (GET_CODE (operands[0]) == SUBREG
3607 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3608 FAIL;
3609
3610 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3611 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3612 else
3613 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3614 DONE;
3615 }")
3616
3617 (define_insn "extzvsi"
3618 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3619 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3620 (match_operand:SI 2 "const_int_operand" "i")
3621 (match_operand:SI 3 "const_int_operand" "i")))]
3622 ""
3623 "*
3624 {
3625 int start = INTVAL (operands[3]) & 31;
3626 int size = INTVAL (operands[2]) & 31;
3627
3628 if (start + size >= 32)
3629 operands[3] = const0_rtx;
3630 else
3631 operands[3] = GEN_INT (start + size);
3632 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3633 }")
3634
3635 (define_insn "*extzvsi_internal1"
3636 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3637 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3638 (match_operand:SI 2 "const_int_operand" "i,i")
3639 (match_operand:SI 3 "const_int_operand" "i,i"))
3640 (const_int 0)))
3641 (clobber (match_scratch:SI 4 "=r,r"))]
3642 ""
3643 "*
3644 {
3645 int start = INTVAL (operands[3]) & 31;
3646 int size = INTVAL (operands[2]) & 31;
3647
3648 /* Force split for non-cc0 compare. */
3649 if (which_alternative == 1)
3650 return \"#\";
3651
3652 /* If the bit-field being tested fits in the upper or lower half of a
3653 word, it is possible to use andiu. or andil. to test it. This is
3654 useful because the condition register set-use delay is smaller for
3655 andi[ul]. than for rlinm. This doesn't work when the starting bit
3656 position is 0 because the LT and GT bits may be set wrong. */
3657
3658 if ((start > 0 && start + size <= 16) || start >= 16)
3659 {
3660 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3661 - (1 << (16 - (start & 15) - size))));
3662 if (start < 16)
3663 return \"{andiu.|andis.} %4,%1,%3\";
3664 else
3665 return \"{andil.|andi.} %4,%1,%3\";
3666 }
3667
3668 if (start + size >= 32)
3669 operands[3] = const0_rtx;
3670 else
3671 operands[3] = GEN_INT (start + size);
3672 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3673 }"
3674 [(set_attr "type" "compare")
3675 (set_attr "length" "4,8")])
3676
3677 (define_split
3678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3679 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3680 (match_operand:SI 2 "const_int_operand" "")
3681 (match_operand:SI 3 "const_int_operand" ""))
3682 (const_int 0)))
3683 (clobber (match_scratch:SI 4 ""))]
3684 "reload_completed"
3685 [(set (match_dup 4)
3686 (zero_extract:SI (match_dup 1) (match_dup 2)
3687 (match_dup 3)))
3688 (set (match_dup 0)
3689 (compare:CC (match_dup 4)
3690 (const_int 0)))]
3691 "")
3692
3693 (define_insn "*extzvsi_internal2"
3694 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3695 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3696 (match_operand:SI 2 "const_int_operand" "i,i")
3697 (match_operand:SI 3 "const_int_operand" "i,i"))
3698 (const_int 0)))
3699 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3700 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3701 ""
3702 "*
3703 {
3704 int start = INTVAL (operands[3]) & 31;
3705 int size = INTVAL (operands[2]) & 31;
3706
3707 /* Force split for non-cc0 compare. */
3708 if (which_alternative == 1)
3709 return \"#\";
3710
3711 /* Since we are using the output value, we can't ignore any need for
3712 a shift. The bit-field must end at the LSB. */
3713 if (start >= 16 && start + size == 32)
3714 {
3715 operands[3] = GEN_INT ((1 << size) - 1);
3716 return \"{andil.|andi.} %0,%1,%3\";
3717 }
3718
3719 if (start + size >= 32)
3720 operands[3] = const0_rtx;
3721 else
3722 operands[3] = GEN_INT (start + size);
3723 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3724 }"
3725 [(set_attr "type" "compare")
3726 (set_attr "length" "4,8")])
3727
3728 (define_split
3729 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3730 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3731 (match_operand:SI 2 "const_int_operand" "")
3732 (match_operand:SI 3 "const_int_operand" ""))
3733 (const_int 0)))
3734 (set (match_operand:SI 0 "gpc_reg_operand" "")
3735 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3736 "reload_completed"
3737 [(set (match_dup 0)
3738 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3739 (set (match_dup 4)
3740 (compare:CC (match_dup 0)
3741 (const_int 0)))]
3742 "")
3743
3744 (define_insn "extzvdi"
3745 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3746 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3747 (match_operand:SI 2 "const_int_operand" "i")
3748 (match_operand:SI 3 "const_int_operand" "i")))]
3749 "TARGET_POWERPC64"
3750 "*
3751 {
3752 int start = INTVAL (operands[3]) & 63;
3753 int size = INTVAL (operands[2]) & 63;
3754
3755 if (start + size >= 64)
3756 operands[3] = const0_rtx;
3757 else
3758 operands[3] = GEN_INT (start + size);
3759 operands[2] = GEN_INT (64 - size);
3760 return \"rldicl %0,%1,%3,%2\";
3761 }")
3762
3763 (define_insn "*extzvdi_internal1"
3764 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3765 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3766 (match_operand:SI 2 "const_int_operand" "i")
3767 (match_operand:SI 3 "const_int_operand" "i"))
3768 (const_int 0)))
3769 (clobber (match_scratch:DI 4 "=r"))]
3770 "TARGET_64BIT"
3771 "*
3772 {
3773 int start = INTVAL (operands[3]) & 63;
3774 int size = INTVAL (operands[2]) & 63;
3775
3776 if (start + size >= 64)
3777 operands[3] = const0_rtx;
3778 else
3779 operands[3] = GEN_INT (start + size);
3780 operands[2] = GEN_INT (64 - size);
3781 return \"rldicl. %4,%1,%3,%2\";
3782 }"
3783 [(set_attr "type" "compare")])
3784
3785 (define_insn "*extzvdi_internal2"
3786 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3787 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3788 (match_operand:SI 2 "const_int_operand" "i")
3789 (match_operand:SI 3 "const_int_operand" "i"))
3790 (const_int 0)))
3791 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3792 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3793 "TARGET_64BIT"
3794 "*
3795 {
3796 int start = INTVAL (operands[3]) & 63;
3797 int size = INTVAL (operands[2]) & 63;
3798
3799 if (start + size >= 64)
3800 operands[3] = const0_rtx;
3801 else
3802 operands[3] = GEN_INT (start + size);
3803 operands[2] = GEN_INT (64 - size);
3804 return \"rldicl. %0,%1,%3,%2\";
3805 }"
3806 [(set_attr "type" "compare")])
3807
3808 (define_insn "rotlsi3"
3809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3810 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3811 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3812 ""
3813 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3814
3815 (define_insn "*rotlsi3_internal2"
3816 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3817 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3818 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3819 (const_int 0)))
3820 (clobber (match_scratch:SI 3 "=r,r"))]
3821 ""
3822 "@
3823 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3824 #"
3825 [(set_attr "type" "delayed_compare")
3826 (set_attr "length" "4,8")])
3827
3828 (define_split
3829 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3830 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3831 (match_operand:SI 2 "reg_or_cint_operand" ""))
3832 (const_int 0)))
3833 (clobber (match_scratch:SI 3 ""))]
3834 "reload_completed"
3835 [(set (match_dup 3)
3836 (rotate:SI (match_dup 1) (match_dup 2)))
3837 (set (match_dup 0)
3838 (compare:CC (match_dup 3)
3839 (const_int 0)))]
3840 "")
3841
3842 (define_insn "*rotlsi3_internal3"
3843 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3844 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3845 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3846 (const_int 0)))
3847 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3848 (rotate:SI (match_dup 1) (match_dup 2)))]
3849 ""
3850 "@
3851 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3852 #"
3853 [(set_attr "type" "delayed_compare")
3854 (set_attr "length" "4,8")])
3855
3856 (define_split
3857 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3858 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3859 (match_operand:SI 2 "reg_or_cint_operand" ""))
3860 (const_int 0)))
3861 (set (match_operand:SI 0 "gpc_reg_operand" "")
3862 (rotate:SI (match_dup 1) (match_dup 2)))]
3863 "reload_completed"
3864 [(set (match_dup 0)
3865 (rotate:SI (match_dup 1) (match_dup 2)))
3866 (set (match_dup 3)
3867 (compare:CC (match_dup 0)
3868 (const_int 0)))]
3869 "")
3870
3871 (define_insn "*rotlsi3_internal4"
3872 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3873 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3874 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3875 (match_operand:SI 3 "mask_operand" "n")))]
3876 ""
3877 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3878
3879 (define_insn "*rotlsi3_internal5"
3880 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3881 (compare:CC (and:SI
3882 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3883 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3884 (match_operand:SI 3 "mask_operand" "n,n"))
3885 (const_int 0)))
3886 (clobber (match_scratch:SI 4 "=r,r"))]
3887 ""
3888 "@
3889 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3890 #"
3891 [(set_attr "type" "delayed_compare")
3892 (set_attr "length" "4,8")])
3893
3894 (define_split
3895 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3896 (compare:CC (and:SI
3897 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3898 (match_operand:SI 2 "reg_or_cint_operand" ""))
3899 (match_operand:SI 3 "mask_operand" ""))
3900 (const_int 0)))
3901 (clobber (match_scratch:SI 4 ""))]
3902 "reload_completed"
3903 [(set (match_dup 4)
3904 (and:SI (rotate:SI (match_dup 1)
3905 (match_dup 2))
3906 (match_dup 3)))
3907 (set (match_dup 0)
3908 (compare:CC (match_dup 4)
3909 (const_int 0)))]
3910 "")
3911
3912 (define_insn "*rotlsi3_internal6"
3913 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3914 (compare:CC (and:SI
3915 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3916 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3917 (match_operand:SI 3 "mask_operand" "n,n"))
3918 (const_int 0)))
3919 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3920 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3921 ""
3922 "@
3923 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3924 #"
3925 [(set_attr "type" "delayed_compare")
3926 (set_attr "length" "4,8")])
3927
3928 (define_split
3929 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3930 (compare:CC (and:SI
3931 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3932 (match_operand:SI 2 "reg_or_cint_operand" ""))
3933 (match_operand:SI 3 "mask_operand" ""))
3934 (const_int 0)))
3935 (set (match_operand:SI 0 "gpc_reg_operand" "")
3936 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3937 "reload_completed"
3938 [(set (match_dup 0)
3939 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3940 (set (match_dup 4)
3941 (compare:CC (match_dup 0)
3942 (const_int 0)))]
3943 "")
3944
3945 (define_insn "*rotlsi3_internal7"
3946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3947 (zero_extend:SI
3948 (subreg:QI
3949 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3950 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3951 ""
3952 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3953
3954 (define_insn "*rotlsi3_internal8"
3955 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3956 (compare:CC (zero_extend:SI
3957 (subreg:QI
3958 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3959 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3960 (const_int 0)))
3961 (clobber (match_scratch:SI 3 "=r,r"))]
3962 ""
3963 "@
3964 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3965 #"
3966 [(set_attr "type" "delayed_compare")
3967 (set_attr "length" "4,8")])
3968
3969 (define_split
3970 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3971 (compare:CC (zero_extend:SI
3972 (subreg:QI
3973 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3974 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3975 (const_int 0)))
3976 (clobber (match_scratch:SI 3 ""))]
3977 "reload_completed"
3978 [(set (match_dup 3)
3979 (zero_extend:SI (subreg:QI
3980 (rotate:SI (match_dup 1)
3981 (match_dup 2)) 0)))
3982 (set (match_dup 0)
3983 (compare:CC (match_dup 3)
3984 (const_int 0)))]
3985 "")
3986
3987 (define_insn "*rotlsi3_internal9"
3988 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3989 (compare:CC (zero_extend:SI
3990 (subreg:QI
3991 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3992 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3993 (const_int 0)))
3994 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3995 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3996 ""
3997 "@
3998 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3999 #"
4000 [(set_attr "type" "delayed_compare")
4001 (set_attr "length" "4,8")])
4002
4003 (define_split
4004 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4005 (compare:CC (zero_extend:SI
4006 (subreg:QI
4007 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4008 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4009 (const_int 0)))
4010 (set (match_operand:SI 0 "gpc_reg_operand" "")
4011 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4012 "reload_completed"
4013 [(set (match_dup 0)
4014 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4015 (set (match_dup 3)
4016 (compare:CC (match_dup 0)
4017 (const_int 0)))]
4018 "")
4019
4020 (define_insn "*rotlsi3_internal10"
4021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4022 (zero_extend:SI
4023 (subreg:HI
4024 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4025 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4026 ""
4027 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
4028
4029 (define_insn "*rotlsi3_internal11"
4030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4031 (compare:CC (zero_extend:SI
4032 (subreg:HI
4033 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4034 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4035 (const_int 0)))
4036 (clobber (match_scratch:SI 3 "=r,r"))]
4037 ""
4038 "@
4039 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
4040 #"
4041 [(set_attr "type" "delayed_compare")
4042 (set_attr "length" "4,8")])
4043
4044 (define_split
4045 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4046 (compare:CC (zero_extend:SI
4047 (subreg:HI
4048 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4049 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4050 (const_int 0)))
4051 (clobber (match_scratch:SI 3 ""))]
4052 "reload_completed"
4053 [(set (match_dup 3)
4054 (zero_extend:SI (subreg:HI
4055 (rotate:SI (match_dup 1)
4056 (match_dup 2)) 0)))
4057 (set (match_dup 0)
4058 (compare:CC (match_dup 3)
4059 (const_int 0)))]
4060 "")
4061
4062 (define_insn "*rotlsi3_internal12"
4063 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4064 (compare:CC (zero_extend:SI
4065 (subreg:HI
4066 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4067 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4068 (const_int 0)))
4069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4070 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4071 ""
4072 "@
4073 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
4074 #"
4075 [(set_attr "type" "delayed_compare")
4076 (set_attr "length" "4,8")])
4077
4078 (define_split
4079 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4080 (compare:CC (zero_extend:SI
4081 (subreg:HI
4082 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4083 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4084 (const_int 0)))
4085 (set (match_operand:SI 0 "gpc_reg_operand" "")
4086 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4087 "reload_completed"
4088 [(set (match_dup 0)
4089 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4090 (set (match_dup 3)
4091 (compare:CC (match_dup 0)
4092 (const_int 0)))]
4093 "")
4094
4095 ;; Note that we use "sle." instead of "sl." so that we can set
4096 ;; SHIFT_COUNT_TRUNCATED.
4097
4098 (define_expand "ashlsi3"
4099 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4100 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4101 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4102 ""
4103 "
4104 {
4105 if (TARGET_POWER)
4106 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4107 else
4108 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4109 DONE;
4110 }")
4111
4112 (define_insn "ashlsi3_power"
4113 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4114 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4115 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4116 (clobber (match_scratch:SI 3 "=q,X"))]
4117 "TARGET_POWER"
4118 "@
4119 sle %0,%1,%2
4120 {sli|slwi} %0,%1,%h2")
4121
4122 (define_insn "ashlsi3_no_power"
4123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4124 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4125 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4126 "! TARGET_POWER"
4127 "{sl|slw}%I2 %0,%1,%h2")
4128
4129 (define_insn ""
4130 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4131 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4132 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4133 (const_int 0)))
4134 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4135 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4136 "TARGET_POWER"
4137 "@
4138 sle. %3,%1,%2
4139 {sli.|slwi.} %3,%1,%h2
4140 #
4141 #"
4142 [(set_attr "type" "delayed_compare")
4143 (set_attr "length" "4,4,8,8")])
4144
4145 (define_split
4146 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4147 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4148 (match_operand:SI 2 "reg_or_cint_operand" ""))
4149 (const_int 0)))
4150 (clobber (match_scratch:SI 3 ""))
4151 (clobber (match_scratch:SI 4 ""))]
4152 "TARGET_POWER && reload_completed"
4153 [(parallel [(set (match_dup 3)
4154 (ashift:SI (match_dup 1) (match_dup 2)))
4155 (clobber (match_dup 4))])
4156 (set (match_dup 0)
4157 (compare:CC (match_dup 3)
4158 (const_int 0)))]
4159 "")
4160
4161 (define_insn ""
4162 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4163 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4164 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4165 (const_int 0)))
4166 (clobber (match_scratch:SI 3 "=r,r"))]
4167 "! TARGET_POWER && TARGET_32BIT"
4168 "@
4169 {sl|slw}%I2. %3,%1,%h2
4170 #"
4171 [(set_attr "type" "delayed_compare")
4172 (set_attr "length" "4,8")])
4173
4174 (define_split
4175 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4176 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4177 (match_operand:SI 2 "reg_or_cint_operand" ""))
4178 (const_int 0)))
4179 (clobber (match_scratch:SI 3 ""))]
4180 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4181 [(set (match_dup 3)
4182 (ashift:SI (match_dup 1) (match_dup 2)))
4183 (set (match_dup 0)
4184 (compare:CC (match_dup 3)
4185 (const_int 0)))]
4186 "")
4187
4188 (define_insn ""
4189 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4190 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4191 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4192 (const_int 0)))
4193 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4194 (ashift:SI (match_dup 1) (match_dup 2)))
4195 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4196 "TARGET_POWER"
4197 "@
4198 sle. %0,%1,%2
4199 {sli.|slwi.} %0,%1,%h2
4200 #
4201 #"
4202 [(set_attr "type" "delayed_compare")
4203 (set_attr "length" "4,4,8,8")])
4204
4205 (define_split
4206 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4207 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4208 (match_operand:SI 2 "reg_or_cint_operand" ""))
4209 (const_int 0)))
4210 (set (match_operand:SI 0 "gpc_reg_operand" "")
4211 (ashift:SI (match_dup 1) (match_dup 2)))
4212 (clobber (match_scratch:SI 4 ""))]
4213 "TARGET_POWER && reload_completed"
4214 [(parallel [(set (match_dup 0)
4215 (ashift:SI (match_dup 1) (match_dup 2)))
4216 (clobber (match_dup 4))])
4217 (set (match_dup 3)
4218 (compare:CC (match_dup 0)
4219 (const_int 0)))]
4220 "")
4221
4222 (define_insn ""
4223 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4224 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4225 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4226 (const_int 0)))
4227 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4228 (ashift:SI (match_dup 1) (match_dup 2)))]
4229 "! TARGET_POWER && TARGET_32BIT"
4230 "@
4231 {sl|slw}%I2. %0,%1,%h2
4232 #"
4233 [(set_attr "type" "delayed_compare")
4234 (set_attr "length" "4,8")])
4235
4236 (define_split
4237 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4238 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4239 (match_operand:SI 2 "reg_or_cint_operand" ""))
4240 (const_int 0)))
4241 (set (match_operand:SI 0 "gpc_reg_operand" "")
4242 (ashift:SI (match_dup 1) (match_dup 2)))]
4243 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4244 [(set (match_dup 0)
4245 (ashift:SI (match_dup 1) (match_dup 2)))
4246 (set (match_dup 3)
4247 (compare:CC (match_dup 0)
4248 (const_int 0)))]
4249 "")
4250
4251 (define_insn "rlwinm"
4252 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4253 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4254 (match_operand:SI 2 "const_int_operand" "i"))
4255 (match_operand:SI 3 "mask_operand" "n")))]
4256 "includes_lshift_p (operands[2], operands[3])"
4257 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4258
4259 (define_insn ""
4260 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4261 (compare:CC
4262 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4263 (match_operand:SI 2 "const_int_operand" "i,i"))
4264 (match_operand:SI 3 "mask_operand" "n,n"))
4265 (const_int 0)))
4266 (clobber (match_scratch:SI 4 "=r,r"))]
4267 "includes_lshift_p (operands[2], operands[3])"
4268 "@
4269 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4270 #"
4271 [(set_attr "type" "delayed_compare")
4272 (set_attr "length" "4,8")])
4273
4274 (define_split
4275 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4276 (compare:CC
4277 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4278 (match_operand:SI 2 "const_int_operand" ""))
4279 (match_operand:SI 3 "mask_operand" ""))
4280 (const_int 0)))
4281 (clobber (match_scratch:SI 4 ""))]
4282 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4283 [(set (match_dup 4)
4284 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4285 (match_dup 3)))
4286 (set (match_dup 0)
4287 (compare:CC (match_dup 4)
4288 (const_int 0)))]
4289 "")
4290
4291 (define_insn ""
4292 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4293 (compare:CC
4294 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4295 (match_operand:SI 2 "const_int_operand" "i,i"))
4296 (match_operand:SI 3 "mask_operand" "n,n"))
4297 (const_int 0)))
4298 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4299 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4300 "includes_lshift_p (operands[2], operands[3])"
4301 "@
4302 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4303 #"
4304 [(set_attr "type" "delayed_compare")
4305 (set_attr "length" "4,8")])
4306
4307 (define_split
4308 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4309 (compare:CC
4310 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4311 (match_operand:SI 2 "const_int_operand" ""))
4312 (match_operand:SI 3 "mask_operand" ""))
4313 (const_int 0)))
4314 (set (match_operand:SI 0 "gpc_reg_operand" "")
4315 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4316 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4317 [(set (match_dup 0)
4318 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4319 (set (match_dup 4)
4320 (compare:CC (match_dup 0)
4321 (const_int 0)))]
4322 "")
4323
4324 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4325 ;; "sli x,x,0".
4326 (define_expand "lshrsi3"
4327 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4328 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4329 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4330 ""
4331 "
4332 {
4333 if (TARGET_POWER)
4334 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4335 else
4336 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4337 DONE;
4338 }")
4339
4340 (define_insn "lshrsi3_power"
4341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4342 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4343 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4344 (clobber (match_scratch:SI 3 "=q,X,X"))]
4345 "TARGET_POWER"
4346 "@
4347 sre %0,%1,%2
4348 mr %0,%1
4349 {s%A2i|s%A2wi} %0,%1,%h2")
4350
4351 (define_insn "lshrsi3_no_power"
4352 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4353 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4354 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4355 "! TARGET_POWER"
4356 "@
4357 mr %0,%1
4358 {sr|srw}%I2 %0,%1,%h2")
4359
4360 (define_insn ""
4361 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4362 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4363 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4364 (const_int 0)))
4365 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4366 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4367 "TARGET_POWER"
4368 "@
4369 sre. %3,%1,%2
4370 mr. %1,%1
4371 {s%A2i.|s%A2wi.} %3,%1,%h2
4372 #
4373 #
4374 #"
4375 [(set_attr "type" "delayed_compare")
4376 (set_attr "length" "4,4,4,8,8,8")])
4377
4378 (define_split
4379 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4380 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4381 (match_operand:SI 2 "reg_or_cint_operand" ""))
4382 (const_int 0)))
4383 (clobber (match_scratch:SI 3 ""))
4384 (clobber (match_scratch:SI 4 ""))]
4385 "TARGET_POWER && reload_completed"
4386 [(parallel [(set (match_dup 3)
4387 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4388 (clobber (match_dup 4))])
4389 (set (match_dup 0)
4390 (compare:CC (match_dup 3)
4391 (const_int 0)))]
4392 "")
4393
4394 (define_insn ""
4395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4396 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4397 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4398 (const_int 0)))
4399 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4400 "! TARGET_POWER && TARGET_32BIT"
4401 "@
4402 mr. %1,%1
4403 {sr|srw}%I2. %3,%1,%h2
4404 #
4405 #"
4406 [(set_attr "type" "delayed_compare")
4407 (set_attr "length" "4,4,8,8")])
4408
4409 (define_split
4410 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4411 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4412 (match_operand:SI 2 "reg_or_cint_operand" ""))
4413 (const_int 0)))
4414 (clobber (match_scratch:SI 3 ""))]
4415 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4416 [(set (match_dup 3)
4417 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4418 (set (match_dup 0)
4419 (compare:CC (match_dup 3)
4420 (const_int 0)))]
4421 "")
4422
4423 (define_insn ""
4424 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4425 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4426 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4427 (const_int 0)))
4428 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4429 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4430 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4431 "TARGET_POWER"
4432 "@
4433 sre. %0,%1,%2
4434 mr. %0,%1
4435 {s%A2i.|s%A2wi.} %0,%1,%h2
4436 #
4437 #
4438 #"
4439 [(set_attr "type" "delayed_compare")
4440 (set_attr "length" "4,4,4,8,8,8")])
4441
4442 (define_split
4443 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4444 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4445 (match_operand:SI 2 "reg_or_cint_operand" ""))
4446 (const_int 0)))
4447 (set (match_operand:SI 0 "gpc_reg_operand" "")
4448 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4449 (clobber (match_scratch:SI 4 ""))]
4450 "TARGET_POWER && reload_completed"
4451 [(parallel [(set (match_dup 0)
4452 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4453 (clobber (match_dup 4))])
4454 (set (match_dup 3)
4455 (compare:CC (match_dup 0)
4456 (const_int 0)))]
4457 "")
4458
4459 (define_insn ""
4460 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4461 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4462 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4463 (const_int 0)))
4464 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4465 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4466 "! TARGET_POWER && TARGET_32BIT"
4467 "@
4468 mr. %0,%1
4469 {sr|srw}%I2. %0,%1,%h2
4470 #
4471 #"
4472 [(set_attr "type" "delayed_compare")
4473 (set_attr "length" "4,4,8,8")])
4474
4475 (define_split
4476 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4477 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4478 (match_operand:SI 2 "reg_or_cint_operand" ""))
4479 (const_int 0)))
4480 (set (match_operand:SI 0 "gpc_reg_operand" "")
4481 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4482 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4483 [(set (match_dup 0)
4484 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4485 (set (match_dup 3)
4486 (compare:CC (match_dup 0)
4487 (const_int 0)))]
4488 "")
4489
4490 (define_insn ""
4491 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4492 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4493 (match_operand:SI 2 "const_int_operand" "i"))
4494 (match_operand:SI 3 "mask_operand" "n")))]
4495 "includes_rshift_p (operands[2], operands[3])"
4496 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4497
4498 (define_insn ""
4499 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4500 (compare:CC
4501 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4502 (match_operand:SI 2 "const_int_operand" "i,i"))
4503 (match_operand:SI 3 "mask_operand" "n,n"))
4504 (const_int 0)))
4505 (clobber (match_scratch:SI 4 "=r,r"))]
4506 "includes_rshift_p (operands[2], operands[3])"
4507 "@
4508 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4509 #"
4510 [(set_attr "type" "delayed_compare")
4511 (set_attr "length" "4,8")])
4512
4513 (define_split
4514 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4515 (compare:CC
4516 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4517 (match_operand:SI 2 "const_int_operand" ""))
4518 (match_operand:SI 3 "mask_operand" ""))
4519 (const_int 0)))
4520 (clobber (match_scratch:SI 4 ""))]
4521 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4522 [(set (match_dup 4)
4523 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4524 (match_dup 3)))
4525 (set (match_dup 0)
4526 (compare:CC (match_dup 4)
4527 (const_int 0)))]
4528 "")
4529
4530 (define_insn ""
4531 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4532 (compare:CC
4533 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4534 (match_operand:SI 2 "const_int_operand" "i,i"))
4535 (match_operand:SI 3 "mask_operand" "n,n"))
4536 (const_int 0)))
4537 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4538 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4539 "includes_rshift_p (operands[2], operands[3])"
4540 "@
4541 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4542 #"
4543 [(set_attr "type" "delayed_compare")
4544 (set_attr "length" "4,8")])
4545
4546 (define_split
4547 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4548 (compare:CC
4549 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4550 (match_operand:SI 2 "const_int_operand" ""))
4551 (match_operand:SI 3 "mask_operand" ""))
4552 (const_int 0)))
4553 (set (match_operand:SI 0 "gpc_reg_operand" "")
4554 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4555 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4556 [(set (match_dup 0)
4557 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4558 (set (match_dup 4)
4559 (compare:CC (match_dup 0)
4560 (const_int 0)))]
4561 "")
4562
4563 (define_insn ""
4564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4565 (zero_extend:SI
4566 (subreg:QI
4567 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4568 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4569 "includes_rshift_p (operands[2], GEN_INT (255))"
4570 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4571
4572 (define_insn ""
4573 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4574 (compare:CC
4575 (zero_extend:SI
4576 (subreg:QI
4577 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4578 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4579 (const_int 0)))
4580 (clobber (match_scratch:SI 3 "=r,r"))]
4581 "includes_rshift_p (operands[2], GEN_INT (255))"
4582 "@
4583 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4584 #"
4585 [(set_attr "type" "delayed_compare")
4586 (set_attr "length" "4,8")])
4587
4588 (define_split
4589 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4590 (compare:CC
4591 (zero_extend:SI
4592 (subreg:QI
4593 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4594 (match_operand:SI 2 "const_int_operand" "")) 0))
4595 (const_int 0)))
4596 (clobber (match_scratch:SI 3 ""))]
4597 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4598 [(set (match_dup 3)
4599 (zero_extend:SI (subreg:QI
4600 (lshiftrt:SI (match_dup 1)
4601 (match_dup 2)) 0)))
4602 (set (match_dup 0)
4603 (compare:CC (match_dup 3)
4604 (const_int 0)))]
4605 "")
4606
4607 (define_insn ""
4608 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4609 (compare:CC
4610 (zero_extend:SI
4611 (subreg:QI
4612 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4613 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4614 (const_int 0)))
4615 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4616 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4617 "includes_rshift_p (operands[2], GEN_INT (255))"
4618 "@
4619 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4620 #"
4621 [(set_attr "type" "delayed_compare")
4622 (set_attr "length" "4,8")])
4623
4624 (define_split
4625 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4626 (compare:CC
4627 (zero_extend:SI
4628 (subreg:QI
4629 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4630 (match_operand:SI 2 "const_int_operand" "")) 0))
4631 (const_int 0)))
4632 (set (match_operand:SI 0 "gpc_reg_operand" "")
4633 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4634 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4635 [(set (match_dup 0)
4636 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4637 (set (match_dup 3)
4638 (compare:CC (match_dup 0)
4639 (const_int 0)))]
4640 "")
4641
4642 (define_insn ""
4643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4644 (zero_extend:SI
4645 (subreg:HI
4646 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4647 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4648 "includes_rshift_p (operands[2], GEN_INT (65535))"
4649 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4650
4651 (define_insn ""
4652 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4653 (compare:CC
4654 (zero_extend:SI
4655 (subreg:HI
4656 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4657 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4658 (const_int 0)))
4659 (clobber (match_scratch:SI 3 "=r,r"))]
4660 "includes_rshift_p (operands[2], GEN_INT (65535))"
4661 "@
4662 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4663 #"
4664 [(set_attr "type" "delayed_compare")
4665 (set_attr "length" "4,8")])
4666
4667 (define_split
4668 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4669 (compare:CC
4670 (zero_extend:SI
4671 (subreg:HI
4672 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4673 (match_operand:SI 2 "const_int_operand" "")) 0))
4674 (const_int 0)))
4675 (clobber (match_scratch:SI 3 ""))]
4676 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4677 [(set (match_dup 3)
4678 (zero_extend:SI (subreg:HI
4679 (lshiftrt:SI (match_dup 1)
4680 (match_dup 2)) 0)))
4681 (set (match_dup 0)
4682 (compare:CC (match_dup 3)
4683 (const_int 0)))]
4684 "")
4685
4686 (define_insn ""
4687 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4688 (compare:CC
4689 (zero_extend:SI
4690 (subreg:HI
4691 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4692 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4693 (const_int 0)))
4694 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4695 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4696 "includes_rshift_p (operands[2], GEN_INT (65535))"
4697 "@
4698 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4699 #"
4700 [(set_attr "type" "delayed_compare")
4701 (set_attr "length" "4,8")])
4702
4703 (define_split
4704 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4705 (compare:CC
4706 (zero_extend:SI
4707 (subreg:HI
4708 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4709 (match_operand:SI 2 "const_int_operand" "")) 0))
4710 (const_int 0)))
4711 (set (match_operand:SI 0 "gpc_reg_operand" "")
4712 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4713 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4714 [(set (match_dup 0)
4715 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4716 (set (match_dup 3)
4717 (compare:CC (match_dup 0)
4718 (const_int 0)))]
4719 "")
4720
4721 (define_insn ""
4722 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4723 (const_int 1)
4724 (match_operand:SI 1 "gpc_reg_operand" "r"))
4725 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4726 (const_int 31)))]
4727 "TARGET_POWER"
4728 "rrib %0,%1,%2")
4729
4730 (define_insn ""
4731 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4732 (const_int 1)
4733 (match_operand:SI 1 "gpc_reg_operand" "r"))
4734 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4735 (const_int 31)))]
4736 "TARGET_POWER"
4737 "rrib %0,%1,%2")
4738
4739 (define_insn ""
4740 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4741 (const_int 1)
4742 (match_operand:SI 1 "gpc_reg_operand" "r"))
4743 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4744 (const_int 1)
4745 (const_int 0)))]
4746 "TARGET_POWER"
4747 "rrib %0,%1,%2")
4748
4749 (define_expand "ashrsi3"
4750 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4751 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4752 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4753 ""
4754 "
4755 {
4756 if (TARGET_POWER)
4757 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4758 else
4759 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4760 DONE;
4761 }")
4762
4763 (define_insn "ashrsi3_power"
4764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4765 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4766 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4767 (clobber (match_scratch:SI 3 "=q,X"))]
4768 "TARGET_POWER"
4769 "@
4770 srea %0,%1,%2
4771 {srai|srawi} %0,%1,%h2")
4772
4773 (define_insn "ashrsi3_no_power"
4774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4775 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4776 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4777 "! TARGET_POWER"
4778 "{sra|sraw}%I2 %0,%1,%h2")
4779
4780 (define_insn ""
4781 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4782 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4783 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4784 (const_int 0)))
4785 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4786 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4787 "TARGET_POWER"
4788 "@
4789 srea. %3,%1,%2
4790 {srai.|srawi.} %3,%1,%h2
4791 #
4792 #"
4793 [(set_attr "type" "delayed_compare")
4794 (set_attr "length" "4,4,8,8")])
4795
4796 (define_split
4797 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4798 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4799 (match_operand:SI 2 "reg_or_cint_operand" ""))
4800 (const_int 0)))
4801 (clobber (match_scratch:SI 3 ""))
4802 (clobber (match_scratch:SI 4 ""))]
4803 "TARGET_POWER && reload_completed"
4804 [(parallel [(set (match_dup 3)
4805 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4806 (clobber (match_dup 4))])
4807 (set (match_dup 0)
4808 (compare:CC (match_dup 3)
4809 (const_int 0)))]
4810 "")
4811
4812 (define_insn ""
4813 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4814 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4815 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4816 (const_int 0)))
4817 (clobber (match_scratch:SI 3 "=r,r"))]
4818 "! TARGET_POWER"
4819 "@
4820 {sra|sraw}%I2. %3,%1,%h2
4821 #"
4822 [(set_attr "type" "delayed_compare")
4823 (set_attr "length" "4,8")])
4824
4825 (define_split
4826 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4827 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4828 (match_operand:SI 2 "reg_or_cint_operand" ""))
4829 (const_int 0)))
4830 (clobber (match_scratch:SI 3 ""))]
4831 "! TARGET_POWER && reload_completed"
4832 [(set (match_dup 3)
4833 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4834 (set (match_dup 0)
4835 (compare:CC (match_dup 3)
4836 (const_int 0)))]
4837 "")
4838
4839 (define_insn ""
4840 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4841 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4842 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4843 (const_int 0)))
4844 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4845 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4846 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4847 "TARGET_POWER"
4848 "@
4849 srea. %0,%1,%2
4850 {srai.|srawi.} %0,%1,%h2
4851 #
4852 #"
4853 [(set_attr "type" "delayed_compare")
4854 (set_attr "length" "4,4,8,8")])
4855
4856 (define_split
4857 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4858 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4859 (match_operand:SI 2 "reg_or_cint_operand" ""))
4860 (const_int 0)))
4861 (set (match_operand:SI 0 "gpc_reg_operand" "")
4862 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4863 (clobber (match_scratch:SI 4 ""))]
4864 "TARGET_POWER && reload_completed"
4865 [(parallel [(set (match_dup 0)
4866 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4867 (clobber (match_dup 4))])
4868 (set (match_dup 3)
4869 (compare:CC (match_dup 0)
4870 (const_int 0)))]
4871 "")
4872
4873 (define_insn ""
4874 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4875 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4876 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4877 (const_int 0)))
4878 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4879 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4880 "! TARGET_POWER"
4881 "@
4882 {sra|sraw}%I2. %0,%1,%h2
4883 #"
4884 [(set_attr "type" "delayed_compare")
4885 (set_attr "length" "4,8")])
4886 \f
4887 (define_split
4888 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4889 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4890 (match_operand:SI 2 "reg_or_cint_operand" ""))
4891 (const_int 0)))
4892 (set (match_operand:SI 0 "gpc_reg_operand" "")
4893 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4894 "! TARGET_POWER && reload_completed"
4895 [(set (match_dup 0)
4896 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4897 (set (match_dup 3)
4898 (compare:CC (match_dup 0)
4899 (const_int 0)))]
4900 "")
4901
4902 ;; Floating-point insns, excluding normal data motion.
4903 ;;
4904 ;; PowerPC has a full set of single-precision floating point instructions.
4905 ;;
4906 ;; For the POWER architecture, we pretend that we have both SFmode and
4907 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4908 ;; The only conversions we will do will be when storing to memory. In that
4909 ;; case, we will use the "frsp" instruction before storing.
4910 ;;
4911 ;; Note that when we store into a single-precision memory location, we need to
4912 ;; use the frsp insn first. If the register being stored isn't dead, we
4913 ;; need a scratch register for the frsp. But this is difficult when the store
4914 ;; is done by reload. It is not incorrect to do the frsp on the register in
4915 ;; this case, we just lose precision that we would have otherwise gotten but
4916 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4917
4918 (define_expand "extendsfdf2"
4919 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4920 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4921 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4922 "")
4923
4924 (define_insn_and_split "*extendsfdf2_fpr"
4925 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f")
4926 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4927 "TARGET_HARD_FLOAT && TARGET_FPRS"
4928 "@
4929 #
4930 fmr %0,%1
4931 lfs%U1%X1 %0,%1"
4932 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4933 [(const_int 0)]
4934 {
4935 emit_note (NOTE_INSN_DELETED);
4936 DONE;
4937 }
4938 [(set_attr "type" "fp,fp,fpload")])
4939
4940 (define_expand "truncdfsf2"
4941 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4942 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4943 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
4944 "")
4945
4946 (define_insn "*truncdfsf2_fpr"
4947 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4948 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4949 "TARGET_HARD_FLOAT && TARGET_FPRS"
4950 "frsp %0,%1"
4951 [(set_attr "type" "fp")])
4952
4953 (define_insn "aux_truncdfsf2"
4954 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4955 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4956 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4957 "frsp %0,%1"
4958 [(set_attr "type" "fp")])
4959
4960 (define_expand "negsf2"
4961 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4962 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4963 "TARGET_HARD_FLOAT"
4964 "")
4965
4966 (define_insn "*negsf2"
4967 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4968 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4969 "TARGET_HARD_FLOAT && TARGET_FPRS"
4970 "fneg %0,%1"
4971 [(set_attr "type" "fp")])
4972
4973 (define_expand "abssf2"
4974 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4975 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4976 "TARGET_HARD_FLOAT"
4977 "")
4978
4979 (define_insn "*abssf2"
4980 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4981 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4982 "TARGET_HARD_FLOAT && TARGET_FPRS"
4983 "fabs %0,%1"
4984 [(set_attr "type" "fp")])
4985
4986 (define_insn ""
4987 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4988 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4989 "TARGET_HARD_FLOAT && TARGET_FPRS"
4990 "fnabs %0,%1"
4991 [(set_attr "type" "fp")])
4992
4993 (define_expand "addsf3"
4994 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4995 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4996 (match_operand:SF 2 "gpc_reg_operand" "")))]
4997 "TARGET_HARD_FLOAT"
4998 "")
4999
5000 (define_insn ""
5001 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5002 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5003 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5004 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5005 "fadds %0,%1,%2"
5006 [(set_attr "type" "fp")])
5007
5008 (define_insn ""
5009 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5010 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5011 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5012 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5013 "{fa|fadd} %0,%1,%2"
5014 [(set_attr "type" "fp")])
5015
5016 (define_expand "subsf3"
5017 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5018 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5019 (match_operand:SF 2 "gpc_reg_operand" "")))]
5020 "TARGET_HARD_FLOAT"
5021 "")
5022
5023 (define_insn ""
5024 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5025 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5026 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5027 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5028 "fsubs %0,%1,%2"
5029 [(set_attr "type" "fp")])
5030
5031 (define_insn ""
5032 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5033 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5034 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5035 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5036 "{fs|fsub} %0,%1,%2"
5037 [(set_attr "type" "fp")])
5038
5039 (define_expand "mulsf3"
5040 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5041 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5042 (match_operand:SF 2 "gpc_reg_operand" "")))]
5043 "TARGET_HARD_FLOAT"
5044 "")
5045
5046 (define_insn ""
5047 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5048 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5049 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5050 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5051 "fmuls %0,%1,%2"
5052 [(set_attr "type" "fp")])
5053
5054 (define_insn ""
5055 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5056 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5057 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5058 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5059 "{fm|fmul} %0,%1,%2"
5060 [(set_attr "type" "dmul")])
5061
5062 (define_insn "fres"
5063 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5064 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5065 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5066 "fres %0,%1"
5067 [(set_attr "type" "fp")])
5068
5069 (define_expand "divsf3"
5070 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5071 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5072 (match_operand:SF 2 "gpc_reg_operand" "")))]
5073 "TARGET_HARD_FLOAT"
5074 {
5075 if (swdiv && !optimize_size && TARGET_PPC_GFXOPT
5076 && flag_finite_math_only && !flag_trapping_math)
5077 {
5078 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5079 DONE;
5080 }
5081 })
5082
5083 (define_insn ""
5084 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5085 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5086 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5087 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5088 "fdivs %0,%1,%2"
5089 [(set_attr "type" "sdiv")])
5090
5091 (define_insn ""
5092 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5093 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5094 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5095 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5096 "{fd|fdiv} %0,%1,%2"
5097 [(set_attr "type" "ddiv")])
5098
5099 (define_insn ""
5100 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5101 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5102 (match_operand:SF 2 "gpc_reg_operand" "f"))
5103 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5104 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5105 "fmadds %0,%1,%2,%3"
5106 [(set_attr "type" "fp")])
5107
5108 (define_insn ""
5109 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5110 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5111 (match_operand:SF 2 "gpc_reg_operand" "f"))
5112 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5113 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5114 "{fma|fmadd} %0,%1,%2,%3"
5115 [(set_attr "type" "dmul")])
5116
5117 (define_insn ""
5118 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5119 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5120 (match_operand:SF 2 "gpc_reg_operand" "f"))
5121 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5122 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5123 "fmsubs %0,%1,%2,%3"
5124 [(set_attr "type" "fp")])
5125
5126 (define_insn ""
5127 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5128 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5129 (match_operand:SF 2 "gpc_reg_operand" "f"))
5130 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5131 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5132 "{fms|fmsub} %0,%1,%2,%3"
5133 [(set_attr "type" "dmul")])
5134
5135 (define_insn ""
5136 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5137 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5138 (match_operand:SF 2 "gpc_reg_operand" "f"))
5139 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5140 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5141 && HONOR_SIGNED_ZEROS (SFmode)"
5142 "fnmadds %0,%1,%2,%3"
5143 [(set_attr "type" "fp")])
5144
5145 (define_insn ""
5146 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5147 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5148 (match_operand:SF 2 "gpc_reg_operand" "f"))
5149 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5150 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5151 && ! HONOR_SIGNED_ZEROS (SFmode)"
5152 "fnmadds %0,%1,%2,%3"
5153 [(set_attr "type" "fp")])
5154
5155 (define_insn ""
5156 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5157 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5158 (match_operand:SF 2 "gpc_reg_operand" "f"))
5159 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5160 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5161 "{fnma|fnmadd} %0,%1,%2,%3"
5162 [(set_attr "type" "dmul")])
5163
5164 (define_insn ""
5165 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5166 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5167 (match_operand:SF 2 "gpc_reg_operand" "f"))
5168 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5169 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5170 && ! HONOR_SIGNED_ZEROS (SFmode)"
5171 "{fnma|fnmadd} %0,%1,%2,%3"
5172 [(set_attr "type" "dmul")])
5173
5174 (define_insn ""
5175 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5176 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5177 (match_operand:SF 2 "gpc_reg_operand" "f"))
5178 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5179 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5180 && HONOR_SIGNED_ZEROS (SFmode)"
5181 "fnmsubs %0,%1,%2,%3"
5182 [(set_attr "type" "fp")])
5183
5184 (define_insn ""
5185 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5186 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5187 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5188 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5189 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5190 && ! HONOR_SIGNED_ZEROS (SFmode)"
5191 "fnmsubs %0,%1,%2,%3"
5192 [(set_attr "type" "fp")])
5193
5194 (define_insn ""
5195 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5196 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5197 (match_operand:SF 2 "gpc_reg_operand" "f"))
5198 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5199 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5200 "{fnms|fnmsub} %0,%1,%2,%3"
5201 [(set_attr "type" "dmul")])
5202
5203 (define_insn ""
5204 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5205 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5206 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5207 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5208 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5209 && ! HONOR_SIGNED_ZEROS (SFmode)"
5210 "{fnms|fnmsub} %0,%1,%2,%3"
5211 [(set_attr "type" "dmul")])
5212
5213 (define_expand "sqrtsf2"
5214 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5215 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5216 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5217 "")
5218
5219 (define_insn ""
5220 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5221 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5222 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5223 "fsqrts %0,%1"
5224 [(set_attr "type" "ssqrt")])
5225
5226 (define_insn ""
5227 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5228 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5229 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5230 "fsqrt %0,%1"
5231 [(set_attr "type" "dsqrt")])
5232
5233 (define_expand "copysignsf3"
5234 [(set (match_dup 3)
5235 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5236 (set (match_dup 4)
5237 (neg:SF (abs:SF (match_dup 1))))
5238 (set (match_operand:SF 0 "gpc_reg_operand" "")
5239 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5240 (match_dup 5))
5241 (match_dup 3)
5242 (match_dup 4)))]
5243 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5244 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5245 {
5246 operands[3] = gen_reg_rtx (SFmode);
5247 operands[4] = gen_reg_rtx (SFmode);
5248 operands[5] = CONST0_RTX (SFmode);
5249 })
5250
5251 (define_expand "copysigndf3"
5252 [(set (match_dup 3)
5253 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5254 (set (match_dup 4)
5255 (neg:DF (abs:DF (match_dup 1))))
5256 (set (match_operand:DF 0 "gpc_reg_operand" "")
5257 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5258 (match_dup 5))
5259 (match_dup 3)
5260 (match_dup 4)))]
5261 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5262 && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)"
5263 {
5264 operands[3] = gen_reg_rtx (DFmode);
5265 operands[4] = gen_reg_rtx (DFmode);
5266 operands[5] = CONST0_RTX (DFmode);
5267 })
5268
5269 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5270 ;; fsel instruction and some auxiliary computations. Then we just have a
5271 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5272 ;; combine.
5273 (define_expand "smaxsf3"
5274 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5275 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5276 (match_operand:SF 2 "gpc_reg_operand" ""))
5277 (match_dup 1)
5278 (match_dup 2)))]
5279 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5280 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5281
5282 (define_expand "sminsf3"
5283 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5284 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5285 (match_operand:SF 2 "gpc_reg_operand" ""))
5286 (match_dup 2)
5287 (match_dup 1)))]
5288 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5289 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5290
5291 (define_split
5292 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5293 (match_operator:SF 3 "min_max_operator"
5294 [(match_operand:SF 1 "gpc_reg_operand" "")
5295 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5296 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5297 [(const_int 0)]
5298 "
5299 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5300 operands[1], operands[2]);
5301 DONE;
5302 }")
5303
5304 (define_expand "movsicc"
5305 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5306 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5307 (match_operand:SI 2 "gpc_reg_operand" "")
5308 (match_operand:SI 3 "gpc_reg_operand" "")))]
5309 "TARGET_ISEL"
5310 "
5311 {
5312 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5313 DONE;
5314 else
5315 FAIL;
5316 }")
5317
5318 ;; We use the BASE_REGS for the isel input operands because, if rA is
5319 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5320 ;; because we may switch the operands and rB may end up being rA.
5321 ;;
5322 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5323 ;; leave out the mode in operand 4 and use one pattern, but reload can
5324 ;; change the mode underneath our feet and then gets confused trying
5325 ;; to reload the value.
5326 (define_insn "isel_signed"
5327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5328 (if_then_else:SI
5329 (match_operator 1 "comparison_operator"
5330 [(match_operand:CC 4 "cc_reg_operand" "y")
5331 (const_int 0)])
5332 (match_operand:SI 2 "gpc_reg_operand" "b")
5333 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5334 "TARGET_ISEL"
5335 "*
5336 { return output_isel (operands); }"
5337 [(set_attr "length" "4")])
5338
5339 (define_insn "isel_unsigned"
5340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5341 (if_then_else:SI
5342 (match_operator 1 "comparison_operator"
5343 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5344 (const_int 0)])
5345 (match_operand:SI 2 "gpc_reg_operand" "b")
5346 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5347 "TARGET_ISEL"
5348 "*
5349 { return output_isel (operands); }"
5350 [(set_attr "length" "4")])
5351
5352 (define_expand "movsfcc"
5353 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5354 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5355 (match_operand:SF 2 "gpc_reg_operand" "")
5356 (match_operand:SF 3 "gpc_reg_operand" "")))]
5357 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5358 "
5359 {
5360 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5361 DONE;
5362 else
5363 FAIL;
5364 }")
5365
5366 (define_insn "*fselsfsf4"
5367 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5368 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5369 (match_operand:SF 4 "zero_fp_constant" "F"))
5370 (match_operand:SF 2 "gpc_reg_operand" "f")
5371 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5372 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5373 "fsel %0,%1,%2,%3"
5374 [(set_attr "type" "fp")])
5375
5376 (define_insn "*fseldfsf4"
5377 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5378 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5379 (match_operand:DF 4 "zero_fp_constant" "F"))
5380 (match_operand:SF 2 "gpc_reg_operand" "f")
5381 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5382 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5383 "fsel %0,%1,%2,%3"
5384 [(set_attr "type" "fp")])
5385
5386 (define_expand "negdf2"
5387 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5388 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5389 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5390 "")
5391
5392 (define_insn "*negdf2_fpr"
5393 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5394 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5395 "TARGET_HARD_FLOAT && TARGET_FPRS"
5396 "fneg %0,%1"
5397 [(set_attr "type" "fp")])
5398
5399 (define_expand "absdf2"
5400 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5401 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5402 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5403 "")
5404
5405 (define_insn "*absdf2_fpr"
5406 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5407 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5408 "TARGET_HARD_FLOAT && TARGET_FPRS"
5409 "fabs %0,%1"
5410 [(set_attr "type" "fp")])
5411
5412 (define_insn "*nabsdf2_fpr"
5413 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5414 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5415 "TARGET_HARD_FLOAT && TARGET_FPRS"
5416 "fnabs %0,%1"
5417 [(set_attr "type" "fp")])
5418
5419 (define_expand "adddf3"
5420 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5421 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5422 (match_operand:DF 2 "gpc_reg_operand" "")))]
5423 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5424 "")
5425
5426 (define_insn "*adddf3_fpr"
5427 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5428 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5429 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5430 "TARGET_HARD_FLOAT && TARGET_FPRS"
5431 "{fa|fadd} %0,%1,%2"
5432 [(set_attr "type" "fp")])
5433
5434 (define_expand "subdf3"
5435 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5436 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5437 (match_operand:DF 2 "gpc_reg_operand" "")))]
5438 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5439 "")
5440
5441 (define_insn "*subdf3_fpr"
5442 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5443 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5444 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5445 "TARGET_HARD_FLOAT && TARGET_FPRS"
5446 "{fs|fsub} %0,%1,%2"
5447 [(set_attr "type" "fp")])
5448
5449 (define_expand "muldf3"
5450 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5451 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5452 (match_operand:DF 2 "gpc_reg_operand" "")))]
5453 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5454 "")
5455
5456 (define_insn "*muldf3_fpr"
5457 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5458 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5459 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5460 "TARGET_HARD_FLOAT && TARGET_FPRS"
5461 "{fm|fmul} %0,%1,%2"
5462 [(set_attr "type" "dmul")])
5463
5464 (define_insn "fred"
5465 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5466 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5467 "TARGET_POPCNTB && flag_finite_math_only"
5468 "fre %0,%1"
5469 [(set_attr "type" "fp")])
5470
5471 (define_expand "divdf3"
5472 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5473 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5474 (match_operand:DF 2 "gpc_reg_operand" "")))]
5475 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5476 {
5477 if (swdiv && !optimize_size && TARGET_POPCNTB
5478 && flag_finite_math_only && !flag_trapping_math)
5479 {
5480 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
5481 DONE;
5482 }
5483 })
5484
5485 (define_insn "*divdf3_fpr"
5486 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5487 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5488 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5489 "TARGET_HARD_FLOAT && TARGET_FPRS"
5490 "{fd|fdiv} %0,%1,%2"
5491 [(set_attr "type" "ddiv")])
5492
5493 (define_insn ""
5494 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5495 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5496 (match_operand:DF 2 "gpc_reg_operand" "f"))
5497 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5498 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5499 "{fma|fmadd} %0,%1,%2,%3"
5500 [(set_attr "type" "dmul")])
5501
5502 (define_insn ""
5503 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5504 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5505 (match_operand:DF 2 "gpc_reg_operand" "f"))
5506 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5507 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5508 "{fms|fmsub} %0,%1,%2,%3"
5509 [(set_attr "type" "dmul")])
5510
5511 (define_insn ""
5512 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5513 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5514 (match_operand:DF 2 "gpc_reg_operand" "f"))
5515 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5516 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5517 && HONOR_SIGNED_ZEROS (DFmode)"
5518 "{fnma|fnmadd} %0,%1,%2,%3"
5519 [(set_attr "type" "dmul")])
5520
5521 (define_insn ""
5522 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5523 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5524 (match_operand:DF 2 "gpc_reg_operand" "f"))
5525 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5526 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5527 && ! HONOR_SIGNED_ZEROS (DFmode)"
5528 "{fnma|fnmadd} %0,%1,%2,%3"
5529 [(set_attr "type" "dmul")])
5530
5531 (define_insn ""
5532 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5533 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5534 (match_operand:DF 2 "gpc_reg_operand" "f"))
5535 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5536 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5537 && HONOR_SIGNED_ZEROS (DFmode)"
5538 "{fnms|fnmsub} %0,%1,%2,%3"
5539 [(set_attr "type" "dmul")])
5540
5541 (define_insn ""
5542 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5543 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5544 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5545 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5546 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5547 && ! HONOR_SIGNED_ZEROS (DFmode)"
5548 "{fnms|fnmsub} %0,%1,%2,%3"
5549 [(set_attr "type" "dmul")])
5550
5551 (define_insn "sqrtdf2"
5552 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5553 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5554 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5555 "fsqrt %0,%1"
5556 [(set_attr "type" "dsqrt")])
5557
5558 ;; The conditional move instructions allow us to perform max and min
5559 ;; operations even when
5560
5561 (define_expand "smaxdf3"
5562 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5563 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5564 (match_operand:DF 2 "gpc_reg_operand" ""))
5565 (match_dup 1)
5566 (match_dup 2)))]
5567 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5568 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5569
5570 (define_expand "smindf3"
5571 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5572 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5573 (match_operand:DF 2 "gpc_reg_operand" ""))
5574 (match_dup 2)
5575 (match_dup 1)))]
5576 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5577 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5578
5579 (define_split
5580 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5581 (match_operator:DF 3 "min_max_operator"
5582 [(match_operand:DF 1 "gpc_reg_operand" "")
5583 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5584 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math"
5585 [(const_int 0)]
5586 "
5587 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5588 operands[1], operands[2]);
5589 DONE;
5590 }")
5591
5592 (define_expand "movdfcc"
5593 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5594 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5595 (match_operand:DF 2 "gpc_reg_operand" "")
5596 (match_operand:DF 3 "gpc_reg_operand" "")))]
5597 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5598 "
5599 {
5600 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5601 DONE;
5602 else
5603 FAIL;
5604 }")
5605
5606 (define_insn "*fseldfdf4"
5607 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5608 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5609 (match_operand:DF 4 "zero_fp_constant" "F"))
5610 (match_operand:DF 2 "gpc_reg_operand" "f")
5611 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5612 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5613 "fsel %0,%1,%2,%3"
5614 [(set_attr "type" "fp")])
5615
5616 (define_insn "*fselsfdf4"
5617 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5618 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5619 (match_operand:SF 4 "zero_fp_constant" "F"))
5620 (match_operand:DF 2 "gpc_reg_operand" "f")
5621 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5622 "TARGET_PPC_GFXOPT"
5623 "fsel %0,%1,%2,%3"
5624 [(set_attr "type" "fp")])
5625 \f
5626 ;; Conversions to and from floating-point.
5627
5628 (define_expand "fixuns_truncsfsi2"
5629 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5630 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5631 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5632 "")
5633
5634 (define_expand "fix_truncsfsi2"
5635 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5636 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5637 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5638 "")
5639
5640 ; For each of these conversions, there is a define_expand, a define_insn
5641 ; with a '#' template, and a define_split (with C code). The idea is
5642 ; to allow constant folding with the template of the define_insn,
5643 ; then to have the insns split later (between sched1 and final).
5644
5645 (define_expand "floatsidf2"
5646 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5647 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5648 (use (match_dup 2))
5649 (use (match_dup 3))
5650 (clobber (match_dup 4))
5651 (clobber (match_dup 5))
5652 (clobber (match_dup 6))])]
5653 "TARGET_HARD_FLOAT && TARGET_FPRS"
5654 "
5655 {
5656 if (TARGET_E500_DOUBLE)
5657 {
5658 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5659 DONE;
5660 }
5661 if (TARGET_POWERPC64)
5662 {
5663 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5664 rtx t1 = gen_reg_rtx (DImode);
5665 rtx t2 = gen_reg_rtx (DImode);
5666 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5667 DONE;
5668 }
5669
5670 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5671 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5672 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5673 operands[5] = gen_reg_rtx (DFmode);
5674 operands[6] = gen_reg_rtx (SImode);
5675 }")
5676
5677 (define_insn_and_split "*floatsidf2_internal"
5678 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5679 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5680 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5681 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5682 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5683 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))
5684 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5685 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5686 "#"
5687 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5688 [(pc)]
5689 "
5690 {
5691 rtx lowword, highword;
5692 gcc_assert (MEM_P (operands[4]));
5693 highword = adjust_address (operands[4], SImode, 0);
5694 lowword = adjust_address (operands[4], SImode, 4);
5695 if (! WORDS_BIG_ENDIAN)
5696 {
5697 rtx tmp;
5698 tmp = highword; highword = lowword; lowword = tmp;
5699 }
5700
5701 emit_insn (gen_xorsi3 (operands[6], operands[1],
5702 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5703 emit_move_insn (lowword, operands[6]);
5704 emit_move_insn (highword, operands[2]);
5705 emit_move_insn (operands[5], operands[4]);
5706 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5707 DONE;
5708 }"
5709 [(set_attr "length" "24")])
5710
5711 (define_expand "floatunssisf2"
5712 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5713 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5714 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5715 "")
5716
5717 (define_expand "floatunssidf2"
5718 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5719 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5720 (use (match_dup 2))
5721 (use (match_dup 3))
5722 (clobber (match_dup 4))
5723 (clobber (match_dup 5))])]
5724 "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5725 "
5726 {
5727 if (TARGET_E500_DOUBLE)
5728 {
5729 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5730 DONE;
5731 }
5732 if (TARGET_POWERPC64)
5733 {
5734 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5735 rtx t1 = gen_reg_rtx (DImode);
5736 rtx t2 = gen_reg_rtx (DImode);
5737 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5738 t1, t2));
5739 DONE;
5740 }
5741
5742 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5743 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5744 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5745 operands[5] = gen_reg_rtx (DFmode);
5746 }")
5747
5748 (define_insn_and_split "*floatunssidf2_internal"
5749 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5750 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5751 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5752 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5753 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5754 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))]
5755 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5756 "#"
5757 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))"
5758 [(pc)]
5759 "
5760 {
5761 rtx lowword, highword;
5762 gcc_assert (MEM_P (operands[4]));
5763 highword = adjust_address (operands[4], SImode, 0);
5764 lowword = adjust_address (operands[4], SImode, 4);
5765 if (! WORDS_BIG_ENDIAN)
5766 {
5767 rtx tmp;
5768 tmp = highword; highword = lowword; lowword = tmp;
5769 }
5770
5771 emit_move_insn (lowword, operands[1]);
5772 emit_move_insn (highword, operands[2]);
5773 emit_move_insn (operands[5], operands[4]);
5774 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5775 DONE;
5776 }"
5777 [(set_attr "length" "20")])
5778
5779 (define_expand "fix_truncdfsi2"
5780 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
5781 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5782 (clobber (match_dup 2))
5783 (clobber (match_dup 3))])]
5784 "(TARGET_POWER2 || TARGET_POWERPC)
5785 && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
5786 "
5787 {
5788 if (TARGET_E500_DOUBLE)
5789 {
5790 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
5791 DONE;
5792 }
5793 operands[2] = gen_reg_rtx (DImode);
5794 if (TARGET_PPC_GFXOPT)
5795 {
5796 rtx orig_dest = operands[0];
5797 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
5798 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
5799 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
5800 operands[2]));
5801 if (operands[0] != orig_dest)
5802 emit_move_insn (orig_dest, operands[0]);
5803 DONE;
5804 }
5805 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5806 }")
5807
5808 (define_insn_and_split "*fix_truncdfsi2_internal"
5809 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5810 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5811 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5812 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5813 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5814 "#"
5815 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))"
5816 [(pc)]
5817 "
5818 {
5819 rtx lowword;
5820 gcc_assert (MEM_P (operands[3]));
5821 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5822
5823 emit_insn (gen_fctiwz (operands[2], operands[1]));
5824 emit_move_insn (operands[3], operands[2]);
5825 emit_move_insn (operands[0], lowword);
5826 DONE;
5827 }"
5828 [(set_attr "length" "16")])
5829
5830 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
5831 [(set (match_operand:SI 0 "memory_operand" "=Z")
5832 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5833 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))]
5834 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
5835 && TARGET_PPC_GFXOPT"
5836 "#"
5837 "&& 1"
5838 [(pc)]
5839 "
5840 {
5841 emit_insn (gen_fctiwz (operands[2], operands[1]));
5842 emit_insn (gen_stfiwx (operands[0], operands[2]));
5843 DONE;
5844 }"
5845 [(set_attr "length" "16")])
5846
5847 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
5848 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5849 ; because the first makes it clear that operand 0 is not live
5850 ; before the instruction.
5851 (define_insn "fctiwz"
5852 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5853 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))]
5854 UNSPEC_FCTIWZ))]
5855 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5856 "{fcirz|fctiwz} %0,%1"
5857 [(set_attr "type" "fp")])
5858
5859 (define_insn "btruncdf2"
5860 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5861 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5862 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5863 "friz %0,%1"
5864 [(set_attr "type" "fp")])
5865
5866 (define_insn "btruncsf2"
5867 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5868 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
5869 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5870 "friz %0,%1"
5871 [(set_attr "type" "fp")])
5872
5873 (define_insn "ceildf2"
5874 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5875 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5876 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5877 "frip %0,%1"
5878 [(set_attr "type" "fp")])
5879
5880 (define_insn "ceilsf2"
5881 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5882 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
5883 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5884 "frip %0,%1"
5885 [(set_attr "type" "fp")])
5886
5887 (define_insn "floordf2"
5888 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5889 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5890 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5891 "frim %0,%1"
5892 [(set_attr "type" "fp")])
5893
5894 (define_insn "floorsf2"
5895 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5896 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
5897 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5898 "frim %0,%1"
5899 [(set_attr "type" "fp")])
5900
5901 (define_insn "rounddf2"
5902 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5903 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5904 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5905 "frin %0,%1"
5906 [(set_attr "type" "fp")])
5907
5908 (define_insn "roundsf2"
5909 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5910 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
5911 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS"
5912 "frin %0,%1"
5913 [(set_attr "type" "fp")])
5914
5915 ; An UNSPEC is used so we don't have to support SImode in FP registers.
5916 (define_insn "stfiwx"
5917 [(set (match_operand:SI 0 "memory_operand" "=Z")
5918 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")]
5919 UNSPEC_STFIWX))]
5920 "TARGET_PPC_GFXOPT"
5921 "stfiwx %1,%y0"
5922 [(set_attr "type" "fpstore")])
5923
5924 (define_expand "floatsisf2"
5925 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5926 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5927 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5928 "")
5929
5930 (define_insn "floatdidf2"
5931 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5932 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5933 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5934 "fcfid %0,%1"
5935 [(set_attr "type" "fp")])
5936
5937 (define_insn_and_split "floatsidf_ppc64"
5938 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5939 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5940 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5941 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5942 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5943 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5944 "#"
5945 "&& 1"
5946 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5947 (set (match_dup 2) (match_dup 3))
5948 (set (match_dup 4) (match_dup 2))
5949 (set (match_dup 0) (float:DF (match_dup 4)))]
5950 "")
5951
5952 (define_insn_and_split "floatunssidf_ppc64"
5953 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5954 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5955 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5956 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5957 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5958 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5959 "#"
5960 "&& 1"
5961 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5962 (set (match_dup 2) (match_dup 3))
5963 (set (match_dup 4) (match_dup 2))
5964 (set (match_dup 0) (float:DF (match_dup 4)))]
5965 "")
5966
5967 (define_insn "fix_truncdfdi2"
5968 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5969 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5970 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5971 "fctidz %0,%1"
5972 [(set_attr "type" "fp")])
5973
5974 (define_expand "floatdisf2"
5975 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5976 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5977 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5978 "
5979 {
5980 rtx val = operands[1];
5981 if (!flag_unsafe_math_optimizations)
5982 {
5983 rtx label = gen_label_rtx ();
5984 val = gen_reg_rtx (DImode);
5985 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
5986 emit_label (label);
5987 }
5988 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
5989 DONE;
5990 }")
5991
5992 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5993 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5994 ;; from double rounding.
5995 (define_insn_and_split "floatdisf2_internal1"
5996 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5997 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5998 (clobber (match_scratch:DF 2 "=f"))]
5999 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6000 "#"
6001 "&& reload_completed"
6002 [(set (match_dup 2)
6003 (float:DF (match_dup 1)))
6004 (set (match_dup 0)
6005 (float_truncate:SF (match_dup 2)))]
6006 "")
6007
6008 ;; Twiddles bits to avoid double rounding.
6009 ;; Bits that might be truncated when converting to DFmode are replaced
6010 ;; by a bit that won't be lost at that stage, but is below the SFmode
6011 ;; rounding position.
6012 (define_expand "floatdisf2_internal2"
6013 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6014 (const_int 53)))
6015 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6016 (const_int 2047)))
6017 (clobber (scratch:CC))])
6018 (set (match_dup 3) (plus:DI (match_dup 3)
6019 (const_int 1)))
6020 (set (match_dup 0) (plus:DI (match_dup 0)
6021 (const_int 2047)))
6022 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6023 (const_int 2)))
6024 (set (match_dup 0) (ior:DI (match_dup 0)
6025 (match_dup 1)))
6026 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6027 (const_int -2048)))
6028 (clobber (scratch:CC))])
6029 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6030 (label_ref (match_operand:DI 2 "" ""))
6031 (pc)))
6032 (set (match_dup 0) (match_dup 1))]
6033 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6034 "
6035 {
6036 operands[3] = gen_reg_rtx (DImode);
6037 operands[4] = gen_reg_rtx (CCUNSmode);
6038 }")
6039 \f
6040 ;; Define the DImode operations that can be done in a small number
6041 ;; of instructions. The & constraints are to prevent the register
6042 ;; allocator from allocating registers that overlap with the inputs
6043 ;; (for example, having an input in 7,8 and an output in 6,7). We
6044 ;; also allow for the output being the same as one of the inputs.
6045
6046 (define_insn "*adddi3_noppc64"
6047 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6048 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6049 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6050 "! TARGET_POWERPC64"
6051 "*
6052 {
6053 if (WORDS_BIG_ENDIAN)
6054 return (GET_CODE (operands[2])) != CONST_INT
6055 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6056 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6057 else
6058 return (GET_CODE (operands[2])) != CONST_INT
6059 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6060 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6061 }"
6062 [(set_attr "type" "two")
6063 (set_attr "length" "8")])
6064
6065 (define_insn "*subdi3_noppc64"
6066 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6067 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6068 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6069 "! TARGET_POWERPC64"
6070 "*
6071 {
6072 if (WORDS_BIG_ENDIAN)
6073 return (GET_CODE (operands[1]) != CONST_INT)
6074 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6075 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6076 else
6077 return (GET_CODE (operands[1]) != CONST_INT)
6078 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6079 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6080 }"
6081 [(set_attr "type" "two")
6082 (set_attr "length" "8")])
6083
6084 (define_insn "*negdi2_noppc64"
6085 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6086 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6087 "! TARGET_POWERPC64"
6088 "*
6089 {
6090 return (WORDS_BIG_ENDIAN)
6091 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6092 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6093 }"
6094 [(set_attr "type" "two")
6095 (set_attr "length" "8")])
6096
6097 (define_expand "mulsidi3"
6098 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6099 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6100 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6101 "! TARGET_POWERPC64"
6102 "
6103 {
6104 if (! TARGET_POWER && ! TARGET_POWERPC)
6105 {
6106 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6107 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6108 emit_insn (gen_mull_call ());
6109 if (WORDS_BIG_ENDIAN)
6110 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6111 else
6112 {
6113 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6114 gen_rtx_REG (SImode, 3));
6115 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6116 gen_rtx_REG (SImode, 4));
6117 }
6118 DONE;
6119 }
6120 else if (TARGET_POWER)
6121 {
6122 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6123 DONE;
6124 }
6125 }")
6126
6127 (define_insn "mulsidi3_mq"
6128 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6129 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6130 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6131 (clobber (match_scratch:SI 3 "=q"))]
6132 "TARGET_POWER"
6133 "mul %0,%1,%2\;mfmq %L0"
6134 [(set_attr "type" "imul")
6135 (set_attr "length" "8")])
6136
6137 (define_insn "*mulsidi3_no_mq"
6138 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6139 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6140 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6141 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6142 "*
6143 {
6144 return (WORDS_BIG_ENDIAN)
6145 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6146 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6147 }"
6148 [(set_attr "type" "imul")
6149 (set_attr "length" "8")])
6150
6151 (define_split
6152 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6153 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6154 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6155 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6156 [(set (match_dup 3)
6157 (truncate:SI
6158 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6159 (sign_extend:DI (match_dup 2)))
6160 (const_int 32))))
6161 (set (match_dup 4)
6162 (mult:SI (match_dup 1)
6163 (match_dup 2)))]
6164 "
6165 {
6166 int endian = (WORDS_BIG_ENDIAN == 0);
6167 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6168 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6169 }")
6170
6171 (define_expand "umulsidi3"
6172 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6173 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6174 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6175 "TARGET_POWERPC && ! TARGET_POWERPC64"
6176 "
6177 {
6178 if (TARGET_POWER)
6179 {
6180 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6181 DONE;
6182 }
6183 }")
6184
6185 (define_insn "umulsidi3_mq"
6186 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6187 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6188 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6189 (clobber (match_scratch:SI 3 "=q"))]
6190 "TARGET_POWERPC && TARGET_POWER"
6191 "*
6192 {
6193 return (WORDS_BIG_ENDIAN)
6194 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6195 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6196 }"
6197 [(set_attr "type" "imul")
6198 (set_attr "length" "8")])
6199
6200 (define_insn "*umulsidi3_no_mq"
6201 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6202 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6203 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6204 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6205 "*
6206 {
6207 return (WORDS_BIG_ENDIAN)
6208 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6209 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6210 }"
6211 [(set_attr "type" "imul")
6212 (set_attr "length" "8")])
6213
6214 (define_split
6215 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6216 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6217 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6218 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6219 [(set (match_dup 3)
6220 (truncate:SI
6221 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6222 (zero_extend:DI (match_dup 2)))
6223 (const_int 32))))
6224 (set (match_dup 4)
6225 (mult:SI (match_dup 1)
6226 (match_dup 2)))]
6227 "
6228 {
6229 int endian = (WORDS_BIG_ENDIAN == 0);
6230 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6231 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6232 }")
6233
6234 (define_expand "smulsi3_highpart"
6235 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6236 (truncate:SI
6237 (lshiftrt:DI (mult:DI (sign_extend:DI
6238 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6239 (sign_extend:DI
6240 (match_operand:SI 2 "gpc_reg_operand" "r")))
6241 (const_int 32))))]
6242 ""
6243 "
6244 {
6245 if (! TARGET_POWER && ! TARGET_POWERPC)
6246 {
6247 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6248 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6249 emit_insn (gen_mulh_call ());
6250 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6251 DONE;
6252 }
6253 else if (TARGET_POWER)
6254 {
6255 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6256 DONE;
6257 }
6258 }")
6259
6260 (define_insn "smulsi3_highpart_mq"
6261 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6262 (truncate:SI
6263 (lshiftrt:DI (mult:DI (sign_extend:DI
6264 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6265 (sign_extend:DI
6266 (match_operand:SI 2 "gpc_reg_operand" "r")))
6267 (const_int 32))))
6268 (clobber (match_scratch:SI 3 "=q"))]
6269 "TARGET_POWER"
6270 "mul %0,%1,%2"
6271 [(set_attr "type" "imul")])
6272
6273 (define_insn "*smulsi3_highpart_no_mq"
6274 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6275 (truncate:SI
6276 (lshiftrt:DI (mult:DI (sign_extend:DI
6277 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6278 (sign_extend:DI
6279 (match_operand:SI 2 "gpc_reg_operand" "r")))
6280 (const_int 32))))]
6281 "TARGET_POWERPC && ! TARGET_POWER"
6282 "mulhw %0,%1,%2"
6283 [(set_attr "type" "imul")])
6284
6285 (define_expand "umulsi3_highpart"
6286 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6287 (truncate:SI
6288 (lshiftrt:DI (mult:DI (zero_extend:DI
6289 (match_operand:SI 1 "gpc_reg_operand" ""))
6290 (zero_extend:DI
6291 (match_operand:SI 2 "gpc_reg_operand" "")))
6292 (const_int 32))))]
6293 "TARGET_POWERPC"
6294 "
6295 {
6296 if (TARGET_POWER)
6297 {
6298 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6299 DONE;
6300 }
6301 }")
6302
6303 (define_insn "umulsi3_highpart_mq"
6304 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6305 (truncate:SI
6306 (lshiftrt:DI (mult:DI (zero_extend:DI
6307 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6308 (zero_extend:DI
6309 (match_operand:SI 2 "gpc_reg_operand" "r")))
6310 (const_int 32))))
6311 (clobber (match_scratch:SI 3 "=q"))]
6312 "TARGET_POWERPC && TARGET_POWER"
6313 "mulhwu %0,%1,%2"
6314 [(set_attr "type" "imul")])
6315
6316 (define_insn "*umulsi3_highpart_no_mq"
6317 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6318 (truncate:SI
6319 (lshiftrt:DI (mult:DI (zero_extend:DI
6320 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6321 (zero_extend:DI
6322 (match_operand:SI 2 "gpc_reg_operand" "r")))
6323 (const_int 32))))]
6324 "TARGET_POWERPC && ! TARGET_POWER"
6325 "mulhwu %0,%1,%2"
6326 [(set_attr "type" "imul")])
6327
6328 ;; If operands 0 and 2 are in the same register, we have a problem. But
6329 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6330 ;; why we have the strange constraints below.
6331 (define_insn "ashldi3_power"
6332 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6333 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6334 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6335 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6336 "TARGET_POWER"
6337 "@
6338 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6339 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6340 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6341 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6342 [(set_attr "length" "8")])
6343
6344 (define_insn "lshrdi3_power"
6345 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6346 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6347 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6348 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6349 "TARGET_POWER"
6350 "@
6351 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6352 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6353 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6354 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6355 [(set_attr "length" "8")])
6356
6357 ;; Shift by a variable amount is too complex to be worth open-coding. We
6358 ;; just handle shifts by constants.
6359 (define_insn "ashrdi3_power"
6360 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6361 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6362 (match_operand:SI 2 "const_int_operand" "M,i")))
6363 (clobber (match_scratch:SI 3 "=X,q"))]
6364 "TARGET_POWER"
6365 "@
6366 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6367 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6368 [(set_attr "length" "8")])
6369
6370 (define_insn "ashrdi3_no_power"
6371 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6372 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6373 (match_operand:SI 2 "const_int_operand" "M,i")))]
6374 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
6375 "@
6376 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6377 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6378 [(set_attr "type" "two,three")
6379 (set_attr "length" "8,12")])
6380
6381 (define_insn "*ashrdisi3_noppc64"
6382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6383 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6384 (const_int 32)) 4))]
6385 "TARGET_32BIT && !TARGET_POWERPC64"
6386 "*
6387 {
6388 if (REGNO (operands[0]) == REGNO (operands[1]))
6389 return \"\";
6390 else
6391 return \"mr %0,%1\";
6392 }"
6393 [(set_attr "length" "4")])
6394
6395 \f
6396 ;; PowerPC64 DImode operations.
6397
6398 (define_insn_and_split "absdi2"
6399 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6400 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6401 (clobber (match_scratch:DI 2 "=&r,&r"))]
6402 "TARGET_POWERPC64"
6403 "#"
6404 "&& reload_completed"
6405 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6406 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6407 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6408 "")
6409
6410 (define_insn_and_split "*nabsdi2"
6411 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6412 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6413 (clobber (match_scratch:DI 2 "=&r,&r"))]
6414 "TARGET_POWERPC64"
6415 "#"
6416 "&& reload_completed"
6417 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6418 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6419 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6420 "")
6421
6422 (define_insn "muldi3"
6423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6424 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6425 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6426 "TARGET_POWERPC64"
6427 "@
6428 mulld %0,%1,%2
6429 mulli %0,%1,%2"
6430 [(set (attr "type")
6431 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6432 (const_string "imul3")
6433 (match_operand:SI 2 "short_cint_operand" "")
6434 (const_string "imul2")]
6435 (const_string "lmul")))])
6436
6437 (define_insn "*muldi3_internal1"
6438 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6439 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6440 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6441 (const_int 0)))
6442 (clobber (match_scratch:DI 3 "=r,r"))]
6443 "TARGET_POWERPC64"
6444 "@
6445 mulld. %3,%1,%2
6446 #"
6447 [(set_attr "type" "lmul_compare")
6448 (set_attr "length" "4,8")])
6449
6450 (define_split
6451 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6452 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6453 (match_operand:DI 2 "gpc_reg_operand" ""))
6454 (const_int 0)))
6455 (clobber (match_scratch:DI 3 ""))]
6456 "TARGET_POWERPC64 && reload_completed"
6457 [(set (match_dup 3)
6458 (mult:DI (match_dup 1) (match_dup 2)))
6459 (set (match_dup 0)
6460 (compare:CC (match_dup 3)
6461 (const_int 0)))]
6462 "")
6463
6464 (define_insn "*muldi3_internal2"
6465 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6466 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6467 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6468 (const_int 0)))
6469 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6470 (mult:DI (match_dup 1) (match_dup 2)))]
6471 "TARGET_POWERPC64"
6472 "@
6473 mulld. %0,%1,%2
6474 #"
6475 [(set_attr "type" "lmul_compare")
6476 (set_attr "length" "4,8")])
6477
6478 (define_split
6479 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6480 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6481 (match_operand:DI 2 "gpc_reg_operand" ""))
6482 (const_int 0)))
6483 (set (match_operand:DI 0 "gpc_reg_operand" "")
6484 (mult:DI (match_dup 1) (match_dup 2)))]
6485 "TARGET_POWERPC64 && reload_completed"
6486 [(set (match_dup 0)
6487 (mult:DI (match_dup 1) (match_dup 2)))
6488 (set (match_dup 3)
6489 (compare:CC (match_dup 0)
6490 (const_int 0)))]
6491 "")
6492
6493 (define_insn "smuldi3_highpart"
6494 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6495 (truncate:DI
6496 (lshiftrt:TI (mult:TI (sign_extend:TI
6497 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6498 (sign_extend:TI
6499 (match_operand:DI 2 "gpc_reg_operand" "r")))
6500 (const_int 64))))]
6501 "TARGET_POWERPC64"
6502 "mulhd %0,%1,%2"
6503 [(set_attr "type" "lmul")])
6504
6505 (define_insn "umuldi3_highpart"
6506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6507 (truncate:DI
6508 (lshiftrt:TI (mult:TI (zero_extend:TI
6509 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6510 (zero_extend:TI
6511 (match_operand:DI 2 "gpc_reg_operand" "r")))
6512 (const_int 64))))]
6513 "TARGET_POWERPC64"
6514 "mulhdu %0,%1,%2"
6515 [(set_attr "type" "lmul")])
6516
6517 (define_insn "rotldi3"
6518 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6519 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6520 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6521 "TARGET_POWERPC64"
6522 "rld%I2cl %0,%1,%H2,0")
6523
6524 (define_insn "*rotldi3_internal2"
6525 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6526 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6527 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6528 (const_int 0)))
6529 (clobber (match_scratch:DI 3 "=r,r"))]
6530 "TARGET_64BIT"
6531 "@
6532 rld%I2cl. %3,%1,%H2,0
6533 #"
6534 [(set_attr "type" "delayed_compare")
6535 (set_attr "length" "4,8")])
6536
6537 (define_split
6538 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6539 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6540 (match_operand:DI 2 "reg_or_cint_operand" ""))
6541 (const_int 0)))
6542 (clobber (match_scratch:DI 3 ""))]
6543 "TARGET_POWERPC64 && reload_completed"
6544 [(set (match_dup 3)
6545 (rotate:DI (match_dup 1) (match_dup 2)))
6546 (set (match_dup 0)
6547 (compare:CC (match_dup 3)
6548 (const_int 0)))]
6549 "")
6550
6551 (define_insn "*rotldi3_internal3"
6552 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6553 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6554 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6555 (const_int 0)))
6556 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6557 (rotate:DI (match_dup 1) (match_dup 2)))]
6558 "TARGET_64BIT"
6559 "@
6560 rld%I2cl. %0,%1,%H2,0
6561 #"
6562 [(set_attr "type" "delayed_compare")
6563 (set_attr "length" "4,8")])
6564
6565 (define_split
6566 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6567 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6568 (match_operand:DI 2 "reg_or_cint_operand" ""))
6569 (const_int 0)))
6570 (set (match_operand:DI 0 "gpc_reg_operand" "")
6571 (rotate:DI (match_dup 1) (match_dup 2)))]
6572 "TARGET_POWERPC64 && reload_completed"
6573 [(set (match_dup 0)
6574 (rotate:DI (match_dup 1) (match_dup 2)))
6575 (set (match_dup 3)
6576 (compare:CC (match_dup 0)
6577 (const_int 0)))]
6578 "")
6579
6580 (define_insn "*rotldi3_internal4"
6581 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6582 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6583 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6584 (match_operand:DI 3 "mask64_operand" "n")))]
6585 "TARGET_POWERPC64"
6586 "rld%I2c%B3 %0,%1,%H2,%S3")
6587
6588 (define_insn "*rotldi3_internal5"
6589 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6590 (compare:CC (and:DI
6591 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6592 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6593 (match_operand:DI 3 "mask64_operand" "n,n"))
6594 (const_int 0)))
6595 (clobber (match_scratch:DI 4 "=r,r"))]
6596 "TARGET_64BIT"
6597 "@
6598 rld%I2c%B3. %4,%1,%H2,%S3
6599 #"
6600 [(set_attr "type" "delayed_compare")
6601 (set_attr "length" "4,8")])
6602
6603 (define_split
6604 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6605 (compare:CC (and:DI
6606 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6607 (match_operand:DI 2 "reg_or_cint_operand" ""))
6608 (match_operand:DI 3 "mask64_operand" ""))
6609 (const_int 0)))
6610 (clobber (match_scratch:DI 4 ""))]
6611 "TARGET_POWERPC64 && reload_completed"
6612 [(set (match_dup 4)
6613 (and:DI (rotate:DI (match_dup 1)
6614 (match_dup 2))
6615 (match_dup 3)))
6616 (set (match_dup 0)
6617 (compare:CC (match_dup 4)
6618 (const_int 0)))]
6619 "")
6620
6621 (define_insn "*rotldi3_internal6"
6622 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6623 (compare:CC (and:DI
6624 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6625 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6626 (match_operand:DI 3 "mask64_operand" "n,n"))
6627 (const_int 0)))
6628 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6629 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6630 "TARGET_64BIT"
6631 "@
6632 rld%I2c%B3. %0,%1,%H2,%S3
6633 #"
6634 [(set_attr "type" "delayed_compare")
6635 (set_attr "length" "4,8")])
6636
6637 (define_split
6638 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6639 (compare:CC (and:DI
6640 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6641 (match_operand:DI 2 "reg_or_cint_operand" ""))
6642 (match_operand:DI 3 "mask64_operand" ""))
6643 (const_int 0)))
6644 (set (match_operand:DI 0 "gpc_reg_operand" "")
6645 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6646 "TARGET_POWERPC64 && reload_completed"
6647 [(set (match_dup 0)
6648 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6649 (set (match_dup 4)
6650 (compare:CC (match_dup 0)
6651 (const_int 0)))]
6652 "")
6653
6654 (define_insn "*rotldi3_internal7"
6655 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6656 (zero_extend:DI
6657 (subreg:QI
6658 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6659 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6660 "TARGET_POWERPC64"
6661 "rld%I2cl %0,%1,%H2,56")
6662
6663 (define_insn "*rotldi3_internal8"
6664 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6665 (compare:CC (zero_extend:DI
6666 (subreg:QI
6667 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6668 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6669 (const_int 0)))
6670 (clobber (match_scratch:DI 3 "=r,r"))]
6671 "TARGET_64BIT"
6672 "@
6673 rld%I2cl. %3,%1,%H2,56
6674 #"
6675 [(set_attr "type" "delayed_compare")
6676 (set_attr "length" "4,8")])
6677
6678 (define_split
6679 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6680 (compare:CC (zero_extend:DI
6681 (subreg:QI
6682 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6683 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6684 (const_int 0)))
6685 (clobber (match_scratch:DI 3 ""))]
6686 "TARGET_POWERPC64 && reload_completed"
6687 [(set (match_dup 3)
6688 (zero_extend:DI (subreg:QI
6689 (rotate:DI (match_dup 1)
6690 (match_dup 2)) 0)))
6691 (set (match_dup 0)
6692 (compare:CC (match_dup 3)
6693 (const_int 0)))]
6694 "")
6695
6696 (define_insn "*rotldi3_internal9"
6697 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6698 (compare:CC (zero_extend:DI
6699 (subreg:QI
6700 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6701 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6702 (const_int 0)))
6703 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6704 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6705 "TARGET_64BIT"
6706 "@
6707 rld%I2cl. %0,%1,%H2,56
6708 #"
6709 [(set_attr "type" "delayed_compare")
6710 (set_attr "length" "4,8")])
6711
6712 (define_split
6713 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6714 (compare:CC (zero_extend:DI
6715 (subreg:QI
6716 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6717 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6718 (const_int 0)))
6719 (set (match_operand:DI 0 "gpc_reg_operand" "")
6720 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6721 "TARGET_POWERPC64 && reload_completed"
6722 [(set (match_dup 0)
6723 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6724 (set (match_dup 3)
6725 (compare:CC (match_dup 0)
6726 (const_int 0)))]
6727 "")
6728
6729 (define_insn "*rotldi3_internal10"
6730 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6731 (zero_extend:DI
6732 (subreg:HI
6733 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6734 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6735 "TARGET_POWERPC64"
6736 "rld%I2cl %0,%1,%H2,48")
6737
6738 (define_insn "*rotldi3_internal11"
6739 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6740 (compare:CC (zero_extend:DI
6741 (subreg:HI
6742 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6743 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6744 (const_int 0)))
6745 (clobber (match_scratch:DI 3 "=r,r"))]
6746 "TARGET_64BIT"
6747 "@
6748 rld%I2cl. %3,%1,%H2,48
6749 #"
6750 [(set_attr "type" "delayed_compare")
6751 (set_attr "length" "4,8")])
6752
6753 (define_split
6754 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6755 (compare:CC (zero_extend:DI
6756 (subreg:HI
6757 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6758 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6759 (const_int 0)))
6760 (clobber (match_scratch:DI 3 ""))]
6761 "TARGET_POWERPC64 && reload_completed"
6762 [(set (match_dup 3)
6763 (zero_extend:DI (subreg:HI
6764 (rotate:DI (match_dup 1)
6765 (match_dup 2)) 0)))
6766 (set (match_dup 0)
6767 (compare:CC (match_dup 3)
6768 (const_int 0)))]
6769 "")
6770
6771 (define_insn "*rotldi3_internal12"
6772 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6773 (compare:CC (zero_extend:DI
6774 (subreg:HI
6775 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6776 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6777 (const_int 0)))
6778 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6779 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6780 "TARGET_64BIT"
6781 "@
6782 rld%I2cl. %0,%1,%H2,48
6783 #"
6784 [(set_attr "type" "delayed_compare")
6785 (set_attr "length" "4,8")])
6786
6787 (define_split
6788 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6789 (compare:CC (zero_extend:DI
6790 (subreg:HI
6791 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6792 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6793 (const_int 0)))
6794 (set (match_operand:DI 0 "gpc_reg_operand" "")
6795 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6796 "TARGET_POWERPC64 && reload_completed"
6797 [(set (match_dup 0)
6798 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6799 (set (match_dup 3)
6800 (compare:CC (match_dup 0)
6801 (const_int 0)))]
6802 "")
6803
6804 (define_insn "*rotldi3_internal13"
6805 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6806 (zero_extend:DI
6807 (subreg:SI
6808 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6809 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6810 "TARGET_POWERPC64"
6811 "rld%I2cl %0,%1,%H2,32")
6812
6813 (define_insn "*rotldi3_internal14"
6814 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6815 (compare:CC (zero_extend:DI
6816 (subreg:SI
6817 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6818 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6819 (const_int 0)))
6820 (clobber (match_scratch:DI 3 "=r,r"))]
6821 "TARGET_64BIT"
6822 "@
6823 rld%I2cl. %3,%1,%H2,32
6824 #"
6825 [(set_attr "type" "delayed_compare")
6826 (set_attr "length" "4,8")])
6827
6828 (define_split
6829 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6830 (compare:CC (zero_extend:DI
6831 (subreg:SI
6832 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6833 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6834 (const_int 0)))
6835 (clobber (match_scratch:DI 3 ""))]
6836 "TARGET_POWERPC64 && reload_completed"
6837 [(set (match_dup 3)
6838 (zero_extend:DI (subreg:SI
6839 (rotate:DI (match_dup 1)
6840 (match_dup 2)) 0)))
6841 (set (match_dup 0)
6842 (compare:CC (match_dup 3)
6843 (const_int 0)))]
6844 "")
6845
6846 (define_insn "*rotldi3_internal15"
6847 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6848 (compare:CC (zero_extend:DI
6849 (subreg:SI
6850 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6851 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6852 (const_int 0)))
6853 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6854 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6855 "TARGET_64BIT"
6856 "@
6857 rld%I2cl. %0,%1,%H2,32
6858 #"
6859 [(set_attr "type" "delayed_compare")
6860 (set_attr "length" "4,8")])
6861
6862 (define_split
6863 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6864 (compare:CC (zero_extend:DI
6865 (subreg:SI
6866 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6867 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6868 (const_int 0)))
6869 (set (match_operand:DI 0 "gpc_reg_operand" "")
6870 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6871 "TARGET_POWERPC64 && reload_completed"
6872 [(set (match_dup 0)
6873 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6874 (set (match_dup 3)
6875 (compare:CC (match_dup 0)
6876 (const_int 0)))]
6877 "")
6878
6879 (define_expand "ashldi3"
6880 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6881 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6882 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6883 "TARGET_POWERPC64 || TARGET_POWER"
6884 "
6885 {
6886 if (TARGET_POWERPC64)
6887 ;
6888 else if (TARGET_POWER)
6889 {
6890 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6891 DONE;
6892 }
6893 else
6894 FAIL;
6895 }")
6896
6897 (define_insn "*ashldi3_internal1"
6898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6899 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6900 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6901 "TARGET_POWERPC64"
6902 "sld%I2 %0,%1,%H2")
6903
6904 (define_insn "*ashldi3_internal2"
6905 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6906 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6907 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6908 (const_int 0)))
6909 (clobber (match_scratch:DI 3 "=r,r"))]
6910 "TARGET_64BIT"
6911 "@
6912 sld%I2. %3,%1,%H2
6913 #"
6914 [(set_attr "type" "delayed_compare")
6915 (set_attr "length" "4,8")])
6916
6917 (define_split
6918 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6919 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6920 (match_operand:SI 2 "reg_or_cint_operand" ""))
6921 (const_int 0)))
6922 (clobber (match_scratch:DI 3 ""))]
6923 "TARGET_POWERPC64 && reload_completed"
6924 [(set (match_dup 3)
6925 (ashift:DI (match_dup 1) (match_dup 2)))
6926 (set (match_dup 0)
6927 (compare:CC (match_dup 3)
6928 (const_int 0)))]
6929 "")
6930
6931 (define_insn "*ashldi3_internal3"
6932 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6933 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6934 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6935 (const_int 0)))
6936 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6937 (ashift:DI (match_dup 1) (match_dup 2)))]
6938 "TARGET_64BIT"
6939 "@
6940 sld%I2. %0,%1,%H2
6941 #"
6942 [(set_attr "type" "delayed_compare")
6943 (set_attr "length" "4,8")])
6944
6945 (define_split
6946 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6947 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6948 (match_operand:SI 2 "reg_or_cint_operand" ""))
6949 (const_int 0)))
6950 (set (match_operand:DI 0 "gpc_reg_operand" "")
6951 (ashift:DI (match_dup 1) (match_dup 2)))]
6952 "TARGET_POWERPC64 && reload_completed"
6953 [(set (match_dup 0)
6954 (ashift:DI (match_dup 1) (match_dup 2)))
6955 (set (match_dup 3)
6956 (compare:CC (match_dup 0)
6957 (const_int 0)))]
6958 "")
6959
6960 (define_insn "*ashldi3_internal4"
6961 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6962 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6963 (match_operand:SI 2 "const_int_operand" "i"))
6964 (match_operand:DI 3 "const_int_operand" "n")))]
6965 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6966 "rldic %0,%1,%H2,%W3")
6967
6968 (define_insn "ashldi3_internal5"
6969 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6970 (compare:CC
6971 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6972 (match_operand:SI 2 "const_int_operand" "i,i"))
6973 (match_operand:DI 3 "const_int_operand" "n,n"))
6974 (const_int 0)))
6975 (clobber (match_scratch:DI 4 "=r,r"))]
6976 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
6977 "@
6978 rldic. %4,%1,%H2,%W3
6979 #"
6980 [(set_attr "type" "compare")
6981 (set_attr "length" "4,8")])
6982
6983 (define_split
6984 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6985 (compare:CC
6986 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6987 (match_operand:SI 2 "const_int_operand" ""))
6988 (match_operand:DI 3 "const_int_operand" ""))
6989 (const_int 0)))
6990 (clobber (match_scratch:DI 4 ""))]
6991 "TARGET_POWERPC64 && reload_completed
6992 && includes_rldic_lshift_p (operands[2], operands[3])"
6993 [(set (match_dup 4)
6994 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6995 (match_dup 3)))
6996 (set (match_dup 0)
6997 (compare:CC (match_dup 4)
6998 (const_int 0)))]
6999 "")
7000
7001 (define_insn "*ashldi3_internal6"
7002 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7003 (compare:CC
7004 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7005 (match_operand:SI 2 "const_int_operand" "i,i"))
7006 (match_operand:DI 3 "const_int_operand" "n,n"))
7007 (const_int 0)))
7008 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7009 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7010 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7011 "@
7012 rldic. %0,%1,%H2,%W3
7013 #"
7014 [(set_attr "type" "compare")
7015 (set_attr "length" "4,8")])
7016
7017 (define_split
7018 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7019 (compare:CC
7020 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7021 (match_operand:SI 2 "const_int_operand" ""))
7022 (match_operand:DI 3 "const_int_operand" ""))
7023 (const_int 0)))
7024 (set (match_operand:DI 0 "gpc_reg_operand" "")
7025 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7026 "TARGET_POWERPC64 && reload_completed
7027 && includes_rldic_lshift_p (operands[2], operands[3])"
7028 [(set (match_dup 0)
7029 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7030 (match_dup 3)))
7031 (set (match_dup 4)
7032 (compare:CC (match_dup 0)
7033 (const_int 0)))]
7034 "")
7035
7036 (define_insn "*ashldi3_internal7"
7037 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7038 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7039 (match_operand:SI 2 "const_int_operand" "i"))
7040 (match_operand:DI 3 "mask64_operand" "n")))]
7041 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7042 "rldicr %0,%1,%H2,%S3")
7043
7044 (define_insn "ashldi3_internal8"
7045 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7046 (compare:CC
7047 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7048 (match_operand:SI 2 "const_int_operand" "i,i"))
7049 (match_operand:DI 3 "mask64_operand" "n,n"))
7050 (const_int 0)))
7051 (clobber (match_scratch:DI 4 "=r,r"))]
7052 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7053 "@
7054 rldicr. %4,%1,%H2,%S3
7055 #"
7056 [(set_attr "type" "compare")
7057 (set_attr "length" "4,8")])
7058
7059 (define_split
7060 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7061 (compare:CC
7062 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7063 (match_operand:SI 2 "const_int_operand" ""))
7064 (match_operand:DI 3 "mask64_operand" ""))
7065 (const_int 0)))
7066 (clobber (match_scratch:DI 4 ""))]
7067 "TARGET_POWERPC64 && reload_completed
7068 && includes_rldicr_lshift_p (operands[2], operands[3])"
7069 [(set (match_dup 4)
7070 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7071 (match_dup 3)))
7072 (set (match_dup 0)
7073 (compare:CC (match_dup 4)
7074 (const_int 0)))]
7075 "")
7076
7077 (define_insn "*ashldi3_internal9"
7078 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7079 (compare:CC
7080 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7081 (match_operand:SI 2 "const_int_operand" "i,i"))
7082 (match_operand:DI 3 "mask64_operand" "n,n"))
7083 (const_int 0)))
7084 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7085 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7086 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7087 "@
7088 rldicr. %0,%1,%H2,%S3
7089 #"
7090 [(set_attr "type" "compare")
7091 (set_attr "length" "4,8")])
7092
7093 (define_split
7094 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7095 (compare:CC
7096 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7097 (match_operand:SI 2 "const_int_operand" ""))
7098 (match_operand:DI 3 "mask64_operand" ""))
7099 (const_int 0)))
7100 (set (match_operand:DI 0 "gpc_reg_operand" "")
7101 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7102 "TARGET_POWERPC64 && reload_completed
7103 && includes_rldicr_lshift_p (operands[2], operands[3])"
7104 [(set (match_dup 0)
7105 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7106 (match_dup 3)))
7107 (set (match_dup 4)
7108 (compare:CC (match_dup 0)
7109 (const_int 0)))]
7110 "")
7111
7112 (define_expand "lshrdi3"
7113 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7114 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7115 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7116 "TARGET_POWERPC64 || TARGET_POWER"
7117 "
7118 {
7119 if (TARGET_POWERPC64)
7120 ;
7121 else if (TARGET_POWER)
7122 {
7123 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7124 DONE;
7125 }
7126 else
7127 FAIL;
7128 }")
7129
7130 (define_insn "*lshrdi3_internal1"
7131 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7132 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7133 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7134 "TARGET_POWERPC64"
7135 "srd%I2 %0,%1,%H2")
7136
7137 (define_insn "*lshrdi3_internal2"
7138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7139 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7140 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7141 (const_int 0)))
7142 (clobber (match_scratch:DI 3 "=r,r"))]
7143 "TARGET_64BIT "
7144 "@
7145 srd%I2. %3,%1,%H2
7146 #"
7147 [(set_attr "type" "delayed_compare")
7148 (set_attr "length" "4,8")])
7149
7150 (define_split
7151 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7152 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7153 (match_operand:SI 2 "reg_or_cint_operand" ""))
7154 (const_int 0)))
7155 (clobber (match_scratch:DI 3 ""))]
7156 "TARGET_POWERPC64 && reload_completed"
7157 [(set (match_dup 3)
7158 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7159 (set (match_dup 0)
7160 (compare:CC (match_dup 3)
7161 (const_int 0)))]
7162 "")
7163
7164 (define_insn "*lshrdi3_internal3"
7165 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7166 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7167 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7168 (const_int 0)))
7169 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7170 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7171 "TARGET_64BIT"
7172 "@
7173 srd%I2. %0,%1,%H2
7174 #"
7175 [(set_attr "type" "delayed_compare")
7176 (set_attr "length" "4,8")])
7177
7178 (define_split
7179 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7180 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7181 (match_operand:SI 2 "reg_or_cint_operand" ""))
7182 (const_int 0)))
7183 (set (match_operand:DI 0 "gpc_reg_operand" "")
7184 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7185 "TARGET_POWERPC64 && reload_completed"
7186 [(set (match_dup 0)
7187 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7188 (set (match_dup 3)
7189 (compare:CC (match_dup 0)
7190 (const_int 0)))]
7191 "")
7192
7193 (define_expand "ashrdi3"
7194 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7195 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7196 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7197 "WORDS_BIG_ENDIAN"
7198 "
7199 {
7200 if (TARGET_POWERPC64)
7201 ;
7202 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7203 {
7204 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7205 DONE;
7206 }
7207 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7208 && WORDS_BIG_ENDIAN)
7209 {
7210 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7211 DONE;
7212 }
7213 else
7214 FAIL;
7215 }")
7216
7217 (define_insn "*ashrdi3_internal1"
7218 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7219 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7220 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7221 "TARGET_POWERPC64"
7222 "srad%I2 %0,%1,%H2")
7223
7224 (define_insn "*ashrdi3_internal2"
7225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7226 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7227 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7228 (const_int 0)))
7229 (clobber (match_scratch:DI 3 "=r,r"))]
7230 "TARGET_64BIT"
7231 "@
7232 srad%I2. %3,%1,%H2
7233 #"
7234 [(set_attr "type" "delayed_compare")
7235 (set_attr "length" "4,8")])
7236
7237 (define_split
7238 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7239 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7240 (match_operand:SI 2 "reg_or_cint_operand" ""))
7241 (const_int 0)))
7242 (clobber (match_scratch:DI 3 ""))]
7243 "TARGET_POWERPC64 && reload_completed"
7244 [(set (match_dup 3)
7245 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7246 (set (match_dup 0)
7247 (compare:CC (match_dup 3)
7248 (const_int 0)))]
7249 "")
7250
7251 (define_insn "*ashrdi3_internal3"
7252 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7253 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7254 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7255 (const_int 0)))
7256 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7257 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7258 "TARGET_64BIT"
7259 "@
7260 srad%I2. %0,%1,%H2
7261 #"
7262 [(set_attr "type" "delayed_compare")
7263 (set_attr "length" "4,8")])
7264
7265 (define_split
7266 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7267 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7268 (match_operand:SI 2 "reg_or_cint_operand" ""))
7269 (const_int 0)))
7270 (set (match_operand:DI 0 "gpc_reg_operand" "")
7271 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7272 "TARGET_POWERPC64 && reload_completed"
7273 [(set (match_dup 0)
7274 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7275 (set (match_dup 3)
7276 (compare:CC (match_dup 0)
7277 (const_int 0)))]
7278 "")
7279
7280 (define_insn "anddi3"
7281 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7282 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7283 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7284 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7285 "TARGET_POWERPC64"
7286 "@
7287 and %0,%1,%2
7288 rldic%B2 %0,%1,0,%S2
7289 rlwinm %0,%1,0,%m2,%M2
7290 andi. %0,%1,%b2
7291 andis. %0,%1,%u2
7292 #"
7293 [(set_attr "type" "*,*,*,compare,compare,*")
7294 (set_attr "length" "4,4,4,4,4,8")])
7295
7296 (define_split
7297 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7298 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7299 (match_operand:DI 2 "mask64_2_operand" "")))
7300 (clobber (match_scratch:CC 3 ""))]
7301 "TARGET_POWERPC64
7302 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7303 && !mask_operand (operands[2], DImode)
7304 && !mask64_operand (operands[2], DImode)"
7305 [(set (match_dup 0)
7306 (and:DI (rotate:DI (match_dup 1)
7307 (match_dup 4))
7308 (match_dup 5)))
7309 (set (match_dup 0)
7310 (and:DI (rotate:DI (match_dup 0)
7311 (match_dup 6))
7312 (match_dup 7)))]
7313 {
7314 build_mask64_2_operands (operands[2], &operands[4]);
7315 })
7316
7317 (define_insn "*anddi3_internal2"
7318 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7319 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7320 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7321 (const_int 0)))
7322 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7323 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7324 "TARGET_64BIT"
7325 "@
7326 and. %3,%1,%2
7327 rldic%B2. %3,%1,0,%S2
7328 rlwinm. %3,%1,0,%m2,%M2
7329 andi. %3,%1,%b2
7330 andis. %3,%1,%u2
7331 #
7332 #
7333 #
7334 #
7335 #
7336 #
7337 #"
7338 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7339 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7340
7341 (define_split
7342 [(set (match_operand:CC 0 "cc_reg_operand" "")
7343 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7344 (match_operand:DI 2 "mask64_2_operand" ""))
7345 (const_int 0)))
7346 (clobber (match_scratch:DI 3 ""))
7347 (clobber (match_scratch:CC 4 ""))]
7348 "TARGET_64BIT && reload_completed
7349 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7350 && !mask_operand (operands[2], DImode)
7351 && !mask64_operand (operands[2], DImode)"
7352 [(set (match_dup 3)
7353 (and:DI (rotate:DI (match_dup 1)
7354 (match_dup 5))
7355 (match_dup 6)))
7356 (parallel [(set (match_dup 0)
7357 (compare:CC (and:DI (rotate:DI (match_dup 3)
7358 (match_dup 7))
7359 (match_dup 8))
7360 (const_int 0)))
7361 (clobber (match_dup 3))])]
7362 "
7363 {
7364 build_mask64_2_operands (operands[2], &operands[5]);
7365 }")
7366
7367 (define_insn "*anddi3_internal3"
7368 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7369 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7370 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7371 (const_int 0)))
7372 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7373 (and:DI (match_dup 1) (match_dup 2)))
7374 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7375 "TARGET_64BIT"
7376 "@
7377 and. %0,%1,%2
7378 rldic%B2. %0,%1,0,%S2
7379 rlwinm. %0,%1,0,%m2,%M2
7380 andi. %0,%1,%b2
7381 andis. %0,%1,%u2
7382 #
7383 #
7384 #
7385 #
7386 #
7387 #
7388 #"
7389 [(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
7390 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7391
7392 (define_split
7393 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7394 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7395 (match_operand:DI 2 "and64_2_operand" ""))
7396 (const_int 0)))
7397 (set (match_operand:DI 0 "gpc_reg_operand" "")
7398 (and:DI (match_dup 1) (match_dup 2)))
7399 (clobber (match_scratch:CC 4 ""))]
7400 "TARGET_64BIT && reload_completed"
7401 [(parallel [(set (match_dup 0)
7402 (and:DI (match_dup 1) (match_dup 2)))
7403 (clobber (match_dup 4))])
7404 (set (match_dup 3)
7405 (compare:CC (match_dup 0)
7406 (const_int 0)))]
7407 "")
7408
7409 (define_split
7410 [(set (match_operand:CC 3 "cc_reg_operand" "")
7411 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7412 (match_operand:DI 2 "mask64_2_operand" ""))
7413 (const_int 0)))
7414 (set (match_operand:DI 0 "gpc_reg_operand" "")
7415 (and:DI (match_dup 1) (match_dup 2)))
7416 (clobber (match_scratch:CC 4 ""))]
7417 "TARGET_64BIT && reload_completed
7418 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7419 && !mask_operand (operands[2], DImode)
7420 && !mask64_operand (operands[2], DImode)"
7421 [(set (match_dup 0)
7422 (and:DI (rotate:DI (match_dup 1)
7423 (match_dup 5))
7424 (match_dup 6)))
7425 (parallel [(set (match_dup 3)
7426 (compare:CC (and:DI (rotate:DI (match_dup 0)
7427 (match_dup 7))
7428 (match_dup 8))
7429 (const_int 0)))
7430 (set (match_dup 0)
7431 (and:DI (rotate:DI (match_dup 0)
7432 (match_dup 7))
7433 (match_dup 8)))])]
7434 "
7435 {
7436 build_mask64_2_operands (operands[2], &operands[5]);
7437 }")
7438
7439 (define_expand "iordi3"
7440 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7441 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7442 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7443 "TARGET_POWERPC64"
7444 "
7445 {
7446 if (non_logical_cint_operand (operands[2], DImode))
7447 {
7448 HOST_WIDE_INT value;
7449 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7450 ? operands[0] : gen_reg_rtx (DImode));
7451
7452 if (GET_CODE (operands[2]) == CONST_INT)
7453 {
7454 value = INTVAL (operands[2]);
7455 emit_insn (gen_iordi3 (tmp, operands[1],
7456 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7457 }
7458 else
7459 {
7460 value = CONST_DOUBLE_LOW (operands[2]);
7461 emit_insn (gen_iordi3 (tmp, operands[1],
7462 immed_double_const (value
7463 & (~ (HOST_WIDE_INT) 0xffff),
7464 0, DImode)));
7465 }
7466
7467 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7468 DONE;
7469 }
7470 }")
7471
7472 (define_expand "xordi3"
7473 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7474 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7475 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7476 "TARGET_POWERPC64"
7477 "
7478 {
7479 if (non_logical_cint_operand (operands[2], DImode))
7480 {
7481 HOST_WIDE_INT value;
7482 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7483 ? operands[0] : gen_reg_rtx (DImode));
7484
7485 if (GET_CODE (operands[2]) == CONST_INT)
7486 {
7487 value = INTVAL (operands[2]);
7488 emit_insn (gen_xordi3 (tmp, operands[1],
7489 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7490 }
7491 else
7492 {
7493 value = CONST_DOUBLE_LOW (operands[2]);
7494 emit_insn (gen_xordi3 (tmp, operands[1],
7495 immed_double_const (value
7496 & (~ (HOST_WIDE_INT) 0xffff),
7497 0, DImode)));
7498 }
7499
7500 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7501 DONE;
7502 }
7503 }")
7504
7505 (define_insn "*booldi3_internal1"
7506 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7507 (match_operator:DI 3 "boolean_or_operator"
7508 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7509 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7510 "TARGET_POWERPC64"
7511 "@
7512 %q3 %0,%1,%2
7513 %q3i %0,%1,%b2
7514 %q3is %0,%1,%u2")
7515
7516 (define_insn "*booldi3_internal2"
7517 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7518 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7519 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7520 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7521 (const_int 0)))
7522 (clobber (match_scratch:DI 3 "=r,r"))]
7523 "TARGET_64BIT"
7524 "@
7525 %q4. %3,%1,%2
7526 #"
7527 [(set_attr "type" "compare")
7528 (set_attr "length" "4,8")])
7529
7530 (define_split
7531 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7532 (compare:CC (match_operator:DI 4 "boolean_operator"
7533 [(match_operand:DI 1 "gpc_reg_operand" "")
7534 (match_operand:DI 2 "gpc_reg_operand" "")])
7535 (const_int 0)))
7536 (clobber (match_scratch:DI 3 ""))]
7537 "TARGET_POWERPC64 && reload_completed"
7538 [(set (match_dup 3) (match_dup 4))
7539 (set (match_dup 0)
7540 (compare:CC (match_dup 3)
7541 (const_int 0)))]
7542 "")
7543
7544 (define_insn "*booldi3_internal3"
7545 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7546 (compare:CC (match_operator:DI 4 "boolean_operator"
7547 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7548 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7549 (const_int 0)))
7550 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7551 (match_dup 4))]
7552 "TARGET_64BIT"
7553 "@
7554 %q4. %0,%1,%2
7555 #"
7556 [(set_attr "type" "compare")
7557 (set_attr "length" "4,8")])
7558
7559 (define_split
7560 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7561 (compare:CC (match_operator:DI 4 "boolean_operator"
7562 [(match_operand:DI 1 "gpc_reg_operand" "")
7563 (match_operand:DI 2 "gpc_reg_operand" "")])
7564 (const_int 0)))
7565 (set (match_operand:DI 0 "gpc_reg_operand" "")
7566 (match_dup 4))]
7567 "TARGET_POWERPC64 && reload_completed"
7568 [(set (match_dup 0) (match_dup 4))
7569 (set (match_dup 3)
7570 (compare:CC (match_dup 0)
7571 (const_int 0)))]
7572 "")
7573
7574 ;; Split a logical operation that we can't do in one insn into two insns,
7575 ;; each of which does one 16-bit part. This is used by combine.
7576
7577 (define_split
7578 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7579 (match_operator:DI 3 "boolean_or_operator"
7580 [(match_operand:DI 1 "gpc_reg_operand" "")
7581 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7582 "TARGET_POWERPC64"
7583 [(set (match_dup 0) (match_dup 4))
7584 (set (match_dup 0) (match_dup 5))]
7585 "
7586 {
7587 rtx i3,i4;
7588
7589 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7590 {
7591 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7592 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7593 0, DImode);
7594 i4 = GEN_INT (value & 0xffff);
7595 }
7596 else
7597 {
7598 i3 = GEN_INT (INTVAL (operands[2])
7599 & (~ (HOST_WIDE_INT) 0xffff));
7600 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7601 }
7602 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7603 operands[1], i3);
7604 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
7605 operands[0], i4);
7606 }")
7607
7608 (define_insn "*boolcdi3_internal1"
7609 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7610 (match_operator:DI 3 "boolean_operator"
7611 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7612 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7613 "TARGET_POWERPC64"
7614 "%q3 %0,%2,%1")
7615
7616 (define_insn "*boolcdi3_internal2"
7617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7618 (compare:CC (match_operator:DI 4 "boolean_operator"
7619 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7620 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7621 (const_int 0)))
7622 (clobber (match_scratch:DI 3 "=r,r"))]
7623 "TARGET_64BIT"
7624 "@
7625 %q4. %3,%2,%1
7626 #"
7627 [(set_attr "type" "compare")
7628 (set_attr "length" "4,8")])
7629
7630 (define_split
7631 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7632 (compare:CC (match_operator:DI 4 "boolean_operator"
7633 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7634 (match_operand:DI 2 "gpc_reg_operand" "")])
7635 (const_int 0)))
7636 (clobber (match_scratch:DI 3 ""))]
7637 "TARGET_POWERPC64 && reload_completed"
7638 [(set (match_dup 3) (match_dup 4))
7639 (set (match_dup 0)
7640 (compare:CC (match_dup 3)
7641 (const_int 0)))]
7642 "")
7643
7644 (define_insn "*boolcdi3_internal3"
7645 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7646 (compare:CC (match_operator:DI 4 "boolean_operator"
7647 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7648 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7649 (const_int 0)))
7650 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7651 (match_dup 4))]
7652 "TARGET_64BIT"
7653 "@
7654 %q4. %0,%2,%1
7655 #"
7656 [(set_attr "type" "compare")
7657 (set_attr "length" "4,8")])
7658
7659 (define_split
7660 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7661 (compare:CC (match_operator:DI 4 "boolean_operator"
7662 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7663 (match_operand:DI 2 "gpc_reg_operand" "")])
7664 (const_int 0)))
7665 (set (match_operand:DI 0 "gpc_reg_operand" "")
7666 (match_dup 4))]
7667 "TARGET_POWERPC64 && reload_completed"
7668 [(set (match_dup 0) (match_dup 4))
7669 (set (match_dup 3)
7670 (compare:CC (match_dup 0)
7671 (const_int 0)))]
7672 "")
7673
7674 (define_insn "*boolccdi3_internal1"
7675 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7676 (match_operator:DI 3 "boolean_operator"
7677 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7678 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7679 "TARGET_POWERPC64"
7680 "%q3 %0,%1,%2")
7681
7682 (define_insn "*boolccdi3_internal2"
7683 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7684 (compare:CC (match_operator:DI 4 "boolean_operator"
7685 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7686 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7687 (const_int 0)))
7688 (clobber (match_scratch:DI 3 "=r,r"))]
7689 "TARGET_64BIT"
7690 "@
7691 %q4. %3,%1,%2
7692 #"
7693 [(set_attr "type" "compare")
7694 (set_attr "length" "4,8")])
7695
7696 (define_split
7697 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7698 (compare:CC (match_operator:DI 4 "boolean_operator"
7699 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7700 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7701 (const_int 0)))
7702 (clobber (match_scratch:DI 3 ""))]
7703 "TARGET_POWERPC64 && reload_completed"
7704 [(set (match_dup 3) (match_dup 4))
7705 (set (match_dup 0)
7706 (compare:CC (match_dup 3)
7707 (const_int 0)))]
7708 "")
7709
7710 (define_insn "*boolccdi3_internal3"
7711 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7712 (compare:CC (match_operator:DI 4 "boolean_operator"
7713 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7714 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7715 (const_int 0)))
7716 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7717 (match_dup 4))]
7718 "TARGET_64BIT"
7719 "@
7720 %q4. %0,%1,%2
7721 #"
7722 [(set_attr "type" "compare")
7723 (set_attr "length" "4,8")])
7724
7725 (define_split
7726 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7727 (compare:CC (match_operator:DI 4 "boolean_operator"
7728 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7729 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7730 (const_int 0)))
7731 (set (match_operand:DI 0 "gpc_reg_operand" "")
7732 (match_dup 4))]
7733 "TARGET_POWERPC64 && reload_completed"
7734 [(set (match_dup 0) (match_dup 4))
7735 (set (match_dup 3)
7736 (compare:CC (match_dup 0)
7737 (const_int 0)))]
7738 "")
7739 \f
7740 ;; Now define ways of moving data around.
7741
7742 ;; Set up a register with a value from the GOT table
7743
7744 (define_expand "movsi_got"
7745 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7746 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7747 (match_dup 2)] UNSPEC_MOVSI_GOT))]
7748 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7749 "
7750 {
7751 if (GET_CODE (operands[1]) == CONST)
7752 {
7753 rtx offset = const0_rtx;
7754 HOST_WIDE_INT value;
7755
7756 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7757 value = INTVAL (offset);
7758 if (value != 0)
7759 {
7760 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7761 emit_insn (gen_movsi_got (tmp, operands[1]));
7762 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7763 DONE;
7764 }
7765 }
7766
7767 operands[2] = rs6000_got_register (operands[1]);
7768 }")
7769
7770 (define_insn "*movsi_got_internal"
7771 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7772 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7773 (match_operand:SI 2 "gpc_reg_operand" "b")]
7774 UNSPEC_MOVSI_GOT))]
7775 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
7776 "{l|lwz} %0,%a1@got(%2)"
7777 [(set_attr "type" "load")])
7778
7779 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7780 ;; didn't get allocated to a hard register.
7781 (define_split
7782 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7783 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7784 (match_operand:SI 2 "memory_operand" "")]
7785 UNSPEC_MOVSI_GOT))]
7786 "DEFAULT_ABI == ABI_V4
7787 && flag_pic == 1
7788 && (reload_in_progress || reload_completed)"
7789 [(set (match_dup 0) (match_dup 2))
7790 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
7791 UNSPEC_MOVSI_GOT))]
7792 "")
7793
7794 ;; For SI, we special-case integers that can't be loaded in one insn. We
7795 ;; do the load 16-bits at a time. We could do this by loading from memory,
7796 ;; and this is even supposed to be faster, but it is simpler not to get
7797 ;; integers in the TOC.
7798 (define_insn "movsi_low"
7799 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7800 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
7801 (match_operand 2 "" ""))))]
7802 "TARGET_MACHO && ! TARGET_64BIT"
7803 "{l|lwz} %0,lo16(%2)(%1)"
7804 [(set_attr "type" "load")
7805 (set_attr "length" "4")])
7806
7807 (define_insn "*movsi_internal1"
7808 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
7809 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
7810 "gpc_reg_operand (operands[0], SImode)
7811 || gpc_reg_operand (operands[1], SImode)"
7812 "@
7813 mr %0,%1
7814 {cal|la} %0,%a1
7815 {l%U1%X1|lwz%U1%X1} %0,%1
7816 {st%U0%X0|stw%U0%X0} %1,%0
7817 {lil|li} %0,%1
7818 {liu|lis} %0,%v1
7819 #
7820 {cal|la} %0,%a1
7821 mf%1 %0
7822 mt%0 %1
7823 mt%0 %1
7824 mt%0 %1
7825 {cror 0,0,0|nop}"
7826 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
7827 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
7828
7829 ;; Split a load of a large constant into the appropriate two-insn
7830 ;; sequence.
7831
7832 (define_split
7833 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7834 (match_operand:SI 1 "const_int_operand" ""))]
7835 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7836 && (INTVAL (operands[1]) & 0xffff) != 0"
7837 [(set (match_dup 0)
7838 (match_dup 2))
7839 (set (match_dup 0)
7840 (ior:SI (match_dup 0)
7841 (match_dup 3)))]
7842 "
7843 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
7844
7845 if (tem == operands[0])
7846 DONE;
7847 else
7848 FAIL;
7849 }")
7850
7851 (define_insn "*mov<mode>_internal2"
7852 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
7853 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
7854 (const_int 0)))
7855 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
7856 ""
7857 "@
7858 {cmpi|cmp<wd>i} %2,%0,0
7859 mr. %0,%1
7860 #"
7861 [(set_attr "type" "cmp,compare,cmp")
7862 (set_attr "length" "4,4,8")])
7863
7864 (define_split
7865 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7866 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
7867 (const_int 0)))
7868 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
7869 "reload_completed"
7870 [(set (match_dup 0) (match_dup 1))
7871 (set (match_dup 2)
7872 (compare:CC (match_dup 0)
7873 (const_int 0)))]
7874 "")
7875 \f
7876 (define_insn "*movhi_internal"
7877 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7878 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7879 "gpc_reg_operand (operands[0], HImode)
7880 || gpc_reg_operand (operands[1], HImode)"
7881 "@
7882 mr %0,%1
7883 lhz%U1%X1 %0,%1
7884 sth%U0%X0 %1,%0
7885 {lil|li} %0,%w1
7886 mf%1 %0
7887 mt%0 %1
7888 mt%0 %1
7889 {cror 0,0,0|nop}"
7890 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7891
7892 (define_expand "mov<mode>"
7893 [(set (match_operand:INT 0 "general_operand" "")
7894 (match_operand:INT 1 "any_operand" ""))]
7895 ""
7896 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
7897
7898 (define_insn "*movqi_internal"
7899 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7900 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7901 "gpc_reg_operand (operands[0], QImode)
7902 || gpc_reg_operand (operands[1], QImode)"
7903 "@
7904 mr %0,%1
7905 lbz%U1%X1 %0,%1
7906 stb%U0%X0 %1,%0
7907 {lil|li} %0,%1
7908 mf%1 %0
7909 mt%0 %1
7910 mt%0 %1
7911 {cror 0,0,0|nop}"
7912 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
7913 \f
7914 ;; Here is how to move condition codes around. When we store CC data in
7915 ;; an integer register or memory, we store just the high-order 4 bits.
7916 ;; This lets us not shift in the most common case of CR0.
7917 (define_expand "movcc"
7918 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7919 (match_operand:CC 1 "nonimmediate_operand" ""))]
7920 ""
7921 "")
7922
7923 (define_insn "*movcc_internal1"
7924 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m")
7925 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))]
7926 "register_operand (operands[0], CCmode)
7927 || register_operand (operands[1], CCmode)"
7928 "@
7929 mcrf %0,%1
7930 mtcrf 128,%1
7931 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7932 mfcr %0%Q1
7933 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7934 mr %0,%1
7935 mf%1 %0
7936 mt%0 %1
7937 mt%0 %1
7938 {l%U1%X1|lwz%U1%X1} %0,%1
7939 {st%U0%U1|stw%U0%U1} %1,%0"
7940 [(set (attr "type")
7941 (cond [(eq_attr "alternative" "0")
7942 (const_string "cr_logical")
7943 (eq_attr "alternative" "1,2")
7944 (const_string "mtcr")
7945 (eq_attr "alternative" "5,7")
7946 (const_string "integer")
7947 (eq_attr "alternative" "6")
7948 (const_string "mfjmpr")
7949 (eq_attr "alternative" "8")
7950 (const_string "mtjmpr")
7951 (eq_attr "alternative" "9")
7952 (const_string "load")
7953 (eq_attr "alternative" "10")
7954 (const_string "store")
7955 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
7956 (const_string "mfcrf")
7957 ]
7958 (const_string "mfcr")))
7959 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
7960 \f
7961 ;; For floating-point, we normally deal with the floating-point registers
7962 ;; unless -msoft-float is used. The sole exception is that parameter passing
7963 ;; can produce floating-point values in fixed-point registers. Unless the
7964 ;; value is a simple constant or already in memory, we deal with this by
7965 ;; allocating memory and copying the value explicitly via that memory location.
7966 (define_expand "movsf"
7967 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7968 (match_operand:SF 1 "any_operand" ""))]
7969 ""
7970 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7971
7972 (define_split
7973 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7974 (match_operand:SF 1 "const_double_operand" ""))]
7975 "reload_completed
7976 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7977 || (GET_CODE (operands[0]) == SUBREG
7978 && GET_CODE (SUBREG_REG (operands[0])) == REG
7979 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7980 [(set (match_dup 2) (match_dup 3))]
7981 "
7982 {
7983 long l;
7984 REAL_VALUE_TYPE rv;
7985
7986 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7987 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7988
7989 if (! TARGET_POWERPC64)
7990 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7991 else
7992 operands[2] = gen_lowpart (SImode, operands[0]);
7993
7994 operands[3] = gen_int_mode (l, SImode);
7995 }")
7996
7997 (define_insn "*movsf_hardfloat"
7998 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
7999 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8000 "(gpc_reg_operand (operands[0], SFmode)
8001 || gpc_reg_operand (operands[1], SFmode))
8002 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8003 "@
8004 mr %0,%1
8005 {l%U1%X1|lwz%U1%X1} %0,%1
8006 {st%U0%X0|stw%U0%X0} %1,%0
8007 fmr %0,%1
8008 lfs%U1%X1 %0,%1
8009 stfs%U0%X0 %1,%0
8010 mt%0 %1
8011 mt%0 %1
8012 mf%1 %0
8013 {cror 0,0,0|nop}
8014 #
8015 #"
8016 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8017 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8018
8019 (define_insn "*movsf_softfloat"
8020 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
8021 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
8022 "(gpc_reg_operand (operands[0], SFmode)
8023 || gpc_reg_operand (operands[1], SFmode))
8024 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8025 "@
8026 mr %0,%1
8027 mt%0 %1
8028 mt%0 %1
8029 mf%1 %0
8030 {l%U1%X1|lwz%U1%X1} %0,%1
8031 {st%U0%X0|stw%U0%X0} %1,%0
8032 {lil|li} %0,%1
8033 {liu|lis} %0,%v1
8034 {cal|la} %0,%a1
8035 #
8036 #
8037 {cror 0,0,0|nop}"
8038 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
8039 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
8040
8041 \f
8042 (define_expand "movdf"
8043 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8044 (match_operand:DF 1 "any_operand" ""))]
8045 ""
8046 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8047
8048 (define_split
8049 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8050 (match_operand:DF 1 "const_int_operand" ""))]
8051 "! TARGET_POWERPC64 && reload_completed
8052 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8053 || (GET_CODE (operands[0]) == SUBREG
8054 && GET_CODE (SUBREG_REG (operands[0])) == REG
8055 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8056 [(set (match_dup 2) (match_dup 4))
8057 (set (match_dup 3) (match_dup 1))]
8058 "
8059 {
8060 int endian = (WORDS_BIG_ENDIAN == 0);
8061 HOST_WIDE_INT value = INTVAL (operands[1]);
8062
8063 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8064 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8065 #if HOST_BITS_PER_WIDE_INT == 32
8066 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8067 #else
8068 operands[4] = GEN_INT (value >> 32);
8069 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8070 #endif
8071 }")
8072
8073 (define_split
8074 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8075 (match_operand:DF 1 "const_double_operand" ""))]
8076 "! TARGET_POWERPC64 && reload_completed
8077 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8078 || (GET_CODE (operands[0]) == SUBREG
8079 && GET_CODE (SUBREG_REG (operands[0])) == REG
8080 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8081 [(set (match_dup 2) (match_dup 4))
8082 (set (match_dup 3) (match_dup 5))]
8083 "
8084 {
8085 int endian = (WORDS_BIG_ENDIAN == 0);
8086 long l[2];
8087 REAL_VALUE_TYPE rv;
8088
8089 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8090 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8091
8092 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8093 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8094 operands[4] = gen_int_mode (l[endian], SImode);
8095 operands[5] = gen_int_mode (l[1 - endian], SImode);
8096 }")
8097
8098 (define_split
8099 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8100 (match_operand:DF 1 "const_double_operand" ""))]
8101 "TARGET_POWERPC64 && reload_completed
8102 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8103 || (GET_CODE (operands[0]) == SUBREG
8104 && GET_CODE (SUBREG_REG (operands[0])) == REG
8105 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8106 [(set (match_dup 2) (match_dup 3))]
8107 "
8108 {
8109 int endian = (WORDS_BIG_ENDIAN == 0);
8110 long l[2];
8111 REAL_VALUE_TYPE rv;
8112 #if HOST_BITS_PER_WIDE_INT >= 64
8113 HOST_WIDE_INT val;
8114 #endif
8115
8116 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8117 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8118
8119 operands[2] = gen_lowpart (DImode, operands[0]);
8120 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8121 #if HOST_BITS_PER_WIDE_INT >= 64
8122 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8123 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8124
8125 operands[3] = gen_int_mode (val, DImode);
8126 #else
8127 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8128 #endif
8129 }")
8130
8131 ;; Don't have reload use general registers to load a constant. First,
8132 ;; it might not work if the output operand is the equivalent of
8133 ;; a non-offsettable memref, but also it is less efficient than loading
8134 ;; the constant into an FP register, since it will probably be used there.
8135 ;; The "??" is a kludge until we can figure out a more reasonable way
8136 ;; of handling these non-offsettable values.
8137 (define_insn "*movdf_hardfloat32"
8138 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8139 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8140 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8141 && (gpc_reg_operand (operands[0], DFmode)
8142 || gpc_reg_operand (operands[1], DFmode))"
8143 "*
8144 {
8145 switch (which_alternative)
8146 {
8147 default:
8148 gcc_unreachable ();
8149 case 0:
8150 /* We normally copy the low-numbered register first. However, if
8151 the first register operand 0 is the same as the second register
8152 of operand 1, we must copy in the opposite order. */
8153 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8154 return \"mr %L0,%L1\;mr %0,%1\";
8155 else
8156 return \"mr %0,%1\;mr %L0,%L1\";
8157 case 1:
8158 if (rs6000_offsettable_memref_p (operands[1])
8159 || (GET_CODE (operands[1]) == MEM
8160 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8161 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8162 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8163 {
8164 /* If the low-address word is used in the address, we must load
8165 it last. Otherwise, load it first. Note that we cannot have
8166 auto-increment in that case since the address register is
8167 known to be dead. */
8168 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8169 operands[1], 0))
8170 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8171 else
8172 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8173 }
8174 else
8175 {
8176 rtx addreg;
8177
8178 addreg = find_addr_reg (XEXP (operands[1], 0));
8179 if (refers_to_regno_p (REGNO (operands[0]),
8180 REGNO (operands[0]) + 1,
8181 operands[1], 0))
8182 {
8183 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8184 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8185 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8186 return \"{lx|lwzx} %0,%1\";
8187 }
8188 else
8189 {
8190 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8191 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8192 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8193 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8194 return \"\";
8195 }
8196 }
8197 case 2:
8198 if (rs6000_offsettable_memref_p (operands[0])
8199 || (GET_CODE (operands[0]) == MEM
8200 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8201 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8202 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8203 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8204 else
8205 {
8206 rtx addreg;
8207
8208 addreg = find_addr_reg (XEXP (operands[0], 0));
8209 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8210 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8211 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8212 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8213 return \"\";
8214 }
8215 case 3:
8216 return \"fmr %0,%1\";
8217 case 4:
8218 return \"lfd%U1%X1 %0,%1\";
8219 case 5:
8220 return \"stfd%U0%X0 %1,%0\";
8221 case 6:
8222 case 7:
8223 case 8:
8224 return \"#\";
8225 }
8226 }"
8227 [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*")
8228 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8229
8230 (define_insn "*movdf_softfloat32"
8231 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8232 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8233 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8234 && (gpc_reg_operand (operands[0], DFmode)
8235 || gpc_reg_operand (operands[1], DFmode))"
8236 "*
8237 {
8238 switch (which_alternative)
8239 {
8240 default:
8241 gcc_unreachable ();
8242 case 0:
8243 /* We normally copy the low-numbered register first. However, if
8244 the first register operand 0 is the same as the second register of
8245 operand 1, we must copy in the opposite order. */
8246 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8247 return \"mr %L0,%L1\;mr %0,%1\";
8248 else
8249 return \"mr %0,%1\;mr %L0,%L1\";
8250 case 1:
8251 /* If the low-address word is used in the address, we must load
8252 it last. Otherwise, load it first. Note that we cannot have
8253 auto-increment in that case since the address register is
8254 known to be dead. */
8255 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8256 operands[1], 0))
8257 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8258 else
8259 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8260 case 2:
8261 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8262 case 3:
8263 case 4:
8264 case 5:
8265 return \"#\";
8266 }
8267 }"
8268 [(set_attr "type" "two,load,store,*,*,*")
8269 (set_attr "length" "8,8,8,8,12,16")])
8270
8271 ; ld/std require word-aligned displacements -> 'Y' constraint.
8272 ; List Y->r and r->Y before r->r for reload.
8273 (define_insn "*movdf_hardfloat64"
8274 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,*c*l,!r,*h,!r,!r,!r")
8275 (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
8276 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8277 && (gpc_reg_operand (operands[0], DFmode)
8278 || gpc_reg_operand (operands[1], DFmode))"
8279 "@
8280 std%U0%X0 %1,%0
8281 ld%U1%X1 %0,%1
8282 mr %0,%1
8283 fmr %0,%1
8284 lfd%U1%X1 %0,%1
8285 stfd%U0%X0 %1,%0
8286 mt%0 %1
8287 mf%1 %0
8288 {cror 0,0,0|nop}
8289 #
8290 #
8291 #"
8292 [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
8293 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
8294
8295 (define_insn "*movdf_softfloat64"
8296 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
8297 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
8298 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8299 && (gpc_reg_operand (operands[0], DFmode)
8300 || gpc_reg_operand (operands[1], DFmode))"
8301 "@
8302 ld%U1%X1 %0,%1
8303 std%U0%X0 %1,%0
8304 mr %0,%1
8305 mt%0 %1
8306 mf%1 %0
8307 #
8308 #
8309 #
8310 {cror 0,0,0|nop}"
8311 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
8312 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8313 \f
8314 (define_expand "movtf"
8315 [(set (match_operand:TF 0 "general_operand" "")
8316 (match_operand:TF 1 "any_operand" ""))]
8317 "!TARGET_IEEEQUAD
8318 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8319 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8320
8321 ; It's important to list the o->f and f->o moves before f->f because
8322 ; otherwise reload, given m->f, will try to pick f->f and reload it,
8323 ; which doesn't make progress. Likewise r->Y must be before r->r.
8324 (define_insn_and_split "*movtf_internal"
8325 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r")
8326 (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))]
8327 "!TARGET_IEEEQUAD
8328 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8329 && (gpc_reg_operand (operands[0], TFmode)
8330 || gpc_reg_operand (operands[1], TFmode))"
8331 "#"
8332 "&& reload_completed"
8333 [(pc)]
8334 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8335 [(set_attr "length" "8,8,8,20,20,16")])
8336
8337 (define_expand "extenddftf2"
8338 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8339 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8340 (use (match_dup 2))])]
8341 "!TARGET_IEEEQUAD
8342 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8343 {
8344 operands[2] = CONST0_RTX (DFmode);
8345 /* Generate GOT reference early for SVR4 PIC. */
8346 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8347 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8348 })
8349
8350 (define_insn_and_split "*extenddftf2_internal"
8351 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r")
8352 (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF")))
8353 (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))]
8354 "!TARGET_IEEEQUAD
8355 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8356 "#"
8357 "&& reload_completed"
8358 [(pc)]
8359 {
8360 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8361 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8362 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8363 operands[1]);
8364 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8365 operands[2]);
8366 DONE;
8367 })
8368
8369 (define_expand "extendsftf2"
8370 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8371 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8372 "!TARGET_IEEEQUAD
8373 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8374 {
8375 rtx tmp = gen_reg_rtx (DFmode);
8376 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8377 emit_insn (gen_extenddftf2 (operands[0], tmp));
8378 DONE;
8379 })
8380
8381 (define_expand "trunctfdf2"
8382 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8383 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8384 "!TARGET_IEEEQUAD
8385 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8386 "")
8387
8388 (define_insn_and_split "trunctfdf2_internal1"
8389 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
8390 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))]
8391 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8392 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8393 "@
8394 #
8395 fmr %0,%1"
8396 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8397 [(const_int 0)]
8398 {
8399 emit_note (NOTE_INSN_DELETED);
8400 DONE;
8401 }
8402 [(set_attr "type" "fp")])
8403
8404 (define_insn "trunctfdf2_internal2"
8405 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8406 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8407 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8408 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8409 "fadd %0,%1,%L1"
8410 [(set_attr "type" "fp")])
8411
8412 (define_insn_and_split "trunctfsf2"
8413 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8414 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8415 (clobber (match_scratch:DF 2 "=f"))]
8416 "!TARGET_IEEEQUAD
8417 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8418 "#"
8419 "&& reload_completed"
8420 [(set (match_dup 2)
8421 (float_truncate:DF (match_dup 1)))
8422 (set (match_dup 0)
8423 (float_truncate:SF (match_dup 2)))]
8424 "")
8425
8426 (define_expand "floatsitf2"
8427 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8428 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))]
8429 "!TARGET_IEEEQUAD
8430 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8431 {
8432 rtx tmp = gen_reg_rtx (DFmode);
8433 expand_float (tmp, operands[1], false);
8434 emit_insn (gen_extenddftf2 (operands[0], tmp));
8435 DONE;
8436 })
8437
8438 ; fadd, but rounding towards zero.
8439 ; This is probably not the optimal code sequence.
8440 (define_insn "fix_trunc_helper"
8441 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8442 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")]
8443 UNSPEC_FIX_TRUNC_TF))
8444 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))]
8445 "TARGET_HARD_FLOAT && TARGET_FPRS"
8446 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8447 [(set_attr "type" "fp")
8448 (set_attr "length" "20")])
8449
8450 (define_expand "fix_trunctfsi2"
8451 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8452 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8453 (clobber (match_dup 2))
8454 (clobber (match_dup 3))
8455 (clobber (match_dup 4))
8456 (clobber (match_dup 5))])]
8457 "!TARGET_IEEEQUAD
8458 && (TARGET_POWER2 || TARGET_POWERPC)
8459 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8460 {
8461 operands[2] = gen_reg_rtx (DFmode);
8462 operands[3] = gen_reg_rtx (DFmode);
8463 operands[4] = gen_reg_rtx (DImode);
8464 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
8465 })
8466
8467 (define_insn_and_split "*fix_trunctfsi2_internal"
8468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8469 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
8470 (clobber (match_operand:DF 2 "gpc_reg_operand" "=f"))
8471 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f"))
8472 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))
8473 (clobber (match_operand:DI 5 "memory_operand" "=o"))]
8474 "!TARGET_IEEEQUAD
8475 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8476 "#"
8477 "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))"
8478 [(pc)]
8479 {
8480 rtx lowword;
8481 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8482
8483 gcc_assert (MEM_P (operands[5]));
8484 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8485
8486 emit_insn (gen_fctiwz (operands[4], operands[2]));
8487 emit_move_insn (operands[5], operands[4]);
8488 emit_move_insn (operands[0], lowword);
8489 DONE;
8490 })
8491
8492 (define_insn "negtf2"
8493 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8494 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8495 "!TARGET_IEEEQUAD
8496 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8497 "*
8498 {
8499 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8500 return \"fneg %L0,%L1\;fneg %0,%1\";
8501 else
8502 return \"fneg %0,%1\;fneg %L0,%L1\";
8503 }"
8504 [(set_attr "type" "fp")
8505 (set_attr "length" "8")])
8506
8507 (define_expand "abstf2"
8508 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8509 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8510 "!TARGET_IEEEQUAD
8511 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8512 "
8513 {
8514 rtx label = gen_label_rtx ();
8515 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
8516 emit_label (label);
8517 DONE;
8518 }")
8519
8520 (define_expand "abstf2_internal"
8521 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8522 (match_operand:TF 1 "gpc_reg_operand" "f"))
8523 (set (match_dup 3) (match_dup 5))
8524 (set (match_dup 5) (abs:DF (match_dup 5)))
8525 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
8526 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
8527 (label_ref (match_operand 2 "" ""))
8528 (pc)))
8529 (set (match_dup 6) (neg:DF (match_dup 6)))]
8530 "!TARGET_IEEEQUAD
8531 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8532 "
8533 {
8534 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8535 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8536 operands[3] = gen_reg_rtx (DFmode);
8537 operands[4] = gen_reg_rtx (CCFPmode);
8538 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
8539 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
8540 }")
8541 \f
8542 ;; Next come the multi-word integer load and store and the load and store
8543 ;; multiple insns.
8544
8545 ; List r->r after r->"o<>", otherwise reload will try to reload a
8546 ; non-offsettable address by using r->r which won't make progress.
8547 (define_insn "*movdi_internal32"
8548 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r")
8549 (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))]
8550 "! TARGET_POWERPC64
8551 && (gpc_reg_operand (operands[0], DImode)
8552 || gpc_reg_operand (operands[1], DImode))"
8553 "@
8554 #
8555 #
8556 #
8557 fmr %0,%1
8558 lfd%U1%X1 %0,%1
8559 stfd%U0%X0 %1,%0
8560 #"
8561 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
8562
8563 (define_split
8564 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8565 (match_operand:DI 1 "const_int_operand" ""))]
8566 "! TARGET_POWERPC64 && reload_completed"
8567 [(set (match_dup 2) (match_dup 4))
8568 (set (match_dup 3) (match_dup 1))]
8569 "
8570 {
8571 HOST_WIDE_INT value = INTVAL (operands[1]);
8572 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8573 DImode);
8574 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8575 DImode);
8576 #if HOST_BITS_PER_WIDE_INT == 32
8577 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8578 #else
8579 operands[4] = GEN_INT (value >> 32);
8580 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8581 #endif
8582 }")
8583
8584 (define_split
8585 [(set (match_operand:DI 0 "nonimmediate_operand" "")
8586 (match_operand:DI 1 "input_operand" ""))]
8587 "reload_completed && !TARGET_POWERPC64
8588 && gpr_or_gpr_p (operands[0], operands[1])"
8589 [(pc)]
8590 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8591
8592 (define_insn "*movdi_internal64"
8593 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h")
8594 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8595 "TARGET_POWERPC64
8596 && (gpc_reg_operand (operands[0], DImode)
8597 || gpc_reg_operand (operands[1], DImode))"
8598 "@
8599 mr %0,%1
8600 ld%U1%X1 %0,%1
8601 std%U0%X0 %1,%0
8602 li %0,%1
8603 lis %0,%v1
8604 #
8605 {cal|la} %0,%a1
8606 fmr %0,%1
8607 lfd%U1%X1 %0,%1
8608 stfd%U0%X0 %1,%0
8609 mf%1 %0
8610 mt%0 %1
8611 {cror 0,0,0|nop}"
8612 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
8613 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8614
8615 ;; immediate value valid for a single instruction hiding in a const_double
8616 (define_insn ""
8617 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8618 (match_operand:DI 1 "const_double_operand" "F"))]
8619 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8620 && GET_CODE (operands[1]) == CONST_DOUBLE
8621 && num_insns_constant (operands[1], DImode) == 1"
8622 "*
8623 {
8624 return ((unsigned HOST_WIDE_INT)
8625 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8626 ? \"li %0,%1\" : \"lis %0,%v1\";
8627 }")
8628
8629 ;; Generate all one-bits and clear left or right.
8630 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8631 (define_split
8632 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8633 (match_operand:DI 1 "mask64_operand" ""))]
8634 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8635 [(set (match_dup 0) (const_int -1))
8636 (set (match_dup 0)
8637 (and:DI (rotate:DI (match_dup 0)
8638 (const_int 0))
8639 (match_dup 1)))]
8640 "")
8641
8642 ;; Split a load of a large constant into the appropriate five-instruction
8643 ;; sequence. Handle anything in a constant number of insns.
8644 ;; When non-easy constants can go in the TOC, this should use
8645 ;; easy_fp_constant predicate.
8646 (define_split
8647 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8648 (match_operand:DI 1 "const_int_operand" ""))]
8649 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8650 [(set (match_dup 0) (match_dup 2))
8651 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8652 "
8653 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8654
8655 if (tem == operands[0])
8656 DONE;
8657 else
8658 FAIL;
8659 }")
8660
8661 (define_split
8662 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8663 (match_operand:DI 1 "const_double_operand" ""))]
8664 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8665 [(set (match_dup 0) (match_dup 2))
8666 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8667 "
8668 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8669
8670 if (tem == operands[0])
8671 DONE;
8672 else
8673 FAIL;
8674 }")
8675 \f
8676 ;; TImode is similar, except that we usually want to compute the address into
8677 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8678 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8679
8680 ;; We say that MQ is clobbered in the last alternative because the first
8681 ;; alternative would never get used otherwise since it would need a reload
8682 ;; while the 2nd alternative would not. We put memory cases first so they
8683 ;; are preferred. Otherwise, we'd try to reload the output instead of
8684 ;; giving the SCRATCH mq.
8685
8686 (define_insn "*movti_power"
8687 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
8688 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
8689 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
8690 "TARGET_POWER && ! TARGET_POWERPC64
8691 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8692 "*
8693 {
8694 switch (which_alternative)
8695 {
8696 default:
8697 gcc_unreachable ();
8698
8699 case 0:
8700 if (TARGET_STRING)
8701 return \"{stsi|stswi} %1,%P0,16\";
8702 case 1:
8703 case 2:
8704 return \"#\";
8705 case 3:
8706 /* If the address is not used in the output, we can use lsi. Otherwise,
8707 fall through to generating four loads. */
8708 if (TARGET_STRING
8709 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8710 return \"{lsi|lswi} %0,%P1,16\";
8711 /* ... fall through ... */
8712 case 4:
8713 case 5:
8714 return \"#\";
8715 }
8716 }"
8717 [(set_attr "type" "store,store,*,load,load,*")])
8718
8719 (define_insn "*movti_string"
8720 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
8721 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
8722 "! TARGET_POWER && ! TARGET_POWERPC64
8723 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8724 "*
8725 {
8726 switch (which_alternative)
8727 {
8728 default:
8729 gcc_unreachable ();
8730 case 0:
8731 if (TARGET_STRING)
8732 return \"{stsi|stswi} %1,%P0,16\";
8733 case 1:
8734 case 2:
8735 return \"#\";
8736 case 3:
8737 /* If the address is not used in the output, we can use lsi. Otherwise,
8738 fall through to generating four loads. */
8739 if (TARGET_STRING
8740 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
8741 return \"{lsi|lswi} %0,%P1,16\";
8742 /* ... fall through ... */
8743 case 4:
8744 case 5:
8745 return \"#\";
8746 }
8747 }"
8748 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
8749
8750 (define_insn "*movti_ppc64"
8751 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
8752 (match_operand:TI 1 "input_operand" "r,r,m"))]
8753 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8754 || gpc_reg_operand (operands[1], TImode))"
8755 "#"
8756 [(set_attr "type" "*,load,store")])
8757
8758 (define_split
8759 [(set (match_operand:TI 0 "gpc_reg_operand" "")
8760 (match_operand:TI 1 "const_double_operand" ""))]
8761 "TARGET_POWERPC64"
8762 [(set (match_dup 2) (match_dup 4))
8763 (set (match_dup 3) (match_dup 5))]
8764 "
8765 {
8766 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
8767 TImode);
8768 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
8769 TImode);
8770 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8771 {
8772 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8773 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8774 }
8775 else if (GET_CODE (operands[1]) == CONST_INT)
8776 {
8777 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
8778 operands[5] = operands[1];
8779 }
8780 else
8781 FAIL;
8782 }")
8783
8784 (define_split
8785 [(set (match_operand:TI 0 "nonimmediate_operand" "")
8786 (match_operand:TI 1 "input_operand" ""))]
8787 "reload_completed
8788 && gpr_or_gpr_p (operands[0], operands[1])"
8789 [(pc)]
8790 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
8791 \f
8792 (define_expand "load_multiple"
8793 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8794 (match_operand:SI 1 "" ""))
8795 (use (match_operand:SI 2 "" ""))])]
8796 "TARGET_STRING && !TARGET_POWERPC64"
8797 "
8798 {
8799 int regno;
8800 int count;
8801 rtx op1;
8802 int i;
8803
8804 /* Support only loading a constant number of fixed-point registers from
8805 memory and only bother with this if more than two; the machine
8806 doesn't support more than eight. */
8807 if (GET_CODE (operands[2]) != CONST_INT
8808 || INTVAL (operands[2]) <= 2
8809 || INTVAL (operands[2]) > 8
8810 || GET_CODE (operands[1]) != MEM
8811 || GET_CODE (operands[0]) != REG
8812 || REGNO (operands[0]) >= 32)
8813 FAIL;
8814
8815 count = INTVAL (operands[2]);
8816 regno = REGNO (operands[0]);
8817
8818 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8819 op1 = replace_equiv_address (operands[1],
8820 force_reg (SImode, XEXP (operands[1], 0)));
8821
8822 for (i = 0; i < count; i++)
8823 XVECEXP (operands[3], 0, i)
8824 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8825 adjust_address_nv (op1, SImode, i * 4));
8826 }")
8827
8828 (define_insn "*ldmsi8"
8829 [(match_parallel 0 "load_multiple_operation"
8830 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8831 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8832 (set (match_operand:SI 3 "gpc_reg_operand" "")
8833 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8834 (set (match_operand:SI 4 "gpc_reg_operand" "")
8835 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8836 (set (match_operand:SI 5 "gpc_reg_operand" "")
8837 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8838 (set (match_operand:SI 6 "gpc_reg_operand" "")
8839 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8840 (set (match_operand:SI 7 "gpc_reg_operand" "")
8841 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8842 (set (match_operand:SI 8 "gpc_reg_operand" "")
8843 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
8844 (set (match_operand:SI 9 "gpc_reg_operand" "")
8845 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
8846 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
8847 "*
8848 { return rs6000_output_load_multiple (operands); }"
8849 [(set_attr "type" "load_ux")
8850 (set_attr "length" "32")])
8851
8852 (define_insn "*ldmsi7"
8853 [(match_parallel 0 "load_multiple_operation"
8854 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8855 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8856 (set (match_operand:SI 3 "gpc_reg_operand" "")
8857 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8858 (set (match_operand:SI 4 "gpc_reg_operand" "")
8859 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8860 (set (match_operand:SI 5 "gpc_reg_operand" "")
8861 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8862 (set (match_operand:SI 6 "gpc_reg_operand" "")
8863 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8864 (set (match_operand:SI 7 "gpc_reg_operand" "")
8865 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
8866 (set (match_operand:SI 8 "gpc_reg_operand" "")
8867 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
8868 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
8869 "*
8870 { return rs6000_output_load_multiple (operands); }"
8871 [(set_attr "type" "load_ux")
8872 (set_attr "length" "32")])
8873
8874 (define_insn "*ldmsi6"
8875 [(match_parallel 0 "load_multiple_operation"
8876 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8877 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8878 (set (match_operand:SI 3 "gpc_reg_operand" "")
8879 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8880 (set (match_operand:SI 4 "gpc_reg_operand" "")
8881 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8882 (set (match_operand:SI 5 "gpc_reg_operand" "")
8883 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8884 (set (match_operand:SI 6 "gpc_reg_operand" "")
8885 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
8886 (set (match_operand:SI 7 "gpc_reg_operand" "")
8887 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
8888 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
8889 "*
8890 { return rs6000_output_load_multiple (operands); }"
8891 [(set_attr "type" "load_ux")
8892 (set_attr "length" "32")])
8893
8894 (define_insn "*ldmsi5"
8895 [(match_parallel 0 "load_multiple_operation"
8896 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8897 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8898 (set (match_operand:SI 3 "gpc_reg_operand" "")
8899 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8900 (set (match_operand:SI 4 "gpc_reg_operand" "")
8901 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8902 (set (match_operand:SI 5 "gpc_reg_operand" "")
8903 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
8904 (set (match_operand:SI 6 "gpc_reg_operand" "")
8905 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
8906 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
8907 "*
8908 { return rs6000_output_load_multiple (operands); }"
8909 [(set_attr "type" "load_ux")
8910 (set_attr "length" "32")])
8911
8912 (define_insn "*ldmsi4"
8913 [(match_parallel 0 "load_multiple_operation"
8914 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8915 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8916 (set (match_operand:SI 3 "gpc_reg_operand" "")
8917 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8918 (set (match_operand:SI 4 "gpc_reg_operand" "")
8919 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
8920 (set (match_operand:SI 5 "gpc_reg_operand" "")
8921 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
8922 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
8923 "*
8924 { return rs6000_output_load_multiple (operands); }"
8925 [(set_attr "type" "load_ux")
8926 (set_attr "length" "32")])
8927
8928 (define_insn "*ldmsi3"
8929 [(match_parallel 0 "load_multiple_operation"
8930 [(set (match_operand:SI 2 "gpc_reg_operand" "")
8931 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
8932 (set (match_operand:SI 3 "gpc_reg_operand" "")
8933 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
8934 (set (match_operand:SI 4 "gpc_reg_operand" "")
8935 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
8936 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
8937 "*
8938 { return rs6000_output_load_multiple (operands); }"
8939 [(set_attr "type" "load_ux")
8940 (set_attr "length" "32")])
8941
8942 (define_expand "store_multiple"
8943 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8944 (match_operand:SI 1 "" ""))
8945 (clobber (scratch:SI))
8946 (use (match_operand:SI 2 "" ""))])]
8947 "TARGET_STRING && !TARGET_POWERPC64"
8948 "
8949 {
8950 int regno;
8951 int count;
8952 rtx to;
8953 rtx op0;
8954 int i;
8955
8956 /* Support only storing a constant number of fixed-point registers to
8957 memory and only bother with this if more than two; the machine
8958 doesn't support more than eight. */
8959 if (GET_CODE (operands[2]) != CONST_INT
8960 || INTVAL (operands[2]) <= 2
8961 || INTVAL (operands[2]) > 8
8962 || GET_CODE (operands[0]) != MEM
8963 || GET_CODE (operands[1]) != REG
8964 || REGNO (operands[1]) >= 32)
8965 FAIL;
8966
8967 count = INTVAL (operands[2]);
8968 regno = REGNO (operands[1]);
8969
8970 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8971 to = force_reg (SImode, XEXP (operands[0], 0));
8972 op0 = replace_equiv_address (operands[0], to);
8973
8974 XVECEXP (operands[3], 0, 0)
8975 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
8976 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8977 gen_rtx_SCRATCH (SImode));
8978
8979 for (i = 1; i < count; i++)
8980 XVECEXP (operands[3], 0, i + 1)
8981 = gen_rtx_SET (VOIDmode,
8982 adjust_address_nv (op0, SImode, i * 4),
8983 gen_rtx_REG (SImode, regno + i));
8984 }")
8985
8986 (define_insn "*stmsi8"
8987 [(match_parallel 0 "store_multiple_operation"
8988 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8989 (match_operand:SI 2 "gpc_reg_operand" "r"))
8990 (clobber (match_scratch:SI 3 "X"))
8991 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
8992 (match_operand:SI 4 "gpc_reg_operand" "r"))
8993 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
8994 (match_operand:SI 5 "gpc_reg_operand" "r"))
8995 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
8996 (match_operand:SI 6 "gpc_reg_operand" "r"))
8997 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
8998 (match_operand:SI 7 "gpc_reg_operand" "r"))
8999 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9000 (match_operand:SI 8 "gpc_reg_operand" "r"))
9001 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9002 (match_operand:SI 9 "gpc_reg_operand" "r"))
9003 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9004 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9005 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9006 "{stsi|stswi} %2,%1,%O0"
9007 [(set_attr "type" "store_ux")])
9008
9009 (define_insn "*stmsi7"
9010 [(match_parallel 0 "store_multiple_operation"
9011 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9012 (match_operand:SI 2 "gpc_reg_operand" "r"))
9013 (clobber (match_scratch:SI 3 "X"))
9014 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9015 (match_operand:SI 4 "gpc_reg_operand" "r"))
9016 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9017 (match_operand:SI 5 "gpc_reg_operand" "r"))
9018 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9019 (match_operand:SI 6 "gpc_reg_operand" "r"))
9020 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9021 (match_operand:SI 7 "gpc_reg_operand" "r"))
9022 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9023 (match_operand:SI 8 "gpc_reg_operand" "r"))
9024 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9025 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9026 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9027 "{stsi|stswi} %2,%1,%O0"
9028 [(set_attr "type" "store_ux")])
9029
9030 (define_insn "*stmsi6"
9031 [(match_parallel 0 "store_multiple_operation"
9032 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9033 (match_operand:SI 2 "gpc_reg_operand" "r"))
9034 (clobber (match_scratch:SI 3 "X"))
9035 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9036 (match_operand:SI 4 "gpc_reg_operand" "r"))
9037 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9038 (match_operand:SI 5 "gpc_reg_operand" "r"))
9039 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9040 (match_operand:SI 6 "gpc_reg_operand" "r"))
9041 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9042 (match_operand:SI 7 "gpc_reg_operand" "r"))
9043 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9044 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9045 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9046 "{stsi|stswi} %2,%1,%O0"
9047 [(set_attr "type" "store_ux")])
9048
9049 (define_insn "*stmsi5"
9050 [(match_parallel 0 "store_multiple_operation"
9051 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9052 (match_operand:SI 2 "gpc_reg_operand" "r"))
9053 (clobber (match_scratch:SI 3 "X"))
9054 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9055 (match_operand:SI 4 "gpc_reg_operand" "r"))
9056 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9057 (match_operand:SI 5 "gpc_reg_operand" "r"))
9058 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9059 (match_operand:SI 6 "gpc_reg_operand" "r"))
9060 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9061 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9062 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9063 "{stsi|stswi} %2,%1,%O0"
9064 [(set_attr "type" "store_ux")])
9065
9066 (define_insn "*stmsi4"
9067 [(match_parallel 0 "store_multiple_operation"
9068 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9069 (match_operand:SI 2 "gpc_reg_operand" "r"))
9070 (clobber (match_scratch:SI 3 "X"))
9071 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9072 (match_operand:SI 4 "gpc_reg_operand" "r"))
9073 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9074 (match_operand:SI 5 "gpc_reg_operand" "r"))
9075 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9076 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9077 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9078 "{stsi|stswi} %2,%1,%O0"
9079 [(set_attr "type" "store_ux")])
9080
9081 (define_insn "*stmsi3"
9082 [(match_parallel 0 "store_multiple_operation"
9083 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9084 (match_operand:SI 2 "gpc_reg_operand" "r"))
9085 (clobber (match_scratch:SI 3 "X"))
9086 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9087 (match_operand:SI 4 "gpc_reg_operand" "r"))
9088 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9089 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9090 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9091 "{stsi|stswi} %2,%1,%O0"
9092 [(set_attr "type" "store_ux")])
9093
9094 (define_insn "*stmsi8_power"
9095 [(match_parallel 0 "store_multiple_operation"
9096 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9097 (match_operand:SI 2 "gpc_reg_operand" "r"))
9098 (clobber (match_scratch:SI 3 "q"))
9099 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9100 (match_operand:SI 4 "gpc_reg_operand" "r"))
9101 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9102 (match_operand:SI 5 "gpc_reg_operand" "r"))
9103 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9104 (match_operand:SI 6 "gpc_reg_operand" "r"))
9105 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9106 (match_operand:SI 7 "gpc_reg_operand" "r"))
9107 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9108 (match_operand:SI 8 "gpc_reg_operand" "r"))
9109 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9110 (match_operand:SI 9 "gpc_reg_operand" "r"))
9111 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9112 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9113 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
9114 "{stsi|stswi} %2,%1,%O0"
9115 [(set_attr "type" "store_ux")])
9116
9117 (define_insn "*stmsi7_power"
9118 [(match_parallel 0 "store_multiple_operation"
9119 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9120 (match_operand:SI 2 "gpc_reg_operand" "r"))
9121 (clobber (match_scratch:SI 3 "q"))
9122 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9123 (match_operand:SI 4 "gpc_reg_operand" "r"))
9124 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9125 (match_operand:SI 5 "gpc_reg_operand" "r"))
9126 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9127 (match_operand:SI 6 "gpc_reg_operand" "r"))
9128 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9129 (match_operand:SI 7 "gpc_reg_operand" "r"))
9130 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9131 (match_operand:SI 8 "gpc_reg_operand" "r"))
9132 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9133 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9134 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
9135 "{stsi|stswi} %2,%1,%O0"
9136 [(set_attr "type" "store_ux")])
9137
9138 (define_insn "*stmsi6_power"
9139 [(match_parallel 0 "store_multiple_operation"
9140 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9141 (match_operand:SI 2 "gpc_reg_operand" "r"))
9142 (clobber (match_scratch:SI 3 "q"))
9143 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9144 (match_operand:SI 4 "gpc_reg_operand" "r"))
9145 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9146 (match_operand:SI 5 "gpc_reg_operand" "r"))
9147 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9148 (match_operand:SI 6 "gpc_reg_operand" "r"))
9149 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9150 (match_operand:SI 7 "gpc_reg_operand" "r"))
9151 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9152 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9153 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
9154 "{stsi|stswi} %2,%1,%O0"
9155 [(set_attr "type" "store_ux")])
9156
9157 (define_insn "*stmsi5_power"
9158 [(match_parallel 0 "store_multiple_operation"
9159 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9160 (match_operand:SI 2 "gpc_reg_operand" "r"))
9161 (clobber (match_scratch:SI 3 "q"))
9162 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9163 (match_operand:SI 4 "gpc_reg_operand" "r"))
9164 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9165 (match_operand:SI 5 "gpc_reg_operand" "r"))
9166 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9167 (match_operand:SI 6 "gpc_reg_operand" "r"))
9168 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9169 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9170 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
9171 "{stsi|stswi} %2,%1,%O0"
9172 [(set_attr "type" "store_ux")])
9173
9174 (define_insn "*stmsi4_power"
9175 [(match_parallel 0 "store_multiple_operation"
9176 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9177 (match_operand:SI 2 "gpc_reg_operand" "r"))
9178 (clobber (match_scratch:SI 3 "q"))
9179 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9180 (match_operand:SI 4 "gpc_reg_operand" "r"))
9181 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9182 (match_operand:SI 5 "gpc_reg_operand" "r"))
9183 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9184 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9185 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
9186 "{stsi|stswi} %2,%1,%O0"
9187 [(set_attr "type" "store_ux")])
9188
9189 (define_insn "*stmsi3_power"
9190 [(match_parallel 0 "store_multiple_operation"
9191 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9192 (match_operand:SI 2 "gpc_reg_operand" "r"))
9193 (clobber (match_scratch:SI 3 "q"))
9194 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9195 (match_operand:SI 4 "gpc_reg_operand" "r"))
9196 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9197 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9198 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
9199 "{stsi|stswi} %2,%1,%O0"
9200 [(set_attr "type" "store_ux")])
9201 \f
9202 (define_expand "setmemsi"
9203 [(parallel [(set (match_operand:BLK 0 "" "")
9204 (match_operand 2 "const_int_operand" ""))
9205 (use (match_operand:SI 1 "" ""))
9206 (use (match_operand:SI 3 "" ""))])]
9207 ""
9208 "
9209 {
9210 /* If value to set is not zero, use the library routine. */
9211 if (operands[2] != const0_rtx)
9212 FAIL;
9213
9214 if (expand_block_clear (operands))
9215 DONE;
9216 else
9217 FAIL;
9218 }")
9219
9220 ;; String/block move insn.
9221 ;; Argument 0 is the destination
9222 ;; Argument 1 is the source
9223 ;; Argument 2 is the length
9224 ;; Argument 3 is the alignment
9225
9226 (define_expand "movmemsi"
9227 [(parallel [(set (match_operand:BLK 0 "" "")
9228 (match_operand:BLK 1 "" ""))
9229 (use (match_operand:SI 2 "" ""))
9230 (use (match_operand:SI 3 "" ""))])]
9231 ""
9232 "
9233 {
9234 if (expand_block_move (operands))
9235 DONE;
9236 else
9237 FAIL;
9238 }")
9239
9240 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9241 ;; register allocator doesn't have a clue about allocating 8 word registers.
9242 ;; rD/rS = r5 is preferred, efficient form.
9243 (define_expand "movmemsi_8reg"
9244 [(parallel [(set (match_operand 0 "" "")
9245 (match_operand 1 "" ""))
9246 (use (match_operand 2 "" ""))
9247 (use (match_operand 3 "" ""))
9248 (clobber (reg:SI 5))
9249 (clobber (reg:SI 6))
9250 (clobber (reg:SI 7))
9251 (clobber (reg:SI 8))
9252 (clobber (reg:SI 9))
9253 (clobber (reg:SI 10))
9254 (clobber (reg:SI 11))
9255 (clobber (reg:SI 12))
9256 (clobber (match_scratch:SI 4 ""))])]
9257 "TARGET_STRING"
9258 "")
9259
9260 (define_insn ""
9261 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9262 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9263 (use (match_operand:SI 2 "immediate_operand" "i"))
9264 (use (match_operand:SI 3 "immediate_operand" "i"))
9265 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9266 (clobber (reg:SI 6))
9267 (clobber (reg:SI 7))
9268 (clobber (reg:SI 8))
9269 (clobber (reg:SI 9))
9270 (clobber (reg:SI 10))
9271 (clobber (reg:SI 11))
9272 (clobber (reg:SI 12))
9273 (clobber (match_scratch:SI 5 "=q"))]
9274 "TARGET_STRING && TARGET_POWER
9275 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9276 || INTVAL (operands[2]) == 0)
9277 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9278 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9279 && REGNO (operands[4]) == 5"
9280 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9281 [(set_attr "type" "store_ux")
9282 (set_attr "length" "8")])
9283
9284 (define_insn ""
9285 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9286 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9287 (use (match_operand:SI 2 "immediate_operand" "i"))
9288 (use (match_operand:SI 3 "immediate_operand" "i"))
9289 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9290 (clobber (reg:SI 6))
9291 (clobber (reg:SI 7))
9292 (clobber (reg:SI 8))
9293 (clobber (reg:SI 9))
9294 (clobber (reg:SI 10))
9295 (clobber (reg:SI 11))
9296 (clobber (reg:SI 12))
9297 (clobber (match_scratch:SI 5 "X"))]
9298 "TARGET_STRING && ! TARGET_POWER
9299 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9300 || INTVAL (operands[2]) == 0)
9301 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9302 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9303 && REGNO (operands[4]) == 5"
9304 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9305 [(set_attr "type" "store_ux")
9306 (set_attr "length" "8")])
9307
9308 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9309 ;; register allocator doesn't have a clue about allocating 6 word registers.
9310 ;; rD/rS = r5 is preferred, efficient form.
9311 (define_expand "movmemsi_6reg"
9312 [(parallel [(set (match_operand 0 "" "")
9313 (match_operand 1 "" ""))
9314 (use (match_operand 2 "" ""))
9315 (use (match_operand 3 "" ""))
9316 (clobber (reg:SI 5))
9317 (clobber (reg:SI 6))
9318 (clobber (reg:SI 7))
9319 (clobber (reg:SI 8))
9320 (clobber (reg:SI 9))
9321 (clobber (reg:SI 10))
9322 (clobber (match_scratch:SI 4 ""))])]
9323 "TARGET_STRING"
9324 "")
9325
9326 (define_insn ""
9327 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9328 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9329 (use (match_operand:SI 2 "immediate_operand" "i"))
9330 (use (match_operand:SI 3 "immediate_operand" "i"))
9331 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9332 (clobber (reg:SI 6))
9333 (clobber (reg:SI 7))
9334 (clobber (reg:SI 8))
9335 (clobber (reg:SI 9))
9336 (clobber (reg:SI 10))
9337 (clobber (match_scratch:SI 5 "=q"))]
9338 "TARGET_STRING && TARGET_POWER
9339 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9340 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9341 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9342 && REGNO (operands[4]) == 5"
9343 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9344 [(set_attr "type" "store_ux")
9345 (set_attr "length" "8")])
9346
9347 (define_insn ""
9348 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9349 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9350 (use (match_operand:SI 2 "immediate_operand" "i"))
9351 (use (match_operand:SI 3 "immediate_operand" "i"))
9352 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9353 (clobber (reg:SI 6))
9354 (clobber (reg:SI 7))
9355 (clobber (reg:SI 8))
9356 (clobber (reg:SI 9))
9357 (clobber (reg:SI 10))
9358 (clobber (match_scratch:SI 5 "X"))]
9359 "TARGET_STRING && ! TARGET_POWER
9360 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9361 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9362 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9363 && REGNO (operands[4]) == 5"
9364 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9365 [(set_attr "type" "store_ux")
9366 (set_attr "length" "8")])
9367
9368 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9369 ;; problems with TImode.
9370 ;; rD/rS = r5 is preferred, efficient form.
9371 (define_expand "movmemsi_4reg"
9372 [(parallel [(set (match_operand 0 "" "")
9373 (match_operand 1 "" ""))
9374 (use (match_operand 2 "" ""))
9375 (use (match_operand 3 "" ""))
9376 (clobber (reg:SI 5))
9377 (clobber (reg:SI 6))
9378 (clobber (reg:SI 7))
9379 (clobber (reg:SI 8))
9380 (clobber (match_scratch:SI 4 ""))])]
9381 "TARGET_STRING"
9382 "")
9383
9384 (define_insn ""
9385 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9386 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9387 (use (match_operand:SI 2 "immediate_operand" "i"))
9388 (use (match_operand:SI 3 "immediate_operand" "i"))
9389 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9390 (clobber (reg:SI 6))
9391 (clobber (reg:SI 7))
9392 (clobber (reg:SI 8))
9393 (clobber (match_scratch:SI 5 "=q"))]
9394 "TARGET_STRING && TARGET_POWER
9395 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9396 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9397 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9398 && REGNO (operands[4]) == 5"
9399 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9400 [(set_attr "type" "store_ux")
9401 (set_attr "length" "8")])
9402
9403 (define_insn ""
9404 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9405 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9406 (use (match_operand:SI 2 "immediate_operand" "i"))
9407 (use (match_operand:SI 3 "immediate_operand" "i"))
9408 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9409 (clobber (reg:SI 6))
9410 (clobber (reg:SI 7))
9411 (clobber (reg:SI 8))
9412 (clobber (match_scratch:SI 5 "X"))]
9413 "TARGET_STRING && ! TARGET_POWER
9414 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9415 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9416 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9417 && REGNO (operands[4]) == 5"
9418 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9419 [(set_attr "type" "store_ux")
9420 (set_attr "length" "8")])
9421
9422 ;; Move up to 8 bytes at a time.
9423 (define_expand "movmemsi_2reg"
9424 [(parallel [(set (match_operand 0 "" "")
9425 (match_operand 1 "" ""))
9426 (use (match_operand 2 "" ""))
9427 (use (match_operand 3 "" ""))
9428 (clobber (match_scratch:DI 4 ""))
9429 (clobber (match_scratch:SI 5 ""))])]
9430 "TARGET_STRING && ! TARGET_POWERPC64"
9431 "")
9432
9433 (define_insn ""
9434 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9435 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9436 (use (match_operand:SI 2 "immediate_operand" "i"))
9437 (use (match_operand:SI 3 "immediate_operand" "i"))
9438 (clobber (match_scratch:DI 4 "=&r"))
9439 (clobber (match_scratch:SI 5 "=q"))]
9440 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9441 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9442 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9443 [(set_attr "type" "store_ux")
9444 (set_attr "length" "8")])
9445
9446 (define_insn ""
9447 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9448 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9449 (use (match_operand:SI 2 "immediate_operand" "i"))
9450 (use (match_operand:SI 3 "immediate_operand" "i"))
9451 (clobber (match_scratch:DI 4 "=&r"))
9452 (clobber (match_scratch:SI 5 "X"))]
9453 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9454 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9455 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9456 [(set_attr "type" "store_ux")
9457 (set_attr "length" "8")])
9458
9459 ;; Move up to 4 bytes at a time.
9460 (define_expand "movmemsi_1reg"
9461 [(parallel [(set (match_operand 0 "" "")
9462 (match_operand 1 "" ""))
9463 (use (match_operand 2 "" ""))
9464 (use (match_operand 3 "" ""))
9465 (clobber (match_scratch:SI 4 ""))
9466 (clobber (match_scratch:SI 5 ""))])]
9467 "TARGET_STRING"
9468 "")
9469
9470 (define_insn ""
9471 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9472 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9473 (use (match_operand:SI 2 "immediate_operand" "i"))
9474 (use (match_operand:SI 3 "immediate_operand" "i"))
9475 (clobber (match_scratch:SI 4 "=&r"))
9476 (clobber (match_scratch:SI 5 "=q"))]
9477 "TARGET_STRING && TARGET_POWER
9478 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9479 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9480 [(set_attr "type" "store_ux")
9481 (set_attr "length" "8")])
9482
9483 (define_insn ""
9484 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9485 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9486 (use (match_operand:SI 2 "immediate_operand" "i"))
9487 (use (match_operand:SI 3 "immediate_operand" "i"))
9488 (clobber (match_scratch:SI 4 "=&r"))
9489 (clobber (match_scratch:SI 5 "X"))]
9490 "TARGET_STRING && ! TARGET_POWER
9491 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9492 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9493 [(set_attr "type" "store_ux")
9494 (set_attr "length" "8")])
9495 \f
9496 ;; Define insns that do load or store with update. Some of these we can
9497 ;; get by using pre-decrement or pre-increment, but the hardware can also
9498 ;; do cases where the increment is not the size of the object.
9499 ;;
9500 ;; In all these cases, we use operands 0 and 1 for the register being
9501 ;; incremented because those are the operands that local-alloc will
9502 ;; tie and these are the pair most likely to be tieable (and the ones
9503 ;; that will benefit the most).
9504
9505 (define_insn "*movdi_update1"
9506 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9507 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9508 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9509 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9510 (plus:DI (match_dup 1) (match_dup 2)))]
9511 "TARGET_POWERPC64 && TARGET_UPDATE"
9512 "@
9513 ldux %3,%0,%2
9514 ldu %3,%2(%0)"
9515 [(set_attr "type" "load_ux,load_u")])
9516
9517 (define_insn "movdi_<mode>_update"
9518 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9519 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9520 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9521 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9522 (plus:P (match_dup 1) (match_dup 2)))]
9523 "TARGET_POWERPC64 && TARGET_UPDATE"
9524 "@
9525 stdux %3,%0,%2
9526 stdu %3,%2(%0)"
9527 [(set_attr "type" "store_ux,store_u")])
9528
9529 (define_insn "*movsi_update1"
9530 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9531 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9532 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9533 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9534 (plus:SI (match_dup 1) (match_dup 2)))]
9535 "TARGET_UPDATE"
9536 "@
9537 {lux|lwzux} %3,%0,%2
9538 {lu|lwzu} %3,%2(%0)"
9539 [(set_attr "type" "load_ux,load_u")])
9540
9541 (define_insn "*movsi_update2"
9542 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9543 (sign_extend:DI
9544 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9545 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9546 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9547 (plus:DI (match_dup 1) (match_dup 2)))]
9548 "TARGET_POWERPC64"
9549 "lwaux %3,%0,%2"
9550 [(set_attr "type" "load_ext_ux")])
9551
9552 (define_insn "movsi_update"
9553 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9554 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9555 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9556 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9557 (plus:SI (match_dup 1) (match_dup 2)))]
9558 "TARGET_UPDATE"
9559 "@
9560 {stux|stwux} %3,%0,%2
9561 {stu|stwu} %3,%2(%0)"
9562 [(set_attr "type" "store_ux,store_u")])
9563
9564 (define_insn "*movhi_update1"
9565 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9566 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9567 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9568 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9569 (plus:SI (match_dup 1) (match_dup 2)))]
9570 "TARGET_UPDATE"
9571 "@
9572 lhzux %3,%0,%2
9573 lhzu %3,%2(%0)"
9574 [(set_attr "type" "load_ux,load_u")])
9575
9576 (define_insn "*movhi_update2"
9577 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9578 (zero_extend:SI
9579 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9580 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9581 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9582 (plus:SI (match_dup 1) (match_dup 2)))]
9583 "TARGET_UPDATE"
9584 "@
9585 lhzux %3,%0,%2
9586 lhzu %3,%2(%0)"
9587 [(set_attr "type" "load_ux,load_u")])
9588
9589 (define_insn "*movhi_update3"
9590 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9591 (sign_extend:SI
9592 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9593 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9594 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9595 (plus:SI (match_dup 1) (match_dup 2)))]
9596 "TARGET_UPDATE"
9597 "@
9598 lhaux %3,%0,%2
9599 lhau %3,%2(%0)"
9600 [(set_attr "type" "load_ext_ux,load_ext_u")])
9601
9602 (define_insn "*movhi_update4"
9603 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9604 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9605 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9606 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9607 (plus:SI (match_dup 1) (match_dup 2)))]
9608 "TARGET_UPDATE"
9609 "@
9610 sthux %3,%0,%2
9611 sthu %3,%2(%0)"
9612 [(set_attr "type" "store_ux,store_u")])
9613
9614 (define_insn "*movqi_update1"
9615 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9616 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9617 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9618 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9619 (plus:SI (match_dup 1) (match_dup 2)))]
9620 "TARGET_UPDATE"
9621 "@
9622 lbzux %3,%0,%2
9623 lbzu %3,%2(%0)"
9624 [(set_attr "type" "load_ux,load_u")])
9625
9626 (define_insn "*movqi_update2"
9627 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9628 (zero_extend:SI
9629 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9630 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9631 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9632 (plus:SI (match_dup 1) (match_dup 2)))]
9633 "TARGET_UPDATE"
9634 "@
9635 lbzux %3,%0,%2
9636 lbzu %3,%2(%0)"
9637 [(set_attr "type" "load_ux,load_u")])
9638
9639 (define_insn "*movqi_update3"
9640 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9641 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9642 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9643 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9644 (plus:SI (match_dup 1) (match_dup 2)))]
9645 "TARGET_UPDATE"
9646 "@
9647 stbux %3,%0,%2
9648 stbu %3,%2(%0)"
9649 [(set_attr "type" "store_ux,store_u")])
9650
9651 (define_insn "*movsf_update1"
9652 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9653 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9654 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9655 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9656 (plus:SI (match_dup 1) (match_dup 2)))]
9657 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9658 "@
9659 lfsux %3,%0,%2
9660 lfsu %3,%2(%0)"
9661 [(set_attr "type" "fpload_ux,fpload_u")])
9662
9663 (define_insn "*movsf_update2"
9664 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9665 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9666 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9667 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9668 (plus:SI (match_dup 1) (match_dup 2)))]
9669 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9670 "@
9671 stfsux %3,%0,%2
9672 stfsu %3,%2(%0)"
9673 [(set_attr "type" "fpstore_ux,fpstore_u")])
9674
9675 (define_insn "*movsf_update3"
9676 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9677 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9678 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9679 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9680 (plus:SI (match_dup 1) (match_dup 2)))]
9681 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9682 "@
9683 {lux|lwzux} %3,%0,%2
9684 {lu|lwzu} %3,%2(%0)"
9685 [(set_attr "type" "load_ux,load_u")])
9686
9687 (define_insn "*movsf_update4"
9688 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9689 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9690 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
9691 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9692 (plus:SI (match_dup 1) (match_dup 2)))]
9693 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
9694 "@
9695 {stux|stwux} %3,%0,%2
9696 {stu|stwu} %3,%2(%0)"
9697 [(set_attr "type" "store_ux,store_u")])
9698
9699 (define_insn "*movdf_update1"
9700 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
9701 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9702 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9703 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9704 (plus:SI (match_dup 1) (match_dup 2)))]
9705 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9706 "@
9707 lfdux %3,%0,%2
9708 lfdu %3,%2(%0)"
9709 [(set_attr "type" "fpload_ux,fpload_u")])
9710
9711 (define_insn "*movdf_update2"
9712 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9713 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9714 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
9715 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9716 (plus:SI (match_dup 1) (match_dup 2)))]
9717 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
9718 "@
9719 stfdux %3,%0,%2
9720 stfdu %3,%2(%0)"
9721 [(set_attr "type" "fpstore_ux,fpstore_u")])
9722
9723 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
9724
9725 (define_insn "*lfq_power2"
9726 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
9727 (match_operand:V2DF 1 "memory_operand" ""))]
9728 "TARGET_POWER2
9729 && TARGET_HARD_FLOAT && TARGET_FPRS"
9730 "lfq%U1%X1 %0,%1")
9731
9732 (define_peephole2
9733 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9734 (match_operand:DF 1 "memory_operand" ""))
9735 (set (match_operand:DF 2 "gpc_reg_operand" "")
9736 (match_operand:DF 3 "memory_operand" ""))]
9737 "TARGET_POWER2
9738 && TARGET_HARD_FLOAT && TARGET_FPRS
9739 && registers_ok_for_quad_peep (operands[0], operands[2])
9740 && mems_ok_for_quad_peep (operands[1], operands[3])"
9741 [(set (match_dup 0)
9742 (match_dup 1))]
9743 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
9744 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
9745
9746 (define_insn "*stfq_power2"
9747 [(set (match_operand:V2DF 0 "memory_operand" "")
9748 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
9749 "TARGET_POWER2
9750 && TARGET_HARD_FLOAT && TARGET_FPRS"
9751 "stfq%U0%X0 %1,%0")
9752
9753
9754 (define_peephole2
9755 [(set (match_operand:DF 0 "memory_operand" "")
9756 (match_operand:DF 1 "gpc_reg_operand" ""))
9757 (set (match_operand:DF 2 "memory_operand" "")
9758 (match_operand:DF 3 "gpc_reg_operand" ""))]
9759 "TARGET_POWER2
9760 && TARGET_HARD_FLOAT && TARGET_FPRS
9761 && registers_ok_for_quad_peep (operands[1], operands[3])
9762 && mems_ok_for_quad_peep (operands[0], operands[2])"
9763 [(set (match_dup 0)
9764 (match_dup 1))]
9765 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
9766 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
9767
9768 ;; After inserting conditional returns we can sometimes have
9769 ;; unnecessary register moves. Unfortunately we cannot have a
9770 ;; modeless peephole here, because some single SImode sets have early
9771 ;; clobber outputs. Although those sets expand to multi-ppc-insn
9772 ;; sequences, using get_attr_length here will smash the operands
9773 ;; array. Neither is there an early_cobbler_p predicate.
9774 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
9775 (define_peephole2
9776 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9777 (match_operand:DF 1 "any_operand" ""))
9778 (set (match_operand:DF 2 "gpc_reg_operand" "")
9779 (match_dup 0))]
9780 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
9781 && peep2_reg_dead_p (2, operands[0])"
9782 [(set (match_dup 2) (match_dup 1))])
9783
9784 (define_peephole2
9785 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9786 (match_operand:SF 1 "any_operand" ""))
9787 (set (match_operand:SF 2 "gpc_reg_operand" "")
9788 (match_dup 0))]
9789 "peep2_reg_dead_p (2, operands[0])"
9790 [(set (match_dup 2) (match_dup 1))])
9791
9792 \f
9793 ;; TLS support.
9794
9795 ;; "b" output constraint here and on tls_ld to support tls linker optimization.
9796 (define_insn "tls_gd_32"
9797 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9798 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9799 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9800 UNSPEC_TLSGD))]
9801 "HAVE_AS_TLS && !TARGET_64BIT"
9802 "addi %0,%1,%2@got@tlsgd")
9803
9804 (define_insn "tls_gd_64"
9805 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9806 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9807 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9808 UNSPEC_TLSGD))]
9809 "HAVE_AS_TLS && TARGET_64BIT"
9810 "addi %0,%1,%2@got@tlsgd")
9811
9812 (define_insn "tls_ld_32"
9813 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9814 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")]
9815 UNSPEC_TLSLD))]
9816 "HAVE_AS_TLS && !TARGET_64BIT"
9817 "addi %0,%1,%&@got@tlsld")
9818
9819 (define_insn "tls_ld_64"
9820 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9821 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")]
9822 UNSPEC_TLSLD))]
9823 "HAVE_AS_TLS && TARGET_64BIT"
9824 "addi %0,%1,%&@got@tlsld")
9825
9826 (define_insn "tls_dtprel_32"
9827 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9828 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9829 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9830 UNSPEC_TLSDTPREL))]
9831 "HAVE_AS_TLS && !TARGET_64BIT"
9832 "addi %0,%1,%2@dtprel")
9833
9834 (define_insn "tls_dtprel_64"
9835 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9836 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9837 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9838 UNSPEC_TLSDTPREL))]
9839 "HAVE_AS_TLS && TARGET_64BIT"
9840 "addi %0,%1,%2@dtprel")
9841
9842 (define_insn "tls_dtprel_ha_32"
9843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9844 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9845 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9846 UNSPEC_TLSDTPRELHA))]
9847 "HAVE_AS_TLS && !TARGET_64BIT"
9848 "addis %0,%1,%2@dtprel@ha")
9849
9850 (define_insn "tls_dtprel_ha_64"
9851 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9852 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9853 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9854 UNSPEC_TLSDTPRELHA))]
9855 "HAVE_AS_TLS && TARGET_64BIT"
9856 "addis %0,%1,%2@dtprel@ha")
9857
9858 (define_insn "tls_dtprel_lo_32"
9859 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9860 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9861 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9862 UNSPEC_TLSDTPRELLO))]
9863 "HAVE_AS_TLS && !TARGET_64BIT"
9864 "addi %0,%1,%2@dtprel@l")
9865
9866 (define_insn "tls_dtprel_lo_64"
9867 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9868 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9869 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9870 UNSPEC_TLSDTPRELLO))]
9871 "HAVE_AS_TLS && TARGET_64BIT"
9872 "addi %0,%1,%2@dtprel@l")
9873
9874 (define_insn "tls_got_dtprel_32"
9875 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9876 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9877 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9878 UNSPEC_TLSGOTDTPREL))]
9879 "HAVE_AS_TLS && !TARGET_64BIT"
9880 "lwz %0,%2@got@dtprel(%1)")
9881
9882 (define_insn "tls_got_dtprel_64"
9883 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9884 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9885 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9886 UNSPEC_TLSGOTDTPREL))]
9887 "HAVE_AS_TLS && TARGET_64BIT"
9888 "ld %0,%2@got@dtprel(%1)")
9889
9890 (define_insn "tls_tprel_32"
9891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9892 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9893 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9894 UNSPEC_TLSTPREL))]
9895 "HAVE_AS_TLS && !TARGET_64BIT"
9896 "addi %0,%1,%2@tprel")
9897
9898 (define_insn "tls_tprel_64"
9899 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9900 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9901 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9902 UNSPEC_TLSTPREL))]
9903 "HAVE_AS_TLS && TARGET_64BIT"
9904 "addi %0,%1,%2@tprel")
9905
9906 (define_insn "tls_tprel_ha_32"
9907 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9908 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9909 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9910 UNSPEC_TLSTPRELHA))]
9911 "HAVE_AS_TLS && !TARGET_64BIT"
9912 "addis %0,%1,%2@tprel@ha")
9913
9914 (define_insn "tls_tprel_ha_64"
9915 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9916 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9917 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9918 UNSPEC_TLSTPRELHA))]
9919 "HAVE_AS_TLS && TARGET_64BIT"
9920 "addis %0,%1,%2@tprel@ha")
9921
9922 (define_insn "tls_tprel_lo_32"
9923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9924 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9925 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9926 UNSPEC_TLSTPRELLO))]
9927 "HAVE_AS_TLS && !TARGET_64BIT"
9928 "addi %0,%1,%2@tprel@l")
9929
9930 (define_insn "tls_tprel_lo_64"
9931 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9932 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9933 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9934 UNSPEC_TLSTPRELLO))]
9935 "HAVE_AS_TLS && TARGET_64BIT"
9936 "addi %0,%1,%2@tprel@l")
9937
9938 ;; "b" output constraint here and on tls_tls input to support linker tls
9939 ;; optimization. The linker may edit the instructions emitted by a
9940 ;; tls_got_tprel/tls_tls pair to addis,addi.
9941 (define_insn "tls_got_tprel_32"
9942 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
9943 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9944 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9945 UNSPEC_TLSGOTTPREL))]
9946 "HAVE_AS_TLS && !TARGET_64BIT"
9947 "lwz %0,%2@got@tprel(%1)")
9948
9949 (define_insn "tls_got_tprel_64"
9950 [(set (match_operand:DI 0 "gpc_reg_operand" "=b")
9951 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9952 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9953 UNSPEC_TLSGOTTPREL))]
9954 "HAVE_AS_TLS && TARGET_64BIT"
9955 "ld %0,%2@got@tprel(%1)")
9956
9957 (define_insn "tls_tls_32"
9958 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9959 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")
9960 (match_operand:SI 2 "rs6000_tls_symbol_ref" "")]
9961 UNSPEC_TLSTLS))]
9962 "HAVE_AS_TLS && !TARGET_64BIT"
9963 "add %0,%1,%2@tls")
9964
9965 (define_insn "tls_tls_64"
9966 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9967 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")
9968 (match_operand:DI 2 "rs6000_tls_symbol_ref" "")]
9969 UNSPEC_TLSTLS))]
9970 "HAVE_AS_TLS && TARGET_64BIT"
9971 "add %0,%1,%2@tls")
9972 \f
9973 ;; Next come insns related to the calling sequence.
9974 ;;
9975 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
9976 ;; We move the back-chain and decrement the stack pointer.
9977
9978 (define_expand "allocate_stack"
9979 [(set (match_operand 0 "gpc_reg_operand" "=r")
9980 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
9981 (set (reg 1)
9982 (minus (reg 1) (match_dup 1)))]
9983 ""
9984 "
9985 { rtx chain = gen_reg_rtx (Pmode);
9986 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
9987 rtx neg_op0;
9988
9989 emit_move_insn (chain, stack_bot);
9990
9991 /* Check stack bounds if necessary. */
9992 if (current_function_limit_stack)
9993 {
9994 rtx available;
9995 available = expand_binop (Pmode, sub_optab,
9996 stack_pointer_rtx, stack_limit_rtx,
9997 NULL_RTX, 1, OPTAB_WIDEN);
9998 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
9999 }
10000
10001 if (GET_CODE (operands[1]) != CONST_INT
10002 || INTVAL (operands[1]) < -32767
10003 || INTVAL (operands[1]) > 32768)
10004 {
10005 neg_op0 = gen_reg_rtx (Pmode);
10006 if (TARGET_32BIT)
10007 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10008 else
10009 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10010 }
10011 else
10012 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10013
10014 if (TARGET_UPDATE)
10015 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update))
10016 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10017
10018 else
10019 {
10020 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10021 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10022 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10023 }
10024
10025 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10026 DONE;
10027 }")
10028
10029 ;; These patterns say how to save and restore the stack pointer. We need not
10030 ;; save the stack pointer at function level since we are careful to
10031 ;; preserve the backchain. At block level, we have to restore the backchain
10032 ;; when we restore the stack pointer.
10033 ;;
10034 ;; For nonlocal gotos, we must save both the stack pointer and its
10035 ;; backchain and restore both. Note that in the nonlocal case, the
10036 ;; save area is a memory location.
10037
10038 (define_expand "save_stack_function"
10039 [(match_operand 0 "any_operand" "")
10040 (match_operand 1 "any_operand" "")]
10041 ""
10042 "DONE;")
10043
10044 (define_expand "restore_stack_function"
10045 [(match_operand 0 "any_operand" "")
10046 (match_operand 1 "any_operand" "")]
10047 ""
10048 "DONE;")
10049
10050 ;; Adjust stack pointer (op0) to a new value (op1).
10051 ;; First copy old stack backchain to new location, and ensure that the
10052 ;; scheduler won't reorder the sp assignment before the backchain write.
10053 (define_expand "restore_stack_block"
10054 [(set (match_dup 2) (match_dup 3))
10055 (set (match_dup 4) (match_dup 2))
10056 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
10057 (set (match_operand 0 "register_operand" "")
10058 (match_operand 1 "register_operand" ""))]
10059 ""
10060 "
10061 {
10062 operands[2] = gen_reg_rtx (Pmode);
10063 operands[3] = gen_frame_mem (Pmode, operands[0]);
10064 operands[4] = gen_frame_mem (Pmode, operands[1]);
10065 operands[5] = gen_frame_mem (BLKmode, operands[0]);
10066 }")
10067
10068 (define_expand "save_stack_nonlocal"
10069 [(set (match_dup 3) (match_dup 4))
10070 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10071 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10072 ""
10073 "
10074 {
10075 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10076
10077 /* Copy the backchain to the first word, sp to the second. */
10078 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10079 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10080 operands[3] = gen_reg_rtx (Pmode);
10081 operands[4] = gen_frame_mem (Pmode, operands[1]);
10082 }")
10083
10084 (define_expand "restore_stack_nonlocal"
10085 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10086 (set (match_dup 3) (match_dup 4))
10087 (set (match_dup 5) (match_dup 2))
10088 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
10089 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10090 ""
10091 "
10092 {
10093 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10094
10095 /* Restore the backchain from the first word, sp from the second. */
10096 operands[2] = gen_reg_rtx (Pmode);
10097 operands[3] = gen_reg_rtx (Pmode);
10098 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10099 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10100 operands[5] = gen_frame_mem (Pmode, operands[3]);
10101 operands[6] = gen_frame_mem (BLKmode, operands[0]);
10102 }")
10103 \f
10104 ;; TOC register handling.
10105
10106 ;; Code to initialize the TOC register...
10107
10108 (define_insn "load_toc_aix_si"
10109 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10110 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10111 (use (reg:SI 2))])]
10112 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10113 "*
10114 {
10115 char buf[30];
10116 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10117 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10118 operands[2] = gen_rtx_REG (Pmode, 2);
10119 return \"{l|lwz} %0,%1(%2)\";
10120 }"
10121 [(set_attr "type" "load")])
10122
10123 (define_insn "load_toc_aix_di"
10124 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10125 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10126 (use (reg:DI 2))])]
10127 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10128 "*
10129 {
10130 char buf[30];
10131 #ifdef TARGET_RELOCATABLE
10132 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10133 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10134 #else
10135 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10136 #endif
10137 if (TARGET_ELF)
10138 strcat (buf, \"@toc\");
10139 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10140 operands[2] = gen_rtx_REG (Pmode, 2);
10141 return \"ld %0,%1(%2)\";
10142 }"
10143 [(set_attr "type" "load")])
10144
10145 (define_insn "load_toc_v4_pic_si"
10146 [(set (match_operand:SI 0 "register_operand" "=l")
10147 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10148 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10149 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10150 [(set_attr "type" "branch")
10151 (set_attr "length" "4")])
10152
10153 (define_insn "load_toc_v4_PIC_1"
10154 [(set (match_operand:SI 0 "register_operand" "=l")
10155 (match_operand:SI 1 "immediate_operand" "s"))
10156 (use (unspec [(match_dup 1)] UNSPEC_TOC))]
10157 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10158 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10159 "bcl 20,31,%1\\n%1:"
10160 [(set_attr "type" "branch")
10161 (set_attr "length" "4")])
10162
10163 (define_insn "load_toc_v4_PIC_1b"
10164 [(set (match_operand:SI 0 "register_operand" "=l")
10165 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")]
10166 UNSPEC_TOCPTR))]
10167 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10168 "bcl 20,31,$+8\\n\\t.long %1-$"
10169 [(set_attr "type" "branch")
10170 (set_attr "length" "8")])
10171
10172 (define_insn "load_toc_v4_PIC_2"
10173 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10174 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10175 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10176 (match_operand:SI 3 "immediate_operand" "s")))))]
10177 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10178 "{l|lwz} %0,%2-%3(%1)"
10179 [(set_attr "type" "load")])
10180
10181 (define_insn "load_toc_v4_PIC_3b"
10182 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
10183 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10184 (high:SI
10185 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10186 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10187 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10188 "{cau|addis} %0,%1,%2-%3@ha")
10189
10190 (define_insn "load_toc_v4_PIC_3c"
10191 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10192 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10193 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10194 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10195 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10196 "{cal|addi} %0,%1,%2-%3@l")
10197
10198 ;; If the TOC is shared over a translation unit, as happens with all
10199 ;; the kinds of PIC that we support, we need to restore the TOC
10200 ;; pointer only when jumping over units of translation.
10201 ;; On Darwin, we need to reload the picbase.
10202
10203 (define_expand "builtin_setjmp_receiver"
10204 [(use (label_ref (match_operand 0 "" "")))]
10205 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10206 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10207 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10208 "
10209 {
10210 #if TARGET_MACHO
10211 if (DEFAULT_ABI == ABI_DARWIN)
10212 {
10213 const char *picbase = machopic_function_base_name ();
10214 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase));
10215 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10216 rtx tmplabrtx;
10217 char tmplab[20];
10218
10219 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10220 CODE_LABEL_NUMBER (operands[0]));
10221 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10222
10223 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10224 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10225 }
10226 else
10227 #endif
10228 rs6000_emit_load_toc_table (FALSE);
10229 DONE;
10230 }")
10231
10232 ;; Elf specific ways of loading addresses for non-PIC code.
10233 ;; The output of this could be r0, but we make a very strong
10234 ;; preference for a base register because it will usually
10235 ;; be needed there.
10236 (define_insn "elf_high"
10237 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10238 (high:SI (match_operand 1 "" "")))]
10239 "TARGET_ELF && ! TARGET_64BIT"
10240 "{liu|lis} %0,%1@ha")
10241
10242 (define_insn "elf_low"
10243 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10244 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10245 (match_operand 2 "" "")))]
10246 "TARGET_ELF && ! TARGET_64BIT"
10247 "@
10248 {cal|la} %0,%2@l(%1)
10249 {ai|addic} %0,%1,%K2")
10250 \f
10251 ;; A function pointer under AIX is a pointer to a data area whose first word
10252 ;; contains the actual address of the function, whose second word contains a
10253 ;; pointer to its TOC, and whose third word contains a value to place in the
10254 ;; static chain register (r11). Note that if we load the static chain, our
10255 ;; "trampoline" need not have any executable code.
10256
10257 (define_expand "call_indirect_aix32"
10258 [(set (match_dup 2)
10259 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10260 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10261 (reg:SI 2))
10262 (set (reg:SI 2)
10263 (mem:SI (plus:SI (match_dup 0)
10264 (const_int 4))))
10265 (set (reg:SI 11)
10266 (mem:SI (plus:SI (match_dup 0)
10267 (const_int 8))))
10268 (parallel [(call (mem:SI (match_dup 2))
10269 (match_operand 1 "" ""))
10270 (use (reg:SI 2))
10271 (use (reg:SI 11))
10272 (set (reg:SI 2)
10273 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10274 (clobber (scratch:SI))])]
10275 "TARGET_32BIT"
10276 "
10277 { operands[2] = gen_reg_rtx (SImode); }")
10278
10279 (define_expand "call_indirect_aix64"
10280 [(set (match_dup 2)
10281 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10282 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10283 (reg:DI 2))
10284 (set (reg:DI 2)
10285 (mem:DI (plus:DI (match_dup 0)
10286 (const_int 8))))
10287 (set (reg:DI 11)
10288 (mem:DI (plus:DI (match_dup 0)
10289 (const_int 16))))
10290 (parallel [(call (mem:SI (match_dup 2))
10291 (match_operand 1 "" ""))
10292 (use (reg:DI 2))
10293 (use (reg:DI 11))
10294 (set (reg:DI 2)
10295 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10296 (clobber (scratch:SI))])]
10297 "TARGET_64BIT"
10298 "
10299 { operands[2] = gen_reg_rtx (DImode); }")
10300
10301 (define_expand "call_value_indirect_aix32"
10302 [(set (match_dup 3)
10303 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10304 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10305 (reg:SI 2))
10306 (set (reg:SI 2)
10307 (mem:SI (plus:SI (match_dup 1)
10308 (const_int 4))))
10309 (set (reg:SI 11)
10310 (mem:SI (plus:SI (match_dup 1)
10311 (const_int 8))))
10312 (parallel [(set (match_operand 0 "" "")
10313 (call (mem:SI (match_dup 3))
10314 (match_operand 2 "" "")))
10315 (use (reg:SI 2))
10316 (use (reg:SI 11))
10317 (set (reg:SI 2)
10318 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10319 (clobber (scratch:SI))])]
10320 "TARGET_32BIT"
10321 "
10322 { operands[3] = gen_reg_rtx (SImode); }")
10323
10324 (define_expand "call_value_indirect_aix64"
10325 [(set (match_dup 3)
10326 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10327 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10328 (reg:DI 2))
10329 (set (reg:DI 2)
10330 (mem:DI (plus:DI (match_dup 1)
10331 (const_int 8))))
10332 (set (reg:DI 11)
10333 (mem:DI (plus:DI (match_dup 1)
10334 (const_int 16))))
10335 (parallel [(set (match_operand 0 "" "")
10336 (call (mem:SI (match_dup 3))
10337 (match_operand 2 "" "")))
10338 (use (reg:DI 2))
10339 (use (reg:DI 11))
10340 (set (reg:DI 2)
10341 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10342 (clobber (scratch:SI))])]
10343 "TARGET_64BIT"
10344 "
10345 { operands[3] = gen_reg_rtx (DImode); }")
10346
10347 ;; Now the definitions for the call and call_value insns
10348 (define_expand "call"
10349 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10350 (match_operand 1 "" ""))
10351 (use (match_operand 2 "" ""))
10352 (clobber (scratch:SI))])]
10353 ""
10354 "
10355 {
10356 #if TARGET_MACHO
10357 if (MACHOPIC_INDIRECT)
10358 operands[0] = machopic_indirect_call_target (operands[0]);
10359 #endif
10360
10361 gcc_assert (GET_CODE (operands[0]) == MEM);
10362 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10363
10364 operands[0] = XEXP (operands[0], 0);
10365
10366 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10367 && flag_pic
10368 && GET_CODE (operands[0]) == SYMBOL_REF
10369 && !SYMBOL_REF_LOCAL_P (operands[0]))
10370 {
10371 rtx call;
10372 rtvec tmp;
10373
10374 tmp = gen_rtvec (3,
10375 gen_rtx_CALL (VOIDmode,
10376 gen_rtx_MEM (SImode, operands[0]),
10377 operands[1]),
10378 gen_rtx_USE (VOIDmode, operands[2]),
10379 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10380 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10381 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10382 DONE;
10383 }
10384
10385 if (GET_CODE (operands[0]) != SYMBOL_REF
10386 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10387 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10388 {
10389 if (INTVAL (operands[2]) & CALL_LONG)
10390 operands[0] = rs6000_longcall_ref (operands[0]);
10391
10392 switch (DEFAULT_ABI)
10393 {
10394 case ABI_V4:
10395 case ABI_DARWIN:
10396 operands[0] = force_reg (Pmode, operands[0]);
10397 break;
10398
10399 case ABI_AIX:
10400 /* AIX function pointers are really pointers to a three word
10401 area. */
10402 emit_call_insn (TARGET_32BIT
10403 ? gen_call_indirect_aix32 (force_reg (SImode,
10404 operands[0]),
10405 operands[1])
10406 : gen_call_indirect_aix64 (force_reg (DImode,
10407 operands[0]),
10408 operands[1]));
10409 DONE;
10410
10411 default:
10412 gcc_unreachable ();
10413 }
10414 }
10415 }")
10416
10417 (define_expand "call_value"
10418 [(parallel [(set (match_operand 0 "" "")
10419 (call (mem:SI (match_operand 1 "address_operand" ""))
10420 (match_operand 2 "" "")))
10421 (use (match_operand 3 "" ""))
10422 (clobber (scratch:SI))])]
10423 ""
10424 "
10425 {
10426 #if TARGET_MACHO
10427 if (MACHOPIC_INDIRECT)
10428 operands[1] = machopic_indirect_call_target (operands[1]);
10429 #endif
10430
10431 gcc_assert (GET_CODE (operands[1]) == MEM);
10432 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
10433
10434 operands[1] = XEXP (operands[1], 0);
10435
10436 if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
10437 && flag_pic
10438 && GET_CODE (operands[1]) == SYMBOL_REF
10439 && !SYMBOL_REF_LOCAL_P (operands[1]))
10440 {
10441 rtx call;
10442 rtvec tmp;
10443
10444 tmp = gen_rtvec (3,
10445 gen_rtx_SET (VOIDmode,
10446 operands[0],
10447 gen_rtx_CALL (VOIDmode,
10448 gen_rtx_MEM (SImode,
10449 operands[1]),
10450 operands[2])),
10451 gen_rtx_USE (VOIDmode, operands[3]),
10452 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
10453 call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
10454 use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
10455 DONE;
10456 }
10457
10458 if (GET_CODE (operands[1]) != SYMBOL_REF
10459 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10460 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
10461 {
10462 if (INTVAL (operands[3]) & CALL_LONG)
10463 operands[1] = rs6000_longcall_ref (operands[1]);
10464
10465 switch (DEFAULT_ABI)
10466 {
10467 case ABI_V4:
10468 case ABI_DARWIN:
10469 operands[1] = force_reg (Pmode, operands[1]);
10470 break;
10471
10472 case ABI_AIX:
10473 /* AIX function pointers are really pointers to a three word
10474 area. */
10475 emit_call_insn (TARGET_32BIT
10476 ? gen_call_value_indirect_aix32 (operands[0],
10477 force_reg (SImode,
10478 operands[1]),
10479 operands[2])
10480 : gen_call_value_indirect_aix64 (operands[0],
10481 force_reg (DImode,
10482 operands[1]),
10483 operands[2]));
10484 DONE;
10485
10486 default:
10487 gcc_unreachable ();
10488 }
10489 }
10490 }")
10491
10492 ;; Call to function in current module. No TOC pointer reload needed.
10493 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10494 ;; either the function was not prototyped, or it was prototyped as a
10495 ;; variable argument function. It is > 0 if FP registers were passed
10496 ;; and < 0 if they were not.
10497
10498 (define_insn "*call_local32"
10499 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10500 (match_operand 1 "" "g,g"))
10501 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10502 (clobber (match_scratch:SI 3 "=l,l"))]
10503 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10504 "*
10505 {
10506 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10507 output_asm_insn (\"crxor 6,6,6\", operands);
10508
10509 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10510 output_asm_insn (\"creqv 6,6,6\", operands);
10511
10512 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10513 }"
10514 [(set_attr "type" "branch")
10515 (set_attr "length" "4,8")])
10516
10517 (define_insn "*call_local64"
10518 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10519 (match_operand 1 "" "g,g"))
10520 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10521 (clobber (match_scratch:SI 3 "=l,l"))]
10522 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10523 "*
10524 {
10525 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10526 output_asm_insn (\"crxor 6,6,6\", operands);
10527
10528 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10529 output_asm_insn (\"creqv 6,6,6\", operands);
10530
10531 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10532 }"
10533 [(set_attr "type" "branch")
10534 (set_attr "length" "4,8")])
10535
10536 (define_insn "*call_value_local32"
10537 [(set (match_operand 0 "" "")
10538 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10539 (match_operand 2 "" "g,g")))
10540 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10541 (clobber (match_scratch:SI 4 "=l,l"))]
10542 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10543 "*
10544 {
10545 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10546 output_asm_insn (\"crxor 6,6,6\", operands);
10547
10548 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10549 output_asm_insn (\"creqv 6,6,6\", operands);
10550
10551 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10552 }"
10553 [(set_attr "type" "branch")
10554 (set_attr "length" "4,8")])
10555
10556
10557 (define_insn "*call_value_local64"
10558 [(set (match_operand 0 "" "")
10559 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10560 (match_operand 2 "" "g,g")))
10561 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10562 (clobber (match_scratch:SI 4 "=l,l"))]
10563 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10564 "*
10565 {
10566 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10567 output_asm_insn (\"crxor 6,6,6\", operands);
10568
10569 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10570 output_asm_insn (\"creqv 6,6,6\", operands);
10571
10572 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10573 }"
10574 [(set_attr "type" "branch")
10575 (set_attr "length" "4,8")])
10576
10577 ;; Call to function which may be in another module. Restore the TOC
10578 ;; pointer (r2) after the call unless this is System V.
10579 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10580 ;; either the function was not prototyped, or it was prototyped as a
10581 ;; variable argument function. It is > 0 if FP registers were passed
10582 ;; and < 0 if they were not.
10583
10584 (define_insn "*call_indirect_nonlocal_aix32"
10585 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
10586 (match_operand 1 "" "g,g"))
10587 (use (reg:SI 2))
10588 (use (reg:SI 11))
10589 (set (reg:SI 2)
10590 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10591 (clobber (match_scratch:SI 2 "=l,l"))]
10592 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10593 "b%T0l\;{l|lwz} 2,20(1)"
10594 [(set_attr "type" "jmpreg")
10595 (set_attr "length" "8")])
10596
10597 (define_insn "*call_nonlocal_aix32"
10598 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10599 (match_operand 1 "" "g"))
10600 (use (match_operand:SI 2 "immediate_operand" "O"))
10601 (clobber (match_scratch:SI 3 "=l"))]
10602 "TARGET_32BIT
10603 && DEFAULT_ABI == ABI_AIX
10604 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10605 "bl %z0\;%."
10606 [(set_attr "type" "branch")
10607 (set_attr "length" "8")])
10608
10609 (define_insn "*call_indirect_nonlocal_aix64"
10610 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
10611 (match_operand 1 "" "g,g"))
10612 (use (reg:DI 2))
10613 (use (reg:DI 11))
10614 (set (reg:DI 2)
10615 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10616 (clobber (match_scratch:SI 2 "=l,l"))]
10617 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10618 "b%T0l\;ld 2,40(1)"
10619 [(set_attr "type" "jmpreg")
10620 (set_attr "length" "8")])
10621
10622 (define_insn "*call_nonlocal_aix64"
10623 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10624 (match_operand 1 "" "g"))
10625 (use (match_operand:SI 2 "immediate_operand" "O"))
10626 (clobber (match_scratch:SI 3 "=l"))]
10627 "TARGET_64BIT
10628 && DEFAULT_ABI == ABI_AIX
10629 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10630 "bl %z0\;%."
10631 [(set_attr "type" "branch")
10632 (set_attr "length" "8")])
10633
10634 (define_insn "*call_value_indirect_nonlocal_aix32"
10635 [(set (match_operand 0 "" "")
10636 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
10637 (match_operand 2 "" "g,g")))
10638 (use (reg:SI 2))
10639 (use (reg:SI 11))
10640 (set (reg:SI 2)
10641 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10642 (clobber (match_scratch:SI 3 "=l,l"))]
10643 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10644 "b%T1l\;{l|lwz} 2,20(1)"
10645 [(set_attr "type" "jmpreg")
10646 (set_attr "length" "8")])
10647
10648 (define_insn "*call_value_nonlocal_aix32"
10649 [(set (match_operand 0 "" "")
10650 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10651 (match_operand 2 "" "g")))
10652 (use (match_operand:SI 3 "immediate_operand" "O"))
10653 (clobber (match_scratch:SI 4 "=l"))]
10654 "TARGET_32BIT
10655 && DEFAULT_ABI == ABI_AIX
10656 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10657 "bl %z1\;%."
10658 [(set_attr "type" "branch")
10659 (set_attr "length" "8")])
10660
10661 (define_insn "*call_value_indirect_nonlocal_aix64"
10662 [(set (match_operand 0 "" "")
10663 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
10664 (match_operand 2 "" "g,g")))
10665 (use (reg:DI 2))
10666 (use (reg:DI 11))
10667 (set (reg:DI 2)
10668 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10669 (clobber (match_scratch:SI 3 "=l,l"))]
10670 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10671 "b%T1l\;ld 2,40(1)"
10672 [(set_attr "type" "jmpreg")
10673 (set_attr "length" "8")])
10674
10675 (define_insn "*call_value_nonlocal_aix64"
10676 [(set (match_operand 0 "" "")
10677 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10678 (match_operand 2 "" "g")))
10679 (use (match_operand:SI 3 "immediate_operand" "O"))
10680 (clobber (match_scratch:SI 4 "=l"))]
10681 "TARGET_64BIT
10682 && DEFAULT_ABI == ABI_AIX
10683 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10684 "bl %z1\;%."
10685 [(set_attr "type" "branch")
10686 (set_attr "length" "8")])
10687
10688 ;; A function pointer under System V is just a normal pointer
10689 ;; operands[0] is the function pointer
10690 ;; operands[1] is the stack size to clean up
10691 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10692 ;; which indicates how to set cr1
10693
10694 (define_insn "*call_indirect_nonlocal_sysv"
10695 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l"))
10696 (match_operand 1 "" "g,g,g,g"))
10697 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
10698 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
10699 "DEFAULT_ABI == ABI_V4
10700 || DEFAULT_ABI == ABI_DARWIN"
10701 {
10702 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10703 output_asm_insn ("crxor 6,6,6", operands);
10704
10705 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10706 output_asm_insn ("creqv 6,6,6", operands);
10707
10708 return "b%T0l";
10709 }
10710 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10711 (set_attr "length" "4,4,8,8")])
10712
10713 (define_insn "*call_nonlocal_sysv"
10714 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10715 (match_operand 1 "" "g,g"))
10716 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10717 (clobber (match_scratch:SI 3 "=l,l"))]
10718 "(DEFAULT_ABI == ABI_DARWIN
10719 || (DEFAULT_ABI == ABI_V4
10720 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
10721 {
10722 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10723 output_asm_insn ("crxor 6,6,6", operands);
10724
10725 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10726 output_asm_insn ("creqv 6,6,6", operands);
10727
10728 #if TARGET_MACHO
10729 return output_call(insn, operands, 0, 2);
10730 #else
10731 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10732 {
10733 if (TARGET_SECURE_PLT && flag_pic == 2)
10734 /* The magic 32768 offset here and in the other sysv call insns
10735 corresponds to the offset of r30 in .got2, as given by LCTOC1.
10736 See sysv4.h:toc_section. */
10737 return "bl %z0+32768@plt";
10738 else
10739 return "bl %z0@plt";
10740 }
10741 else
10742 return "bl %z0";
10743 #endif
10744 }
10745 [(set_attr "type" "branch,branch")
10746 (set_attr "length" "4,8")])
10747
10748 (define_insn "*call_value_indirect_nonlocal_sysv"
10749 [(set (match_operand 0 "" "")
10750 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l"))
10751 (match_operand 2 "" "g,g,g,g")))
10752 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
10753 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
10754 "DEFAULT_ABI == ABI_V4
10755 || DEFAULT_ABI == ABI_DARWIN"
10756 {
10757 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10758 output_asm_insn ("crxor 6,6,6", operands);
10759
10760 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10761 output_asm_insn ("creqv 6,6,6", operands);
10762
10763 return "b%T1l";
10764 }
10765 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
10766 (set_attr "length" "4,4,8,8")])
10767
10768 (define_insn "*call_value_nonlocal_sysv"
10769 [(set (match_operand 0 "" "")
10770 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10771 (match_operand 2 "" "g,g")))
10772 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10773 (clobber (match_scratch:SI 4 "=l,l"))]
10774 "(DEFAULT_ABI == ABI_DARWIN
10775 || (DEFAULT_ABI == ABI_V4
10776 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
10777 {
10778 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10779 output_asm_insn ("crxor 6,6,6", operands);
10780
10781 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10782 output_asm_insn ("creqv 6,6,6", operands);
10783
10784 #if TARGET_MACHO
10785 return output_call(insn, operands, 1, 3);
10786 #else
10787 if (DEFAULT_ABI == ABI_V4 && flag_pic)
10788 {
10789 if (TARGET_SECURE_PLT && flag_pic == 2)
10790 return "bl %z1+32768@plt";
10791 else
10792 return "bl %z1@plt";
10793 }
10794 else
10795 return "bl %z1";
10796 #endif
10797 }
10798 [(set_attr "type" "branch,branch")
10799 (set_attr "length" "4,8")])
10800
10801 ;; Call subroutine returning any type.
10802 (define_expand "untyped_call"
10803 [(parallel [(call (match_operand 0 "" "")
10804 (const_int 0))
10805 (match_operand 1 "" "")
10806 (match_operand 2 "" "")])]
10807 ""
10808 "
10809 {
10810 int i;
10811
10812 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
10813
10814 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10815 {
10816 rtx set = XVECEXP (operands[2], 0, i);
10817 emit_move_insn (SET_DEST (set), SET_SRC (set));
10818 }
10819
10820 /* The optimizer does not know that the call sets the function value
10821 registers we stored in the result block. We avoid problems by
10822 claiming that all hard registers are used and clobbered at this
10823 point. */
10824 emit_insn (gen_blockage ());
10825
10826 DONE;
10827 }")
10828
10829 ;; sibling call patterns
10830 (define_expand "sibcall"
10831 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10832 (match_operand 1 "" ""))
10833 (use (match_operand 2 "" ""))
10834 (use (match_operand 3 "" ""))
10835 (return)])]
10836 ""
10837 "
10838 {
10839 #if TARGET_MACHO
10840 if (MACHOPIC_INDIRECT)
10841 operands[0] = machopic_indirect_call_target (operands[0]);
10842 #endif
10843
10844 gcc_assert (GET_CODE (operands[0]) == MEM);
10845 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10846
10847 operands[0] = XEXP (operands[0], 0);
10848 operands[3] = gen_reg_rtx (SImode);
10849
10850 }")
10851
10852 ;; this and similar patterns must be marked as using LR, otherwise
10853 ;; dataflow will try to delete the store into it. This is true
10854 ;; even when the actual reg to jump to is in CTR, when LR was
10855 ;; saved and restored around the PIC-setting BCL.
10856 (define_insn "*sibcall_local32"
10857 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10858 (match_operand 1 "" "g,g"))
10859 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10860 (use (match_operand:SI 3 "register_operand" "l,l"))
10861 (return)]
10862 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10863 "*
10864 {
10865 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10866 output_asm_insn (\"crxor 6,6,6\", operands);
10867
10868 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10869 output_asm_insn (\"creqv 6,6,6\", operands);
10870
10871 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10872 }"
10873 [(set_attr "type" "branch")
10874 (set_attr "length" "4,8")])
10875
10876 (define_insn "*sibcall_local64"
10877 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10878 (match_operand 1 "" "g,g"))
10879 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10880 (use (match_operand:SI 3 "register_operand" "l,l"))
10881 (return)]
10882 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10883 "*
10884 {
10885 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10886 output_asm_insn (\"crxor 6,6,6\", operands);
10887
10888 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10889 output_asm_insn (\"creqv 6,6,6\", operands);
10890
10891 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
10892 }"
10893 [(set_attr "type" "branch")
10894 (set_attr "length" "4,8")])
10895
10896 (define_insn "*sibcall_value_local32"
10897 [(set (match_operand 0 "" "")
10898 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10899 (match_operand 2 "" "g,g")))
10900 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10901 (use (match_operand:SI 4 "register_operand" "l,l"))
10902 (return)]
10903 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10904 "*
10905 {
10906 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10907 output_asm_insn (\"crxor 6,6,6\", operands);
10908
10909 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10910 output_asm_insn (\"creqv 6,6,6\", operands);
10911
10912 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10913 }"
10914 [(set_attr "type" "branch")
10915 (set_attr "length" "4,8")])
10916
10917
10918 (define_insn "*sibcall_value_local64"
10919 [(set (match_operand 0 "" "")
10920 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10921 (match_operand 2 "" "g,g")))
10922 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10923 (use (match_operand:SI 4 "register_operand" "l,l"))
10924 (return)]
10925 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10926 "*
10927 {
10928 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10929 output_asm_insn (\"crxor 6,6,6\", operands);
10930
10931 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10932 output_asm_insn (\"creqv 6,6,6\", operands);
10933
10934 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
10935 }"
10936 [(set_attr "type" "branch")
10937 (set_attr "length" "4,8")])
10938
10939 (define_insn "*sibcall_nonlocal_aix32"
10940 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10941 (match_operand 1 "" "g"))
10942 (use (match_operand:SI 2 "immediate_operand" "O"))
10943 (use (match_operand:SI 3 "register_operand" "l"))
10944 (return)]
10945 "TARGET_32BIT
10946 && DEFAULT_ABI == ABI_AIX
10947 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10948 "b %z0"
10949 [(set_attr "type" "branch")
10950 (set_attr "length" "4")])
10951
10952 (define_insn "*sibcall_nonlocal_aix64"
10953 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10954 (match_operand 1 "" "g"))
10955 (use (match_operand:SI 2 "immediate_operand" "O"))
10956 (use (match_operand:SI 3 "register_operand" "l"))
10957 (return)]
10958 "TARGET_64BIT
10959 && DEFAULT_ABI == ABI_AIX
10960 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10961 "b %z0"
10962 [(set_attr "type" "branch")
10963 (set_attr "length" "4")])
10964
10965 (define_insn "*sibcall_value_nonlocal_aix32"
10966 [(set (match_operand 0 "" "")
10967 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10968 (match_operand 2 "" "g")))
10969 (use (match_operand:SI 3 "immediate_operand" "O"))
10970 (use (match_operand:SI 4 "register_operand" "l"))
10971 (return)]
10972 "TARGET_32BIT
10973 && DEFAULT_ABI == ABI_AIX
10974 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10975 "b %z1"
10976 [(set_attr "type" "branch")
10977 (set_attr "length" "4")])
10978
10979 (define_insn "*sibcall_value_nonlocal_aix64"
10980 [(set (match_operand 0 "" "")
10981 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10982 (match_operand 2 "" "g")))
10983 (use (match_operand:SI 3 "immediate_operand" "O"))
10984 (use (match_operand:SI 4 "register_operand" "l"))
10985 (return)]
10986 "TARGET_64BIT
10987 && DEFAULT_ABI == ABI_AIX
10988 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10989 "b %z1"
10990 [(set_attr "type" "branch")
10991 (set_attr "length" "4")])
10992
10993 (define_insn "*sibcall_nonlocal_sysv"
10994 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10995 (match_operand 1 "" ""))
10996 (use (match_operand 2 "immediate_operand" "O,n"))
10997 (use (match_operand:SI 3 "register_operand" "l,l"))
10998 (return)]
10999 "(DEFAULT_ABI == ABI_DARWIN
11000 || DEFAULT_ABI == ABI_V4)
11001 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11002 "*
11003 {
11004 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11005 output_asm_insn (\"crxor 6,6,6\", operands);
11006
11007 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11008 output_asm_insn (\"creqv 6,6,6\", operands);
11009
11010 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11011 {
11012 if (TARGET_SECURE_PLT && flag_pic == 2)
11013 return \"b %z0+32768@plt\";
11014 else
11015 return \"b %z0@plt\";
11016 }
11017 else
11018 return \"b %z0\";
11019 }"
11020 [(set_attr "type" "branch,branch")
11021 (set_attr "length" "4,8")])
11022
11023 (define_expand "sibcall_value"
11024 [(parallel [(set (match_operand 0 "register_operand" "")
11025 (call (mem:SI (match_operand 1 "address_operand" ""))
11026 (match_operand 2 "" "")))
11027 (use (match_operand 3 "" ""))
11028 (use (match_operand 4 "" ""))
11029 (return)])]
11030 ""
11031 "
11032 {
11033 #if TARGET_MACHO
11034 if (MACHOPIC_INDIRECT)
11035 operands[1] = machopic_indirect_call_target (operands[1]);
11036 #endif
11037
11038 gcc_assert (GET_CODE (operands[1]) == MEM);
11039 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11040
11041 operands[1] = XEXP (operands[1], 0);
11042 operands[4] = gen_reg_rtx (SImode);
11043
11044 }")
11045
11046 (define_insn "*sibcall_value_nonlocal_sysv"
11047 [(set (match_operand 0 "" "")
11048 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
11049 (match_operand 2 "" "")))
11050 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11051 (use (match_operand:SI 4 "register_operand" "l,l"))
11052 (return)]
11053 "(DEFAULT_ABI == ABI_DARWIN
11054 || DEFAULT_ABI == ABI_V4)
11055 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11056 "*
11057 {
11058 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11059 output_asm_insn (\"crxor 6,6,6\", operands);
11060
11061 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11062 output_asm_insn (\"creqv 6,6,6\", operands);
11063
11064 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11065 {
11066 if (TARGET_SECURE_PLT && flag_pic == 2)
11067 return \"b %z1+32768@plt\";
11068 else
11069 return \"b %z1@plt\";
11070 }
11071 else
11072 return \"b %z1\";
11073 }"
11074 [(set_attr "type" "branch,branch")
11075 (set_attr "length" "4,8")])
11076
11077 (define_expand "sibcall_epilogue"
11078 [(use (const_int 0))]
11079 "TARGET_SCHED_PROLOG"
11080 "
11081 {
11082 rs6000_emit_epilogue (TRUE);
11083 DONE;
11084 }")
11085
11086 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11087 ;; all of memory. This blocks insns from being moved across this point.
11088
11089 (define_insn "blockage"
11090 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11091 ""
11092 "")
11093 \f
11094 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11095 ;; signed & unsigned, and one type of branch.
11096 ;;
11097 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11098 ;; insns, and branches. We store the operands of compares until we see
11099 ;; how it is used.
11100 (define_expand "cmp<mode>"
11101 [(set (cc0)
11102 (compare (match_operand:GPR 0 "gpc_reg_operand" "")
11103 (match_operand:GPR 1 "reg_or_short_operand" "")))]
11104 ""
11105 "
11106 {
11107 /* Take care of the possibility that operands[1] might be negative but
11108 this might be a logical operation. That insn doesn't exist. */
11109 if (GET_CODE (operands[1]) == CONST_INT
11110 && INTVAL (operands[1]) < 0)
11111 operands[1] = force_reg (<MODE>mode, operands[1]);
11112
11113 rs6000_compare_op0 = operands[0];
11114 rs6000_compare_op1 = operands[1];
11115 rs6000_compare_fp_p = 0;
11116 DONE;
11117 }")
11118
11119 (define_expand "cmp<mode>"
11120 [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "")
11121 (match_operand:FP 1 "gpc_reg_operand" "")))]
11122 ""
11123 "
11124 {
11125 rs6000_compare_op0 = operands[0];
11126 rs6000_compare_op1 = operands[1];
11127 rs6000_compare_fp_p = 1;
11128 DONE;
11129 }")
11130
11131 (define_expand "beq"
11132 [(use (match_operand 0 "" ""))]
11133 ""
11134 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11135
11136 (define_expand "bne"
11137 [(use (match_operand 0 "" ""))]
11138 ""
11139 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11140
11141 (define_expand "bge"
11142 [(use (match_operand 0 "" ""))]
11143 ""
11144 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11145
11146 (define_expand "bgt"
11147 [(use (match_operand 0 "" ""))]
11148 ""
11149 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11150
11151 (define_expand "ble"
11152 [(use (match_operand 0 "" ""))]
11153 ""
11154 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11155
11156 (define_expand "blt"
11157 [(use (match_operand 0 "" ""))]
11158 ""
11159 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11160
11161 (define_expand "bgeu"
11162 [(use (match_operand 0 "" ""))]
11163 ""
11164 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11165
11166 (define_expand "bgtu"
11167 [(use (match_operand 0 "" ""))]
11168 ""
11169 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11170
11171 (define_expand "bleu"
11172 [(use (match_operand 0 "" ""))]
11173 ""
11174 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11175
11176 (define_expand "bltu"
11177 [(use (match_operand 0 "" ""))]
11178 ""
11179 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11180
11181 (define_expand "bunordered"
11182 [(use (match_operand 0 "" ""))]
11183 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11184 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11185
11186 (define_expand "bordered"
11187 [(use (match_operand 0 "" ""))]
11188 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11189 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11190
11191 (define_expand "buneq"
11192 [(use (match_operand 0 "" ""))]
11193 ""
11194 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11195
11196 (define_expand "bunge"
11197 [(use (match_operand 0 "" ""))]
11198 ""
11199 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11200
11201 (define_expand "bungt"
11202 [(use (match_operand 0 "" ""))]
11203 ""
11204 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11205
11206 (define_expand "bunle"
11207 [(use (match_operand 0 "" ""))]
11208 ""
11209 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11210
11211 (define_expand "bunlt"
11212 [(use (match_operand 0 "" ""))]
11213 ""
11214 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11215
11216 (define_expand "bltgt"
11217 [(use (match_operand 0 "" ""))]
11218 ""
11219 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11220
11221 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11222 ;; For SEQ, likewise, except that comparisons with zero should be done
11223 ;; with an scc insns. However, due to the order that combine see the
11224 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11225 ;; the cases we don't want to handle.
11226 (define_expand "seq"
11227 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11228 ""
11229 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11230
11231 (define_expand "sne"
11232 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11233 ""
11234 "
11235 {
11236 if (! rs6000_compare_fp_p)
11237 FAIL;
11238
11239 rs6000_emit_sCOND (NE, operands[0]);
11240 DONE;
11241 }")
11242
11243 ;; A >= 0 is best done the portable way for A an integer.
11244 (define_expand "sge"
11245 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11246 ""
11247 "
11248 {
11249 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11250 FAIL;
11251
11252 rs6000_emit_sCOND (GE, operands[0]);
11253 DONE;
11254 }")
11255
11256 ;; A > 0 is best done using the portable sequence, so fail in that case.
11257 (define_expand "sgt"
11258 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11259 ""
11260 "
11261 {
11262 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11263 FAIL;
11264
11265 rs6000_emit_sCOND (GT, operands[0]);
11266 DONE;
11267 }")
11268
11269 ;; A <= 0 is best done the portable way for A an integer.
11270 (define_expand "sle"
11271 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11272 ""
11273 "
11274 {
11275 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11276 FAIL;
11277
11278 rs6000_emit_sCOND (LE, operands[0]);
11279 DONE;
11280 }")
11281
11282 ;; A < 0 is best done in the portable way for A an integer.
11283 (define_expand "slt"
11284 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11285 ""
11286 "
11287 {
11288 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11289 FAIL;
11290
11291 rs6000_emit_sCOND (LT, operands[0]);
11292 DONE;
11293 }")
11294
11295 (define_expand "sgeu"
11296 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11297 ""
11298 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11299
11300 (define_expand "sgtu"
11301 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11302 ""
11303 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11304
11305 (define_expand "sleu"
11306 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11307 ""
11308 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11309
11310 (define_expand "sltu"
11311 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11312 ""
11313 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11314
11315 (define_expand "sunordered"
11316 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11317 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11318 "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }")
11319
11320 (define_expand "sordered"
11321 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11322 "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)"
11323 "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }")
11324
11325 (define_expand "suneq"
11326 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11327 ""
11328 "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }")
11329
11330 (define_expand "sunge"
11331 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11332 ""
11333 "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }")
11334
11335 (define_expand "sungt"
11336 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11337 ""
11338 "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }")
11339
11340 (define_expand "sunle"
11341 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11342 ""
11343 "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }")
11344
11345 (define_expand "sunlt"
11346 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11347 ""
11348 "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }")
11349
11350 (define_expand "sltgt"
11351 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11352 ""
11353 "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }")
11354
11355 (define_expand "stack_protect_set"
11356 [(match_operand 0 "memory_operand" "")
11357 (match_operand 1 "memory_operand" "")]
11358 ""
11359 {
11360 #ifdef TARGET_THREAD_SSP_OFFSET
11361 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11362 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11363 operands[1] = gen_rtx_MEM (Pmode, addr);
11364 #endif
11365 if (TARGET_64BIT)
11366 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11367 else
11368 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11369 DONE;
11370 })
11371
11372 (define_insn "stack_protect_setsi"
11373 [(set (match_operand:SI 0 "memory_operand" "=m")
11374 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11375 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11376 "TARGET_32BIT"
11377 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11378 [(set_attr "type" "three")
11379 (set_attr "length" "12")])
11380
11381 (define_insn "stack_protect_setdi"
11382 [(set (match_operand:DI 0 "memory_operand" "=m")
11383 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11384 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11385 "TARGET_64BIT"
11386 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11387 [(set_attr "type" "three")
11388 (set_attr "length" "12")])
11389
11390 (define_expand "stack_protect_test"
11391 [(match_operand 0 "memory_operand" "")
11392 (match_operand 1 "memory_operand" "")
11393 (match_operand 2 "" "")]
11394 ""
11395 {
11396 #ifdef TARGET_THREAD_SSP_OFFSET
11397 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11398 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11399 operands[1] = gen_rtx_MEM (Pmode, addr);
11400 #endif
11401 rs6000_compare_op0 = operands[0];
11402 rs6000_compare_op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]),
11403 UNSPEC_SP_TEST);
11404 rs6000_compare_fp_p = 0;
11405 emit_jump_insn (gen_beq (operands[2]));
11406 DONE;
11407 })
11408
11409 (define_insn "stack_protect_testsi"
11410 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11411 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11412 (match_operand:SI 2 "memory_operand" "m,m")]
11413 UNSPEC_SP_TEST))
11414 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11415 (clobber (match_scratch:SI 3 "=&r,&r"))]
11416 "TARGET_32BIT"
11417 "@
11418 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11419 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11420 [(set_attr "length" "16,20")])
11421
11422 (define_insn "stack_protect_testdi"
11423 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11424 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
11425 (match_operand:DI 2 "memory_operand" "m,m")]
11426 UNSPEC_SP_TEST))
11427 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11428 (clobber (match_scratch:DI 3 "=&r,&r"))]
11429 "TARGET_64BIT"
11430 "@
11431 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11432 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11433 [(set_attr "length" "16,20")])
11434
11435 \f
11436 ;; Here are the actual compare insns.
11437 (define_insn "*cmp<mode>_internal1"
11438 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11439 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11440 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11441 ""
11442 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11443 [(set_attr "type" "cmp")])
11444
11445 ;; If we are comparing a register for equality with a large constant,
11446 ;; we can do this with an XOR followed by a compare. But this is profitable
11447 ;; only if the large constant is only used for the comparison (and in this
11448 ;; case we already have a register to reuse as scratch).
11449 ;;
11450 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11451 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11452
11453 (define_peephole2
11454 [(set (match_operand:SI 0 "register_operand")
11455 (match_operand:SI 1 "logical_const_operand" ""))
11456 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11457 [(match_dup 0)
11458 (match_operand:SI 2 "logical_const_operand" "")]))
11459 (set (match_operand:CC 4 "cc_reg_operand" "")
11460 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11461 (match_dup 0)))
11462 (set (pc)
11463 (if_then_else (match_operator 6 "equality_operator"
11464 [(match_dup 4) (const_int 0)])
11465 (match_operand 7 "" "")
11466 (match_operand 8 "" "")))]
11467 "peep2_reg_dead_p (3, operands[0])
11468 && peep2_reg_dead_p (4, operands[4])"
11469 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11470 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11471 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11472
11473 {
11474 /* Get the constant we are comparing against, and see what it looks like
11475 when sign-extended from 16 to 32 bits. Then see what constant we could
11476 XOR with SEXTC to get the sign-extended value. */
11477 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11478 SImode,
11479 operands[1], operands[2]);
11480 HOST_WIDE_INT c = INTVAL (cnst);
11481 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11482 HOST_WIDE_INT xorv = c ^ sextc;
11483
11484 operands[9] = GEN_INT (xorv);
11485 operands[10] = GEN_INT (sextc);
11486 })
11487
11488 (define_insn "*cmpsi_internal2"
11489 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11490 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11491 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11492 ""
11493 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11494 [(set_attr "type" "cmp")])
11495
11496 (define_insn "*cmpdi_internal2"
11497 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11498 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11499 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11500 ""
11501 "cmpld%I2 %0,%1,%b2"
11502 [(set_attr "type" "cmp")])
11503
11504 ;; The following two insns don't exist as single insns, but if we provide
11505 ;; them, we can swap an add and compare, which will enable us to overlap more
11506 ;; of the required delay between a compare and branch. We generate code for
11507 ;; them by splitting.
11508
11509 (define_insn ""
11510 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11511 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11512 (match_operand:SI 2 "short_cint_operand" "i")))
11513 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11514 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11515 ""
11516 "#"
11517 [(set_attr "length" "8")])
11518
11519 (define_insn ""
11520 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11521 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11522 (match_operand:SI 2 "u_short_cint_operand" "i")))
11523 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11524 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11525 ""
11526 "#"
11527 [(set_attr "length" "8")])
11528
11529 (define_split
11530 [(set (match_operand:CC 3 "cc_reg_operand" "")
11531 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11532 (match_operand:SI 2 "short_cint_operand" "")))
11533 (set (match_operand:SI 0 "gpc_reg_operand" "")
11534 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11535 ""
11536 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11537 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11538
11539 (define_split
11540 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11541 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11542 (match_operand:SI 2 "u_short_cint_operand" "")))
11543 (set (match_operand:SI 0 "gpc_reg_operand" "")
11544 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11545 ""
11546 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11547 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11548
11549 (define_insn "*cmpsf_internal1"
11550 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11551 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11552 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11553 "TARGET_HARD_FLOAT && TARGET_FPRS"
11554 "fcmpu %0,%1,%2"
11555 [(set_attr "type" "fpcompare")])
11556
11557 (define_insn "*cmpdf_internal1"
11558 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11559 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11560 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11561 "TARGET_HARD_FLOAT && TARGET_FPRS"
11562 "fcmpu %0,%1,%2"
11563 [(set_attr "type" "fpcompare")])
11564
11565 ;; Only need to compare second words if first words equal
11566 (define_insn "*cmptf_internal1"
11567 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11568 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11569 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11570 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
11571 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11572 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
11573 [(set_attr "type" "fpcompare")
11574 (set_attr "length" "12")])
11575
11576 (define_insn_and_split "*cmptf_internal2"
11577 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11578 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11579 (match_operand:TF 2 "gpc_reg_operand" "f")))
11580 (clobber (match_scratch:DF 3 "=f"))
11581 (clobber (match_scratch:DF 4 "=f"))
11582 (clobber (match_scratch:DF 5 "=f"))
11583 (clobber (match_scratch:DF 6 "=f"))
11584 (clobber (match_scratch:DF 7 "=f"))
11585 (clobber (match_scratch:DF 8 "=f"))
11586 (clobber (match_scratch:DF 9 "=f"))
11587 (clobber (match_scratch:DF 10 "=f"))]
11588 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
11589 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11590 "#"
11591 "&& reload_completed"
11592 [(set (match_dup 3) (match_dup 13))
11593 (set (match_dup 4) (match_dup 14))
11594 (set (match_dup 9) (abs:DF (match_dup 5)))
11595 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
11596 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
11597 (label_ref (match_dup 11))
11598 (pc)))
11599 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
11600 (set (pc) (label_ref (match_dup 12)))
11601 (match_dup 11)
11602 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
11603 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
11604 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
11605 (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4)))
11606 (match_dup 12)]
11607 {
11608 REAL_VALUE_TYPE rv;
11609 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
11610 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
11611
11612 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
11613 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
11614 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
11615 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
11616 operands[11] = gen_label_rtx ();
11617 operands[12] = gen_label_rtx ();
11618 real_inf (&rv);
11619 operands[13] = force_const_mem (DFmode,
11620 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
11621 operands[14] = force_const_mem (DFmode,
11622 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
11623 DFmode));
11624 if (TARGET_TOC)
11625 {
11626 operands[13] = gen_const_mem (DFmode,
11627 create_TOC_reference (XEXP (operands[13], 0)));
11628 operands[14] = gen_const_mem (DFmode,
11629 create_TOC_reference (XEXP (operands[14], 0)));
11630 set_mem_alias_set (operands[13], get_TOC_alias_set ());
11631 set_mem_alias_set (operands[14], get_TOC_alias_set ());
11632 }
11633 })
11634 \f
11635 ;; Now we have the scc insns. We can do some combinations because of the
11636 ;; way the machine works.
11637 ;;
11638 ;; Note that this is probably faster if we can put an insn between the
11639 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11640 ;; cases the insns below which don't use an intermediate CR field will
11641 ;; be used instead.
11642 (define_insn ""
11643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11644 (match_operator:SI 1 "scc_comparison_operator"
11645 [(match_operand 2 "cc_reg_operand" "y")
11646 (const_int 0)]))]
11647 ""
11648 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11649 [(set (attr "type")
11650 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11651 (const_string "mfcrf")
11652 ]
11653 (const_string "mfcr")))
11654 (set_attr "length" "8")])
11655
11656 ;; Same as above, but get the GT bit.
11657 (define_insn "move_from_CR_gt_bit"
11658 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11659 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
11660 "TARGET_E500"
11661 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
11662 [(set_attr "type" "mfcr")
11663 (set_attr "length" "8")])
11664
11665 ;; Same as above, but get the OV/ORDERED bit.
11666 (define_insn "move_from_CR_ov_bit"
11667 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11668 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
11669 "TARGET_ISEL"
11670 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11671 [(set_attr "type" "mfcr")
11672 (set_attr "length" "8")])
11673
11674 (define_insn ""
11675 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11676 (match_operator:DI 1 "scc_comparison_operator"
11677 [(match_operand 2 "cc_reg_operand" "y")
11678 (const_int 0)]))]
11679 "TARGET_POWERPC64"
11680 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
11681 [(set (attr "type")
11682 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11683 (const_string "mfcrf")
11684 ]
11685 (const_string "mfcr")))
11686 (set_attr "length" "8")])
11687
11688 (define_insn ""
11689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11690 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11691 [(match_operand 2 "cc_reg_operand" "y,y")
11692 (const_int 0)])
11693 (const_int 0)))
11694 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11695 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11696 "TARGET_32BIT"
11697 "@
11698 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
11699 #"
11700 [(set_attr "type" "delayed_compare")
11701 (set_attr "length" "8,16")])
11702
11703 (define_split
11704 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11705 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11706 [(match_operand 2 "cc_reg_operand" "")
11707 (const_int 0)])
11708 (const_int 0)))
11709 (set (match_operand:SI 3 "gpc_reg_operand" "")
11710 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11711 "TARGET_32BIT && reload_completed"
11712 [(set (match_dup 3)
11713 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11714 (set (match_dup 0)
11715 (compare:CC (match_dup 3)
11716 (const_int 0)))]
11717 "")
11718
11719 (define_insn ""
11720 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11721 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11722 [(match_operand 2 "cc_reg_operand" "y")
11723 (const_int 0)])
11724 (match_operand:SI 3 "const_int_operand" "n")))]
11725 ""
11726 "*
11727 {
11728 int is_bit = ccr_bit (operands[1], 1);
11729 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11730 int count;
11731
11732 if (is_bit >= put_bit)
11733 count = is_bit - put_bit;
11734 else
11735 count = 32 - (put_bit - is_bit);
11736
11737 operands[4] = GEN_INT (count);
11738 operands[5] = GEN_INT (put_bit);
11739
11740 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11741 }"
11742 [(set (attr "type")
11743 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
11744 (const_string "mfcrf")
11745 ]
11746 (const_string "mfcr")))
11747 (set_attr "length" "8")])
11748
11749 (define_insn ""
11750 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11751 (compare:CC
11752 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11753 [(match_operand 2 "cc_reg_operand" "y,y")
11754 (const_int 0)])
11755 (match_operand:SI 3 "const_int_operand" "n,n"))
11756 (const_int 0)))
11757 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11758 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11759 (match_dup 3)))]
11760 ""
11761 "*
11762 {
11763 int is_bit = ccr_bit (operands[1], 1);
11764 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11765 int count;
11766
11767 /* Force split for non-cc0 compare. */
11768 if (which_alternative == 1)
11769 return \"#\";
11770
11771 if (is_bit >= put_bit)
11772 count = is_bit - put_bit;
11773 else
11774 count = 32 - (put_bit - is_bit);
11775
11776 operands[5] = GEN_INT (count);
11777 operands[6] = GEN_INT (put_bit);
11778
11779 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11780 }"
11781 [(set_attr "type" "delayed_compare")
11782 (set_attr "length" "8,16")])
11783
11784 (define_split
11785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11786 (compare:CC
11787 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11788 [(match_operand 2 "cc_reg_operand" "")
11789 (const_int 0)])
11790 (match_operand:SI 3 "const_int_operand" ""))
11791 (const_int 0)))
11792 (set (match_operand:SI 4 "gpc_reg_operand" "")
11793 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11794 (match_dup 3)))]
11795 "reload_completed"
11796 [(set (match_dup 4)
11797 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11798 (match_dup 3)))
11799 (set (match_dup 0)
11800 (compare:CC (match_dup 4)
11801 (const_int 0)))]
11802 "")
11803
11804 ;; There is a 3 cycle delay between consecutive mfcr instructions
11805 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11806
11807 (define_peephole
11808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11809 (match_operator:SI 1 "scc_comparison_operator"
11810 [(match_operand 2 "cc_reg_operand" "y")
11811 (const_int 0)]))
11812 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11813 (match_operator:SI 4 "scc_comparison_operator"
11814 [(match_operand 5 "cc_reg_operand" "y")
11815 (const_int 0)]))]
11816 "REGNO (operands[2]) != REGNO (operands[5])"
11817 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11818 [(set_attr "type" "mfcr")
11819 (set_attr "length" "12")])
11820
11821 (define_peephole
11822 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11823 (match_operator:DI 1 "scc_comparison_operator"
11824 [(match_operand 2 "cc_reg_operand" "y")
11825 (const_int 0)]))
11826 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11827 (match_operator:DI 4 "scc_comparison_operator"
11828 [(match_operand 5 "cc_reg_operand" "y")
11829 (const_int 0)]))]
11830 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11831 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11832 [(set_attr "type" "mfcr")
11833 (set_attr "length" "12")])
11834
11835 ;; There are some scc insns that can be done directly, without a compare.
11836 ;; These are faster because they don't involve the communications between
11837 ;; the FXU and branch units. In fact, we will be replacing all of the
11838 ;; integer scc insns here or in the portable methods in emit_store_flag.
11839 ;;
11840 ;; Also support (neg (scc ..)) since that construct is used to replace
11841 ;; branches, (plus (scc ..) ..) since that construct is common and
11842 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11843 ;; cases where it is no more expensive than (neg (scc ..)).
11844
11845 ;; Have reload force a constant into a register for the simple insns that
11846 ;; otherwise won't accept constants. We do this because it is faster than
11847 ;; the cmp/mfcr sequence we would otherwise generate.
11848
11849 (define_mode_attr scc_eq_op2 [(SI "rKLI")
11850 (DI "rKJI")])
11851
11852 (define_insn_and_split "*eq<mode>"
11853 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
11854 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
11855 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
11856 "!TARGET_POWER"
11857 "#"
11858 "!TARGET_POWER"
11859 [(set (match_dup 0)
11860 (clz:GPR (match_dup 3)))
11861 (set (match_dup 0)
11862 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
11863 {
11864 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11865 {
11866 /* Use output operand as intermediate. */
11867 operands[3] = operands[0];
11868
11869 if (logical_operand (operands[2], <MODE>mode))
11870 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11871 gen_rtx_XOR (<MODE>mode,
11872 operands[1], operands[2])));
11873 else
11874 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
11875 gen_rtx_PLUS (<MODE>mode, operands[1],
11876 negate_rtx (<MODE>mode,
11877 operands[2]))));
11878 }
11879 else
11880 operands[3] = operands[1];
11881
11882 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11883 })
11884
11885 (define_insn_and_split "*eq<mode>_compare"
11886 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11887 (compare:CC
11888 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
11889 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
11890 (const_int 0)))
11891 (set (match_operand:P 0 "gpc_reg_operand" "=r")
11892 (eq:P (match_dup 1) (match_dup 2)))]
11893 "!TARGET_POWER && optimize_size"
11894 "#"
11895 "!TARGET_POWER && optimize_size"
11896 [(set (match_dup 0)
11897 (clz:P (match_dup 4)))
11898 (parallel [(set (match_dup 3)
11899 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
11900 (const_int 0)))
11901 (set (match_dup 0)
11902 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
11903 {
11904 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
11905 {
11906 /* Use output operand as intermediate. */
11907 operands[4] = operands[0];
11908
11909 if (logical_operand (operands[2], <MODE>mode))
11910 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11911 gen_rtx_XOR (<MODE>mode,
11912 operands[1], operands[2])));
11913 else
11914 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
11915 gen_rtx_PLUS (<MODE>mode, operands[1],
11916 negate_rtx (<MODE>mode,
11917 operands[2]))));
11918 }
11919 else
11920 operands[4] = operands[1];
11921
11922 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
11923 })
11924
11925 (define_insn "*eqsi_power"
11926 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11927 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11928 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11929 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11930 "TARGET_POWER"
11931 "@
11932 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11933 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11934 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11935 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11936 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11937 [(set_attr "type" "three,two,three,three,three")
11938 (set_attr "length" "12,8,12,12,12")])
11939
11940 ;; We have insns of the form shown by the first define_insn below. If
11941 ;; there is something inside the comparison operation, we must split it.
11942 (define_split
11943 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11944 (plus:SI (match_operator 1 "comparison_operator"
11945 [(match_operand:SI 2 "" "")
11946 (match_operand:SI 3
11947 "reg_or_cint_operand" "")])
11948 (match_operand:SI 4 "gpc_reg_operand" "")))
11949 (clobber (match_operand:SI 5 "register_operand" ""))]
11950 "! gpc_reg_operand (operands[2], SImode)"
11951 [(set (match_dup 5) (match_dup 2))
11952 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11953 (match_dup 4)))])
11954
11955 (define_insn "*plus_eqsi"
11956 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11957 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11958 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
11959 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11960 "TARGET_32BIT"
11961 "@
11962 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11963 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11964 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11965 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11966 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11967 [(set_attr "type" "three,two,three,three,three")
11968 (set_attr "length" "12,8,12,12,12")])
11969
11970 (define_insn "*compare_plus_eqsi"
11971 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11972 (compare:CC
11973 (plus:SI
11974 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11975 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
11976 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11977 (const_int 0)))
11978 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11979 "TARGET_32BIT && optimize_size"
11980 "@
11981 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11982 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11983 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11984 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11985 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11986 #
11987 #
11988 #
11989 #
11990 #"
11991 [(set_attr "type" "compare")
11992 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11993
11994 (define_split
11995 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11996 (compare:CC
11997 (plus:SI
11998 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11999 (match_operand:SI 2 "scc_eq_operand" ""))
12000 (match_operand:SI 3 "gpc_reg_operand" ""))
12001 (const_int 0)))
12002 (clobber (match_scratch:SI 4 ""))]
12003 "TARGET_32BIT && optimize_size && reload_completed"
12004 [(set (match_dup 4)
12005 (plus:SI (eq:SI (match_dup 1)
12006 (match_dup 2))
12007 (match_dup 3)))
12008 (set (match_dup 0)
12009 (compare:CC (match_dup 4)
12010 (const_int 0)))]
12011 "")
12012
12013 (define_insn "*plus_eqsi_compare"
12014 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12015 (compare:CC
12016 (plus:SI
12017 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12018 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12019 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12020 (const_int 0)))
12021 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12022 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12023 "TARGET_32BIT && optimize_size"
12024 "@
12025 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12026 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12027 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12028 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12029 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12030 #
12031 #
12032 #
12033 #
12034 #"
12035 [(set_attr "type" "compare")
12036 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12037
12038 (define_split
12039 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12040 (compare:CC
12041 (plus:SI
12042 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12043 (match_operand:SI 2 "scc_eq_operand" ""))
12044 (match_operand:SI 3 "gpc_reg_operand" ""))
12045 (const_int 0)))
12046 (set (match_operand:SI 0 "gpc_reg_operand" "")
12047 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12048 "TARGET_32BIT && optimize_size && reload_completed"
12049 [(set (match_dup 0)
12050 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12051 (set (match_dup 4)
12052 (compare:CC (match_dup 0)
12053 (const_int 0)))]
12054 "")
12055
12056 (define_insn "*neg_eq0<mode>"
12057 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12058 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12059 (const_int 0))))]
12060 ""
12061 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12062 [(set_attr "type" "two")
12063 (set_attr "length" "8")])
12064
12065 (define_insn_and_split "*neg_eq<mode>"
12066 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12067 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12068 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12069 ""
12070 "#"
12071 ""
12072 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12073 {
12074 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12075 {
12076 /* Use output operand as intermediate. */
12077 operands[3] = operands[0];
12078
12079 if (logical_operand (operands[2], <MODE>mode))
12080 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12081 gen_rtx_XOR (<MODE>mode,
12082 operands[1], operands[2])));
12083 else
12084 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12085 gen_rtx_PLUS (<MODE>mode, operands[1],
12086 negate_rtx (<MODE>mode,
12087 operands[2]))));
12088 }
12089 else
12090 operands[3] = operands[1];
12091 })
12092
12093 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12094 ;; since it nabs/sr is just as fast.
12095 (define_insn "*ne0si"
12096 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12097 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12098 (const_int 31)))
12099 (clobber (match_scratch:SI 2 "=&r"))]
12100 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
12101 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12102 [(set_attr "type" "two")
12103 (set_attr "length" "8")])
12104
12105 (define_insn "*ne0di"
12106 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12107 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12108 (const_int 63)))
12109 (clobber (match_scratch:DI 2 "=&r"))]
12110 "TARGET_64BIT"
12111 "addic %2,%1,-1\;subfe %0,%2,%1"
12112 [(set_attr "type" "two")
12113 (set_attr "length" "8")])
12114
12115 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12116 (define_insn "*plus_ne0si"
12117 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12118 (plus:SI (lshiftrt:SI
12119 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12120 (const_int 31))
12121 (match_operand:SI 2 "gpc_reg_operand" "r")))
12122 (clobber (match_scratch:SI 3 "=&r"))]
12123 "TARGET_32BIT"
12124 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12125 [(set_attr "type" "two")
12126 (set_attr "length" "8")])
12127
12128 (define_insn "*plus_ne0di"
12129 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12130 (plus:DI (lshiftrt:DI
12131 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12132 (const_int 63))
12133 (match_operand:DI 2 "gpc_reg_operand" "r")))
12134 (clobber (match_scratch:DI 3 "=&r"))]
12135 "TARGET_64BIT"
12136 "addic %3,%1,-1\;addze %0,%2"
12137 [(set_attr "type" "two")
12138 (set_attr "length" "8")])
12139
12140 (define_insn "*compare_plus_ne0si"
12141 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12142 (compare:CC
12143 (plus:SI (lshiftrt:SI
12144 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12145 (const_int 31))
12146 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12147 (const_int 0)))
12148 (clobber (match_scratch:SI 3 "=&r,&r"))
12149 (clobber (match_scratch:SI 4 "=X,&r"))]
12150 "TARGET_32BIT"
12151 "@
12152 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12153 #"
12154 [(set_attr "type" "compare")
12155 (set_attr "length" "8,12")])
12156
12157 (define_split
12158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12159 (compare:CC
12160 (plus:SI (lshiftrt:SI
12161 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12162 (const_int 31))
12163 (match_operand:SI 2 "gpc_reg_operand" ""))
12164 (const_int 0)))
12165 (clobber (match_scratch:SI 3 ""))
12166 (clobber (match_scratch:SI 4 ""))]
12167 "TARGET_32BIT && reload_completed"
12168 [(parallel [(set (match_dup 3)
12169 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12170 (const_int 31))
12171 (match_dup 2)))
12172 (clobber (match_dup 4))])
12173 (set (match_dup 0)
12174 (compare:CC (match_dup 3)
12175 (const_int 0)))]
12176 "")
12177
12178 (define_insn "*compare_plus_ne0di"
12179 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12180 (compare:CC
12181 (plus:DI (lshiftrt:DI
12182 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12183 (const_int 63))
12184 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12185 (const_int 0)))
12186 (clobber (match_scratch:DI 3 "=&r,&r"))]
12187 "TARGET_64BIT"
12188 "@
12189 addic %3,%1,-1\;addze. %3,%2
12190 #"
12191 [(set_attr "type" "compare")
12192 (set_attr "length" "8,12")])
12193
12194 (define_split
12195 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12196 (compare:CC
12197 (plus:DI (lshiftrt:DI
12198 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12199 (const_int 63))
12200 (match_operand:DI 2 "gpc_reg_operand" ""))
12201 (const_int 0)))
12202 (clobber (match_scratch:DI 3 ""))]
12203 "TARGET_64BIT && reload_completed"
12204 [(set (match_dup 3)
12205 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12206 (const_int 63))
12207 (match_dup 2)))
12208 (set (match_dup 0)
12209 (compare:CC (match_dup 3)
12210 (const_int 0)))]
12211 "")
12212
12213 (define_insn "*plus_ne0si_compare"
12214 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12215 (compare:CC
12216 (plus:SI (lshiftrt:SI
12217 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12218 (const_int 31))
12219 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12220 (const_int 0)))
12221 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12222 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12223 (match_dup 2)))
12224 (clobber (match_scratch:SI 3 "=&r,&r"))]
12225 "TARGET_32BIT"
12226 "@
12227 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12228 #"
12229 [(set_attr "type" "compare")
12230 (set_attr "length" "8,12")])
12231
12232 (define_split
12233 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12234 (compare:CC
12235 (plus:SI (lshiftrt:SI
12236 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12237 (const_int 31))
12238 (match_operand:SI 2 "gpc_reg_operand" ""))
12239 (const_int 0)))
12240 (set (match_operand:SI 0 "gpc_reg_operand" "")
12241 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12242 (match_dup 2)))
12243 (clobber (match_scratch:SI 3 ""))]
12244 "TARGET_32BIT && reload_completed"
12245 [(parallel [(set (match_dup 0)
12246 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12247 (match_dup 2)))
12248 (clobber (match_dup 3))])
12249 (set (match_dup 4)
12250 (compare:CC (match_dup 0)
12251 (const_int 0)))]
12252 "")
12253
12254 (define_insn "*plus_ne0di_compare"
12255 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12256 (compare:CC
12257 (plus:DI (lshiftrt:DI
12258 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12259 (const_int 63))
12260 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12261 (const_int 0)))
12262 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12263 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12264 (match_dup 2)))
12265 (clobber (match_scratch:DI 3 "=&r,&r"))]
12266 "TARGET_64BIT"
12267 "@
12268 addic %3,%1,-1\;addze. %0,%2
12269 #"
12270 [(set_attr "type" "compare")
12271 (set_attr "length" "8,12")])
12272
12273 (define_split
12274 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12275 (compare:CC
12276 (plus:DI (lshiftrt:DI
12277 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12278 (const_int 63))
12279 (match_operand:DI 2 "gpc_reg_operand" ""))
12280 (const_int 0)))
12281 (set (match_operand:DI 0 "gpc_reg_operand" "")
12282 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12283 (match_dup 2)))
12284 (clobber (match_scratch:DI 3 ""))]
12285 "TARGET_64BIT && reload_completed"
12286 [(parallel [(set (match_dup 0)
12287 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12288 (match_dup 2)))
12289 (clobber (match_dup 3))])
12290 (set (match_dup 4)
12291 (compare:CC (match_dup 0)
12292 (const_int 0)))]
12293 "")
12294
12295 (define_insn ""
12296 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12297 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12298 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12299 (clobber (match_scratch:SI 3 "=r,X"))]
12300 "TARGET_POWER"
12301 "@
12302 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12303 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12304 [(set_attr "length" "12")])
12305
12306 (define_insn ""
12307 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12308 (compare:CC
12309 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12310 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12311 (const_int 0)))
12312 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12313 (le:SI (match_dup 1) (match_dup 2)))
12314 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12315 "TARGET_POWER"
12316 "@
12317 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12318 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12319 #
12320 #"
12321 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12322 (set_attr "length" "12,12,16,16")])
12323
12324 (define_split
12325 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12326 (compare:CC
12327 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12328 (match_operand:SI 2 "reg_or_short_operand" ""))
12329 (const_int 0)))
12330 (set (match_operand:SI 0 "gpc_reg_operand" "")
12331 (le:SI (match_dup 1) (match_dup 2)))
12332 (clobber (match_scratch:SI 3 ""))]
12333 "TARGET_POWER && reload_completed"
12334 [(parallel [(set (match_dup 0)
12335 (le:SI (match_dup 1) (match_dup 2)))
12336 (clobber (match_dup 3))])
12337 (set (match_dup 4)
12338 (compare:CC (match_dup 0)
12339 (const_int 0)))]
12340 "")
12341
12342 (define_insn ""
12343 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12344 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12345 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12346 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12347 "TARGET_POWER"
12348 "@
12349 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12350 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12351 [(set_attr "length" "12")])
12352
12353 (define_insn ""
12354 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12355 (compare:CC
12356 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12357 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12358 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12359 (const_int 0)))
12360 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12361 "TARGET_POWER"
12362 "@
12363 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12364 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12365 #
12366 #"
12367 [(set_attr "type" "compare")
12368 (set_attr "length" "12,12,16,16")])
12369
12370 (define_split
12371 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12372 (compare:CC
12373 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12374 (match_operand:SI 2 "reg_or_short_operand" ""))
12375 (match_operand:SI 3 "gpc_reg_operand" ""))
12376 (const_int 0)))
12377 (clobber (match_scratch:SI 4 ""))]
12378 "TARGET_POWER && reload_completed"
12379 [(set (match_dup 4)
12380 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12381 (match_dup 3)))
12382 (set (match_dup 0)
12383 (compare:CC (match_dup 4)
12384 (const_int 0)))]
12385 "")
12386
12387 (define_insn ""
12388 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12389 (compare:CC
12390 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12391 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12392 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12393 (const_int 0)))
12394 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12395 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12396 "TARGET_POWER"
12397 "@
12398 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12399 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12400 #
12401 #"
12402 [(set_attr "type" "compare")
12403 (set_attr "length" "12,12,16,16")])
12404
12405 (define_split
12406 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12407 (compare:CC
12408 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12409 (match_operand:SI 2 "reg_or_short_operand" ""))
12410 (match_operand:SI 3 "gpc_reg_operand" ""))
12411 (const_int 0)))
12412 (set (match_operand:SI 0 "gpc_reg_operand" "")
12413 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12414 "TARGET_POWER && reload_completed"
12415 [(set (match_dup 0)
12416 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12417 (set (match_dup 4)
12418 (compare:CC (match_dup 0)
12419 (const_int 0)))]
12420 "")
12421
12422 (define_insn ""
12423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12424 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12425 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12426 "TARGET_POWER"
12427 "@
12428 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12429 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12430 [(set_attr "length" "12")])
12431
12432 (define_insn "*leu<mode>"
12433 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12434 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12435 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12436 ""
12437 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12438 [(set_attr "type" "three")
12439 (set_attr "length" "12")])
12440
12441 (define_insn "*leu<mode>_compare"
12442 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12443 (compare:CC
12444 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12445 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12446 (const_int 0)))
12447 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12448 (leu:P (match_dup 1) (match_dup 2)))]
12449 ""
12450 "@
12451 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12452 #"
12453 [(set_attr "type" "compare")
12454 (set_attr "length" "12,16")])
12455
12456 (define_split
12457 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12458 (compare:CC
12459 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12460 (match_operand:P 2 "reg_or_short_operand" ""))
12461 (const_int 0)))
12462 (set (match_operand:P 0 "gpc_reg_operand" "")
12463 (leu:P (match_dup 1) (match_dup 2)))]
12464 "reload_completed"
12465 [(set (match_dup 0)
12466 (leu:P (match_dup 1) (match_dup 2)))
12467 (set (match_dup 3)
12468 (compare:CC (match_dup 0)
12469 (const_int 0)))]
12470 "")
12471
12472 (define_insn "*plus_leu<mode>"
12473 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12474 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12475 (match_operand:P 2 "reg_or_short_operand" "rI"))
12476 (match_operand:P 3 "gpc_reg_operand" "r")))]
12477 ""
12478 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12479 [(set_attr "type" "two")
12480 (set_attr "length" "8")])
12481
12482 (define_insn ""
12483 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12484 (compare:CC
12485 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12486 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12487 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12488 (const_int 0)))
12489 (clobber (match_scratch:SI 4 "=&r,&r"))]
12490 "TARGET_32BIT"
12491 "@
12492 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12493 #"
12494 [(set_attr "type" "compare")
12495 (set_attr "length" "8,12")])
12496
12497 (define_split
12498 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12499 (compare:CC
12500 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12501 (match_operand:SI 2 "reg_or_short_operand" ""))
12502 (match_operand:SI 3 "gpc_reg_operand" ""))
12503 (const_int 0)))
12504 (clobber (match_scratch:SI 4 ""))]
12505 "TARGET_32BIT && reload_completed"
12506 [(set (match_dup 4)
12507 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12508 (match_dup 3)))
12509 (set (match_dup 0)
12510 (compare:CC (match_dup 4)
12511 (const_int 0)))]
12512 "")
12513
12514 (define_insn ""
12515 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12516 (compare:CC
12517 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12518 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12519 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12520 (const_int 0)))
12521 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12522 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12523 "TARGET_32BIT"
12524 "@
12525 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12526 #"
12527 [(set_attr "type" "compare")
12528 (set_attr "length" "8,12")])
12529
12530 (define_split
12531 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12532 (compare:CC
12533 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12534 (match_operand:SI 2 "reg_or_short_operand" ""))
12535 (match_operand:SI 3 "gpc_reg_operand" ""))
12536 (const_int 0)))
12537 (set (match_operand:SI 0 "gpc_reg_operand" "")
12538 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12539 "TARGET_32BIT && reload_completed"
12540 [(set (match_dup 0)
12541 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12542 (set (match_dup 4)
12543 (compare:CC (match_dup 0)
12544 (const_int 0)))]
12545 "")
12546
12547 (define_insn "*neg_leu<mode>"
12548 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12549 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12550 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12551 ""
12552 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12553 [(set_attr "type" "three")
12554 (set_attr "length" "12")])
12555
12556 (define_insn "*and_neg_leu<mode>"
12557 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12558 (and:P (neg:P
12559 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12560 (match_operand:P 2 "reg_or_short_operand" "rI")))
12561 (match_operand:P 3 "gpc_reg_operand" "r")))]
12562 ""
12563 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12564 [(set_attr "type" "three")
12565 (set_attr "length" "12")])
12566
12567 (define_insn ""
12568 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12569 (compare:CC
12570 (and:SI (neg:SI
12571 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12572 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12573 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12574 (const_int 0)))
12575 (clobber (match_scratch:SI 4 "=&r,&r"))]
12576 "TARGET_32BIT"
12577 "@
12578 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12579 #"
12580 [(set_attr "type" "compare")
12581 (set_attr "length" "12,16")])
12582
12583 (define_split
12584 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12585 (compare:CC
12586 (and:SI (neg:SI
12587 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12588 (match_operand:SI 2 "reg_or_short_operand" "")))
12589 (match_operand:SI 3 "gpc_reg_operand" ""))
12590 (const_int 0)))
12591 (clobber (match_scratch:SI 4 ""))]
12592 "TARGET_32BIT && reload_completed"
12593 [(set (match_dup 4)
12594 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12595 (match_dup 3)))
12596 (set (match_dup 0)
12597 (compare:CC (match_dup 4)
12598 (const_int 0)))]
12599 "")
12600
12601 (define_insn ""
12602 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12603 (compare:CC
12604 (and:SI (neg:SI
12605 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12606 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12607 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12608 (const_int 0)))
12609 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12610 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12611 "TARGET_32BIT"
12612 "@
12613 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12614 #"
12615 [(set_attr "type" "compare")
12616 (set_attr "length" "12,16")])
12617
12618 (define_split
12619 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12620 (compare:CC
12621 (and:SI (neg:SI
12622 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12623 (match_operand:SI 2 "reg_or_short_operand" "")))
12624 (match_operand:SI 3 "gpc_reg_operand" ""))
12625 (const_int 0)))
12626 (set (match_operand:SI 0 "gpc_reg_operand" "")
12627 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12628 "TARGET_32BIT && reload_completed"
12629 [(set (match_dup 0)
12630 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12631 (match_dup 3)))
12632 (set (match_dup 4)
12633 (compare:CC (match_dup 0)
12634 (const_int 0)))]
12635 "")
12636
12637 (define_insn ""
12638 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12639 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12640 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12641 "TARGET_POWER"
12642 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12643 [(set_attr "length" "12")])
12644
12645 (define_insn ""
12646 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12647 (compare:CC
12648 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12649 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12650 (const_int 0)))
12651 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12652 (lt:SI (match_dup 1) (match_dup 2)))]
12653 "TARGET_POWER"
12654 "@
12655 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12656 #"
12657 [(set_attr "type" "delayed_compare")
12658 (set_attr "length" "12,16")])
12659
12660 (define_split
12661 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12662 (compare:CC
12663 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12664 (match_operand:SI 2 "reg_or_short_operand" ""))
12665 (const_int 0)))
12666 (set (match_operand:SI 0 "gpc_reg_operand" "")
12667 (lt:SI (match_dup 1) (match_dup 2)))]
12668 "TARGET_POWER && reload_completed"
12669 [(set (match_dup 0)
12670 (lt:SI (match_dup 1) (match_dup 2)))
12671 (set (match_dup 3)
12672 (compare:CC (match_dup 0)
12673 (const_int 0)))]
12674 "")
12675
12676 (define_insn ""
12677 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12678 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12679 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12680 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12681 "TARGET_POWER"
12682 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12683 [(set_attr "length" "12")])
12684
12685 (define_insn ""
12686 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12687 (compare:CC
12688 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12689 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12690 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12691 (const_int 0)))
12692 (clobber (match_scratch:SI 4 "=&r,&r"))]
12693 "TARGET_POWER"
12694 "@
12695 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12696 #"
12697 [(set_attr "type" "compare")
12698 (set_attr "length" "12,16")])
12699
12700 (define_split
12701 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12702 (compare:CC
12703 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12704 (match_operand:SI 2 "reg_or_short_operand" ""))
12705 (match_operand:SI 3 "gpc_reg_operand" ""))
12706 (const_int 0)))
12707 (clobber (match_scratch:SI 4 ""))]
12708 "TARGET_POWER && reload_completed"
12709 [(set (match_dup 4)
12710 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12711 (match_dup 3)))
12712 (set (match_dup 0)
12713 (compare:CC (match_dup 4)
12714 (const_int 0)))]
12715 "")
12716
12717 (define_insn ""
12718 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12719 (compare:CC
12720 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12721 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12722 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12723 (const_int 0)))
12724 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12725 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12726 "TARGET_POWER"
12727 "@
12728 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12729 #"
12730 [(set_attr "type" "compare")
12731 (set_attr "length" "12,16")])
12732
12733 (define_split
12734 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12735 (compare:CC
12736 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12737 (match_operand:SI 2 "reg_or_short_operand" ""))
12738 (match_operand:SI 3 "gpc_reg_operand" ""))
12739 (const_int 0)))
12740 (set (match_operand:SI 0 "gpc_reg_operand" "")
12741 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12742 "TARGET_POWER && reload_completed"
12743 [(set (match_dup 0)
12744 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12745 (set (match_dup 4)
12746 (compare:CC (match_dup 0)
12747 (const_int 0)))]
12748 "")
12749
12750 (define_insn ""
12751 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12752 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12753 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12754 "TARGET_POWER"
12755 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12756 [(set_attr "length" "12")])
12757
12758 (define_insn_and_split "*ltu<mode>"
12759 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12760 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12761 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12762 ""
12763 "#"
12764 ""
12765 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12766 (set (match_dup 0) (neg:P (match_dup 0)))]
12767 "")
12768
12769 (define_insn_and_split "*ltu<mode>_compare"
12770 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12771 (compare:CC
12772 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12773 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12774 (const_int 0)))
12775 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12776 (ltu:P (match_dup 1) (match_dup 2)))]
12777 ""
12778 "#"
12779 ""
12780 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12781 (parallel [(set (match_dup 3)
12782 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12783 (set (match_dup 0) (neg:P (match_dup 0)))])]
12784 "")
12785
12786 (define_insn_and_split "*plus_ltu<mode>"
12787 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12788 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12789 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12790 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12791 ""
12792 "#"
12793 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12794 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12795 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
12796 "")
12797
12798 (define_insn_and_split "*plus_ltu<mode>_compare"
12799 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12800 (compare:CC
12801 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12802 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12803 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
12804 (const_int 0)))
12805 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12806 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
12807 ""
12808 "#"
12809 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12810 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12811 (parallel [(set (match_dup 4)
12812 (compare:CC (minus:P (match_dup 3) (match_dup 0))
12813 (const_int 0)))
12814 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
12815 "")
12816
12817 (define_insn "*neg_ltu<mode>"
12818 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12819 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12820 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
12821 ""
12822 "@
12823 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12824 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12825 [(set_attr "type" "two")
12826 (set_attr "length" "8")])
12827
12828 (define_insn ""
12829 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12830 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12831 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12832 (clobber (match_scratch:SI 3 "=r"))]
12833 "TARGET_POWER"
12834 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12835 [(set_attr "length" "12")])
12836
12837 (define_insn ""
12838 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12839 (compare:CC
12840 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12841 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12842 (const_int 0)))
12843 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12844 (ge:SI (match_dup 1) (match_dup 2)))
12845 (clobber (match_scratch:SI 3 "=r,r"))]
12846 "TARGET_POWER"
12847 "@
12848 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12849 #"
12850 [(set_attr "type" "compare")
12851 (set_attr "length" "12,16")])
12852
12853 (define_split
12854 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12855 (compare:CC
12856 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12857 (match_operand:SI 2 "reg_or_short_operand" ""))
12858 (const_int 0)))
12859 (set (match_operand:SI 0 "gpc_reg_operand" "")
12860 (ge:SI (match_dup 1) (match_dup 2)))
12861 (clobber (match_scratch:SI 3 ""))]
12862 "TARGET_POWER && reload_completed"
12863 [(parallel [(set (match_dup 0)
12864 (ge:SI (match_dup 1) (match_dup 2)))
12865 (clobber (match_dup 3))])
12866 (set (match_dup 4)
12867 (compare:CC (match_dup 0)
12868 (const_int 0)))]
12869 "")
12870
12871 (define_insn ""
12872 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12873 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12874 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12875 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12876 "TARGET_POWER"
12877 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12878 [(set_attr "length" "12")])
12879
12880 (define_insn ""
12881 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12882 (compare:CC
12883 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12884 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12885 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12886 (const_int 0)))
12887 (clobber (match_scratch:SI 4 "=&r,&r"))]
12888 "TARGET_POWER"
12889 "@
12890 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12891 #"
12892 [(set_attr "type" "compare")
12893 (set_attr "length" "12,16")])
12894
12895 (define_split
12896 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12897 (compare:CC
12898 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12899 (match_operand:SI 2 "reg_or_short_operand" ""))
12900 (match_operand:SI 3 "gpc_reg_operand" ""))
12901 (const_int 0)))
12902 (clobber (match_scratch:SI 4 ""))]
12903 "TARGET_POWER && reload_completed"
12904 [(set (match_dup 4)
12905 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
12906 (match_dup 3)))
12907 (set (match_dup 0)
12908 (compare:CC (match_dup 4)
12909 (const_int 0)))]
12910 "")
12911
12912 (define_insn ""
12913 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12914 (compare:CC
12915 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12916 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12917 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12918 (const_int 0)))
12919 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12920 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12921 "TARGET_POWER"
12922 "@
12923 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12924 #"
12925 [(set_attr "type" "compare")
12926 (set_attr "length" "12,16")])
12927
12928 (define_split
12929 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12930 (compare:CC
12931 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12932 (match_operand:SI 2 "reg_or_short_operand" ""))
12933 (match_operand:SI 3 "gpc_reg_operand" ""))
12934 (const_int 0)))
12935 (set (match_operand:SI 0 "gpc_reg_operand" "")
12936 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12937 "TARGET_POWER && reload_completed"
12938 [(set (match_dup 0)
12939 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12940 (set (match_dup 4)
12941 (compare:CC (match_dup 0)
12942 (const_int 0)))]
12943 "")
12944
12945 (define_insn ""
12946 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12947 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12948 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12949 "TARGET_POWER"
12950 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12951 [(set_attr "length" "12")])
12952
12953 (define_insn "*geu<mode>"
12954 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12955 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12956 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12957 ""
12958 "@
12959 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12960 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12961 [(set_attr "type" "three")
12962 (set_attr "length" "12")])
12963
12964 (define_insn "*geu<mode>_compare"
12965 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12966 (compare:CC
12967 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12968 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12969 (const_int 0)))
12970 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12971 (geu:P (match_dup 1) (match_dup 2)))]
12972 ""
12973 "@
12974 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12975 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12976 #
12977 #"
12978 [(set_attr "type" "compare")
12979 (set_attr "length" "12,12,16,16")])
12980
12981 (define_split
12982 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12983 (compare:CC
12984 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
12985 (match_operand:P 2 "reg_or_neg_short_operand" ""))
12986 (const_int 0)))
12987 (set (match_operand:P 0 "gpc_reg_operand" "")
12988 (geu:P (match_dup 1) (match_dup 2)))]
12989 "reload_completed"
12990 [(set (match_dup 0)
12991 (geu:P (match_dup 1) (match_dup 2)))
12992 (set (match_dup 3)
12993 (compare:CC (match_dup 0)
12994 (const_int 0)))]
12995 "")
12996
12997 (define_insn "*plus_geu<mode>"
12998 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
12999 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13000 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13001 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13002 ""
13003 "@
13004 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13005 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13006 [(set_attr "type" "two")
13007 (set_attr "length" "8")])
13008
13009 (define_insn ""
13010 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13011 (compare:CC
13012 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13013 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13014 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13015 (const_int 0)))
13016 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13017 "TARGET_32BIT"
13018 "@
13019 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13020 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13021 #
13022 #"
13023 [(set_attr "type" "compare")
13024 (set_attr "length" "8,8,12,12")])
13025
13026 (define_split
13027 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13028 (compare:CC
13029 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13030 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13031 (match_operand:SI 3 "gpc_reg_operand" ""))
13032 (const_int 0)))
13033 (clobber (match_scratch:SI 4 ""))]
13034 "TARGET_32BIT && reload_completed"
13035 [(set (match_dup 4)
13036 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13037 (match_dup 3)))
13038 (set (match_dup 0)
13039 (compare:CC (match_dup 4)
13040 (const_int 0)))]
13041 "")
13042
13043 (define_insn ""
13044 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13045 (compare:CC
13046 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13047 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13048 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13049 (const_int 0)))
13050 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13051 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13052 "TARGET_32BIT"
13053 "@
13054 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13055 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13056 #
13057 #"
13058 [(set_attr "type" "compare")
13059 (set_attr "length" "8,8,12,12")])
13060
13061 (define_split
13062 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13063 (compare:CC
13064 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13065 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13066 (match_operand:SI 3 "gpc_reg_operand" ""))
13067 (const_int 0)))
13068 (set (match_operand:SI 0 "gpc_reg_operand" "")
13069 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13070 "TARGET_32BIT && reload_completed"
13071 [(set (match_dup 0)
13072 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13073 (set (match_dup 4)
13074 (compare:CC (match_dup 0)
13075 (const_int 0)))]
13076 "")
13077
13078 (define_insn "*neg_geu<mode>"
13079 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13080 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13081 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13082 ""
13083 "@
13084 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13085 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13086 [(set_attr "type" "three")
13087 (set_attr "length" "12")])
13088
13089 (define_insn "*and_neg_geu<mode>"
13090 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13091 (and:P (neg:P
13092 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13093 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13094 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13095 ""
13096 "@
13097 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13098 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13099 [(set_attr "type" "three")
13100 (set_attr "length" "12")])
13101
13102 (define_insn ""
13103 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13104 (compare:CC
13105 (and:SI (neg:SI
13106 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13107 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13108 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13109 (const_int 0)))
13110 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13111 "TARGET_32BIT"
13112 "@
13113 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13114 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13115 #
13116 #"
13117 [(set_attr "type" "compare")
13118 (set_attr "length" "12,12,16,16")])
13119
13120 (define_split
13121 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13122 (compare:CC
13123 (and:SI (neg:SI
13124 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13125 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13126 (match_operand:SI 3 "gpc_reg_operand" ""))
13127 (const_int 0)))
13128 (clobber (match_scratch:SI 4 ""))]
13129 "TARGET_32BIT && reload_completed"
13130 [(set (match_dup 4)
13131 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13132 (match_dup 3)))
13133 (set (match_dup 0)
13134 (compare:CC (match_dup 4)
13135 (const_int 0)))]
13136 "")
13137
13138 (define_insn ""
13139 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13140 (compare:CC
13141 (and:SI (neg:SI
13142 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13143 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13144 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13145 (const_int 0)))
13146 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13147 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13148 "TARGET_32BIT"
13149 "@
13150 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13151 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13152 #
13153 #"
13154 [(set_attr "type" "compare")
13155 (set_attr "length" "12,12,16,16")])
13156
13157 (define_split
13158 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13159 (compare:CC
13160 (and:SI (neg:SI
13161 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13162 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13163 (match_operand:SI 3 "gpc_reg_operand" ""))
13164 (const_int 0)))
13165 (set (match_operand:SI 0 "gpc_reg_operand" "")
13166 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13167 "TARGET_32BIT && reload_completed"
13168 [(set (match_dup 0)
13169 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13170 (set (match_dup 4)
13171 (compare:CC (match_dup 0)
13172 (const_int 0)))]
13173 "")
13174
13175 (define_insn ""
13176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13177 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13178 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13179 "TARGET_POWER"
13180 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13181 [(set_attr "length" "12")])
13182
13183 (define_insn ""
13184 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13185 (compare:CC
13186 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13187 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13188 (const_int 0)))
13189 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13190 (gt:SI (match_dup 1) (match_dup 2)))]
13191 "TARGET_POWER"
13192 "@
13193 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13194 #"
13195 [(set_attr "type" "delayed_compare")
13196 (set_attr "length" "12,16")])
13197
13198 (define_split
13199 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13200 (compare:CC
13201 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13202 (match_operand:SI 2 "reg_or_short_operand" ""))
13203 (const_int 0)))
13204 (set (match_operand:SI 0 "gpc_reg_operand" "")
13205 (gt:SI (match_dup 1) (match_dup 2)))]
13206 "TARGET_POWER && reload_completed"
13207 [(set (match_dup 0)
13208 (gt:SI (match_dup 1) (match_dup 2)))
13209 (set (match_dup 3)
13210 (compare:CC (match_dup 0)
13211 (const_int 0)))]
13212 "")
13213
13214 (define_insn "*plus_gt0<mode>"
13215 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13216 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13217 (const_int 0))
13218 (match_operand:P 2 "gpc_reg_operand" "r")))]
13219 ""
13220 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13221 [(set_attr "type" "three")
13222 (set_attr "length" "12")])
13223
13224 (define_insn ""
13225 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13226 (compare:CC
13227 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13228 (const_int 0))
13229 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13230 (const_int 0)))
13231 (clobber (match_scratch:SI 3 "=&r,&r"))]
13232 "TARGET_32BIT"
13233 "@
13234 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13235 #"
13236 [(set_attr "type" "compare")
13237 (set_attr "length" "12,16")])
13238
13239 (define_split
13240 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13241 (compare:CC
13242 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13243 (const_int 0))
13244 (match_operand:SI 2 "gpc_reg_operand" ""))
13245 (const_int 0)))
13246 (clobber (match_scratch:SI 3 ""))]
13247 "TARGET_32BIT && reload_completed"
13248 [(set (match_dup 3)
13249 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13250 (match_dup 2)))
13251 (set (match_dup 0)
13252 (compare:CC (match_dup 3)
13253 (const_int 0)))]
13254 "")
13255
13256 (define_insn ""
13257 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13258 (compare:CC
13259 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13260 (const_int 0))
13261 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13262 (const_int 0)))
13263 (clobber (match_scratch:DI 3 "=&r,&r"))]
13264 "TARGET_64BIT"
13265 "@
13266 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13267 #"
13268 [(set_attr "type" "compare")
13269 (set_attr "length" "12,16")])
13270
13271 (define_split
13272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13273 (compare:CC
13274 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13275 (const_int 0))
13276 (match_operand:DI 2 "gpc_reg_operand" ""))
13277 (const_int 0)))
13278 (clobber (match_scratch:DI 3 ""))]
13279 "TARGET_64BIT && reload_completed"
13280 [(set (match_dup 3)
13281 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13282 (match_dup 2)))
13283 (set (match_dup 0)
13284 (compare:CC (match_dup 3)
13285 (const_int 0)))]
13286 "")
13287
13288 (define_insn ""
13289 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13290 (compare:CC
13291 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13292 (const_int 0))
13293 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13294 (const_int 0)))
13295 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13296 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13297 "TARGET_32BIT"
13298 "@
13299 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13300 #"
13301 [(set_attr "type" "compare")
13302 (set_attr "length" "12,16")])
13303
13304 (define_split
13305 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13306 (compare:CC
13307 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13308 (const_int 0))
13309 (match_operand:SI 2 "gpc_reg_operand" ""))
13310 (const_int 0)))
13311 (set (match_operand:SI 0 "gpc_reg_operand" "")
13312 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13313 "TARGET_32BIT && reload_completed"
13314 [(set (match_dup 0)
13315 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13316 (set (match_dup 3)
13317 (compare:CC (match_dup 0)
13318 (const_int 0)))]
13319 "")
13320
13321 (define_insn ""
13322 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13323 (compare:CC
13324 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13325 (const_int 0))
13326 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13327 (const_int 0)))
13328 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13329 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13330 "TARGET_64BIT"
13331 "@
13332 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13333 #"
13334 [(set_attr "type" "compare")
13335 (set_attr "length" "12,16")])
13336
13337 (define_split
13338 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13339 (compare:CC
13340 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13341 (const_int 0))
13342 (match_operand:DI 2 "gpc_reg_operand" ""))
13343 (const_int 0)))
13344 (set (match_operand:DI 0 "gpc_reg_operand" "")
13345 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13346 "TARGET_64BIT && reload_completed"
13347 [(set (match_dup 0)
13348 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13349 (set (match_dup 3)
13350 (compare:CC (match_dup 0)
13351 (const_int 0)))]
13352 "")
13353
13354 (define_insn ""
13355 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13356 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13357 (match_operand:SI 2 "reg_or_short_operand" "r"))
13358 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13359 "TARGET_POWER"
13360 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13361 [(set_attr "length" "12")])
13362
13363 (define_insn ""
13364 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13365 (compare:CC
13366 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13367 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13368 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13369 (const_int 0)))
13370 (clobber (match_scratch:SI 4 "=&r,&r"))]
13371 "TARGET_POWER"
13372 "@
13373 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13374 #"
13375 [(set_attr "type" "compare")
13376 (set_attr "length" "12,16")])
13377
13378 (define_split
13379 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13380 (compare:CC
13381 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13382 (match_operand:SI 2 "reg_or_short_operand" ""))
13383 (match_operand:SI 3 "gpc_reg_operand" ""))
13384 (const_int 0)))
13385 (clobber (match_scratch:SI 4 ""))]
13386 "TARGET_POWER && reload_completed"
13387 [(set (match_dup 4)
13388 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13389 (set (match_dup 0)
13390 (compare:CC (match_dup 4)
13391 (const_int 0)))]
13392 "")
13393
13394 (define_insn ""
13395 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13396 (compare:CC
13397 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13398 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13399 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13400 (const_int 0)))
13401 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13402 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13403 "TARGET_POWER"
13404 "@
13405 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13406 #"
13407 [(set_attr "type" "compare")
13408 (set_attr "length" "12,16")])
13409
13410 (define_split
13411 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13412 (compare:CC
13413 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13414 (match_operand:SI 2 "reg_or_short_operand" ""))
13415 (match_operand:SI 3 "gpc_reg_operand" ""))
13416 (const_int 0)))
13417 (set (match_operand:SI 0 "gpc_reg_operand" "")
13418 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13419 "TARGET_POWER && reload_completed"
13420 [(set (match_dup 0)
13421 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13422 (set (match_dup 4)
13423 (compare:CC (match_dup 0)
13424 (const_int 0)))]
13425 "")
13426
13427 (define_insn ""
13428 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13429 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13430 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13431 "TARGET_POWER"
13432 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13433 [(set_attr "length" "12")])
13434
13435 (define_insn_and_split "*gtu<mode>"
13436 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13437 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13438 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13439 ""
13440 "#"
13441 ""
13442 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13443 (set (match_dup 0) (neg:P (match_dup 0)))]
13444 "")
13445
13446 (define_insn_and_split "*gtu<mode>_compare"
13447 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13448 (compare:CC
13449 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13450 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13451 (const_int 0)))
13452 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13453 (gtu:P (match_dup 1) (match_dup 2)))]
13454 ""
13455 "#"
13456 ""
13457 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13458 (parallel [(set (match_dup 3)
13459 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13460 (set (match_dup 0) (neg:P (match_dup 0)))])]
13461 "")
13462
13463 (define_insn_and_split "*plus_gtu<mode>"
13464 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13465 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13466 (match_operand:P 2 "reg_or_short_operand" "rI"))
13467 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13468 ""
13469 "#"
13470 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13471 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13472 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13473 "")
13474
13475 (define_insn_and_split "*plus_gtu<mode>_compare"
13476 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13477 (compare:CC
13478 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13479 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13480 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13481 (const_int 0)))
13482 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13483 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13484 ""
13485 "#"
13486 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13487 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13488 (parallel [(set (match_dup 4)
13489 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13490 (const_int 0)))
13491 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13492 "")
13493
13494 (define_insn "*neg_gtu<mode>"
13495 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13496 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13497 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13498 ""
13499 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13500 [(set_attr "type" "two")
13501 (set_attr "length" "8")])
13502
13503 \f
13504 ;; Define both directions of branch and return. If we need a reload
13505 ;; register, we'd rather use CR0 since it is much easier to copy a
13506 ;; register CC value to there.
13507
13508 (define_insn ""
13509 [(set (pc)
13510 (if_then_else (match_operator 1 "branch_comparison_operator"
13511 [(match_operand 2
13512 "cc_reg_operand" "y")
13513 (const_int 0)])
13514 (label_ref (match_operand 0 "" ""))
13515 (pc)))]
13516 ""
13517 "*
13518 {
13519 return output_cbranch (operands[1], \"%l0\", 0, insn);
13520 }"
13521 [(set_attr "type" "branch")])
13522
13523 (define_insn ""
13524 [(set (pc)
13525 (if_then_else (match_operator 0 "branch_comparison_operator"
13526 [(match_operand 1
13527 "cc_reg_operand" "y")
13528 (const_int 0)])
13529 (return)
13530 (pc)))]
13531 "direct_return ()"
13532 "*
13533 {
13534 return output_cbranch (operands[0], NULL, 0, insn);
13535 }"
13536 [(set_attr "type" "jmpreg")
13537 (set_attr "length" "4")])
13538
13539 (define_insn ""
13540 [(set (pc)
13541 (if_then_else (match_operator 1 "branch_comparison_operator"
13542 [(match_operand 2
13543 "cc_reg_operand" "y")
13544 (const_int 0)])
13545 (pc)
13546 (label_ref (match_operand 0 "" ""))))]
13547 ""
13548 "*
13549 {
13550 return output_cbranch (operands[1], \"%l0\", 1, insn);
13551 }"
13552 [(set_attr "type" "branch")])
13553
13554 (define_insn ""
13555 [(set (pc)
13556 (if_then_else (match_operator 0 "branch_comparison_operator"
13557 [(match_operand 1
13558 "cc_reg_operand" "y")
13559 (const_int 0)])
13560 (pc)
13561 (return)))]
13562 "direct_return ()"
13563 "*
13564 {
13565 return output_cbranch (operands[0], NULL, 1, insn);
13566 }"
13567 [(set_attr "type" "jmpreg")
13568 (set_attr "length" "4")])
13569
13570 ;; Logic on condition register values.
13571
13572 ; This pattern matches things like
13573 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13574 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13575 ; (const_int 1)))
13576 ; which are generated by the branch logic.
13577 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13578
13579 (define_insn "*cceq_ior_compare"
13580 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13581 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13582 [(match_operator:SI 2
13583 "branch_positive_comparison_operator"
13584 [(match_operand 3
13585 "cc_reg_operand" "y,y")
13586 (const_int 0)])
13587 (match_operator:SI 4
13588 "branch_positive_comparison_operator"
13589 [(match_operand 5
13590 "cc_reg_operand" "0,y")
13591 (const_int 0)])])
13592 (const_int 1)))]
13593 ""
13594 "cr%q1 %E0,%j2,%j4"
13595 [(set_attr "type" "cr_logical,delayed_cr")])
13596
13597 ; Why is the constant -1 here, but 1 in the previous pattern?
13598 ; Because ~1 has all but the low bit set.
13599 (define_insn ""
13600 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13601 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13602 [(not:SI (match_operator:SI 2
13603 "branch_positive_comparison_operator"
13604 [(match_operand 3
13605 "cc_reg_operand" "y,y")
13606 (const_int 0)]))
13607 (match_operator:SI 4
13608 "branch_positive_comparison_operator"
13609 [(match_operand 5
13610 "cc_reg_operand" "0,y")
13611 (const_int 0)])])
13612 (const_int -1)))]
13613 ""
13614 "cr%q1 %E0,%j2,%j4"
13615 [(set_attr "type" "cr_logical,delayed_cr")])
13616
13617 (define_insn "*cceq_rev_compare"
13618 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13619 (compare:CCEQ (match_operator:SI 1
13620 "branch_positive_comparison_operator"
13621 [(match_operand 2
13622 "cc_reg_operand" "0,y")
13623 (const_int 0)])
13624 (const_int 0)))]
13625 ""
13626 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13627 [(set_attr "type" "cr_logical,delayed_cr")])
13628
13629 ;; If we are comparing the result of two comparisons, this can be done
13630 ;; using creqv or crxor.
13631
13632 (define_insn_and_split ""
13633 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13634 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13635 [(match_operand 2 "cc_reg_operand" "y")
13636 (const_int 0)])
13637 (match_operator 3 "branch_comparison_operator"
13638 [(match_operand 4 "cc_reg_operand" "y")
13639 (const_int 0)])))]
13640 ""
13641 "#"
13642 ""
13643 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13644 (match_dup 5)))]
13645 "
13646 {
13647 int positive_1, positive_2;
13648
13649 positive_1 = branch_positive_comparison_operator (operands[1],
13650 GET_MODE (operands[1]));
13651 positive_2 = branch_positive_comparison_operator (operands[3],
13652 GET_MODE (operands[3]));
13653
13654 if (! positive_1)
13655 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13656 GET_CODE (operands[1])),
13657 SImode,
13658 operands[2], const0_rtx);
13659 else if (GET_MODE (operands[1]) != SImode)
13660 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13661 operands[2], const0_rtx);
13662
13663 if (! positive_2)
13664 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13665 GET_CODE (operands[3])),
13666 SImode,
13667 operands[4], const0_rtx);
13668 else if (GET_MODE (operands[3]) != SImode)
13669 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13670 operands[4], const0_rtx);
13671
13672 if (positive_1 == positive_2)
13673 {
13674 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13675 operands[5] = constm1_rtx;
13676 }
13677 else
13678 {
13679 operands[5] = const1_rtx;
13680 }
13681 }")
13682
13683 ;; Unconditional branch and return.
13684
13685 (define_insn "jump"
13686 [(set (pc)
13687 (label_ref (match_operand 0 "" "")))]
13688 ""
13689 "b %l0"
13690 [(set_attr "type" "branch")])
13691
13692 (define_insn "return"
13693 [(return)]
13694 "direct_return ()"
13695 "{br|blr}"
13696 [(set_attr "type" "jmpreg")])
13697
13698 (define_expand "indirect_jump"
13699 [(set (pc) (match_operand 0 "register_operand" ""))])
13700
13701 (define_insn "*indirect_jump<mode>"
13702 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13703 ""
13704 "@
13705 bctr
13706 {br|blr}"
13707 [(set_attr "type" "jmpreg")])
13708
13709 ;; Table jump for switch statements:
13710 (define_expand "tablejump"
13711 [(use (match_operand 0 "" ""))
13712 (use (label_ref (match_operand 1 "" "")))]
13713 ""
13714 "
13715 {
13716 if (TARGET_32BIT)
13717 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13718 else
13719 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13720 DONE;
13721 }")
13722
13723 (define_expand "tablejumpsi"
13724 [(set (match_dup 3)
13725 (plus:SI (match_operand:SI 0 "" "")
13726 (match_dup 2)))
13727 (parallel [(set (pc) (match_dup 3))
13728 (use (label_ref (match_operand 1 "" "")))])]
13729 "TARGET_32BIT"
13730 "
13731 { operands[0] = force_reg (SImode, operands[0]);
13732 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13733 operands[3] = gen_reg_rtx (SImode);
13734 }")
13735
13736 (define_expand "tablejumpdi"
13737 [(set (match_dup 4)
13738 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
13739 (set (match_dup 3)
13740 (plus:DI (match_dup 4)
13741 (match_dup 2)))
13742 (parallel [(set (pc) (match_dup 3))
13743 (use (label_ref (match_operand 1 "" "")))])]
13744 "TARGET_64BIT"
13745 "
13746 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13747 operands[3] = gen_reg_rtx (DImode);
13748 operands[4] = gen_reg_rtx (DImode);
13749 }")
13750
13751 (define_insn "*tablejump<mode>_internal1"
13752 [(set (pc)
13753 (match_operand:P 0 "register_operand" "c,*l"))
13754 (use (label_ref (match_operand 1 "" "")))]
13755 ""
13756 "@
13757 bctr
13758 {br|blr}"
13759 [(set_attr "type" "jmpreg")])
13760
13761 (define_insn "nop"
13762 [(const_int 0)]
13763 ""
13764 "{cror 0,0,0|nop}")
13765 \f
13766 ;; Define the subtract-one-and-jump insns, starting with the template
13767 ;; so loop.c knows what to generate.
13768
13769 (define_expand "doloop_end"
13770 [(use (match_operand 0 "" "")) ; loop pseudo
13771 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13772 (use (match_operand 2 "" "")) ; max iterations
13773 (use (match_operand 3 "" "")) ; loop level
13774 (use (match_operand 4 "" ""))] ; label
13775 ""
13776 "
13777 {
13778 /* Only use this on innermost loops. */
13779 if (INTVAL (operands[3]) > 1)
13780 FAIL;
13781 if (TARGET_64BIT)
13782 {
13783 if (GET_MODE (operands[0]) != DImode)
13784 FAIL;
13785 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13786 }
13787 else
13788 {
13789 if (GET_MODE (operands[0]) != SImode)
13790 FAIL;
13791 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13792 }
13793 DONE;
13794 }")
13795
13796 (define_expand "ctr<mode>"
13797 [(parallel [(set (pc)
13798 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13799 (const_int 1))
13800 (label_ref (match_operand 1 "" ""))
13801 (pc)))
13802 (set (match_dup 0)
13803 (plus:P (match_dup 0)
13804 (const_int -1)))
13805 (clobber (match_scratch:CC 2 ""))
13806 (clobber (match_scratch:P 3 ""))])]
13807 ""
13808 "")
13809
13810 ;; We need to be able to do this for any operand, including MEM, or we
13811 ;; will cause reload to blow up since we don't allow output reloads on
13812 ;; JUMP_INSNs.
13813 ;; For the length attribute to be calculated correctly, the
13814 ;; label MUST be operand 0.
13815
13816 (define_insn "*ctr<mode>_internal1"
13817 [(set (pc)
13818 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13819 (const_int 1))
13820 (label_ref (match_operand 0 "" ""))
13821 (pc)))
13822 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13823 (plus:P (match_dup 1)
13824 (const_int -1)))
13825 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13826 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13827 ""
13828 "*
13829 {
13830 if (which_alternative != 0)
13831 return \"#\";
13832 else if (get_attr_length (insn) == 4)
13833 return \"{bdn|bdnz} %l0\";
13834 else
13835 return \"bdz $+8\;b %l0\";
13836 }"
13837 [(set_attr "type" "branch")
13838 (set_attr "length" "*,12,16,16")])
13839
13840 (define_insn "*ctr<mode>_internal2"
13841 [(set (pc)
13842 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13843 (const_int 1))
13844 (pc)
13845 (label_ref (match_operand 0 "" ""))))
13846 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13847 (plus:P (match_dup 1)
13848 (const_int -1)))
13849 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13850 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13851 ""
13852 "*
13853 {
13854 if (which_alternative != 0)
13855 return \"#\";
13856 else if (get_attr_length (insn) == 4)
13857 return \"bdz %l0\";
13858 else
13859 return \"{bdn|bdnz} $+8\;b %l0\";
13860 }"
13861 [(set_attr "type" "branch")
13862 (set_attr "length" "*,12,16,16")])
13863
13864 ;; Similar but use EQ
13865
13866 (define_insn "*ctr<mode>_internal5"
13867 [(set (pc)
13868 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13869 (const_int 1))
13870 (label_ref (match_operand 0 "" ""))
13871 (pc)))
13872 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13873 (plus:P (match_dup 1)
13874 (const_int -1)))
13875 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13876 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13877 ""
13878 "*
13879 {
13880 if (which_alternative != 0)
13881 return \"#\";
13882 else if (get_attr_length (insn) == 4)
13883 return \"bdz %l0\";
13884 else
13885 return \"{bdn|bdnz} $+8\;b %l0\";
13886 }"
13887 [(set_attr "type" "branch")
13888 (set_attr "length" "*,12,16,16")])
13889
13890 (define_insn "*ctr<mode>_internal6"
13891 [(set (pc)
13892 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13893 (const_int 1))
13894 (pc)
13895 (label_ref (match_operand 0 "" ""))))
13896 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13897 (plus:P (match_dup 1)
13898 (const_int -1)))
13899 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13900 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13901 ""
13902 "*
13903 {
13904 if (which_alternative != 0)
13905 return \"#\";
13906 else if (get_attr_length (insn) == 4)
13907 return \"{bdn|bdnz} %l0\";
13908 else
13909 return \"bdz $+8\;b %l0\";
13910 }"
13911 [(set_attr "type" "branch")
13912 (set_attr "length" "*,12,16,16")])
13913
13914 ;; Now the splitters if we could not allocate the CTR register
13915
13916 (define_split
13917 [(set (pc)
13918 (if_then_else (match_operator 2 "comparison_operator"
13919 [(match_operand:P 1 "gpc_reg_operand" "")
13920 (const_int 1)])
13921 (match_operand 5 "" "")
13922 (match_operand 6 "" "")))
13923 (set (match_operand:P 0 "gpc_reg_operand" "")
13924 (plus:P (match_dup 1) (const_int -1)))
13925 (clobber (match_scratch:CC 3 ""))
13926 (clobber (match_scratch:P 4 ""))]
13927 "reload_completed"
13928 [(parallel [(set (match_dup 3)
13929 (compare:CC (plus:P (match_dup 1)
13930 (const_int -1))
13931 (const_int 0)))
13932 (set (match_dup 0)
13933 (plus:P (match_dup 1)
13934 (const_int -1)))])
13935 (set (pc) (if_then_else (match_dup 7)
13936 (match_dup 5)
13937 (match_dup 6)))]
13938 "
13939 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13940 operands[3], const0_rtx); }")
13941
13942 (define_split
13943 [(set (pc)
13944 (if_then_else (match_operator 2 "comparison_operator"
13945 [(match_operand:P 1 "gpc_reg_operand" "")
13946 (const_int 1)])
13947 (match_operand 5 "" "")
13948 (match_operand 6 "" "")))
13949 (set (match_operand:P 0 "nonimmediate_operand" "")
13950 (plus:P (match_dup 1) (const_int -1)))
13951 (clobber (match_scratch:CC 3 ""))
13952 (clobber (match_scratch:P 4 ""))]
13953 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13954 [(parallel [(set (match_dup 3)
13955 (compare:CC (plus:P (match_dup 1)
13956 (const_int -1))
13957 (const_int 0)))
13958 (set (match_dup 4)
13959 (plus:P (match_dup 1)
13960 (const_int -1)))])
13961 (set (match_dup 0)
13962 (match_dup 4))
13963 (set (pc) (if_then_else (match_dup 7)
13964 (match_dup 5)
13965 (match_dup 6)))]
13966 "
13967 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13968 operands[3], const0_rtx); }")
13969 \f
13970 (define_insn "trap"
13971 [(trap_if (const_int 1) (const_int 0))]
13972 ""
13973 "{t 31,0,0|trap}")
13974
13975 (define_expand "conditional_trap"
13976 [(trap_if (match_operator 0 "trap_comparison_operator"
13977 [(match_dup 2) (match_dup 3)])
13978 (match_operand 1 "const_int_operand" ""))]
13979 ""
13980 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13981 operands[2] = rs6000_compare_op0;
13982 operands[3] = rs6000_compare_op1;")
13983
13984 (define_insn ""
13985 [(trap_if (match_operator 0 "trap_comparison_operator"
13986 [(match_operand:GPR 1 "register_operand" "r")
13987 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13988 (const_int 0))]
13989 ""
13990 "{t|t<wd>}%V0%I2 %1,%2")
13991 \f
13992 ;; Insns related to generating the function prologue and epilogue.
13993
13994 (define_expand "prologue"
13995 [(use (const_int 0))]
13996 "TARGET_SCHED_PROLOG"
13997 "
13998 {
13999 rs6000_emit_prologue ();
14000 DONE;
14001 }")
14002
14003 (define_insn "*movesi_from_cr_one"
14004 [(match_parallel 0 "mfcr_operation"
14005 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14006 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
14007 (match_operand 3 "immediate_operand" "n")]
14008 UNSPEC_MOVESI_FROM_CR))])]
14009 "TARGET_MFCRF"
14010 "*
14011 {
14012 int mask = 0;
14013 int i;
14014 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14015 {
14016 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14017 operands[4] = GEN_INT (mask);
14018 output_asm_insn (\"mfcr %1,%4\", operands);
14019 }
14020 return \"\";
14021 }"
14022 [(set_attr "type" "mfcrf")])
14023
14024 (define_insn "movesi_from_cr"
14025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14026 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14027 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)]
14028 UNSPEC_MOVESI_FROM_CR))]
14029 ""
14030 "mfcr %0"
14031 [(set_attr "type" "mfcr")])
14032
14033 (define_insn "*stmw"
14034 [(match_parallel 0 "stmw_operation"
14035 [(set (match_operand:SI 1 "memory_operand" "=m")
14036 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14037 "TARGET_MULTIPLE"
14038 "{stm|stmw} %2,%1"
14039 [(set_attr "type" "store_ux")])
14040
14041 (define_insn "*save_fpregs_<mode>"
14042 [(match_parallel 0 "any_parallel_operand"
14043 [(clobber (match_operand:P 1 "register_operand" "=l"))
14044 (use (match_operand:P 2 "call_operand" "s"))
14045 (set (match_operand:DF 3 "memory_operand" "=m")
14046 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14047 ""
14048 "bl %z2"
14049 [(set_attr "type" "branch")
14050 (set_attr "length" "4")])
14051
14052 ; These are to explain that changes to the stack pointer should
14053 ; not be moved over stores to stack memory.
14054 (define_insn "stack_tie"
14055 [(set (match_operand:BLK 0 "memory_operand" "+m")
14056 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
14057 ""
14058 ""
14059 [(set_attr "length" "0")])
14060
14061
14062 (define_expand "epilogue"
14063 [(use (const_int 0))]
14064 "TARGET_SCHED_PROLOG"
14065 "
14066 {
14067 rs6000_emit_epilogue (FALSE);
14068 DONE;
14069 }")
14070
14071 ; On some processors, doing the mtcrf one CC register at a time is
14072 ; faster (like on the 604e). On others, doing them all at once is
14073 ; faster; for instance, on the 601 and 750.
14074
14075 (define_expand "movsi_to_cr_one"
14076 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14077 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14078 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14079 ""
14080 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14081
14082 (define_insn "*movsi_to_cr"
14083 [(match_parallel 0 "mtcrf_operation"
14084 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14085 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14086 (match_operand 3 "immediate_operand" "n")]
14087 UNSPEC_MOVESI_TO_CR))])]
14088 ""
14089 "*
14090 {
14091 int mask = 0;
14092 int i;
14093 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14094 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14095 operands[4] = GEN_INT (mask);
14096 return \"mtcrf %4,%2\";
14097 }"
14098 [(set_attr "type" "mtcr")])
14099
14100 (define_insn "*mtcrfsi"
14101 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14102 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14103 (match_operand 2 "immediate_operand" "n")]
14104 UNSPEC_MOVESI_TO_CR))]
14105 "GET_CODE (operands[0]) == REG
14106 && CR_REGNO_P (REGNO (operands[0]))
14107 && GET_CODE (operands[2]) == CONST_INT
14108 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14109 "mtcrf %R0,%1"
14110 [(set_attr "type" "mtcr")])
14111
14112 ; The load-multiple instructions have similar properties.
14113 ; Note that "load_multiple" is a name known to the machine-independent
14114 ; code that actually corresponds to the PowerPC load-string.
14115
14116 (define_insn "*lmw"
14117 [(match_parallel 0 "lmw_operation"
14118 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14119 (match_operand:SI 2 "memory_operand" "m"))])]
14120 "TARGET_MULTIPLE"
14121 "{lm|lmw} %1,%2"
14122 [(set_attr "type" "load_ux")])
14123
14124 (define_insn "*return_internal_<mode>"
14125 [(return)
14126 (use (match_operand:P 0 "register_operand" "lc"))]
14127 ""
14128 "b%T0"
14129 [(set_attr "type" "jmpreg")])
14130
14131 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14132 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14133
14134 (define_insn "*return_and_restore_fpregs_<mode>"
14135 [(match_parallel 0 "any_parallel_operand"
14136 [(return)
14137 (use (match_operand:P 1 "register_operand" "l"))
14138 (use (match_operand:P 2 "call_operand" "s"))
14139 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14140 (match_operand:DF 4 "memory_operand" "m"))])]
14141 ""
14142 "b %z2")
14143
14144 ; This is used in compiling the unwind routines.
14145 (define_expand "eh_return"
14146 [(use (match_operand 0 "general_operand" ""))]
14147 ""
14148 "
14149 {
14150 if (TARGET_32BIT)
14151 emit_insn (gen_eh_set_lr_si (operands[0]));
14152 else
14153 emit_insn (gen_eh_set_lr_di (operands[0]));
14154 DONE;
14155 }")
14156
14157 ; We can't expand this before we know where the link register is stored.
14158 (define_insn "eh_set_lr_<mode>"
14159 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14160 UNSPECV_EH_RR)
14161 (clobber (match_scratch:P 1 "=&b"))]
14162 ""
14163 "#")
14164
14165 (define_split
14166 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14167 (clobber (match_scratch 1 ""))]
14168 "reload_completed"
14169 [(const_int 0)]
14170 "
14171 {
14172 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14173 DONE;
14174 }")
14175
14176 (define_insn "prefetch"
14177 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14178 (match_operand:SI 1 "const_int_operand" "n")
14179 (match_operand:SI 2 "const_int_operand" "n"))]
14180 "TARGET_POWERPC"
14181 "*
14182 {
14183 if (GET_CODE (operands[0]) == REG)
14184 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14185 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14186 }"
14187 [(set_attr "type" "load")])
14188 \f
14189
14190 (include "sync.md")
14191 (include "altivec.md")
14192 (include "spe.md")
Mirror of https://gcc.gnu.org/git/gcc.git