1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; `unspec' values used in rs6000.md:
27 ;; 0 frsp for POWER machines
29 ;; 5 used to tie the stack contents and the stack pointer
30 ;; 6 address of a word pointing to the TOC
31 ;; 7 address of the TOC (more-or-less)
38 ;; Define an insn type attribute. This is used in function unit delay
40 (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
41 (const_string "integer"))
44 ; '(pc)' in the following doesn't include the instruction itself; it is
45 ; calculated as if the instruction had zero size.
46 (define_attr "length" ""
47 (if_then_else (eq_attr "type" "branch")
48 (if_then_else (and (ge (minus (match_dup 0) (pc))
50 (lt (minus (match_dup 0) (pc))
56 ;; Processor type -- this attribute must exactly match the processor_type
57 ;; enumeration in rs6000.h.
59 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450"
60 (const (symbol_ref "rs6000_cpu_attr")))
62 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
63 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
65 ; Load/Store Unit -- pure PowerPC only
66 ; (POWER and 601 use Integer Unit)
67 (define_function_unit "lsu" 1 0
68 (and (eq_attr "type" "load")
69 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
72 (define_function_unit "lsu" 1 0
73 (and (eq_attr "type" "load")
74 (eq_attr "cpu" "ppc7450"))
77 (define_function_unit "lsu" 1 0
78 (and (eq_attr "type" "store,fpstore")
79 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630"))
82 (define_function_unit "lsu" 1 0
83 (and (eq_attr "type" "store,fpstore")
84 (eq_attr "cpu" "ppc750,ppc7400"))
87 (define_function_unit "lsu" 1 0
88 (and (eq_attr "type" "store")
89 (eq_attr "cpu" "ppc7450"))
92 (define_function_unit "lsu" 1 0
93 (and (eq_attr "type" "fpstore")
94 (eq_attr "cpu" "ppc7450"))
97 (define_function_unit "lsu" 1 0
98 (and (eq_attr "type" "fpload")
99 (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400"))
102 (define_function_unit "lsu" 1 0
103 (and (eq_attr "type" "fpload")
104 (eq_attr "cpu" "ppc7450"))
107 (define_function_unit "lsu" 1 0
108 (and (eq_attr "type" "fpload")
109 (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
112 (define_function_unit "iu" 1 0
113 (and (eq_attr "type" "load")
114 (eq_attr "cpu" "rios1,ppc403,ppc601"))
117 (define_function_unit "iu" 1 0
118 (and (eq_attr "type" "store,fpstore")
119 (eq_attr "cpu" "rios1,ppc403,ppc601"))
122 (define_function_unit "fpu" 1 0
123 (and (eq_attr "type" "fpstore")
124 (eq_attr "cpu" "rios1,ppc601"))
127 (define_function_unit "iu" 1 0
128 (and (eq_attr "type" "fpload")
129 (eq_attr "cpu" "rios1"))
132 (define_function_unit "iu" 1 0
133 (and (eq_attr "type" "fpload")
134 (eq_attr "cpu" "ppc601"))
137 (define_function_unit "iu2" 2 0
138 (and (eq_attr "type" "load,fpload")
139 (eq_attr "cpu" "rios2"))
142 (define_function_unit "iu2" 2 0
143 (and (eq_attr "type" "store,fpstore")
144 (eq_attr "cpu" "rios2"))
147 ; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
148 (define_function_unit "iu" 1 0
149 (and (eq_attr "type" "integer")
150 (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603"))
153 (define_function_unit "iu" 1 0
154 (and (eq_attr "type" "cr_logical")
155 (eq_attr "cpu" "mpccore,ppc403,ppc601"))
158 (define_function_unit "iu" 1 0
159 (and (eq_attr "type" "imul")
160 (eq_attr "cpu" "ppc403"))
163 (define_function_unit "iu" 1 0
164 (and (eq_attr "type" "imul")
165 (eq_attr "cpu" "rios1,ppc601,ppc603"))
168 (define_function_unit "iu" 1 0
169 (and (eq_attr "type" "imul")
170 (eq_attr "cpu" "rs64a"))
173 (define_function_unit "iu" 1 0
174 (and (eq_attr "type" "lmul")
175 (eq_attr "cpu" "rs64a"))
178 (define_function_unit "iu" 1 0
179 (and (eq_attr "type" "idiv")
180 (eq_attr "cpu" "rios1"))
183 (define_function_unit "iu" 1 0
184 (and (eq_attr "type" "idiv")
185 (eq_attr "cpu" "rs64a"))
188 (define_function_unit "iu" 1 0
189 (and (eq_attr "type" "ldiv")
190 (eq_attr "cpu" "rs64a"))
193 (define_function_unit "iu" 1 0
194 (and (eq_attr "type" "idiv")
195 (eq_attr "cpu" "ppc403"))
198 (define_function_unit "iu" 1 0
199 (and (eq_attr "type" "idiv")
200 (eq_attr "cpu" "ppc601"))
203 (define_function_unit "iu" 1 0
204 (and (eq_attr "type" "idiv")
205 (eq_attr "cpu" "ppc603"))
208 ; RIOS2 has two integer units: a primary one which can perform all
209 ; operations and a secondary one which is fed in lock step with the first
210 ; and can perform "simple" integer operations.
211 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
212 ; for the complex insns.
213 (define_function_unit "iu2" 2 0
214 (and (eq_attr "type" "integer")
215 (eq_attr "cpu" "rios2"))
218 (define_function_unit "iu2" 2 0
219 (and (eq_attr "type" "imul")
220 (eq_attr "cpu" "rios2"))
223 (define_function_unit "iu2" 2 0
224 (and (eq_attr "type" "idiv")
225 (eq_attr "cpu" "rios2"))
228 (define_function_unit "imuldiv" 1 0
229 (and (eq_attr "type" "imul")
230 (eq_attr "cpu" "rios2"))
233 (define_function_unit "imuldiv" 1 0
234 (and (eq_attr "type" "idiv")
235 (eq_attr "cpu" "rios2"))
238 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
239 ; Divide latency varies greatly from 2-11, use 6 as average
240 (define_function_unit "imuldiv" 1 0
241 (and (eq_attr "type" "imul")
242 (eq_attr "cpu" "mpccore"))
245 (define_function_unit "imuldiv" 1 0
246 (and (eq_attr "type" "idiv")
247 (eq_attr "cpu" "mpccore"))
250 ; PPC604{,e} has two units that perform integer operations
251 ; and one unit for divide/multiply operations (and move
253 (define_function_unit "iu2" 2 0
254 (and (eq_attr "type" "integer")
255 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
258 (define_function_unit "imuldiv" 1 0
259 (and (eq_attr "type" "imul")
260 (eq_attr "cpu" "ppc604"))
263 (define_function_unit "imuldiv" 1 0
264 (and (eq_attr "type" "imul")
265 (eq_attr "cpu" "ppc620,ppc630"))
268 (define_function_unit "imuldiv" 1 0
269 (and (eq_attr "type" "lmul")
270 (eq_attr "cpu" "ppc620,ppc630"))
273 (define_function_unit "imuldiv" 1 0
274 (and (eq_attr "type" "imul")
275 (eq_attr "cpu" "ppc604e"))
278 (define_function_unit "imuldiv" 1 0
279 (and (eq_attr "type" "idiv")
280 (eq_attr "cpu" "ppc604,ppc604e"))
283 (define_function_unit "imuldiv" 1 0
284 (and (eq_attr "type" "idiv")
285 (eq_attr "cpu" "ppc620"))
288 (define_function_unit "imuldiv" 1 0
289 (and (eq_attr "type" "idiv")
290 (eq_attr "cpu" "ppc630"))
293 (define_function_unit "imuldiv" 1 0
294 (and (eq_attr "type" "ldiv")
295 (eq_attr "cpu" "ppc620,ppc630"))
298 ; PPC7450 has 3 integer units (for most integer insns) and one mul/div
299 ; unit, which also does CR-logical insns and move to/from SPR.
301 (define_function_unit "iu3" 3 0
302 (and (eq_attr "type" "integer")
303 (eq_attr "cpu" "ppc7450"))
306 (define_function_unit "imuldiv" 1 0
307 (and (eq_attr "type" "imul")
308 (eq_attr "cpu" "ppc7450"))
311 (define_function_unit "imuldiv" 1 0
312 (and (eq_attr "type" "idiv")
313 (eq_attr "cpu" "ppc7450"))
316 (define_function_unit "imuldiv" 1 0
317 (and (eq_attr "type" "cr_logical")
318 (eq_attr "cpu" "ppc7450"))
321 ; PPC750 has two integer units: a primary one which can perform all
322 ; operations and a secondary one which is fed in lock step with the first
323 ; and can perform "simple" integer operations.
324 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
325 ; for the complex insns.
326 (define_function_unit "iu2" 2 0
327 (and (eq_attr "type" "integer")
328 (eq_attr "cpu" "ppc750,ppc7400"))
331 (define_function_unit "iu2" 2 0
332 (and (eq_attr "type" "imul")
333 (eq_attr "cpu" "ppc750,ppc7400"))
336 (define_function_unit "iu2" 2 0
337 (and (eq_attr "type" "idiv")
338 (eq_attr "cpu" "ppc750,ppc7400"))
341 (define_function_unit "imuldiv" 1 0
342 (and (eq_attr "type" "imul")
343 (eq_attr "cpu" "ppc750,ppc7400"))
346 (define_function_unit "imuldiv" 1 0
347 (and (eq_attr "type" "idiv")
348 (eq_attr "cpu" "ppc750,ppc7400"))
351 ; CR-logical operations are execute-serialized, that is they don't
352 ; start (and block the function unit) until all preceding operations
353 ; have finished. They don't block dispatch of other insns, though.
354 ; I've imitated this by giving them longer latency.
355 (define_function_unit "sru" 1 0
356 (and (eq_attr "type" "cr_logical")
357 (eq_attr "cpu" "ppc603,ppc750,ppc7400"))
360 ; compare is done on integer unit, but feeds insns which
361 ; execute on the branch unit.
362 (define_function_unit "iu" 1 0
363 (and (eq_attr "type" "compare")
364 (eq_attr "cpu" "rios1"))
367 (define_function_unit "iu" 1 0
368 (and (eq_attr "type" "delayed_compare")
369 (eq_attr "cpu" "rios1"))
372 (define_function_unit "iu" 1 0
373 (and (eq_attr "type" "compare,delayed_compare")
374 (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
377 ; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare
378 ; and a following branch, to reduce mispredicts
379 (define_function_unit "iu" 1 0
380 (and (eq_attr "type" "compare,delayed_compare")
381 (eq_attr "cpu" "ppc750,ppc7400"))
384 (define_function_unit "iu3" 3 0
385 (and (eq_attr "type" "compare,delayed_compare")
386 (eq_attr "cpu" "ppc7450"))
389 (define_function_unit "iu2" 2 0
390 (and (eq_attr "type" "compare,delayed_compare")
391 (eq_attr "cpu" "rios2"))
394 (define_function_unit "iu2" 2 0
395 (and (eq_attr "type" "compare,delayed_compare")
396 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
399 ; fp compare uses fp unit
400 (define_function_unit "fpu" 1 0
401 (and (eq_attr "type" "fpcompare")
402 (eq_attr "cpu" "rios1"))
405 ; rios1 and rios2 have different fpcompare delays
406 (define_function_unit "fpu2" 2 0
407 (and (eq_attr "type" "fpcompare")
408 (eq_attr "cpu" "rios2,ppc630"))
411 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
413 ; here we do not define delays, just occupy the unit. The dependencies
414 ; will be assigned by the fpcompare definition in the fpu.
415 (define_function_unit "iu" 1 0
416 (and (eq_attr "type" "fpcompare")
417 (eq_attr "cpu" "ppc601,ppc603"))
420 ; fp compare uses fp unit
421 (define_function_unit "fpu" 1 0
422 (and (eq_attr "type" "fpcompare")
423 (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
426 (define_function_unit "fpu" 1 0
427 (and (eq_attr "type" "fpcompare")
428 (eq_attr "cpu" "ppc750,ppc7400,ppc7450"))
431 (define_function_unit "fpu" 1 0
432 (and (eq_attr "type" "fpcompare")
433 (eq_attr "cpu" "mpccore"))
436 (define_function_unit "bpu" 1 0
437 (and (eq_attr "type" "mtjmpr")
438 (eq_attr "cpu" "rios1,rios2,rs64a"))
441 (define_function_unit "bpu" 1 0
442 (and (eq_attr "type" "mtjmpr")
443 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450"))
446 (define_function_unit "bpu" 1 0
447 (and (eq_attr "type" "cr_logical")
448 (eq_attr "cpu" "rios1,rios2,ppc604"))
451 (define_function_unit "cru" 1 0
452 (and (eq_attr "type" "cr_logical")
453 (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a"))
456 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
457 (define_function_unit "bpu" 1 0
458 (eq_attr "type" "jmpreg")
461 (define_function_unit "bpu" 1 0
462 (eq_attr "type" "branch")
465 ; Floating Point Unit
466 (define_function_unit "fpu" 1 0
467 (and (eq_attr "type" "fp,dmul")
468 (eq_attr "cpu" "rios1"))
471 (define_function_unit "fpu" 1 0
472 (and (eq_attr "type" "fp")
473 (eq_attr "cpu" "rs64a,mpccore"))
476 (define_function_unit "fpu" 1 0
477 (and (eq_attr "type" "fp")
478 (eq_attr "cpu" "ppc601"))
481 (define_function_unit "fpu" 1 0
482 (and (eq_attr "type" "fp")
483 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400"))
486 (define_function_unit "fpu" 1 0
487 (and (eq_attr "type" "fp,dmul")
488 (eq_attr "cpu" "ppc7450"))
491 (define_function_unit "fpu" 1 0
492 (and (eq_attr "type" "dmul")
493 (eq_attr "cpu" "rs64a"))
496 (define_function_unit "fpu" 1 0
497 (and (eq_attr "type" "dmul")
498 (eq_attr "cpu" "mpccore"))
501 (define_function_unit "fpu" 1 0
502 (and (eq_attr "type" "dmul")
503 (eq_attr "cpu" "ppc601"))
507 (define_function_unit "fpu" 1 0
508 (and (eq_attr "type" "dmul")
509 (eq_attr "cpu" "ppc603,ppc750"))
512 (define_function_unit "fpu" 1 0
513 (and (eq_attr "type" "dmul")
514 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400"))
517 (define_function_unit "fpu" 1 0
518 (and (eq_attr "type" "sdiv,ddiv")
519 (eq_attr "cpu" "rios1"))
522 (define_function_unit "fpu" 1 0
523 (and (eq_attr "type" "sdiv")
524 (eq_attr "cpu" "rs64a"))
527 (define_function_unit "fpu" 1 0
528 (and (eq_attr "type" "sdiv")
529 (eq_attr "cpu" "ppc601,ppc750,ppc7400"))
532 (define_function_unit "fpu" 1 0
533 (and (eq_attr "type" "sdiv")
534 (eq_attr "cpu" "ppc7450"))
537 (define_function_unit "fpu" 1 0
538 (and (eq_attr "type" "sdiv")
539 (eq_attr "cpu" "mpccore"))
542 (define_function_unit "fpu" 1 0
543 (and (eq_attr "type" "sdiv")
544 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
547 (define_function_unit "fpu" 1 0
548 (and (eq_attr "type" "ddiv")
549 (eq_attr "cpu" "mpccore"))
552 (define_function_unit "fpu" 1 0
553 (and (eq_attr "type" "ddiv")
554 (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400"))
557 (define_function_unit "fpu" 1 0
558 (and (eq_attr "type" "ddiv")
559 (eq_attr "cpu" "ppc7450"))
562 (define_function_unit "fpu" 1 0
563 (and (eq_attr "type" "ddiv")
564 (eq_attr "cpu" "ppc603"))
567 (define_function_unit "fpu" 1 0
568 (and (eq_attr "type" "ssqrt")
569 (eq_attr "cpu" "ppc620"))
572 (define_function_unit "fpu" 1 0
573 (and (eq_attr "type" "dsqrt")
574 (eq_attr "cpu" "ppc620"))
577 ; RIOS2 has two symmetric FPUs.
578 (define_function_unit "fpu2" 2 0
579 (and (eq_attr "type" "fp")
580 (eq_attr "cpu" "rios2"))
583 (define_function_unit "fpu2" 2 0
584 (and (eq_attr "type" "fp")
585 (eq_attr "cpu" "ppc630"))
588 (define_function_unit "fpu2" 2 0
589 (and (eq_attr "type" "dmul")
590 (eq_attr "cpu" "rios2"))
593 (define_function_unit "fpu2" 2 0
594 (and (eq_attr "type" "dmul")
595 (eq_attr "cpu" "ppc630"))
598 (define_function_unit "fpu2" 2 0
599 (and (eq_attr "type" "sdiv,ddiv")
600 (eq_attr "cpu" "rios2"))
603 (define_function_unit "fpu2" 2 0
604 (and (eq_attr "type" "sdiv")
605 (eq_attr "cpu" "ppc630"))
608 (define_function_unit "fpu2" 2 0
609 (and (eq_attr "type" "ddiv")
610 (eq_attr "cpu" "ppc630"))
613 (define_function_unit "fpu2" 2 0
614 (and (eq_attr "type" "ssqrt,dsqrt")
615 (eq_attr "cpu" "rios2"))
618 (define_function_unit "fpu2" 2 0
619 (and (eq_attr "type" "ssqrt")
620 (eq_attr "cpu" "ppc630"))
623 (define_function_unit "fpu2" 2 0
624 (and (eq_attr "type" "dsqrt")
625 (eq_attr "cpu" "ppc630"))
629 ;; Start with fixed-point load and store insns. Here we put only the more
630 ;; complex forms. Basic data transfer is done later.
632 (define_expand "zero_extendqidi2"
633 [(set (match_operand:DI 0 "gpc_reg_operand" "")
634 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
639 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
640 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
645 [(set_attr "type" "load,*")])
648 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
649 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
651 (clobber (match_scratch:DI 2 "=r,r"))]
656 [(set_attr "type" "compare")
657 (set_attr "length" "4,8")])
660 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
661 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
663 (clobber (match_scratch:DI 2 ""))]
664 "TARGET_POWERPC64 && reload_completed"
666 (zero_extend:DI (match_dup 1)))
668 (compare:CC (match_dup 2)
673 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
674 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
676 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
677 (zero_extend:DI (match_dup 1)))]
682 [(set_attr "type" "compare")
683 (set_attr "length" "4,8")])
686 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
687 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
689 (set (match_operand:DI 0 "gpc_reg_operand" "")
690 (zero_extend:DI (match_dup 1)))]
691 "TARGET_POWERPC64 && reload_completed"
693 (zero_extend:DI (match_dup 1)))
695 (compare:CC (match_dup 0)
699 (define_insn "extendqidi2"
700 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
701 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
706 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
707 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
709 (clobber (match_scratch:DI 2 "=r,r"))]
714 [(set_attr "type" "compare")
715 (set_attr "length" "4,8")])
718 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
719 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
721 (clobber (match_scratch:DI 2 ""))]
722 "TARGET_POWERPC64 && reload_completed"
724 (sign_extend:DI (match_dup 1)))
726 (compare:CC (match_dup 2)
731 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
732 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
734 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
735 (sign_extend:DI (match_dup 1)))]
740 [(set_attr "type" "compare")
741 (set_attr "length" "4,8")])
744 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
745 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
747 (set (match_operand:DI 0 "gpc_reg_operand" "")
748 (sign_extend:DI (match_dup 1)))]
749 "TARGET_POWERPC64 && reload_completed"
751 (sign_extend:DI (match_dup 1)))
753 (compare:CC (match_dup 0)
757 (define_expand "zero_extendhidi2"
758 [(set (match_operand:DI 0 "gpc_reg_operand" "")
759 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
764 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
765 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
770 [(set_attr "type" "load,*")])
773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
774 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
776 (clobber (match_scratch:DI 2 "=r,r"))]
781 [(set_attr "type" "compare")
782 (set_attr "length" "4,8")])
785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
786 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
788 (clobber (match_scratch:DI 2 ""))]
789 "TARGET_POWERPC64 && reload_completed"
791 (zero_extend:DI (match_dup 1)))
793 (compare:CC (match_dup 2)
798 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
799 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
801 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
802 (zero_extend:DI (match_dup 1)))]
807 [(set_attr "type" "compare")
808 (set_attr "length" "4,8")])
811 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
812 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
814 (set (match_operand:DI 0 "gpc_reg_operand" "")
815 (zero_extend:DI (match_dup 1)))]
816 "TARGET_POWERPC64 && reload_completed"
818 (zero_extend:DI (match_dup 1)))
820 (compare:CC (match_dup 0)
824 (define_expand "extendhidi2"
825 [(set (match_operand:DI 0 "gpc_reg_operand" "")
826 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
831 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
832 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
837 [(set_attr "type" "load,*")])
840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
841 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
843 (clobber (match_scratch:DI 2 "=r,r"))]
848 [(set_attr "type" "compare")
849 (set_attr "length" "4,8")])
852 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
853 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
855 (clobber (match_scratch:DI 2 ""))]
856 "TARGET_POWERPC64 && reload_completed"
858 (sign_extend:DI (match_dup 1)))
860 (compare:CC (match_dup 2)
865 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
866 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
868 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
869 (sign_extend:DI (match_dup 1)))]
874 [(set_attr "type" "compare")
875 (set_attr "length" "4,8")])
878 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
879 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
881 (set (match_operand:DI 0 "gpc_reg_operand" "")
882 (sign_extend:DI (match_dup 1)))]
883 "TARGET_POWERPC64 && reload_completed"
885 (sign_extend:DI (match_dup 1)))
887 (compare:CC (match_dup 0)
891 (define_expand "zero_extendsidi2"
892 [(set (match_operand:DI 0 "gpc_reg_operand" "")
893 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
898 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
899 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
904 [(set_attr "type" "load,*")])
907 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
908 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
910 (clobber (match_scratch:DI 2 "=r,r"))]
915 [(set_attr "type" "compare")
916 (set_attr "length" "4,8")])
919 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
920 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
922 (clobber (match_scratch:DI 2 ""))]
923 "TARGET_POWERPC64 && reload_completed"
925 (zero_extend:DI (match_dup 1)))
927 (compare:CC (match_dup 2)
932 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
933 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
935 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
936 (zero_extend:DI (match_dup 1)))]
941 [(set_attr "type" "compare")
942 (set_attr "length" "4,8")])
945 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
946 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
948 (set (match_operand:DI 0 "gpc_reg_operand" "")
949 (zero_extend:DI (match_dup 1)))]
950 "TARGET_POWERPC64 && reload_completed"
952 (zero_extend:DI (match_dup 1)))
954 (compare:CC (match_dup 0)
958 (define_expand "extendsidi2"
959 [(set (match_operand:DI 0 "gpc_reg_operand" "")
960 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
965 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
966 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
971 [(set_attr "type" "load,*")])
974 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
975 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
977 (clobber (match_scratch:DI 2 "=r,r"))]
982 [(set_attr "type" "compare")
983 (set_attr "length" "4,8")])
986 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
987 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
989 (clobber (match_scratch:DI 2 ""))]
990 "TARGET_POWERPC64 && reload_completed"
992 (sign_extend:DI (match_dup 1)))
994 (compare:CC (match_dup 2)
999 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1000 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1002 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1003 (sign_extend:DI (match_dup 1)))]
1008 [(set_attr "type" "compare")
1009 (set_attr "length" "4,8")])
1012 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1013 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1015 (set (match_operand:DI 0 "gpc_reg_operand" "")
1016 (sign_extend:DI (match_dup 1)))]
1017 "TARGET_POWERPC64 && reload_completed"
1019 (sign_extend:DI (match_dup 1)))
1021 (compare:CC (match_dup 0)
1025 (define_expand "zero_extendqisi2"
1026 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1027 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1032 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1033 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1037 {rlinm|rlwinm} %0,%1,0,0xff"
1038 [(set_attr "type" "load,*")])
1041 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1042 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1044 (clobber (match_scratch:SI 2 "=r,r"))]
1047 {andil.|andi.} %2,%1,0xff
1049 [(set_attr "type" "compare")
1050 (set_attr "length" "4,8")])
1053 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1054 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1056 (clobber (match_scratch:SI 2 ""))]
1059 (zero_extend:SI (match_dup 1)))
1061 (compare:CC (match_dup 2)
1066 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1067 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1069 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1070 (zero_extend:SI (match_dup 1)))]
1073 {andil.|andi.} %0,%1,0xff
1075 [(set_attr "type" "compare")
1076 (set_attr "length" "4,8")])
1079 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1080 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1082 (set (match_operand:SI 0 "gpc_reg_operand" "")
1083 (zero_extend:SI (match_dup 1)))]
1086 (zero_extend:SI (match_dup 1)))
1088 (compare:CC (match_dup 0)
1092 (define_expand "extendqisi2"
1093 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1094 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1099 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
1100 else if (TARGET_POWER)
1101 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
1103 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
1107 (define_insn "extendqisi2_ppc"
1108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1109 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1114 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1115 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1117 (clobber (match_scratch:SI 2 "=r,r"))]
1122 [(set_attr "type" "compare")
1123 (set_attr "length" "4,8")])
1126 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1127 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1129 (clobber (match_scratch:SI 2 ""))]
1130 "TARGET_POWERPC && reload_completed"
1132 (sign_extend:SI (match_dup 1)))
1134 (compare:CC (match_dup 2)
1139 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1140 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1142 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1143 (sign_extend:SI (match_dup 1)))]
1148 [(set_attr "type" "compare")
1149 (set_attr "length" "4,8")])
1152 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1153 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1155 (set (match_operand:SI 0 "gpc_reg_operand" "")
1156 (sign_extend:SI (match_dup 1)))]
1157 "TARGET_POWERPC && reload_completed"
1159 (sign_extend:SI (match_dup 1)))
1161 (compare:CC (match_dup 0)
1165 (define_expand "extendqisi2_power"
1166 [(parallel [(set (match_dup 2)
1167 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1169 (clobber (scratch:SI))])
1170 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1171 (ashiftrt:SI (match_dup 2)
1173 (clobber (scratch:SI))])]
1176 { operands[1] = gen_lowpart (SImode, operands[1]);
1177 operands[2] = gen_reg_rtx (SImode); }")
1179 (define_expand "extendqisi2_no_power"
1181 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1183 (set (match_operand:SI 0 "gpc_reg_operand" "")
1184 (ashiftrt:SI (match_dup 2)
1186 "! TARGET_POWER && ! TARGET_POWERPC"
1188 { operands[1] = gen_lowpart (SImode, operands[1]);
1189 operands[2] = gen_reg_rtx (SImode); }")
1191 (define_expand "zero_extendqihi2"
1192 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1193 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1198 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1199 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1203 {rlinm|rlwinm} %0,%1,0,0xff"
1204 [(set_attr "type" "load,*")])
1207 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1208 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1210 (clobber (match_scratch:HI 2 "=r,r"))]
1213 {andil.|andi.} %2,%1,0xff
1215 [(set_attr "type" "compare")
1216 (set_attr "length" "4,8")])
1219 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1220 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1222 (clobber (match_scratch:HI 2 ""))]
1225 (zero_extend:HI (match_dup 1)))
1227 (compare:CC (match_dup 2)
1232 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1233 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1235 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1236 (zero_extend:HI (match_dup 1)))]
1239 {andil.|andi.} %0,%1,0xff
1241 [(set_attr "type" "compare")
1242 (set_attr "length" "4,8")])
1245 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1246 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1248 (set (match_operand:HI 0 "gpc_reg_operand" "")
1249 (zero_extend:HI (match_dup 1)))]
1252 (zero_extend:HI (match_dup 1)))
1254 (compare:CC (match_dup 0)
1258 (define_expand "extendqihi2"
1259 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
1260 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1265 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
1266 else if (TARGET_POWER)
1267 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
1269 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
1273 (define_insn "extendqihi2_ppc"
1274 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1275 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1281 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1283 (clobber (match_scratch:HI 2 "=r,r"))]
1288 [(set_attr "type" "compare")
1289 (set_attr "length" "4,8")])
1292 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1293 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1295 (clobber (match_scratch:HI 2 ""))]
1296 "TARGET_POWERPC && reload_completed"
1298 (sign_extend:HI (match_dup 1)))
1300 (compare:CC (match_dup 2)
1305 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1306 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1308 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1309 (sign_extend:HI (match_dup 1)))]
1314 [(set_attr "type" "compare")
1315 (set_attr "length" "4,8")])
1318 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1319 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1321 (set (match_operand:HI 0 "gpc_reg_operand" "")
1322 (sign_extend:HI (match_dup 1)))]
1323 "TARGET_POWERPC && reload_completed"
1325 (sign_extend:HI (match_dup 1)))
1327 (compare:CC (match_dup 0)
1331 (define_expand "extendqihi2_power"
1332 [(parallel [(set (match_dup 2)
1333 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1335 (clobber (scratch:SI))])
1336 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1337 (ashiftrt:SI (match_dup 2)
1339 (clobber (scratch:SI))])]
1342 { operands[0] = gen_lowpart (SImode, operands[0]);
1343 operands[1] = gen_lowpart (SImode, operands[1]);
1344 operands[2] = gen_reg_rtx (SImode); }")
1346 (define_expand "extendqihi2_no_power"
1348 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1350 (set (match_operand:HI 0 "gpc_reg_operand" "")
1351 (ashiftrt:SI (match_dup 2)
1353 "! TARGET_POWER && ! TARGET_POWERPC"
1355 { operands[0] = gen_lowpart (SImode, operands[0]);
1356 operands[1] = gen_lowpart (SImode, operands[1]);
1357 operands[2] = gen_reg_rtx (SImode); }")
1359 (define_expand "zero_extendhisi2"
1360 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1361 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1366 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1367 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1371 {rlinm|rlwinm} %0,%1,0,0xffff"
1372 [(set_attr "type" "load,*")])
1375 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1376 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1378 (clobber (match_scratch:SI 2 "=r,r"))]
1381 {andil.|andi.} %2,%1,0xffff
1383 [(set_attr "type" "compare")
1384 (set_attr "length" "4,8")])
1387 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1388 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1390 (clobber (match_scratch:SI 2 ""))]
1393 (zero_extend:SI (match_dup 1)))
1395 (compare:CC (match_dup 2)
1400 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1401 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1403 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1404 (zero_extend:SI (match_dup 1)))]
1407 {andil.|andi.} %0,%1,0xffff
1409 [(set_attr "type" "compare")
1410 (set_attr "length" "4,8")])
1413 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1414 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1416 (set (match_operand:SI 0 "gpc_reg_operand" "")
1417 (zero_extend:SI (match_dup 1)))]
1420 (zero_extend:SI (match_dup 1)))
1422 (compare:CC (match_dup 0)
1426 (define_expand "extendhisi2"
1427 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1428 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1433 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1434 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1439 [(set_attr "type" "load,*")])
1442 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1443 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1445 (clobber (match_scratch:SI 2 "=r,r"))]
1448 {exts.|extsh.} %2,%1
1450 [(set_attr "type" "compare")
1451 (set_attr "length" "4,8")])
1454 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1455 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1457 (clobber (match_scratch:SI 2 ""))]
1460 (sign_extend:SI (match_dup 1)))
1462 (compare:CC (match_dup 2)
1467 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1468 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1470 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1471 (sign_extend:SI (match_dup 1)))]
1474 {exts.|extsh.} %0,%1
1476 [(set_attr "type" "compare")
1477 (set_attr "length" "4,8")])
1480 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1481 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1483 (set (match_operand:SI 0 "gpc_reg_operand" "")
1484 (sign_extend:SI (match_dup 1)))]
1487 (sign_extend:SI (match_dup 1)))
1489 (compare:CC (match_dup 0)
1493 ;; Fixed-point arithmetic insns.
1495 ;; Discourage ai/addic because of carry but provide it in an alternative
1496 ;; allowing register zero as source.
1497 (define_expand "addsi3"
1498 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1499 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1500 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1504 if (GET_CODE (operands[2]) == CONST_INT
1505 && ! add_operand (operands[2], SImode))
1507 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1508 ? operands[0] : gen_reg_rtx (SImode));
1510 HOST_WIDE_INT val = INTVAL (operands[2]);
1511 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
1512 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1514 /* The ordering here is important for the prolog expander.
1515 When space is allocated from the stack, adding 'low' first may
1516 produce a temporary deallocation (which would be bad). */
1517 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1518 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1523 (define_insn "*addsi3_internal1"
1524 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1525 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1526 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1530 {cal %0,%2(%1)|addi %0,%1,%2}
1532 {cau|addis} %0,%1,%v2"
1533 [(set_attr "length" "4,4,4,4")])
1535 (define_insn "addsi3_high"
1536 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1537 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1538 (high:SI (match_operand 2 "" ""))))]
1539 "TARGET_MACHO && !TARGET_64BIT"
1540 "{cau|addis} %0,%1,ha16(%2)"
1541 [(set_attr "length" "4")])
1543 (define_insn "*addsi3_internal2"
1544 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1545 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1546 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1548 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1549 "! TARGET_POWERPC64"
1551 {cax.|add.} %3,%1,%2
1552 {ai.|addic.} %3,%1,%2
1555 [(set_attr "type" "compare")
1556 (set_attr "length" "4,4,8,8")])
1559 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1560 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1561 (match_operand:SI 2 "reg_or_short_operand" ""))
1563 (clobber (match_scratch:SI 3 ""))]
1564 "! TARGET_POWERPC64 && reload_completed"
1566 (plus:SI (match_dup 1)
1569 (compare:CC (match_dup 3)
1573 (define_insn "*addsi3_internal3"
1574 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1575 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1576 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1578 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1579 (plus:SI (match_dup 1)
1581 "! TARGET_POWERPC64"
1583 {cax.|add.} %0,%1,%2
1584 {ai.|addic.} %0,%1,%2
1587 [(set_attr "type" "compare")
1588 (set_attr "length" "4,4,8,8")])
1591 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1592 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1593 (match_operand:SI 2 "reg_or_short_operand" ""))
1595 (set (match_operand:SI 0 "gpc_reg_operand" "")
1596 (plus:SI (match_dup 1) (match_dup 2)))]
1597 "! TARGET_POWERPC64 && reload_completed"
1599 (plus:SI (match_dup 1)
1602 (compare:CC (match_dup 0)
1606 ;; Split an add that we can't do in one insn into two insns, each of which
1607 ;; does one 16-bit part. This is used by combine. Note that the low-order
1608 ;; add should be last in case the result gets used in an address.
1611 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1612 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1613 (match_operand:SI 2 "non_add_cint_operand" "")))]
1615 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1616 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1619 HOST_WIDE_INT val = INTVAL (operands[2]);
1620 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
1621 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1623 operands[3] = GEN_INT (rest);
1624 operands[4] = GEN_INT (low);
1627 (define_insn "one_cmplsi2"
1628 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1629 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1634 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1635 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1637 (clobber (match_scratch:SI 2 "=r,r"))]
1638 "! TARGET_POWERPC64"
1642 [(set_attr "type" "compare")
1643 (set_attr "length" "4,8")])
1646 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1647 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1649 (clobber (match_scratch:SI 2 ""))]
1650 "! TARGET_POWERPC64 && reload_completed"
1652 (not:SI (match_dup 1)))
1654 (compare:CC (match_dup 2)
1659 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1660 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1662 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1663 (not:SI (match_dup 1)))]
1664 "! TARGET_POWERPC64"
1668 [(set_attr "type" "compare")
1669 (set_attr "length" "4,8")])
1672 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1673 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1675 (set (match_operand:SI 0 "gpc_reg_operand" "")
1676 (not:SI (match_dup 1)))]
1677 "! TARGET_POWERPC64 && reload_completed"
1679 (not:SI (match_dup 1)))
1681 (compare:CC (match_dup 0)
1686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1687 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1688 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1690 "{sf%I1|subf%I1c} %0,%2,%1")
1693 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1694 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1695 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1702 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1703 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1704 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1706 (clobber (match_scratch:SI 3 "=r,r"))]
1709 {sf.|subfc.} %3,%2,%1
1711 [(set_attr "type" "compare")
1712 (set_attr "length" "4,8")])
1715 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1716 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1717 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1719 (clobber (match_scratch:SI 3 "=r,r"))]
1720 "TARGET_POWERPC && ! TARGET_POWERPC64"
1724 [(set_attr "type" "compare")
1725 (set_attr "length" "4,8")])
1728 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1729 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1730 (match_operand:SI 2 "gpc_reg_operand" ""))
1732 (clobber (match_scratch:SI 3 ""))]
1733 "! TARGET_POWERPC64 && reload_completed"
1735 (minus:SI (match_dup 1)
1738 (compare:CC (match_dup 3)
1743 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1744 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1745 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1747 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1748 (minus:SI (match_dup 1) (match_dup 2)))]
1751 {sf.|subfc.} %0,%2,%1
1753 [(set_attr "type" "compare")
1754 (set_attr "length" "4,8")])
1757 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1758 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1759 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1761 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1762 (minus:SI (match_dup 1)
1764 "TARGET_POWERPC && ! TARGET_POWERPC64"
1768 [(set_attr "type" "compare")
1769 (set_attr "length" "4,8")])
1772 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1773 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1774 (match_operand:SI 2 "gpc_reg_operand" ""))
1776 (set (match_operand:SI 0 "gpc_reg_operand" "")
1777 (minus:SI (match_dup 1)
1779 "! TARGET_POWERPC64 && reload_completed"
1781 (minus:SI (match_dup 1)
1784 (compare:CC (match_dup 0)
1788 (define_expand "subsi3"
1789 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1790 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1791 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1795 if (GET_CODE (operands[2]) == CONST_INT)
1797 emit_insn (gen_addsi3 (operands[0], operands[1],
1798 negate_rtx (SImode, operands[2])));
1803 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1804 ;; instruction and some auxiliary computations. Then we just have a single
1805 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1808 (define_expand "sminsi3"
1810 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1811 (match_operand:SI 2 "reg_or_short_operand" ""))
1813 (minus:SI (match_dup 2) (match_dup 1))))
1814 (set (match_operand:SI 0 "gpc_reg_operand" "")
1815 (minus:SI (match_dup 2) (match_dup 3)))]
1818 { operands[3] = gen_reg_rtx (SImode); }")
1821 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1822 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1823 (match_operand:SI 2 "reg_or_short_operand" "")))
1824 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1827 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1829 (minus:SI (match_dup 2) (match_dup 1))))
1830 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1833 (define_expand "smaxsi3"
1835 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1836 (match_operand:SI 2 "reg_or_short_operand" ""))
1838 (minus:SI (match_dup 2) (match_dup 1))))
1839 (set (match_operand:SI 0 "gpc_reg_operand" "")
1840 (plus:SI (match_dup 3) (match_dup 1)))]
1843 { operands[3] = gen_reg_rtx (SImode); }")
1846 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1847 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1848 (match_operand:SI 2 "reg_or_short_operand" "")))
1849 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1852 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1854 (minus:SI (match_dup 2) (match_dup 1))))
1855 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1858 (define_expand "uminsi3"
1859 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1861 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1863 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1865 (minus:SI (match_dup 4) (match_dup 3))))
1866 (set (match_operand:SI 0 "gpc_reg_operand" "")
1867 (minus:SI (match_dup 2) (match_dup 3)))]
1871 operands[3] = gen_reg_rtx (SImode);
1872 operands[4] = gen_reg_rtx (SImode);
1873 operands[5] = GEN_INT (-2147483647 - 1);
1876 (define_expand "umaxsi3"
1877 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1879 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1881 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1883 (minus:SI (match_dup 4) (match_dup 3))))
1884 (set (match_operand:SI 0 "gpc_reg_operand" "")
1885 (plus:SI (match_dup 3) (match_dup 1)))]
1889 operands[3] = gen_reg_rtx (SImode);
1890 operands[4] = gen_reg_rtx (SImode);
1891 operands[5] = GEN_INT (-2147483647 - 1);
1895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1896 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1897 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1899 (minus:SI (match_dup 2) (match_dup 1))))]
1904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1906 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1907 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1909 (minus:SI (match_dup 2) (match_dup 1)))
1911 (clobber (match_scratch:SI 3 "=r,r"))]
1916 [(set_attr "type" "delayed_compare")
1917 (set_attr "length" "4,8")])
1920 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1922 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1923 (match_operand:SI 2 "reg_or_short_operand" ""))
1925 (minus:SI (match_dup 2) (match_dup 1)))
1927 (clobber (match_scratch:SI 3 ""))]
1928 "TARGET_POWER && reload_completed"
1930 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1932 (minus:SI (match_dup 2) (match_dup 1))))
1934 (compare:CC (match_dup 3)
1939 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1941 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1942 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1944 (minus:SI (match_dup 2) (match_dup 1)))
1946 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1947 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1949 (minus:SI (match_dup 2) (match_dup 1))))]
1954 [(set_attr "type" "delayed_compare")
1955 (set_attr "length" "4,8")])
1958 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1960 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
1961 (match_operand:SI 2 "reg_or_short_operand" ""))
1963 (minus:SI (match_dup 2) (match_dup 1)))
1965 (set (match_operand:SI 0 "gpc_reg_operand" "")
1966 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1968 (minus:SI (match_dup 2) (match_dup 1))))]
1969 "TARGET_POWER && reload_completed"
1971 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1973 (minus:SI (match_dup 2) (match_dup 1))))
1975 (compare:CC (match_dup 0)
1979 ;; We don't need abs with condition code because such comparisons should
1981 (define_expand "abssi2"
1982 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1983 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1989 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1994 (define_insn "abssi2_power"
1995 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1996 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2000 (define_insn "abssi2_nopower"
2001 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2002 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2003 (clobber (match_scratch:SI 2 "=&r,&r"))]
2007 return (TARGET_POWERPC)
2008 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
2009 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
2011 [(set_attr "length" "12")])
2014 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2015 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
2016 (clobber (match_scratch:SI 2 ""))]
2017 "! TARGET_POWER && reload_completed"
2018 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2019 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2020 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2023 (define_insn "*nabs_power"
2024 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2025 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2029 (define_insn "*nabs_no_power"
2030 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2031 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2032 (clobber (match_scratch:SI 2 "=&r,&r"))]
2036 return (TARGET_POWERPC)
2037 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
2038 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
2040 [(set_attr "length" "12")])
2043 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2044 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))))
2045 (clobber (match_scratch:SI 2 ""))]
2046 "! TARGET_POWER && reload_completed"
2047 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2048 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2049 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2052 (define_insn "negsi2"
2053 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2054 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2059 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2060 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2062 (clobber (match_scratch:SI 2 "=r,r"))]
2063 "! TARGET_POWERPC64"
2067 [(set_attr "type" "compare")
2068 (set_attr "length" "4,8")])
2071 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2072 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2074 (clobber (match_scratch:SI 2 ""))]
2075 "! TARGET_POWERPC64 && reload_completed"
2077 (neg:SI (match_dup 1)))
2079 (compare:CC (match_dup 2)
2084 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2085 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2087 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2088 (neg:SI (match_dup 1)))]
2089 "! TARGET_POWERPC64"
2093 [(set_attr "type" "compare")
2094 (set_attr "length" "4,8")])
2097 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2098 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2100 (set (match_operand:SI 0 "gpc_reg_operand" "")
2101 (neg:SI (match_dup 1)))]
2102 "! TARGET_POWERPC64 && reload_completed"
2104 (neg:SI (match_dup 1)))
2106 (compare:CC (match_dup 0)
2110 (define_insn "ffssi2"
2111 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
2112 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2114 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
2115 [(set_attr "length" "16")])
2117 (define_expand "mulsi3"
2118 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2119 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2120 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2125 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2127 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2131 (define_insn "mulsi3_mq"
2132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2133 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2134 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2135 (clobber (match_scratch:SI 3 "=q,q"))]
2138 {muls|mullw} %0,%1,%2
2139 {muli|mulli} %0,%1,%2"
2140 [(set_attr "type" "imul")])
2142 (define_insn "mulsi3_no_mq"
2143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2144 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2145 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2148 {muls|mullw} %0,%1,%2
2149 {muli|mulli} %0,%1,%2"
2150 [(set_attr "type" "imul")])
2153 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2154 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2155 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2157 (clobber (match_scratch:SI 3 "=r,r"))
2158 (clobber (match_scratch:SI 4 "=q,q"))]
2161 {muls.|mullw.} %3,%1,%2
2163 [(set_attr "type" "delayed_compare")
2164 (set_attr "length" "4,8")])
2167 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2168 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2169 (match_operand:SI 2 "gpc_reg_operand" ""))
2171 (clobber (match_scratch:SI 3 ""))
2172 (clobber (match_scratch:SI 4 ""))]
2173 "TARGET_POWER && reload_completed"
2174 [(parallel [(set (match_dup 3)
2175 (mult:SI (match_dup 1) (match_dup 2)))
2176 (clobber (match_dup 4))])
2178 (compare:CC (match_dup 3)
2183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2184 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2185 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2187 (clobber (match_scratch:SI 3 "=r,r"))]
2190 {muls.|mullw.} %3,%1,%2
2192 [(set_attr "type" "delayed_compare")
2193 (set_attr "length" "4,8")])
2196 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2197 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2198 (match_operand:SI 2 "gpc_reg_operand" ""))
2200 (clobber (match_scratch:SI 3 ""))]
2201 "! TARGET_POWER && reload_completed"
2203 (mult:SI (match_dup 1) (match_dup 2)))
2205 (compare:CC (match_dup 3)
2210 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2211 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2212 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2214 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2215 (mult:SI (match_dup 1) (match_dup 2)))
2216 (clobber (match_scratch:SI 4 "=q,q"))]
2219 {muls.|mullw.} %0,%1,%2
2221 [(set_attr "type" "delayed_compare")
2222 (set_attr "length" "4,8")])
2225 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2226 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2227 (match_operand:SI 2 "gpc_reg_operand" ""))
2229 (set (match_operand:SI 0 "gpc_reg_operand" "")
2230 (mult:SI (match_dup 1) (match_dup 2)))
2231 (clobber (match_scratch:SI 4 ""))]
2232 "TARGET_POWER && reload_completed"
2233 [(parallel [(set (match_dup 0)
2234 (mult:SI (match_dup 1) (match_dup 2)))
2235 (clobber (match_dup 4))])
2237 (compare:CC (match_dup 0)
2242 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2243 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2244 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2246 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2247 (mult:SI (match_dup 1) (match_dup 2)))]
2250 {muls.|mullw.} %0,%1,%2
2252 [(set_attr "type" "delayed_compare")
2253 (set_attr "length" "4,8")])
2256 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2257 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2258 (match_operand:SI 2 "gpc_reg_operand" ""))
2260 (set (match_operand:SI 0 "gpc_reg_operand" "")
2261 (mult:SI (match_dup 1) (match_dup 2)))]
2262 "! TARGET_POWER && reload_completed"
2264 (mult:SI (match_dup 1) (match_dup 2)))
2266 (compare:CC (match_dup 0)
2270 ;; Operand 1 is divided by operand 2; quotient goes to operand
2271 ;; 0 and remainder to operand 3.
2272 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2274 (define_expand "divmodsi4"
2275 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2276 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2277 (match_operand:SI 2 "gpc_reg_operand" "")))
2278 (set (match_operand:SI 3 "gpc_reg_operand" "")
2279 (mod:SI (match_dup 1) (match_dup 2)))])]
2280 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2283 if (! TARGET_POWER && ! TARGET_POWERPC)
2285 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2286 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2287 emit_insn (gen_divss_call ());
2288 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2289 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2296 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2297 (match_operand:SI 2 "gpc_reg_operand" "r")))
2298 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
2299 (mod:SI (match_dup 1) (match_dup 2)))]
2302 [(set_attr "type" "idiv")])
2304 (define_expand "udivsi3"
2305 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2306 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2307 (match_operand:SI 2 "gpc_reg_operand" "")))]
2308 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2311 if (! TARGET_POWER && ! TARGET_POWERPC)
2313 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2314 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2315 emit_insn (gen_quous_call ());
2316 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2319 else if (TARGET_POWER)
2321 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2326 (define_insn "udivsi3_mq"
2327 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2328 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2329 (match_operand:SI 2 "gpc_reg_operand" "r")))
2330 (clobber (match_scratch:SI 3 "=q"))]
2331 "TARGET_POWERPC && TARGET_POWER"
2333 [(set_attr "type" "idiv")])
2335 (define_insn "*udivsi3_no_mq"
2336 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2337 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2338 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2339 "TARGET_POWERPC && ! TARGET_POWER"
2341 [(set_attr "type" "idiv")])
2343 ;; For powers of two we can do srai/aze for divide and then adjust for
2344 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2345 ;; used; for PowerPC, force operands into register and do a normal divide;
2346 ;; for AIX common-mode, use quoss call on register operands.
2347 (define_expand "divsi3"
2348 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2349 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2350 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2354 if (GET_CODE (operands[2]) == CONST_INT
2355 && INTVAL (operands[2]) > 0
2356 && exact_log2 (INTVAL (operands[2])) >= 0)
2358 else if (TARGET_POWERPC)
2360 operands[2] = force_reg (SImode, operands[2]);
2363 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2367 else if (TARGET_POWER)
2371 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2372 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2373 emit_insn (gen_quoss_call ());
2374 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2379 (define_insn "divsi3_mq"
2380 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2381 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2382 (match_operand:SI 2 "gpc_reg_operand" "r")))
2383 (clobber (match_scratch:SI 3 "=q"))]
2384 "TARGET_POWERPC && TARGET_POWER"
2386 [(set_attr "type" "idiv")])
2388 (define_insn "*divsi3_no_mq"
2389 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2390 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2391 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2392 "TARGET_POWERPC && ! TARGET_POWER"
2394 [(set_attr "type" "idiv")])
2396 (define_expand "modsi3"
2397 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2398 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2399 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2407 if (GET_CODE (operands[2]) != CONST_INT
2408 || INTVAL (operands[2]) < 0
2409 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2412 temp1 = gen_reg_rtx (SImode);
2413 temp2 = gen_reg_rtx (SImode);
2415 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2416 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2417 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2422 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2423 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2424 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
2426 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2427 [(set_attr "length" "8")])
2430 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2431 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2432 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2434 (clobber (match_scratch:SI 3 "=r,r"))]
2437 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2439 [(set_attr "type" "compare")
2440 (set_attr "length" "8,12")])
2443 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2444 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2445 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2447 (clobber (match_scratch:SI 3 ""))]
2450 (div:SI (match_dup 1) (match_dup 2)))
2452 (compare:CC (match_dup 3)
2457 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2458 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2459 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2461 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2462 (div:SI (match_dup 1) (match_dup 2)))]
2465 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2467 [(set_attr "type" "compare")
2468 (set_attr "length" "8,12")])
2471 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2472 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2473 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2475 (set (match_operand:SI 0 "gpc_reg_operand" "")
2476 (div:SI (match_dup 1) (match_dup 2)))]
2479 (div:SI (match_dup 1) (match_dup 2)))
2481 (compare:CC (match_dup 0)
2486 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2489 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2491 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2492 (match_operand:SI 3 "gpc_reg_operand" "r")))
2493 (set (match_operand:SI 2 "register_operand" "=*q")
2496 (zero_extend:DI (match_dup 1)) (const_int 32))
2497 (zero_extend:DI (match_dup 4)))
2501 [(set_attr "type" "idiv")])
2503 ;; To do unsigned divide we handle the cases of the divisor looking like a
2504 ;; negative number. If it is a constant that is less than 2**31, we don't
2505 ;; have to worry about the branches. So make a few subroutines here.
2507 ;; First comes the normal case.
2508 (define_expand "udivmodsi4_normal"
2509 [(set (match_dup 4) (const_int 0))
2510 (parallel [(set (match_operand:SI 0 "" "")
2511 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2513 (zero_extend:DI (match_operand:SI 1 "" "")))
2514 (match_operand:SI 2 "" "")))
2515 (set (match_operand:SI 3 "" "")
2516 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2518 (zero_extend:DI (match_dup 1)))
2522 { operands[4] = gen_reg_rtx (SImode); }")
2524 ;; This handles the branches.
2525 (define_expand "udivmodsi4_tests"
2526 [(set (match_operand:SI 0 "" "") (const_int 0))
2527 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2528 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2529 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2530 (label_ref (match_operand:SI 4 "" "")) (pc)))
2531 (set (match_dup 0) (const_int 1))
2532 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2533 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2534 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2535 (label_ref (match_dup 4)) (pc)))]
2538 { operands[5] = gen_reg_rtx (CCUNSmode);
2539 operands[6] = gen_reg_rtx (CCmode);
2542 (define_expand "udivmodsi4"
2543 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2544 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2545 (match_operand:SI 2 "reg_or_cint_operand" "")))
2546 (set (match_operand:SI 3 "gpc_reg_operand" "")
2547 (umod:SI (match_dup 1) (match_dup 2)))])]
2555 if (! TARGET_POWERPC)
2557 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2558 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2559 emit_insn (gen_divus_call ());
2560 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2561 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2568 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2570 operands[2] = force_reg (SImode, operands[2]);
2571 label = gen_label_rtx ();
2572 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2573 operands[3], label));
2576 operands[2] = force_reg (SImode, operands[2]);
2578 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2586 ;; AIX architecture-independent common-mode multiply (DImode),
2587 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2588 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2589 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2590 ;; assumed unused if generating common-mode, so ignore.
2591 (define_insn "mulh_call"
2594 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2595 (sign_extend:DI (reg:SI 4)))
2597 (clobber (match_scratch:SI 0 "=l"))]
2598 "! TARGET_POWER && ! TARGET_POWERPC"
2600 [(set_attr "type" "imul")])
2602 (define_insn "mull_call"
2604 (mult:DI (sign_extend:DI (reg:SI 3))
2605 (sign_extend:DI (reg:SI 4))))
2606 (clobber (match_scratch:SI 0 "=l"))
2607 (clobber (reg:SI 0))]
2608 "! TARGET_POWER && ! TARGET_POWERPC"
2610 [(set_attr "type" "imul")])
2612 (define_insn "divss_call"
2614 (div:SI (reg:SI 3) (reg:SI 4)))
2616 (mod:SI (reg:SI 3) (reg:SI 4)))
2617 (clobber (match_scratch:SI 0 "=l"))
2618 (clobber (reg:SI 0))]
2619 "! TARGET_POWER && ! TARGET_POWERPC"
2621 [(set_attr "type" "idiv")])
2623 (define_insn "divus_call"
2625 (udiv:SI (reg:SI 3) (reg:SI 4)))
2627 (umod:SI (reg:SI 3) (reg:SI 4)))
2628 (clobber (match_scratch:SI 0 "=l"))
2629 (clobber (reg:SI 0))
2630 (clobber (match_scratch:CC 1 "=x"))
2631 (clobber (reg:CC 69))]
2632 "! TARGET_POWER && ! TARGET_POWERPC"
2634 [(set_attr "type" "idiv")])
2636 (define_insn "quoss_call"
2638 (div:SI (reg:SI 3) (reg:SI 4)))
2639 (clobber (match_scratch:SI 0 "=l"))]
2640 "! TARGET_POWER && ! TARGET_POWERPC"
2642 [(set_attr "type" "idiv")])
2644 (define_insn "quous_call"
2646 (udiv:SI (reg:SI 3) (reg:SI 4)))
2647 (clobber (match_scratch:SI 0 "=l"))
2648 (clobber (reg:SI 0))
2649 (clobber (match_scratch:CC 1 "=x"))
2650 (clobber (reg:CC 69))]
2651 "! TARGET_POWER && ! TARGET_POWERPC"
2653 [(set_attr "type" "idiv")])
2655 ;; Logical instructions
2656 ;; The logical instructions are mostly combined by using match_operator,
2657 ;; but the plain AND insns are somewhat different because there is no
2658 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2659 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2661 (define_insn "andsi3"
2662 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2663 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2664 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2665 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2669 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2670 {andil.|andi.} %0,%1,%b2
2671 {andiu.|andis.} %0,%1,%u2")
2673 ;; Note to set cr's other than cr0 we do the and immediate and then
2674 ;; the test again -- this avoids a mcrf which on the higher end
2675 ;; machines causes an execution serialization
2677 (define_insn "*andsi3_internal2"
2678 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2679 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2680 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2682 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2683 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2684 "! TARGET_POWERPC64"
2687 {andil.|andi.} %3,%1,%b2
2688 {andiu.|andis.} %3,%1,%u2
2689 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2694 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2695 (set_attr "length" "4,4,4,4,8,8,8,8")])
2698 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2699 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2700 (match_operand:SI 2 "and_operand" ""))
2702 (clobber (match_scratch:SI 3 ""))
2703 (clobber (match_scratch:CC 4 ""))]
2704 "! TARGET_POWERPC64 && reload_completed"
2705 [(parallel [(set (match_dup 3)
2706 (and:SI (match_dup 1)
2708 (clobber (match_dup 4))])
2710 (compare:CC (match_dup 3)
2714 (define_insn "*andsi3_internal3"
2715 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2716 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2717 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2719 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
2720 (and:SI (match_dup 1)
2722 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2723 "! TARGET_POWERPC64"
2726 {andil.|andi.} %0,%1,%b2
2727 {andiu.|andis.} %0,%1,%u2
2728 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2733 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2734 (set_attr "length" "4,4,4,4,8,8,8,8")])
2737 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2738 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2739 (match_operand:SI 2 "and_operand" ""))
2741 (set (match_operand:SI 0 "gpc_reg_operand" "")
2742 (and:SI (match_dup 1)
2744 (clobber (match_scratch:CC 4 ""))]
2745 "! TARGET_POWERPC64 && reload_completed"
2746 [(parallel [(set (match_dup 0)
2747 (and:SI (match_dup 1)
2749 (clobber (match_dup 4))])
2751 (compare:CC (match_dup 0)
2755 (define_expand "iorsi3"
2756 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2757 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2758 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2762 if (GET_CODE (operands[2]) == CONST_INT
2763 && ! logical_operand (operands[2], SImode))
2765 HOST_WIDE_INT value = INTVAL (operands[2]);
2766 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2767 ? operands[0] : gen_reg_rtx (SImode));
2769 emit_insn (gen_iorsi3 (tmp, operands[1],
2770 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2771 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2776 (define_expand "xorsi3"
2777 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2778 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2779 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
2783 if (GET_CODE (operands[2]) == CONST_INT
2784 && ! logical_operand (operands[2], SImode))
2786 HOST_WIDE_INT value = INTVAL (operands[2]);
2787 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
2788 ? operands[0] : gen_reg_rtx (SImode));
2790 emit_insn (gen_xorsi3 (tmp, operands[1],
2791 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2792 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2797 (define_insn "*boolsi3_internal1"
2798 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2799 (match_operator:SI 3 "boolean_or_operator"
2800 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2801 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
2805 {%q3il|%q3i} %0,%1,%b2
2806 {%q3iu|%q3is} %0,%1,%u2")
2808 (define_insn "*boolsi3_internal2"
2809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2810 (compare:CC (match_operator:SI 4 "boolean_or_operator"
2811 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2812 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2814 (clobber (match_scratch:SI 3 "=r,r"))]
2815 "! TARGET_POWERPC64"
2819 [(set_attr "type" "compare")
2820 (set_attr "length" "4,8")])
2823 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2824 (compare:CC (match_operator:SI 4 "boolean_operator"
2825 [(match_operand:SI 1 "gpc_reg_operand" "")
2826 (match_operand:SI 2 "gpc_reg_operand" "")])
2828 (clobber (match_scratch:SI 3 ""))]
2829 "! TARGET_POWERPC64 && reload_completed"
2830 [(set (match_dup 3) (match_dup 4))
2832 (compare:CC (match_dup 3)
2836 (define_insn "*boolsi3_internal3"
2837 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2838 (compare:CC (match_operator:SI 4 "boolean_operator"
2839 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
2840 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2842 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2844 "! TARGET_POWERPC64"
2848 [(set_attr "type" "compare")
2849 (set_attr "length" "4,8")])
2852 [(set (match_operand:CC 3 "cc_reg_operand" "")
2853 (compare:CC (match_operator:SI 4 "boolean_operator"
2854 [(match_operand:SI 1 "gpc_reg_operand" "")
2855 (match_operand:SI 2 "gpc_reg_operand" "")])
2857 (set (match_operand:SI 0 "gpc_reg_operand" "")
2859 "! TARGET_POWERPC64 && reload_completed"
2860 [(set (match_dup 0) (match_dup 4))
2862 (compare:CC (match_dup 0)
2866 ;; Split an logical operation that we can't do in one insn into two insns,
2867 ;; each of which does one 16-bit part. This is used by combine.
2870 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2871 (match_operator:SI 3 "boolean_or_operator"
2872 [(match_operand:SI 1 "gpc_reg_operand" "")
2873 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
2875 [(set (match_dup 0) (match_dup 4))
2876 (set (match_dup 0) (match_dup 5))]
2880 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2881 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
2883 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
2884 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
2888 (define_insn "*boolcsi3_internal1"
2889 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2890 (match_operator:SI 3 "boolean_operator"
2891 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2892 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
2896 (define_insn "*boolcsi3_internal2"
2897 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2898 (compare:CC (match_operator:SI 4 "boolean_operator"
2899 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2900 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2902 (clobber (match_scratch:SI 3 "=r,r"))]
2903 "! TARGET_POWERPC64"
2907 [(set_attr "type" "compare")
2908 (set_attr "length" "4,8")])
2911 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2912 (compare:CC (match_operator:SI 4 "boolean_operator"
2913 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2914 (match_operand:SI 2 "gpc_reg_operand" "")])
2916 (clobber (match_scratch:SI 3 ""))]
2917 "! TARGET_POWERPC64 && reload_completed"
2918 [(set (match_dup 3) (match_dup 4))
2920 (compare:CC (match_dup 3)
2924 (define_insn "*boolcsi3_internal3"
2925 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2926 (compare:CC (match_operator:SI 4 "boolean_operator"
2927 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2928 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
2930 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2932 "! TARGET_POWERPC64"
2936 [(set_attr "type" "compare")
2937 (set_attr "length" "4,8")])
2940 [(set (match_operand:CC 3 "cc_reg_operand" "")
2941 (compare:CC (match_operator:SI 4 "boolean_operator"
2942 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2943 (match_operand:SI 2 "gpc_reg_operand" "")])
2945 (set (match_operand:SI 0 "gpc_reg_operand" "")
2947 "! TARGET_POWERPC64 && reload_completed"
2948 [(set (match_dup 0) (match_dup 4))
2950 (compare:CC (match_dup 0)
2954 (define_insn "*boolccsi3_internal1"
2955 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2956 (match_operator:SI 3 "boolean_operator"
2957 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2958 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
2962 (define_insn "*boolccsi3_internal2"
2963 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2964 (compare:CC (match_operator:SI 4 "boolean_operator"
2965 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2966 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2968 (clobber (match_scratch:SI 3 "=r,r"))]
2969 "! TARGET_POWERPC64"
2973 [(set_attr "type" "compare")
2974 (set_attr "length" "4,8")])
2977 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2978 (compare:CC (match_operator:SI 4 "boolean_operator"
2979 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2980 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
2982 (clobber (match_scratch:SI 3 ""))]
2983 "! TARGET_POWERPC64 && reload_completed"
2984 [(set (match_dup 3) (match_dup 4))
2986 (compare:CC (match_dup 3)
2990 (define_insn "*boolccsi3_internal3"
2991 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2992 (compare:CC (match_operator:SI 4 "boolean_operator"
2993 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
2994 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
2996 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2998 "! TARGET_POWERPC64"
3002 [(set_attr "type" "compare")
3003 (set_attr "length" "4,8")])
3006 [(set (match_operand:CC 3 "cc_reg_operand" "")
3007 (compare:CC (match_operator:SI 4 "boolean_operator"
3008 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3009 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3011 (set (match_operand:SI 0 "gpc_reg_operand" "")
3013 "! TARGET_POWERPC64 && reload_completed"
3014 [(set (match_dup 0) (match_dup 4))
3016 (compare:CC (match_dup 0)
3020 ;; maskir insn. We need four forms because things might be in arbitrary
3021 ;; orders. Don't define forms that only set CR fields because these
3022 ;; would modify an input register.
3024 (define_insn "*maskir_internal1"
3025 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3026 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3027 (match_operand:SI 1 "gpc_reg_operand" "0"))
3028 (and:SI (match_dup 2)
3029 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3033 (define_insn "*maskir_internal2"
3034 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3035 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3036 (match_operand:SI 1 "gpc_reg_operand" "0"))
3037 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3042 (define_insn "*maskir_internal3"
3043 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3044 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3045 (match_operand:SI 3 "gpc_reg_operand" "r"))
3046 (and:SI (not:SI (match_dup 2))
3047 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3051 (define_insn "*maskir_internal4"
3052 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3053 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3054 (match_operand:SI 2 "gpc_reg_operand" "r"))
3055 (and:SI (not:SI (match_dup 2))
3056 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3060 (define_insn "*maskir_internal5"
3061 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3063 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3064 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3065 (and:SI (match_dup 2)
3066 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3068 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3069 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3070 (and:SI (match_dup 2) (match_dup 3))))]
3075 [(set_attr "type" "compare")
3076 (set_attr "length" "4,8")])
3079 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3081 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3082 (match_operand:SI 1 "gpc_reg_operand" ""))
3083 (and:SI (match_dup 2)
3084 (match_operand:SI 3 "gpc_reg_operand" "")))
3086 (set (match_operand:SI 0 "gpc_reg_operand" "")
3087 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3088 (and:SI (match_dup 2) (match_dup 3))))]
3089 "TARGET_POWER && reload_completed"
3091 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3092 (and:SI (match_dup 2) (match_dup 3))))
3094 (compare:CC (match_dup 0)
3098 (define_insn "*maskir_internal6"
3099 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3101 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3102 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3103 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3106 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3107 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3108 (and:SI (match_dup 3) (match_dup 2))))]
3113 [(set_attr "type" "compare")
3114 (set_attr "length" "4,8")])
3117 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3119 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3120 (match_operand:SI 1 "gpc_reg_operand" ""))
3121 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3124 (set (match_operand:SI 0 "gpc_reg_operand" "")
3125 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3126 (and:SI (match_dup 3) (match_dup 2))))]
3127 "TARGET_POWER && reload_completed"
3129 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3130 (and:SI (match_dup 3) (match_dup 2))))
3132 (compare:CC (match_dup 0)
3136 (define_insn "*maskir_internal7"
3137 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3139 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3140 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3141 (and:SI (not:SI (match_dup 2))
3142 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3144 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3145 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3146 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3151 [(set_attr "type" "compare")
3152 (set_attr "length" "4,8")])
3155 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3157 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3158 (match_operand:SI 3 "gpc_reg_operand" ""))
3159 (and:SI (not:SI (match_dup 2))
3160 (match_operand:SI 1 "gpc_reg_operand" "")))
3162 (set (match_operand:SI 0 "gpc_reg_operand" "")
3163 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3164 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3165 "TARGET_POWER && reload_completed"
3167 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3168 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3170 (compare:CC (match_dup 0)
3174 (define_insn "*maskir_internal8"
3175 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3177 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3178 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3179 (and:SI (not:SI (match_dup 2))
3180 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3182 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3183 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3184 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3189 [(set_attr "type" "compare")
3190 (set_attr "length" "4,8")])
3193 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3195 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3196 (match_operand:SI 2 "gpc_reg_operand" ""))
3197 (and:SI (not:SI (match_dup 2))
3198 (match_operand:SI 1 "gpc_reg_operand" "")))
3200 (set (match_operand:SI 0 "gpc_reg_operand" "")
3201 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3202 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3203 "TARGET_POWER && reload_completed"
3205 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3206 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3208 (compare:CC (match_dup 0)
3212 ;; Rotate and shift insns, in all their variants. These support shifts,
3213 ;; field inserts and extracts, and various combinations thereof.
3214 (define_expand "insv"
3215 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3216 (match_operand:SI 1 "const_int_operand" "")
3217 (match_operand:SI 2 "const_int_operand" ""))
3218 (match_operand 3 "gpc_reg_operand" ""))]
3222 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3223 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3224 compiler if the address of the structure is taken later. */
3225 if (GET_CODE (operands[0]) == SUBREG
3226 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3229 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3230 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3232 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3236 (define_insn "insvsi"
3237 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3238 (match_operand:SI 1 "const_int_operand" "i")
3239 (match_operand:SI 2 "const_int_operand" "i"))
3240 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3244 int start = INTVAL (operands[2]) & 31;
3245 int size = INTVAL (operands[1]) & 31;
3247 operands[4] = GEN_INT (32 - start - size);
3248 operands[1] = GEN_INT (start + size - 1);
3249 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3252 (define_insn "*insvsi_internal1"
3253 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3254 (match_operand:SI 1 "const_int_operand" "i")
3255 (match_operand:SI 2 "const_int_operand" "i"))
3256 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3257 (match_operand:SI 4 "const_int_operand" "i")))]
3258 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3261 int shift = INTVAL (operands[4]) & 31;
3262 int start = INTVAL (operands[2]) & 31;
3263 int size = INTVAL (operands[1]) & 31;
3265 operands[4] = GEN_INT (shift - start - size);
3266 operands[1] = GEN_INT (start + size - 1);
3267 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3270 (define_insn "*insvsi_internal2"
3271 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3272 (match_operand:SI 1 "const_int_operand" "i")
3273 (match_operand:SI 2 "const_int_operand" "i"))
3274 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3275 (match_operand:SI 4 "const_int_operand" "i")))]
3276 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3279 int shift = INTVAL (operands[4]) & 31;
3280 int start = INTVAL (operands[2]) & 31;
3281 int size = INTVAL (operands[1]) & 31;
3283 operands[4] = GEN_INT (32 - shift - start - size);
3284 operands[1] = GEN_INT (start + size - 1);
3285 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3288 (define_insn "*insvsi_internal3"
3289 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3290 (match_operand:SI 1 "const_int_operand" "i")
3291 (match_operand:SI 2 "const_int_operand" "i"))
3292 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3293 (match_operand:SI 4 "const_int_operand" "i")))]
3294 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3297 int shift = INTVAL (operands[4]) & 31;
3298 int start = INTVAL (operands[2]) & 31;
3299 int size = INTVAL (operands[1]) & 31;
3301 operands[4] = GEN_INT (32 - shift - start - size);
3302 operands[1] = GEN_INT (start + size - 1);
3303 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3306 (define_insn "*insvsi_internal4"
3307 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3308 (match_operand:SI 1 "const_int_operand" "i")
3309 (match_operand:SI 2 "const_int_operand" "i"))
3310 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3311 (match_operand:SI 4 "const_int_operand" "i")
3312 (match_operand:SI 5 "const_int_operand" "i")))]
3313 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3316 int extract_start = INTVAL (operands[5]) & 31;
3317 int extract_size = INTVAL (operands[4]) & 31;
3318 int insert_start = INTVAL (operands[2]) & 31;
3319 int insert_size = INTVAL (operands[1]) & 31;
3321 /* Align extract field with insert field */
3322 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3323 operands[1] = GEN_INT (insert_start + insert_size - 1);
3324 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3327 (define_insn "insvdi"
3328 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3329 (match_operand:SI 1 "const_int_operand" "i")
3330 (match_operand:SI 2 "const_int_operand" "i"))
3331 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3335 int start = INTVAL (operands[2]) & 63;
3336 int size = INTVAL (operands[1]) & 63;
3338 operands[1] = GEN_INT (64 - start - size);
3339 return \"rldimi %0,%3,%H1,%H2\";
3342 (define_expand "extzv"
3343 [(set (match_operand 0 "gpc_reg_operand" "")
3344 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3345 (match_operand:SI 2 "const_int_operand" "")
3346 (match_operand:SI 3 "const_int_operand" "")))]
3350 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3351 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3352 compiler if the address of the structure is taken later. */
3353 if (GET_CODE (operands[0]) == SUBREG
3354 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3357 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3358 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3360 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3364 (define_insn "extzvsi"
3365 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3366 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3367 (match_operand:SI 2 "const_int_operand" "i")
3368 (match_operand:SI 3 "const_int_operand" "i")))]
3372 int start = INTVAL (operands[3]) & 31;
3373 int size = INTVAL (operands[2]) & 31;
3375 if (start + size >= 32)
3376 operands[3] = const0_rtx;
3378 operands[3] = GEN_INT (start + size);
3379 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3382 (define_insn "*extzvsi_internal1"
3383 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3384 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3385 (match_operand:SI 2 "const_int_operand" "i,i")
3386 (match_operand:SI 3 "const_int_operand" "i,i"))
3388 (clobber (match_scratch:SI 4 "=r,r"))]
3389 "! TARGET_POWERPC64"
3392 int start = INTVAL (operands[3]) & 31;
3393 int size = INTVAL (operands[2]) & 31;
3395 /* Force split for non-cc0 compare. */
3396 if (which_alternative == 1)
3399 /* If the bitfield being tested fits in the upper or lower half of a
3400 word, it is possible to use andiu. or andil. to test it. This is
3401 useful because the condition register set-use delay is smaller for
3402 andi[ul]. than for rlinm. This doesn't work when the starting bit
3403 position is 0 because the LT and GT bits may be set wrong. */
3405 if ((start > 0 && start + size <= 16) || start >= 16)
3407 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3408 - (1 << (16 - (start & 15) - size))));
3410 return \"{andiu.|andis.} %4,%1,%3\";
3412 return \"{andil.|andi.} %4,%1,%3\";
3415 if (start + size >= 32)
3416 operands[3] = const0_rtx;
3418 operands[3] = GEN_INT (start + size);
3419 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3421 [(set_attr "type" "compare")
3422 (set_attr "length" "4,8")])
3425 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3426 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3427 (match_operand:SI 2 "const_int_operand" "")
3428 (match_operand:SI 3 "const_int_operand" ""))
3430 (clobber (match_scratch:SI 4 ""))]
3431 "! TARGET_POWERPC64 && reload_completed"
3433 (zero_extract:SI (match_dup 1) (match_dup 2)
3436 (compare:CC (match_dup 4)
3440 (define_insn "*extzvsi_internal2"
3441 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3442 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3443 (match_operand:SI 2 "const_int_operand" "i,i")
3444 (match_operand:SI 3 "const_int_operand" "i,i"))
3446 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3447 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3448 "! TARGET_POWERPC64"
3451 int start = INTVAL (operands[3]) & 31;
3452 int size = INTVAL (operands[2]) & 31;
3454 /* Force split for non-cc0 compare. */
3455 if (which_alternative == 1)
3458 if (start >= 16 && start + size == 32)
3460 operands[3] = GEN_INT ((1 << (32 - start)) - 1);
3461 return \"{andil.|andi.} %0,%1,%3\";
3464 if (start + size >= 32)
3465 operands[3] = const0_rtx;
3467 operands[3] = GEN_INT (start + size);
3468 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3470 [(set_attr "type" "delayed_compare")
3471 (set_attr "length" "4,8")])
3474 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3475 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3476 (match_operand:SI 2 "const_int_operand" "")
3477 (match_operand:SI 3 "const_int_operand" ""))
3479 (set (match_operand:SI 0 "gpc_reg_operand" "")
3480 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3481 "! TARGET_POWERPC64 && reload_completed"
3483 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3485 (compare:CC (match_dup 0)
3489 (define_insn "extzvdi"
3490 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3491 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3492 (match_operand:SI 2 "const_int_operand" "i")
3493 (match_operand:SI 3 "const_int_operand" "i")))]
3497 int start = INTVAL (operands[3]) & 63;
3498 int size = INTVAL (operands[2]) & 63;
3500 if (start + size >= 64)
3501 operands[3] = const0_rtx;
3503 operands[3] = GEN_INT (start + size);
3504 operands[2] = GEN_INT (64 - size);
3505 return \"rldicl %0,%1,%3,%2\";
3508 (define_insn "*extzvdi_internal1"
3509 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3510 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3511 (match_operand:SI 2 "const_int_operand" "i")
3512 (match_operand:SI 3 "const_int_operand" "i"))
3514 (clobber (match_scratch:DI 4 "=r"))]
3518 int start = INTVAL (operands[3]) & 63;
3519 int size = INTVAL (operands[2]) & 63;
3521 if (start + size >= 64)
3522 operands[3] = const0_rtx;
3524 operands[3] = GEN_INT (start + size);
3525 operands[2] = GEN_INT (64 - size);
3526 return \"rldicl. %4,%1,%3,%2\";
3529 (define_insn "*extzvdi_internal2"
3530 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3531 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3532 (match_operand:SI 2 "const_int_operand" "i")
3533 (match_operand:SI 3 "const_int_operand" "i"))
3535 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3536 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3540 int start = INTVAL (operands[3]) & 63;
3541 int size = INTVAL (operands[2]) & 63;
3543 if (start + size >= 64)
3544 operands[3] = const0_rtx;
3546 operands[3] = GEN_INT (start + size);
3547 operands[2] = GEN_INT (64 - size);
3548 return \"rldicl. %0,%1,%3,%2\";
3551 (define_insn "rotlsi3"
3552 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3553 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3554 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3556 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3558 (define_insn "*rotlsi3_internal2"
3559 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3560 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3561 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3563 (clobber (match_scratch:SI 3 "=r,r"))]
3564 "! TARGET_POWERPC64"
3566 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3568 [(set_attr "type" "delayed_compare")
3569 (set_attr "length" "4,8")])
3572 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3573 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3574 (match_operand:SI 2 "reg_or_cint_operand" ""))
3576 (clobber (match_scratch:SI 3 ""))]
3577 "! TARGET_POWERPC64 && reload_completed"
3579 (rotate:SI (match_dup 1) (match_dup 2)))
3581 (compare:CC (match_dup 3)
3585 (define_insn "*rotlsi3_internal3"
3586 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3587 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3588 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3590 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3591 (rotate:SI (match_dup 1) (match_dup 2)))]
3592 "! TARGET_POWERPC64"
3594 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3596 [(set_attr "type" "delayed_compare")
3597 (set_attr "length" "4,8")])
3600 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3601 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3602 (match_operand:SI 2 "reg_or_cint_operand" ""))
3604 (set (match_operand:SI 0 "gpc_reg_operand" "")
3605 (rotate:SI (match_dup 1) (match_dup 2)))]
3606 "! TARGET_POWERPC64 && reload_completed"
3608 (rotate:SI (match_dup 1) (match_dup 2)))
3610 (compare:CC (match_dup 0)
3614 (define_insn "*rotlsi3_internal4"
3615 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3616 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3617 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3618 (match_operand:SI 3 "mask_operand" "T")))]
3620 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3622 (define_insn "*rotlsi3_internal5"
3623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3625 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3626 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3627 (match_operand:SI 3 "mask_operand" "T,T"))
3629 (clobber (match_scratch:SI 4 "=r,r"))]
3630 "! TARGET_POWERPC64"
3632 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3634 [(set_attr "type" "delayed_compare")
3635 (set_attr "length" "4,8")])
3638 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3640 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3641 (match_operand:SI 2 "reg_or_cint_operand" ""))
3642 (match_operand:SI 3 "mask_operand" ""))
3644 (clobber (match_scratch:SI 4 ""))]
3645 "! TARGET_POWERPC64 && reload_completed"
3647 (and:SI (rotate:SI (match_dup 1)
3651 (compare:CC (match_dup 4)
3655 (define_insn "*rotlsi3_internal6"
3656 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3658 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3659 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3660 (match_operand:SI 3 "mask_operand" "T,T"))
3662 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3663 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3664 "! TARGET_POWERPC64"
3666 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3668 [(set_attr "type" "delayed_compare")
3669 (set_attr "length" "4,8")])
3672 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3674 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3675 (match_operand:SI 2 "reg_or_cint_operand" ""))
3676 (match_operand:SI 3 "mask_operand" ""))
3678 (set (match_operand:SI 0 "gpc_reg_operand" "")
3679 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3680 "! TARGET_POWERPC64 && reload_completed"
3682 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3684 (compare:CC (match_dup 0)
3688 (define_insn "*rotlsi3_internal7"
3689 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3692 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3693 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3695 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3697 (define_insn "*rotlsi3_internal8"
3698 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3699 (compare:CC (zero_extend:SI
3701 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3702 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3704 (clobber (match_scratch:SI 3 "=r,r"))]
3707 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3709 [(set_attr "type" "delayed_compare")
3710 (set_attr "length" "4,8")])
3713 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3714 (compare:CC (zero_extend:SI
3716 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3717 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3719 (clobber (match_scratch:SI 3 ""))]
3722 (zero_extend:SI (subreg:QI
3723 (rotate:SI (match_dup 1)
3726 (compare:CC (match_dup 3)
3730 (define_insn "*rotlsi3_internal9"
3731 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3732 (compare:CC (zero_extend:SI
3734 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3735 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3737 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3738 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3741 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3743 [(set_attr "type" "delayed_compare")
3744 (set_attr "length" "4,8")])
3747 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3748 (compare:CC (zero_extend:SI
3750 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3751 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3753 (set (match_operand:SI 0 "gpc_reg_operand" "")
3754 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3757 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3759 (compare:CC (match_dup 0)
3763 (define_insn "*rotlsi3_internal10"
3764 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3767 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3768 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3770 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
3772 (define_insn "*rotlsi3_internal11"
3773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3774 (compare:CC (zero_extend:SI
3776 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3777 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3779 (clobber (match_scratch:SI 3 "=r,r"))]
3782 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
3784 [(set_attr "type" "delayed_compare")
3785 (set_attr "length" "4,8")])
3788 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3789 (compare:CC (zero_extend:SI
3791 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3792 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3794 (clobber (match_scratch:SI 3 ""))]
3797 (zero_extend:SI (subreg:HI
3798 (rotate:SI (match_dup 1)
3801 (compare:CC (match_dup 3)
3805 (define_insn "*rotlsi3_internal12"
3806 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3807 (compare:CC (zero_extend:SI
3809 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3810 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3812 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3813 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3816 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
3818 [(set_attr "type" "delayed_compare")
3819 (set_attr "length" "4,8")])
3822 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3823 (compare:CC (zero_extend:SI
3825 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3826 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3828 (set (match_operand:SI 0 "gpc_reg_operand" "")
3829 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3832 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
3834 (compare:CC (match_dup 0)
3838 ;; Note that we use "sle." instead of "sl." so that we can set
3839 ;; SHIFT_COUNT_TRUNCATED.
3841 (define_expand "ashlsi3"
3842 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
3843 (use (match_operand:SI 1 "gpc_reg_operand" ""))
3844 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
3849 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
3851 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
3855 (define_insn "ashlsi3_power"
3856 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3857 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3858 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
3859 (clobber (match_scratch:SI 3 "=q,X"))]
3863 {sli|slwi} %0,%1,%h2")
3865 (define_insn "ashlsi3_no_power"
3866 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3867 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3868 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3870 "{sl|slw}%I2 %0,%1,%h2")
3873 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3874 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3875 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3877 (clobber (match_scratch:SI 3 "=r,r,r,r"))
3878 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3882 {sli.|slwi.} %3,%1,%h2
3885 [(set_attr "type" "delayed_compare")
3886 (set_attr "length" "4,4,8,8")])
3889 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3890 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3891 (match_operand:SI 2 "reg_or_cint_operand" ""))
3893 (clobber (match_scratch:SI 3 ""))
3894 (clobber (match_scratch:SI 4 ""))]
3895 "TARGET_POWER && reload_completed"
3896 [(parallel [(set (match_dup 3)
3897 (ashift:SI (match_dup 1) (match_dup 2)))
3898 (clobber (match_dup 4))])
3900 (compare:CC (match_dup 3)
3905 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3906 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3907 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3909 (clobber (match_scratch:SI 3 "=r,r"))]
3910 "! TARGET_POWER && ! TARGET_POWERPC64"
3912 {sl|slw}%I2. %3,%1,%h2
3914 [(set_attr "type" "delayed_compare")
3915 (set_attr "length" "4,8")])
3918 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3919 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3920 (match_operand:SI 2 "reg_or_cint_operand" ""))
3922 (clobber (match_scratch:SI 3 ""))]
3923 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3925 (ashift:SI (match_dup 1) (match_dup 2)))
3927 (compare:CC (match_dup 3)
3932 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3933 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3934 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3936 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3937 (ashift:SI (match_dup 1) (match_dup 2)))
3938 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
3942 {sli.|slwi.} %0,%1,%h2
3945 [(set_attr "type" "delayed_compare")
3946 (set_attr "length" "4,4,8,8")])
3949 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3950 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3951 (match_operand:SI 2 "reg_or_cint_operand" ""))
3953 (set (match_operand:SI 0 "gpc_reg_operand" "")
3954 (ashift:SI (match_dup 1) (match_dup 2)))
3955 (clobber (match_scratch:SI 4 ""))]
3956 "TARGET_POWER && reload_completed"
3957 [(parallel [(set (match_dup 0)
3958 (ashift:SI (match_dup 1) (match_dup 2)))
3959 (clobber (match_dup 4))])
3961 (compare:CC (match_dup 0)
3966 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3967 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3968 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3970 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3971 (ashift:SI (match_dup 1) (match_dup 2)))]
3972 "! TARGET_POWER && ! TARGET_POWERPC64"
3974 {sl|slw}%I2. %0,%1,%h2
3976 [(set_attr "type" "delayed_compare")
3977 (set_attr "length" "4,8")])
3980 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3981 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
3982 (match_operand:SI 2 "reg_or_cint_operand" ""))
3984 (set (match_operand:SI 0 "gpc_reg_operand" "")
3985 (ashift:SI (match_dup 1) (match_dup 2)))]
3986 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
3988 (ashift:SI (match_dup 1) (match_dup 2)))
3990 (compare:CC (match_dup 0)
3995 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3996 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3997 (match_operand:SI 2 "const_int_operand" "i"))
3998 (match_operand:SI 3 "mask_operand" "T")))]
3999 "includes_lshift_p (operands[2], operands[3])"
4000 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4003 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4005 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4006 (match_operand:SI 2 "const_int_operand" "i,i"))
4007 (match_operand:SI 3 "mask_operand" "T,T"))
4009 (clobber (match_scratch:SI 4 "=r,r"))]
4010 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
4012 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4014 [(set_attr "type" "delayed_compare")
4015 (set_attr "length" "4,8")])
4018 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4020 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4021 (match_operand:SI 2 "const_int_operand" ""))
4022 (match_operand:SI 3 "mask_operand" ""))
4024 (clobber (match_scratch:SI 4 ""))]
4025 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
4027 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4030 (compare:CC (match_dup 4)
4035 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4037 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4038 (match_operand:SI 2 "const_int_operand" "i,i"))
4039 (match_operand:SI 3 "mask_operand" "T,T"))
4041 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4042 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4043 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])"
4045 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4047 [(set_attr "type" "delayed_compare")
4048 (set_attr "length" "4,8")])
4051 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4053 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4054 (match_operand:SI 2 "const_int_operand" ""))
4055 (match_operand:SI 3 "mask_operand" ""))
4057 (set (match_operand:SI 0 "gpc_reg_operand" "")
4058 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4059 "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed"
4061 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4063 (compare:CC (match_dup 0)
4067 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4069 (define_expand "lshrsi3"
4070 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4071 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4072 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4077 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4079 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4083 (define_insn "lshrsi3_power"
4084 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4085 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4086 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4087 (clobber (match_scratch:SI 3 "=q,X,X"))]
4092 {s%A2i|s%A2wi} %0,%1,%h2")
4094 (define_insn "lshrsi3_no_power"
4095 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4096 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4097 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4101 {sr|srw}%I2 %0,%1,%h2")
4104 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4105 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4106 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4108 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4109 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4114 {s%A2i.|s%A2wi.} %3,%1,%h2
4118 [(set_attr "type" "delayed_compare")
4119 (set_attr "length" "4,4,4,8,8,8")])
4122 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4123 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4124 (match_operand:SI 2 "reg_or_cint_operand" ""))
4126 (clobber (match_scratch:SI 3 ""))
4127 (clobber (match_scratch:SI 4 ""))]
4128 "TARGET_POWER && reload_completed"
4129 [(parallel [(set (match_dup 3)
4130 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4131 (clobber (match_dup 4))])
4133 (compare:CC (match_dup 3)
4138 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4139 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4140 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4142 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4143 "! TARGET_POWER && ! TARGET_POWERPC64"
4146 {sr|srw}%I2. %3,%1,%h2
4149 [(set_attr "type" "delayed_compare")
4150 (set_attr "length" "4,4,8,8")])
4153 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4154 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4155 (match_operand:SI 2 "reg_or_cint_operand" ""))
4157 (clobber (match_scratch:SI 3 ""))]
4158 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4160 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4162 (compare:CC (match_dup 3)
4167 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4168 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4169 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4171 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4172 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4173 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4178 {s%A2i.|s%A2wi.} %0,%1,%h2
4182 [(set_attr "type" "delayed_compare")
4183 (set_attr "length" "4,4,4,8,8,8")])
4186 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4187 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4188 (match_operand:SI 2 "reg_or_cint_operand" ""))
4190 (set (match_operand:SI 0 "gpc_reg_operand" "")
4191 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4192 (clobber (match_scratch:SI 4 ""))]
4193 "TARGET_POWER && reload_completed"
4194 [(parallel [(set (match_dup 0)
4195 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4196 (clobber (match_dup 4))])
4198 (compare:CC (match_dup 0)
4203 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4204 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4205 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4207 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4208 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4209 "! TARGET_POWER && ! TARGET_POWERPC64"
4212 {sr|srw}%I2. %0,%1,%h2
4215 [(set_attr "type" "delayed_compare")
4216 (set_attr "length" "4,4,8,8")])
4219 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4220 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4221 (match_operand:SI 2 "reg_or_cint_operand" ""))
4223 (set (match_operand:SI 0 "gpc_reg_operand" "")
4224 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4225 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4227 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4229 (compare:CC (match_dup 0)
4234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4235 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4236 (match_operand:SI 2 "const_int_operand" "i"))
4237 (match_operand:SI 3 "mask_operand" "T")))]
4238 "includes_rshift_p (operands[2], operands[3])"
4239 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4242 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4244 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4245 (match_operand:SI 2 "const_int_operand" "i,i"))
4246 (match_operand:SI 3 "mask_operand" "T,T"))
4248 (clobber (match_scratch:SI 4 "=r,r"))]
4249 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
4251 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4253 [(set_attr "type" "delayed_compare")
4254 (set_attr "length" "4,8")])
4257 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4259 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4260 (match_operand:SI 2 "const_int_operand" ""))
4261 (match_operand:SI 3 "mask_operand" ""))
4263 (clobber (match_scratch:SI 4 ""))]
4264 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
4266 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4269 (compare:CC (match_dup 4)
4274 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4276 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4277 (match_operand:SI 2 "const_int_operand" "i,i"))
4278 (match_operand:SI 3 "mask_operand" "T,T"))
4280 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4281 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4282 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])"
4284 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4286 [(set_attr "type" "delayed_compare")
4287 (set_attr "length" "4,8")])
4290 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4292 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4293 (match_operand:SI 2 "const_int_operand" ""))
4294 (match_operand:SI 3 "mask_operand" ""))
4296 (set (match_operand:SI 0 "gpc_reg_operand" "")
4297 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4298 "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed"
4300 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4302 (compare:CC (match_dup 0)
4307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4310 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4311 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4312 "includes_rshift_p (operands[2], GEN_INT (255))"
4313 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4320 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4321 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4323 (clobber (match_scratch:SI 3 "=r,r"))]
4324 "includes_rshift_p (operands[2], GEN_INT (255))"
4326 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4328 [(set_attr "type" "delayed_compare")
4329 (set_attr "length" "4,8")])
4332 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4336 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4337 (match_operand:SI 2 "const_int_operand" "")) 0))
4339 (clobber (match_scratch:SI 3 ""))]
4340 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4342 (zero_extend:SI (subreg:QI
4343 (lshiftrt:SI (match_dup 1)
4346 (compare:CC (match_dup 3)
4351 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4355 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4356 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4358 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4359 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4360 "includes_rshift_p (operands[2], GEN_INT (255))"
4362 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4364 [(set_attr "type" "delayed_compare")
4365 (set_attr "length" "4,8")])
4368 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4372 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4373 (match_operand:SI 2 "const_int_operand" "")) 0))
4375 (set (match_operand:SI 0 "gpc_reg_operand" "")
4376 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4377 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4379 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4381 (compare:CC (match_dup 0)
4386 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4389 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4390 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4391 "includes_rshift_p (operands[2], GEN_INT (65535))"
4392 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4395 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4399 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4400 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4402 (clobber (match_scratch:SI 3 "=r,r"))]
4403 "includes_rshift_p (operands[2], GEN_INT (65535))"
4405 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4407 [(set_attr "type" "delayed_compare")
4408 (set_attr "length" "4,8")])
4411 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4415 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4416 (match_operand:SI 2 "const_int_operand" "")) 0))
4418 (clobber (match_scratch:SI 3 ""))]
4419 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4421 (zero_extend:SI (subreg:HI
4422 (lshiftrt:SI (match_dup 1)
4425 (compare:CC (match_dup 3)
4430 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4434 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4435 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4437 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4438 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4439 "includes_rshift_p (operands[2], GEN_INT (65535))"
4441 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4443 [(set_attr "type" "delayed_compare")
4444 (set_attr "length" "4,8")])
4447 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4451 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4452 (match_operand:SI 2 "const_int_operand" "")) 0))
4454 (set (match_operand:SI 0 "gpc_reg_operand" "")
4455 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4456 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4458 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4460 (compare:CC (match_dup 0)
4465 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4467 (match_operand:SI 1 "gpc_reg_operand" "r"))
4468 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4474 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4476 (match_operand:SI 1 "gpc_reg_operand" "r"))
4477 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4483 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4485 (match_operand:SI 1 "gpc_reg_operand" "r"))
4486 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4492 (define_expand "ashrsi3"
4493 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4494 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4495 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4500 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4502 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4506 (define_insn "ashrsi3_power"
4507 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4508 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4509 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4510 (clobber (match_scratch:SI 3 "=q,X"))]
4514 {srai|srawi} %0,%1,%h2")
4516 (define_insn "ashrsi3_no_power"
4517 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4518 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4519 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4521 "{sra|sraw}%I2 %0,%1,%h2")
4524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4525 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4526 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4528 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4529 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4533 {srai.|srawi.} %3,%1,%h2
4536 [(set_attr "type" "delayed_compare")
4537 (set_attr "length" "4,4,8,8")])
4540 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4541 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4542 (match_operand:SI 2 "reg_or_cint_operand" ""))
4544 (clobber (match_scratch:SI 3 ""))
4545 (clobber (match_scratch:SI 4 ""))]
4546 "TARGET_POWER && reload_completed"
4547 [(parallel [(set (match_dup 3)
4548 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4549 (clobber (match_dup 4))])
4551 (compare:CC (match_dup 3)
4556 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4557 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4558 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4560 (clobber (match_scratch:SI 3 "=r,r"))]
4563 {sra|sraw}%I2. %3,%1,%h2
4565 [(set_attr "type" "delayed_compare")
4566 (set_attr "length" "4,8")])
4569 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4570 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4571 (match_operand:SI 2 "reg_or_cint_operand" ""))
4573 (clobber (match_scratch:SI 3 ""))]
4574 "! TARGET_POWER && reload_completed"
4576 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4578 (compare:CC (match_dup 3)
4583 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4584 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4585 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4587 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4588 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4589 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4593 {srai.|srawi.} %0,%1,%h2
4596 [(set_attr "type" "delayed_compare")
4597 (set_attr "length" "4,4,8,8")])
4600 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4601 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4602 (match_operand:SI 2 "reg_or_cint_operand" ""))
4604 (set (match_operand:SI 0 "gpc_reg_operand" "")
4605 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4606 (clobber (match_scratch:SI 4 ""))]
4607 "TARGET_POWER && reload_completed"
4608 [(parallel [(set (match_dup 0)
4609 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4610 (clobber (match_dup 4))])
4612 (compare:CC (match_dup 0)
4617 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4618 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4619 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4621 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4622 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4625 {sra|sraw}%I2. %0,%1,%h2
4627 [(set_attr "type" "delayed_compare")
4628 (set_attr "length" "4,8")])
4631 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4632 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4633 (match_operand:SI 2 "reg_or_cint_operand" ""))
4635 (set (match_operand:SI 0 "gpc_reg_operand" "")
4636 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4637 "! TARGET_POWER && reload_completed"
4639 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4641 (compare:CC (match_dup 0)
4645 ;; Floating-point insns, excluding normal data motion.
4647 ;; PowerPC has a full set of single-precision floating point instructions.
4649 ;; For the POWER architecture, we pretend that we have both SFmode and
4650 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4651 ;; The only conversions we will do will be when storing to memory. In that
4652 ;; case, we will use the "frsp" instruction before storing.
4654 ;; Note that when we store into a single-precision memory location, we need to
4655 ;; use the frsp insn first. If the register being stored isn't dead, we
4656 ;; need a scratch register for the frsp. But this is difficult when the store
4657 ;; is done by reload. It is not incorrect to do the frsp on the register in
4658 ;; this case, we just lose precision that we would have otherwise gotten but
4659 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4661 (define_insn "extendsfdf2"
4662 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4663 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4667 if (REGNO (operands[0]) == REGNO (operands[1]))
4670 return \"fmr %0,%1\";
4672 [(set_attr "type" "fp")])
4674 (define_insn "truncdfsf2"
4675 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4676 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4679 [(set_attr "type" "fp")])
4681 (define_insn "aux_truncdfsf2"
4682 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4683 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
4684 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4686 [(set_attr "type" "fp")])
4688 (define_insn "negsf2"
4689 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4690 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4693 [(set_attr "type" "fp")])
4695 (define_insn "abssf2"
4696 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4697 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4700 [(set_attr "type" "fp")])
4703 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4704 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4707 [(set_attr "type" "fp")])
4709 (define_expand "addsf3"
4710 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4711 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4712 (match_operand:SF 2 "gpc_reg_operand" "")))]
4717 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4718 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4719 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4720 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4722 [(set_attr "type" "fp")])
4725 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4726 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4727 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4728 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4729 "{fa|fadd} %0,%1,%2"
4730 [(set_attr "type" "fp")])
4732 (define_expand "subsf3"
4733 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4734 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4735 (match_operand:SF 2 "gpc_reg_operand" "")))]
4740 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4741 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4742 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4743 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4745 [(set_attr "type" "fp")])
4748 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4749 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4750 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4751 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4752 "{fs|fsub} %0,%1,%2"
4753 [(set_attr "type" "fp")])
4755 (define_expand "mulsf3"
4756 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4757 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4758 (match_operand:SF 2 "gpc_reg_operand" "")))]
4763 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4764 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4765 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4766 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4768 [(set_attr "type" "fp")])
4771 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4772 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4773 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4774 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4775 "{fm|fmul} %0,%1,%2"
4776 [(set_attr "type" "dmul")])
4778 (define_expand "divsf3"
4779 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4780 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
4781 (match_operand:SF 2 "gpc_reg_operand" "")))]
4786 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4787 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4788 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4789 "TARGET_POWERPC && TARGET_HARD_FLOAT"
4791 [(set_attr "type" "sdiv")])
4794 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4795 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4796 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4797 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4798 "{fd|fdiv} %0,%1,%2"
4799 [(set_attr "type" "ddiv")])
4802 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4803 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4804 (match_operand:SF 2 "gpc_reg_operand" "f"))
4805 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4806 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4807 "fmadds %0,%1,%2,%3"
4808 [(set_attr "type" "fp")])
4811 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4812 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4813 (match_operand:SF 2 "gpc_reg_operand" "f"))
4814 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4815 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4816 "{fma|fmadd} %0,%1,%2,%3"
4817 [(set_attr "type" "dmul")])
4820 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4821 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4822 (match_operand:SF 2 "gpc_reg_operand" "f"))
4823 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4824 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4825 "fmsubs %0,%1,%2,%3"
4826 [(set_attr "type" "fp")])
4829 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4830 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4831 (match_operand:SF 2 "gpc_reg_operand" "f"))
4832 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4833 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4834 "{fms|fmsub} %0,%1,%2,%3"
4835 [(set_attr "type" "dmul")])
4838 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4839 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4840 (match_operand:SF 2 "gpc_reg_operand" "f"))
4841 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4842 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4843 "fnmadds %0,%1,%2,%3"
4844 [(set_attr "type" "fp")])
4847 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4848 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4849 (match_operand:SF 2 "gpc_reg_operand" "f"))
4850 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4851 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4852 "{fnma|fnmadd} %0,%1,%2,%3"
4853 [(set_attr "type" "dmul")])
4856 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4857 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4858 (match_operand:SF 2 "gpc_reg_operand" "f"))
4859 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4860 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4861 "fnmsubs %0,%1,%2,%3"
4862 [(set_attr "type" "fp")])
4865 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4866 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4867 (match_operand:SF 2 "gpc_reg_operand" "f"))
4868 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
4869 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
4870 "{fnms|fnmsub} %0,%1,%2,%3"
4871 [(set_attr "type" "dmul")])
4873 (define_expand "sqrtsf2"
4874 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4875 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4876 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
4880 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4881 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4882 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
4884 [(set_attr "type" "ssqrt")])
4887 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4888 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4889 "TARGET_POWER2 && TARGET_HARD_FLOAT"
4891 [(set_attr "type" "dsqrt")])
4893 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
4894 ;; fsel instruction and some auxiliary computations. Then we just have a
4895 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
4897 (define_expand "maxsf3"
4898 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4899 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4900 (match_operand:SF 2 "gpc_reg_operand" ""))
4903 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4904 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
4906 (define_expand "minsf3"
4907 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4908 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
4909 (match_operand:SF 2 "gpc_reg_operand" ""))
4912 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4913 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
4916 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4917 (match_operator:SF 3 "min_max_operator"
4918 [(match_operand:SF 1 "gpc_reg_operand" "")
4919 (match_operand:SF 2 "gpc_reg_operand" "")]))]
4920 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4923 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
4924 operands[1], operands[2]);
4928 (define_expand "movsfcc"
4929 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4930 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4931 (match_operand:SF 2 "gpc_reg_operand" "")
4932 (match_operand:SF 3 "gpc_reg_operand" "")))]
4933 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4936 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
4942 (define_insn "*fselsfsf4"
4943 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4944 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
4945 (match_operand:SF 4 "zero_fp_constant" "F"))
4946 (match_operand:SF 2 "gpc_reg_operand" "f")
4947 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4948 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4950 [(set_attr "type" "fp")])
4952 (define_insn "*fseldfsf4"
4953 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4954 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
4955 (match_operand:DF 4 "zero_fp_constant" "F"))
4956 (match_operand:SF 2 "gpc_reg_operand" "f")
4957 (match_operand:SF 3 "gpc_reg_operand" "f")))]
4958 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
4960 [(set_attr "type" "fp")])
4962 (define_insn "negdf2"
4963 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4964 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4967 [(set_attr "type" "fp")])
4969 (define_insn "absdf2"
4970 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4971 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4974 [(set_attr "type" "fp")])
4977 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4978 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
4981 [(set_attr "type" "fp")])
4983 (define_insn "adddf3"
4984 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4985 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
4986 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4988 "{fa|fadd} %0,%1,%2"
4989 [(set_attr "type" "fp")])
4991 (define_insn "subdf3"
4992 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4993 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
4994 (match_operand:DF 2 "gpc_reg_operand" "f")))]
4996 "{fs|fsub} %0,%1,%2"
4997 [(set_attr "type" "fp")])
4999 (define_insn "muldf3"
5000 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5001 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5002 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5004 "{fm|fmul} %0,%1,%2"
5005 [(set_attr "type" "dmul")])
5007 (define_insn "divdf3"
5008 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5009 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5010 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5012 "{fd|fdiv} %0,%1,%2"
5013 [(set_attr "type" "ddiv")])
5016 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5017 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5018 (match_operand:DF 2 "gpc_reg_operand" "f"))
5019 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5020 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5021 "{fma|fmadd} %0,%1,%2,%3"
5022 [(set_attr "type" "dmul")])
5025 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5026 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5027 (match_operand:DF 2 "gpc_reg_operand" "f"))
5028 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5029 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5030 "{fms|fmsub} %0,%1,%2,%3"
5031 [(set_attr "type" "dmul")])
5034 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5035 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5036 (match_operand:DF 2 "gpc_reg_operand" "f"))
5037 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5038 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5039 "{fnma|fnmadd} %0,%1,%2,%3"
5040 [(set_attr "type" "dmul")])
5043 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5044 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5045 (match_operand:DF 2 "gpc_reg_operand" "f"))
5046 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5047 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5048 "{fnms|fnmsub} %0,%1,%2,%3"
5049 [(set_attr "type" "dmul")])
5051 (define_insn "sqrtdf2"
5052 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5053 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5054 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
5056 [(set_attr "type" "dsqrt")])
5058 ;; The conditional move instructions allow us to perform max and min
5059 ;; operations even when
5061 (define_expand "maxdf3"
5062 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5063 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5064 (match_operand:DF 2 "gpc_reg_operand" ""))
5067 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5068 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5070 (define_expand "mindf3"
5071 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5072 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5073 (match_operand:DF 2 "gpc_reg_operand" ""))
5076 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5077 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5080 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5081 (match_operator:DF 3 "min_max_operator"
5082 [(match_operand:DF 1 "gpc_reg_operand" "")
5083 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5084 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5087 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5088 operands[1], operands[2]);
5092 (define_expand "movdfcc"
5093 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5094 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5095 (match_operand:DF 2 "gpc_reg_operand" "")
5096 (match_operand:DF 3 "gpc_reg_operand" "")))]
5097 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5100 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5106 (define_insn "*fseldfdf4"
5107 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5108 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5109 (match_operand:DF 4 "zero_fp_constant" "F"))
5110 (match_operand:DF 2 "gpc_reg_operand" "f")
5111 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5112 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5114 [(set_attr "type" "fp")])
5116 (define_insn "*fselsfdf4"
5117 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5118 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5119 (match_operand:SF 4 "zero_fp_constant" "F"))
5120 (match_operand:DF 2 "gpc_reg_operand" "f")
5121 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5124 [(set_attr "type" "fp")])
5126 ;; Conversions to and from floating-point.
5128 ; For each of these conversions, there is a define_expand, a define_insn
5129 ; with a '#' template, and a define_split (with C code). The idea is
5130 ; to allow constant folding with the template of the define_insn,
5131 ; then to have the insns split later (between sched1 and final).
5133 (define_expand "floatsidf2"
5134 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5135 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5138 (clobber (match_dup 4))
5139 (clobber (match_dup 5))
5140 (clobber (match_dup 6))])]
5141 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5144 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5145 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
5146 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5147 operands[5] = gen_reg_rtx (DFmode);
5148 operands[6] = gen_reg_rtx (SImode);
5151 (define_insn "*floatsidf2_internal"
5152 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5153 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5154 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5155 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5156 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5157 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))
5158 (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))]
5159 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5161 [(set_attr "length" "24")])
5164 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5165 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5166 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5167 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5168 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5169 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5170 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5171 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5172 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5173 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5174 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5175 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5176 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5177 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5178 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5181 rtx lowword, highword;
5182 if (GET_CODE (operands[4]) != MEM)
5184 highword = XEXP (operands[4], 0);
5185 lowword = plus_constant (highword, 4);
5186 if (! WORDS_BIG_ENDIAN)
5189 tmp = highword; highword = lowword; lowword = tmp;
5192 emit_insn (gen_xorsi3 (operands[6], operands[1],
5193 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5194 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5195 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5196 emit_move_insn (operands[5], operands[4]);
5197 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5201 (define_expand "floatunssidf2"
5202 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5203 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5206 (clobber (match_dup 4))
5207 (clobber (match_dup 5))])]
5208 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5211 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5212 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
5213 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5214 operands[5] = gen_reg_rtx (DFmode);
5217 (define_insn "*floatunssidf2_internal"
5218 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5219 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5220 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5221 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5222 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5223 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))]
5224 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5226 [(set_attr "length" "20")])
5229 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5230 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5231 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5232 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5233 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5234 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5235 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5236 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5237 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5238 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5239 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5240 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5241 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5244 rtx lowword, highword;
5245 if (GET_CODE (operands[4]) != MEM)
5247 highword = XEXP (operands[4], 0);
5248 lowword = plus_constant (highword, 4);
5249 if (! WORDS_BIG_ENDIAN)
5252 tmp = highword; highword = lowword; lowword = tmp;
5255 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5256 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5257 emit_move_insn (operands[5], operands[4]);
5258 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5262 (define_expand "fix_truncdfsi2"
5263 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5264 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5265 (clobber (match_dup 2))
5266 (clobber (match_dup 3))])]
5267 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5270 operands[2] = gen_reg_rtx (DImode);
5271 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5274 (define_insn "*fix_truncdfsi2_internal"
5275 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5276 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5277 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5278 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5279 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5281 [(set_attr "length" "16")])
5284 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5285 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5286 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5287 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5288 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5289 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5290 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5291 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5292 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5296 if (GET_CODE (operands[3]) != MEM)
5298 lowword = XEXP (operands[3], 0);
5299 if (WORDS_BIG_ENDIAN)
5300 lowword = plus_constant (lowword, 4);
5302 emit_insn (gen_fctiwz (operands[2], operands[1]));
5303 emit_move_insn (operands[3], operands[2]);
5304 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5308 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
5309 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5310 ; because the first makes it clear that operand 0 is not live
5311 ; before the instruction.
5312 (define_insn "fctiwz"
5313 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5314 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
5315 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5316 "{fcirz|fctiwz} %0,%1"
5317 [(set_attr "type" "fp")])
5319 (define_insn "floatdidf2"
5320 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5321 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
5322 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5324 [(set_attr "type" "fp")])
5326 (define_insn "fix_truncdfdi2"
5327 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5328 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5329 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5331 [(set_attr "type" "fp")])
5333 ;; Define the DImode operations that can be done in a small number
5334 ;; of instructions. The & constraints are to prevent the register
5335 ;; allocator from allocating registers that overlap with the inputs
5336 ;; (for example, having an input in 7,8 and an output in 6,7). We
5337 ;; also allow for the output being the same as one of the inputs.
5339 (define_insn "*adddi3_noppc64"
5340 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5341 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5342 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5343 "! TARGET_POWERPC64"
5346 if (WORDS_BIG_ENDIAN)
5347 return (GET_CODE (operands[2])) != CONST_INT
5348 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5349 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5351 return (GET_CODE (operands[2])) != CONST_INT
5352 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5353 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5355 [(set_attr "length" "8")])
5357 (define_insn "*subdi3_noppc64"
5358 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5359 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5360 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5361 "! TARGET_POWERPC64"
5364 if (WORDS_BIG_ENDIAN)
5365 return (GET_CODE (operands[1]) != CONST_INT)
5366 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5367 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5369 return (GET_CODE (operands[1]) != CONST_INT)
5370 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5371 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5373 [(set_attr "length" "8")])
5375 (define_insn "*negdi2_noppc64"
5376 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5377 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
5378 "! TARGET_POWERPC64"
5381 return (WORDS_BIG_ENDIAN)
5382 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
5383 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
5385 [(set_attr "length" "8")])
5387 (define_expand "mulsidi3"
5388 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5389 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5390 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5391 "! TARGET_POWERPC64"
5394 if (! TARGET_POWER && ! TARGET_POWERPC)
5396 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5397 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5398 emit_insn (gen_mull_call ());
5399 if (WORDS_BIG_ENDIAN)
5400 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
5403 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
5404 gen_rtx_REG (SImode, 3));
5405 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
5406 gen_rtx_REG (SImode, 4));
5410 else if (TARGET_POWER)
5412 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
5417 (define_insn "mulsidi3_mq"
5418 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5419 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5420 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5421 (clobber (match_scratch:SI 3 "=q"))]
5423 "mul %0,%1,%2\;mfmq %L0"
5424 [(set_attr "type" "imul")
5425 (set_attr "length" "8")])
5427 (define_insn "*mulsidi3_no_mq"
5428 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5429 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5430 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5431 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5434 return (WORDS_BIG_ENDIAN)
5435 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
5436 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
5438 [(set_attr "type" "imul")
5439 (set_attr "length" "8")])
5442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5443 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5444 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5445 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5448 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
5449 (sign_extend:DI (match_dup 2)))
5452 (mult:SI (match_dup 1)
5456 int endian = (WORDS_BIG_ENDIAN == 0);
5457 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5458 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5461 (define_expand "umulsidi3"
5462 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5463 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5464 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5465 "TARGET_POWERPC && ! TARGET_POWERPC64"
5470 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
5475 (define_insn "umulsidi3_mq"
5476 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5477 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5478 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
5479 (clobber (match_scratch:SI 3 "=q"))]
5480 "TARGET_POWERPC && TARGET_POWER"
5483 return (WORDS_BIG_ENDIAN)
5484 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5485 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5487 [(set_attr "type" "imul")
5488 (set_attr "length" "8")])
5490 (define_insn "*umulsidi3_no_mq"
5491 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
5492 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
5493 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
5494 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
5497 return (WORDS_BIG_ENDIAN)
5498 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
5499 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
5501 [(set_attr "type" "imul")
5502 (set_attr "length" "8")])
5505 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5506 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
5507 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
5508 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
5511 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
5512 (zero_extend:DI (match_dup 2)))
5515 (mult:SI (match_dup 1)
5519 int endian = (WORDS_BIG_ENDIAN == 0);
5520 operands[3] = operand_subword (operands[0], endian, 0, DImode);
5521 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
5524 (define_expand "smulsi3_highpart"
5525 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5527 (lshiftrt:DI (mult:DI (sign_extend:DI
5528 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5530 (match_operand:SI 2 "gpc_reg_operand" "r")))
5535 if (! TARGET_POWER && ! TARGET_POWERPC)
5537 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
5538 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
5539 emit_insn (gen_mulh_call ());
5540 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
5543 else if (TARGET_POWER)
5545 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5550 (define_insn "smulsi3_highpart_mq"
5551 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5553 (lshiftrt:DI (mult:DI (sign_extend:DI
5554 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5556 (match_operand:SI 2 "gpc_reg_operand" "r")))
5558 (clobber (match_scratch:SI 3 "=q"))]
5561 [(set_attr "type" "imul")])
5563 (define_insn "*smulsi3_highpart_no_mq"
5564 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5566 (lshiftrt:DI (mult:DI (sign_extend:DI
5567 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5569 (match_operand:SI 2 "gpc_reg_operand" "r")))
5571 "TARGET_POWERPC && ! TARGET_POWER"
5573 [(set_attr "type" "imul")])
5575 (define_expand "umulsi3_highpart"
5576 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5578 (lshiftrt:DI (mult:DI (zero_extend:DI
5579 (match_operand:SI 1 "gpc_reg_operand" ""))
5581 (match_operand:SI 2 "gpc_reg_operand" "")))
5588 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
5593 (define_insn "umulsi3_highpart_mq"
5594 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5596 (lshiftrt:DI (mult:DI (zero_extend:DI
5597 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5599 (match_operand:SI 2 "gpc_reg_operand" "r")))
5601 (clobber (match_scratch:SI 3 "=q"))]
5602 "TARGET_POWERPC && TARGET_POWER"
5604 [(set_attr "type" "imul")])
5606 (define_insn "*umulsi3_highpart_no_mq"
5607 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5609 (lshiftrt:DI (mult:DI (zero_extend:DI
5610 (match_operand:SI 1 "gpc_reg_operand" "%r"))
5612 (match_operand:SI 2 "gpc_reg_operand" "r")))
5614 "TARGET_POWERPC && ! TARGET_POWER"
5616 [(set_attr "type" "imul")])
5618 ;; If operands 0 and 2 are in the same register, we have a problem. But
5619 ;; operands 0 and 1 (the usual case) can be in the same register. That's
5620 ;; why we have the strange constraints below.
5621 (define_insn "ashldi3_power"
5622 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5623 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5624 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5625 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5628 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
5629 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5630 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
5631 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
5632 [(set_attr "length" "8")])
5634 (define_insn "lshrdi3_power"
5635 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
5636 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
5637 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
5638 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
5641 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
5642 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5643 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
5644 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
5645 [(set_attr "length" "8")])
5647 ;; Shift by a variable amount is too complex to be worth open-coding. We
5648 ;; just handle shifts by constants.
5649 (define_insn "ashrdi3_power"
5650 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5651 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5652 (match_operand:SI 2 "const_int_operand" "M,i")))
5653 (clobber (match_scratch:SI 3 "=X,q"))]
5656 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
5657 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
5658 [(set_attr "length" "8")])
5660 ;; PowerPC64 DImode operations.
5662 (define_expand "adddi3"
5663 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5664 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5665 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
5669 if (! TARGET_POWERPC64)
5671 if (non_short_cint_operand (operands[2], DImode))
5675 if (GET_CODE (operands[2]) == CONST_INT
5676 && ! add_operand (operands[2], DImode))
5678 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
5679 ? operands[0] : gen_reg_rtx (DImode));
5681 HOST_WIDE_INT val = INTVAL (operands[2]);
5682 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
5683 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5685 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
5688 /* The ordering here is important for the prolog expander.
5689 When space is allocated from the stack, adding 'low' first may
5690 produce a temporary deallocation (which would be bad). */
5691 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
5692 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
5697 ;; Discourage ai/addic because of carry but provide it in an alternative
5698 ;; allowing register zero as source.
5700 (define_insn "*adddi3_internal1"
5701 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
5702 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
5703 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
5711 (define_insn "*adddi3_internal2"
5712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5713 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5714 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5716 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
5723 [(set_attr "type" "compare")
5724 (set_attr "length" "4,4,8,8")])
5727 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5728 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5729 (match_operand:DI 2 "reg_or_short_operand" ""))
5731 (clobber (match_scratch:DI 3 ""))]
5732 "TARGET_POWERPC64 && reload_completed"
5734 (plus:DI (match_dup 1) (match_dup 2)))
5736 (compare:CC (match_dup 3)
5740 (define_insn "*adddi3_internal3"
5741 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5742 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
5743 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
5745 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
5746 (plus:DI (match_dup 1) (match_dup 2)))]
5753 [(set_attr "type" "compare")
5754 (set_attr "length" "4,4,8,8")])
5757 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5758 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5759 (match_operand:DI 2 "reg_or_short_operand" ""))
5761 (set (match_operand:DI 0 "gpc_reg_operand" "")
5762 (plus:DI (match_dup 1) (match_dup 2)))]
5763 "TARGET_POWERPC64 && reload_completed"
5765 (plus:DI (match_dup 1) (match_dup 2)))
5767 (compare:CC (match_dup 0)
5771 ;; Split an add that we can't do in one insn into two insns, each of which
5772 ;; does one 16-bit part. This is used by combine. Note that the low-order
5773 ;; add should be last in case the result gets used in an address.
5776 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5777 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5778 (match_operand:DI 2 "non_add_cint_operand" "")))]
5780 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
5781 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
5784 HOST_WIDE_INT val = INTVAL (operands[2]);
5785 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
5786 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
5788 operands[4] = GEN_INT (low);
5789 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
5790 operands[3] = GEN_INT (rest);
5791 else if (! no_new_pseudos)
5793 operands[3] = gen_reg_rtx (DImode);
5794 emit_move_insn (operands[3], operands[2]);
5795 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
5802 (define_insn "one_cmpldi2"
5803 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5804 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5809 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5810 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5812 (clobber (match_scratch:DI 2 "=r,r"))]
5817 [(set_attr "type" "compare")
5818 (set_attr "length" "4,8")])
5821 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5822 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5824 (clobber (match_scratch:DI 2 ""))]
5825 "TARGET_POWERPC64 && reload_completed"
5827 (not:DI (match_dup 1)))
5829 (compare:CC (match_dup 2)
5834 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
5835 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5837 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5838 (not:DI (match_dup 1)))]
5843 [(set_attr "type" "compare")
5844 (set_attr "length" "4,8")])
5847 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
5848 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
5850 (set (match_operand:DI 0 "gpc_reg_operand" "")
5851 (not:DI (match_dup 1)))]
5852 "TARGET_POWERPC64 && reload_completed"
5854 (not:DI (match_dup 1)))
5856 (compare:CC (match_dup 0)
5861 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5862 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
5863 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
5870 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5871 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5872 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5874 (clobber (match_scratch:DI 3 "=r,r"))]
5879 [(set_attr "type" "compare")
5880 (set_attr "length" "4,8")])
5883 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5884 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5885 (match_operand:DI 2 "gpc_reg_operand" ""))
5887 (clobber (match_scratch:DI 3 ""))]
5888 "TARGET_POWERPC64 && reload_completed"
5890 (minus:DI (match_dup 1) (match_dup 2)))
5892 (compare:CC (match_dup 3)
5897 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5898 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
5899 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
5901 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5902 (minus:DI (match_dup 1) (match_dup 2)))]
5907 [(set_attr "type" "compare")
5908 (set_attr "length" "4,8")])
5911 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5912 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
5913 (match_operand:DI 2 "gpc_reg_operand" ""))
5915 (set (match_operand:DI 0 "gpc_reg_operand" "")
5916 (minus:DI (match_dup 1) (match_dup 2)))]
5917 "TARGET_POWERPC64 && reload_completed"
5919 (minus:DI (match_dup 1) (match_dup 2)))
5921 (compare:CC (match_dup 0)
5925 (define_expand "subdi3"
5926 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5927 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
5928 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
5932 if (GET_CODE (operands[2]) == CONST_INT)
5934 emit_insn (gen_adddi3 (operands[0], operands[1],
5935 negate_rtx (DImode, operands[2])));
5940 (define_insn "absdi2"
5941 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5942 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
5943 (clobber (match_scratch:DI 2 "=&r,&r"))]
5945 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
5946 [(set_attr "length" "12")])
5949 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5950 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
5951 (clobber (match_scratch:DI 2 ""))]
5952 "TARGET_POWERPC64 && reload_completed"
5953 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5954 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5955 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
5958 (define_insn "*nabsdi2"
5959 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
5960 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
5961 (clobber (match_scratch:DI 2 "=&r,&r"))]
5963 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
5964 [(set_attr "length" "12")])
5967 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5968 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))))
5969 (clobber (match_scratch:DI 2 ""))]
5970 "TARGET_POWERPC64 && reload_completed"
5971 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
5972 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
5973 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
5976 (define_expand "negdi2"
5977 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5978 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
5983 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
5984 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
5989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5990 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
5992 (clobber (match_scratch:DI 2 "=r,r"))]
5997 [(set_attr "type" "compare")
5998 (set_attr "length" "4,8")])
6001 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6002 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6004 (clobber (match_scratch:DI 2 ""))]
6005 "TARGET_POWERPC64 && reload_completed"
6007 (neg:DI (match_dup 1)))
6009 (compare:CC (match_dup 2)
6014 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6015 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6017 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6018 (neg:DI (match_dup 1)))]
6023 [(set_attr "type" "compare")
6024 (set_attr "length" "4,8")])
6027 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6028 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6030 (set (match_operand:DI 0 "gpc_reg_operand" "")
6031 (neg:DI (match_dup 1)))]
6032 "TARGET_POWERPC64 && reload_completed"
6034 (neg:DI (match_dup 1)))
6036 (compare:CC (match_dup 0)
6040 (define_insn "ffsdi2"
6041 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6042 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6044 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
6045 [(set_attr "length" "16")])
6047 (define_insn "muldi3"
6048 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6049 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6050 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6053 [(set_attr "type" "lmul")])
6055 (define_insn "smuldi3_highpart"
6056 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6058 (lshiftrt:TI (mult:TI (sign_extend:TI
6059 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6061 (match_operand:DI 2 "gpc_reg_operand" "r")))
6065 [(set_attr "type" "lmul")])
6067 (define_insn "umuldi3_highpart"
6068 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6070 (lshiftrt:TI (mult:TI (zero_extend:TI
6071 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6073 (match_operand:DI 2 "gpc_reg_operand" "r")))
6077 [(set_attr "type" "lmul")])
6079 (define_expand "divdi3"
6080 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6081 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6082 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6086 if (GET_CODE (operands[2]) == CONST_INT
6087 && INTVAL (operands[2]) > 0
6088 && exact_log2 (INTVAL (operands[2])) >= 0)
6091 operands[2] = force_reg (DImode, operands[2]);
6094 (define_expand "moddi3"
6095 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6096 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6097 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6105 if (GET_CODE (operands[2]) != CONST_INT
6106 || INTVAL (operands[2]) <= 0
6107 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6110 temp1 = gen_reg_rtx (DImode);
6111 temp2 = gen_reg_rtx (DImode);
6113 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6114 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6115 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6120 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6121 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6122 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6124 "sradi %0,%1,%p2\;addze %0,%0"
6125 [(set_attr "length" "8")])
6128 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6129 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6130 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6132 (clobber (match_scratch:DI 3 "=r,r"))]
6135 sradi %3,%1,%p2\;addze. %3,%3
6137 [(set_attr "type" "compare")
6138 (set_attr "length" "8,12")])
6141 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6142 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6143 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6145 (clobber (match_scratch:DI 3 ""))]
6146 "TARGET_POWERPC64 && reload_completed"
6148 (div:DI (match_dup 1) (match_dup 2)))
6150 (compare:CC (match_dup 3)
6155 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6156 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6157 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6159 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6160 (div:DI (match_dup 1) (match_dup 2)))]
6163 sradi %0,%1,%p2\;addze. %0,%0
6165 [(set_attr "type" "compare")
6166 (set_attr "length" "8,12")])
6169 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6170 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6171 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6173 (set (match_operand:DI 0 "gpc_reg_operand" "")
6174 (div:DI (match_dup 1) (match_dup 2)))]
6175 "TARGET_POWERPC64 && reload_completed"
6177 (div:DI (match_dup 1) (match_dup 2)))
6179 (compare:CC (match_dup 0)
6184 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6185 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6186 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6189 [(set_attr "type" "ldiv")])
6191 (define_insn "udivdi3"
6192 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6193 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6194 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6197 [(set_attr "type" "ldiv")])
6199 (define_insn "rotldi3"
6200 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6201 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6202 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6204 "rld%I2cl %0,%1,%H2,0")
6206 (define_insn "*rotldi3_internal2"
6207 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6208 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6209 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6211 (clobber (match_scratch:DI 3 "=r,r"))]
6214 rld%I2cl. %3,%1,%H2,0
6216 [(set_attr "type" "delayed_compare")
6217 (set_attr "length" "4,8")])
6220 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6221 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6222 (match_operand:DI 2 "reg_or_cint_operand" ""))
6224 (clobber (match_scratch:DI 3 ""))]
6225 "TARGET_POWERPC64 && reload_completed"
6227 (rotate:DI (match_dup 1) (match_dup 2)))
6229 (compare:CC (match_dup 3)
6233 (define_insn "*rotldi3_internal3"
6234 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6235 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6236 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6238 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6239 (rotate:DI (match_dup 1) (match_dup 2)))]
6242 rld%I2cl. %0,%1,%H2,0
6244 [(set_attr "type" "delayed_compare")
6245 (set_attr "length" "4,8")])
6248 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6249 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6250 (match_operand:DI 2 "reg_or_cint_operand" ""))
6252 (set (match_operand:DI 0 "gpc_reg_operand" "")
6253 (rotate:DI (match_dup 1) (match_dup 2)))]
6254 "TARGET_POWERPC64 && reload_completed"
6256 (rotate:DI (match_dup 1) (match_dup 2)))
6258 (compare:CC (match_dup 0)
6262 (define_insn "*rotldi3_internal4"
6263 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6264 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6265 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6266 (match_operand:DI 3 "mask64_operand" "S")))]
6268 "rld%I2c%B3 %0,%1,%H2,%S3")
6270 (define_insn "*rotldi3_internal5"
6271 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6273 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6274 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6275 (match_operand:DI 3 "mask64_operand" "S,S"))
6277 (clobber (match_scratch:DI 4 "=r,r"))]
6280 rld%I2c%B3. %4,%1,%H2,%S3
6282 [(set_attr "type" "delayed_compare")
6283 (set_attr "length" "4,8")])
6286 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6288 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6289 (match_operand:DI 2 "reg_or_cint_operand" ""))
6290 (match_operand:DI 3 "mask64_operand" ""))
6292 (clobber (match_scratch:DI 4 ""))]
6293 "TARGET_POWERPC64 && reload_completed"
6295 (and:DI (rotate:DI (match_dup 1)
6299 (compare:CC (match_dup 4)
6303 (define_insn "*rotldi3_internal6"
6304 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6306 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6307 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6308 (match_operand:DI 3 "mask64_operand" "S,S"))
6310 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6311 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6314 rld%I2c%B3. %0,%1,%H2,%S3
6316 [(set_attr "type" "delayed_compare")
6317 (set_attr "length" "4,8")])
6320 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6322 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6323 (match_operand:DI 2 "reg_or_cint_operand" ""))
6324 (match_operand:DI 3 "mask64_operand" ""))
6326 (set (match_operand:DI 0 "gpc_reg_operand" "")
6327 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6328 "TARGET_POWERPC64 && reload_completed"
6330 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
6332 (compare:CC (match_dup 0)
6336 (define_insn "*rotldi3_internal7"
6337 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6340 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6341 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6343 "rld%I2cl %0,%1,%H2,56")
6345 (define_insn "*rotldi3_internal8"
6346 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6347 (compare:CC (zero_extend:DI
6349 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6350 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6352 (clobber (match_scratch:DI 3 "=r,r"))]
6355 rld%I2cl. %3,%1,%H2,56
6357 [(set_attr "type" "delayed_compare")
6358 (set_attr "length" "4,8")])
6361 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6362 (compare:CC (zero_extend:DI
6364 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6365 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6367 (clobber (match_scratch:DI 3 ""))]
6368 "TARGET_POWERPC64 && reload_completed"
6370 (zero_extend:DI (subreg:QI
6371 (rotate:DI (match_dup 1)
6374 (compare:CC (match_dup 3)
6378 (define_insn "*rotldi3_internal9"
6379 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6380 (compare:CC (zero_extend:DI
6382 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6383 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6385 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6386 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6389 rld%I2cl. %0,%1,%H2,56
6391 [(set_attr "type" "delayed_compare")
6392 (set_attr "length" "4,8")])
6395 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6396 (compare:CC (zero_extend:DI
6398 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6399 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6401 (set (match_operand:DI 0 "gpc_reg_operand" "")
6402 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6403 "TARGET_POWERPC64 && reload_completed"
6405 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6407 (compare:CC (match_dup 0)
6411 (define_insn "*rotldi3_internal10"
6412 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6415 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6416 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6418 "rld%I2cl %0,%1,%H2,48")
6420 (define_insn "*rotldi3_internal11"
6421 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6422 (compare:CC (zero_extend:DI
6424 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6425 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6427 (clobber (match_scratch:DI 3 "=r,r"))]
6430 rld%I2cl. %3,%1,%H2,48
6432 [(set_attr "type" "delayed_compare")
6433 (set_attr "length" "4,8")])
6436 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6437 (compare:CC (zero_extend:DI
6439 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6440 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6442 (clobber (match_scratch:DI 3 ""))]
6443 "TARGET_POWERPC64 && reload_completed"
6445 (zero_extend:DI (subreg:HI
6446 (rotate:DI (match_dup 1)
6449 (compare:CC (match_dup 3)
6453 (define_insn "*rotldi3_internal12"
6454 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6455 (compare:CC (zero_extend:DI
6457 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6458 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6460 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6461 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6464 rld%I2cl. %0,%1,%H2,48
6466 [(set_attr "type" "delayed_compare")
6467 (set_attr "length" "4,8")])
6470 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6471 (compare:CC (zero_extend:DI
6473 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6474 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6476 (set (match_operand:DI 0 "gpc_reg_operand" "")
6477 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6478 "TARGET_POWERPC64 && reload_completed"
6480 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6482 (compare:CC (match_dup 0)
6486 (define_insn "*rotldi3_internal13"
6487 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6490 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6491 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6493 "rld%I2cl %0,%1,%H2,32")
6495 (define_insn "*rotldi3_internal14"
6496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6497 (compare:CC (zero_extend:DI
6499 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6500 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6502 (clobber (match_scratch:DI 3 "=r,r"))]
6505 rld%I2cl. %3,%1,%H2,32
6507 [(set_attr "type" "delayed_compare")
6508 (set_attr "length" "4,8")])
6511 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6512 (compare:CC (zero_extend:DI
6514 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6515 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6517 (clobber (match_scratch:DI 3 ""))]
6518 "TARGET_POWERPC64 && reload_completed"
6520 (zero_extend:DI (subreg:SI
6521 (rotate:DI (match_dup 1)
6524 (compare:CC (match_dup 3)
6528 (define_insn "*rotldi3_internal15"
6529 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6530 (compare:CC (zero_extend:DI
6532 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6533 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6535 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6536 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6539 rld%I2cl. %0,%1,%H2,32
6541 [(set_attr "type" "delayed_compare")
6542 (set_attr "length" "4,8")])
6545 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6546 (compare:CC (zero_extend:DI
6548 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6549 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6551 (set (match_operand:DI 0 "gpc_reg_operand" "")
6552 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
6553 "TARGET_POWERPC64 && reload_completed"
6555 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
6557 (compare:CC (match_dup 0)
6561 (define_expand "ashldi3"
6562 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6563 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6564 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6565 "TARGET_POWERPC64 || TARGET_POWER"
6568 if (TARGET_POWERPC64)
6570 else if (TARGET_POWER)
6572 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
6579 (define_insn "*ashldi3_internal1"
6580 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6581 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6582 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6585 [(set_attr "length" "8")])
6587 (define_insn "*ashldi3_internal2"
6588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6589 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6590 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6592 (clobber (match_scratch:DI 3 "=r,r"))]
6597 [(set_attr "type" "delayed_compare")
6598 (set_attr "length" "4,8")])
6601 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6602 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6603 (match_operand:SI 2 "reg_or_cint_operand" ""))
6605 (clobber (match_scratch:DI 3 ""))]
6606 "TARGET_POWERPC64 && reload_completed"
6608 (ashift:DI (match_dup 1) (match_dup 2)))
6610 (compare:CC (match_dup 3)
6614 (define_insn "*ashldi3_internal3"
6615 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6616 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6617 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6619 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6620 (ashift:DI (match_dup 1) (match_dup 2)))]
6625 [(set_attr "type" "delayed_compare")
6626 (set_attr "length" "4,8")])
6629 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6630 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6631 (match_operand:SI 2 "reg_or_cint_operand" ""))
6633 (set (match_operand:DI 0 "gpc_reg_operand" "")
6634 (ashift:DI (match_dup 1) (match_dup 2)))]
6635 "TARGET_POWERPC64 && reload_completed"
6637 (ashift:DI (match_dup 1) (match_dup 2)))
6639 (compare:CC (match_dup 0)
6643 (define_insn "*ashldi3_internal4"
6644 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6645 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6646 (match_operand:SI 2 "const_int_operand" "i"))
6647 (match_operand:DI 3 "const_int_operand" "n")))]
6648 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6649 "rldic %0,%1,%H2,%W3")
6651 (define_insn "ashldi3_internal5"
6652 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6654 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6655 (match_operand:SI 2 "const_int_operand" "i,i"))
6656 (match_operand:DI 3 "const_int_operand" "n,n"))
6658 (clobber (match_scratch:DI 4 "=r,r"))]
6659 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6661 rldic. %4,%1,%H2,%W3
6663 [(set_attr "type" "delayed_compare")
6664 (set_attr "length" "4,8")])
6667 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6669 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6670 (match_operand:SI 2 "const_int_operand" ""))
6671 (match_operand:DI 3 "const_int_operand" ""))
6673 (clobber (match_scratch:DI 4 ""))]
6674 "TARGET_POWERPC64 && reload_completed
6675 && includes_rldic_lshift_p (operands[2], operands[3])"
6677 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6680 (compare:CC (match_dup 4)
6684 (define_insn "*ashldi3_internal6"
6685 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6687 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6688 (match_operand:SI 2 "const_int_operand" "i,i"))
6689 (match_operand:DI 3 "const_int_operand" "n,n"))
6691 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6692 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6693 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
6695 rldic. %0,%1,%H2,%W3
6697 [(set_attr "type" "delayed_compare")
6698 (set_attr "length" "4,8")])
6701 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6703 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6704 (match_operand:SI 2 "const_int_operand" ""))
6705 (match_operand:DI 3 "const_int_operand" ""))
6707 (set (match_operand:DI 0 "gpc_reg_operand" "")
6708 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6709 "TARGET_POWERPC64 && reload_completed
6710 && includes_rldic_lshift_p (operands[2], operands[3])"
6712 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6715 (compare:CC (match_dup 0)
6719 (define_insn "*ashldi3_internal7"
6720 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6721 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6722 (match_operand:SI 2 "const_int_operand" "i"))
6723 (match_operand:DI 3 "mask64_operand" "S")))]
6724 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6725 "rldicr %0,%1,%H2,%S3")
6727 (define_insn "ashldi3_internal8"
6728 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6730 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6731 (match_operand:SI 2 "const_int_operand" "i,i"))
6732 (match_operand:DI 3 "mask64_operand" "S,S"))
6734 (clobber (match_scratch:DI 4 "=r,r"))]
6735 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6737 rldicr. %4,%1,%H2,%S3
6739 [(set_attr "type" "delayed_compare")
6740 (set_attr "length" "4,8")])
6743 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6745 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6746 (match_operand:SI 2 "const_int_operand" ""))
6747 (match_operand:DI 3 "mask64_operand" ""))
6749 (clobber (match_scratch:DI 4 ""))]
6750 "TARGET_POWERPC64 && reload_completed
6751 && includes_rldicr_lshift_p (operands[2], operands[3])"
6753 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6756 (compare:CC (match_dup 4)
6760 (define_insn "*ashldi3_internal9"
6761 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6763 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6764 (match_operand:SI 2 "const_int_operand" "i,i"))
6765 (match_operand:DI 3 "mask64_operand" "S,S"))
6767 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6768 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6769 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
6771 rldicr. %0,%1,%H2,%S3
6773 [(set_attr "type" "delayed_compare")
6774 (set_attr "length" "4,8")])
6777 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6779 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
6780 (match_operand:SI 2 "const_int_operand" ""))
6781 (match_operand:DI 3 "mask64_operand" ""))
6783 (set (match_operand:DI 0 "gpc_reg_operand" "")
6784 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6785 "TARGET_POWERPC64 && reload_completed
6786 && includes_rldicr_lshift_p (operands[2], operands[3])"
6788 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
6791 (compare:CC (match_dup 0)
6795 (define_expand "lshrdi3"
6796 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6797 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6798 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6799 "TARGET_POWERPC64 || TARGET_POWER"
6802 if (TARGET_POWERPC64)
6804 else if (TARGET_POWER)
6806 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
6813 (define_insn "*lshrdi3_internal1"
6814 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6815 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6816 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6820 (define_insn "*lshrdi3_internal2"
6821 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6822 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6823 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6825 (clobber (match_scratch:DI 3 "=r,r"))]
6830 [(set_attr "type" "delayed_compare")
6831 (set_attr "length" "4,8")])
6834 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6835 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6836 (match_operand:SI 2 "reg_or_cint_operand" ""))
6838 (clobber (match_scratch:DI 3 ""))]
6839 "TARGET_POWERPC64 && reload_completed"
6841 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6843 (compare:CC (match_dup 3)
6847 (define_insn "*lshrdi3_internal3"
6848 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6849 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6850 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6852 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6853 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6858 [(set_attr "type" "delayed_compare")
6859 (set_attr "length" "4,8")])
6862 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6863 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6864 (match_operand:SI 2 "reg_or_cint_operand" ""))
6866 (set (match_operand:DI 0 "gpc_reg_operand" "")
6867 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
6868 "TARGET_POWERPC64 && reload_completed"
6870 (lshiftrt:DI (match_dup 1) (match_dup 2)))
6872 (compare:CC (match_dup 0)
6876 (define_expand "ashrdi3"
6877 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6878 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6879 (match_operand:SI 2 "reg_or_cint_operand" "")))]
6880 "TARGET_POWERPC64 || TARGET_POWER"
6883 if (TARGET_POWERPC64)
6885 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
6887 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
6894 (define_insn "*ashrdi3_internal1"
6895 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6896 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6897 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
6899 "srad%I2 %0,%1,%H2")
6901 (define_insn "*ashrdi3_internal2"
6902 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6903 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6904 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6906 (clobber (match_scratch:DI 3 "=r,r"))]
6911 [(set_attr "type" "delayed_compare")
6912 (set_attr "length" "4,8")])
6915 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6916 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6917 (match_operand:SI 2 "reg_or_cint_operand" ""))
6919 (clobber (match_scratch:DI 3 ""))]
6920 "TARGET_POWERPC64 && reload_completed"
6922 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6924 (compare:CC (match_dup 3)
6928 (define_insn "*ashrdi3_internal3"
6929 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6930 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6931 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
6933 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6934 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6939 [(set_attr "type" "delayed_compare")
6940 (set_attr "length" "4,8")])
6943 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6944 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
6945 (match_operand:SI 2 "reg_or_cint_operand" ""))
6947 (set (match_operand:DI 0 "gpc_reg_operand" "")
6948 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6949 "TARGET_POWERPC64 && reload_completed"
6951 (ashiftrt:DI (match_dup 1) (match_dup 2)))
6953 (compare:CC (match_dup 0)
6957 (define_insn "anddi3"
6958 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6959 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
6960 (match_operand:DI 2 "and64_operand" "?r,S,K,J")))
6961 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
6965 rldic%B2 %0,%1,0,%S2
6969 (define_insn "*anddi3_internal2"
6970 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
6971 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,")
6972 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
6974 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r"))
6975 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
6979 rldic%B2. %3,%1,0,%S2
6986 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
6987 (set_attr "length" "4,4,4,4,8,8,8,8")])
6990 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6991 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
6992 (match_operand:DI 2 "and64_operand" ""))
6994 (clobber (match_scratch:DI 3 ""))
6995 (clobber (match_scratch:CC 4 ""))]
6996 "TARGET_POWERPC64 && reload_completed"
6997 [(parallel [(set (match_dup 3)
6998 (and:DI (match_dup 1)
7000 (clobber (match_dup 4))])
7002 (compare:CC (match_dup 3)
7006 (define_insn "*anddi3_internal3"
7007 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y")
7008 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
7009 (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J"))
7011 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
7012 (and:DI (match_dup 1) (match_dup 2)))
7013 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))]
7017 rldic%B2. %0,%1,0,%S2
7024 [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare")
7025 (set_attr "length" "4,4,4,4,8,8,8,8")])
7028 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7029 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7030 (match_operand:DI 2 "and64_operand" ""))
7032 (set (match_operand:DI 0 "gpc_reg_operand" "")
7033 (and:DI (match_dup 1) (match_dup 2)))
7034 (clobber (match_scratch:CC 4 ""))]
7035 "TARGET_POWERPC64 && reload_completed"
7036 [(parallel [(set (match_dup 0)
7037 (and:DI (match_dup 1) (match_dup 2)))
7038 (clobber (match_dup 4))])
7040 (compare:CC (match_dup 0)
7044 (define_expand "iordi3"
7045 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7046 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7047 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7051 if (non_logical_cint_operand (operands[2], DImode))
7053 HOST_WIDE_INT value;
7054 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7055 ? operands[0] : gen_reg_rtx (DImode));
7057 if (GET_CODE (operands[2]) == CONST_INT)
7059 value = INTVAL (operands[2]);
7060 emit_insn (gen_iordi3 (tmp, operands[1],
7061 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7065 value = CONST_DOUBLE_LOW (operands[2]);
7066 emit_insn (gen_iordi3 (tmp, operands[1],
7067 immed_double_const (value
7068 & (~ (HOST_WIDE_INT) 0xffff),
7072 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7077 (define_expand "xordi3"
7078 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7079 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7080 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7084 if (non_logical_cint_operand (operands[2], DImode))
7086 HOST_WIDE_INT value;
7087 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7088 ? operands[0] : gen_reg_rtx (DImode));
7090 if (GET_CODE (operands[2]) == CONST_INT)
7092 value = INTVAL (operands[2]);
7093 emit_insn (gen_xordi3 (tmp, operands[1],
7094 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7098 value = CONST_DOUBLE_LOW (operands[2]);
7099 emit_insn (gen_xordi3 (tmp, operands[1],
7100 immed_double_const (value
7101 & (~ (HOST_WIDE_INT) 0xffff),
7105 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7110 (define_insn "*booldi3_internal1"
7111 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7112 (match_operator:DI 3 "boolean_or_operator"
7113 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7114 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7121 (define_insn "*booldi3_internal2"
7122 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7123 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7124 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7125 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7127 (clobber (match_scratch:DI 3 "=r,r"))]
7132 [(set_attr "type" "compare")
7133 (set_attr "length" "4,8")])
7136 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7137 (compare:CC (match_operator:DI 4 "boolean_operator"
7138 [(match_operand:DI 1 "gpc_reg_operand" "")
7139 (match_operand:DI 2 "gpc_reg_operand" "")])
7141 (clobber (match_scratch:DI 3 ""))]
7142 "TARGET_POWERPC64 && reload_completed"
7143 [(set (match_dup 3) (match_dup 4))
7145 (compare:CC (match_dup 3)
7149 (define_insn "*booldi3_internal3"
7150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7151 (compare:CC (match_operator:DI 4 "boolean_operator"
7152 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7153 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7155 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7161 [(set_attr "type" "compare")
7162 (set_attr "length" "4,8")])
7165 [(set (match_operand:CC 3 "cc_reg_operand" "")
7166 (compare:CC (match_operator:DI 4 "boolean_operator"
7167 [(match_operand:DI 1 "gpc_reg_operand" "")
7168 (match_operand:DI 2 "gpc_reg_operand" "")])
7170 (set (match_operand:DI 0 "gpc_reg_operand" "")
7172 "TARGET_POWERPC64 && reload_completed"
7173 [(set (match_dup 0) (match_dup 4))
7175 (compare:CC (match_dup 0)
7179 ;; Split an logical operation that we can't do in one insn into two insns,
7180 ;; each of which does one 16-bit part. This is used by combine.
7183 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7184 (match_operator:DI 3 "boolean_or_operator"
7185 [(match_operand:DI 1 "gpc_reg_operand" "")
7186 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7188 [(set (match_dup 0) (match_dup 4))
7189 (set (match_dup 0) (match_dup 5))]
7194 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7196 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7197 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7199 i4 = GEN_INT (value & 0xffff);
7203 i3 = GEN_INT (INTVAL (operands[2])
7204 & (~ (HOST_WIDE_INT) 0xffff));
7205 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7207 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
7209 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
7213 (define_insn "*boolcdi3_internal1"
7214 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7215 (match_operator:DI 3 "boolean_operator"
7216 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7217 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
7221 (define_insn "*boolcdi3_internal2"
7222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7223 (compare:CC (match_operator:DI 4 "boolean_operator"
7224 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7225 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7227 (clobber (match_scratch:DI 3 "=r,r"))]
7232 [(set_attr "type" "compare")
7233 (set_attr "length" "4,8")])
7236 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7237 (compare:CC (match_operator:DI 4 "boolean_operator"
7238 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7239 (match_operand:DI 2 "gpc_reg_operand" "")])
7241 (clobber (match_scratch:DI 3 ""))]
7242 "TARGET_POWERPC64 && reload_completed"
7243 [(set (match_dup 3) (match_dup 4))
7245 (compare:CC (match_dup 3)
7249 (define_insn "*boolcdi3_internal3"
7250 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7251 (compare:CC (match_operator:DI 4 "boolean_operator"
7252 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7253 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7255 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7261 [(set_attr "type" "compare")
7262 (set_attr "length" "4,8")])
7265 [(set (match_operand:CC 3 "cc_reg_operand" "")
7266 (compare:CC (match_operator:DI 4 "boolean_operator"
7267 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7268 (match_operand:DI 2 "gpc_reg_operand" "")])
7270 (set (match_operand:DI 0 "gpc_reg_operand" "")
7272 "TARGET_POWERPC64 && reload_completed"
7273 [(set (match_dup 0) (match_dup 4))
7275 (compare:CC (match_dup 0)
7279 (define_insn "*boolccdi3_internal1"
7280 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7281 (match_operator:DI 3 "boolean_operator"
7282 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7283 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
7287 (define_insn "*boolccdi3_internal2"
7288 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7289 (compare:CC (match_operator:DI 4 "boolean_operator"
7290 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7291 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7293 (clobber (match_scratch:DI 3 "=r,r"))]
7298 [(set_attr "type" "compare")
7299 (set_attr "length" "4,8")])
7302 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7303 (compare:CC (match_operator:DI 4 "boolean_operator"
7304 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7305 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7307 (clobber (match_scratch:DI 3 ""))]
7308 "TARGET_POWERPC64 && reload_completed"
7309 [(set (match_dup 3) (match_dup 4))
7311 (compare:CC (match_dup 3)
7315 (define_insn "*boolccdi3_internal3"
7316 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7317 (compare:CC (match_operator:DI 4 "boolean_operator"
7318 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
7319 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
7321 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7327 [(set_attr "type" "compare")
7328 (set_attr "length" "4,8")])
7331 [(set (match_operand:CC 3 "cc_reg_operand" "")
7332 (compare:CC (match_operator:DI 4 "boolean_operator"
7333 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7334 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
7336 (set (match_operand:DI 0 "gpc_reg_operand" "")
7338 "TARGET_POWERPC64 && reload_completed"
7339 [(set (match_dup 0) (match_dup 4))
7341 (compare:CC (match_dup 0)
7345 ;; Now define ways of moving data around.
7347 ;; Elf specific ways of loading addresses for non-PIC code.
7348 ;; The output of this could be r0, but we make a very strong
7349 ;; preference for a base register because it will usually
7351 (define_insn "elf_high"
7352 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7353 (high:SI (match_operand 1 "" "")))]
7354 "TARGET_ELF && ! TARGET_64BIT"
7355 "{liu|lis} %0,%1@ha")
7357 (define_insn "elf_low"
7358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7359 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7360 (match_operand 2 "" "")))]
7361 "TARGET_ELF && ! TARGET_64BIT"
7363 {cal|la} %0,%2@l(%1)
7364 {ai|addic} %0,%1,%K2")
7366 ;; Mach-O PIC trickery.
7367 (define_insn "macho_high"
7368 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7369 (high:SI (match_operand 1 "" "")))]
7370 "TARGET_MACHO && ! TARGET_64BIT"
7371 "{liu|lis} %0,ha16(%1)")
7373 (define_insn "macho_low"
7374 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7375 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7376 (match_operand 2 "" "")))]
7377 "TARGET_MACHO && ! TARGET_64BIT"
7379 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
7380 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
7382 ;; Set up a register with a value from the GOT table
7384 (define_expand "movsi_got"
7385 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7386 (unspec:SI [(match_operand:SI 1 "got_operand" "")
7388 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
7391 if (GET_CODE (operands[1]) == CONST)
7393 rtx offset = const0_rtx;
7394 HOST_WIDE_INT value;
7396 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
7397 value = INTVAL (offset);
7400 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
7401 emit_insn (gen_movsi_got (tmp, operands[1]));
7402 emit_insn (gen_addsi3 (operands[0], tmp, offset));
7407 operands[2] = rs6000_got_register (operands[1]);
7410 (define_insn "*movsi_got_internal"
7411 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7412 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7413 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
7414 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
7415 "{l|lwz} %0,%a1@got(%2)"
7416 [(set_attr "type" "load")])
7418 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
7419 ;; didn't get allocated to a hard register.
7421 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7422 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
7423 (match_operand:SI 2 "memory_operand" "")] 8))]
7424 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
7426 && (reload_in_progress || reload_completed)"
7427 [(set (match_dup 0) (match_dup 2))
7428 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
7431 ;; For SI, we special-case integers that can't be loaded in one insn. We
7432 ;; do the load 16-bits at a time. We could do this by loading from memory,
7433 ;; and this is even supposed to be faster, but it is simpler not to get
7434 ;; integers in the TOC.
7435 (define_expand "movsi"
7436 [(set (match_operand:SI 0 "general_operand" "")
7437 (match_operand:SI 1 "any_operand" ""))]
7439 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
7441 (define_insn "movsi_low"
7442 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7443 (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
7444 (match_operand 2 "" ""))))]
7445 "TARGET_MACHO && ! TARGET_64BIT"
7446 "{l|lwz} %0,lo16(%2)(%1)"
7447 [(set_attr "type" "load")
7448 (set_attr "length" "4")])
7450 (define_insn "*movsi_internal1"
7451 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
7452 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))]
7453 "gpc_reg_operand (operands[0], SImode)
7454 || gpc_reg_operand (operands[1], SImode)"
7458 {l%U1%X1|lwz%U1%X1} %0,%1
7459 {st%U0%X0|stw%U0%X0} %1,%0
7468 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
7469 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
7471 ;; Split a load of a large constant into the appropriate two-insn
7475 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7476 (match_operand:SI 1 "const_int_operand" ""))]
7477 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
7478 && (INTVAL (operands[1]) & 0xffff) != 0"
7482 (ior:SI (match_dup 0)
7486 operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff));
7487 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
7490 (define_insn "*movsi_internal2"
7491 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
7492 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
7494 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
7495 "! TARGET_POWERPC64"
7499 [(set_attr "type" "compare")
7500 (set_attr "length" "4,8")])
7503 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
7504 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
7506 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
7507 "! TARGET_POWERPC64 && reload_completed"
7508 [(set (match_dup 0) (match_dup 1))
7510 (compare:CC (match_dup 0)
7514 (define_expand "movhi"
7515 [(set (match_operand:HI 0 "general_operand" "")
7516 (match_operand:HI 1 "any_operand" ""))]
7518 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
7521 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7522 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7523 "gpc_reg_operand (operands[0], HImode)
7524 || gpc_reg_operand (operands[1], HImode)"
7534 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7536 (define_expand "movqi"
7537 [(set (match_operand:QI 0 "general_operand" "")
7538 (match_operand:QI 1 "any_operand" ""))]
7540 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
7543 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
7544 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
7545 "gpc_reg_operand (operands[0], QImode)
7546 || gpc_reg_operand (operands[1], QImode)"
7556 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
7558 ;; Here is how to move condition codes around. When we store CC data in
7559 ;; an integer register or memory, we store just the high-order 4 bits.
7560 ;; This lets us not shift in the most common case of CR0.
7561 (define_expand "movcc"
7562 [(set (match_operand:CC 0 "nonimmediate_operand" "")
7563 (match_operand:CC 1 "nonimmediate_operand" ""))]
7568 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
7569 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
7570 "register_operand (operands[0], CCmode)
7571 || register_operand (operands[1], CCmode)"
7575 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
7577 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
7579 {l%U1%X1|lwz%U1%X1} %0,%1
7580 {st%U0%U1|stw%U0%U1} %1,%0"
7581 [(set_attr "type" "*,*,*,compare,*,*,load,store")
7582 (set_attr "length" "*,*,12,*,8,*,*,*")])
7584 ;; For floating-point, we normally deal with the floating-point registers
7585 ;; unless -msoft-float is used. The sole exception is that parameter passing
7586 ;; can produce floating-point values in fixed-point registers. Unless the
7587 ;; value is a simple constant or already in memory, we deal with this by
7588 ;; allocating memory and copying the value explicitly via that memory location.
7589 (define_expand "movsf"
7590 [(set (match_operand:SF 0 "nonimmediate_operand" "")
7591 (match_operand:SF 1 "any_operand" ""))]
7593 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
7596 [(set (match_operand:SF 0 "gpc_reg_operand" "")
7597 (match_operand:SF 1 "const_double_operand" ""))]
7599 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7600 || (GET_CODE (operands[0]) == SUBREG
7601 && GET_CODE (SUBREG_REG (operands[0])) == REG
7602 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7603 [(set (match_dup 2) (match_dup 3))]
7609 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7610 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
7612 if (! TARGET_POWERPC64)
7613 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
7615 operands[2] = gen_lowpart (SImode, operands[0]);
7617 operands[3] = GEN_INT (trunc_int_for_mode (l, SImode));
7620 (define_insn "*movsf_hardfloat"
7621 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
7622 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
7623 "(gpc_reg_operand (operands[0], SFmode)
7624 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
7627 {l%U1%X1|lwz%U1%X1} %0,%1
7628 {st%U0%X0|stw%U0%X0} %1,%0
7634 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
7635 (set_attr "length" "4,4,4,4,4,4,4,8")])
7637 (define_insn "*movsf_softfloat"
7638 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
7639 (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))]
7640 "(gpc_reg_operand (operands[0], SFmode)
7641 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
7644 {l%U1%X1|lwz%U1%X1} %0,%1
7645 {st%U0%X0|stw%U0%X0} %1,%0
7651 [(set_attr "type" "*,load,store,*,*,*,*,*")
7652 (set_attr "length" "4,4,4,4,4,4,4,8")])
7655 (define_expand "movdf"
7656 [(set (match_operand:DF 0 "nonimmediate_operand" "")
7657 (match_operand:DF 1 "any_operand" ""))]
7659 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
7662 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7663 (match_operand:DF 1 "const_int_operand" ""))]
7664 "! TARGET_POWERPC64 && reload_completed
7665 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7666 || (GET_CODE (operands[0]) == SUBREG
7667 && GET_CODE (SUBREG_REG (operands[0])) == REG
7668 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7669 [(set (match_dup 2) (match_dup 4))
7670 (set (match_dup 3) (match_dup 1))]
7673 int endian = (WORDS_BIG_ENDIAN == 0);
7674 HOST_WIDE_INT value = INTVAL (operands[1]);
7676 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7677 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7678 #if HOST_BITS_PER_WIDE_INT == 32
7679 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7681 operands[4] = GEN_INT (value >> 32);
7682 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
7687 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7688 (match_operand:DF 1 "const_double_operand" ""))]
7689 "! TARGET_POWERPC64 && reload_completed
7690 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7691 || (GET_CODE (operands[0]) == SUBREG
7692 && GET_CODE (SUBREG_REG (operands[0])) == REG
7693 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7694 [(set (match_dup 2) (match_dup 4))
7695 (set (match_dup 3) (match_dup 5))]
7698 int endian = (WORDS_BIG_ENDIAN == 0);
7702 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7703 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7705 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
7706 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
7707 operands[4] = GEN_INT (trunc_int_for_mode (l[endian], SImode));
7708 operands[5] = GEN_INT (trunc_int_for_mode (l[1 - endian], SImode));
7712 [(set (match_operand:DF 0 "gpc_reg_operand" "")
7713 (match_operand:DF 1 "easy_fp_constant" ""))]
7714 "TARGET_POWERPC64 && reload_completed
7715 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
7716 || (GET_CODE (operands[0]) == SUBREG
7717 && GET_CODE (SUBREG_REG (operands[0])) == REG
7718 && REGNO (SUBREG_REG (operands[0])) <= 31))"
7719 [(set (match_dup 2) (match_dup 3))]
7722 int endian = (WORDS_BIG_ENDIAN == 0);
7726 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
7727 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
7729 operands[2] = gen_lowpart (DImode, operands[0]);
7730 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
7731 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
7734 ;; Don't have reload use general registers to load a constant. First,
7735 ;; it might not work if the output operand is the equivalent of
7736 ;; a non-offsettable memref, but also it is less efficient than loading
7737 ;; the constant into an FP register, since it will probably be used there.
7738 ;; The "??" is a kludge until we can figure out a more reasonable way
7739 ;; of handling these non-offsettable values.
7740 (define_insn "*movdf_hardfloat32"
7741 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
7742 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
7743 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
7744 && (gpc_reg_operand (operands[0], DFmode)
7745 || gpc_reg_operand (operands[1], DFmode))"
7748 switch (which_alternative)
7753 /* We normally copy the low-numbered register first. However, if
7754 the first register operand 0 is the same as the second register
7755 of operand 1, we must copy in the opposite order. */
7756 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7757 return \"mr %L0,%L1\;mr %0,%1\";
7759 return \"mr %0,%1\;mr %L0,%L1\";
7761 if (offsettable_memref_p (operands[1])
7762 || (GET_CODE (operands[1]) == MEM
7763 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
7764 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
7765 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
7767 /* If the low-address word is used in the address, we must load
7768 it last. Otherwise, load it first. Note that we cannot have
7769 auto-increment in that case since the address register is
7770 known to be dead. */
7771 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7773 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7775 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7781 addreg = find_addr_reg (XEXP (operands[1], 0));
7782 if (refers_to_regno_p (REGNO (operands[0]),
7783 REGNO (operands[0]) + 1,
7786 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7787 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7788 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7789 return \"{lx|lwzx} %0,%1\";
7793 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
7794 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7795 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
7796 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7801 if (offsettable_memref_p (operands[0])
7802 || (GET_CODE (operands[0]) == MEM
7803 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
7804 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
7805 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
7806 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7811 addreg = find_addr_reg (XEXP (operands[0], 0));
7812 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
7813 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
7814 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
7815 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
7823 return \"fmr %0,%1\";
7825 return \"lfd%U1%X1 %0,%1\";
7827 return \"stfd%U0%X0 %1,%0\";
7830 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
7831 (set_attr "length" "8,16,16,8,12,16,*,*,*")])
7833 (define_insn "*movdf_softfloat32"
7834 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7835 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7836 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
7837 && (gpc_reg_operand (operands[0], DFmode)
7838 || gpc_reg_operand (operands[1], DFmode))"
7841 switch (which_alternative)
7846 /* We normally copy the low-numbered register first. However, if
7847 the first register operand 0 is the same as the second register of
7848 operand 1, we must copy in the opposite order. */
7849 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7850 return \"mr %L0,%L1\;mr %0,%1\";
7852 return \"mr %0,%1\;mr %L0,%L1\";
7854 /* If the low-address word is used in the address, we must load
7855 it last. Otherwise, load it first. Note that we cannot have
7856 auto-increment in that case since the address register is
7857 known to be dead. */
7858 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7860 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7862 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7864 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7871 [(set_attr "type" "*,load,store,*,*,*")
7872 (set_attr "length" "8,8,8,8,12,16")])
7874 (define_insn "*movdf_hardfloat64"
7875 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
7876 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
7877 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
7878 && (gpc_reg_operand (operands[0], DFmode)
7879 || gpc_reg_operand (operands[1], DFmode))"
7890 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
7891 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
7893 (define_insn "*movdf_softfloat64"
7894 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
7895 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
7896 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
7897 && (gpc_reg_operand (operands[0], DFmode)
7898 || gpc_reg_operand (operands[1], DFmode))"
7906 [(set_attr "type" "*,load,store,*,*,*")
7907 (set_attr "length" "*,*,*,8,12,16")])
7909 ;; Next come the multi-word integer load and store and the load and store
7911 (define_expand "movdi"
7912 [(set (match_operand:DI 0 "general_operand" "")
7913 (match_operand:DI 1 "any_operand" ""))]
7915 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
7917 (define_insn "*movdi_internal32"
7918 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
7919 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
7921 && (gpc_reg_operand (operands[0], DImode)
7922 || gpc_reg_operand (operands[1], DImode))"
7925 switch (which_alternative)
7930 /* We normally copy the low-numbered register first. However, if
7931 the first register operand 0 is the same as the second register of
7932 operand 1, we must copy in the opposite order. */
7933 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
7934 return \"mr %L0,%L1\;mr %0,%1\";
7936 return \"mr %0,%1\;mr %L0,%L1\";
7938 /* If the low-address word is used in the address, we must load it
7939 last. Otherwise, load it first. Note that we cannot have
7940 auto-increment in that case since the address register is known to be
7942 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
7944 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
7946 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
7948 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
7950 return \"fmr %0,%1\";
7952 return \"lfd%U1%X1 %0,%1\";
7954 return \"stfd%U0%X0 %1,%0\";
7963 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
7964 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
7967 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7968 (match_operand:DI 1 "const_int_operand" ""))]
7969 "! TARGET_POWERPC64 && reload_completed"
7970 [(set (match_dup 2) (match_dup 4))
7971 (set (match_dup 3) (match_dup 1))]
7974 HOST_WIDE_INT value = INTVAL (operands[1]);
7975 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7977 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7979 #if HOST_BITS_PER_WIDE_INT == 32
7980 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
7982 operands[4] = GEN_INT (value >> 32);
7983 operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000));
7988 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7989 (match_operand:DI 1 "const_double_operand" ""))]
7990 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
7991 [(set (match_dup 2) (match_dup 4))
7992 (set (match_dup 3) (match_dup 5))]
7995 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
7997 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
7999 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
8000 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8003 (define_insn "*movdi_internal64"
8004 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
8005 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
8007 && (gpc_reg_operand (operands[0], DImode)
8008 || gpc_reg_operand (operands[1], DImode))"
8023 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
8024 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
8026 ;; immediate value valid for a single instruction hiding in a const_double
8028 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8029 (match_operand:DI 1 "const_double_operand" "F"))]
8030 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
8031 && GET_CODE (operands[1]) == CONST_DOUBLE
8032 && num_insns_constant (operands[1], DImode) == 1"
8035 return ((unsigned HOST_WIDE_INT)
8036 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
8037 ? \"li %0,%1\" : \"lis %0,%v1\";
8040 ;; Generate all one-bits and clear left or right.
8041 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
8043 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8044 (match_operand:DI 1 "mask64_operand" ""))]
8045 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8046 [(set (match_dup 0) (const_int -1))
8048 (and:DI (rotate:DI (match_dup 0)
8053 ;; Split a load of a large constant into the appropriate five-instruction
8054 ;; sequence. Handle anything in a constant number of insns.
8055 ;; When non-easy constants can go in the TOC, this should use
8056 ;; easy_fp_constant predicate.
8058 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8059 (match_operand:DI 1 "const_int_operand" ""))]
8060 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8061 [(set (match_dup 0) (match_dup 2))
8062 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8064 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8066 if (tem == operands[0])
8073 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8074 (match_operand:DI 1 "const_double_operand" ""))]
8075 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
8076 [(set (match_dup 0) (match_dup 2))
8077 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
8079 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
8081 if (tem == operands[0])
8087 ;; Split a load of a large constant into the appropriate five-instruction
8088 (define_insn "*movdi_internal2"
8089 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8090 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
8092 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
8097 [(set_attr "type" "compare")
8098 (set_attr "length" "4,8")])
8101 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8102 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
8104 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
8105 "TARGET_POWERPC64 && reload_completed"
8106 [(set (match_dup 0) (match_dup 1))
8108 (compare:CC (match_dup 0)
8112 ;; TImode is similar, except that we usually want to compute the address into
8113 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
8114 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
8115 (define_expand "movti"
8116 [(parallel [(set (match_operand:TI 0 "general_operand" "")
8117 (match_operand:TI 1 "general_operand" ""))
8118 (clobber (scratch:SI))])]
8119 "TARGET_STRING || TARGET_POWERPC64"
8120 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
8122 ;; We say that MQ is clobbered in the last alternative because the first
8123 ;; alternative would never get used otherwise since it would need a reload
8124 ;; while the 2nd alternative would not. We put memory cases first so they
8125 ;; are preferred. Otherwise, we'd try to reload the output instead of
8126 ;; giving the SCRATCH mq.
8127 (define_insn "*movti_power"
8128 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
8129 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
8130 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
8131 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8132 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8135 switch (which_alternative)
8141 return \"{stsi|stswi} %1,%P0,16\";
8144 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8147 /* Normally copy registers with lowest numbered register copied first.
8148 But copy in the other order if the first register of the output
8149 is the second, third, or fourth register in the input. */
8150 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8151 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8152 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8154 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8156 /* If the address is not used in the output, we can use lsi. Otherwise,
8157 fall through to generating four loads. */
8158 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
8159 return \"{lsi|lswi} %0,%P1,16\";
8160 /* ... fall through ... */
8162 /* If the address register is the same as the register for the lowest-
8163 addressed word, load it last. Similarly for the next two words.
8164 Otherwise load lowest address to highest. */
8165 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8167 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8168 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8169 REGNO (operands[0]) + 2, operands[1], 0))
8170 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8171 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8172 REGNO (operands[0]) + 3, operands[1], 0))
8173 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8175 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8178 [(set_attr "type" "store,store,*,load,load")
8179 (set_attr "length" "*,16,16,*,16")])
8181 (define_insn "*movti_string"
8182 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
8183 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
8184 (clobber (match_scratch:SI 2 "=X,X,X"))]
8185 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8186 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
8189 switch (which_alternative)
8195 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
8198 /* Normally copy registers with lowest numbered register copied first.
8199 But copy in the other order if the first register of the output
8200 is the second, third, or fourth register in the input. */
8201 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
8202 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
8203 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
8205 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
8207 /* If the address register is the same as the register for the lowest-
8208 addressed word, load it last. Similarly for the next two words.
8209 Otherwise load lowest address to highest. */
8210 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8212 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
8213 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
8214 REGNO (operands[0]) + 2, operands[1], 0))
8215 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
8216 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
8217 REGNO (operands[0]) + 3, operands[1], 0))
8218 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
8220 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
8223 [(set_attr "type" "store,*,load")
8224 (set_attr "length" "16,16,16")])
8226 (define_insn "*movti_ppc64"
8227 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
8228 (match_operand:TI 1 "input_operand" "r,m,r"))]
8229 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
8230 || gpc_reg_operand (operands[1], TImode))"
8233 switch (which_alternative)
8238 /* We normally copy the low-numbered register first. However, if
8239 the first register operand 0 is the same as the second register of
8240 operand 1, we must copy in the opposite order. */
8241 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8242 return \"mr %L0,%L1\;mr %0,%1\";
8244 return \"mr %0,%1\;mr %L0,%L1\";
8246 /* If the low-address word is used in the address, we must load it
8247 last. Otherwise, load it first. Note that we cannot have
8248 auto-increment in that case since the address register is known to be
8250 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8252 return \"ld %L0,%L1\;ld %0,%1\";
8254 return \"ld%U1 %0,%1\;ld %L0,%L1\";
8256 return \"std%U0 %1,%0\;std %L1,%L0\";
8259 [(set_attr "type" "*,load,store")
8260 (set_attr "length" "8,8,8")])
8262 (define_expand "load_multiple"
8263 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8264 (match_operand:SI 1 "" ""))
8265 (use (match_operand:SI 2 "" ""))])]
8274 /* Support only loading a constant number of fixed-point registers from
8275 memory and only bother with this if more than two; the machine
8276 doesn't support more than eight. */
8277 if (GET_CODE (operands[2]) != CONST_INT
8278 || INTVAL (operands[2]) <= 2
8279 || INTVAL (operands[2]) > 8
8280 || GET_CODE (operands[1]) != MEM
8281 || GET_CODE (operands[0]) != REG
8282 || REGNO (operands[0]) >= 32)
8285 count = INTVAL (operands[2]);
8286 regno = REGNO (operands[0]);
8288 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
8289 op1 = replace_equiv_address (operands[1],
8290 force_reg (SImode, XEXP (operands[1], 0)));
8292 for (i = 0; i < count; i++)
8293 XVECEXP (operands[3], 0, i)
8294 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
8295 adjust_address (op1, SImode, i * 4));
8299 [(match_parallel 0 "load_multiple_operation"
8300 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8301 (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])]
8305 /* We have to handle the case where the pseudo used to contain the address
8306 is assigned to one of the output registers. */
8308 int words = XVECLEN (operands[0], 0);
8311 if (XVECLEN (operands[0], 0) == 1)
8312 return \"{l|lwz} %1,0(%2)\";
8314 for (i = 0; i < words; i++)
8315 if (refers_to_regno_p (REGNO (operands[1]) + i,
8316 REGNO (operands[1]) + i + 1, operands[2], 0))
8320 xop[0] = operands[1];
8321 xop[1] = operands[2];
8322 xop[2] = GEN_INT (4 * (words-1));
8323 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
8328 xop[0] = operands[1];
8329 xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
8330 xop[2] = GEN_INT (4 * (words-1));
8331 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
8336 for (j = 0; j < words; j++)
8339 xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j);
8340 xop[1] = operands[2];
8341 xop[2] = GEN_INT (j * 4);
8342 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
8344 xop[0] = operands[2];
8345 xop[1] = GEN_INT (i * 4);
8346 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
8351 return \"{lsi|lswi} %1,%2,%N0\";
8353 [(set_attr "type" "load")
8354 (set_attr "length" "32")])
8357 (define_expand "store_multiple"
8358 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
8359 (match_operand:SI 1 "" ""))
8360 (clobber (scratch:SI))
8361 (use (match_operand:SI 2 "" ""))])]
8371 /* Support only storing a constant number of fixed-point registers to
8372 memory and only bother with this if more than two; the machine
8373 doesn't support more than eight. */
8374 if (GET_CODE (operands[2]) != CONST_INT
8375 || INTVAL (operands[2]) <= 2
8376 || INTVAL (operands[2]) > 8
8377 || GET_CODE (operands[0]) != MEM
8378 || GET_CODE (operands[1]) != REG
8379 || REGNO (operands[1]) >= 32)
8382 count = INTVAL (operands[2]);
8383 regno = REGNO (operands[1]);
8385 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
8386 to = force_reg (SImode, XEXP (operands[0], 0));
8387 op0 = replace_equiv_address (operands[0], to);
8389 XVECEXP (operands[3], 0, 0)
8390 = gen_rtx_SET (VOIDmode, adjust_address (op0, SImode, 0), operands[1]);
8391 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
8392 gen_rtx_SCRATCH (SImode));
8394 for (i = 1; i < count; i++)
8395 XVECEXP (operands[3], 0, i + 1)
8396 = gen_rtx_SET (VOIDmode,
8397 adjust_address (op0, SImode, i * 4),
8398 gen_rtx_REG (SImode, regno + i));
8402 [(match_parallel 0 "store_multiple_operation"
8403 [(set (match_operand:SI 1 "indirect_operand" "=Q")
8404 (match_operand:SI 2 "gpc_reg_operand" "r"))
8405 (clobber (match_scratch:SI 3 "=q"))])]
8406 "TARGET_STRING && TARGET_POWER"
8407 "{stsi|stswi} %2,%P1,%O0"
8408 [(set_attr "type" "store")])
8411 [(match_parallel 0 "store_multiple_operation"
8412 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
8413 (match_operand:SI 2 "gpc_reg_operand" "r"))
8414 (clobber (match_scratch:SI 3 "X"))])]
8415 "TARGET_STRING && ! TARGET_POWER"
8416 "{stsi|stswi} %2,%1,%O0"
8417 [(set_attr "type" "store")])
8420 ;; String/block move insn.
8421 ;; Argument 0 is the destination
8422 ;; Argument 1 is the source
8423 ;; Argument 2 is the length
8424 ;; Argument 3 is the alignment
8426 (define_expand "movstrsi"
8427 [(parallel [(set (match_operand:BLK 0 "" "")
8428 (match_operand:BLK 1 "" ""))
8429 (use (match_operand:SI 2 "" ""))
8430 (use (match_operand:SI 3 "" ""))])]
8434 if (expand_block_move (operands))
8440 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
8441 ;; register allocator doesn't have a clue about allocating 8 word registers.
8442 ;; rD/rS = r5 is preferred, efficient form.
8443 (define_expand "movstrsi_8reg"
8444 [(parallel [(set (match_operand 0 "" "")
8445 (match_operand 1 "" ""))
8446 (use (match_operand 2 "" ""))
8447 (use (match_operand 3 "" ""))
8448 (clobber (reg:SI 5))
8449 (clobber (reg:SI 6))
8450 (clobber (reg:SI 7))
8451 (clobber (reg:SI 8))
8452 (clobber (reg:SI 9))
8453 (clobber (reg:SI 10))
8454 (clobber (reg:SI 11))
8455 (clobber (reg:SI 12))
8456 (clobber (match_scratch:SI 4 ""))])]
8461 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8462 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8463 (use (match_operand:SI 2 "immediate_operand" "i"))
8464 (use (match_operand:SI 3 "immediate_operand" "i"))
8465 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8466 (clobber (reg:SI 6))
8467 (clobber (reg:SI 7))
8468 (clobber (reg:SI 8))
8469 (clobber (reg:SI 9))
8470 (clobber (reg:SI 10))
8471 (clobber (reg:SI 11))
8472 (clobber (reg:SI 12))
8473 (clobber (match_scratch:SI 5 "=q"))]
8474 "TARGET_STRING && TARGET_POWER
8475 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8476 || INTVAL (operands[2]) == 0)
8477 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8478 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8479 && REGNO (operands[4]) == 5"
8480 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8481 [(set_attr "type" "load")
8482 (set_attr "length" "8")])
8485 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8486 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8487 (use (match_operand:SI 2 "immediate_operand" "i"))
8488 (use (match_operand:SI 3 "immediate_operand" "i"))
8489 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8490 (clobber (reg:SI 6))
8491 (clobber (reg:SI 7))
8492 (clobber (reg:SI 8))
8493 (clobber (reg:SI 9))
8494 (clobber (reg:SI 10))
8495 (clobber (reg:SI 11))
8496 (clobber (reg:SI 12))
8497 (clobber (match_scratch:SI 5 "X"))]
8498 "TARGET_STRING && ! TARGET_POWER
8499 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
8500 || INTVAL (operands[2]) == 0)
8501 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
8502 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
8503 && REGNO (operands[4]) == 5"
8504 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8505 [(set_attr "type" "load")
8506 (set_attr "length" "8")])
8508 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
8509 ;; register allocator doesn't have a clue about allocating 6 word registers.
8510 ;; rD/rS = r5 is preferred, efficient form.
8511 (define_expand "movstrsi_6reg"
8512 [(parallel [(set (match_operand 0 "" "")
8513 (match_operand 1 "" ""))
8514 (use (match_operand 2 "" ""))
8515 (use (match_operand 3 "" ""))
8516 (clobber (reg:SI 5))
8517 (clobber (reg:SI 6))
8518 (clobber (reg:SI 7))
8519 (clobber (reg:SI 8))
8520 (clobber (reg:SI 9))
8521 (clobber (reg:SI 10))
8522 (clobber (match_scratch:SI 4 ""))])]
8527 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8528 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8529 (use (match_operand:SI 2 "immediate_operand" "i"))
8530 (use (match_operand:SI 3 "immediate_operand" "i"))
8531 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8532 (clobber (reg:SI 6))
8533 (clobber (reg:SI 7))
8534 (clobber (reg:SI 8))
8535 (clobber (reg:SI 9))
8536 (clobber (reg:SI 10))
8537 (clobber (match_scratch:SI 5 "=q"))]
8538 "TARGET_STRING && TARGET_POWER
8539 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
8540 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8541 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8542 && REGNO (operands[4]) == 5"
8543 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8544 [(set_attr "type" "load")
8545 (set_attr "length" "8")])
8548 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8549 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8550 (use (match_operand:SI 2 "immediate_operand" "i"))
8551 (use (match_operand:SI 3 "immediate_operand" "i"))
8552 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8553 (clobber (reg:SI 6))
8554 (clobber (reg:SI 7))
8555 (clobber (reg:SI 8))
8556 (clobber (reg:SI 9))
8557 (clobber (reg:SI 10))
8558 (clobber (match_scratch:SI 5 "X"))]
8559 "TARGET_STRING && ! TARGET_POWER
8560 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
8561 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
8562 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
8563 && REGNO (operands[4]) == 5"
8564 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8565 [(set_attr "type" "load")
8566 (set_attr "length" "8")])
8568 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
8569 ;; problems with TImode.
8570 ;; rD/rS = r5 is preferred, efficient form.
8571 (define_expand "movstrsi_4reg"
8572 [(parallel [(set (match_operand 0 "" "")
8573 (match_operand 1 "" ""))
8574 (use (match_operand 2 "" ""))
8575 (use (match_operand 3 "" ""))
8576 (clobber (reg:SI 5))
8577 (clobber (reg:SI 6))
8578 (clobber (reg:SI 7))
8579 (clobber (reg:SI 8))
8580 (clobber (match_scratch:SI 4 ""))])]
8585 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8586 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8587 (use (match_operand:SI 2 "immediate_operand" "i"))
8588 (use (match_operand:SI 3 "immediate_operand" "i"))
8589 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8590 (clobber (reg:SI 6))
8591 (clobber (reg:SI 7))
8592 (clobber (reg:SI 8))
8593 (clobber (match_scratch:SI 5 "=q"))]
8594 "TARGET_STRING && TARGET_POWER
8595 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8596 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8597 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8598 && REGNO (operands[4]) == 5"
8599 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8600 [(set_attr "type" "load")
8601 (set_attr "length" "8")])
8604 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8605 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8606 (use (match_operand:SI 2 "immediate_operand" "i"))
8607 (use (match_operand:SI 3 "immediate_operand" "i"))
8608 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
8609 (clobber (reg:SI 6))
8610 (clobber (reg:SI 7))
8611 (clobber (reg:SI 8))
8612 (clobber (match_scratch:SI 5 "X"))]
8613 "TARGET_STRING && ! TARGET_POWER
8614 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
8615 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
8616 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
8617 && REGNO (operands[4]) == 5"
8618 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8619 [(set_attr "type" "load")
8620 (set_attr "length" "8")])
8622 ;; Move up to 8 bytes at a time.
8623 (define_expand "movstrsi_2reg"
8624 [(parallel [(set (match_operand 0 "" "")
8625 (match_operand 1 "" ""))
8626 (use (match_operand 2 "" ""))
8627 (use (match_operand 3 "" ""))
8628 (clobber (match_scratch:DI 4 ""))
8629 (clobber (match_scratch:SI 5 ""))])]
8630 "TARGET_STRING && ! TARGET_POWERPC64"
8634 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8635 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8636 (use (match_operand:SI 2 "immediate_operand" "i"))
8637 (use (match_operand:SI 3 "immediate_operand" "i"))
8638 (clobber (match_scratch:DI 4 "=&r"))
8639 (clobber (match_scratch:SI 5 "=q"))]
8640 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
8641 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8642 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8643 [(set_attr "type" "load")
8644 (set_attr "length" "8")])
8647 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8648 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8649 (use (match_operand:SI 2 "immediate_operand" "i"))
8650 (use (match_operand:SI 3 "immediate_operand" "i"))
8651 (clobber (match_scratch:DI 4 "=&r"))
8652 (clobber (match_scratch:SI 5 "X"))]
8653 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
8654 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
8655 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8656 [(set_attr "type" "load")
8657 (set_attr "length" "8")])
8659 ;; Move up to 4 bytes at a time.
8660 (define_expand "movstrsi_1reg"
8661 [(parallel [(set (match_operand 0 "" "")
8662 (match_operand 1 "" ""))
8663 (use (match_operand 2 "" ""))
8664 (use (match_operand 3 "" ""))
8665 (clobber (match_scratch:SI 4 ""))
8666 (clobber (match_scratch:SI 5 ""))])]
8671 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8672 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8673 (use (match_operand:SI 2 "immediate_operand" "i"))
8674 (use (match_operand:SI 3 "immediate_operand" "i"))
8675 (clobber (match_scratch:SI 4 "=&r"))
8676 (clobber (match_scratch:SI 5 "=q"))]
8677 "TARGET_STRING && TARGET_POWER
8678 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8679 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8680 [(set_attr "type" "load")
8681 (set_attr "length" "8")])
8684 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
8685 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
8686 (use (match_operand:SI 2 "immediate_operand" "i"))
8687 (use (match_operand:SI 3 "immediate_operand" "i"))
8688 (clobber (match_scratch:SI 4 "=&r"))
8689 (clobber (match_scratch:SI 5 "X"))]
8690 "TARGET_STRING && ! TARGET_POWER
8691 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
8692 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
8693 [(set_attr "type" "load")
8694 (set_attr "length" "8")])
8697 ;; Define insns that do load or store with update. Some of these we can
8698 ;; get by using pre-decrement or pre-increment, but the hardware can also
8699 ;; do cases where the increment is not the size of the object.
8701 ;; In all these cases, we use operands 0 and 1 for the register being
8702 ;; incremented because those are the operands that local-alloc will
8703 ;; tie and these are the pair most likely to be tieable (and the ones
8704 ;; that will benefit the most).
8706 (define_insn "*movdi_update1"
8707 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
8708 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8709 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
8710 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8711 (plus:DI (match_dup 1) (match_dup 2)))]
8712 "TARGET_POWERPC64 && TARGET_UPDATE"
8716 [(set_attr "type" "load")])
8718 (define_insn "*movdi_update2"
8719 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
8721 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
8722 (match_operand:DI 2 "gpc_reg_operand" "r")))))
8723 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
8724 (plus:DI (match_dup 1) (match_dup 2)))]
8727 [(set_attr "type" "load")])
8729 (define_insn "movdi_update"
8730 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
8731 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
8732 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
8733 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
8734 (plus:DI (match_dup 1) (match_dup 2)))]
8735 "TARGET_POWERPC64 && TARGET_UPDATE"
8739 [(set_attr "type" "store")])
8741 (define_insn "*movsi_update1"
8742 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8743 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8744 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8745 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8746 (plus:SI (match_dup 1) (match_dup 2)))]
8749 {lux|lwzux} %3,%0,%2
8750 {lu|lwzu} %3,%2(%0)"
8751 [(set_attr "type" "load")])
8753 (define_insn "movsi_update"
8754 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8755 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8756 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
8757 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8758 (plus:SI (match_dup 1) (match_dup 2)))]
8761 {stux|stwux} %3,%0,%2
8762 {stu|stwu} %3,%2(%0)"
8763 [(set_attr "type" "store")])
8765 (define_insn "*movhi_update"
8766 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
8767 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8768 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8769 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8770 (plus:SI (match_dup 1) (match_dup 2)))]
8775 [(set_attr "type" "load")])
8777 (define_insn "*movhi_update2"
8778 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8780 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8781 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8782 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8783 (plus:SI (match_dup 1) (match_dup 2)))]
8788 [(set_attr "type" "load")])
8790 (define_insn "*movhi_update3"
8791 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8793 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8794 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8795 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8796 (plus:SI (match_dup 1) (match_dup 2)))]
8801 [(set_attr "type" "load")])
8803 (define_insn "*movhi_update4"
8804 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8805 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8806 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
8807 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8808 (plus:SI (match_dup 1) (match_dup 2)))]
8813 [(set_attr "type" "store")])
8815 (define_insn "*movqi_update1"
8816 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
8817 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8818 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8819 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8820 (plus:SI (match_dup 1) (match_dup 2)))]
8825 [(set_attr "type" "load")])
8827 (define_insn "*movqi_update2"
8828 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
8830 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8831 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
8832 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8833 (plus:SI (match_dup 1) (match_dup 2)))]
8838 [(set_attr "type" "load")])
8840 (define_insn "*movqi_update3"
8841 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8842 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8843 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
8844 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8845 (plus:SI (match_dup 1) (match_dup 2)))]
8850 [(set_attr "type" "store")])
8852 (define_insn "*movsf_update1"
8853 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
8854 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8855 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8856 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8857 (plus:SI (match_dup 1) (match_dup 2)))]
8858 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8862 [(set_attr "type" "fpload")])
8864 (define_insn "*movsf_update2"
8865 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8866 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8867 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
8868 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8869 (plus:SI (match_dup 1) (match_dup 2)))]
8870 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8874 [(set_attr "type" "fpstore")])
8876 (define_insn "*movsf_update3"
8877 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
8878 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8879 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8880 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8881 (plus:SI (match_dup 1) (match_dup 2)))]
8882 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
8884 {lux|lwzux} %3,%0,%2
8885 {lu|lwzu} %3,%2(%0)"
8886 [(set_attr "type" "load")])
8888 (define_insn "*movsf_update4"
8889 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8890 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8891 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
8892 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8893 (plus:SI (match_dup 1) (match_dup 2)))]
8894 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
8896 {stux|stwux} %3,%0,%2
8897 {stu|stwu} %3,%2(%0)"
8898 [(set_attr "type" "store")])
8900 (define_insn "*movdf_update1"
8901 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
8902 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8903 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
8904 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8905 (plus:SI (match_dup 1) (match_dup 2)))]
8906 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8910 [(set_attr "type" "fpload")])
8912 (define_insn "*movdf_update2"
8913 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
8914 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
8915 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
8916 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
8917 (plus:SI (match_dup 1) (match_dup 2)))]
8918 "TARGET_HARD_FLOAT && TARGET_UPDATE"
8922 [(set_attr "type" "fpstore")])
8924 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
8927 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8928 (match_operand:DF 1 "memory_operand" ""))
8929 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
8930 (match_operand:DF 3 "memory_operand" ""))]
8932 && TARGET_HARD_FLOAT
8933 && registers_ok_for_quad_peep (operands[0], operands[2])
8934 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
8935 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
8939 [(set (match_operand:DF 0 "memory_operand" "")
8940 (match_operand:DF 1 "gpc_reg_operand" "f"))
8941 (set (match_operand:DF 2 "memory_operand" "")
8942 (match_operand:DF 3 "gpc_reg_operand" "f"))]
8944 && TARGET_HARD_FLOAT
8945 && registers_ok_for_quad_peep (operands[1], operands[3])
8946 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
8947 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
8950 ;; Next come insns related to the calling sequence.
8952 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
8953 ;; We move the back-chain and decrement the stack pointer.
8955 (define_expand "allocate_stack"
8956 [(set (match_operand 0 "gpc_reg_operand" "=r")
8957 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
8959 (minus (reg 1) (match_dup 1)))]
8962 { rtx chain = gen_reg_rtx (Pmode);
8963 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
8966 emit_move_insn (chain, stack_bot);
8968 /* Check stack bounds if necessary. */
8969 if (current_function_limit_stack)
8972 available = expand_binop (Pmode, sub_optab,
8973 stack_pointer_rtx, stack_limit_rtx,
8974 NULL_RTX, 1, OPTAB_WIDEN);
8975 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
8978 if (GET_CODE (operands[1]) != CONST_INT
8979 || INTVAL (operands[1]) < -32767
8980 || INTVAL (operands[1]) > 32768)
8982 neg_op0 = gen_reg_rtx (Pmode);
8984 emit_insn (gen_negsi2 (neg_op0, operands[1]));
8986 emit_insn (gen_negdi2 (neg_op0, operands[1]));
8989 neg_op0 = GEN_INT (- INTVAL (operands[1]));
8992 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
8993 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
8997 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
8998 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
8999 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
9002 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9006 ;; These patterns say how to save and restore the stack pointer. We need not
9007 ;; save the stack pointer at function level since we are careful to
9008 ;; preserve the backchain. At block level, we have to restore the backchain
9009 ;; when we restore the stack pointer.
9011 ;; For nonlocal gotos, we must save both the stack pointer and its
9012 ;; backchain and restore both. Note that in the nonlocal case, the
9013 ;; save area is a memory location.
9015 (define_expand "save_stack_function"
9016 [(match_operand 0 "any_operand" "")
9017 (match_operand 1 "any_operand" "")]
9021 (define_expand "restore_stack_function"
9022 [(match_operand 0 "any_operand" "")
9023 (match_operand 1 "any_operand" "")]
9027 (define_expand "restore_stack_block"
9028 [(use (match_operand 0 "register_operand" ""))
9029 (set (match_dup 2) (match_dup 3))
9030 (set (match_dup 0) (match_operand 1 "register_operand" ""))
9031 (set (match_dup 3) (match_dup 2))]
9035 operands[2] = gen_reg_rtx (Pmode);
9036 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
9039 (define_expand "save_stack_nonlocal"
9040 [(match_operand 0 "memory_operand" "")
9041 (match_operand 1 "register_operand" "")]
9045 rtx temp = gen_reg_rtx (Pmode);
9047 /* Copy the backchain to the first word, sp to the second. */
9048 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
9049 emit_move_insn (operand_subword (operands[0], 0, 0,
9050 (TARGET_32BIT ? DImode : TImode)),
9052 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
9057 (define_expand "restore_stack_nonlocal"
9058 [(match_operand 0 "register_operand" "")
9059 (match_operand 1 "memory_operand" "")]
9063 rtx temp = gen_reg_rtx (Pmode);
9065 /* Restore the backchain from the first word, sp from the second. */
9066 emit_move_insn (temp,
9067 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
9068 emit_move_insn (operands[0],
9069 operand_subword (operands[1], 1, 0,
9070 (TARGET_32BIT ? DImode : TImode)));
9071 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
9075 ;; TOC register handling.
9077 ;; Code to initialize the TOC register...
9079 (define_insn "load_toc_aix_si"
9080 [(parallel [(set (match_operand:SI 0 "register_operand" "=r")
9081 (unspec:SI [(const_int 0)] 7))
9083 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
9087 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9088 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9089 operands[2] = gen_rtx_REG (Pmode, 2);
9090 return \"{l|lwz} %0,%1(%2)\";
9092 [(set_attr "type" "load")])
9094 (define_insn "load_toc_aix_di"
9095 [(parallel [(set (match_operand:DI 0 "register_operand" "=r")
9096 (unspec:DI [(const_int 0)] 7))
9098 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
9102 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
9104 strcat (buf, \"@toc\");
9105 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
9106 operands[2] = gen_rtx_REG (Pmode, 2);
9107 return \"ld %0,%1(%2)\";
9109 [(set_attr "type" "load")])
9111 (define_insn "load_toc_v4_pic_si"
9112 [(set (match_operand:SI 0 "register_operand" "=l")
9113 (unspec:SI [(const_int 0)] 7))]
9114 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1
9116 "bl _GLOBAL_OFFSET_TABLE_@local-4"
9117 [(set_attr "type" "branch")
9118 (set_attr "length" "4")])
9120 (define_insn "load_toc_v4_PIC_1"
9121 [(set (match_operand:SI 0 "register_operand" "=l")
9122 (match_operand:SI 1 "immediate_operand" "s"))
9123 (unspec [(match_dup 1)] 7)]
9124 "TARGET_ELF && flag_pic == 2"
9126 [(set_attr "type" "branch")
9127 (set_attr "length" "4")])
9129 (define_insn "load_toc_v4_PIC_1b"
9130 [(set (match_operand:SI 0 "register_operand" "=l")
9131 (match_operand:SI 1 "immediate_operand" "s"))
9132 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
9133 "TARGET_ELF && flag_pic == 2"
9134 "bl %1\\n\\t.long %2-%1+4\\n%1:"
9135 [(set_attr "type" "branch")
9136 (set_attr "length" "8")])
9138 (define_insn "load_toc_v4_PIC_2"
9139 [(set (match_operand:SI 0 "register_operand" "=r")
9140 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
9141 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
9142 (match_operand:SI 3 "immediate_operand" "s")))))]
9143 "TARGET_ELF && flag_pic == 2"
9144 "{l|lwz} %0,%2-%3(%1)"
9145 [(set_attr "type" "load")])
9147 (define_insn "load_macho_picbase"
9148 [(set (match_operand:SI 0 "register_operand" "=l")
9149 (unspec:SI [(const_int 0)] 15))]
9150 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
9154 char *picbase = machopic_function_base_name ();
9155 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
9157 return \"bcl 20,31,%1\\n%1:\";
9159 [(set_attr "type" "branch")
9160 (set_attr "length" "4")])
9162 ;; If the TOC is shared over a translation unit, as happens with all
9163 ;; the kinds of PIC that we support, we need to restore the TOC
9164 ;; pointer only when jumping over units of translation.
9166 (define_expand "builtin_setjmp_receiver"
9167 [(use (label_ref (match_operand 0 "" "")))]
9168 "((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1)
9169 || (TARGET_TOC && TARGET_MINIMAL_TOC)"
9172 rs6000_emit_load_toc_table (FALSE);
9176 ;; A function pointer under AIX is a pointer to a data area whose first word
9177 ;; contains the actual address of the function, whose second word contains a
9178 ;; pointer to its TOC, and whose third word contains a value to place in the
9179 ;; static chain register (r11). Note that if we load the static chain, our
9180 ;; "trampoline" need not have any executable code.
9182 (define_expand "call_indirect_aix32"
9184 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
9185 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9188 (mem:SI (plus:SI (match_dup 0)
9191 (mem:SI (plus:SI (match_dup 0)
9193 (parallel [(call (mem:SI (match_dup 2))
9194 (match_operand 1 "" ""))
9198 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9199 (clobber (scratch:SI))])]
9202 { operands[2] = gen_reg_rtx (SImode); }")
9204 (define_expand "call_indirect_aix64"
9206 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
9207 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9210 (mem:DI (plus:DI (match_dup 0)
9213 (mem:DI (plus:DI (match_dup 0)
9215 (parallel [(call (mem:SI (match_dup 2))
9216 (match_operand 1 "" ""))
9220 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9221 (clobber (scratch:SI))])]
9224 { operands[2] = gen_reg_rtx (DImode); }")
9226 (define_expand "call_value_indirect_aix32"
9228 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
9229 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
9232 (mem:SI (plus:SI (match_dup 1)
9235 (mem:SI (plus:SI (match_dup 1)
9237 (parallel [(set (match_operand 0 "" "")
9238 (call (mem:SI (match_dup 3))
9239 (match_operand 2 "" "")))
9243 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9244 (clobber (scratch:SI))])]
9247 { operands[3] = gen_reg_rtx (SImode); }")
9249 (define_expand "call_value_indirect_aix64"
9251 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
9252 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
9255 (mem:DI (plus:DI (match_dup 1)
9258 (mem:DI (plus:DI (match_dup 1)
9260 (parallel [(set (match_operand 0 "" "")
9261 (call (mem:SI (match_dup 3))
9262 (match_operand 2 "" "")))
9266 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9267 (clobber (scratch:SI))])]
9270 { operands[3] = gen_reg_rtx (DImode); }")
9272 ;; Now the definitions for the call and call_value insns
9273 (define_expand "call"
9274 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
9275 (match_operand 1 "" ""))
9276 (use (match_operand 2 "" ""))
9277 (clobber (scratch:SI))])]
9283 operands[0] = machopic_indirect_call_target (operands[0]);
9286 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
9289 operands[0] = XEXP (operands[0], 0);
9291 if (GET_CODE (operands[0]) != SYMBOL_REF
9292 || (INTVAL (operands[2]) & CALL_LONG) != 0)
9294 if (INTVAL (operands[2]) & CALL_LONG)
9295 operands[0] = rs6000_longcall_ref (operands[0]);
9297 if (DEFAULT_ABI == ABI_V4
9298 || DEFAULT_ABI == ABI_AIX_NODESC
9299 || DEFAULT_ABI == ABI_DARWIN
9300 || DEFAULT_ABI == ABI_SOLARIS)
9301 operands[0] = force_reg (Pmode, operands[0]);
9303 else if (DEFAULT_ABI == ABI_AIX)
9305 /* AIX function pointers are really pointers to a three word
9307 emit_call_insn (TARGET_32BIT
9308 ? gen_call_indirect_aix32 (force_reg (SImode,
9311 : gen_call_indirect_aix64 (force_reg (DImode,
9321 (define_expand "call_value"
9322 [(parallel [(set (match_operand 0 "" "")
9323 (call (mem:SI (match_operand 1 "address_operand" ""))
9324 (match_operand 2 "" "")))
9325 (use (match_operand 3 "" ""))
9326 (clobber (scratch:SI))])]
9332 operands[1] = machopic_indirect_call_target (operands[1]);
9335 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
9338 operands[1] = XEXP (operands[1], 0);
9340 if (GET_CODE (operands[1]) != SYMBOL_REF
9341 || (INTVAL (operands[3]) & CALL_LONG) != 0)
9343 if (INTVAL (operands[3]) & CALL_LONG)
9344 operands[1] = rs6000_longcall_ref (operands[1]);
9346 if (DEFAULT_ABI == ABI_V4
9347 || DEFAULT_ABI == ABI_AIX_NODESC
9348 || DEFAULT_ABI == ABI_DARWIN
9349 || DEFAULT_ABI == ABI_SOLARIS)
9350 operands[0] = force_reg (Pmode, operands[0]);
9352 else if (DEFAULT_ABI == ABI_AIX)
9354 /* AIX function pointers are really pointers to a three word
9356 emit_call_insn (TARGET_32BIT
9357 ? gen_call_value_indirect_aix32 (operands[0],
9361 : gen_call_value_indirect_aix64 (operands[0],
9372 ;; Call to function in current module. No TOC pointer reload needed.
9373 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
9374 ;; either the function was not prototyped, or it was prototyped as a
9375 ;; variable argument function. It is > 0 if FP registers were passed
9376 ;; and < 0 if they were not.
9378 (define_insn "*call_local32"
9379 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
9380 (match_operand 1 "" "g,g"))
9381 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9382 (clobber (match_scratch:SI 3 "=l,l"))]
9383 "(INTVAL (operands[2]) & CALL_LONG) == 0"
9386 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9387 output_asm_insn (\"crxor 6,6,6\", operands);
9389 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9390 output_asm_insn (\"creqv 6,6,6\", operands);
9392 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9394 [(set_attr "type" "branch")
9395 (set_attr "length" "4,8")])
9397 (define_insn "*call_local64"
9398 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
9399 (match_operand 1 "" "g,g"))
9400 (use (match_operand:SI 2 "immediate_operand" "O,n"))
9401 (clobber (match_scratch:SI 3 "=l,l"))]
9402 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
9405 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9406 output_asm_insn (\"crxor 6,6,6\", operands);
9408 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9409 output_asm_insn (\"creqv 6,6,6\", operands);
9411 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
9413 [(set_attr "type" "branch")
9414 (set_attr "length" "4,8")])
9416 (define_insn "*call_value_local32"
9417 [(set (match_operand 0 "" "=fg,fg")
9418 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
9419 (match_operand 2 "" "g,g")))
9420 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9421 (clobber (match_scratch:SI 4 "=l,l"))]
9422 "(INTVAL (operands[3]) & CALL_LONG) == 0"
9425 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9426 output_asm_insn (\"crxor 6,6,6\", operands);
9428 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9429 output_asm_insn (\"creqv 6,6,6\", operands);
9431 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9433 [(set_attr "type" "branch")
9434 (set_attr "length" "4,8")])
9437 (define_insn "*call_value_local64"
9438 [(set (match_operand 0 "" "=fg,fg")
9439 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
9440 (match_operand 2 "" "g,g")))
9441 (use (match_operand:SI 3 "immediate_operand" "O,n"))
9442 (clobber (match_scratch:SI 4 "=l,l"))]
9443 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
9446 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9447 output_asm_insn (\"crxor 6,6,6\", operands);
9449 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9450 output_asm_insn (\"creqv 6,6,6\", operands);
9452 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
9454 [(set_attr "type" "branch")
9455 (set_attr "length" "4,8")])
9457 ;; Call to function which may be in another module. Restore the TOC
9458 ;; pointer (r2) after the call unless this is System V.
9459 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
9460 ;; either the function was not prototyped, or it was prototyped as a
9461 ;; variable argument function. It is > 0 if FP registers were passed
9462 ;; and < 0 if they were not.
9464 (define_insn "*call_indirect_nonlocal_aix32"
9465 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
9466 (match_operand 1 "" "g"))
9470 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9471 (clobber (match_scratch:SI 2 "=l"))]
9472 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9473 "b%T0l\;{l|lwz} 2,20(1)"
9474 [(set_attr "type" "jmpreg")
9475 (set_attr "length" "8")])
9477 (define_insn "*call_nonlocal_aix32"
9478 [(call (mem:SI (match_operand:SI 0 "call_operand" "s"))
9479 (match_operand 1 "" "g"))
9480 (use (match_operand:SI 2 "immediate_operand" "O"))
9481 (clobber (match_scratch:SI 3 "=l"))]
9483 && DEFAULT_ABI == ABI_AIX
9484 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9486 [(set_attr "type" "branch")
9487 (set_attr "length" "8")])
9489 (define_insn "*call_indirect_nonlocal_aix64"
9490 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
9491 (match_operand 1 "" "g"))
9495 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9496 (clobber (match_scratch:SI 2 "=l"))]
9497 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9499 [(set_attr "type" "jmpreg")
9500 (set_attr "length" "8")])
9502 (define_insn "*call_nonlocal_aix64"
9503 [(call (mem:SI (match_operand:DI 0 "call_operand" "s"))
9504 (match_operand 1 "" "g"))
9505 (use (match_operand:SI 2 "immediate_operand" "O"))
9506 (clobber (match_scratch:SI 3 "=l"))]
9508 && DEFAULT_ABI == ABI_AIX
9509 && (INTVAL (operands[2]) & CALL_LONG) == 0"
9511 [(set_attr "type" "branch")
9512 (set_attr "length" "8")])
9514 (define_insn "*call_value_indirect_nonlocal_aix32"
9515 [(set (match_operand 0 "" "=fg")
9516 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
9517 (match_operand 2 "" "g")))
9521 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
9522 (clobber (match_scratch:SI 3 "=l"))]
9523 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
9524 "b%T1l\;{l|lwz} 2,20(1)"
9525 [(set_attr "type" "jmpreg")
9526 (set_attr "length" "8")])
9528 (define_insn "*call_value_nonlocal_aix32"
9529 [(set (match_operand 0 "" "=fg")
9530 (call (mem:SI (match_operand:SI 1 "call_operand" "s"))
9531 (match_operand 2 "" "g")))
9532 (use (match_operand:SI 3 "immediate_operand" "O"))
9533 (clobber (match_scratch:SI 4 "=l"))]
9535 && DEFAULT_ABI == ABI_AIX
9536 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9538 [(set_attr "type" "branch")
9539 (set_attr "length" "8")])
9541 (define_insn "*call_value_indirect_nonlocal_aix64"
9542 [(set (match_operand 0 "" "=fg")
9543 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
9544 (match_operand 2 "" "g")))
9548 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
9549 (clobber (match_scratch:SI 3 "=l"))]
9550 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
9552 [(set_attr "type" "jmpreg")
9553 (set_attr "length" "8")])
9555 (define_insn "*call_value_nonlocal_aix64"
9556 [(set (match_operand 0 "" "=fg")
9557 (call (mem:SI (match_operand:DI 1 "call_operand" "s"))
9558 (match_operand 2 "" "g")))
9559 (use (match_operand:SI 3 "immediate_operand" "O"))
9560 (clobber (match_scratch:SI 4 "=l"))]
9562 && DEFAULT_ABI == ABI_AIX
9563 && (INTVAL (operands[3]) & CALL_LONG) == 0"
9565 [(set_attr "type" "branch")
9566 (set_attr "length" "8")])
9568 ;; A function pointer under System V is just a normal pointer
9569 ;; operands[0] is the function pointer
9570 ;; operands[1] is the stack size to clean up
9571 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
9572 ;; which indicates how to set cr1
9574 (define_insn "*call_nonlocal_sysv"
9575 [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s"))
9576 (match_operand 1 "" "g,g,g,g"))
9577 (use (match_operand:SI 2 "immediate_operand" "O,n,O,n"))
9578 (clobber (match_scratch:SI 3 "=l,l,l,l"))]
9579 "DEFAULT_ABI == ABI_AIX_NODESC
9580 || DEFAULT_ABI == ABI_V4
9581 || DEFAULT_ABI == ABI_DARWIN
9582 || DEFAULT_ABI == ABI_SOLARIS"
9585 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
9586 output_asm_insn (\"crxor 6,6,6\", operands);
9588 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
9589 output_asm_insn (\"creqv 6,6,6\", operands);
9591 switch (which_alternative)
9600 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
9603 [(set_attr "type" "jmpreg,jmpreg,branch,branch")
9604 (set_attr "length" "4,8,4,8")])
9606 (define_insn "*call_value_nonlocal_sysv"
9607 [(set (match_operand 0 "" "=fg,fg,fg,fg")
9608 (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s"))
9609 (match_operand 2 "" "g,g,g,g")))
9610 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
9611 (clobber (match_scratch:SI 4 "=l,l,l,l"))]
9612 "DEFAULT_ABI == ABI_AIX_NODESC
9613 || DEFAULT_ABI == ABI_V4
9614 || DEFAULT_ABI == ABI_DARWIN
9615 || DEFAULT_ABI == ABI_SOLARIS"
9618 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
9619 output_asm_insn (\"crxor 6,6,6\", operands);
9621 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
9622 output_asm_insn (\"creqv 6,6,6\", operands);
9624 switch (which_alternative)
9633 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
9636 [(set_attr "type" "jmpreg,jmpreg,branch,branch")
9637 (set_attr "length" "4,8,4,8")])
9639 ;; Call subroutine returning any type.
9640 (define_expand "untyped_call"
9641 [(parallel [(call (match_operand 0 "" "")
9643 (match_operand 1 "" "")
9644 (match_operand 2 "" "")])]
9650 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
9652 for (i = 0; i < XVECLEN (operands[2], 0); i++)
9654 rtx set = XVECEXP (operands[2], 0, i);
9655 emit_move_insn (SET_DEST (set), SET_SRC (set));
9658 /* The optimizer does not know that the call sets the function value
9659 registers we stored in the result block. We avoid problems by
9660 claiming that all hard registers are used and clobbered at this
9662 emit_insn (gen_blockage ());
9667 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
9668 ;; all of memory. This blocks insns from being moved across this point.
9670 (define_insn "blockage"
9671 [(unspec_volatile [(const_int 0)] 0)]
9675 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
9676 ;; signed & unsigned, and one type of branch.
9678 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
9679 ;; insns, and branches. We store the operands of compares until we see
9681 (define_expand "cmpsi"
9683 (compare (match_operand:SI 0 "gpc_reg_operand" "")
9684 (match_operand:SI 1 "reg_or_short_operand" "")))]
9688 /* Take care of the possibility that operands[1] might be negative but
9689 this might be a logical operation. That insn doesn't exist. */
9690 if (GET_CODE (operands[1]) == CONST_INT
9691 && INTVAL (operands[1]) < 0)
9692 operands[1] = force_reg (SImode, operands[1]);
9694 rs6000_compare_op0 = operands[0];
9695 rs6000_compare_op1 = operands[1];
9696 rs6000_compare_fp_p = 0;
9700 (define_expand "cmpdi"
9702 (compare (match_operand:DI 0 "gpc_reg_operand" "")
9703 (match_operand:DI 1 "reg_or_short_operand" "")))]
9707 /* Take care of the possibility that operands[1] might be negative but
9708 this might be a logical operation. That insn doesn't exist. */
9709 if (GET_CODE (operands[1]) == CONST_INT
9710 && INTVAL (operands[1]) < 0)
9711 operands[1] = force_reg (DImode, operands[1]);
9713 rs6000_compare_op0 = operands[0];
9714 rs6000_compare_op1 = operands[1];
9715 rs6000_compare_fp_p = 0;
9719 (define_expand "cmpsf"
9720 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
9721 (match_operand:SF 1 "gpc_reg_operand" "")))]
9725 rs6000_compare_op0 = operands[0];
9726 rs6000_compare_op1 = operands[1];
9727 rs6000_compare_fp_p = 1;
9731 (define_expand "cmpdf"
9732 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
9733 (match_operand:DF 1 "gpc_reg_operand" "")))]
9737 rs6000_compare_op0 = operands[0];
9738 rs6000_compare_op1 = operands[1];
9739 rs6000_compare_fp_p = 1;
9743 (define_expand "beq"
9744 [(use (match_operand 0 "" ""))]
9746 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
9748 (define_expand "bne"
9749 [(use (match_operand 0 "" ""))]
9751 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
9753 (define_expand "bge"
9754 [(use (match_operand 0 "" ""))]
9756 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
9758 (define_expand "bgt"
9759 [(use (match_operand 0 "" ""))]
9761 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
9763 (define_expand "ble"
9764 [(use (match_operand 0 "" ""))]
9766 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
9768 (define_expand "blt"
9769 [(use (match_operand 0 "" ""))]
9771 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
9773 (define_expand "bgeu"
9774 [(use (match_operand 0 "" ""))]
9776 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
9778 (define_expand "bgtu"
9779 [(use (match_operand 0 "" ""))]
9781 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
9783 (define_expand "bleu"
9784 [(use (match_operand 0 "" ""))]
9786 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
9788 (define_expand "bltu"
9789 [(use (match_operand 0 "" ""))]
9791 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
9793 (define_expand "bunordered"
9794 [(use (match_operand 0 "" ""))]
9796 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
9798 (define_expand "bordered"
9799 [(use (match_operand 0 "" ""))]
9801 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
9803 (define_expand "buneq"
9804 [(use (match_operand 0 "" ""))]
9806 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
9808 (define_expand "bunge"
9809 [(use (match_operand 0 "" ""))]
9811 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
9813 (define_expand "bungt"
9814 [(use (match_operand 0 "" ""))]
9816 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
9818 (define_expand "bunle"
9819 [(use (match_operand 0 "" ""))]
9821 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
9823 (define_expand "bunlt"
9824 [(use (match_operand 0 "" ""))]
9826 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
9828 (define_expand "bltgt"
9829 [(use (match_operand 0 "" ""))]
9831 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
9833 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
9834 ;; For SEQ, likewise, except that comparisons with zero should be done
9835 ;; with an scc insns. However, due to the order that combine see the
9836 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
9837 ;; the cases we don't want to handle.
9838 (define_expand "seq"
9839 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9841 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
9843 (define_expand "sne"
9844 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9848 if (! rs6000_compare_fp_p)
9851 rs6000_emit_sCOND (NE, operands[0]);
9855 ;; A > 0 is best done using the portable sequence, so fail in that case.
9856 (define_expand "sgt"
9857 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9861 if (! rs6000_compare_fp_p
9862 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9865 rs6000_emit_sCOND (GT, operands[0]);
9869 ;; A < 0 is best done in the portable way for A an integer.
9870 (define_expand "slt"
9871 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9875 if (! rs6000_compare_fp_p
9876 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9879 rs6000_emit_sCOND (LT, operands[0]);
9883 ;; A >= 0 is best done the portable way for A an integer.
9884 (define_expand "sge"
9885 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9889 if (! rs6000_compare_fp_p
9890 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9893 rs6000_emit_sCOND (GE, operands[0]);
9897 ;; A <= 0 is best done the portable way for A an integer.
9898 (define_expand "sle"
9899 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9903 if (! rs6000_compare_fp_p
9904 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
9907 rs6000_emit_sCOND (LE, operands[0]);
9911 (define_expand "sgtu"
9912 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9914 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
9916 (define_expand "sltu"
9917 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9919 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
9921 (define_expand "sgeu"
9922 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9924 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
9926 (define_expand "sleu"
9927 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
9929 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
9931 ;; Here are the actual compare insns.
9932 (define_insn "*cmpsi_internal1"
9933 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
9934 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
9935 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
9937 "{cmp%I2|cmpw%I2} %0,%1,%2"
9938 [(set_attr "type" "compare")])
9940 (define_insn "*cmpdi_internal1"
9941 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
9942 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
9943 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
9946 [(set_attr "type" "compare")])
9948 ;; If we are comparing a register for equality with a large constant,
9949 ;; we can do this with an XOR followed by a compare. But we need a scratch
9950 ;; register for the result of the XOR.
9953 [(set (match_operand:CC 0 "cc_reg_operand" "")
9954 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
9955 (match_operand:SI 2 "non_short_cint_operand" "")))
9956 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
9957 "find_single_use (operands[0], insn, 0)
9958 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
9959 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
9960 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
9961 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
9964 /* Get the constant we are comparing against, C, and see what it looks like
9965 sign-extended to 16 bits. Then see what constant could be XOR'ed
9966 with C to get the sign-extended value. */
9968 HOST_WIDE_INT c = INTVAL (operands[2]);
9969 HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000);
9970 HOST_WIDE_INT xorv = c ^ sextc;
9972 operands[4] = GEN_INT (xorv);
9973 operands[5] = GEN_INT (sextc);
9976 (define_insn "*cmpsi_internal2"
9977 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
9978 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
9979 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
9981 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
9982 [(set_attr "type" "compare")])
9984 (define_insn "*cmpdi_internal2"
9985 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
9986 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
9987 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
9989 "cmpld%I2 %0,%1,%b2"
9990 [(set_attr "type" "compare")])
9992 ;; The following two insns don't exist as single insns, but if we provide
9993 ;; them, we can swap an add and compare, which will enable us to overlap more
9994 ;; of the required delay between a compare and branch. We generate code for
9995 ;; them by splitting.
9998 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
9999 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
10000 (match_operand:SI 2 "short_cint_operand" "i")))
10001 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10002 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10005 [(set_attr "length" "8")])
10008 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
10009 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
10010 (match_operand:SI 2 "u_short_cint_operand" "i")))
10011 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
10012 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
10015 [(set_attr "length" "8")])
10018 [(set (match_operand:CC 3 "cc_reg_operand" "")
10019 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
10020 (match_operand:SI 2 "short_cint_operand" "")))
10021 (set (match_operand:SI 0 "gpc_reg_operand" "")
10022 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10024 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
10025 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10028 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
10029 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
10030 (match_operand:SI 2 "u_short_cint_operand" "")))
10031 (set (match_operand:SI 0 "gpc_reg_operand" "")
10032 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
10034 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
10035 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
10037 (define_insn "*cmpsf_internal1"
10038 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10039 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
10040 (match_operand:SF 2 "gpc_reg_operand" "f")))]
10041 "TARGET_HARD_FLOAT"
10043 [(set_attr "type" "fpcompare")])
10045 (define_insn "*cmpdf_internal1"
10046 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
10047 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
10048 (match_operand:DF 2 "gpc_reg_operand" "f")))]
10049 "TARGET_HARD_FLOAT"
10051 [(set_attr "type" "fpcompare")])
10053 ;; Now we have the scc insns. We can do some combinations because of the
10054 ;; way the machine works.
10056 ;; Note that this is probably faster if we can put an insn between the
10057 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
10058 ;; cases the insns below which don't use an intermediate CR field will
10059 ;; be used instead.
10061 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10062 (match_operator:SI 1 "scc_comparison_operator"
10063 [(match_operand 2 "cc_reg_operand" "y")
10066 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
10067 [(set_attr "length" "12")])
10070 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10071 (match_operator:DI 1 "scc_comparison_operator"
10072 [(match_operand 2 "cc_reg_operand" "y")
10075 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
10076 [(set_attr "length" "12")])
10079 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10080 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10081 [(match_operand 2 "cc_reg_operand" "y,y")
10084 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10085 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10086 "! TARGET_POWERPC64"
10088 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
10090 [(set_attr "type" "delayed_compare")
10091 (set_attr "length" "12,16")])
10094 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10095 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
10096 [(match_operand 2 "cc_reg_operand" "")
10099 (set (match_operand:SI 3 "gpc_reg_operand" "")
10100 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
10101 "! TARGET_POWERPC64 && reload_completed"
10102 [(set (match_dup 3)
10103 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
10105 (compare:CC (match_dup 3)
10110 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10111 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10112 [(match_operand 2 "cc_reg_operand" "y")
10114 (match_operand:SI 3 "const_int_operand" "n")))]
10118 int is_bit = ccr_bit (operands[1], 1);
10119 int put_bit = 31 - (INTVAL (operands[3]) & 31);
10122 if (is_bit >= put_bit)
10123 count = is_bit - put_bit;
10125 count = 32 - (put_bit - is_bit);
10127 operands[4] = GEN_INT (count);
10128 operands[5] = GEN_INT (put_bit);
10130 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
10132 [(set_attr "length" "12")])
10135 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10137 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10138 [(match_operand 2 "cc_reg_operand" "y,y")
10140 (match_operand:SI 3 "const_int_operand" "n,n"))
10142 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
10143 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10145 "! TARGET_POWERPC64"
10148 int is_bit = ccr_bit (operands[1], 1);
10149 int put_bit = 31 - (INTVAL (operands[3]) & 31);
10152 /* Force split for non-cc0 compare. */
10153 if (which_alternative == 1)
10156 if (is_bit >= put_bit)
10157 count = is_bit - put_bit;
10159 count = 32 - (put_bit - is_bit);
10161 operands[5] = GEN_INT (count);
10162 operands[6] = GEN_INT (put_bit);
10164 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
10166 [(set_attr "type" "delayed_compare")
10167 (set_attr "length" "12,16")])
10170 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10172 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
10173 [(match_operand 2 "cc_reg_operand" "")
10175 (match_operand:SI 3 "const_int_operand" ""))
10177 (set (match_operand:SI 4 "gpc_reg_operand" "")
10178 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10180 "! TARGET_POWERPC64 && reload_completed"
10181 [(set (match_dup 4)
10182 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
10185 (compare:CC (match_dup 4)
10189 ;; There is a 3 cycle delay between consecutive mfcr instructions
10190 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
10193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10194 (match_operator:SI 1 "scc_comparison_operator"
10195 [(match_operand 2 "cc_reg_operand" "y")
10197 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
10198 (match_operator:SI 4 "scc_comparison_operator"
10199 [(match_operand 5 "cc_reg_operand" "y")
10201 "REGNO (operands[2]) != REGNO (operands[5])"
10202 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
10203 [(set_attr "length" "20")])
10206 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10207 (match_operator:DI 1 "scc_comparison_operator"
10208 [(match_operand 2 "cc_reg_operand" "y")
10210 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
10211 (match_operator:DI 4 "scc_comparison_operator"
10212 [(match_operand 5 "cc_reg_operand" "y")
10214 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
10215 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
10216 [(set_attr "length" "20")])
10218 ;; There are some scc insns that can be done directly, without a compare.
10219 ;; These are faster because they don't involve the communications between
10220 ;; the FXU and branch units. In fact, we will be replacing all of the
10221 ;; integer scc insns here or in the portable methods in emit_store_flag.
10223 ;; Also support (neg (scc ..)) since that construct is used to replace
10224 ;; branches, (plus (scc ..) ..) since that construct is common and
10225 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
10226 ;; cases where it is no more expensive than (neg (scc ..)).
10228 ;; Have reload force a constant into a register for the simple insns that
10229 ;; otherwise won't accept constants. We do this because it is faster than
10230 ;; the cmp/mfcr sequence we would otherwise generate.
10233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10234 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10235 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
10236 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
10237 "! TARGET_POWERPC64"
10239 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10240 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
10241 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10242 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
10243 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
10244 [(set_attr "length" "12,8,12,12,12")])
10247 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
10248 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
10249 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
10250 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
10253 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
10254 subfic %3,%1,0\;adde %0,%3,%1
10255 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
10256 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
10257 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
10258 [(set_attr "length" "12,8,12,12,12")])
10261 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10263 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10264 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10266 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10267 (eq:SI (match_dup 1) (match_dup 2)))
10268 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
10269 "! TARGET_POWERPC64"
10271 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10272 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
10273 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10274 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10275 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
10281 [(set_attr "type" "compare")
10282 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10285 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10287 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10288 (match_operand:SI 2 "reg_or_cint_operand" ""))
10290 (set (match_operand:SI 0 "gpc_reg_operand" "")
10291 (eq:SI (match_dup 1) (match_dup 2)))
10292 (clobber (match_scratch:SI 3 ""))]
10293 "! TARGET_POWERPC64 && reload_completed"
10294 [(parallel [(set (match_dup 0)
10295 (eq:SI (match_dup 1) (match_dup 2)))
10296 (clobber (match_dup 3))])
10298 (compare:CC (match_dup 0)
10303 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10305 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10306 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
10308 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10309 (eq:DI (match_dup 1) (match_dup 2)))
10310 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
10313 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
10314 subfic %3,%1,0\;adde. %0,%3,%1
10315 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
10316 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
10317 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
10323 [(set_attr "type" "compare")
10324 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10327 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10329 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
10330 (match_operand:DI 2 "reg_or_cint_operand" ""))
10332 (set (match_operand:DI 0 "gpc_reg_operand" "")
10333 (eq:DI (match_dup 1) (match_dup 2)))
10334 (clobber (match_scratch:DI 3 ""))]
10335 "TARGET_POWERPC64 && reload_completed"
10336 [(parallel [(set (match_dup 0)
10337 (eq:DI (match_dup 1) (match_dup 2)))
10338 (clobber (match_dup 3))])
10340 (compare:CC (match_dup 0)
10344 ;; We have insns of the form shown by the first define_insn below. If
10345 ;; there is something inside the comparison operation, we must split it.
10347 [(set (match_operand:SI 0 "gpc_reg_operand" "")
10348 (plus:SI (match_operator 1 "comparison_operator"
10349 [(match_operand:SI 2 "" "")
10350 (match_operand:SI 3
10351 "reg_or_cint_operand" "")])
10352 (match_operand:SI 4 "gpc_reg_operand" "")))
10353 (clobber (match_operand:SI 5 "register_operand" ""))]
10354 "! gpc_reg_operand (operands[2], SImode)"
10355 [(set (match_dup 5) (match_dup 2))
10356 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
10360 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10361 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10362 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
10363 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
10364 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
10365 "! TARGET_POWERPC64"
10367 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10368 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
10369 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10370 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10371 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
10372 [(set_attr "length" "12,8,12,12,12")])
10375 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10378 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10379 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10380 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
10382 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
10383 "! TARGET_POWERPC64"
10385 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10386 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
10387 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10388 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10389 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10395 [(set_attr "type" "compare")
10396 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10399 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10402 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10403 (match_operand:SI 2 "reg_or_cint_operand" ""))
10404 (match_operand:SI 3 "gpc_reg_operand" ""))
10406 (clobber (match_scratch:SI 4 ""))]
10407 "! TARGET_POWERPC64 && reload_completed"
10408 [(set (match_dup 4)
10409 (plus:SI (eq:SI (match_dup 1)
10413 (compare:CC (match_dup 4)
10418 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
10421 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
10422 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
10423 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
10425 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
10426 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10427 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
10428 "! TARGET_POWERPC64"
10430 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10431 {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3
10432 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10433 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10434 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10440 [(set_attr "type" "compare")
10441 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
10444 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10447 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
10448 (match_operand:SI 2 "reg_or_cint_operand" ""))
10449 (match_operand:SI 3 "gpc_reg_operand" ""))
10451 (set (match_operand:SI 0 "gpc_reg_operand" "")
10452 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10453 (clobber (match_scratch:SI 4 ""))]
10454 "! TARGET_POWERPC64 && reload_completed"
10455 [(parallel [(set (match_dup 0)
10456 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10457 (clobber (match_dup 4))])
10459 (compare:CC (match_dup 0)
10464 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
10465 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
10466 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
10467 "! TARGET_POWERPC64"
10469 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10470 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
10471 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10472 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10473 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
10474 [(set_attr "length" "12,8,12,12,12")])
10476 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
10477 ;; since it nabs/sr is just as fast.
10478 (define_insn "*ne0"
10479 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
10480 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
10482 (clobber (match_scratch:SI 2 "=&r"))]
10483 "! TARGET_POWER && ! TARGET_POWERPC64"
10484 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
10485 [(set_attr "length" "8")])
10488 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10489 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
10491 (clobber (match_scratch:DI 2 "=&r"))]
10493 "addic %2,%1,-1\;subfe %0,%2,%1"
10494 [(set_attr "length" "8")])
10496 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
10498 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10499 (plus:SI (lshiftrt:SI
10500 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
10502 (match_operand:SI 2 "gpc_reg_operand" "r")))
10503 (clobber (match_scratch:SI 3 "=&r"))]
10504 "! TARGET_POWERPC64"
10505 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
10506 [(set_attr "length" "8")])
10509 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10510 (plus:DI (lshiftrt:DI
10511 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
10513 (match_operand:DI 2 "gpc_reg_operand" "r")))
10514 (clobber (match_scratch:DI 3 "=&r"))]
10516 "addic %3,%1,-1\;addze %0,%2"
10517 [(set_attr "length" "8")])
10520 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10522 (plus:SI (lshiftrt:SI
10523 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
10525 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
10527 (clobber (match_scratch:SI 3 "=&r,&r"))]
10528 "! TARGET_POWERPC64"
10530 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
10532 [(set_attr "type" "compare")
10533 (set_attr "length" "8,12")])
10536 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10538 (plus:SI (lshiftrt:SI
10539 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10541 (match_operand:SI 2 "gpc_reg_operand" ""))
10543 (clobber (match_scratch:SI 3 ""))]
10544 "! TARGET_POWERPC64 && reload_completed"
10545 [(set (match_dup 3)
10546 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
10550 (compare:CC (match_dup 3)
10555 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10557 (plus:DI (lshiftrt:DI
10558 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
10560 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
10562 (clobber (match_scratch:DI 3 "=&r,&r"))]
10565 addic %3,%1,-1\;addze. %3,%2
10567 [(set_attr "type" "compare")
10568 (set_attr "length" "8,12")])
10571 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10573 (plus:DI (lshiftrt:DI
10574 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10576 (match_operand:DI 2 "gpc_reg_operand" ""))
10578 (clobber (match_scratch:DI 3 ""))]
10579 "TARGET_POWERPC64 && reload_completed"
10580 [(set (match_dup 3)
10581 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
10585 (compare:CC (match_dup 3)
10590 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
10592 (plus:SI (lshiftrt:SI
10593 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
10595 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
10597 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10598 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10600 (clobber (match_scratch:SI 3 "=&r,&r"))]
10601 "! TARGET_POWERPC64"
10603 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
10605 [(set_attr "type" "compare")
10606 (set_attr "length" "8,12")])
10609 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10611 (plus:SI (lshiftrt:SI
10612 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10614 (match_operand:SI 2 "gpc_reg_operand" ""))
10616 (set (match_operand:SI 0 "gpc_reg_operand" "")
10617 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10619 (clobber (match_scratch:SI 3 ""))]
10620 "! TARGET_POWERPC64 && reload_completed"
10621 [(parallel [(set (match_dup 0)
10622 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
10624 (clobber (match_dup 3))])
10626 (compare:CC (match_dup 0)
10631 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
10633 (plus:DI (lshiftrt:DI
10634 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
10636 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
10638 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10639 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10641 (clobber (match_scratch:DI 3 "=&r,&r"))]
10644 addic %3,%1,-1\;addze. %0,%2
10646 [(set_attr "type" "compare")
10647 (set_attr "length" "8,12")])
10650 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10652 (plus:DI (lshiftrt:DI
10653 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10655 (match_operand:DI 2 "gpc_reg_operand" ""))
10657 (set (match_operand:DI 0 "gpc_reg_operand" "")
10658 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10660 (clobber (match_scratch:DI 3 ""))]
10661 "TARGET_POWERPC64 && reload_completed"
10662 [(parallel [(set (match_dup 0)
10663 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
10665 (clobber (match_dup 3))])
10667 (compare:CC (match_dup 0)
10672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10673 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10674 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
10675 (clobber (match_scratch:SI 3 "=r,X"))]
10678 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
10679 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
10680 [(set_attr "length" "12")])
10683 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
10685 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10686 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10688 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
10689 (le:SI (match_dup 1) (match_dup 2)))
10690 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
10693 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
10694 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
10697 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
10698 (set_attr "length" "12,12,16,16")])
10701 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
10703 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10704 (match_operand:SI 2 "reg_or_short_operand" ""))
10706 (set (match_operand:SI 0 "gpc_reg_operand" "")
10707 (le:SI (match_dup 1) (match_dup 2)))
10708 (clobber (match_scratch:SI 3 ""))]
10709 "TARGET_POWER && reload_completed"
10710 [(parallel [(set (match_dup 0)
10711 (le:SI (match_dup 1) (match_dup 2)))
10712 (clobber (match_dup 3))])
10714 (compare:CC (match_dup 0)
10719 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10720 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10721 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
10722 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
10723 (clobber (match_scratch:SI 4 "=&r,&r"))]
10726 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
10727 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
10728 [(set_attr "length" "12")])
10731 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
10733 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10734 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10735 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
10737 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
10740 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
10741 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
10744 [(set_attr "type" "compare")
10745 (set_attr "length" "12,12,16,16")])
10748 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10750 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10751 (match_operand:SI 2 "reg_or_short_operand" ""))
10752 (match_operand:SI 3 "gpc_reg_operand" ""))
10754 (clobber (match_scratch:SI 4 ""))]
10755 "TARGET_POWER && reload_completed"
10756 [(set (match_dup 4)
10757 (plus:SI (le:SI (match_dup 1) (match_dup 2))
10760 (compare:CC (match_dup 4)
10765 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
10767 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
10768 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
10769 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
10771 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
10772 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10773 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
10776 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
10777 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3
10780 [(set_attr "type" "compare")
10781 (set_attr "length" "12,12,16,16")])
10784 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10786 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
10787 (match_operand:SI 2 "reg_or_short_operand" ""))
10788 (match_operand:SI 3 "gpc_reg_operand" ""))
10790 (set (match_operand:SI 0 "gpc_reg_operand" "")
10791 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10792 (clobber (match_scratch:SI 4 ""))]
10793 "TARGET_POWER && reload_completed"
10794 [(parallel [(set (match_dup 0)
10795 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10796 (clobber (match_dup 4))])
10798 (compare:CC (match_dup 0)
10803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10804 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10805 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
10808 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
10809 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
10810 [(set_attr "length" "12")])
10813 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10814 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10815 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
10816 "! TARGET_POWERPC64"
10817 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
10818 [(set_attr "length" "12")])
10821 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10822 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
10823 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
10825 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
10826 [(set_attr "length" "12")])
10829 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10831 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10832 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
10834 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10835 (leu:DI (match_dup 1) (match_dup 2)))]
10838 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
10840 [(set_attr "type" "compare")
10841 (set_attr "length" "12,16")])
10844 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
10846 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
10847 (match_operand:DI 2 "reg_or_short_operand" ""))
10849 (set (match_operand:DI 0 "gpc_reg_operand" "")
10850 (leu:DI (match_dup 1) (match_dup 2)))]
10851 "TARGET_POWERPC64 && reload_completed"
10852 [(set (match_dup 0)
10853 (leu:DI (match_dup 1) (match_dup 2)))
10855 (compare:CC (match_dup 0)
10860 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10862 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10863 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
10865 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10866 (leu:SI (match_dup 1) (match_dup 2)))]
10867 "! TARGET_POWERPC64"
10869 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
10871 [(set_attr "type" "compare")
10872 (set_attr "length" "12,16")])
10875 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
10877 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10878 (match_operand:SI 2 "reg_or_short_operand" ""))
10880 (set (match_operand:SI 0 "gpc_reg_operand" "")
10881 (leu:SI (match_dup 1) (match_dup 2)))]
10882 "! TARGET_POWERPC64 && reload_completed"
10883 [(set (match_dup 0)
10884 (leu:SI (match_dup 1) (match_dup 2)))
10886 (compare:CC (match_dup 0)
10891 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
10893 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
10894 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
10896 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10897 (leu:DI (match_dup 1) (match_dup 2)))]
10900 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
10902 [(set_attr "type" "compare")
10903 (set_attr "length" "12,16")])
10906 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10907 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10908 (match_operand:SI 2 "reg_or_short_operand" "rI"))
10909 (match_operand:SI 3 "gpc_reg_operand" "r")))
10910 (clobber (match_scratch:SI 4 "=&r"))]
10911 "! TARGET_POWERPC64"
10912 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
10913 [(set_attr "length" "8")])
10916 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
10918 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10919 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
10920 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10922 (clobber (match_scratch:SI 4 "=&r,&r"))]
10923 "! TARGET_POWERPC64"
10925 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
10927 [(set_attr "type" "compare")
10928 (set_attr "length" "8,12")])
10931 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
10933 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10934 (match_operand:SI 2 "reg_or_short_operand" ""))
10935 (match_operand:SI 3 "gpc_reg_operand" ""))
10937 (clobber (match_scratch:SI 4 ""))]
10938 "! TARGET_POWERPC64 && reload_completed"
10939 [(set (match_dup 4)
10940 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
10943 (compare:CC (match_dup 4)
10948 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
10950 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
10951 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
10952 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10954 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10955 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10956 (clobber (match_scratch:SI 4 "=&r,&r"))]
10957 "! TARGET_POWERPC64"
10959 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3
10961 [(set_attr "type" "compare")
10962 (set_attr "length" "8,12")])
10965 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
10967 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
10968 (match_operand:SI 2 "reg_or_short_operand" ""))
10969 (match_operand:SI 3 "gpc_reg_operand" ""))
10971 (set (match_operand:SI 0 "gpc_reg_operand" "")
10972 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10973 (clobber (match_scratch:SI 4 ""))]
10974 "! TARGET_POWERPC64 && reload_completed"
10975 [(parallel [(set (match_dup 0)
10976 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
10977 (clobber (match_dup 4))])
10979 (compare:CC (match_dup 0)
10984 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10985 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10986 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
10987 "! TARGET_POWERPC64"
10988 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
10989 [(set_attr "length" "12")])
10992 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10994 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
10995 (match_operand:SI 2 "reg_or_short_operand" "rI")))
10996 (match_operand:SI 3 "gpc_reg_operand" "r")))
10997 (clobber (match_scratch:SI 4 "=&r"))]
10998 "! TARGET_POWERPC64"
10999 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
11000 [(set_attr "length" "12")])
11003 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11006 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11007 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11008 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11010 (clobber (match_scratch:SI 4 "=&r,&r"))]
11011 "! TARGET_POWERPC64"
11013 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11015 [(set_attr "type" "compare")
11016 (set_attr "length" "12,16")])
11019 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11022 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11023 (match_operand:SI 2 "reg_or_short_operand" "")))
11024 (match_operand:SI 3 "gpc_reg_operand" ""))
11026 (clobber (match_scratch:SI 4 ""))]
11027 "! TARGET_POWERPC64 && reload_completed"
11028 [(set (match_dup 4)
11029 (and:SI (neg:SI (leu:SI (match_dup 1)
11033 (compare:CC (match_dup 4)
11038 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11041 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11042 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11043 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11045 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11046 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11047 (clobber (match_scratch:SI 4 "=&r,&r"))]
11048 "! TARGET_POWERPC64"
11050 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11052 [(set_attr "type" "compare")
11053 (set_attr "length" "12,16")])
11056 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11059 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11060 (match_operand:SI 2 "reg_or_short_operand" "")))
11061 (match_operand:SI 3 "gpc_reg_operand" ""))
11063 (set (match_operand:SI 0 "gpc_reg_operand" "")
11064 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11065 (clobber (match_scratch:SI 4 ""))]
11066 "! TARGET_POWERPC64 && reload_completed"
11067 [(parallel [(set (match_dup 0)
11068 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11069 (clobber (match_dup 4))])
11071 (compare:CC (match_dup 0)
11076 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11077 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11078 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11080 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11081 [(set_attr "length" "12")])
11084 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11086 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11087 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11089 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11090 (lt:SI (match_dup 1) (match_dup 2)))]
11093 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11095 [(set_attr "type" "delayed_compare")
11096 (set_attr "length" "12,16")])
11099 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11101 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11102 (match_operand:SI 2 "reg_or_short_operand" ""))
11104 (set (match_operand:SI 0 "gpc_reg_operand" "")
11105 (lt:SI (match_dup 1) (match_dup 2)))]
11106 "TARGET_POWER && reload_completed"
11107 [(set (match_dup 0)
11108 (lt:SI (match_dup 1) (match_dup 2)))
11110 (compare:CC (match_dup 0)
11115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11116 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11117 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11118 (match_operand:SI 3 "gpc_reg_operand" "r")))
11119 (clobber (match_scratch:SI 4 "=&r"))]
11121 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
11122 [(set_attr "length" "12")])
11125 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11127 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11128 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11129 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11131 (clobber (match_scratch:SI 4 "=&r,&r"))]
11134 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11136 [(set_attr "type" "compare")
11137 (set_attr "length" "12,16")])
11140 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11142 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11143 (match_operand:SI 2 "reg_or_short_operand" ""))
11144 (match_operand:SI 3 "gpc_reg_operand" ""))
11146 (clobber (match_scratch:SI 4 ""))]
11147 "TARGET_POWER && reload_completed"
11148 [(set (match_dup 4)
11149 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
11152 (compare:CC (match_dup 4)
11157 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11159 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11160 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11161 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11163 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11164 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11165 (clobber (match_scratch:SI 4 "=&r,&r"))]
11168 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
11170 [(set_attr "type" "compare")
11171 (set_attr "length" "12,16")])
11174 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11176 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11177 (match_operand:SI 2 "reg_or_short_operand" ""))
11178 (match_operand:SI 3 "gpc_reg_operand" ""))
11180 (set (match_operand:SI 0 "gpc_reg_operand" "")
11181 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11182 (clobber (match_scratch:SI 4 ""))]
11183 "TARGET_POWER && reload_completed"
11184 [(parallel [(set (match_dup 0)
11185 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11186 (clobber (match_dup 4))])
11188 (compare:CC (match_dup 0)
11193 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11194 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11195 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11197 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
11198 [(set_attr "length" "12")])
11201 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11202 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11203 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11204 "! TARGET_POWERPC64"
11206 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
11207 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
11208 [(set_attr "length" "12")])
11211 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11213 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11214 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11216 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11217 (ltu:SI (match_dup 1) (match_dup 2)))]
11218 "! TARGET_POWERPC64"
11220 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11221 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11224 [(set_attr "type" "compare")
11225 (set_attr "length" "12,12,16,16")])
11228 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11230 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11231 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11233 (set (match_operand:SI 0 "gpc_reg_operand" "")
11234 (ltu:SI (match_dup 1) (match_dup 2)))]
11235 "! TARGET_POWERPC64 && reload_completed"
11236 [(set (match_dup 0)
11237 (ltu:SI (match_dup 1) (match_dup 2)))
11239 (compare:CC (match_dup 0)
11244 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11245 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11246 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
11247 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))
11248 (clobber (match_scratch:SI 4 "=&r,&r"))]
11249 "! TARGET_POWERPC64"
11251 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
11252 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
11253 [(set_attr "length" "12")])
11256 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11258 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11259 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11260 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11262 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11263 "! TARGET_POWERPC64"
11265 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
11266 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
11269 [(set_attr "type" "compare")
11270 (set_attr "length" "12,12,16,16")])
11273 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11275 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11276 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11277 (match_operand:SI 3 "gpc_reg_operand" ""))
11279 (clobber (match_scratch:SI 4 ""))]
11280 "! TARGET_POWERPC64 && reload_completed"
11281 [(set (match_dup 4)
11282 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
11285 (compare:CC (match_dup 4)
11290 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11292 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11293 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11294 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11296 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11297 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11298 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11299 "! TARGET_POWERPC64"
11301 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
11302 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
11305 [(set_attr "type" "compare")
11306 (set_attr "length" "12,12,16,16")])
11309 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11311 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11312 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11313 (match_operand:SI 3 "gpc_reg_operand" ""))
11315 (set (match_operand:SI 0 "gpc_reg_operand" "")
11316 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11317 (clobber (match_scratch:SI 4 ""))]
11318 "! TARGET_POWERPC64 && reload_completed"
11319 [(parallel [(set (match_dup 0)
11320 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11321 (clobber (match_dup 4))])
11323 (compare:CC (match_dup 0)
11328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11329 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11330 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
11331 "! TARGET_POWERPC64"
11333 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
11334 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
11335 [(set_attr "length" "8")])
11338 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11339 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11340 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11341 (clobber (match_scratch:SI 3 "=r"))]
11343 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
11344 [(set_attr "length" "12")])
11347 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11349 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11350 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11352 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11353 (ge:SI (match_dup 1) (match_dup 2)))
11354 (clobber (match_scratch:SI 3 "=r,r"))]
11357 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11359 [(set_attr "type" "compare")
11360 (set_attr "length" "12,16")])
11363 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11365 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11366 (match_operand:SI 2 "reg_or_short_operand" ""))
11368 (set (match_operand:SI 0 "gpc_reg_operand" "")
11369 (ge:SI (match_dup 1) (match_dup 2)))
11370 (clobber (match_scratch:SI 3 ""))]
11371 "TARGET_POWER && reload_completed"
11372 [(parallel [(set (match_dup 0)
11373 (ge:SI (match_dup 1) (match_dup 2)))
11374 (clobber (match_dup 3))])
11376 (compare:CC (match_dup 0)
11381 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11382 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11383 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11384 (match_operand:SI 3 "gpc_reg_operand" "r")))
11385 (clobber (match_scratch:SI 4 "=&r"))]
11387 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
11388 [(set_attr "length" "12")])
11391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11393 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11394 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11395 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11397 (clobber (match_scratch:SI 4 "=&r,&r"))]
11400 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11402 [(set_attr "type" "compare")
11403 (set_attr "length" "12,16")])
11406 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11408 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11409 (match_operand:SI 2 "reg_or_short_operand" ""))
11410 (match_operand:SI 3 "gpc_reg_operand" ""))
11412 (clobber (match_scratch:SI 4 ""))]
11413 "TARGET_POWER && reload_completed"
11414 [(set (match_dup 4)
11415 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
11418 (compare:CC (match_dup 4)
11423 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11425 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11426 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11427 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11429 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11430 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11431 (clobber (match_scratch:SI 4 "=&r,&r"))]
11434 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11436 [(set_attr "type" "compare")
11437 (set_attr "length" "12,16")])
11440 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11442 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
11443 (match_operand:SI 2 "reg_or_short_operand" ""))
11444 (match_operand:SI 3 "gpc_reg_operand" ""))
11446 (set (match_operand:SI 0 "gpc_reg_operand" "")
11447 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11448 (clobber (match_scratch:SI 4 ""))]
11449 "TARGET_POWER && reload_completed"
11450 [(parallel [(set (match_dup 0)
11451 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11452 (clobber (match_dup 4))])
11454 (compare:CC (match_dup 0)
11459 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11460 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11461 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11463 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11464 [(set_attr "length" "12")])
11467 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11468 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11469 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11470 "! TARGET_POWERPC64"
11472 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
11473 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11474 [(set_attr "length" "12")])
11477 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11478 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11479 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
11482 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
11483 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
11484 [(set_attr "length" "12")])
11487 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11489 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11490 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11492 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11493 (geu:SI (match_dup 1) (match_dup 2)))]
11494 "! TARGET_POWERPC64"
11496 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11497 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11500 [(set_attr "type" "compare")
11501 (set_attr "length" "12,12,16,16")])
11504 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11506 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11507 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11509 (set (match_operand:SI 0 "gpc_reg_operand" "")
11510 (geu:SI (match_dup 1) (match_dup 2)))]
11511 "! TARGET_POWERPC64 && reload_completed"
11512 [(set (match_dup 0)
11513 (geu:SI (match_dup 1) (match_dup 2)))
11515 (compare:CC (match_dup 0)
11520 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11522 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
11523 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11525 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
11526 (geu:DI (match_dup 1) (match_dup 2)))]
11529 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
11530 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
11533 [(set_attr "type" "compare")
11534 (set_attr "length" "12,12,16,16")])
11537 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11539 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
11540 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
11542 (set (match_operand:DI 0 "gpc_reg_operand" "")
11543 (geu:DI (match_dup 1) (match_dup 2)))]
11544 "TARGET_POWERPC64 && reload_completed"
11545 [(set (match_dup 0)
11546 (geu:DI (match_dup 1) (match_dup 2)))
11548 (compare:CC (match_dup 0)
11553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11554 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11555 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
11556 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
11557 (clobber (match_scratch:SI 4 "=&r,&r"))]
11558 "! TARGET_POWERPC64"
11560 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
11561 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
11562 [(set_attr "length" "8")])
11565 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11567 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11568 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11569 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11571 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11572 "! TARGET_POWERPC64"
11574 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
11575 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
11578 [(set_attr "type" "compare")
11579 (set_attr "length" "8,8,12,12")])
11582 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11584 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11585 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11586 (match_operand:SI 3 "gpc_reg_operand" ""))
11588 (clobber (match_scratch:SI 4 ""))]
11589 "! TARGET_POWERPC64 && reload_completed"
11590 [(set (match_dup 4)
11591 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
11594 (compare:CC (match_dup 4)
11599 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11601 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11602 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11603 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11605 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11606 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11607 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11608 "! TARGET_POWERPC64"
11610 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
11611 {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3
11614 [(set_attr "type" "compare")
11615 (set_attr "length" "8,8,12,12")])
11618 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11620 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11621 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
11622 (match_operand:SI 3 "gpc_reg_operand" ""))
11624 (set (match_operand:SI 0 "gpc_reg_operand" "")
11625 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11626 (clobber (match_scratch:SI 4 ""))]
11627 "! TARGET_POWERPC64 && reload_completed"
11628 [(parallel [(set (match_dup 0)
11629 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11630 (clobber (match_dup 4))])
11632 (compare:CC (match_dup 0)
11637 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11638 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11639 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
11640 "! TARGET_POWERPC64"
11642 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
11643 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
11644 [(set_attr "length" "12")])
11647 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11649 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11650 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
11651 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
11652 (clobber (match_scratch:SI 4 "=&r,&r"))]
11653 "! TARGET_POWERPC64"
11655 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
11656 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
11657 [(set_attr "length" "12")])
11660 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11663 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11664 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
11665 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11667 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11668 "! TARGET_POWERPC64"
11670 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11671 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11674 [(set_attr "type" "compare")
11675 (set_attr "length" "12,12,16,16")])
11678 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11681 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11682 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
11683 (match_operand:SI 3 "gpc_reg_operand" ""))
11685 (clobber (match_scratch:SI 4 ""))]
11686 "! TARGET_POWERPC64 && reload_completed"
11687 [(set (match_dup 4)
11688 (and:SI (neg:SI (geu:SI (match_dup 1)
11692 (compare:CC (match_dup 4)
11697 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11700 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11701 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
11702 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11704 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11705 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11706 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11707 "! TARGET_POWERPC64"
11709 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11710 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11713 [(set_attr "type" "compare")
11714 (set_attr "length" "12,12,16,16")])
11717 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
11720 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
11721 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
11722 (match_operand:SI 3 "gpc_reg_operand" ""))
11724 (set (match_operand:SI 0 "gpc_reg_operand" "")
11725 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11726 (clobber (match_scratch:SI 4 ""))]
11727 "! TARGET_POWERPC64 && reload_completed"
11728 [(parallel [(set (match_dup 0)
11729 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11730 (clobber (match_dup 4))])
11732 (compare:CC (match_dup 0)
11737 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11738 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11740 "! TARGET_POWERPC64"
11741 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
11742 [(set_attr "length" "12")])
11745 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11746 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11749 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
11750 [(set_attr "length" "12")])
11753 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
11755 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11758 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11759 (gt:SI (match_dup 1) (const_int 0)))]
11760 "! TARGET_POWERPC64"
11762 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
11764 [(set_attr "type" "delayed_compare")
11765 (set_attr "length" "12,16")])
11768 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
11770 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11773 (set (match_operand:SI 0 "gpc_reg_operand" "")
11774 (gt:SI (match_dup 1) (const_int 0)))]
11775 "! TARGET_POWERPC64 && reload_completed"
11776 [(set (match_dup 0)
11777 (gt:SI (match_dup 1) (const_int 0)))
11779 (compare:CC (match_dup 0)
11784 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
11786 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11789 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11790 (gt:DI (match_dup 1) (const_int 0)))]
11793 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
11795 [(set_attr "type" "delayed_compare")
11796 (set_attr "length" "12,16")])
11799 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
11801 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
11804 (set (match_operand:DI 0 "gpc_reg_operand" "")
11805 (gt:DI (match_dup 1) (const_int 0)))]
11806 "TARGET_POWERPC64 && reload_completed"
11807 [(set (match_dup 0)
11808 (gt:DI (match_dup 1) (const_int 0)))
11810 (compare:CC (match_dup 0)
11815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11816 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11817 (match_operand:SI 2 "reg_or_short_operand" "r")))]
11819 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11820 [(set_attr "length" "12")])
11823 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11825 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11826 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
11828 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11829 (gt:SI (match_dup 1) (match_dup 2)))]
11832 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11834 [(set_attr "type" "delayed_compare")
11835 (set_attr "length" "12,16")])
11838 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
11840 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11841 (match_operand:SI 2 "reg_or_short_operand" ""))
11843 (set (match_operand:SI 0 "gpc_reg_operand" "")
11844 (gt:SI (match_dup 1) (match_dup 2)))]
11845 "TARGET_POWER && reload_completed"
11846 [(set (match_dup 0)
11847 (gt:SI (match_dup 1) (match_dup 2)))
11849 (compare:CC (match_dup 0)
11854 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11855 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11857 (match_operand:SI 2 "gpc_reg_operand" "r")))
11858 (clobber (match_scratch:SI 3 "=&r"))]
11859 "! TARGET_POWERPC64"
11860 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
11861 [(set_attr "length" "12")])
11864 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11865 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
11867 (match_operand:DI 2 "gpc_reg_operand" "r")))
11868 (clobber (match_scratch:DI 3 "=&r"))]
11870 "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2"
11871 [(set_attr "length" "12")])
11874 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11876 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11878 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11880 (clobber (match_scratch:SI 3 "=&r,&r"))]
11881 "! TARGET_POWERPC64"
11883 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
11885 [(set_attr "type" "compare")
11886 (set_attr "length" "12,16")])
11889 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11891 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11893 (match_operand:SI 2 "gpc_reg_operand" ""))
11895 (clobber (match_scratch:SI 3 ""))]
11896 "! TARGET_POWERPC64 && reload_completed"
11897 [(set (match_dup 3)
11898 (plus:SI (gt:SI (match_dup 1) (const_int 0))
11901 (compare:CC (match_dup 3)
11906 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11908 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11910 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11912 (clobber (match_scratch:DI 3 "=&r,&r"))]
11915 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
11917 [(set_attr "type" "compare")
11918 (set_attr "length" "12,16")])
11921 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11923 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
11925 (match_operand:DI 2 "gpc_reg_operand" ""))
11927 (clobber (match_scratch:DI 3 ""))]
11928 "TARGET_POWERPC64 && reload_completed"
11929 [(set (match_dup 3)
11930 (plus:DI (gt:DI (match_dup 1) (const_int 0))
11933 (compare:CC (match_dup 3)
11938 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11940 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11942 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11944 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11945 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
11946 (clobber (match_scratch:SI 3 "=&r,&r"))]
11947 "! TARGET_POWERPC64"
11949 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2
11951 [(set_attr "type" "compare")
11952 (set_attr "length" "12,16")])
11955 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11957 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
11959 (match_operand:SI 2 "gpc_reg_operand" ""))
11961 (set (match_operand:SI 0 "gpc_reg_operand" "")
11962 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
11963 (clobber (match_scratch:SI 3 ""))]
11964 "! TARGET_POWERPC64 && reload_completed"
11965 [(parallel [(set (match_dup 0)
11966 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
11967 (clobber (match_dup 3))])
11969 (compare:CC (match_dup 0)
11974 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11976 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
11978 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11980 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11981 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
11982 (clobber (match_scratch:DI 3 "=&r,&r"))]
11985 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2
11987 [(set_attr "type" "compare")
11988 (set_attr "length" "12,16")])
11991 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11993 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
11995 (match_operand:DI 2 "gpc_reg_operand" ""))
11997 (set (match_operand:DI 0 "gpc_reg_operand" "")
11998 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
11999 (clobber (match_scratch:DI 3 ""))]
12000 "TARGET_POWERPC64 && reload_completed"
12001 [(parallel [(set (match_dup 0)
12002 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
12003 (clobber (match_dup 3))])
12005 (compare:CC (match_dup 0)
12010 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12011 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12012 (match_operand:SI 2 "reg_or_short_operand" "r"))
12013 (match_operand:SI 3 "gpc_reg_operand" "r")))
12014 (clobber (match_scratch:SI 4 "=&r"))]
12016 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
12017 [(set_attr "length" "12")])
12020 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12022 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12023 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12024 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12026 (clobber (match_scratch:SI 4 "=&r,&r"))]
12029 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12031 [(set_attr "type" "compare")
12032 (set_attr "length" "12,16")])
12035 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12037 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12038 (match_operand:SI 2 "reg_or_short_operand" ""))
12039 (match_operand:SI 3 "gpc_reg_operand" ""))
12041 (clobber (match_scratch:SI 4 ""))]
12042 "TARGET_POWER && reload_completed"
12043 [(set (match_dup 4)
12044 (plus:SI (gt:SI (match_dup 1) (match_dup 2))
12047 (compare:CC (match_dup 4)
12052 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
12054 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12055 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12056 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12058 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12059 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12060 (clobber (match_scratch:SI 4 "=&r,&r"))]
12063 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
12065 [(set_attr "type" "compare")
12066 (set_attr "length" "12,16")])
12069 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12071 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12072 (match_operand:SI 2 "reg_or_short_operand" ""))
12073 (match_operand:SI 3 "gpc_reg_operand" ""))
12075 (set (match_operand:SI 0 "gpc_reg_operand" "")
12076 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12077 (clobber (match_scratch:SI 4 ""))]
12078 "TARGET_POWER && reload_completed"
12079 [(parallel [(set (match_dup 0)
12080 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12081 (clobber (match_dup 4))])
12083 (compare:CC (match_dup 0)
12088 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12089 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12091 "! TARGET_POWERPC64"
12092 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
12093 [(set_attr "length" "12")])
12096 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12097 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12100 "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63"
12101 [(set_attr "length" "12")])
12104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12105 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12106 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12108 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12109 [(set_attr "length" "12")])
12112 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12113 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12114 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12115 "! TARGET_POWERPC64"
12116 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12117 [(set_attr "length" "12")])
12120 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12121 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12122 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12124 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
12125 [(set_attr "length" "12")])
12128 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12130 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12131 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12133 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12134 (gtu:SI (match_dup 1) (match_dup 2)))]
12135 "! TARGET_POWERPC64"
12137 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12139 [(set_attr "type" "compare")
12140 (set_attr "length" "12,16")])
12143 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12145 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12146 (match_operand:SI 2 "reg_or_short_operand" ""))
12148 (set (match_operand:SI 0 "gpc_reg_operand" "")
12149 (gtu:SI (match_dup 1) (match_dup 2)))]
12150 "! TARGET_POWERPC64 && reload_completed"
12151 [(set (match_dup 0)
12152 (gtu:SI (match_dup 1) (match_dup 2)))
12154 (compare:CC (match_dup 0)
12159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12161 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12162 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12164 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12165 (gtu:DI (match_dup 1) (match_dup 2)))]
12168 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
12170 [(set_attr "type" "compare")
12171 (set_attr "length" "12,16")])
12174 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12176 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12177 (match_operand:DI 2 "reg_or_short_operand" ""))
12179 (set (match_operand:DI 0 "gpc_reg_operand" "")
12180 (gtu:DI (match_dup 1) (match_dup 2)))]
12181 "TARGET_POWERPC64 && reload_completed"
12182 [(set (match_dup 0)
12183 (gtu:DI (match_dup 1) (match_dup 2)))
12185 (compare:CC (match_dup 0)
12190 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12191 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12192 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
12193 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))
12194 (clobber (match_scratch:SI 4 "=&r,&r"))]
12195 "! TARGET_POWERPC64"
12197 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
12198 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
12199 [(set_attr "length" "8,12")])
12202 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12203 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12204 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
12205 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))
12206 (clobber (match_scratch:DI 4 "=&r,&r"))]
12209 addic %4,%1,%k2\;addze %0,%3
12210 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3"
12211 [(set_attr "length" "8,12")])
12214 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12216 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12217 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12218 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12220 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12221 "! TARGET_POWERPC64"
12223 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
12224 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12227 [(set_attr "type" "compare")
12228 (set_attr "length" "8,12,12,16")])
12231 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12233 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12234 (match_operand:SI 2 "reg_or_short_operand" ""))
12235 (match_operand:SI 3 "gpc_reg_operand" ""))
12237 (clobber (match_scratch:SI 4 ""))]
12238 "! TARGET_POWERPC64 && reload_completed"
12239 [(set (match_dup 4)
12240 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
12243 (compare:CC (match_dup 4)
12248 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12250 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12251 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
12252 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
12254 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
12257 addic %4,%1,%k2\;addze. %4,%3
12258 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
12261 [(set_attr "type" "compare")
12262 (set_attr "length" "8,12,12,16")])
12265 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12267 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12268 (match_operand:DI 2 "reg_or_short_operand" ""))
12269 (match_operand:DI 3 "gpc_reg_operand" ""))
12271 (clobber (match_scratch:DI 4 ""))]
12272 "TARGET_POWERPC64 && reload_completed"
12273 [(set (match_dup 4)
12274 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
12277 (compare:CC (match_dup 4)
12282 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12284 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12285 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12286 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12288 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12289 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12290 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12291 "! TARGET_POWERPC64"
12293 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
12294 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
12297 [(set_attr "type" "compare")
12298 (set_attr "length" "8,12,12,16")])
12301 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12303 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12304 (match_operand:SI 2 "reg_or_short_operand" ""))
12305 (match_operand:SI 3 "gpc_reg_operand" ""))
12307 (set (match_operand:SI 0 "gpc_reg_operand" "")
12308 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12309 (clobber (match_scratch:SI 4 ""))]
12310 "! TARGET_POWERPC64 && reload_completed"
12311 [(parallel [(set (match_dup 0)
12312 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12313 (clobber (match_dup 4))])
12315 (compare:CC (match_dup 0)
12320 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12322 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
12323 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
12324 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
12326 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
12327 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12328 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
12331 addic %4,%1,%k2\;addze. %0,%3
12332 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3
12335 [(set_attr "type" "compare")
12336 (set_attr "length" "8,12,12,16")])
12339 [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "")
12341 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12342 (match_operand:DI 2 "reg_or_short_operand" ""))
12343 (match_operand:DI 3 "gpc_reg_operand" ""))
12345 (set (match_operand:DI 0 "gpc_reg_operand" "")
12346 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12347 (clobber (match_scratch:DI 4 ""))]
12348 "TARGET_POWERPC64 && reload_completed"
12349 [(parallel [(set (match_dup 0)
12350 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
12351 (clobber (match_dup 4))])
12353 (compare:CC (match_dup 0)
12358 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12359 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12360 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12361 "! TARGET_POWERPC64"
12362 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12363 [(set_attr "length" "8")])
12366 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12367 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12368 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
12370 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
12371 [(set_attr "length" "8")])
12373 ;; Define both directions of branch and return. If we need a reload
12374 ;; register, we'd rather use CR0 since it is much easier to copy a
12375 ;; register CC value to there.
12379 (if_then_else (match_operator 1 "branch_comparison_operator"
12381 "cc_reg_operand" "x,?y")
12383 (label_ref (match_operand 0 "" ""))
12388 return output_cbranch (operands[1], \"%l0\", 0, insn);
12390 [(set_attr "type" "branch")])
12394 (if_then_else (match_operator 0 "branch_comparison_operator"
12396 "cc_reg_operand" "x,?y")
12403 return output_cbranch (operands[0], NULL, 0, insn);
12405 [(set_attr "type" "branch")
12406 (set_attr "length" "4")])
12410 (if_then_else (match_operator 1 "branch_comparison_operator"
12412 "cc_reg_operand" "x,?y")
12415 (label_ref (match_operand 0 "" ""))))]
12419 return output_cbranch (operands[1], \"%l0\", 1, insn);
12421 [(set_attr "type" "branch")])
12425 (if_then_else (match_operator 0 "branch_comparison_operator"
12427 "cc_reg_operand" "x,?y")
12434 return output_cbranch (operands[0], NULL, 1, insn);
12436 [(set_attr "type" "branch")
12437 (set_attr "length" "4")])
12439 ;; Logic on condition register values.
12441 ; This pattern matches things like
12442 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
12443 ; (eq:SI (reg:CCFP 68) (const_int 0)))
12445 ; which are generated by the branch logic.
12448 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12449 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
12450 [(match_operator:SI 2
12451 "branch_positive_comparison_operator"
12453 "cc_reg_operand" "y")
12455 (match_operator:SI 4
12456 "branch_positive_comparison_operator"
12458 "cc_reg_operand" "y")
12462 "cr%q1 %E0,%j2,%j4"
12463 [(set_attr "type" "cr_logical")])
12465 ; Why is the constant -1 here, but 1 in the previous pattern?
12466 ; Because ~1 has all but the low bit set.
12468 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12469 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
12470 [(not:SI (match_operator:SI 2
12471 "branch_positive_comparison_operator"
12473 "cc_reg_operand" "y")
12475 (match_operator:SI 4
12476 "branch_positive_comparison_operator"
12478 "cc_reg_operand" "y")
12482 "cr%q1 %E0,%j2,%j4"
12483 [(set_attr "type" "cr_logical")])
12486 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12487 (compare:CCEQ (match_operator:SI 1
12488 "branch_positive_comparison_operator"
12490 "cc_reg_operand" "y")
12494 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
12495 [(set_attr "type" "cr_logical")])
12497 ;; If we are comparing the result of two comparisons, this can be done
12498 ;; using creqv or crxor.
12500 (define_insn_and_split ""
12501 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
12502 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
12503 [(match_operand 2 "cc_reg_operand" "y")
12505 (match_operator 3 "branch_comparison_operator"
12506 [(match_operand 4 "cc_reg_operand" "y")
12511 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
12515 int positive_1, positive_2;
12517 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
12518 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
12521 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
12522 GET_CODE (operands[1])),
12524 operands[2], const0_rtx);
12525 else if (GET_MODE (operands[1]) != SImode)
12526 operands[1] = gen_rtx (GET_CODE (operands[1]),
12528 operands[2], const0_rtx);
12531 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
12532 GET_CODE (operands[3])),
12534 operands[4], const0_rtx);
12535 else if (GET_MODE (operands[3]) != SImode)
12536 operands[3] = gen_rtx (GET_CODE (operands[3]),
12538 operands[4], const0_rtx);
12540 if (positive_1 == positive_2)
12542 operands[1] = gen_rtx_NOT (SImode, operands[1]);
12543 operands[5] = constm1_rtx;
12547 operands[5] = const1_rtx;
12551 ;; Unconditional branch and return.
12553 (define_insn "jump"
12555 (label_ref (match_operand 0 "" "")))]
12558 [(set_attr "type" "branch")])
12560 (define_insn "return"
12564 [(set_attr "type" "jmpreg")])
12566 (define_expand "indirect_jump"
12567 [(set (pc) (match_operand 0 "register_operand" ""))]
12572 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
12574 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
12578 (define_insn "indirect_jumpsi"
12579 [(set (pc) (match_operand:SI 0 "register_operand" "cl"))]
12582 [(set_attr "type" "jmpreg")])
12584 (define_insn "indirect_jumpdi"
12585 [(set (pc) (match_operand:DI 0 "register_operand" "cl"))]
12588 [(set_attr "type" "jmpreg")])
12590 ;; Table jump for switch statements:
12591 (define_expand "tablejump"
12592 [(use (match_operand 0 "" ""))
12593 (use (label_ref (match_operand 1 "" "")))]
12598 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12600 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12604 (define_expand "tablejumpsi"
12605 [(set (match_dup 3)
12606 (plus:SI (match_operand:SI 0 "" "")
12608 (parallel [(set (pc) (match_dup 3))
12609 (use (label_ref (match_operand 1 "" "")))])]
12612 { operands[0] = force_reg (SImode, operands[0]);
12613 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
12614 operands[3] = gen_reg_rtx (SImode);
12617 (define_expand "tablejumpdi"
12618 [(set (match_dup 4)
12619 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
12621 (plus:DI (match_dup 4)
12623 (parallel [(set (pc) (match_dup 3))
12624 (use (label_ref (match_operand 1 "" "")))])]
12627 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
12628 operands[3] = gen_reg_rtx (DImode);
12629 operands[4] = gen_reg_rtx (DImode);
12634 (match_operand:SI 0 "register_operand" "cl"))
12635 (use (label_ref (match_operand 1 "" "")))]
12638 [(set_attr "type" "jmpreg")])
12642 (match_operand:DI 0 "register_operand" "cl"))
12643 (use (label_ref (match_operand 1 "" "")))]
12646 [(set_attr "type" "jmpreg")])
12651 "{cror 0,0,0|nop}")
12653 ;; Define the subtract-one-and-jump insns, starting with the template
12654 ;; so loop.c knows what to generate.
12656 (define_expand "doloop_end"
12657 [(use (match_operand 0 "" "")) ; loop pseudo
12658 (use (match_operand 1 "" "")) ; iterations; zero if unknown
12659 (use (match_operand 2 "" "")) ; max iterations
12660 (use (match_operand 3 "" "")) ; loop level
12661 (use (match_operand 4 "" ""))] ; label
12665 /* Only use this on innermost loops. */
12666 if (INTVAL (operands[3]) > 1)
12668 if (TARGET_POWERPC64)
12670 if (GET_MODE (operands[0]) != DImode)
12672 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
12676 if (GET_MODE (operands[0]) != SImode)
12678 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
12683 (define_expand "ctrsi"
12684 [(parallel [(set (pc)
12685 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
12687 (label_ref (match_operand 1 "" ""))
12690 (plus:SI (match_dup 0)
12692 (clobber (match_scratch:CC 2 ""))
12693 (clobber (match_scratch:SI 3 ""))])]
12694 "! TARGET_POWERPC64"
12697 (define_expand "ctrdi"
12698 [(parallel [(set (pc)
12699 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
12701 (label_ref (match_operand 1 "" ""))
12704 (plus:DI (match_dup 0)
12706 (clobber (match_scratch:CC 2 ""))
12707 (clobber (match_scratch:DI 3 ""))])]
12711 ;; We need to be able to do this for any operand, including MEM, or we
12712 ;; will cause reload to blow up since we don't allow output reloads on
12714 ;; For the length attribute to be calculated correctly, the
12715 ;; label MUST be operand 0.
12717 (define_insn "*ctrsi_internal1"
12719 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
12721 (label_ref (match_operand 0 "" ""))
12723 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12724 (plus:SI (match_dup 1)
12726 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12727 (clobber (match_scratch:SI 4 "=X,X,r"))]
12728 "! TARGET_POWERPC64"
12731 if (which_alternative != 0)
12733 else if (get_attr_length (insn) == 4)
12734 return \"{bdn|bdnz} %l0\";
12736 return \"bdz %$+8\;b %l0\";
12738 [(set_attr "type" "branch")
12739 (set_attr "length" "*,12,16")])
12741 (define_insn "*ctrsi_internal2"
12743 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
12746 (label_ref (match_operand 0 "" ""))))
12747 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12748 (plus:SI (match_dup 1)
12750 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12751 (clobber (match_scratch:SI 4 "=X,X,r"))]
12752 "! TARGET_POWERPC64"
12755 if (which_alternative != 0)
12757 else if (get_attr_length (insn) == 4)
12758 return \"bdz %l0\";
12760 return \"{bdn|bdnz} %$+8\;b %l0\";
12762 [(set_attr "type" "branch")
12763 (set_attr "length" "*,12,16")])
12765 (define_insn "*ctrdi_internal1"
12767 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
12769 (label_ref (match_operand 0 "" ""))
12771 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12772 (plus:DI (match_dup 1)
12774 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12775 (clobber (match_scratch:DI 4 "=X,X,r"))]
12779 if (which_alternative != 0)
12781 else if (get_attr_length (insn) == 4)
12782 return \"{bdn|bdnz} %l0\";
12784 return \"bdz %$+8\;b %l0\";
12786 [(set_attr "type" "branch")
12787 (set_attr "length" "*,12,16")])
12789 (define_insn "*ctrdi_internal2"
12791 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
12794 (label_ref (match_operand 0 "" ""))))
12795 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12796 (plus:DI (match_dup 1)
12798 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12799 (clobber (match_scratch:DI 4 "=X,X,r"))]
12803 if (which_alternative != 0)
12805 else if (get_attr_length (insn) == 4)
12806 return \"bdz %l0\";
12808 return \"{bdn|bdnz} %$+8\;b %l0\";
12810 [(set_attr "type" "branch")
12811 (set_attr "length" "*,12,16")])
12813 ;; Similar, but we can use GE since we have a REG_NONNEG.
12815 (define_insn "*ctrsi_internal3"
12817 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
12819 (label_ref (match_operand 0 "" ""))
12821 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12822 (plus:SI (match_dup 1)
12824 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12825 (clobber (match_scratch:SI 4 "=X,X,r"))]
12826 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12829 if (which_alternative != 0)
12831 else if (get_attr_length (insn) == 4)
12832 return \"{bdn|bdnz} %l0\";
12834 return \"bdz %$+8\;b %l0\";
12836 [(set_attr "type" "branch")
12837 (set_attr "length" "*,12,16")])
12839 (define_insn "*ctrsi_internal4"
12841 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
12844 (label_ref (match_operand 0 "" ""))))
12845 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12846 (plus:SI (match_dup 1)
12848 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12849 (clobber (match_scratch:SI 4 "=X,X,r"))]
12850 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12853 if (which_alternative != 0)
12855 else if (get_attr_length (insn) == 4)
12856 return \"bdz %l0\";
12858 return \"{bdn|bdnz} %$+8\;b %l0\";
12860 [(set_attr "type" "branch")
12861 (set_attr "length" "*,12,16")])
12863 (define_insn "*ctrdi_internal3"
12865 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
12867 (label_ref (match_operand 0 "" ""))
12869 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12870 (plus:DI (match_dup 1)
12872 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12873 (clobber (match_scratch:DI 4 "=X,X,r"))]
12874 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12877 if (which_alternative != 0)
12879 else if (get_attr_length (insn) == 4)
12880 return \"{bdn|bdnz} %l0\";
12882 return \"bdz %$+8\;b %l0\";
12884 [(set_attr "type" "branch")
12885 (set_attr "length" "*,12,16")])
12887 (define_insn "*ctrdi_internal4"
12889 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
12892 (label_ref (match_operand 0 "" ""))))
12893 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12894 (plus:DI (match_dup 1)
12896 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12897 (clobber (match_scratch:DI 4 "=X,X,r"))]
12898 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
12901 if (which_alternative != 0)
12903 else if (get_attr_length (insn) == 4)
12904 return \"bdz %l0\";
12906 return \"{bdn|bdnz} %$+8\;b %l0\";
12908 [(set_attr "type" "branch")
12909 (set_attr "length" "*,12,16")])
12911 ;; Similar but use EQ
12913 (define_insn "*ctrsi_internal5"
12915 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
12917 (label_ref (match_operand 0 "" ""))
12919 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12920 (plus:SI (match_dup 1)
12922 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12923 (clobber (match_scratch:SI 4 "=X,X,r"))]
12924 "! TARGET_POWERPC64"
12927 if (which_alternative != 0)
12929 else if (get_attr_length (insn) == 4)
12930 return \"bdz %l0\";
12932 return \"{bdn|bdnz} %$+8\;b %l0\";
12934 [(set_attr "type" "branch")
12935 (set_attr "length" "*,12,16")])
12937 (define_insn "*ctrsi_internal6"
12939 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
12942 (label_ref (match_operand 0 "" ""))))
12943 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12944 (plus:SI (match_dup 1)
12946 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12947 (clobber (match_scratch:SI 4 "=X,X,r"))]
12948 "! TARGET_POWERPC64"
12951 if (which_alternative != 0)
12953 else if (get_attr_length (insn) == 4)
12954 return \"{bdn|bdnz} %l0\";
12956 return \"bdz %$+8\;b %l0\";
12958 [(set_attr "type" "branch")
12959 (set_attr "length" "*,12,16")])
12961 (define_insn "*ctrdi_internal5"
12963 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
12965 (label_ref (match_operand 0 "" ""))
12967 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12968 (plus:DI (match_dup 1)
12970 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12971 (clobber (match_scratch:DI 4 "=X,X,r"))]
12975 if (which_alternative != 0)
12977 else if (get_attr_length (insn) == 4)
12978 return \"bdz %l0\";
12980 return \"{bdn|bdnz} %$+8\;b %l0\";
12982 [(set_attr "type" "branch")
12983 (set_attr "length" "*,12,16")])
12985 (define_insn "*ctrdi_internal6"
12987 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
12990 (label_ref (match_operand 0 "" ""))))
12991 (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l")
12992 (plus:DI (match_dup 1)
12994 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12995 (clobber (match_scratch:DI 4 "=X,X,r"))]
12999 if (which_alternative != 0)
13001 else if (get_attr_length (insn) == 4)
13002 return \"{bdn|bdnz} %l0\";
13004 return \"bdz %$+8\;b %l0\";
13006 [(set_attr "type" "branch")
13007 (set_attr "length" "*,12,16")])
13009 ;; Now the splitters if we could not allocate the CTR register
13013 (if_then_else (match_operator 2 "comparison_operator"
13014 [(match_operand:SI 1 "gpc_reg_operand" "")
13016 (match_operand 5 "" "")
13017 (match_operand 6 "" "")))
13018 (set (match_operand:SI 0 "gpc_reg_operand" "")
13019 (plus:SI (match_dup 1)
13021 (clobber (match_scratch:CC 3 ""))
13022 (clobber (match_scratch:SI 4 ""))]
13023 "! TARGET_POWERPC64 && reload_completed"
13024 [(parallel [(set (match_dup 3)
13025 (compare:CC (plus:SI (match_dup 1)
13029 (plus:SI (match_dup 1)
13031 (set (pc) (if_then_else (match_dup 7)
13035 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13040 (if_then_else (match_operator 2 "comparison_operator"
13041 [(match_operand:SI 1 "gpc_reg_operand" "")
13043 (match_operand 5 "" "")
13044 (match_operand 6 "" "")))
13045 (set (match_operand:SI 0 "nonimmediate_operand" "")
13046 (plus:SI (match_dup 1) (const_int -1)))
13047 (clobber (match_scratch:CC 3 ""))
13048 (clobber (match_scratch:SI 4 ""))]
13049 "! TARGET_POWERPC64 && reload_completed
13050 && ! gpc_reg_operand (operands[0], SImode)"
13051 [(parallel [(set (match_dup 3)
13052 (compare:CC (plus:SI (match_dup 1)
13056 (plus:SI (match_dup 1)
13060 (set (pc) (if_then_else (match_dup 7)
13064 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13068 (if_then_else (match_operator 2 "comparison_operator"
13069 [(match_operand:DI 1 "gpc_reg_operand" "")
13071 (match_operand 5 "" "")
13072 (match_operand 6 "" "")))
13073 (set (match_operand:DI 0 "gpc_reg_operand" "")
13074 (plus:DI (match_dup 1)
13076 (clobber (match_scratch:CC 3 ""))
13077 (clobber (match_scratch:DI 4 ""))]
13078 "TARGET_POWERPC64 && reload_completed"
13079 [(parallel [(set (match_dup 3)
13080 (compare:CC (plus:DI (match_dup 1)
13084 (plus:DI (match_dup 1)
13086 (set (pc) (if_then_else (match_dup 7)
13090 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13095 (if_then_else (match_operator 2 "comparison_operator"
13096 [(match_operand:DI 1 "gpc_reg_operand" "")
13098 (match_operand 5 "" "")
13099 (match_operand 6 "" "")))
13100 (set (match_operand:DI 0 "nonimmediate_operand" "")
13101 (plus:DI (match_dup 1) (const_int -1)))
13102 (clobber (match_scratch:CC 3 ""))
13103 (clobber (match_scratch:DI 4 ""))]
13104 "TARGET_POWERPC64 && reload_completed
13105 && ! gpc_reg_operand (operands[0], DImode)"
13106 [(parallel [(set (match_dup 3)
13107 (compare:CC (plus:DI (match_dup 1)
13111 (plus:DI (match_dup 1)
13115 (set (pc) (if_then_else (match_dup 7)
13119 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
13122 (define_insn "trap"
13123 [(trap_if (const_int 1) (const_int 0))]
13127 (define_expand "conditional_trap"
13128 [(trap_if (match_operator 0 "trap_comparison_operator"
13129 [(match_dup 2) (match_dup 3)])
13130 (match_operand 1 "const_int_operand" ""))]
13132 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
13133 operands[2] = rs6000_compare_op0;
13134 operands[3] = rs6000_compare_op1;")
13137 [(trap_if (match_operator 0 "trap_comparison_operator"
13138 [(match_operand:SI 1 "register_operand" "r")
13139 (match_operand:SI 2 "reg_or_short_operand" "rI")])
13142 "{t|tw}%V0%I2 %1,%2")
13145 [(trap_if (match_operator 0 "trap_comparison_operator"
13146 [(match_operand:DI 1 "register_operand" "r")
13147 (match_operand:DI 2 "reg_or_short_operand" "rI")])
13152 ;; Insns related to generating the function prologue and epilogue.
13154 (define_expand "prologue"
13155 [(use (const_int 0))]
13156 "TARGET_SCHED_PROLOG"
13159 rs6000_emit_prologue ();
13163 (define_insn "movesi_from_cr"
13164 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13165 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
13166 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
13170 (define_insn "*stmw"
13171 [(match_parallel 0 "stmw_operation"
13172 [(set (match_operand:SI 1 "memory_operand" "=m")
13173 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
13175 "{stm|stmw} %2,%1")
13177 (define_insn "*save_fpregs_si"
13178 [(match_parallel 0 "any_operand"
13179 [(clobber (match_operand:SI 1 "register_operand" "=l"))
13180 (use (match_operand:SI 2 "call_operand" "s"))
13181 (set (match_operand:DF 3 "memory_operand" "=m")
13182 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13186 (define_insn "*save_fpregs_di"
13187 [(match_parallel 0 "any_operand"
13188 [(clobber (match_operand:DI 1 "register_operand" "=l"))
13189 (use (match_operand:DI 2 "call_operand" "s"))
13190 (set (match_operand:DF 3 "memory_operand" "=m")
13191 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
13195 ; These are to explain that changes to the stack pointer should
13196 ; not be moved over stores to stack memory.
13197 (define_insn "stack_tie"
13198 [(set (match_operand:BLK 0 "memory_operand" "+m")
13199 (unspec:BLK [(match_dup 0)] 5))]
13202 [(set_attr "length" "0")])
13205 (define_expand "epilogue"
13206 [(use (const_int 0))]
13207 "TARGET_SCHED_PROLOG"
13210 rs6000_emit_epilogue (FALSE);
13214 ; On some processors, doing the mtcrf one CC register at a time is
13215 ; faster (like on the 604e). On others, doing them all at once is
13216 ; faster; for instance, on the 601 and 750.
13218 (define_expand "movsi_to_cr_one"
13219 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13220 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13221 (match_dup 2)] 20))]
13223 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
13225 (define_insn "*movsi_to_cr"
13226 [(match_parallel 0 "mtcrf_operation"
13227 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
13228 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
13229 (match_operand 3 "immediate_operand" "n")]
13236 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13237 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13238 operands[4] = GEN_INT (mask);
13239 return \"mtcrf %4,%2\";
13243 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
13244 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
13245 (match_operand 2 "immediate_operand" "n")] 20))]
13246 "GET_CODE (operands[0]) == REG
13247 && CR_REGNO_P (REGNO (operands[0]))
13248 && GET_CODE (operands[2]) == CONST_INT
13249 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
13252 ; The load-multiple instructions have similar properties.
13253 ; Note that "load_multiple" is a name known to the machine-independent
13254 ; code that actually corresponds to the powerpc load-string.
13256 (define_insn "*lmw"
13257 [(match_parallel 0 "lmw_operation"
13258 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13259 (match_operand:SI 2 "memory_operand" "m"))])]
13263 (define_insn "*return_internal_si"
13265 (use (match_operand:SI 0 "register_operand" "lc"))]
13268 [(set_attr "type" "jmpreg")])
13270 (define_insn "*return_internal_di"
13272 (use (match_operand:DI 0 "register_operand" "lc"))]
13275 [(set_attr "type" "jmpreg")])
13277 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
13278 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
13280 (define_insn "*return_and_restore_fpregs_si"
13281 [(match_parallel 0 "any_operand"
13283 (use (match_operand:SI 1 "register_operand" "l"))
13284 (use (match_operand:SI 2 "call_operand" "s"))
13285 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13286 (match_operand:DF 4 "memory_operand" "m"))])]
13290 (define_insn "*return_and_restore_fpregs_di"
13291 [(match_parallel 0 "any_operand"
13293 (use (match_operand:DI 1 "register_operand" "l"))
13294 (use (match_operand:DI 2 "call_operand" "s"))
13295 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
13296 (match_operand:DF 4 "memory_operand" "m"))])]
13300 ; This is used in compiling the unwind routines.
13301 (define_expand "eh_return"
13302 [(use (match_operand 0 "general_operand" ""))
13303 (use (match_operand 1 "general_operand" ""))]
13308 rs6000_emit_eh_toc_restore (operands[0]);
13311 emit_insn (gen_eh_set_lr_si (operands[1]));
13313 emit_insn (gen_eh_set_lr_di (operands[1]));
13314 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
13318 ; We can't expand this before we know where the link register is stored.
13319 (define_insn "eh_set_lr_si"
13320 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9)
13321 (clobber (match_scratch:SI 1 "=&r"))]
13325 (define_insn "eh_set_lr_di"
13326 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9)
13327 (clobber (match_scratch:DI 1 "=&r"))]
13332 [(unspec_volatile [(match_operand 0 "register_operand" "")] 9)
13333 (clobber (match_scratch 1 ""))]
13338 rs6000_stack_t *info = rs6000_stack_info ();
13340 if (info->lr_save_p)
13342 rtx frame_rtx = stack_pointer_rtx;
13346 if (frame_pointer_needed
13347 || current_function_calls_alloca
13348 || info->total_size > 32767)
13350 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
13351 frame_rtx = operands[1];
13353 else if (info->push_p)
13354 sp_offset = info->total_size;
13356 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13357 tmp = gen_rtx_MEM (Pmode, tmp);
13358 emit_move_insn (tmp, operands[0]);
13361 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);