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[thirdparty/gcc.git] / gcc / config / rx / rx.h
1 /* GCC backend definitions for the Renesas RX processor.
2 Copyright (C) 2008-2017 Free Software Foundation, Inc.
3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20 \f
21
22 #define TARGET_CPU_CPP_BUILTINS() \
23 do \
24 { \
25 builtin_define ("__RX__"); \
26 builtin_assert ("cpu=RX"); \
27 if (rx_cpu_type == RX610) \
28 { \
29 builtin_define ("__RX610__"); \
30 builtin_assert ("machine=RX610"); \
31 } \
32 else if (rx_cpu_type == RX100) \
33 { \
34 builtin_define ("__RX100__"); \
35 builtin_assert ("machine=RX100"); \
36 } \
37 else if (rx_cpu_type == RX200) \
38 { \
39 builtin_define ("__RX200__"); \
40 builtin_assert ("machine=RX200"); \
41 } \
42 else if (rx_cpu_type == RX600) \
43 { \
44 builtin_define ("__RX600__"); \
45 builtin_assert ("machine=RX600"); \
46 } \
47 \
48 if (TARGET_BIG_ENDIAN_DATA) \
49 builtin_define ("__RX_BIG_ENDIAN__"); \
50 else \
51 builtin_define ("__RX_LITTLE_ENDIAN__");\
52 \
53 if (TARGET_64BIT_DOUBLES) \
54 builtin_define ("__RX_64BIT_DOUBLES__");\
55 else \
56 builtin_define ("__RX_32BIT_DOUBLES__");\
57 \
58 if (ALLOW_RX_FPU_INSNS) \
59 builtin_define ("__RX_FPU_INSNS__"); \
60 \
61 if (TARGET_AS100_SYNTAX) \
62 builtin_define ("__RX_AS100_SYNTAX__"); \
63 else \
64 builtin_define ("__RX_GAS_SYNTAX__"); \
65 \
66 if (TARGET_GCC_ABI) \
67 builtin_define ("__RX_GCC_ABI__"); \
68 else \
69 builtin_define ("__RX_ABI__"); \
70 \
71 if (rx_allow_string_insns) \
72 builtin_define ("__RX_ALLOW_STRING_INSNS__"); \
73 else \
74 builtin_define ("__RX_DISALLOW_STRING_INSNS__");\
75 } \
76 while (0)
77
78 #undef CC1_SPEC
79 #define CC1_SPEC "\
80 %{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}} \
81 %{mcpu=rx100:%{fpu:%erx100 cpu does not have FPU hardware}} \
82 %{mcpu=rx200:%{fpu:%erx200 cpu does not have FPU hardware}}"
83
84 #undef STARTFILE_SPEC
85 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s"
86
87 #undef ENDFILE_SPEC
88 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
89
90 #undef CPP_SPEC
91 #define CPP_SPEC "\
92 %{mpid:-D_RX_PID=1} \
93 %{mint-register=*:-D_RX_INT_REGISTERS=%*} \
94 %{msmall-data-limit*:-D_RX_SMALL_DATA} \
95 "
96
97 #undef ASM_SPEC
98 #define ASM_SPEC "\
99 %{mbig-endian-data:-mbig-endian-data} \
100 %{m64bit-doubles:-m64bit-doubles} \
101 %{!m64bit-doubles:-m32bit-doubles} \
102 %{msmall-data-limit*:-msmall-data-limit} \
103 %{mrelax:-relax} \
104 %{mpid} \
105 %{mno-allow-string-insns} \
106 %{mint-register=*} \
107 %{mgcc-abi:-mgcc-abi} %{!mgcc-abi:-mrx-abi} \
108 %{mcpu=*} \
109 "
110
111 #undef LIB_SPEC
112 #define LIB_SPEC " \
113 --start-group \
114 -lc \
115 %{msim:-lsim}%{!msim:-lnosys} \
116 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \
117 --end-group \
118 %{!T*: %{msim:%Trx-sim.ld}%{!msim:%Trx.ld}} \
119 "
120
121 #undef LINK_SPEC
122 #define LINK_SPEC "%{mbig-endian-data:--oformat elf32-rx-be} %{mrelax:-relax}"
123 \f
124
125 #define BITS_BIG_ENDIAN 0
126 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA
127 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA
128
129 #define UNITS_PER_WORD 4
130
131 #define INT_TYPE_SIZE 32
132 #define LONG_TYPE_SIZE 32
133 #define LONG_LONG_TYPE_SIZE 64
134
135 #define FLOAT_TYPE_SIZE 32
136 #define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32)
137 #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE
138
139 #define DEFAULT_SIGNED_CHAR 0
140
141 /* RX load/store instructions can handle unaligned addresses. */
142 #define STRICT_ALIGNMENT 0
143 #define FUNCTION_BOUNDARY ((rx_cpu_type == RX100 || rx_cpu_type == RX200) ? 4 : 8)
144 #define BIGGEST_ALIGNMENT 32
145 #define STACK_BOUNDARY 32
146 #define PARM_BOUNDARY 8
147
148 #define STACK_GROWS_DOWNWARD 1
149 #define FRAME_GROWS_DOWNWARD 0
150 #define FIRST_PARM_OFFSET(FNDECL) 0
151
152 #define MAX_REGS_PER_ADDRESS 2
153
154 #define Pmode SImode
155 #define POINTER_SIZE 32
156 #undef SIZE_TYPE
157 #define SIZE_TYPE "long unsigned int"
158 #undef PTRDIFF_TYPE
159 #define PTRDIFF_TYPE "long int"
160 #undef WCHAR_TYPE
161 #define WCHAR_TYPE "long int"
162 #undef WCHAR_TYPE_SIZE
163 #define WCHAR_TYPE_SIZE BITS_PER_WORD
164 #define POINTERS_EXTEND_UNSIGNED 1
165 #define FUNCTION_MODE QImode
166 #define CASE_VECTOR_MODE Pmode
167 #define WORD_REGISTER_OPERATIONS 1
168 #define HAS_LONG_COND_BRANCH 0
169 #define HAS_LONG_UNCOND_BRANCH 0
170
171 #define MOVE_MAX 4
172 #define STARTING_FRAME_OFFSET 0
173
174 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
175
176 #define HAVE_PRE_DECREMENT 1
177 #define HAVE_POST_INCREMENT 1
178
179 #define MOVE_RATIO(SPEED) ((SPEED) ? 4 : 2)
180 #define SLOW_BYTE_ACCESS 1
181
182 #define STORE_FLAG_VALUE 1
183 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
184 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
185 \f
186 enum reg_class
187 {
188 NO_REGS, /* No registers in set. */
189 GR_REGS, /* Integer registers. */
190 ALL_REGS, /* All registers. */
191 LIM_REG_CLASSES /* Max value + 1. */
192 };
193
194 #define REG_CLASS_NAMES \
195 { \
196 "NO_REGS", \
197 "GR_REGS", \
198 "ALL_REGS" \
199 }
200
201 #define REG_CLASS_CONTENTS \
202 { \
203 { 0x00000000 }, /* No registers, */ \
204 { 0x0000ffff }, /* Integer registers. */ \
205 { 0x0000ffff } /* All registers. */ \
206 }
207
208 #define N_REG_CLASSES (int) LIM_REG_CLASSES
209 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \
210 + UNITS_PER_WORD - 1) \
211 / UNITS_PER_WORD)
212
213 #define GENERAL_REGS GR_REGS
214 #define BASE_REG_CLASS GR_REGS
215 #define INDEX_REG_CLASS GR_REGS
216
217 #define FIRST_PSEUDO_REGISTER 17
218
219 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \
220 ? GR_REGS : NO_REGS)
221
222 #define STACK_POINTER_REGNUM 0
223 #define FUNC_RETURN_REGNUM 1
224 #define FRAME_POINTER_REGNUM 6
225 #define ARG_POINTER_REGNUM 7
226 #define STATIC_CHAIN_REGNUM 8
227 #define TRAMPOLINE_TEMP_REGNUM 9
228 #define STRUCT_VAL_REGNUM 15
229 #define CC_REGNUM 16
230
231 /* This is the register which will probably be used to hold the address of
232 the start of the small data area, if -msmall-data-limit is being used,
233 or the address of the constant data area if -mpid is being used. If both
234 features are in use then two consecutive registers will be used.
235
236 Note - these registers must not be call_used because otherwise library
237 functions that are compiled without -msmall-data-limit/-mpid support
238 might clobber them.
239
240 Note that the actual values used depends on other options; use
241 rx_gp_base_regnum() and rx_pid_base_regnum() instead. */
242 #define GP_BASE_REGNUM 13
243
244 #define ELIMINABLE_REGS \
245 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
246 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \
247 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }}
248
249 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
250 (OFFSET) = rx_initial_elimination_offset ((FROM), (TO))
251
252
253 #define FUNCTION_ARG_REGNO_P(N) (((N) >= 1) && ((N) <= 4))
254 #define FUNCTION_VALUE_REGNO_P(N) ((N) == FUNC_RETURN_REGNUM)
255 #define DEFAULT_PCC_STRUCT_RETURN 0
256
257 #define FIXED_REGISTERS \
258 { \
259 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \
260 }
261
262 #define CALL_USED_REGISTERS \
263 { \
264 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 \
265 }
266
267 #define LIBCALL_VALUE(MODE) \
268 gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \
269 || COMPLEX_MODE_P (MODE) \
270 || VECTOR_MODE_P (MODE) \
271 || GET_MODE_SIZE (MODE) >= 4) \
272 ? (MODE) \
273 : SImode), \
274 FUNC_RETURN_REGNUM)
275
276 /* Order of allocation of registers. */
277
278 #define REG_ALLOC_ORDER \
279 { 7, 10, 11, 12, 13, 14, 4, 3, 2, 1, 9, 8, 6, 5, 15 \
280 }
281
282 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \
283 (IN_RANGE ((REGNO), (MIN), (MAX)) \
284 || (reg_renumber != NULL \
285 && reg_renumber[(REGNO)] >= (MIN) \
286 && reg_renumber[(REGNO)] <= (MAX)))
287
288 #ifdef REG_OK_STRICT
289 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 0, 15)
290 #else
291 #define REGNO_OK_FOR_BASE_P(regno) 1
292 #endif
293
294 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno)
295
296 #define RTX_OK_FOR_BASE(X, STRICT) \
297 ((STRICT) ? \
298 ( (REG_P (X) \
299 && REGNO_IN_RANGE (REGNO (X), 0, 15)) \
300 || (GET_CODE (X) == SUBREG \
301 && REG_P (SUBREG_REG (X)) \
302 && REGNO_IN_RANGE (REGNO (SUBREG_REG (X)), 0, 15))) \
303 : \
304 ( (REG_P (X) \
305 || (GET_CODE (X) == SUBREG \
306 && REG_P (SUBREG_REG (X))))))
307 \f
308
309 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
310 ((COUNT) == 0 \
311 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, arg_pointer_rtx, GEN_INT (-4))) \
312 : NULL_RTX)
313
314 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx)
315
316 #define ACCUMULATE_OUTGOING_ARGS 1
317
318 typedef unsigned int CUMULATIVE_ARGS;
319
320 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
321 (CUM) = 0
322
323 \f
324 #define TRAMPOLINE_SIZE (! TARGET_BIG_ENDIAN_DATA ? 14 : 20)
325 #define TRAMPOLINE_ALIGNMENT 32
326 \f
327 #define NO_PROFILE_COUNTERS 1
328 #define PROFILE_BEFORE_PROLOGUE 1
329
330 #define FUNCTION_PROFILER(FILE, LABELNO) \
331 fprintf (FILE, "\tbsr\t__mcount\n");
332 \f
333
334 #define REGISTER_NAMES \
335 { \
336 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
337 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "cc" \
338 }
339
340 #define ADDITIONAL_REGISTER_NAMES \
341 { \
342 { "sp", STACK_POINTER_REGNUM } \
343 , { "fp", FRAME_POINTER_REGNUM } \
344 , { "arg", ARG_POINTER_REGNUM } \
345 , { "chain", STATIC_CHAIN_REGNUM } \
346 }
347
348 #define DATA_SECTION_ASM_OP \
349 (TARGET_AS100_SYNTAX ? "\t.SECTION D,DATA" \
350 : "\t.section D,\"aw\",@progbits\n\t.p2align 2")
351
352 #define SDATA_SECTION_ASM_OP \
353 (TARGET_AS100_SYNTAX ? "\t.SECTION D_2,DATA,ALIGN=2" \
354 : "\t.section D_2,\"aw\",@progbits\n\t.p2align 1")
355
356 #undef READONLY_DATA_SECTION_ASM_OP
357 #define READONLY_DATA_SECTION_ASM_OP \
358 (TARGET_AS100_SYNTAX ? "\t.SECTION C,ROMDATA,ALIGN=4" \
359 : "\t.section C,\"a\",@progbits\n\t.p2align 2")
360
361 #define BSS_SECTION_ASM_OP \
362 (TARGET_AS100_SYNTAX ? "\t.SECTION B,DATA,ALIGN=4" \
363 : "\t.section B,\"w\",@nobits\n\t.p2align 2")
364
365 #define SBSS_SECTION_ASM_OP \
366 (TARGET_AS100_SYNTAX ? "\t.SECTION B_2,DATA,ALIGN=2" \
367 : "\t.section B_2,\"w\",@nobits\n\t.p2align 1")
368
369 /* The following definitions are conditional depending upon whether the
370 compiler is being built or crtstuff.c is being compiled by the built
371 compiler. */
372 #if defined CRT_BEGIN || defined CRT_END
373 # ifdef __RX_AS100_SYNTAX
374 # define TEXT_SECTION_ASM_OP "\t.SECTION P,CODE"
375 # define CTORS_SECTION_ASM_OP "\t.SECTION init_array,CODE"
376 # define DTORS_SECTION_ASM_OP "\t.SECTION fini_array,CODE"
377 # define INIT_ARRAY_SECTION_ASM_OP "\t.SECTION init_array,CODE"
378 # define FINI_ARRAY_SECTION_ASM_OP "\t.SECTION fini_array,CODE"
379 # else
380 # define TEXT_SECTION_ASM_OP "\t.section P,\"ax\""
381 # define CTORS_SECTION_ASM_OP \
382 "\t.section\t.init_array,\"awx\",@init_array"
383 # define DTORS_SECTION_ASM_OP \
384 "\t.section\t.fini_array,\"awx\",@fini_array"
385 # define INIT_ARRAY_SECTION_ASM_OP \
386 "\t.section\t.init_array,\"awx\",@init_array"
387 # define FINI_ARRAY_SECTION_ASM_OP \
388 "\t.section\t.fini_array,\"awx\",@fini_array"
389 # endif
390 #else
391 # define TEXT_SECTION_ASM_OP \
392 (TARGET_AS100_SYNTAX ? "\t.SECTION P,CODE" : "\t.section P,\"ax\"")
393
394 # define CTORS_SECTION_ASM_OP \
395 (TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \
396 : "\t.section\t.init_array,\"awx\",@init_array")
397
398 # define DTORS_SECTION_ASM_OP \
399 (TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \
400 : "\t.section\t.fini_array,\"awx\",@fini_array")
401
402 # define INIT_ARRAY_SECTION_ASM_OP \
403 (TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \
404 : "\t.section\t.init_array,\"awx\",@init_array")
405
406 # define FINI_ARRAY_SECTION_ASM_OP \
407 (TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \
408 : "\t.section\t.fini_array,\"awx\",@fini_array")
409 #endif
410
411 #define GLOBAL_ASM_OP \
412 (TARGET_AS100_SYNTAX ? "\t.GLB\t" : "\t.global\t")
413 #define ASM_COMMENT_START " ;"
414 #define ASM_APP_ON ""
415 #define ASM_APP_OFF ""
416 #define LOCAL_LABEL_PREFIX "L"
417 #undef USER_LABEL_PREFIX
418 #define USER_LABEL_PREFIX "_"
419
420 /* Compute the alignment needed for label X in various situations.
421 If the user has specified an alignment then honour that, otherwise
422 use rx_align_for_label. */
423 #define JUMP_ALIGN(x) (align_jumps > 1 ? align_jumps_log : rx_align_for_label (x, 0))
424 #define LABEL_ALIGN(x) (align_labels > 1 ? align_labels_log : rx_align_for_label (x, 3))
425 #define LOOP_ALIGN(x) (align_loops > 1 ? align_loops_log : rx_align_for_label (x, 2))
426 #define LABEL_ALIGN_AFTER_BARRIER(x) rx_align_for_label (x, 0)
427
428 #define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM, LOG, MAX_SKIP) \
429 do \
430 { \
431 if ((LOG) == 0 || (MAX_SKIP) == 0) \
432 break; \
433 if (TARGET_AS100_SYNTAX) \
434 { \
435 if ((LOG) >= 2) \
436 fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
437 else \
438 fprintf (STREAM, "\t.ALIGN 2\n"); \
439 } \
440 else \
441 fprintf (STREAM, "\t.balign %d,3,%d\n", 1 << (LOG), (MAX_SKIP)); \
442 } \
443 while (0)
444
445 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
446 do \
447 { \
448 if ((LOG) == 0) \
449 break; \
450 if (TARGET_AS100_SYNTAX) \
451 { \
452 if ((LOG) >= 2) \
453 fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \
454 else \
455 fprintf (STREAM, "\t.ALIGN 2\n"); \
456 } \
457 else \
458 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \
459 } \
460 while (0)
461
462 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
463 fprintf (FILE, TARGET_AS100_SYNTAX ? "\t.LWORD L%d\n" : "\t.long .L%d\n", \
464 VALUE)
465
466 /* This is how to output an element of a case-vector that is relative.
467 Note: The local label referenced by the "1b" below is emitted by
468 the tablejump insn. */
469
470 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
471 fprintf (FILE, TARGET_AS100_SYNTAX \
472 ? "\t.LWORD L%d - ?-\n" : "\t.long .L%d - 1b\n", VALUE)
473
474 #define CASE_VECTOR_PC_RELATIVE (TARGET_PID)
475
476 #define ASM_OUTPUT_SIZE_DIRECTIVE(STREAM, NAME, SIZE) \
477 do \
478 { \
479 HOST_WIDE_INT size_ = (SIZE); \
480 \
481 /* The as100 assembler does not have an equivalent of the SVR4 \
482 .size pseudo-op. */ \
483 if (TARGET_AS100_SYNTAX) \
484 break; \
485 \
486 fputs (SIZE_ASM_OP, STREAM); \
487 assemble_name (STREAM, NAME); \
488 fprintf (STREAM, ", " HOST_WIDE_INT_PRINT_DEC "\n", size_); \
489 } \
490 while (0)
491
492 #define ASM_OUTPUT_MEASURED_SIZE(STREAM, NAME) \
493 do \
494 { \
495 /* The as100 assembler does not have an equivalent of the SVR4 \
496 .size pseudo-op. */ \
497 if (TARGET_AS100_SYNTAX) \
498 break; \
499 fputs (SIZE_ASM_OP, STREAM); \
500 assemble_name (STREAM, NAME); \
501 fputs (", .-", STREAM); \
502 assemble_name (STREAM, NAME); \
503 putc ('\n', STREAM); \
504 } \
505 while (0)
506
507 #define ASM_OUTPUT_TYPE_DIRECTIVE(STREAM, NAME, TYPE) \
508 do \
509 { \
510 /* The as100 assembler does not have an equivalent of the SVR4 \
511 .size pseudo-op. */ \
512 if (TARGET_AS100_SYNTAX) \
513 break; \
514 fputs (TYPE_ASM_OP, STREAM); \
515 assemble_name (STREAM, NAME); \
516 fputs (", ", STREAM); \
517 fprintf (STREAM, TYPE_OPERAND_FMT, TYPE); \
518 putc ('\n', STREAM); \
519 } \
520 while (0)
521
522 #undef ASM_GENERATE_INTERNAL_LABEL
523 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
524 do \
525 { \
526 sprintf (LABEL, TARGET_AS100_SYNTAX ? "*%s%u" : "*.%s%u", \
527 PREFIX, (unsigned) (NUM)); \
528 } \
529 while (0)
530
531 #undef ASM_OUTPUT_EXTERNAL
532 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
533 do \
534 { \
535 if (TARGET_AS100_SYNTAX) \
536 targetm.asm_out.globalize_label (FILE, NAME); \
537 default_elf_asm_output_external (FILE, DECL, NAME); \
538 } \
539 while (0)
540
541 #undef ASM_OUTPUT_ALIGNED_COMMON
542 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
543 do \
544 { \
545 if (TARGET_AS100_SYNTAX) \
546 { \
547 fprintf ((FILE), "\t.GLB\t"); \
548 assemble_name ((FILE), (NAME)); \
549 fprintf ((FILE), "\n"); \
550 assemble_name ((FILE), (NAME)); \
551 switch ((ALIGN) / BITS_PER_UNIT) \
552 { \
553 case 4: \
554 fprintf ((FILE), ":\t.BLKL\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
555 (SIZE) / 4); \
556 break; \
557 case 2: \
558 fprintf ((FILE), ":\t.BLKW\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
559 (SIZE) / 2); \
560 break; \
561 default: \
562 fprintf ((FILE), ":\t.BLKB\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\
563 (SIZE)); \
564 break; \
565 } \
566 } \
567 else \
568 { \
569 fprintf ((FILE), "%s", COMMON_ASM_OP); \
570 assemble_name ((FILE), (NAME)); \
571 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
572 (SIZE), (ALIGN) / BITS_PER_UNIT); \
573 } \
574 } \
575 while (0)
576
577 #undef SKIP_ASM_OP
578 #define SKIP_ASM_OP (TARGET_AS100_SYNTAX ? "\t.BLKB\t" : "\t.zero\t")
579
580 #undef ASM_OUTPUT_LIMITED_STRING
581 #define ASM_OUTPUT_LIMITED_STRING(FILE, STR) \
582 do \
583 { \
584 const unsigned char *_limited_str = \
585 (const unsigned char *) (STR); \
586 unsigned ch; \
587 \
588 fprintf ((FILE), TARGET_AS100_SYNTAX \
589 ? "\t.BYTE\t\"" : "\t.string\t\""); \
590 \
591 for (; (ch = *_limited_str); _limited_str++) \
592 { \
593 int escape; \
594 \
595 switch (escape = ESCAPES[ch]) \
596 { \
597 case 0: \
598 putc (ch, (FILE)); \
599 break; \
600 case 1: \
601 fprintf ((FILE), "\\%03o", ch); \
602 break; \
603 default: \
604 putc ('\\', (FILE)); \
605 putc (escape, (FILE)); \
606 break; \
607 } \
608 } \
609 \
610 fprintf ((FILE), TARGET_AS100_SYNTAX ? "\"\n\t.BYTE\t0\n" : "\"\n");\
611 } \
612 while (0)
613
614 /* For PIC put jump tables into the text section so that the offsets that
615 they contain are always computed between two same-section symbols. */
616 #define JUMP_TABLES_IN_TEXT_SECTION (TARGET_PID || flag_pic)
617 \f
618 /* This is a version of REG_P that also returns TRUE for SUBREGs. */
619 #define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
620
621 /* Like REG_P except that this macro is true for SET expressions. */
622 #define SET_P(rtl) (GET_CODE (rtl) == SET)
623 \f
624 /* The AS100 assembler does not support .leb128 and .uleb128, but
625 the compiler-build-time configure tests will have enabled their
626 use because GAS supports them. So default to generating STABS
627 debug information instead of DWARF2 when generating AS100
628 compatible output. */
629 #undef PREFERRED_DEBUGGING_TYPE
630 #define PREFERRED_DEBUGGING_TYPE (TARGET_AS100_SYNTAX \
631 ? DBX_DEBUG : DWARF2_DEBUG)
632
633 #define INCOMING_FRAME_SP_OFFSET 4
634 #define ARG_POINTER_CFA_OFFSET(FNDECL) 4
635 \f
636 #define TARGET_USE_FPU (! TARGET_NO_USE_FPU)
637
638 /* This macro is used to decide when RX FPU instructions can be used. */
639 #define ALLOW_RX_FPU_INSNS (TARGET_USE_FPU)
640
641 #define BRANCH_COST(SPEED,PREDICT) 1
642 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2
643
644 #define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode(OP, X, Y)
645
646 #define ADJUST_INSN_LENGTH(INSN,LENGTH) \
647 do \
648 { \
649 (LENGTH) = rx_adjust_insn_length ((INSN), (LENGTH)); \
650 } \
651 while (0)
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