1 /* Subroutines used for code generation on IBM S/390 and zSeries
2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
3 2007 Free Software Foundation, Inc.
4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 Ulrich Weigand (uweigand@de.ibm.com).
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 3, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
48 #include "target-def.h"
50 #include "langhooks.h"
52 #include "tree-gimple.h"
56 /* Define the specific costs for a given cpu. */
58 struct processor_costs
61 const int m
; /* cost of an M instruction. */
62 const int mghi
; /* cost of an MGHI instruction. */
63 const int mh
; /* cost of an MH instruction. */
64 const int mhi
; /* cost of an MHI instruction. */
65 const int ml
; /* cost of an ML instruction. */
66 const int mr
; /* cost of an MR instruction. */
67 const int ms
; /* cost of an MS instruction. */
68 const int msg
; /* cost of an MSG instruction. */
69 const int msgf
; /* cost of an MSGF instruction. */
70 const int msgfr
; /* cost of an MSGFR instruction. */
71 const int msgr
; /* cost of an MSGR instruction. */
72 const int msr
; /* cost of an MSR instruction. */
73 const int mult_df
; /* cost of multiplication in DFmode. */
76 const int sqxbr
; /* cost of square root in TFmode. */
77 const int sqdbr
; /* cost of square root in DFmode. */
78 const int sqebr
; /* cost of square root in SFmode. */
79 /* multiply and add */
80 const int madbr
; /* cost of multiply and add in DFmode. */
81 const int maebr
; /* cost of multiply and add in SFmode. */
93 const struct processor_costs
*s390_cost
;
96 struct processor_costs z900_cost
=
98 COSTS_N_INSNS (5), /* M */
99 COSTS_N_INSNS (10), /* MGHI */
100 COSTS_N_INSNS (5), /* MH */
101 COSTS_N_INSNS (4), /* MHI */
102 COSTS_N_INSNS (5), /* ML */
103 COSTS_N_INSNS (5), /* MR */
104 COSTS_N_INSNS (4), /* MS */
105 COSTS_N_INSNS (15), /* MSG */
106 COSTS_N_INSNS (7), /* MSGF */
107 COSTS_N_INSNS (7), /* MSGFR */
108 COSTS_N_INSNS (10), /* MSGR */
109 COSTS_N_INSNS (4), /* MSR */
110 COSTS_N_INSNS (7), /* multiplication in DFmode */
111 COSTS_N_INSNS (13), /* MXBR */
112 COSTS_N_INSNS (136), /* SQXBR */
113 COSTS_N_INSNS (44), /* SQDBR */
114 COSTS_N_INSNS (35), /* SQEBR */
115 COSTS_N_INSNS (18), /* MADBR */
116 COSTS_N_INSNS (13), /* MAEBR */
117 COSTS_N_INSNS (134), /* DXBR */
118 COSTS_N_INSNS (30), /* DDBR */
119 COSTS_N_INSNS (27), /* DEBR */
120 COSTS_N_INSNS (220), /* DLGR */
121 COSTS_N_INSNS (34), /* DLR */
122 COSTS_N_INSNS (34), /* DR */
123 COSTS_N_INSNS (32), /* DSGFR */
124 COSTS_N_INSNS (32), /* DSGR */
128 struct processor_costs z990_cost
=
130 COSTS_N_INSNS (4), /* M */
131 COSTS_N_INSNS (2), /* MGHI */
132 COSTS_N_INSNS (2), /* MH */
133 COSTS_N_INSNS (2), /* MHI */
134 COSTS_N_INSNS (4), /* ML */
135 COSTS_N_INSNS (4), /* MR */
136 COSTS_N_INSNS (5), /* MS */
137 COSTS_N_INSNS (6), /* MSG */
138 COSTS_N_INSNS (4), /* MSGF */
139 COSTS_N_INSNS (4), /* MSGFR */
140 COSTS_N_INSNS (4), /* MSGR */
141 COSTS_N_INSNS (4), /* MSR */
142 COSTS_N_INSNS (1), /* multiplication in DFmode */
143 COSTS_N_INSNS (28), /* MXBR */
144 COSTS_N_INSNS (130), /* SQXBR */
145 COSTS_N_INSNS (66), /* SQDBR */
146 COSTS_N_INSNS (38), /* SQEBR */
147 COSTS_N_INSNS (1), /* MADBR */
148 COSTS_N_INSNS (1), /* MAEBR */
149 COSTS_N_INSNS (60), /* DXBR */
150 COSTS_N_INSNS (40), /* DDBR */
151 COSTS_N_INSNS (26), /* DEBR */
152 COSTS_N_INSNS (176), /* DLGR */
153 COSTS_N_INSNS (31), /* DLR */
154 COSTS_N_INSNS (31), /* DR */
155 COSTS_N_INSNS (31), /* DSGFR */
156 COSTS_N_INSNS (31), /* DSGR */
160 struct processor_costs z9_109_cost
=
162 COSTS_N_INSNS (4), /* M */
163 COSTS_N_INSNS (2), /* MGHI */
164 COSTS_N_INSNS (2), /* MH */
165 COSTS_N_INSNS (2), /* MHI */
166 COSTS_N_INSNS (4), /* ML */
167 COSTS_N_INSNS (4), /* MR */
168 COSTS_N_INSNS (5), /* MS */
169 COSTS_N_INSNS (6), /* MSG */
170 COSTS_N_INSNS (4), /* MSGF */
171 COSTS_N_INSNS (4), /* MSGFR */
172 COSTS_N_INSNS (4), /* MSGR */
173 COSTS_N_INSNS (4), /* MSR */
174 COSTS_N_INSNS (1), /* multiplication in DFmode */
175 COSTS_N_INSNS (28), /* MXBR */
176 COSTS_N_INSNS (130), /* SQXBR */
177 COSTS_N_INSNS (66), /* SQDBR */
178 COSTS_N_INSNS (38), /* SQEBR */
179 COSTS_N_INSNS (1), /* MADBR */
180 COSTS_N_INSNS (1), /* MAEBR */
181 COSTS_N_INSNS (60), /* DXBR */
182 COSTS_N_INSNS (40), /* DDBR */
183 COSTS_N_INSNS (26), /* DEBR */
184 COSTS_N_INSNS (30), /* DLGR */
185 COSTS_N_INSNS (23), /* DLR */
186 COSTS_N_INSNS (23), /* DR */
187 COSTS_N_INSNS (24), /* DSGFR */
188 COSTS_N_INSNS (24), /* DSGR */
191 extern int reload_completed
;
193 /* Save information from a "cmpxx" operation until the branch or scc is
195 rtx s390_compare_op0
, s390_compare_op1
;
197 /* Save the result of a compare_and_swap until the branch or scc is
199 rtx s390_compare_emitted
= NULL_RTX
;
201 /* Structure used to hold the components of a S/390 memory
202 address. A legitimate address on S/390 is of the general
204 base + index + displacement
205 where any of the components is optional.
207 base and index are registers of the class ADDR_REGS,
208 displacement is an unsigned 12-bit immediate constant. */
219 /* Which cpu are we tuning for. */
220 enum processor_type s390_tune
= PROCESSOR_max
;
221 enum processor_flags s390_tune_flags
;
222 /* Which instruction set architecture to use. */
223 enum processor_type s390_arch
;
224 enum processor_flags s390_arch_flags
;
226 HOST_WIDE_INT s390_warn_framesize
= 0;
227 HOST_WIDE_INT s390_stack_size
= 0;
228 HOST_WIDE_INT s390_stack_guard
= 0;
230 /* The following structure is embedded in the machine
231 specific part of struct function. */
233 struct s390_frame_layout
GTY (())
235 /* Offset within stack frame. */
236 HOST_WIDE_INT gprs_offset
;
237 HOST_WIDE_INT f0_offset
;
238 HOST_WIDE_INT f4_offset
;
239 HOST_WIDE_INT f8_offset
;
240 HOST_WIDE_INT backchain_offset
;
242 /* Number of first and last gpr where slots in the register
243 save area are reserved for. */
244 int first_save_gpr_slot
;
245 int last_save_gpr_slot
;
247 /* Number of first and last gpr to be saved, restored. */
249 int first_restore_gpr
;
251 int last_restore_gpr
;
253 /* Bits standing for floating point registers. Set, if the
254 respective register has to be saved. Starting with reg 16 (f0)
255 at the rightmost bit.
256 Bit 15 - 8 7 6 5 4 3 2 1 0
257 fpr 15 - 8 7 5 3 1 6 4 2 0
258 reg 31 - 24 23 22 21 20 19 18 17 16 */
259 unsigned int fpr_bitmap
;
261 /* Number of floating point registers f8-f15 which must be saved. */
264 /* Set if return address needs to be saved.
265 This flag is set by s390_return_addr_rtx if it could not use
266 the initial value of r14 and therefore depends on r14 saved
268 bool save_return_addr_p
;
270 /* Size of stack frame. */
271 HOST_WIDE_INT frame_size
;
274 /* Define the structure for the machine field in struct function. */
276 struct machine_function
GTY(())
278 struct s390_frame_layout frame_layout
;
280 /* Literal pool base register. */
283 /* True if we may need to perform branch splitting. */
284 bool split_branches_pending_p
;
286 /* True during final stage of literal pool processing. */
287 bool decomposed_literal_pool_addresses_ok_p
;
289 /* Some local-dynamic TLS symbol name. */
290 const char *some_ld_name
;
292 bool has_landing_pad_p
;
295 /* Few accessor macros for struct cfun->machine->s390_frame_layout. */
297 #define cfun_frame_layout (cfun->machine->frame_layout)
298 #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
299 #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
300 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_WORD)
301 #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \
303 #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \
306 /* Number of GPRs and FPRs used for argument passing. */
307 #define GP_ARG_NUM_REG 5
308 #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
310 /* A couple of shortcuts. */
311 #define CONST_OK_FOR_J(x) \
312 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
313 #define CONST_OK_FOR_K(x) \
314 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
315 #define CONST_OK_FOR_Os(x) \
316 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
317 #define CONST_OK_FOR_Op(x) \
318 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
319 #define CONST_OK_FOR_On(x) \
320 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
322 #define REGNO_PAIR_OK(REGNO, MODE) \
323 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
325 static enum machine_mode
326 s390_libgcc_cmp_return_mode (void)
328 return TARGET_64BIT
? DImode
: SImode
;
331 static enum machine_mode
332 s390_libgcc_shift_count_mode (void)
334 return TARGET_64BIT
? DImode
: SImode
;
337 /* Return true if the back end supports mode MODE. */
339 s390_scalar_mode_supported_p (enum machine_mode mode
)
341 if (DECIMAL_FLOAT_MODE_P (mode
))
344 return default_scalar_mode_supported_p (mode
);
347 /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
350 s390_set_has_landing_pad_p (bool value
)
352 cfun
->machine
->has_landing_pad_p
= value
;
355 /* If two condition code modes are compatible, return a condition code
356 mode which is compatible with both. Otherwise, return
359 static enum machine_mode
360 s390_cc_modes_compatible (enum machine_mode m1
, enum machine_mode m2
)
368 if (m2
== CCUmode
|| m2
== CCTmode
|| m2
== CCZ1mode
369 || m2
== CCSmode
|| m2
== CCSRmode
|| m2
== CCURmode
)
390 /* Return true if SET either doesn't set the CC register, or else
391 the source and destination have matching CC modes and that
392 CC mode is at least as constrained as REQ_MODE. */
395 s390_match_ccmode_set (rtx set
, enum machine_mode req_mode
)
397 enum machine_mode set_mode
;
399 gcc_assert (GET_CODE (set
) == SET
);
401 if (GET_CODE (SET_DEST (set
)) != REG
|| !CC_REGNO_P (REGNO (SET_DEST (set
))))
404 set_mode
= GET_MODE (SET_DEST (set
));
418 if (req_mode
!= set_mode
)
423 if (req_mode
!= CCSmode
&& req_mode
!= CCUmode
&& req_mode
!= CCTmode
424 && req_mode
!= CCSRmode
&& req_mode
!= CCURmode
)
430 if (req_mode
!= CCAmode
)
438 return (GET_MODE (SET_SRC (set
)) == set_mode
);
441 /* Return true if every SET in INSN that sets the CC register
442 has source and destination with matching CC modes and that
443 CC mode is at least as constrained as REQ_MODE.
444 If REQ_MODE is VOIDmode, always return false. */
447 s390_match_ccmode (rtx insn
, enum machine_mode req_mode
)
451 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
452 if (req_mode
== VOIDmode
)
455 if (GET_CODE (PATTERN (insn
)) == SET
)
456 return s390_match_ccmode_set (PATTERN (insn
), req_mode
);
458 if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
459 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
461 rtx set
= XVECEXP (PATTERN (insn
), 0, i
);
462 if (GET_CODE (set
) == SET
)
463 if (!s390_match_ccmode_set (set
, req_mode
))
470 /* If a test-under-mask instruction can be used to implement
471 (compare (and ... OP1) OP2), return the CC mode required
472 to do that. Otherwise, return VOIDmode.
473 MIXED is true if the instruction can distinguish between
474 CC1 and CC2 for mixed selected bits (TMxx), it is false
475 if the instruction cannot (TM). */
478 s390_tm_ccmode (rtx op1
, rtx op2
, bool mixed
)
482 /* ??? Fixme: should work on CONST_DOUBLE as well. */
483 if (GET_CODE (op1
) != CONST_INT
|| GET_CODE (op2
) != CONST_INT
)
486 /* Selected bits all zero: CC0.
487 e.g.: int a; if ((a & (16 + 128)) == 0) */
488 if (INTVAL (op2
) == 0)
491 /* Selected bits all one: CC3.
492 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
493 if (INTVAL (op2
) == INTVAL (op1
))
496 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
498 if ((a & (16 + 128)) == 16) -> CCT1
499 if ((a & (16 + 128)) == 128) -> CCT2 */
502 bit1
= exact_log2 (INTVAL (op2
));
503 bit0
= exact_log2 (INTVAL (op1
) ^ INTVAL (op2
));
504 if (bit0
!= -1 && bit1
!= -1)
505 return bit0
> bit1
? CCT1mode
: CCT2mode
;
511 /* Given a comparison code OP (EQ, NE, etc.) and the operands
512 OP0 and OP1 of a COMPARE, return the mode to be used for the
516 s390_select_ccmode (enum rtx_code code
, rtx op0
, rtx op1
)
522 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
523 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
525 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
526 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
528 if ((GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
529 || GET_CODE (op1
) == NEG
)
530 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
533 if (GET_CODE (op0
) == AND
)
535 /* Check whether we can potentially do it via TM. */
536 enum machine_mode ccmode
;
537 ccmode
= s390_tm_ccmode (XEXP (op0
, 1), op1
, 1);
538 if (ccmode
!= VOIDmode
)
540 /* Relax CCTmode to CCZmode to allow fall-back to AND
541 if that turns out to be beneficial. */
542 return ccmode
== CCTmode
? CCZmode
: ccmode
;
546 if (register_operand (op0
, HImode
)
547 && GET_CODE (op1
) == CONST_INT
548 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 65535))
550 if (register_operand (op0
, QImode
)
551 && GET_CODE (op1
) == CONST_INT
552 && (INTVAL (op1
) == -1 || INTVAL (op1
) == 255))
561 /* The only overflow condition of NEG and ABS happens when
562 -INT_MAX is used as parameter, which stays negative. So
563 we have an overflow from a positive value to a negative.
564 Using CCAP mode the resulting cc can be used for comparisons. */
565 if ((GET_CODE (op0
) == NEG
|| GET_CODE (op0
) == ABS
)
566 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
569 /* If constants are involved in an add instruction it is possible to use
570 the resulting cc for comparisons with zero. Knowing the sign of the
571 constant the overflow behavior gets predictable. e.g.:
572 int a, b; if ((b = a + c) > 0)
573 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
574 if (GET_CODE (op0
) == PLUS
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
575 && CONST_OK_FOR_K (INTVAL (XEXP (op0
, 1))))
577 if (INTVAL (XEXP((op0
), 1)) < 0)
591 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
592 && GET_CODE (op1
) != CONST_INT
)
598 if (GET_CODE (op0
) == PLUS
599 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
602 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
603 && GET_CODE (op1
) != CONST_INT
)
609 if (GET_CODE (op0
) == MINUS
610 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
)
613 if ((GET_CODE (op0
) == SIGN_EXTEND
|| GET_CODE (op0
) == ZERO_EXTEND
)
614 && GET_CODE (op1
) != CONST_INT
)
623 /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
624 that we can implement more efficiently. */
627 s390_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
)
629 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
630 if ((*code
== EQ
|| *code
== NE
)
631 && *op1
== const0_rtx
632 && GET_CODE (*op0
) == ZERO_EXTRACT
633 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
634 && GET_CODE (XEXP (*op0
, 2)) == CONST_INT
635 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
637 rtx inner
= XEXP (*op0
, 0);
638 HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (GET_MODE (inner
));
639 HOST_WIDE_INT len
= INTVAL (XEXP (*op0
, 1));
640 HOST_WIDE_INT pos
= INTVAL (XEXP (*op0
, 2));
642 if (len
> 0 && len
< modesize
643 && pos
>= 0 && pos
+ len
<= modesize
644 && modesize
<= HOST_BITS_PER_WIDE_INT
)
646 unsigned HOST_WIDE_INT block
;
647 block
= ((unsigned HOST_WIDE_INT
) 1 << len
) - 1;
648 block
<<= modesize
- pos
- len
;
650 *op0
= gen_rtx_AND (GET_MODE (inner
), inner
,
651 gen_int_mode (block
, GET_MODE (inner
)));
655 /* Narrow AND of memory against immediate to enable TM. */
656 if ((*code
== EQ
|| *code
== NE
)
657 && *op1
== const0_rtx
658 && GET_CODE (*op0
) == AND
659 && GET_CODE (XEXP (*op0
, 1)) == CONST_INT
660 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0
, 0))))
662 rtx inner
= XEXP (*op0
, 0);
663 rtx mask
= XEXP (*op0
, 1);
665 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
666 if (GET_CODE (inner
) == SUBREG
667 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner
)))
668 && (GET_MODE_SIZE (GET_MODE (inner
))
669 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner
))))
671 & GET_MODE_MASK (GET_MODE (inner
))
672 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner
))))
674 inner
= SUBREG_REG (inner
);
676 /* Do not change volatile MEMs. */
677 if (MEM_P (inner
) && !MEM_VOLATILE_P (inner
))
679 int part
= s390_single_part (XEXP (*op0
, 1),
680 GET_MODE (inner
), QImode
, 0);
683 mask
= gen_int_mode (s390_extract_part (mask
, QImode
, 0), QImode
);
684 inner
= adjust_address_nv (inner
, QImode
, part
);
685 *op0
= gen_rtx_AND (QImode
, inner
, mask
);
690 /* Narrow comparisons against 0xffff to HImode if possible. */
691 if ((*code
== EQ
|| *code
== NE
)
692 && GET_CODE (*op1
) == CONST_INT
693 && INTVAL (*op1
) == 0xffff
694 && SCALAR_INT_MODE_P (GET_MODE (*op0
))
695 && (nonzero_bits (*op0
, GET_MODE (*op0
))
696 & ~(unsigned HOST_WIDE_INT
) 0xffff) == 0)
698 *op0
= gen_lowpart (HImode
, *op0
);
702 /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */
703 if (GET_CODE (*op0
) == UNSPEC
704 && XINT (*op0
, 1) == UNSPEC_CCU_TO_INT
705 && XVECLEN (*op0
, 0) == 1
706 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCUmode
707 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
708 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
709 && *op1
== const0_rtx
)
711 enum rtx_code new_code
= UNKNOWN
;
714 case EQ
: new_code
= EQ
; break;
715 case NE
: new_code
= NE
; break;
716 case LT
: new_code
= GTU
; break;
717 case GT
: new_code
= LTU
; break;
718 case LE
: new_code
= GEU
; break;
719 case GE
: new_code
= LEU
; break;
723 if (new_code
!= UNKNOWN
)
725 *op0
= XVECEXP (*op0
, 0, 0);
730 /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */
731 if (GET_CODE (*op0
) == UNSPEC
732 && XINT (*op0
, 1) == UNSPEC_CCZ_TO_INT
733 && XVECLEN (*op0
, 0) == 1
734 && GET_MODE (XVECEXP (*op0
, 0, 0)) == CCZmode
735 && GET_CODE (XVECEXP (*op0
, 0, 0)) == REG
736 && REGNO (XVECEXP (*op0
, 0, 0)) == CC_REGNUM
737 && *op1
== const0_rtx
)
739 enum rtx_code new_code
= UNKNOWN
;
742 case EQ
: new_code
= EQ
; break;
743 case NE
: new_code
= NE
; break;
747 if (new_code
!= UNKNOWN
)
749 *op0
= XVECEXP (*op0
, 0, 0);
754 /* Simplify cascaded EQ, NE with const0_rtx. */
755 if ((*code
== NE
|| *code
== EQ
)
756 && (GET_CODE (*op0
) == EQ
|| GET_CODE (*op0
) == NE
)
757 && GET_MODE (*op0
) == SImode
758 && GET_MODE (XEXP (*op0
, 0)) == CCZ1mode
759 && REG_P (XEXP (*op0
, 0))
760 && XEXP (*op0
, 1) == const0_rtx
761 && *op1
== const0_rtx
)
763 if ((*code
== EQ
&& GET_CODE (*op0
) == NE
)
764 || (*code
== NE
&& GET_CODE (*op0
) == EQ
))
768 *op0
= XEXP (*op0
, 0);
771 /* Prefer register over memory as first operand. */
772 if (MEM_P (*op0
) && REG_P (*op1
))
774 rtx tem
= *op0
; *op0
= *op1
; *op1
= tem
;
775 *code
= swap_condition (*code
);
779 /* Emit a compare instruction suitable to implement the comparison
780 OP0 CODE OP1. Return the correct condition RTL to be placed in
781 the IF_THEN_ELSE of the conditional branch testing the result. */
784 s390_emit_compare (enum rtx_code code
, rtx op0
, rtx op1
)
786 enum machine_mode mode
= s390_select_ccmode (code
, op0
, op1
);
789 /* Do not output a redundant compare instruction if a compare_and_swap
790 pattern already computed the result and the machine modes are compatible. */
791 if (s390_compare_emitted
792 && (s390_cc_modes_compatible (GET_MODE (s390_compare_emitted
), mode
)
793 == GET_MODE (s390_compare_emitted
)))
794 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, s390_compare_emitted
, const0_rtx
);
797 rtx cc
= gen_rtx_REG (mode
, CC_REGNUM
);
799 emit_insn (gen_rtx_SET (VOIDmode
, cc
, gen_rtx_COMPARE (mode
, op0
, op1
)));
800 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, cc
, const0_rtx
);
802 s390_compare_emitted
= NULL_RTX
;
806 /* Emit a SImode compare and swap instruction setting MEM to NEW if OLD
808 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
809 conditional branch testing the result. */
812 s390_emit_compare_and_swap (enum rtx_code code
, rtx old
, rtx mem
, rtx cmp
, rtx
new)
816 emit_insn (gen_sync_compare_and_swap_ccsi (old
, mem
, cmp
, new));
817 ret
= gen_rtx_fmt_ee (code
, VOIDmode
, s390_compare_emitted
, const0_rtx
);
819 s390_compare_emitted
= NULL_RTX
;
824 /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an
825 unconditional jump, else a conditional jump under condition COND. */
828 s390_emit_jump (rtx target
, rtx cond
)
832 target
= gen_rtx_LABEL_REF (VOIDmode
, target
);
834 target
= gen_rtx_IF_THEN_ELSE (VOIDmode
, cond
, target
, pc_rtx
);
836 insn
= gen_rtx_SET (VOIDmode
, pc_rtx
, target
);
837 emit_jump_insn (insn
);
840 /* Return branch condition mask to implement a branch
841 specified by CODE. Return -1 for invalid comparisons. */
844 s390_branch_condition_mask (rtx code
)
846 const int CC0
= 1 << 3;
847 const int CC1
= 1 << 2;
848 const int CC2
= 1 << 1;
849 const int CC3
= 1 << 0;
851 gcc_assert (GET_CODE (XEXP (code
, 0)) == REG
);
852 gcc_assert (REGNO (XEXP (code
, 0)) == CC_REGNUM
);
853 gcc_assert (XEXP (code
, 1) == const0_rtx
);
855 switch (GET_MODE (XEXP (code
, 0)))
859 switch (GET_CODE (code
))
862 case NE
: return CC1
| CC2
| CC3
;
868 switch (GET_CODE (code
))
871 case NE
: return CC0
| CC2
| CC3
;
877 switch (GET_CODE (code
))
880 case NE
: return CC0
| CC1
| CC3
;
886 switch (GET_CODE (code
))
889 case NE
: return CC0
| CC1
| CC2
;
895 switch (GET_CODE (code
))
897 case EQ
: return CC0
| CC2
;
898 case NE
: return CC1
| CC3
;
904 switch (GET_CODE (code
))
906 case LTU
: return CC2
| CC3
; /* carry */
907 case GEU
: return CC0
| CC1
; /* no carry */
913 switch (GET_CODE (code
))
915 case GTU
: return CC0
| CC1
; /* borrow */
916 case LEU
: return CC2
| CC3
; /* no borrow */
922 switch (GET_CODE (code
))
924 case EQ
: return CC0
| CC2
;
925 case NE
: return CC1
| CC3
;
926 case LTU
: return CC1
;
927 case GTU
: return CC3
;
928 case LEU
: return CC1
| CC2
;
929 case GEU
: return CC2
| CC3
;
934 switch (GET_CODE (code
))
937 case NE
: return CC1
| CC2
| CC3
;
938 case LTU
: return CC1
;
939 case GTU
: return CC2
;
940 case LEU
: return CC0
| CC1
;
941 case GEU
: return CC0
| CC2
;
947 switch (GET_CODE (code
))
950 case NE
: return CC2
| CC1
| CC3
;
951 case LTU
: return CC2
;
952 case GTU
: return CC1
;
953 case LEU
: return CC0
| CC2
;
954 case GEU
: return CC0
| CC1
;
960 switch (GET_CODE (code
))
963 case NE
: return CC1
| CC2
| CC3
;
964 case LT
: return CC1
| CC3
;
966 case LE
: return CC0
| CC1
| CC3
;
967 case GE
: return CC0
| CC2
;
973 switch (GET_CODE (code
))
976 case NE
: return CC1
| CC2
| CC3
;
978 case GT
: return CC2
| CC3
;
979 case LE
: return CC0
| CC1
;
980 case GE
: return CC0
| CC2
| CC3
;
986 switch (GET_CODE (code
))
989 case NE
: return CC1
| CC2
| CC3
;
992 case LE
: return CC0
| CC1
;
993 case GE
: return CC0
| CC2
;
994 case UNORDERED
: return CC3
;
995 case ORDERED
: return CC0
| CC1
| CC2
;
996 case UNEQ
: return CC0
| CC3
;
997 case UNLT
: return CC1
| CC3
;
998 case UNGT
: return CC2
| CC3
;
999 case UNLE
: return CC0
| CC1
| CC3
;
1000 case UNGE
: return CC0
| CC2
| CC3
;
1001 case LTGT
: return CC1
| CC2
;
1007 switch (GET_CODE (code
))
1009 case EQ
: return CC0
;
1010 case NE
: return CC2
| CC1
| CC3
;
1011 case LT
: return CC2
;
1012 case GT
: return CC1
;
1013 case LE
: return CC0
| CC2
;
1014 case GE
: return CC0
| CC1
;
1015 case UNORDERED
: return CC3
;
1016 case ORDERED
: return CC0
| CC2
| CC1
;
1017 case UNEQ
: return CC0
| CC3
;
1018 case UNLT
: return CC2
| CC3
;
1019 case UNGT
: return CC1
| CC3
;
1020 case UNLE
: return CC0
| CC2
| CC3
;
1021 case UNGE
: return CC0
| CC1
| CC3
;
1022 case LTGT
: return CC2
| CC1
;
1032 /* If INV is false, return assembler mnemonic string to implement
1033 a branch specified by CODE. If INV is true, return mnemonic
1034 for the corresponding inverted branch. */
1037 s390_branch_condition_mnemonic (rtx code
, int inv
)
1039 static const char *const mnemonic
[16] =
1041 NULL
, "o", "h", "nle",
1042 "l", "nhe", "lh", "ne",
1043 "e", "nlh", "he", "nl",
1044 "le", "nh", "no", NULL
1047 int mask
= s390_branch_condition_mask (code
);
1048 gcc_assert (mask
>= 0);
1053 gcc_assert (mask
>= 1 && mask
<= 14);
1055 return mnemonic
[mask
];
1058 /* Return the part of op which has a value different from def.
1059 The size of the part is determined by mode.
1060 Use this function only if you already know that op really
1061 contains such a part. */
1063 unsigned HOST_WIDE_INT
1064 s390_extract_part (rtx op
, enum machine_mode mode
, int def
)
1066 unsigned HOST_WIDE_INT value
= 0;
1067 int max_parts
= HOST_BITS_PER_WIDE_INT
/ GET_MODE_BITSIZE (mode
);
1068 int part_bits
= GET_MODE_BITSIZE (mode
);
1069 unsigned HOST_WIDE_INT part_mask
1070 = ((unsigned HOST_WIDE_INT
)1 << part_bits
) - 1;
1073 for (i
= 0; i
< max_parts
; i
++)
1076 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1078 value
>>= part_bits
;
1080 if ((value
& part_mask
) != (def
& part_mask
))
1081 return value
& part_mask
;
1087 /* If OP is an integer constant of mode MODE with exactly one
1088 part of mode PART_MODE unequal to DEF, return the number of that
1089 part. Otherwise, return -1. */
1092 s390_single_part (rtx op
,
1093 enum machine_mode mode
,
1094 enum machine_mode part_mode
,
1097 unsigned HOST_WIDE_INT value
= 0;
1098 int n_parts
= GET_MODE_SIZE (mode
) / GET_MODE_SIZE (part_mode
);
1099 unsigned HOST_WIDE_INT part_mask
1100 = ((unsigned HOST_WIDE_INT
)1 << GET_MODE_BITSIZE (part_mode
)) - 1;
1103 if (GET_CODE (op
) != CONST_INT
)
1106 for (i
= 0; i
< n_parts
; i
++)
1109 value
= (unsigned HOST_WIDE_INT
) INTVAL (op
);
1111 value
>>= GET_MODE_BITSIZE (part_mode
);
1113 if ((value
& part_mask
) != (def
& part_mask
))
1121 return part
== -1 ? -1 : n_parts
- 1 - part
;
1124 /* Check whether we can (and want to) split a double-word
1125 move in mode MODE from SRC to DST into two single-word
1126 moves, moving the subword FIRST_SUBWORD first. */
1129 s390_split_ok_p (rtx dst
, rtx src
, enum machine_mode mode
, int first_subword
)
1131 /* Floating point registers cannot be split. */
1132 if (FP_REG_P (src
) || FP_REG_P (dst
))
1135 /* We don't need to split if operands are directly accessible. */
1136 if (s_operand (src
, mode
) || s_operand (dst
, mode
))
1139 /* Non-offsettable memory references cannot be split. */
1140 if ((GET_CODE (src
) == MEM
&& !offsettable_memref_p (src
))
1141 || (GET_CODE (dst
) == MEM
&& !offsettable_memref_p (dst
)))
1144 /* Moving the first subword must not clobber a register
1145 needed to move the second subword. */
1146 if (register_operand (dst
, mode
))
1148 rtx subreg
= operand_subword (dst
, first_subword
, 0, mode
);
1149 if (reg_overlap_mentioned_p (subreg
, src
))
1156 /* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1157 and [MEM2, MEM2 + SIZE] do overlap and false
1161 s390_overlap_p (rtx mem1
, rtx mem2
, HOST_WIDE_INT size
)
1163 rtx addr1
, addr2
, addr_delta
;
1164 HOST_WIDE_INT delta
;
1166 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1172 addr1
= XEXP (mem1
, 0);
1173 addr2
= XEXP (mem2
, 0);
1175 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1177 /* This overlapping check is used by peepholes merging memory block operations.
1178 Overlapping operations would otherwise be recognized by the S/390 hardware
1179 and would fall back to a slower implementation. Allowing overlapping
1180 operations would lead to slow code but not to wrong code. Therefore we are
1181 somewhat optimistic if we cannot prove that the memory blocks are
1183 That's why we return false here although this may accept operations on
1184 overlapping memory areas. */
1185 if (!addr_delta
|| GET_CODE (addr_delta
) != CONST_INT
)
1188 delta
= INTVAL (addr_delta
);
1191 || (delta
> 0 && delta
< size
)
1192 || (delta
< 0 && -delta
< size
))
1198 /* Check whether the address of memory reference MEM2 equals exactly
1199 the address of memory reference MEM1 plus DELTA. Return true if
1200 we can prove this to be the case, false otherwise. */
1203 s390_offset_p (rtx mem1
, rtx mem2
, rtx delta
)
1205 rtx addr1
, addr2
, addr_delta
;
1207 if (GET_CODE (mem1
) != MEM
|| GET_CODE (mem2
) != MEM
)
1210 addr1
= XEXP (mem1
, 0);
1211 addr2
= XEXP (mem2
, 0);
1213 addr_delta
= simplify_binary_operation (MINUS
, Pmode
, addr2
, addr1
);
1214 if (!addr_delta
|| !rtx_equal_p (addr_delta
, delta
))
1220 /* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1223 s390_expand_logical_operator (enum rtx_code code
, enum machine_mode mode
,
1226 enum machine_mode wmode
= mode
;
1227 rtx dst
= operands
[0];
1228 rtx src1
= operands
[1];
1229 rtx src2
= operands
[2];
1232 /* If we cannot handle the operation directly, use a temp register. */
1233 if (!s390_logical_operator_ok_p (operands
))
1234 dst
= gen_reg_rtx (mode
);
1236 /* QImode and HImode patterns make sense only if we have a destination
1237 in memory. Otherwise perform the operation in SImode. */
1238 if ((mode
== QImode
|| mode
== HImode
) && GET_CODE (dst
) != MEM
)
1241 /* Widen operands if required. */
1244 if (GET_CODE (dst
) == SUBREG
1245 && (tem
= simplify_subreg (wmode
, dst
, mode
, 0)) != 0)
1247 else if (REG_P (dst
))
1248 dst
= gen_rtx_SUBREG (wmode
, dst
, 0);
1250 dst
= gen_reg_rtx (wmode
);
1252 if (GET_CODE (src1
) == SUBREG
1253 && (tem
= simplify_subreg (wmode
, src1
, mode
, 0)) != 0)
1255 else if (GET_MODE (src1
) != VOIDmode
)
1256 src1
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src1
), 0);
1258 if (GET_CODE (src2
) == SUBREG
1259 && (tem
= simplify_subreg (wmode
, src2
, mode
, 0)) != 0)
1261 else if (GET_MODE (src2
) != VOIDmode
)
1262 src2
= gen_rtx_SUBREG (wmode
, force_reg (mode
, src2
), 0);
1265 /* Emit the instruction. */
1266 op
= gen_rtx_SET (VOIDmode
, dst
, gen_rtx_fmt_ee (code
, wmode
, src1
, src2
));
1267 clob
= gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
1268 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, op
, clob
)));
1270 /* Fix up the destination if needed. */
1271 if (dst
!= operands
[0])
1272 emit_move_insn (operands
[0], gen_lowpart (mode
, dst
));
1275 /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1278 s390_logical_operator_ok_p (rtx
*operands
)
1280 /* If the destination operand is in memory, it needs to coincide
1281 with one of the source operands. After reload, it has to be
1282 the first source operand. */
1283 if (GET_CODE (operands
[0]) == MEM
)
1284 return rtx_equal_p (operands
[0], operands
[1])
1285 || (!reload_completed
&& rtx_equal_p (operands
[0], operands
[2]));
1290 /* Narrow logical operation CODE of memory operand MEMOP with immediate
1291 operand IMMOP to switch from SS to SI type instructions. */
1294 s390_narrow_logical_operator (enum rtx_code code
, rtx
*memop
, rtx
*immop
)
1296 int def
= code
== AND
? -1 : 0;
1300 gcc_assert (GET_CODE (*memop
) == MEM
);
1301 gcc_assert (!MEM_VOLATILE_P (*memop
));
1303 mask
= s390_extract_part (*immop
, QImode
, def
);
1304 part
= s390_single_part (*immop
, GET_MODE (*memop
), QImode
, def
);
1305 gcc_assert (part
>= 0);
1307 *memop
= adjust_address (*memop
, QImode
, part
);
1308 *immop
= gen_int_mode (mask
, QImode
);
1312 /* How to allocate a 'struct machine_function'. */
1314 static struct machine_function
*
1315 s390_init_machine_status (void)
1317 return ggc_alloc_cleared (sizeof (struct machine_function
));
1320 /* Change optimizations to be performed, depending on the
1323 LEVEL is the optimization level specified; 2 if `-O2' is
1324 specified, 1 if `-O' is specified, and 0 if neither is specified.
1326 SIZE is nonzero if `-Os' is specified and zero otherwise. */
1329 optimization_options (int level ATTRIBUTE_UNUSED
, int size ATTRIBUTE_UNUSED
)
1331 /* ??? There are apparently still problems with -fcaller-saves. */
1332 flag_caller_saves
= 0;
1334 /* By default, always emit DWARF-2 unwind info. This allows debugging
1335 without maintaining a stack frame back-chain. */
1336 flag_asynchronous_unwind_tables
= 1;
1338 /* Use MVCLE instructions to decrease code size if requested. */
1340 target_flags
|= MASK_MVCLE
;
1343 /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS
1344 to the associated processor_type and processor_flags if so. */
1347 s390_handle_arch_option (const char *arg
,
1348 enum processor_type
*type
,
1349 enum processor_flags
*flags
)
1353 const char *const name
; /* processor name or nickname. */
1354 const enum processor_type processor
;
1355 const enum processor_flags flags
;
1357 const processor_alias_table
[] =
1359 {"g5", PROCESSOR_9672_G5
, PF_IEEE_FLOAT
},
1360 {"g6", PROCESSOR_9672_G6
, PF_IEEE_FLOAT
},
1361 {"z900", PROCESSOR_2064_Z900
, PF_IEEE_FLOAT
| PF_ZARCH
},
1362 {"z990", PROCESSOR_2084_Z990
, PF_IEEE_FLOAT
| PF_ZARCH
1363 | PF_LONG_DISPLACEMENT
},
1364 {"z9-109", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1365 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
},
1366 {"z9-ec", PROCESSOR_2094_Z9_109
, PF_IEEE_FLOAT
| PF_ZARCH
1367 | PF_LONG_DISPLACEMENT
| PF_EXTIMM
| PF_DFP
},
1371 for (i
= 0; i
< ARRAY_SIZE (processor_alias_table
); i
++)
1372 if (strcmp (arg
, processor_alias_table
[i
].name
) == 0)
1374 *type
= processor_alias_table
[i
].processor
;
1375 *flags
= processor_alias_table
[i
].flags
;
1381 /* Implement TARGET_HANDLE_OPTION. */
1384 s390_handle_option (size_t code
, const char *arg
, int value ATTRIBUTE_UNUSED
)
1389 return s390_handle_arch_option (arg
, &s390_arch
, &s390_arch_flags
);
1391 case OPT_mstack_guard_
:
1392 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_guard
) != 1)
1394 if (exact_log2 (s390_stack_guard
) == -1)
1395 error ("stack guard value must be an exact power of 2");
1398 case OPT_mstack_size_
:
1399 if (sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_stack_size
) != 1)
1401 if (exact_log2 (s390_stack_size
) == -1)
1402 error ("stack size must be an exact power of 2");
1406 return s390_handle_arch_option (arg
, &s390_tune
, &s390_tune_flags
);
1408 case OPT_mwarn_framesize_
:
1409 return sscanf (arg
, HOST_WIDE_INT_PRINT_DEC
, &s390_warn_framesize
) == 1;
1417 override_options (void)
1419 /* Set up function hooks. */
1420 init_machine_status
= s390_init_machine_status
;
1422 /* Architecture mode defaults according to ABI. */
1423 if (!(target_flags_explicit
& MASK_ZARCH
))
1426 target_flags
|= MASK_ZARCH
;
1428 target_flags
&= ~MASK_ZARCH
;
1431 /* Determine processor architectural level. */
1432 if (!s390_arch_string
)
1434 s390_arch_string
= TARGET_ZARCH
? "z900" : "g5";
1435 s390_handle_arch_option (s390_arch_string
, &s390_arch
, &s390_arch_flags
);
1438 /* Determine processor to tune for. */
1439 if (s390_tune
== PROCESSOR_max
)
1441 s390_tune
= s390_arch
;
1442 s390_tune_flags
= s390_arch_flags
;
1445 /* Sanity checks. */
1446 if (TARGET_ZARCH
&& !TARGET_CPU_ZARCH
)
1447 error ("z/Architecture mode not supported on %s", s390_arch_string
);
1448 if (TARGET_64BIT
&& !TARGET_ZARCH
)
1449 error ("64-bit ABI not supported in ESA/390 mode");
1451 if (TARGET_HARD_DFP
&& (!TARGET_CPU_DFP
|| !TARGET_ZARCH
))
1453 if (target_flags_explicit
& MASK_SOFT_DFP
)
1455 if (!TARGET_CPU_DFP
)
1456 error ("Hardware decimal floating point instructions"
1457 " not available on %s", s390_arch_string
);
1459 error ("Hardware decimal floating point instructions"
1460 " not available in ESA/390 mode");
1463 target_flags
|= MASK_SOFT_DFP
;
1466 if ((target_flags_explicit
& MASK_SOFT_FLOAT
) && TARGET_SOFT_FLOAT
)
1468 if ((target_flags_explicit
& MASK_SOFT_DFP
) && TARGET_HARD_DFP
)
1469 error ("-mhard-dfp can't be used in conjunction with -msoft-float");
1471 target_flags
|= MASK_SOFT_DFP
;
1474 /* Set processor cost function. */
1475 if (s390_tune
== PROCESSOR_2094_Z9_109
)
1476 s390_cost
= &z9_109_cost
;
1477 else if (s390_tune
== PROCESSOR_2084_Z990
)
1478 s390_cost
= &z990_cost
;
1480 s390_cost
= &z900_cost
;
1482 if (TARGET_BACKCHAIN
&& TARGET_PACKED_STACK
&& TARGET_HARD_FLOAT
)
1483 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
1486 if (s390_stack_size
)
1488 if (s390_stack_guard
>= s390_stack_size
)
1489 error ("stack size must be greater than the stack guard value");
1490 else if (s390_stack_size
> 1 << 16)
1491 error ("stack size must not be greater than 64k");
1493 else if (s390_stack_guard
)
1494 error ("-mstack-guard implies use of -mstack-size");
1496 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1497 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1498 target_flags
|= MASK_LONG_DOUBLE_128
;
1502 /* Map for smallest class containing reg regno. */
1504 const enum reg_class regclass_map
[FIRST_PSEUDO_REGISTER
] =
1505 { GENERAL_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1506 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1507 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1508 ADDR_REGS
, ADDR_REGS
, ADDR_REGS
, ADDR_REGS
,
1509 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1510 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1511 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1512 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
1513 ADDR_REGS
, CC_REGS
, ADDR_REGS
, ADDR_REGS
,
1514 ACCESS_REGS
, ACCESS_REGS
1517 /* Return attribute type of insn. */
1519 static enum attr_type
1520 s390_safe_attr_type (rtx insn
)
1522 if (recog_memoized (insn
) >= 0)
1523 return get_attr_type (insn
);
1528 /* Return true if DISP is a valid short displacement. */
1531 s390_short_displacement (rtx disp
)
1533 /* No displacement is OK. */
1537 /* Integer displacement in range. */
1538 if (GET_CODE (disp
) == CONST_INT
)
1539 return INTVAL (disp
) >= 0 && INTVAL (disp
) < 4096;
1541 /* GOT offset is not OK, the GOT can be large. */
1542 if (GET_CODE (disp
) == CONST
1543 && GET_CODE (XEXP (disp
, 0)) == UNSPEC
1544 && (XINT (XEXP (disp
, 0), 1) == UNSPEC_GOT
1545 || XINT (XEXP (disp
, 0), 1) == UNSPEC_GOTNTPOFF
))
1548 /* All other symbolic constants are literal pool references,
1549 which are OK as the literal pool must be small. */
1550 if (GET_CODE (disp
) == CONST
)
1556 /* Decompose a RTL expression ADDR for a memory address into
1557 its components, returned in OUT.
1559 Returns false if ADDR is not a valid memory address, true
1560 otherwise. If OUT is NULL, don't return the components,
1561 but check for validity only.
1563 Note: Only addresses in canonical form are recognized.
1564 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1565 canonical form so that they will be recognized. */
1568 s390_decompose_address (rtx addr
, struct s390_address
*out
)
1570 HOST_WIDE_INT offset
= 0;
1571 rtx base
= NULL_RTX
;
1572 rtx indx
= NULL_RTX
;
1573 rtx disp
= NULL_RTX
;
1575 bool pointer
= false;
1576 bool base_ptr
= false;
1577 bool indx_ptr
= false;
1578 bool literal_pool
= false;
1580 /* We may need to substitute the literal pool base register into the address
1581 below. However, at this point we do not know which register is going to
1582 be used as base, so we substitute the arg pointer register. This is going
1583 to be treated as holding a pointer below -- it shouldn't be used for any
1585 rtx fake_pool_base
= gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
);
1587 /* Decompose address into base + index + displacement. */
1589 if (GET_CODE (addr
) == REG
|| GET_CODE (addr
) == UNSPEC
)
1592 else if (GET_CODE (addr
) == PLUS
)
1594 rtx op0
= XEXP (addr
, 0);
1595 rtx op1
= XEXP (addr
, 1);
1596 enum rtx_code code0
= GET_CODE (op0
);
1597 enum rtx_code code1
= GET_CODE (op1
);
1599 if (code0
== REG
|| code0
== UNSPEC
)
1601 if (code1
== REG
|| code1
== UNSPEC
)
1603 indx
= op0
; /* index + base */
1609 base
= op0
; /* base + displacement */
1614 else if (code0
== PLUS
)
1616 indx
= XEXP (op0
, 0); /* index + base + disp */
1617 base
= XEXP (op0
, 1);
1628 disp
= addr
; /* displacement */
1630 /* Extract integer part of displacement. */
1634 if (GET_CODE (disp
) == CONST_INT
)
1636 offset
= INTVAL (disp
);
1639 else if (GET_CODE (disp
) == CONST
1640 && GET_CODE (XEXP (disp
, 0)) == PLUS
1641 && GET_CODE (XEXP (XEXP (disp
, 0), 1)) == CONST_INT
)
1643 offset
= INTVAL (XEXP (XEXP (disp
, 0), 1));
1644 disp
= XEXP (XEXP (disp
, 0), 0);
1648 /* Strip off CONST here to avoid special case tests later. */
1649 if (disp
&& GET_CODE (disp
) == CONST
)
1650 disp
= XEXP (disp
, 0);
1652 /* We can convert literal pool addresses to
1653 displacements by basing them off the base register. */
1654 if (disp
&& GET_CODE (disp
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (disp
))
1656 /* Either base or index must be free to hold the base register. */
1658 base
= fake_pool_base
, literal_pool
= true;
1660 indx
= fake_pool_base
, literal_pool
= true;
1664 /* Mark up the displacement. */
1665 disp
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, disp
),
1666 UNSPEC_LTREL_OFFSET
);
1669 /* Validate base register. */
1672 if (GET_CODE (base
) == UNSPEC
)
1673 switch (XINT (base
, 1))
1677 disp
= gen_rtx_UNSPEC (Pmode
,
1678 gen_rtvec (1, XVECEXP (base
, 0, 0)),
1679 UNSPEC_LTREL_OFFSET
);
1683 base
= XVECEXP (base
, 0, 1);
1686 case UNSPEC_LTREL_BASE
:
1687 if (XVECLEN (base
, 0) == 1)
1688 base
= fake_pool_base
, literal_pool
= true;
1690 base
= XVECEXP (base
, 0, 1);
1698 || (GET_MODE (base
) != SImode
1699 && GET_MODE (base
) != Pmode
))
1702 if (REGNO (base
) == STACK_POINTER_REGNUM
1703 || REGNO (base
) == FRAME_POINTER_REGNUM
1704 || ((reload_completed
|| reload_in_progress
)
1705 && frame_pointer_needed
1706 && REGNO (base
) == HARD_FRAME_POINTER_REGNUM
)
1707 || REGNO (base
) == ARG_POINTER_REGNUM
1709 && REGNO (base
) == PIC_OFFSET_TABLE_REGNUM
))
1710 pointer
= base_ptr
= true;
1712 if ((reload_completed
|| reload_in_progress
)
1713 && base
== cfun
->machine
->base_reg
)
1714 pointer
= base_ptr
= literal_pool
= true;
1717 /* Validate index register. */
1720 if (GET_CODE (indx
) == UNSPEC
)
1721 switch (XINT (indx
, 1))
1725 disp
= gen_rtx_UNSPEC (Pmode
,
1726 gen_rtvec (1, XVECEXP (indx
, 0, 0)),
1727 UNSPEC_LTREL_OFFSET
);
1731 indx
= XVECEXP (indx
, 0, 1);
1734 case UNSPEC_LTREL_BASE
:
1735 if (XVECLEN (indx
, 0) == 1)
1736 indx
= fake_pool_base
, literal_pool
= true;
1738 indx
= XVECEXP (indx
, 0, 1);
1746 || (GET_MODE (indx
) != SImode
1747 && GET_MODE (indx
) != Pmode
))
1750 if (REGNO (indx
) == STACK_POINTER_REGNUM
1751 || REGNO (indx
) == FRAME_POINTER_REGNUM
1752 || ((reload_completed
|| reload_in_progress
)
1753 && frame_pointer_needed
1754 && REGNO (indx
) == HARD_FRAME_POINTER_REGNUM
)
1755 || REGNO (indx
) == ARG_POINTER_REGNUM
1757 && REGNO (indx
) == PIC_OFFSET_TABLE_REGNUM
))
1758 pointer
= indx_ptr
= true;
1760 if ((reload_completed
|| reload_in_progress
)
1761 && indx
== cfun
->machine
->base_reg
)
1762 pointer
= indx_ptr
= literal_pool
= true;
1765 /* Prefer to use pointer as base, not index. */
1766 if (base
&& indx
&& !base_ptr
1767 && (indx_ptr
|| (!REG_POINTER (base
) && REG_POINTER (indx
))))
1774 /* Validate displacement. */
1777 /* If virtual registers are involved, the displacement will change later
1778 anyway as the virtual registers get eliminated. This could make a
1779 valid displacement invalid, but it is more likely to make an invalid
1780 displacement valid, because we sometimes access the register save area
1781 via negative offsets to one of those registers.
1782 Thus we don't check the displacement for validity here. If after
1783 elimination the displacement turns out to be invalid after all,
1784 this is fixed up by reload in any case. */
1785 if (base
!= arg_pointer_rtx
1786 && indx
!= arg_pointer_rtx
1787 && base
!= return_address_pointer_rtx
1788 && indx
!= return_address_pointer_rtx
1789 && base
!= frame_pointer_rtx
1790 && indx
!= frame_pointer_rtx
1791 && base
!= virtual_stack_vars_rtx
1792 && indx
!= virtual_stack_vars_rtx
)
1793 if (!DISP_IN_RANGE (offset
))
1798 /* All the special cases are pointers. */
1801 /* In the small-PIC case, the linker converts @GOT
1802 and @GOTNTPOFF offsets to possible displacements. */
1803 if (GET_CODE (disp
) == UNSPEC
1804 && (XINT (disp
, 1) == UNSPEC_GOT
1805 || XINT (disp
, 1) == UNSPEC_GOTNTPOFF
)
1811 /* Accept chunkified literal pool symbol references. */
1812 else if (cfun
&& cfun
->machine
1813 && cfun
->machine
->decomposed_literal_pool_addresses_ok_p
1814 && GET_CODE (disp
) == MINUS
1815 && GET_CODE (XEXP (disp
, 0)) == LABEL_REF
1816 && GET_CODE (XEXP (disp
, 1)) == LABEL_REF
)
1821 /* Accept literal pool references. */
1822 else if (GET_CODE (disp
) == UNSPEC
1823 && XINT (disp
, 1) == UNSPEC_LTREL_OFFSET
)
1825 orig_disp
= gen_rtx_CONST (Pmode
, disp
);
1828 /* If we have an offset, make sure it does not
1829 exceed the size of the constant pool entry. */
1830 rtx sym
= XVECEXP (disp
, 0, 0);
1831 if (offset
>= GET_MODE_SIZE (get_pool_mode (sym
)))
1834 orig_disp
= plus_constant (orig_disp
, offset
);
1849 out
->disp
= orig_disp
;
1850 out
->pointer
= pointer
;
1851 out
->literal_pool
= literal_pool
;
1857 /* Decompose a RTL expression OP for a shift count into its components,
1858 and return the base register in BASE and the offset in OFFSET.
1860 Return true if OP is a valid shift count, false if not. */
1863 s390_decompose_shift_count (rtx op
, rtx
*base
, HOST_WIDE_INT
*offset
)
1865 HOST_WIDE_INT off
= 0;
1867 /* We can have an integer constant, an address register,
1868 or a sum of the two. */
1869 if (GET_CODE (op
) == CONST_INT
)
1874 if (op
&& GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
)
1876 off
= INTVAL (XEXP (op
, 1));
1879 while (op
&& GET_CODE (op
) == SUBREG
)
1880 op
= SUBREG_REG (op
);
1882 if (op
&& GET_CODE (op
) != REG
)
1894 /* Return true if CODE is a valid address without index. */
1897 s390_legitimate_address_without_index_p (rtx op
)
1899 struct s390_address addr
;
1901 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1910 /* Evaluates constraint strings described by the regular expression
1911 ([A|B](Q|R|S|T))|U|W and returns 1 if OP is a valid operand for the
1912 constraint given in STR, or 0 else. */
1915 s390_mem_constraint (const char *str
, rtx op
)
1917 struct s390_address addr
;
1920 /* Check for offsettable variants of memory constraints. */
1923 /* Only accept non-volatile MEMs. */
1924 if (!MEM_P (op
) || MEM_VOLATILE_P (op
))
1927 if ((reload_completed
|| reload_in_progress
)
1928 ? !offsettable_memref_p (op
) : !offsettable_nonstrict_memref_p (op
))
1934 /* Check for non-literal-pool variants of memory constraints. */
1937 if (GET_CODE (op
) != MEM
)
1939 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1941 if (addr
.literal_pool
)
1950 if (GET_CODE (op
) != MEM
)
1952 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1957 if (TARGET_LONG_DISPLACEMENT
)
1959 if (!s390_short_displacement (addr
.disp
))
1965 if (GET_CODE (op
) != MEM
)
1968 if (TARGET_LONG_DISPLACEMENT
)
1970 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1972 if (!s390_short_displacement (addr
.disp
))
1978 if (!TARGET_LONG_DISPLACEMENT
)
1980 if (GET_CODE (op
) != MEM
)
1982 if (!s390_decompose_address (XEXP (op
, 0), &addr
))
1986 if (s390_short_displacement (addr
.disp
))
1991 if (!TARGET_LONG_DISPLACEMENT
)
1993 if (GET_CODE (op
) != MEM
)
1995 /* Any invalid address here will be fixed up by reload,
1996 so accept it for the most generic constraint. */
1997 if (s390_decompose_address (XEXP (op
, 0), &addr
)
1998 && s390_short_displacement (addr
.disp
))
2003 if (TARGET_LONG_DISPLACEMENT
)
2005 if (!s390_decompose_address (op
, &addr
))
2007 if (!s390_short_displacement (addr
.disp
))
2013 if (!TARGET_LONG_DISPLACEMENT
)
2015 /* Any invalid address here will be fixed up by reload,
2016 so accept it for the most generic constraint. */
2017 if (s390_decompose_address (op
, &addr
)
2018 && s390_short_displacement (addr
.disp
))
2023 /* Simply check for the basic form of a shift count. Reload will
2024 take care of making sure we have a proper base register. */
2025 if (!s390_decompose_shift_count (op
, NULL
, NULL
))
2038 /* Evaluates constraint strings starting with letter O. Input
2039 parameter C is the second letter following the "O" in the constraint
2040 string. Returns 1 if VALUE meets the respective constraint and 0
2044 s390_O_constraint_str (const char c
, HOST_WIDE_INT value
)
2052 return trunc_int_for_mode (value
, SImode
) == value
;
2056 || s390_single_part (GEN_INT (value
), DImode
, SImode
, 0) == 1;
2060 || s390_single_part (GEN_INT (value
), DImode
, SImode
, -1) == 1;
2068 /* Evaluates constraint strings starting with letter N. Parameter STR
2069 contains the letters following letter "N" in the constraint string.
2070 Returns true if VALUE matches the constraint. */
2073 s390_N_constraint_str (const char *str
, HOST_WIDE_INT value
)
2075 enum machine_mode mode
, part_mode
;
2077 int part
, part_goal
;
2083 part_goal
= str
[0] - '0';
2127 if (GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (part_mode
))
2130 part
= s390_single_part (GEN_INT (value
), mode
, part_mode
, def
);
2133 if (part_goal
!= -1 && part_goal
!= part
)
2140 /* Returns true if the input parameter VALUE is a float zero. */
2143 s390_float_const_zero_p (rtx value
)
2145 return (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
2146 && value
== CONST0_RTX (GET_MODE (value
)));
2150 /* Compute a (partial) cost for rtx X. Return true if the complete
2151 cost has been computed, and false if subexpressions should be
2152 scanned. In either case, *TOTAL contains the cost result.
2153 CODE contains GET_CODE (x), OUTER_CODE contains the code
2154 of the superexpression of x. */
2157 s390_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2180 *total
= COSTS_N_INSNS (1);
2185 /* Check for multiply and add. */
2186 if ((GET_MODE (x
) == DFmode
|| GET_MODE (x
) == SFmode
)
2187 && GET_CODE (XEXP (x
, 0)) == MULT
2188 && TARGET_HARD_FLOAT
&& TARGET_FUSED_MADD
)
2190 /* This is the multiply and add case. */
2191 if (GET_MODE (x
) == DFmode
)
2192 *total
= s390_cost
->madbr
;
2194 *total
= s390_cost
->maebr
;
2195 *total
+= rtx_cost (XEXP (XEXP (x
, 0), 0), MULT
)
2196 + rtx_cost (XEXP (XEXP (x
, 0), 1), MULT
)
2197 + rtx_cost (XEXP (x
, 1), code
);
2198 return true; /* Do not do an additional recursive descent. */
2200 *total
= COSTS_N_INSNS (1);
2204 switch (GET_MODE (x
))
2208 rtx left
= XEXP (x
, 0);
2209 rtx right
= XEXP (x
, 1);
2210 if (GET_CODE (right
) == CONST_INT
2211 && CONST_OK_FOR_K (INTVAL (right
)))
2212 *total
= s390_cost
->mhi
;
2213 else if (GET_CODE (left
) == SIGN_EXTEND
)
2214 *total
= s390_cost
->mh
;
2216 *total
= s390_cost
->ms
; /* msr, ms, msy */
2221 rtx left
= XEXP (x
, 0);
2222 rtx right
= XEXP (x
, 1);
2225 if (GET_CODE (right
) == CONST_INT
2226 && CONST_OK_FOR_K (INTVAL (right
)))
2227 *total
= s390_cost
->mghi
;
2228 else if (GET_CODE (left
) == SIGN_EXTEND
)
2229 *total
= s390_cost
->msgf
;
2231 *total
= s390_cost
->msg
; /* msgr, msg */
2233 else /* TARGET_31BIT */
2235 if (GET_CODE (left
) == SIGN_EXTEND
2236 && GET_CODE (right
) == SIGN_EXTEND
)
2237 /* mulsidi case: mr, m */
2238 *total
= s390_cost
->m
;
2239 else if (GET_CODE (left
) == ZERO_EXTEND
2240 && GET_CODE (right
) == ZERO_EXTEND
2241 && TARGET_CPU_ZARCH
)
2242 /* umulsidi case: ml, mlr */
2243 *total
= s390_cost
->ml
;
2245 /* Complex calculation is required. */
2246 *total
= COSTS_N_INSNS (40);
2252 *total
= s390_cost
->mult_df
;
2255 *total
= s390_cost
->mxbr
;
2264 if (GET_MODE (x
) == TImode
) /* 128 bit division */
2265 *total
= s390_cost
->dlgr
;
2266 else if (GET_MODE (x
) == DImode
)
2268 rtx right
= XEXP (x
, 1);
2269 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2270 *total
= s390_cost
->dlr
;
2271 else /* 64 by 64 bit division */
2272 *total
= s390_cost
->dlgr
;
2274 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2275 *total
= s390_cost
->dlr
;
2280 if (GET_MODE (x
) == DImode
)
2282 rtx right
= XEXP (x
, 1);
2283 if (GET_CODE (right
) == ZERO_EXTEND
) /* 64 by 32 bit division */
2285 *total
= s390_cost
->dsgfr
;
2287 *total
= s390_cost
->dr
;
2288 else /* 64 by 64 bit division */
2289 *total
= s390_cost
->dsgr
;
2291 else if (GET_MODE (x
) == SImode
) /* 32 bit division */
2292 *total
= s390_cost
->dlr
;
2293 else if (GET_MODE (x
) == SFmode
)
2295 *total
= s390_cost
->debr
;
2297 else if (GET_MODE (x
) == DFmode
)
2299 *total
= s390_cost
->ddbr
;
2301 else if (GET_MODE (x
) == TFmode
)
2303 *total
= s390_cost
->dxbr
;
2308 if (GET_MODE (x
) == SFmode
)
2309 *total
= s390_cost
->sqebr
;
2310 else if (GET_MODE (x
) == DFmode
)
2311 *total
= s390_cost
->sqdbr
;
2313 *total
= s390_cost
->sqxbr
;
2318 if (outer_code
== MULT
|| outer_code
== DIV
|| outer_code
== MOD
2319 || outer_code
== PLUS
|| outer_code
== MINUS
2320 || outer_code
== COMPARE
)
2325 *total
= COSTS_N_INSNS (1);
2326 if (GET_CODE (XEXP (x
, 0)) == AND
2327 && GET_CODE (XEXP (x
, 1)) == CONST_INT
2328 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)
2330 rtx op0
= XEXP (XEXP (x
, 0), 0);
2331 rtx op1
= XEXP (XEXP (x
, 0), 1);
2332 rtx op2
= XEXP (x
, 1);
2334 if (memory_operand (op0
, GET_MODE (op0
))
2335 && s390_tm_ccmode (op1
, op2
, 0) != VOIDmode
)
2337 if (register_operand (op0
, GET_MODE (op0
))
2338 && s390_tm_ccmode (op1
, op2
, 1) != VOIDmode
)
2348 /* Return the cost of an address rtx ADDR. */
2351 s390_address_cost (rtx addr
)
2353 struct s390_address ad
;
2354 if (!s390_decompose_address (addr
, &ad
))
2357 return ad
.indx
? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2360 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2361 otherwise return 0. */
2364 tls_symbolic_operand (rtx op
)
2366 if (GET_CODE (op
) != SYMBOL_REF
)
2368 return SYMBOL_REF_TLS_MODEL (op
);
2371 /* Split DImode access register reference REG (on 64-bit) into its constituent
2372 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2373 gen_highpart cannot be used as they assume all registers are word-sized,
2374 while our access registers have only half that size. */
2377 s390_split_access_reg (rtx reg
, rtx
*lo
, rtx
*hi
)
2379 gcc_assert (TARGET_64BIT
);
2380 gcc_assert (ACCESS_REG_P (reg
));
2381 gcc_assert (GET_MODE (reg
) == DImode
);
2382 gcc_assert (!(REGNO (reg
) & 1));
2384 *lo
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
2385 *hi
= gen_rtx_REG (SImode
, REGNO (reg
));
2388 /* Return true if OP contains a symbol reference */
2391 symbolic_reference_mentioned_p (rtx op
)
2396 if (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == LABEL_REF
)
2399 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2400 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2406 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2407 if (symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2411 else if (fmt
[i
] == 'e' && symbolic_reference_mentioned_p (XEXP (op
, i
)))
2418 /* Return true if OP contains a reference to a thread-local symbol. */
2421 tls_symbolic_reference_mentioned_p (rtx op
)
2426 if (GET_CODE (op
) == SYMBOL_REF
)
2427 return tls_symbolic_operand (op
);
2429 fmt
= GET_RTX_FORMAT (GET_CODE (op
));
2430 for (i
= GET_RTX_LENGTH (GET_CODE (op
)) - 1; i
>= 0; i
--)
2436 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
2437 if (tls_symbolic_reference_mentioned_p (XVECEXP (op
, i
, j
)))
2441 else if (fmt
[i
] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op
, i
)))
2449 /* Return true if OP is a legitimate general operand when
2450 generating PIC code. It is given that flag_pic is on
2451 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2454 legitimate_pic_operand_p (rtx op
)
2456 /* Accept all non-symbolic constants. */
2457 if (!SYMBOLIC_CONST (op
))
2460 /* Reject everything else; must be handled
2461 via emit_symbolic_move. */
2465 /* Returns true if the constant value OP is a legitimate general operand.
2466 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2469 legitimate_constant_p (rtx op
)
2471 /* Accept all non-symbolic constants. */
2472 if (!SYMBOLIC_CONST (op
))
2475 /* Accept immediate LARL operands. */
2476 if (TARGET_CPU_ZARCH
&& larl_operand (op
, VOIDmode
))
2479 /* Thread-local symbols are never legal constants. This is
2480 so that emit_call knows that computing such addresses
2481 might require a function call. */
2482 if (TLS_SYMBOLIC_CONST (op
))
2485 /* In the PIC case, symbolic constants must *not* be
2486 forced into the literal pool. We accept them here,
2487 so that they will be handled by emit_symbolic_move. */
2491 /* All remaining non-PIC symbolic constants are
2492 forced into the literal pool. */
2496 /* Determine if it's legal to put X into the constant pool. This
2497 is not possible if X contains the address of a symbol that is
2498 not constant (TLS) or not known at final link time (PIC). */
2501 s390_cannot_force_const_mem (rtx x
)
2503 switch (GET_CODE (x
))
2507 /* Accept all non-symbolic constants. */
2511 /* Labels are OK iff we are non-PIC. */
2512 return flag_pic
!= 0;
2515 /* 'Naked' TLS symbol references are never OK,
2516 non-TLS symbols are OK iff we are non-PIC. */
2517 if (tls_symbolic_operand (x
))
2520 return flag_pic
!= 0;
2523 return s390_cannot_force_const_mem (XEXP (x
, 0));
2526 return s390_cannot_force_const_mem (XEXP (x
, 0))
2527 || s390_cannot_force_const_mem (XEXP (x
, 1));
2530 switch (XINT (x
, 1))
2532 /* Only lt-relative or GOT-relative UNSPECs are OK. */
2533 case UNSPEC_LTREL_OFFSET
:
2541 case UNSPEC_GOTNTPOFF
:
2542 case UNSPEC_INDNTPOFF
:
2545 /* If the literal pool shares the code section, be put
2546 execute template placeholders into the pool as well. */
2548 return TARGET_CPU_ZARCH
;
2560 /* Returns true if the constant value OP is a legitimate general
2561 operand during and after reload. The difference to
2562 legitimate_constant_p is that this function will not accept
2563 a constant that would need to be forced to the literal pool
2564 before it can be used as operand. */
2567 legitimate_reload_constant_p (rtx op
)
2569 /* Accept la(y) operands. */
2570 if (GET_CODE (op
) == CONST_INT
2571 && DISP_IN_RANGE (INTVAL (op
)))
2574 /* Accept l(g)hi/l(g)fi operands. */
2575 if (GET_CODE (op
) == CONST_INT
2576 && (CONST_OK_FOR_K (INTVAL (op
)) || CONST_OK_FOR_Os (INTVAL (op
))))
2579 /* Accept lliXX operands. */
2581 && GET_CODE (op
) == CONST_INT
2582 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2583 && s390_single_part (op
, word_mode
, HImode
, 0) >= 0)
2587 && GET_CODE (op
) == CONST_INT
2588 && trunc_int_for_mode (INTVAL (op
), word_mode
) == INTVAL (op
)
2589 && s390_single_part (op
, word_mode
, SImode
, 0) >= 0)
2592 /* Accept larl operands. */
2593 if (TARGET_CPU_ZARCH
2594 && larl_operand (op
, VOIDmode
))
2597 /* Accept lzXX operands. */
2598 if (GET_CODE (op
) == CONST_DOUBLE
2599 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, 'G', "G"))
2602 /* Accept double-word operands that can be split. */
2603 if (GET_CODE (op
) == CONST_INT
2604 && trunc_int_for_mode (INTVAL (op
), word_mode
) != INTVAL (op
))
2606 enum machine_mode dword_mode
= word_mode
== SImode
? DImode
: TImode
;
2607 rtx hi
= operand_subword (op
, 0, 0, dword_mode
);
2608 rtx lo
= operand_subword (op
, 1, 0, dword_mode
);
2609 return legitimate_reload_constant_p (hi
)
2610 && legitimate_reload_constant_p (lo
);
2613 /* Everything else cannot be handled without reload. */
2617 /* Given an rtx OP being reloaded into a reg required to be in class CLASS,
2618 return the class of reg to actually use. */
2621 s390_preferred_reload_class (rtx op
, enum reg_class
class)
2623 switch (GET_CODE (op
))
2625 /* Constants we cannot reload must be forced into the
2630 if (legitimate_reload_constant_p (op
))
2635 /* If a symbolic constant or a PLUS is reloaded,
2636 it is most likely being used as an address, so
2637 prefer ADDR_REGS. If 'class' is not a superset
2638 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
2643 if (reg_class_subset_p (ADDR_REGS
, class))
2655 /* Inform reload about cases where moving X with a mode MODE to a register in
2656 CLASS requires an extra scratch or immediate register. Return the class
2657 needed for the immediate register. */
2659 static enum reg_class
2660 s390_secondary_reload (bool in_p
, rtx x
, enum reg_class
class,
2661 enum machine_mode mode
, secondary_reload_info
*sri
)
2663 /* Intermediate register needed. */
2664 if (reg_classes_intersect_p (CC_REGS
, class))
2665 return GENERAL_REGS
;
2667 /* We need a scratch register when loading a PLUS expression which
2668 is not a legitimate operand of the LOAD ADDRESS instruction. */
2669 if (in_p
&& s390_plus_operand (x
, mode
))
2670 sri
->icode
= (TARGET_64BIT
?
2671 CODE_FOR_reloaddi_plus
: CODE_FOR_reloadsi_plus
);
2673 /* Performing a multiword move from or to memory we have to make sure the
2674 second chunk in memory is addressable without causing a displacement
2675 overflow. If that would be the case we calculate the address in
2676 a scratch register. */
2678 && GET_CODE (XEXP (x
, 0)) == PLUS
2679 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2680 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x
, 0), 1))
2681 + GET_MODE_SIZE (mode
) - 1))
2683 /* For GENERAL_REGS a displacement overflow is no problem if occurring
2684 in a s_operand address since we may fallback to lm/stm. So we only
2685 have to care about overflows in the b+i+d case. */
2686 if ((reg_classes_intersect_p (GENERAL_REGS
, class)
2687 && s390_class_max_nregs (GENERAL_REGS
, mode
) > 1
2688 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
)
2689 /* For FP_REGS no lm/stm is available so this check is triggered
2690 for displacement overflows in b+i+d and b+d like addresses. */
2691 || (reg_classes_intersect_p (FP_REGS
, class)
2692 && s390_class_max_nregs (FP_REGS
, mode
) > 1))
2695 sri
->icode
= (TARGET_64BIT
?
2696 CODE_FOR_reloaddi_nonoffmem_in
:
2697 CODE_FOR_reloadsi_nonoffmem_in
);
2699 sri
->icode
= (TARGET_64BIT
?
2700 CODE_FOR_reloaddi_nonoffmem_out
:
2701 CODE_FOR_reloadsi_nonoffmem_out
);
2705 /* Either scratch or no register needed. */
2709 /* Generate code to load SRC, which is PLUS that is not a
2710 legitimate operand for the LA instruction, into TARGET.
2711 SCRATCH may be used as scratch register. */
2714 s390_expand_plus_operand (rtx target
, rtx src
,
2718 struct s390_address ad
;
2720 /* src must be a PLUS; get its two operands. */
2721 gcc_assert (GET_CODE (src
) == PLUS
);
2722 gcc_assert (GET_MODE (src
) == Pmode
);
2724 /* Check if any of the two operands is already scheduled
2725 for replacement by reload. This can happen e.g. when
2726 float registers occur in an address. */
2727 sum1
= find_replacement (&XEXP (src
, 0));
2728 sum2
= find_replacement (&XEXP (src
, 1));
2729 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
2731 /* If the address is already strictly valid, there's nothing to do. */
2732 if (!s390_decompose_address (src
, &ad
)
2733 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
2734 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
2736 /* Otherwise, one of the operands cannot be an address register;
2737 we reload its value into the scratch register. */
2738 if (true_regnum (sum1
) < 1 || true_regnum (sum1
) > 15)
2740 emit_move_insn (scratch
, sum1
);
2743 if (true_regnum (sum2
) < 1 || true_regnum (sum2
) > 15)
2745 emit_move_insn (scratch
, sum2
);
2749 /* According to the way these invalid addresses are generated
2750 in reload.c, it should never happen (at least on s390) that
2751 *neither* of the PLUS components, after find_replacements
2752 was applied, is an address register. */
2753 if (sum1
== scratch
&& sum2
== scratch
)
2759 src
= gen_rtx_PLUS (Pmode
, sum1
, sum2
);
2762 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
2763 is only ever performed on addresses, so we can mark the
2764 sum as legitimate for LA in any case. */
2765 s390_load_address (target
, src
);
2769 /* Return true if ADDR is a valid memory address.
2770 STRICT specifies whether strict register checking applies. */
2773 legitimate_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2774 rtx addr
, int strict
)
2776 struct s390_address ad
;
2777 if (!s390_decompose_address (addr
, &ad
))
2782 if (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
2785 if (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
)))
2791 && !(REGNO (ad
.base
) >= FIRST_PSEUDO_REGISTER
2792 || REGNO_REG_CLASS (REGNO (ad
.base
)) == ADDR_REGS
))
2796 && !(REGNO (ad
.indx
) >= FIRST_PSEUDO_REGISTER
2797 || REGNO_REG_CLASS (REGNO (ad
.indx
)) == ADDR_REGS
))
2803 /* Return true if OP is a valid operand for the LA instruction.
2804 In 31-bit, we need to prove that the result is used as an
2805 address, as LA performs only a 31-bit addition. */
2808 legitimate_la_operand_p (rtx op
)
2810 struct s390_address addr
;
2811 if (!s390_decompose_address (op
, &addr
))
2814 return (TARGET_64BIT
|| addr
.pointer
);
2817 /* Return true if it is valid *and* preferable to use LA to
2818 compute the sum of OP1 and OP2. */
2821 preferred_la_operand_p (rtx op1
, rtx op2
)
2823 struct s390_address addr
;
2825 if (op2
!= const0_rtx
)
2826 op1
= gen_rtx_PLUS (Pmode
, op1
, op2
);
2828 if (!s390_decompose_address (op1
, &addr
))
2830 if (addr
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (addr
.base
)))
2832 if (addr
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (addr
.indx
)))
2835 if (!TARGET_64BIT
&& !addr
.pointer
)
2841 if ((addr
.base
&& REG_P (addr
.base
) && REG_POINTER (addr
.base
))
2842 || (addr
.indx
&& REG_P (addr
.indx
) && REG_POINTER (addr
.indx
)))
2848 /* Emit a forced load-address operation to load SRC into DST.
2849 This will use the LOAD ADDRESS instruction even in situations
2850 where legitimate_la_operand_p (SRC) returns false. */
2853 s390_load_address (rtx dst
, rtx src
)
2856 emit_move_insn (dst
, src
);
2858 emit_insn (gen_force_la_31 (dst
, src
));
2861 /* Return a legitimate reference for ORIG (an address) using the
2862 register REG. If REG is 0, a new pseudo is generated.
2864 There are two types of references that must be handled:
2866 1. Global data references must load the address from the GOT, via
2867 the PIC reg. An insn is emitted to do this load, and the reg is
2870 2. Static data references, constant pool addresses, and code labels
2871 compute the address as an offset from the GOT, whose base is in
2872 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
2873 differentiate them from global data objects. The returned
2874 address is the PIC reg + an unspec constant.
2876 GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC
2877 reg also appears in the address. */
2880 legitimize_pic_address (rtx orig
, rtx reg
)
2886 gcc_assert (!TLS_SYMBOLIC_CONST (addr
));
2888 if (GET_CODE (addr
) == LABEL_REF
2889 || (GET_CODE (addr
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (addr
)))
2891 /* This is a local symbol. */
2892 if (TARGET_CPU_ZARCH
&& larl_operand (addr
, VOIDmode
))
2894 /* Access local symbols PC-relative via LARL.
2895 This is the same as in the non-PIC case, so it is
2896 handled automatically ... */
2900 /* Access local symbols relative to the GOT. */
2902 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
2904 if (reload_in_progress
|| reload_completed
)
2905 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
2907 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTOFF
);
2908 addr
= gen_rtx_CONST (Pmode
, addr
);
2909 addr
= force_const_mem (Pmode
, addr
);
2910 emit_move_insn (temp
, addr
);
2912 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
2915 s390_load_address (reg
, new);
2920 else if (GET_CODE (addr
) == SYMBOL_REF
)
2923 reg
= gen_reg_rtx (Pmode
);
2927 /* Assume GOT offset < 4k. This is handled the same way
2928 in both 31- and 64-bit code (@GOT). */
2930 if (reload_in_progress
|| reload_completed
)
2931 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
2933 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
2934 new = gen_rtx_CONST (Pmode
, new);
2935 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
2936 new = gen_const_mem (Pmode
, new);
2937 emit_move_insn (reg
, new);
2940 else if (TARGET_CPU_ZARCH
)
2942 /* If the GOT offset might be >= 4k, we determine the position
2943 of the GOT entry via a PC-relative LARL (@GOTENT). */
2945 rtx temp
= gen_reg_rtx (Pmode
);
2947 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTENT
);
2948 new = gen_rtx_CONST (Pmode
, new);
2949 emit_move_insn (temp
, new);
2951 new = gen_const_mem (Pmode
, temp
);
2952 emit_move_insn (reg
, new);
2957 /* If the GOT offset might be >= 4k, we have to load it
2958 from the literal pool (@GOT). */
2960 rtx temp
= gen_reg_rtx (Pmode
);
2962 if (reload_in_progress
|| reload_completed
)
2963 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
2965 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOT
);
2966 addr
= gen_rtx_CONST (Pmode
, addr
);
2967 addr
= force_const_mem (Pmode
, addr
);
2968 emit_move_insn (temp
, addr
);
2970 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
2971 new = gen_const_mem (Pmode
, new);
2972 emit_move_insn (reg
, new);
2978 if (GET_CODE (addr
) == CONST
)
2980 addr
= XEXP (addr
, 0);
2981 if (GET_CODE (addr
) == UNSPEC
)
2983 gcc_assert (XVECLEN (addr
, 0) == 1);
2984 switch (XINT (addr
, 1))
2986 /* If someone moved a GOT-relative UNSPEC
2987 out of the literal pool, force them back in. */
2990 new = force_const_mem (Pmode
, orig
);
2993 /* @GOT is OK as is if small. */
2996 new = force_const_mem (Pmode
, orig
);
2999 /* @GOTENT is OK as is. */
3003 /* @PLT is OK as is on 64-bit, must be converted to
3004 GOT-relative @PLTOFF on 31-bit. */
3006 if (!TARGET_CPU_ZARCH
)
3008 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3010 if (reload_in_progress
|| reload_completed
)
3011 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3013 addr
= XVECEXP (addr
, 0, 0);
3014 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
),
3016 addr
= gen_rtx_CONST (Pmode
, addr
);
3017 addr
= force_const_mem (Pmode
, addr
);
3018 emit_move_insn (temp
, addr
);
3020 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3023 s390_load_address (reg
, new);
3029 /* Everything else cannot happen. */
3035 gcc_assert (GET_CODE (addr
) == PLUS
);
3037 if (GET_CODE (addr
) == PLUS
)
3039 rtx op0
= XEXP (addr
, 0), op1
= XEXP (addr
, 1);
3041 gcc_assert (!TLS_SYMBOLIC_CONST (op0
));
3042 gcc_assert (!TLS_SYMBOLIC_CONST (op1
));
3044 /* Check first to see if this is a constant offset
3045 from a local symbol reference. */
3046 if ((GET_CODE (op0
) == LABEL_REF
3047 || (GET_CODE (op0
) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (op0
)))
3048 && GET_CODE (op1
) == CONST_INT
)
3050 if (TARGET_CPU_ZARCH
3051 && larl_operand (op0
, VOIDmode
)
3052 && INTVAL (op1
) < (HOST_WIDE_INT
)1 << 31
3053 && INTVAL (op1
) >= -((HOST_WIDE_INT
)1 << 31))
3055 if (INTVAL (op1
) & 1)
3057 /* LARL can't handle odd offsets, so emit a
3058 pair of LARL and LA. */
3059 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3061 if (!DISP_IN_RANGE (INTVAL (op1
)))
3063 HOST_WIDE_INT even
= INTVAL (op1
) - 1;
3064 op0
= gen_rtx_PLUS (Pmode
, op0
, GEN_INT (even
));
3065 op0
= gen_rtx_CONST (Pmode
, op0
);
3069 emit_move_insn (temp
, op0
);
3070 new = gen_rtx_PLUS (Pmode
, temp
, op1
);
3074 s390_load_address (reg
, new);
3080 /* If the offset is even, we can just use LARL.
3081 This will happen automatically. */
3086 /* Access local symbols relative to the GOT. */
3088 rtx temp
= reg
? reg
: gen_reg_rtx (Pmode
);
3090 if (reload_in_progress
|| reload_completed
)
3091 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3093 addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op0
),
3095 addr
= gen_rtx_PLUS (Pmode
, addr
, op1
);
3096 addr
= gen_rtx_CONST (Pmode
, addr
);
3097 addr
= force_const_mem (Pmode
, addr
);
3098 emit_move_insn (temp
, addr
);
3100 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3103 s390_load_address (reg
, new);
3109 /* Now, check whether it is a GOT relative symbol plus offset
3110 that was pulled out of the literal pool. Force it back in. */
3112 else if (GET_CODE (op0
) == UNSPEC
3113 && GET_CODE (op1
) == CONST_INT
3114 && XINT (op0
, 1) == UNSPEC_GOTOFF
)
3116 gcc_assert (XVECLEN (op0
, 0) == 1);
3118 new = force_const_mem (Pmode
, orig
);
3121 /* Otherwise, compute the sum. */
3124 base
= legitimize_pic_address (XEXP (addr
, 0), reg
);
3125 new = legitimize_pic_address (XEXP (addr
, 1),
3126 base
== reg
? NULL_RTX
: reg
);
3127 if (GET_CODE (new) == CONST_INT
)
3128 new = plus_constant (base
, INTVAL (new));
3131 if (GET_CODE (new) == PLUS
&& CONSTANT_P (XEXP (new, 1)))
3133 base
= gen_rtx_PLUS (Pmode
, base
, XEXP (new, 0));
3134 new = XEXP (new, 1);
3136 new = gen_rtx_PLUS (Pmode
, base
, new);
3139 if (GET_CODE (new) == CONST
)
3140 new = XEXP (new, 0);
3141 new = force_operand (new, 0);
3148 /* Load the thread pointer into a register. */
3151 s390_get_thread_pointer (void)
3153 rtx tp
= gen_reg_rtx (Pmode
);
3155 emit_move_insn (tp
, gen_rtx_REG (Pmode
, TP_REGNUM
));
3156 mark_reg_pointer (tp
, BITS_PER_WORD
);
3161 /* Emit a tls call insn. The call target is the SYMBOL_REF stored
3162 in s390_tls_symbol which always refers to __tls_get_offset.
3163 The returned offset is written to RESULT_REG and an USE rtx is
3164 generated for TLS_CALL. */
3166 static GTY(()) rtx s390_tls_symbol
;
3169 s390_emit_tls_call_insn (rtx result_reg
, rtx tls_call
)
3173 gcc_assert (flag_pic
);
3175 if (!s390_tls_symbol
)
3176 s390_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_offset");
3178 insn
= s390_emit_call (s390_tls_symbol
, tls_call
, result_reg
,
3179 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
3181 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), result_reg
);
3182 CONST_OR_PURE_CALL_P (insn
) = 1;
3185 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3186 this (thread-local) address. REG may be used as temporary. */
3189 legitimize_tls_address (rtx addr
, rtx reg
)
3191 rtx
new, tls_call
, temp
, base
, r2
, insn
;
3193 if (GET_CODE (addr
) == SYMBOL_REF
)
3194 switch (tls_symbolic_operand (addr
))
3196 case TLS_MODEL_GLOBAL_DYNAMIC
:
3198 r2
= gen_rtx_REG (Pmode
, 2);
3199 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_TLSGD
);
3200 new = gen_rtx_CONST (Pmode
, tls_call
);
3201 new = force_const_mem (Pmode
, new);
3202 emit_move_insn (r2
, new);
3203 s390_emit_tls_call_insn (r2
, tls_call
);
3204 insn
= get_insns ();
3207 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3208 temp
= gen_reg_rtx (Pmode
);
3209 emit_libcall_block (insn
, temp
, r2
, new);
3211 new = gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3214 s390_load_address (reg
, new);
3219 case TLS_MODEL_LOCAL_DYNAMIC
:
3221 r2
= gen_rtx_REG (Pmode
, 2);
3222 tls_call
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM
);
3223 new = gen_rtx_CONST (Pmode
, tls_call
);
3224 new = force_const_mem (Pmode
, new);
3225 emit_move_insn (r2
, new);
3226 s390_emit_tls_call_insn (r2
, tls_call
);
3227 insn
= get_insns ();
3230 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
), UNSPEC_TLSLDM_NTPOFF
);
3231 temp
= gen_reg_rtx (Pmode
);
3232 emit_libcall_block (insn
, temp
, r2
, new);
3234 new = gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3235 base
= gen_reg_rtx (Pmode
);
3236 s390_load_address (base
, new);
3238 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_DTPOFF
);
3239 new = gen_rtx_CONST (Pmode
, new);
3240 new = force_const_mem (Pmode
, new);
3241 temp
= gen_reg_rtx (Pmode
);
3242 emit_move_insn (temp
, new);
3244 new = gen_rtx_PLUS (Pmode
, base
, temp
);
3247 s390_load_address (reg
, new);
3252 case TLS_MODEL_INITIAL_EXEC
:
3255 /* Assume GOT offset < 4k. This is handled the same way
3256 in both 31- and 64-bit code. */
3258 if (reload_in_progress
|| reload_completed
)
3259 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3261 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3262 new = gen_rtx_CONST (Pmode
, new);
3263 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, new);
3264 new = gen_const_mem (Pmode
, new);
3265 temp
= gen_reg_rtx (Pmode
);
3266 emit_move_insn (temp
, new);
3268 else if (TARGET_CPU_ZARCH
)
3270 /* If the GOT offset might be >= 4k, we determine the position
3271 of the GOT entry via a PC-relative LARL. */
3273 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3274 new = gen_rtx_CONST (Pmode
, new);
3275 temp
= gen_reg_rtx (Pmode
);
3276 emit_move_insn (temp
, new);
3278 new = gen_const_mem (Pmode
, temp
);
3279 temp
= gen_reg_rtx (Pmode
);
3280 emit_move_insn (temp
, new);
3284 /* If the GOT offset might be >= 4k, we have to load it
3285 from the literal pool. */
3287 if (reload_in_progress
|| reload_completed
)
3288 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM
, true);
3290 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_GOTNTPOFF
);
3291 new = gen_rtx_CONST (Pmode
, new);
3292 new = force_const_mem (Pmode
, new);
3293 temp
= gen_reg_rtx (Pmode
);
3294 emit_move_insn (temp
, new);
3296 new = gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, temp
);
3297 new = gen_const_mem (Pmode
, new);
3299 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new, addr
), UNSPEC_TLS_LOAD
);
3300 temp
= gen_reg_rtx (Pmode
);
3301 emit_insn (gen_rtx_SET (Pmode
, temp
, new));
3305 /* In position-dependent code, load the absolute address of
3306 the GOT entry from the literal pool. */
3308 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_INDNTPOFF
);
3309 new = gen_rtx_CONST (Pmode
, new);
3310 new = force_const_mem (Pmode
, new);
3311 temp
= gen_reg_rtx (Pmode
);
3312 emit_move_insn (temp
, new);
3315 new = gen_const_mem (Pmode
, new);
3316 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, new, addr
), UNSPEC_TLS_LOAD
);
3317 temp
= gen_reg_rtx (Pmode
);
3318 emit_insn (gen_rtx_SET (Pmode
, temp
, new));
3321 new = gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3324 s390_load_address (reg
, new);
3329 case TLS_MODEL_LOCAL_EXEC
:
3330 new = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, addr
), UNSPEC_NTPOFF
);
3331 new = gen_rtx_CONST (Pmode
, new);
3332 new = force_const_mem (Pmode
, new);
3333 temp
= gen_reg_rtx (Pmode
);
3334 emit_move_insn (temp
, new);
3336 new = gen_rtx_PLUS (Pmode
, s390_get_thread_pointer (), temp
);
3339 s390_load_address (reg
, new);
3348 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == UNSPEC
)
3350 switch (XINT (XEXP (addr
, 0), 1))
3352 case UNSPEC_INDNTPOFF
:
3353 gcc_assert (TARGET_CPU_ZARCH
);
3362 else if (GET_CODE (addr
) == CONST
&& GET_CODE (XEXP (addr
, 0)) == PLUS
3363 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST_INT
)
3365 new = XEXP (XEXP (addr
, 0), 0);
3366 if (GET_CODE (new) != SYMBOL_REF
)
3367 new = gen_rtx_CONST (Pmode
, new);
3369 new = legitimize_tls_address (new, reg
);
3370 new = plus_constant (new, INTVAL (XEXP (XEXP (addr
, 0), 1)));
3371 new = force_operand (new, 0);
3375 gcc_unreachable (); /* for now ... */
3380 /* Emit insns to move operands[1] into operands[0]. */
3383 emit_symbolic_move (rtx
*operands
)
3385 rtx temp
= !can_create_pseudo_p () ? operands
[0] : gen_reg_rtx (Pmode
);
3387 if (GET_CODE (operands
[0]) == MEM
)
3388 operands
[1] = force_reg (Pmode
, operands
[1]);
3389 else if (TLS_SYMBOLIC_CONST (operands
[1]))
3390 operands
[1] = legitimize_tls_address (operands
[1], temp
);
3392 operands
[1] = legitimize_pic_address (operands
[1], temp
);
3395 /* Try machine-dependent ways of modifying an illegitimate address X
3396 to be legitimate. If we find one, return the new, valid address.
3398 OLDX is the address as it was before break_out_memory_refs was called.
3399 In some cases it is useful to look at this to decide what needs to be done.
3401 MODE is the mode of the operand pointed to by X.
3403 When -fpic is used, special handling is needed for symbolic references.
3404 See comments by legitimize_pic_address for details. */
3407 legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
3408 enum machine_mode mode ATTRIBUTE_UNUSED
)
3410 rtx constant_term
= const0_rtx
;
3412 if (TLS_SYMBOLIC_CONST (x
))
3414 x
= legitimize_tls_address (x
, 0);
3416 if (legitimate_address_p (mode
, x
, FALSE
))
3419 else if (GET_CODE (x
) == PLUS
3420 && (TLS_SYMBOLIC_CONST (XEXP (x
, 0))
3421 || TLS_SYMBOLIC_CONST (XEXP (x
, 1))))
3427 if (SYMBOLIC_CONST (x
)
3428 || (GET_CODE (x
) == PLUS
3429 && (SYMBOLIC_CONST (XEXP (x
, 0))
3430 || SYMBOLIC_CONST (XEXP (x
, 1)))))
3431 x
= legitimize_pic_address (x
, 0);
3433 if (legitimate_address_p (mode
, x
, FALSE
))
3437 x
= eliminate_constant_term (x
, &constant_term
);
3439 /* Optimize loading of large displacements by splitting them
3440 into the multiple of 4K and the rest; this allows the
3441 former to be CSE'd if possible.
3443 Don't do this if the displacement is added to a register
3444 pointing into the stack frame, as the offsets will
3445 change later anyway. */
3447 if (GET_CODE (constant_term
) == CONST_INT
3448 && !TARGET_LONG_DISPLACEMENT
3449 && !DISP_IN_RANGE (INTVAL (constant_term
))
3450 && !(REG_P (x
) && REGNO_PTR_FRAME_P (REGNO (x
))))
3452 HOST_WIDE_INT lower
= INTVAL (constant_term
) & 0xfff;
3453 HOST_WIDE_INT upper
= INTVAL (constant_term
) ^ lower
;
3455 rtx temp
= gen_reg_rtx (Pmode
);
3456 rtx val
= force_operand (GEN_INT (upper
), temp
);
3458 emit_move_insn (temp
, val
);
3460 x
= gen_rtx_PLUS (Pmode
, x
, temp
);
3461 constant_term
= GEN_INT (lower
);
3464 if (GET_CODE (x
) == PLUS
)
3466 if (GET_CODE (XEXP (x
, 0)) == REG
)
3468 rtx temp
= gen_reg_rtx (Pmode
);
3469 rtx val
= force_operand (XEXP (x
, 1), temp
);
3471 emit_move_insn (temp
, val
);
3473 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0), temp
);
3476 else if (GET_CODE (XEXP (x
, 1)) == REG
)
3478 rtx temp
= gen_reg_rtx (Pmode
);
3479 rtx val
= force_operand (XEXP (x
, 0), temp
);
3481 emit_move_insn (temp
, val
);
3483 x
= gen_rtx_PLUS (Pmode
, temp
, XEXP (x
, 1));
3487 if (constant_term
!= const0_rtx
)
3488 x
= gen_rtx_PLUS (Pmode
, x
, constant_term
);
3493 /* Try a machine-dependent way of reloading an illegitimate address AD
3494 operand. If we find one, push the reload and and return the new address.
3496 MODE is the mode of the enclosing MEM. OPNUM is the operand number
3497 and TYPE is the reload type of the current reload. */
3500 legitimize_reload_address (rtx ad
, enum machine_mode mode ATTRIBUTE_UNUSED
,
3501 int opnum
, int type
)
3503 if (!optimize
|| TARGET_LONG_DISPLACEMENT
)
3506 if (GET_CODE (ad
) == PLUS
)
3508 rtx tem
= simplify_binary_operation (PLUS
, Pmode
,
3509 XEXP (ad
, 0), XEXP (ad
, 1));
3514 if (GET_CODE (ad
) == PLUS
3515 && GET_CODE (XEXP (ad
, 0)) == REG
3516 && GET_CODE (XEXP (ad
, 1)) == CONST_INT
3517 && !DISP_IN_RANGE (INTVAL (XEXP (ad
, 1))))
3519 HOST_WIDE_INT lower
= INTVAL (XEXP (ad
, 1)) & 0xfff;
3520 HOST_WIDE_INT upper
= INTVAL (XEXP (ad
, 1)) ^ lower
;
3523 cst
= GEN_INT (upper
);
3524 if (!legitimate_reload_constant_p (cst
))
3525 cst
= force_const_mem (Pmode
, cst
);
3527 tem
= gen_rtx_PLUS (Pmode
, XEXP (ad
, 0), cst
);
3528 new = gen_rtx_PLUS (Pmode
, tem
, GEN_INT (lower
));
3530 push_reload (XEXP (tem
, 1), 0, &XEXP (tem
, 1), 0,
3531 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0,
3532 opnum
, (enum reload_type
) type
);
3539 /* Emit code to move LEN bytes from DST to SRC. */
3542 s390_expand_movmem (rtx dst
, rtx src
, rtx len
)
3544 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3546 if (INTVAL (len
) > 0)
3547 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (INTVAL (len
) - 1)));
3550 else if (TARGET_MVCLE
)
3552 emit_insn (gen_movmem_long (dst
, src
, convert_to_mode (Pmode
, len
, 1)));
3557 rtx dst_addr
, src_addr
, count
, blocks
, temp
;
3558 rtx loop_start_label
= gen_label_rtx ();
3559 rtx loop_end_label
= gen_label_rtx ();
3560 rtx end_label
= gen_label_rtx ();
3561 enum machine_mode mode
;
3563 mode
= GET_MODE (len
);
3564 if (mode
== VOIDmode
)
3567 dst_addr
= gen_reg_rtx (Pmode
);
3568 src_addr
= gen_reg_rtx (Pmode
);
3569 count
= gen_reg_rtx (mode
);
3570 blocks
= gen_reg_rtx (mode
);
3572 convert_move (count
, len
, 1);
3573 emit_cmp_and_jump_insns (count
, const0_rtx
,
3574 EQ
, NULL_RTX
, mode
, 1, end_label
);
3576 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
3577 emit_move_insn (src_addr
, force_operand (XEXP (src
, 0), NULL_RTX
));
3578 dst
= change_address (dst
, VOIDmode
, dst_addr
);
3579 src
= change_address (src
, VOIDmode
, src_addr
);
3581 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1, 0);
3583 emit_move_insn (count
, temp
);
3585 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1, 0);
3587 emit_move_insn (blocks
, temp
);
3589 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3590 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3592 emit_label (loop_start_label
);
3594 emit_insn (gen_movmem_short (dst
, src
, GEN_INT (255)));
3595 s390_load_address (dst_addr
,
3596 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
3597 s390_load_address (src_addr
,
3598 gen_rtx_PLUS (Pmode
, src_addr
, GEN_INT (256)));
3600 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1, 0);
3602 emit_move_insn (blocks
, temp
);
3604 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3605 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3607 emit_jump (loop_start_label
);
3608 emit_label (loop_end_label
);
3610 emit_insn (gen_movmem_short (dst
, src
,
3611 convert_to_mode (Pmode
, count
, 1)));
3612 emit_label (end_label
);
3616 /* Emit code to set LEN bytes at DST to VAL.
3617 Make use of clrmem if VAL is zero. */
3620 s390_expand_setmem (rtx dst
, rtx len
, rtx val
)
3622 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) == 0)
3625 gcc_assert (GET_CODE (val
) == CONST_INT
|| GET_MODE (val
) == QImode
);
3627 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) > 0 && INTVAL (len
) <= 257)
3629 if (val
== const0_rtx
&& INTVAL (len
) <= 256)
3630 emit_insn (gen_clrmem_short (dst
, GEN_INT (INTVAL (len
) - 1)));
3633 /* Initialize memory by storing the first byte. */
3634 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
3636 if (INTVAL (len
) > 1)
3638 /* Initiate 1 byte overlap move.
3639 The first byte of DST is propagated through DSTP1.
3640 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
3641 DST is set to size 1 so the rest of the memory location
3642 does not count as source operand. */
3643 rtx dstp1
= adjust_address (dst
, VOIDmode
, 1);
3644 set_mem_size (dst
, const1_rtx
);
3646 emit_insn (gen_movmem_short (dstp1
, dst
,
3647 GEN_INT (INTVAL (len
) - 2)));
3652 else if (TARGET_MVCLE
)
3654 val
= force_not_mem (convert_modes (Pmode
, QImode
, val
, 1));
3655 emit_insn (gen_setmem_long (dst
, convert_to_mode (Pmode
, len
, 1), val
));
3660 rtx dst_addr
, src_addr
, count
, blocks
, temp
, dstp1
= NULL_RTX
;
3661 rtx loop_start_label
= gen_label_rtx ();
3662 rtx loop_end_label
= gen_label_rtx ();
3663 rtx end_label
= gen_label_rtx ();
3664 enum machine_mode mode
;
3666 mode
= GET_MODE (len
);
3667 if (mode
== VOIDmode
)
3670 dst_addr
= gen_reg_rtx (Pmode
);
3671 src_addr
= gen_reg_rtx (Pmode
);
3672 count
= gen_reg_rtx (mode
);
3673 blocks
= gen_reg_rtx (mode
);
3675 convert_move (count
, len
, 1);
3676 emit_cmp_and_jump_insns (count
, const0_rtx
,
3677 EQ
, NULL_RTX
, mode
, 1, end_label
);
3679 emit_move_insn (dst_addr
, force_operand (XEXP (dst
, 0), NULL_RTX
));
3680 dst
= change_address (dst
, VOIDmode
, dst_addr
);
3682 if (val
== const0_rtx
)
3683 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1, 0);
3686 dstp1
= adjust_address (dst
, VOIDmode
, 1);
3687 set_mem_size (dst
, const1_rtx
);
3689 /* Initialize memory by storing the first byte. */
3690 emit_move_insn (adjust_address (dst
, QImode
, 0), val
);
3692 /* If count is 1 we are done. */
3693 emit_cmp_and_jump_insns (count
, const1_rtx
,
3694 EQ
, NULL_RTX
, mode
, 1, end_label
);
3696 temp
= expand_binop (mode
, add_optab
, count
, GEN_INT (-2), count
, 1, 0);
3699 emit_move_insn (count
, temp
);
3701 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1, 0);
3703 emit_move_insn (blocks
, temp
);
3705 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3706 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3708 emit_label (loop_start_label
);
3710 if (val
== const0_rtx
)
3711 emit_insn (gen_clrmem_short (dst
, GEN_INT (255)));
3713 emit_insn (gen_movmem_short (dstp1
, dst
, GEN_INT (255)));
3714 s390_load_address (dst_addr
,
3715 gen_rtx_PLUS (Pmode
, dst_addr
, GEN_INT (256)));
3717 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1, 0);
3719 emit_move_insn (blocks
, temp
);
3721 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3722 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3724 emit_jump (loop_start_label
);
3725 emit_label (loop_end_label
);
3727 if (val
== const0_rtx
)
3728 emit_insn (gen_clrmem_short (dst
, convert_to_mode (Pmode
, count
, 1)));
3730 emit_insn (gen_movmem_short (dstp1
, dst
, convert_to_mode (Pmode
, count
, 1)));
3731 emit_label (end_label
);
3735 /* Emit code to compare LEN bytes at OP0 with those at OP1,
3736 and return the result in TARGET. */
3739 s390_expand_cmpmem (rtx target
, rtx op0
, rtx op1
, rtx len
)
3741 rtx ccreg
= gen_rtx_REG (CCUmode
, CC_REGNUM
);
3744 /* As the result of CMPINT is inverted compared to what we need,
3745 we have to swap the operands. */
3746 tmp
= op0
; op0
= op1
; op1
= tmp
;
3748 if (GET_CODE (len
) == CONST_INT
&& INTVAL (len
) >= 0 && INTVAL (len
) <= 256)
3750 if (INTVAL (len
) > 0)
3752 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (INTVAL (len
) - 1)));
3753 emit_insn (gen_cmpint (target
, ccreg
));
3756 emit_move_insn (target
, const0_rtx
);
3758 else if (TARGET_MVCLE
)
3760 emit_insn (gen_cmpmem_long (op0
, op1
, convert_to_mode (Pmode
, len
, 1)));
3761 emit_insn (gen_cmpint (target
, ccreg
));
3765 rtx addr0
, addr1
, count
, blocks
, temp
;
3766 rtx loop_start_label
= gen_label_rtx ();
3767 rtx loop_end_label
= gen_label_rtx ();
3768 rtx end_label
= gen_label_rtx ();
3769 enum machine_mode mode
;
3771 mode
= GET_MODE (len
);
3772 if (mode
== VOIDmode
)
3775 addr0
= gen_reg_rtx (Pmode
);
3776 addr1
= gen_reg_rtx (Pmode
);
3777 count
= gen_reg_rtx (mode
);
3778 blocks
= gen_reg_rtx (mode
);
3780 convert_move (count
, len
, 1);
3781 emit_cmp_and_jump_insns (count
, const0_rtx
,
3782 EQ
, NULL_RTX
, mode
, 1, end_label
);
3784 emit_move_insn (addr0
, force_operand (XEXP (op0
, 0), NULL_RTX
));
3785 emit_move_insn (addr1
, force_operand (XEXP (op1
, 0), NULL_RTX
));
3786 op0
= change_address (op0
, VOIDmode
, addr0
);
3787 op1
= change_address (op1
, VOIDmode
, addr1
);
3789 temp
= expand_binop (mode
, add_optab
, count
, constm1_rtx
, count
, 1, 0);
3791 emit_move_insn (count
, temp
);
3793 temp
= expand_binop (mode
, lshr_optab
, count
, GEN_INT (8), blocks
, 1, 0);
3795 emit_move_insn (blocks
, temp
);
3797 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3798 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3800 emit_label (loop_start_label
);
3802 emit_insn (gen_cmpmem_short (op0
, op1
, GEN_INT (255)));
3803 temp
= gen_rtx_NE (VOIDmode
, ccreg
, const0_rtx
);
3804 temp
= gen_rtx_IF_THEN_ELSE (VOIDmode
, temp
,
3805 gen_rtx_LABEL_REF (VOIDmode
, end_label
), pc_rtx
);
3806 temp
= gen_rtx_SET (VOIDmode
, pc_rtx
, temp
);
3807 emit_jump_insn (temp
);
3809 s390_load_address (addr0
,
3810 gen_rtx_PLUS (Pmode
, addr0
, GEN_INT (256)));
3811 s390_load_address (addr1
,
3812 gen_rtx_PLUS (Pmode
, addr1
, GEN_INT (256)));
3814 temp
= expand_binop (mode
, add_optab
, blocks
, constm1_rtx
, blocks
, 1, 0);
3816 emit_move_insn (blocks
, temp
);
3818 emit_cmp_and_jump_insns (blocks
, const0_rtx
,
3819 EQ
, NULL_RTX
, mode
, 1, loop_end_label
);
3821 emit_jump (loop_start_label
);
3822 emit_label (loop_end_label
);
3824 emit_insn (gen_cmpmem_short (op0
, op1
,
3825 convert_to_mode (Pmode
, count
, 1)));
3826 emit_label (end_label
);
3828 emit_insn (gen_cmpint (target
, ccreg
));
3833 /* Expand conditional increment or decrement using alc/slb instructions.
3834 Should generate code setting DST to either SRC or SRC + INCREMENT,
3835 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
3836 Returns true if successful, false otherwise.
3838 That makes it possible to implement some if-constructs without jumps e.g.:
3839 (borrow = CC0 | CC1 and carry = CC2 | CC3)
3840 unsigned int a, b, c;
3841 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
3842 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
3843 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
3844 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
3846 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
3847 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
3848 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
3849 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
3850 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3853 s390_expand_addcc (enum rtx_code cmp_code
, rtx cmp_op0
, rtx cmp_op1
,
3854 rtx dst
, rtx src
, rtx increment
)
3856 enum machine_mode cmp_mode
;
3857 enum machine_mode cc_mode
;
3863 if ((GET_MODE (cmp_op0
) == SImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
3864 && (GET_MODE (cmp_op1
) == SImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
3866 else if ((GET_MODE (cmp_op0
) == DImode
|| GET_MODE (cmp_op0
) == VOIDmode
)
3867 && (GET_MODE (cmp_op1
) == DImode
|| GET_MODE (cmp_op1
) == VOIDmode
))
3872 /* Try ADD LOGICAL WITH CARRY. */
3873 if (increment
== const1_rtx
)
3875 /* Determine CC mode to use. */
3876 if (cmp_code
== EQ
|| cmp_code
== NE
)
3878 if (cmp_op1
!= const0_rtx
)
3880 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
3881 NULL_RTX
, 0, OPTAB_WIDEN
);
3882 cmp_op1
= const0_rtx
;
3885 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
3888 if (cmp_code
== LTU
|| cmp_code
== LEU
)
3893 cmp_code
= swap_condition (cmp_code
);
3910 /* Emit comparison instruction pattern. */
3911 if (!register_operand (cmp_op0
, cmp_mode
))
3912 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
3914 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
3915 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
3916 /* We use insn_invalid_p here to add clobbers if required. */
3917 ret
= insn_invalid_p (emit_insn (insn
));
3920 /* Emit ALC instruction pattern. */
3921 op_res
= gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
3922 gen_rtx_REG (cc_mode
, CC_REGNUM
),
3925 if (src
!= const0_rtx
)
3927 if (!register_operand (src
, GET_MODE (dst
)))
3928 src
= force_reg (GET_MODE (dst
), src
);
3930 src
= gen_rtx_PLUS (GET_MODE (dst
), src
, const0_rtx
);
3931 op_res
= gen_rtx_PLUS (GET_MODE (dst
), src
, op_res
);
3934 p
= rtvec_alloc (2);
3936 gen_rtx_SET (VOIDmode
, dst
, op_res
);
3938 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
3939 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
3944 /* Try SUBTRACT LOGICAL WITH BORROW. */
3945 if (increment
== constm1_rtx
)
3947 /* Determine CC mode to use. */
3948 if (cmp_code
== EQ
|| cmp_code
== NE
)
3950 if (cmp_op1
!= const0_rtx
)
3952 cmp_op0
= expand_simple_binop (cmp_mode
, XOR
, cmp_op0
, cmp_op1
,
3953 NULL_RTX
, 0, OPTAB_WIDEN
);
3954 cmp_op1
= const0_rtx
;
3957 cmp_code
= cmp_code
== EQ
? LEU
: GTU
;
3960 if (cmp_code
== GTU
|| cmp_code
== GEU
)
3965 cmp_code
= swap_condition (cmp_code
);
3982 /* Emit comparison instruction pattern. */
3983 if (!register_operand (cmp_op0
, cmp_mode
))
3984 cmp_op0
= force_reg (cmp_mode
, cmp_op0
);
3986 insn
= gen_rtx_SET (VOIDmode
, gen_rtx_REG (cc_mode
, CC_REGNUM
),
3987 gen_rtx_COMPARE (cc_mode
, cmp_op0
, cmp_op1
));
3988 /* We use insn_invalid_p here to add clobbers if required. */
3989 ret
= insn_invalid_p (emit_insn (insn
));
3992 /* Emit SLB instruction pattern. */
3993 if (!register_operand (src
, GET_MODE (dst
)))
3994 src
= force_reg (GET_MODE (dst
), src
);
3996 op_res
= gen_rtx_MINUS (GET_MODE (dst
),
3997 gen_rtx_MINUS (GET_MODE (dst
), src
, const0_rtx
),
3998 gen_rtx_fmt_ee (cmp_code
, GET_MODE (dst
),
3999 gen_rtx_REG (cc_mode
, CC_REGNUM
),
4001 p
= rtvec_alloc (2);
4003 gen_rtx_SET (VOIDmode
, dst
, op_res
);
4005 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (CCmode
, CC_REGNUM
));
4006 emit_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
4014 /* Expand code for the insv template. Return true if successful, false else. */
4017 s390_expand_insv (rtx dest
, rtx op1
, rtx op2
, rtx src
)
4019 int bitsize
= INTVAL (op1
);
4020 int bitpos
= INTVAL (op2
);
4022 /* We need byte alignment. */
4023 if (bitsize
% BITS_PER_UNIT
)
4027 && memory_operand (dest
, VOIDmode
)
4028 && (register_operand (src
, word_mode
)
4029 || const_int_operand (src
, VOIDmode
)))
4031 /* Emit standard pattern if possible. */
4032 enum machine_mode mode
= smallest_mode_for_size (bitsize
, MODE_INT
);
4033 if (GET_MODE_BITSIZE (mode
) == bitsize
)
4034 emit_move_insn (adjust_address (dest
, mode
, 0), gen_lowpart (mode
, src
));
4036 /* (set (ze (mem)) (const_int)). */
4037 else if (const_int_operand (src
, VOIDmode
))
4039 int size
= bitsize
/ BITS_PER_UNIT
;
4040 rtx src_mem
= adjust_address (force_const_mem (word_mode
, src
), BLKmode
,
4041 GET_MODE_SIZE (word_mode
) - size
);
4043 dest
= adjust_address (dest
, BLKmode
, 0);
4044 set_mem_size (dest
, GEN_INT (size
));
4045 s390_expand_movmem (dest
, src_mem
, GEN_INT (size
));
4048 /* (set (ze (mem)) (reg)). */
4049 else if (register_operand (src
, word_mode
))
4051 if (bitsize
<= GET_MODE_BITSIZE (SImode
))
4052 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, op1
,
4056 /* Emit st,stcmh sequence. */
4057 int stcmh_width
= bitsize
- GET_MODE_BITSIZE (SImode
);
4058 int size
= stcmh_width
/ BITS_PER_UNIT
;
4060 emit_move_insn (adjust_address (dest
, SImode
, size
),
4061 gen_lowpart (SImode
, src
));
4062 set_mem_size (dest
, GEN_INT (size
));
4063 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
, GEN_INT
4064 (stcmh_width
), const0_rtx
),
4065 gen_rtx_LSHIFTRT (word_mode
, src
, GEN_INT
4066 (GET_MODE_BITSIZE (SImode
))));
4075 /* (set (ze (reg)) (const_int)). */
4077 && register_operand (dest
, word_mode
)
4078 && (bitpos
% 16) == 0
4079 && (bitsize
% 16) == 0
4080 && const_int_operand (src
, VOIDmode
))
4082 HOST_WIDE_INT val
= INTVAL (src
);
4083 int regpos
= bitpos
+ bitsize
;
4085 while (regpos
> bitpos
)
4087 enum machine_mode putmode
;
4090 if (TARGET_EXTIMM
&& (regpos
% 32 == 0) && (regpos
>= bitpos
+ 32))
4095 putsize
= GET_MODE_BITSIZE (putmode
);
4097 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode
, dest
,
4100 gen_int_mode (val
, putmode
));
4103 gcc_assert (regpos
== bitpos
);
4110 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4111 register that holds VAL of mode MODE shifted by COUNT bits. */
4114 s390_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
4116 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
4117 NULL_RTX
, 1, OPTAB_DIRECT
);
4118 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
4119 NULL_RTX
, 1, OPTAB_DIRECT
);
4122 /* Structure to hold the initial parameters for a compare_and_swap operation
4123 in HImode and QImode. */
4125 struct alignment_context
4127 rtx memsi
; /* SI aligned memory location. */
4128 rtx shift
; /* Bit offset with regard to lsb. */
4129 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
4130 rtx modemaski
; /* ~modemask */
4131 bool aligned
; /* True if memory is aligned, false else. */
4134 /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4135 structure AC for transparent simplifying, if the memory alignment is known
4136 to be at least 32bit. MEM is the memory location for the actual operation
4137 and MODE its mode. */
4140 init_alignment_context (struct alignment_context
*ac
, rtx mem
,
4141 enum machine_mode mode
)
4143 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
4144 ac
->aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
4147 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
4150 /* Alignment is unknown. */
4151 rtx byteoffset
, addr
, align
;
4153 /* Force the address into a register. */
4154 addr
= force_reg (Pmode
, XEXP (mem
, 0));
4156 /* Align it to SImode. */
4157 align
= expand_simple_binop (Pmode
, AND
, addr
,
4158 GEN_INT (-GET_MODE_SIZE (SImode
)),
4159 NULL_RTX
, 1, OPTAB_DIRECT
);
4161 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
4162 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
4163 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
4164 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
4166 /* Calculate shiftcount. */
4167 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
4168 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
4169 NULL_RTX
, 1, OPTAB_DIRECT
);
4170 /* As we already have some offset, evaluate the remaining distance. */
4171 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
4172 NULL_RTX
, 1, OPTAB_DIRECT
);
4175 /* Shift is the byte count, but we need the bitcount. */
4176 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
, GEN_INT (BITS_PER_UNIT
),
4177 NULL_RTX
, 1, OPTAB_DIRECT
);
4178 /* Calculate masks. */
4179 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
4180 GEN_INT (GET_MODE_MASK (mode
)), ac
->shift
,
4181 NULL_RTX
, 1, OPTAB_DIRECT
);
4182 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
4185 /* Expand an atomic compare and swap operation for HImode and QImode. MEM is
4186 the memory location, CMP the old value to compare MEM with and NEW the value
4187 to set if CMP == MEM.
4188 CMP is never in memory for compare_and_swap_cc because
4189 expand_bool_compare_and_swap puts it into a register for later compare. */
4192 s390_expand_cs_hqi (enum machine_mode mode
, rtx target
, rtx mem
, rtx cmp
, rtx
new)
4194 struct alignment_context ac
;
4195 rtx cmpv
, newv
, val
, resv
, cc
;
4196 rtx res
= gen_reg_rtx (SImode
);
4197 rtx csloop
= gen_label_rtx ();
4198 rtx csend
= gen_label_rtx ();
4200 gcc_assert (register_operand (target
, VOIDmode
));
4201 gcc_assert (MEM_P (mem
));
4203 init_alignment_context (&ac
, mem
, mode
);
4205 /* Shift the values to the correct bit positions. */
4206 if (!(ac
.aligned
&& MEM_P (cmp
)))
4207 cmp
= s390_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
4208 if (!(ac
.aligned
&& MEM_P (new)))
4209 new = s390_expand_mask_and_shift (new, mode
, ac
.shift
);
4211 /* Load full word. Subsequent loads are performed by CS. */
4212 val
= expand_simple_binop (SImode
, AND
, ac
.memsi
, ac
.modemaski
,
4213 NULL_RTX
, 1, OPTAB_DIRECT
);
4215 /* Start CS loop. */
4216 emit_label (csloop
);
4217 /* val = "<mem>00..0<mem>"
4218 * cmp = "00..0<cmp>00..0"
4219 * new = "00..0<new>00..0"
4222 /* Patch cmp and new with val at correct position. */
4223 if (ac
.aligned
&& MEM_P (cmp
))
4225 cmpv
= force_reg (SImode
, val
);
4226 store_bit_field (cmpv
, GET_MODE_BITSIZE (mode
), 0, SImode
, cmp
);
4229 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
4230 NULL_RTX
, 1, OPTAB_DIRECT
));
4231 if (ac
.aligned
&& MEM_P (new))
4233 newv
= force_reg (SImode
, val
);
4234 store_bit_field (newv
, GET_MODE_BITSIZE (mode
), 0, SImode
, new);
4237 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new, val
,
4238 NULL_RTX
, 1, OPTAB_DIRECT
));
4240 /* Jump to end if we're done (likely?). */
4241 s390_emit_jump (csend
, s390_emit_compare_and_swap (EQ
, res
, ac
.memsi
,
4244 /* Check for changes outside mode. */
4245 resv
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
4246 NULL_RTX
, 1, OPTAB_DIRECT
);
4247 cc
= s390_emit_compare (NE
, resv
, val
);
4248 emit_move_insn (val
, resv
);
4249 /* Loop internal if so. */
4250 s390_emit_jump (csloop
, cc
);
4254 /* Return the correct part of the bitfield. */
4255 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
4256 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4259 /* Expand an atomic operation CODE of mode MODE. MEM is the memory location
4260 and VAL the value to play with. If AFTER is true then store the value
4261 MEM holds after the operation, if AFTER is false then store the value MEM
4262 holds before the operation. If TARGET is zero then discard that value, else
4263 store it to TARGET. */
4266 s390_expand_atomic (enum machine_mode mode
, enum rtx_code code
,
4267 rtx target
, rtx mem
, rtx val
, bool after
)
4269 struct alignment_context ac
;
4271 rtx
new = gen_reg_rtx (SImode
);
4272 rtx orig
= gen_reg_rtx (SImode
);
4273 rtx csloop
= gen_label_rtx ();
4275 gcc_assert (!target
|| register_operand (target
, VOIDmode
));
4276 gcc_assert (MEM_P (mem
));
4278 init_alignment_context (&ac
, mem
, mode
);
4280 /* Shift val to the correct bit positions.
4281 Preserve "icm", but prevent "ex icm". */
4282 if (!(ac
.aligned
&& code
== SET
&& MEM_P (val
)))
4283 val
= s390_expand_mask_and_shift (val
, mode
, ac
.shift
);
4285 /* Further preparation insns. */
4286 if (code
== PLUS
|| code
== MINUS
)
4287 emit_move_insn (orig
, val
);
4288 else if (code
== MULT
|| code
== AND
) /* val = "11..1<val>11..1" */
4289 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
4290 NULL_RTX
, 1, OPTAB_DIRECT
);
4292 /* Load full word. Subsequent loads are performed by CS. */
4293 cmp
= force_reg (SImode
, ac
.memsi
);
4295 /* Start CS loop. */
4296 emit_label (csloop
);
4297 emit_move_insn (new, cmp
);
4299 /* Patch new with val at correct position. */
4304 val
= expand_simple_binop (SImode
, code
, new, orig
,
4305 NULL_RTX
, 1, OPTAB_DIRECT
);
4306 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
4307 NULL_RTX
, 1, OPTAB_DIRECT
);
4310 if (ac
.aligned
&& MEM_P (val
))
4311 store_bit_field (new, GET_MODE_BITSIZE (mode
), 0, SImode
, val
);
4314 new = expand_simple_binop (SImode
, AND
, new, ac
.modemaski
,
4315 NULL_RTX
, 1, OPTAB_DIRECT
);
4316 new = expand_simple_binop (SImode
, IOR
, new, val
,
4317 NULL_RTX
, 1, OPTAB_DIRECT
);
4323 new = expand_simple_binop (SImode
, code
, new, val
,
4324 NULL_RTX
, 1, OPTAB_DIRECT
);
4326 case MULT
: /* NAND */
4327 new = expand_simple_binop (SImode
, XOR
, new, ac
.modemask
,
4328 NULL_RTX
, 1, OPTAB_DIRECT
);
4329 new = expand_simple_binop (SImode
, AND
, new, val
,
4330 NULL_RTX
, 1, OPTAB_DIRECT
);
4336 s390_emit_jump (csloop
, s390_emit_compare_and_swap (NE
, cmp
,
4337 ac
.memsi
, cmp
, new));
4339 /* Return the correct part of the bitfield. */
4341 convert_move (target
, expand_simple_binop (SImode
, LSHIFTRT
,
4342 after
? new : cmp
, ac
.shift
,
4343 NULL_RTX
, 1, OPTAB_DIRECT
), 1);
4346 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
4347 We need to emit DTP-relative relocations. */
4349 static void s390_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
4352 s390_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
4357 fputs ("\t.long\t", file
);
4360 fputs ("\t.quad\t", file
);
4365 output_addr_const (file
, x
);
4366 fputs ("@DTPOFF", file
);
4369 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
4370 /* Implement TARGET_MANGLE_TYPE. */
4373 s390_mangle_type (tree type
)
4375 if (TYPE_MAIN_VARIANT (type
) == long_double_type_node
4376 && TARGET_LONG_DOUBLE_128
)
4379 /* For all other types, use normal C++ mangling. */
4384 /* In the name of slightly smaller debug output, and to cater to
4385 general assembler lossage, recognize various UNSPEC sequences
4386 and turn them back into a direct symbol reference. */
4389 s390_delegitimize_address (rtx orig_x
)
4393 if (GET_CODE (x
) != MEM
)
4397 if (GET_CODE (x
) == PLUS
4398 && GET_CODE (XEXP (x
, 1)) == CONST
4399 && GET_CODE (XEXP (x
, 0)) == REG
4400 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
)
4402 y
= XEXP (XEXP (x
, 1), 0);
4403 if (GET_CODE (y
) == UNSPEC
4404 && XINT (y
, 1) == UNSPEC_GOT
)
4405 return XVECEXP (y
, 0, 0);
4409 if (GET_CODE (x
) == CONST
)
4412 if (GET_CODE (y
) == UNSPEC
4413 && XINT (y
, 1) == UNSPEC_GOTENT
)
4414 return XVECEXP (y
, 0, 0);
4421 /* Output operand OP to stdio stream FILE.
4422 OP is an address (register + offset) which is not used to address data;
4423 instead the rightmost bits are interpreted as the value. */
4426 print_shift_count_operand (FILE *file
, rtx op
)
4428 HOST_WIDE_INT offset
;
4431 /* Extract base register and offset. */
4432 if (!s390_decompose_shift_count (op
, &base
, &offset
))
4438 gcc_assert (GET_CODE (base
) == REG
);
4439 gcc_assert (REGNO (base
) < FIRST_PSEUDO_REGISTER
);
4440 gcc_assert (REGNO_REG_CLASS (REGNO (base
)) == ADDR_REGS
);
4443 /* Offsets are constricted to twelve bits. */
4444 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, offset
& ((1 << 12) - 1));
4446 fprintf (file
, "(%s)", reg_names
[REGNO (base
)]);
4449 /* See 'get_some_local_dynamic_name'. */
4452 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
4456 if (GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
4458 x
= get_pool_constant (x
);
4459 return for_each_rtx (&x
, get_some_local_dynamic_name_1
, 0);
4462 if (GET_CODE (x
) == SYMBOL_REF
4463 && tls_symbolic_operand (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
4465 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
4472 /* Locate some local-dynamic symbol still in use by this function
4473 so that we can print its name in local-dynamic base patterns. */
4476 get_some_local_dynamic_name (void)
4480 if (cfun
->machine
->some_ld_name
)
4481 return cfun
->machine
->some_ld_name
;
4483 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
4485 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
4486 return cfun
->machine
->some_ld_name
;
4491 /* Output machine-dependent UNSPECs occurring in address constant X
4492 in assembler syntax to stdio stream FILE. Returns true if the
4493 constant X could be recognized, false otherwise. */
4496 s390_output_addr_const_extra (FILE *file
, rtx x
)
4498 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
4499 switch (XINT (x
, 1))
4502 output_addr_const (file
, XVECEXP (x
, 0, 0));
4503 fprintf (file
, "@GOTENT");
4506 output_addr_const (file
, XVECEXP (x
, 0, 0));
4507 fprintf (file
, "@GOT");
4510 output_addr_const (file
, XVECEXP (x
, 0, 0));
4511 fprintf (file
, "@GOTOFF");
4514 output_addr_const (file
, XVECEXP (x
, 0, 0));
4515 fprintf (file
, "@PLT");
4518 output_addr_const (file
, XVECEXP (x
, 0, 0));
4519 fprintf (file
, "@PLTOFF");
4522 output_addr_const (file
, XVECEXP (x
, 0, 0));
4523 fprintf (file
, "@TLSGD");
4526 assemble_name (file
, get_some_local_dynamic_name ());
4527 fprintf (file
, "@TLSLDM");
4530 output_addr_const (file
, XVECEXP (x
, 0, 0));
4531 fprintf (file
, "@DTPOFF");
4534 output_addr_const (file
, XVECEXP (x
, 0, 0));
4535 fprintf (file
, "@NTPOFF");
4537 case UNSPEC_GOTNTPOFF
:
4538 output_addr_const (file
, XVECEXP (x
, 0, 0));
4539 fprintf (file
, "@GOTNTPOFF");
4541 case UNSPEC_INDNTPOFF
:
4542 output_addr_const (file
, XVECEXP (x
, 0, 0));
4543 fprintf (file
, "@INDNTPOFF");
4550 /* Output address operand ADDR in assembler syntax to
4551 stdio stream FILE. */
4554 print_operand_address (FILE *file
, rtx addr
)
4556 struct s390_address ad
;
4558 if (!s390_decompose_address (addr
, &ad
)
4559 || (ad
.base
&& !REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)))
4560 || (ad
.indx
&& !REGNO_OK_FOR_INDEX_P (REGNO (ad
.indx
))))
4561 output_operand_lossage ("cannot decompose address");
4564 output_addr_const (file
, ad
.disp
);
4566 fprintf (file
, "0");
4568 if (ad
.base
&& ad
.indx
)
4569 fprintf (file
, "(%s,%s)", reg_names
[REGNO (ad
.indx
)],
4570 reg_names
[REGNO (ad
.base
)]);
4572 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
4575 /* Output operand X in assembler syntax to stdio stream FILE.
4576 CODE specified the format flag. The following format flags
4579 'C': print opcode suffix for branch condition.
4580 'D': print opcode suffix for inverse branch condition.
4581 'J': print tls_load/tls_gdcall/tls_ldcall suffix
4582 'G': print the size of the operand in bytes.
4583 'O': print only the displacement of a memory reference.
4584 'R': print only the base register of a memory reference.
4585 'S': print S-type memory reference (base+displacement).
4586 'N': print the second word of a DImode operand.
4587 'M': print the second word of a TImode operand.
4588 'Y': print shift count operand.
4590 'b': print integer X as if it's an unsigned byte.
4591 'x': print integer X as if it's an unsigned halfword.
4592 'h': print integer X as if it's a signed halfword.
4593 'i': print the first nonzero HImode part of X.
4594 'j': print the first HImode part unequal to -1 of X.
4595 'k': print the first nonzero SImode part of X.
4596 'm': print the first SImode part unequal to -1 of X.
4597 'o': print integer X as if it's an unsigned 32bit word. */
4600 print_operand (FILE *file
, rtx x
, int code
)
4605 fprintf (file
, s390_branch_condition_mnemonic (x
, FALSE
));
4609 fprintf (file
, s390_branch_condition_mnemonic (x
, TRUE
));
4613 if (GET_CODE (x
) == SYMBOL_REF
)
4615 fprintf (file
, "%s", ":tls_load:");
4616 output_addr_const (file
, x
);
4618 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSGD
)
4620 fprintf (file
, "%s", ":tls_gdcall:");
4621 output_addr_const (file
, XVECEXP (x
, 0, 0));
4623 else if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_TLSLDM
)
4625 fprintf (file
, "%s", ":tls_ldcall:");
4626 assemble_name (file
, get_some_local_dynamic_name ());
4633 fprintf (file
, "%u", GET_MODE_SIZE (GET_MODE (x
)));
4638 struct s390_address ad
;
4641 gcc_assert (GET_CODE (x
) == MEM
);
4642 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
4644 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
4645 gcc_assert (!ad
.indx
);
4648 output_addr_const (file
, ad
.disp
);
4650 fprintf (file
, "0");
4656 struct s390_address ad
;
4659 gcc_assert (GET_CODE (x
) == MEM
);
4660 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
4662 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
4663 gcc_assert (!ad
.indx
);
4666 fprintf (file
, "%s", reg_names
[REGNO (ad
.base
)]);
4668 fprintf (file
, "0");
4674 struct s390_address ad
;
4677 gcc_assert (GET_CODE (x
) == MEM
);
4678 ret
= s390_decompose_address (XEXP (x
, 0), &ad
);
4680 gcc_assert (!ad
.base
|| REGNO_OK_FOR_BASE_P (REGNO (ad
.base
)));
4681 gcc_assert (!ad
.indx
);
4684 output_addr_const (file
, ad
.disp
);
4686 fprintf (file
, "0");
4689 fprintf (file
, "(%s)", reg_names
[REGNO (ad
.base
)]);
4694 if (GET_CODE (x
) == REG
)
4695 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
4696 else if (GET_CODE (x
) == MEM
)
4697 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 4));
4703 if (GET_CODE (x
) == REG
)
4704 x
= gen_rtx_REG (GET_MODE (x
), REGNO (x
) + 1);
4705 else if (GET_CODE (x
) == MEM
)
4706 x
= change_address (x
, VOIDmode
, plus_constant (XEXP (x
, 0), 8));
4712 print_shift_count_operand (file
, x
);
4716 switch (GET_CODE (x
))
4719 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
4723 output_address (XEXP (x
, 0));
4730 output_addr_const (file
, x
);
4735 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xff);
4736 else if (code
== 'x')
4737 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffff);
4738 else if (code
== 'h')
4739 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((INTVAL (x
) & 0xffff) ^ 0x8000) - 0x8000);
4740 else if (code
== 'i')
4741 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4742 s390_extract_part (x
, HImode
, 0));
4743 else if (code
== 'j')
4744 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4745 s390_extract_part (x
, HImode
, -1));
4746 else if (code
== 'k')
4747 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4748 s390_extract_part (x
, SImode
, 0));
4749 else if (code
== 'm')
4750 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
4751 s390_extract_part (x
, SImode
, -1));
4752 else if (code
== 'o')
4753 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) & 0xffffffff);
4755 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
4759 gcc_assert (GET_MODE (x
) == VOIDmode
);
4761 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xff);
4762 else if (code
== 'x')
4763 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, CONST_DOUBLE_LOW (x
) & 0xffff);
4764 else if (code
== 'h')
4765 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, ((CONST_DOUBLE_LOW (x
) & 0xffff) ^ 0x8000) - 0x8000);
4771 fatal_insn ("UNKNOWN in print_operand !?", x
);
4776 /* Target hook for assembling integer objects. We need to define it
4777 here to work a round a bug in some versions of GAS, which couldn't
4778 handle values smaller than INT_MIN when printed in decimal. */
4781 s390_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
4783 if (size
== 8 && aligned_p
4784 && GET_CODE (x
) == CONST_INT
&& INTVAL (x
) < INT_MIN
)
4786 fprintf (asm_out_file
, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX
"\n",
4790 return default_assemble_integer (x
, size
, aligned_p
);
4793 /* Returns true if register REGNO is used for forming
4794 a memory address in expression X. */
4797 reg_used_in_mem_p (int regno
, rtx x
)
4799 enum rtx_code code
= GET_CODE (x
);
4805 if (refers_to_regno_p (regno
, regno
+1,
4809 else if (code
== SET
4810 && GET_CODE (SET_DEST (x
)) == PC
)
4812 if (refers_to_regno_p (regno
, regno
+1,
4817 fmt
= GET_RTX_FORMAT (code
);
4818 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4821 && reg_used_in_mem_p (regno
, XEXP (x
, i
)))
4824 else if (fmt
[i
] == 'E')
4825 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
4826 if (reg_used_in_mem_p (regno
, XVECEXP (x
, i
, j
)))
4832 /* Returns true if expression DEP_RTX sets an address register
4833 used by instruction INSN to address memory. */
4836 addr_generation_dependency_p (rtx dep_rtx
, rtx insn
)
4840 if (GET_CODE (dep_rtx
) == INSN
)
4841 dep_rtx
= PATTERN (dep_rtx
);
4843 if (GET_CODE (dep_rtx
) == SET
)
4845 target
= SET_DEST (dep_rtx
);
4846 if (GET_CODE (target
) == STRICT_LOW_PART
)
4847 target
= XEXP (target
, 0);
4848 while (GET_CODE (target
) == SUBREG
)
4849 target
= SUBREG_REG (target
);
4851 if (GET_CODE (target
) == REG
)
4853 int regno
= REGNO (target
);
4855 if (s390_safe_attr_type (insn
) == TYPE_LA
)
4857 pat
= PATTERN (insn
);
4858 if (GET_CODE (pat
) == PARALLEL
)
4860 gcc_assert (XVECLEN (pat
, 0) == 2);
4861 pat
= XVECEXP (pat
, 0, 0);
4863 gcc_assert (GET_CODE (pat
) == SET
);
4864 return refers_to_regno_p (regno
, regno
+1, SET_SRC (pat
), 0);
4866 else if (get_attr_atype (insn
) == ATYPE_AGEN
)
4867 return reg_used_in_mem_p (regno
, PATTERN (insn
));
4873 /* Return 1, if dep_insn sets register used in insn in the agen unit. */
4876 s390_agen_dep_p (rtx dep_insn
, rtx insn
)
4878 rtx dep_rtx
= PATTERN (dep_insn
);
4881 if (GET_CODE (dep_rtx
) == SET
4882 && addr_generation_dependency_p (dep_rtx
, insn
))
4884 else if (GET_CODE (dep_rtx
) == PARALLEL
)
4886 for (i
= 0; i
< XVECLEN (dep_rtx
, 0); i
++)
4888 if (addr_generation_dependency_p (XVECEXP (dep_rtx
, 0, i
), insn
))
4895 /* A C statement (sans semicolon) to update the integer scheduling priority
4896 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
4897 reduce the priority to execute INSN later. Do not define this macro if
4898 you do not need to adjust the scheduling priorities of insns.
4900 A STD instruction should be scheduled earlier,
4901 in order to use the bypass. */
4904 s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED
, int priority
)
4906 if (! INSN_P (insn
))
4909 if (s390_tune
!= PROCESSOR_2084_Z990
4910 && s390_tune
!= PROCESSOR_2094_Z9_109
)
4913 switch (s390_safe_attr_type (insn
))
4917 priority
= priority
<< 3;
4921 priority
= priority
<< 1;
4929 /* The number of instructions that can be issued per cycle. */
4932 s390_issue_rate (void)
4934 if (s390_tune
== PROCESSOR_2084_Z990
4935 || s390_tune
== PROCESSOR_2094_Z9_109
)
4941 s390_first_cycle_multipass_dfa_lookahead (void)
4947 /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
4948 Fix up MEMs as required. */
4951 annotate_constant_pool_refs (rtx
*x
)
4956 gcc_assert (GET_CODE (*x
) != SYMBOL_REF
4957 || !CONSTANT_POOL_ADDRESS_P (*x
));
4959 /* Literal pool references can only occur inside a MEM ... */
4960 if (GET_CODE (*x
) == MEM
)
4962 rtx memref
= XEXP (*x
, 0);
4964 if (GET_CODE (memref
) == SYMBOL_REF
4965 && CONSTANT_POOL_ADDRESS_P (memref
))
4967 rtx base
= cfun
->machine
->base_reg
;
4968 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, memref
, base
),
4971 *x
= replace_equiv_address (*x
, addr
);
4975 if (GET_CODE (memref
) == CONST
4976 && GET_CODE (XEXP (memref
, 0)) == PLUS
4977 && GET_CODE (XEXP (XEXP (memref
, 0), 1)) == CONST_INT
4978 && GET_CODE (XEXP (XEXP (memref
, 0), 0)) == SYMBOL_REF
4979 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref
, 0), 0)))
4981 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (memref
, 0), 1));
4982 rtx sym
= XEXP (XEXP (memref
, 0), 0);
4983 rtx base
= cfun
->machine
->base_reg
;
4984 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
4987 *x
= replace_equiv_address (*x
, plus_constant (addr
, off
));
4992 /* ... or a load-address type pattern. */
4993 if (GET_CODE (*x
) == SET
)
4995 rtx addrref
= SET_SRC (*x
);
4997 if (GET_CODE (addrref
) == SYMBOL_REF
4998 && CONSTANT_POOL_ADDRESS_P (addrref
))
5000 rtx base
= cfun
->machine
->base_reg
;
5001 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, addrref
, base
),
5004 SET_SRC (*x
) = addr
;
5008 if (GET_CODE (addrref
) == CONST
5009 && GET_CODE (XEXP (addrref
, 0)) == PLUS
5010 && GET_CODE (XEXP (XEXP (addrref
, 0), 1)) == CONST_INT
5011 && GET_CODE (XEXP (XEXP (addrref
, 0), 0)) == SYMBOL_REF
5012 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref
, 0), 0)))
5014 HOST_WIDE_INT off
= INTVAL (XEXP (XEXP (addrref
, 0), 1));
5015 rtx sym
= XEXP (XEXP (addrref
, 0), 0);
5016 rtx base
= cfun
->machine
->base_reg
;
5017 rtx addr
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, sym
, base
),
5020 SET_SRC (*x
) = plus_constant (addr
, off
);
5025 /* Annotate LTREL_BASE as well. */
5026 if (GET_CODE (*x
) == UNSPEC
5027 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5029 rtx base
= cfun
->machine
->base_reg
;
5030 *x
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XVECEXP (*x
, 0, 0), base
),
5035 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5036 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5040 annotate_constant_pool_refs (&XEXP (*x
, i
));
5042 else if (fmt
[i
] == 'E')
5044 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5045 annotate_constant_pool_refs (&XVECEXP (*x
, i
, j
));
5050 /* Split all branches that exceed the maximum distance.
5051 Returns true if this created a new literal pool entry. */
5054 s390_split_branches (void)
5056 rtx temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
5057 int new_literal
= 0, ret
;
5058 rtx insn
, pat
, tmp
, target
;
5061 /* We need correct insn addresses. */
5063 shorten_branches (get_insns ());
5065 /* Find all branches that exceed 64KB, and split them. */
5067 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5069 if (GET_CODE (insn
) != JUMP_INSN
)
5072 pat
= PATTERN (insn
);
5073 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
5074 pat
= XVECEXP (pat
, 0, 0);
5075 if (GET_CODE (pat
) != SET
|| SET_DEST (pat
) != pc_rtx
)
5078 if (GET_CODE (SET_SRC (pat
)) == LABEL_REF
)
5080 label
= &SET_SRC (pat
);
5082 else if (GET_CODE (SET_SRC (pat
)) == IF_THEN_ELSE
)
5084 if (GET_CODE (XEXP (SET_SRC (pat
), 1)) == LABEL_REF
)
5085 label
= &XEXP (SET_SRC (pat
), 1);
5086 else if (GET_CODE (XEXP (SET_SRC (pat
), 2)) == LABEL_REF
)
5087 label
= &XEXP (SET_SRC (pat
), 2);
5094 if (get_attr_length (insn
) <= 4)
5097 /* We are going to use the return register as scratch register,
5098 make sure it will be saved/restored by the prologue/epilogue. */
5099 cfun_frame_layout
.save_return_addr_p
= 1;
5104 tmp
= force_const_mem (Pmode
, *label
);
5105 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, tmp
), insn
);
5106 INSN_ADDRESSES_NEW (tmp
, -1);
5107 annotate_constant_pool_refs (&PATTERN (tmp
));
5114 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, *label
),
5115 UNSPEC_LTREL_OFFSET
);
5116 target
= gen_rtx_CONST (Pmode
, target
);
5117 target
= force_const_mem (Pmode
, target
);
5118 tmp
= emit_insn_before (gen_rtx_SET (Pmode
, temp_reg
, target
), insn
);
5119 INSN_ADDRESSES_NEW (tmp
, -1);
5120 annotate_constant_pool_refs (&PATTERN (tmp
));
5122 target
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (2, XEXP (target
, 0),
5123 cfun
->machine
->base_reg
),
5125 target
= gen_rtx_PLUS (Pmode
, temp_reg
, target
);
5128 ret
= validate_change (insn
, label
, target
, 0);
5136 /* Find an annotated literal pool symbol referenced in RTX X,
5137 and store it at REF. Will abort if X contains references to
5138 more than one such pool symbol; multiple references to the same
5139 symbol are allowed, however.
5141 The rtx pointed to by REF must be initialized to NULL_RTX
5142 by the caller before calling this routine. */
5145 find_constant_pool_ref (rtx x
, rtx
*ref
)
5150 /* Ignore LTREL_BASE references. */
5151 if (GET_CODE (x
) == UNSPEC
5152 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5154 /* Likewise POOL_ENTRY insns. */
5155 if (GET_CODE (x
) == UNSPEC_VOLATILE
5156 && XINT (x
, 1) == UNSPECV_POOL_ENTRY
)
5159 gcc_assert (GET_CODE (x
) != SYMBOL_REF
5160 || !CONSTANT_POOL_ADDRESS_P (x
));
5162 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_LTREF
)
5164 rtx sym
= XVECEXP (x
, 0, 0);
5165 gcc_assert (GET_CODE (sym
) == SYMBOL_REF
5166 && CONSTANT_POOL_ADDRESS_P (sym
));
5168 if (*ref
== NULL_RTX
)
5171 gcc_assert (*ref
== sym
);
5176 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5177 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5181 find_constant_pool_ref (XEXP (x
, i
), ref
);
5183 else if (fmt
[i
] == 'E')
5185 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5186 find_constant_pool_ref (XVECEXP (x
, i
, j
), ref
);
5191 /* Replace every reference to the annotated literal pool
5192 symbol REF in X by its base plus OFFSET. */
5195 replace_constant_pool_ref (rtx
*x
, rtx ref
, rtx offset
)
5200 gcc_assert (*x
!= ref
);
5202 if (GET_CODE (*x
) == UNSPEC
5203 && XINT (*x
, 1) == UNSPEC_LTREF
5204 && XVECEXP (*x
, 0, 0) == ref
)
5206 *x
= gen_rtx_PLUS (Pmode
, XVECEXP (*x
, 0, 1), offset
);
5210 if (GET_CODE (*x
) == PLUS
5211 && GET_CODE (XEXP (*x
, 1)) == CONST_INT
5212 && GET_CODE (XEXP (*x
, 0)) == UNSPEC
5213 && XINT (XEXP (*x
, 0), 1) == UNSPEC_LTREF
5214 && XVECEXP (XEXP (*x
, 0), 0, 0) == ref
)
5216 rtx addr
= gen_rtx_PLUS (Pmode
, XVECEXP (XEXP (*x
, 0), 0, 1), offset
);
5217 *x
= plus_constant (addr
, INTVAL (XEXP (*x
, 1)));
5221 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5222 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5226 replace_constant_pool_ref (&XEXP (*x
, i
), ref
, offset
);
5228 else if (fmt
[i
] == 'E')
5230 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5231 replace_constant_pool_ref (&XVECEXP (*x
, i
, j
), ref
, offset
);
5236 /* Check whether X contains an UNSPEC_LTREL_BASE.
5237 Return its constant pool symbol if found, NULL_RTX otherwise. */
5240 find_ltrel_base (rtx x
)
5245 if (GET_CODE (x
) == UNSPEC
5246 && XINT (x
, 1) == UNSPEC_LTREL_BASE
)
5247 return XVECEXP (x
, 0, 0);
5249 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
5250 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
5254 rtx fnd
= find_ltrel_base (XEXP (x
, i
));
5258 else if (fmt
[i
] == 'E')
5260 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
5262 rtx fnd
= find_ltrel_base (XVECEXP (x
, i
, j
));
5272 /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
5275 replace_ltrel_base (rtx
*x
)
5280 if (GET_CODE (*x
) == UNSPEC
5281 && XINT (*x
, 1) == UNSPEC_LTREL_BASE
)
5283 *x
= XVECEXP (*x
, 0, 1);
5287 fmt
= GET_RTX_FORMAT (GET_CODE (*x
));
5288 for (i
= GET_RTX_LENGTH (GET_CODE (*x
)) - 1; i
>= 0; i
--)
5292 replace_ltrel_base (&XEXP (*x
, i
));
5294 else if (fmt
[i
] == 'E')
5296 for (j
= 0; j
< XVECLEN (*x
, i
); j
++)
5297 replace_ltrel_base (&XVECEXP (*x
, i
, j
));
5303 /* We keep a list of constants which we have to add to internal
5304 constant tables in the middle of large functions. */
5306 #define NR_C_MODES 11
5307 enum machine_mode constant_modes
[NR_C_MODES
] =
5309 TFmode
, TImode
, TDmode
,
5310 DFmode
, DImode
, DDmode
,
5311 SFmode
, SImode
, SDmode
,
5318 struct constant
*next
;
5323 struct constant_pool
5325 struct constant_pool
*next
;
5330 struct constant
*constants
[NR_C_MODES
];
5331 struct constant
*execute
;
5336 /* Allocate new constant_pool structure. */
5338 static struct constant_pool
*
5339 s390_alloc_pool (void)
5341 struct constant_pool
*pool
;
5344 pool
= (struct constant_pool
*) xmalloc (sizeof *pool
);
5346 for (i
= 0; i
< NR_C_MODES
; i
++)
5347 pool
->constants
[i
] = NULL
;
5349 pool
->execute
= NULL
;
5350 pool
->label
= gen_label_rtx ();
5351 pool
->first_insn
= NULL_RTX
;
5352 pool
->pool_insn
= NULL_RTX
;
5353 pool
->insns
= BITMAP_ALLOC (NULL
);
5359 /* Create new constant pool covering instructions starting at INSN
5360 and chain it to the end of POOL_LIST. */
5362 static struct constant_pool
*
5363 s390_start_pool (struct constant_pool
**pool_list
, rtx insn
)
5365 struct constant_pool
*pool
, **prev
;
5367 pool
= s390_alloc_pool ();
5368 pool
->first_insn
= insn
;
5370 for (prev
= pool_list
; *prev
; prev
= &(*prev
)->next
)
5377 /* End range of instructions covered by POOL at INSN and emit
5378 placeholder insn representing the pool. */
5381 s390_end_pool (struct constant_pool
*pool
, rtx insn
)
5383 rtx pool_size
= GEN_INT (pool
->size
+ 8 /* alignment slop */);
5386 insn
= get_last_insn ();
5388 pool
->pool_insn
= emit_insn_after (gen_pool (pool_size
), insn
);
5389 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5392 /* Add INSN to the list of insns covered by POOL. */
5395 s390_add_pool_insn (struct constant_pool
*pool
, rtx insn
)
5397 bitmap_set_bit (pool
->insns
, INSN_UID (insn
));
5400 /* Return pool out of POOL_LIST that covers INSN. */
5402 static struct constant_pool
*
5403 s390_find_pool (struct constant_pool
*pool_list
, rtx insn
)
5405 struct constant_pool
*pool
;
5407 for (pool
= pool_list
; pool
; pool
= pool
->next
)
5408 if (bitmap_bit_p (pool
->insns
, INSN_UID (insn
)))
5414 /* Add constant VAL of mode MODE to the constant pool POOL. */
5417 s390_add_constant (struct constant_pool
*pool
, rtx val
, enum machine_mode mode
)
5422 for (i
= 0; i
< NR_C_MODES
; i
++)
5423 if (constant_modes
[i
] == mode
)
5425 gcc_assert (i
!= NR_C_MODES
);
5427 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5428 if (rtx_equal_p (val
, c
->value
))
5433 c
= (struct constant
*) xmalloc (sizeof *c
);
5435 c
->label
= gen_label_rtx ();
5436 c
->next
= pool
->constants
[i
];
5437 pool
->constants
[i
] = c
;
5438 pool
->size
+= GET_MODE_SIZE (mode
);
5442 /* Find constant VAL of mode MODE in the constant pool POOL.
5443 Return an RTX describing the distance from the start of
5444 the pool to the location of the new constant. */
5447 s390_find_constant (struct constant_pool
*pool
, rtx val
,
5448 enum machine_mode mode
)
5454 for (i
= 0; i
< NR_C_MODES
; i
++)
5455 if (constant_modes
[i
] == mode
)
5457 gcc_assert (i
!= NR_C_MODES
);
5459 for (c
= pool
->constants
[i
]; c
!= NULL
; c
= c
->next
)
5460 if (rtx_equal_p (val
, c
->value
))
5465 offset
= gen_rtx_MINUS (Pmode
, gen_rtx_LABEL_REF (Pmode
, c
->label
),
5466 gen_rtx_LABEL_REF (Pmode
, pool
->label
));
5467 offset
= gen_rtx_CONST (Pmode
, offset
);
5471 /* Check whether INSN is an execute. Return the label_ref to its
5472 execute target template if so, NULL_RTX otherwise. */
5475 s390_execute_label (rtx insn
)
5477 if (GET_CODE (insn
) == INSN
5478 && GET_CODE (PATTERN (insn
)) == PARALLEL
5479 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == UNSPEC
5480 && XINT (XVECEXP (PATTERN (insn
), 0, 0), 1) == UNSPEC_EXECUTE
)
5481 return XVECEXP (XVECEXP (PATTERN (insn
), 0, 0), 0, 2);
5486 /* Add execute target for INSN to the constant pool POOL. */
5489 s390_add_execute (struct constant_pool
*pool
, rtx insn
)
5493 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
5494 if (INSN_UID (insn
) == INSN_UID (c
->value
))
5499 c
= (struct constant
*) xmalloc (sizeof *c
);
5501 c
->label
= gen_label_rtx ();
5502 c
->next
= pool
->execute
;
5508 /* Find execute target for INSN in the constant pool POOL.
5509 Return an RTX describing the distance from the start of
5510 the pool to the location of the execute target. */
5513 s390_find_execute (struct constant_pool
*pool
, rtx insn
)
5518 for (c
= pool
->execute
; c
!= NULL
; c
= c
->next
)
5519 if (INSN_UID (insn
) == INSN_UID (c
->value
))
5524 offset
= gen_rtx_MINUS (Pmode
, gen_rtx_LABEL_REF (Pmode
, c
->label
),
5525 gen_rtx_LABEL_REF (Pmode
, pool
->label
));
5526 offset
= gen_rtx_CONST (Pmode
, offset
);
5530 /* For an execute INSN, extract the execute target template. */
5533 s390_execute_target (rtx insn
)
5535 rtx pattern
= PATTERN (insn
);
5536 gcc_assert (s390_execute_label (insn
));
5538 if (XVECLEN (pattern
, 0) == 2)
5540 pattern
= copy_rtx (XVECEXP (pattern
, 0, 1));
5544 rtvec vec
= rtvec_alloc (XVECLEN (pattern
, 0) - 1);
5547 for (i
= 0; i
< XVECLEN (pattern
, 0) - 1; i
++)
5548 RTVEC_ELT (vec
, i
) = copy_rtx (XVECEXP (pattern
, 0, i
+ 1));
5550 pattern
= gen_rtx_PARALLEL (VOIDmode
, vec
);
5556 /* Indicate that INSN cannot be duplicated. This is the case for
5557 execute insns that carry a unique label. */
5560 s390_cannot_copy_insn_p (rtx insn
)
5562 rtx label
= s390_execute_label (insn
);
5563 return label
&& label
!= const0_rtx
;
5566 /* Dump out the constants in POOL. If REMOTE_LABEL is true,
5567 do not emit the pool base label. */
5570 s390_dump_pool (struct constant_pool
*pool
, bool remote_label
)
5573 rtx insn
= pool
->pool_insn
;
5576 /* Switch to rodata section. */
5577 if (TARGET_CPU_ZARCH
)
5579 insn
= emit_insn_after (gen_pool_section_start (), insn
);
5580 INSN_ADDRESSES_NEW (insn
, -1);
5583 /* Ensure minimum pool alignment. */
5584 if (TARGET_CPU_ZARCH
)
5585 insn
= emit_insn_after (gen_pool_align (GEN_INT (8)), insn
);
5587 insn
= emit_insn_after (gen_pool_align (GEN_INT (4)), insn
);
5588 INSN_ADDRESSES_NEW (insn
, -1);
5590 /* Emit pool base label. */
5593 insn
= emit_label_after (pool
->label
, insn
);
5594 INSN_ADDRESSES_NEW (insn
, -1);
5597 /* Dump constants in descending alignment requirement order,
5598 ensuring proper alignment for every constant. */
5599 for (i
= 0; i
< NR_C_MODES
; i
++)
5600 for (c
= pool
->constants
[i
]; c
; c
= c
->next
)
5602 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
5603 rtx value
= c
->value
;
5604 if (GET_CODE (value
) == CONST
5605 && GET_CODE (XEXP (value
, 0)) == UNSPEC
5606 && XINT (XEXP (value
, 0), 1) == UNSPEC_LTREL_OFFSET
5607 && XVECLEN (XEXP (value
, 0), 0) == 1)
5609 value
= gen_rtx_MINUS (Pmode
, XVECEXP (XEXP (value
, 0), 0, 0),
5610 gen_rtx_LABEL_REF (VOIDmode
, pool
->label
));
5611 value
= gen_rtx_CONST (VOIDmode
, value
);
5614 insn
= emit_label_after (c
->label
, insn
);
5615 INSN_ADDRESSES_NEW (insn
, -1);
5617 value
= gen_rtx_UNSPEC_VOLATILE (constant_modes
[i
],
5618 gen_rtvec (1, value
),
5619 UNSPECV_POOL_ENTRY
);
5620 insn
= emit_insn_after (value
, insn
);
5621 INSN_ADDRESSES_NEW (insn
, -1);
5624 /* Ensure minimum alignment for instructions. */
5625 insn
= emit_insn_after (gen_pool_align (GEN_INT (2)), insn
);
5626 INSN_ADDRESSES_NEW (insn
, -1);
5628 /* Output in-pool execute template insns. */
5629 for (c
= pool
->execute
; c
; c
= c
->next
)
5631 insn
= emit_label_after (c
->label
, insn
);
5632 INSN_ADDRESSES_NEW (insn
, -1);
5634 insn
= emit_insn_after (s390_execute_target (c
->value
), insn
);
5635 INSN_ADDRESSES_NEW (insn
, -1);
5638 /* Switch back to previous section. */
5639 if (TARGET_CPU_ZARCH
)
5641 insn
= emit_insn_after (gen_pool_section_end (), insn
);
5642 INSN_ADDRESSES_NEW (insn
, -1);
5645 insn
= emit_barrier_after (insn
);
5646 INSN_ADDRESSES_NEW (insn
, -1);
5648 /* Remove placeholder insn. */
5649 remove_insn (pool
->pool_insn
);
5652 /* Free all memory used by POOL. */
5655 s390_free_pool (struct constant_pool
*pool
)
5657 struct constant
*c
, *next
;
5660 for (i
= 0; i
< NR_C_MODES
; i
++)
5661 for (c
= pool
->constants
[i
]; c
; c
= next
)
5667 for (c
= pool
->execute
; c
; c
= next
)
5673 BITMAP_FREE (pool
->insns
);
5678 /* Collect main literal pool. Return NULL on overflow. */
5680 static struct constant_pool
*
5681 s390_mainpool_start (void)
5683 struct constant_pool
*pool
;
5686 pool
= s390_alloc_pool ();
5688 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5690 if (GET_CODE (insn
) == INSN
5691 && GET_CODE (PATTERN (insn
)) == SET
5692 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC_VOLATILE
5693 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPECV_MAIN_POOL
)
5695 gcc_assert (!pool
->pool_insn
);
5696 pool
->pool_insn
= insn
;
5699 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
5701 s390_add_execute (pool
, insn
);
5703 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
5705 rtx pool_ref
= NULL_RTX
;
5706 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
5709 rtx constant
= get_pool_constant (pool_ref
);
5710 enum machine_mode mode
= get_pool_mode (pool_ref
);
5711 s390_add_constant (pool
, constant
, mode
);
5716 gcc_assert (pool
->pool_insn
|| pool
->size
== 0);
5718 if (pool
->size
>= 4096)
5720 /* We're going to chunkify the pool, so remove the main
5721 pool placeholder insn. */
5722 remove_insn (pool
->pool_insn
);
5724 s390_free_pool (pool
);
5731 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5732 Modify the current function to output the pool constants as well as
5733 the pool register setup instruction. */
5736 s390_mainpool_finish (struct constant_pool
*pool
)
5738 rtx base_reg
= cfun
->machine
->base_reg
;
5741 /* If the pool is empty, we're done. */
5742 if (pool
->size
== 0)
5744 /* We don't actually need a base register after all. */
5745 cfun
->machine
->base_reg
= NULL_RTX
;
5747 if (pool
->pool_insn
)
5748 remove_insn (pool
->pool_insn
);
5749 s390_free_pool (pool
);
5753 /* We need correct insn addresses. */
5754 shorten_branches (get_insns ());
5756 /* On zSeries, we use a LARL to load the pool register. The pool is
5757 located in the .rodata section, so we emit it after the function. */
5758 if (TARGET_CPU_ZARCH
)
5760 insn
= gen_main_base_64 (base_reg
, pool
->label
);
5761 insn
= emit_insn_after (insn
, pool
->pool_insn
);
5762 INSN_ADDRESSES_NEW (insn
, -1);
5763 remove_insn (pool
->pool_insn
);
5765 insn
= get_last_insn ();
5766 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
5767 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5769 s390_dump_pool (pool
, 0);
5772 /* On S/390, if the total size of the function's code plus literal pool
5773 does not exceed 4096 bytes, we use BASR to set up a function base
5774 pointer, and emit the literal pool at the end of the function. */
5775 else if (INSN_ADDRESSES (INSN_UID (get_last_insn ()))
5776 + pool
->size
+ 8 /* alignment slop */ < 4096)
5778 insn
= gen_main_base_31_small (base_reg
, pool
->label
);
5779 insn
= emit_insn_after (insn
, pool
->pool_insn
);
5780 INSN_ADDRESSES_NEW (insn
, -1);
5781 remove_insn (pool
->pool_insn
);
5783 insn
= emit_label_after (pool
->label
, insn
);
5784 INSN_ADDRESSES_NEW (insn
, -1);
5786 insn
= get_last_insn ();
5787 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
5788 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5790 s390_dump_pool (pool
, 1);
5793 /* Otherwise, we emit an inline literal pool and use BASR to branch
5794 over it, setting up the pool register at the same time. */
5797 rtx pool_end
= gen_label_rtx ();
5799 insn
= gen_main_base_31_large (base_reg
, pool
->label
, pool_end
);
5800 insn
= emit_insn_after (insn
, pool
->pool_insn
);
5801 INSN_ADDRESSES_NEW (insn
, -1);
5802 remove_insn (pool
->pool_insn
);
5804 insn
= emit_label_after (pool
->label
, insn
);
5805 INSN_ADDRESSES_NEW (insn
, -1);
5807 pool
->pool_insn
= emit_insn_after (gen_pool (const0_rtx
), insn
);
5808 INSN_ADDRESSES_NEW (pool
->pool_insn
, -1);
5810 insn
= emit_label_after (pool_end
, pool
->pool_insn
);
5811 INSN_ADDRESSES_NEW (insn
, -1);
5813 s390_dump_pool (pool
, 1);
5817 /* Replace all literal pool references. */
5819 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5822 replace_ltrel_base (&PATTERN (insn
));
5824 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
5826 rtx addr
, pool_ref
= NULL_RTX
;
5827 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
5830 if (s390_execute_label (insn
))
5831 addr
= s390_find_execute (pool
, insn
);
5833 addr
= s390_find_constant (pool
, get_pool_constant (pool_ref
),
5834 get_pool_mode (pool_ref
));
5836 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
5837 INSN_CODE (insn
) = -1;
5843 /* Free the pool. */
5844 s390_free_pool (pool
);
5847 /* POOL holds the main literal pool as collected by s390_mainpool_start.
5848 We have decided we cannot use this pool, so revert all changes
5849 to the current function that were done by s390_mainpool_start. */
5851 s390_mainpool_cancel (struct constant_pool
*pool
)
5853 /* We didn't actually change the instruction stream, so simply
5854 free the pool memory. */
5855 s390_free_pool (pool
);
5859 /* Chunkify the literal pool. */
5861 #define S390_POOL_CHUNK_MIN 0xc00
5862 #define S390_POOL_CHUNK_MAX 0xe00
5864 static struct constant_pool
*
5865 s390_chunkify_start (void)
5867 struct constant_pool
*curr_pool
= NULL
, *pool_list
= NULL
;
5870 rtx pending_ltrel
= NULL_RTX
;
5873 rtx (*gen_reload_base
) (rtx
, rtx
) =
5874 TARGET_CPU_ZARCH
? gen_reload_base_64
: gen_reload_base_31
;
5877 /* We need correct insn addresses. */
5879 shorten_branches (get_insns ());
5881 /* Scan all insns and move literals to pool chunks. */
5883 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
5885 /* Check for pending LTREL_BASE. */
5888 rtx ltrel_base
= find_ltrel_base (PATTERN (insn
));
5891 gcc_assert (ltrel_base
== pending_ltrel
);
5892 pending_ltrel
= NULL_RTX
;
5896 if (!TARGET_CPU_ZARCH
&& s390_execute_label (insn
))
5899 curr_pool
= s390_start_pool (&pool_list
, insn
);
5901 s390_add_execute (curr_pool
, insn
);
5902 s390_add_pool_insn (curr_pool
, insn
);
5904 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
5906 rtx pool_ref
= NULL_RTX
;
5907 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
5910 rtx constant
= get_pool_constant (pool_ref
);
5911 enum machine_mode mode
= get_pool_mode (pool_ref
);
5914 curr_pool
= s390_start_pool (&pool_list
, insn
);
5916 s390_add_constant (curr_pool
, constant
, mode
);
5917 s390_add_pool_insn (curr_pool
, insn
);
5919 /* Don't split the pool chunk between a LTREL_OFFSET load
5920 and the corresponding LTREL_BASE. */
5921 if (GET_CODE (constant
) == CONST
5922 && GET_CODE (XEXP (constant
, 0)) == UNSPEC
5923 && XINT (XEXP (constant
, 0), 1) == UNSPEC_LTREL_OFFSET
)
5925 gcc_assert (!pending_ltrel
);
5926 pending_ltrel
= pool_ref
;
5931 if (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CODE_LABEL
)
5934 s390_add_pool_insn (curr_pool
, insn
);
5935 /* An LTREL_BASE must follow within the same basic block. */
5936 gcc_assert (!pending_ltrel
);
5940 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn
)
5941 || INSN_ADDRESSES (INSN_UID (insn
)) == -1)
5944 if (TARGET_CPU_ZARCH
)
5946 if (curr_pool
->size
< S390_POOL_CHUNK_MAX
)
5949 s390_end_pool (curr_pool
, NULL_RTX
);
5954 int chunk_size
= INSN_ADDRESSES (INSN_UID (insn
))
5955 - INSN_ADDRESSES (INSN_UID (curr_pool
->first_insn
))
5958 /* We will later have to insert base register reload insns.
5959 Those will have an effect on code size, which we need to
5960 consider here. This calculation makes rather pessimistic
5961 worst-case assumptions. */
5962 if (GET_CODE (insn
) == CODE_LABEL
)
5965 if (chunk_size
< S390_POOL_CHUNK_MIN
5966 && curr_pool
->size
< S390_POOL_CHUNK_MIN
)
5969 /* Pool chunks can only be inserted after BARRIERs ... */
5970 if (GET_CODE (insn
) == BARRIER
)
5972 s390_end_pool (curr_pool
, insn
);
5977 /* ... so if we don't find one in time, create one. */
5978 else if ((chunk_size
> S390_POOL_CHUNK_MAX
5979 || curr_pool
->size
> S390_POOL_CHUNK_MAX
))
5981 rtx label
, jump
, barrier
;
5983 /* We can insert the barrier only after a 'real' insn. */
5984 if (GET_CODE (insn
) != INSN
&& GET_CODE (insn
) != CALL_INSN
)
5986 if (get_attr_length (insn
) == 0)
5989 /* Don't separate LTREL_BASE from the corresponding
5990 LTREL_OFFSET load. */
5994 label
= gen_label_rtx ();
5995 jump
= emit_jump_insn_after (gen_jump (label
), insn
);
5996 barrier
= emit_barrier_after (jump
);
5997 insn
= emit_label_after (label
, barrier
);
5998 JUMP_LABEL (jump
) = label
;
5999 LABEL_NUSES (label
) = 1;
6001 INSN_ADDRESSES_NEW (jump
, -1);
6002 INSN_ADDRESSES_NEW (barrier
, -1);
6003 INSN_ADDRESSES_NEW (insn
, -1);
6005 s390_end_pool (curr_pool
, barrier
);
6013 s390_end_pool (curr_pool
, NULL_RTX
);
6014 gcc_assert (!pending_ltrel
);
6016 /* Find all labels that are branched into
6017 from an insn belonging to a different chunk. */
6019 far_labels
= BITMAP_ALLOC (NULL
);
6021 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6023 /* Labels marked with LABEL_PRESERVE_P can be target
6024 of non-local jumps, so we have to mark them.
6025 The same holds for named labels.
6027 Don't do that, however, if it is the label before
6030 if (GET_CODE (insn
) == CODE_LABEL
6031 && (LABEL_PRESERVE_P (insn
) || LABEL_NAME (insn
)))
6033 rtx vec_insn
= next_real_insn (insn
);
6034 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6035 PATTERN (vec_insn
) : NULL_RTX
;
6037 || !(GET_CODE (vec_pat
) == ADDR_VEC
6038 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6039 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (insn
));
6042 /* If we have a direct jump (conditional or unconditional)
6043 or a casesi jump, check all potential targets. */
6044 else if (GET_CODE (insn
) == JUMP_INSN
)
6046 rtx pat
= PATTERN (insn
);
6047 if (GET_CODE (pat
) == PARALLEL
&& XVECLEN (pat
, 0) > 2)
6048 pat
= XVECEXP (pat
, 0, 0);
6050 if (GET_CODE (pat
) == SET
)
6052 rtx label
= JUMP_LABEL (insn
);
6055 if (s390_find_pool (pool_list
, label
)
6056 != s390_find_pool (pool_list
, insn
))
6057 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6060 else if (GET_CODE (pat
) == PARALLEL
6061 && XVECLEN (pat
, 0) == 2
6062 && GET_CODE (XVECEXP (pat
, 0, 0)) == SET
6063 && GET_CODE (XVECEXP (pat
, 0, 1)) == USE
6064 && GET_CODE (XEXP (XVECEXP (pat
, 0, 1), 0)) == LABEL_REF
)
6066 /* Find the jump table used by this casesi jump. */
6067 rtx vec_label
= XEXP (XEXP (XVECEXP (pat
, 0, 1), 0), 0);
6068 rtx vec_insn
= next_real_insn (vec_label
);
6069 rtx vec_pat
= vec_insn
&& GET_CODE (vec_insn
) == JUMP_INSN
?
6070 PATTERN (vec_insn
) : NULL_RTX
;
6072 && (GET_CODE (vec_pat
) == ADDR_VEC
6073 || GET_CODE (vec_pat
) == ADDR_DIFF_VEC
))
6075 int i
, diff_p
= GET_CODE (vec_pat
) == ADDR_DIFF_VEC
;
6077 for (i
= 0; i
< XVECLEN (vec_pat
, diff_p
); i
++)
6079 rtx label
= XEXP (XVECEXP (vec_pat
, diff_p
, i
), 0);
6081 if (s390_find_pool (pool_list
, label
)
6082 != s390_find_pool (pool_list
, insn
))
6083 bitmap_set_bit (far_labels
, CODE_LABEL_NUMBER (label
));
6090 /* Insert base register reload insns before every pool. */
6092 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6094 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6096 rtx insn
= curr_pool
->first_insn
;
6097 INSN_ADDRESSES_NEW (emit_insn_before (new_insn
, insn
), -1);
6100 /* Insert base register reload insns at every far label. */
6102 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6103 if (GET_CODE (insn
) == CODE_LABEL
6104 && bitmap_bit_p (far_labels
, CODE_LABEL_NUMBER (insn
)))
6106 struct constant_pool
*pool
= s390_find_pool (pool_list
, insn
);
6109 rtx new_insn
= gen_reload_base (cfun
->machine
->base_reg
,
6111 INSN_ADDRESSES_NEW (emit_insn_after (new_insn
, insn
), -1);
6116 BITMAP_FREE (far_labels
);
6119 /* Recompute insn addresses. */
6121 init_insn_lengths ();
6122 shorten_branches (get_insns ());
6127 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6128 After we have decided to use this list, finish implementing
6129 all changes to the current function as required. */
6132 s390_chunkify_finish (struct constant_pool
*pool_list
)
6134 struct constant_pool
*curr_pool
= NULL
;
6138 /* Replace all literal pool references. */
6140 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
6143 replace_ltrel_base (&PATTERN (insn
));
6145 curr_pool
= s390_find_pool (pool_list
, insn
);
6149 if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
)
6151 rtx addr
, pool_ref
= NULL_RTX
;
6152 find_constant_pool_ref (PATTERN (insn
), &pool_ref
);
6155 if (s390_execute_label (insn
))
6156 addr
= s390_find_execute (curr_pool
, insn
);
6158 addr
= s390_find_constant (curr_pool
,
6159 get_pool_constant (pool_ref
),
6160 get_pool_mode (pool_ref
));
6162 replace_constant_pool_ref (&PATTERN (insn
), pool_ref
, addr
);
6163 INSN_CODE (insn
) = -1;
6168 /* Dump out all literal pools. */
6170 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6171 s390_dump_pool (curr_pool
, 0);
6173 /* Free pool list. */
6177 struct constant_pool
*next
= pool_list
->next
;
6178 s390_free_pool (pool_list
);
6183 /* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
6184 We have decided we cannot use this list, so revert all changes
6185 to the current function that were done by s390_chunkify_start. */
6188 s390_chunkify_cancel (struct constant_pool
*pool_list
)
6190 struct constant_pool
*curr_pool
= NULL
;
6193 /* Remove all pool placeholder insns. */
6195 for (curr_pool
= pool_list
; curr_pool
; curr_pool
= curr_pool
->next
)
6197 /* Did we insert an extra barrier? Remove it. */
6198 rtx barrier
= PREV_INSN (curr_pool
->pool_insn
);
6199 rtx jump
= barrier
? PREV_INSN (barrier
) : NULL_RTX
;
6200 rtx label
= NEXT_INSN (curr_pool
->pool_insn
);
6202 if (jump
&& GET_CODE (jump
) == JUMP_INSN
6203 && barrier
&& GET_CODE (barrier
) == BARRIER
6204 && label
&& GET_CODE (label
) == CODE_LABEL
6205 && GET_CODE (PATTERN (jump
)) == SET
6206 && SET_DEST (PATTERN (jump
)) == pc_rtx
6207 && GET_CODE (SET_SRC (PATTERN (jump
))) == LABEL_REF
6208 && XEXP (SET_SRC (PATTERN (jump
)), 0) == label
)
6211 remove_insn (barrier
);
6212 remove_insn (label
);
6215 remove_insn (curr_pool
->pool_insn
);
6218 /* Remove all base register reload insns. */
6220 for (insn
= get_insns (); insn
; )
6222 rtx next_insn
= NEXT_INSN (insn
);
6224 if (GET_CODE (insn
) == INSN
6225 && GET_CODE (PATTERN (insn
)) == SET
6226 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
6227 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_RELOAD_BASE
)
6233 /* Free pool list. */
6237 struct constant_pool
*next
= pool_list
->next
;
6238 s390_free_pool (pool_list
);
6244 /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
6247 s390_output_pool_entry (rtx exp
, enum machine_mode mode
, unsigned int align
)
6251 switch (GET_MODE_CLASS (mode
))
6254 case MODE_DECIMAL_FLOAT
:
6255 gcc_assert (GET_CODE (exp
) == CONST_DOUBLE
);
6257 REAL_VALUE_FROM_CONST_DOUBLE (r
, exp
);
6258 assemble_real (r
, mode
, align
);
6262 assemble_integer (exp
, GET_MODE_SIZE (mode
), align
, 1);
6271 /* Return an RTL expression representing the value of the return address
6272 for the frame COUNT steps up from the current frame. FRAME is the
6273 frame pointer of that frame. */
6276 s390_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
6281 /* Without backchain, we fail for all but the current frame. */
6283 if (!TARGET_BACKCHAIN
&& count
> 0)
6286 /* For the current frame, we need to make sure the initial
6287 value of RETURN_REGNUM is actually saved. */
6291 /* On non-z architectures branch splitting could overwrite r14. */
6292 if (TARGET_CPU_ZARCH
)
6293 return get_hard_reg_initial_val (Pmode
, RETURN_REGNUM
);
6296 cfun_frame_layout
.save_return_addr_p
= true;
6297 return gen_rtx_MEM (Pmode
, return_address_pointer_rtx
);
6301 if (TARGET_PACKED_STACK
)
6302 offset
= -2 * UNITS_PER_WORD
;
6304 offset
= RETURN_REGNUM
* UNITS_PER_WORD
;
6306 addr
= plus_constant (frame
, offset
);
6307 addr
= memory_address (Pmode
, addr
);
6308 return gen_rtx_MEM (Pmode
, addr
);
6311 /* Return an RTL expression representing the back chain stored in
6312 the current stack frame. */
6315 s390_back_chain_rtx (void)
6319 gcc_assert (TARGET_BACKCHAIN
);
6321 if (TARGET_PACKED_STACK
)
6322 chain
= plus_constant (stack_pointer_rtx
,
6323 STACK_POINTER_OFFSET
- UNITS_PER_WORD
);
6325 chain
= stack_pointer_rtx
;
6327 chain
= gen_rtx_MEM (Pmode
, chain
);
6331 /* Find first call clobbered register unused in a function.
6332 This could be used as base register in a leaf function
6333 or for holding the return address before epilogue. */
6336 find_unused_clobbered_reg (void)
6339 for (i
= 0; i
< 6; i
++)
6340 if (!df_regs_ever_live_p (i
))
6346 /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
6347 clobbered hard regs in SETREG. */
6350 s390_reg_clobbered_rtx (rtx setreg
, const_rtx set_insn ATTRIBUTE_UNUSED
, void *data
)
6352 int *regs_ever_clobbered
= (int *)data
;
6353 unsigned int i
, regno
;
6354 enum machine_mode mode
= GET_MODE (setreg
);
6356 if (GET_CODE (setreg
) == SUBREG
)
6358 rtx inner
= SUBREG_REG (setreg
);
6359 if (!GENERAL_REG_P (inner
))
6361 regno
= subreg_regno (setreg
);
6363 else if (GENERAL_REG_P (setreg
))
6364 regno
= REGNO (setreg
);
6369 i
< regno
+ HARD_REGNO_NREGS (regno
, mode
);
6371 regs_ever_clobbered
[i
] = 1;
6374 /* Walks through all basic blocks of the current function looking
6375 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
6376 of the passed integer array REGS_EVER_CLOBBERED are set to one for
6377 each of those regs. */
6380 s390_regs_ever_clobbered (int *regs_ever_clobbered
)
6386 memset (regs_ever_clobbered
, 0, 16 * sizeof (int));
6388 /* For non-leaf functions we have to consider all call clobbered regs to be
6390 if (!current_function_is_leaf
)
6392 for (i
= 0; i
< 16; i
++)
6393 regs_ever_clobbered
[i
] = call_really_used_regs
[i
];
6396 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
6397 this work is done by liveness analysis (mark_regs_live_at_end).
6398 Special care is needed for functions containing landing pads. Landing pads
6399 may use the eh registers, but the code which sets these registers is not
6400 contained in that function. Hence s390_regs_ever_clobbered is not able to
6401 deal with this automatically. */
6402 if (current_function_calls_eh_return
|| cfun
->machine
->has_landing_pad_p
)
6403 for (i
= 0; EH_RETURN_DATA_REGNO (i
) != INVALID_REGNUM
; i
++)
6404 if (current_function_calls_eh_return
6405 || (cfun
->machine
->has_landing_pad_p
6406 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i
))))
6407 regs_ever_clobbered
[EH_RETURN_DATA_REGNO (i
)] = 1;
6409 /* For nonlocal gotos all call-saved registers have to be saved.
6410 This flag is also set for the unwinding code in libgcc.
6411 See expand_builtin_unwind_init. For regs_ever_live this is done by
6413 if (current_function_has_nonlocal_label
)
6414 for (i
= 0; i
< 16; i
++)
6415 if (!call_really_used_regs
[i
])
6416 regs_ever_clobbered
[i
] = 1;
6418 FOR_EACH_BB (cur_bb
)
6420 FOR_BB_INSNS (cur_bb
, cur_insn
)
6422 if (INSN_P (cur_insn
))
6423 note_stores (PATTERN (cur_insn
),
6424 s390_reg_clobbered_rtx
,
6425 regs_ever_clobbered
);
6430 /* Determine the frame area which actually has to be accessed
6431 in the function epilogue. The values are stored at the
6432 given pointers AREA_BOTTOM (address of the lowest used stack
6433 address) and AREA_TOP (address of the first item which does
6434 not belong to the stack frame). */
6437 s390_frame_area (int *area_bottom
, int *area_top
)
6445 if (cfun_frame_layout
.first_restore_gpr
!= -1)
6447 b
= (cfun_frame_layout
.gprs_offset
6448 + cfun_frame_layout
.first_restore_gpr
* UNITS_PER_WORD
);
6449 t
= b
+ (cfun_frame_layout
.last_restore_gpr
6450 - cfun_frame_layout
.first_restore_gpr
+ 1) * UNITS_PER_WORD
;
6453 if (TARGET_64BIT
&& cfun_save_high_fprs_p
)
6455 b
= MIN (b
, cfun_frame_layout
.f8_offset
);
6456 t
= MAX (t
, (cfun_frame_layout
.f8_offset
6457 + cfun_frame_layout
.high_fprs
* 8));
6461 for (i
= 2; i
< 4; i
++)
6462 if (cfun_fpr_bit_p (i
))
6464 b
= MIN (b
, cfun_frame_layout
.f4_offset
+ (i
- 2) * 8);
6465 t
= MAX (t
, cfun_frame_layout
.f4_offset
+ (i
- 1) * 8);
6472 /* Fill cfun->machine with info about register usage of current function.
6473 Return in CLOBBERED_REGS which GPRs are currently considered set. */
6476 s390_register_info (int clobbered_regs
[])
6480 /* fprs 8 - 15 are call saved for 64 Bit ABI. */
6481 cfun_frame_layout
.fpr_bitmap
= 0;
6482 cfun_frame_layout
.high_fprs
= 0;
6484 for (i
= 24; i
< 32; i
++)
6485 if (df_regs_ever_live_p (i
) && !global_regs
[i
])
6487 cfun_set_fpr_bit (i
- 16);
6488 cfun_frame_layout
.high_fprs
++;
6491 /* Find first and last gpr to be saved. We trust regs_ever_live
6492 data, except that we don't save and restore global registers.
6494 Also, all registers with special meaning to the compiler need
6495 to be handled extra. */
6497 s390_regs_ever_clobbered (clobbered_regs
);
6499 for (i
= 0; i
< 16; i
++)
6500 clobbered_regs
[i
] = clobbered_regs
[i
] && !global_regs
[i
] && !fixed_regs
[i
];
6502 if (frame_pointer_needed
)
6503 clobbered_regs
[HARD_FRAME_POINTER_REGNUM
] = 1;
6506 clobbered_regs
[PIC_OFFSET_TABLE_REGNUM
]
6507 |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
);
6509 clobbered_regs
[BASE_REGNUM
]
6510 |= (cfun
->machine
->base_reg
6511 && REGNO (cfun
->machine
->base_reg
) == BASE_REGNUM
);
6513 clobbered_regs
[RETURN_REGNUM
]
6514 |= (!current_function_is_leaf
6515 || TARGET_TPF_PROFILING
6516 || cfun
->machine
->split_branches_pending_p
6517 || cfun_frame_layout
.save_return_addr_p
6518 || current_function_calls_eh_return
6519 || current_function_stdarg
);
6521 clobbered_regs
[STACK_POINTER_REGNUM
]
6522 |= (!current_function_is_leaf
6523 || TARGET_TPF_PROFILING
6524 || cfun_save_high_fprs_p
6525 || get_frame_size () > 0
6526 || current_function_calls_alloca
6527 || current_function_stdarg
);
6529 for (i
= 6; i
< 16; i
++)
6530 if (df_regs_ever_live_p (i
) || clobbered_regs
[i
])
6532 for (j
= 15; j
> i
; j
--)
6533 if (df_regs_ever_live_p (j
) || clobbered_regs
[j
])
6538 /* Nothing to save/restore. */
6539 cfun_frame_layout
.first_save_gpr_slot
= -1;
6540 cfun_frame_layout
.last_save_gpr_slot
= -1;
6541 cfun_frame_layout
.first_save_gpr
= -1;
6542 cfun_frame_layout
.first_restore_gpr
= -1;
6543 cfun_frame_layout
.last_save_gpr
= -1;
6544 cfun_frame_layout
.last_restore_gpr
= -1;
6548 /* Save slots for gprs from i to j. */
6549 cfun_frame_layout
.first_save_gpr_slot
= i
;
6550 cfun_frame_layout
.last_save_gpr_slot
= j
;
6552 for (i
= cfun_frame_layout
.first_save_gpr_slot
;
6553 i
< cfun_frame_layout
.last_save_gpr_slot
+ 1;
6555 if (clobbered_regs
[i
])
6558 for (j
= cfun_frame_layout
.last_save_gpr_slot
; j
> i
; j
--)
6559 if (clobbered_regs
[j
])
6562 if (i
== cfun_frame_layout
.last_save_gpr_slot
+ 1)
6564 /* Nothing to save/restore. */
6565 cfun_frame_layout
.first_save_gpr
= -1;
6566 cfun_frame_layout
.first_restore_gpr
= -1;
6567 cfun_frame_layout
.last_save_gpr
= -1;
6568 cfun_frame_layout
.last_restore_gpr
= -1;
6572 /* Save / Restore from gpr i to j. */
6573 cfun_frame_layout
.first_save_gpr
= i
;
6574 cfun_frame_layout
.first_restore_gpr
= i
;
6575 cfun_frame_layout
.last_save_gpr
= j
;
6576 cfun_frame_layout
.last_restore_gpr
= j
;
6580 if (current_function_stdarg
)
6582 /* Varargs functions need to save gprs 2 to 6. */
6583 if (cfun
->va_list_gpr_size
6584 && current_function_args_info
.gprs
< GP_ARG_NUM_REG
)
6586 int min_gpr
= current_function_args_info
.gprs
;
6587 int max_gpr
= min_gpr
+ cfun
->va_list_gpr_size
;
6588 if (max_gpr
> GP_ARG_NUM_REG
)
6589 max_gpr
= GP_ARG_NUM_REG
;
6591 if (cfun_frame_layout
.first_save_gpr
== -1
6592 || cfun_frame_layout
.first_save_gpr
> 2 + min_gpr
)
6594 cfun_frame_layout
.first_save_gpr
= 2 + min_gpr
;
6595 cfun_frame_layout
.first_save_gpr_slot
= 2 + min_gpr
;
6598 if (cfun_frame_layout
.last_save_gpr
== -1
6599 || cfun_frame_layout
.last_save_gpr
< 2 + max_gpr
- 1)
6601 cfun_frame_layout
.last_save_gpr
= 2 + max_gpr
- 1;
6602 cfun_frame_layout
.last_save_gpr_slot
= 2 + max_gpr
- 1;
6606 /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */
6607 if (TARGET_HARD_FLOAT
&& cfun
->va_list_fpr_size
6608 && current_function_args_info
.fprs
< FP_ARG_NUM_REG
)
6610 int min_fpr
= current_function_args_info
.fprs
;
6611 int max_fpr
= min_fpr
+ cfun
->va_list_fpr_size
;
6612 if (max_fpr
> FP_ARG_NUM_REG
)
6613 max_fpr
= FP_ARG_NUM_REG
;
6615 /* ??? This is currently required to ensure proper location
6616 of the fpr save slots within the va_list save area. */
6617 if (TARGET_PACKED_STACK
)
6620 for (i
= min_fpr
; i
< max_fpr
; i
++)
6621 cfun_set_fpr_bit (i
);
6626 for (i
= 2; i
< 4; i
++)
6627 if (df_regs_ever_live_p (i
+ 16) && !global_regs
[i
+ 16])
6628 cfun_set_fpr_bit (i
);
6631 /* Fill cfun->machine with info about frame of current function. */
6634 s390_frame_info (void)
6638 cfun_frame_layout
.frame_size
= get_frame_size ();
6639 if (!TARGET_64BIT
&& cfun_frame_layout
.frame_size
> 0x7fff0000)
6640 fatal_error ("total size of local variables exceeds architecture limit");
6642 if (!TARGET_PACKED_STACK
)
6644 cfun_frame_layout
.backchain_offset
= 0;
6645 cfun_frame_layout
.f0_offset
= 16 * UNITS_PER_WORD
;
6646 cfun_frame_layout
.f4_offset
= cfun_frame_layout
.f0_offset
+ 2 * 8;
6647 cfun_frame_layout
.f8_offset
= -cfun_frame_layout
.high_fprs
* 8;
6648 cfun_frame_layout
.gprs_offset
= (cfun_frame_layout
.first_save_gpr_slot
6651 else if (TARGET_BACKCHAIN
) /* kernel stack layout */
6653 cfun_frame_layout
.backchain_offset
= (STACK_POINTER_OFFSET
6655 cfun_frame_layout
.gprs_offset
6656 = (cfun_frame_layout
.backchain_offset
6657 - (STACK_POINTER_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
+ 1)
6662 cfun_frame_layout
.f4_offset
6663 = (cfun_frame_layout
.gprs_offset
6664 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6666 cfun_frame_layout
.f0_offset
6667 = (cfun_frame_layout
.f4_offset
6668 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6672 /* On 31 bit we have to care about alignment of the
6673 floating point regs to provide fastest access. */
6674 cfun_frame_layout
.f0_offset
6675 = ((cfun_frame_layout
.gprs_offset
6676 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1))
6677 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6679 cfun_frame_layout
.f4_offset
6680 = (cfun_frame_layout
.f0_offset
6681 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6684 else /* no backchain */
6686 cfun_frame_layout
.f4_offset
6687 = (STACK_POINTER_OFFSET
6688 - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3)));
6690 cfun_frame_layout
.f0_offset
6691 = (cfun_frame_layout
.f4_offset
6692 - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1)));
6694 cfun_frame_layout
.gprs_offset
6695 = cfun_frame_layout
.f0_offset
- cfun_gprs_save_area_size
;
6698 if (current_function_is_leaf
6699 && !TARGET_TPF_PROFILING
6700 && cfun_frame_layout
.frame_size
== 0
6701 && !cfun_save_high_fprs_p
6702 && !current_function_calls_alloca
6703 && !current_function_stdarg
)
6706 if (!TARGET_PACKED_STACK
)
6707 cfun_frame_layout
.frame_size
+= (STACK_POINTER_OFFSET
6708 + current_function_outgoing_args_size
6709 + cfun_frame_layout
.high_fprs
* 8);
6712 if (TARGET_BACKCHAIN
)
6713 cfun_frame_layout
.frame_size
+= UNITS_PER_WORD
;
6715 /* No alignment trouble here because f8-f15 are only saved under
6717 cfun_frame_layout
.f8_offset
= (MIN (MIN (cfun_frame_layout
.f0_offset
,
6718 cfun_frame_layout
.f4_offset
),
6719 cfun_frame_layout
.gprs_offset
)
6720 - cfun_frame_layout
.high_fprs
* 8);
6722 cfun_frame_layout
.frame_size
+= cfun_frame_layout
.high_fprs
* 8;
6724 for (i
= 0; i
< 8; i
++)
6725 if (cfun_fpr_bit_p (i
))
6726 cfun_frame_layout
.frame_size
+= 8;
6728 cfun_frame_layout
.frame_size
+= cfun_gprs_save_area_size
;
6730 /* If under 31 bit an odd number of gprs has to be saved we have to adjust
6731 the frame size to sustain 8 byte alignment of stack frames. */
6732 cfun_frame_layout
.frame_size
= ((cfun_frame_layout
.frame_size
+
6733 STACK_BOUNDARY
/ BITS_PER_UNIT
- 1)
6734 & ~(STACK_BOUNDARY
/ BITS_PER_UNIT
- 1));
6736 cfun_frame_layout
.frame_size
+= current_function_outgoing_args_size
;
6740 /* Generate frame layout. Fills in register and frame data for the current
6741 function in cfun->machine. This routine can be called multiple times;
6742 it will re-do the complete frame layout every time. */
6745 s390_init_frame_layout (void)
6747 HOST_WIDE_INT frame_size
;
6749 int clobbered_regs
[16];
6751 /* On S/390 machines, we may need to perform branch splitting, which
6752 will require both base and return address register. We have no
6753 choice but to assume we're going to need them until right at the
6754 end of the machine dependent reorg phase. */
6755 if (!TARGET_CPU_ZARCH
)
6756 cfun
->machine
->split_branches_pending_p
= true;
6760 frame_size
= cfun_frame_layout
.frame_size
;
6762 /* Try to predict whether we'll need the base register. */
6763 base_used
= cfun
->machine
->split_branches_pending_p
6764 || current_function_uses_const_pool
6765 || (!DISP_IN_RANGE (frame_size
)
6766 && !CONST_OK_FOR_K (frame_size
));
6768 /* Decide which register to use as literal pool base. In small
6769 leaf functions, try to use an unused call-clobbered register
6770 as base register to avoid save/restore overhead. */
6772 cfun
->machine
->base_reg
= NULL_RTX
;
6773 else if (current_function_is_leaf
&& !df_regs_ever_live_p (5))
6774 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, 5);
6776 cfun
->machine
->base_reg
= gen_rtx_REG (Pmode
, BASE_REGNUM
);
6778 s390_register_info (clobbered_regs
);
6781 while (frame_size
!= cfun_frame_layout
.frame_size
);
6784 /* Update frame layout. Recompute actual register save data based on
6785 current info and update regs_ever_live for the special registers.
6786 May be called multiple times, but may never cause *more* registers
6787 to be saved than s390_init_frame_layout allocated room for. */
6790 s390_update_frame_layout (void)
6792 int clobbered_regs
[16];
6794 s390_register_info (clobbered_regs
);
6796 df_set_regs_ever_live (BASE_REGNUM
,
6797 clobbered_regs
[BASE_REGNUM
] ? true : false);
6798 df_set_regs_ever_live (RETURN_REGNUM
,
6799 clobbered_regs
[RETURN_REGNUM
] ? true : false);
6800 df_set_regs_ever_live (STACK_POINTER_REGNUM
,
6801 clobbered_regs
[STACK_POINTER_REGNUM
] ? true : false);
6803 if (cfun
->machine
->base_reg
)
6804 df_set_regs_ever_live (REGNO (cfun
->machine
->base_reg
), true);
6807 /* Return true if it is legal to put a value with MODE into REGNO. */
6810 s390_hard_regno_mode_ok (unsigned int regno
, enum machine_mode mode
)
6812 switch (REGNO_REG_CLASS (regno
))
6815 if (REGNO_PAIR_OK (regno
, mode
))
6817 if (mode
== SImode
|| mode
== DImode
)
6820 if (FLOAT_MODE_P (mode
) && GET_MODE_CLASS (mode
) != MODE_VECTOR_FLOAT
)
6825 if (FRAME_REGNO_P (regno
) && mode
== Pmode
)
6830 if (REGNO_PAIR_OK (regno
, mode
))
6833 || (mode
!= TFmode
&& mode
!= TCmode
&& mode
!= TDmode
))
6838 if (GET_MODE_CLASS (mode
) == MODE_CC
)
6842 if (REGNO_PAIR_OK (regno
, mode
))
6844 if (mode
== SImode
|| mode
== Pmode
)
6855 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
6858 s390_hard_regno_rename_ok (unsigned int old_reg
, unsigned int new_reg
)
6860 /* Once we've decided upon a register to use as base register, it must
6861 no longer be used for any other purpose. */
6862 if (cfun
->machine
->base_reg
)
6863 if (REGNO (cfun
->machine
->base_reg
) == old_reg
6864 || REGNO (cfun
->machine
->base_reg
) == new_reg
)
6870 /* Maximum number of registers to represent a value of mode MODE
6871 in a register of class CLASS. */
6874 s390_class_max_nregs (enum reg_class
class, enum machine_mode mode
)
6879 if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
6880 return 2 * ((GET_MODE_SIZE (mode
) / 2 + 8 - 1) / 8);
6882 return (GET_MODE_SIZE (mode
) + 8 - 1) / 8;
6884 return (GET_MODE_SIZE (mode
) + 4 - 1) / 4;
6888 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6891 /* Return true if register FROM can be eliminated via register TO. */
6894 s390_can_eliminate (int from
, int to
)
6896 /* On zSeries machines, we have not marked the base register as fixed.
6897 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
6898 If a function requires the base register, we say here that this
6899 elimination cannot be performed. This will cause reload to free
6900 up the base register (as if it were fixed). On the other hand,
6901 if the current function does *not* require the base register, we
6902 say here the elimination succeeds, which in turn allows reload
6903 to allocate the base register for any other purpose. */
6904 if (from
== BASE_REGNUM
&& to
== BASE_REGNUM
)
6906 if (TARGET_CPU_ZARCH
)
6908 s390_init_frame_layout ();
6909 return cfun
->machine
->base_reg
== NULL_RTX
;
6915 /* Everything else must point into the stack frame. */
6916 gcc_assert (to
== STACK_POINTER_REGNUM
6917 || to
== HARD_FRAME_POINTER_REGNUM
);
6919 gcc_assert (from
== FRAME_POINTER_REGNUM
6920 || from
== ARG_POINTER_REGNUM
6921 || from
== RETURN_ADDRESS_POINTER_REGNUM
);
6923 /* Make sure we actually saved the return address. */
6924 if (from
== RETURN_ADDRESS_POINTER_REGNUM
)
6925 if (!current_function_calls_eh_return
6926 && !current_function_stdarg
6927 && !cfun_frame_layout
.save_return_addr_p
)
6933 /* Return offset between register FROM and TO initially after prolog. */
6936 s390_initial_elimination_offset (int from
, int to
)
6938 HOST_WIDE_INT offset
;
6941 /* ??? Why are we called for non-eliminable pairs? */
6942 if (!s390_can_eliminate (from
, to
))
6947 case FRAME_POINTER_REGNUM
:
6948 offset
= (get_frame_size()
6949 + STACK_POINTER_OFFSET
6950 + current_function_outgoing_args_size
);
6953 case ARG_POINTER_REGNUM
:
6954 s390_init_frame_layout ();
6955 offset
= cfun_frame_layout
.frame_size
+ STACK_POINTER_OFFSET
;
6958 case RETURN_ADDRESS_POINTER_REGNUM
:
6959 s390_init_frame_layout ();
6960 index
= RETURN_REGNUM
- cfun_frame_layout
.first_save_gpr_slot
;
6961 gcc_assert (index
>= 0);
6962 offset
= cfun_frame_layout
.frame_size
+ cfun_frame_layout
.gprs_offset
;
6963 offset
+= index
* UNITS_PER_WORD
;
6977 /* Emit insn to save fpr REGNUM at offset OFFSET relative
6978 to register BASE. Return generated insn. */
6981 save_fpr (rtx base
, int offset
, int regnum
)
6984 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
6986 if (regnum
>= 16 && regnum
<= (16 + FP_ARG_NUM_REG
))
6987 set_mem_alias_set (addr
, get_varargs_alias_set ());
6989 set_mem_alias_set (addr
, get_frame_alias_set ());
6991 return emit_move_insn (addr
, gen_rtx_REG (DFmode
, regnum
));
6994 /* Emit insn to restore fpr REGNUM from offset OFFSET relative
6995 to register BASE. Return generated insn. */
6998 restore_fpr (rtx base
, int offset
, int regnum
)
7001 addr
= gen_rtx_MEM (DFmode
, plus_constant (base
, offset
));
7002 set_mem_alias_set (addr
, get_frame_alias_set ());
7004 return emit_move_insn (gen_rtx_REG (DFmode
, regnum
), addr
);
7007 /* Generate insn to save registers FIRST to LAST into
7008 the register save area located at offset OFFSET
7009 relative to register BASE. */
7012 save_gprs (rtx base
, int offset
, int first
, int last
)
7014 rtx addr
, insn
, note
;
7017 addr
= plus_constant (base
, offset
);
7018 addr
= gen_rtx_MEM (Pmode
, addr
);
7020 set_mem_alias_set (addr
, get_frame_alias_set ());
7022 /* Special-case single register. */
7026 insn
= gen_movdi (addr
, gen_rtx_REG (Pmode
, first
));
7028 insn
= gen_movsi (addr
, gen_rtx_REG (Pmode
, first
));
7030 RTX_FRAME_RELATED_P (insn
) = 1;
7035 insn
= gen_store_multiple (addr
,
7036 gen_rtx_REG (Pmode
, first
),
7037 GEN_INT (last
- first
+ 1));
7039 if (first
<= 6 && current_function_stdarg
)
7040 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
7042 rtx mem
= XEXP (XVECEXP (PATTERN (insn
), 0, i
), 0);
7045 set_mem_alias_set (mem
, get_varargs_alias_set ());
7048 /* We need to set the FRAME_RELATED flag on all SETs
7049 inside the store-multiple pattern.
7051 However, we must not emit DWARF records for registers 2..5
7052 if they are stored for use by variable arguments ...
7054 ??? Unfortunately, it is not enough to simply not the
7055 FRAME_RELATED flags for those SETs, because the first SET
7056 of the PARALLEL is always treated as if it had the flag
7057 set, even if it does not. Therefore we emit a new pattern
7058 without those registers as REG_FRAME_RELATED_EXPR note. */
7062 rtx pat
= PATTERN (insn
);
7064 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
7065 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
7066 RTX_FRAME_RELATED_P (XVECEXP (pat
, 0, i
)) = 1;
7068 RTX_FRAME_RELATED_P (insn
) = 1;
7072 addr
= plus_constant (base
, offset
+ (6 - first
) * UNITS_PER_WORD
);
7073 note
= gen_store_multiple (gen_rtx_MEM (Pmode
, addr
),
7074 gen_rtx_REG (Pmode
, 6),
7075 GEN_INT (last
- 6 + 1));
7076 note
= PATTERN (note
);
7079 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7080 note
, REG_NOTES (insn
));
7082 for (i
= 0; i
< XVECLEN (note
, 0); i
++)
7083 if (GET_CODE (XVECEXP (note
, 0, i
)) == SET
)
7084 RTX_FRAME_RELATED_P (XVECEXP (note
, 0, i
)) = 1;
7086 RTX_FRAME_RELATED_P (insn
) = 1;
7092 /* Generate insn to restore registers FIRST to LAST from
7093 the register save area located at offset OFFSET
7094 relative to register BASE. */
7097 restore_gprs (rtx base
, int offset
, int first
, int last
)
7101 addr
= plus_constant (base
, offset
);
7102 addr
= gen_rtx_MEM (Pmode
, addr
);
7103 set_mem_alias_set (addr
, get_frame_alias_set ());
7105 /* Special-case single register. */
7109 insn
= gen_movdi (gen_rtx_REG (Pmode
, first
), addr
);
7111 insn
= gen_movsi (gen_rtx_REG (Pmode
, first
), addr
);
7116 insn
= gen_load_multiple (gen_rtx_REG (Pmode
, first
),
7118 GEN_INT (last
- first
+ 1));
7122 /* Return insn sequence to load the GOT register. */
7124 static GTY(()) rtx got_symbol
;
7126 s390_load_got (void)
7132 got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
7133 SYMBOL_REF_FLAGS (got_symbol
) = SYMBOL_FLAG_LOCAL
;
7138 if (TARGET_CPU_ZARCH
)
7140 emit_move_insn (pic_offset_table_rtx
, got_symbol
);
7146 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, got_symbol
),
7147 UNSPEC_LTREL_OFFSET
);
7148 offset
= gen_rtx_CONST (Pmode
, offset
);
7149 offset
= force_const_mem (Pmode
, offset
);
7151 emit_move_insn (pic_offset_table_rtx
, offset
);
7153 offset
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, XEXP (offset
, 0)),
7155 offset
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, offset
);
7157 emit_move_insn (pic_offset_table_rtx
, offset
);
7160 insns
= get_insns ();
7165 /* Expand the prologue into a bunch of separate insns. */
7168 s390_emit_prologue (void)
7176 /* Complete frame layout. */
7178 s390_update_frame_layout ();
7180 /* Annotate all constant pool references to let the scheduler know
7181 they implicitly use the base register. */
7183 push_topmost_sequence ();
7185 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
7188 annotate_constant_pool_refs (&PATTERN (insn
));
7189 df_insn_rescan (insn
);
7192 pop_topmost_sequence ();
7194 /* Choose best register to use for temp use within prologue.
7195 See below for why TPF must use the register 1. */
7197 if (!has_hard_reg_initial_val (Pmode
, RETURN_REGNUM
)
7198 && !current_function_is_leaf
7199 && !TARGET_TPF_PROFILING
)
7200 temp_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7202 temp_reg
= gen_rtx_REG (Pmode
, 1);
7204 /* Save call saved gprs. */
7205 if (cfun_frame_layout
.first_save_gpr
!= -1)
7207 insn
= save_gprs (stack_pointer_rtx
,
7208 cfun_frame_layout
.gprs_offset
+
7209 UNITS_PER_WORD
* (cfun_frame_layout
.first_save_gpr
7210 - cfun_frame_layout
.first_save_gpr_slot
),
7211 cfun_frame_layout
.first_save_gpr
,
7212 cfun_frame_layout
.last_save_gpr
);
7216 /* Dummy insn to mark literal pool slot. */
7218 if (cfun
->machine
->base_reg
)
7219 emit_insn (gen_main_pool (cfun
->machine
->base_reg
));
7221 offset
= cfun_frame_layout
.f0_offset
;
7223 /* Save f0 and f2. */
7224 for (i
= 0; i
< 2; i
++)
7226 if (cfun_fpr_bit_p (i
))
7228 save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7231 else if (!TARGET_PACKED_STACK
)
7235 /* Save f4 and f6. */
7236 offset
= cfun_frame_layout
.f4_offset
;
7237 for (i
= 2; i
< 4; i
++)
7239 if (cfun_fpr_bit_p (i
))
7241 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7244 /* If f4 and f6 are call clobbered they are saved due to stdargs and
7245 therefore are not frame related. */
7246 if (!call_really_used_regs
[i
+ 16])
7247 RTX_FRAME_RELATED_P (insn
) = 1;
7249 else if (!TARGET_PACKED_STACK
)
7253 if (TARGET_PACKED_STACK
7254 && cfun_save_high_fprs_p
7255 && cfun_frame_layout
.f8_offset
+ cfun_frame_layout
.high_fprs
* 8 > 0)
7257 offset
= (cfun_frame_layout
.f8_offset
7258 + (cfun_frame_layout
.high_fprs
- 1) * 8);
7260 for (i
= 15; i
> 7 && offset
>= 0; i
--)
7261 if (cfun_fpr_bit_p (i
))
7263 insn
= save_fpr (stack_pointer_rtx
, offset
, i
+ 16);
7265 RTX_FRAME_RELATED_P (insn
) = 1;
7268 if (offset
>= cfun_frame_layout
.f8_offset
)
7272 if (!TARGET_PACKED_STACK
)
7273 next_fpr
= cfun_save_high_fprs_p
? 31 : 0;
7275 /* Decrement stack pointer. */
7277 if (cfun_frame_layout
.frame_size
> 0)
7279 rtx frame_off
= GEN_INT (-cfun_frame_layout
.frame_size
);
7281 if (s390_stack_size
)
7283 HOST_WIDE_INT stack_guard
;
7285 if (s390_stack_guard
)
7286 stack_guard
= s390_stack_guard
;
7289 /* If no value for stack guard is provided the smallest power of 2
7290 larger than the current frame size is chosen. */
7292 while (stack_guard
< cfun_frame_layout
.frame_size
)
7296 if (cfun_frame_layout
.frame_size
>= s390_stack_size
)
7298 warning (0, "frame size of function %qs is "
7299 HOST_WIDE_INT_PRINT_DEC
7300 " bytes exceeding user provided stack limit of "
7301 HOST_WIDE_INT_PRINT_DEC
" bytes. "
7302 "An unconditional trap is added.",
7303 current_function_name(), cfun_frame_layout
.frame_size
,
7305 emit_insn (gen_trap ());
7309 HOST_WIDE_INT stack_check_mask
= ((s390_stack_size
- 1)
7310 & ~(stack_guard
- 1));
7311 rtx t
= gen_rtx_AND (Pmode
, stack_pointer_rtx
,
7312 GEN_INT (stack_check_mask
));
7314 gen_cmpdi (t
, const0_rtx
);
7316 gen_cmpsi (t
, const0_rtx
);
7318 emit_insn (gen_conditional_trap (gen_rtx_EQ (CCmode
,
7319 gen_rtx_REG (CCmode
,
7326 if (s390_warn_framesize
> 0
7327 && cfun_frame_layout
.frame_size
>= s390_warn_framesize
)
7328 warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC
" bytes",
7329 current_function_name (), cfun_frame_layout
.frame_size
);
7331 if (s390_warn_dynamicstack_p
&& cfun
->calls_alloca
)
7332 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
7334 /* Save incoming stack pointer into temp reg. */
7335 if (TARGET_BACKCHAIN
|| next_fpr
)
7336 insn
= emit_insn (gen_move_insn (temp_reg
, stack_pointer_rtx
));
7338 /* Subtract frame size from stack pointer. */
7340 if (DISP_IN_RANGE (INTVAL (frame_off
)))
7342 insn
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7343 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7345 insn
= emit_insn (insn
);
7349 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
7350 frame_off
= force_const_mem (Pmode
, frame_off
);
7352 insn
= emit_insn (gen_add2_insn (stack_pointer_rtx
, frame_off
));
7353 annotate_constant_pool_refs (&PATTERN (insn
));
7356 RTX_FRAME_RELATED_P (insn
) = 1;
7358 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7359 gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
7360 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
7361 GEN_INT (-cfun_frame_layout
.frame_size
))),
7364 /* Set backchain. */
7366 if (TARGET_BACKCHAIN
)
7368 if (cfun_frame_layout
.backchain_offset
)
7369 addr
= gen_rtx_MEM (Pmode
,
7370 plus_constant (stack_pointer_rtx
,
7371 cfun_frame_layout
.backchain_offset
));
7373 addr
= gen_rtx_MEM (Pmode
, stack_pointer_rtx
);
7374 set_mem_alias_set (addr
, get_frame_alias_set ());
7375 insn
= emit_insn (gen_move_insn (addr
, temp_reg
));
7378 /* If we support asynchronous exceptions (e.g. for Java),
7379 we need to make sure the backchain pointer is set up
7380 before any possibly trapping memory access. */
7382 if (TARGET_BACKCHAIN
&& flag_non_call_exceptions
)
7384 addr
= gen_rtx_MEM (BLKmode
, gen_rtx_SCRATCH (VOIDmode
));
7385 emit_insn (gen_rtx_CLOBBER (VOIDmode
, addr
));
7389 /* Save fprs 8 - 15 (64 bit ABI). */
7391 if (cfun_save_high_fprs_p
&& next_fpr
)
7393 insn
= emit_insn (gen_add2_insn (temp_reg
,
7394 GEN_INT (cfun_frame_layout
.f8_offset
)));
7398 for (i
= 24; i
<= next_fpr
; i
++)
7399 if (cfun_fpr_bit_p (i
- 16))
7401 rtx addr
= plus_constant (stack_pointer_rtx
,
7402 cfun_frame_layout
.frame_size
7403 + cfun_frame_layout
.f8_offset
7406 insn
= save_fpr (temp_reg
, offset
, i
);
7408 RTX_FRAME_RELATED_P (insn
) = 1;
7410 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
7411 gen_rtx_SET (VOIDmode
,
7412 gen_rtx_MEM (DFmode
, addr
),
7413 gen_rtx_REG (DFmode
, i
)),
7418 /* Set frame pointer, if needed. */
7420 if (frame_pointer_needed
)
7422 insn
= emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
7423 RTX_FRAME_RELATED_P (insn
) = 1;
7426 /* Set up got pointer, if needed. */
7428 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
7430 rtx insns
= s390_load_got ();
7432 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
7433 annotate_constant_pool_refs (&PATTERN (insn
));
7438 if (TARGET_TPF_PROFILING
)
7440 /* Generate a BAS instruction to serve as a function
7441 entry intercept to facilitate the use of tracing
7442 algorithms located at the branch target. */
7443 emit_insn (gen_prologue_tpf ());
7445 /* Emit a blockage here so that all code
7446 lies between the profiling mechanisms. */
7447 emit_insn (gen_blockage ());
7451 /* Expand the epilogue into a bunch of separate insns. */
7454 s390_emit_epilogue (bool sibcall
)
7456 rtx frame_pointer
, return_reg
;
7457 int area_bottom
, area_top
, offset
= 0;
7462 if (TARGET_TPF_PROFILING
)
7465 /* Generate a BAS instruction to serve as a function
7466 entry intercept to facilitate the use of tracing
7467 algorithms located at the branch target. */
7469 /* Emit a blockage here so that all code
7470 lies between the profiling mechanisms. */
7471 emit_insn (gen_blockage ());
7473 emit_insn (gen_epilogue_tpf ());
7476 /* Check whether to use frame or stack pointer for restore. */
7478 frame_pointer
= (frame_pointer_needed
7479 ? hard_frame_pointer_rtx
: stack_pointer_rtx
);
7481 s390_frame_area (&area_bottom
, &area_top
);
7483 /* Check whether we can access the register save area.
7484 If not, increment the frame pointer as required. */
7486 if (area_top
<= area_bottom
)
7488 /* Nothing to restore. */
7490 else if (DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_bottom
)
7491 && DISP_IN_RANGE (cfun_frame_layout
.frame_size
+ area_top
- 1))
7493 /* Area is in range. */
7494 offset
= cfun_frame_layout
.frame_size
;
7498 rtx insn
, frame_off
;
7500 offset
= area_bottom
< 0 ? -area_bottom
: 0;
7501 frame_off
= GEN_INT (cfun_frame_layout
.frame_size
- offset
);
7503 if (DISP_IN_RANGE (INTVAL (frame_off
)))
7505 insn
= gen_rtx_SET (VOIDmode
, frame_pointer
,
7506 gen_rtx_PLUS (Pmode
, frame_pointer
, frame_off
));
7507 insn
= emit_insn (insn
);
7511 if (!CONST_OK_FOR_K (INTVAL (frame_off
)))
7512 frame_off
= force_const_mem (Pmode
, frame_off
);
7514 insn
= emit_insn (gen_add2_insn (frame_pointer
, frame_off
));
7515 annotate_constant_pool_refs (&PATTERN (insn
));
7519 /* Restore call saved fprs. */
7523 if (cfun_save_high_fprs_p
)
7525 next_offset
= cfun_frame_layout
.f8_offset
;
7526 for (i
= 24; i
< 32; i
++)
7528 if (cfun_fpr_bit_p (i
- 16))
7530 restore_fpr (frame_pointer
,
7531 offset
+ next_offset
, i
);
7540 next_offset
= cfun_frame_layout
.f4_offset
;
7541 for (i
= 18; i
< 20; i
++)
7543 if (cfun_fpr_bit_p (i
- 16))
7545 restore_fpr (frame_pointer
,
7546 offset
+ next_offset
, i
);
7549 else if (!TARGET_PACKED_STACK
)
7555 /* Return register. */
7557 return_reg
= gen_rtx_REG (Pmode
, RETURN_REGNUM
);
7559 /* Restore call saved gprs. */
7561 if (cfun_frame_layout
.first_restore_gpr
!= -1)
7566 /* Check for global register and save them
7567 to stack location from where they get restored. */
7569 for (i
= cfun_frame_layout
.first_restore_gpr
;
7570 i
<= cfun_frame_layout
.last_restore_gpr
;
7573 /* These registers are special and need to be
7574 restored in any case. */
7575 if (i
== STACK_POINTER_REGNUM
7576 || i
== RETURN_REGNUM
7578 || (flag_pic
&& i
== (int)PIC_OFFSET_TABLE_REGNUM
))
7583 addr
= plus_constant (frame_pointer
,
7584 offset
+ cfun_frame_layout
.gprs_offset
7585 + (i
- cfun_frame_layout
.first_save_gpr_slot
)
7587 addr
= gen_rtx_MEM (Pmode
, addr
);
7588 set_mem_alias_set (addr
, get_frame_alias_set ());
7589 emit_move_insn (addr
, gen_rtx_REG (Pmode
, i
));
7595 /* Fetch return address from stack before load multiple,
7596 this will do good for scheduling. */
7598 if (cfun_frame_layout
.save_return_addr_p
7599 || (cfun_frame_layout
.first_restore_gpr
< BASE_REGNUM
7600 && cfun_frame_layout
.last_restore_gpr
> RETURN_REGNUM
))
7602 int return_regnum
= find_unused_clobbered_reg();
7605 return_reg
= gen_rtx_REG (Pmode
, return_regnum
);
7607 addr
= plus_constant (frame_pointer
,
7608 offset
+ cfun_frame_layout
.gprs_offset
7610 - cfun_frame_layout
.first_save_gpr_slot
)
7612 addr
= gen_rtx_MEM (Pmode
, addr
);
7613 set_mem_alias_set (addr
, get_frame_alias_set ());
7614 emit_move_insn (return_reg
, addr
);
7618 insn
= restore_gprs (frame_pointer
,
7619 offset
+ cfun_frame_layout
.gprs_offset
7620 + (cfun_frame_layout
.first_restore_gpr
7621 - cfun_frame_layout
.first_save_gpr_slot
)
7623 cfun_frame_layout
.first_restore_gpr
,
7624 cfun_frame_layout
.last_restore_gpr
);
7631 /* Return to caller. */
7633 p
= rtvec_alloc (2);
7635 RTVEC_ELT (p
, 0) = gen_rtx_RETURN (VOIDmode
);
7636 RTVEC_ELT (p
, 1) = gen_rtx_USE (VOIDmode
, return_reg
);
7637 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode
, p
));
7642 /* Return the size in bytes of a function argument of
7643 type TYPE and/or mode MODE. At least one of TYPE or
7644 MODE must be specified. */
7647 s390_function_arg_size (enum machine_mode mode
, const_tree type
)
7650 return int_size_in_bytes (type
);
7652 /* No type info available for some library calls ... */
7653 if (mode
!= BLKmode
)
7654 return GET_MODE_SIZE (mode
);
7656 /* If we have neither type nor mode, abort */
7660 /* Return true if a function argument of type TYPE and mode MODE
7661 is to be passed in a floating-point register, if available. */
7664 s390_function_arg_float (enum machine_mode mode
, tree type
)
7666 int size
= s390_function_arg_size (mode
, type
);
7670 /* Soft-float changes the ABI: no floating-point registers are used. */
7671 if (TARGET_SOFT_FLOAT
)
7674 /* No type info available for some library calls ... */
7676 return mode
== SFmode
|| mode
== DFmode
|| mode
== SDmode
|| mode
== DDmode
;
7678 /* The ABI says that record types with a single member are treated
7679 just like that member would be. */
7680 while (TREE_CODE (type
) == RECORD_TYPE
)
7682 tree field
, single
= NULL_TREE
;
7684 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
7686 if (TREE_CODE (field
) != FIELD_DECL
)
7689 if (single
== NULL_TREE
)
7690 single
= TREE_TYPE (field
);
7695 if (single
== NULL_TREE
)
7701 return TREE_CODE (type
) == REAL_TYPE
;
7704 /* Return true if a function argument of type TYPE and mode MODE
7705 is to be passed in an integer register, or a pair of integer
7706 registers, if available. */
7709 s390_function_arg_integer (enum machine_mode mode
, tree type
)
7711 int size
= s390_function_arg_size (mode
, type
);
7715 /* No type info available for some library calls ... */
7717 return GET_MODE_CLASS (mode
) == MODE_INT
7718 || (TARGET_SOFT_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
));
7720 /* We accept small integral (and similar) types. */
7721 if (INTEGRAL_TYPE_P (type
)
7722 || POINTER_TYPE_P (type
)
7723 || TREE_CODE (type
) == OFFSET_TYPE
7724 || (TARGET_SOFT_FLOAT
&& TREE_CODE (type
) == REAL_TYPE
))
7727 /* We also accept structs of size 1, 2, 4, 8 that are not
7728 passed in floating-point registers. */
7729 if (AGGREGATE_TYPE_P (type
)
7730 && exact_log2 (size
) >= 0
7731 && !s390_function_arg_float (mode
, type
))
7737 /* Return 1 if a function argument of type TYPE and mode MODE
7738 is to be passed by reference. The ABI specifies that only
7739 structures of size 1, 2, 4, or 8 bytes are passed by value,
7740 all other structures (and complex numbers) are passed by
7744 s390_pass_by_reference (CUMULATIVE_ARGS
*ca ATTRIBUTE_UNUSED
,
7745 enum machine_mode mode
, const_tree type
,
7746 bool named ATTRIBUTE_UNUSED
)
7748 int size
= s390_function_arg_size (mode
, type
);
7754 if (AGGREGATE_TYPE_P (type
) && exact_log2 (size
) < 0)
7757 if (TREE_CODE (type
) == COMPLEX_TYPE
7758 || TREE_CODE (type
) == VECTOR_TYPE
)
7765 /* Update the data in CUM to advance over an argument of mode MODE and
7766 data type TYPE. (TYPE is null for libcalls where that information
7767 may not be available.). The boolean NAMED specifies whether the
7768 argument is a named argument (as opposed to an unnamed argument
7769 matching an ellipsis). */
7772 s390_function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
,
7773 tree type
, int named ATTRIBUTE_UNUSED
)
7775 if (s390_function_arg_float (mode
, type
))
7779 else if (s390_function_arg_integer (mode
, type
))
7781 int size
= s390_function_arg_size (mode
, type
);
7782 cum
->gprs
+= ((size
+ UNITS_PER_WORD
-1) / UNITS_PER_WORD
);
7788 /* Define where to put the arguments to a function.
7789 Value is zero to push the argument on the stack,
7790 or a hard register in which to store the argument.
7792 MODE is the argument's machine mode.
7793 TYPE is the data type of the argument (as a tree).
7794 This is null for libcalls where that information may
7796 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7797 the preceding args and about the function being called.
7798 NAMED is nonzero if this argument is a named parameter
7799 (otherwise it is an extra parameter matching an ellipsis).
7801 On S/390, we use general purpose registers 2 through 6 to
7802 pass integer, pointer, and certain structure arguments, and
7803 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
7804 to pass floating point arguments. All remaining arguments
7805 are pushed to the stack. */
7808 s390_function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
7809 int named ATTRIBUTE_UNUSED
)
7811 if (s390_function_arg_float (mode
, type
))
7813 if (cum
->fprs
+ 1 > FP_ARG_NUM_REG
)
7816 return gen_rtx_REG (mode
, cum
->fprs
+ 16);
7818 else if (s390_function_arg_integer (mode
, type
))
7820 int size
= s390_function_arg_size (mode
, type
);
7821 int n_gprs
= (size
+ UNITS_PER_WORD
-1) / UNITS_PER_WORD
;
7823 if (cum
->gprs
+ n_gprs
> GP_ARG_NUM_REG
)
7826 return gen_rtx_REG (mode
, cum
->gprs
+ 2);
7829 /* After the real arguments, expand_call calls us once again
7830 with a void_type_node type. Whatever we return here is
7831 passed as operand 2 to the call expanders.
7833 We don't need this feature ... */
7834 else if (type
== void_type_node
)
7840 /* Return true if return values of type TYPE should be returned
7841 in a memory buffer whose address is passed by the caller as
7842 hidden first argument. */
7845 s390_return_in_memory (const_tree type
, const_tree fundecl ATTRIBUTE_UNUSED
)
7847 /* We accept small integral (and similar) types. */
7848 if (INTEGRAL_TYPE_P (type
)
7849 || POINTER_TYPE_P (type
)
7850 || TREE_CODE (type
) == OFFSET_TYPE
7851 || TREE_CODE (type
) == REAL_TYPE
)
7852 return int_size_in_bytes (type
) > 8;
7854 /* Aggregates and similar constructs are always returned
7856 if (AGGREGATE_TYPE_P (type
)
7857 || TREE_CODE (type
) == COMPLEX_TYPE
7858 || TREE_CODE (type
) == VECTOR_TYPE
)
7861 /* ??? We get called on all sorts of random stuff from
7862 aggregate_value_p. We can't abort, but it's not clear
7863 what's safe to return. Pretend it's a struct I guess. */
7867 /* Define where to return a (scalar) value of type TYPE.
7868 If TYPE is null, define where to return a (scalar)
7869 value of mode MODE from a libcall. */
7872 s390_function_value (const_tree type
, enum machine_mode mode
)
7876 int unsignedp
= TYPE_UNSIGNED (type
);
7877 mode
= promote_mode (type
, TYPE_MODE (type
), &unsignedp
, 1);
7880 gcc_assert (GET_MODE_CLASS (mode
) == MODE_INT
|| SCALAR_FLOAT_MODE_P (mode
));
7881 gcc_assert (GET_MODE_SIZE (mode
) <= 8);
7883 if (TARGET_HARD_FLOAT
&& SCALAR_FLOAT_MODE_P (mode
))
7884 return gen_rtx_REG (mode
, 16);
7886 return gen_rtx_REG (mode
, 2);
7890 /* Create and return the va_list datatype.
7892 On S/390, va_list is an array type equivalent to
7894 typedef struct __va_list_tag
7898 void *__overflow_arg_area;
7899 void *__reg_save_area;
7902 where __gpr and __fpr hold the number of general purpose
7903 or floating point arguments used up to now, respectively,
7904 __overflow_arg_area points to the stack location of the
7905 next argument passed on the stack, and __reg_save_area
7906 always points to the start of the register area in the
7907 call frame of the current function. The function prologue
7908 saves all registers used for argument passing into this
7909 area if the function uses variable arguments. */
7912 s390_build_builtin_va_list (void)
7914 tree f_gpr
, f_fpr
, f_ovf
, f_sav
, record
, type_decl
;
7916 record
= lang_hooks
.types
.make_type (RECORD_TYPE
);
7919 build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
7921 f_gpr
= build_decl (FIELD_DECL
, get_identifier ("__gpr"),
7922 long_integer_type_node
);
7923 f_fpr
= build_decl (FIELD_DECL
, get_identifier ("__fpr"),
7924 long_integer_type_node
);
7925 f_ovf
= build_decl (FIELD_DECL
, get_identifier ("__overflow_arg_area"),
7927 f_sav
= build_decl (FIELD_DECL
, get_identifier ("__reg_save_area"),
7930 va_list_gpr_counter_field
= f_gpr
;
7931 va_list_fpr_counter_field
= f_fpr
;
7933 DECL_FIELD_CONTEXT (f_gpr
) = record
;
7934 DECL_FIELD_CONTEXT (f_fpr
) = record
;
7935 DECL_FIELD_CONTEXT (f_ovf
) = record
;
7936 DECL_FIELD_CONTEXT (f_sav
) = record
;
7938 TREE_CHAIN (record
) = type_decl
;
7939 TYPE_NAME (record
) = type_decl
;
7940 TYPE_FIELDS (record
) = f_gpr
;
7941 TREE_CHAIN (f_gpr
) = f_fpr
;
7942 TREE_CHAIN (f_fpr
) = f_ovf
;
7943 TREE_CHAIN (f_ovf
) = f_sav
;
7945 layout_type (record
);
7947 /* The correct type is an array type of one element. */
7948 return build_array_type (record
, build_index_type (size_zero_node
));
7951 /* Implement va_start by filling the va_list structure VALIST.
7952 STDARG_P is always true, and ignored.
7953 NEXTARG points to the first anonymous stack argument.
7955 The following global variables are used to initialize
7956 the va_list structure:
7958 current_function_args_info:
7959 holds number of gprs and fprs used for named arguments.
7960 current_function_arg_offset_rtx:
7961 holds the offset of the first anonymous stack argument
7962 (relative to the virtual arg pointer). */
7965 s390_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
7967 HOST_WIDE_INT n_gpr
, n_fpr
;
7969 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
7970 tree gpr
, fpr
, ovf
, sav
, t
;
7972 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
7973 f_fpr
= TREE_CHAIN (f_gpr
);
7974 f_ovf
= TREE_CHAIN (f_fpr
);
7975 f_sav
= TREE_CHAIN (f_ovf
);
7977 valist
= build_va_arg_indirect_ref (valist
);
7978 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
7979 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
7980 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
7981 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
7983 /* Count number of gp and fp argument registers used. */
7985 n_gpr
= current_function_args_info
.gprs
;
7986 n_fpr
= current_function_args_info
.fprs
;
7988 if (cfun
->va_list_gpr_size
)
7990 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (gpr
), gpr
,
7991 build_int_cst (NULL_TREE
, n_gpr
));
7992 TREE_SIDE_EFFECTS (t
) = 1;
7993 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
7996 if (cfun
->va_list_fpr_size
)
7998 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (fpr
), fpr
,
7999 build_int_cst (NULL_TREE
, n_fpr
));
8000 TREE_SIDE_EFFECTS (t
) = 1;
8001 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8004 /* Find the overflow area. */
8005 if (n_gpr
+ cfun
->va_list_gpr_size
> GP_ARG_NUM_REG
8006 || n_fpr
+ cfun
->va_list_fpr_size
> FP_ARG_NUM_REG
)
8008 t
= make_tree (TREE_TYPE (ovf
), virtual_incoming_args_rtx
);
8010 off
= INTVAL (current_function_arg_offset_rtx
);
8011 off
= off
< 0 ? 0 : off
;
8012 if (TARGET_DEBUG_ARG
)
8013 fprintf (stderr
, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
8014 (int)n_gpr
, (int)n_fpr
, off
);
8016 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovf
), t
, size_int (off
));
8018 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (ovf
), ovf
, t
);
8019 TREE_SIDE_EFFECTS (t
) = 1;
8020 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8023 /* Find the register save area. */
8024 if ((cfun
->va_list_gpr_size
&& n_gpr
< GP_ARG_NUM_REG
)
8025 || (cfun
->va_list_fpr_size
&& n_fpr
< FP_ARG_NUM_REG
))
8027 t
= make_tree (TREE_TYPE (sav
), return_address_pointer_rtx
);
8028 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (sav
), t
,
8029 size_int (-RETURN_REGNUM
* UNITS_PER_WORD
));
8031 t
= build2 (GIMPLE_MODIFY_STMT
, TREE_TYPE (sav
), sav
, t
);
8032 TREE_SIDE_EFFECTS (t
) = 1;
8033 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
8037 /* Implement va_arg by updating the va_list structure
8038 VALIST as required to retrieve an argument of type
8039 TYPE, and returning that argument.
8041 Generates code equivalent to:
8043 if (integral value) {
8044 if (size <= 4 && args.gpr < 5 ||
8045 size > 4 && args.gpr < 4 )
8046 ret = args.reg_save_area[args.gpr+8]
8048 ret = *args.overflow_arg_area++;
8049 } else if (float value) {
8051 ret = args.reg_save_area[args.fpr+64]
8053 ret = *args.overflow_arg_area++;
8054 } else if (aggregate value) {
8056 ret = *args.reg_save_area[args.gpr]
8058 ret = **args.overflow_arg_area++;
8062 s390_gimplify_va_arg (tree valist
, tree type
, tree
*pre_p
,
8063 tree
*post_p ATTRIBUTE_UNUSED
)
8065 tree f_gpr
, f_fpr
, f_ovf
, f_sav
;
8066 tree gpr
, fpr
, ovf
, sav
, reg
, t
, u
;
8067 int indirect_p
, size
, n_reg
, sav_ofs
, sav_scale
, max_reg
;
8068 tree lab_false
, lab_over
, addr
;
8070 f_gpr
= TYPE_FIELDS (TREE_TYPE (va_list_type_node
));
8071 f_fpr
= TREE_CHAIN (f_gpr
);
8072 f_ovf
= TREE_CHAIN (f_fpr
);
8073 f_sav
= TREE_CHAIN (f_ovf
);
8075 valist
= build_va_arg_indirect_ref (valist
);
8076 gpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_gpr
), valist
, f_gpr
, NULL_TREE
);
8077 fpr
= build3 (COMPONENT_REF
, TREE_TYPE (f_fpr
), valist
, f_fpr
, NULL_TREE
);
8078 ovf
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovf
), valist
, f_ovf
, NULL_TREE
);
8079 sav
= build3 (COMPONENT_REF
, TREE_TYPE (f_sav
), valist
, f_sav
, NULL_TREE
);
8081 size
= int_size_in_bytes (type
);
8083 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
8085 if (TARGET_DEBUG_ARG
)
8087 fprintf (stderr
, "va_arg: aggregate type");
8091 /* Aggregates are passed by reference. */
8096 /* kernel stack layout on 31 bit: It is assumed here that no padding
8097 will be added by s390_frame_info because for va_args always an even
8098 number of gprs has to be saved r15-r2 = 14 regs. */
8099 sav_ofs
= 2 * UNITS_PER_WORD
;
8100 sav_scale
= UNITS_PER_WORD
;
8101 size
= UNITS_PER_WORD
;
8102 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8104 else if (s390_function_arg_float (TYPE_MODE (type
), type
))
8106 if (TARGET_DEBUG_ARG
)
8108 fprintf (stderr
, "va_arg: float type");
8112 /* FP args go in FP registers, if present. */
8116 sav_ofs
= 16 * UNITS_PER_WORD
;
8118 max_reg
= FP_ARG_NUM_REG
- n_reg
;
8122 if (TARGET_DEBUG_ARG
)
8124 fprintf (stderr
, "va_arg: other type");
8128 /* Otherwise into GP registers. */
8131 n_reg
= (size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
8133 /* kernel stack layout on 31 bit: It is assumed here that no padding
8134 will be added by s390_frame_info because for va_args always an even
8135 number of gprs has to be saved r15-r2 = 14 regs. */
8136 sav_ofs
= 2 * UNITS_PER_WORD
;
8138 if (size
< UNITS_PER_WORD
)
8139 sav_ofs
+= UNITS_PER_WORD
- size
;
8141 sav_scale
= UNITS_PER_WORD
;
8142 max_reg
= GP_ARG_NUM_REG
- n_reg
;
8145 /* Pull the value out of the saved registers ... */
8147 lab_false
= create_artificial_label ();
8148 lab_over
= create_artificial_label ();
8149 addr
= create_tmp_var (ptr_type_node
, "addr");
8150 DECL_POINTER_ALIAS_SET (addr
) = get_varargs_alias_set ();
8152 t
= fold_convert (TREE_TYPE (reg
), size_int (max_reg
));
8153 t
= build2 (GT_EXPR
, boolean_type_node
, reg
, t
);
8154 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
8155 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
8156 gimplify_and_add (t
, pre_p
);
8158 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, sav
,
8159 size_int (sav_ofs
));
8160 u
= build2 (MULT_EXPR
, TREE_TYPE (reg
), reg
,
8161 fold_convert (TREE_TYPE (reg
), size_int (sav_scale
)));
8162 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
, fold_convert (sizetype
, u
));
8164 t
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, addr
, t
);
8165 gimplify_and_add (t
, pre_p
);
8167 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
8168 gimplify_and_add (t
, pre_p
);
8170 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
8171 append_to_statement_list (t
, pre_p
);
8174 /* ... Otherwise out of the overflow area. */
8177 if (size
< UNITS_PER_WORD
)
8178 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8179 size_int (UNITS_PER_WORD
- size
));
8181 gimplify_expr (&t
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
8183 u
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, addr
, t
);
8184 gimplify_and_add (u
, pre_p
);
8186 t
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, t
,
8188 t
= build2 (GIMPLE_MODIFY_STMT
, ptr_type_node
, ovf
, t
);
8189 gimplify_and_add (t
, pre_p
);
8191 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
8192 append_to_statement_list (t
, pre_p
);
8195 /* Increment register save count. */
8197 u
= build2 (PREINCREMENT_EXPR
, TREE_TYPE (reg
), reg
,
8198 fold_convert (TREE_TYPE (reg
), size_int (n_reg
)));
8199 gimplify_and_add (u
, pre_p
);
8203 t
= build_pointer_type (build_pointer_type (type
));
8204 addr
= fold_convert (t
, addr
);
8205 addr
= build_va_arg_indirect_ref (addr
);
8209 t
= build_pointer_type (type
);
8210 addr
= fold_convert (t
, addr
);
8213 return build_va_arg_indirect_ref (addr
);
8221 S390_BUILTIN_THREAD_POINTER
,
8222 S390_BUILTIN_SET_THREAD_POINTER
,
8227 static unsigned int const code_for_builtin_64
[S390_BUILTIN_max
] = {
8232 static unsigned int const code_for_builtin_31
[S390_BUILTIN_max
] = {
8238 s390_init_builtins (void)
8242 ftype
= build_function_type (ptr_type_node
, void_list_node
);
8243 add_builtin_function ("__builtin_thread_pointer", ftype
,
8244 S390_BUILTIN_THREAD_POINTER
, BUILT_IN_MD
,
8247 ftype
= build_function_type_list (void_type_node
, ptr_type_node
, NULL_TREE
);
8248 add_builtin_function ("__builtin_set_thread_pointer", ftype
,
8249 S390_BUILTIN_SET_THREAD_POINTER
, BUILT_IN_MD
,
8253 /* Expand an expression EXP that calls a built-in function,
8254 with result going to TARGET if that's convenient
8255 (and in mode MODE if that's convenient).
8256 SUBTARGET may be used as the target for computing one of EXP's operands.
8257 IGNORE is nonzero if the value is to be ignored. */
8260 s390_expand_builtin (tree exp
, rtx target
, rtx subtarget ATTRIBUTE_UNUSED
,
8261 enum machine_mode mode ATTRIBUTE_UNUSED
,
8262 int ignore ATTRIBUTE_UNUSED
)
8266 unsigned int const *code_for_builtin
=
8267 TARGET_64BIT
? code_for_builtin_64
: code_for_builtin_31
;
8269 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
8270 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
8271 enum insn_code icode
;
8272 rtx op
[MAX_ARGS
], pat
;
8276 call_expr_arg_iterator iter
;
8278 if (fcode
>= S390_BUILTIN_max
)
8279 internal_error ("bad builtin fcode");
8280 icode
= code_for_builtin
[fcode
];
8282 internal_error ("bad builtin fcode");
8284 nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
8287 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
8289 const struct insn_operand_data
*insn_op
;
8291 if (arg
== error_mark_node
)
8293 if (arity
> MAX_ARGS
)
8296 insn_op
= &insn_data
[icode
].operand
[arity
+ nonvoid
];
8298 op
[arity
] = expand_expr (arg
, NULL_RTX
, insn_op
->mode
, 0);
8300 if (!(*insn_op
->predicate
) (op
[arity
], insn_op
->mode
))
8301 op
[arity
] = copy_to_mode_reg (insn_op
->mode
, op
[arity
]);
8307 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
8309 || GET_MODE (target
) != tmode
8310 || !(*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
8311 target
= gen_reg_rtx (tmode
);
8317 pat
= GEN_FCN (icode
) (target
);
8321 pat
= GEN_FCN (icode
) (target
, op
[0]);
8323 pat
= GEN_FCN (icode
) (op
[0]);
8326 pat
= GEN_FCN (icode
) (target
, op
[0], op
[1]);
8342 /* Output assembly code for the trampoline template to
8345 On S/390, we use gpr 1 internally in the trampoline code;
8346 gpr 0 is used to hold the static chain. */
8349 s390_trampoline_template (FILE *file
)
8352 op
[0] = gen_rtx_REG (Pmode
, 0);
8353 op
[1] = gen_rtx_REG (Pmode
, 1);
8357 output_asm_insn ("basr\t%1,0", op
);
8358 output_asm_insn ("lmg\t%0,%1,14(%1)", op
);
8359 output_asm_insn ("br\t%1", op
);
8360 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 10));
8364 output_asm_insn ("basr\t%1,0", op
);
8365 output_asm_insn ("lm\t%0,%1,6(%1)", op
);
8366 output_asm_insn ("br\t%1", op
);
8367 ASM_OUTPUT_SKIP (file
, (HOST_WIDE_INT
)(TRAMPOLINE_SIZE
- 8));
8371 /* Emit RTL insns to initialize the variable parts of a trampoline.
8372 FNADDR is an RTX for the address of the function's pure code.
8373 CXT is an RTX for the static chain value for the function. */
8376 s390_initialize_trampoline (rtx addr
, rtx fnaddr
, rtx cxt
)
8378 emit_move_insn (gen_rtx_MEM (Pmode
,
8379 memory_address (Pmode
,
8380 plus_constant (addr
, (TARGET_64BIT
? 16 : 8)))), cxt
);
8381 emit_move_insn (gen_rtx_MEM (Pmode
,
8382 memory_address (Pmode
,
8383 plus_constant (addr
, (TARGET_64BIT
? 24 : 12)))), fnaddr
);
8386 /* Output assembler code to FILE to increment profiler label # LABELNO
8387 for profiling a function entry. */
8390 s390_function_profiler (FILE *file
, int labelno
)
8395 ASM_GENERATE_INTERNAL_LABEL (label
, "LP", labelno
);
8397 fprintf (file
, "# function profiler \n");
8399 op
[0] = gen_rtx_REG (Pmode
, RETURN_REGNUM
);
8400 op
[1] = gen_rtx_REG (Pmode
, STACK_POINTER_REGNUM
);
8401 op
[1] = gen_rtx_MEM (Pmode
, plus_constant (op
[1], UNITS_PER_WORD
));
8403 op
[2] = gen_rtx_REG (Pmode
, 1);
8404 op
[3] = gen_rtx_SYMBOL_REF (Pmode
, label
);
8405 SYMBOL_REF_FLAGS (op
[3]) = SYMBOL_FLAG_LOCAL
;
8407 op
[4] = gen_rtx_SYMBOL_REF (Pmode
, "_mcount");
8410 op
[4] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[4]), UNSPEC_PLT
);
8411 op
[4] = gen_rtx_CONST (Pmode
, op
[4]);
8416 output_asm_insn ("stg\t%0,%1", op
);
8417 output_asm_insn ("larl\t%2,%3", op
);
8418 output_asm_insn ("brasl\t%0,%4", op
);
8419 output_asm_insn ("lg\t%0,%1", op
);
8423 op
[6] = gen_label_rtx ();
8425 output_asm_insn ("st\t%0,%1", op
);
8426 output_asm_insn ("bras\t%2,%l6", op
);
8427 output_asm_insn (".long\t%4", op
);
8428 output_asm_insn (".long\t%3", op
);
8429 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
8430 output_asm_insn ("l\t%0,0(%2)", op
);
8431 output_asm_insn ("l\t%2,4(%2)", op
);
8432 output_asm_insn ("basr\t%0,%0", op
);
8433 output_asm_insn ("l\t%0,%1", op
);
8437 op
[5] = gen_label_rtx ();
8438 op
[6] = gen_label_rtx ();
8440 output_asm_insn ("st\t%0,%1", op
);
8441 output_asm_insn ("bras\t%2,%l6", op
);
8442 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[5]));
8443 output_asm_insn (".long\t%4-%l5", op
);
8444 output_asm_insn (".long\t%3-%l5", op
);
8445 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[6]));
8446 output_asm_insn ("lr\t%0,%2", op
);
8447 output_asm_insn ("a\t%0,0(%2)", op
);
8448 output_asm_insn ("a\t%2,4(%2)", op
);
8449 output_asm_insn ("basr\t%0,%0", op
);
8450 output_asm_insn ("l\t%0,%1", op
);
8454 /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
8455 into its SYMBOL_REF_FLAGS. */
8458 s390_encode_section_info (tree decl
, rtx rtl
, int first
)
8460 default_encode_section_info (decl
, rtl
, first
);
8462 /* If a variable has a forced alignment to < 2 bytes, mark it with
8463 SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL operand. */
8464 if (TREE_CODE (decl
) == VAR_DECL
8465 && DECL_USER_ALIGN (decl
) && DECL_ALIGN (decl
) < 16)
8466 SYMBOL_REF_FLAGS (XEXP (rtl
, 0)) |= SYMBOL_FLAG_ALIGN1
;
8469 /* Output thunk to FILE that implements a C++ virtual function call (with
8470 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
8471 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
8472 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
8473 relative to the resulting this pointer. */
8476 s390_output_mi_thunk (FILE *file
, tree thunk ATTRIBUTE_UNUSED
,
8477 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
8483 /* Operand 0 is the target function. */
8484 op
[0] = XEXP (DECL_RTL (function
), 0);
8485 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (op
[0]))
8488 op
[0] = gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
[0]),
8489 TARGET_64BIT
? UNSPEC_PLT
: UNSPEC_GOT
);
8490 op
[0] = gen_rtx_CONST (Pmode
, op
[0]);
8493 /* Operand 1 is the 'this' pointer. */
8494 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
8495 op
[1] = gen_rtx_REG (Pmode
, 3);
8497 op
[1] = gen_rtx_REG (Pmode
, 2);
8499 /* Operand 2 is the delta. */
8500 op
[2] = GEN_INT (delta
);
8502 /* Operand 3 is the vcall_offset. */
8503 op
[3] = GEN_INT (vcall_offset
);
8505 /* Operand 4 is the temporary register. */
8506 op
[4] = gen_rtx_REG (Pmode
, 1);
8508 /* Operands 5 to 8 can be used as labels. */
8514 /* Operand 9 can be used for temporary register. */
8517 /* Generate code. */
8520 /* Setup literal pool pointer if required. */
8521 if ((!DISP_IN_RANGE (delta
)
8522 && !CONST_OK_FOR_K (delta
)
8523 && !CONST_OK_FOR_Os (delta
))
8524 || (!DISP_IN_RANGE (vcall_offset
)
8525 && !CONST_OK_FOR_K (vcall_offset
)
8526 && !CONST_OK_FOR_Os (vcall_offset
)))
8528 op
[5] = gen_label_rtx ();
8529 output_asm_insn ("larl\t%4,%5", op
);
8532 /* Add DELTA to this pointer. */
8535 if (CONST_OK_FOR_J (delta
))
8536 output_asm_insn ("la\t%1,%2(%1)", op
);
8537 else if (DISP_IN_RANGE (delta
))
8538 output_asm_insn ("lay\t%1,%2(%1)", op
);
8539 else if (CONST_OK_FOR_K (delta
))
8540 output_asm_insn ("aghi\t%1,%2", op
);
8541 else if (CONST_OK_FOR_Os (delta
))
8542 output_asm_insn ("agfi\t%1,%2", op
);
8545 op
[6] = gen_label_rtx ();
8546 output_asm_insn ("agf\t%1,%6-%5(%4)", op
);
8550 /* Perform vcall adjustment. */
8553 if (DISP_IN_RANGE (vcall_offset
))
8555 output_asm_insn ("lg\t%4,0(%1)", op
);
8556 output_asm_insn ("ag\t%1,%3(%4)", op
);
8558 else if (CONST_OK_FOR_K (vcall_offset
))
8560 output_asm_insn ("lghi\t%4,%3", op
);
8561 output_asm_insn ("ag\t%4,0(%1)", op
);
8562 output_asm_insn ("ag\t%1,0(%4)", op
);
8564 else if (CONST_OK_FOR_Os (vcall_offset
))
8566 output_asm_insn ("lgfi\t%4,%3", op
);
8567 output_asm_insn ("ag\t%4,0(%1)", op
);
8568 output_asm_insn ("ag\t%1,0(%4)", op
);
8572 op
[7] = gen_label_rtx ();
8573 output_asm_insn ("llgf\t%4,%7-%5(%4)", op
);
8574 output_asm_insn ("ag\t%4,0(%1)", op
);
8575 output_asm_insn ("ag\t%1,0(%4)", op
);
8579 /* Jump to target. */
8580 output_asm_insn ("jg\t%0", op
);
8582 /* Output literal pool if required. */
8585 output_asm_insn (".align\t4", op
);
8586 targetm
.asm_out
.internal_label (file
, "L",
8587 CODE_LABEL_NUMBER (op
[5]));
8591 targetm
.asm_out
.internal_label (file
, "L",
8592 CODE_LABEL_NUMBER (op
[6]));
8593 output_asm_insn (".long\t%2", op
);
8597 targetm
.asm_out
.internal_label (file
, "L",
8598 CODE_LABEL_NUMBER (op
[7]));
8599 output_asm_insn (".long\t%3", op
);
8604 /* Setup base pointer if required. */
8606 || (!DISP_IN_RANGE (delta
)
8607 && !CONST_OK_FOR_K (delta
)
8608 && !CONST_OK_FOR_Os (delta
))
8609 || (!DISP_IN_RANGE (delta
)
8610 && !CONST_OK_FOR_K (vcall_offset
)
8611 && !CONST_OK_FOR_Os (vcall_offset
)))
8613 op
[5] = gen_label_rtx ();
8614 output_asm_insn ("basr\t%4,0", op
);
8615 targetm
.asm_out
.internal_label (file
, "L",
8616 CODE_LABEL_NUMBER (op
[5]));
8619 /* Add DELTA to this pointer. */
8622 if (CONST_OK_FOR_J (delta
))
8623 output_asm_insn ("la\t%1,%2(%1)", op
);
8624 else if (DISP_IN_RANGE (delta
))
8625 output_asm_insn ("lay\t%1,%2(%1)", op
);
8626 else if (CONST_OK_FOR_K (delta
))
8627 output_asm_insn ("ahi\t%1,%2", op
);
8628 else if (CONST_OK_FOR_Os (delta
))
8629 output_asm_insn ("afi\t%1,%2", op
);
8632 op
[6] = gen_label_rtx ();
8633 output_asm_insn ("a\t%1,%6-%5(%4)", op
);
8637 /* Perform vcall adjustment. */
8640 if (CONST_OK_FOR_J (vcall_offset
))
8642 output_asm_insn ("l\t%4,0(%1)", op
);
8643 output_asm_insn ("a\t%1,%3(%4)", op
);
8645 else if (DISP_IN_RANGE (vcall_offset
))
8647 output_asm_insn ("l\t%4,0(%1)", op
);
8648 output_asm_insn ("ay\t%1,%3(%4)", op
);
8650 else if (CONST_OK_FOR_K (vcall_offset
))
8652 output_asm_insn ("lhi\t%4,%3", op
);
8653 output_asm_insn ("a\t%4,0(%1)", op
);
8654 output_asm_insn ("a\t%1,0(%4)", op
);
8656 else if (CONST_OK_FOR_Os (vcall_offset
))
8658 output_asm_insn ("iilf\t%4,%3", op
);
8659 output_asm_insn ("a\t%4,0(%1)", op
);
8660 output_asm_insn ("a\t%1,0(%4)", op
);
8664 op
[7] = gen_label_rtx ();
8665 output_asm_insn ("l\t%4,%7-%5(%4)", op
);
8666 output_asm_insn ("a\t%4,0(%1)", op
);
8667 output_asm_insn ("a\t%1,0(%4)", op
);
8670 /* We had to clobber the base pointer register.
8671 Re-setup the base pointer (with a different base). */
8672 op
[5] = gen_label_rtx ();
8673 output_asm_insn ("basr\t%4,0", op
);
8674 targetm
.asm_out
.internal_label (file
, "L",
8675 CODE_LABEL_NUMBER (op
[5]));
8678 /* Jump to target. */
8679 op
[8] = gen_label_rtx ();
8682 output_asm_insn ("l\t%4,%8-%5(%4)", op
);
8684 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
8685 /* We cannot call through .plt, since .plt requires %r12 loaded. */
8686 else if (flag_pic
== 1)
8688 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
8689 output_asm_insn ("l\t%4,%0(%4)", op
);
8691 else if (flag_pic
== 2)
8693 op
[9] = gen_rtx_REG (Pmode
, 0);
8694 output_asm_insn ("l\t%9,%8-4-%5(%4)", op
);
8695 output_asm_insn ("a\t%4,%8-%5(%4)", op
);
8696 output_asm_insn ("ar\t%4,%9", op
);
8697 output_asm_insn ("l\t%4,0(%4)", op
);
8700 output_asm_insn ("br\t%4", op
);
8702 /* Output literal pool. */
8703 output_asm_insn (".align\t4", op
);
8705 if (nonlocal
&& flag_pic
== 2)
8706 output_asm_insn (".long\t%0", op
);
8709 op
[0] = gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
8710 SYMBOL_REF_FLAGS (op
[0]) = SYMBOL_FLAG_LOCAL
;
8713 targetm
.asm_out
.internal_label (file
, "L", CODE_LABEL_NUMBER (op
[8]));
8715 output_asm_insn (".long\t%0", op
);
8717 output_asm_insn (".long\t%0-%5", op
);
8721 targetm
.asm_out
.internal_label (file
, "L",
8722 CODE_LABEL_NUMBER (op
[6]));
8723 output_asm_insn (".long\t%2", op
);
8727 targetm
.asm_out
.internal_label (file
, "L",
8728 CODE_LABEL_NUMBER (op
[7]));
8729 output_asm_insn (".long\t%3", op
);
8735 s390_valid_pointer_mode (enum machine_mode mode
)
8737 return (mode
== SImode
|| (TARGET_64BIT
&& mode
== DImode
));
8740 /* Checks whether the given CALL_EXPR would use a caller
8741 saved register. This is used to decide whether sibling call
8742 optimization could be performed on the respective function
8746 s390_call_saved_register_used (tree call_expr
)
8748 CUMULATIVE_ARGS cum
;
8750 enum machine_mode mode
;
8755 INIT_CUMULATIVE_ARGS (cum
, NULL
, NULL
, 0, 0);
8757 for (i
= 0; i
< call_expr_nargs (call_expr
); i
++)
8759 parameter
= CALL_EXPR_ARG (call_expr
, i
);
8760 gcc_assert (parameter
);
8762 /* For an undeclared variable passed as parameter we will get
8763 an ERROR_MARK node here. */
8764 if (TREE_CODE (parameter
) == ERROR_MARK
)
8767 type
= TREE_TYPE (parameter
);
8770 mode
= TYPE_MODE (type
);
8773 if (pass_by_reference (&cum
, mode
, type
, true))
8776 type
= build_pointer_type (type
);
8779 parm_rtx
= s390_function_arg (&cum
, mode
, type
, 0);
8781 s390_function_arg_advance (&cum
, mode
, type
, 0);
8783 if (parm_rtx
&& REG_P (parm_rtx
))
8786 reg
< HARD_REGNO_NREGS (REGNO (parm_rtx
), GET_MODE (parm_rtx
));
8788 if (! call_used_regs
[reg
+ REGNO (parm_rtx
)])
8795 /* Return true if the given call expression can be
8796 turned into a sibling call.
8797 DECL holds the declaration of the function to be called whereas
8798 EXP is the call expression itself. */
8801 s390_function_ok_for_sibcall (tree decl
, tree exp
)
8803 /* The TPF epilogue uses register 1. */
8804 if (TARGET_TPF_PROFILING
)
8807 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
8808 which would have to be restored before the sibcall. */
8809 if (!TARGET_64BIT
&& flag_pic
&& decl
&& !targetm
.binds_local_p (decl
))
8812 /* Register 6 on s390 is available as an argument register but unfortunately
8813 "caller saved". This makes functions needing this register for arguments
8814 not suitable for sibcalls. */
8815 return !s390_call_saved_register_used (exp
);
8818 /* Return the fixed registers used for condition codes. */
8821 s390_fixed_condition_code_regs (unsigned int *p1
, unsigned int *p2
)
8824 *p2
= INVALID_REGNUM
;
8829 /* This function is used by the call expanders of the machine description.
8830 It emits the call insn itself together with the necessary operations
8831 to adjust the target address and returns the emitted insn.
8832 ADDR_LOCATION is the target address rtx
8833 TLS_CALL the location of the thread-local symbol
8834 RESULT_REG the register where the result of the call should be stored
8835 RETADDR_REG the register where the return address should be stored
8836 If this parameter is NULL_RTX the call is considered
8837 to be a sibling call. */
8840 s390_emit_call (rtx addr_location
, rtx tls_call
, rtx result_reg
,
8843 bool plt_call
= false;
8849 /* Direct function calls need special treatment. */
8850 if (GET_CODE (addr_location
) == SYMBOL_REF
)
8852 /* When calling a global routine in PIC mode, we must
8853 replace the symbol itself with the PLT stub. */
8854 if (flag_pic
&& !SYMBOL_REF_LOCAL_P (addr_location
))
8856 addr_location
= gen_rtx_UNSPEC (Pmode
,
8857 gen_rtvec (1, addr_location
),
8859 addr_location
= gen_rtx_CONST (Pmode
, addr_location
);
8863 /* Unless we can use the bras(l) insn, force the
8864 routine address into a register. */
8865 if (!TARGET_SMALL_EXEC
&& !TARGET_CPU_ZARCH
)
8868 addr_location
= legitimize_pic_address (addr_location
, 0);
8870 addr_location
= force_reg (Pmode
, addr_location
);
8874 /* If it is already an indirect call or the code above moved the
8875 SYMBOL_REF to somewhere else make sure the address can be found in
8877 if (retaddr_reg
== NULL_RTX
8878 && GET_CODE (addr_location
) != SYMBOL_REF
8881 emit_move_insn (gen_rtx_REG (Pmode
, SIBCALL_REGNUM
), addr_location
);
8882 addr_location
= gen_rtx_REG (Pmode
, SIBCALL_REGNUM
);
8885 addr_location
= gen_rtx_MEM (QImode
, addr_location
);
8886 call
= gen_rtx_CALL (VOIDmode
, addr_location
, const0_rtx
);
8888 if (result_reg
!= NULL_RTX
)
8889 call
= gen_rtx_SET (VOIDmode
, result_reg
, call
);
8891 if (retaddr_reg
!= NULL_RTX
)
8893 clobber
= gen_rtx_CLOBBER (VOIDmode
, retaddr_reg
);
8895 if (tls_call
!= NULL_RTX
)
8896 vec
= gen_rtvec (3, call
, clobber
,
8897 gen_rtx_USE (VOIDmode
, tls_call
));
8899 vec
= gen_rtvec (2, call
, clobber
);
8901 call
= gen_rtx_PARALLEL (VOIDmode
, vec
);
8904 insn
= emit_call_insn (call
);
8906 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
8907 if ((!TARGET_64BIT
&& plt_call
) || tls_call
!= NULL_RTX
)
8909 /* s390_function_ok_for_sibcall should
8910 have denied sibcalls in this case. */
8911 gcc_assert (retaddr_reg
!= NULL_RTX
);
8913 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
8918 /* Implement CONDITIONAL_REGISTER_USAGE. */
8921 s390_conditional_register_usage (void)
8927 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
8928 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
8930 if (TARGET_CPU_ZARCH
)
8932 fixed_regs
[BASE_REGNUM
] = 0;
8933 call_used_regs
[BASE_REGNUM
] = 0;
8934 fixed_regs
[RETURN_REGNUM
] = 0;
8935 call_used_regs
[RETURN_REGNUM
] = 0;
8939 for (i
= 24; i
< 32; i
++)
8940 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
8944 for (i
= 18; i
< 20; i
++)
8945 call_used_regs
[i
] = call_really_used_regs
[i
] = 0;
8948 if (TARGET_SOFT_FLOAT
)
8950 for (i
= 16; i
< 32; i
++)
8951 call_used_regs
[i
] = fixed_regs
[i
] = 1;
8955 /* Corresponding function to eh_return expander. */
8957 static GTY(()) rtx s390_tpf_eh_return_symbol
;
8959 s390_emit_tpf_eh_return (rtx target
)
8963 if (!s390_tpf_eh_return_symbol
)
8964 s390_tpf_eh_return_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tpf_eh_return");
8966 reg
= gen_rtx_REG (Pmode
, 2);
8968 emit_move_insn (reg
, target
);
8969 insn
= s390_emit_call (s390_tpf_eh_return_symbol
, NULL_RTX
, reg
,
8970 gen_rtx_REG (Pmode
, RETURN_REGNUM
));
8971 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), reg
);
8973 emit_move_insn (EH_RETURN_HANDLER_RTX
, reg
);
8976 /* Rework the prologue/epilogue to avoid saving/restoring
8977 registers unnecessarily. */
8980 s390_optimize_prologue (void)
8982 rtx insn
, new_insn
, next_insn
;
8984 /* Do a final recompute of the frame-related data. */
8986 s390_update_frame_layout ();
8988 /* If all special registers are in fact used, there's nothing we
8989 can do, so no point in walking the insn list. */
8991 if (cfun_frame_layout
.first_save_gpr
<= BASE_REGNUM
8992 && cfun_frame_layout
.last_save_gpr
>= BASE_REGNUM
8993 && (TARGET_CPU_ZARCH
8994 || (cfun_frame_layout
.first_save_gpr
<= RETURN_REGNUM
8995 && cfun_frame_layout
.last_save_gpr
>= RETURN_REGNUM
)))
8998 /* Search for prologue/epilogue insns and replace them. */
9000 for (insn
= get_insns (); insn
; insn
= next_insn
)
9002 int first
, last
, off
;
9003 rtx set
, base
, offset
;
9005 next_insn
= NEXT_INSN (insn
);
9007 if (GET_CODE (insn
) != INSN
)
9010 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9011 && store_multiple_operation (PATTERN (insn
), VOIDmode
))
9013 set
= XVECEXP (PATTERN (insn
), 0, 0);
9014 first
= REGNO (SET_SRC (set
));
9015 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9016 offset
= const0_rtx
;
9017 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9018 off
= INTVAL (offset
);
9020 if (GET_CODE (base
) != REG
|| off
< 0)
9022 if (cfun_frame_layout
.first_save_gpr
!= -1
9023 && (cfun_frame_layout
.first_save_gpr
< first
9024 || cfun_frame_layout
.last_save_gpr
> last
))
9026 if (REGNO (base
) != STACK_POINTER_REGNUM
9027 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9029 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9032 if (cfun_frame_layout
.first_save_gpr
!= -1)
9034 new_insn
= save_gprs (base
,
9035 off
+ (cfun_frame_layout
.first_save_gpr
9036 - first
) * UNITS_PER_WORD
,
9037 cfun_frame_layout
.first_save_gpr
,
9038 cfun_frame_layout
.last_save_gpr
);
9039 new_insn
= emit_insn_before (new_insn
, insn
);
9040 INSN_ADDRESSES_NEW (new_insn
, -1);
9047 if (cfun_frame_layout
.first_save_gpr
== -1
9048 && GET_CODE (PATTERN (insn
)) == SET
9049 && GET_CODE (SET_SRC (PATTERN (insn
))) == REG
9050 && (REGNO (SET_SRC (PATTERN (insn
))) == BASE_REGNUM
9051 || (!TARGET_CPU_ZARCH
9052 && REGNO (SET_SRC (PATTERN (insn
))) == RETURN_REGNUM
))
9053 && GET_CODE (SET_DEST (PATTERN (insn
))) == MEM
)
9055 set
= PATTERN (insn
);
9056 first
= REGNO (SET_SRC (set
));
9057 offset
= const0_rtx
;
9058 base
= eliminate_constant_term (XEXP (SET_DEST (set
), 0), &offset
);
9059 off
= INTVAL (offset
);
9061 if (GET_CODE (base
) != REG
|| off
< 0)
9063 if (REGNO (base
) != STACK_POINTER_REGNUM
9064 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9071 if (GET_CODE (PATTERN (insn
)) == PARALLEL
9072 && load_multiple_operation (PATTERN (insn
), VOIDmode
))
9074 set
= XVECEXP (PATTERN (insn
), 0, 0);
9075 first
= REGNO (SET_DEST (set
));
9076 last
= first
+ XVECLEN (PATTERN (insn
), 0) - 1;
9077 offset
= const0_rtx
;
9078 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9079 off
= INTVAL (offset
);
9081 if (GET_CODE (base
) != REG
|| off
< 0)
9083 if (cfun_frame_layout
.first_restore_gpr
!= -1
9084 && (cfun_frame_layout
.first_restore_gpr
< first
9085 || cfun_frame_layout
.last_restore_gpr
> last
))
9087 if (REGNO (base
) != STACK_POINTER_REGNUM
9088 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9090 if (first
> BASE_REGNUM
|| last
< BASE_REGNUM
)
9093 if (cfun_frame_layout
.first_restore_gpr
!= -1)
9095 new_insn
= restore_gprs (base
,
9096 off
+ (cfun_frame_layout
.first_restore_gpr
9097 - first
) * UNITS_PER_WORD
,
9098 cfun_frame_layout
.first_restore_gpr
,
9099 cfun_frame_layout
.last_restore_gpr
);
9100 new_insn
= emit_insn_before (new_insn
, insn
);
9101 INSN_ADDRESSES_NEW (new_insn
, -1);
9108 if (cfun_frame_layout
.first_restore_gpr
== -1
9109 && GET_CODE (PATTERN (insn
)) == SET
9110 && GET_CODE (SET_DEST (PATTERN (insn
))) == REG
9111 && (REGNO (SET_DEST (PATTERN (insn
))) == BASE_REGNUM
9112 || (!TARGET_CPU_ZARCH
9113 && REGNO (SET_DEST (PATTERN (insn
))) == RETURN_REGNUM
))
9114 && GET_CODE (SET_SRC (PATTERN (insn
))) == MEM
)
9116 set
= PATTERN (insn
);
9117 first
= REGNO (SET_DEST (set
));
9118 offset
= const0_rtx
;
9119 base
= eliminate_constant_term (XEXP (SET_SRC (set
), 0), &offset
);
9120 off
= INTVAL (offset
);
9122 if (GET_CODE (base
) != REG
|| off
< 0)
9124 if (REGNO (base
) != STACK_POINTER_REGNUM
9125 && REGNO (base
) != HARD_FRAME_POINTER_REGNUM
)
9134 /* Perform machine-dependent processing. */
9139 bool pool_overflow
= false;
9141 /* Make sure all splits have been performed; splits after
9142 machine_dependent_reorg might confuse insn length counts. */
9143 split_all_insns_noflow ();
9145 /* From here on decomposed literal pool addresses must be accepted. */
9146 cfun
->machine
->decomposed_literal_pool_addresses_ok_p
= true;
9148 /* Install the main literal pool and the associated base
9149 register load insns.
9151 In addition, there are two problematic situations we need
9154 - the literal pool might be > 4096 bytes in size, so that
9155 some of its elements cannot be directly accessed
9157 - a branch target might be > 64K away from the branch, so that
9158 it is not possible to use a PC-relative instruction.
9160 To fix those, we split the single literal pool into multiple
9161 pool chunks, reloading the pool base register at various
9162 points throughout the function to ensure it always points to
9163 the pool chunk the following code expects, and / or replace
9164 PC-relative branches by absolute branches.
9166 However, the two problems are interdependent: splitting the
9167 literal pool can move a branch further away from its target,
9168 causing the 64K limit to overflow, and on the other hand,
9169 replacing a PC-relative branch by an absolute branch means
9170 we need to put the branch target address into the literal
9171 pool, possibly causing it to overflow.
9173 So, we loop trying to fix up both problems until we manage
9174 to satisfy both conditions at the same time. Note that the
9175 loop is guaranteed to terminate as every pass of the loop
9176 strictly decreases the total number of PC-relative branches
9177 in the function. (This is not completely true as there
9178 might be branch-over-pool insns introduced by chunkify_start.
9179 Those never need to be split however.) */
9183 struct constant_pool
*pool
= NULL
;
9185 /* Collect the literal pool. */
9188 pool
= s390_mainpool_start ();
9190 pool_overflow
= true;
9193 /* If literal pool overflowed, start to chunkify it. */
9195 pool
= s390_chunkify_start ();
9197 /* Split out-of-range branches. If this has created new
9198 literal pool entries, cancel current chunk list and
9199 recompute it. zSeries machines have large branch
9200 instructions, so we never need to split a branch. */
9201 if (!TARGET_CPU_ZARCH
&& s390_split_branches ())
9204 s390_chunkify_cancel (pool
);
9206 s390_mainpool_cancel (pool
);
9211 /* If we made it up to here, both conditions are satisfied.
9212 Finish up literal pool related changes. */
9214 s390_chunkify_finish (pool
);
9216 s390_mainpool_finish (pool
);
9218 /* We're done splitting branches. */
9219 cfun
->machine
->split_branches_pending_p
= false;
9223 /* Generate out-of-pool execute target insns. */
9224 if (TARGET_CPU_ZARCH
)
9226 rtx insn
, label
, target
;
9228 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9230 label
= s390_execute_label (insn
);
9234 gcc_assert (label
!= const0_rtx
);
9236 target
= emit_label (XEXP (label
, 0));
9237 INSN_ADDRESSES_NEW (target
, -1);
9239 target
= emit_insn (s390_execute_target (insn
));
9240 INSN_ADDRESSES_NEW (target
, -1);
9244 /* Try to optimize prologue and epilogue further. */
9245 s390_optimize_prologue ();
9249 /* Initialize GCC target structure. */
9251 #undef TARGET_ASM_ALIGNED_HI_OP
9252 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
9253 #undef TARGET_ASM_ALIGNED_DI_OP
9254 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
9255 #undef TARGET_ASM_INTEGER
9256 #define TARGET_ASM_INTEGER s390_assemble_integer
9258 #undef TARGET_ASM_OPEN_PAREN
9259 #define TARGET_ASM_OPEN_PAREN ""
9261 #undef TARGET_ASM_CLOSE_PAREN
9262 #define TARGET_ASM_CLOSE_PAREN ""
9264 #undef TARGET_DEFAULT_TARGET_FLAGS
9265 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
9266 #undef TARGET_HANDLE_OPTION
9267 #define TARGET_HANDLE_OPTION s390_handle_option
9269 #undef TARGET_ENCODE_SECTION_INFO
9270 #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
9273 #undef TARGET_HAVE_TLS
9274 #define TARGET_HAVE_TLS true
9276 #undef TARGET_CANNOT_FORCE_CONST_MEM
9277 #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
9279 #undef TARGET_DELEGITIMIZE_ADDRESS
9280 #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
9282 #undef TARGET_RETURN_IN_MEMORY
9283 #define TARGET_RETURN_IN_MEMORY s390_return_in_memory
9285 #undef TARGET_INIT_BUILTINS
9286 #define TARGET_INIT_BUILTINS s390_init_builtins
9287 #undef TARGET_EXPAND_BUILTIN
9288 #define TARGET_EXPAND_BUILTIN s390_expand_builtin
9290 #undef TARGET_ASM_OUTPUT_MI_THUNK
9291 #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
9292 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
9293 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
9295 #undef TARGET_SCHED_ADJUST_PRIORITY
9296 #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
9297 #undef TARGET_SCHED_ISSUE_RATE
9298 #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
9299 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
9300 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
9302 #undef TARGET_CANNOT_COPY_INSN_P
9303 #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
9304 #undef TARGET_RTX_COSTS
9305 #define TARGET_RTX_COSTS s390_rtx_costs
9306 #undef TARGET_ADDRESS_COST
9307 #define TARGET_ADDRESS_COST s390_address_cost
9309 #undef TARGET_MACHINE_DEPENDENT_REORG
9310 #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
9312 #undef TARGET_VALID_POINTER_MODE
9313 #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
9315 #undef TARGET_BUILD_BUILTIN_VA_LIST
9316 #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
9317 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
9318 #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
9320 #undef TARGET_PROMOTE_FUNCTION_ARGS
9321 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
9322 #undef TARGET_PROMOTE_FUNCTION_RETURN
9323 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
9324 #undef TARGET_PASS_BY_REFERENCE
9325 #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
9327 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
9328 #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
9330 #undef TARGET_FIXED_CONDITION_CODE_REGS
9331 #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
9333 #undef TARGET_CC_MODES_COMPATIBLE
9334 #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
9336 #undef TARGET_INVALID_WITHIN_DOLOOP
9337 #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_rtx_null
9340 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
9341 #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
9344 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
9345 #undef TARGET_MANGLE_TYPE
9346 #define TARGET_MANGLE_TYPE s390_mangle_type
9349 #undef TARGET_SCALAR_MODE_SUPPORTED_P
9350 #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
9352 #undef TARGET_SECONDARY_RELOAD
9353 #define TARGET_SECONDARY_RELOAD s390_secondary_reload
9355 #undef TARGET_LIBGCC_CMP_RETURN_MODE
9356 #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
9358 #undef TARGET_LIBGCC_SHIFT_COUNT_MODE
9359 #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
9361 struct gcc_target targetm
= TARGET_INITIALIZER
;
9363 #include "gt-s390.h"