1 /* Output routines for GCC for Hitachi / SuperH SH.
2 Copyright (C) 1993, 1994, 1995, 1997, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Steve Chamberlain (sac@cygnus.com).
5 Improved by Jim Wilson (wilson@cygnus.com).
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
26 #include "insn-config.h"
34 #include "hard-reg-set.h"
36 #include "insn-attr.h"
40 #include "integrate.h"
43 #include "target-def.h"
45 #include "langhooks.h"
47 int code_for_indirect_jump_scratch
= CODE_FOR_indirect_jump_scratch
;
49 #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0)
50 #define LSW (TARGET_LITTLE_ENDIAN ? 0 : 1)
52 /* These are some macros to abstract register modes. */
53 #define CONST_OK_FOR_ADD(size) \
54 (TARGET_SHMEDIA ? CONST_OK_FOR_P (size) : CONST_OK_FOR_I (size))
55 #define GEN_MOV (*(TARGET_SHMEDIA64 ? gen_movdi : gen_movsi))
56 #define GEN_ADD3 (*(TARGET_SHMEDIA64 ? gen_adddi3 : gen_addsi3))
57 #define GEN_SUB3 (*(TARGET_SHMEDIA64 ? gen_subdi3 : gen_subsi3))
59 /* Set to 1 by expand_prologue() when the function is an interrupt handler. */
60 int current_function_interrupt
;
62 /* ??? The pragma interrupt support will not work for SH3. */
63 /* This is set by #pragma interrupt and #pragma trapa, and causes gcc to
64 output code for the next function appropriate for an interrupt handler. */
67 /* This is set by the trap_exit attribute for functions. It specifies
68 a trap number to be used in a trapa instruction at function exit
69 (instead of an rte instruction). */
72 /* This is used by the sp_switch attribute for functions. It specifies
73 a variable holding the address of the stack the interrupt function
74 should switch to/from at entry/exit. */
77 /* This is set by #pragma trapa, and is similar to the above, except that
78 the compiler doesn't emit code to preserve all registers. */
79 static int pragma_trapa
;
81 /* This is set by #pragma nosave_low_regs. This is useful on the SH3,
82 which has a separate set of low regs for User and Supervisor modes.
83 This should only be used for the lowest level of interrupts. Higher levels
84 of interrupts must save the registers in case they themselves are
86 int pragma_nosave_low_regs
;
88 /* This is used for communication between SETUP_INCOMING_VARARGS and
89 sh_expand_prologue. */
90 int current_function_anonymous_args
;
92 /* Global variables for machine-dependent things. */
94 /* Which cpu are we scheduling for. */
95 enum processor_type sh_cpu
;
97 /* Saved operands from the last compare to use when we generate an scc
103 /* Provides the class number of the smallest class containing
106 int regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
108 R0_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
109 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
110 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
111 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
112 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
113 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
114 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
115 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
116 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
117 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
118 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
119 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
120 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
121 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
122 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
123 GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
, GENERAL_REGS
,
124 FP0_REGS
,FP_REGS
, FP_REGS
, FP_REGS
,
125 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
126 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
127 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
128 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
129 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
130 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
131 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
132 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
133 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
134 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
135 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
136 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
137 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
138 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
139 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
140 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
141 TARGET_REGS
, TARGET_REGS
, TARGET_REGS
, TARGET_REGS
,
142 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
143 DF_REGS
, DF_REGS
, DF_REGS
, DF_REGS
,
144 NO_REGS
, GENERAL_REGS
, PR_REGS
, T_REGS
,
145 MAC_REGS
, MAC_REGS
, FPUL_REGS
, FPSCR_REGS
,
149 char sh_register_names
[FIRST_PSEUDO_REGISTER
] \
150 [MAX_REGISTER_NAME_LENGTH
+ 1] = SH_REGISTER_NAMES_INITIALIZER
;
152 char sh_additional_register_names
[ADDREGNAMES_SIZE
] \
153 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH
+ 1]
154 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER
;
156 /* Provide reg_class from a letter such as appears in the machine
157 description. *: target independently reserved letter.
158 reg_class_from_letter['e'] is set to NO_REGS for TARGET_FMOVD. */
160 enum reg_class reg_class_from_letter
[] =
162 /* a */ ALL_REGS
, /* b */ TARGET_REGS
, /* c */ FPSCR_REGS
, /* d */ DF_REGS
,
163 /* e */ FP_REGS
, /* f */ FP_REGS
, /* g **/ NO_REGS
, /* h */ NO_REGS
,
164 /* i **/ NO_REGS
, /* j */ NO_REGS
, /* k */ SIBCALL_REGS
, /* l */ PR_REGS
,
165 /* m **/ NO_REGS
, /* n **/ NO_REGS
, /* o **/ NO_REGS
, /* p **/ NO_REGS
,
166 /* q */ NO_REGS
, /* r **/ NO_REGS
, /* s **/ NO_REGS
, /* t */ T_REGS
,
167 /* u */ NO_REGS
, /* v */ NO_REGS
, /* w */ FP0_REGS
, /* x */ MAC_REGS
,
168 /* y */ FPUL_REGS
, /* z */ R0_REGS
171 int assembler_dialect
;
173 static void split_branches
PARAMS ((rtx
));
174 static int branch_dest
PARAMS ((rtx
));
175 static void force_into
PARAMS ((rtx
, rtx
));
176 static void print_slot
PARAMS ((rtx
));
177 static rtx add_constant
PARAMS ((rtx
, enum machine_mode
, rtx
));
178 static void dump_table
PARAMS ((rtx
));
179 static int hi_const
PARAMS ((rtx
));
180 static int broken_move
PARAMS ((rtx
));
181 static int mova_p
PARAMS ((rtx
));
182 static rtx find_barrier
PARAMS ((int, rtx
, rtx
));
183 static int noncall_uses_reg
PARAMS ((rtx
, rtx
, rtx
*));
184 static rtx gen_block_redirect
PARAMS ((rtx
, int, int));
185 static void output_stack_adjust
PARAMS ((int, rtx
, int, rtx (*) (rtx
)));
186 static rtx frame_insn
PARAMS ((rtx
));
187 static rtx push
PARAMS ((int));
188 static void pop
PARAMS ((int));
189 static void push_regs
PARAMS ((HOST_WIDE_INT
*));
190 static void calc_live_regs
PARAMS ((int *, HOST_WIDE_INT
*));
191 static void mark_use
PARAMS ((rtx
, rtx
*));
192 static HOST_WIDE_INT rounded_frame_size
PARAMS ((int));
193 static rtx mark_constant_pool_use
PARAMS ((rtx
));
194 const struct attribute_spec sh_attribute_table
[];
195 static tree sh_handle_interrupt_handler_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
196 static tree sh_handle_sp_switch_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
197 static tree sh_handle_trap_exit_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
198 static void sh_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
199 static void sh_insert_attributes
PARAMS ((tree
, tree
*));
200 static int sh_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
201 static int sh_use_dfa_interface
PARAMS ((void));
202 static int sh_issue_rate
PARAMS ((void));
204 static bool sh_cannot_modify_jumps_p
PARAMS ((void));
205 static bool sh_ms_bitfield_layout_p
PARAMS ((tree
));
207 static void sh_encode_section_info
PARAMS ((tree
, int));
208 static const char *sh_strip_name_encoding
PARAMS ((const char *));
209 static void sh_init_builtins
PARAMS ((void));
210 static void sh_media_init_builtins
PARAMS ((void));
211 static rtx sh_expand_builtin
PARAMS ((tree
, rtx
, rtx
, enum machine_mode
, int));
212 static int flow_dependent_p
PARAMS ((rtx
, rtx
));
213 static void flow_dependent_p_1
PARAMS ((rtx
, rtx
, void *));
216 /* Initialize the GCC target structure. */
217 #undef TARGET_ATTRIBUTE_TABLE
218 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
220 /* The next two are used for debug info when compiling with -gdwarf. */
221 #undef TARGET_ASM_UNALIGNED_HI_OP
222 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
223 #undef TARGET_ASM_UNALIGNED_SI_OP
224 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
226 /* These are NULLed out on non-SH5 in OVERRIDE_OPTIONS. */
227 #undef TARGET_ASM_UNALIGNED_DI_OP
228 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaquad\t"
229 #undef TARGET_ASM_ALIGNED_DI_OP
230 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
232 #undef TARGET_ASM_FUNCTION_EPILOGUE
233 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
235 #undef TARGET_INSERT_ATTRIBUTES
236 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
238 #undef TARGET_SCHED_ADJUST_COST
239 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
241 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
242 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \
244 #undef TARGET_SCHED_ISSUE_RATE
245 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
247 #undef TARGET_CANNOT_MODIFY_JUMPS_P
248 #define TARGET_CANNOT_MODIFY_JUMPS_P sh_cannot_modify_jumps_p
250 #undef TARGET_MS_BITFIELD_LAYOUT_P
251 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
253 #undef TARGET_ENCODE_SECTION_INFO
254 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
255 #undef TARGET_STRIP_NAME_ENCODING
256 #define TARGET_STRIP_NAME_ENCODING sh_strip_name_encoding
258 #undef TARGET_INIT_BUILTINS
259 #define TARGET_INIT_BUILTINS sh_init_builtins
260 #undef TARGET_EXPAND_BUILTIN
261 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
263 struct gcc_target targetm
= TARGET_INITIALIZER
;
265 /* Print the operand address in x to the stream. */
268 print_operand_address (stream
, x
)
272 switch (GET_CODE (x
))
276 fprintf (stream
, "@%s", reg_names
[true_regnum (x
)]);
281 rtx base
= XEXP (x
, 0);
282 rtx index
= XEXP (x
, 1);
284 switch (GET_CODE (index
))
287 fprintf (stream
, "@(%d,%s)", (int) INTVAL (index
),
288 reg_names
[true_regnum (base
)]);
294 int base_num
= true_regnum (base
);
295 int index_num
= true_regnum (index
);
297 fprintf (stream
, "@(r0,%s)",
298 reg_names
[MAX (base_num
, index_num
)]);
310 fprintf (stream
, "@-%s", reg_names
[true_regnum (XEXP (x
, 0))]);
314 fprintf (stream
, "@%s+", reg_names
[true_regnum (XEXP (x
, 0))]);
318 x
= mark_constant_pool_use (x
);
319 output_addr_const (stream
, x
);
324 /* Print operand x (an rtx) in assembler syntax to file stream
325 according to modifier code.
327 '.' print a .s if insn needs delay slot
328 ',' print LOCAL_LABEL_PREFIX
329 '@' print trap, rte or rts depending upon pragma interruptness
330 '#' output a nop if there is nothing to put in the delay slot
331 ''' print likelyhood suffix (/u for unlikely).
332 'O' print a constant without the #
333 'R' print the LSW of a dp value - changes if in little endian
334 'S' print the MSW of a dp value - changes if in little endian
335 'T' print the next word of a dp value - same as 'R' in big endian mode.
336 'M' print an `x' if `m' will print `base,index'.
337 'N' print 'r63' if the operand is (const_int 0).
338 'm' print a pair `base,offset' or `base,index', for LD and ST.
339 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
340 'o' output an operator. */
343 print_operand (stream
, x
, code
)
352 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0))
353 && get_attr_length (XVECEXP (final_sequence
, 0, 1)))
354 fprintf (stream
, ASSEMBLER_DIALECT
? "/s" : ".s");
357 fprintf (stream
, "%s", LOCAL_LABEL_PREFIX
);
361 fprintf (stream
, "trapa #%d", trap_exit
);
362 else if (sh_cfun_interrupt_handler_p ())
363 fprintf (stream
, "rte");
365 fprintf (stream
, "rts");
368 /* Output a nop if there's nothing in the delay slot. */
369 if (dbr_sequence_length () == 0)
370 fprintf (stream
, "\n\tnop");
374 rtx note
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
376 if (note
&& INTVAL (XEXP (note
, 0)) * 2 < REG_BR_PROB_BASE
)
377 fputs ("/u", stream
);
381 x
= mark_constant_pool_use (x
);
382 output_addr_const (stream
, x
);
385 fputs (reg_names
[REGNO (x
) + LSW
], (stream
));
388 fputs (reg_names
[REGNO (x
) + MSW
], (stream
));
391 /* Next word of a double. */
392 switch (GET_CODE (x
))
395 fputs (reg_names
[REGNO (x
) + 1], (stream
));
398 if (GET_CODE (XEXP (x
, 0)) != PRE_DEC
399 && GET_CODE (XEXP (x
, 0)) != POST_INC
)
400 x
= adjust_address (x
, SImode
, 4);
401 print_operand_address (stream
, XEXP (x
, 0));
408 switch (GET_CODE (x
))
410 case PLUS
: fputs ("add", stream
); break;
411 case MINUS
: fputs ("sub", stream
); break;
412 case MULT
: fputs ("mul", stream
); break;
413 case DIV
: fputs ("div", stream
); break;
414 case EQ
: fputs ("eq", stream
); break;
415 case NE
: fputs ("ne", stream
); break;
416 case GT
: case LT
: fputs ("gt", stream
); break;
417 case GE
: case LE
: fputs ("ge", stream
); break;
418 case GTU
: case LTU
: fputs ("gtu", stream
); break;
419 case GEU
: case LEU
: fputs ("geu", stream
); break;
425 if (GET_CODE (x
) == MEM
426 && GET_CODE (XEXP (x
, 0)) == PLUS
427 && (GET_CODE (XEXP (XEXP (x
, 0), 1)) == REG
428 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == SUBREG
))
433 if (GET_CODE (x
) != MEM
)
436 switch (GET_CODE (x
))
440 print_operand (stream
, x
, 0);
441 fputs (", 0", stream
);
445 print_operand (stream
, XEXP (x
, 0), 0);
446 fputs (", ", stream
);
447 print_operand (stream
, XEXP (x
, 1), 0);
456 if (x
== CONST0_RTX (GET_MODE (x
)))
458 fprintf ((stream
), "r63");
463 if (GET_CODE (x
) == CONST_INT
)
465 fprintf ((stream
), "%u", (unsigned) INTVAL (x
) & (0x10000 - 1));
472 switch (GET_CODE (x
))
474 /* FIXME: We need this on SHmedia32 because reload generates
475 some sign-extended HI or QI loads into DImode registers
476 but, because Pmode is SImode, the address ends up with a
477 subreg:SI of the DImode register. Maybe reload should be
478 fixed so as to apply alter_subreg to such loads? */
480 if (SUBREG_BYTE (x
) != 0
481 || GET_CODE (SUBREG_REG (x
)) != REG
)
488 if (FP_REGISTER_P (REGNO (x
))
489 && GET_MODE (x
) == V16SFmode
)
490 fprintf ((stream
), "mtrx%s", reg_names
[REGNO (x
)] + 2);
491 else if (FP_REGISTER_P (REGNO (x
))
492 && GET_MODE (x
) == V4SFmode
)
493 fprintf ((stream
), "fv%s", reg_names
[REGNO (x
)] + 2);
494 else if (GET_CODE (x
) == REG
495 && GET_MODE (x
) == V2SFmode
)
496 fprintf ((stream
), "fp%s", reg_names
[REGNO (x
)] + 2);
497 else if (FP_REGISTER_P (REGNO (x
))
498 && GET_MODE_SIZE (GET_MODE (x
)) > 4)
499 fprintf ((stream
), "d%s", reg_names
[REGNO (x
)] + 1);
501 fputs (reg_names
[REGNO (x
)], (stream
));
505 output_address (XEXP (x
, 0));
510 && GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
511 && GET_MODE (XEXP (x
, 0)) == DImode
512 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == TRUNCATE
513 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == HImode
)
515 rtx val
= XEXP (XEXP (XEXP (x
, 0), 0), 0);
518 if (GET_CODE (val
) == ASHIFTRT
)
521 if (GET_CODE (XEXP (val
, 0)) == CONST
)
523 output_addr_const (stream
, XEXP (val
, 0));
524 if (GET_CODE (XEXP (val
, 0)) == CONST
)
526 fputs (" >> ", stream
);
527 output_addr_const (stream
, XEXP (val
, 1));
532 if (GET_CODE (val
) == CONST
)
534 output_addr_const (stream
, val
);
535 if (GET_CODE (val
) == CONST
)
538 fputs (" & 65535)", stream
);
546 output_addr_const (stream
, x
);
553 /* Like force_operand, but guarantees that VALUE ends up in TARGET. */
555 force_into (value
, target
)
558 value
= force_operand (value
, target
);
559 if (! rtx_equal_p (value
, target
))
560 emit_insn (gen_move_insn (target
, value
));
563 /* Emit code to perform a block move. Choose the best method.
565 OPERANDS[0] is the destination.
566 OPERANDS[1] is the source.
567 OPERANDS[2] is the size.
568 OPERANDS[3] is the alignment safe to use. */
571 expand_block_move (operands
)
574 int align
= INTVAL (operands
[3]);
575 int constp
= (GET_CODE (operands
[2]) == CONST_INT
);
576 int bytes
= (constp
? INTVAL (operands
[2]) : 0);
578 /* If it isn't a constant number of bytes, or if it doesn't have 4 byte
579 alignment, or if it isn't a multiple of 4 bytes, then fail. */
580 if (! constp
|| align
< 4 || (bytes
% 4 != 0))
587 else if (bytes
== 12)
592 rtx r4
= gen_rtx (REG
, SImode
, 4);
593 rtx r5
= gen_rtx (REG
, SImode
, 5);
595 entry_name
= get_identifier ("__movstrSI12_i4");
597 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
598 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
599 force_into (XEXP (operands
[0], 0), r4
);
600 force_into (XEXP (operands
[1], 0), r5
);
601 emit_insn (gen_block_move_real_i4 (func_addr_rtx
));
604 else if (! TARGET_SMALLCODE
)
610 rtx r4
= gen_rtx (REG
, SImode
, 4);
611 rtx r5
= gen_rtx (REG
, SImode
, 5);
612 rtx r6
= gen_rtx (REG
, SImode
, 6);
614 entry_name
= get_identifier (bytes
& 4
616 : "__movstr_i4_even");
617 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
618 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
619 force_into (XEXP (operands
[0], 0), r4
);
620 force_into (XEXP (operands
[1], 0), r5
);
623 emit_insn (gen_move_insn (r6
, GEN_INT (dwords
- 1)));
624 emit_insn (gen_block_lump_real_i4 (func_addr_rtx
));
636 rtx r4
= gen_rtx_REG (SImode
, 4);
637 rtx r5
= gen_rtx_REG (SImode
, 5);
639 sprintf (entry
, "__movstrSI%d", bytes
);
640 entry_name
= get_identifier (entry
);
641 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
642 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
643 force_into (XEXP (operands
[0], 0), r4
);
644 force_into (XEXP (operands
[1], 0), r5
);
645 emit_insn (gen_block_move_real (func_addr_rtx
));
649 /* This is the same number of bytes as a memcpy call, but to a different
650 less common function name, so this will occasionally use more space. */
651 if (! TARGET_SMALLCODE
)
656 int final_switch
, while_loop
;
657 rtx r4
= gen_rtx_REG (SImode
, 4);
658 rtx r5
= gen_rtx_REG (SImode
, 5);
659 rtx r6
= gen_rtx_REG (SImode
, 6);
661 entry_name
= get_identifier ("__movstr");
662 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (entry_name
));
663 func_addr_rtx
= copy_to_mode_reg (Pmode
, sym
);
664 force_into (XEXP (operands
[0], 0), r4
);
665 force_into (XEXP (operands
[1], 0), r5
);
667 /* r6 controls the size of the move. 16 is decremented from it
668 for each 64 bytes moved. Then the negative bit left over is used
669 as an index into a list of move instructions. e.g., a 72 byte move
670 would be set up with size(r6) = 14, for one iteration through the
671 big while loop, and a switch of -2 for the last part. */
673 final_switch
= 16 - ((bytes
/ 4) % 16);
674 while_loop
= ((bytes
/ 4) / 16 - 1) * 16;
675 emit_insn (gen_move_insn (r6
, GEN_INT (while_loop
+ final_switch
)));
676 emit_insn (gen_block_lump_real (func_addr_rtx
));
683 /* Prepare operands for a move define_expand; specifically, one of the
684 operands must be in a register. */
687 prepare_move_operands (operands
, mode
)
689 enum machine_mode mode
;
691 if ((mode
== SImode
|| mode
== DImode
) && flag_pic
)
694 if (SYMBOLIC_CONST_P (operands
[1]))
696 if (GET_CODE (operands
[0]) == MEM
)
697 operands
[1] = force_reg (Pmode
, operands
[1]);
698 else if (TARGET_SHMEDIA
699 && GET_CODE (operands
[1]) == LABEL_REF
700 && target_reg_operand (operands
[0], mode
))
704 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
705 operands
[1] = legitimize_pic_address (operands
[1], mode
, temp
);
708 else if (GET_CODE (operands
[1]) == CONST
709 && GET_CODE (XEXP (operands
[1], 0)) == PLUS
710 && SYMBOLIC_CONST_P (XEXP (XEXP (operands
[1], 0), 0)))
712 temp
= no_new_pseudos
? operands
[0] : gen_reg_rtx (Pmode
);
713 temp
= legitimize_pic_address (XEXP (XEXP (operands
[1], 0), 0),
715 operands
[1] = expand_binop (mode
, add_optab
, temp
,
716 XEXP (XEXP (operands
[1], 0), 1),
717 no_new_pseudos
? temp
718 : gen_reg_rtx (Pmode
),
723 if (! reload_in_progress
&& ! reload_completed
)
725 /* Copy the source to a register if both operands aren't registers. */
726 if (! register_operand (operands
[0], mode
)
727 && ! sh_register_operand (operands
[1], mode
))
728 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
730 /* This case can happen while generating code to move the result
731 of a library call to the target. Reject `st r0,@(rX,rY)' because
732 reload will fail to find a spill register for rX, since r0 is already
733 being used for the source. */
734 else if (GET_CODE (operands
[1]) == REG
&& REGNO (operands
[1]) == 0
735 && GET_CODE (operands
[0]) == MEM
736 && GET_CODE (XEXP (operands
[0], 0)) == PLUS
737 && GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == REG
)
738 operands
[1] = copy_to_mode_reg (mode
, operands
[1]);
744 /* Prepare the operands for an scc instruction; make sure that the
745 compare has been done. */
747 prepare_scc_operands (code
)
750 rtx t_reg
= gen_rtx_REG (SImode
, T_REG
);
751 enum rtx_code oldcode
= code
;
752 enum machine_mode mode
;
754 /* First need a compare insn. */
758 /* It isn't possible to handle this case. */
777 rtx tmp
= sh_compare_op0
;
778 sh_compare_op0
= sh_compare_op1
;
779 sh_compare_op1
= tmp
;
782 mode
= GET_MODE (sh_compare_op0
);
783 if (mode
== VOIDmode
)
784 mode
= GET_MODE (sh_compare_op1
);
786 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
787 if ((code
!= EQ
&& code
!= NE
788 && (sh_compare_op1
!= const0_rtx
789 || code
== GTU
|| code
== GEU
|| code
== LTU
|| code
== LEU
))
790 || (mode
== DImode
&& sh_compare_op1
!= const0_rtx
)
791 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
792 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
794 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
795 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
)
796 (gen_rtx (PARALLEL
, VOIDmode
, gen_rtvec (2,
797 gen_rtx (SET
, VOIDmode
, t_reg
,
798 gen_rtx (code
, SImode
,
799 sh_compare_op0
, sh_compare_op1
)),
800 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ()))));
802 emit_insn (gen_rtx (SET
, VOIDmode
, t_reg
,
803 gen_rtx (code
, SImode
, sh_compare_op0
,
809 /* Called from the md file, set up the operands of a compare instruction. */
812 from_compare (operands
, code
)
816 enum machine_mode mode
= GET_MODE (sh_compare_op0
);
818 if (mode
== VOIDmode
)
819 mode
= GET_MODE (sh_compare_op1
);
822 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
824 /* Force args into regs, since we can't use constants here. */
825 sh_compare_op0
= force_reg (mode
, sh_compare_op0
);
826 if (sh_compare_op1
!= const0_rtx
827 || code
== GTU
|| code
== GEU
828 || (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
))
829 sh_compare_op1
= force_reg (mode
, sh_compare_op1
);
831 if (TARGET_SH3E
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
&& code
== GE
)
833 from_compare (operands
, GT
);
834 insn
= gen_ieee_ccmpeqsf_t (sh_compare_op0
, sh_compare_op1
);
837 insn
= gen_rtx_SET (VOIDmode
,
838 gen_rtx_REG (SImode
, T_REG
),
839 gen_rtx (code
, SImode
, sh_compare_op0
,
841 if (TARGET_SH4
&& GET_MODE_CLASS (mode
) == MODE_FLOAT
)
843 insn
= gen_rtx (PARALLEL
, VOIDmode
,
845 gen_rtx (USE
, VOIDmode
, get_fpscr_rtx ())));
846 (mode
== SFmode
? emit_sf_insn
: emit_df_insn
) (insn
);
852 /* Functions to output assembly code. */
854 /* Return a sequence of instructions to perform DI or DF move.
856 Since the SH cannot move a DI or DF in one instruction, we have
857 to take care when we see overlapping source and dest registers. */
860 output_movedouble (insn
, operands
, mode
)
861 rtx insn ATTRIBUTE_UNUSED
;
863 enum machine_mode mode
;
865 rtx dst
= operands
[0];
866 rtx src
= operands
[1];
868 if (GET_CODE (dst
) == MEM
869 && GET_CODE (XEXP (dst
, 0)) == PRE_DEC
)
870 return "mov.l %T1,%0\n\tmov.l %1,%0";
872 if (register_operand (dst
, mode
)
873 && register_operand (src
, mode
))
875 if (REGNO (src
) == MACH_REG
)
876 return "sts mach,%S0\n\tsts macl,%R0";
878 /* When mov.d r1,r2 do r2->r3 then r1->r2;
879 when mov.d r1,r0 do r1->r0 then r2->r1. */
881 if (REGNO (src
) + 1 == REGNO (dst
))
882 return "mov %T1,%T0\n\tmov %1,%0";
884 return "mov %1,%0\n\tmov %T1,%T0";
886 else if (GET_CODE (src
) == CONST_INT
)
888 if (INTVAL (src
) < 0)
889 output_asm_insn ("mov #-1,%S0", operands
);
891 output_asm_insn ("mov #0,%S0", operands
);
895 else if (GET_CODE (src
) == MEM
)
898 int dreg
= REGNO (dst
);
899 rtx inside
= XEXP (src
, 0);
901 if (GET_CODE (inside
) == REG
)
902 ptrreg
= REGNO (inside
);
903 else if (GET_CODE (inside
) == SUBREG
)
904 ptrreg
= subreg_regno (inside
);
905 else if (GET_CODE (inside
) == PLUS
)
907 ptrreg
= REGNO (XEXP (inside
, 0));
908 /* ??? A r0+REG address shouldn't be possible here, because it isn't
909 an offsettable address. Unfortunately, offsettable addresses use
910 QImode to check the offset, and a QImode offsettable address
911 requires r0 for the other operand, which is not currently
912 supported, so we can't use the 'o' constraint.
913 Thus we must check for and handle r0+REG addresses here.
914 We punt for now, since this is likely very rare. */
915 if (GET_CODE (XEXP (inside
, 1)) == REG
)
918 else if (GET_CODE (inside
) == LABEL_REF
)
919 return "mov.l %1,%0\n\tmov.l %1+4,%T0";
920 else if (GET_CODE (inside
) == POST_INC
)
921 return "mov.l %1,%0\n\tmov.l %1,%T0";
925 /* Work out the safe way to copy. Copy into the second half first. */
927 return "mov.l %T1,%T0\n\tmov.l %1,%0";
930 return "mov.l %1,%0\n\tmov.l %T1,%T0";
933 /* Print an instruction which would have gone into a delay slot after
934 another instruction, but couldn't because the other instruction expanded
935 into a sequence where putting the slot insn at the end wouldn't work. */
941 final_scan_insn (XVECEXP (insn
, 0, 1), asm_out_file
, optimize
, 0, 1);
943 INSN_DELETED_P (XVECEXP (insn
, 0, 1)) = 1;
947 output_far_jump (insn
, op
)
951 struct { rtx lab
, reg
, op
; } this;
952 rtx braf_base_lab
= NULL_RTX
;
955 int offset
= branch_dest (insn
) - INSN_ADDRESSES (INSN_UID (insn
));
957 this.lab
= gen_label_rtx ();
961 && offset
- get_attr_length (insn
) <= 32766)
964 jump
= "mov.w %O0,%1; braf %1";
972 jump
= "mov.l %O0,%1; braf %1";
974 jump
= "mov.l r0,@-r15; mova %O0,r0; mov.l @r0,%1; add r0,%1; mov.l @r15+,r0; jmp @%1";
977 jump
= "mov.l %O0,%1; jmp @%1";
979 /* If we have a scratch register available, use it. */
980 if (GET_CODE (PREV_INSN (insn
)) == INSN
981 && INSN_CODE (PREV_INSN (insn
)) == CODE_FOR_indirect_jump_scratch
)
983 this.reg
= SET_DEST (PATTERN (PREV_INSN (insn
)));
984 if (REGNO (this.reg
) == R0_REG
&& flag_pic
&& ! TARGET_SH2
)
985 jump
= "mov.l r1,@-r15; mova %O0,r0; mov.l @r0,r1; add r1,r0; mov.l @r15+,r1; jmp @%1";
986 output_asm_insn (jump
, &this.lab
);
987 if (dbr_sequence_length ())
988 print_slot (final_sequence
);
990 output_asm_insn ("nop", 0);
994 /* Output the delay slot insn first if any. */
995 if (dbr_sequence_length ())
996 print_slot (final_sequence
);
998 this.reg
= gen_rtx_REG (SImode
, 13);
999 /* We must keep the stack aligned to 8-byte boundaries on SH5.
1000 Fortunately, MACL is fixed and call-clobbered, and we never
1001 need its value across jumps, so save r13 in it instead of in
1004 output_asm_insn ("lds r13, macl", 0);
1006 output_asm_insn ("mov.l r13,@-r15", 0);
1007 output_asm_insn (jump
, &this.lab
);
1009 output_asm_insn ("sts macl, r13", 0);
1011 output_asm_insn ("mov.l @r15+,r13", 0);
1013 if (far
&& flag_pic
&& TARGET_SH2
)
1015 braf_base_lab
= gen_label_rtx ();
1016 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
1017 CODE_LABEL_NUMBER (braf_base_lab
));
1020 output_asm_insn (".align 2", 0);
1021 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (this.lab
));
1023 if (far
&& flag_pic
)
1026 this.lab
= braf_base_lab
;
1027 output_asm_insn (".long %O2-%O0", &this.lab
);
1030 output_asm_insn (far
? ".long %O2" : ".word %O2-%O0", &this.lab
);
1034 /* Local label counter, used for constants in the pool and inside
1035 pattern branches. */
1037 static int lf
= 100;
1039 /* Output code for ordinary branches. */
1042 output_branch (logic
, insn
, operands
)
1047 switch (get_attr_length (insn
))
1050 /* This can happen if filling the delay slot has caused a forward
1051 branch to exceed its range (we could reverse it, but only
1052 when we know we won't overextend other branches; this should
1053 best be handled by relaxation).
1054 It can also happen when other condbranches hoist delay slot insn
1055 from their destination, thus leading to code size increase.
1056 But the branch will still be in the range -4092..+4098 bytes. */
1061 /* The call to print_slot will clobber the operands. */
1062 rtx op0
= operands
[0];
1064 /* If the instruction in the delay slot is annulled (true), then
1065 there is no delay slot where we can put it now. The only safe
1066 place for it is after the label. final will do that by default. */
1069 && ! INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence
, 0, 0)))
1071 asm_fprintf (asm_out_file
, "\tb%s%ss\t%LLF%d\n", logic
? "f" : "t",
1072 ASSEMBLER_DIALECT
? "/" : ".", label
);
1073 print_slot (final_sequence
);
1076 asm_fprintf (asm_out_file
, "\tb%s\t%LLF%d\n", logic
? "f" : "t", label
);
1078 output_asm_insn ("bra\t%l0", &op0
);
1079 fprintf (asm_out_file
, "\tnop\n");
1080 ASM_OUTPUT_INTERNAL_LABEL(asm_out_file
, "LF", label
);
1084 /* When relaxing, handle this like a short branch. The linker
1085 will fix it up if it still doesn't fit after relaxation. */
1087 return logic
? "bt%.\t%l0" : "bf%.\t%l0";
1089 /* There should be no longer branches now - that would
1090 indicate that something has destroyed the branches set
1091 up in machine_dependent_reorg. */
1097 output_branchy_insn (code
, template, insn
, operands
)
1099 const char *template;
1103 rtx next_insn
= NEXT_INSN (insn
);
1105 if (next_insn
&& GET_CODE (next_insn
) == JUMP_INSN
&& condjump_p (next_insn
))
1107 rtx src
= SET_SRC (PATTERN (next_insn
));
1108 if (GET_CODE (src
) == IF_THEN_ELSE
&& GET_CODE (XEXP (src
, 0)) != code
)
1110 /* Following branch not taken */
1111 operands
[9] = gen_label_rtx ();
1112 emit_label_after (operands
[9], next_insn
);
1113 INSN_ADDRESSES_NEW (operands
[9],
1114 INSN_ADDRESSES (INSN_UID (next_insn
))
1115 + get_attr_length (next_insn
));
1120 int offset
= (branch_dest (next_insn
)
1121 - INSN_ADDRESSES (INSN_UID (next_insn
)) + 4);
1122 if (offset
>= -252 && offset
<= 258)
1124 if (GET_CODE (src
) == IF_THEN_ELSE
)
1126 src
= XEXP (src
, 1);
1132 operands
[9] = gen_label_rtx ();
1133 emit_label_after (operands
[9], insn
);
1134 INSN_ADDRESSES_NEW (operands
[9],
1135 INSN_ADDRESSES (INSN_UID (insn
))
1136 + get_attr_length (insn
));
1141 output_ieee_ccmpeq (insn
, operands
)
1142 rtx insn
, *operands
;
1144 return output_branchy_insn (NE
, "bt\t%l9\\;fcmp/eq\t%1,%0", insn
, operands
);
1147 /* Output to FILE the start of the assembler file. */
1150 output_file_start (file
)
1153 output_file_directive (file
, main_input_filename
);
1155 /* Switch to the data section so that the coffsem symbol
1156 isn't in the text section. */
1159 if (TARGET_LITTLE_ENDIAN
)
1160 fprintf (file
, "\t.little\n");
1162 if (TARGET_SHCOMPACT
)
1163 fprintf (file
, "\t.mode\tSHcompact\n");
1164 else if (TARGET_SHMEDIA
)
1165 fprintf (file
, "\t.mode\tSHmedia\n\t.abi\t%i\n",
1166 TARGET_SHMEDIA64
? 64 : 32);
1169 /* Actual number of instructions used to make a shift by N. */
1170 static const char ashiftrt_insns
[] =
1171 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
1173 /* Left shift and logical right shift are the same. */
1174 static const char shift_insns
[] =
1175 { 0,1,1,2,2,3,3,4,1,2,2,3,3,4,3,3,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1177 /* Individual shift amounts needed to get the above length sequences.
1178 One bit right shifts clobber the T bit, so when possible, put one bit
1179 shifts in the middle of the sequence, so the ends are eligible for
1180 branch delay slots. */
1181 static const short shift_amounts
[32][5] = {
1182 {0}, {1}, {2}, {2, 1},
1183 {2, 2}, {2, 1, 2}, {2, 2, 2}, {2, 2, 1, 2},
1184 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1185 {8, 2, 2}, {8, 2, 1, 2}, {8, -2, 8}, {8, -1, 8},
1186 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1187 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1188 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1189 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1191 /* Likewise, but for shift amounts < 16, up to three highmost bits
1192 might be clobbered. This is typically used when combined with some
1193 kind of sign or zero extension. */
1195 static const char ext_shift_insns
[] =
1196 { 0,1,1,2,2,3,2,2,1,2,2,3,3,3,2,2,1,2,2,3,3,4,3,3,2,3,3,4,4,4,3,3};
1198 static const short ext_shift_amounts
[32][4] = {
1199 {0}, {1}, {2}, {2, 1},
1200 {2, 2}, {2, 1, 2}, {8, -2}, {8, -1},
1201 {8}, {8, 1}, {8, 2}, {8, 1, 2},
1202 {8, 2, 2}, {16, -2, -1}, {16, -2}, {16, -1},
1203 {16}, {16, 1}, {16, 2}, {16, 1, 2},
1204 {16, 2, 2}, {16, 2, 1, 2}, {16, -2, 8}, {16, -1, 8},
1205 {16, 8}, {16, 1, 8}, {16, 8, 2}, {16, 8, 1, 2},
1206 {16, 8, 2, 2}, {16, -1, -2, 16}, {16, -2, 16}, {16, -1, 16}};
1208 /* Assuming we have a value that has been sign-extended by at least one bit,
1209 can we use the ext_shift_amounts with the last shift turned to an arithmetic shift
1210 to shift it by N without data loss, and quicker than by other means? */
1211 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
1213 /* This is used in length attributes in sh.md to help compute the length
1214 of arbitrary constant shift instructions. */
1217 shift_insns_rtx (insn
)
1220 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1221 int shift_count
= INTVAL (XEXP (set_src
, 1));
1222 enum rtx_code shift_code
= GET_CODE (set_src
);
1227 return ashiftrt_insns
[shift_count
];
1230 return shift_insns
[shift_count
];
1236 /* Return the cost of a shift. */
1247 if (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
1249 if (GET_MODE (x
) == DImode
1250 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1251 && INTVAL (XEXP (x
, 1)) == 1)
1254 /* Everything else is invalid, because there is no pattern for it. */
1257 /* If shift by a non constant, then this will be expensive. */
1258 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1259 return SH_DYNAMIC_SHIFT_COST
;
1261 value
= INTVAL (XEXP (x
, 1));
1263 /* Otherwise, return the true cost in instructions. */
1264 if (GET_CODE (x
) == ASHIFTRT
)
1266 int cost
= ashiftrt_insns
[value
];
1267 /* If SH3, then we put the constant in a reg and use shad. */
1268 if (cost
> 1 + SH_DYNAMIC_SHIFT_COST
)
1269 cost
= 1 + SH_DYNAMIC_SHIFT_COST
;
1273 return shift_insns
[value
];
1276 /* Return the cost of an AND operation. */
1284 /* Anding with a register is a single cycle and instruction. */
1285 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1288 i
= INTVAL (XEXP (x
, 1));
1292 if ((GET_CODE (XEXP (x
, 1)) == CONST_INT
1293 && CONST_OK_FOR_J (INTVAL (XEXP (x
, 1))))
1294 || EXTRA_CONSTRAINT_S (XEXP (x
, 1)))
1300 /* These constants are single cycle extu.[bw] instructions. */
1301 if (i
== 0xff || i
== 0xffff)
1303 /* Constants that can be used in an and immediate instruction is a single
1304 cycle, but this requires r0, so make it a little more expensive. */
1305 if (CONST_OK_FOR_L (i
))
1307 /* Constants that can be loaded with a mov immediate and an and.
1308 This case is probably unnecessary. */
1309 if (CONST_OK_FOR_I (i
))
1311 /* Any other constants requires a 2 cycle pc-relative load plus an and.
1312 This case is probably unnecessary. */
1316 /* Return the cost of an addition or a subtraction. */
1322 /* Adding a register is a single cycle insn. */
1323 if (GET_CODE (XEXP (x
, 1)) == REG
1324 || GET_CODE (XEXP (x
, 1)) == SUBREG
)
1327 /* Likewise for small constants. */
1328 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
1329 && CONST_OK_FOR_ADD (INTVAL (XEXP (x
, 1))))
1333 switch (GET_CODE (XEXP (x
, 1)))
1338 return TARGET_SHMEDIA64
? 5 : 3;
1341 if (CONST_OK_FOR_J (INTVAL (XEXP (x
, 1))))
1343 else if (CONST_OK_FOR_J (INTVAL (XEXP (x
, 1)) >> 16))
1345 else if (CONST_OK_FOR_J ((INTVAL (XEXP (x
, 1)) >> 16) >> 16))
1353 /* Any other constant requires a 2 cycle pc-relative load plus an
1358 /* Return the cost of a multiply. */
1361 rtx x ATTRIBUTE_UNUSED
;
1368 /* We have a mul insn, so we can never take more than the mul and the
1369 read of the mac reg, but count more because of the latency and extra
1371 if (TARGET_SMALLCODE
)
1376 /* If we're aiming at small code, then just count the number of
1377 insns in a multiply call sequence. */
1378 if (TARGET_SMALLCODE
)
1381 /* Otherwise count all the insns in the routine we'd be calling too. */
1385 /* Code to expand a shift. */
1388 gen_ashift (type
, n
, reg
)
1393 /* Negative values here come from the shift_amounts array. */
1406 emit_insn (gen_ashrsi3_k (reg
, reg
, GEN_INT (n
)));
1410 emit_insn (gen_lshrsi3_m (reg
, reg
, GEN_INT (n
)));
1412 emit_insn (gen_lshrsi3_k (reg
, reg
, GEN_INT (n
)));
1415 emit_insn (gen_ashlsi3_std (reg
, reg
, GEN_INT (n
)));
1420 /* Same for HImode */
1423 gen_ashift_hi (type
, n
, reg
)
1428 /* Negative values here come from the shift_amounts array. */
1442 /* We don't have HImode right shift operations because using the
1443 ordinary 32 bit shift instructions for that doesn't generate proper
1444 zero/sign extension.
1445 gen_ashift_hi is only called in contexts where we know that the
1446 sign extension works out correctly. */
1449 if (GET_CODE (reg
) == SUBREG
)
1451 offset
= SUBREG_BYTE (reg
);
1452 reg
= SUBREG_REG (reg
);
1454 gen_ashift (type
, n
, gen_rtx_SUBREG (SImode
, reg
, offset
));
1458 emit_insn (gen_ashlhi3_k (reg
, reg
, GEN_INT (n
)));
1463 /* Output RTL to split a constant shift into its component SH constant
1464 shift instructions. */
1467 gen_shifty_op (code
, operands
)
1471 int value
= INTVAL (operands
[2]);
1474 /* Truncate the shift count in case it is out of bounds. */
1475 value
= value
& 0x1f;
1479 if (code
== LSHIFTRT
)
1481 emit_insn (gen_rotlsi3_1 (operands
[0], operands
[0]));
1482 emit_insn (gen_movt (operands
[0]));
1485 else if (code
== ASHIFT
)
1487 /* There is a two instruction sequence for 31 bit left shifts,
1488 but it requires r0. */
1489 if (GET_CODE (operands
[0]) == REG
&& REGNO (operands
[0]) == 0)
1491 emit_insn (gen_andsi3 (operands
[0], operands
[0], const1_rtx
));
1492 emit_insn (gen_rotlsi3_31 (operands
[0], operands
[0]));
1497 else if (value
== 0)
1499 /* This can happen when not optimizing. We must output something here
1500 to prevent the compiler from aborting in final.c after the try_split
1502 emit_insn (gen_nop ());
1506 max
= shift_insns
[value
];
1507 for (i
= 0; i
< max
; i
++)
1508 gen_ashift (code
, shift_amounts
[value
][i
], operands
[0]);
1511 /* Same as above, but optimized for values where the topmost bits don't
1515 gen_shifty_hi_op (code
, operands
)
1519 int value
= INTVAL (operands
[2]);
1521 void (*gen_fun
) PARAMS ((int, int, rtx
));
1523 /* This operation is used by and_shl for SImode values with a few
1524 high bits known to be cleared. */
1528 emit_insn (gen_nop ());
1532 gen_fun
= GET_MODE (operands
[0]) == HImode
? gen_ashift_hi
: gen_ashift
;
1535 max
= ext_shift_insns
[value
];
1536 for (i
= 0; i
< max
; i
++)
1537 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1540 /* When shifting right, emit the shifts in reverse order, so that
1541 solitary negative values come first. */
1542 for (i
= ext_shift_insns
[value
] - 1; i
>= 0; i
--)
1543 gen_fun (code
, ext_shift_amounts
[value
][i
], operands
[0]);
1546 /* Output RTL for an arithmetic right shift. */
1548 /* ??? Rewrite to use super-optimizer sequences. */
1551 expand_ashiftrt (operands
)
1562 if (GET_CODE (operands
[2]) != CONST_INT
)
1564 rtx count
= copy_to_mode_reg (SImode
, operands
[2]);
1565 emit_insn (gen_negsi2 (count
, count
));
1566 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1569 else if (ashiftrt_insns
[INTVAL (operands
[2]) & 31]
1570 > 1 + SH_DYNAMIC_SHIFT_COST
)
1573 = force_reg (SImode
, GEN_INT (- (INTVAL (operands
[2]) & 31)));
1574 emit_insn (gen_ashrsi3_d (operands
[0], operands
[1], count
));
1578 if (GET_CODE (operands
[2]) != CONST_INT
)
1581 value
= INTVAL (operands
[2]) & 31;
1585 emit_insn (gen_ashrsi2_31 (operands
[0], operands
[1]));
1588 else if (value
>= 16 && value
<= 19)
1590 wrk
= gen_reg_rtx (SImode
);
1591 emit_insn (gen_ashrsi2_16 (wrk
, operands
[1]));
1594 gen_ashift (ASHIFTRT
, 1, wrk
);
1595 emit_move_insn (operands
[0], wrk
);
1598 /* Expand a short sequence inline, longer call a magic routine. */
1599 else if (value
<= 5)
1601 wrk
= gen_reg_rtx (SImode
);
1602 emit_move_insn (wrk
, operands
[1]);
1604 gen_ashift (ASHIFTRT
, 1, wrk
);
1605 emit_move_insn (operands
[0], wrk
);
1609 wrk
= gen_reg_rtx (Pmode
);
1611 /* Load the value into an arg reg and call a helper. */
1612 emit_move_insn (gen_rtx_REG (SImode
, 4), operands
[1]);
1613 sprintf (func
, "__ashiftrt_r4_%d", value
);
1614 func_name
= get_identifier (func
);
1615 sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (func_name
));
1616 emit_move_insn (wrk
, sym
);
1617 emit_insn (gen_ashrsi3_n (GEN_INT (value
), wrk
));
1618 emit_move_insn (operands
[0], gen_rtx_REG (SImode
, 4));
1623 sh_dynamicalize_shift_p (count
)
1626 return shift_insns
[INTVAL (count
)] > 1 + SH_DYNAMIC_SHIFT_COST
;
1629 /* Try to find a good way to implement the combiner pattern
1630 [(set (match_operand:SI 0 "register_operand" "r")
1631 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1632 (match_operand:SI 2 "const_int_operand" "n"))
1633 (match_operand:SI 3 "const_int_operand" "n"))) .
1634 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
1635 return 0 for simple right / left or left/right shift combination.
1636 return 1 for a combination of shifts with zero_extend.
1637 return 2 for a combination of shifts with an AND that needs r0.
1638 return 3 for a combination of shifts with an AND that needs an extra
1639 scratch register, when the three highmost bits of the AND mask are clear.
1640 return 4 for a combination of shifts with an AND that needs an extra
1641 scratch register, when any of the three highmost bits of the AND mask
1643 If ATTRP is set, store an initial right shift width in ATTRP[0],
1644 and the instruction length in ATTRP[1] . These values are not valid
1646 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
1647 shift_amounts for the last shift value that is to be used before the
1650 shl_and_kind (left_rtx
, mask_rtx
, attrp
)
1651 rtx left_rtx
, mask_rtx
;
1654 unsigned HOST_WIDE_INT mask
, lsb
, mask2
, lsb2
;
1655 int left
= INTVAL (left_rtx
), right
;
1657 int cost
, best_cost
= 10000;
1658 int best_right
= 0, best_len
= 0;
1662 if (left
< 0 || left
> 31)
1664 if (GET_CODE (mask_rtx
) == CONST_INT
)
1665 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> left
;
1667 mask
= (unsigned HOST_WIDE_INT
) GET_MODE_MASK (SImode
) >> left
;
1668 /* Can this be expressed as a right shift / left shift pair ? */
1669 lsb
= ((mask
^ (mask
- 1)) >> 1) + 1;
1670 right
= exact_log2 (lsb
);
1671 mask2
= ~(mask
+ lsb
- 1);
1672 lsb2
= ((mask2
^ (mask2
- 1)) >> 1) + 1;
1673 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
1675 best_cost
= shift_insns
[right
] + shift_insns
[right
+ left
];
1676 /* mask has no trailing zeroes <==> ! right */
1677 else if (! right
&& mask2
== ~(lsb2
- 1))
1679 int late_right
= exact_log2 (lsb2
);
1680 best_cost
= shift_insns
[left
+ late_right
] + shift_insns
[late_right
];
1682 /* Try to use zero extend */
1683 if (mask2
== ~(lsb2
- 1))
1687 for (width
= 8; width
<= 16; width
+= 8)
1689 /* Can we zero-extend right away? */
1690 if (lsb2
== (unsigned HOST_WIDE_INT
)1 << width
)
1693 = 1 + ext_shift_insns
[right
] + ext_shift_insns
[left
+ right
];
1694 if (cost
< best_cost
)
1705 /* ??? Could try to put zero extend into initial right shift,
1706 or even shift a bit left before the right shift. */
1707 /* Determine value of first part of left shift, to get to the
1708 zero extend cut-off point. */
1709 first
= width
- exact_log2 (lsb2
) + right
;
1710 if (first
>= 0 && right
+ left
- first
>= 0)
1712 cost
= ext_shift_insns
[right
] + ext_shift_insns
[first
] + 1
1713 + ext_shift_insns
[right
+ left
- first
];
1714 if (cost
< best_cost
)
1726 /* Try to use r0 AND pattern */
1727 for (i
= 0; i
<= 2; i
++)
1731 if (! CONST_OK_FOR_L (mask
>> i
))
1733 cost
= (i
!= 0) + 2 + ext_shift_insns
[left
+ i
];
1734 if (cost
< best_cost
)
1739 best_len
= cost
- 1;
1742 /* Try to use a scratch register to hold the AND operand. */
1743 can_ext
= ((mask
<< left
) & ((unsigned HOST_WIDE_INT
)3 << 30)) == 0;
1744 for (i
= 0; i
<= 2; i
++)
1748 cost
= (i
!= 0) + (CONST_OK_FOR_I (mask
>> i
) ? 2 : 3)
1749 + (can_ext
? ext_shift_insns
: shift_insns
)[left
+ i
];
1750 if (cost
< best_cost
)
1755 best_len
= cost
- 1 - ! CONST_OK_FOR_I (mask
>> i
);
1761 attrp
[0] = best_right
;
1762 attrp
[1] = best_len
;
1767 /* This is used in length attributes of the unnamed instructions
1768 corresponding to shl_and_kind return values of 1 and 2. */
1770 shl_and_length (insn
)
1773 rtx set_src
, left_rtx
, mask_rtx
;
1776 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1777 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
1778 mask_rtx
= XEXP (set_src
, 1);
1779 shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1780 return attributes
[1];
1783 /* This is used in length attribute of the and_shl_scratch instruction. */
1786 shl_and_scr_length (insn
)
1789 rtx set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
1790 int len
= shift_insns
[INTVAL (XEXP (set_src
, 1))];
1791 rtx op
= XEXP (set_src
, 0);
1792 len
+= shift_insns
[INTVAL (XEXP (op
, 1))] + 1;
1793 op
= XEXP (XEXP (op
, 0), 0);
1794 return len
+ shift_insns
[INTVAL (XEXP (op
, 1))];
1797 /* Generating rtl? */
1798 extern int rtx_equal_function_value_matters
;
1800 /* Generate rtl for instructions for which shl_and_kind advised a particular
1801 method of generating them, i.e. returned zero. */
1804 gen_shl_and (dest
, left_rtx
, mask_rtx
, source
)
1805 rtx dest
, left_rtx
, mask_rtx
, source
;
1808 unsigned HOST_WIDE_INT mask
;
1809 int kind
= shl_and_kind (left_rtx
, mask_rtx
, attributes
);
1810 int right
, total_shift
;
1811 void (*shift_gen_fun
) PARAMS ((int, rtx
*)) = gen_shifty_hi_op
;
1813 right
= attributes
[0];
1814 total_shift
= INTVAL (left_rtx
) + right
;
1815 mask
= (unsigned HOST_WIDE_INT
) INTVAL (mask_rtx
) >> total_shift
;
1822 int first
= attributes
[2];
1827 emit_insn ((mask
<< right
) <= 0xff
1828 ? gen_zero_extendqisi2(dest
,
1829 gen_lowpart (QImode
, source
))
1830 : gen_zero_extendhisi2(dest
,
1831 gen_lowpart (HImode
, source
)));
1835 emit_insn (gen_movsi (dest
, source
));
1839 operands
[2] = GEN_INT (right
);
1840 gen_shifty_hi_op (LSHIFTRT
, operands
);
1844 operands
[2] = GEN_INT (first
);
1845 gen_shifty_hi_op (ASHIFT
, operands
);
1846 total_shift
-= first
;
1850 emit_insn (mask
<= 0xff
1851 ? gen_zero_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
1852 : gen_zero_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
1853 if (total_shift
> 0)
1855 operands
[2] = GEN_INT (total_shift
);
1856 gen_shifty_hi_op (ASHIFT
, operands
);
1861 shift_gen_fun
= gen_shifty_op
;
1863 /* If the topmost bit that matters is set, set the topmost bits
1864 that don't matter. This way, we might be able to get a shorter
1866 if (mask
& ((HOST_WIDE_INT
)1 << (31 - total_shift
)))
1867 mask
|= (HOST_WIDE_INT
)~0 << (31 - total_shift
);
1869 /* Don't expand fine-grained when combining, because that will
1870 make the pattern fail. */
1871 if (rtx_equal_function_value_matters
1872 || reload_in_progress
|| reload_completed
)
1876 /* Cases 3 and 4 should be handled by this split
1877 only while combining */
1882 emit_insn (gen_lshrsi3 (dest
, source
, GEN_INT (right
)));
1885 emit_insn (gen_andsi3 (dest
, source
, GEN_INT (mask
)));
1890 operands
[2] = GEN_INT (total_shift
);
1891 shift_gen_fun (ASHIFT
, operands
);
1898 if (kind
!= 4 && total_shift
< 16)
1900 neg
= -ext_shift_amounts
[total_shift
][1];
1902 neg
-= ext_shift_amounts
[total_shift
][2];
1906 emit_insn (gen_and_shl_scratch (dest
, source
,
1909 GEN_INT (total_shift
+ neg
),
1911 emit_insn (gen_movsi (dest
, dest
));
1918 /* Try to find a good way to implement the combiner pattern
1919 [(set (match_operand:SI 0 "register_operand" "=r")
1920 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1921 (match_operand:SI 2 "const_int_operand" "n")
1922 (match_operand:SI 3 "const_int_operand" "n")
1924 (clobber (reg:SI T_REG))]
1925 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
1926 return 0 for simple left / right shift combination.
1927 return 1 for left shift / 8 bit sign extend / left shift.
1928 return 2 for left shift / 16 bit sign extend / left shift.
1929 return 3 for left shift / 8 bit sign extend / shift / sign extend.
1930 return 4 for left shift / 16 bit sign extend / shift / sign extend.
1931 return 5 for left shift / 16 bit sign extend / right shift
1932 return 6 for < 8 bit sign extend / left shift.
1933 return 7 for < 8 bit sign extend / left shift / single right shift.
1934 If COSTP is nonzero, assign the calculated cost to *COSTP. */
1937 shl_sext_kind (left_rtx
, size_rtx
, costp
)
1938 rtx left_rtx
, size_rtx
;
1941 int left
, size
, insize
, ext
;
1942 int cost
, best_cost
;
1945 left
= INTVAL (left_rtx
);
1946 size
= INTVAL (size_rtx
);
1947 insize
= size
- left
;
1950 /* Default to left / right shift. */
1952 best_cost
= shift_insns
[32 - insize
] + ashiftrt_insns
[32 - size
];
1955 /* 16 bit shift / sign extend / 16 bit shift */
1956 cost
= shift_insns
[16 - insize
] + 1 + ashiftrt_insns
[16 - size
];
1957 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
1958 below, by alternative 3 or something even better. */
1959 if (cost
< best_cost
)
1965 /* Try a plain sign extend between two shifts. */
1966 for (ext
= 16; ext
>= insize
; ext
-= 8)
1970 cost
= ext_shift_insns
[ext
- insize
] + 1 + shift_insns
[size
- ext
];
1971 if (cost
< best_cost
)
1973 kind
= ext
/ (unsigned) 8;
1977 /* Check if we can do a sloppy shift with a final signed shift
1978 restoring the sign. */
1979 if (EXT_SHIFT_SIGNED (size
- ext
))
1980 cost
= ext_shift_insns
[ext
- insize
] + ext_shift_insns
[size
- ext
] + 1;
1981 /* If not, maybe it's still cheaper to do the second shift sloppy,
1982 and do a final sign extend? */
1983 else if (size
<= 16)
1984 cost
= ext_shift_insns
[ext
- insize
] + 1
1985 + ext_shift_insns
[size
> ext
? size
- ext
: ext
- size
] + 1;
1988 if (cost
< best_cost
)
1990 kind
= ext
/ (unsigned) 8 + 2;
1994 /* Check if we can sign extend in r0 */
1997 cost
= 3 + shift_insns
[left
];
1998 if (cost
< best_cost
)
2003 /* Try the same with a final signed shift. */
2006 cost
= 3 + ext_shift_insns
[left
+ 1] + 1;
2007 if (cost
< best_cost
)
2016 /* Try to use a dynamic shift. */
2017 cost
= shift_insns
[32 - insize
] + 1 + SH_DYNAMIC_SHIFT_COST
;
2018 if (cost
< best_cost
)
2029 /* Function to be used in the length attribute of the instructions
2030 implementing this pattern. */
2033 shl_sext_length (insn
)
2036 rtx set_src
, left_rtx
, size_rtx
;
2039 set_src
= SET_SRC (XVECEXP (PATTERN (insn
), 0, 0));
2040 left_rtx
= XEXP (XEXP (set_src
, 0), 1);
2041 size_rtx
= XEXP (set_src
, 1);
2042 shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2046 /* Generate rtl for this pattern */
2049 gen_shl_sext (dest
, left_rtx
, size_rtx
, source
)
2050 rtx dest
, left_rtx
, size_rtx
, source
;
2053 int left
, size
, insize
, cost
;
2056 kind
= shl_sext_kind (left_rtx
, size_rtx
, &cost
);
2057 left
= INTVAL (left_rtx
);
2058 size
= INTVAL (size_rtx
);
2059 insize
= size
- left
;
2067 int ext
= kind
& 1 ? 8 : 16;
2068 int shift2
= size
- ext
;
2070 /* Don't expand fine-grained when combining, because that will
2071 make the pattern fail. */
2072 if (! rtx_equal_function_value_matters
2073 && ! reload_in_progress
&& ! reload_completed
)
2075 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2076 emit_insn (gen_movsi (dest
, source
));
2080 emit_insn (gen_movsi (dest
, source
));
2084 operands
[2] = GEN_INT (ext
- insize
);
2085 gen_shifty_hi_op (ASHIFT
, operands
);
2088 ? gen_extendqisi2(dest
, gen_lowpart (QImode
, dest
))
2089 : gen_extendhisi2(dest
, gen_lowpart (HImode
, dest
)));
2094 operands
[2] = GEN_INT (shift2
);
2095 gen_shifty_op (ASHIFT
, operands
);
2102 if (EXT_SHIFT_SIGNED (shift2
))
2104 operands
[2] = GEN_INT (shift2
+ 1);
2105 gen_shifty_op (ASHIFT
, operands
);
2106 operands
[2] = GEN_INT (1);
2107 gen_shifty_op (ASHIFTRT
, operands
);
2110 operands
[2] = GEN_INT (shift2
);
2111 gen_shifty_hi_op (ASHIFT
, operands
);
2115 operands
[2] = GEN_INT (-shift2
);
2116 gen_shifty_hi_op (LSHIFTRT
, operands
);
2118 emit_insn (size
<= 8
2119 ? gen_extendqisi2 (dest
, gen_lowpart (QImode
, dest
))
2120 : gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2127 if (! rtx_equal_function_value_matters
2128 && ! reload_in_progress
&& ! reload_completed
)
2129 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2133 operands
[2] = GEN_INT (16 - insize
);
2134 gen_shifty_hi_op (ASHIFT
, operands
);
2135 emit_insn (gen_extendhisi2 (dest
, gen_lowpart (HImode
, dest
)));
2137 /* Don't use gen_ashrsi3 because it generates new pseudos. */
2139 gen_ashift (ASHIFTRT
, 1, dest
);
2144 /* Don't expand fine-grained when combining, because that will
2145 make the pattern fail. */
2146 if (! rtx_equal_function_value_matters
2147 && ! reload_in_progress
&& ! reload_completed
)
2149 emit_insn (gen_shl_sext_ext (dest
, source
, left_rtx
, size_rtx
));
2150 emit_insn (gen_movsi (dest
, source
));
2153 emit_insn (gen_andsi3 (dest
, source
, GEN_INT ((1 << insize
) - 1)));
2154 emit_insn (gen_xorsi3 (dest
, dest
, GEN_INT (1 << (insize
- 1))));
2155 emit_insn (gen_addsi3 (dest
, dest
, GEN_INT (-1 << (insize
- 1))));
2157 operands
[2] = kind
== 7 ? GEN_INT (left
+ 1) : left_rtx
;
2158 gen_shifty_op (ASHIFT
, operands
);
2160 emit_insn (gen_ashrsi3_k (dest
, dest
, GEN_INT (1)));
2168 /* Prefix a symbol_ref name with "datalabel". */
2171 gen_datalabel_ref (sym
)
2174 if (GET_CODE (sym
) == LABEL_REF
)
2175 return gen_rtx_CONST (GET_MODE (sym
),
2176 gen_rtx_UNSPEC (GET_MODE (sym
),
2180 if (GET_CODE (sym
) != SYMBOL_REF
)
2183 XSTR (sym
, 0) = concat (SH_DATALABEL_ENCODING
, XSTR (sym
, 0), NULL
);
2189 /* The SH cannot load a large constant into a register, constants have to
2190 come from a pc relative load. The reference of a pc relative load
2191 instruction must be less than 1k infront of the instruction. This
2192 means that we often have to dump a constant inside a function, and
2193 generate code to branch around it.
2195 It is important to minimize this, since the branches will slow things
2196 down and make things bigger.
2198 Worst case code looks like:
2216 We fix this by performing a scan before scheduling, which notices which
2217 instructions need to have their operands fetched from the constant table
2218 and builds the table.
2222 scan, find an instruction which needs a pcrel move. Look forward, find the
2223 last barrier which is within MAX_COUNT bytes of the requirement.
2224 If there isn't one, make one. Process all the instructions between
2225 the find and the barrier.
2227 In the above example, we can tell that L3 is within 1k of L1, so
2228 the first move can be shrunk from the 3 insn+constant sequence into
2229 just 1 insn, and the constant moved to L3 to make:
2240 Then the second move becomes the target for the shortening process. */
2244 rtx value
; /* Value in table. */
2245 rtx label
; /* Label of value. */
2246 rtx wend
; /* End of window. */
2247 enum machine_mode mode
; /* Mode of value. */
2249 /* True if this constant is accessed as part of a post-increment
2250 sequence. Note that HImode constants are never accessed in this way. */
2251 bool part_of_sequence_p
;
2254 /* The maximum number of constants that can fit into one pool, since
2255 the pc relative range is 0...1020 bytes and constants are at least 4
2258 #define MAX_POOL_SIZE (1020/4)
2259 static pool_node pool_vector
[MAX_POOL_SIZE
];
2260 static int pool_size
;
2261 static rtx pool_window_label
;
2262 static int pool_window_last
;
2264 /* ??? If we need a constant in HImode which is the truncated value of a
2265 constant we need in SImode, we could combine the two entries thus saving
2266 two bytes. Is this common enough to be worth the effort of implementing
2269 /* ??? This stuff should be done at the same time that we shorten branches.
2270 As it is now, we must assume that all branches are the maximum size, and
2271 this causes us to almost always output constant pools sooner than
2274 /* Add a constant to the pool and return its label. */
2277 add_constant (x
, mode
, last_value
)
2279 enum machine_mode mode
;
2283 rtx lab
, new, ref
, newref
;
2285 /* First see if we've already got it. */
2286 for (i
= 0; i
< pool_size
; i
++)
2288 if (x
->code
== pool_vector
[i
].value
->code
2289 && mode
== pool_vector
[i
].mode
)
2291 if (x
->code
== CODE_LABEL
)
2293 if (XINT (x
, 3) != XINT (pool_vector
[i
].value
, 3))
2296 if (rtx_equal_p (x
, pool_vector
[i
].value
))
2301 || ! rtx_equal_p (last_value
, pool_vector
[i
-1].value
))
2303 new = gen_label_rtx ();
2304 LABEL_REFS (new) = pool_vector
[i
].label
;
2305 pool_vector
[i
].label
= lab
= new;
2307 if (lab
&& pool_window_label
)
2309 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2310 ref
= pool_vector
[pool_window_last
].wend
;
2311 LABEL_NEXTREF (newref
) = ref
;
2312 pool_vector
[pool_window_last
].wend
= newref
;
2315 pool_window_label
= new;
2316 pool_window_last
= i
;
2322 /* Need a new one. */
2323 pool_vector
[pool_size
].value
= x
;
2324 if (last_value
&& rtx_equal_p (last_value
, pool_vector
[pool_size
- 1].value
))
2327 pool_vector
[pool_size
- 1].part_of_sequence_p
= true;
2330 lab
= gen_label_rtx ();
2331 pool_vector
[pool_size
].mode
= mode
;
2332 pool_vector
[pool_size
].label
= lab
;
2333 pool_vector
[pool_size
].wend
= NULL_RTX
;
2334 pool_vector
[pool_size
].part_of_sequence_p
= (lab
== 0);
2335 if (lab
&& pool_window_label
)
2337 newref
= gen_rtx_LABEL_REF (VOIDmode
, pool_window_label
);
2338 ref
= pool_vector
[pool_window_last
].wend
;
2339 LABEL_NEXTREF (newref
) = ref
;
2340 pool_vector
[pool_window_last
].wend
= newref
;
2343 pool_window_label
= lab
;
2344 pool_window_last
= pool_size
;
2349 /* Output the literal table. */
2360 /* Do two passes, first time dump out the HI sized constants. */
2362 for (i
= 0; i
< pool_size
; i
++)
2364 pool_node
*p
= &pool_vector
[i
];
2366 if (p
->mode
== HImode
)
2370 scan
= emit_insn_after (gen_align_2 (), scan
);
2373 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2374 scan
= emit_label_after (lab
, scan
);
2375 scan
= emit_insn_after (gen_consttable_2 (p
->value
, const0_rtx
),
2377 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2379 lab
= XEXP (ref
, 0);
2380 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2383 else if (p
->mode
== DFmode
)
2389 if (TARGET_FMOVD
&& TARGET_ALIGN_DOUBLE
&& have_df
)
2391 rtx align_insn
= NULL_RTX
;
2393 scan
= emit_label_after (gen_label_rtx (), scan
);
2394 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2397 for (i
= 0; i
< pool_size
; i
++)
2399 pool_node
*p
= &pool_vector
[i
];
2407 if (align_insn
&& !p
->part_of_sequence_p
)
2409 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2410 emit_label_before (lab
, align_insn
);
2411 emit_insn_before (gen_consttable_4 (p
->value
, const0_rtx
),
2413 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2415 lab
= XEXP (ref
, 0);
2416 emit_insn_before (gen_consttable_window_end (lab
),
2419 delete_insn (align_insn
);
2420 align_insn
= NULL_RTX
;
2425 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2426 scan
= emit_label_after (lab
, scan
);
2427 scan
= emit_insn_after (gen_consttable_4 (p
->value
,
2429 need_align
= ! need_align
;
2435 scan
= emit_insn_after (gen_align_log (GEN_INT (3)), scan
);
2440 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2441 scan
= emit_label_after (lab
, scan
);
2442 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2450 if (p
->mode
!= HImode
)
2452 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2454 lab
= XEXP (ref
, 0);
2455 scan
= emit_insn_after (gen_consttable_window_end (lab
),
2464 for (i
= 0; i
< pool_size
; i
++)
2466 pool_node
*p
= &pool_vector
[i
];
2477 scan
= emit_label_after (gen_label_rtx (), scan
);
2478 scan
= emit_insn_after (gen_align_4 (), scan
);
2480 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2481 scan
= emit_label_after (lab
, scan
);
2482 scan
= emit_insn_after (gen_consttable_4 (p
->value
, const0_rtx
),
2490 scan
= emit_label_after (gen_label_rtx (), scan
);
2491 scan
= emit_insn_after (gen_align_4 (), scan
);
2493 for (lab
= p
->label
; lab
; lab
= LABEL_REFS (lab
))
2494 scan
= emit_label_after (lab
, scan
);
2495 scan
= emit_insn_after (gen_consttable_8 (p
->value
, const0_rtx
),
2503 if (p
->mode
!= HImode
)
2505 for (ref
= p
->wend
; ref
; ref
= LABEL_NEXTREF (ref
))
2507 lab
= XEXP (ref
, 0);
2508 scan
= emit_insn_after (gen_consttable_window_end (lab
), scan
);
2513 scan
= emit_insn_after (gen_consttable_end (), scan
);
2514 scan
= emit_barrier_after (scan
);
2516 pool_window_label
= NULL_RTX
;
2517 pool_window_last
= 0;
2520 /* Return nonzero if constant would be an ok source for a
2521 mov.w instead of a mov.l. */
2527 return (GET_CODE (src
) == CONST_INT
2528 && INTVAL (src
) >= -32768
2529 && INTVAL (src
) <= 32767);
2532 /* Nonzero if the insn is a move instruction which needs to be fixed. */
2534 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
2535 CONST_DOUBLE input value is CONST_OK_FOR_I. For a SFmode move, we don't
2536 need to fix it if the input value is CONST_OK_FOR_I. */
2542 if (GET_CODE (insn
) == INSN
)
2544 rtx pat
= PATTERN (insn
);
2545 if (GET_CODE (pat
) == PARALLEL
)
2546 pat
= XVECEXP (pat
, 0, 0);
2547 if (GET_CODE (pat
) == SET
2548 /* We can load any 8 bit value if we don't care what the high
2549 order bits end up as. */
2550 && GET_MODE (SET_DEST (pat
)) != QImode
2551 && (CONSTANT_P (SET_SRC (pat
))
2552 /* Match mova_const. */
2553 || (GET_CODE (SET_SRC (pat
)) == UNSPEC
2554 && XINT (SET_SRC (pat
), 1) == UNSPEC_MOVA
2555 && GET_CODE (XVECEXP (SET_SRC (pat
), 0, 0)) == CONST
))
2557 && GET_CODE (SET_SRC (pat
)) == CONST_DOUBLE
2558 && (fp_zero_operand (SET_SRC (pat
))
2559 || fp_one_operand (SET_SRC (pat
)))
2560 /* ??? If this is a -m4 or -m4-single compilation, in general
2561 we don't know the current setting of fpscr, so disable fldi.
2562 There is an exception if this was a register-register move
2563 before reload - and hence it was ascertained that we have
2564 single precision setting - and in a post-reload optimization
2565 we changed this to do a constant load. In that case
2566 we don't have an r0 clobber, hence we must use fldi. */
2567 && (! TARGET_SH4
|| TARGET_FMOVD
2568 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn
), 0, 2), 0))
2570 && GET_CODE (SET_DEST (pat
)) == REG
2571 && FP_REGISTER_P (REGNO (SET_DEST (pat
))))
2572 && (GET_CODE (SET_SRC (pat
)) != CONST_INT
2573 || ! CONST_OK_FOR_I (INTVAL (SET_SRC (pat
)))))
2584 return (GET_CODE (insn
) == INSN
2585 && GET_CODE (PATTERN (insn
)) == SET
2586 && GET_CODE (SET_SRC (PATTERN (insn
))) == UNSPEC
2587 && XINT (SET_SRC (PATTERN (insn
)), 1) == UNSPEC_MOVA
2588 /* Don't match mova_const. */
2589 && GET_CODE (XVECEXP (SET_SRC (PATTERN (insn
)), 0, 0)) == LABEL_REF
);
2592 /* Find the last barrier from insn FROM which is close enough to hold the
2593 constant pool. If we can't find one, then create one near the end of
2597 find_barrier (num_mova
, mova
, from
)
2608 int leading_mova
= num_mova
;
2609 rtx barrier_before_mova
, found_barrier
= 0, good_barrier
= 0;
2613 /* For HImode: range is 510, add 4 because pc counts from address of
2614 second instruction after this one, subtract 2 for the jump instruction
2615 that we may need to emit before the table, subtract 2 for the instruction
2616 that fills the jump delay slot (in very rare cases, reorg will take an
2617 instruction from after the constant pool or will leave the delay slot
2618 empty). This gives 510.
2619 For SImode: range is 1020, add 4 because pc counts from address of
2620 second instruction after this one, subtract 2 in case pc is 2 byte
2621 aligned, subtract 2 for the jump instruction that we may need to emit
2622 before the table, subtract 2 for the instruction that fills the jump
2623 delay slot. This gives 1018. */
2625 /* The branch will always be shortened now that the reference address for
2626 forward branches is the successor address, thus we need no longer make
2627 adjustments to the [sh]i_limit for -O0. */
2632 while (from
&& count_si
< si_limit
&& count_hi
< hi_limit
)
2634 int inc
= get_attr_length (from
);
2637 if (GET_CODE (from
) == CODE_LABEL
)
2640 new_align
= 1 << label_to_alignment (from
);
2641 else if (GET_CODE (prev_nonnote_insn (from
)) == BARRIER
)
2642 new_align
= 1 << barrier_align (from
);
2648 if (GET_CODE (from
) == BARRIER
)
2651 found_barrier
= from
;
2653 /* If we are at the end of the function, or in front of an alignment
2654 instruction, we need not insert an extra alignment. We prefer
2655 this kind of barrier. */
2656 if (barrier_align (from
) > 2)
2657 good_barrier
= from
;
2660 if (broken_move (from
))
2663 enum machine_mode mode
;
2665 pat
= PATTERN (from
);
2666 if (GET_CODE (pat
) == PARALLEL
)
2667 pat
= XVECEXP (pat
, 0, 0);
2668 src
= SET_SRC (pat
);
2669 dst
= SET_DEST (pat
);
2670 mode
= GET_MODE (dst
);
2672 /* We must explicitly check the mode, because sometimes the
2673 front end will generate code to load unsigned constants into
2674 HImode targets without properly sign extending them. */
2676 || (mode
== SImode
&& hi_const (src
) && REGNO (dst
) != FPUL_REG
))
2679 /* We put the short constants before the long constants, so
2680 we must count the length of short constants in the range
2681 for the long constants. */
2682 /* ??? This isn't optimal, but is easy to do. */
2687 /* We dump DF/DI constants before SF/SI ones, because
2688 the limit is the same, but the alignment requirements
2689 are higher. We may waste up to 4 additional bytes
2690 for alignment, and the DF/DI constant may have
2691 another SF/SI constant placed before it. */
2692 if (TARGET_SHCOMPACT
2694 && (mode
== DFmode
|| mode
== DImode
))
2699 while (si_align
> 2 && found_si
+ si_align
- 2 > count_si
)
2701 if (found_si
> count_si
)
2702 count_si
= found_si
;
2703 found_si
+= GET_MODE_SIZE (mode
);
2705 si_limit
-= GET_MODE_SIZE (mode
);
2708 /* See the code in machine_dependent_reorg, which has a similar if
2709 statement that generates a new mova insn in many cases. */
2710 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
2720 barrier_before_mova
= good_barrier
? good_barrier
: found_barrier
;
2722 if (found_si
> count_si
)
2723 count_si
= found_si
;
2725 else if (GET_CODE (from
) == JUMP_INSN
2726 && (GET_CODE (PATTERN (from
)) == ADDR_VEC
2727 || GET_CODE (PATTERN (from
)) == ADDR_DIFF_VEC
))
2731 if (barrier_align (next_real_insn (from
)) == CACHE_LOG
)
2733 /* We have just passed the barrier in front of the
2734 ADDR_DIFF_VEC, which is stored in found_barrier. Since
2735 the ADDR_DIFF_VEC is accessed as data, just like our pool
2736 constants, this is a good opportunity to accommodate what
2737 we have gathered so far.
2738 If we waited any longer, we could end up at a barrier in
2739 front of code, which gives worse cache usage for separated
2740 instruction / data caches. */
2741 good_barrier
= found_barrier
;
2746 rtx body
= PATTERN (from
);
2747 inc
= XVECLEN (body
, 1) * GET_MODE_SIZE (GET_MODE (body
));
2750 /* For the SH1, we generate alignments even after jumps-around-jumps. */
2751 else if (GET_CODE (from
) == JUMP_INSN
2753 && ! TARGET_SMALLCODE
)
2759 if (new_align
> si_align
)
2761 si_limit
-= (count_si
- 1) & (new_align
- si_align
);
2762 si_align
= new_align
;
2764 count_si
= (count_si
+ new_align
- 1) & -new_align
;
2769 if (new_align
> hi_align
)
2771 hi_limit
-= (count_hi
- 1) & (new_align
- hi_align
);
2772 hi_align
= new_align
;
2774 count_hi
= (count_hi
+ new_align
- 1) & -new_align
;
2776 from
= NEXT_INSN (from
);
2783 /* Try as we might, the leading mova is out of range. Change
2784 it into a load (which will become a pcload) and retry. */
2785 SET_SRC (PATTERN (mova
)) = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
2786 INSN_CODE (mova
) = -1;
2787 return find_barrier (0, 0, mova
);
2791 /* Insert the constant pool table before the mova instruction,
2792 to prevent the mova label reference from going out of range. */
2794 good_barrier
= found_barrier
= barrier_before_mova
;
2800 if (good_barrier
&& next_real_insn (found_barrier
))
2801 found_barrier
= good_barrier
;
2805 /* We didn't find a barrier in time to dump our stuff,
2806 so we'll make one. */
2807 rtx label
= gen_label_rtx ();
2809 /* If we exceeded the range, then we must back up over the last
2810 instruction we looked at. Otherwise, we just need to undo the
2811 NEXT_INSN at the end of the loop. */
2812 if (count_hi
> hi_limit
|| count_si
> si_limit
)
2813 from
= PREV_INSN (PREV_INSN (from
));
2815 from
= PREV_INSN (from
);
2817 /* Walk back to be just before any jump or label.
2818 Putting it before a label reduces the number of times the branch
2819 around the constant pool table will be hit. Putting it before
2820 a jump makes it more likely that the bra delay slot will be
2822 while (GET_CODE (from
) == JUMP_INSN
|| GET_CODE (from
) == NOTE
2823 || GET_CODE (from
) == CODE_LABEL
)
2824 from
= PREV_INSN (from
);
2826 from
= emit_jump_insn_after (gen_jump (label
), from
);
2827 JUMP_LABEL (from
) = label
;
2828 LABEL_NUSES (label
) = 1;
2829 found_barrier
= emit_barrier_after (from
);
2830 emit_label_after (label
, found_barrier
);
2833 return found_barrier
;
2836 /* If the instruction INSN is implemented by a special function, and we can
2837 positively find the register that is used to call the sfunc, and this
2838 register is not used anywhere else in this instruction - except as the
2839 destination of a set, return this register; else, return 0. */
2841 sfunc_uses_reg (insn
)
2845 rtx pattern
, part
, reg_part
, reg
;
2847 if (GET_CODE (insn
) != INSN
)
2849 pattern
= PATTERN (insn
);
2850 if (GET_CODE (pattern
) != PARALLEL
|| get_attr_type (insn
) != TYPE_SFUNC
)
2853 for (reg_part
= 0, i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2855 part
= XVECEXP (pattern
, 0, i
);
2856 if (GET_CODE (part
) == USE
&& GET_MODE (XEXP (part
, 0)) == SImode
)
2861 reg
= XEXP (reg_part
, 0);
2862 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 0; i
--)
2864 part
= XVECEXP (pattern
, 0, i
);
2865 if (part
== reg_part
|| GET_CODE (part
) == CLOBBER
)
2867 if (reg_mentioned_p (reg
, ((GET_CODE (part
) == SET
2868 && GET_CODE (SET_DEST (part
)) == REG
)
2869 ? SET_SRC (part
) : part
)))
2875 /* See if the only way in which INSN uses REG is by calling it, or by
2876 setting it while calling it. Set *SET to a SET rtx if the register
2880 noncall_uses_reg (reg
, insn
, set
)
2889 reg2
= sfunc_uses_reg (insn
);
2890 if (reg2
&& REGNO (reg2
) == REGNO (reg
))
2892 pattern
= single_set (insn
);
2894 && GET_CODE (SET_DEST (pattern
)) == REG
2895 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2899 if (GET_CODE (insn
) != CALL_INSN
)
2901 /* We don't use rtx_equal_p because we don't care if the mode is
2903 pattern
= single_set (insn
);
2905 && GET_CODE (SET_DEST (pattern
)) == REG
2906 && REGNO (reg
) == REGNO (SET_DEST (pattern
)))
2912 par
= PATTERN (insn
);
2913 if (GET_CODE (par
) == PARALLEL
)
2914 for (i
= XVECLEN (par
, 0) - 1; i
>= 0; i
--)
2916 part
= XVECEXP (par
, 0, i
);
2917 if (GET_CODE (part
) != SET
&& reg_mentioned_p (reg
, part
))
2920 return reg_mentioned_p (reg
, SET_SRC (pattern
));
2926 pattern
= PATTERN (insn
);
2928 if (GET_CODE (pattern
) == PARALLEL
)
2932 for (i
= XVECLEN (pattern
, 0) - 1; i
>= 1; i
--)
2933 if (reg_mentioned_p (reg
, XVECEXP (pattern
, 0, i
)))
2935 pattern
= XVECEXP (pattern
, 0, 0);
2938 if (GET_CODE (pattern
) == SET
)
2940 if (reg_mentioned_p (reg
, SET_DEST (pattern
)))
2942 /* We don't use rtx_equal_p, because we don't care if the
2943 mode is different. */
2944 if (GET_CODE (SET_DEST (pattern
)) != REG
2945 || REGNO (reg
) != REGNO (SET_DEST (pattern
)))
2951 pattern
= SET_SRC (pattern
);
2954 if (GET_CODE (pattern
) != CALL
2955 || GET_CODE (XEXP (pattern
, 0)) != MEM
2956 || ! rtx_equal_p (reg
, XEXP (XEXP (pattern
, 0), 0)))
2962 /* Given a X, a pattern of an insn or a part of it, return a mask of used
2963 general registers. Bits 0..15 mean that the respective registers
2964 are used as inputs in the instruction. Bits 16..31 mean that the
2965 registers 0..15, respectively, are used as outputs, or are clobbered.
2966 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
2968 regs_used (x
, is_dest
)
2977 code
= GET_CODE (x
);
2982 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2983 << (REGNO (x
) + is_dest
));
2987 rtx y
= SUBREG_REG (x
);
2989 if (GET_CODE (y
) != REG
)
2992 return (((1 << HARD_REGNO_NREGS (0, GET_MODE (x
))) - 1)
2994 subreg_regno_offset (REGNO (y
),
2997 GET_MODE (x
)) + is_dest
));
3001 return regs_used (SET_SRC (x
), 0) | regs_used (SET_DEST (x
), 16);
3003 /* If there was a return value, it must have been indicated with USE. */
3018 fmt
= GET_RTX_FORMAT (code
);
3020 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3025 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3026 used
|= regs_used (XVECEXP (x
, i
, j
), is_dest
);
3028 else if (fmt
[i
] == 'e')
3029 used
|= regs_used (XEXP (x
, i
), is_dest
);
3034 /* Create an instruction that prevents redirection of a conditional branch
3035 to the destination of the JUMP with address ADDR.
3036 If the branch needs to be implemented as an indirect jump, try to find
3037 a scratch register for it.
3038 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
3039 If any preceding insn that doesn't fit into a delay slot is good enough,
3040 pass 1. Pass 2 if a definite blocking insn is needed.
3041 -1 is used internally to avoid deep recursion.
3042 If a blocking instruction is made or recognized, return it. */
3045 gen_block_redirect (jump
, addr
, need_block
)
3047 int addr
, need_block
;
3050 rtx prev
= prev_nonnote_insn (jump
);
3053 /* First, check if we already have an instruction that satisfies our need. */
3054 if (prev
&& GET_CODE (prev
) == INSN
&& ! INSN_DELETED_P (prev
))
3056 if (INSN_CODE (prev
) == CODE_FOR_indirect_jump_scratch
)
3058 if (GET_CODE (PATTERN (prev
)) == USE
3059 || GET_CODE (PATTERN (prev
)) == CLOBBER
3060 || get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3062 else if ((need_block
&= ~1) < 0)
3064 else if (recog_memoized (prev
) == CODE_FOR_block_branch_redirect
)
3067 /* We can't use JUMP_LABEL here because it might be undefined
3068 when not optimizing. */
3069 dest
= XEXP (SET_SRC (PATTERN (jump
)), 0);
3070 /* If the branch is out of range, try to find a scratch register for it. */
3072 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3076 /* Don't look for the stack pointer as a scratch register,
3077 it would cause trouble if an interrupt occurred. */
3078 unsigned try = 0x7fff, used
;
3079 int jump_left
= flag_expensive_optimizations
+ 1;
3081 /* It is likely that the most recent eligible instruction is wanted for
3082 the delay slot. Therefore, find out which registers it uses, and
3083 try to avoid using them. */
3085 for (scan
= jump
; (scan
= PREV_INSN (scan
)); )
3089 if (INSN_DELETED_P (scan
))
3091 code
= GET_CODE (scan
);
3092 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
3095 && GET_CODE (PATTERN (scan
)) != USE
3096 && GET_CODE (PATTERN (scan
)) != CLOBBER
3097 && get_attr_in_delay_slot (scan
) == IN_DELAY_SLOT_YES
)
3099 try &= ~regs_used (PATTERN (scan
), 0);
3103 for (used
= dead
= 0, scan
= JUMP_LABEL (jump
);
3104 (scan
= NEXT_INSN (scan
)); )
3108 if (INSN_DELETED_P (scan
))
3110 code
= GET_CODE (scan
);
3111 if (GET_RTX_CLASS (code
) == 'i')
3113 used
|= regs_used (PATTERN (scan
), 0);
3114 if (code
== CALL_INSN
)
3115 used
|= regs_used (CALL_INSN_FUNCTION_USAGE (scan
), 0);
3116 dead
|= (used
>> 16) & ~used
;
3122 if (code
== JUMP_INSN
)
3124 if (jump_left
-- && simplejump_p (scan
))
3125 scan
= JUMP_LABEL (scan
);
3131 /* Mask out the stack pointer again, in case it was
3132 the only 'free' register we have found. */
3135 /* If the immediate destination is still in range, check for possible
3136 threading with a jump beyond the delay slot insn.
3137 Don't check if we are called recursively; the jump has been or will be
3138 checked in a different invocation then. */
3140 else if (optimize
&& need_block
>= 0)
3142 rtx next
= next_active_insn (next_active_insn (dest
));
3143 if (next
&& GET_CODE (next
) == JUMP_INSN
3144 && GET_CODE (PATTERN (next
)) == SET
3145 && recog_memoized (next
) == CODE_FOR_jump
)
3147 dest
= JUMP_LABEL (next
);
3149 && (INSN_ADDRESSES (INSN_UID (dest
)) - addr
+ (unsigned) 4092
3151 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), -1);
3157 rtx reg
= gen_rtx_REG (SImode
, exact_log2 (dead
& -dead
));
3159 /* It would be nice if we could convert the jump into an indirect
3160 jump / far branch right now, and thus exposing all constituent
3161 instructions to further optimization. However, reorg uses
3162 simplejump_p to determine if there is an unconditional jump where
3163 it should try to schedule instructions from the target of the
3164 branch; simplejump_p fails for indirect jumps even if they have
3166 rtx insn
= emit_insn_before (gen_indirect_jump_scratch
3167 (reg
, GEN_INT (INSN_UID (JUMP_LABEL (jump
))))
3169 INSN_CODE (insn
) = CODE_FOR_indirect_jump_scratch
;
3172 else if (need_block
)
3173 /* We can't use JUMP_LABEL here because it might be undefined
3174 when not optimizing. */
3175 return emit_insn_before (gen_block_branch_redirect
3176 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))))
3181 #define CONDJUMP_MIN -252
3182 #define CONDJUMP_MAX 262
3185 /* A label (to be placed) in front of the jump
3186 that jumps to our ultimate destination. */
3188 /* Where we are going to insert it if we cannot move the jump any farther,
3189 or the jump itself if we have picked up an existing jump. */
3191 /* The ultimate destination. */
3193 struct far_branch
*prev
;
3194 /* If the branch has already been created, its address;
3195 else the address of its first prospective user. */
3199 static void gen_far_branch
PARAMS ((struct far_branch
*));
3200 enum mdep_reorg_phase_e mdep_reorg_phase
;
3203 struct far_branch
*bp
;
3205 rtx insn
= bp
->insert_place
;
3207 rtx label
= gen_label_rtx ();
3209 emit_label_after (label
, insn
);
3212 jump
= emit_jump_insn_after (gen_jump (bp
->far_label
), insn
);
3213 LABEL_NUSES (bp
->far_label
)++;
3216 jump
= emit_jump_insn_after (gen_return (), insn
);
3217 /* Emit a barrier so that reorg knows that any following instructions
3218 are not reachable via a fall-through path.
3219 But don't do this when not optimizing, since we wouldn't supress the
3220 alignment for the barrier then, and could end up with out-of-range
3221 pc-relative loads. */
3223 emit_barrier_after (jump
);
3224 emit_label_after (bp
->near_label
, insn
);
3225 JUMP_LABEL (jump
) = bp
->far_label
;
3226 if (! invert_jump (insn
, label
, 1))
3229 (gen_stuff_delay_slot
3230 (GEN_INT (INSN_UID (XEXP (SET_SRC (PATTERN (jump
)), 0))),
3231 GEN_INT (recog_memoized (insn
) == CODE_FOR_branch_false
)),
3233 /* Prevent reorg from undoing our splits. */
3234 gen_block_redirect (jump
, bp
->address
+= 2, 2);
3237 /* Fix up ADDR_DIFF_VECs. */
3239 fixup_addr_diff_vecs (first
)
3244 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3246 rtx vec_lab
, pat
, prev
, prevpat
, x
, braf_label
;
3248 if (GET_CODE (insn
) != JUMP_INSN
3249 || GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
3251 pat
= PATTERN (insn
);
3252 vec_lab
= XEXP (XEXP (pat
, 0), 0);
3254 /* Search the matching casesi_jump_2. */
3255 for (prev
= vec_lab
; ; prev
= PREV_INSN (prev
))
3257 if (GET_CODE (prev
) != JUMP_INSN
)
3259 prevpat
= PATTERN (prev
);
3260 if (GET_CODE (prevpat
) != PARALLEL
|| XVECLEN (prevpat
, 0) != 2)
3262 x
= XVECEXP (prevpat
, 0, 1);
3263 if (GET_CODE (x
) != USE
)
3266 if (GET_CODE (x
) == LABEL_REF
&& XEXP (x
, 0) == vec_lab
)
3270 /* Emit the reference label of the braf where it belongs, right after
3271 the casesi_jump_2 (i.e. braf). */
3272 braf_label
= XEXP (XEXP (SET_SRC (XVECEXP (prevpat
, 0, 0)), 1), 0);
3273 emit_label_after (braf_label
, prev
);
3275 /* Fix up the ADDR_DIF_VEC to be relative
3276 to the reference address of the braf. */
3277 XEXP (XEXP (pat
, 0), 0) = braf_label
;
3281 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
3282 a barrier. Return the base 2 logarithm of the desired alignment. */
3284 barrier_align (barrier_or_label
)
3285 rtx barrier_or_label
;
3287 rtx next
= next_real_insn (barrier_or_label
), pat
, prev
;
3288 int slot
, credit
, jump_to_next
;
3293 pat
= PATTERN (next
);
3295 if (GET_CODE (pat
) == ADDR_DIFF_VEC
)
3298 if (GET_CODE (pat
) == UNSPEC_VOLATILE
&& XINT (pat
, 1) == UNSPECV_ALIGN
)
3299 /* This is a barrier in front of a constant table. */
3302 prev
= prev_real_insn (barrier_or_label
);
3303 if (GET_CODE (PATTERN (prev
)) == ADDR_DIFF_VEC
)
3305 pat
= PATTERN (prev
);
3306 /* If this is a very small table, we want to keep the alignment after
3307 the table to the minimum for proper code alignment. */
3308 return ((TARGET_SMALLCODE
3309 || ((unsigned) XVECLEN (pat
, 1) * GET_MODE_SIZE (GET_MODE (pat
))
3310 <= (unsigned)1 << (CACHE_LOG
- 2)))
3311 ? 1 << TARGET_SHMEDIA
: CACHE_LOG
);
3314 if (TARGET_SMALLCODE
)
3317 if (! TARGET_SH2
|| ! optimize
)
3320 /* When fixing up pcloads, a constant table might be inserted just before
3321 the basic block that ends with the barrier. Thus, we can't trust the
3322 instruction lengths before that. */
3323 if (mdep_reorg_phase
> SH_FIXUP_PCLOAD
)
3325 /* Check if there is an immediately preceding branch to the insn beyond
3326 the barrier. We must weight the cost of discarding useful information
3327 from the current cache line when executing this branch and there is
3328 an alignment, against that of fetching unneeded insn in front of the
3329 branch target when there is no alignment. */
3331 /* There are two delay_slot cases to consider. One is the simple case
3332 where the preceding branch is to the insn beyond the barrier (simple
3333 delay slot filling), and the other is where the preceding branch has
3334 a delay slot that is a duplicate of the insn after the barrier
3335 (fill_eager_delay_slots) and the branch is to the insn after the insn
3336 after the barrier. */
3338 /* PREV is presumed to be the JUMP_INSN for the barrier under
3339 investigation. Skip to the insn before it. */
3340 prev
= prev_real_insn (prev
);
3342 for (slot
= 2, credit
= (1 << (CACHE_LOG
- 2)) + 2;
3343 credit
>= 0 && prev
&& GET_CODE (prev
) == INSN
;
3344 prev
= prev_real_insn (prev
))
3347 if (GET_CODE (PATTERN (prev
)) == USE
3348 || GET_CODE (PATTERN (prev
)) == CLOBBER
)
3350 if (GET_CODE (PATTERN (prev
)) == SEQUENCE
)
3352 prev
= XVECEXP (PATTERN (prev
), 0, 1);
3353 if (INSN_UID (prev
) == INSN_UID (next
))
3355 /* Delay slot was filled with insn at jump target. */
3362 get_attr_in_delay_slot (prev
) == IN_DELAY_SLOT_YES
)
3364 credit
-= get_attr_length (prev
);
3367 && GET_CODE (prev
) == JUMP_INSN
3368 && JUMP_LABEL (prev
))
3372 || next_real_insn (JUMP_LABEL (prev
)) == next
3373 /* If relax_delay_slots() decides NEXT was redundant
3374 with some previous instruction, it will have
3375 redirected PREV's jump to the following insn. */
3376 || JUMP_LABEL (prev
) == next_nonnote_insn (next
)
3377 /* There is no upper bound on redundant instructions
3378 that might have been skipped, but we must not put an
3379 alignment where none had been before. */
3380 || (x
= (NEXT_INSN (NEXT_INSN (PREV_INSN (prev
)))),
3382 && (INSN_CODE (x
) == CODE_FOR_block_branch_redirect
3383 || INSN_CODE (x
) == CODE_FOR_indirect_jump_scratch
))))
3385 rtx pat
= PATTERN (prev
);
3386 if (GET_CODE (pat
) == PARALLEL
)
3387 pat
= XVECEXP (pat
, 0, 0);
3388 if (credit
- slot
>= (GET_CODE (SET_SRC (pat
)) == PC
? 2 : 0))
3397 /* If we are inside a phony loop, almost any kind of label can turn up as the
3398 first one in the loop. Aligning a braf label causes incorrect switch
3399 destination addresses; we can detect braf labels because they are
3400 followed by a BARRIER.
3401 Applying loop alignment to small constant or switch tables is a waste
3402 of space, so we suppress this too. */
3404 sh_loop_align (label
)
3410 next
= next_nonnote_insn (next
);
3411 while (next
&& GET_CODE (next
) == CODE_LABEL
);
3415 || GET_CODE (PATTERN (next
)) == ADDR_DIFF_VEC
3416 || recog_memoized (next
) == CODE_FOR_consttable_2
)
3425 /* Exported to toplev.c.
3427 Do a final pass over the function, just before delayed branch
3431 machine_dependent_reorg (first
)
3436 rtx r0_rtx
= gen_rtx_REG (Pmode
, 0);
3437 rtx r0_inc_rtx
= gen_rtx_POST_INC (Pmode
, r0_rtx
);
3439 /* We must split call insns before introducing `mova's. If we're
3440 optimizing, they'll have already been split. Otherwise, make
3441 sure we don't split them too late. */
3443 split_all_insns_noflow ();
3448 /* If relaxing, generate pseudo-ops to associate function calls with
3449 the symbols they call. It does no harm to not generate these
3450 pseudo-ops. However, when we can generate them, it enables to
3451 linker to potentially relax the jsr to a bsr, and eliminate the
3452 register load and, possibly, the constant pool entry. */
3454 mdep_reorg_phase
= SH_INSERT_USES_LABELS
;
3457 /* Remove all REG_LABEL notes. We want to use them for our own
3458 purposes. This works because none of the remaining passes
3459 need to look at them.
3461 ??? But it may break in the future. We should use a machine
3462 dependent REG_NOTE, or some other approach entirely. */
3463 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3469 while ((note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
)) != 0)
3470 remove_note (insn
, note
);
3474 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3476 rtx pattern
, reg
, link
, set
, scan
, dies
, label
;
3477 int rescan
= 0, foundinsn
= 0;
3479 if (GET_CODE (insn
) == CALL_INSN
)
3481 pattern
= PATTERN (insn
);
3483 if (GET_CODE (pattern
) == PARALLEL
)
3484 pattern
= XVECEXP (pattern
, 0, 0);
3485 if (GET_CODE (pattern
) == SET
)
3486 pattern
= SET_SRC (pattern
);
3488 if (GET_CODE (pattern
) != CALL
3489 || GET_CODE (XEXP (pattern
, 0)) != MEM
)
3492 reg
= XEXP (XEXP (pattern
, 0), 0);
3496 reg
= sfunc_uses_reg (insn
);
3501 if (GET_CODE (reg
) != REG
)
3504 /* This is a function call via REG. If the only uses of REG
3505 between the time that it is set and the time that it dies
3506 are in function calls, then we can associate all the
3507 function calls with the setting of REG. */
3509 for (link
= LOG_LINKS (insn
); link
; link
= XEXP (link
, 1))
3511 if (REG_NOTE_KIND (link
) != 0)
3513 set
= single_set (XEXP (link
, 0));
3514 if (set
&& rtx_equal_p (reg
, SET_DEST (set
)))
3516 link
= XEXP (link
, 0);
3523 /* ??? Sometimes global register allocation will have
3524 deleted the insn pointed to by LOG_LINKS. Try
3525 scanning backward to find where the register is set. */
3526 for (scan
= PREV_INSN (insn
);
3527 scan
&& GET_CODE (scan
) != CODE_LABEL
;
3528 scan
= PREV_INSN (scan
))
3530 if (! INSN_P (scan
))
3533 if (! reg_mentioned_p (reg
, scan
))
3536 if (noncall_uses_reg (reg
, scan
, &set
))
3550 /* The register is set at LINK. */
3552 /* We can only optimize the function call if the register is
3553 being set to a symbol. In theory, we could sometimes
3554 optimize calls to a constant location, but the assembler
3555 and linker do not support that at present. */
3556 if (GET_CODE (SET_SRC (set
)) != SYMBOL_REF
3557 && GET_CODE (SET_SRC (set
)) != LABEL_REF
)
3560 /* Scan forward from LINK to the place where REG dies, and
3561 make sure that the only insns which use REG are
3562 themselves function calls. */
3564 /* ??? This doesn't work for call targets that were allocated
3565 by reload, since there may not be a REG_DEAD note for the
3569 for (scan
= NEXT_INSN (link
); scan
; scan
= NEXT_INSN (scan
))
3573 /* Don't try to trace forward past a CODE_LABEL if we haven't
3574 seen INSN yet. Ordinarily, we will only find the setting insn
3575 in LOG_LINKS if it is in the same basic block. However,
3576 cross-jumping can insert code labels in between the load and
3577 the call, and can result in situations where a single call
3578 insn may have two targets depending on where we came from. */
3580 if (GET_CODE (scan
) == CODE_LABEL
&& ! foundinsn
)
3583 if (! INSN_P (scan
))
3586 /* Don't try to trace forward past a JUMP. To optimize
3587 safely, we would have to check that all the
3588 instructions at the jump destination did not use REG. */
3590 if (GET_CODE (scan
) == JUMP_INSN
)
3593 if (! reg_mentioned_p (reg
, scan
))
3596 if (noncall_uses_reg (reg
, scan
, &scanset
))
3603 && (GET_CODE (scan
) == CALL_INSN
|| sfunc_uses_reg (scan
)))
3605 /* There is a function call to this register other
3606 than the one we are checking. If we optimize
3607 this call, we need to rescan again below. */
3611 /* ??? We shouldn't have to worry about SCANSET here.
3612 We should just be able to check for a REG_DEAD note
3613 on a function call. However, the REG_DEAD notes are
3614 apparently not dependable around libcalls; c-torture
3615 execute/920501-2 is a test case. If SCANSET is set,
3616 then this insn sets the register, so it must have
3617 died earlier. Unfortunately, this will only handle
3618 the cases in which the register is, in fact, set in a
3621 /* ??? We shouldn't have to use FOUNDINSN here.
3622 However, the LOG_LINKS fields are apparently not
3623 entirely reliable around libcalls;
3624 newlib/libm/math/e_pow.c is a test case. Sometimes
3625 an insn will appear in LOG_LINKS even though it is
3626 not the most recent insn which sets the register. */
3630 || find_reg_note (scan
, REG_DEAD
, reg
)))
3639 /* Either there was a branch, or some insn used REG
3640 other than as a function call address. */
3644 /* Create a code label, and put it in a REG_LABEL note on
3645 the insn which sets the register, and on each call insn
3646 which uses the register. In final_prescan_insn we look
3647 for the REG_LABEL notes, and output the appropriate label
3650 label
= gen_label_rtx ();
3651 REG_NOTES (link
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
3653 REG_NOTES (insn
) = gen_rtx_INSN_LIST (REG_LABEL
, label
,
3662 scan
= NEXT_INSN (scan
);
3664 && ((GET_CODE (scan
) == CALL_INSN
3665 && reg_mentioned_p (reg
, scan
))
3666 || ((reg2
= sfunc_uses_reg (scan
))
3667 && REGNO (reg2
) == REGNO (reg
))))
3669 = gen_rtx_INSN_LIST (REG_LABEL
, label
, REG_NOTES (scan
));
3671 while (scan
!= dies
);
3677 fixup_addr_diff_vecs (first
);
3681 mdep_reorg_phase
= SH_SHORTEN_BRANCHES0
;
3682 shorten_branches (first
);
3684 /* Scan the function looking for move instructions which have to be
3685 changed to pc-relative loads and insert the literal tables. */
3687 mdep_reorg_phase
= SH_FIXUP_PCLOAD
;
3688 for (insn
= first
, num_mova
= 0; insn
; insn
= NEXT_INSN (insn
))
3695 else if (GET_CODE (insn
) == JUMP_INSN
3696 && GET_CODE (PATTERN (insn
)) == ADDR_DIFF_VEC
3704 /* Some code might have been inserted between the mova and
3705 its ADDR_DIFF_VEC. Check if the mova is still in range. */
3706 for (scan
= mova
, total
= 0; scan
!= insn
; scan
= NEXT_INSN (scan
))
3707 total
+= get_attr_length (scan
);
3709 /* range of mova is 1020, add 4 because pc counts from address of
3710 second instruction after this one, subtract 2 in case pc is 2
3711 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
3712 cancels out with alignment effects of the mova itself. */
3715 /* Change the mova into a load, and restart scanning
3716 there. broken_move will then return true for mova. */
3717 SET_SRC (PATTERN (mova
))
3718 = XVECEXP (SET_SRC (PATTERN (mova
)), 0, 0);
3719 INSN_CODE (mova
) = -1;
3723 if (broken_move (insn
))
3726 /* Scan ahead looking for a barrier to stick the constant table
3728 rtx barrier
= find_barrier (num_mova
, mova
, insn
);
3729 rtx last_float_move
, last_float
= 0, *last_float_addr
;
3731 if (num_mova
&& ! mova_p (mova
))
3733 /* find_barrier had to change the first mova into a
3734 pcload; thus, we have to start with this new pcload. */
3738 /* Now find all the moves between the points and modify them. */
3739 for (scan
= insn
; scan
!= barrier
; scan
= NEXT_INSN (scan
))
3741 if (GET_CODE (scan
) == CODE_LABEL
)
3743 if (broken_move (scan
))
3745 rtx
*patp
= &PATTERN (scan
), pat
= *patp
;
3749 enum machine_mode mode
;
3751 if (GET_CODE (pat
) == PARALLEL
)
3752 patp
= &XVECEXP (pat
, 0, 0), pat
= *patp
;
3753 src
= SET_SRC (pat
);
3754 dst
= SET_DEST (pat
);
3755 mode
= GET_MODE (dst
);
3757 if (mode
== SImode
&& hi_const (src
)
3758 && REGNO (dst
) != FPUL_REG
)
3763 while (GET_CODE (dst
) == SUBREG
)
3765 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
3766 GET_MODE (SUBREG_REG (dst
)),
3769 dst
= SUBREG_REG (dst
);
3771 dst
= gen_rtx_REG (HImode
, REGNO (dst
) + offset
);
3774 if (GET_CODE (dst
) == REG
&& FP_ANY_REGISTER_P (REGNO (dst
)))
3776 /* This must be an insn that clobbers r0. */
3777 rtx clobber
= XVECEXP (PATTERN (scan
), 0,
3778 XVECLEN (PATTERN (scan
), 0) - 1);
3780 if (GET_CODE (clobber
) != CLOBBER
3781 || ! rtx_equal_p (XEXP (clobber
, 0), r0_rtx
))
3785 && reg_set_between_p (r0_rtx
, last_float_move
, scan
))
3789 && GET_MODE_SIZE (mode
) != 4
3790 && GET_MODE_SIZE (GET_MODE (last_float
)) == 4)
3792 lab
= add_constant (src
, mode
, last_float
);
3794 emit_insn_before (gen_mova (lab
), scan
);
3797 /* There will be a REG_UNUSED note for r0 on
3798 LAST_FLOAT_MOVE; we have to change it to REG_INC,
3799 lest reorg:mark_target_live_regs will not
3800 consider r0 to be used, and we end up with delay
3801 slot insn in front of SCAN that clobbers r0. */
3803 = find_regno_note (last_float_move
, REG_UNUSED
, 0);
3805 /* If we are not optimizing, then there may not be
3808 PUT_MODE (note
, REG_INC
);
3810 *last_float_addr
= r0_inc_rtx
;
3812 last_float_move
= scan
;
3814 newsrc
= gen_rtx (MEM
, mode
,
3815 (((TARGET_SH4
&& ! TARGET_FMOVD
)
3816 || REGNO (dst
) == FPUL_REG
)
3819 last_float_addr
= &XEXP (newsrc
, 0);
3821 /* Remove the clobber of r0. */
3822 XEXP (clobber
, 0) = gen_rtx_SCRATCH (Pmode
);
3823 RTX_UNCHANGING_P (newsrc
) = 1;
3825 /* This is a mova needing a label. Create it. */
3826 else if (GET_CODE (src
) == UNSPEC
3827 && XINT (src
, 1) == UNSPEC_MOVA
3828 && GET_CODE (XVECEXP (src
, 0, 0)) == CONST
)
3830 lab
= add_constant (XVECEXP (src
, 0, 0), mode
, 0);
3831 newsrc
= gen_rtx_LABEL_REF (VOIDmode
, lab
);
3832 newsrc
= gen_rtx_UNSPEC (SImode
,
3833 gen_rtvec (1, newsrc
),
3838 lab
= add_constant (src
, mode
, 0);
3839 newsrc
= gen_rtx_MEM (mode
,
3840 gen_rtx_LABEL_REF (VOIDmode
, lab
));
3841 RTX_UNCHANGING_P (newsrc
) = 1;
3843 *patp
= gen_rtx_SET (VOIDmode
, dst
, newsrc
);
3844 INSN_CODE (scan
) = -1;
3847 dump_table (barrier
);
3852 mdep_reorg_phase
= SH_SHORTEN_BRANCHES1
;
3853 INSN_ADDRESSES_FREE ();
3854 split_branches (first
);
3856 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
3857 also has an effect on the register that holds the address of the sfunc.
3858 Insert an extra dummy insn in front of each sfunc that pretends to
3859 use this register. */
3860 if (flag_delayed_branch
)
3862 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3864 rtx reg
= sfunc_uses_reg (insn
);
3868 emit_insn_before (gen_use_sfunc_addr (reg
), insn
);
3872 /* fpscr is not actually a user variable, but we pretend it is for the
3873 sake of the previous optimization passes, since we want it handled like
3874 one. However, we don't have any debugging information for it, so turn
3875 it into a non-user variable now. */
3877 REG_USERVAR_P (get_fpscr_rtx ()) = 0;
3879 mdep_reorg_phase
= SH_AFTER_MDEP_REORG
;
3883 get_dest_uid (label
, max_uid
)
3887 rtx dest
= next_real_insn (label
);
3890 /* This can happen for an undefined label. */
3892 dest_uid
= INSN_UID (dest
);
3893 /* If this is a newly created branch redirection blocking instruction,
3894 we cannot index the branch_uid or insn_addresses arrays with its
3895 uid. But then, we won't need to, because the actual destination is
3896 the following branch. */
3897 while (dest_uid
>= max_uid
)
3899 dest
= NEXT_INSN (dest
);
3900 dest_uid
= INSN_UID (dest
);
3902 if (GET_CODE (dest
) == JUMP_INSN
&& GET_CODE (PATTERN (dest
)) == RETURN
)
3907 /* Split condbranches that are out of range. Also add clobbers for
3908 scratch registers that are needed in far jumps.
3909 We do this before delay slot scheduling, so that it can take our
3910 newly created instructions into account. It also allows us to
3911 find branches with common targets more easily. */
3914 split_branches (first
)
3918 struct far_branch
**uid_branch
, *far_branch_list
= 0;
3919 int max_uid
= get_max_uid ();
3921 /* Find out which branches are out of range. */
3922 shorten_branches (first
);
3924 uid_branch
= (struct far_branch
**) alloca (max_uid
* sizeof *uid_branch
);
3925 memset ((char *) uid_branch
, 0, max_uid
* sizeof *uid_branch
);
3927 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
3928 if (! INSN_P (insn
))
3930 else if (INSN_DELETED_P (insn
))
3932 /* Shorten_branches would split this instruction again,
3933 so transform it into a note. */
3934 PUT_CODE (insn
, NOTE
);
3935 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
3936 NOTE_SOURCE_FILE (insn
) = 0;
3938 else if (GET_CODE (insn
) == JUMP_INSN
3939 /* Don't mess with ADDR_DIFF_VEC */
3940 && (GET_CODE (PATTERN (insn
)) == SET
3941 || GET_CODE (PATTERN (insn
)) == RETURN
))
3943 enum attr_type type
= get_attr_type (insn
);
3944 if (type
== TYPE_CBRANCH
)
3948 if (get_attr_length (insn
) > 4)
3950 rtx src
= SET_SRC (PATTERN (insn
));
3951 rtx olabel
= XEXP (XEXP (src
, 1), 0);
3952 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
3954 int dest_uid
= get_dest_uid (olabel
, max_uid
);
3955 struct far_branch
*bp
= uid_branch
[dest_uid
];
3957 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
3958 the label if the LABEL_NUSES count drops to zero. There is
3959 always a jump_optimize pass that sets these values, but it
3960 proceeds to delete unreferenced code, and then if not
3961 optimizing, to un-delete the deleted instructions, thus
3962 leaving labels with too low uses counts. */
3965 JUMP_LABEL (insn
) = olabel
;
3966 LABEL_NUSES (olabel
)++;
3970 bp
= (struct far_branch
*) alloca (sizeof *bp
);
3971 uid_branch
[dest_uid
] = bp
;
3972 bp
->prev
= far_branch_list
;
3973 far_branch_list
= bp
;
3975 = XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1), 0);
3976 LABEL_NUSES (bp
->far_label
)++;
3980 label
= bp
->near_label
;
3981 if (! label
&& bp
->address
- addr
>= CONDJUMP_MIN
)
3983 rtx block
= bp
->insert_place
;
3985 if (GET_CODE (PATTERN (block
)) == RETURN
)
3986 block
= PREV_INSN (block
);
3988 block
= gen_block_redirect (block
,
3990 label
= emit_label_after (gen_label_rtx (),
3992 bp
->near_label
= label
;
3994 else if (label
&& ! NEXT_INSN (label
))
3996 if (addr
+ 2 - bp
->address
<= CONDJUMP_MAX
)
3997 bp
->insert_place
= insn
;
3999 gen_far_branch (bp
);
4003 || (NEXT_INSN (label
) && bp
->address
- addr
< CONDJUMP_MIN
))
4005 bp
->near_label
= label
= gen_label_rtx ();
4006 bp
->insert_place
= insn
;
4009 if (! redirect_jump (insn
, label
, 1))
4014 /* get_attr_length (insn) == 2 */
4015 /* Check if we have a pattern where reorg wants to redirect
4016 the branch to a label from an unconditional branch that
4018 /* We can't use JUMP_LABEL here because it might be undefined
4019 when not optimizing. */
4020 /* A syntax error might cause beyond to be NULL_RTX. */
4022 = next_active_insn (XEXP (XEXP (SET_SRC (PATTERN (insn
)), 1),
4026 && (GET_CODE (beyond
) == JUMP_INSN
4027 || ((beyond
= next_active_insn (beyond
))
4028 && GET_CODE (beyond
) == JUMP_INSN
))
4029 && GET_CODE (PATTERN (beyond
)) == SET
4030 && recog_memoized (beyond
) == CODE_FOR_jump
4032 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond
)), 0)))
4033 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4035 gen_block_redirect (beyond
,
4036 INSN_ADDRESSES (INSN_UID (beyond
)), 1);
4039 next
= next_active_insn (insn
);
4041 if ((GET_CODE (next
) == JUMP_INSN
4042 || GET_CODE (next
= next_active_insn (next
)) == JUMP_INSN
)
4043 && GET_CODE (PATTERN (next
)) == SET
4044 && recog_memoized (next
) == CODE_FOR_jump
4046 (INSN_UID (XEXP (SET_SRC (PATTERN (next
)), 0)))
4047 - INSN_ADDRESSES (INSN_UID (insn
)) + (unsigned) 252)
4049 gen_block_redirect (next
, INSN_ADDRESSES (INSN_UID (next
)), 1);
4051 else if (type
== TYPE_JUMP
|| type
== TYPE_RETURN
)
4053 int addr
= INSN_ADDRESSES (INSN_UID (insn
));
4056 struct far_branch
*bp
;
4058 if (type
== TYPE_JUMP
)
4060 far_label
= XEXP (SET_SRC (PATTERN (insn
)), 0);
4061 dest_uid
= get_dest_uid (far_label
, max_uid
);
4064 /* Parse errors can lead to labels outside
4066 if (! NEXT_INSN (far_label
))
4071 JUMP_LABEL (insn
) = far_label
;
4072 LABEL_NUSES (far_label
)++;
4074 redirect_jump (insn
, NULL_RTX
, 1);
4078 bp
= uid_branch
[dest_uid
];
4081 bp
= (struct far_branch
*) alloca (sizeof *bp
);
4082 uid_branch
[dest_uid
] = bp
;
4083 bp
->prev
= far_branch_list
;
4084 far_branch_list
= bp
;
4086 bp
->far_label
= far_label
;
4088 LABEL_NUSES (far_label
)++;
4090 else if (bp
->near_label
&& ! NEXT_INSN (bp
->near_label
))
4091 if (addr
- bp
->address
<= CONDJUMP_MAX
)
4092 emit_label_after (bp
->near_label
, PREV_INSN (insn
));
4095 gen_far_branch (bp
);
4101 bp
->insert_place
= insn
;
4103 emit_insn_before (gen_block_branch_redirect (const0_rtx
), insn
);
4105 gen_block_redirect (insn
, addr
, bp
->near_label
? 2 : 0);
4108 /* Generate all pending far branches,
4109 and free our references to the far labels. */
4110 while (far_branch_list
)
4112 if (far_branch_list
->near_label
4113 && ! NEXT_INSN (far_branch_list
->near_label
))
4114 gen_far_branch (far_branch_list
);
4116 && far_branch_list
->far_label
4117 && ! --LABEL_NUSES (far_branch_list
->far_label
))
4118 delete_insn (far_branch_list
->far_label
);
4119 far_branch_list
= far_branch_list
->prev
;
4122 /* Instruction length information is no longer valid due to the new
4123 instructions that have been generated. */
4124 init_insn_lengths ();
4127 /* Dump out instruction addresses, which is useful for debugging the
4128 constant pool table stuff.
4130 If relaxing, output the label and pseudo-ops used to link together
4131 calls and the instruction which set the registers. */
4133 /* ??? This is unnecessary, and probably should be deleted. This makes
4134 the insn_addresses declaration above unnecessary. */
4136 /* ??? The addresses printed by this routine for insns are nonsense for
4137 insns which are inside of a sequence where none of the inner insns have
4138 variable length. This is because the second pass of shorten_branches
4139 does not bother to update them. */
4142 final_prescan_insn (insn
, opvec
, noperands
)
4144 rtx
*opvec ATTRIBUTE_UNUSED
;
4145 int noperands ATTRIBUTE_UNUSED
;
4147 if (TARGET_DUMPISIZE
)
4148 fprintf (asm_out_file
, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn
)));
4154 note
= find_reg_note (insn
, REG_LABEL
, NULL_RTX
);
4159 pattern
= PATTERN (insn
);
4160 if (GET_CODE (pattern
) == PARALLEL
)
4161 pattern
= XVECEXP (pattern
, 0, 0);
4162 if (GET_CODE (pattern
) == CALL
4163 || (GET_CODE (pattern
) == SET
4164 && (GET_CODE (SET_SRC (pattern
)) == CALL
4165 || get_attr_type (insn
) == TYPE_SFUNC
)))
4166 asm_fprintf (asm_out_file
, "\t.uses %LL%d\n",
4167 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4168 else if (GET_CODE (pattern
) == SET
)
4169 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4170 CODE_LABEL_NUMBER (XEXP (note
, 0)));
4177 /* Dump out any constants accumulated in the final pass. These will
4181 output_jump_label_table ()
4187 fprintf (asm_out_file
, "\t.align 2\n");
4188 for (i
= 0; i
< pool_size
; i
++)
4190 pool_node
*p
= &pool_vector
[i
];
4192 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L",
4193 CODE_LABEL_NUMBER (p
->label
));
4194 output_asm_insn (".long %O0", &p
->value
);
4202 /* A full frame looks like:
4206 [ if current_function_anonymous_args
4219 local-0 <- fp points here. */
4221 /* Number of bytes pushed for anonymous args, used to pass information
4222 between expand_prologue and expand_epilogue. */
4224 static int extra_push
;
4226 /* Adjust the stack by SIZE bytes. REG holds the rtl of the register
4227 to be adjusted, and TEMP, if nonnegative, holds the register number
4228 of a general register that we may clobber. */
4231 output_stack_adjust (size
, reg
, temp
, emit_fn
)
4235 rtx (*emit_fn
) PARAMS ((rtx
));
4239 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4244 if (CONST_OK_FOR_ADD (size
))
4245 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
)));
4246 /* Try to do it with two partial adjustments; however, we must make
4247 sure that the stack is properly aligned at all times, in case
4248 an interrupt occurs between the two partial adjustments. */
4249 else if (CONST_OK_FOR_ADD (size
/ 2 & -align
)
4250 && CONST_OK_FOR_ADD (size
- (size
/ 2 & -align
)))
4252 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
/ 2 & -align
)));
4253 emit_fn (GEN_ADD3 (reg
, reg
, GEN_INT (size
- (size
/ 2 & -align
))));
4260 /* If TEMP is invalid, we could temporarily save a general
4261 register to MACL. However, there is currently no need
4262 to handle this case, so just abort when we see it. */
4265 const_reg
= gen_rtx_REG (GET_MODE (reg
), temp
);
4267 /* If SIZE is negative, subtract the positive value.
4268 This sometimes allows a constant pool entry to be shared
4269 between prologue and epilogue code. */
4272 emit_insn (GEN_MOV (const_reg
, GEN_INT (-size
)));
4273 insn
= emit_fn (GEN_SUB3 (reg
, reg
, const_reg
));
4277 emit_insn (GEN_MOV (const_reg
, GEN_INT (size
)));
4278 insn
= emit_fn (GEN_ADD3 (reg
, reg
, const_reg
));
4280 if (emit_fn
== frame_insn
)
4282 = (gen_rtx_EXPR_LIST
4283 (REG_FRAME_RELATED_EXPR
,
4284 gen_rtx_SET (VOIDmode
, reg
,
4285 gen_rtx_PLUS (SImode
, reg
, GEN_INT (size
))),
4296 RTX_FRAME_RELATED_P (x
) = 1;
4300 /* Output RTL to push register RN onto the stack. */
4308 x
= gen_push_fpul ();
4309 else if (rn
== FPSCR_REG
)
4310 x
= gen_push_fpscr ();
4311 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4312 && FP_OR_XD_REGISTER_P (rn
))
4314 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4316 x
= gen_push_4 (gen_rtx_REG (DFmode
, rn
));
4318 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
4319 x
= gen_push_e (gen_rtx_REG (SFmode
, rn
));
4321 x
= gen_push (gen_rtx_REG (SImode
, rn
));
4325 = gen_rtx_EXPR_LIST (REG_INC
,
4326 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4330 /* Output RTL to pop register RN from the stack. */
4338 x
= gen_pop_fpul ();
4339 else if (rn
== FPSCR_REG
)
4340 x
= gen_pop_fpscr ();
4341 else if (TARGET_SH4
&& TARGET_FMOVD
&& ! TARGET_FPU_SINGLE
4342 && FP_OR_XD_REGISTER_P (rn
))
4344 if (FP_REGISTER_P (rn
) && (rn
- FIRST_FP_REG
) & 1)
4346 x
= gen_pop_4 (gen_rtx_REG (DFmode
, rn
));
4348 else if (TARGET_SH3E
&& FP_REGISTER_P (rn
))
4349 x
= gen_pop_e (gen_rtx_REG (SFmode
, rn
));
4351 x
= gen_pop (gen_rtx_REG (SImode
, rn
));
4355 = gen_rtx_EXPR_LIST (REG_INC
,
4356 gen_rtx_REG (SImode
, STACK_POINTER_REGNUM
), 0);
4359 /* Generate code to push the regs specified in the mask. */
4363 HOST_WIDE_INT
*mask
;
4367 /* Push PR last; this gives better latencies after the prologue, and
4368 candidates for the return delay slot when there are no general
4369 registers pushed. */
4370 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4371 if (i
!= PR_REG
&& mask
[i
/ 32] & (1 << (i
% 32)))
4373 if (mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
4377 /* Work out the registers which need to be saved, both as a mask and a
4378 count of saved words.
4380 If doing a pragma interrupt function, then push all regs used by the
4381 function, and if we call another function (we can tell by looking at PR),
4382 make sure that all the regs it clobbers are safe too. */
4385 calc_live_regs (count_ptr
, live_regs_mask
)
4387 HOST_WIDE_INT
*live_regs_mask
;
4391 int interrupt_handler
;
4394 interrupt_handler
= sh_cfun_interrupt_handler_p ();
4396 for (count
= 0; 32 * count
< FIRST_PSEUDO_REGISTER
; count
++)
4397 live_regs_mask
[count
] = 0;
4398 /* If we can save a lot of saves by switching to double mode, do that. */
4399 if (TARGET_SH4
&& TARGET_FMOVD
&& TARGET_FPU_SINGLE
)
4400 for (count
= 0, reg
= FIRST_FP_REG
; reg
<= LAST_FP_REG
; reg
+= 2)
4401 if (regs_ever_live
[reg
] && regs_ever_live
[reg
+1]
4402 && (! call_used_regs
[reg
] || (interrupt_handler
&& ! pragma_trapa
))
4405 target_flags
&= ~FPU_SINGLE_BIT
;
4408 /* PR_MEDIA_REG is a general purpose register, thus global_alloc already
4409 knows how to use it. That means the pseudo originally allocated for
4410 the initial value can become the PR_MEDIA_REG hard register, as seen for
4411 execute/20010122-1.c:test9. */
4413 pr_live
= regs_ever_live
[PR_MEDIA_REG
];
4416 rtx pr_initial
= has_hard_reg_initial_val (Pmode
, PR_REG
);
4417 pr_live
= (pr_initial
4418 ? REGNO (pr_initial
) != (PR_REG
) : regs_ever_live
[PR_REG
]);
4420 /* Force PR to be live if the prologue has to call the SHmedia
4421 argument decoder or register saver. */
4422 if (TARGET_SHCOMPACT
4423 && ((current_function_args_info
.call_cookie
4424 & ~ CALL_COOKIE_RET_TRAMP (1))
4425 || current_function_has_nonlocal_label
))
4427 for (count
= 0, reg
= FIRST_PSEUDO_REGISTER
- 1; reg
>= 0; reg
--)
4429 if (reg
== (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
)
4431 : (interrupt_handler
&& ! pragma_trapa
)
4432 ? (/* Need to save all the regs ever live. */
4433 (regs_ever_live
[reg
]
4434 || (call_used_regs
[reg
]
4435 && (! fixed_regs
[reg
] || reg
== MACH_REG
|| reg
== MACL_REG
)
4437 && reg
!= STACK_POINTER_REGNUM
&& reg
!= ARG_POINTER_REGNUM
4438 && reg
!= RETURN_ADDRESS_POINTER_REGNUM
4439 && reg
!= T_REG
&& reg
!= GBR_REG
4440 /* Push fpscr only on targets which have FPU */
4441 && (reg
!= FPSCR_REG
|| TARGET_FPU_ANY
))
4442 : (/* Only push those regs which are used and need to be saved. */
4445 && current_function_args_info
.call_cookie
4446 && reg
== PIC_OFFSET_TABLE_REGNUM
)
4447 || (regs_ever_live
[reg
] && ! call_used_regs
[reg
])))
4449 live_regs_mask
[reg
/ 32] |= 1 << (reg
% 32);
4450 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
));
4452 if ((TARGET_SH4
|| TARGET_SH5
) && TARGET_FMOVD
4453 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg
)) == MODE_FLOAT
)
4455 if (FP_REGISTER_P (reg
))
4457 if (! TARGET_FPU_SINGLE
&& ! regs_ever_live
[reg
^ 1])
4459 live_regs_mask
[(reg
^ 1) / 32] |= 1 << ((reg
^ 1) % 32);
4460 count
+= GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg
^ 1));
4463 else if (XD_REGISTER_P (reg
))
4465 /* Must switch to double mode to access these registers. */
4466 target_flags
&= ~FPU_SINGLE_BIT
;
4475 /* Code to generate prologue and epilogue sequences */
4477 /* PUSHED is the number of bytes that are bing pushed on the
4478 stack for register saves. Return the frame size, padded
4479 appropriately so that the stack stays properly aligned. */
4480 static HOST_WIDE_INT
4481 rounded_frame_size (pushed
)
4484 HOST_WIDE_INT size
= get_frame_size ();
4485 HOST_WIDE_INT align
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
4487 return ((size
+ pushed
+ align
- 1) & -align
) - pushed
;
4490 /* Choose a call-clobbered target-branch register that remains
4491 unchanged along the whole function. We set it up as the return
4492 value in the prologue. */
4494 sh_media_register_for_return ()
4499 if (! current_function_is_leaf
)
4502 tr0_used
= flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
];
4504 for (regno
= FIRST_TARGET_REG
+ tr0_used
; regno
<= LAST_TARGET_REG
; regno
++)
4505 if (call_used_regs
[regno
] && ! regs_ever_live
[regno
])
4512 sh_expand_prologue ()
4514 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
4517 int save_flags
= target_flags
;
4519 current_function_interrupt
= sh_cfun_interrupt_handler_p ();
4521 /* We have pretend args if we had an object sent partially in registers
4522 and partially on the stack, e.g. a large structure. */
4523 output_stack_adjust (-current_function_pretend_args_size
4524 - current_function_args_info
.stack_regs
* 8,
4525 stack_pointer_rtx
, TARGET_SH5
? 0 : 1, frame_insn
);
4529 if (TARGET_SHCOMPACT
&& flag_pic
&& current_function_args_info
.call_cookie
)
4530 /* We're going to use the PIC register to load the address of the
4531 incoming-argument decoder and/or of the return trampoline from
4532 the GOT, so make sure the PIC register is preserved and
4534 regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
] = 1;
4536 if (TARGET_SHCOMPACT
4537 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
4541 /* First, make all registers with incoming arguments that will
4542 be pushed onto the stack live, so that register renaming
4543 doesn't overwrite them. */
4544 for (reg
= 0; reg
< NPARM_REGS (SImode
); reg
++)
4545 if (CALL_COOKIE_STACKSEQ_GET (current_function_args_info
.call_cookie
)
4546 >= NPARM_REGS (SImode
) - reg
)
4547 for (; reg
< NPARM_REGS (SImode
); reg
++)
4548 emit_insn (gen_shcompact_preserve_incoming_args
4549 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
4550 else if (CALL_COOKIE_INT_REG_GET
4551 (current_function_args_info
.call_cookie
, reg
) == 1)
4552 emit_insn (gen_shcompact_preserve_incoming_args
4553 (gen_rtx_REG (SImode
, FIRST_PARM_REG
+ reg
)));
4555 emit_move_insn (gen_rtx_REG (Pmode
, MACL_REG
),
4557 emit_move_insn (gen_rtx_REG (SImode
, R0_REG
),
4558 GEN_INT (current_function_args_info
.call_cookie
));
4559 emit_move_insn (gen_rtx_REG (SImode
, MACH_REG
),
4560 gen_rtx_REG (SImode
, R0_REG
));
4562 else if (TARGET_SHMEDIA
)
4564 int tr
= sh_media_register_for_return ();
4568 rtx insn
= emit_move_insn (gen_rtx_REG (DImode
, tr
),
4569 gen_rtx_REG (DImode
, PR_MEDIA_REG
));
4571 /* If this function only exits with sibcalls, this copy
4572 will be flagged as dead. */
4573 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4579 /* Emit the code for SETUP_VARARGS. */
4580 if (current_function_stdarg
)
4582 /* This is not used by the SH3E calling convention */
4583 if (TARGET_SH1
&& ! TARGET_SH3E
&& ! TARGET_SH5
&& ! TARGET_HITACHI
)
4585 /* Push arg regs as if they'd been provided by caller in stack. */
4586 for (i
= 0; i
< NPARM_REGS(SImode
); i
++)
4588 int rn
= NPARM_REGS(SImode
) + FIRST_PARM_REG
- i
- 1;
4591 if (i
>= (NPARM_REGS(SImode
)
4592 - current_function_args_info
.arg_count
[(int) SH_ARG_INT
]
4596 RTX_FRAME_RELATED_P (insn
) = 0;
4602 /* If we're supposed to switch stacks at function entry, do so now. */
4604 emit_insn (gen_sp_switch_1 ());
4606 calc_live_regs (&d
, live_regs_mask
);
4607 /* ??? Maybe we could save some switching if we can move a mode switch
4608 that already happens to be at the function start into the prologue. */
4609 if (target_flags
!= save_flags
)
4610 emit_insn (gen_toggle_sz ());
4617 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
4618 int offset_in_r0
= -1;
4621 if (d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
4622 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
4623 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
4625 offset
= d
+ d_rounding
;
4626 output_stack_adjust (-offset
, stack_pointer_rtx
, 1, frame_insn
);
4628 /* We loop twice: first, we save 8-byte aligned registers in the
4629 higher addresses, that are known to be aligned. Then, we
4630 proceed to saving 32-bit registers that don't need 8-byte
4632 for (align
= 1; align
>= 0; align
--)
4633 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
4634 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
4636 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
4638 rtx reg_rtx
, mem_rtx
, pre_dec
= NULL_RTX
;
4640 if (mode
== SFmode
&& (i
% 2) == 1
4641 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
4642 && (live_regs_mask
[(i
^ 1) / 32] & (1 << ((i
^ 1) % 32))))
4649 /* If we're doing the aligned pass and this is not aligned,
4650 or we're doing the unaligned pass and this is aligned,
4652 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
4656 offset
-= GET_MODE_SIZE (mode
);
4658 reg_rtx
= gen_rtx_REG (mode
, reg
);
4660 mem_rtx
= gen_rtx_MEM (mode
,
4661 gen_rtx_PLUS (Pmode
,
4665 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_pre_dec
);
4671 if (HAVE_PRE_DECREMENT
4672 && (offset_in_r0
- offset
== GET_MODE_SIZE (mode
)
4673 || mem_rtx
== NULL_RTX
4674 || i
== PR_REG
|| SPECIAL_REGISTER_P (i
)))
4676 pre_dec
= gen_rtx_MEM (mode
,
4677 gen_rtx_PRE_DEC (Pmode
, r0
));
4679 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (pre_dec
, 0),
4688 offset
+= GET_MODE_SIZE (mode
);
4692 if (mem_rtx
!= NULL_RTX
)
4695 if (offset_in_r0
== -1)
4697 emit_move_insn (r0
, GEN_INT (offset
));
4698 offset_in_r0
= offset
;
4700 else if (offset
!= offset_in_r0
)
4705 GEN_INT (offset
- offset_in_r0
)));
4706 offset_in_r0
+= offset
- offset_in_r0
;
4709 if (pre_dec
!= NULL_RTX
)
4715 (Pmode
, r0
, stack_pointer_rtx
));
4719 offset
-= GET_MODE_SIZE (mode
);
4720 offset_in_r0
-= GET_MODE_SIZE (mode
);
4725 mem_rtx
= gen_rtx_MEM (mode
, r0
);
4727 mem_rtx
= gen_rtx_MEM (mode
,
4728 gen_rtx_PLUS (Pmode
,
4732 /* We must not use an r0-based address for target-branch
4733 registers or for special registers without pre-dec
4734 memory addresses, since we store their values in r0
4736 if (TARGET_REGISTER_P (i
)
4737 || ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4738 && mem_rtx
!= pre_dec
))
4742 if (TARGET_REGISTER_P (i
)
4743 || ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4744 && mem_rtx
!= pre_dec
))
4746 rtx r0mode
= gen_rtx_REG (GET_MODE (reg_rtx
), R0_REG
);
4748 emit_move_insn (r0mode
, reg_rtx
);
4756 emit_move_insn (mem_rtx
, reg_rtx
);
4759 if (offset
!= d_rounding
)
4763 push_regs (live_regs_mask
);
4765 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
4767 rtx insn
= get_last_insn ();
4768 rtx last
= emit_insn (gen_GOTaddr2picreg ());
4770 /* Mark these insns as possibly dead. Sometimes, flow2 may
4771 delete all uses of the PIC register. In this case, let it
4772 delete the initialization too. */
4775 insn
= NEXT_INSN (insn
);
4777 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4781 while (insn
!= last
);
4784 if (SHMEDIA_REGS_STACK_ADJUST ())
4786 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4787 gen_rtx_SYMBOL_REF (Pmode
,
4789 ? "__GCC_push_shmedia_regs"
4790 : "__GCC_push_shmedia_regs_nofpu"));
4791 /* This must NOT go through the PLT, otherwise mach and macl
4792 may be clobbered. */
4793 emit_insn (gen_shmedia_save_restore_regs_compact
4794 (GEN_INT (-SHMEDIA_REGS_STACK_ADJUST ())));
4797 if (target_flags
!= save_flags
)
4799 rtx insn
= emit_insn (gen_toggle_sz ());
4801 /* If we're lucky, a mode switch in the function body will
4802 overwrite fpscr, turning this insn dead. Tell flow this
4803 insn is ok to delete. */
4804 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD
,
4809 target_flags
= save_flags
;
4811 output_stack_adjust (-rounded_frame_size (d
) + d_rounding
,
4812 stack_pointer_rtx
, TARGET_SH5
? 0 : 1, frame_insn
);
4814 if (frame_pointer_needed
)
4815 frame_insn (GEN_MOV (frame_pointer_rtx
, stack_pointer_rtx
));
4817 if (TARGET_SHCOMPACT
4818 && (current_function_args_info
.call_cookie
& ~ CALL_COOKIE_RET_TRAMP(1)))
4820 /* This must NOT go through the PLT, otherwise mach and macl
4821 may be clobbered. */
4822 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4823 gen_rtx_SYMBOL_REF (Pmode
,
4824 "__GCC_shcompact_incoming_args"));
4825 emit_insn (gen_shcompact_incoming_args ());
4830 sh_expand_epilogue ()
4832 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
4836 int save_flags
= target_flags
;
4839 calc_live_regs (&d
, live_regs_mask
);
4841 if (TARGET_SH5
&& d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
4842 d_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
4843 - d
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
4845 frame_size
= rounded_frame_size (d
) - d_rounding
;
4847 if (frame_pointer_needed
)
4849 output_stack_adjust (frame_size
, frame_pointer_rtx
, 7, emit_insn
);
4851 /* We must avoid moving the stack pointer adjustment past code
4852 which reads from the local frame, else an interrupt could
4853 occur after the SP adjustment and clobber data in the local
4855 emit_insn (gen_blockage ());
4856 emit_insn (GEN_MOV (stack_pointer_rtx
, frame_pointer_rtx
));
4858 else if (frame_size
)
4860 /* We must avoid moving the stack pointer adjustment past code
4861 which reads from the local frame, else an interrupt could
4862 occur after the SP adjustment and clobber data in the local
4864 emit_insn (gen_blockage ());
4865 output_stack_adjust (frame_size
, stack_pointer_rtx
, 7, emit_insn
);
4868 if (SHMEDIA_REGS_STACK_ADJUST ())
4870 emit_move_insn (gen_rtx_REG (Pmode
, R0_REG
),
4871 gen_rtx_SYMBOL_REF (Pmode
,
4873 ? "__GCC_pop_shmedia_regs"
4874 : "__GCC_pop_shmedia_regs_nofpu"));
4875 /* This must NOT go through the PLT, otherwise mach and macl
4876 may be clobbered. */
4877 emit_insn (gen_shmedia_save_restore_regs_compact
4878 (GEN_INT (SHMEDIA_REGS_STACK_ADJUST ())));
4881 /* Pop all the registers. */
4883 if (target_flags
!= save_flags
)
4884 emit_insn (gen_toggle_sz ());
4887 int offset
= d_rounding
;
4888 int offset_in_r0
= -1;
4891 rtx r0
= gen_rtx_REG (Pmode
, R0_REG
);
4893 /* We loop twice: first, we save 8-byte aligned registers in the
4894 higher addresses, that are known to be aligned. Then, we
4895 proceed to saving 32-bit registers that don't need 8-byte
4897 for (align
= 0; align
<= 1; align
++)
4898 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4899 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
4901 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
4903 rtx reg_rtx
, mem_rtx
, post_inc
= NULL_RTX
, insn
;
4905 if (mode
== SFmode
&& (i
% 2) == 0
4906 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
4907 && (live_regs_mask
[(i
^ 1) / 32] & (1 << ((i
^ 1) % 32))))
4913 /* If we're doing the aligned pass and this is not aligned,
4914 or we're doing the unaligned pass and this is aligned,
4916 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
4920 reg_rtx
= gen_rtx_REG (mode
, reg
);
4922 mem_rtx
= gen_rtx_MEM (mode
,
4923 gen_rtx_PLUS (Pmode
,
4927 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (mem_rtx
, 0), try_post_inc
);
4933 if (HAVE_POST_INCREMENT
4934 && (offset
== offset_in_r0
4935 || (offset
+ GET_MODE_SIZE (mode
) != d
+ d_rounding
4936 && mem_rtx
== NULL_RTX
)
4937 || i
== PR_REG
|| SPECIAL_REGISTER_P (i
)))
4939 post_inc
= gen_rtx_MEM (mode
,
4940 gen_rtx_POST_INC (Pmode
, r0
));
4942 GO_IF_LEGITIMATE_ADDRESS (mode
, XEXP (post_inc
, 0),
4945 post_inc
= NULL_RTX
;
4954 if (mem_rtx
!= NULL_RTX
)
4957 if (offset_in_r0
== -1)
4959 emit_move_insn (r0
, GEN_INT (offset
));
4960 offset_in_r0
= offset
;
4962 else if (offset
!= offset_in_r0
)
4967 GEN_INT (offset
- offset_in_r0
)));
4968 offset_in_r0
+= offset
- offset_in_r0
;
4971 if (post_inc
!= NULL_RTX
)
4977 (Pmode
, r0
, stack_pointer_rtx
));
4983 offset_in_r0
+= GET_MODE_SIZE (mode
);
4986 mem_rtx
= gen_rtx_MEM (mode
, r0
);
4988 mem_rtx
= gen_rtx_MEM (mode
,
4989 gen_rtx_PLUS (Pmode
,
4993 if ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4994 && mem_rtx
!= post_inc
)
4998 if ((i
== PR_REG
|| SPECIAL_REGISTER_P (i
))
4999 && mem_rtx
!= post_inc
)
5001 insn
= emit_move_insn (r0
, mem_rtx
);
5004 else if (TARGET_REGISTER_P (i
))
5006 rtx r1
= gen_rtx_REG (mode
, R1_REG
);
5008 insn
= emit_move_insn (r1
, mem_rtx
);
5012 insn
= emit_move_insn (reg_rtx
, mem_rtx
);
5014 offset
+= GET_MODE_SIZE (mode
);
5017 if (offset
!= d
+ d_rounding
)
5024 if (live_regs_mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
5026 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5028 int j
= (FIRST_PSEUDO_REGISTER
- 1) - i
;
5030 if (j
!= PR_REG
&& live_regs_mask
[j
/ 32] & (1 << (j
% 32)))
5034 if (target_flags
!= save_flags
)
5035 emit_insn (gen_toggle_sz ());
5036 target_flags
= save_flags
;
5038 output_stack_adjust (extra_push
+ current_function_pretend_args_size
5040 + current_function_args_info
.stack_regs
* 8,
5041 stack_pointer_rtx
, 7, emit_insn
);
5043 /* Switch back to the normal stack if necessary. */
5045 emit_insn (gen_sp_switch_2 ());
5047 /* Tell flow the insn that pops PR isn't dead. */
5048 /* PR_REG will never be live in SHmedia mode, and we don't need to
5049 USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
5050 by the return pattern. */
5051 if (live_regs_mask
[PR_REG
/ 32] & (1 << (PR_REG
% 32)))
5052 emit_insn (gen_rtx_USE (VOIDmode
, gen_rtx_REG (SImode
, PR_REG
)));
5055 static int sh_need_epilogue_known
= 0;
5060 if (! sh_need_epilogue_known
)
5065 sh_expand_epilogue ();
5066 epilogue
= get_insns ();
5068 sh_need_epilogue_known
= (epilogue
== NULL
? -1 : 1);
5070 return sh_need_epilogue_known
> 0;
5073 /* Clear variables at function end. */
5076 sh_output_function_epilogue (file
, size
)
5077 FILE *file ATTRIBUTE_UNUSED
;
5078 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
5080 trap_exit
= pragma_interrupt
= pragma_trapa
= pragma_nosave_low_regs
= 0;
5081 sh_need_epilogue_known
= 0;
5082 sp_switch
= NULL_RTX
;
5086 sh_builtin_saveregs ()
5088 /* First unnamed integer register. */
5089 int first_intreg
= current_function_args_info
.arg_count
[(int) SH_ARG_INT
];
5090 /* Number of integer registers we need to save. */
5091 int n_intregs
= MAX (0, NPARM_REGS (SImode
) - first_intreg
);
5092 /* First unnamed SFmode float reg */
5093 int first_floatreg
= current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
5094 /* Number of SFmode float regs to save. */
5095 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
5098 HOST_WIDE_INT alias_set
;
5104 int pushregs
= n_intregs
;
5106 while (pushregs
< NPARM_REGS (SImode
) - 1
5107 && (CALL_COOKIE_INT_REG_GET
5108 (current_function_args_info
.call_cookie
,
5109 NPARM_REGS (SImode
) - pushregs
)
5112 current_function_args_info
.call_cookie
5113 &= ~ CALL_COOKIE_INT_REG (NPARM_REGS (SImode
)
5118 if (pushregs
== NPARM_REGS (SImode
))
5119 current_function_args_info
.call_cookie
5120 |= (CALL_COOKIE_INT_REG (0, 1)
5121 | CALL_COOKIE_STACKSEQ (pushregs
- 1));
5123 current_function_args_info
.call_cookie
5124 |= CALL_COOKIE_STACKSEQ (pushregs
);
5126 current_function_pretend_args_size
+= 8 * n_intregs
;
5128 if (TARGET_SHCOMPACT
)
5132 if (! TARGET_SH3E
&& ! TARGET_SH4
&& ! TARGET_SH5
)
5134 error ("__builtin_saveregs not supported by this subtarget");
5141 /* Allocate block of memory for the regs. */
5142 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
5143 Or can assign_stack_local accept a 0 SIZE argument? */
5144 bufsize
= (n_intregs
* UNITS_PER_WORD
) + (n_floatregs
* UNITS_PER_WORD
);
5147 regbuf
= gen_rtx_MEM (BLKmode
,
5148 gen_rtx_REG (Pmode
, ARG_POINTER_REGNUM
));
5149 else if (n_floatregs
& 1)
5153 regbuf
= assign_stack_local (BLKmode
, bufsize
+ UNITS_PER_WORD
, 0);
5154 addr
= copy_to_mode_reg (Pmode
, XEXP (regbuf
, 0));
5155 emit_insn (gen_iorsi3 (addr
, addr
, GEN_INT (UNITS_PER_WORD
)));
5156 regbuf
= change_address (regbuf
, BLKmode
, addr
);
5159 regbuf
= assign_stack_local (BLKmode
, bufsize
, 0);
5160 alias_set
= get_varargs_alias_set ();
5161 set_mem_alias_set (regbuf
, alias_set
);
5164 This is optimized to only save the regs that are necessary. Explicitly
5165 named args need not be saved. */
5167 move_block_from_reg (BASE_ARG_REG (SImode
) + first_intreg
,
5168 adjust_address (regbuf
, BLKmode
,
5169 n_floatregs
* UNITS_PER_WORD
),
5170 n_intregs
, n_intregs
* UNITS_PER_WORD
);
5173 /* Return the address of the regbuf. */
5174 return XEXP (regbuf
, 0);
5177 This is optimized to only save the regs that are necessary. Explicitly
5178 named args need not be saved.
5179 We explicitly build a pointer to the buffer because it halves the insn
5180 count when not optimizing (otherwise the pointer is built for each reg
5182 We emit the moves in reverse order so that we can use predecrement. */
5184 fpregs
= gen_reg_rtx (Pmode
);
5185 emit_move_insn (fpregs
, XEXP (regbuf
, 0));
5186 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5187 GEN_INT (n_floatregs
* UNITS_PER_WORD
)));
5191 for (regno
= NPARM_REGS (DFmode
) - 2; regno
>= first_floatreg
; regno
-= 2)
5193 emit_insn (gen_addsi3 (fpregs
, fpregs
,
5194 GEN_INT (-2 * UNITS_PER_WORD
)));
5195 mem
= gen_rtx_MEM (DFmode
, fpregs
);
5196 set_mem_alias_set (mem
, alias_set
);
5197 emit_move_insn (mem
,
5198 gen_rtx (REG
, DFmode
, BASE_ARG_REG (DFmode
) + regno
));
5200 regno
= first_floatreg
;
5203 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5204 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5205 set_mem_alias_set (mem
, alias_set
);
5206 emit_move_insn (mem
,
5207 gen_rtx (REG
, SFmode
, BASE_ARG_REG (SFmode
) + regno
5208 - (TARGET_LITTLE_ENDIAN
!= 0)));
5212 for (regno
= NPARM_REGS (SFmode
) - 1; regno
>= first_floatreg
; regno
--)
5216 emit_insn (gen_addsi3 (fpregs
, fpregs
, GEN_INT (- UNITS_PER_WORD
)));
5217 mem
= gen_rtx_MEM (SFmode
, fpregs
);
5218 set_mem_alias_set (mem
, alias_set
);
5219 emit_move_insn (mem
,
5220 gen_rtx_REG (SFmode
, BASE_ARG_REG (SFmode
) + regno
));
5223 /* Return the address of the regbuf. */
5224 return XEXP (regbuf
, 0);
5227 /* Define the `__builtin_va_list' type for the ABI. */
5232 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5235 if (TARGET_SH5
|| (! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
5236 return ptr_type_node
;
5238 record
= make_node (RECORD_TYPE
);
5240 f_next_o
= build_decl (FIELD_DECL
, get_identifier ("__va_next_o"),
5242 f_next_o_limit
= build_decl (FIELD_DECL
,
5243 get_identifier ("__va_next_o_limit"),
5245 f_next_fp
= build_decl (FIELD_DECL
, get_identifier ("__va_next_fp"),
5247 f_next_fp_limit
= build_decl (FIELD_DECL
,
5248 get_identifier ("__va_next_fp_limit"),
5250 f_next_stack
= build_decl (FIELD_DECL
, get_identifier ("__va_next_stack"),
5253 DECL_FIELD_CONTEXT (f_next_o
) = record
;
5254 DECL_FIELD_CONTEXT (f_next_o_limit
) = record
;
5255 DECL_FIELD_CONTEXT (f_next_fp
) = record
;
5256 DECL_FIELD_CONTEXT (f_next_fp_limit
) = record
;
5257 DECL_FIELD_CONTEXT (f_next_stack
) = record
;
5259 TYPE_FIELDS (record
) = f_next_o
;
5260 TREE_CHAIN (f_next_o
) = f_next_o_limit
;
5261 TREE_CHAIN (f_next_o_limit
) = f_next_fp
;
5262 TREE_CHAIN (f_next_fp
) = f_next_fp_limit
;
5263 TREE_CHAIN (f_next_fp_limit
) = f_next_stack
;
5265 layout_type (record
);
5270 /* Implement `va_start' for varargs and stdarg. */
5273 sh_va_start (valist
, nextarg
)
5277 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5278 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
5284 expand_builtin_saveregs ();
5285 std_expand_builtin_va_start (valist
, nextarg
);
5289 if ((! TARGET_SH3E
&& ! TARGET_SH4
) || TARGET_HITACHI
)
5291 std_expand_builtin_va_start (valist
, nextarg
);
5295 f_next_o
= TYPE_FIELDS (va_list_type_node
);
5296 f_next_o_limit
= TREE_CHAIN (f_next_o
);
5297 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
5298 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
5299 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
5301 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
5302 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
5303 valist
, f_next_o_limit
);
5304 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
), valist
, f_next_fp
);
5305 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
5306 valist
, f_next_fp_limit
);
5307 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
5308 valist
, f_next_stack
);
5310 /* Call __builtin_saveregs. */
5311 u
= make_tree (ptr_type_node
, expand_builtin_saveregs ());
5312 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, u
);
5313 TREE_SIDE_EFFECTS (t
) = 1;
5314 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5316 nfp
= current_function_args_info
.arg_count
[SH_ARG_FLOAT
];
5321 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5322 build_int_2 (UNITS_PER_WORD
* nfp
, 0)));
5323 t
= build (MODIFY_EXPR
, ptr_type_node
, next_fp_limit
, u
);
5324 TREE_SIDE_EFFECTS (t
) = 1;
5325 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5327 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, u
);
5328 TREE_SIDE_EFFECTS (t
) = 1;
5329 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5331 nint
= current_function_args_info
.arg_count
[SH_ARG_INT
];
5336 u
= fold (build (PLUS_EXPR
, ptr_type_node
, u
,
5337 build_int_2 (UNITS_PER_WORD
* nint
, 0)));
5338 t
= build (MODIFY_EXPR
, ptr_type_node
, next_o_limit
, u
);
5339 TREE_SIDE_EFFECTS (t
) = 1;
5340 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5342 u
= make_tree (ptr_type_node
, nextarg
);
5343 t
= build (MODIFY_EXPR
, ptr_type_node
, next_stack
, u
);
5344 TREE_SIDE_EFFECTS (t
) = 1;
5345 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5348 /* Implement `va_arg'. */
5351 sh_va_arg (valist
, type
)
5354 HOST_WIDE_INT size
, rsize
;
5355 tree tmp
, pptr_type_node
;
5358 int pass_by_ref
= MUST_PASS_IN_STACK (TYPE_MODE (type
), type
);
5360 size
= int_size_in_bytes (type
);
5361 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5362 pptr_type_node
= build_pointer_type (ptr_type_node
);
5365 type
= build_pointer_type (type
);
5367 if (! TARGET_SH5
&& (TARGET_SH3E
|| TARGET_SH4
) && ! TARGET_HITACHI
)
5369 tree f_next_o
, f_next_o_limit
, f_next_fp
, f_next_fp_limit
, f_next_stack
;
5370 tree next_o
, next_o_limit
, next_fp
, next_fp_limit
, next_stack
;
5372 rtx lab_false
, lab_over
;
5374 f_next_o
= TYPE_FIELDS (va_list_type_node
);
5375 f_next_o_limit
= TREE_CHAIN (f_next_o
);
5376 f_next_fp
= TREE_CHAIN (f_next_o_limit
);
5377 f_next_fp_limit
= TREE_CHAIN (f_next_fp
);
5378 f_next_stack
= TREE_CHAIN (f_next_fp_limit
);
5380 next_o
= build (COMPONENT_REF
, TREE_TYPE (f_next_o
), valist
, f_next_o
);
5381 next_o_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_o_limit
),
5382 valist
, f_next_o_limit
);
5383 next_fp
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp
),
5385 next_fp_limit
= build (COMPONENT_REF
, TREE_TYPE (f_next_fp_limit
),
5386 valist
, f_next_fp_limit
);
5387 next_stack
= build (COMPONENT_REF
, TREE_TYPE (f_next_stack
),
5388 valist
, f_next_stack
);
5392 pass_as_float
= ((TREE_CODE (type
) == REAL_TYPE
&& size
<= 8)
5393 || (TREE_CODE (type
) == COMPLEX_TYPE
5394 && TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
5399 pass_as_float
= (TREE_CODE (type
) == REAL_TYPE
&& size
== 4);
5402 addr_rtx
= gen_reg_rtx (Pmode
);
5403 lab_false
= gen_label_rtx ();
5404 lab_over
= gen_label_rtx ();
5409 = current_function_args_info
.arg_count
[(int) SH_ARG_FLOAT
];
5410 int n_floatregs
= MAX (0, NPARM_REGS (SFmode
) - first_floatreg
);
5412 emit_cmp_and_jump_insns (expand_expr (next_fp
, NULL_RTX
, Pmode
,
5414 expand_expr (next_fp_limit
, NULL_RTX
,
5415 Pmode
, EXPAND_NORMAL
),
5416 GE
, const1_rtx
, Pmode
, 1, lab_false
);
5418 if (TYPE_ALIGN (type
) > BITS_PER_WORD
5419 || (((TREE_CODE (type
) == REAL_TYPE
&& size
== 8) || size
== 16)
5420 && (n_floatregs
& 1)))
5422 tmp
= build (BIT_AND_EXPR
, ptr_type_node
, next_fp
,
5423 build_int_2 (UNITS_PER_WORD
, 0));
5424 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_fp
, tmp
);
5425 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_fp
, tmp
);
5426 TREE_SIDE_EFFECTS (tmp
) = 1;
5427 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5430 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_fp
);
5431 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5433 emit_move_insn (addr_rtx
, r
);
5435 emit_jump_insn (gen_jump (lab_over
));
5437 emit_label (lab_false
);
5439 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
5440 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5442 emit_move_insn (addr_rtx
, r
);
5446 tmp
= build (PLUS_EXPR
, ptr_type_node
, next_o
,
5447 build_int_2 (rsize
, 0));
5449 emit_cmp_and_jump_insns (expand_expr (tmp
, NULL_RTX
, Pmode
,
5451 expand_expr (next_o_limit
, NULL_RTX
,
5452 Pmode
, EXPAND_NORMAL
),
5453 GT
, const1_rtx
, Pmode
, 1, lab_false
);
5455 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_o
);
5456 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5458 emit_move_insn (addr_rtx
, r
);
5460 emit_jump_insn (gen_jump (lab_over
));
5462 emit_label (lab_false
);
5464 if (size
> 4 && ! TARGET_SH4
)
5466 tmp
= build (MODIFY_EXPR
, ptr_type_node
, next_o
, next_o_limit
);
5467 TREE_SIDE_EFFECTS (tmp
) = 1;
5468 expand_expr (tmp
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5471 tmp
= build1 (ADDR_EXPR
, pptr_type_node
, next_stack
);
5472 r
= expand_expr (tmp
, addr_rtx
, Pmode
, EXPAND_NORMAL
);
5474 emit_move_insn (addr_rtx
, r
);
5477 emit_label (lab_over
);
5479 tmp
= make_tree (pptr_type_node
, addr_rtx
);
5480 valist
= build1 (INDIRECT_REF
, ptr_type_node
, tmp
);
5483 /* ??? In va-sh.h, there had been code to make values larger than
5484 size 8 indirect. This does not match the FUNCTION_ARG macros. */
5486 result
= std_expand_builtin_va_arg (valist
, type
);
5489 #ifdef POINTERS_EXTEND_UNSIGNED
5490 if (GET_MODE (addr
) != Pmode
)
5491 addr
= convert_memory_address (Pmode
, result
);
5493 result
= gen_rtx_MEM (ptr_mode
, force_reg (Pmode
, result
));
5494 set_mem_alias_set (result
, get_varargs_alias_set ());
5496 /* ??? expand_builtin_va_arg will also set the alias set of the dereferenced
5497 argument to the varargs alias set. */
5501 /* Define the offset between two registers, one to be eliminated, and
5502 the other its replacement, at the start of a routine. */
5505 initial_elimination_offset (from
, to
)
5510 int regs_saved_rounding
= 0;
5511 int total_saved_regs_space
;
5512 int total_auto_space
;
5513 int save_flags
= target_flags
;
5516 HOST_WIDE_INT live_regs_mask
[(FIRST_PSEUDO_REGISTER
+ 31) / 32];
5517 calc_live_regs (®s_saved
, live_regs_mask
);
5518 regs_saved
+= SHMEDIA_REGS_STACK_ADJUST ();
5519 if (TARGET_SH5
&& regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
))
5520 regs_saved_rounding
= ((STACK_BOUNDARY
/ BITS_PER_UNIT
)
5521 - regs_saved
% (STACK_BOUNDARY
/ BITS_PER_UNIT
));
5523 total_auto_space
= rounded_frame_size (regs_saved
) - regs_saved_rounding
;
5524 copy_flags
= target_flags
;
5525 target_flags
= save_flags
;
5527 total_saved_regs_space
= regs_saved
+ regs_saved_rounding
;
5529 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
5530 return total_saved_regs_space
+ total_auto_space
5531 + current_function_args_info
.byref_regs
* 8;
5533 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5534 return total_saved_regs_space
+ total_auto_space
5535 + current_function_args_info
.byref_regs
* 8;
5537 /* Initial gap between fp and sp is 0. */
5538 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
5541 if (from
== RETURN_ADDRESS_POINTER_REGNUM
5542 && (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
))
5546 int i
, n
= total_saved_regs_space
;
5548 int pr_reg
= TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
;
5550 n
+= total_auto_space
;
5552 /* If it wasn't saved, there's not much we can do. */
5553 if ((live_regs_mask
[pr_reg
/ 32] & (1 << (pr_reg
% 32))) == 0)
5556 target_flags
= copy_flags
;
5558 /* We loop twice: first, check 8-byte aligned registers,
5559 that are stored in the higher addresses, that are known
5560 to be aligned. Then, check 32-bit registers that don't
5561 need 8-byte alignment. */
5562 for (align
= 1; align
>= 0; align
--)
5563 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
5564 if (live_regs_mask
[i
/32] & (1 << (i
% 32)))
5566 enum machine_mode mode
= REGISTER_NATURAL_MODE (i
);
5568 if (mode
== SFmode
&& (i
% 2) == 1
5569 && ! TARGET_FPU_SINGLE
&& FP_REGISTER_P (i
)
5570 && (live_regs_mask
[(i
^ 1) / 32]
5571 & (1 << ((i
^ 1) % 32))))
5577 /* If we're doing the aligned pass and this is not aligned,
5578 or we're doing the unaligned pass and this is aligned,
5580 if ((GET_MODE_SIZE (mode
) % (STACK_BOUNDARY
/ BITS_PER_UNIT
)
5584 n
-= GET_MODE_SIZE (mode
);
5588 target_flags
= save_flags
;
5596 return total_auto_space
;
5602 /* Handle machine specific pragmas to be semi-compatible with Hitachi
5606 sh_pr_interrupt (pfile
)
5607 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5609 pragma_interrupt
= 1;
5614 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5616 pragma_interrupt
= pragma_trapa
= 1;
5620 sh_pr_nosave_low_regs (pfile
)
5621 cpp_reader
*pfile ATTRIBUTE_UNUSED
;
5623 pragma_nosave_low_regs
= 1;
5626 /* Generate 'handle_interrupt' attribute for decls */
5629 sh_insert_attributes (node
, attributes
)
5633 if (! pragma_interrupt
5634 || TREE_CODE (node
) != FUNCTION_DECL
)
5637 /* We are only interested in fields. */
5638 if (TREE_CODE_CLASS (TREE_CODE (node
)) != 'd')
5641 /* Add a 'handle_interrupt' attribute. */
5642 * attributes
= tree_cons (get_identifier ("interrupt_handler"), NULL
, * attributes
);
5647 /* Supported attributes:
5649 interrupt_handler -- specifies this function is an interrupt handler.
5651 sp_switch -- specifies an alternate stack for an interrupt handler
5654 trap_exit -- use a trapa to exit an interrupt function instead of
5655 an rte instruction. */
5657 const struct attribute_spec sh_attribute_table
[] =
5659 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
5660 { "interrupt_handler", 0, 0, true, false, false, sh_handle_interrupt_handler_attribute
},
5661 { "sp_switch", 1, 1, true, false, false, sh_handle_sp_switch_attribute
},
5662 { "trap_exit", 1, 1, true, false, false, sh_handle_trap_exit_attribute
},
5663 { NULL
, 0, 0, false, false, false, NULL
}
5666 /* Handle an "interrupt_handler" attribute; arguments as in
5667 struct attribute_spec.handler. */
5669 sh_handle_interrupt_handler_attribute (node
, name
, args
, flags
, no_add_attrs
)
5672 tree args ATTRIBUTE_UNUSED
;
5673 int flags ATTRIBUTE_UNUSED
;
5676 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5678 warning ("`%s' attribute only applies to functions",
5679 IDENTIFIER_POINTER (name
));
5680 *no_add_attrs
= true;
5682 else if (TARGET_SHCOMPACT
)
5684 error ("attribute interrupt_handler is not compatible with -m5-compact");
5685 *no_add_attrs
= true;
5691 /* Handle an "sp_switch" attribute; arguments as in
5692 struct attribute_spec.handler. */
5694 sh_handle_sp_switch_attribute (node
, name
, args
, flags
, no_add_attrs
)
5698 int flags ATTRIBUTE_UNUSED
;
5701 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5703 warning ("`%s' attribute only applies to functions",
5704 IDENTIFIER_POINTER (name
));
5705 *no_add_attrs
= true;
5707 else if (!pragma_interrupt
)
5709 /* The sp_switch attribute only has meaning for interrupt functions. */
5710 warning ("`%s' attribute only applies to interrupt functions",
5711 IDENTIFIER_POINTER (name
));
5712 *no_add_attrs
= true;
5714 else if (TREE_CODE (TREE_VALUE (args
)) != STRING_CST
)
5716 /* The argument must be a constant string. */
5717 warning ("`%s' attribute argument not a string constant",
5718 IDENTIFIER_POINTER (name
));
5719 *no_add_attrs
= true;
5723 sp_switch
= gen_rtx_SYMBOL_REF (VOIDmode
,
5724 TREE_STRING_POINTER (TREE_VALUE (args
)));
5730 /* Handle an "trap_exit" attribute; arguments as in
5731 struct attribute_spec.handler. */
5733 sh_handle_trap_exit_attribute (node
, name
, args
, flags
, no_add_attrs
)
5737 int flags ATTRIBUTE_UNUSED
;
5740 if (TREE_CODE (*node
) != FUNCTION_DECL
)
5742 warning ("`%s' attribute only applies to functions",
5743 IDENTIFIER_POINTER (name
));
5744 *no_add_attrs
= true;
5746 else if (!pragma_interrupt
)
5748 /* The trap_exit attribute only has meaning for interrupt functions. */
5749 warning ("`%s' attribute only applies to interrupt functions",
5750 IDENTIFIER_POINTER (name
));
5751 *no_add_attrs
= true;
5753 else if (TREE_CODE (TREE_VALUE (args
)) != INTEGER_CST
)
5755 /* The argument must be a constant integer. */
5756 warning ("`%s' attribute argument not an integer constant",
5757 IDENTIFIER_POINTER (name
));
5758 *no_add_attrs
= true;
5762 trap_exit
= TREE_INT_CST_LOW (TREE_VALUE (args
));
5769 sh_cfun_interrupt_handler_p ()
5771 return (lookup_attribute ("interrupt_handler",
5772 DECL_ATTRIBUTES (current_function_decl
))
5776 /* Predicates used by the templates. */
5778 /* Returns 1 if OP is MACL, MACH or PR. The input must be a REG rtx.
5779 Used only in general_movsrc_operand. */
5782 system_reg_operand (op
, mode
)
5784 enum machine_mode mode ATTRIBUTE_UNUSED
;
5796 /* Returns 1 if OP can be source of a simple move operation.
5797 Same as general_operand, but a LABEL_REF is valid, PRE_DEC is
5798 invalid as are subregs of system registers. */
5801 general_movsrc_operand (op
, mode
)
5803 enum machine_mode mode
;
5805 if (GET_CODE (op
) == MEM
)
5807 rtx inside
= XEXP (op
, 0);
5808 if (GET_CODE (inside
) == CONST
)
5809 inside
= XEXP (inside
, 0);
5811 if (GET_CODE (inside
) == LABEL_REF
)
5814 if (GET_CODE (inside
) == PLUS
5815 && GET_CODE (XEXP (inside
, 0)) == LABEL_REF
5816 && GET_CODE (XEXP (inside
, 1)) == CONST_INT
)
5819 /* Only post inc allowed. */
5820 if (GET_CODE (inside
) == PRE_DEC
)
5824 if ((mode
== QImode
|| mode
== HImode
)
5825 && (GET_CODE (op
) == SUBREG
5826 && GET_CODE (XEXP (op
, 0)) == REG
5827 && system_reg_operand (XEXP (op
, 0), mode
)))
5830 return general_operand (op
, mode
);
5833 /* Returns 1 if OP can be a destination of a move.
5834 Same as general_operand, but no preinc allowed. */
5837 general_movdst_operand (op
, mode
)
5839 enum machine_mode mode
;
5841 /* Only pre dec allowed. */
5842 if (GET_CODE (op
) == MEM
&& GET_CODE (XEXP (op
, 0)) == POST_INC
)
5845 return general_operand (op
, mode
);
5848 /* Returns 1 if OP is a normal arithmetic register. */
5851 arith_reg_operand (op
, mode
)
5853 enum machine_mode mode
;
5855 if (register_operand (op
, mode
))
5859 if (GET_CODE (op
) == REG
)
5861 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
5862 regno
= REGNO (SUBREG_REG (op
));
5866 return (regno
!= T_REG
&& regno
!= PR_REG
5867 && ! TARGET_REGISTER_P (regno
)
5868 && (regno
!= FPUL_REG
|| TARGET_SH4
)
5869 && regno
!= MACH_REG
&& regno
!= MACL_REG
);
5874 /* Like above, but for DImode destinations: forbid paradoxical DImode subregs,
5875 because this would lead to missing sign extensions when truncating from
5876 DImode to SImode. */
5878 arith_reg_dest (op
, mode
)
5880 enum machine_mode mode
;
5882 if (mode
== DImode
&& GET_CODE (op
) == SUBREG
5883 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))) < 8)
5885 return arith_reg_operand (op
, mode
);
5889 int_gpr_dest (op
, mode
)
5891 enum machine_mode mode ATTRIBUTE_UNUSED
;
5893 enum machine_mode op_mode
= GET_MODE (op
);
5895 if (GET_MODE_CLASS (op_mode
) != MODE_INT
5896 || GET_MODE_SIZE (op_mode
) >= UNITS_PER_WORD
)
5898 if (! reload_completed
)
5900 return true_regnum (op
) <= LAST_GENERAL_REG
;
5904 fp_arith_reg_operand (op
, mode
)
5906 enum machine_mode mode
;
5908 if (register_operand (op
, mode
))
5912 if (GET_CODE (op
) == REG
)
5914 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
5915 regno
= REGNO (SUBREG_REG (op
));
5919 return (regno
>= FIRST_PSEUDO_REGISTER
5920 || FP_REGISTER_P (regno
));
5925 /* Returns 1 if OP is a valid source operand for an arithmetic insn. */
5928 arith_operand (op
, mode
)
5930 enum machine_mode mode
;
5932 if (arith_reg_operand (op
, mode
))
5937 /* FIXME: We should be checking whether the CONST_INT fits in a
5938 CONST_OK_FOR_J here, but this causes reload_cse to crash when
5939 attempting to transform a sequence of two 64-bit sets of the
5940 same register from literal constants into a set and an add,
5941 when the difference is too wide for an add. */
5942 if (GET_CODE (op
) == CONST_INT
5943 || EXTRA_CONSTRAINT_S (op
))
5948 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_I (INTVAL (op
)))
5954 /* Returns 1 if OP is a valid source operand for a compare insn. */
5957 arith_reg_or_0_operand (op
, mode
)
5959 enum machine_mode mode
;
5961 if (arith_reg_operand (op
, mode
))
5964 if (EXTRA_CONSTRAINT_U (op
))
5970 /* Return 1 if OP is a valid source operand for an SHmedia operation
5971 that takes either a register or a 6-bit immediate. */
5974 shmedia_6bit_operand (op
, mode
)
5976 enum machine_mode mode
;
5978 return (arith_reg_operand (op
, mode
)
5979 || (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_O (INTVAL (op
))));
5982 /* Returns 1 if OP is a valid source operand for a logical operation. */
5985 logical_operand (op
, mode
)
5987 enum machine_mode mode
;
5989 if (arith_reg_operand (op
, mode
))
5994 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_P (INTVAL (op
)))
5999 else if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_L (INTVAL (op
)))
6006 and_operand (op
, mode
)
6008 enum machine_mode mode
;
6010 if (logical_operand (op
, mode
))
6013 /* Check mshflo.l / mshflhi.l opportunities. */
6016 && GET_CODE (op
) == CONST_INT
6017 && (INTVAL (op
) == (unsigned) 0xffffffff
6018 || INTVAL (op
) == (HOST_WIDE_INT
) -1 << 32))
6024 /* Nonzero if OP is a floating point value with value 0.0. */
6027 fp_zero_operand (op
)
6032 if (GET_MODE (op
) != SFmode
)
6035 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
6036 return REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
);
6039 /* Nonzero if OP is a floating point value with value 1.0. */
6047 if (GET_MODE (op
) != SFmode
)
6050 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
6051 return REAL_VALUES_EQUAL (r
, dconst1
);
6054 /* For -m4 and -m4-single-only, mode switching is used. If we are
6055 compiling without -mfmovd, movsf_ie isn't taken into account for
6056 mode switching. We could check in machine_dependent_reorg for
6057 cases where we know we are in single precision mode, but there is
6058 interface to find that out during reload, so we must avoid
6059 choosing an fldi alternative during reload and thus failing to
6060 allocate a scratch register for the constant loading. */
6064 return ! TARGET_SH4
|| TARGET_FMOVD
|| reload_completed
;
6068 tertiary_reload_operand (op
, mode
)
6070 enum machine_mode mode ATTRIBUTE_UNUSED
;
6072 enum rtx_code code
= GET_CODE (op
);
6073 return code
== MEM
|| (TARGET_SH4
&& code
== CONST_DOUBLE
);
6077 fpscr_operand (op
, mode
)
6079 enum machine_mode mode ATTRIBUTE_UNUSED
;
6081 return (GET_CODE (op
) == REG
&& REGNO (op
) == FPSCR_REG
6082 && GET_MODE (op
) == PSImode
);
6086 fpul_operand (op
, mode
)
6088 enum machine_mode mode
;
6091 return fp_arith_reg_operand (op
, mode
);
6093 return (GET_CODE (op
) == REG
6094 && (REGNO (op
) == FPUL_REG
|| REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
6095 && GET_MODE (op
) == mode
);
6099 symbol_ref_operand (op
, mode
)
6101 enum machine_mode mode ATTRIBUTE_UNUSED
;
6103 return (GET_CODE (op
) == SYMBOL_REF
);
6107 commutative_float_operator (op
, mode
)
6109 enum machine_mode mode
;
6111 if (GET_MODE (op
) != mode
)
6113 switch (GET_CODE (op
))
6125 noncommutative_float_operator (op
, mode
)
6127 enum machine_mode mode
;
6129 if (GET_MODE (op
) != mode
)
6131 switch (GET_CODE (op
))
6143 unary_float_operator (op
, mode
)
6145 enum machine_mode mode
;
6147 if (GET_MODE (op
) != mode
)
6149 switch (GET_CODE (op
))
6162 binary_float_operator (op
, mode
)
6164 enum machine_mode mode
;
6166 if (GET_MODE (op
) != mode
)
6168 switch (GET_CODE (op
))
6182 binary_logical_operator (op
, mode
)
6184 enum machine_mode mode
;
6186 if (GET_MODE (op
) != mode
)
6188 switch (GET_CODE (op
))
6201 equality_comparison_operator (op
, mode
)
6203 enum machine_mode mode
;
6205 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
6206 && (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
));
6209 int greater_comparison_operator (op
, mode
)
6211 enum machine_mode mode
;
6213 if (mode
!= VOIDmode
&& GET_MODE (op
) == mode
)
6215 switch (GET_CODE (op
))
6227 int less_comparison_operator (op
, mode
)
6229 enum machine_mode mode
;
6231 if (mode
!= VOIDmode
&& GET_MODE (op
) == mode
)
6233 switch (GET_CODE (op
))
6245 /* Accept pseudos and branch target registers. */
6247 target_reg_operand (op
, mode
)
6249 enum machine_mode mode
;
6252 || GET_MODE (op
) != DImode
)
6255 if (GET_CODE (op
) == SUBREG
)
6258 if (GET_CODE (op
) != REG
)
6261 /* We must protect ourselves from matching pseudos that are virtual
6262 register, because they will eventually be replaced with hardware
6263 registers that aren't branch-target registers. */
6264 if (REGNO (op
) > LAST_VIRTUAL_REGISTER
6265 || TARGET_REGISTER_P (REGNO (op
)))
6271 /* Same as target_reg_operand, except that label_refs and symbol_refs
6272 are accepted before reload. */
6274 target_operand (op
, mode
)
6276 enum machine_mode mode
;
6281 if ((GET_MODE (op
) == DImode
|| GET_MODE (op
) == VOIDmode
)
6282 && EXTRA_CONSTRAINT_T (op
))
6283 return ! reload_completed
;
6285 return target_reg_operand (op
, mode
);
6289 mextr_bit_offset (op
, mode
)
6291 enum machine_mode mode ATTRIBUTE_UNUSED
;
6295 if (GET_CODE (op
) != CONST_INT
)
6298 return i
>= 1*8 && i
<= 7*8 && (i
& 7) == 0;
6302 extend_reg_operand (op
, mode
)
6304 enum machine_mode mode
;
6306 return (GET_CODE (op
) == TRUNCATE
6308 : arith_reg_operand
) (op
, mode
);
6312 trunc_hi_operand (op
, mode
)
6314 enum machine_mode mode
;
6316 enum machine_mode op_mode
= GET_MODE (op
);
6318 if (op_mode
!= SImode
&& op_mode
!= DImode
6319 && op_mode
!= V4HImode
&& op_mode
!= V2SImode
)
6321 return extend_reg_operand (op
, mode
);
6325 extend_reg_or_0_operand (op
, mode
)
6327 enum machine_mode mode
;
6329 return (GET_CODE (op
) == TRUNCATE
6331 : arith_reg_or_0_operand
) (op
, mode
);
6335 general_extend_operand (op
, mode
)
6337 enum machine_mode mode
;
6339 return (GET_CODE (op
) == TRUNCATE
6341 : nonimmediate_operand
) (op
, mode
);
6345 inqhi_operand (op
, mode
)
6347 enum machine_mode mode
;
6349 if (GET_CODE (op
) != TRUNCATE
|| mode
!= GET_MODE (op
))
6352 /* Can't use true_regnum here because copy_cost wants to know about
6353 SECONDARY_INPUT_RELOAD_CLASS. */
6354 return GET_CODE (op
) == REG
&& FP_REGISTER_P (REGNO (op
));
6358 sh_rep_vec (v
, mode
)
6360 enum machine_mode mode
;
6365 if ((GET_CODE (v
) != CONST_VECTOR
&& GET_CODE (v
) != PARALLEL
)
6366 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
6368 i
= XVECLEN (v
, 0) - 2;
6369 x
= XVECEXP (v
, 0, i
+ 1);
6370 if (GET_MODE_UNIT_SIZE (mode
) == 1)
6372 y
= XVECEXP (v
, 0, i
);
6373 for (i
-= 2 ; i
>= 0; i
-= 2)
6374 if (! rtx_equal_p (XVECEXP (v
, 0, i
+ 1), x
)
6375 || ! rtx_equal_p (XVECEXP (v
, 0, i
), y
))
6380 if (XVECEXP (v
, 0, i
) != x
)
6385 /* Determine if V is a constant vector matching MODE with only one element
6386 that is not a sign extension. Two byte-sized elements count as one. */
6388 sh_1el_vec (v
, mode
)
6390 enum machine_mode mode
;
6393 int i
, last
, least
, sign_ix
;
6396 if (GET_CODE (v
) != CONST_VECTOR
6397 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
6399 /* Determine numbers of last and of least significat elements. */
6400 last
= XVECLEN (v
, 0) - 1;
6401 least
= TARGET_LITTLE_ENDIAN
? 0 : last
;
6402 if (GET_CODE (XVECEXP (v
, 0, least
)) != CONST_INT
)
6405 if (GET_MODE_UNIT_SIZE (mode
) == 1)
6406 sign_ix
= TARGET_LITTLE_ENDIAN
? 1 : last
- 1;
6407 if (GET_CODE (XVECEXP (v
, 0, sign_ix
)) != CONST_INT
)
6409 unit_size
= GET_MODE_UNIT_SIZE (GET_MODE (v
));
6410 sign
= (INTVAL (XVECEXP (v
, 0, sign_ix
)) >> (unit_size
* BITS_PER_UNIT
- 1)
6411 ? constm1_rtx
: const0_rtx
);
6412 i
= XVECLEN (v
, 0) - 1;
6414 if (i
!= least
&& i
!= sign_ix
&& XVECEXP (v
, 0, i
) != sign
)
6421 sh_const_vec (v
, mode
)
6423 enum machine_mode mode
;
6427 if (GET_CODE (v
) != CONST_VECTOR
6428 || (GET_MODE (v
) != mode
&& mode
!= VOIDmode
))
6430 i
= XVECLEN (v
, 0) - 1;
6432 if (GET_CODE (XVECEXP (v
, 0, i
)) != CONST_INT
)
6437 /* Return the destination address of a branch. */
6440 branch_dest (branch
)
6443 rtx dest
= SET_SRC (PATTERN (branch
));
6446 if (GET_CODE (dest
) == IF_THEN_ELSE
)
6447 dest
= XEXP (dest
, 1);
6448 dest
= XEXP (dest
, 0);
6449 dest_uid
= INSN_UID (dest
);
6450 return INSN_ADDRESSES (dest_uid
);
6453 /* Return nonzero if REG is not used after INSN.
6454 We assume REG is a reload reg, and therefore does
6455 not live past labels. It may live past calls or jumps though. */
6457 reg_unused_after (reg
, insn
)
6464 /* If the reg is set by this instruction, then it is safe for our
6465 case. Disregard the case where this is a store to memory, since
6466 we are checking a register used in the store address. */
6467 set
= single_set (insn
);
6468 if (set
&& GET_CODE (SET_DEST (set
)) != MEM
6469 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6472 while ((insn
= NEXT_INSN (insn
)))
6474 code
= GET_CODE (insn
);
6477 /* If this is a label that existed before reload, then the register
6478 if dead here. However, if this is a label added by reorg, then
6479 the register may still be live here. We can't tell the difference,
6480 so we just ignore labels completely. */
6481 if (code
== CODE_LABEL
)
6486 if (code
== JUMP_INSN
)
6489 /* If this is a sequence, we must handle them all at once.
6490 We could have for instance a call that sets the target register,
6491 and an insn in a delay slot that uses the register. In this case,
6492 we must return 0. */
6493 else if (code
== INSN
&& GET_CODE (PATTERN (insn
)) == SEQUENCE
)
6498 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
6500 rtx this_insn
= XVECEXP (PATTERN (insn
), 0, i
);
6501 rtx set
= single_set (this_insn
);
6503 if (GET_CODE (this_insn
) == CALL_INSN
)
6505 else if (GET_CODE (this_insn
) == JUMP_INSN
)
6507 if (INSN_ANNULLED_BRANCH_P (this_insn
))
6512 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
6514 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6516 if (GET_CODE (SET_DEST (set
)) != MEM
)
6522 && reg_overlap_mentioned_p (reg
, PATTERN (this_insn
)))
6527 else if (code
== JUMP_INSN
)
6530 else if (GET_RTX_CLASS (code
) == 'i')
6532 rtx set
= single_set (insn
);
6534 if (set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
)))
6536 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
6537 return GET_CODE (SET_DEST (set
)) != MEM
;
6538 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
6542 if (code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
6550 static GTY(()) rtx fpscr_rtx
;
6556 fpscr_rtx
= gen_rtx (REG
, PSImode
, FPSCR_REG
);
6557 REG_USERVAR_P (fpscr_rtx
) = 1;
6558 mark_user_reg (fpscr_rtx
);
6560 if (! reload_completed
|| mdep_reorg_phase
!= SH_AFTER_MDEP_REORG
)
6561 mark_user_reg (fpscr_rtx
);
6580 expand_sf_unop (fun
, operands
)
6581 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
6584 emit_sf_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
6588 expand_sf_binop (fun
, operands
)
6589 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
6592 emit_sf_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
6597 expand_df_unop (fun
, operands
)
6598 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
));
6601 emit_df_insn ((*fun
) (operands
[0], operands
[1], get_fpscr_rtx ()));
6605 expand_df_binop (fun
, operands
)
6606 rtx (*fun
) PARAMS ((rtx
, rtx
, rtx
, rtx
));
6609 emit_df_insn ((*fun
) (operands
[0], operands
[1], operands
[2],
6613 /* ??? gcc does flow analysis strictly after common subexpression
6614 elimination. As a result, common subespression elimination fails
6615 when there are some intervening statements setting the same register.
6616 If we did nothing about this, this would hurt the precision switching
6617 for SH4 badly. There is some cse after reload, but it is unable to
6618 undo the extra register pressure from the unused instructions, and
6619 it cannot remove auto-increment loads.
6621 A C code example that shows this flow/cse weakness for (at least) SH
6622 and sparc (as of gcc ss-970706) is this:
6636 So we add another pass before common subexpression elimination, to
6637 remove assignments that are dead due to a following assignment in the
6638 same basic block. */
6641 mark_use (x
, reg_set_block
)
6642 rtx x
, *reg_set_block
;
6648 code
= GET_CODE (x
);
6653 int regno
= REGNO (x
);
6654 int nregs
= (regno
< FIRST_PSEUDO_REGISTER
6655 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
))
6659 reg_set_block
[regno
+ nregs
- 1] = 0;
6666 rtx dest
= SET_DEST (x
);
6668 if (GET_CODE (dest
) == SUBREG
)
6669 dest
= SUBREG_REG (dest
);
6670 if (GET_CODE (dest
) != REG
)
6671 mark_use (dest
, reg_set_block
);
6672 mark_use (SET_SRC (x
), reg_set_block
);
6679 const char *fmt
= GET_RTX_FORMAT (code
);
6681 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6684 mark_use (XEXP (x
, i
), reg_set_block
);
6685 else if (fmt
[i
] == 'E')
6686 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6687 mark_use (XVECEXP (x
, i
, j
), reg_set_block
);
6694 static rtx get_free_reg
PARAMS ((HARD_REG_SET
));
6696 /* This function returns a register to use to load the address to load
6697 the fpscr from. Currently it always returns r1 or r7, but when we are
6698 able to use pseudo registers after combine, or have a better mechanism
6699 for choosing a register, it should be done here. */
6700 /* REGS_LIVE is the liveness information for the point for which we
6701 need this allocation. In some bare-bones exit blocks, r1 is live at the
6702 start. We can even have all of r0..r3 being live:
6703 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
6704 INSN before which new insns are placed with will clobber the register
6705 we return. If a basic block consists only of setting the return value
6706 register to a pseudo and using that register, the return value is not
6707 live before or after this block, yet we we'll insert our insns right in
6711 get_free_reg (regs_live
)
6712 HARD_REG_SET regs_live
;
6714 if (! TEST_HARD_REG_BIT (regs_live
, 1))
6715 return gen_rtx_REG (Pmode
, 1);
6717 /* Hard reg 1 is live; since this is a SMALL_REGISTER_CLASSES target,
6718 there shouldn't be anything but a jump before the function end. */
6719 if (! TEST_HARD_REG_BIT (regs_live
, 7))
6720 return gen_rtx_REG (Pmode
, 7);
6725 /* This function will set the fpscr from memory.
6726 MODE is the mode we are setting it to. */
6728 fpscr_set_from_mem (mode
, regs_live
)
6730 HARD_REG_SET regs_live
;
6732 enum attr_fp_mode fp_mode
= mode
;
6733 rtx addr_reg
= get_free_reg (regs_live
);
6735 if (fp_mode
== (enum attr_fp_mode
) NORMAL_MODE (FP_MODE
))
6736 emit_insn (gen_fpu_switch1 (addr_reg
));
6738 emit_insn (gen_fpu_switch0 (addr_reg
));
6741 /* Is the given character a logical line separator for the assembler? */
6742 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
6743 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == ';')
6747 sh_insn_length_adjustment (insn
)
6750 /* Instructions with unfilled delay slots take up an extra two bytes for
6751 the nop in the delay slot. */
6752 if (((GET_CODE (insn
) == INSN
6753 && GET_CODE (PATTERN (insn
)) != USE
6754 && GET_CODE (PATTERN (insn
)) != CLOBBER
)
6755 || GET_CODE (insn
) == CALL_INSN
6756 || (GET_CODE (insn
) == JUMP_INSN
6757 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
6758 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
))
6759 && GET_CODE (PATTERN (NEXT_INSN (PREV_INSN (insn
)))) != SEQUENCE
6760 && get_attr_needs_delay_slot (insn
) == NEEDS_DELAY_SLOT_YES
)
6763 /* sh-dsp parallel processing insn take four bytes instead of two. */
6765 if (GET_CODE (insn
) == INSN
)
6768 rtx body
= PATTERN (insn
);
6769 const char *template;
6771 int maybe_label
= 1;
6773 if (GET_CODE (body
) == ASM_INPUT
)
6774 template = XSTR (body
, 0);
6775 else if (asm_noperands (body
) >= 0)
6777 = decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
);
6786 while (c
== ' ' || c
== '\t');
6787 /* all sh-dsp parallel-processing insns start with p.
6788 The only non-ppi sh insn starting with p is pref.
6789 The only ppi starting with pr is prnd. */
6790 if ((c
== 'p' || c
== 'P') && strncasecmp ("re", template, 2))
6792 /* The repeat pseudo-insn expands two three insns, a total of
6793 six bytes in size. */
6794 else if ((c
== 'r' || c
== 'R')
6795 && ! strncasecmp ("epeat", template, 5))
6797 while (c
&& c
!= '\n' && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c
))
6799 /* If this is a label, it is obviously not a ppi insn. */
6800 if (c
== ':' && maybe_label
)
6805 else if (c
== '\'' || c
== '"')
6810 maybe_label
= c
!= ':';
6818 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
6819 isn't protected by a PIC unspec. */
6821 nonpic_symbol_mentioned_p (x
)
6824 register const char *fmt
;
6827 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
6828 || GET_CODE (x
) == PC
)
6831 /* We don't want to look into the possible MEM location of a
6832 CONST_DOUBLE, since we're not going to use it, in general. */
6833 if (GET_CODE (x
) == CONST_DOUBLE
)
6836 if (GET_CODE (x
) == UNSPEC
6837 && (XINT (x
, 1) == UNSPEC_PIC
6838 || XINT (x
, 1) == UNSPEC_GOT
6839 || XINT (x
, 1) == UNSPEC_GOTOFF
6840 || XINT (x
, 1) == UNSPEC_GOTPLT
6841 || XINT (x
, 1) == UNSPEC_PLT
))
6844 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
6845 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
6851 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
6852 if (nonpic_symbol_mentioned_p (XVECEXP (x
, i
, j
)))
6855 else if (fmt
[i
] == 'e' && nonpic_symbol_mentioned_p (XEXP (x
, i
)))
6862 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
6863 @GOTOFF in `reg'. */
6865 legitimize_pic_address (orig
, mode
, reg
)
6867 enum machine_mode mode ATTRIBUTE_UNUSED
;
6870 if (GET_CODE (orig
) == LABEL_REF
6871 || (GET_CODE (orig
) == SYMBOL_REF
6872 && (CONSTANT_POOL_ADDRESS_P (orig
)
6873 /* SYMBOL_REF_FLAG is set on static symbols. */
6874 || SYMBOL_REF_FLAG (orig
))))
6877 reg
= gen_reg_rtx (Pmode
);
6879 emit_insn (gen_symGOTOFF2reg (reg
, orig
));
6882 else if (GET_CODE (orig
) == SYMBOL_REF
)
6885 reg
= gen_reg_rtx (Pmode
);
6887 emit_insn (gen_symGOT2reg (reg
, orig
));
6893 /* Mark the use of a constant in the literal table. If the constant
6894 has multiple labels, make it unique. */
6896 mark_constant_pool_use (x
)
6899 rtx insn
, lab
, pattern
;
6904 switch (GET_CODE (x
))
6914 /* Get the first label in the list of labels for the same constant
6915 and delete another labels in the list. */
6917 for (insn
= PREV_INSN (x
); insn
; insn
= PREV_INSN (insn
))
6919 if (GET_CODE (insn
) != CODE_LABEL
6920 || LABEL_REFS (insn
) != NEXT_INSN (insn
))
6925 for (insn
= LABEL_REFS (lab
); insn
; insn
= LABEL_REFS (insn
))
6926 INSN_DELETED_P (insn
) = 1;
6928 /* Mark constants in a window. */
6929 for (insn
= NEXT_INSN (x
); insn
; insn
= NEXT_INSN (insn
))
6931 if (GET_CODE (insn
) != INSN
)
6934 pattern
= PATTERN (insn
);
6935 if (GET_CODE (pattern
) != UNSPEC_VOLATILE
)
6938 switch (XINT (pattern
, 1))
6940 case UNSPECV_CONST2
:
6941 case UNSPECV_CONST4
:
6942 case UNSPECV_CONST8
:
6943 XVECEXP (pattern
, 0, 1) = const1_rtx
;
6945 case UNSPECV_WINDOW_END
:
6946 if (XVECEXP (pattern
, 0, 0) == x
)
6949 case UNSPECV_CONST_END
:
6959 /* Return true if it's possible to redirect BRANCH1 to the destination
6960 of an unconditional jump BRANCH2. We only want to do this if the
6961 resulting branch will have a short displacement. */
6963 sh_can_redirect_branch (branch1
, branch2
)
6967 if (flag_expensive_optimizations
&& simplejump_p (branch2
))
6969 rtx dest
= XEXP (SET_SRC (single_set (branch2
)), 0);
6973 for (distance
= 0, insn
= NEXT_INSN (branch1
);
6974 insn
&& distance
< 256;
6975 insn
= PREV_INSN (insn
))
6980 distance
+= get_attr_length (insn
);
6982 for (distance
= 0, insn
= NEXT_INSN (branch1
);
6983 insn
&& distance
< 256;
6984 insn
= NEXT_INSN (insn
))
6989 distance
+= get_attr_length (insn
);
6995 /* Return nonzero if register old_reg can be renamed to register new_reg. */
6997 sh_hard_regno_rename_ok (old_reg
, new_reg
)
6998 unsigned int old_reg ATTRIBUTE_UNUSED
;
6999 unsigned int new_reg
;
7002 /* Interrupt functions can only use registers that have already been
7003 saved by the prologue, even if they would normally be
7006 if (sh_cfun_interrupt_handler_p () && !regs_ever_live
[new_reg
])
7012 /* Function to update the integer COST
7013 based on the relationship between INSN that is dependent on
7014 DEP_INSN through the dependence LINK. The default is to make no
7015 adjustment to COST. This can be used for example to specify to
7016 the scheduler that an output- or anti-dependence does not incur
7017 the same cost as a data-dependence. The return value should be
7018 the new value for COST. */
7020 sh_adjust_cost (insn
, link
, dep_insn
, cost
)
7022 rtx link ATTRIBUTE_UNUSED
;
7030 /* On SHmedia, if the dependence is an anti-dependence or
7031 output-dependence, there is no cost. */
7032 if (REG_NOTE_KIND (link
) != 0)
7035 if (get_attr_is_mac_media (insn
)
7036 && get_attr_is_mac_media (dep_insn
))
7039 else if (REG_NOTE_KIND (link
) == 0)
7041 enum attr_type dep_type
, type
;
7043 if (recog_memoized (insn
) < 0
7044 || recog_memoized (dep_insn
) < 0)
7047 dep_type
= get_attr_type (dep_insn
);
7048 if (dep_type
== TYPE_FLOAD
|| dep_type
== TYPE_PCFLOAD
)
7050 if ((dep_type
== TYPE_LOAD_SI
|| dep_type
== TYPE_PCLOAD_SI
)
7051 && (type
= get_attr_type (insn
)) != TYPE_CALL
7052 && type
!= TYPE_SFUNC
)
7055 /* The only input for a call that is timing-critical is the
7056 function's address. */
7057 if (GET_CODE(insn
) == CALL_INSN
)
7059 rtx call
= PATTERN (insn
);
7061 if (GET_CODE (call
) == PARALLEL
)
7062 call
= XVECEXP (call
, 0 ,0);
7063 if (GET_CODE (call
) == SET
)
7064 call
= SET_SRC (call
);
7065 if (GET_CODE (call
) == CALL
&& GET_CODE (XEXP (call
, 0)) == MEM
7066 && ! reg_set_p (XEXP (XEXP (call
, 0), 0), dep_insn
))
7069 /* Likewise, the most timing critical input for an sfuncs call
7070 is the function address. However, sfuncs typically start
7071 using their arguments pretty quickly.
7072 Assume a four cycle delay before they are needed. */
7073 /* All sfunc calls are parallels with at least four components.
7074 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
7075 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
7076 && XVECLEN (PATTERN (insn
), 0) >= 4
7077 && (reg
= sfunc_uses_reg (insn
)))
7079 if (! reg_set_p (reg
, dep_insn
))
7082 /* When the preceding instruction loads the shift amount of
7083 the following SHAD/SHLD, the latency of the load is increased
7086 && get_attr_type (insn
) == TYPE_DYN_SHIFT
7087 && get_attr_any_int_load (dep_insn
) == ANY_INT_LOAD_YES
7088 && reg_overlap_mentioned_p (SET_DEST (PATTERN (dep_insn
)),
7089 XEXP (SET_SRC (single_set(insn
)),
7092 /* When an LS group instruction with a latency of less than
7093 3 cycles is followed by a double-precision floating-point
7094 instruction, FIPR, or FTRV, the latency of the first
7095 instruction is increased to 3 cycles. */
7097 && get_attr_insn_class (dep_insn
) == INSN_CLASS_LS_GROUP
7098 && get_attr_dfp_comp (insn
) == DFP_COMP_YES
)
7100 /* The lsw register of a double-precision computation is ready one
7102 else if (reload_completed
7103 && get_attr_dfp_comp (dep_insn
) == DFP_COMP_YES
7104 && (use_pat
= single_set (insn
))
7105 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn
))),
7109 if (get_attr_any_fp_comp (dep_insn
) == ANY_FP_COMP_YES
7110 && get_attr_late_fp_use (insn
) == LATE_FP_USE_YES
)
7113 /* An anti-dependence penalty of two applies if the first insn is a double
7114 precision fadd / fsub / fmul. */
7115 else if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
7116 && recog_memoized (dep_insn
) >= 0
7117 && get_attr_type (dep_insn
) == TYPE_DFP_ARITH
7118 /* A lot of alleged anti-flow dependences are fake,
7119 so check this one is real. */
7120 && flow_dependent_p (dep_insn
, insn
))
7127 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
7128 if DEP_INSN is anti-flow dependent on INSN. */
7130 flow_dependent_p (insn
, dep_insn
)
7133 rtx tmp
= PATTERN (insn
);
7135 note_stores (PATTERN (dep_insn
), flow_dependent_p_1
, &tmp
);
7136 return tmp
== NULL_RTX
;
7139 /* A helper function for flow_dependent_p called through note_stores. */
7141 flow_dependent_p_1 (x
, pat
, data
)
7143 rtx pat ATTRIBUTE_UNUSED
;
7146 rtx
* pinsn
= (rtx
*) data
;
7148 if (*pinsn
&& reg_referenced_p (x
, *pinsn
))
7152 /* For use by ALLOCATE_INITIAL_VALUE. Note that sh.md contains some
7153 'special function' patterns (type sfunc) that clobber pr, but that
7154 do not look like function calls to leaf_function_p. Hence we must
7155 do this extra check. */
7159 return REG_N_SETS (TARGET_SHMEDIA
? PR_MEDIA_REG
: PR_REG
);
7162 /* This Function returns nonzero if the DFA based scheduler interface
7163 is to be used. At present this is supported for the SH4 only. */
7165 sh_use_dfa_interface()
7167 if (TARGET_HARD_SH4
)
7173 /* This function returns "2" to indicate dual issue for the SH4
7174 processor. To be used by the DFA pipeline description. */
7178 if (TARGET_SUPERSCALAR
)
7184 /* SHmedia requires registers for branches, so we can't generate new
7185 branches past reload. */
7187 sh_cannot_modify_jumps_p ()
7189 return (TARGET_SHMEDIA
&& (reload_in_progress
|| reload_completed
));
7193 sh_ms_bitfield_layout_p (record_type
)
7194 tree record_type ATTRIBUTE_UNUSED
;
7199 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
7200 may access it using GOTOFF instead of GOT. */
7203 sh_encode_section_info (decl
, first
)
7210 rtl
= DECL_RTL (decl
);
7212 rtl
= TREE_CST_RTL (decl
);
7213 if (GET_CODE (rtl
) != MEM
)
7215 symbol
= XEXP (rtl
, 0);
7216 if (GET_CODE (symbol
) != SYMBOL_REF
)
7220 SYMBOL_REF_FLAG (symbol
) = (*targetm
.binds_local_p
) (decl
);
7222 if (TARGET_SH5
&& first
&& TREE_CODE (decl
) != FUNCTION_DECL
)
7223 XEXP (rtl
, 0) = gen_datalabel_ref (symbol
);
7226 /* Undo the effects of the above. */
7229 sh_strip_name_encoding (str
)
7232 STRIP_DATALABEL_ENCODING (str
, str
);
7239 On the SH1..SH4, the trampoline looks like
7240 2 0002 D202 mov.l l2,r2
7241 1 0000 D301 mov.l l1,r3
7244 5 0008 00000000 l1: .long area
7245 6 000c 00000000 l2: .long function
7247 SH5 (compact) uses r1 instead of r3 for the static chain. */
7250 /* Emit RTL insns to initialize the variable parts of a trampoline.
7251 FNADDR is an RTX for the address of the function's pure code.
7252 CXT is an RTX for the static chain value for the function. */
7255 sh_initialize_trampoline (tramp
, fnaddr
, cxt
)
7256 rtx tramp
, fnaddr
, cxt
;
7258 if (TARGET_SHMEDIA64
)
7263 rtx movi1
= GEN_INT (0xcc000010);
7264 rtx shori1
= GEN_INT (0xc8000010);
7267 /* The following trampoline works within a +- 128 KB range for cxt:
7268 ptb/u cxt,tr1; movi fnaddr >> 48,r0; shori fnaddr >> 32,r0;
7269 shori fnaddr >> 16,r0; shori fnaddr,r0; ptabs/l r0,tr0
7270 gettr tr1,r1; blink tr0,r63 */
7271 /* Address rounding makes it hard to compute the exact bounds of the
7272 offset for this trampoline, but we have a rather generous offset
7273 range, so frame_offset should do fine as an upper bound. */
7274 if (cxt
== virtual_stack_vars_rtx
&& frame_offset
< 0x20000)
7276 /* ??? could optimize this trampoline initialization
7277 by writing DImode words with two insns each. */
7278 rtx mask
= force_reg (DImode
, GEN_INT (0x3fffc00));
7279 rtx insn
= gen_rtx_MINUS (DImode
, cxt
, tramp
);
7280 insn
= gen_rtx_ASHIFT (DImode
, insn
, GEN_INT (10-2));
7281 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7282 /* Or in ptb/u .,tr1 pattern */
7283 insn
= gen_rtx_IOR (DImode
, insn
, gen_int_mode (0xec000010, SImode
));
7284 insn
= force_operand (insn
, NULL_RTX
);
7285 insn
= gen_lowpart (SImode
, insn
);
7286 emit_move_insn (gen_rtx_MEM (SImode
, tramp
), insn
);
7287 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (38));
7288 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7289 insn
= force_operand (gen_rtx_IOR (DImode
, movi1
, insn
), NULL_RTX
);
7290 insn
= gen_lowpart (SImode
, insn
);
7291 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)), insn
);
7292 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (22));
7293 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7294 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
7295 insn
= gen_lowpart (SImode
, insn
);
7296 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)), insn
);
7297 insn
= gen_rtx_LSHIFTRT (DImode
, fnaddr
, GEN_INT (6));
7298 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7299 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
7300 insn
= gen_lowpart (SImode
, insn
);
7301 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7303 insn
= gen_rtx_ASHIFT (DImode
, fnaddr
, GEN_INT (10));
7304 insn
= gen_rtx_AND (DImode
, insn
, mask
);
7305 insn
= force_operand (gen_rtx_IOR (DImode
, shori1
, insn
), NULL_RTX
);
7306 insn
= gen_lowpart (SImode
, insn
);
7307 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 16)),
7309 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 20)),
7310 GEN_INT (0x6bf10600));
7311 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 24)),
7312 GEN_INT (0x4415fc10));
7313 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 28)),
7314 GEN_INT (0x4401fff0));
7315 emit_insn (gen_ic_invalidate_line (tramp
));
7318 tramp_templ
= gen_rtx_SYMBOL_REF (Pmode
,"__GCC_nested_trampoline");
7319 fixed_len
= TRAMPOLINE_SIZE
- 2 * GET_MODE_SIZE (Pmode
);
7321 tramp_templ
= gen_datalabel_ref (tramp_templ
);
7322 dst
= gen_rtx_MEM (BLKmode
, tramp
);
7323 src
= gen_rtx_MEM (BLKmode
, tramp_templ
);
7324 set_mem_align (dst
, 256);
7325 set_mem_align (src
, 64);
7326 emit_block_move (dst
, src
, GEN_INT (fixed_len
), BLOCK_OP_NORMAL
);
7328 emit_move_insn (gen_rtx_MEM (Pmode
, plus_constant (tramp
, fixed_len
)),
7330 emit_move_insn (gen_rtx_MEM (Pmode
,
7331 plus_constant (tramp
,
7333 + GET_MODE_SIZE (Pmode
))),
7335 emit_insn (gen_ic_invalidate_line (tramp
));
7338 else if (TARGET_SHMEDIA
)
7340 /* movi fnaddr >> 16,r1; shori fnaddr,r1; ptabs/l r1,tr0
7341 movi cxt >> 16,r1; shori cxt,r1; blink tr0,r63 */
7342 rtx quad0
= gen_reg_rtx (DImode
), cxtload
= gen_reg_rtx (DImode
);
7343 rtx quad1
= gen_reg_rtx (DImode
), quad2
= gen_reg_rtx (DImode
);
7344 /* movi 0,r1: 0xcc000010 shori 0,r1: c8000010 concatenated,
7345 rotated 10 right, and higer 16 bit of every 32 selected. */
7347 = force_reg (V2HImode
, (simplify_gen_subreg
7348 (V2HImode
, GEN_INT (0x4330432), SImode
, 0)));
7349 rtx ptabs
= force_reg (DImode
, GEN_INT (0x6bf10600));
7350 rtx blink
= force_reg (DImode
, GEN_INT (0x4401fff0));
7352 tramp
= force_reg (Pmode
, tramp
);
7353 fnaddr
= force_reg (SImode
, fnaddr
);
7354 cxt
= force_reg (SImode
, cxt
);
7355 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, quad0
, 0),
7356 gen_rtx_SUBREG (V2HImode
, fnaddr
, 0),
7358 emit_insn (gen_rotldi3_mextr (quad0
, quad0
,
7359 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
7360 emit_insn (gen_ashldi3_media (quad0
, quad0
, GEN_INT (2)));
7361 emit_move_insn (gen_rtx_MEM (DImode
, tramp
), quad0
);
7362 emit_insn (gen_mshflo_w_x (gen_rtx_SUBREG (V4HImode
, cxtload
, 0),
7363 gen_rtx_SUBREG (V2HImode
, cxt
, 0),
7365 emit_insn (gen_rotldi3_mextr (cxtload
, cxtload
,
7366 GEN_INT (TARGET_LITTLE_ENDIAN
? 24 : 56)));
7367 emit_insn (gen_ashldi3_media (cxtload
, cxtload
, GEN_INT (2)));
7368 if (TARGET_LITTLE_ENDIAN
)
7370 emit_insn (gen_mshflo_l_di (quad1
, ptabs
, cxtload
));
7371 emit_insn (gen_mextr4 (quad2
, cxtload
, blink
));
7375 emit_insn (gen_mextr4 (quad1
, cxtload
, ptabs
));
7376 emit_insn (gen_mshflo_l_di (quad2
, blink
, cxtload
));
7378 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)), quad1
);
7379 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), quad2
);
7380 emit_insn (gen_ic_invalidate_line (tramp
));
7383 else if (TARGET_SHCOMPACT
)
7385 emit_insn (gen_initialize_trampoline (tramp
, cxt
, fnaddr
));
7388 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
7389 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0xd301d202 : 0xd202d301,
7391 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
7392 gen_int_mode (TARGET_LITTLE_ENDIAN
? 0x0009422b : 0x422b0009,
7394 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
7396 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
7400 if (TARGET_USERMODE
)
7401 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__ic_invalidate"),
7402 0, VOIDmode
, 1, tramp
, SImode
);
7404 emit_insn (gen_ic_invalidate_line (tramp
));
7409 /* Machine specific built-in functions. */
7411 struct builtin_description
7413 const enum insn_code icode
;
7414 const char *const name
;
7418 /* describe number and signedness of arguments; arg[0] == result
7419 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
7420 static const char signature_args
[][4] =
7422 #define SH_BLTIN_V2SI2 0
7424 #define SH_BLTIN_V4HI2 1
7426 #define SH_BLTIN_V2SI3 2
7428 #define SH_BLTIN_V4HI3 3
7430 #define SH_BLTIN_V8QI3 4
7432 #define SH_BLTIN_MAC_HISI 5
7434 #define SH_BLTIN_SH_HI 6
7436 #define SH_BLTIN_SH_SI 7
7438 #define SH_BLTIN_V4HI2V2SI 8
7440 #define SH_BLTIN_V4HI2V8QI 9
7442 #define SH_BLTIN_SISF 10
7444 #define SH_BLTIN_LDUA_L 11
7446 #define SH_BLTIN_LDUA_Q 12
7448 #define SH_BLTIN_STUA_L 13
7450 #define SH_BLTIN_STUA_Q 14
7452 #define SH_BLTIN_UDI 15
7454 #define SH_BLTIN_NUM_SHARED_SIGNATURES 16
7455 #define SH_BLTIN_2 16
7456 #define SH_BLTIN_SU 16
7458 #define SH_BLTIN_3 17
7459 #define SH_BLTIN_SUS 17
7461 #define SH_BLTIN_PSSV 18
7463 #define SH_BLTIN_XXUU 19
7464 #define SH_BLTIN_UUUU 19
7466 #define SH_BLTIN_PV 20
7469 /* mcmv: operands considered unsigned. */
7470 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
7471 /* mperm: control value considered unsigned int. */
7472 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
7473 /* mshards_q: returns signed short. */
7474 /* nsb: takes long long arg, returns unsigned char. */
7475 static const struct builtin_description bdesc
[] =
7477 { CODE_FOR_absv2si2
, "__builtin_absv2si2", SH_BLTIN_V2SI2
},
7478 { CODE_FOR_absv4hi2
, "__builtin_absv4hi2", SH_BLTIN_V4HI2
},
7479 { CODE_FOR_addv2si3
, "__builtin_addv2si3", SH_BLTIN_V2SI3
},
7480 { CODE_FOR_addv4hi3
, "__builtin_addv4hi3", SH_BLTIN_V4HI3
},
7481 { CODE_FOR_ssaddv2si3
,"__builtin_ssaddv2si3", SH_BLTIN_V2SI3
},
7482 { CODE_FOR_usaddv8qi3
,"__builtin_usaddv8qi3", SH_BLTIN_V8QI3
},
7483 { CODE_FOR_ssaddv4hi3
,"__builtin_ssaddv4hi3", SH_BLTIN_V4HI3
},
7485 { CODE_FOR_alloco32
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
},
7486 { CODE_FOR_alloco64
, "__builtin_sh_media_ALLOCO", SH_BLTIN_PV
},
7488 { CODE_FOR_negcmpeqv8qi
,"__builtin_sh_media_MCMPEQ_B", SH_BLTIN_V8QI3
},
7489 { CODE_FOR_negcmpeqv2si
,"__builtin_sh_media_MCMPEQ_L", SH_BLTIN_V2SI3
},
7490 { CODE_FOR_negcmpeqv4hi
,"__builtin_sh_media_MCMPEQ_W", SH_BLTIN_V4HI3
},
7491 { CODE_FOR_negcmpgtuv8qi
,"__builtin_sh_media_MCMPGT_UB", SH_BLTIN_V8QI3
},
7492 { CODE_FOR_negcmpgtv2si
,"__builtin_sh_media_MCMPGT_L", SH_BLTIN_V2SI3
},
7493 { CODE_FOR_negcmpgtv4hi
,"__builtin_sh_media_MCMPGT_W", SH_BLTIN_V4HI3
},
7494 { CODE_FOR_mcmv
, "__builtin_sh_media_MCMV", SH_BLTIN_UUUU
},
7495 { CODE_FOR_mcnvs_lw
, "__builtin_sh_media_MCNVS_LW", SH_BLTIN_3
},
7496 { CODE_FOR_mcnvs_wb
, "__builtin_sh_media_MCNVS_WB", SH_BLTIN_V4HI2V8QI
},
7497 { CODE_FOR_mcnvs_wub
, "__builtin_sh_media_MCNVS_WUB", SH_BLTIN_V4HI2V8QI
},
7498 { CODE_FOR_mextr1
, "__builtin_sh_media_MEXTR1", SH_BLTIN_UDI
},
7499 { CODE_FOR_mextr2
, "__builtin_sh_media_MEXTR2", SH_BLTIN_UDI
},
7500 { CODE_FOR_mextr3
, "__builtin_sh_media_MEXTR3", SH_BLTIN_UDI
},
7501 { CODE_FOR_mextr4
, "__builtin_sh_media_MEXTR4", SH_BLTIN_UDI
},
7502 { CODE_FOR_mextr5
, "__builtin_sh_media_MEXTR5", SH_BLTIN_UDI
},
7503 { CODE_FOR_mextr6
, "__builtin_sh_media_MEXTR6", SH_BLTIN_UDI
},
7504 { CODE_FOR_mextr7
, "__builtin_sh_media_MEXTR7", SH_BLTIN_UDI
},
7505 { CODE_FOR_mmacfx_wl
, "__builtin_sh_media_MMACFX_WL", SH_BLTIN_MAC_HISI
},
7506 { CODE_FOR_mmacnfx_wl
,"__builtin_sh_media_MMACNFX_WL", SH_BLTIN_MAC_HISI
},
7507 { CODE_FOR_mulv2si3
, "__builtin_mulv2si3", SH_BLTIN_V2SI3
, },
7508 { CODE_FOR_mulv4hi3
, "__builtin_mulv4hi3", SH_BLTIN_V4HI3
},
7509 { CODE_FOR_mmulfx_l
, "__builtin_sh_media_MMULFX_L", SH_BLTIN_V2SI3
},
7510 { CODE_FOR_mmulfx_w
, "__builtin_sh_media_MMULFX_W", SH_BLTIN_V4HI3
},
7511 { CODE_FOR_mmulfxrp_w
,"__builtin_sh_media_MMULFXRP_W", SH_BLTIN_V4HI3
},
7512 { CODE_FOR_mmulhi_wl
, "__builtin_sh_media_MMULHI_WL", SH_BLTIN_V4HI2V2SI
},
7513 { CODE_FOR_mmullo_wl
, "__builtin_sh_media_MMULLO_WL", SH_BLTIN_V4HI2V2SI
},
7514 { CODE_FOR_mmulsum_wq
,"__builtin_sh_media_MMULSUM_WQ", SH_BLTIN_XXUU
},
7515 { CODE_FOR_mperm_w
, "__builtin_sh_media_MPERM_W", SH_BLTIN_SH_HI
},
7516 { CODE_FOR_msad_ubq
, "__builtin_sh_media_MSAD_UBQ", SH_BLTIN_XXUU
},
7517 { CODE_FOR_mshalds_l
, "__builtin_sh_media_MSHALDS_L", SH_BLTIN_SH_SI
},
7518 { CODE_FOR_mshalds_w
, "__builtin_sh_media_MSHALDS_W", SH_BLTIN_SH_HI
},
7519 { CODE_FOR_ashrv2si3
, "__builtin_ashrv2si3", SH_BLTIN_SH_SI
},
7520 { CODE_FOR_ashrv4hi3
, "__builtin_ashrv4hi3", SH_BLTIN_SH_HI
},
7521 { CODE_FOR_mshards_q
, "__builtin_sh_media_MSHARDS_Q", SH_BLTIN_SUS
},
7522 { CODE_FOR_mshfhi_b
, "__builtin_sh_media_MSHFHI_B", SH_BLTIN_V8QI3
},
7523 { CODE_FOR_mshfhi_l
, "__builtin_sh_media_MSHFHI_L", SH_BLTIN_V2SI3
},
7524 { CODE_FOR_mshfhi_w
, "__builtin_sh_media_MSHFHI_W", SH_BLTIN_V4HI3
},
7525 { CODE_FOR_mshflo_b
, "__builtin_sh_media_MSHFLO_B", SH_BLTIN_V8QI3
},
7526 { CODE_FOR_mshflo_l
, "__builtin_sh_media_MSHFLO_L", SH_BLTIN_V2SI3
},
7527 { CODE_FOR_mshflo_w
, "__builtin_sh_media_MSHFLO_W", SH_BLTIN_V4HI3
},
7528 { CODE_FOR_ashlv2si3
, "__builtin_ashlv2si3", SH_BLTIN_SH_SI
},
7529 { CODE_FOR_ashlv4hi3
, "__builtin_ashlv4hi3", SH_BLTIN_SH_HI
},
7530 { CODE_FOR_lshrv2si3
, "__builtin_lshrv2si3", SH_BLTIN_SH_SI
},
7531 { CODE_FOR_lshrv4hi3
, "__builtin_lshrv4hi3", SH_BLTIN_SH_HI
},
7532 { CODE_FOR_subv2si3
, "__builtin_subv2si3", SH_BLTIN_V2SI3
},
7533 { CODE_FOR_subv4hi3
, "__builtin_subv4hi3", SH_BLTIN_V4HI3
},
7534 { CODE_FOR_sssubv2si3
,"__builtin_sssubv2si3", SH_BLTIN_V2SI3
},
7535 { CODE_FOR_ussubv8qi3
,"__builtin_ussubv8qi3", SH_BLTIN_V8QI3
},
7536 { CODE_FOR_sssubv4hi3
,"__builtin_sssubv4hi3", SH_BLTIN_V4HI3
},
7537 { CODE_FOR_fcosa_s
, "__builtin_sh_media_FCOSA_S", SH_BLTIN_SISF
},
7538 { CODE_FOR_fsina_s
, "__builtin_sh_media_FSINA_S", SH_BLTIN_SISF
},
7539 { CODE_FOR_fipr
, "__builtin_sh_media_FIPR_S", SH_BLTIN_3
},
7540 { CODE_FOR_ftrv
, "__builtin_sh_media_FTRV_S", SH_BLTIN_3
},
7541 { CODE_FOR_fsrra_s
, "__builtin_sh_media_FSRRA_S", SH_BLTIN_2
},
7543 { CODE_FOR_ldhi_l
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
},
7544 { CODE_FOR_ldhi_q
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
},
7545 { CODE_FOR_ldlo_l
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
},
7546 { CODE_FOR_ldlo_q
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
},
7547 { CODE_FOR_sthi_l
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
},
7548 { CODE_FOR_sthi_q
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
},
7549 { CODE_FOR_stlo_l
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
},
7550 { CODE_FOR_stlo_q
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
},
7551 { CODE_FOR_ldhi_l64
, "__builtin_sh_media_LDHI_L", SH_BLTIN_LDUA_L
},
7552 { CODE_FOR_ldhi_q64
, "__builtin_sh_media_LDHI_Q", SH_BLTIN_LDUA_Q
},
7553 { CODE_FOR_ldlo_l64
, "__builtin_sh_media_LDLO_L", SH_BLTIN_LDUA_L
},
7554 { CODE_FOR_ldlo_q64
, "__builtin_sh_media_LDLO_Q", SH_BLTIN_LDUA_Q
},
7555 { CODE_FOR_sthi_l64
, "__builtin_sh_media_STHI_L", SH_BLTIN_STUA_L
},
7556 { CODE_FOR_sthi_q64
, "__builtin_sh_media_STHI_Q", SH_BLTIN_STUA_Q
},
7557 { CODE_FOR_stlo_l64
, "__builtin_sh_media_STLO_L", SH_BLTIN_STUA_L
},
7558 { CODE_FOR_stlo_q64
, "__builtin_sh_media_STLO_Q", SH_BLTIN_STUA_Q
},
7560 { CODE_FOR_nsb
, "__builtin_sh_media_NSB", SH_BLTIN_SU
},
7561 { CODE_FOR_byterev
, "__builtin_sh_media_BYTEREV", SH_BLTIN_2
},
7563 { CODE_FOR_prefetch32
,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV
},
7564 { CODE_FOR_prefetch64
,"__builtin_sh_media_PREFO", SH_BLTIN_PSSV
}
7569 sh_media_init_builtins ()
7571 tree shared
[SH_BLTIN_NUM_SHARED_SIGNATURES
];
7572 const struct builtin_description
*d
;
7574 memset (shared
, 0, sizeof shared
);
7575 for (d
= bdesc
; d
- bdesc
< (int) (sizeof bdesc
/ sizeof bdesc
[0]); d
++)
7577 tree type
, arg_type
;
7578 int signature
= d
->signature
;
7581 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
&& shared
[signature
])
7582 type
= shared
[signature
];
7585 int has_result
= signature_args
[signature
][0] != 0;
7587 if (signature_args
[signature
][1] == 8
7588 && (insn_data
[d
->icode
].operand
[has_result
].mode
!= Pmode
))
7590 if (! TARGET_FPU_ANY
7591 && FLOAT_MODE_P (insn_data
[d
->icode
].operand
[0].mode
))
7593 type
= void_list_node
;
7596 int arg
= signature_args
[signature
][i
];
7597 int opno
= i
- 1 + has_result
;
7600 arg_type
= ptr_type_node
;
7602 arg_type
= ((*lang_hooks
.types
.type_for_mode
)
7603 (insn_data
[d
->icode
].operand
[opno
].mode
,
7608 arg_type
= void_type_node
;
7611 type
= tree_cons (NULL_TREE
, arg_type
, type
);
7613 type
= build_function_type (arg_type
, type
);
7614 if (signature
< SH_BLTIN_NUM_SHARED_SIGNATURES
)
7615 shared
[signature
] = type
;
7617 builtin_function (d
->name
, type
, d
- bdesc
, BUILT_IN_MD
,
7626 sh_media_init_builtins ();
7629 /* Expand an expression EXP that calls a built-in function,
7630 with result going to TARGET if that's convenient
7631 (and in mode MODE if that's convenient).
7632 SUBTARGET may be used as the target for computing one of EXP's operands.
7633 IGNORE is nonzero if the value is to be ignored. */
7636 sh_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
7639 rtx subtarget ATTRIBUTE_UNUSED
;
7640 enum machine_mode mode ATTRIBUTE_UNUSED
;
7643 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
7644 tree arglist
= TREE_OPERAND (exp
, 1);
7645 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
7646 const struct builtin_description
*d
= &bdesc
[fcode
];
7647 enum insn_code icode
= d
->icode
;
7648 int signature
= d
->signature
;
7649 enum machine_mode tmode
= VOIDmode
;
7654 if (signature_args
[signature
][0])
7659 tmode
= insn_data
[icode
].operand
[0].mode
;
7661 || GET_MODE (target
) != tmode
7662 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
7663 target
= gen_reg_rtx (tmode
);
7669 for (i
= 1; i
<= 3; i
++, nop
++)
7672 enum machine_mode opmode
, argmode
;
7674 if (! signature_args
[signature
][i
])
7676 arg
= TREE_VALUE (arglist
);
7677 if (arg
== error_mark_node
)
7679 arglist
= TREE_CHAIN (arglist
);
7680 opmode
= insn_data
[icode
].operand
[nop
].mode
;
7681 argmode
= TYPE_MODE (TREE_TYPE (arg
));
7682 if (argmode
!= opmode
)
7683 arg
= build1 (NOP_EXPR
,
7684 (*lang_hooks
.types
.type_for_mode
) (opmode
, 0), arg
);
7685 op
[nop
] = expand_expr (arg
, NULL_RTX
, opmode
, 0);
7686 if (! (*insn_data
[icode
].operand
[nop
].predicate
) (op
[nop
], opmode
))
7687 op
[nop
] = copy_to_mode_reg (opmode
, op
[nop
]);
7693 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0]);
7696 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1]);
7699 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2]);
7702 pat
= (*insn_data
[d
->icode
].genfun
) (op
[0], op
[1], op
[2], op
[3]);
7714 sh_expand_unop_v2sf (code
, op0
, op1
)
7718 rtx sel0
= const0_rtx
;
7719 rtx sel1
= const1_rtx
;
7720 rtx (*fn
) PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
)) = gen_unary_sf_op
;
7721 rtx op
= gen_rtx_fmt_e (code
, SFmode
, op1
);
7723 emit_insn ((*fn
) (op0
, op1
, op
, sel0
, sel0
));
7724 emit_insn ((*fn
) (op0
, op1
, op
, sel1
, sel1
));
7728 sh_expand_binop_v2sf (code
, op0
, op1
, op2
)
7732 rtx sel0
= const0_rtx
;
7733 rtx sel1
= const1_rtx
;
7734 rtx (*fn
) PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
, rtx
)) = gen_binary_sf_op
;
7735 rtx op
= gen_rtx_fmt_ee (code
, SFmode
, op1
, op2
);
7737 emit_insn ((*fn
) (op0
, op1
, op2
, op
, sel0
, sel0
, sel0
));
7738 emit_insn ((*fn
) (op0
, op1
, op2
, op
, sel1
, sel1
, sel1
));
7741 /* Return the class of registers for which a mode change from FROM to TO
7744 sh_cannot_change_mode_class (from
, to
)
7745 enum machine_mode from
, to
;
7747 if (GET_MODE_SIZE (from
) != GET_MODE_SIZE (to
))
7749 if (TARGET_LITTLE_ENDIAN
)
7751 if (GET_MODE_SIZE (to
) < 8 || GET_MODE_SIZE (from
) < 8)
7756 if (GET_MODE_SIZE (from
) < 8)
7764 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
7765 that label is used. */
7768 sh_mark_label (address
, nuses
)
7772 if (GOTOFF_P (address
))
7774 /* Extract the label or symbol. */
7775 address
= XEXP (address
, 0);
7776 if (GET_CODE (address
) == PLUS
)
7777 address
= XEXP (address
, 0);
7778 address
= XVECEXP (address
, 0, 0);
7780 if (GET_CODE (address
) == LABEL_REF
7781 && GET_CODE (XEXP (address
, 0)) == CODE_LABEL
)
7782 LABEL_NUSES (XEXP (address
, 0)) += nuses
;
7785 /* Compute extra cost of moving data between one register class
7788 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
7789 uses this information. Hence, the general register <-> floating point
7790 register information here is not used for SFmode. */
7793 sh_register_move_cost (mode
, srcclass
, dstclass
)
7794 enum machine_mode mode
;
7795 enum reg_class srcclass
, dstclass
;
7797 if (dstclass
== T_REGS
|| dstclass
== PR_REGS
)
7800 if (mode
== SImode
&& ! TARGET_SHMEDIA
&& TARGET_FMOVD
7801 && REGCLASS_HAS_FP_REG (srcclass
)
7802 && REGCLASS_HAS_FP_REG (dstclass
))
7805 if ((REGCLASS_HAS_FP_REG (dstclass
)
7806 && REGCLASS_HAS_GENERAL_REG (srcclass
))
7807 || (REGCLASS_HAS_GENERAL_REG (dstclass
)
7808 && REGCLASS_HAS_FP_REG (srcclass
)))
7809 return ((TARGET_SHMEDIA
? 4 : TARGET_FMOVD
? 8 : 12)
7810 * ((GET_MODE_SIZE (mode
) + 7) / 8U));
7812 if ((dstclass
== FPUL_REGS
7813 && REGCLASS_HAS_GENERAL_REG (srcclass
))
7814 || (srcclass
== FPUL_REGS
7815 && REGCLASS_HAS_GENERAL_REG (dstclass
)))
7818 if ((dstclass
== FPUL_REGS
7819 && (srcclass
== PR_REGS
|| srcclass
== MAC_REGS
|| srcclass
== T_REGS
))
7820 || (srcclass
== FPUL_REGS
7821 && (dstclass
== PR_REGS
|| dstclass
== MAC_REGS
)))
7824 if ((srcclass
== TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
7825 || ((dstclass
) == TARGET_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
7828 if ((srcclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (dstclass
))
7829 || (dstclass
== FPSCR_REGS
&& ! REGCLASS_HAS_GENERAL_REG (srcclass
)))
7834 && ! REGCLASS_HAS_GENERAL_REG (srcclass
)
7835 && ! REGCLASS_HAS_GENERAL_REG (dstclass
)))
7836 return 2 * ((GET_MODE_SIZE (mode
) + 7) / 8U);
7838 return 2 * ((GET_MODE_SIZE (mode
) + 3) / 4U);
7841 /* Like register_operand, but take into account that SHMEDIA can use
7842 the constant zero like a general register. */
7844 sh_register_operand (op
, mode
)
7846 enum machine_mode mode
;
7848 if (op
== CONST0_RTX (mode
) && TARGET_SHMEDIA
)
7850 return register_operand (op
, mode
);