1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993 - 1999 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
24 ;; ??? Should prepend a * to all pattern names which are not used.
25 ;; This will make the compiler smaller, and rebuilds after changes faster.
27 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
28 ;; sequences. Especially the sequences for arithmetic right shifts.
30 ;; ??? Should check all DImode patterns for consistency and usefulness.
32 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
33 ;; way to generate them.
35 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
36 ;; for a str* inline function.
38 ;; BSR is not generated by the compiler proper, but when relaxing, it
39 ;; generates .uses pseudo-ops that allow linker relaxation to create
40 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
42 ;; Special constraints for SH machine description:
49 ;; Special formats used for outputting SH instructions:
51 ;; %. -- print a .s if insn needs delay slot
52 ;; %@ -- print rte/rts if is/isn't an interrupt function
53 ;; %# -- output a nop if there is nothing to put in the delay slot
54 ;; %O -- print a constant without the #
55 ;; %R -- print the lsw reg of a double
56 ;; %S -- print the msw reg of a double
57 ;; %T -- print next word of a double REG or MEM
59 ;; Special predicates:
61 ;; arith_operand -- operand is valid source for arithmetic op
62 ;; arith_reg_operand -- operand is valid register for arithmetic op
63 ;; general_movdst_operand -- operand is valid move destination
64 ;; general_movsrc_operand -- operand is valid move source
65 ;; logical_operand -- operand is valid source for logical op
66 ;; -------------------------------------------------------------------------
68 ;; -------------------------------------------------------------------------
73 "sh1,sh2,sh3,sh3e,sh4"
74 (const (symbol_ref "sh_cpu_attr")))
76 (define_attr "endian" "big,little"
77 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
78 (const_string "little") (const_string "big"))))
80 (define_attr "fmovd" "yes,no"
81 (const (if_then_else (symbol_ref "TARGET_FMOVD")
82 (const_string "yes") (const_string "no"))))
84 (define_attr "issues" "1,2"
85 (const (if_then_else (symbol_ref "TARGET_SUPERSCALAR") (const_string "2") (const_string "1"))))
87 ;; cbranch conditional branch instructions
88 ;; jump unconditional jumps
89 ;; arith ordinary arithmetic
90 ;; arith3 a compound insn that behaves similarly to a sequence of
91 ;; three insns of type arith
92 ;; arith3b like above, but might end with a redirected branch
94 ;; load_si Likewise, SImode variant for general register.
96 ;; move register to register
97 ;; fmove register to register, floating point
98 ;; smpy word precision integer multiply
99 ;; dmpy longword or doublelongword precision integer multiply
101 ;; pload load of pr reg, which can't be put into delay slot of rts
102 ;; pstore store of pr reg, which can't be put into delay slot of jsr
103 ;; pcload pc relative load of constant value
104 ;; pcload_si Likewise, SImode variant for general register.
105 ;; rte return from exception
106 ;; sfunc special function call with known used registers
107 ;; call function call
109 ;; fdiv floating point divide (or square root)
110 ;; gp_fpul move between general purpose register and fpul
111 ;; dfp_arith, dfp_cmp,dfp_conv
112 ;; dfdiv double precision floating point divide (or square root)
113 ;; nil no-op move, will be deleted.
116 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,pstore,pcload,pcload_si,rte,sfunc,call,fp,fdiv,dfp_arith,dfp_cmp,dfp_conv,dfdiv,gp_fpul,nil"
117 (const_string "other"))
119 ; If a conditional branch destination is within -252..258 bytes away
120 ; from the instruction it can be 2 bytes long. Something in the
121 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
122 ; branches are initially assumed to be 16 bytes long.
123 ; In machine_dependent_reorg, we split all branches that are longer than
126 ;; The maximum range used for SImode constant pool entrys is 1018. A final
127 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
128 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
129 ;; instruction around the pool table, 2 bytes of alignment before the table,
130 ;; and 30 bytes of alignment after the table. That gives a maximum total
131 ;; pool size of 1058 bytes.
132 ;; Worst case code/pool content size ratio is 1:2 (using asms).
133 ;; Thus, in the worst case, there is one instruction in front of a maximum
134 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
135 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
136 ;; If we have a forward branch, the initial table will be put after the
137 ;; unconditional branch.
139 ;; ??? We could do much better by keeping track of the actual pcloads within
140 ;; the branch range and in the pcload range in front of the branch range.
142 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
144 (define_attr "short_cbranch_p" "no,yes"
145 (cond [(ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
147 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
149 (ne (symbol_ref "NEXT_INSN (PREV_INSN (insn)) != insn") (const_int 0))
151 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
153 ] (const_string "no")))
155 (define_attr "med_branch_p" "no,yes"
156 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
159 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
161 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
164 ] (const_string "no")))
166 (define_attr "med_cbranch_p" "no,yes"
167 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
170 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
172 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
175 ] (const_string "no")))
177 (define_attr "braf_branch_p" "no,yes"
178 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
180 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
183 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
185 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
188 ] (const_string "no")))
190 (define_attr "braf_cbranch_p" "no,yes"
191 (cond [(ne (symbol_ref "! TARGET_SH2") (const_int 0))
193 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
196 (ne (symbol_ref "mdep_reorg_phase <= SH_FIXUP_PCLOAD") (const_int 0))
198 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
201 ] (const_string "no")))
203 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
204 ; For wider ranges, we need a combination of a code and a data part.
205 ; If we can get a scratch register for a long range jump, the code
206 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
207 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
208 ; long; otherwise, it must be 6 bytes long.
210 ; All other instructions are two bytes long by default.
212 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
213 ;; but getattrtab doesn't understand this.
214 (define_attr "length" ""
215 (cond [(eq_attr "type" "cbranch")
216 (cond [(eq_attr "short_cbranch_p" "yes")
218 (eq_attr "med_cbranch_p" "yes")
220 (eq_attr "braf_cbranch_p" "yes")
222 ;; ??? using pc is not computed transitively.
223 (ne (match_dup 0) (match_dup 0))
226 (eq_attr "type" "jump")
227 (cond [(eq_attr "med_branch_p" "yes")
229 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
231 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
232 (symbol_ref "code_for_indirect_jump_scratch")))
233 (if_then_else (eq_attr "braf_branch_p" "yes")
236 (eq_attr "braf_branch_p" "yes")
238 ;; ??? using pc is not computed transitively.
239 (ne (match_dup 0) (match_dup 0))
244 ;; (define_function_unit {name} {num-units} {n-users} {test}
245 ;; {ready-delay} {issue-delay} [{conflict-list}])
247 ;; Load and store instructions save a cycle if they are aligned on a
248 ;; four byte boundary. Using a function unit for stores encourages
249 ;; gcc to separate load and store instructions by one instruction,
250 ;; which makes it more likely that the linker will be able to word
251 ;; align them when relaxing.
253 ;; Loads have a latency of two.
254 ;; However, call insns can have a delay slot, so that we want one more
255 ;; insn to be scheduled between the load of the function address and the call.
256 ;; This is equivalent to a latency of three.
257 ;; We cannot use a conflict list for this, because we need to distinguish
258 ;; between the actual call address and the function arguments.
259 ;; ADJUST_COST can only properly handle reductions of the cost, so we
260 ;; use a latency of three here.
261 ;; We only do this for SImode loads of general registers, to make the work
262 ;; for ADJUST_COST easier.
263 (define_function_unit "memory" 1 0
264 (and (eq_attr "issues" "1")
265 (eq_attr "type" "load_si,pcload_si"))
267 (define_function_unit "memory" 1 0
268 (and (eq_attr "issues" "1")
269 (eq_attr "type" "load,pcload,pload,store,pstore"))
272 (define_function_unit "int" 1 0
273 (and (eq_attr "issues" "1") (eq_attr "type" "arith3,arith3b")) 3 3)
275 (define_function_unit "int" 1 0
276 (and (eq_attr "issues" "1") (eq_attr "type" "dyn_shift")) 2 2)
278 (define_function_unit "int" 1 0
279 (and (eq_attr "issues" "1") (eq_attr "type" "!arith3,arith3b,dyn_shift")) 1 1)
281 ;; ??? These are approximations.
282 (define_function_unit "mpy" 1 0
283 (and (eq_attr "issues" "1") (eq_attr "type" "smpy")) 2 2)
284 (define_function_unit "mpy" 1 0
285 (and (eq_attr "issues" "1") (eq_attr "type" "dmpy")) 3 3)
287 (define_function_unit "fp" 1 0
288 (and (eq_attr "issues" "1") (eq_attr "type" "fp,fmove")) 2 1)
289 (define_function_unit "fp" 1 0
290 (and (eq_attr "issues" "1") (eq_attr "type" "fdiv")) 13 12)
294 ;; The SH4 is a dual-issue implementation, thus we have to multiply all
295 ;; costs by at least two.
296 ;; There will be single increments of the modeled that don't correspond
297 ;; to the actual target ;; whenever two insns to be issued depend one a
298 ;; single resource, and the scheduler picks to be the first one.
299 ;; If we multiplied the costs just by two, just two of these single
300 ;; increments would amount to an actual cycle. By picking a larger
301 ;; factor, we can ameliorate the effect; However, we then have to make sure
302 ;; that only two insns are modeled as issued per actual cycle.
303 ;; Moreover, we need a way to specify the latency of insns that don't
304 ;; use an actual function unit.
305 ;; We use an 'issue' function unit to do that, and a cost factor of 10.
307 (define_function_unit "issue" 2 0
308 (and (eq_attr "issues" "2") (eq_attr "type" "!nil,arith3"))
311 (define_function_unit "issue" 2 0
312 (and (eq_attr "issues" "2") (eq_attr "type" "arith3"))
315 ;; There is no point in providing exact scheduling information about branches,
316 ;; because they are at the starts / ends of basic blocks anyways.
318 ;; Some insns cannot be issued before/after another insn in the same cycle,
319 ;; irrespective of the type of the other insn.
321 ;; default is dual-issue, but can't be paired with an insn that
322 ;; uses multiple function units.
323 (define_function_unit "single_issue" 1 0
324 (and (eq_attr "issues" "2")
325 (eq_attr "type" "!smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul,call,sfunc,arith3,arith3b"))
327 [(eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul")])
329 (define_function_unit "single_issue" 1 0
330 (and (eq_attr "issues" "2")
331 (eq_attr "type" "smpy,dmpy,pload,pstore,dfp_cmp,gp_fpul"))
335 ;; arith3 insns are always pairable at the start, but not inecessarily at
336 ;; the end; however, there doesn;t seem to be a way to express that.
337 (define_function_unit "single_issue" 1 0
338 (and (eq_attr "issues" "2")
339 (eq_attr "type" "arith3"))
343 ;; arith3b insn are pairable at the end and have latency that prevents pairing
344 ;; with the following branch, but we don't want this latency be respected;
345 ;; When the following branch is immediately adjacent, we can redirect the
346 ;; internal branch, which is likly to be a larger win.
347 (define_function_unit "single_issue" 1 0
348 (and (eq_attr "issues" "2")
349 (eq_attr "type" "arith3b"))
353 ;; calls introduce a longisch delay that is likely to flush the pipelines.
354 (define_function_unit "single_issue" 1 0
355 (and (eq_attr "issues" "2")
356 (eq_attr "type" "call,sfunc"))
358 [(eq_attr "type" "!call") (eq_attr "type" "call")])
360 ;; Load and store instructions have no alignment peculiarities for the SH4,
361 ;; but they use the load-store unit, which they share with the fmove type
362 ;; insns (fldi[01]; fmov frn,frm; flds; fsts; fabs; fneg) .
363 ;; Loads have a latency of two.
364 ;; However, call insns can only paired with a preceding insn, and have
365 ;; a delay slot, so that we want two more insns to be scheduled between the
366 ;; load of the function address and the call. This is equivalent to a
368 ;; We cannot use a conflict list for this, because we need to distinguish
369 ;; between the actual call address and the function arguments.
370 ;; ADJUST_COST can only properly handle reductions of the cost, so we
371 ;; use a latency of three here, which gets multiplied by 10 to yield 30.
372 ;; We only do this for SImode loads of general registers, to make the work
373 ;; for ADJUST_COST easier.
375 ;; When specifying different latencies for different insns using the
376 ;; the same function unit, genattrtab.c assumes a 'FIFO constraint'
377 ;; so that the blockage is at least READY-COST (E) + 1 - READY-COST (C)
378 ;; for an executing insn E and a candidate insn C.
379 ;; Therefore, we define three different function units for load_store:
380 ;; load_store, load and load_si.
382 (define_function_unit "load_si" 1 0
383 (and (eq_attr "issues" "2")
384 (eq_attr "type" "load_si,pcload_si")) 30 10)
385 (define_function_unit "load" 1 0
386 (and (eq_attr "issues" "2")
387 (eq_attr "type" "load,pcload,pload")) 20 10)
388 (define_function_unit "load_store" 1 0
389 (and (eq_attr "issues" "2")
390 (eq_attr "type" "load_si,pcload_si,load,pcload,pload,store,pstore,fmove"))
393 (define_function_unit "int" 1 0
394 (and (eq_attr "issues" "2") (eq_attr "type" "arith,dyn_shift")) 10 10)
396 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
397 ;; spurious FIFO constraint; the multiply instructions use the "int"
398 ;; unit actually only for two cycles.
399 (define_function_unit "int" 1 0
400 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 20 20)
402 ;; We use a fictous "mpy" unit to express the actual latency.
403 (define_function_unit "mpy" 1 0
404 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 20)
406 ;; Again, we have to pretend a lower latency for the "int" unit to avoid a
407 ;; spurious FIFO constraint.
408 (define_function_unit "int" 1 0
409 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 10 10)
411 ;; We use a fictous "gp_fpul" unit to express the actual latency.
412 (define_function_unit "gp_fpul" 1 0
413 (and (eq_attr "issues" "2") (eq_attr "type" "gp_fpul")) 20 10)
415 ;; ??? multiply uses the floating point unit, but with a two cycle delay.
416 ;; Thus, a simple single-precision fp operation could finish if issued in
417 ;; the very next cycle, but stalls when issued two or three cycles later.
418 ;; Similarily, a divide / sqrt can work without stalls if issued in
419 ;; the very next cycle, while it would have to block if issued two or
420 ;; three cycles later.
421 ;; There is no way to model this with gcc's function units. This problem is
422 ;; actually mentioned in md.texi. Tackling this problem requires first that
423 ;; it is possible to speak about the target in an open discussion.
425 ;; However, simple double-precision operations always conflict.
427 (define_function_unit "fp" 1 0
428 (and (eq_attr "issues" "2") (eq_attr "type" "smpy,dmpy")) 40 40
429 [(eq_attr "type" "dfp_cmp,dfp_conv,dfp_arith")])
431 ;; The "fp" unit is for pipeline stages F1 and F2.
433 (define_function_unit "fp" 1 0
434 (and (eq_attr "issues" "2") (eq_attr "type" "fp")) 30 10)
436 ;; Again, we have to pretend a lower latency for the "fp" unit to avoid a
437 ;; spurious FIFO constraint; the bulk of the fdiv type insns executes in
439 (define_function_unit "fp" 1 0
440 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 30 10)
442 ;; The "fdiv" function unit models the aggregate effect of the F1, F2 and F3
443 ;; pipeline stages on the pipelining of fdiv/fsqrt insns.
444 ;; We also use it to give the actual latency here.
445 ;; fsqrt is actually one cycle faster than fdiv (and the value used here),
446 ;; but that will hardly matter in practice for scheduling.
447 (define_function_unit "fdiv" 1 0
448 (and (eq_attr "issues" "2") (eq_attr "type" "fdiv")) 120 100)
450 ;; There is again a late use of the "fp" unit by [d]fdiv type insns
451 ;; that we can't express.
453 (define_function_unit "fp" 1 0
454 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_cmp,dfp_conv")) 40 20)
456 (define_function_unit "fp" 1 0
457 (and (eq_attr "issues" "2") (eq_attr "type" "dfp_arith")) 80 60)
459 (define_function_unit "fp" 1 0
460 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 10)
462 (define_function_unit "fdiv" 1 0
463 (and (eq_attr "issues" "2") (eq_attr "type" "dfdiv")) 230 210)
465 ; Definitions for filling branch delay slots.
467 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
469 ;; ??? This should be (nil) instead of (const_int 0)
470 (define_attr "hit_stack" "yes,no"
471 (cond [(eq (symbol_ref "find_regno_note (insn, REG_INC, 15)") (const_int 0))
473 (const_string "yes")))
475 (define_attr "interrupt_function" "no,yes"
476 (const (symbol_ref "pragma_interrupt")))
478 (define_attr "in_delay_slot" "yes,no"
479 (cond [(eq_attr "type" "cbranch") (const_string "no")
480 (eq_attr "type" "pcload,pcload_si") (const_string "no")
481 (eq_attr "needs_delay_slot" "yes") (const_string "no")
482 (eq_attr "length" "2") (const_string "yes")
483 ] (const_string "no")))
485 (define_attr "is_sfunc" ""
486 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
489 (eq_attr "needs_delay_slot" "yes")
490 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
492 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
493 ;; and thus we can't put a pop instruction in its delay slot.
494 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
495 ;; instruction can go in the delay slot.
497 ;; Since a normal return (rts) implicitly uses the PR register,
498 ;; we can't allow PR register loads in an rts delay slot.
501 (eq_attr "type" "return")
502 [(and (eq_attr "in_delay_slot" "yes")
503 (ior (and (eq_attr "interrupt_function" "no")
504 (eq_attr "type" "!pload"))
505 (and (eq_attr "interrupt_function" "yes")
506 (eq_attr "hit_stack" "no")))) (nil) (nil)])
508 ;; Since a call implicitly uses the PR register, we can't allow
509 ;; a PR register store in a jsr delay slot.
512 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
513 [(and (eq_attr "in_delay_slot" "yes")
514 (eq_attr "type" "!pstore")) (nil) (nil)])
516 ;; Say that we have annulled true branches, since this gives smaller and
517 ;; faster code when branches are predicted as not taken.
520 (and (eq_attr "type" "cbranch")
521 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
522 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
524 ;; -------------------------------------------------------------------------
525 ;; SImode signed integer comparisons
526 ;; -------------------------------------------------------------------------
530 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
531 (match_operand:SI 1 "arith_operand" "L,r"))
536 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
537 ;; That would still allow reload to create cmpi instructions, but would
538 ;; perhaps allow forcing the constant into a register when that is better.
539 ;; Probably should use r0 for mem/imm compares, but force constant into a
540 ;; register for pseudo/imm compares.
542 (define_insn "cmpeqsi_t"
543 [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
544 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
551 (define_insn "cmpgtsi_t"
552 [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
553 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
559 (define_insn "cmpgesi_t"
560 [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
561 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
567 ;; -------------------------------------------------------------------------
568 ;; SImode unsigned integer comparisons
569 ;; -------------------------------------------------------------------------
571 (define_insn "cmpgeusi_t"
572 [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
573 (match_operand:SI 1 "arith_reg_operand" "r")))]
577 (define_insn "cmpgtusi_t"
578 [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
579 (match_operand:SI 1 "arith_reg_operand" "r")))]
583 ;; We save the compare operands in the cmpxx patterns and use them when
584 ;; we generate the branch.
586 (define_expand "cmpsi"
587 [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "")
588 (match_operand:SI 1 "arith_operand" "")))]
592 sh_compare_op0 = operands[0];
593 sh_compare_op1 = operands[1];
597 ;; -------------------------------------------------------------------------
598 ;; DImode signed integer comparisons
599 ;; -------------------------------------------------------------------------
601 ;; ??? Could get better scheduling by splitting the initial test from the
602 ;; rest of the insn after reload. However, the gain would hardly justify
603 ;; the sh.md size increase necessary to do that.
607 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
608 (match_operand:DI 1 "arith_operand" "r"))
611 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
613 [(set_attr "length" "6")
614 (set_attr "type" "arith3b")])
616 (define_insn "cmpeqdi_t"
617 [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
618 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
621 return output_branchy_insn
624 ? \"cmp/eq\\t%S1,%S0\;bf\\t%l9\;cmp/eq\\t%R1,%R0\"
625 : \"tst\\t%S0,%S0\;bf\\t%l9\;tst\\t%R0,%R0\"),
627 [(set_attr "length" "6")
628 (set_attr "type" "arith3b")])
630 (define_insn "cmpgtdi_t"
631 [(set (reg:SI 18) (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
632 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
635 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
636 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
637 [(set_attr "length" "8")
638 (set_attr "type" "arith3")])
640 (define_insn "cmpgedi_t"
641 [(set (reg:SI 18) (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
642 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
645 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
647 [(set_attr "length" "8,2")
648 (set_attr "type" "arith3,arith")])
650 ;; -------------------------------------------------------------------------
651 ;; DImode unsigned integer comparisons
652 ;; -------------------------------------------------------------------------
654 (define_insn "cmpgeudi_t"
655 [(set (reg:SI 18) (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
656 (match_operand:DI 1 "arith_reg_operand" "r")))]
658 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
659 [(set_attr "length" "8")
660 (set_attr "type" "arith3")])
662 (define_insn "cmpgtudi_t"
663 [(set (reg:SI 18) (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
664 (match_operand:DI 1 "arith_reg_operand" "r")))]
666 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
667 [(set_attr "length" "8")
668 (set_attr "type" "arith3")])
670 ;; We save the compare operands in the cmpxx patterns and use them when
671 ;; we generate the branch.
673 (define_expand "cmpdi"
674 [(set (reg:SI 18) (compare (match_operand:DI 0 "arith_operand" "")
675 (match_operand:DI 1 "arith_operand" "")))]
679 sh_compare_op0 = operands[0];
680 sh_compare_op1 = operands[1];
684 ;; -------------------------------------------------------------------------
685 ;; Addition instructions
686 ;; -------------------------------------------------------------------------
688 ;; ??? This should be a define expand.
690 (define_insn "adddi3"
691 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
692 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
693 (match_operand:DI 2 "arith_reg_operand" "r")))
694 (clobber (reg:SI 18))]
697 [(set_attr "length" "6")])
700 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
701 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
702 (match_operand:DI 2 "arith_reg_operand" "r")))
703 (clobber (reg:SI 18))]
708 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
709 high0 = gen_rtx (REG, SImode,
710 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
711 high2 = gen_rtx (REG, SImode,
712 true_regnum (operands[2]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
713 emit_insn (gen_clrt ());
714 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
715 emit_insn (gen_addc1 (high0, high0, high2));
720 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
721 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
722 (match_operand:SI 2 "arith_reg_operand" "r"))
725 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
728 [(set_attr "type" "arith")])
731 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
732 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
733 (match_operand:SI 2 "arith_reg_operand" "r"))
735 (clobber (reg:SI 18))]
738 [(set_attr "type" "arith")])
740 (define_insn "addsi3"
741 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
742 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
743 (match_operand:SI 2 "arith_operand" "rI")))]
746 [(set_attr "type" "arith")])
748 ;; -------------------------------------------------------------------------
749 ;; Subtraction instructions
750 ;; -------------------------------------------------------------------------
752 ;; ??? This should be a define expand.
754 (define_insn "subdi3"
755 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
756 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
757 (match_operand:DI 2 "arith_reg_operand" "r")))
758 (clobber (reg:SI 18))]
761 [(set_attr "length" "6")])
764 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
765 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
766 (match_operand:DI 2 "arith_reg_operand" "r")))
767 (clobber (reg:SI 18))]
772 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
773 high0 = gen_rtx (REG, SImode,
774 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
775 high2 = gen_rtx (REG, SImode,
776 true_regnum (operands[2]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
777 emit_insn (gen_clrt ());
778 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
779 emit_insn (gen_subc1 (high0, high0, high2));
784 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
785 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
786 (match_operand:SI 2 "arith_reg_operand" "r"))
789 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
792 [(set_attr "type" "arith")])
795 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
796 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
797 (match_operand:SI 2 "arith_reg_operand" "r"))
799 (clobber (reg:SI 18))]
802 [(set_attr "type" "arith")])
804 (define_insn "*subsi3_internal"
805 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
806 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
807 (match_operand:SI 2 "arith_reg_operand" "r")))]
810 [(set_attr "type" "arith")])
812 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
813 ;; will sometimes save one instruction. Otherwise we might get
814 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
817 (define_expand "subsi3"
818 [(set (match_operand:SI 0 "arith_reg_operand" "")
819 (minus:SI (match_operand:SI 1 "arith_operand" "")
820 (match_operand:SI 2 "arith_reg_operand" "")))]
824 if (GET_CODE (operands[1]) == CONST_INT)
826 emit_insn (gen_negsi2 (operands[0], operands[2]));
827 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
832 ;; -------------------------------------------------------------------------
833 ;; Division instructions
834 ;; -------------------------------------------------------------------------
836 ;; We take advantage of the library routines which don't clobber as many
837 ;; registers as a normal function call would.
839 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
840 ;; also has an effect on the register that holds the address of the sfunc.
841 ;; To make this work, we have an extra dummy insns that shows the use
842 ;; of this register for reorg.
844 (define_insn "use_sfunc_addr"
845 [(set (reg:SI 17) (unspec [(match_operand:SI 0 "register_operand" "r")] 5))]
848 [(set_attr "length" "0")])
850 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
851 ;; hard register 0. If we used hard register 0, then the next instruction
852 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
853 ;; gets allocated to a stack slot that needs its address reloaded, then
854 ;; there is nothing to prevent reload from using r0 to reload the address.
855 ;; This reload would clobber the value in r0 we are trying to store.
856 ;; If we let reload allocate r0, then this problem can never happen.
859 [(set (match_operand:SI 0 "register_operand" "=z")
860 (udiv:SI (reg:SI 4) (reg:SI 5)))
861 (clobber (reg:SI 18))
862 (clobber (reg:SI 17))
864 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
867 [(set_attr "type" "sfunc")
868 (set_attr "needs_delay_slot" "yes")])
870 (define_insn "udivsi3_i4"
871 [(set (match_operand:SI 0 "register_operand" "=y")
872 (udiv:SI (reg:SI 4) (reg:SI 5)))
873 (clobber (reg:SI 17))
874 (clobber (reg:DF 24))
875 (clobber (reg:DF 26))
876 (clobber (reg:DF 28))
882 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
883 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
885 [(set_attr "type" "sfunc")
886 (set_attr "needs_delay_slot" "yes")])
888 (define_insn "udivsi3_i4_single"
889 [(set (match_operand:SI 0 "register_operand" "=y")
890 (udiv:SI (reg:SI 4) (reg:SI 5)))
891 (clobber (reg:SI 17))
892 (clobber (reg:DF 24))
893 (clobber (reg:DF 26))
894 (clobber (reg:DF 28))
899 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
900 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
902 [(set_attr "type" "sfunc")
903 (set_attr "needs_delay_slot" "yes")])
905 (define_expand "udivsi3"
906 [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
907 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
908 (set (match_dup 3) (symbol_ref:SI "__udivsi3"))
909 (parallel [(set (match_operand:SI 0 "register_operand" "")
912 (clobber (reg:SI 18))
913 (clobber (reg:SI 17))
915 (use (match_dup 3))])]
919 operands[3] = gen_reg_rtx(SImode);
922 emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
923 emit_move_insn (gen_rtx (REG, SImode, 5), operands[2]);
924 emit_move_insn (operands[3],
925 gen_rtx_SYMBOL_REF (SImode, \"__udivsi3_i4\"));
926 if (TARGET_FPU_SINGLE)
927 emit_insn (gen_udivsi3_i4_single (operands[0], operands[3]));
929 emit_insn (gen_udivsi3_i4 (operands[0], operands[3]));
935 [(set (match_operand:SI 0 "register_operand" "=z")
936 (div:SI (reg:SI 4) (reg:SI 5)))
937 (clobber (reg:SI 18))
938 (clobber (reg:SI 17))
942 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
945 [(set_attr "type" "sfunc")
946 (set_attr "needs_delay_slot" "yes")])
948 (define_insn "divsi3_i4"
949 [(set (match_operand:SI 0 "register_operand" "=y")
950 (div:SI (reg:SI 4) (reg:SI 5)))
951 (clobber (reg:SI 17))
952 (clobber (reg:DF 24))
953 (clobber (reg:DF 26))
955 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
956 "TARGET_SH4 && ! TARGET_FPU_SINGLE"
958 [(set_attr "type" "sfunc")
959 (set_attr "needs_delay_slot" "yes")])
961 (define_insn "divsi3_i4_single"
962 [(set (match_operand:SI 0 "register_operand" "=y")
963 (div:SI (reg:SI 4) (reg:SI 5)))
964 (clobber (reg:SI 17))
965 (clobber (reg:DF 24))
966 (clobber (reg:DF 26))
968 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
969 "TARGET_HARD_SH4 && TARGET_FPU_SINGLE"
971 [(set_attr "type" "sfunc")
972 (set_attr "needs_delay_slot" "yes")])
974 (define_expand "divsi3"
975 [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
976 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
977 (set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
978 (parallel [(set (match_operand:SI 0 "register_operand" "")
981 (clobber (reg:SI 18))
982 (clobber (reg:SI 17))
986 (use (match_dup 3))])]
990 operands[3] = gen_reg_rtx(SImode);
993 emit_move_insn (gen_rtx (REG, SImode, 4), operands[1]);
994 emit_move_insn (gen_rtx (REG, SImode, 5), operands[2]);
995 emit_move_insn (operands[3],
996 gen_rtx_SYMBOL_REF (SImode, \"__sdivsi3_i4\"));
997 if (TARGET_FPU_SINGLE)
998 emit_insn (gen_divsi3_i4_single (operands[0], operands[3]));
1000 emit_insn (gen_divsi3_i4 (operands[0], operands[3]));
1005 ;; -------------------------------------------------------------------------
1006 ;; Multiplication instructions
1007 ;; -------------------------------------------------------------------------
1011 (mult:SI (zero_extend:SI (match_operand:HI 0 "arith_reg_operand" "r"))
1012 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))))]
1015 [(set_attr "type" "smpy")])
1019 (mult:SI (sign_extend:SI
1020 (match_operand:HI 0 "arith_reg_operand" "r"))
1022 (match_operand:HI 1 "arith_reg_operand" "r"))))]
1025 [(set_attr "type" "smpy")])
1027 (define_expand "mulhisi3"
1029 (mult:SI (sign_extend:SI
1030 (match_operand:HI 1 "arith_reg_operand" ""))
1032 (match_operand:HI 2 "arith_reg_operand" ""))))
1033 (set (match_operand:SI 0 "arith_reg_operand" "")
1038 (define_expand "umulhisi3"
1040 (mult:SI (zero_extend:SI
1041 (match_operand:HI 1 "arith_reg_operand" ""))
1043 (match_operand:HI 2 "arith_reg_operand" ""))))
1044 (set (match_operand:SI 0 "arith_reg_operand" "")
1049 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
1050 ;; a call to a routine which clobbers known registers.
1053 [(set (match_operand:SI 1 "register_operand" "=z")
1054 (mult:SI (reg:SI 4) (reg:SI 5)))
1055 (clobber (reg:SI 21))
1056 (clobber (reg:SI 18))
1057 (clobber (reg:SI 17))
1058 (clobber (reg:SI 3))
1059 (clobber (reg:SI 2))
1060 (clobber (reg:SI 1))
1061 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
1064 [(set_attr "type" "sfunc")
1065 (set_attr "needs_delay_slot" "yes")])
1067 (define_expand "mulsi3_call"
1068 [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
1069 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
1070 (parallel[(set (match_operand:SI 0 "register_operand" "")
1073 (clobber (reg:SI 21))
1074 (clobber (reg:SI 18))
1075 (clobber (reg:SI 17))
1076 (clobber (reg:SI 3))
1077 (clobber (reg:SI 2))
1078 (clobber (reg:SI 1))
1079 (use (match_operand:SI 3 "register_operand" ""))])]
1083 (define_insn "mul_l"
1085 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
1086 (match_operand:SI 1 "arith_reg_operand" "r")))]
1089 [(set_attr "type" "dmpy")])
1091 (define_expand "mulsi3"
1093 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
1094 (match_operand:SI 2 "arith_reg_operand" "")))
1095 (set (match_operand:SI 0 "arith_reg_operand" "")
1104 /* The address must be set outside the libcall,
1105 since it goes into a pseudo. */
1106 rtx addr = force_reg (SImode, gen_rtx_SYMBOL_REF (SImode, \"__mulsi3\"));
1107 rtx insns = gen_mulsi3_call (operands[0], operands[1], operands[2], addr);
1108 first = XVECEXP (insns, 0, 0);
1109 last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1114 rtx macl = gen_rtx_REG (SImode, MACL_REG);
1116 first = emit_insn (gen_mul_l (operands[1], operands[2]));
1117 /* consec_sets_giv can only recognize the first insn that sets a
1118 giv as the giv insn. So we must tag this also with a REG_EQUAL
1120 last = emit_insn (gen_movsi_i ((operands[0]), macl));
1122 /* Wrap the sequence in REG_LIBCALL / REG_RETVAL notes so that loop
1123 invariant code motion can move it. */
1124 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, REG_NOTES (first));
1125 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
1129 (define_insn "mulsidi3_i"
1131 (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1132 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))))]
1135 [(set_attr "type" "dmpy")])
1137 (define_expand "mulsidi3"
1139 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1140 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1141 (set (match_operand:DI 0 "arith_reg_operand" "")
1146 /* We must swap the two words when copying them from MACH/MACL to the
1148 if (TARGET_LITTLE_ENDIAN)
1150 rtx low_dst = operand_subword (operands[0], 0, 1, DImode);
1151 rtx high_dst = operand_subword (operands[0], 1, 1, DImode);
1153 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
1155 emit_insn (gen_rtx (CLOBBER, VOIDmode, operands[0]));
1156 emit_move_insn (low_dst, gen_rtx (REG, SImode, 21));
1157 emit_move_insn (high_dst, gen_rtx (REG, SImode, 20));
1162 (define_insn "umulsidi3_i"
1164 (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1165 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))))]
1168 [(set_attr "type" "dmpy")])
1170 (define_expand "umulsidi3"
1172 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1173 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
1174 (set (match_operand:DI 0 "arith_reg_operand" "")
1179 /* We must swap the two words when copying them from MACH/MACL to the
1181 if (TARGET_LITTLE_ENDIAN)
1183 rtx low_dst = operand_subword (operands[0], 0, 1, DImode);
1184 rtx high_dst = operand_subword (operands[0], 1, 1, DImode);
1186 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
1188 emit_insn (gen_rtx (CLOBBER, VOIDmode, operands[0]));
1189 emit_move_insn (low_dst, gen_rtx (REG, SImode, 21));
1190 emit_move_insn (high_dst, gen_rtx (REG, SImode, 20));
1198 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1199 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1201 (clobber (reg:SI 21))]
1204 [(set_attr "type" "dmpy")])
1206 (define_expand "smulsi3_highpart"
1207 [(parallel [(set (reg:SI 20)
1209 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1210 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1212 (clobber (reg:SI 21))])
1213 (set (match_operand:SI 0 "arith_reg_operand" "")
1221 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
1222 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
1224 (clobber (reg:SI 21))]
1227 [(set_attr "type" "dmpy")])
1229 (define_expand "umulsi3_highpart"
1230 [(parallel [(set (reg:SI 20)
1232 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
1233 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
1235 (clobber (reg:SI 21))])
1236 (set (match_operand:SI 0 "arith_reg_operand" "")
1241 ;; -------------------------------------------------------------------------
1242 ;; Logical operations
1243 ;; -------------------------------------------------------------------------
1246 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1247 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1248 (match_operand:SI 2 "logical_operand" "r,L")))]
1251 [(set_attr "type" "arith")])
1253 ;; If the constant is 255, then emit a extu.b instruction instead of an
1254 ;; and, since that will give better code.
1256 (define_expand "andsi3"
1257 [(set (match_operand:SI 0 "arith_reg_operand" "")
1258 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
1259 (match_operand:SI 2 "logical_operand" "")))]
1263 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
1265 emit_insn (gen_zero_extendqisi2 (operands[0],
1266 gen_lowpart (QImode, operands[1])));
1271 (define_insn "iorsi3"
1272 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
1273 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1274 (match_operand:SI 2 "logical_operand" "r,L")))]
1277 [(set_attr "type" "arith")])
1279 (define_insn "xorsi3"
1280 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
1281 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
1282 (match_operand:SI 2 "logical_operand" "L,r")))]
1285 [(set_attr "type" "arith")])
1287 ;; -------------------------------------------------------------------------
1288 ;; Shifts and rotates
1289 ;; -------------------------------------------------------------------------
1291 (define_insn "rotlsi3_1"
1292 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1293 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1296 (lshiftrt:SI (match_dup 1) (const_int 31)))]
1299 [(set_attr "type" "arith")])
1301 (define_insn "rotlsi3_31"
1302 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1303 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
1305 (clobber (reg:SI 18))]
1308 [(set_attr "type" "arith")])
1310 (define_insn "rotlsi3_16"
1311 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1312 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
1316 [(set_attr "type" "arith")])
1318 (define_expand "rotlsi3"
1319 [(set (match_operand:SI 0 "arith_reg_operand" "")
1320 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
1321 (match_operand:SI 2 "immediate_operand" "")))]
1325 static char rot_tab[] = {
1326 000, 000, 000, 000, 000, 000, 010, 001,
1327 001, 001, 011, 013, 003, 003, 003, 003,
1328 003, 003, 003, 003, 003, 013, 012, 002,
1329 002, 002, 010, 000, 000, 000, 000, 000,
1334 if (GET_CODE (operands[2]) != CONST_INT)
1336 count = INTVAL (operands[2]);
1337 choice = rot_tab[count];
1338 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
1344 emit_move_insn (operands[0], operands[1]);
1345 count -= (count & 16) * 2;
1348 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
1355 parts[0] = gen_reg_rtx (SImode);
1356 parts[1] = gen_reg_rtx (SImode);
1357 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
1358 parts[choice-1] = operands[1];
1359 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
1360 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
1361 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
1362 count = (count & ~16) - 8;
1366 for (; count > 0; count--)
1367 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
1368 for (; count < 0; count++)
1369 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
1374 (define_insn "*rotlhi3_8"
1375 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1376 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
1380 [(set_attr "type" "arith")])
1382 (define_expand "rotlhi3"
1383 [(set (match_operand:HI 0 "arith_reg_operand" "")
1384 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1385 (match_operand:HI 2 "immediate_operand" "")))]
1389 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1396 (define_insn "ashlsi3_d"
1397 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1398 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1399 (match_operand:SI 2 "arith_reg_operand" "r")))]
1402 [(set_attr "type" "dyn_shift")])
1404 (define_insn "ashlsi3_k"
1405 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
1406 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
1407 (match_operand:SI 2 "const_int_operand" "M,K")))]
1408 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1412 [(set_attr "type" "arith")])
1414 (define_insn "ashlhi3_k"
1415 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1416 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1417 (match_operand:HI 2 "const_int_operand" "M,K")))]
1418 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1422 [(set_attr "type" "arith")])
1424 (define_insn "ashlsi3_n"
1425 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1426 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1427 (match_operand:SI 2 "const_int_operand" "n")))
1428 (clobber (reg:SI 18))]
1429 "! sh_dynamicalize_shift_p (operands[2])"
1431 [(set (attr "length")
1432 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1434 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1436 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1438 (const_string "8")))
1439 (set_attr "type" "arith")])
1442 [(set (match_operand:SI 0 "arith_reg_operand" "")
1443 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1444 (match_operand:SI 2 "const_int_operand" "n")))
1445 (clobber (reg:SI 18))]
1450 gen_shifty_op (ASHIFT, operands);
1454 (define_expand "ashlsi3"
1455 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1456 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1457 (match_operand:SI 2 "nonmemory_operand" "")))
1458 (clobber (reg:SI 18))])]
1462 if (GET_CODE (operands[2]) == CONST_INT
1463 && sh_dynamicalize_shift_p (operands[2]))
1464 operands[2] = force_reg (SImode, operands[2]);
1465 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1467 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
1470 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1474 (define_insn "ashlhi3"
1475 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1476 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1477 (match_operand:HI 2 "const_int_operand" "n")))
1478 (clobber (reg:SI 18))]
1481 [(set (attr "length")
1482 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1484 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1486 (const_string "6")))
1487 (set_attr "type" "arith")])
1490 [(set (match_operand:HI 0 "arith_reg_operand" "")
1491 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1492 (match_operand:HI 2 "const_int_operand" "n")))
1493 (clobber (reg:SI 18))]
1498 gen_shifty_hi_op (ASHIFT, operands);
1503 ; arithmetic shift right
1506 (define_insn "ashrsi3_k"
1507 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1508 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1509 (match_operand:SI 2 "const_int_operand" "M")))
1510 (clobber (reg:SI 18))]
1511 "INTVAL (operands[2]) == 1"
1513 [(set_attr "type" "arith")])
1515 ;; We can't do HImode right shifts correctly unless we start out with an
1516 ;; explicit zero / sign extension; doing that would result in worse overall
1517 ;; code, so just let the machine independent code widen the mode.
1518 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
1521 ;; ??? This should be a define expand.
1523 (define_insn "ashrsi2_16"
1524 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1525 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1529 [(set_attr "length" "4")])
1532 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1533 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1536 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1537 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1538 "operands[2] = gen_lowpart (HImode, operands[0]);")
1540 ;; ??? This should be a define expand.
1542 (define_insn "ashrsi2_31"
1543 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1544 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1546 (clobber (reg:SI 18))]
1549 [(set_attr "length" "4")])
1552 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1553 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1555 (clobber (reg:SI 18))]
1560 emit_insn (gen_ashlsi_c (operands[0], operands[1]));
1561 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1565 (define_insn "ashlsi_c"
1566 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1567 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1568 (set (reg:SI 18) (lt:SI (match_dup 1)
1572 [(set_attr "type" "arith")])
1574 (define_insn "ashrsi3_d"
1575 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1576 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1577 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1580 [(set_attr "type" "dyn_shift")])
1582 (define_insn "ashrsi3_n"
1584 (ashiftrt:SI (reg:SI 4)
1585 (match_operand:SI 0 "const_int_operand" "i")))
1586 (clobber (reg:SI 18))
1587 (clobber (reg:SI 17))
1588 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1591 [(set_attr "type" "sfunc")
1592 (set_attr "needs_delay_slot" "yes")])
1594 (define_expand "ashrsi3"
1595 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1596 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1597 (match_operand:SI 2 "nonmemory_operand" "")))
1598 (clobber (reg:SI 18))])]
1600 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1602 ;; logical shift right
1604 (define_insn "lshrsi3_d"
1605 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1606 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1607 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1610 [(set_attr "type" "dyn_shift")])
1612 ;; Only the single bit shift clobbers the T bit.
1614 (define_insn "lshrsi3_m"
1615 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1616 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1617 (match_operand:SI 2 "const_int_operand" "M")))
1618 (clobber (reg:SI 18))]
1619 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1621 [(set_attr "type" "arith")])
1623 (define_insn "lshrsi3_k"
1624 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1625 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1626 (match_operand:SI 2 "const_int_operand" "K")))]
1627 "CONST_OK_FOR_K (INTVAL (operands[2]))
1628 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1630 [(set_attr "type" "arith")])
1632 (define_insn "lshrsi3_n"
1633 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1634 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1635 (match_operand:SI 2 "const_int_operand" "n")))
1636 (clobber (reg:SI 18))]
1637 "! sh_dynamicalize_shift_p (operands[2])"
1639 [(set (attr "length")
1640 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1642 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1644 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1646 (const_string "8")))
1647 (set_attr "type" "arith")])
1650 [(set (match_operand:SI 0 "arith_reg_operand" "")
1651 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1652 (match_operand:SI 2 "const_int_operand" "n")))
1653 (clobber (reg:SI 18))]
1658 gen_shifty_op (LSHIFTRT, operands);
1662 (define_expand "lshrsi3"
1663 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1664 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1665 (match_operand:SI 2 "nonmemory_operand" "")))
1666 (clobber (reg:SI 18))])]
1670 if (GET_CODE (operands[2]) == CONST_INT
1671 && sh_dynamicalize_shift_p (operands[2]))
1672 operands[2] = force_reg (SImode, operands[2]);
1673 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1675 rtx count = copy_to_mode_reg (SImode, operands[2]);
1676 emit_insn (gen_negsi2 (count, count));
1677 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1680 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1684 ;; ??? This should be a define expand.
1686 (define_insn "ashldi3_k"
1687 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1688 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1690 (clobber (reg:SI 18))]
1692 "shll %R0\;rotcl %S0"
1693 [(set_attr "length" "4")
1694 (set_attr "type" "arith")])
1696 (define_expand "ashldi3"
1697 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1698 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1699 (match_operand:DI 2 "immediate_operand" "")))
1700 (clobber (reg:SI 18))])]
1702 "{ if (GET_CODE (operands[2]) != CONST_INT
1703 || INTVAL (operands[2]) != 1) FAIL;} ")
1705 ;; ??? This should be a define expand.
1707 (define_insn "lshrdi3_k"
1708 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1709 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1711 (clobber (reg:SI 18))]
1713 "shlr %S0\;rotcr %R0"
1714 [(set_attr "length" "4")
1715 (set_attr "type" "arith")])
1717 (define_expand "lshrdi3"
1718 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1719 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1720 (match_operand:DI 2 "immediate_operand" "")))
1721 (clobber (reg:SI 18))])]
1723 "{ if (GET_CODE (operands[2]) != CONST_INT
1724 || INTVAL (operands[2]) != 1) FAIL;} ")
1726 ;; ??? This should be a define expand.
1728 (define_insn "ashrdi3_k"
1729 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1730 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1732 (clobber (reg:SI 18))]
1734 "shar %S0\;rotcr %R0"
1735 [(set_attr "length" "4")
1736 (set_attr "type" "arith")])
1738 (define_expand "ashrdi3"
1739 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1740 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1741 (match_operand:DI 2 "immediate_operand" "")))
1742 (clobber (reg:SI 18))])]
1744 "{ if (GET_CODE (operands[2]) != CONST_INT
1745 || INTVAL (operands[2]) != 1) FAIL; } ")
1747 ;; combined left/right shift
1750 [(set (match_operand:SI 0 "register_operand" "")
1751 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1752 (match_operand:SI 2 "const_int_operand" "n"))
1753 (match_operand:SI 3 "const_int_operand" "n")))]
1754 "(unsigned)INTVAL (operands[2]) < 32"
1756 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
1760 [(set (match_operand:SI 0 "register_operand" "")
1761 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1762 (match_operand:SI 2 "const_int_operand" "n"))
1763 (match_operand:SI 3 "const_int_operand" "n")))
1764 (clobber (reg:SI 18))]
1765 "(unsigned)INTVAL (operands[2]) < 32"
1767 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
1771 [(set (match_operand:SI 0 "register_operand" "=r")
1772 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1773 (match_operand:SI 2 "const_int_operand" "n"))
1774 (match_operand:SI 3 "const_int_operand" "n")))
1775 (clobber (reg:SI 18))]
1776 "shl_and_kind (operands[2], operands[3], 0) == 1"
1778 [(set (attr "length")
1779 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
1781 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
1783 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
1785 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
1787 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
1789 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
1791 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
1792 (const_string "16")]
1793 (const_string "18")))
1794 (set_attr "type" "arith")])
1797 [(set (match_operand:SI 0 "register_operand" "=z")
1798 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1799 (match_operand:SI 2 "const_int_operand" "n"))
1800 (match_operand:SI 3 "const_int_operand" "n")))
1801 (clobber (reg:SI 18))]
1802 "shl_and_kind (operands[2], operands[3], 0) == 2"
1804 [(set (attr "length")
1805 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
1807 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
1809 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
1811 (const_string "10")))
1812 (set_attr "type" "arith")])
1814 ;; shift left / and combination with a scratch register: The combine pass
1815 ;; does not accept the individual instructions, even though they are
1816 ;; cheap. But it needs a precise description so that it is usable after
1818 (define_insn "and_shl_scratch"
1819 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1820 (lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
1821 (match_operand:SI 2 "const_int_operand" "N,n"))
1822 (match_operand:SI 3 "" "0,r"))
1823 (match_operand:SI 4 "const_int_operand" "n,n"))
1824 (match_operand:SI 5 "const_int_operand" "n,n")))
1825 (clobber (reg:SI 18))]
1828 [(set (attr "length")
1829 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
1831 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
1833 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
1835 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
1836 (const_string "10")]
1837 (const_string "12")))
1838 (set_attr "type" "arith")])
1841 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1842 (lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
1843 (match_operand:SI 2 "const_int_operand" "N,n"))
1844 (match_operand:SI 3 "register_operand" "0,r"))
1845 (match_operand:SI 4 "const_int_operand" "n,n"))
1846 (match_operand:SI 5 "const_int_operand" "n,n")))
1847 (clobber (reg:SI 18))]
1852 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
1854 if (INTVAL (operands[2]))
1856 gen_shifty_op (LSHIFTRT, operands);
1858 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
1859 operands[2] = operands[4];
1860 gen_shifty_op (ASHIFT, operands);
1861 if (INTVAL (operands[5]))
1863 operands[2] = operands[5];
1864 gen_shifty_op (LSHIFTRT, operands);
1869 ;; signed left/right shift combination.
1871 [(set (match_operand:SI 0 "register_operand" "=r")
1872 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1873 (match_operand:SI 2 "const_int_operand" "n"))
1874 (match_operand:SI 3 "const_int_operand" "n")
1876 (clobber (reg:SI 18))]
1879 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
1882 (define_insn "shl_sext_ext"
1883 [(set (match_operand:SI 0 "register_operand" "=r")
1884 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1885 (match_operand:SI 2 "const_int_operand" "n"))
1886 (match_operand:SI 3 "const_int_operand" "n")
1888 (clobber (reg:SI 18))]
1889 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
1891 [(set (attr "length")
1892 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
1894 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
1896 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
1898 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
1900 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
1902 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
1904 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
1906 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
1907 (const_string "16")]
1908 (const_string "18")))
1909 (set_attr "type" "arith")])
1911 (define_insn "shl_sext_sub"
1912 [(set (match_operand:SI 0 "register_operand" "=z")
1913 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1914 (match_operand:SI 2 "const_int_operand" "n"))
1915 (match_operand:SI 3 "const_int_operand" "n")
1917 (clobber (reg:SI 18))]
1918 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
1920 [(set (attr "length")
1921 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
1923 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
1925 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
1927 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
1928 (const_string "12")]
1929 (const_string "14")))
1930 (set_attr "type" "arith")])
1932 ;; These patterns are found in expansions of DImode shifts by 16, and
1933 ;; allow the xtrct instruction to be generated from C source.
1935 (define_insn "xtrct_left"
1936 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1937 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
1939 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
1943 [(set_attr "type" "arith")])
1945 (define_insn "xtrct_right"
1946 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1947 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1949 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
1953 [(set_attr "type" "arith")])
1955 ;; -------------------------------------------------------------------------
1957 ;; -------------------------------------------------------------------------
1960 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1961 (neg:SI (plus:SI (reg:SI 18)
1962 (match_operand:SI 1 "arith_reg_operand" "r"))))
1964 (ne:SI (ior:SI (reg:SI 18) (match_dup 1))
1968 [(set_attr "type" "arith")])
1970 (define_expand "negdi2"
1971 [(set (match_operand:DI 0 "arith_reg_operand" "")
1972 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
1973 (clobber (reg:SI 18))]
1977 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
1978 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
1980 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
1981 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
1983 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
1984 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
1986 emit_insn (gen_clrt ());
1987 emit_insn (gen_negc (low_dst, low_src));
1988 emit_insn (gen_negc (high_dst, high_src));
1992 (define_insn "negsi2"
1993 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1994 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
1997 [(set_attr "type" "arith")])
1999 (define_insn "one_cmplsi2"
2000 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2001 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
2004 [(set_attr "type" "arith")])
2006 ;; -------------------------------------------------------------------------
2007 ;; Zero extension instructions
2008 ;; -------------------------------------------------------------------------
2010 (define_insn "zero_extendhisi2"
2011 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2012 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
2015 [(set_attr "type" "arith")])
2017 (define_insn "zero_extendqisi2"
2018 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2019 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
2022 [(set_attr "type" "arith")])
2024 (define_insn "zero_extendqihi2"
2025 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
2026 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
2029 [(set_attr "type" "arith")])
2031 ;; -------------------------------------------------------------------------
2032 ;; Sign extension instructions
2033 ;; -------------------------------------------------------------------------
2035 ;; ??? This should be a define expand.
2036 ;; ??? Or perhaps it should be dropped?
2038 /* There is no point in defining extendsidi2; convert_move generates good
2041 (define_insn "extendhisi2"
2042 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2043 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
2048 [(set_attr "type" "arith,load")])
2050 (define_insn "extendqisi2"
2051 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
2052 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2057 [(set_attr "type" "arith,load")])
2059 (define_insn "extendqihi2"
2060 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
2061 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
2066 [(set_attr "type" "arith,load")])
2068 ;; -------------------------------------------------------------------------
2069 ;; Move instructions
2070 ;; -------------------------------------------------------------------------
2072 ;; define push and pop so it is easy for sh.c
2074 (define_expand "push"
2075 [(set (mem:SI (pre_dec:SI (reg:SI 15)))
2076 (match_operand:SI 0 "register_operand" "r,l,x"))]
2080 (define_expand "pop"
2081 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
2082 (mem:SI (post_inc:SI (reg:SI 15))))]
2086 (define_expand "push_e"
2087 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI 15)))
2088 (match_operand:SF 0 "" ""))
2090 (clobber (scratch:SI))])]
2094 (define_insn "push_fpul"
2095 [(set (mem:SF (pre_dec:SI (reg:SI 15))) (reg:SF 22))]
2098 [(set_attr "type" "store")
2099 (set_attr "hit_stack" "yes")])
2101 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
2103 (define_expand "push_4"
2104 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI 15))) (match_operand:DF 0 "" ""))
2106 (clobber (scratch:SI))])]
2110 (define_expand "pop_e"
2111 [(parallel [(set (match_operand:SF 0 "" "")
2112 (mem:SF (post_inc:SI (reg:SI 15))))
2114 (clobber (scratch:SI))])]
2118 (define_insn "pop_fpul"
2119 [(set (reg:SF 22) (mem:SF (post_inc:SI (reg:SI 15))))]
2122 [(set_attr "type" "load")
2123 (set_attr "hit_stack" "yes")])
2125 (define_expand "pop_4"
2126 [(parallel [(set (match_operand:DF 0 "" "")
2127 (mem:DF (post_inc:SI (reg:SI 15))))
2129 (clobber (scratch:SI))])]
2133 ;; These two patterns can happen as the result of optimization, when
2134 ;; comparisons get simplified to a move of zero or 1 into the T reg.
2135 ;; They don't disappear completely, because the T reg is a fixed hard reg.
2138 [(set (reg:SI 18) (const_int 0))]
2143 [(set (reg:SI 18) (const_int 1))]
2147 ;; t/r must come after r/r, lest reload will try to reload stuff like
2148 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI 15 r15) (const_int 12)) 0) 0)
2149 ;; (made from (set (subreg:SI (reg:QI 73) 0) ) into T.
2150 (define_insn "movsi_i"
2151 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,r")
2152 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,i"))]
2155 && (register_operand (operands[0], SImode)
2156 || register_operand (operands[1], SImode))"
2171 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,pcload_si")
2172 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*")])
2174 ;; t/r must come after r/r, lest reload will try to reload stuff like
2175 ;; (subreg:SI (reg:SF 38 fr14) 0) into T (compiling stdlib/strtod.c -m3e -O2)
2176 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
2177 ;; will require a reload.
2178 (define_insn "movsi_ie"
2179 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,y,r,y,r,y")
2180 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,mr,xl,t,r,x,l,r,>,>,>,i,r,y,y"))]
2182 && (register_operand (operands[0], SImode)
2183 || register_operand (operands[1], SImode))"
2201 ! move optimized away"
2202 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,load,pcload_si,gp_fpul,gp_fpul,nil")
2203 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
2205 (define_insn "movsi_i_lowpart"
2206 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,r,m,r"))
2207 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,mr,xl,t,r,i"))]
2208 "register_operand (operands[0], SImode)
2209 || register_operand (operands[1], SImode)"
2218 [(set_attr "type" "pcload,move,load,move,move,store,pcload")])
2219 (define_expand "movsi"
2220 [(set (match_operand:SI 0 "general_movdst_operand" "")
2221 (match_operand:SI 1 "general_movsrc_operand" ""))]
2223 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
2225 (define_expand "ic_invalidate_line"
2226 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand" "+r")
2228 (clobber (scratch:SI))])]
2232 operands[0] = force_reg (Pmode, operands[0]);
2233 operands[1] = force_reg (Pmode, GEN_INT (0xf0000008));
2236 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
2237 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
2238 ;; the requirement *1*00 for associative address writes. The alignment of
2239 ;; %0 implies that its least significant bit is cleared,
2240 ;; thus we clear the V bit of a matching entry if there is one.
2241 (define_insn "ic_invalidate_line_i"
2242 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
2243 (match_operand:SI 1 "register_operand" "r")] 12)
2244 (clobber (match_scratch:SI 2 "=&r"))]
2246 "ocbwb\\t@%0\;extu.w\\t%0,%2\;or\\t%1,%2\;mov.l\\t%0,@%2"
2247 [(set_attr "length" "8")])
2249 (define_insn "movqi_i"
2250 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
2251 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
2252 "arith_reg_operand (operands[0], QImode)
2253 || arith_reg_operand (operands[1], QImode)"
2261 [(set_attr "type" "move,load,store,move,move,move")])
2263 (define_expand "movqi"
2264 [(set (match_operand:QI 0 "general_operand" "")
2265 (match_operand:QI 1 "general_operand" ""))]
2267 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
2269 (define_insn "movhi_i"
2270 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
2271 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
2272 "arith_reg_operand (operands[0], HImode)
2273 || arith_reg_operand (operands[1], HImode)"
2283 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
2285 (define_expand "movhi"
2286 [(set (match_operand:HI 0 "general_movdst_operand" "")
2287 (match_operand:HI 1 "general_movsrc_operand" ""))]
2289 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
2291 ;; ??? This should be a define expand.
2293 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
2294 ;; compiled with -m2 -ml -O3 -funroll-loops
2296 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
2297 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
2298 "arith_reg_operand (operands[0], DImode)
2299 || arith_reg_operand (operands[1], DImode)"
2300 "* return output_movedouble (insn, operands, DImode);"
2301 [(set_attr "length" "4")
2302 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
2304 ;; If the output is a register and the input is memory or a register, we have
2305 ;; to be careful and see which word needs to be loaded first.
2308 [(set (match_operand:DI 0 "general_movdst_operand" "")
2309 (match_operand:DI 1 "general_movsrc_operand" ""))]
2311 [(set (match_dup 2) (match_dup 3))
2312 (set (match_dup 4) (match_dup 5))]
2317 if ((GET_CODE (operands[0]) == MEM
2318 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2319 || (GET_CODE (operands[1]) == MEM
2320 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2323 if (GET_CODE (operands[0]) == REG)
2324 regno = REGNO (operands[0]);
2325 else if (GET_CODE (operands[0]) == SUBREG)
2326 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2327 else if (GET_CODE (operands[0]) == MEM)
2331 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2333 operands[2] = operand_subword (operands[0], 0, 0, DImode);
2334 operands[3] = operand_subword (operands[1], 0, 0, DImode);
2335 operands[4] = operand_subword (operands[0], 1, 0, DImode);
2336 operands[5] = operand_subword (operands[1], 1, 0, DImode);
2340 operands[2] = operand_subword (operands[0], 1, 0, DImode);
2341 operands[3] = operand_subword (operands[1], 1, 0, DImode);
2342 operands[4] = operand_subword (operands[0], 0, 0, DImode);
2343 operands[5] = operand_subword (operands[1], 0, 0, DImode);
2346 if (operands[2] == 0 || operands[3] == 0
2347 || operands[4] == 0 || operands[5] == 0)
2351 (define_expand "movdi"
2352 [(set (match_operand:DI 0 "general_movdst_operand" "")
2353 (match_operand:DI 1 "general_movsrc_operand" ""))]
2355 "{ if ( prepare_move_operands (operands, DImode)) DONE; }")
2357 ;; ??? This should be a define expand.
2359 (define_insn "movdf_k"
2360 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
2361 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
2362 "(! TARGET_SH4 || reload_completed
2363 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
2364 || GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3
2365 || GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3)
2366 && (arith_reg_operand (operands[0], DFmode)
2367 || arith_reg_operand (operands[1], DFmode))"
2368 "* return output_movedouble (insn, operands, DFmode);"
2369 [(set_attr "length" "4")
2370 (set_attr "type" "move,pcload,load,store")])
2372 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
2373 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
2374 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
2375 ;; the d/m/c/X alternative, which is split later into single-precision
2376 ;; instructions. And when not optimizing, no splits are done before fixing
2377 ;; up pcloads, so we need usable length information for that.
2378 (define_insn "movdf_i4"
2379 [(set (match_operand:DF 0 "general_movdst_operand" "=d,r,d,d,m,r,r,m,!??r,!???d")
2380 (match_operand:DF 1 "general_movsrc_operand" "d,r,F,m,d,FQ,m,r,d,r"))
2381 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c"))
2382 (clobber (match_scratch:SI 3 "=X,X,&z,X,X,X,X,X,X,X"))]
2384 && (arith_reg_operand (operands[0], DFmode)
2385 || arith_reg_operand (operands[1], DFmode))"
2397 [(set_attr_alternative "length"
2398 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
2400 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 6))
2401 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2402 (if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 6))
2404 (const_int 8) (const_int 8) ;; these need only 8 bytes for @(r0,rn)
2405 (const_int 8) (const_int 8)])
2406 (set_attr "type" "fmove,move,pcload,load,store,pcload,load,store,load,load")])
2408 ;; Moving DFmode between fp/general registers through memory
2409 ;; (the top of the stack) is faster than moving through fpul even for
2410 ;; little endian. Because the type of an instruction is important for its
2411 ;; scheduling, it is beneficial to split these operations, rather than
2412 ;; emitting them in one single chunk, even if this will expose a stack
2413 ;; use that will prevent scheduling of other stack accesses beyond this
2416 [(set (match_operand:DF 0 "register_operand" "")
2417 (match_operand:DF 1 "register_operand" ""))
2418 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2419 (clobber (match_scratch:SI 3 "=X"))]
2420 "TARGET_SH4 && reload_completed
2421 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
2427 tos = gen_rtx (MEM, DFmode, gen_rtx (PRE_DEC, Pmode, stack_pointer_rtx));
2428 insn = emit_insn (gen_movdf_i4 (tos, operands[1], operands[2]));
2429 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2430 tos = gen_rtx (MEM, DFmode, gen_rtx (POST_INC, Pmode, stack_pointer_rtx));
2431 insn = emit_insn (gen_movdf_i4 (operands[0], tos, operands[2]));
2432 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, stack_pointer_rtx, NULL_RTX);
2436 ;; local-alloc sometimes allocates scratch registers even when not required,
2437 ;; so we must be prepared to handle these.
2439 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
2441 [(set (match_operand:DF 0 "general_movdst_operand" "")
2442 (match_operand:DF 1 "general_movsrc_operand" ""))
2443 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2444 (clobber (match_scratch:SI 3 "X"))]
2447 && true_regnum (operands[0]) < 16
2448 && true_regnum (operands[1]) < 16"
2449 [(set (match_dup 0) (match_dup 1))]
2452 /* If this was a reg <-> mem operation with base + index reg addressing,
2453 we have to handle this in a special way. */
2454 rtx mem = operands[0];
2456 if (! memory_operand (mem, DFmode))
2461 if (GET_CODE (mem) == SUBREG && SUBREG_WORD (mem) == 0)
2462 mem = SUBREG_REG (mem);
2463 if (GET_CODE (mem) == MEM)
2465 rtx addr = XEXP (mem, 0);
2466 if (GET_CODE (addr) == PLUS
2467 && GET_CODE (XEXP (addr, 0)) == REG
2468 && GET_CODE (XEXP (addr, 1)) == REG)
2471 rtx reg0 = gen_rtx (REG, Pmode, 0);
2472 rtx regop = operands[store_p], word0 ,word1;
2474 if (GET_CODE (regop) == SUBREG)
2475 regop = alter_subreg (regop);
2476 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
2480 mem = copy_rtx (mem);
2481 PUT_MODE (mem, SImode);
2482 word0 = gen_rtx(SUBREG, SImode, regop, 0);
2484 ? gen_movsi_ie (mem, word0) : gen_movsi_ie (word0, mem));
2485 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
2486 mem = copy_rtx (mem);
2487 word1 = gen_rtx(SUBREG, SImode, regop, 1);
2489 ? gen_movsi_ie (mem, word1) : gen_movsi_ie (word1, mem));
2490 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
2496 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
2498 [(set (match_operand:DF 0 "register_operand" "")
2499 (match_operand:DF 1 "memory_operand" ""))
2500 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2501 (clobber (reg:SI 0))]
2502 "TARGET_SH4 && reload_completed"
2503 [(parallel [(set (match_dup 0) (match_dup 1))
2505 (clobber (scratch:SI))])]
2508 (define_expand "reload_indf"
2509 [(parallel [(set (match_operand:DF 0 "register_operand" "=f")
2510 (match_operand:DF 1 "immediate_operand" "FQ"))
2512 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2516 (define_expand "reload_outdf"
2517 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
2518 (match_operand:DF 1 "register_operand" "af,r"))
2519 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
2523 ;; Simplify no-op moves.
2525 [(set (match_operand:SF 0 "register_operand" "")
2526 (match_operand:SF 1 "register_operand" ""))
2527 (use (match_operand:PSI 2 "fpscr_operand" ""))
2528 (clobber (match_scratch:SI 3 "X"))]
2529 "TARGET_SH3E && reload_completed
2530 && true_regnum (operands[0]) == true_regnum (operands[1])"
2531 [(set (match_dup 0) (match_dup 0))]
2534 ;; fmovd substitute post-reload splits
2536 [(set (match_operand:DF 0 "register_operand" "")
2537 (match_operand:DF 1 "register_operand" ""))
2538 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2539 (clobber (match_scratch:SI 3 "X"))]
2540 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2541 && true_regnum (operands[0]) >= FIRST_FP_REG
2542 && true_regnum (operands[1]) >= FIRST_FP_REG"
2546 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
2547 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst),
2548 gen_rtx (REG, SFmode, src), operands[2]));
2549 emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode, dst + 1),
2550 gen_rtx (REG, SFmode, src + 1), operands[2]));
2555 [(set (match_operand:DF 0 "register_operand" "")
2556 (mem:DF (match_operand:SI 1 "register_operand" "")))
2557 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2558 (clobber (match_scratch:SI 3 "X"))]
2559 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2560 && true_regnum (operands[0]) >= FIRST_FP_REG
2561 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
2565 int regno = true_regnum (operands[0]);
2567 rtx mem2 = gen_rtx (MEM, SFmode, gen_rtx (POST_INC, Pmode, operands[1]));
2569 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2570 regno + !! TARGET_LITTLE_ENDIAN),
2571 mem2, operands[2]));
2572 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[1], NULL_RTX);
2573 insn = emit_insn (gen_movsf_ie (gen_rtx (REG, SFmode,
2574 regno + ! TARGET_LITTLE_ENDIAN),
2575 gen_rtx (MEM, SFmode, operands[1]),
2581 [(set (match_operand:DF 0 "register_operand" "")
2582 (match_operand:DF 1 "memory_operand" ""))
2583 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2584 (clobber (match_scratch:SI 3 "X"))]
2585 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2586 && true_regnum (operands[0]) >= FIRST_FP_REG"
2590 int regno = true_regnum (operands[0]);
2591 rtx addr, insn, adjust = NULL_RTX;
2592 rtx mem2 = copy_rtx (operands[1]);
2593 rtx reg0 = gen_rtx_REG (SFmode, regno + !! TARGET_LITTLE_ENDIAN);
2594 rtx reg1 = gen_rtx_REG (SFmode, regno + ! TARGET_LITTLE_ENDIAN);
2596 PUT_MODE (mem2, SFmode);
2597 operands[1] = copy_rtx (mem2);
2598 addr = XEXP (mem2, 0);
2599 if (GET_CODE (addr) != POST_INC)
2601 /* If we have to modify the stack pointer, the value that we have
2602 read with post-increment might be modified by an interrupt,
2603 so write it back. */
2604 if (REGNO (addr) == STACK_POINTER_REGNUM)
2605 adjust = gen_push_e (reg0);
2607 adjust = gen_addsi3 (addr, addr, GEN_INT (-4));
2608 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
2610 addr = XEXP (addr, 0);
2611 insn = emit_insn (gen_movsf_ie (reg0, mem2, operands[2]));
2612 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2613 insn = emit_insn (gen_movsf_ie (reg1, operands[1], operands[2]));
2617 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_INC, addr, NULL_RTX);
2622 [(set (match_operand:DF 0 "memory_operand" "")
2623 (match_operand:DF 1 "register_operand" ""))
2624 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2625 (clobber (match_scratch:SI 3 "X"))]
2626 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
2627 && true_regnum (operands[1]) >= FIRST_FP_REG"
2631 int regno = true_regnum (operands[1]);
2632 rtx insn, addr, adjust = NULL_RTX;
2634 operands[0] = copy_rtx (operands[0]);
2635 PUT_MODE (operands[0], SFmode);
2636 insn = emit_insn (gen_movsf_ie (operands[0],
2637 gen_rtx (REG, SFmode,
2638 regno + ! TARGET_LITTLE_ENDIAN),
2640 operands[0] = copy_rtx (operands[0]);
2641 addr = XEXP (operands[0], 0);
2642 if (GET_CODE (addr) != PRE_DEC)
2644 adjust = gen_addsi3 (addr, addr, GEN_INT (4));
2645 emit_insn_before (adjust, insn);
2646 XEXP (operands[0], 0) = addr = gen_rtx (PRE_DEC, SImode, addr);
2648 addr = XEXP (addr, 0);
2650 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2651 insn = emit_insn (gen_movsf_ie (operands[0],
2652 gen_rtx (REG, SFmode,
2653 regno + !! TARGET_LITTLE_ENDIAN),
2655 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, addr, NULL_RTX);
2659 ;; The '&' for operand 2 is not really true, but push_secondary_reload
2661 ;; Operand 1 must accept FPUL_REGS in case fpul is reloaded to memory,
2662 ;; to avoid a bogus tertiary reload.
2663 ;; We need a tertiary reload when a floating point register is reloaded
2664 ;; to memory, so the predicate for operand 0 must accept this, while the
2665 ;; constraint of operand 1 must reject the secondary reload register.
2666 ;; Thus, the secondary reload register for this case has to be GENERAL_REGS,
2668 ;; By having the predicate for operand 0 reject any register, we make
2669 ;; sure that the ordinary moves that just need an intermediate register
2670 ;; won't get a bogus tertiary reload.
2671 ;; We use tertiary_reload_operand instead of memory_operand here because
2672 ;; memory_operand rejects operands that are not directly addressible, e.g.:
2673 ;; (mem:SF (plus:SI (reg:SI 14 r14)
2674 ;; (const_int 132)))
2676 (define_expand "reload_outsf"
2677 [(parallel [(set (match_operand:SF 2 "register_operand" "=&r")
2678 (match_operand:SF 1 "register_operand" "y"))
2679 (clobber (scratch:SI))])
2680 (parallel [(set (match_operand:SF 0 "tertiary_reload_operand" "=m")
2682 (clobber (scratch:SI))])]
2686 ;; If the output is a register and the input is memory or a register, we have
2687 ;; to be careful and see which word needs to be loaded first.
2690 [(set (match_operand:DF 0 "general_movdst_operand" "")
2691 (match_operand:DF 1 "general_movsrc_operand" ""))]
2693 [(set (match_dup 2) (match_dup 3))
2694 (set (match_dup 4) (match_dup 5))]
2699 if ((GET_CODE (operands[0]) == MEM
2700 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2701 || (GET_CODE (operands[1]) == MEM
2702 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2705 if (GET_CODE (operands[0]) == REG)
2706 regno = REGNO (operands[0]);
2707 else if (GET_CODE (operands[0]) == SUBREG)
2708 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2709 else if (GET_CODE (operands[0]) == MEM)
2713 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2715 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2716 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2717 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2718 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
2722 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
2723 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
2724 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
2725 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
2728 if (operands[2] == 0 || operands[3] == 0
2729 || operands[4] == 0 || operands[5] == 0)
2733 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
2734 ;; used only once, let combine add in the index again.
2737 [(set (match_operand:SI 0 "register_operand" "")
2738 (match_operand:SI 1 "" ""))
2739 (clobber (match_operand 2 "register_operand" ""))]
2740 "! reload_in_progress && ! reload_completed"
2744 rtx addr, reg, const_int;
2746 if (GET_CODE (operands[1]) != MEM)
2748 addr = XEXP (operands[1], 0);
2749 if (GET_CODE (addr) != PLUS)
2751 reg = XEXP (addr, 0);
2752 const_int = XEXP (addr, 1);
2753 if (GET_CODE (reg) != REG || GET_CODE (const_int) != CONST_INT)
2755 emit_move_insn (operands[2], const_int);
2756 emit_move_insn (operands[0],
2757 change_address (operands[1], VOIDmode,
2758 gen_rtx (PLUS, SImode, reg, operands[2])));
2763 [(set (match_operand:SI 1 "" "")
2764 (match_operand:SI 0 "register_operand" ""))
2765 (clobber (match_operand 2 "register_operand" ""))]
2766 "! reload_in_progress && ! reload_completed"
2770 rtx addr, reg, const_int;
2772 if (GET_CODE (operands[1]) != MEM)
2774 addr = XEXP (operands[1], 0);
2775 if (GET_CODE (addr) != PLUS)
2777 reg = XEXP (addr, 0);
2778 const_int = XEXP (addr, 1);
2779 if (GET_CODE (reg) != REG || GET_CODE (const_int) != CONST_INT)
2781 emit_move_insn (operands[2], const_int);
2782 emit_move_insn (change_address (operands[1], VOIDmode,
2783 gen_rtx (PLUS, SImode, reg, operands[2])),
2788 (define_expand "movdf"
2789 [(set (match_operand:DF 0 "general_movdst_operand" "")
2790 (match_operand:DF 1 "general_movsrc_operand" ""))]
2794 if (prepare_move_operands (operands, DFmode)) DONE;
2799 /* ??? FIXME: This is only a stopgap fix. There is no guarantee
2800 that fpscr is in the right state. */
2801 emit_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
2804 emit_df_insn (gen_movdf_i4 (operands[0], operands[1], get_fpscr_rtx ()));
2805 /* We need something to tag possible REG_LIBCALL notes on to. */
2806 if (TARGET_FPU_SINGLE && rtx_equal_function_value_matters
2807 && GET_CODE (operands[0]) == REG)
2808 emit_insn (gen_mov_nop (operands[0]));
2814 (define_insn "movsf_i"
2815 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
2816 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,mr,r,r,l"))]
2819 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
2820 || GET_CODE (operands[0]) == REG && REGNO (operands[0]) == 3
2821 || GET_CODE (operands[1]) == REG && REGNO (operands[1]) == 3)
2822 && (arith_reg_operand (operands[0], SFmode)
2823 || arith_reg_operand (operands[1], SFmode))"
2832 [(set_attr "type" "move,move,pcload,load,store,move,move")])
2834 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
2835 ;; update_flow_info would not know where to put REG_EQUAL notes
2836 ;; when the destination changes mode.
2837 (define_insn "movsf_ie"
2838 [(set (match_operand:SF 0 "general_movdst_operand"
2839 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
2840 (match_operand:SF 1 "general_movsrc_operand"
2841 "f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y"))
2842 (use (match_operand:PSI 2 "fpscr_operand" "c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c,c"))
2843 (clobber (match_scratch:SI 3 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
2846 && (arith_reg_operand (operands[0], SFmode)
2847 || arith_reg_operand (operands[1], SFmode))"
2865 ! move optimized away"
2866 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
2867 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,4,2,2,0")])
2870 [(set (match_operand:SF 0 "register_operand" "")
2871 (match_operand:SF 1 "register_operand" ""))
2872 (use (match_operand:PSI 2 "fpscr_operand" "c"))
2873 (clobber (reg:SI 22))]
2875 [(parallel [(set (reg:SF 22) (match_dup 1))
2877 (clobber (scratch:SI))])
2878 (parallel [(set (match_dup 0) (reg:SF 22))
2880 (clobber (scratch:SI))])]
2883 (define_expand "movsf"
2884 [(set (match_operand:SF 0 "general_movdst_operand" "")
2885 (match_operand:SF 1 "general_movsrc_operand" ""))]
2889 if (prepare_move_operands (operands, SFmode))
2895 /* ??? FIXME: This is only a stopgap fix. There is no guarantee
2896 that fpscr is in the right state. */
2897 emit_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
2900 emit_sf_insn (gen_movsf_ie (operands[0], operands[1], get_fpscr_rtx ()));
2901 /* We need something to tag possible REG_LIBCALL notes on to. */
2902 if (! TARGET_FPU_SINGLE && rtx_equal_function_value_matters
2903 && GET_CODE (operands[0]) == REG)
2904 emit_insn (gen_mov_nop (operands[0]));
2909 (define_insn "mov_nop"
2910 [(set (match_operand 0 "register_operand" "") (match_dup 0))]
2913 [(set_attr "length" "0")
2914 (set_attr "type" "nil")])
2916 (define_expand "reload_insf"
2917 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
2918 (match_operand:SF 1 "immediate_operand" "FQ"))
2920 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2924 (define_expand "reload_insi"
2925 [(parallel [(set (match_operand:SF 0 "register_operand" "=y")
2926 (match_operand:SF 1 "immediate_operand" "FQ"))
2927 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2931 (define_insn "*movsi_y"
2932 [(set (match_operand:SI 0 "register_operand" "=y,y")
2933 (match_operand:SI 1 "immediate_operand" "Qi,I"))
2934 (clobber (match_scratch:SI 3 "=&z,r"))]
2936 && (reload_in_progress || reload_completed)"
2938 [(set_attr "length" "4")
2939 (set_attr "type" "pcload,move")])
2942 [(set (match_operand:SI 0 "register_operand" "y")
2943 (match_operand:SI 1 "immediate_operand" "I"))
2944 (clobber (match_operand:SI 2 "register_operand" "r"))]
2946 [(set (match_dup 2) (match_dup 1))
2947 (set (match_dup 0) (match_dup 2))]
2951 [(set (match_operand:SI 0 "register_operand" "y")
2952 (match_operand:SI 1 "memory_operand" ">"))
2953 (clobber (reg:SI 0))]
2955 [(set (match_dup 0) (match_dup 1))]
2958 ;; ------------------------------------------------------------------------
2959 ;; Define the real conditional branch instructions.
2960 ;; ------------------------------------------------------------------------
2962 (define_insn "branch_true"
2963 [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 0))
2964 (label_ref (match_operand 0 "" ""))
2967 "* return output_branch (1, insn, operands);"
2968 [(set_attr "type" "cbranch")])
2970 (define_insn "branch_false"
2971 [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 0))
2972 (label_ref (match_operand 0 "" ""))
2975 "* return output_branch (0, insn, operands);"
2976 [(set_attr "type" "cbranch")])
2978 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
2979 ;; which destination is too far away.
2980 ;; The const_int_operand is distinct for each branch target; it avoids
2981 ;; unwanted matches with redundant_insn.
2982 (define_insn "block_branch_redirect"
2983 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] 4))]
2986 [(set_attr "length" "0")])
2988 ;; This one has the additional purpose to record a possible scratch register
2989 ;; for the following branch.
2990 (define_insn "indirect_jump_scratch"
2991 [(set (match_operand 0 "register_operand" "r")
2992 (unspec [(match_operand 1 "const_int_operand" "")] 4))]
2995 [(set_attr "length" "0")])
2997 ;; Conditional branch insns
2999 (define_expand "beq"
3001 (if_then_else (ne (reg:SI 18) (const_int 0))
3002 (label_ref (match_operand 0 "" ""))
3005 "from_compare (operands, EQ);")
3007 (define_expand "bne"
3009 (if_then_else (eq (reg:SI 18) (const_int 0))
3010 (label_ref (match_operand 0 "" ""))
3013 "from_compare (operands, EQ);")
3015 (define_expand "bgt"
3017 (if_then_else (ne (reg:SI 18) (const_int 0))
3018 (label_ref (match_operand 0 "" ""))
3021 "from_compare (operands, GT);")
3023 (define_expand "blt"
3025 (if_then_else (eq (reg:SI 18) (const_int 0))
3026 (label_ref (match_operand 0 "" ""))
3031 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3033 rtx tmp = sh_compare_op0;
3034 sh_compare_op0 = sh_compare_op1;
3035 sh_compare_op1 = tmp;
3036 emit_insn (gen_bgt (operands[0]));
3039 from_compare (operands, GE);
3042 (define_expand "ble"
3044 (if_then_else (eq (reg:SI 18) (const_int 0))
3045 (label_ref (match_operand 0 "" ""))
3052 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3054 rtx tmp = sh_compare_op0;
3055 sh_compare_op0 = sh_compare_op1;
3056 sh_compare_op1 = tmp;
3057 emit_insn (gen_bge (operands[0]));
3060 from_compare (operands, GT);
3063 (define_expand "bge"
3065 (if_then_else (ne (reg:SI 18) (const_int 0))
3066 (label_ref (match_operand 0 "" ""))
3073 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3075 rtx tmp = sh_compare_op0;
3076 sh_compare_op0 = sh_compare_op1;
3077 sh_compare_op1 = tmp;
3078 emit_insn (gen_ble (operands[0]));
3081 from_compare (operands, GE);
3084 (define_expand "bgtu"
3086 (if_then_else (ne (reg:SI 18) (const_int 0))
3087 (label_ref (match_operand 0 "" ""))
3090 "from_compare (operands, GTU); ")
3092 (define_expand "bltu"
3094 (if_then_else (eq (reg:SI 18) (const_int 0))
3095 (label_ref (match_operand 0 "" ""))
3098 "from_compare (operands, GEU);")
3100 (define_expand "bgeu"
3102 (if_then_else (ne (reg:SI 18) (const_int 0))
3103 (label_ref (match_operand 0 "" ""))
3106 "from_compare (operands, GEU);")
3108 (define_expand "bleu"
3110 (if_then_else (eq (reg:SI 18) (const_int 0))
3111 (label_ref (match_operand 0 "" ""))
3114 "from_compare (operands, GTU);")
3116 ;; ------------------------------------------------------------------------
3117 ;; Jump and linkage insns
3118 ;; ------------------------------------------------------------------------
3122 (label_ref (match_operand 0 "" "")))]
3126 /* The length is 16 if the delay slot is unfilled. */
3127 if (get_attr_length(insn) > 4)
3128 return output_far_jump(insn, operands[0]);
3130 return \"bra %l0%#\";
3132 [(set_attr "type" "jump")
3133 (set_attr "needs_delay_slot" "yes")])
3135 (define_insn "calli"
3136 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
3137 (match_operand 1 "" ""))
3139 (clobber (reg:SI 17))]
3142 [(set_attr "type" "call")
3143 (set_attr "needs_delay_slot" "yes")])
3145 (define_insn "call_valuei"
3146 [(set (match_operand 0 "" "=rf")
3147 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
3148 (match_operand 2 "" "")))
3150 (clobber (reg:SI 17))]
3153 [(set_attr "type" "call")
3154 (set_attr "needs_delay_slot" "yes")])
3156 (define_expand "call"
3157 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
3158 (match_operand 1 "" ""))
3160 (clobber (reg:SI 17))])]
3162 "operands[0] = force_reg (SImode, XEXP (operands[0], 0));")
3164 (define_expand "call_value"
3165 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
3166 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
3167 (match_operand 2 "" "")))
3169 (clobber (reg:SI 17))])]
3171 "operands[1] = force_reg (SImode, XEXP (operands[1], 0));")
3173 (define_insn "indirect_jump"
3175 (match_operand:SI 0 "arith_reg_operand" "r"))]
3178 [(set_attr "needs_delay_slot" "yes")
3179 (set_attr "type" "jump_ind")])
3181 ;; The use of operand 1 / 2 helps us distinguish case table jumps
3182 ;; which can be present in structured code from indirect jumps which can not
3183 ;; be present in structured code. This allows -fprofile-arcs to work.
3185 ;; For SH1 processors.
3186 (define_insn "casesi_jump_1"
3188 (match_operand:SI 0 "register_operand" "r"))
3189 (use (label_ref (match_operand 1 "" "")))]
3192 [(set_attr "needs_delay_slot" "yes")
3193 (set_attr "type" "jump_ind")])
3195 ;; For all later processors.
3196 (define_insn "casesi_jump_2"
3197 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
3198 (label_ref (match_operand 1 "" ""))))
3199 (use (label_ref (match_operand 2 "" "")))]
3200 "! INSN_UID (operands[1]) || prev_real_insn (operands[1]) == insn"
3202 [(set_attr "needs_delay_slot" "yes")
3203 (set_attr "type" "jump_ind")])
3205 ;; Call subroutine returning any type.
3206 ;; ??? This probably doesn't work.
3208 (define_expand "untyped_call"
3209 [(parallel [(call (match_operand 0 "" "")
3211 (match_operand 1 "" "")
3212 (match_operand 2 "" "")])]
3218 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
3220 for (i = 0; i < XVECLEN (operands[2], 0); i++)
3222 rtx set = XVECEXP (operands[2], 0, i);
3223 emit_move_insn (SET_DEST (set), SET_SRC (set));
3226 /* The optimizer does not know that the call sets the function value
3227 registers we stored in the result block. We avoid problems by
3228 claiming that all hard registers are used and clobbered at this
3230 emit_insn (gen_blockage ());
3235 ;; ------------------------------------------------------------------------
3237 ;; ------------------------------------------------------------------------
3241 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
3242 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3245 [(set_attr "type" "arith")])
3252 ;; Load address of a label. This is only generated by the casesi expand,
3253 ;; and by machine_dependent_reorg (fixing up fp moves).
3254 ;; This must use unspec, because this only works for labels that are
3259 (unspec [(label_ref (match_operand 0 "" ""))] 1))]
3262 [(set_attr "in_delay_slot" "no")
3263 (set_attr "type" "arith")])
3265 ;; case instruction for switch statements.
3267 ;; Operand 0 is index
3268 ;; operand 1 is the minimum bound
3269 ;; operand 2 is the maximum bound - minimum bound + 1
3270 ;; operand 3 is CODE_LABEL for the table;
3271 ;; operand 4 is the CODE_LABEL to go to if index out of range.
3273 (define_expand "casesi"
3274 [(match_operand:SI 0 "arith_reg_operand" "")
3275 (match_operand:SI 1 "arith_reg_operand" "")
3276 (match_operand:SI 2 "arith_reg_operand" "")
3277 (match_operand 3 "" "") (match_operand 4 "" "")]
3281 rtx reg = gen_reg_rtx (SImode);
3282 rtx reg2 = gen_reg_rtx (SImode);
3283 operands[1] = copy_to_mode_reg (SImode, operands[1]);
3284 operands[2] = copy_to_mode_reg (SImode, operands[2]);
3285 /* If optimizing, casesi_worker depends on the mode of the instruction
3286 before label it 'uses' - operands[3]. */
3287 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
3289 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
3291 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
3293 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
3294 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
3295 operands[3], but to lab. We will fix this up in
3296 machine_dependent_reorg. */
3301 (define_expand "casesi_0"
3302 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
3303 (set (match_dup 4) (minus:SI (match_dup 4)
3304 (match_operand:SI 1 "arith_operand" "")))
3306 (gtu:SI (match_dup 4)
3307 (match_operand:SI 2 "arith_reg_operand" "")))
3309 (if_then_else (ne (reg:SI 18)
3311 (label_ref (match_operand 3 "" ""))
3316 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
3317 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
3318 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
3320 (define_insn "casesi_worker_0"
3321 [(set (match_operand:SI 0 "register_operand" "=r,r")
3322 (unspec [(match_operand 1 "register_operand" "0,r")
3323 (label_ref (match_operand 2 "" ""))] 2))
3324 (clobber (match_scratch:SI 3 "=X,1"))
3325 (clobber (match_scratch:SI 4 "=&z,z"))]
3330 [(set (match_operand:SI 0 "register_operand" "")
3331 (unspec [(match_operand 1 "register_operand" "")
3332 (label_ref (match_operand 2 "" ""))] 2))
3333 (clobber (match_scratch:SI 3 ""))
3334 (clobber (match_scratch:SI 4 ""))]
3335 "! TARGET_SH2 && reload_completed"
3336 [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
3337 (parallel [(set (match_dup 0)
3338 (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
3339 (clobber (match_dup 3))])
3340 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
3341 "LABEL_NUSES (operands[2])++;")
3344 [(set (match_operand:SI 0 "register_operand" "")
3345 (unspec [(match_operand 1 "register_operand" "")
3346 (label_ref (match_operand 2 "" ""))] 2))
3347 (clobber (match_scratch:SI 3 ""))
3348 (clobber (match_scratch:SI 4 ""))]
3349 "TARGET_SH2 && reload_completed"
3350 [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
3351 (parallel [(set (match_dup 0)
3352 (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
3353 (clobber (match_dup 3))])]
3354 "LABEL_NUSES (operands[2])++;")
3356 (define_insn "*casesi_worker"
3357 [(set (match_operand:SI 0 "register_operand" "=r,r")
3358 (unspec [(reg:SI 0) (match_operand 1 "register_operand" "0,r")
3359 (label_ref (match_operand 2 "" ""))] 2))
3360 (clobber (match_scratch:SI 3 "=X,1"))]
3364 rtx diff_vec = PATTERN (next_real_insn (operands[2]));
3366 if (GET_CODE (diff_vec) != ADDR_DIFF_VEC)
3369 switch (GET_MODE (diff_vec))
3372 return \"shll2 %1\;mov.l @(r0,%1),%0\";
3374 return \"add %1,%1\;mov.w @(r0,%1),%0\";
3376 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
3377 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
3378 return \"mov.b @(r0,%1),%0\";
3383 [(set_attr "length" "4")])
3385 ;; ??? This is not the proper place to invoke another compiler pass;
3386 ;; Alas, there is no proper place to put it.
3387 ;; ??? This is also an odd place for the call to emit_fpscr_use. It
3388 ;; would be all right if it were for an define_expand for return, but
3389 ;; that doesn't mix with emitting a prologue.
3390 (define_insn "return"
3393 remove_dead_before_cse (),
3396 [(set_attr "type" "return")
3397 (set_attr "needs_delay_slot" "yes")])
3399 (define_expand "prologue"
3402 "sh_expand_prologue (); DONE;")
3404 (define_expand "epilogue"
3407 "sh_expand_epilogue ();")
3409 (define_insn "blockage"
3410 [(unspec_volatile [(const_int 0)] 0)]
3413 [(set_attr "length" "0")])
3415 ;; ------------------------------------------------------------------------
3417 ;; ------------------------------------------------------------------------
3420 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3421 (eq:SI (reg:SI 18) (const_int 1)))]
3424 [(set_attr "type" "arith")])
3426 (define_expand "seq"
3427 [(set (match_operand:SI 0 "arith_reg_operand" "")
3430 "operands[1] = prepare_scc_operands (EQ);")
3432 (define_expand "slt"
3433 [(set (match_operand:SI 0 "arith_reg_operand" "")
3436 "operands[1] = prepare_scc_operands (LT);")
3438 (define_expand "sle"
3439 [(match_operand:SI 0 "arith_reg_operand" "")]
3443 rtx tmp = sh_compare_op0;
3444 sh_compare_op0 = sh_compare_op1;
3445 sh_compare_op1 = tmp;
3446 emit_insn (gen_sge (operands[0]));
3450 (define_expand "sgt"
3451 [(set (match_operand:SI 0 "arith_reg_operand" "")
3454 "operands[1] = prepare_scc_operands (GT);")
3456 (define_expand "sge"
3457 [(set (match_operand:SI 0 "arith_reg_operand" "")
3462 if (GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
3466 rtx t_reg = gen_rtx (REG, SImode, T_REG);
3467 rtx lab = gen_label_rtx ();
3468 prepare_scc_operands (EQ);
3469 emit_jump_insn (gen_branch_true (lab));
3470 prepare_scc_operands (GT);
3472 emit_insn (gen_movt (operands[0]));
3475 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
3478 operands[1] = prepare_scc_operands (GE);
3481 (define_expand "sgtu"
3482 [(set (match_operand:SI 0 "arith_reg_operand" "")
3485 "operands[1] = prepare_scc_operands (GTU);")
3487 (define_expand "sltu"
3488 [(set (match_operand:SI 0 "arith_reg_operand" "")
3491 "operands[1] = prepare_scc_operands (LTU);")
3493 (define_expand "sleu"
3494 [(set (match_operand:SI 0 "arith_reg_operand" "")
3497 "operands[1] = prepare_scc_operands (LEU);")
3499 (define_expand "sgeu"
3500 [(set (match_operand:SI 0 "arith_reg_operand" "")
3503 "operands[1] = prepare_scc_operands (GEU);")
3505 ;; sne moves the complement of the T reg to DEST like this:
3509 ;; This is better than xoring compare result with 1 because it does
3510 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
3513 (define_expand "sne"
3514 [(set (match_dup 2) (const_int -1))
3515 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
3516 (neg:SI (plus:SI (match_dup 1)
3519 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
3524 operands[1] = prepare_scc_operands (EQ);
3525 operands[2] = gen_reg_rtx (SImode);
3528 ;; Use the same trick for FP sle / sge
3529 (define_expand "movnegt"
3530 [(set (match_dup 2) (const_int -1))
3531 (parallel [(set (match_operand 0 "" "")
3532 (neg:SI (plus:SI (match_dup 1)
3535 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
3538 "operands[2] = gen_reg_rtx (SImode);")
3540 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
3541 ;; This prevents a regression that occurred when we switched from xor to
3545 [(set (match_operand:SI 0 "arith_reg_operand" "")
3546 (plus:SI (reg:SI 18)
3549 [(set (match_dup 0) (eq:SI (reg:SI 18) (const_int 1)))
3550 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
3553 ;; -------------------------------------------------------------------------
3554 ;; Instructions to cope with inline literal tables
3555 ;; -------------------------------------------------------------------------
3557 ; 2 byte integer in line
3559 (define_insn "consttable_2"
3560 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 2)]
3564 assemble_integer (operands[0], 2, 1);
3567 [(set_attr "length" "2")
3568 (set_attr "in_delay_slot" "no")])
3570 ; 4 byte integer in line
3572 (define_insn "consttable_4"
3573 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 4)]
3577 assemble_integer (operands[0], 4, 1);
3580 [(set_attr "length" "4")
3581 (set_attr "in_delay_slot" "no")])
3583 ; 8 byte integer in line
3585 (define_insn "consttable_8"
3586 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 6)]
3590 assemble_integer (operands[0], 8, 1);
3593 [(set_attr "length" "8")
3594 (set_attr "in_delay_slot" "no")])
3596 ; 4 byte floating point
3598 (define_insn "consttable_sf"
3599 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")] 4)]
3603 union real_extract u;
3604 bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
3605 assemble_real (u.d, SFmode);
3608 [(set_attr "length" "4")
3609 (set_attr "in_delay_slot" "no")])
3611 ; 8 byte floating point
3613 (define_insn "consttable_df"
3614 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")] 6)]
3618 union real_extract u;
3619 bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
3620 assemble_real (u.d, DFmode);
3623 [(set_attr "length" "8")
3624 (set_attr "in_delay_slot" "no")])
3626 ;; Alignment is needed for some constant tables; it may also be added for
3627 ;; Instructions at the start of loops, or after unconditional branches.
3628 ;; ??? We would get more accurate lengths if we did instruction
3629 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
3630 ;; here is too conservative.
3632 ; align to a two byte boundary
3634 (define_expand "align_2"
3635 [(unspec_volatile [(const_int 1)] 1)]
3639 ; align to a four byte boundary
3640 ;; align_4 and align_log are instructions for the starts of loops, or
3641 ;; after unconditional branches, which may take up extra room.
3643 (define_expand "align_4"
3644 [(unspec_volatile [(const_int 2)] 1)]
3648 ; align to a cache line boundary
3650 (define_insn "align_log"
3651 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 1)]
3654 [(set_attr "length" "0")
3655 (set_attr "in_delay_slot" "no")])
3657 ; emitted at the end of the literal table, used to emit the
3658 ; 32bit branch labels if needed.
3660 (define_insn "consttable_end"
3661 [(unspec_volatile [(const_int 0)] 11)]
3663 "* return output_jump_label_table ();"
3664 [(set_attr "in_delay_slot" "no")])
3666 ;; -------------------------------------------------------------------------
3668 ;; -------------------------------------------------------------------------
3670 ;; String/block move insn.
3672 (define_expand "movstrsi"
3673 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
3674 (mem:BLK (match_operand:BLK 1 "" "")))
3675 (use (match_operand:SI 2 "nonmemory_operand" ""))
3676 (use (match_operand:SI 3 "immediate_operand" ""))
3677 (clobber (reg:SI 17))
3678 (clobber (reg:SI 4))
3679 (clobber (reg:SI 5))
3680 (clobber (reg:SI 0))])]
3684 if(expand_block_move (operands))
3689 (define_insn "block_move_real"
3690 [(parallel [(set (mem:BLK (reg:SI 4))
3691 (mem:BLK (reg:SI 5)))
3692 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3693 (clobber (reg:SI 17))
3694 (clobber (reg:SI 0))])]
3697 [(set_attr "type" "sfunc")
3698 (set_attr "needs_delay_slot" "yes")])
3700 (define_insn "block_lump_real"
3701 [(parallel [(set (mem:BLK (reg:SI 4))
3702 (mem:BLK (reg:SI 5)))
3703 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3705 (clobber (reg:SI 17))
3706 (clobber (reg:SI 4))
3707 (clobber (reg:SI 5))
3708 (clobber (reg:SI 6))
3709 (clobber (reg:SI 0))])]
3712 [(set_attr "type" "sfunc")
3713 (set_attr "needs_delay_slot" "yes")])
3715 (define_insn "block_move_real_i4"
3716 [(parallel [(set (mem:BLK (reg:SI 4))
3717 (mem:BLK (reg:SI 5)))
3718 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3719 (clobber (reg:SI 17))
3720 (clobber (reg:SI 0))
3721 (clobber (reg:SI 1))
3722 (clobber (reg:SI 2))])]
3725 [(set_attr "type" "sfunc")
3726 (set_attr "needs_delay_slot" "yes")])
3728 (define_insn "block_lump_real_i4"
3729 [(parallel [(set (mem:BLK (reg:SI 4))
3730 (mem:BLK (reg:SI 5)))
3731 (use (match_operand:SI 0 "arith_reg_operand" "r"))
3733 (clobber (reg:SI 17))
3734 (clobber (reg:SI 4))
3735 (clobber (reg:SI 5))
3736 (clobber (reg:SI 6))
3737 (clobber (reg:SI 0))
3738 (clobber (reg:SI 1))
3739 (clobber (reg:SI 2))
3740 (clobber (reg:SI 3))])]
3743 [(set_attr "type" "sfunc")
3744 (set_attr "needs_delay_slot" "yes")])
3746 ;; -------------------------------------------------------------------------
3747 ;; Floating point instructions.
3748 ;; -------------------------------------------------------------------------
3750 ;; ??? All patterns should have a type attribute.
3752 (define_expand "fpu_switch0"
3753 [(set (match_operand:SI 0 "" "") (symbol_ref "__fpscr_values"))
3754 (set (match_dup 2) (match_dup 1))]
3758 operands[1] = gen_rtx (MEM, PSImode, operands[0]);
3759 RTX_UNCHANGING_P (operands[1]) = 1;
3760 operands[2] = get_fpscr_rtx ();
3763 (define_expand "fpu_switch1"
3764 [(set (match_operand:SI 0 "" "") (symbol_ref "__fpscr_values"))
3765 (set (match_dup 1) (plus:SI (match_dup 0) (const_int 4)))
3766 (set (match_dup 3) (match_dup 2))]
3770 operands[1] = gen_reg_rtx (SImode);
3771 operands[2] = gen_rtx (MEM, PSImode, operands[1]);
3772 RTX_UNCHANGING_P (operands[2]) = 1;
3773 operands[3] = get_fpscr_rtx ();
3776 (define_expand "movpsi"
3777 [(set (match_operand:PSI 0 "register_operand" "")
3778 (match_operand:PSI 1 "general_movsrc_operand" ""))]
3782 ;; The c / m alternative is a fake to guide reload to load directly into
3783 ;; fpscr, since reload doesn't know how to use post-increment.
3784 ;; GO_IF_LEGITIMATE_ADDRESS guards about bogus addresses before reload,
3785 ;; SECONDARY_INPUT_RELOAD_CLASS does this during reload, and the insn's
3786 ;; predicate after reload.
3787 ;; The gp_fpul type for r/!c might look a bit odd, but it actually schedules
3788 ;; like a gpr <-> fpul move.
3789 (define_insn "fpu_switch"
3790 [(set (match_operand:PSI 0 "register_operand" "c,c,r,c,c,r,m,r")
3791 (match_operand:PSI 1 "general_movsrc_operand" "c,>,m,m,r,r,r,!c"))]
3793 || true_regnum (operands[0]) != FPSCR_REG || GET_CODE (operands[1]) != MEM
3794 || GET_CODE (XEXP (operands[1], 0)) != PLUS"
3796 ! precision stays the same
3804 [(set_attr "length" "0,2,2,4,2,2,2,2")
3805 (set_attr "type" "dfp_conv,dfp_conv,load,dfp_conv,dfp_conv,move,store,gp_fpul")])
3808 [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
3809 "find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))"
3810 [(set (match_dup 0) (match_dup 0))]
3813 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
3814 gen_rtx (MEM, PSImode,
3815 gen_rtx (POST_INC, Pmode,
3817 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
3821 [(set (reg:PSI 48) (mem:PSI (match_operand:SI 0 "register_operand" "r")))]
3823 [(set (match_dup 0) (plus:SI (match_dup 0) (const_int -4)))]
3826 rtx insn = emit_insn (gen_fpu_switch (get_fpscr_rtx (),
3827 gen_rtx (MEM, PSImode,
3828 gen_rtx (POST_INC, Pmode,
3830 REG_NOTES (insn) = gen_rtx (EXPR_LIST, REG_INC, operands[0], NULL_RTX);
3833 ;; ??? This uses the fp unit, but has no type indicating that.
3834 ;; If we did that, this would either give a bogus latency or introduce
3835 ;; a bogus FIFO constraint.
3836 ;; Since this insn is currently only used for prologues/epilogues,
3837 ;; it is probably best to claim no function unit, which matches the
3839 (define_insn "toggle_sz"
3840 [(set (reg:PSI 48) (xor:PSI (reg:PSI 48) (const_int 1048576)))]
3844 (define_expand "addsf3"
3845 [(match_operand:SF 0 "arith_reg_operand" "")
3846 (match_operand:SF 1 "arith_reg_operand" "")
3847 (match_operand:SF 2 "arith_reg_operand" "")]
3849 "{ expand_sf_binop (&gen_addsf3_i, operands); DONE; }")
3851 (define_insn "addsf3_i"
3852 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3853 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
3854 (match_operand:SF 2 "arith_reg_operand" "f")))
3855 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
3858 [(set_attr "type" "fp")])
3860 (define_expand "subsf3"
3861 [(match_operand:SF 0 "fp_arith_reg_operand" "")
3862 (match_operand:SF 1 "fp_arith_reg_operand" "")
3863 (match_operand:SF 2 "fp_arith_reg_operand" "")]
3865 "{ expand_sf_binop (&gen_subsf3_i, operands); DONE; }")
3867 (define_insn "subsf3_i"
3868 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
3869 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
3870 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
3871 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
3874 [(set_attr "type" "fp")])
3876 ;; Unfortunately, the combiner is unable to cope with the USE of the FPSCR
3877 ;; register in feeding fp instructions. Thus, we cannot generate fmac for
3878 ;; mixed-precision SH4 targets. To allow it to be still generated for the
3879 ;; SH3E, we use a separate insn for SH3E mulsf3.
3881 (define_expand "mulsf3"
3882 [(match_operand:SF 0 "arith_reg_operand" "")
3883 (match_operand:SF 1 "arith_reg_operand" "")
3884 (match_operand:SF 2 "arith_reg_operand" "")]
3889 expand_sf_binop (&gen_mulsf3_i4, operands);
3891 emit_insn (gen_mulsf3_ie (operands[0], operands[1], operands[2]));
3895 (define_insn "mulsf3_i4"
3896 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3897 (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
3898 (match_operand:SF 2 "arith_reg_operand" "f")))
3899 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
3902 [(set_attr "type" "fp")])
3904 (define_insn "mulsf3_ie"
3905 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3906 (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
3907 (match_operand:SF 2 "arith_reg_operand" "f")))]
3908 "TARGET_SH3E && ! TARGET_SH4"
3910 [(set_attr "type" "fp")])
3912 (define_insn "*macsf3"
3913 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3914 (plus:SF (mult:SF (match_operand:SF 1 "arith_reg_operand" "%w")
3915 (match_operand:SF 2 "arith_reg_operand" "f"))
3916 (match_operand:SF 3 "arith_reg_operand" "0")))
3917 (use (match_operand:PSI 4 "fpscr_operand" "c"))]
3918 "TARGET_SH3E && ! TARGET_SH4"
3920 [(set_attr "type" "fp")])
3922 (define_expand "divsf3"
3923 [(match_operand:SF 0 "arith_reg_operand" "")
3924 (match_operand:SF 1 "arith_reg_operand" "")
3925 (match_operand:SF 2 "arith_reg_operand" "")]
3927 "{ expand_sf_binop (&gen_divsf3_i, operands); DONE; }")
3929 (define_insn "divsf3_i"
3930 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3931 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
3932 (match_operand:SF 2 "arith_reg_operand" "f")))
3933 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
3936 [(set_attr "type" "fdiv")])
3938 (define_expand "floatsisf2"
3940 (match_operand:SI 1 "arith_reg_operand" ""))
3941 (parallel [(set (match_operand:SF 0 "arith_reg_operand" "")
3942 (float:SF (reg:SI 22)))
3943 (use (match_dup 2))])]
3949 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 22),
3951 emit_sf_insn (gen_floatsisf2_i4 (operands[0], get_fpscr_rtx ()));
3954 operands[2] = get_fpscr_rtx ();
3957 (define_insn "floatsisf2_i4"
3958 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3959 (float:SF (reg:SI 22)))
3960 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
3963 [(set_attr "type" "fp")])
3965 (define_insn "*floatsisf2_ie"
3966 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3967 (float:SF (reg:SI 22)))]
3968 "TARGET_SH3E && ! TARGET_SH4"
3970 [(set_attr "type" "fp")])
3972 (define_expand "fix_truncsfsi2"
3974 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
3975 (set (match_operand:SI 0 "arith_reg_operand" "=r")
3982 emit_sf_insn (gen_fix_truncsfsi2_i4 (operands[1], get_fpscr_rtx ()));
3983 emit_insn (gen_rtx (SET, VOIDmode, operands[0],
3984 gen_rtx (REG, SImode, 22)));
3989 (define_insn "fix_truncsfsi2_i4"
3991 (fix:SI (match_operand:SF 0 "arith_reg_operand" "f")))
3992 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
3995 [(set_attr "type" "fp")])
3997 (define_insn "fix_truncsfsi2_i4_2"
3998 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3999 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4001 (clobber (reg:SI 22))]
4004 [(set_attr "length" "4")])
4007 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4008 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
4009 (use (match_operand:PSI 2 "fpscr_operand" "c"))
4010 (clobber (reg:SI 22))]
4012 [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
4013 (use (match_dup 2))])
4014 (set (match_dup 0) (reg:SI 22))])
4016 (define_insn "*fixsfsi"
4018 (fix:SI (match_operand:SF 0 "arith_reg_operand" "f")))]
4019 "TARGET_SH3E && ! TARGET_SH4"
4021 [(set_attr "type" "fp")])
4023 (define_insn "cmpgtsf_t"
4024 [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
4025 (match_operand:SF 1 "arith_reg_operand" "f")))]
4026 "TARGET_SH3E && ! TARGET_SH4"
4028 [(set_attr "type" "fp")])
4030 (define_insn "cmpeqsf_t"
4031 [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4032 (match_operand:SF 1 "arith_reg_operand" "f")))]
4033 "TARGET_SH3E && ! TARGET_SH4"
4035 [(set_attr "type" "fp")])
4037 (define_insn "ieee_ccmpeqsf_t"
4038 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4039 (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4040 (match_operand:SF 1 "arith_reg_operand" "f"))))]
4041 "TARGET_SH3E && TARGET_IEEE && ! TARGET_SH4"
4042 "* return output_ieee_ccmpeq (insn, operands);"
4043 [(set_attr "length" "4")])
4046 (define_insn "cmpgtsf_t_i4"
4047 [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
4048 (match_operand:SF 1 "arith_reg_operand" "f")))
4049 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4052 [(set_attr "type" "fp")])
4054 (define_insn "cmpeqsf_t_i4"
4055 [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4056 (match_operand:SF 1 "arith_reg_operand" "f")))
4057 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4060 [(set_attr "type" "fp")])
4062 (define_insn "*ieee_ccmpeqsf_t_4"
4063 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4064 (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
4065 (match_operand:SF 1 "arith_reg_operand" "f"))))
4066 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4067 "TARGET_IEEE && TARGET_SH4"
4068 "* return output_ieee_ccmpeq (insn, operands);"
4069 [(set_attr "length" "4")])
4071 (define_expand "cmpsf"
4072 [(set (reg:SI 18) (compare (match_operand:SF 0 "arith_operand" "")
4073 (match_operand:SF 1 "arith_operand" "")))]
4077 sh_compare_op0 = operands[0];
4078 sh_compare_op1 = operands[1];
4082 (define_expand "negsf2"
4083 [(match_operand:SF 0 "arith_reg_operand" "")
4084 (match_operand:SF 1 "arith_reg_operand" "")]
4086 "{ expand_sf_unop (&gen_negsf2_i, operands); DONE; }")
4088 (define_insn "negsf2_i"
4089 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4090 (neg:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4091 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4094 [(set_attr "type" "fmove")])
4096 (define_expand "sqrtsf2"
4097 [(match_operand:SF 0 "arith_reg_operand" "")
4098 (match_operand:SF 1 "arith_reg_operand" "")]
4100 "{ expand_sf_unop (&gen_sqrtsf2_i, operands); DONE; }")
4102 (define_insn "sqrtsf2_i"
4103 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4104 (sqrt:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4105 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4108 [(set_attr "type" "fdiv")])
4110 (define_expand "abssf2"
4111 [(match_operand:SF 0 "arith_reg_operand" "")
4112 (match_operand:SF 1 "arith_reg_operand" "")]
4114 "{ expand_sf_unop (&gen_abssf2_i, operands); DONE; }")
4116 (define_insn "abssf2_i"
4117 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
4118 (abs:SF (match_operand:SF 1 "arith_reg_operand" "0")))
4119 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4122 [(set_attr "type" "fmove")])
4124 (define_expand "adddf3"
4125 [(match_operand:DF 0 "arith_reg_operand" "")
4126 (match_operand:DF 1 "arith_reg_operand" "")
4127 (match_operand:DF 2 "arith_reg_operand" "")]
4129 "{ expand_df_binop (&gen_adddf3_i, operands); DONE; }")
4131 (define_insn "adddf3_i"
4132 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4133 (plus:DF (match_operand:DF 1 "arith_reg_operand" "%0")
4134 (match_operand:DF 2 "arith_reg_operand" "f")))
4135 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4138 [(set_attr "type" "dfp_arith")])
4140 (define_expand "subdf3"
4141 [(match_operand:DF 0 "arith_reg_operand" "")
4142 (match_operand:DF 1 "arith_reg_operand" "")
4143 (match_operand:DF 2 "arith_reg_operand" "")]
4145 "{ expand_df_binop (&gen_subdf3_i, operands); DONE; }")
4147 (define_insn "subdf3_i"
4148 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4149 (minus:DF (match_operand:DF 1 "arith_reg_operand" "0")
4150 (match_operand:DF 2 "arith_reg_operand" "f")))
4151 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4154 [(set_attr "type" "dfp_arith")])
4156 (define_expand "muldf3"
4157 [(match_operand:DF 0 "arith_reg_operand" "")
4158 (match_operand:DF 1 "arith_reg_operand" "")
4159 (match_operand:DF 2 "arith_reg_operand" "")]
4161 "{ expand_df_binop (&gen_muldf3_i, operands); DONE; }")
4163 (define_insn "muldf3_i"
4164 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4165 (mult:DF (match_operand:DF 1 "arith_reg_operand" "%0")
4166 (match_operand:DF 2 "arith_reg_operand" "f")))
4167 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4170 [(set_attr "type" "dfp_arith")])
4172 (define_expand "divdf3"
4173 [(match_operand:DF 0 "arith_reg_operand" "")
4174 (match_operand:DF 1 "arith_reg_operand" "")
4175 (match_operand:DF 2 "arith_reg_operand" "")]
4177 "{ expand_df_binop (&gen_divdf3_i, operands); DONE; }")
4179 (define_insn "divdf3_i"
4180 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4181 (div:DF (match_operand:DF 1 "arith_reg_operand" "0")
4182 (match_operand:DF 2 "arith_reg_operand" "f")))
4183 (use (match_operand:PSI 3 "fpscr_operand" "c"))]
4186 [(set_attr "type" "dfdiv")])
4188 (define_expand "floatsidf2"
4189 [(match_operand:DF 0 "arith_reg_operand" "")
4190 (match_operand:SI 1 "arith_reg_operand" "")]
4194 emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 22), operands[1]));
4195 emit_df_insn (gen_floatsidf2_i (operands[0], get_fpscr_rtx ()));
4199 (define_insn "floatsidf2_i"
4200 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4201 (float:DF (reg:SI 22)))
4202 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4205 [(set_attr "type" "dfp_conv")])
4207 (define_expand "fix_truncdfsi2"
4208 [(match_operand:SI 0 "arith_reg_operand" "=r")
4209 (match_operand:DF 1 "arith_reg_operand" "f")]
4213 emit_df_insn (gen_fix_truncdfsi2_i (operands[1], get_fpscr_rtx ()));
4214 emit_insn (gen_rtx (SET, VOIDmode, operands[0], gen_rtx (REG, SImode, 22)));
4218 (define_insn "fix_truncdfsi2_i"
4220 (fix:SI (match_operand:DF 0 "arith_reg_operand" "f")))
4221 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4224 [(set_attr "type" "dfp_conv")])
4226 (define_insn "fix_truncdfsi2_i4"
4227 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4228 (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4229 (use (match_operand:PSI 2 "fpscr_operand" "c"))
4230 (clobber (reg:SI 22))]
4233 [(set_attr "length" "4")])
4236 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4237 (fix:SI (match_operand:DF 1 "arith_reg_operand" "f")))
4238 (use (match_operand:PSI 2 "fpscr_operand" "c"))
4239 (clobber (reg:SI 22))]
4241 [(parallel [(set (reg:SI 22) (fix:SI (match_dup 1)))
4242 (use (match_dup 2))])
4243 (set (match_dup 0) (reg:SI 22))])
4245 (define_insn "cmpgtdf_t"
4246 [(set (reg:SI 18) (gt:SI (match_operand:DF 0 "arith_reg_operand" "f")
4247 (match_operand:DF 1 "arith_reg_operand" "f")))
4248 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4251 [(set_attr "type" "dfp_cmp")])
4253 (define_insn "cmpeqdf_t"
4254 [(set (reg:SI 18) (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4255 (match_operand:DF 1 "arith_reg_operand" "f")))
4256 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4259 [(set_attr "type" "dfp_cmp")])
4261 (define_insn "*ieee_ccmpeqdf_t"
4262 [(set (reg:SI 18) (ior:SI (reg:SI 18)
4263 (eq:SI (match_operand:DF 0 "arith_reg_operand" "f")
4264 (match_operand:DF 1 "arith_reg_operand" "f"))))
4265 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4266 "TARGET_IEEE && TARGET_SH4"
4267 "* return output_ieee_ccmpeq (insn, operands);"
4268 [(set_attr "length" "4")])
4270 (define_expand "cmpdf"
4271 [(set (reg:SI 18) (compare (match_operand:DF 0 "arith_operand" "")
4272 (match_operand:DF 1 "arith_operand" "")))]
4276 sh_compare_op0 = operands[0];
4277 sh_compare_op1 = operands[1];
4281 (define_expand "negdf2"
4282 [(match_operand:DF 0 "arith_reg_operand" "")
4283 (match_operand:DF 1 "arith_reg_operand" "")]
4285 "{ expand_df_unop (&gen_negdf2_i, operands); DONE; }")
4287 (define_insn "negdf2_i"
4288 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4289 (neg:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4290 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4293 [(set_attr "type" "fmove")])
4295 (define_expand "sqrtdf2"
4296 [(match_operand:DF 0 "arith_reg_operand" "")
4297 (match_operand:DF 1 "arith_reg_operand" "")]
4299 "{ expand_df_unop (&gen_sqrtdf2_i, operands); DONE; }")
4301 (define_insn "sqrtdf2_i"
4302 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4303 (sqrt:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4304 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4307 [(set_attr "type" "dfdiv")])
4309 (define_expand "absdf2"
4310 [(match_operand:DF 0 "arith_reg_operand" "")
4311 (match_operand:DF 1 "arith_reg_operand" "")]
4313 "{ expand_df_unop (&gen_absdf2_i, operands); DONE; }")
4315 (define_insn "absdf2_i"
4316 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4317 (abs:DF (match_operand:DF 1 "arith_reg_operand" "0")))
4318 (use (match_operand:PSI 2 "fpscr_operand" "c"))]
4321 [(set_attr "type" "fmove")])
4323 (define_expand "extendsfdf2"
4324 [(match_operand:DF 0 "arith_reg_operand" "")
4325 (match_operand:SF 1 "arith_reg_operand" "")]
4329 emit_sf_insn (gen_movsf_ie (gen_rtx (REG, SFmode, 22), operands[1],
4331 emit_df_insn (gen_extendsfdf2_i4 (operands[0], get_fpscr_rtx ()));
4335 (define_insn "extendsfdf2_i4"
4336 [(set (match_operand:DF 0 "arith_reg_operand" "=f")
4337 (float_extend:DF (reg:SF 22)))
4338 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4341 [(set_attr "type" "fp")])
4343 (define_expand "truncdfsf2"
4344 [(match_operand:SF 0 "arith_reg_operand" "")
4345 (match_operand:DF 1 "arith_reg_operand" "")]
4349 emit_df_insn (gen_truncdfsf2_i4 (operands[1], get_fpscr_rtx ()));
4350 emit_sf_insn (gen_movsf_ie (operands[0], gen_rtx (REG, SFmode, 22),
4355 (define_insn "truncdfsf2_i4"
4357 (float_truncate:SF (match_operand:DF 0 "arith_reg_operand" "f")))
4358 (use (match_operand:PSI 1 "fpscr_operand" "c"))]
4361 [(set_attr "type" "fp")])
4363 ;; Bit field extract patterns. These give better code for packed bitfields,
4364 ;; because they allow auto-increment addresses to be generated.
4366 (define_expand "insv"
4367 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
4368 (match_operand:SI 1 "immediate_operand" "")
4369 (match_operand:SI 2 "immediate_operand" ""))
4370 (match_operand:SI 3 "general_operand" ""))]
4371 "! TARGET_LITTLE_ENDIAN"
4374 rtx addr_target, orig_address, shift_reg;
4377 /* ??? expmed doesn't care for non-register predicates. */
4378 if (! memory_operand (operands[0], VOIDmode)
4379 || ! immediate_operand (operands[1], VOIDmode)
4380 || ! immediate_operand (operands[2], VOIDmode)
4381 || ! general_operand (operands[3], VOIDmode))
4383 /* If this isn't a 16 / 24 / 32 bit field, or if
4384 it doesn't start on a byte boundary, then fail. */
4385 size = INTVAL (operands[1]);
4386 if (size < 16 || size > 32 || size % 8 != 0
4387 || (INTVAL (operands[2]) % 8) != 0)
4391 orig_address = XEXP (operands[0], 0);
4392 shift_reg = gen_reg_rtx (SImode);
4393 emit_insn (gen_movsi (shift_reg, operands[3]));
4394 addr_target = copy_addr_to_reg (plus_constant (orig_address, size - 1));
4396 operands[0] = change_address (operands[0], QImode, addr_target);
4397 emit_insn (gen_movqi (operands[0], gen_rtx (SUBREG, QImode, shift_reg, 0)));
4401 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
4402 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
4403 emit_insn (gen_movqi (operands[0],
4404 gen_rtx (SUBREG, QImode, shift_reg, 0)));
4410 ;; -------------------------------------------------------------------------
4412 ;; -------------------------------------------------------------------------
4414 ;; This matches cases where a stack pointer increment at the start of the
4415 ;; epilogue combines with a stack slot read loading the return value.
4418 [(set (match_operand:SI 0 "arith_reg_operand" "")
4419 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
4420 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
4421 "REGNO (operands[1]) != REGNO (operands[0])"
4424 ;; See the comment on the dt combiner pattern above.
4427 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
4428 (plus:SI (match_dup 0)
4431 (eq:SI (match_dup 0)
4436 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
4437 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
4438 ;; reload when the constant is too large for a reg+offset address.
4440 ;; ??? We would get much better code if this was done in reload. This would
4441 ;; require modifying find_reloads_address to recognize that if the constant
4442 ;; is out-of-range for an immediate add, then we get better code by reloading
4443 ;; the constant into a register than by reloading the sum into a register,
4444 ;; since the former is one instruction shorter if the address does not need
4445 ;; to be offsettable. Unfortunately this does not work, because there is
4446 ;; only one register, r0, that can be used as an index register. This register
4447 ;; is also the function return value register. So, if we try to force reload
4448 ;; to use double-reg addresses, then we end up with some instructions that
4449 ;; need to use r0 twice. The only way to fix this is to change the calling
4450 ;; convention so that r0 is not used to return values.
4453 [(set (match_operand:SI 0 "register_operand" "=r")
4454 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4455 (set (mem:SI (match_dup 0))
4456 (match_operand:SI 2 "general_movsrc_operand" ""))]
4457 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4458 "mov.l %2,@(%0,%1)")
4461 [(set (match_operand:SI 0 "register_operand" "=r")
4462 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4463 (set (match_operand:SI 2 "general_movdst_operand" "")
4464 (mem:SI (match_dup 0)))]
4465 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4466 "mov.l @(%0,%1),%2")
4469 [(set (match_operand:SI 0 "register_operand" "=r")
4470 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4471 (set (mem:HI (match_dup 0))
4472 (match_operand:HI 2 "general_movsrc_operand" ""))]
4473 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4474 "mov.w %2,@(%0,%1)")
4477 [(set (match_operand:SI 0 "register_operand" "=r")
4478 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4479 (set (match_operand:HI 2 "general_movdst_operand" "")
4480 (mem:HI (match_dup 0)))]
4481 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4482 "mov.w @(%0,%1),%2")
4485 [(set (match_operand:SI 0 "register_operand" "=r")
4486 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4487 (set (mem:QI (match_dup 0))
4488 (match_operand:QI 2 "general_movsrc_operand" ""))]
4489 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4490 "mov.b %2,@(%0,%1)")
4493 [(set (match_operand:SI 0 "register_operand" "=r")
4494 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4495 (set (match_operand:QI 2 "general_movdst_operand" "")
4496 (mem:QI (match_dup 0)))]
4497 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
4498 "mov.b @(%0,%1),%2")
4501 [(set (match_operand:SI 0 "register_operand" "=r")
4502 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4503 (set (mem:SF (match_dup 0))
4504 (match_operand:SF 2 "general_movsrc_operand" ""))]
4505 "REGNO (operands[0]) == 0
4506 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
4507 || (GET_CODE (operands[2]) == SUBREG
4508 && REGNO (SUBREG_REG (operands[2])) < 16))
4509 && reg_unused_after (operands[0], insn)"
4510 "mov.l %2,@(%0,%1)")
4513 [(set (match_operand:SI 0 "register_operand" "=r")
4514 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4515 (set (match_operand:SF 2 "general_movdst_operand" "")
4517 (mem:SF (match_dup 0)))]
4518 "REGNO (operands[0]) == 0
4519 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
4520 || (GET_CODE (operands[2]) == SUBREG
4521 && REGNO (SUBREG_REG (operands[2])) < 16))
4522 && reg_unused_after (operands[0], insn)"
4523 "mov.l @(%0,%1),%2")
4526 [(set (match_operand:SI 0 "register_operand" "=r")
4527 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4528 (set (mem:SF (match_dup 0))
4529 (match_operand:SF 2 "general_movsrc_operand" ""))]
4530 "REGNO (operands[0]) == 0
4531 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
4532 || (GET_CODE (operands[2]) == SUBREG
4533 && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
4534 && reg_unused_after (operands[0], insn)"
4535 "fmov{.s|} %2,@(%0,%1)")
4538 [(set (match_operand:SI 0 "register_operand" "=r")
4539 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
4540 (set (match_operand:SF 2 "general_movdst_operand" "")
4542 (mem:SF (match_dup 0)))]
4543 "REGNO (operands[0]) == 0
4544 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
4545 || (GET_CODE (operands[2]) == SUBREG
4546 && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
4547 && reg_unused_after (operands[0], insn)"
4548 "fmov{.s|} @(%0,%1),%2")
4550 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
4551 (define_insn "sp_switch_1"
4558 xoperands[0] = sp_switch;
4559 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
4560 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
4561 return \"mov r0,r15\";
4563 [(set_attr "length" "10")])
4565 ;; Switch back to the original stack for interrupt functions with the
4566 ;; sp_switch attribute. */
4567 (define_insn "sp_switch_2"
4570 "mov.l @r15+,r15\;mov.l @r15+,r0"
4571 [(set_attr "length" "4")])