1 ;;- Machine description for the Hitachi SH.
2 ;; Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
24 ;; ??? Should prepend a * to all pattern names which are not used.
25 ;; This will make the compiler smaller, and rebuilds after changes faster.
27 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
28 ;; sequences. Especially the sequences for arithmetic right shifts.
30 ;; ??? Should check all DImode patterns for consistency and usefulness.
32 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
33 ;; way to generate them.
35 ;; ??? The cmp/str instruction is not supported. Perhaps it can be used
36 ;; for a str* inline function.
38 ;; BSR is not generated by the compiler proper, but when relaxing, it
39 ;; generates .uses pseudo-ops that allow linker relaxation to create
40 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
42 ;; Special constraints for SH machine description:
49 ;; Special formats used for outputting SH instructions:
51 ;; %. -- print a .s if insn needs delay slot
52 ;; %@ -- print rte/rts if is/isn't an interrupt function
53 ;; %# -- output a nop if there is nothing to put in the delay slot
54 ;; %O -- print a constant without the #
55 ;; %R -- print the lsw reg of a double
56 ;; %S -- print the msw reg of a double
57 ;; %T -- print next word of a double REG or MEM
59 ;; Special predicates:
61 ;; arith_operand -- operand is valid source for arithmetic op
62 ;; arith_reg_operand -- operand is valid register for arithmetic op
63 ;; general_movdst_operand -- operand is valid move destination
64 ;; general_movsrc_operand -- operand is valid move source
65 ;; logical_operand -- operand is valid source for logical op
66 ;; -------------------------------------------------------------------------
68 ;; -------------------------------------------------------------------------
74 (const (symbol_ref "sh_cpu_attr")))
76 (define_attr "endian" "big,little"
77 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
78 (const_string "little") (const_string "big"))))
80 ;; cbranch conditional branch instructions
81 ;; jump unconditional jumps
82 ;; arith ordinary arithmetic
83 ;; arith3 a compound insn that behaves similarily to a sequence of
84 ;; three insns of type arith
85 ;; arith3b like above, but might end with a redirected branch
87 ;; load_si Likewise, SImode variant for general register.
89 ;; move register to register
90 ;; fmove register to register, floating point
91 ;; smpy word precision integer multiply
92 ;; dmpy longword or doublelongword precision integer multiply
94 ;; pload load of pr reg, which can't be put into delay slot of rts
95 ;; pstore store of pr reg, which can't be put into delay slot of jsr
96 ;; pcload pc relative load of constant value
97 ;; pcload_si Likewise, SImode variant for general register.
98 ;; rte return from exception
99 ;; sfunc special function call with known used registers
100 ;; call function call
102 ;; fdiv floating point divide (or square root)
103 ;; gp_fpul move between general purpose register and fpul
104 ;; nil no-op move, will be deleted.
107 "cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,other,load,load_si,store,move,fmove,smpy,dmpy,return,pload,pstore,pcload,pcload_si,rte,sfunc,call,fp,fdiv,gp_fpul,nil"
108 (const_string "other"))
110 ; If a conditional branch destination is within -252..258 bytes away
111 ; from the instruction it can be 2 bytes long. Something in the
112 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
113 ; branches are initially assumed to be 16 bytes long.
114 ; In machine_dependent_reorg, we split all branches that are longer than
117 ; An unconditional jump in the range -4092..4098 can be 2 bytes long.
118 ; For wider ranges, we need a combination of a code and a data part.
119 ; If we can get a scratch register for a long range jump, the code
120 ; part can be 4 bytes long; otherwise, it must be 8 bytes long.
121 ; If the jump is in the range -32764..32770, the data part can be 2 bytes
122 ; long; otherwise, it must be 6 bytes long.
124 ; All other instructions are two bytes long by default.
126 (define_attr "length" ""
127 (cond [(eq_attr "type" "cbranch")
128 (cond [(ne (symbol_ref "short_cbranch_p (insn)") (const_int 0))
130 (ne (symbol_ref "med_branch_p (insn, 2)") (const_int 0))
132 (ne (symbol_ref "braf_branch_p (insn, 2)") (const_int 0))
137 (eq_attr "type" "jump")
138 (cond [(ne (symbol_ref "med_branch_p (insn, 0)") (const_int 0))
140 (and (eq (symbol_ref "GET_CODE (PREV_INSN (insn))")
142 (eq (symbol_ref "INSN_CODE (PREV_INSN (insn))")
143 (symbol_ref "code_for_indirect_jump_scratch")))
144 (if_then_else (ne (symbol_ref "braf_branch_p (insn, 0)")
148 (ne (symbol_ref "braf_branch_p (insn, 0)") (const_int 0))
155 ;; (define_function_unit {name} {num-units} {n-users} {test}
156 ;; {ready-delay} {issue-delay} [{conflict-list}])
158 ;; Load and store instructions save a cycle if they are aligned on a
159 ;; four byte boundary. Using a function unit for stores encourages
160 ;; gcc to separate load and store instructions by one instruction,
161 ;; which makes it more likely that the linker will be able to word
162 ;; align them when relaxing.
164 ;; Loads have a latency of two.
165 ;; However, call insn can have ;; a delay slot, so that we want one more
166 ;; insn to be scheduled between the load of the function address and the call.
167 ;; This is equivalent to a latency of three.
168 ;; We cannot use a conflict list for this, because we need to distinguish
169 ;; between the actual call address and the function arguments.
170 ;; ADJUST_COST can only properly handle reductions of the cost, so we
171 ;; use a latency of three here.
172 ;; We only do this for SImode loads of general regsiters, to make the work
173 ;; for ADJUST_COST easier.
174 (define_function_unit "memory" 1 0
175 (eq_attr "type" "load_si,pcload_si")
177 (define_function_unit "memory" 1 0
178 (eq_attr "type" "load,pcload,pload,store,pstore")
181 (define_function_unit "int" 1 0
182 (eq_attr "type" "arith3,arith3b") 3 3)
184 (define_function_unit "int" 1 0
185 (eq_attr "type" "dyn_shift") 2 2)
187 (define_function_unit "int" 1 0
188 (eq_attr "type" "arith,arith3b,dyn_shift") 2 2)
190 ;; ??? These are approximations.
191 (define_function_unit "mpy" 1 0 (eq_attr "type" "smpy") 2 2)
192 (define_function_unit "mpy" 1 0 (eq_attr "type" "dmpy") 3 3)
194 (define_function_unit "fp" 1 0 (eq_attr "type" "fp,fmove") 2 1)
195 (define_function_unit "fp" 1 0 (eq_attr "type" "fdiv") 13 12)
198 ; Definitions for filling branch delay slots.
200 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
202 (define_attr "hit_stack" "yes,no" (const_string "no"))
204 (define_attr "interrupt_function" "no,yes"
205 (const (symbol_ref "pragma_interrupt")))
207 (define_attr "in_delay_slot" "yes,no"
208 (cond [(eq_attr "type" "cbranch") (const_string "no")
209 (eq_attr "type" "pcload,pcload_si") (const_string "no")
210 (eq_attr "needs_delay_slot" "yes") (const_string "no")
211 (eq_attr "length" "2") (const_string "yes")
212 ] (const_string "no")))
215 (eq_attr "needs_delay_slot" "yes")
216 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
218 ;; On the SH and SH2, the rte instruction reads the return pc from the stack,
219 ;; and thus we can't put a pop instruction in its delay slot.
220 ;; ??? On the SH3, the rte instruction does not use the stack, so a pop
221 ;; instruction can go in the delay slot.
223 ;; Since a normal return (rts) implicitly uses the PR register,
224 ;; we can't allow PR register loads in an rts delay slot.
227 (eq_attr "type" "return")
228 [(and (eq_attr "in_delay_slot" "yes")
229 (ior (and (eq_attr "interrupt_function" "no")
230 (eq_attr "type" "!pload"))
231 (and (eq_attr "interrupt_function" "yes")
232 (eq_attr "hit_stack" "no")))) (nil) (nil)])
234 ;; Since a call implicitly uses the PR register, we can't allow
235 ;; a PR register store in a jsr delay slot.
238 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
239 [(and (eq_attr "in_delay_slot" "yes")
240 (eq_attr "type" "!pstore")) (nil) (nil)])
242 ;; Say that we have annulled true branches, since this gives smaller and
243 ;; faster code when branches are predicted as not taken.
246 (and (eq_attr "type" "cbranch")
247 (ne (symbol_ref "TARGET_SH2") (const_int 0)))
248 [(eq_attr "in_delay_slot" "yes") (eq_attr "in_delay_slot" "yes") (nil)])
250 ;; -------------------------------------------------------------------------
251 ;; SImode signed integer comparisons
252 ;; -------------------------------------------------------------------------
256 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "z,r")
257 (match_operand:SI 1 "arith_operand" "L,r"))
262 ;; ??? Perhaps should only accept reg/constant if the register is reg 0.
263 ;; That would still allow reload to create cmpi instructions, but would
264 ;; perhaps allow forcing the constant into a register when that is better.
265 ;; Probably should use r0 for mem/imm compares, but force constant into a
266 ;; register for pseudo/imm compares.
268 (define_insn "cmpeqsi_t"
269 [(set (reg:SI 18) (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
270 (match_operand:SI 1 "arith_operand" "N,rI,r")))]
277 (define_insn "cmpgtsi_t"
278 [(set (reg:SI 18) (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
279 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
285 (define_insn "cmpgesi_t"
286 [(set (reg:SI 18) (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
287 (match_operand:SI 1 "arith_reg_or_0_operand" "r,N")))]
293 ;; -------------------------------------------------------------------------
294 ;; SImode unsigned integer comparisons
295 ;; -------------------------------------------------------------------------
297 (define_insn "cmpgeusi_t"
298 [(set (reg:SI 18) (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
299 (match_operand:SI 1 "arith_reg_operand" "r")))]
303 (define_insn "cmpgtusi_t"
304 [(set (reg:SI 18) (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
305 (match_operand:SI 1 "arith_reg_operand" "r")))]
309 ;; We save the compare operands in the cmpxx patterns and use them when
310 ;; we generate the branch.
312 (define_expand "cmpsi"
313 [(set (reg:SI 18) (compare (match_operand:SI 0 "arith_operand" "")
314 (match_operand:SI 1 "arith_operand" "")))]
318 sh_compare_op0 = operands[0];
319 sh_compare_op1 = operands[1];
323 ;; -------------------------------------------------------------------------
324 ;; DImode signed integer comparisons
325 ;; -------------------------------------------------------------------------
327 ;; ??? Could get better scheduling by splitting the initial test from the
328 ;; rest of the insn after reload. However, the gain would hardly justify
329 ;; the sh.md size increase necessary to do that.
333 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
334 (match_operand:DI 1 "arith_operand" "r"))
337 "* return output_branchy_insn (EQ, \"tst\\t%S1,%S0\;bf\\t%l9\;tst\\t%R1,%R0\",
339 [(set_attr "length" "6")
340 (set_attr "type" "arith3b")])
342 (define_insn "cmpeqdi_t"
343 [(set (reg:SI 18) (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
344 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
347 return output_branchy_insn
350 ? \"cmp/eq\\t%S1,%S0\;bf\\t%l9\;cmp/eq\\t%R1,%R0\"
351 : \"tst\\t%S0,%S0\;bf\\t%l9\;tst\\t%R0,%R0\"),
353 [(set_attr "length" "6")
354 (set_attr "type" "arith3b")])
356 (define_insn "cmpgtdi_t"
357 [(set (reg:SI 18) (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
358 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
361 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/gt\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:
362 tst\\t%S0,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/pl\\t%S0\;cmp/hi\\t%S0,%R0\\n%,Ldi%=:"
363 [(set_attr "length" "8")
364 (set_attr "type" "arith3")])
366 (define_insn "cmpgedi_t"
367 [(set (reg:SI 18) (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
368 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
371 cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/ge\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:
373 [(set_attr "length" "8,2")
374 (set_attr "type" "arith3,arith")])
376 ;; -------------------------------------------------------------------------
377 ;; DImode unsigned integer comparisons
378 ;; -------------------------------------------------------------------------
380 (define_insn "cmpgeudi_t"
381 [(set (reg:SI 18) (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
382 (match_operand:DI 1 "arith_reg_operand" "r")))]
384 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hs\\t%S1,%S0\;cmp/hs\\t%R1,%R0\\n%,Ldi%=:"
385 [(set_attr "length" "8")
386 (set_attr "type" "arith3")])
388 (define_insn "cmpgtudi_t"
389 [(set (reg:SI 18) (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
390 (match_operand:DI 1 "arith_reg_operand" "r")))]
392 "cmp/eq\\t%S1,%S0\;bf{.|/}s\\t%,Ldi%=\;cmp/hi\\t%S1,%S0\;cmp/hi\\t%R1,%R0\\n%,Ldi%=:"
393 [(set_attr "length" "8")
394 (set_attr "type" "arith3")])
396 ;; We save the compare operands in the cmpxx patterns and use them when
397 ;; we generate the branch.
399 (define_expand "cmpdi"
400 [(set (reg:SI 18) (compare (match_operand:DI 0 "arith_operand" "")
401 (match_operand:DI 1 "arith_operand" "")))]
405 sh_compare_op0 = operands[0];
406 sh_compare_op1 = operands[1];
410 ;; -------------------------------------------------------------------------
411 ;; Addition instructions
412 ;; -------------------------------------------------------------------------
414 ;; ??? This should be a define expand.
416 (define_insn "adddi3"
417 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
418 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
419 (match_operand:DI 2 "arith_reg_operand" "r")))
420 (clobber (reg:SI 18))]
423 [(set_attr "length" "6")])
426 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
427 (plus:DI (match_operand:DI 1 "arith_reg_operand" "%0")
428 (match_operand:DI 2 "arith_reg_operand" "r")))
429 (clobber (reg:SI 18))]
434 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
435 high0 = gen_rtx (REG, SImode,
436 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
437 high2 = gen_rtx (REG, SImode,
438 true_regnum (operands[2]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
439 emit_insn (gen_clrt ());
440 emit_insn (gen_addc (low0, low0, gen_lowpart (SImode, operands[2])));
441 emit_insn (gen_addc1 (high0, high0, high2));
446 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
447 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
448 (match_operand:SI 2 "arith_reg_operand" "r"))
451 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
454 [(set_attr "type" "arith")])
457 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
458 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "0")
459 (match_operand:SI 2 "arith_reg_operand" "r"))
461 (clobber (reg:SI 18))]
464 [(set_attr "type" "arith")])
466 (define_insn "addsi3"
467 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
468 (plus:SI (match_operand:SI 1 "arith_operand" "%0")
469 (match_operand:SI 2 "arith_operand" "rI")))]
472 [(set_attr "type" "arith")])
474 ;; -------------------------------------------------------------------------
475 ;; Subtraction instructions
476 ;; -------------------------------------------------------------------------
478 ;; ??? This should be a define expand.
480 (define_insn "subdi3"
481 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
482 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
483 (match_operand:DI 2 "arith_reg_operand" "r")))
484 (clobber (reg:SI 18))]
487 [(set_attr "length" "6")])
490 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
491 (minus:DI (match_operand:DI 1 "arith_reg_operand" "0")
492 (match_operand:DI 2 "arith_reg_operand" "r")))
493 (clobber (reg:SI 18))]
498 rtx high0, high2, low0 = gen_lowpart (SImode, operands[0]);
499 high0 = gen_rtx (REG, SImode,
500 true_regnum (operands[0]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
501 high2 = gen_rtx (REG, SImode,
502 true_regnum (operands[2]) + (TARGET_LITTLE_ENDIAN ? 1 : 0));
503 emit_insn (gen_clrt ());
504 emit_insn (gen_subc (low0, low0, gen_lowpart (SImode, operands[2])));
505 emit_insn (gen_subc1 (high0, high0, high2));
510 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
511 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
512 (match_operand:SI 2 "arith_reg_operand" "r"))
515 (gtu:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
518 [(set_attr "type" "arith")])
521 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
522 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
523 (match_operand:SI 2 "arith_reg_operand" "r"))
525 (clobber (reg:SI 18))]
528 [(set_attr "type" "arith")])
530 (define_insn "*subsi3_internal"
531 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
532 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
533 (match_operand:SI 2 "arith_reg_operand" "r")))]
536 [(set_attr "type" "arith")])
538 ;; Convert `constant - reg' to `neg rX; add rX, #const' since this
539 ;; will sometimes save one instruction. Otherwise we might get
540 ;; `mov #const, rY; sub rY,rX; mov rX, rY' if the source and dest regs
543 (define_expand "subsi3"
544 [(set (match_operand:SI 0 "arith_reg_operand" "")
545 (minus:SI (match_operand:SI 1 "arith_operand" "")
546 (match_operand:SI 2 "arith_reg_operand" "")))]
550 if (GET_CODE (operands[1]) == CONST_INT)
552 emit_insn (gen_negsi2 (operands[0], operands[2]));
553 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
558 ;; -------------------------------------------------------------------------
559 ;; Division instructions
560 ;; -------------------------------------------------------------------------
562 ;; We take advantage of the library routines which don't clobber as many
563 ;; registers as a normal function call would.
565 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
566 ;; also has an effect on the register that holds the addres of the sfunc.
567 ;; To make this work, we have an extra dummy insns that shows the use
568 ;; of this register for reorg.
570 (define_insn "use_sfunc_addr"
571 [(set (reg:SI 17) (unspec [(match_operand:SI 0 "register_operand" "r")] 5))]
574 [(set_attr "length" "0")])
576 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
577 ;; hard register 0. If we used hard register 0, then the next instruction
578 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
579 ;; gets allocated to a stack slot that needs its address reloaded, then
580 ;; there is nothing to prevent reload from using r0 to reload the address.
581 ;; This reload would clobber the value in r0 we are trying to store.
582 ;; If we let reload allocate r0, then this problem can never happen.
585 [(set (match_operand:SI 0 "register_operand" "=z")
586 (udiv:SI (reg:SI 4) (reg:SI 5)))
587 (clobber (reg:SI 18))
588 (clobber (reg:SI 17))
590 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
593 [(set_attr "type" "sfunc")
594 (set_attr "needs_delay_slot" "yes")])
596 (define_expand "udivsi3"
597 [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
598 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
599 (set (match_dup 3) (symbol_ref:SI "__udivsi3"))
600 (parallel [(set (match_operand:SI 0 "register_operand" "")
603 (clobber (reg:SI 18))
604 (clobber (reg:SI 17))
606 (use (match_dup 3))])]
608 "operands[3] = gen_reg_rtx(SImode);")
611 [(set (match_operand:SI 0 "register_operand" "=z")
612 (div:SI (reg:SI 4) (reg:SI 5)))
613 (clobber (reg:SI 18))
614 (clobber (reg:SI 17))
618 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
621 [(set_attr "type" "sfunc")
622 (set_attr "needs_delay_slot" "yes")])
624 (define_expand "divsi3"
625 [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
626 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
627 (set (match_dup 3) (symbol_ref:SI "__sdivsi3"))
628 (parallel [(set (match_operand:SI 0 "register_operand" "")
631 (clobber (reg:SI 18))
632 (clobber (reg:SI 17))
636 (use (match_dup 3))])]
638 "operands[3] = gen_reg_rtx(SImode);")
640 ;; -------------------------------------------------------------------------
641 ;; Multiplication instructions
642 ;; -------------------------------------------------------------------------
646 (mult:SI (zero_extend:SI (match_operand:HI 0 "arith_reg_operand" "r"))
647 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r"))))]
650 [(set_attr "type" "smpy")])
654 (mult:SI (sign_extend:SI
655 (match_operand:HI 0 "arith_reg_operand" "r"))
657 (match_operand:HI 1 "arith_reg_operand" "r"))))]
660 [(set_attr "type" "smpy")])
662 (define_expand "mulhisi3"
664 (mult:SI (sign_extend:SI
665 (match_operand:HI 1 "arith_reg_operand" ""))
667 (match_operand:HI 2 "arith_reg_operand" ""))))
668 (set (match_operand:SI 0 "arith_reg_operand" "")
673 (define_expand "umulhisi3"
675 (mult:SI (zero_extend:SI
676 (match_operand:HI 1 "arith_reg_operand" ""))
678 (match_operand:HI 2 "arith_reg_operand" ""))))
679 (set (match_operand:SI 0 "arith_reg_operand" "")
684 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
685 ;; a call to a routine which clobbers known registers.
688 [(set (match_operand:SI 1 "register_operand" "=z")
689 (mult:SI (reg:SI 4) (reg:SI 5)))
690 (clobber (reg:SI 21))
691 (clobber (reg:SI 18))
692 (clobber (reg:SI 17))
696 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
699 [(set_attr "type" "sfunc")
700 (set_attr "needs_delay_slot" "yes")])
702 (define_expand "mulsi3_call"
703 [(set (reg:SI 4) (match_operand:SI 1 "general_operand" ""))
704 (set (reg:SI 5) (match_operand:SI 2 "general_operand" ""))
705 (set (match_dup 3) (symbol_ref:SI "__mulsi3"))
706 (parallel[(set (match_operand:SI 0 "register_operand" "")
709 (clobber (reg:SI 21))
710 (clobber (reg:SI 18))
711 (clobber (reg:SI 17))
715 (use (match_dup 3))])]
717 "operands[3] = gen_reg_rtx(SImode);")
721 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
722 (match_operand:SI 1 "arith_reg_operand" "r")))]
725 [(set_attr "type" "dmpy")])
727 (define_expand "mulsi3"
729 (mult:SI (match_operand:SI 1 "arith_reg_operand" "")
730 (match_operand:SI 2 "arith_reg_operand" "")))
731 (set (match_operand:SI 0 "arith_reg_operand" "")
739 /* ??? Does this give worse or better code? */
740 emit_insn (gen_mulsi3_call (operands[0], operands[1], operands[2]));
745 (define_insn "mulsidi3_i"
747 (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
748 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))))]
751 [(set_attr "type" "dmpy")])
753 (define_expand "mulsidi3"
755 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
756 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
757 (set (match_operand:DI 0 "arith_reg_operand" "")
762 /* We must swap the two words when copying them from MACH/MACL to the
764 if (TARGET_LITTLE_ENDIAN)
766 rtx low_dst = operand_subword (operands[0], 0, 1, DImode);
767 rtx high_dst = operand_subword (operands[0], 1, 1, DImode);
769 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
771 emit_insn (gen_rtx (CLOBBER, VOIDmode, operands[0]));
772 emit_move_insn (low_dst, gen_rtx (REG, SImode, 21));
773 emit_move_insn (high_dst, gen_rtx (REG, SImode, 20));
778 (define_insn "umulsidi3_i"
780 (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
781 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r"))))]
784 [(set_attr "type" "dmpy")])
786 (define_expand "umulsidi3"
788 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
789 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" ""))))
790 (set (match_operand:DI 0 "arith_reg_operand" "")
795 /* We must swap the two words when copying them from MACH/MACL to the
797 if (TARGET_LITTLE_ENDIAN)
799 rtx low_dst = operand_subword (operands[0], 0, 1, DImode);
800 rtx high_dst = operand_subword (operands[0], 1, 1, DImode);
802 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
804 emit_insn (gen_rtx (CLOBBER, VOIDmode, operands[0]));
805 emit_move_insn (low_dst, gen_rtx (REG, SImode, 21));
806 emit_move_insn (high_dst, gen_rtx (REG, SImode, 20));
814 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
815 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
817 (clobber (reg:SI 21))]
820 [(set_attr "type" "dmpy")])
822 (define_expand "smulsi3_highpart"
823 [(parallel [(set (reg:SI 20)
825 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
826 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
828 (clobber (reg:SI 21))])
829 (set (match_operand:SI 0 "arith_reg_operand" "")
837 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
838 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
840 (clobber (reg:SI 21))]
843 [(set_attr "type" "dmpy")])
845 (define_expand "umulsi3_highpart"
846 [(parallel [(set (reg:SI 20)
848 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" ""))
849 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand" "")))
851 (clobber (reg:SI 21))])
852 (set (match_operand:SI 0 "arith_reg_operand" "")
857 ;; -------------------------------------------------------------------------
858 ;; Logical operations
859 ;; -------------------------------------------------------------------------
862 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
863 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
864 (match_operand:SI 2 "logical_operand" "r,L")))]
867 [(set_attr "type" "arith")])
869 ;; If the constant is 255, then emit a extu.b instruction instead of an
870 ;; and, since that will give better code.
872 (define_expand "andsi3"
873 [(set (match_operand:SI 0 "arith_reg_operand" "")
874 (and:SI (match_operand:SI 1 "arith_reg_operand" "")
875 (match_operand:SI 2 "logical_operand" "")))]
879 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 255)
881 emit_insn (gen_zero_extendqisi2 (operands[0],
882 gen_lowpart (QImode, operands[1])));
887 (define_insn "iorsi3"
888 [(set (match_operand:SI 0 "arith_reg_operand" "=r,z")
889 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
890 (match_operand:SI 2 "logical_operand" "r,L")))]
893 [(set_attr "type" "arith")])
895 (define_insn "xorsi3"
896 [(set (match_operand:SI 0 "arith_reg_operand" "=z,r")
897 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
898 (match_operand:SI 2 "logical_operand" "L,r")))]
901 [(set_attr "type" "arith")])
903 ;; -------------------------------------------------------------------------
904 ;; Shifts and rotates
905 ;; -------------------------------------------------------------------------
907 (define_insn "rotlsi3_1"
908 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
909 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
912 (lshiftrt:SI (match_dup 1) (const_int 31)))]
915 [(set_attr "type" "arith")])
917 (define_insn "rotlsi3_31"
918 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
919 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
921 (clobber (reg:SI 18))]
924 [(set_attr "type" "arith")])
926 (define_insn "rotlsi3_16"
927 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
928 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
932 [(set_attr "type" "arith")])
934 (define_expand "rotlsi3"
935 [(set (match_operand:SI 0 "arith_reg_operand" "")
936 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "")
937 (match_operand:SI 2 "immediate_operand" "")))]
941 static char rot_tab[] = {
942 000, 000, 000, 000, 000, 000, 010, 001,
943 001, 001, 011, 013, 003, 003, 003, 003,
944 003, 003, 003, 003, 003, 013, 012, 002,
945 002, 002, 010, 000, 000, 000, 000, 000,
950 if (GET_CODE (operands[2]) != CONST_INT)
952 count = INTVAL (operands[2]);
953 choice = rot_tab[count];
954 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
960 emit_move_insn (operands[0], operands[1]);
961 count -= (count & 16) * 2;
964 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
971 parts[0] = gen_reg_rtx (SImode);
972 parts[1] = gen_reg_rtx (SImode);
973 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
974 parts[choice-1] = operands[1];
975 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
976 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
977 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
978 count = (count & ~16) - 8;
982 for (; count > 0; count--)
983 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
984 for (; count < 0; count++)
985 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
990 (define_insn "*rotlhi3_8"
991 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
992 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
996 [(set_attr "type" "arith")])
998 (define_expand "rotlhi3"
999 [(set (match_operand:HI 0 "arith_reg_operand" "")
1000 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "")
1001 (match_operand:HI 2 "immediate_operand" "")))]
1005 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 8)
1012 (define_insn "ashlsi3_d"
1013 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1014 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1015 (match_operand:SI 2 "arith_reg_operand" "r")))]
1018 [(set_attr "type" "dyn_shift")])
1020 (define_insn "ashlsi3_k"
1021 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
1022 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
1023 (match_operand:SI 2 "const_int_operand" "M,K")))]
1024 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1028 [(set_attr "type" "arith")])
1030 (define_insn "ashlhi3_k"
1031 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1032 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
1033 (match_operand:HI 2 "const_int_operand" "M,K")))]
1034 "CONST_OK_FOR_K (INTVAL (operands[2]))"
1038 [(set_attr "type" "arith")])
1040 (define_insn "ashlsi3_n"
1041 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1042 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
1043 (match_operand:SI 2 "const_int_operand" "n")))
1044 (clobber (reg:SI 18))]
1045 "! sh_dynamicalize_shift_p (operands[2])"
1047 [(set (attr "length")
1048 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1050 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1052 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1054 (const_string "8")))
1055 (set_attr "type" "arith")])
1058 [(set (match_operand:SI 0 "arith_reg_operand" "")
1059 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1060 (match_operand:SI 2 "const_int_operand" "n")))
1061 (clobber (reg:SI 18))]
1066 gen_shifty_op (ASHIFT, operands);
1070 (define_expand "ashlsi3"
1071 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1072 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
1073 (match_operand:SI 2 "nonmemory_operand" "")))
1074 (clobber (reg:SI 18))])]
1078 if (GET_CODE (operands[2]) == CONST_INT
1079 && sh_dynamicalize_shift_p (operands[2]))
1080 operands[2] = force_reg (SImode, operands[2]);
1081 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1083 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
1086 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1090 (define_insn "ashlhi3"
1091 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1092 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
1093 (match_operand:HI 2 "const_int_operand" "n")))
1094 (clobber (reg:SI 18))]
1097 [(set (attr "length")
1098 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1100 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1102 (const_string "6")))
1103 (set_attr "type" "arith")])
1106 [(set (match_operand:HI 0 "arith_reg_operand" "")
1107 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
1108 (match_operand:HI 2 "const_int_operand" "n")))
1109 (clobber (reg:SI 18))]
1114 gen_shifty_hi_op (ASHIFT, operands);
1119 ; arithmetic shift right
1122 (define_insn "ashrsi3_k"
1123 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1124 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1125 (match_operand:SI 2 "const_int_operand" "M")))
1126 (clobber (reg:SI 18))]
1127 "INTVAL (operands[2]) == 1"
1129 [(set_attr "type" "arith")])
1131 (define_insn "ashrhi3_k"
1132 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1133 (ashiftrt:HI (match_operand:HI 1 "arith_reg_operand" "0")
1134 (match_operand:HI 2 "const_int_operand" "M")))
1135 (clobber (reg:SI 18))]
1136 "INTVAL (operands[2]) == 1"
1138 [(set_attr "type" "arith")])
1140 ;; ??? This should be a define expand.
1142 (define_insn "ashrsi2_16"
1143 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1144 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1148 [(set_attr "length" "4")])
1151 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1152 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
1155 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
1156 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
1157 "operands[2] = gen_lowpart (HImode, operands[0]);")
1159 ;; ??? This should be a define expand.
1161 (define_insn "ashrsi2_31"
1162 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1163 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1165 (clobber (reg:SI 18))]
1168 [(set_attr "length" "4")])
1171 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1172 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1174 (clobber (reg:SI 18))]
1179 emit_insn (gen_ashlsi_c (operands[0], operands[1], operands[1]));
1180 emit_insn (gen_subc1 (operands[0], operands[0], operands[0]));
1184 (define_insn "ashlsi_c"
1185 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1186 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
1187 (set (reg:SI 18) (lt:SI (match_operand:SI 2 "arith_reg_operand" "0")
1191 [(set_attr "type" "arith")])
1193 (define_insn "ashrsi3_d"
1194 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1195 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1196 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1199 [(set_attr "type" "dyn_shift")])
1201 (define_insn "ashrsi3_n"
1203 (ashiftrt:SI (reg:SI 4)
1204 (match_operand:SI 0 "const_int_operand" "i")))
1205 (clobber (reg:SI 18))
1206 (clobber (reg:SI 17))
1207 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
1210 [(set_attr "type" "sfunc")
1211 (set_attr "needs_delay_slot" "yes")])
1213 (define_expand "ashrsi3"
1214 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1215 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1216 (match_operand:SI 2 "nonmemory_operand" "")))
1217 (clobber (reg:SI 18))])]
1219 "if (expand_ashiftrt (operands)) DONE; else FAIL;")
1221 ;; logical shift right
1223 (define_insn "lshrsi3_d"
1224 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1225 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1226 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
1229 [(set_attr "type" "dyn_shift")])
1231 ;; Only the single bit shift clobbers the T bit.
1233 (define_insn "lshrsi3_m"
1234 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1235 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1236 (match_operand:SI 2 "const_int_operand" "M")))
1237 (clobber (reg:SI 18))]
1238 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1240 [(set_attr "type" "arith")])
1242 (define_insn "lshrsi3_k"
1243 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1244 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1245 (match_operand:SI 2 "const_int_operand" "K")))]
1246 "CONST_OK_FOR_K (INTVAL (operands[2]))
1247 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1249 [(set_attr "type" "arith")])
1251 (define_insn "lshrhi3_m"
1252 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1253 (lshiftrt:HI (match_operand:HI 1 "arith_reg_operand" "0")
1254 (match_operand:HI 2 "const_int_operand" "M")))
1255 (clobber (reg:SI 18))]
1256 "CONST_OK_FOR_M (INTVAL (operands[2]))"
1258 [(set_attr "type" "arith")])
1260 (define_insn "lshrhi3_k"
1261 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1262 (lshiftrt:HI (match_operand:HI 1 "arith_reg_operand" "0")
1263 (match_operand:HI 2 "const_int_operand" "K")))]
1264 "CONST_OK_FOR_K (INTVAL (operands[2]))
1265 && ! CONST_OK_FOR_M (INTVAL (operands[2]))"
1267 [(set_attr "type" "arith")])
1269 (define_insn "lshrsi3_n"
1270 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1271 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1272 (match_operand:SI 2 "const_int_operand" "n")))
1273 (clobber (reg:SI 18))]
1274 "! sh_dynamicalize_shift_p (operands[2])"
1276 [(set (attr "length")
1277 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1279 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1281 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 3))
1283 (const_string "8")))
1284 (set_attr "type" "arith")])
1287 [(set (match_operand:SI 0 "arith_reg_operand" "")
1288 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1289 (match_operand:SI 2 "const_int_operand" "n")))
1290 (clobber (reg:SI 18))]
1295 gen_shifty_op (LSHIFTRT, operands);
1299 (define_expand "lshrsi3"
1300 [(parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
1301 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
1302 (match_operand:SI 2 "nonmemory_operand" "")))
1303 (clobber (reg:SI 18))])]
1307 if (GET_CODE (operands[2]) == CONST_INT
1308 && sh_dynamicalize_shift_p (operands[2]))
1309 operands[2] = force_reg (SImode, operands[2]);
1310 if (TARGET_SH3 && arith_reg_operand (operands[2], GET_MODE (operands[2])))
1312 rtx count = copy_to_mode_reg (SImode, operands[2]);
1313 emit_insn (gen_negsi2 (count, count));
1314 emit_insn (gen_lshrsi3_d (operands[0], operands[1], count));
1317 if (! immediate_operand (operands[2], GET_MODE (operands[2])))
1321 (define_insn "lshrhi3"
1322 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1323 (lshiftrt:HI (match_operand:HI 1 "arith_reg_operand" "0")
1324 (match_operand:HI 2 "const_int_operand" "n")))
1325 (clobber (reg:SI 18))]
1328 ;; ??? length attribute is sometimes six instead of four.
1329 [(set (attr "length")
1330 (cond [(eq (symbol_ref "shift_insns_rtx (insn)") (const_int 1))
1332 (eq (symbol_ref "shift_insns_rtx (insn)") (const_int 2))
1334 (const_string "6")))
1335 (set_attr "type" "arith")])
1338 [(set (match_operand:HI 0 "arith_reg_operand" "")
1339 (lshiftrt:HI (match_operand:HI 1 "arith_reg_operand" "")
1340 (match_operand:HI 2 "const_int_operand" "n")))
1341 (clobber (reg:SI 18))]
1346 gen_shifty_hi_op (LSHIFTRT, operands);
1350 ;; ??? This should be a define expand.
1352 (define_insn "ashldi3_k"
1353 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1354 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
1356 (clobber (reg:SI 18))]
1358 "shll %R0\;rotcl %S0"
1359 [(set_attr "length" "4")
1360 (set_attr "type" "arith")])
1362 (define_expand "ashldi3"
1363 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1364 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
1365 (match_operand:DI 2 "immediate_operand" "")))
1366 (clobber (reg:SI 18))])]
1368 "{ if (GET_CODE (operands[2]) != CONST_INT
1369 || INTVAL (operands[2]) != 1) FAIL;} ")
1371 ;; ??? This should be a define expand.
1373 (define_insn "lshrdi3_k"
1374 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1375 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1377 (clobber (reg:SI 18))]
1379 "shlr %S0\;rotcr %R0"
1380 [(set_attr "length" "4")
1381 (set_attr "type" "arith")])
1383 (define_expand "lshrdi3"
1384 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1385 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1386 (match_operand:DI 2 "immediate_operand" "")))
1387 (clobber (reg:SI 18))])]
1389 "{ if (GET_CODE (operands[2]) != CONST_INT
1390 || INTVAL (operands[2]) != 1) FAIL;} ")
1392 ;; ??? This should be a define expand.
1394 (define_insn "ashrdi3_k"
1395 [(set (match_operand:DI 0 "arith_reg_operand" "=r")
1396 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
1398 (clobber (reg:SI 18))]
1400 "shar %S0\;rotcr %R0"
1401 [(set_attr "length" "4")
1402 (set_attr "type" "arith")])
1404 (define_expand "ashrdi3"
1405 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
1406 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
1407 (match_operand:DI 2 "immediate_operand" "")))
1408 (clobber (reg:SI 18))])]
1410 "{ if (GET_CODE (operands[2]) != CONST_INT
1411 || INTVAL (operands[2]) != 1) FAIL; } ")
1413 ;; combined left/right shift
1416 [(set (match_operand:SI 0 "register_operand" "")
1417 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1418 (match_operand:SI 2 "const_int_operand" "n"))
1419 (match_operand:SI 3 "const_int_operand" "n")))]
1420 "(unsigned)INTVAL (operands[2]) < 32"
1422 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
1426 [(set (match_operand:SI 0 "register_operand" "")
1427 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
1428 (match_operand:SI 2 "const_int_operand" "n"))
1429 (match_operand:SI 3 "const_int_operand" "n")))
1430 (clobber (reg:SI 18))]
1431 "(unsigned)INTVAL (operands[2]) < 32"
1433 "if (gen_shl_and (operands[0], operands[2], operands[3], operands[1])) FAIL;
1437 [(set (match_operand:SI 0 "register_operand" "=r")
1438 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1439 (match_operand:SI 2 "const_int_operand" "n"))
1440 (match_operand:SI 3 "const_int_operand" "n")))
1441 (clobber (reg:SI 18))]
1442 "shl_and_kind (operands[2], operands[3], 0) == 1"
1444 [(set (attr "length")
1445 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
1447 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
1449 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
1451 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
1453 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
1455 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
1457 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
1458 (const_string "16")]
1459 (const_string "18")))
1460 (set_attr "type" "arith")])
1463 [(set (match_operand:SI 0 "register_operand" "=z")
1464 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1465 (match_operand:SI 2 "const_int_operand" "n"))
1466 (match_operand:SI 3 "const_int_operand" "n")))
1467 (clobber (reg:SI 18))]
1468 "shl_and_kind (operands[2], operands[3], 0) == 2"
1470 [(set (attr "length")
1471 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
1473 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
1475 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
1477 (const_string "10")))
1478 (set_attr "type" "arith")])
1480 ;; shift left / and combination with a scratch register: The combine pass
1481 ;; does not accept the individual instructions, even though they are
1482 ;; cheap. But it needs a precise description so that it is usable after
1484 (define_insn "and_shl_scratch"
1485 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1486 (lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
1487 (match_operand:SI 2 "const_int_operand" "N,n"))
1488 (match_operand:SI 3 "" "0,r"))
1489 (match_operand:SI 4 "const_int_operand" "n,n"))
1490 (match_operand:SI 5 "const_int_operand" "n,n")))
1491 (clobber (reg:SI 18))]
1494 [(set (attr "length")
1495 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
1497 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
1499 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
1501 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
1502 (const_string "10")]
1503 (const_string "12")))
1504 (set_attr "type" "arith")])
1507 [(set (match_operand:SI 0 "register_operand" "=r,&r")
1508 (lshiftrt:SI (ashift:SI (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
1509 (match_operand:SI 2 "const_int_operand" "N,n"))
1510 (match_operand:SI 3 "register_operand" "0,r"))
1511 (match_operand:SI 4 "const_int_operand" "n,n"))
1512 (match_operand:SI 5 "const_int_operand" "n,n")))
1513 (clobber (reg:SI 18))]
1518 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
1520 if (INTVAL (operands[2]))
1522 gen_shifty_op (LSHIFTRT, operands);
1524 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
1525 operands[2] = operands[4];
1526 gen_shifty_op (ASHIFT, operands);
1527 if (INTVAL (operands[5]))
1529 operands[2] = operands[5];
1530 gen_shifty_op (LSHIFTRT, operands);
1535 ;; signed left/right shift combination.
1537 [(set (match_operand:SI 0 "register_operand" "=r")
1538 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
1539 (match_operand:SI 2 "const_int_operand" "n"))
1540 (match_operand:SI 3 "const_int_operand" "n")
1542 (clobber (reg:SI 18))]
1545 "if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1])) FAIL;
1548 (define_insn "shl_sext_ext"
1549 [(set (match_operand:SI 0 "register_operand" "=r")
1550 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1551 (match_operand:SI 2 "const_int_operand" "n"))
1552 (match_operand:SI 3 "const_int_operand" "n")
1554 (clobber (reg:SI 18))]
1555 "(unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
1557 [(set (attr "length")
1558 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 1))
1560 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
1562 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
1564 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
1566 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
1568 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
1570 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
1572 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
1573 (const_string "16")]
1574 (const_string "18")))
1575 (set_attr "type" "arith")])
1577 (define_insn "shl_sext_sub"
1578 [(set (match_operand:SI 0 "register_operand" "=z")
1579 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
1580 (match_operand:SI 2 "const_int_operand" "n"))
1581 (match_operand:SI 3 "const_int_operand" "n")
1583 (clobber (reg:SI 18))]
1584 "(shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
1586 [(set (attr "length")
1587 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
1589 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
1591 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
1593 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
1594 (const_string "12")]
1595 (const_string "14")))
1596 (set_attr "type" "arith")])
1598 ;; These patterns are found in expansions of DImode shifts by 16, and
1599 ;; allow the xtrct instruction to be generated from C source.
1601 (define_insn "xtrct_left"
1602 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1603 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
1605 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
1609 [(set_attr "type" "arith")])
1611 (define_insn "xtrct_right"
1612 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1613 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
1615 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
1619 [(set_attr "type" "arith")])
1621 ;; -------------------------------------------------------------------------
1623 ;; -------------------------------------------------------------------------
1626 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1627 (neg:SI (plus:SI (reg:SI 18)
1628 (match_operand:SI 1 "arith_reg_operand" "r"))))
1630 (ne:SI (ior:SI (reg:SI 18) (match_dup 1))
1634 [(set_attr "type" "arith")])
1636 (define_expand "negdi2"
1637 [(set (match_operand:DI 0 "arith_reg_operand" "")
1638 (neg:DI (match_operand:DI 1 "arith_reg_operand" "")))
1639 (clobber (reg:SI 18))]
1643 int low_word = (TARGET_LITTLE_ENDIAN ? 0 : 1);
1644 int high_word = (TARGET_LITTLE_ENDIAN ? 1 : 0);
1646 rtx low_src = operand_subword (operands[1], low_word, 0, DImode);
1647 rtx high_src = operand_subword (operands[1], high_word, 0, DImode);
1649 rtx low_dst = operand_subword (operands[0], low_word, 1, DImode);
1650 rtx high_dst = operand_subword (operands[0], high_word, 1, DImode);
1652 emit_insn (gen_clrt ());
1653 emit_insn (gen_negc (low_dst, low_src));
1654 emit_insn (gen_negc (high_dst, high_src));
1658 (define_insn "negsi2"
1659 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1660 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
1663 [(set_attr "type" "arith")])
1665 (define_insn "one_cmplsi2"
1666 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1667 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
1670 [(set_attr "type" "arith")])
1672 ;; -------------------------------------------------------------------------
1673 ;; Zero extension instructions
1674 ;; -------------------------------------------------------------------------
1676 (define_insn "zero_extendhisi2"
1677 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1678 (zero_extend:SI (match_operand:HI 1 "arith_reg_operand" "r")))]
1681 [(set_attr "type" "arith")])
1683 (define_insn "zero_extendqisi2"
1684 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
1685 (zero_extend:SI (match_operand:QI 1 "arith_reg_operand" "r")))]
1688 [(set_attr "type" "arith")])
1690 (define_insn "zero_extendqihi2"
1691 [(set (match_operand:HI 0 "arith_reg_operand" "=r")
1692 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
1695 [(set_attr "type" "arith")])
1697 ;; -------------------------------------------------------------------------
1698 ;; Sign extension instructions
1699 ;; -------------------------------------------------------------------------
1701 ;; ??? This should be a define expand.
1702 ;; ??? Or perhaps it should be dropped?
1704 /* There is no point in defining extendsidi2; convert_move generates good
1707 (define_insn "extendhisi2"
1708 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
1709 (sign_extend:SI (match_operand:HI 1 "general_movsrc_operand" "r,m")))]
1714 [(set_attr "type" "arith,load")])
1716 (define_insn "extendqisi2"
1717 [(set (match_operand:SI 0 "arith_reg_operand" "=r,r")
1718 (sign_extend:SI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
1723 [(set_attr "type" "arith,load")])
1725 (define_insn "extendqihi2"
1726 [(set (match_operand:HI 0 "arith_reg_operand" "=r,r")
1727 (sign_extend:HI (match_operand:QI 1 "general_movsrc_operand" "r,m")))]
1732 [(set_attr "type" "arith,load")])
1734 ;; -------------------------------------------------------------------------
1735 ;; Move instructions
1736 ;; -------------------------------------------------------------------------
1738 ;; define push and pop so it is easy for sh.c
1741 [(set (mem:SI (pre_dec:SI (reg:SI 15)))
1742 (match_operand:SI 0 "register_operand" "r,l,x"))]
1748 [(set_attr "type" "store,pstore,store")
1749 (set_attr "hit_stack" "yes")])
1752 [(set (match_operand:SI 0 "register_operand" "=r,l,x")
1753 (mem:SI (post_inc:SI (reg:SI 15))))]
1759 [(set_attr "type" "load,pload,load")
1760 (set_attr "hit_stack" "yes")])
1762 (define_insn "push_e"
1763 [(set (mem:SF (pre_dec:SI (reg:SI 15)))
1764 (match_operand:SF 0 "register_operand" "r,f,y"))]
1770 [(set_attr "type" "store")
1771 (set_attr "hit_stack" "yes")])
1773 (define_insn "pop_e"
1774 [(set (match_operand:SF 0 "register_operand" "=r,f,y")
1775 (mem:SF (post_inc:SI (reg:SI 15))))]
1781 [(set_attr "type" "load")
1782 (set_attr "hit_stack" "yes")])
1784 ;; These two patterns can happen as the result of optimization, when
1785 ;; comparisons get simplified to a move of zero or 1 into the T reg.
1786 ;; They don't disappear completely, because the T reg is a fixed hard reg.
1789 [(set (reg:SI 18) (const_int 0))]
1794 [(set (reg:SI 18) (const_int 1))]
1798 ;; t/r is first, so that it will be preferred over r/r when reloading a move
1799 ;; of a pseudo-reg into the T reg
1800 (define_insn "movsi_i"
1801 [(set (match_operand:SI 0 "general_movdst_operand" "=t,r,r,r,r,r,m,<,<,xl,x,l,r")
1802 (match_operand:SI 1 "general_movsrc_operand" "r,Q,rI,m,xl,t,r,x,l,r,>,>,i"))]
1805 && (register_operand (operands[0], SImode)
1806 || register_operand (operands[1], SImode))"
1821 [(set_attr "type" "*,pcload_si,move,load_si,move,move,store,store,pstore,move,load,pload,pcload_si")
1822 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*")])
1824 ;; t/r must come after r/r, lest reload will try to reload stuff like
1825 ;; (subreg:SI (reg:SF 38 fr14) 0) into T (compiling stdlib/strtod.c -m3e -O2)
1826 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
1827 ;; will require a reload.
1828 (define_insn "movsi_ie"
1829 [(set (match_operand:SI 0 "general_movdst_operand" "=r,r,t,r,r,r,m,<,<,xl,x,l,r,y,r,y")
1830 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,r,m,xl,t,r,x,l,r,>,>,i,r,y,y"))]
1832 && (register_operand (operands[0], SImode)
1833 || register_operand (operands[1], SImode))"
1850 ! move optimized away"
1851 [(set_attr "type" "pcload_si,move,*,load_si,move,move,store,store,pstore,move,load,pload,pcload_si,gp_fpul,gp_fpul,nil")
1852 (set_attr "length" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
1854 (define_insn "movsi_i_lowpart"
1855 [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "=r,r,r,r,r,m,r"))
1856 (match_operand:SI 1 "general_movsrc_operand" "Q,rI,m,xl,t,r,i"))]
1857 "register_operand (operands[0], SImode)
1858 || register_operand (operands[1], SImode)"
1867 [(set_attr "type" "pcload,move,load,move,move,store,pcload")])
1868 (define_expand "movsi"
1869 [(set (match_operand:SI 0 "general_movdst_operand" "")
1870 (match_operand:SI 1 "general_movsrc_operand" ""))]
1872 "{ if (prepare_move_operands (operands, SImode)) DONE; }")
1874 (define_insn "movqi_i"
1875 [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,r,l")
1876 (match_operand:QI 1 "general_movsrc_operand" "ri,m,r,t,l,r"))]
1877 "arith_reg_operand (operands[0], QImode)
1878 || arith_reg_operand (operands[1], QImode)"
1886 [(set_attr "type" "move,load,store,move,move,move")])
1888 (define_expand "movqi"
1889 [(set (match_operand:QI 0 "general_operand" "")
1890 (match_operand:QI 1 "general_operand" ""))]
1892 "{ if (prepare_move_operands (operands, QImode)) DONE; }")
1894 (define_insn "movhi_i"
1895 [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,r,m,r,l,r")
1896 (match_operand:HI 1 "general_movsrc_operand" "Q,rI,m,t,r,l,r,i"))]
1897 "arith_reg_operand (operands[0], HImode)
1898 || arith_reg_operand (operands[1], HImode)"
1908 [(set_attr "type" "pcload,move,load,move,store,move,move,pcload")])
1910 (define_expand "movhi"
1911 [(set (match_operand:HI 0 "general_movdst_operand" "")
1912 (match_operand:HI 1 "general_movsrc_operand" ""))]
1914 "{ if (prepare_move_operands (operands, HImode)) DONE; }")
1916 ;; ??? This should be a define expand.
1918 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
1919 ;; compiled with -m2 -ml -O3 -funroll-loops
1921 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m,r,r,r,*!x")
1922 (match_operand:DI 1 "general_movsrc_operand" "Q,r,m,r,I,i,x,r"))]
1923 "arith_reg_operand (operands[0], DImode)
1924 || arith_reg_operand (operands[1], DImode)"
1925 "* return output_movedouble (insn, operands, DImode);"
1926 [(set_attr "length" "4")
1927 (set_attr "type" "pcload,move,load,store,move,pcload,move,move")])
1929 ;; If the output is a register and the input is memory or a register, we have
1930 ;; to be careful and see which word needs to be loaded first.
1933 [(set (match_operand:DI 0 "general_movdst_operand" "")
1934 (match_operand:DI 1 "general_movsrc_operand" ""))]
1936 [(set (match_dup 2) (match_dup 3))
1937 (set (match_dup 4) (match_dup 5))]
1942 if ((GET_CODE (operands[0]) == MEM
1943 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1944 || (GET_CODE (operands[1]) == MEM
1945 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
1948 if (GET_CODE (operands[0]) == REG)
1949 regno = REGNO (operands[0]);
1950 else if (GET_CODE (operands[0]) == SUBREG)
1951 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
1952 else if (GET_CODE (operands[0]) == MEM)
1956 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
1958 operands[2] = operand_subword (operands[0], 0, 0, DImode);
1959 operands[3] = operand_subword (operands[1], 0, 0, DImode);
1960 operands[4] = operand_subword (operands[0], 1, 0, DImode);
1961 operands[5] = operand_subword (operands[1], 1, 0, DImode);
1965 operands[2] = operand_subword (operands[0], 1, 0, DImode);
1966 operands[3] = operand_subword (operands[1], 1, 0, DImode);
1967 operands[4] = operand_subword (operands[0], 0, 0, DImode);
1968 operands[5] = operand_subword (operands[1], 0, 0, DImode);
1971 if (operands[2] == 0 || operands[3] == 0
1972 || operands[4] == 0 || operands[5] == 0)
1976 (define_expand "movdi"
1977 [(set (match_operand:DI 0 "general_movdst_operand" "")
1978 (match_operand:DI 1 "general_movsrc_operand" ""))]
1980 "{ if ( prepare_move_operands (operands, DImode)) DONE; }")
1982 ;; ??? This should be a define expand.
1984 (define_insn "movdf_k"
1985 [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
1986 (match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
1987 "arith_reg_operand (operands[0], DFmode)
1988 || arith_reg_operand (operands[1], DFmode)"
1989 "* return output_movedouble (insn, operands, DFmode);"
1990 [(set_attr "length" "4")
1991 (set_attr "type" "move,pcload,load,store")])
1993 ;; If the output is a register and the input is memory or a register, we have
1994 ;; to be careful and see which word needs to be loaded first.
1997 [(set (match_operand:DF 0 "general_movdst_operand" "")
1998 (match_operand:DF 1 "general_movsrc_operand" ""))]
2000 [(set (match_dup 2) (match_dup 3))
2001 (set (match_dup 4) (match_dup 5))]
2006 if ((GET_CODE (operands[0]) == MEM
2007 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2008 || (GET_CODE (operands[1]) == MEM
2009 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
2012 if (GET_CODE (operands[0]) == REG)
2013 regno = REGNO (operands[0]);
2014 else if (GET_CODE (operands[0]) == SUBREG)
2015 regno = REGNO (SUBREG_REG (operands[0])) + SUBREG_WORD (operands[0]);
2016 else if (GET_CODE (operands[0]) == MEM)
2020 || ! refers_to_regno_p (regno, regno + 1, operands[1], 0))
2022 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2023 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2024 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2025 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
2029 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
2030 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
2031 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
2032 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
2035 if (operands[2] == 0 || operands[3] == 0
2036 || operands[4] == 0 || operands[5] == 0)
2040 ;; If a base address generated by LEGITIMIZE_ADDRESS for SImode is
2041 ;; used only once, let combine add in the index again.
2044 [(set (match_operand:SI 0 "register_operand" "")
2045 (match_operand:SI 1 "" ""))
2046 (clobber (match_operand 2 "register_operand" ""))]
2047 "! reload_in_progress && ! reload_completed"
2051 rtx addr, reg, const_int;
2053 if (GET_CODE (operands[1]) != MEM)
2055 addr = XEXP (operands[1], 0);
2056 if (GET_CODE (addr) != PLUS)
2058 reg = XEXP (addr, 0);
2059 const_int = XEXP (addr, 1);
2060 if (GET_CODE (reg) != REG || GET_CODE (const_int) != CONST_INT)
2062 emit_move_insn (operands[2], const_int);
2063 emit_move_insn (operands[0],
2064 change_address (operands[1], VOIDmode,
2065 gen_rtx (PLUS, SImode, reg, operands[2])));
2070 [(set (match_operand:SI 1 "" "")
2071 (match_operand:SI 0 "register_operand" ""))
2072 (clobber (match_operand 2 "register_operand" ""))]
2073 "! reload_in_progress && ! reload_completed"
2077 rtx addr, reg, const_int;
2079 if (GET_CODE (operands[1]) != MEM)
2081 addr = XEXP (operands[1], 0);
2082 if (GET_CODE (addr) != PLUS)
2084 reg = XEXP (addr, 0);
2085 const_int = XEXP (addr, 1);
2086 if (GET_CODE (reg) != REG || GET_CODE (const_int) != CONST_INT)
2088 emit_move_insn (operands[2], const_int);
2089 emit_move_insn (change_address (operands[1], VOIDmode,
2090 gen_rtx (PLUS, SImode, reg, operands[2])),
2095 (define_expand "movdf"
2096 [(set (match_operand:DF 0 "general_movdst_operand" "")
2097 (match_operand:DF 1 "general_movsrc_operand" ""))]
2101 if (prepare_move_operands (operands, DFmode)) DONE;
2105 (define_insn "movsf_i"
2106 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r,r,r,m,l,r")
2107 (match_operand:SF 1 "general_movsrc_operand" "r,I,FQ,m,r,r,l"))]
2110 && (arith_reg_operand (operands[0], SFmode)
2111 || arith_reg_operand (operands[1], SFmode))"
2120 [(set_attr "type" "move,move,pcload,load,store,move,move")])
2122 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
2123 ;; update_flow_info would not know where to put REG_EQUAL notes
2124 ;; when the destination changes mode.
2125 (define_insn "movsf_ie"
2126 [(set (match_operand:SF 0 "general_movdst_operand"
2127 "=f,r,f,f,fy,f,m,r,r,m,f,y,y,rf,r,y,y")
2128 (match_operand:SF 1 "general_movsrc_operand"
2129 "f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y"))
2130 (clobber (match_scratch:SI 2 "=X,X,X,X,&z,X,X,X,X,X,X,X,X,y,X,X,X"))]
2133 && (arith_reg_operand (operands[0], SFmode)
2134 || arith_reg_operand (operands[1], SFmode))"
2152 ! move optimized away"
2153 [(set_attr "type" "fmove,move,fmove,fmove,pcload,load,store,pcload,load,store,fmove,fmove,load,*,gp_fpul,gp_fpul,nil")
2154 (set_attr "length" "*,*,*,*,4,*,*,*,*,*,2,2,2,*,2,2,0")])
2157 [(set (match_operand:SF 0 "register_operand" "")
2158 (match_operand:SF 1 "register_operand" ""))
2159 (clobber (reg:SI 22))]
2161 [(parallel [(set (reg:SF 22) (match_dup 1))
2162 (clobber (scratch:SI))])
2163 (parallel [(set (match_dup 0) (reg:SF 22))
2164 (clobber (scratch:SI))])]
2167 (define_expand "movsf"
2168 [(set (match_operand:SF 0 "general_movdst_operand" "")
2169 (match_operand:SF 1 "general_movsrc_operand" ""))]
2173 if (prepare_move_operands (operands, SFmode))
2177 emit_insn (gen_movsf_ie (operands[0], operands[1]));
2182 (define_expand "reload_insf"
2183 [(parallel [(set (match_operand:SF 0 "register_operand" "=f")
2184 (match_operand:SF 1 "immediate_operand" "FQ"))
2185 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
2189 ;; ------------------------------------------------------------------------
2190 ;; Define the real conditional branch instructions.
2191 ;; ------------------------------------------------------------------------
2193 (define_insn "branch_true"
2194 [(set (pc) (if_then_else (ne (reg:SI 18) (const_int 0))
2195 (label_ref (match_operand 0 "" ""))
2198 "* return output_branch (1, insn, operands);"
2199 [(set_attr "type" "cbranch")])
2201 (define_insn "branch_false"
2202 [(set (pc) (if_then_else (eq (reg:SI 18) (const_int 0))
2203 (label_ref (match_operand 0 "" ""))
2206 "* return output_branch (0, insn, operands);"
2207 [(set_attr "type" "cbranch")])
2209 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
2210 ;; which destination is too far away.
2211 ;; The const_int_operand is distinct for each branch target; it avoids
2212 ;; unwanted matches with redundant_insn.
2213 (define_insn "block_branch_redirect"
2214 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] 4))]
2217 [(set_attr "length" "0")])
2219 ;; This one has the additional purpose to record a possible scratch register
2220 ;; for the following branch.
2221 (define_insn "indirect_jump_scratch"
2222 [(set (match_operand 0 "register_operand" "r")
2223 (unspec [(match_operand 1 "const_int_operand" "")] 4))]
2226 [(set_attr "length" "0")])
2228 ;; Conditional branch insns
2230 (define_expand "beq"
2232 (if_then_else (ne (reg:SI 18) (const_int 0))
2233 (label_ref (match_operand 0 "" ""))
2236 "from_compare (operands, EQ);")
2238 (define_expand "bne"
2240 (if_then_else (eq (reg:SI 18) (const_int 0))
2241 (label_ref (match_operand 0 "" ""))
2244 "from_compare (operands, EQ);")
2246 (define_expand "bgt"
2248 (if_then_else (ne (reg:SI 18) (const_int 0))
2249 (label_ref (match_operand 0 "" ""))
2252 "from_compare (operands, GT);")
2254 (define_expand "blt"
2256 (if_then_else (eq (reg:SI 18) (const_int 0))
2257 (label_ref (match_operand 0 "" ""))
2262 if (GET_MODE (sh_compare_op0) == SFmode)
2264 rtx tmp = sh_compare_op0;
2265 sh_compare_op0 = sh_compare_op1;
2266 sh_compare_op1 = tmp;
2267 emit_insn (gen_bgt (operands[0]));
2270 from_compare (operands, GE);
2273 (define_expand "ble"
2275 (if_then_else (eq (reg:SI 18) (const_int 0))
2276 (label_ref (match_operand 0 "" ""))
2283 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
2285 rtx tmp = sh_compare_op0;
2286 sh_compare_op0 = sh_compare_op1;
2287 sh_compare_op1 = tmp;
2288 emit_insn (gen_bge (operands[0]));
2291 from_compare (operands, GT);
2294 (define_expand "bge"
2296 (if_then_else (ne (reg:SI 18) (const_int 0))
2297 (label_ref (match_operand 0 "" ""))
2304 && GET_MODE_CLASS (GET_MODE (sh_compare_op0)) == MODE_FLOAT)
2306 rtx tmp = sh_compare_op0;
2307 sh_compare_op0 = sh_compare_op1;
2308 sh_compare_op1 = tmp;
2309 emit_insn (gen_ble (operands[0]));
2312 from_compare (operands, GE);
2315 (define_expand "bgtu"
2317 (if_then_else (ne (reg:SI 18) (const_int 0))
2318 (label_ref (match_operand 0 "" ""))
2321 "from_compare (operands, GTU); ")
2323 (define_expand "bltu"
2325 (if_then_else (eq (reg:SI 18) (const_int 0))
2326 (label_ref (match_operand 0 "" ""))
2329 "from_compare (operands, GEU);")
2331 (define_expand "bgeu"
2333 (if_then_else (ne (reg:SI 18) (const_int 0))
2334 (label_ref (match_operand 0 "" ""))
2337 "from_compare (operands, GEU);")
2339 (define_expand "bleu"
2341 (if_then_else (eq (reg:SI 18) (const_int 0))
2342 (label_ref (match_operand 0 "" ""))
2345 "from_compare (operands, GTU);")
2347 ;; ------------------------------------------------------------------------
2348 ;; Jump and linkage insns
2349 ;; ------------------------------------------------------------------------
2353 (label_ref (match_operand 0 "" "")))]
2357 /* The length is 16 if the delay slot is unfilled. */
2358 if (get_attr_length(insn) > 4)
2359 return output_far_jump(insn, operands[0]);
2361 return \"bra %l0%#\";
2363 [(set_attr "type" "jump")
2364 (set_attr "needs_delay_slot" "yes")])
2366 (define_insn "calli"
2367 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
2368 (match_operand 1 "" ""))
2369 (clobber (reg:SI 17))]
2372 [(set_attr "type" "call")
2373 (set_attr "needs_delay_slot" "yes")])
2375 (define_insn "call_valuei"
2376 [(set (match_operand 0 "" "=rf")
2377 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
2378 (match_operand 2 "" "")))
2379 (clobber (reg:SI 17))]
2382 [(set_attr "type" "call")
2383 (set_attr "needs_delay_slot" "yes")])
2385 (define_expand "call"
2386 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
2387 (match_operand 1 "" ""))
2388 (clobber (reg:SI 17))])]
2390 "operands[0] = force_reg (SImode, XEXP (operands[0], 0));")
2392 (define_expand "call_value"
2393 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
2394 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
2395 (match_operand 2 "" "")))
2396 (clobber (reg:SI 17))])]
2398 "operands[1] = force_reg (SImode, XEXP (operands[1], 0));")
2400 (define_insn "indirect_jump"
2402 (match_operand:SI 0 "arith_reg_operand" "r"))]
2405 [(set_attr "needs_delay_slot" "yes")
2406 (set_attr "type" "jump_ind")])
2408 ;; The use of operand 1 / 2 helps us distinguish case table jumps
2409 ;; which can be present in structured code from indirect jumps which can not
2410 ;; be present in structured code. This allows -fprofile-arcs to work.
2412 ;; For SH1 processors.
2413 (define_insn "casesi_jump_1"
2415 (match_operand:SI 0 "register_operand" "r"))
2416 (use (label_ref (match_operand 1 "" "")))]
2419 [(set_attr "needs_delay_slot" "yes")
2420 (set_attr "type" "jump_ind")])
2422 ;; For all later processors.
2423 (define_insn "casesi_jump_2"
2424 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
2425 (match_operand 1 "braf_label_ref_operand" "")))
2426 (use (label_ref (match_operand 2 "" "")))]
2429 [(set_attr "needs_delay_slot" "yes")
2430 (set_attr "type" "jump_ind")])
2432 (define_insn "dummy_jump"
2433 [(set (pc) (const_int 0))]
2436 [(set_attr "length" "0")])
2438 ;; Call subroutine returning any type.
2439 ;; ??? This probably doesn't work.
2441 (define_expand "untyped_call"
2442 [(parallel [(call (match_operand 0 "" "")
2444 (match_operand 1 "" "")
2445 (match_operand 2 "" "")])]
2451 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
2453 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2455 rtx set = XVECEXP (operands[2], 0, i);
2456 emit_move_insn (SET_DEST (set), SET_SRC (set));
2459 /* The optimizer does not know that the call sets the function value
2460 registers we stored in the result block. We avoid problems by
2461 claiming that all hard registers are used and clobbered at this
2463 emit_insn (gen_blockage ());
2468 ;; ------------------------------------------------------------------------
2470 ;; ------------------------------------------------------------------------
2474 (eq:SI (match_operand:SI 0 "arith_reg_operand" "+r") (const_int 1)))
2475 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
2478 [(set_attr "type" "arith")])
2485 ;; Load address of a label. This is only generated by the casesi expand,
2486 ;; and by machine_dependent_reorg (fixing up fp moves).
2487 ;; This must use unspec, because this only works for labels that are
2492 (unspec [(label_ref (match_operand 0 "" ""))] 1))]
2495 [(set_attr "in_delay_slot" "no")
2496 (set_attr "type" "arith")])
2498 ;; case instruction for switch statements.
2500 ;; Operand 0 is index
2501 ;; operand 1 is the minimum bound
2502 ;; operand 2 is the maximum bound - minimum bound + 1
2503 ;; operand 3 is CODE_LABEL for the table;
2504 ;; operand 4 is the CODE_LABEL to go to if index out of range.
2506 (define_expand "casesi"
2507 [(match_operand:SI 0 "arith_reg_operand" "")
2508 (match_operand:SI 1 "arith_reg_operand" "")
2509 (match_operand:SI 2 "arith_reg_operand" "")
2510 (match_operand 3 "" "") (match_operand 4 "" "")]
2514 rtx reg = gen_reg_rtx (SImode);
2515 rtx reg2 = gen_reg_rtx (SImode);
2516 operands[1] = copy_to_mode_reg (SImode, operands[1]);
2517 operands[2] = copy_to_mode_reg (SImode, operands[2]);
2518 /* If optimizing, casesi_worker depends on the mode of the instruction
2519 before label it 'uses' - operands[3]. */
2520 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
2522 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
2525 rtx lab = gen_label_rtx ();
2526 emit_jump_insn (gen_casesi_jump_2 (reg2,
2527 gen_rtx (LABEL_REF, VOIDmode, lab),
2530 /* Put a fake jump after the label, lest some optimization might
2531 delete the barrier and LAB. */
2532 emit_jump_insn (gen_dummy_jump ());
2536 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
2538 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
2539 operands[3], but to lab. We will fix this up in
2540 machine_dependent_reorg. */
2545 (define_expand "casesi_0"
2546 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
2547 (set (match_dup 4) (minus:SI (match_dup 4)
2548 (match_operand:SI 1 "arith_operand" "")))
2550 (gtu:SI (match_dup 4)
2551 (match_operand:SI 2 "arith_reg_operand" "")))
2553 (if_then_else (ne (reg:SI 18)
2555 (label_ref (match_operand 3 "" ""))
2560 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
2561 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
2562 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
2564 (define_insn "casesi_worker_0"
2565 [(set (match_operand:SI 0 "register_operand" "=r,r")
2566 (unspec [(match_operand 1 "register_operand" "0,r")
2567 (label_ref (match_operand 2 "" ""))] 2))
2568 (clobber (match_scratch:SI 3 "=X,1"))
2569 (clobber (match_scratch:SI 4 "=&z,z"))]
2574 [(set (match_operand:SI 0 "register_operand" "")
2575 (unspec [(match_operand 1 "register_operand" "")
2576 (label_ref (match_operand 2 "" ""))] 2))
2577 (clobber (match_scratch:SI 3 ""))
2578 (clobber (match_scratch:SI 4 ""))]
2579 "! TARGET_SH2 && reload_completed"
2580 [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
2581 (parallel [(set (match_dup 0)
2582 (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
2583 (clobber (match_dup 3))])
2584 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI 0)))]
2585 "LABEL_NUSES (operands[2])++;")
2588 [(set (match_operand:SI 0 "register_operand" "")
2589 (unspec [(match_operand 1 "register_operand" "")
2590 (label_ref (match_operand 2 "" ""))] 2))
2591 (clobber (match_scratch:SI 3 ""))
2592 (clobber (match_scratch:SI 4 ""))]
2593 "TARGET_SH2 && reload_completed"
2594 [(set (reg:SI 0) (unspec [(label_ref (match_dup 2))] 1))
2595 (parallel [(set (match_dup 0)
2596 (unspec [(reg:SI 0) (match_dup 1) (label_ref (match_dup 2))] 2))
2597 (clobber (match_dup 3))])]
2598 "LABEL_NUSES (operands[2])++;")
2600 (define_insn "*casesi_worker"
2601 [(set (match_operand:SI 0 "register_operand" "=r,r")
2602 (unspec [(reg:SI 0) (match_operand 1 "register_operand" "0,r")
2603 (label_ref (match_operand 2 "" ""))] 2))
2604 (clobber (match_scratch:SI 3 "=X,1"))]
2608 enum machine_mode mode
2610 ? GET_MODE (PATTERN (prev_real_insn (operands[2])))
2611 : sh_addr_diff_vec_mode;
2615 return \"shll2 %1\;mov.l @(r0,%1),%0\";
2617 return \"add %1,%1\;mov.w @(r0,%1),%0\";
2620 rtx adj = PATTERN (prev_real_insn (operands[2]));
2621 if ((insn_addresses[INSN_UID (XEXP ( XVECEXP (adj, 0, 1), 0))]
2622 - insn_addresses[INSN_UID (XEXP (XVECEXP (adj, 0, 2), 0))])
2624 return \"mov.b @(r0,%1),%0\";
2625 return \"mov.b @(r0,%1),%0\;extu.b %0,%0\";
2631 [(set_attr "length" "4")])
2633 ;; Include ADDR_DIFF_VECS in the shorten_branches pass; we have to
2634 ;; use a negative-length instruction to actually accomplish this.
2635 (define_insn "addr_diff_vec_adjust"
2636 [(unspec_volatile [(label_ref (match_operand 0 "" ""))
2637 (label_ref (match_operand 1 "" ""))
2638 (label_ref (match_operand 2 "" ""))
2639 (match_operand 3 "const_int_operand" "")] 7)]
2643 /* ??? ASM_OUTPUT_ADDR_DIFF_ELT gets passed no context information, so
2644 we must use a kludge with a global variable. */
2645 sh_addr_diff_vec_mode = GET_MODE (PATTERN (insn));
2648 ;; Need a variable length for this to be processed in each shorten_branch pass.
2649 ;; The actual work is done in ADJUST_INSN_LENTH, because length attributes
2650 ;; need to be (a choice of) constants.
2651 ;; We use the calculated length before ADJUST_INSN_LENGTH to
2652 ;; determine if the insn_addresses array contents are valid.
2653 [(set (attr "length")
2654 (if_then_else (eq (pc) (const_int -1))
2655 (const_int 2) (const_int 0)))])
2657 (define_insn "return"
2661 [(set_attr "type" "return")
2662 (set_attr "needs_delay_slot" "yes")])
2664 (define_expand "prologue"
2667 "sh_expand_prologue (); DONE;")
2669 (define_expand "epilogue"
2672 "sh_expand_epilogue ();")
2674 (define_insn "blockage"
2675 [(unspec_volatile [(const_int 0)] 0)]
2678 [(set_attr "length" "0")])
2680 ;; ------------------------------------------------------------------------
2682 ;; ------------------------------------------------------------------------
2685 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
2686 (eq:SI (reg:SI 18) (const_int 1)))]
2689 [(set_attr "type" "arith")])
2691 (define_expand "seq"
2692 [(set (match_operand:SI 0 "arith_reg_operand" "")
2695 "operands[1] = prepare_scc_operands (EQ);")
2697 (define_expand "slt"
2698 [(set (match_operand:SI 0 "arith_reg_operand" "")
2701 "operands[1] = prepare_scc_operands (LT);")
2703 (define_expand "sle"
2704 [(match_operand:SI 0 "arith_reg_operand" "")]
2708 rtx tmp = sh_compare_op0;
2709 sh_compare_op0 = sh_compare_op1;
2710 sh_compare_op1 = tmp;
2711 emit_insn (gen_sge (operands[0]));
2715 (define_expand "sgt"
2716 [(set (match_operand:SI 0 "arith_reg_operand" "")
2719 "operands[1] = prepare_scc_operands (GT);")
2721 (define_expand "sge"
2722 [(set (match_operand:SI 0 "arith_reg_operand" "")
2727 if (GET_MODE (sh_compare_op0) == SFmode)
2731 rtx t_reg = gen_rtx (REG, SImode, T_REG);
2732 rtx lab = gen_label_rtx ();
2733 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
2734 gen_rtx (EQ, SImode, sh_compare_op0,
2736 emit_jump_insn (gen_branch_true (lab));
2737 emit_insn (gen_rtx (SET, VOIDmode, t_reg,
2738 gen_rtx (GT, SImode, sh_compare_op0,
2741 emit_insn (gen_movt (operands[0]));
2744 emit_insn (gen_movnegt (operands[0], prepare_scc_operands (LT)));
2747 operands[1] = prepare_scc_operands (GE);
2750 (define_expand "sgtu"
2751 [(set (match_operand:SI 0 "arith_reg_operand" "")
2754 "operands[1] = prepare_scc_operands (GTU);")
2756 (define_expand "sltu"
2757 [(set (match_operand:SI 0 "arith_reg_operand" "")
2760 "operands[1] = prepare_scc_operands (LTU);")
2762 (define_expand "sleu"
2763 [(set (match_operand:SI 0 "arith_reg_operand" "")
2766 "operands[1] = prepare_scc_operands (LEU);")
2768 (define_expand "sgeu"
2769 [(set (match_operand:SI 0 "arith_reg_operand" "")
2772 "operands[1] = prepare_scc_operands (GEU);")
2774 ;; sne moves the complement of the T reg to DEST like this:
2778 ;; This is better than xoring compare result with 1 because it does
2779 ;; not require r0 and further, the -1 may be CSE-ed or lifted out of a
2782 (define_expand "sne"
2783 [(set (match_dup 2) (const_int -1))
2784 (parallel [(set (match_operand:SI 0 "arith_reg_operand" "")
2785 (neg:SI (plus:SI (match_dup 1)
2788 (ne:SI (ior:SI (match_dup 1) (match_dup 2))
2793 operands[1] = prepare_scc_operands (EQ);
2794 operands[2] = gen_reg_rtx (SImode);
2797 ;; Use the same trick for FP sle / sge
2798 (define_expand "movnegt"
2799 [(set (match_dup 2) (const_int -1))
2800 (parallel [(set (match_operand 0 "" "")
2801 (neg:SI (plus:SI (match_dup 1)
2804 (ne:SI (ior:SI (match_operand 1 "" "") (match_dup 2))
2807 "operands[2] = gen_reg_rtx (SImode);")
2809 ;; Recognize mov #-1/negc/neg sequence, and change it to movt/add #-1.
2810 ;; This prevents a regression that occured when we switched from xor to
2814 [(set (match_operand:SI 0 "arith_reg_operand" "")
2815 (plus:SI (reg:SI 18)
2818 [(set (match_dup 0) (eq:SI (reg:SI 18) (const_int 1)))
2819 (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))]
2822 ;; -------------------------------------------------------------------------
2823 ;; Instructions to cope with inline literal tables
2824 ;; -------------------------------------------------------------------------
2826 ; 2 byte integer in line
2828 (define_insn "consttable_2"
2829 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 2)]
2833 assemble_integer (operands[0], 2, 1);
2836 [(set_attr "length" "2")
2837 (set_attr "in_delay_slot" "no")])
2839 ; 4 byte integer in line
2841 (define_insn "consttable_4"
2842 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 4)]
2846 assemble_integer (operands[0], 4, 1);
2849 [(set_attr "length" "4")
2850 (set_attr "in_delay_slot" "no")])
2852 ; 8 byte integer in line
2854 (define_insn "consttable_8"
2855 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")] 6)]
2859 assemble_integer (operands[0], 8, 1);
2862 [(set_attr "length" "8")
2863 (set_attr "in_delay_slot" "no")])
2865 ; 4 byte floating point
2867 (define_insn "consttable_sf"
2868 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")] 4)]
2872 union real_extract u;
2873 bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
2874 assemble_real (u.d, SFmode);
2877 [(set_attr "length" "4")
2878 (set_attr "in_delay_slot" "no")])
2880 ; 8 byte floating point
2882 (define_insn "consttable_df"
2883 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")] 6)]
2887 union real_extract u;
2888 bcopy ((char *) &CONST_DOUBLE_LOW (operands[0]), (char *) &u, sizeof u);
2889 assemble_real (u.d, DFmode);
2892 [(set_attr "length" "8")
2893 (set_attr "in_delay_slot" "no")])
2895 ;; Alignment is needed for some constant tables; it may also be added for
2896 ;; Instructions at the start of loops, or after unconditional branches.
2897 ;; ??? We would get more accurate lengths if we did instruction
2898 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
2899 ;; here is too conservative.
2901 ; align to a two byte boundary
2903 (define_insn "align_2"
2904 [(unspec_volatile [(const_int 1)] 1)]
2907 [(set_attr "length" "0")
2908 (set_attr "in_delay_slot" "no")])
2910 ; align to a four byte boundary
2911 ;; align_4 and align_log are instructions for the starts of loops, or
2912 ;; after unconditional branches, which may take up extra room.
2914 (define_expand "align_4"
2915 [(unspec_volatile [(const_int 2)] 1)]
2919 ; align to a cache line boundary
2921 (define_insn "align_log"
2922 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] 1)]
2925 ;; Need a variable length for this to be processed in each shorten_branch pass.
2926 ;; The actual work is done in ADJUST_INSN_LENTH, because length attributes
2927 ;; need to be (a choice of) constants.
2928 [(set (attr "length")
2929 (if_then_else (ne (pc) (pc)) (const_int 2) (const_int 0)))
2930 (set_attr "in_delay_slot" "no")])
2932 ; emitted at the end of the literal table, used to emit the
2933 ; 32bit branch labels if needed.
2935 (define_insn "consttable_end"
2936 [(unspec_volatile [(const_int 0)] 11)]
2938 "* return output_jump_label_table ();"
2939 [(set_attr "in_delay_slot" "no")])
2941 ;; -------------------------------------------------------------------------
2943 ;; -------------------------------------------------------------------------
2945 ;; String/block move insn.
2947 (define_expand "movstrsi"
2948 [(parallel [(set (mem:BLK (match_operand:BLK 0 "" ""))
2949 (mem:BLK (match_operand:BLK 1 "" "")))
2950 (use (match_operand:SI 2 "nonmemory_operand" ""))
2951 (use (match_operand:SI 3 "immediate_operand" ""))
2952 (clobber (reg:SI 17))
2953 (clobber (reg:SI 4))
2954 (clobber (reg:SI 5))
2955 (clobber (reg:SI 0))])]
2959 if(expand_block_move (operands))
2964 (define_insn "block_move_real"
2965 [(parallel [(set (mem:BLK (reg:SI 4))
2966 (mem:BLK (reg:SI 5)))
2967 (use (match_operand:SI 0 "arith_reg_operand" "r"))
2968 (clobber (reg:SI 17))
2969 (clobber (reg:SI 0))])]
2972 [(set_attr "type" "sfunc")
2973 (set_attr "needs_delay_slot" "yes")])
2975 (define_insn "block_lump_real"
2976 [(parallel [(set (mem:BLK (reg:SI 4))
2977 (mem:BLK (reg:SI 5)))
2978 (use (match_operand:SI 0 "arith_reg_operand" "r"))
2980 (clobber (reg:SI 17))
2981 (clobber (reg:SI 4))
2982 (clobber (reg:SI 5))
2983 (clobber (reg:SI 6))
2984 (clobber (reg:SI 0))])]
2987 [(set_attr "type" "sfunc")
2988 (set_attr "needs_delay_slot" "yes")])
2990 ;; -------------------------------------------------------------------------
2991 ;; Floating point instructions.
2992 ;; -------------------------------------------------------------------------
2994 ;; ??? All patterns should have a type attribute.
2996 (define_insn "addsf3"
2997 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
2998 (plus:SF (match_operand:SF 1 "arith_reg_operand" "%0")
2999 (match_operand:SF 2 "arith_reg_operand" "f")))]
3002 [(set_attr "type" "fp")])
3004 (define_insn "subsf3"
3005 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3006 (minus:SF (match_operand:SF 1 "arith_reg_operand" "0")
3007 (match_operand:SF 2 "arith_reg_operand" "f")))]
3010 [(set_attr "type" "fp")])
3012 (define_insn "mulsf3"
3013 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3014 (mult:SF (match_operand:SF 1 "arith_reg_operand" "%0")
3015 (match_operand:SF 2 "arith_reg_operand" "f")))]
3018 [(set_attr "type" "fp")])
3020 (define_insn "*macsf3"
3021 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3022 (plus:SF (mult:SF (match_operand:SF 1 "arith_reg_operand" "%w")
3023 (match_operand:SF 2 "arith_reg_operand" "f"))
3024 (match_operand:SF 3 "arith_reg_operand" "0")))]
3027 [(set_attr "type" "fp")])
3029 (define_insn "divsf3"
3030 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3031 (div:SF (match_operand:SF 1 "arith_reg_operand" "0")
3032 (match_operand:SF 2 "arith_reg_operand" "f")))]
3035 [(set_attr "type" "fdiv")])
3037 (define_expand "floatsisf2"
3039 (match_operand:SI 1 "arith_reg_operand" ""))
3040 (set (match_operand:SF 0 "arith_reg_operand" "")
3041 (float:SF (reg:SI 22)))]
3045 (define_insn "*floatsisf2_ie"
3046 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3047 (float:SF (reg:SI 22)))]
3050 [(set_attr "type" "fp")])
3052 (define_expand "fix_truncsfsi2"
3054 (fix:SI (match_operand:SF 1 "arith_reg_operand" "f")))
3055 (set (match_operand:SI 0 "arith_reg_operand" "=r")
3060 (define_insn "*fixsfsi"
3062 (fix:SI (match_operand:SF 0 "arith_reg_operand" "f")))]
3065 [(set_attr "type" "fp")])
3067 (define_insn "cmpgtsf_t"
3068 [(set (reg:SI 18) (gt:SI (match_operand:SF 0 "arith_reg_operand" "f")
3069 (match_operand:SF 1 "arith_reg_operand" "f")))]
3072 [(set_attr "type" "fp")])
3074 (define_insn "cmpeqsf_t"
3075 [(set (reg:SI 18) (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
3076 (match_operand:SF 1 "arith_reg_operand" "f")))]
3079 [(set_attr "type" "fp")])
3081 (define_insn "ieee_ccmpeqsf_t"
3082 [(set (reg:SI 18) (ior:SI (reg:SI 18)
3083 (eq:SI (match_operand:SF 0 "arith_reg_operand" "f")
3084 (match_operand:SF 1 "arith_reg_operand" "f"))))]
3085 "TARGET_SH3E && TARGET_IEEE"
3086 "* return output_ieee_ccmpeq (insn, operands);"
3087 [(set_attr "length" "4")])
3090 (define_expand "cmpsf"
3091 [(set (reg:SI 18) (compare (match_operand:SF 0 "arith_operand" "")
3092 (match_operand:SF 1 "arith_operand" "")))]
3096 sh_compare_op0 = operands[0];
3097 sh_compare_op1 = operands[1];
3101 (define_insn "negsf2"
3102 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3103 (neg:SF (match_operand:SF 1 "arith_reg_operand" "0")))]
3106 [(set_attr "type" "fp")])
3108 (define_insn "sqrtsf2"
3109 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3110 (sqrt:DF (match_operand:SF 1 "arith_reg_operand" "0")))]
3113 [(set_attr "type" "fdiv")])
3115 (define_insn "abssf2"
3116 [(set (match_operand:SF 0 "arith_reg_operand" "=f")
3117 (abs:SF (match_operand:SF 1 "arith_reg_operand" "0")))]
3120 [(set_attr "type" "fp")])
3122 ;; Bit field extract patterns. These give better code for packed bitfields,
3123 ;; because they allow auto-increment addresses to be generated.
3125 (define_expand "insv"
3126 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
3127 (match_operand:SI 1 "immediate_operand" "")
3128 (match_operand:SI 2 "immediate_operand" ""))
3129 (match_operand:SI 3 "general_operand" ""))]
3130 "! TARGET_LITTLE_ENDIAN"
3133 rtx addr_target, orig_address, shift_reg;
3136 /* ??? expmed doesn't care for non-register predicates. */
3137 if (! memory_operand (operands[0], VOIDmode)
3138 || ! immediate_operand (operands[1], VOIDmode)
3139 || ! immediate_operand (operands[2], VOIDmode)
3140 || ! general_operand (operands[3], VOIDmode))
3142 /* If this isn't a 16 / 24 / 32 bit field, or if
3143 it doesn't start on a byte boundary, then fail. */
3144 size = INTVAL (operands[1]);
3145 if (size < 16 || size > 32 || size % 8 != 0
3146 || (INTVAL (operands[2]) % 8) != 0)
3150 orig_address = XEXP (operands[0], 0);
3151 addr_target = gen_reg_rtx (SImode);
3152 shift_reg = gen_reg_rtx (SImode);
3153 emit_insn (gen_movsi (shift_reg, operands[3]));
3154 emit_insn (gen_addsi3 (addr_target, orig_address, GEN_INT (size - 1)));
3156 operands[0] = change_address (operands[0], QImode, addr_target);
3157 emit_insn (gen_movqi (operands[0], gen_rtx (SUBREG, QImode, shift_reg, 0)));
3161 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
3162 emit_insn (gen_addsi3 (addr_target, addr_target, GEN_INT (-1)));
3163 emit_insn (gen_movqi (operands[0],
3164 gen_rtx (SUBREG, QImode, shift_reg, 0)));
3170 ;; -------------------------------------------------------------------------
3172 ;; -------------------------------------------------------------------------
3174 ;; This matches cases where a stack pointer increment at the start of the
3175 ;; epilogue combines with a stack slot read loading the return value.
3178 [(set (match_operand:SI 0 "arith_reg_operand" "")
3179 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
3180 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
3181 "REGNO (operands[1]) != REGNO (operands[0])"
3184 ;; See the comment on the dt combiner pattern above.
3187 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
3188 (plus:SI (match_dup 0)
3191 (eq:SI (match_dup 0)
3196 ;; These convert sequences such as `mov #k,r0; add r15,r0; mov.l @r0,rn'
3197 ;; to `mov #k,r0; mov.l @(r0,r15),rn'. These sequences are generated by
3198 ;; reload when the constant is too large for a reg+offset address.
3200 ;; ??? We would get much better code if this was done in reload. This would
3201 ;; require modifying find_reloads_address to recognize that if the constant
3202 ;; is out-of-range for an immediate add, then we get better code by reloading
3203 ;; the constant into a register than by reloading the sum into a register,
3204 ;; since the former is one instruction shorter if the address does not need
3205 ;; to be offsettable. Unfortunately this does not work, because there is
3206 ;; only one register, r0, that can be used as an index register. This register
3207 ;; is also the function return value register. So, if we try to force reload
3208 ;; to use double-reg addresses, then we end up with some instructions that
3209 ;; need to use r0 twice. The only way to fix this is to change the calling
3210 ;; convention so that r0 is not used to return values.
3213 [(set (match_operand:SI 0 "register_operand" "=r")
3214 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3215 (set (mem:SI (match_dup 0))
3216 (match_operand:SI 2 "general_movsrc_operand" ""))]
3217 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
3218 "mov.l %2,@(%0,%1)")
3221 [(set (match_operand:SI 0 "register_operand" "=r")
3222 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3223 (set (match_operand:SI 2 "general_movdst_operand" "")
3224 (mem:SI (match_dup 0)))]
3225 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
3226 "mov.l @(%0,%1),%2")
3229 [(set (match_operand:SI 0 "register_operand" "=r")
3230 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3231 (set (mem:HI (match_dup 0))
3232 (match_operand:HI 2 "general_movsrc_operand" ""))]
3233 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
3234 "mov.w %2,@(%0,%1)")
3237 [(set (match_operand:SI 0 "register_operand" "=r")
3238 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3239 (set (match_operand:HI 2 "general_movdst_operand" "")
3240 (mem:HI (match_dup 0)))]
3241 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
3242 "mov.w @(%0,%1),%2")
3245 [(set (match_operand:SI 0 "register_operand" "=r")
3246 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3247 (set (mem:QI (match_dup 0))
3248 (match_operand:QI 2 "general_movsrc_operand" ""))]
3249 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
3250 "mov.b %2,@(%0,%1)")
3253 [(set (match_operand:SI 0 "register_operand" "=r")
3254 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3255 (set (match_operand:QI 2 "general_movdst_operand" "")
3256 (mem:QI (match_dup 0)))]
3257 "REGNO (operands[0]) == 0 && reg_unused_after (operands[0], insn)"
3258 "mov.b @(%0,%1),%2")
3261 [(set (match_operand:SI 0 "register_operand" "=r")
3262 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3263 (set (mem:SF (match_dup 0))
3264 (match_operand:SF 2 "general_movsrc_operand" ""))]
3265 "REGNO (operands[0]) == 0
3266 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
3267 || (GET_CODE (operands[2]) == SUBREG
3268 && REGNO (SUBREG_REG (operands[2])) < 16))
3269 && reg_unused_after (operands[0], insn)"
3270 "mov.l %2,@(%0,%1)")
3273 [(set (match_operand:SI 0 "register_operand" "=r")
3274 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3275 (set (match_operand:SF 2 "general_movdst_operand" "")
3277 (mem:SF (match_dup 0)))]
3278 "REGNO (operands[0]) == 0
3279 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) < 16)
3280 || (GET_CODE (operands[2]) == SUBREG
3281 && REGNO (SUBREG_REG (operands[2])) < 16))
3282 && reg_unused_after (operands[0], insn)"
3283 "mov.l @(%0,%1),%2")
3286 [(set (match_operand:SI 0 "register_operand" "=r")
3287 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3288 (set (mem:SF (match_dup 0))
3289 (match_operand:SF 2 "general_movsrc_operand" ""))]
3290 "REGNO (operands[0]) == 0
3291 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
3292 || (GET_CODE (operands[2]) == SUBREG
3293 && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
3294 && reg_unused_after (operands[0], insn)"
3295 "fmov{.s|} %2,@(%0,%1)")
3298 [(set (match_operand:SI 0 "register_operand" "=r")
3299 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
3300 (set (match_operand:SF 2 "general_movdst_operand" "")
3302 (mem:SF (match_dup 0)))]
3303 "REGNO (operands[0]) == 0
3304 && ((GET_CODE (operands[2]) == REG && REGNO (operands[2]) >= FIRST_FP_REG)
3305 || (GET_CODE (operands[2]) == SUBREG
3306 && REGNO (SUBREG_REG (operands[2])) >= FIRST_FP_REG))
3307 && reg_unused_after (operands[0], insn)"
3308 "fmov{.s|} @(%0,%1),%2")
3310 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF). */
3311 (define_insn "sp_switch_1"
3318 xoperands[0] = sp_switch;
3319 output_asm_insn (\"mov.l r0,@-r15\;mov.l %0,r0\", xoperands);
3320 output_asm_insn (\"mov.l @r0,r0\;mov.l r15,@-r0\", xoperands);
3321 return \"mov r0,r15\";
3323 [(set_attr "length" "10")])
3325 ;; Switch back to the original stack for interrupt funtions with the
3326 ;; sp_switch attribute. */
3327 (define_insn "sp_switch_2"
3330 "mov.l @r15+,r15\;mov.l @r15+,r0"
3331 [(set_attr "length" "4")])