1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
28 #include "stringpool.h"
29 #include "stor-layout.h"
34 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "insn-codes.h"
37 #include "conditions.h"
39 #include "insn-attr.h"
46 #include "diagnostic-core.h"
51 #include "target-def.h"
52 #include "common/common-target.h"
53 #include "hash-table.h"
55 #include "basic-block.h"
56 #include "tree-ssa-alias.h"
57 #include "internal-fn.h"
58 #include "gimple-fold.h"
60 #include "gimple-expr.h"
64 #include "langhooks.h"
69 #include "tree-pass.h"
76 struct processor_costs
{
80 /* Integer signed load */
83 /* Integer zeroed load */
89 /* fmov, fneg, fabs */
93 const int float_plusminus
;
99 const int float_cmove
;
105 const int float_div_sf
;
108 const int float_div_df
;
111 const int float_sqrt_sf
;
114 const int float_sqrt_df
;
122 /* integer multiply cost for each bit set past the most
123 significant 3, so the formula for multiply cost becomes:
126 highest_bit = highest_clear_bit(rs1);
128 highest_bit = highest_set_bit(rs1);
131 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
133 A value of zero indicates that the multiply costs is fixed,
135 const int int_mul_bit_factor
;
146 /* penalty for shifts, due to scheduling rules etc. */
147 const int shift_penalty
;
151 struct processor_costs cypress_costs
= {
152 COSTS_N_INSNS (2), /* int load */
153 COSTS_N_INSNS (2), /* int signed load */
154 COSTS_N_INSNS (2), /* int zeroed load */
155 COSTS_N_INSNS (2), /* float load */
156 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
157 COSTS_N_INSNS (5), /* fadd, fsub */
158 COSTS_N_INSNS (1), /* fcmp */
159 COSTS_N_INSNS (1), /* fmov, fmovr */
160 COSTS_N_INSNS (7), /* fmul */
161 COSTS_N_INSNS (37), /* fdivs */
162 COSTS_N_INSNS (37), /* fdivd */
163 COSTS_N_INSNS (63), /* fsqrts */
164 COSTS_N_INSNS (63), /* fsqrtd */
165 COSTS_N_INSNS (1), /* imul */
166 COSTS_N_INSNS (1), /* imulX */
167 0, /* imul bit factor */
168 COSTS_N_INSNS (1), /* idiv */
169 COSTS_N_INSNS (1), /* idivX */
170 COSTS_N_INSNS (1), /* movcc/movr */
171 0, /* shift penalty */
175 struct processor_costs supersparc_costs
= {
176 COSTS_N_INSNS (1), /* int load */
177 COSTS_N_INSNS (1), /* int signed load */
178 COSTS_N_INSNS (1), /* int zeroed load */
179 COSTS_N_INSNS (0), /* float load */
180 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
181 COSTS_N_INSNS (3), /* fadd, fsub */
182 COSTS_N_INSNS (3), /* fcmp */
183 COSTS_N_INSNS (1), /* fmov, fmovr */
184 COSTS_N_INSNS (3), /* fmul */
185 COSTS_N_INSNS (6), /* fdivs */
186 COSTS_N_INSNS (9), /* fdivd */
187 COSTS_N_INSNS (12), /* fsqrts */
188 COSTS_N_INSNS (12), /* fsqrtd */
189 COSTS_N_INSNS (4), /* imul */
190 COSTS_N_INSNS (4), /* imulX */
191 0, /* imul bit factor */
192 COSTS_N_INSNS (4), /* idiv */
193 COSTS_N_INSNS (4), /* idivX */
194 COSTS_N_INSNS (1), /* movcc/movr */
195 1, /* shift penalty */
199 struct processor_costs hypersparc_costs
= {
200 COSTS_N_INSNS (1), /* int load */
201 COSTS_N_INSNS (1), /* int signed load */
202 COSTS_N_INSNS (1), /* int zeroed load */
203 COSTS_N_INSNS (1), /* float load */
204 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
205 COSTS_N_INSNS (1), /* fadd, fsub */
206 COSTS_N_INSNS (1), /* fcmp */
207 COSTS_N_INSNS (1), /* fmov, fmovr */
208 COSTS_N_INSNS (1), /* fmul */
209 COSTS_N_INSNS (8), /* fdivs */
210 COSTS_N_INSNS (12), /* fdivd */
211 COSTS_N_INSNS (17), /* fsqrts */
212 COSTS_N_INSNS (17), /* fsqrtd */
213 COSTS_N_INSNS (17), /* imul */
214 COSTS_N_INSNS (17), /* imulX */
215 0, /* imul bit factor */
216 COSTS_N_INSNS (17), /* idiv */
217 COSTS_N_INSNS (17), /* idivX */
218 COSTS_N_INSNS (1), /* movcc/movr */
219 0, /* shift penalty */
223 struct processor_costs leon_costs
= {
224 COSTS_N_INSNS (1), /* int load */
225 COSTS_N_INSNS (1), /* int signed load */
226 COSTS_N_INSNS (1), /* int zeroed load */
227 COSTS_N_INSNS (1), /* float load */
228 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
229 COSTS_N_INSNS (1), /* fadd, fsub */
230 COSTS_N_INSNS (1), /* fcmp */
231 COSTS_N_INSNS (1), /* fmov, fmovr */
232 COSTS_N_INSNS (1), /* fmul */
233 COSTS_N_INSNS (15), /* fdivs */
234 COSTS_N_INSNS (15), /* fdivd */
235 COSTS_N_INSNS (23), /* fsqrts */
236 COSTS_N_INSNS (23), /* fsqrtd */
237 COSTS_N_INSNS (5), /* imul */
238 COSTS_N_INSNS (5), /* imulX */
239 0, /* imul bit factor */
240 COSTS_N_INSNS (5), /* idiv */
241 COSTS_N_INSNS (5), /* idivX */
242 COSTS_N_INSNS (1), /* movcc/movr */
243 0, /* shift penalty */
247 struct processor_costs leon3_costs
= {
248 COSTS_N_INSNS (1), /* int load */
249 COSTS_N_INSNS (1), /* int signed load */
250 COSTS_N_INSNS (1), /* int zeroed load */
251 COSTS_N_INSNS (1), /* float load */
252 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
253 COSTS_N_INSNS (1), /* fadd, fsub */
254 COSTS_N_INSNS (1), /* fcmp */
255 COSTS_N_INSNS (1), /* fmov, fmovr */
256 COSTS_N_INSNS (1), /* fmul */
257 COSTS_N_INSNS (14), /* fdivs */
258 COSTS_N_INSNS (15), /* fdivd */
259 COSTS_N_INSNS (22), /* fsqrts */
260 COSTS_N_INSNS (23), /* fsqrtd */
261 COSTS_N_INSNS (5), /* imul */
262 COSTS_N_INSNS (5), /* imulX */
263 0, /* imul bit factor */
264 COSTS_N_INSNS (35), /* idiv */
265 COSTS_N_INSNS (35), /* idivX */
266 COSTS_N_INSNS (1), /* movcc/movr */
267 0, /* shift penalty */
271 struct processor_costs sparclet_costs
= {
272 COSTS_N_INSNS (3), /* int load */
273 COSTS_N_INSNS (3), /* int signed load */
274 COSTS_N_INSNS (1), /* int zeroed load */
275 COSTS_N_INSNS (1), /* float load */
276 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
277 COSTS_N_INSNS (1), /* fadd, fsub */
278 COSTS_N_INSNS (1), /* fcmp */
279 COSTS_N_INSNS (1), /* fmov, fmovr */
280 COSTS_N_INSNS (1), /* fmul */
281 COSTS_N_INSNS (1), /* fdivs */
282 COSTS_N_INSNS (1), /* fdivd */
283 COSTS_N_INSNS (1), /* fsqrts */
284 COSTS_N_INSNS (1), /* fsqrtd */
285 COSTS_N_INSNS (5), /* imul */
286 COSTS_N_INSNS (5), /* imulX */
287 0, /* imul bit factor */
288 COSTS_N_INSNS (5), /* idiv */
289 COSTS_N_INSNS (5), /* idivX */
290 COSTS_N_INSNS (1), /* movcc/movr */
291 0, /* shift penalty */
295 struct processor_costs ultrasparc_costs
= {
296 COSTS_N_INSNS (2), /* int load */
297 COSTS_N_INSNS (3), /* int signed load */
298 COSTS_N_INSNS (2), /* int zeroed load */
299 COSTS_N_INSNS (2), /* float load */
300 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
301 COSTS_N_INSNS (4), /* fadd, fsub */
302 COSTS_N_INSNS (1), /* fcmp */
303 COSTS_N_INSNS (2), /* fmov, fmovr */
304 COSTS_N_INSNS (4), /* fmul */
305 COSTS_N_INSNS (13), /* fdivs */
306 COSTS_N_INSNS (23), /* fdivd */
307 COSTS_N_INSNS (13), /* fsqrts */
308 COSTS_N_INSNS (23), /* fsqrtd */
309 COSTS_N_INSNS (4), /* imul */
310 COSTS_N_INSNS (4), /* imulX */
311 2, /* imul bit factor */
312 COSTS_N_INSNS (37), /* idiv */
313 COSTS_N_INSNS (68), /* idivX */
314 COSTS_N_INSNS (2), /* movcc/movr */
315 2, /* shift penalty */
319 struct processor_costs ultrasparc3_costs
= {
320 COSTS_N_INSNS (2), /* int load */
321 COSTS_N_INSNS (3), /* int signed load */
322 COSTS_N_INSNS (3), /* int zeroed load */
323 COSTS_N_INSNS (2), /* float load */
324 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
325 COSTS_N_INSNS (4), /* fadd, fsub */
326 COSTS_N_INSNS (5), /* fcmp */
327 COSTS_N_INSNS (3), /* fmov, fmovr */
328 COSTS_N_INSNS (4), /* fmul */
329 COSTS_N_INSNS (17), /* fdivs */
330 COSTS_N_INSNS (20), /* fdivd */
331 COSTS_N_INSNS (20), /* fsqrts */
332 COSTS_N_INSNS (29), /* fsqrtd */
333 COSTS_N_INSNS (6), /* imul */
334 COSTS_N_INSNS (6), /* imulX */
335 0, /* imul bit factor */
336 COSTS_N_INSNS (40), /* idiv */
337 COSTS_N_INSNS (71), /* idivX */
338 COSTS_N_INSNS (2), /* movcc/movr */
339 0, /* shift penalty */
343 struct processor_costs niagara_costs
= {
344 COSTS_N_INSNS (3), /* int load */
345 COSTS_N_INSNS (3), /* int signed load */
346 COSTS_N_INSNS (3), /* int zeroed load */
347 COSTS_N_INSNS (9), /* float load */
348 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
349 COSTS_N_INSNS (8), /* fadd, fsub */
350 COSTS_N_INSNS (26), /* fcmp */
351 COSTS_N_INSNS (8), /* fmov, fmovr */
352 COSTS_N_INSNS (29), /* fmul */
353 COSTS_N_INSNS (54), /* fdivs */
354 COSTS_N_INSNS (83), /* fdivd */
355 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
356 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
357 COSTS_N_INSNS (11), /* imul */
358 COSTS_N_INSNS (11), /* imulX */
359 0, /* imul bit factor */
360 COSTS_N_INSNS (72), /* idiv */
361 COSTS_N_INSNS (72), /* idivX */
362 COSTS_N_INSNS (1), /* movcc/movr */
363 0, /* shift penalty */
367 struct processor_costs niagara2_costs
= {
368 COSTS_N_INSNS (3), /* int load */
369 COSTS_N_INSNS (3), /* int signed load */
370 COSTS_N_INSNS (3), /* int zeroed load */
371 COSTS_N_INSNS (3), /* float load */
372 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
373 COSTS_N_INSNS (6), /* fadd, fsub */
374 COSTS_N_INSNS (6), /* fcmp */
375 COSTS_N_INSNS (6), /* fmov, fmovr */
376 COSTS_N_INSNS (6), /* fmul */
377 COSTS_N_INSNS (19), /* fdivs */
378 COSTS_N_INSNS (33), /* fdivd */
379 COSTS_N_INSNS (19), /* fsqrts */
380 COSTS_N_INSNS (33), /* fsqrtd */
381 COSTS_N_INSNS (5), /* imul */
382 COSTS_N_INSNS (5), /* imulX */
383 0, /* imul bit factor */
384 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
385 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
386 COSTS_N_INSNS (1), /* movcc/movr */
387 0, /* shift penalty */
391 struct processor_costs niagara3_costs
= {
392 COSTS_N_INSNS (3), /* int load */
393 COSTS_N_INSNS (3), /* int signed load */
394 COSTS_N_INSNS (3), /* int zeroed load */
395 COSTS_N_INSNS (3), /* float load */
396 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
397 COSTS_N_INSNS (9), /* fadd, fsub */
398 COSTS_N_INSNS (9), /* fcmp */
399 COSTS_N_INSNS (9), /* fmov, fmovr */
400 COSTS_N_INSNS (9), /* fmul */
401 COSTS_N_INSNS (23), /* fdivs */
402 COSTS_N_INSNS (37), /* fdivd */
403 COSTS_N_INSNS (23), /* fsqrts */
404 COSTS_N_INSNS (37), /* fsqrtd */
405 COSTS_N_INSNS (9), /* imul */
406 COSTS_N_INSNS (9), /* imulX */
407 0, /* imul bit factor */
408 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
409 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
410 COSTS_N_INSNS (1), /* movcc/movr */
411 0, /* shift penalty */
415 struct processor_costs niagara4_costs
= {
416 COSTS_N_INSNS (5), /* int load */
417 COSTS_N_INSNS (5), /* int signed load */
418 COSTS_N_INSNS (5), /* int zeroed load */
419 COSTS_N_INSNS (5), /* float load */
420 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
421 COSTS_N_INSNS (11), /* fadd, fsub */
422 COSTS_N_INSNS (11), /* fcmp */
423 COSTS_N_INSNS (11), /* fmov, fmovr */
424 COSTS_N_INSNS (11), /* fmul */
425 COSTS_N_INSNS (24), /* fdivs */
426 COSTS_N_INSNS (37), /* fdivd */
427 COSTS_N_INSNS (24), /* fsqrts */
428 COSTS_N_INSNS (37), /* fsqrtd */
429 COSTS_N_INSNS (12), /* imul */
430 COSTS_N_INSNS (12), /* imulX */
431 0, /* imul bit factor */
432 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
433 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
434 COSTS_N_INSNS (1), /* movcc/movr */
435 0, /* shift penalty */
438 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
440 #ifdef HAVE_AS_RELAX_OPTION
441 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
442 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
443 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
444 somebody does not branch between the sethi and jmp. */
445 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
447 #define LEAF_SIBCALL_SLOT_RESERVED_P \
448 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
451 /* Vector to say how input registers are mapped to output registers.
452 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
453 eliminate it. You must use -fomit-frame-pointer to get that. */
454 char leaf_reg_remap
[] =
455 { 0, 1, 2, 3, 4, 5, 6, 7,
456 -1, -1, -1, -1, -1, -1, 14, -1,
457 -1, -1, -1, -1, -1, -1, -1, -1,
458 8, 9, 10, 11, 12, 13, -1, 15,
460 32, 33, 34, 35, 36, 37, 38, 39,
461 40, 41, 42, 43, 44, 45, 46, 47,
462 48, 49, 50, 51, 52, 53, 54, 55,
463 56, 57, 58, 59, 60, 61, 62, 63,
464 64, 65, 66, 67, 68, 69, 70, 71,
465 72, 73, 74, 75, 76, 77, 78, 79,
466 80, 81, 82, 83, 84, 85, 86, 87,
467 88, 89, 90, 91, 92, 93, 94, 95,
468 96, 97, 98, 99, 100, 101, 102};
470 /* Vector, indexed by hard register number, which contains 1
471 for a register that is allowable in a candidate for leaf
472 function treatment. */
473 char sparc_leaf_regs
[] =
474 { 1, 1, 1, 1, 1, 1, 1, 1,
475 0, 0, 0, 0, 0, 0, 1, 0,
476 0, 0, 0, 0, 0, 0, 0, 0,
477 1, 1, 1, 1, 1, 1, 0, 1,
478 1, 1, 1, 1, 1, 1, 1, 1,
479 1, 1, 1, 1, 1, 1, 1, 1,
480 1, 1, 1, 1, 1, 1, 1, 1,
481 1, 1, 1, 1, 1, 1, 1, 1,
482 1, 1, 1, 1, 1, 1, 1, 1,
483 1, 1, 1, 1, 1, 1, 1, 1,
484 1, 1, 1, 1, 1, 1, 1, 1,
485 1, 1, 1, 1, 1, 1, 1, 1,
486 1, 1, 1, 1, 1, 1, 1};
488 struct GTY(()) machine_function
490 /* Size of the frame of the function. */
491 HOST_WIDE_INT frame_size
;
493 /* Size of the frame of the function minus the register window save area
494 and the outgoing argument area. */
495 HOST_WIDE_INT apparent_frame_size
;
497 /* Register we pretend the frame pointer is allocated to. Normally, this
498 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
499 record "offset" separately as it may be too big for (reg + disp). */
501 HOST_WIDE_INT frame_base_offset
;
503 /* Some local-dynamic TLS symbol name. */
504 const char *some_ld_name
;
506 /* Number of global or FP registers to be saved (as 4-byte quantities). */
507 int n_global_fp_regs
;
509 /* True if the current function is leaf and uses only leaf regs,
510 so that the SPARC leaf function optimization can be applied.
511 Private version of crtl->uses_only_leaf_regs, see
512 sparc_expand_prologue for the rationale. */
515 /* True if the prologue saves local or in registers. */
516 bool save_local_in_regs_p
;
518 /* True if the data calculated by sparc_expand_prologue are valid. */
519 bool prologue_data_valid_p
;
522 #define sparc_frame_size cfun->machine->frame_size
523 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
524 #define sparc_frame_base_reg cfun->machine->frame_base_reg
525 #define sparc_frame_base_offset cfun->machine->frame_base_offset
526 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
527 #define sparc_leaf_function_p cfun->machine->leaf_function_p
528 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
529 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
531 /* 1 if the next opcode is to be specially indented. */
532 int sparc_indent_opcode
= 0;
534 static void sparc_option_override (void);
535 static void sparc_init_modes (void);
536 static void scan_record_type (const_tree
, int *, int *, int *);
537 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
538 const_tree
, bool, bool, int *, int *);
540 static int supersparc_adjust_cost (rtx
, rtx
, rtx
, int);
541 static int hypersparc_adjust_cost (rtx
, rtx
, rtx
, int);
543 static void sparc_emit_set_const32 (rtx
, rtx
);
544 static void sparc_emit_set_const64 (rtx
, rtx
);
545 static void sparc_output_addr_vec (rtx
);
546 static void sparc_output_addr_diff_vec (rtx
);
547 static void sparc_output_deferred_case_vectors (void);
548 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
549 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
550 static rtx
sparc_builtin_saveregs (void);
551 static int epilogue_renumber (rtx
*, int);
552 static bool sparc_assemble_integer (rtx
, unsigned int, int);
553 static int set_extends (rtx
);
554 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
555 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
556 #ifdef TARGET_SOLARIS
557 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
558 tree
) ATTRIBUTE_UNUSED
;
560 static int sparc_adjust_cost (rtx
, rtx
, rtx
, int);
561 static int sparc_issue_rate (void);
562 static void sparc_sched_init (FILE *, int, int);
563 static int sparc_use_sched_lookahead (void);
565 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
566 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
567 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
568 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
569 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
571 static bool sparc_function_ok_for_sibcall (tree
, tree
);
572 static void sparc_init_libfuncs (void);
573 static void sparc_init_builtins (void);
574 static void sparc_fpu_init_builtins (void);
575 static void sparc_vis_init_builtins (void);
576 static tree
sparc_builtin_decl (unsigned, bool);
577 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
578 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
579 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
580 HOST_WIDE_INT
, tree
);
581 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
582 HOST_WIDE_INT
, const_tree
);
583 static struct machine_function
* sparc_init_machine_status (void);
584 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
585 static rtx
sparc_tls_get_addr (void);
586 static rtx
sparc_tls_got (void);
587 static const char *get_some_local_dynamic_name (void);
588 static int get_some_local_dynamic_name_1 (rtx
*, void *);
589 static int sparc_register_move_cost (enum machine_mode
,
590 reg_class_t
, reg_class_t
);
591 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
592 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
593 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
594 static bool sparc_function_value_regno_p (const unsigned int);
595 static rtx
sparc_struct_value_rtx (tree
, int);
596 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
597 int *, const_tree
, int);
598 static bool sparc_return_in_memory (const_tree
, const_tree
);
599 static bool sparc_strict_argument_naming (cumulative_args_t
);
600 static void sparc_va_start (tree
, rtx
);
601 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
602 static bool sparc_vector_mode_supported_p (enum machine_mode
);
603 static bool sparc_tls_referenced_p (rtx
);
604 static rtx
sparc_legitimize_tls_address (rtx
);
605 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
606 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
607 static rtx
sparc_delegitimize_address (rtx
);
608 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
609 static bool sparc_pass_by_reference (cumulative_args_t
,
610 enum machine_mode
, const_tree
, bool);
611 static void sparc_function_arg_advance (cumulative_args_t
,
612 enum machine_mode
, const_tree
, bool);
613 static rtx
sparc_function_arg_1 (cumulative_args_t
,
614 enum machine_mode
, const_tree
, bool, bool);
615 static rtx
sparc_function_arg (cumulative_args_t
,
616 enum machine_mode
, const_tree
, bool);
617 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
618 enum machine_mode
, const_tree
, bool);
619 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
621 static int sparc_arg_partial_bytes (cumulative_args_t
,
622 enum machine_mode
, tree
, bool);
623 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
624 static void sparc_file_end (void);
625 static bool sparc_frame_pointer_required (void);
626 static bool sparc_can_eliminate (const int, const int);
627 static rtx
sparc_builtin_setjmp_frame_value (void);
628 static void sparc_conditional_register_usage (void);
629 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
630 static const char *sparc_mangle_type (const_tree
);
632 static void sparc_trampoline_init (rtx
, tree
, rtx
);
633 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
634 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
635 static bool sparc_print_operand_punct_valid_p (unsigned char);
636 static void sparc_print_operand (FILE *, rtx
, int);
637 static void sparc_print_operand_address (FILE *, rtx
);
638 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
640 secondary_reload_info
*);
641 static enum machine_mode
sparc_cstore_mode (enum insn_code icode
);
642 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
644 #ifdef SUBTARGET_ATTRIBUTE_TABLE
645 /* Table of valid machine attributes. */
646 static const struct attribute_spec sparc_attribute_table
[] =
648 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
650 SUBTARGET_ATTRIBUTE_TABLE
,
651 { NULL
, 0, 0, false, false, false, NULL
, false }
655 /* Option handling. */
658 enum cmodel sparc_cmodel
;
660 char sparc_hard_reg_printed
[8];
662 /* Initialize the GCC target structure. */
664 /* The default is to use .half rather than .short for aligned HI objects. */
665 #undef TARGET_ASM_ALIGNED_HI_OP
666 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
668 #undef TARGET_ASM_UNALIGNED_HI_OP
669 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
670 #undef TARGET_ASM_UNALIGNED_SI_OP
671 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
672 #undef TARGET_ASM_UNALIGNED_DI_OP
673 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
675 /* The target hook has to handle DI-mode values. */
676 #undef TARGET_ASM_INTEGER
677 #define TARGET_ASM_INTEGER sparc_assemble_integer
679 #undef TARGET_ASM_FUNCTION_PROLOGUE
680 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
681 #undef TARGET_ASM_FUNCTION_EPILOGUE
682 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
684 #undef TARGET_SCHED_ADJUST_COST
685 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
686 #undef TARGET_SCHED_ISSUE_RATE
687 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
688 #undef TARGET_SCHED_INIT
689 #define TARGET_SCHED_INIT sparc_sched_init
690 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
691 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
693 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
694 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
696 #undef TARGET_INIT_LIBFUNCS
697 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
699 #undef TARGET_LEGITIMIZE_ADDRESS
700 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
701 #undef TARGET_DELEGITIMIZE_ADDRESS
702 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
703 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
704 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
706 #undef TARGET_INIT_BUILTINS
707 #define TARGET_INIT_BUILTINS sparc_init_builtins
708 #undef TARGET_BUILTIN_DECL
709 #define TARGET_BUILTIN_DECL sparc_builtin_decl
710 #undef TARGET_EXPAND_BUILTIN
711 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
712 #undef TARGET_FOLD_BUILTIN
713 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
716 #undef TARGET_HAVE_TLS
717 #define TARGET_HAVE_TLS true
720 #undef TARGET_CANNOT_FORCE_CONST_MEM
721 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
723 #undef TARGET_ASM_OUTPUT_MI_THUNK
724 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
725 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
726 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
728 #undef TARGET_RTX_COSTS
729 #define TARGET_RTX_COSTS sparc_rtx_costs
730 #undef TARGET_ADDRESS_COST
731 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
732 #undef TARGET_REGISTER_MOVE_COST
733 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
735 #undef TARGET_PROMOTE_FUNCTION_MODE
736 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
738 #undef TARGET_FUNCTION_VALUE
739 #define TARGET_FUNCTION_VALUE sparc_function_value
740 #undef TARGET_LIBCALL_VALUE
741 #define TARGET_LIBCALL_VALUE sparc_libcall_value
742 #undef TARGET_FUNCTION_VALUE_REGNO_P
743 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
745 #undef TARGET_STRUCT_VALUE_RTX
746 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
747 #undef TARGET_RETURN_IN_MEMORY
748 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
749 #undef TARGET_MUST_PASS_IN_STACK
750 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
751 #undef TARGET_PASS_BY_REFERENCE
752 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
753 #undef TARGET_ARG_PARTIAL_BYTES
754 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
755 #undef TARGET_FUNCTION_ARG_ADVANCE
756 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
757 #undef TARGET_FUNCTION_ARG
758 #define TARGET_FUNCTION_ARG sparc_function_arg
759 #undef TARGET_FUNCTION_INCOMING_ARG
760 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
761 #undef TARGET_FUNCTION_ARG_BOUNDARY
762 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
764 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
765 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
766 #undef TARGET_STRICT_ARGUMENT_NAMING
767 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
769 #undef TARGET_EXPAND_BUILTIN_VA_START
770 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
771 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
772 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
774 #undef TARGET_VECTOR_MODE_SUPPORTED_P
775 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
777 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
778 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
780 #ifdef SUBTARGET_INSERT_ATTRIBUTES
781 #undef TARGET_INSERT_ATTRIBUTES
782 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
785 #ifdef SUBTARGET_ATTRIBUTE_TABLE
786 #undef TARGET_ATTRIBUTE_TABLE
787 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
790 #undef TARGET_RELAXED_ORDERING
791 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
793 #undef TARGET_OPTION_OVERRIDE
794 #define TARGET_OPTION_OVERRIDE sparc_option_override
796 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
797 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
798 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
801 #undef TARGET_ASM_FILE_END
802 #define TARGET_ASM_FILE_END sparc_file_end
804 #undef TARGET_FRAME_POINTER_REQUIRED
805 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
807 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
808 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
810 #undef TARGET_CAN_ELIMINATE
811 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
813 #undef TARGET_PREFERRED_RELOAD_CLASS
814 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
816 #undef TARGET_SECONDARY_RELOAD
817 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
819 #undef TARGET_CONDITIONAL_REGISTER_USAGE
820 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
822 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
823 #undef TARGET_MANGLE_TYPE
824 #define TARGET_MANGLE_TYPE sparc_mangle_type
827 #undef TARGET_LEGITIMATE_ADDRESS_P
828 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
830 #undef TARGET_LEGITIMATE_CONSTANT_P
831 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
833 #undef TARGET_TRAMPOLINE_INIT
834 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
836 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
837 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
838 #undef TARGET_PRINT_OPERAND
839 #define TARGET_PRINT_OPERAND sparc_print_operand
840 #undef TARGET_PRINT_OPERAND_ADDRESS
841 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
843 /* The value stored by LDSTUB. */
844 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
845 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
847 #undef TARGET_CSTORE_MODE
848 #define TARGET_CSTORE_MODE sparc_cstore_mode
850 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
851 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
853 struct gcc_target targetm
= TARGET_INITIALIZER
;
855 /* Return the memory reference contained in X if any, zero otherwise. */
860 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
869 /* We use a machine specific pass to enable workarounds for errata.
870 We need to have the (essentially) final form of the insn stream in order
871 to properly detect the various hazards. Therefore, this machine specific
872 pass runs as late as possible. The pass is inserted in the pass pipeline
873 at the end of sparc_option_override. */
876 sparc_do_work_around_errata (void)
880 /* Force all instructions to be split into their final form. */
881 split_all_insns_noflow ();
883 /* Now look for specific patterns in the insn stream. */
884 for (insn
= get_insns (); insn
; insn
= next
)
886 bool insert_nop
= false;
889 /* Look into the instruction in a delay slot. */
890 if (NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
891 insn
= XVECEXP (PATTERN (insn
), 0, 1);
893 /* Look for a single-word load into an odd-numbered FP register. */
895 && NONJUMP_INSN_P (insn
)
896 && (set
= single_set (insn
)) != NULL_RTX
897 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
898 && MEM_P (SET_SRC (set
))
899 && REG_P (SET_DEST (set
))
900 && REGNO (SET_DEST (set
)) > 31
901 && REGNO (SET_DEST (set
)) % 2 != 0)
903 /* The wrong dependency is on the enclosing double register. */
904 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
905 unsigned int src1
, src2
, dest
;
908 next
= next_active_insn (insn
);
911 /* If the insn is a branch, then it cannot be problematic. */
912 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
916 code
= INSN_CODE (next
);
920 case CODE_FOR_adddf3
:
921 case CODE_FOR_subdf3
:
922 case CODE_FOR_muldf3
:
923 case CODE_FOR_divdf3
:
924 dest
= REGNO (recog_data
.operand
[0]);
925 src1
= REGNO (recog_data
.operand
[1]);
926 src2
= REGNO (recog_data
.operand
[2]);
931 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
932 if ((src1
== x
|| src2
== x
)
933 && (dest
== src1
|| dest
== src2
))
940 FPOPd %fx, %fx, %fx */
943 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
948 case CODE_FOR_sqrtdf2
:
949 dest
= REGNO (recog_data
.operand
[0]);
950 src1
= REGNO (recog_data
.operand
[1]);
954 if (src1
== x
&& dest
== src1
)
963 /* Look for a single-word load into an integer register. */
964 else if (sparc_fix_ut699
965 && NONJUMP_INSN_P (insn
)
966 && (set
= single_set (insn
)) != NULL_RTX
967 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
968 && mem_ref (SET_SRC (set
)) != NULL_RTX
969 && REG_P (SET_DEST (set
))
970 && REGNO (SET_DEST (set
)) < 32)
972 /* There is no problem if the second memory access has a data
973 dependency on the first single-cycle load. */
974 rtx x
= SET_DEST (set
);
976 next
= next_active_insn (insn
);
979 /* If the insn is a branch, then it cannot be problematic. */
980 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
983 /* Look for a second memory access to/from an integer register. */
984 if ((set
= single_set (next
)) != NULL_RTX
)
986 rtx src
= SET_SRC (set
);
987 rtx dest
= SET_DEST (set
);
990 /* LDD is affected. */
991 if ((mem
= mem_ref (src
)) != NULL_RTX
994 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
997 /* STD is *not* affected. */
998 else if (MEM_P (dest
)
999 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1000 && (src
== CONST0_RTX (GET_MODE (dest
))
1003 && REGNO (src
) != REGNO (x
)))
1004 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1009 /* Look for a single-word load/operation into an FP register. */
1010 else if (sparc_fix_ut699
1011 && NONJUMP_INSN_P (insn
)
1012 && (set
= single_set (insn
)) != NULL_RTX
1013 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1014 && REG_P (SET_DEST (set
))
1015 && REGNO (SET_DEST (set
)) > 31)
1017 /* Number of instructions in the problematic window. */
1018 const int n_insns
= 4;
1019 /* The problematic combination is with the sibling FP register. */
1020 const unsigned int x
= REGNO (SET_DEST (set
));
1021 const unsigned int y
= x
^ 1;
1025 next
= next_active_insn (insn
);
1028 /* If the insn is a branch, then it cannot be problematic. */
1029 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1032 /* Look for a second load/operation into the sibling FP register. */
1033 if (!((set
= single_set (next
)) != NULL_RTX
1034 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1035 && REG_P (SET_DEST (set
))
1036 && REGNO (SET_DEST (set
)) == y
))
1039 /* Look for a (possible) store from the FP register in the next N
1040 instructions, but bail out if it is again modified or if there
1041 is a store from the sibling FP register before this store. */
1042 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1046 after
= next_active_insn (after
);
1050 /* This is a branch with an empty delay slot. */
1051 if (!NONJUMP_INSN_P (after
))
1058 /* This is a branch with a filled delay slot. */
1059 else if (GET_CODE (PATTERN (after
)) == SEQUENCE
)
1064 after
= XVECEXP (PATTERN (after
), 0, 1);
1066 /* This is a regular instruction. */
1070 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1072 const rtx src
= SET_SRC (set
);
1073 const rtx dest
= SET_DEST (set
);
1074 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1076 /* If the FP register is again modified before the store,
1077 then the store isn't affected. */
1079 && (REGNO (dest
) == x
1080 || (REGNO (dest
) == y
&& size
== 8)))
1083 if (MEM_P (dest
) && REG_P (src
))
1085 /* If there is a store from the sibling FP register
1086 before the store, then the store is not affected. */
1087 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1090 /* Otherwise, the store is affected. */
1091 if (REGNO (src
) == x
&& size
== 4)
1099 /* If we have a branch in the first M instructions, then we
1100 cannot see the (M+2)th instruction so we play safe. */
1101 if (branch_p
&& i
<= (n_insns
- 2))
1110 next
= NEXT_INSN (insn
);
1113 emit_insn_before (gen_nop (), next
);
1121 const pass_data pass_data_work_around_errata
=
1123 RTL_PASS
, /* type */
1124 "errata", /* name */
1125 OPTGROUP_NONE
, /* optinfo_flags */
1126 TV_MACH_DEP
, /* tv_id */
1127 0, /* properties_required */
1128 0, /* properties_provided */
1129 0, /* properties_destroyed */
1130 0, /* todo_flags_start */
1131 0, /* todo_flags_finish */
1134 class pass_work_around_errata
: public rtl_opt_pass
1137 pass_work_around_errata(gcc::context
*ctxt
)
1138 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1141 /* opt_pass methods: */
1142 virtual bool gate (function
*)
1144 /* The only errata we handle are those of the AT697F and UT699. */
1145 return sparc_fix_at697f
!= 0 || sparc_fix_ut699
!= 0;
1148 virtual unsigned int execute (function
*)
1150 return sparc_do_work_around_errata ();
1153 }; // class pass_work_around_errata
1158 make_pass_work_around_errata (gcc::context
*ctxt
)
1160 return new pass_work_around_errata (ctxt
);
1163 /* Helpers for TARGET_DEBUG_OPTIONS. */
1165 dump_target_flag_bits (const int flags
)
1167 if (flags
& MASK_64BIT
)
1168 fprintf (stderr
, "64BIT ");
1169 if (flags
& MASK_APP_REGS
)
1170 fprintf (stderr
, "APP_REGS ");
1171 if (flags
& MASK_FASTER_STRUCTS
)
1172 fprintf (stderr
, "FASTER_STRUCTS ");
1173 if (flags
& MASK_FLAT
)
1174 fprintf (stderr
, "FLAT ");
1175 if (flags
& MASK_FMAF
)
1176 fprintf (stderr
, "FMAF ");
1177 if (flags
& MASK_FPU
)
1178 fprintf (stderr
, "FPU ");
1179 if (flags
& MASK_HARD_QUAD
)
1180 fprintf (stderr
, "HARD_QUAD ");
1181 if (flags
& MASK_POPC
)
1182 fprintf (stderr
, "POPC ");
1183 if (flags
& MASK_PTR64
)
1184 fprintf (stderr
, "PTR64 ");
1185 if (flags
& MASK_STACK_BIAS
)
1186 fprintf (stderr
, "STACK_BIAS ");
1187 if (flags
& MASK_UNALIGNED_DOUBLES
)
1188 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1189 if (flags
& MASK_V8PLUS
)
1190 fprintf (stderr
, "V8PLUS ");
1191 if (flags
& MASK_VIS
)
1192 fprintf (stderr
, "VIS ");
1193 if (flags
& MASK_VIS2
)
1194 fprintf (stderr
, "VIS2 ");
1195 if (flags
& MASK_VIS3
)
1196 fprintf (stderr
, "VIS3 ");
1197 if (flags
& MASK_CBCOND
)
1198 fprintf (stderr
, "CBCOND ");
1199 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1200 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1201 if (flags
& MASK_SPARCLET
)
1202 fprintf (stderr
, "SPARCLET ");
1203 if (flags
& MASK_SPARCLITE
)
1204 fprintf (stderr
, "SPARCLITE ");
1205 if (flags
& MASK_V8
)
1206 fprintf (stderr
, "V8 ");
1207 if (flags
& MASK_V9
)
1208 fprintf (stderr
, "V9 ");
1212 dump_target_flags (const char *prefix
, const int flags
)
1214 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1215 dump_target_flag_bits (flags
);
1216 fprintf(stderr
, "]\n");
1219 /* Validate and override various options, and do some machine dependent
1223 sparc_option_override (void)
1225 static struct code_model
{
1226 const char *const name
;
1227 const enum cmodel value
;
1228 } const cmodels
[] = {
1230 { "medlow", CM_MEDLOW
},
1231 { "medmid", CM_MEDMID
},
1232 { "medany", CM_MEDANY
},
1233 { "embmedany", CM_EMBMEDANY
},
1234 { NULL
, (enum cmodel
) 0 }
1236 const struct code_model
*cmodel
;
1237 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1238 static struct cpu_default
{
1240 const enum processor_type processor
;
1241 } const cpu_default
[] = {
1242 /* There must be one entry here for each TARGET_CPU value. */
1243 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1244 { TARGET_CPU_v8
, PROCESSOR_V8
},
1245 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1246 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1247 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1248 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1249 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1250 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1251 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1252 { TARGET_CPU_v9
, PROCESSOR_V9
},
1253 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1254 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1255 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1256 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1257 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1258 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1259 { -1, PROCESSOR_V7
}
1261 const struct cpu_default
*def
;
1262 /* Table of values for -m{cpu,tune}=. This must match the order of
1263 the enum processor_type in sparc-opts.h. */
1264 static struct cpu_table
{
1265 const char *const name
;
1268 } const cpu_table
[] = {
1269 { "v7", MASK_ISA
, 0 },
1270 { "cypress", MASK_ISA
, 0 },
1271 { "v8", MASK_ISA
, MASK_V8
},
1272 /* TI TMS390Z55 supersparc */
1273 { "supersparc", MASK_ISA
, MASK_V8
},
1274 { "hypersparc", MASK_ISA
, MASK_V8
|MASK_FPU
},
1275 { "leon", MASK_ISA
, MASK_V8
|MASK_LEON
|MASK_FPU
},
1276 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
|MASK_FPU
},
1277 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1278 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1279 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1280 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1281 { "f934", MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
1282 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1283 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1284 /* TEMIC sparclet */
1285 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1286 { "v9", MASK_ISA
, MASK_V9
},
1287 /* UltraSPARC I, II, IIi */
1288 { "ultrasparc", MASK_ISA
,
1289 /* Although insns using %y are deprecated, it is a clear win. */
1290 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1291 /* UltraSPARC III */
1292 /* ??? Check if %y issue still holds true. */
1293 { "ultrasparc3", MASK_ISA
,
1294 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1296 { "niagara", MASK_ISA
,
1297 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1299 { "niagara2", MASK_ISA
,
1300 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1302 { "niagara3", MASK_ISA
,
1303 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
1305 { "niagara4", MASK_ISA
,
1306 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1308 const struct cpu_table
*cpu
;
1312 if (sparc_debug_string
!= NULL
)
1317 p
= ASTRDUP (sparc_debug_string
);
1318 while ((q
= strtok (p
, ",")) != NULL
)
1332 if (! strcmp (q
, "all"))
1333 mask
= MASK_DEBUG_ALL
;
1334 else if (! strcmp (q
, "options"))
1335 mask
= MASK_DEBUG_OPTIONS
;
1337 error ("unknown -mdebug-%s switch", q
);
1340 sparc_debug
&= ~mask
;
1342 sparc_debug
|= mask
;
1346 if (TARGET_DEBUG_OPTIONS
)
1348 dump_target_flags("Initial target_flags", target_flags
);
1349 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1352 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1353 SUBTARGET_OVERRIDE_OPTIONS
;
1356 #ifndef SPARC_BI_ARCH
1357 /* Check for unsupported architecture size. */
1358 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1359 error ("%s is not supported by this configuration",
1360 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1363 /* We force all 64bit archs to use 128 bit long double */
1364 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
1366 error ("-mlong-double-64 not allowed with -m64");
1367 target_flags
|= MASK_LONG_DOUBLE_128
;
1370 /* Code model selection. */
1371 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1373 #ifdef SPARC_BI_ARCH
1375 sparc_cmodel
= CM_32
;
1378 if (sparc_cmodel_string
!= NULL
)
1382 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1383 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1385 if (cmodel
->name
== NULL
)
1386 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1388 sparc_cmodel
= cmodel
->value
;
1391 error ("-mcmodel= is not supported on 32 bit systems");
1394 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1395 for (i
= 8; i
< 16; i
++)
1396 if (!call_used_regs
[i
])
1398 error ("-fcall-saved-REG is not supported for out registers");
1399 call_used_regs
[i
] = 1;
1402 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
1404 /* Set the default CPU. */
1405 if (!global_options_set
.x_sparc_cpu_and_features
)
1407 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1408 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1410 gcc_assert (def
->cpu
!= -1);
1411 sparc_cpu_and_features
= def
->processor
;
1414 if (!global_options_set
.x_sparc_cpu
)
1415 sparc_cpu
= sparc_cpu_and_features
;
1417 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1419 if (TARGET_DEBUG_OPTIONS
)
1421 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1422 fprintf (stderr
, "sparc_cpu: %s\n",
1423 cpu_table
[(int) sparc_cpu
].name
);
1424 dump_target_flags ("cpu->disable", cpu
->disable
);
1425 dump_target_flags ("cpu->enable", cpu
->enable
);
1428 target_flags
&= ~cpu
->disable
;
1429 target_flags
|= (cpu
->enable
1430 #ifndef HAVE_AS_FMAF_HPC_VIS3
1431 & ~(MASK_FMAF
| MASK_VIS3
)
1433 #ifndef HAVE_AS_SPARC4
1436 #ifndef HAVE_AS_LEON
1437 & ~(MASK_LEON
| MASK_LEON3
)
1441 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1442 the processor default. */
1443 if (target_flags_explicit
& MASK_FPU
)
1444 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
1446 /* -mvis2 implies -mvis */
1448 target_flags
|= MASK_VIS
;
1450 /* -mvis3 implies -mvis2 and -mvis */
1452 target_flags
|= MASK_VIS2
| MASK_VIS
;
1454 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is
1457 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_FMAF
);
1459 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1461 -m64 also implies v9. */
1462 if (TARGET_VIS
|| TARGET_ARCH64
)
1464 target_flags
|= MASK_V9
;
1465 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1468 /* -mvis also implies -mv8plus on 32-bit */
1469 if (TARGET_VIS
&& ! TARGET_ARCH64
)
1470 target_flags
|= MASK_V8PLUS
;
1472 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1473 if (TARGET_V9
&& TARGET_ARCH32
)
1474 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1476 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1477 if (! TARGET_V9
|| TARGET_ARCH64
)
1478 target_flags
&= ~MASK_V8PLUS
;
1480 /* Don't use stack biasing in 32 bit mode. */
1482 target_flags
&= ~MASK_STACK_BIAS
;
1484 /* Supply a default value for align_functions. */
1485 if (align_functions
== 0
1486 && (sparc_cpu
== PROCESSOR_ULTRASPARC
1487 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1488 || sparc_cpu
== PROCESSOR_NIAGARA
1489 || sparc_cpu
== PROCESSOR_NIAGARA2
1490 || sparc_cpu
== PROCESSOR_NIAGARA3
1491 || sparc_cpu
== PROCESSOR_NIAGARA4
))
1492 align_functions
= 32;
1494 /* Validate PCC_STRUCT_RETURN. */
1495 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1496 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1498 /* Only use .uaxword when compiling for a 64-bit target. */
1500 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1502 /* Do various machine dependent initializations. */
1503 sparc_init_modes ();
1505 /* Set up function hooks. */
1506 init_machine_status
= sparc_init_machine_status
;
1511 case PROCESSOR_CYPRESS
:
1512 sparc_costs
= &cypress_costs
;
1515 case PROCESSOR_SPARCLITE
:
1516 case PROCESSOR_SUPERSPARC
:
1517 sparc_costs
= &supersparc_costs
;
1519 case PROCESSOR_F930
:
1520 case PROCESSOR_F934
:
1521 case PROCESSOR_HYPERSPARC
:
1522 case PROCESSOR_SPARCLITE86X
:
1523 sparc_costs
= &hypersparc_costs
;
1525 case PROCESSOR_LEON
:
1526 sparc_costs
= &leon_costs
;
1528 case PROCESSOR_LEON3
:
1529 sparc_costs
= &leon3_costs
;
1531 case PROCESSOR_SPARCLET
:
1532 case PROCESSOR_TSC701
:
1533 sparc_costs
= &sparclet_costs
;
1536 case PROCESSOR_ULTRASPARC
:
1537 sparc_costs
= &ultrasparc_costs
;
1539 case PROCESSOR_ULTRASPARC3
:
1540 sparc_costs
= &ultrasparc3_costs
;
1542 case PROCESSOR_NIAGARA
:
1543 sparc_costs
= &niagara_costs
;
1545 case PROCESSOR_NIAGARA2
:
1546 sparc_costs
= &niagara2_costs
;
1548 case PROCESSOR_NIAGARA3
:
1549 sparc_costs
= &niagara3_costs
;
1551 case PROCESSOR_NIAGARA4
:
1552 sparc_costs
= &niagara4_costs
;
1554 case PROCESSOR_NATIVE
:
1558 if (sparc_memory_model
== SMM_DEFAULT
)
1560 /* Choose the memory model for the operating system. */
1561 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1562 if (os_default
!= SMM_DEFAULT
)
1563 sparc_memory_model
= os_default
;
1564 /* Choose the most relaxed model for the processor. */
1566 sparc_memory_model
= SMM_RMO
;
1567 else if (TARGET_LEON3
)
1568 sparc_memory_model
= SMM_TSO
;
1569 else if (TARGET_LEON
)
1570 sparc_memory_model
= SMM_SC
;
1572 sparc_memory_model
= SMM_PSO
;
1574 sparc_memory_model
= SMM_SC
;
1577 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1578 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1579 target_flags
|= MASK_LONG_DOUBLE_128
;
1582 if (TARGET_DEBUG_OPTIONS
)
1583 dump_target_flags ("Final target_flags", target_flags
);
1585 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1586 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1587 || sparc_cpu
== PROCESSOR_NIAGARA
1588 || sparc_cpu
== PROCESSOR_NIAGARA2
1589 || sparc_cpu
== PROCESSOR_NIAGARA3
1590 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1592 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1594 global_options
.x_param_values
,
1595 global_options_set
.x_param_values
);
1596 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
1597 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1598 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1599 || sparc_cpu
== PROCESSOR_NIAGARA
1600 || sparc_cpu
== PROCESSOR_NIAGARA2
1601 || sparc_cpu
== PROCESSOR_NIAGARA3
1602 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1604 global_options
.x_param_values
,
1605 global_options_set
.x_param_values
);
1607 /* Disable save slot sharing for call-clobbered registers by default.
1608 The IRA sharing algorithm works on single registers only and this
1609 pessimizes for double floating-point registers. */
1610 if (!global_options_set
.x_flag_ira_share_save_slots
)
1611 flag_ira_share_save_slots
= 0;
1613 /* We register a machine specific pass to work around errata, if any.
1614 The pass mut be scheduled as late as possible so that we have the
1615 (essentially) final form of the insn stream to work on.
1616 Registering the pass must be done at start up. It's convenient to
1618 opt_pass
*errata_pass
= make_pass_work_around_errata (g
);
1619 struct register_pass_info insert_pass_work_around_errata
=
1621 errata_pass
, /* pass */
1622 "dbr", /* reference_pass_name */
1623 1, /* ref_pass_instance_number */
1624 PASS_POS_INSERT_AFTER
/* po_op */
1626 register_pass (&insert_pass_work_around_errata
);
1629 /* Miscellaneous utilities. */
1631 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1632 or branch on register contents instructions. */
1635 v9_regcmp_p (enum rtx_code code
)
1637 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1638 || code
== LE
|| code
== GT
);
1641 /* Nonzero if OP is a floating point constant which can
1642 be loaded into an integer register using a single
1643 sethi instruction. */
1648 if (GET_CODE (op
) == CONST_DOUBLE
)
1653 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1654 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1655 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1661 /* Nonzero if OP is a floating point constant which can
1662 be loaded into an integer register using a single
1668 if (GET_CODE (op
) == CONST_DOUBLE
)
1673 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1674 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1675 return SPARC_SIMM13_P (i
);
1681 /* Nonzero if OP is a floating point constant which can
1682 be loaded into an integer register using a high/losum
1683 instruction sequence. */
1686 fp_high_losum_p (rtx op
)
1688 /* The constraints calling this should only be in
1689 SFmode move insns, so any constant which cannot
1690 be moved using a single insn will do. */
1691 if (GET_CODE (op
) == CONST_DOUBLE
)
1696 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1697 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1698 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1704 /* Return true if the address of LABEL can be loaded by means of the
1705 mov{si,di}_pic_label_ref patterns in PIC mode. */
1708 can_use_mov_pic_label_ref (rtx label
)
1710 /* VxWorks does not impose a fixed gap between segments; the run-time
1711 gap can be different from the object-file gap. We therefore can't
1712 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1713 are absolutely sure that X is in the same segment as the GOT.
1714 Unfortunately, the flexibility of linker scripts means that we
1715 can't be sure of that in general, so assume that GOT-relative
1716 accesses are never valid on VxWorks. */
1717 if (TARGET_VXWORKS_RTP
)
1720 /* Similarly, if the label is non-local, it might end up being placed
1721 in a different section than the current one; now mov_pic_label_ref
1722 requires the label and the code to be in the same section. */
1723 if (LABEL_REF_NONLOCAL_P (label
))
1726 /* Finally, if we are reordering basic blocks and partition into hot
1727 and cold sections, this might happen for any label. */
1728 if (flag_reorder_blocks_and_partition
)
1734 /* Expand a move instruction. Return true if all work is done. */
1737 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1739 /* Handle sets of MEM first. */
1740 if (GET_CODE (operands
[0]) == MEM
)
1742 /* 0 is a register (or a pair of registers) on SPARC. */
1743 if (register_or_zero_operand (operands
[1], mode
))
1746 if (!reload_in_progress
)
1748 operands
[0] = validize_mem (operands
[0]);
1749 operands
[1] = force_reg (mode
, operands
[1]);
1753 /* Fixup TLS cases. */
1755 && CONSTANT_P (operands
[1])
1756 && sparc_tls_referenced_p (operands
[1]))
1758 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1762 /* Fixup PIC cases. */
1763 if (flag_pic
&& CONSTANT_P (operands
[1]))
1765 if (pic_address_needs_scratch (operands
[1]))
1766 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1768 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1769 if (GET_CODE (operands
[1]) == LABEL_REF
1770 && can_use_mov_pic_label_ref (operands
[1]))
1774 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1780 gcc_assert (TARGET_ARCH64
);
1781 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1786 if (symbolic_operand (operands
[1], mode
))
1789 = sparc_legitimize_pic_address (operands
[1],
1791 ? operands
[0] : NULL_RTX
);
1796 /* If we are trying to toss an integer constant into FP registers,
1797 or loading a FP or vector constant, force it into memory. */
1798 if (CONSTANT_P (operands
[1])
1799 && REG_P (operands
[0])
1800 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1801 || SCALAR_FLOAT_MODE_P (mode
)
1802 || VECTOR_MODE_P (mode
)))
1804 /* emit_group_store will send such bogosity to us when it is
1805 not storing directly into memory. So fix this up to avoid
1806 crashes in output_constant_pool. */
1807 if (operands
[1] == const0_rtx
)
1808 operands
[1] = CONST0_RTX (mode
);
1810 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1811 always other regs. */
1812 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1813 && (const_zero_operand (operands
[1], mode
)
1814 || const_all_ones_operand (operands
[1], mode
)))
1817 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1818 /* We are able to build any SF constant in integer registers
1819 with at most 2 instructions. */
1821 /* And any DF constant in integer registers. */
1823 && ! can_create_pseudo_p ())))
1826 operands
[1] = force_const_mem (mode
, operands
[1]);
1827 if (!reload_in_progress
)
1828 operands
[1] = validize_mem (operands
[1]);
1832 /* Accept non-constants and valid constants unmodified. */
1833 if (!CONSTANT_P (operands
[1])
1834 || GET_CODE (operands
[1]) == HIGH
1835 || input_operand (operands
[1], mode
))
1841 /* All QImode constants require only one insn, so proceed. */
1846 sparc_emit_set_const32 (operands
[0], operands
[1]);
1850 /* input_operand should have filtered out 32-bit mode. */
1851 sparc_emit_set_const64 (operands
[0], operands
[1]);
1857 /* TImode isn't available in 32-bit mode. */
1858 split_double (operands
[1], &high
, &low
);
1859 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
1861 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
1873 /* Load OP1, a 32-bit constant, into OP0, a register.
1874 We know it can't be done in one insn when we get
1875 here, the move expander guarantees this. */
1878 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1880 enum machine_mode mode
= GET_MODE (op0
);
1883 if (can_create_pseudo_p ())
1884 temp
= gen_reg_rtx (mode
);
1886 if (GET_CODE (op1
) == CONST_INT
)
1888 gcc_assert (!small_int_operand (op1
, mode
)
1889 && !const_high_operand (op1
, mode
));
1891 /* Emit them as real moves instead of a HIGH/LO_SUM,
1892 this way CSE can see everything and reuse intermediate
1893 values if it wants. */
1894 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1895 GEN_INT (INTVAL (op1
)
1896 & ~(HOST_WIDE_INT
)0x3ff)));
1898 emit_insn (gen_rtx_SET (VOIDmode
,
1900 gen_rtx_IOR (mode
, temp
,
1901 GEN_INT (INTVAL (op1
) & 0x3ff))));
1905 /* A symbol, emit in the traditional way. */
1906 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1907 gen_rtx_HIGH (mode
, op1
)));
1908 emit_insn (gen_rtx_SET (VOIDmode
,
1909 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1913 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1914 If TEMP is nonzero, we are forbidden to use any other scratch
1915 registers. Otherwise, we are allowed to generate them as needed.
1917 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1918 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1921 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1923 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1926 if (temp
&& GET_MODE (temp
) == TImode
)
1929 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1932 /* SPARC-V9 code-model support. */
1933 switch (sparc_cmodel
)
1936 /* The range spanned by all instructions in the object is less
1937 than 2^31 bytes (2GB) and the distance from any instruction
1938 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1939 than 2^31 bytes (2GB).
1941 The executable must be in the low 4TB of the virtual address
1944 sethi %hi(symbol), %temp1
1945 or %temp1, %lo(symbol), %reg */
1947 temp1
= temp
; /* op0 is allowed. */
1949 temp1
= gen_reg_rtx (DImode
);
1951 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1952 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1956 /* The range spanned by all instructions in the object is less
1957 than 2^31 bytes (2GB) and the distance from any instruction
1958 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1959 than 2^31 bytes (2GB).
1961 The executable must be in the low 16TB of the virtual address
1964 sethi %h44(symbol), %temp1
1965 or %temp1, %m44(symbol), %temp2
1966 sllx %temp2, 12, %temp3
1967 or %temp3, %l44(symbol), %reg */
1972 temp3
= temp
; /* op0 is allowed. */
1976 temp1
= gen_reg_rtx (DImode
);
1977 temp2
= gen_reg_rtx (DImode
);
1978 temp3
= gen_reg_rtx (DImode
);
1981 emit_insn (gen_seth44 (temp1
, op1
));
1982 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1983 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1984 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1985 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1989 /* The range spanned by all instructions in the object is less
1990 than 2^31 bytes (2GB) and the distance from any instruction
1991 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1992 than 2^31 bytes (2GB).
1994 The executable can be placed anywhere in the virtual address
1997 sethi %hh(symbol), %temp1
1998 sethi %lm(symbol), %temp2
1999 or %temp1, %hm(symbol), %temp3
2000 sllx %temp3, 32, %temp4
2001 or %temp4, %temp2, %temp5
2002 or %temp5, %lo(symbol), %reg */
2005 /* It is possible that one of the registers we got for operands[2]
2006 might coincide with that of operands[0] (which is why we made
2007 it TImode). Pick the other one to use as our scratch. */
2008 if (rtx_equal_p (temp
, op0
))
2010 gcc_assert (ti_temp
);
2011 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2014 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2021 temp1
= gen_reg_rtx (DImode
);
2022 temp2
= gen_reg_rtx (DImode
);
2023 temp3
= gen_reg_rtx (DImode
);
2024 temp4
= gen_reg_rtx (DImode
);
2025 temp5
= gen_reg_rtx (DImode
);
2028 emit_insn (gen_sethh (temp1
, op1
));
2029 emit_insn (gen_setlm (temp2
, op1
));
2030 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2031 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2032 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2033 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
2034 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2035 emit_insn (gen_setlo (op0
, temp5
, op1
));
2039 /* Old old old backwards compatibility kruft here.
2040 Essentially it is MEDLOW with a fixed 64-bit
2041 virtual base added to all data segment addresses.
2042 Text-segment stuff is computed like MEDANY, we can't
2043 reuse the code above because the relocation knobs
2046 Data segment: sethi %hi(symbol), %temp1
2047 add %temp1, EMBMEDANY_BASE_REG, %temp2
2048 or %temp2, %lo(symbol), %reg */
2049 if (data_segment_operand (op1
, GET_MODE (op1
)))
2053 temp1
= temp
; /* op0 is allowed. */
2058 temp1
= gen_reg_rtx (DImode
);
2059 temp2
= gen_reg_rtx (DImode
);
2062 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2063 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2064 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2067 /* Text segment: sethi %uhi(symbol), %temp1
2068 sethi %hi(symbol), %temp2
2069 or %temp1, %ulo(symbol), %temp3
2070 sllx %temp3, 32, %temp4
2071 or %temp4, %temp2, %temp5
2072 or %temp5, %lo(symbol), %reg */
2077 /* It is possible that one of the registers we got for operands[2]
2078 might coincide with that of operands[0] (which is why we made
2079 it TImode). Pick the other one to use as our scratch. */
2080 if (rtx_equal_p (temp
, op0
))
2082 gcc_assert (ti_temp
);
2083 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2086 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2093 temp1
= gen_reg_rtx (DImode
);
2094 temp2
= gen_reg_rtx (DImode
);
2095 temp3
= gen_reg_rtx (DImode
);
2096 temp4
= gen_reg_rtx (DImode
);
2097 temp5
= gen_reg_rtx (DImode
);
2100 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2101 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2102 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2103 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2104 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2105 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
2106 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2107 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2116 #if HOST_BITS_PER_WIDE_INT == 32
2118 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
2123 /* These avoid problems when cross compiling. If we do not
2124 go through all this hair then the optimizer will see
2125 invalid REG_EQUAL notes or in some cases none at all. */
2126 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2127 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2128 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2129 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2131 /* The optimizer is not to assume anything about exactly
2132 which bits are set for a HIGH, they are unspecified.
2133 Unfortunately this leads to many missed optimizations
2134 during CSE. We mask out the non-HIGH bits, and matches
2135 a plain movdi, to alleviate this problem. */
2137 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2139 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2143 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2145 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
2149 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2151 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2155 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2157 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2160 /* Worker routines for 64-bit constant formation on arch64.
2161 One of the key things to be doing in these emissions is
2162 to create as many temp REGs as possible. This makes it
2163 possible for half-built constants to be used later when
2164 such values are similar to something required later on.
2165 Without doing this, the optimizer cannot see such
2168 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2169 unsigned HOST_WIDE_INT
, int);
2172 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2173 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2175 unsigned HOST_WIDE_INT high_bits
;
2178 high_bits
= (~low_bits
) & 0xffffffff;
2180 high_bits
= low_bits
;
2182 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2185 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2186 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2190 /* If we are XOR'ing with -1, then we should emit a one's complement
2191 instead. This way the combiner will notice logical operations
2192 such as ANDN later on and substitute. */
2193 if ((low_bits
& 0x3ff) == 0x3ff)
2195 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2196 gen_rtx_NOT (DImode
, temp
)));
2200 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2201 gen_safe_XOR64 (temp
,
2202 (-(HOST_WIDE_INT
)0x400
2203 | (low_bits
& 0x3ff)))));
2208 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2209 unsigned HOST_WIDE_INT
, int);
2212 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2213 unsigned HOST_WIDE_INT high_bits
,
2214 unsigned HOST_WIDE_INT low_immediate
,
2219 if ((high_bits
& 0xfffffc00) != 0)
2221 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2222 if ((high_bits
& ~0xfffffc00) != 0)
2223 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2224 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2230 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2234 /* Now shift it up into place. */
2235 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2236 gen_rtx_ASHIFT (DImode
, temp2
,
2237 GEN_INT (shift_count
))));
2239 /* If there is a low immediate part piece, finish up by
2240 putting that in as well. */
2241 if (low_immediate
!= 0)
2242 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2243 gen_safe_OR64 (op0
, low_immediate
)));
2246 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2247 unsigned HOST_WIDE_INT
);
2249 /* Full 64-bit constant decomposition. Even though this is the
2250 'worst' case, we still optimize a few things away. */
2252 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2253 unsigned HOST_WIDE_INT high_bits
,
2254 unsigned HOST_WIDE_INT low_bits
)
2258 if (can_create_pseudo_p ())
2259 sub_temp
= gen_reg_rtx (DImode
);
2261 if ((high_bits
& 0xfffffc00) != 0)
2263 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2264 if ((high_bits
& ~0xfffffc00) != 0)
2265 emit_insn (gen_rtx_SET (VOIDmode
,
2267 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2273 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2277 if (can_create_pseudo_p ())
2279 rtx temp2
= gen_reg_rtx (DImode
);
2280 rtx temp3
= gen_reg_rtx (DImode
);
2281 rtx temp4
= gen_reg_rtx (DImode
);
2283 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2284 gen_rtx_ASHIFT (DImode
, sub_temp
,
2287 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2288 if ((low_bits
& ~0xfffffc00) != 0)
2290 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
2291 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2292 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2293 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2297 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2298 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2303 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2304 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2305 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2308 /* We are in the middle of reload, so this is really
2309 painful. However we do still make an attempt to
2310 avoid emitting truly stupid code. */
2311 if (low1
!= const0_rtx
)
2313 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2314 gen_rtx_ASHIFT (DImode
, sub_temp
,
2315 GEN_INT (to_shift
))));
2316 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2317 gen_rtx_IOR (DImode
, op0
, low1
)));
2325 if (low2
!= const0_rtx
)
2327 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2328 gen_rtx_ASHIFT (DImode
, sub_temp
,
2329 GEN_INT (to_shift
))));
2330 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2331 gen_rtx_IOR (DImode
, op0
, low2
)));
2339 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2340 gen_rtx_ASHIFT (DImode
, sub_temp
,
2341 GEN_INT (to_shift
))));
2342 if (low3
!= const0_rtx
)
2343 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2344 gen_rtx_IOR (DImode
, op0
, low3
)));
2349 /* Analyze a 64-bit constant for certain properties. */
2350 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2351 unsigned HOST_WIDE_INT
,
2352 int *, int *, int *);
2355 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2356 unsigned HOST_WIDE_INT low_bits
,
2357 int *hbsp
, int *lbsp
, int *abbasp
)
2359 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2362 lowest_bit_set
= highest_bit_set
= -1;
2366 if ((lowest_bit_set
== -1)
2367 && ((low_bits
>> i
) & 1))
2369 if ((highest_bit_set
== -1)
2370 && ((high_bits
>> (32 - i
- 1)) & 1))
2371 highest_bit_set
= (64 - i
- 1);
2374 && ((highest_bit_set
== -1)
2375 || (lowest_bit_set
== -1)));
2381 if ((lowest_bit_set
== -1)
2382 && ((high_bits
>> i
) & 1))
2383 lowest_bit_set
= i
+ 32;
2384 if ((highest_bit_set
== -1)
2385 && ((low_bits
>> (32 - i
- 1)) & 1))
2386 highest_bit_set
= 32 - i
- 1;
2389 && ((highest_bit_set
== -1)
2390 || (lowest_bit_set
== -1)));
2392 /* If there are no bits set this should have gone out
2393 as one instruction! */
2394 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2395 all_bits_between_are_set
= 1;
2396 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2400 if ((low_bits
& (1 << i
)) != 0)
2405 if ((high_bits
& (1 << (i
- 32))) != 0)
2408 all_bits_between_are_set
= 0;
2411 *hbsp
= highest_bit_set
;
2412 *lbsp
= lowest_bit_set
;
2413 *abbasp
= all_bits_between_are_set
;
2416 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2419 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2420 unsigned HOST_WIDE_INT low_bits
)
2422 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2425 || high_bits
== 0xffffffff)
2428 analyze_64bit_constant (high_bits
, low_bits
,
2429 &highest_bit_set
, &lowest_bit_set
,
2430 &all_bits_between_are_set
);
2432 if ((highest_bit_set
== 63
2433 || lowest_bit_set
== 0)
2434 && all_bits_between_are_set
!= 0)
2437 if ((highest_bit_set
- lowest_bit_set
) < 21)
2443 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2444 unsigned HOST_WIDE_INT
,
2447 static unsigned HOST_WIDE_INT
2448 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2449 unsigned HOST_WIDE_INT low_bits
,
2450 int lowest_bit_set
, int shift
)
2452 HOST_WIDE_INT hi
, lo
;
2454 if (lowest_bit_set
< 32)
2456 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2457 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2462 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2464 gcc_assert (! (hi
& lo
));
2468 /* Here we are sure to be arch64 and this is an integer constant
2469 being loaded into a register. Emit the most efficient
2470 insn sequence possible. Detection of all the 1-insn cases
2471 has been done already. */
2473 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2475 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2476 int lowest_bit_set
, highest_bit_set
;
2477 int all_bits_between_are_set
;
2480 /* Sanity check that we know what we are working with. */
2481 gcc_assert (TARGET_ARCH64
2482 && (GET_CODE (op0
) == SUBREG
2483 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2485 if (! can_create_pseudo_p ())
2488 if (GET_CODE (op1
) != CONST_INT
)
2490 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2495 temp
= gen_reg_rtx (DImode
);
2497 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2498 low_bits
= (INTVAL (op1
) & 0xffffffff);
2500 /* low_bits bits 0 --> 31
2501 high_bits bits 32 --> 63 */
2503 analyze_64bit_constant (high_bits
, low_bits
,
2504 &highest_bit_set
, &lowest_bit_set
,
2505 &all_bits_between_are_set
);
2507 /* First try for a 2-insn sequence. */
2509 /* These situations are preferred because the optimizer can
2510 * do more things with them:
2512 * sllx %reg, shift, %reg
2514 * srlx %reg, shift, %reg
2515 * 3) mov some_small_const, %reg
2516 * sllx %reg, shift, %reg
2518 if (((highest_bit_set
== 63
2519 || lowest_bit_set
== 0)
2520 && all_bits_between_are_set
!= 0)
2521 || ((highest_bit_set
- lowest_bit_set
) < 12))
2523 HOST_WIDE_INT the_const
= -1;
2524 int shift
= lowest_bit_set
;
2526 if ((highest_bit_set
!= 63
2527 && lowest_bit_set
!= 0)
2528 || all_bits_between_are_set
== 0)
2531 create_simple_focus_bits (high_bits
, low_bits
,
2534 else if (lowest_bit_set
== 0)
2535 shift
= -(63 - highest_bit_set
);
2537 gcc_assert (SPARC_SIMM13_P (the_const
));
2538 gcc_assert (shift
!= 0);
2540 emit_insn (gen_safe_SET64 (temp
, the_const
));
2542 emit_insn (gen_rtx_SET (VOIDmode
,
2544 gen_rtx_ASHIFT (DImode
,
2548 emit_insn (gen_rtx_SET (VOIDmode
,
2550 gen_rtx_LSHIFTRT (DImode
,
2552 GEN_INT (-shift
))));
2556 /* Now a range of 22 or less bits set somewhere.
2557 * 1) sethi %hi(focus_bits), %reg
2558 * sllx %reg, shift, %reg
2559 * 2) sethi %hi(focus_bits), %reg
2560 * srlx %reg, shift, %reg
2562 if ((highest_bit_set
- lowest_bit_set
) < 21)
2564 unsigned HOST_WIDE_INT focus_bits
=
2565 create_simple_focus_bits (high_bits
, low_bits
,
2566 lowest_bit_set
, 10);
2568 gcc_assert (SPARC_SETHI_P (focus_bits
));
2569 gcc_assert (lowest_bit_set
!= 10);
2571 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2573 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2574 if (lowest_bit_set
< 10)
2575 emit_insn (gen_rtx_SET (VOIDmode
,
2577 gen_rtx_LSHIFTRT (DImode
, temp
,
2578 GEN_INT (10 - lowest_bit_set
))));
2579 else if (lowest_bit_set
> 10)
2580 emit_insn (gen_rtx_SET (VOIDmode
,
2582 gen_rtx_ASHIFT (DImode
, temp
,
2583 GEN_INT (lowest_bit_set
- 10))));
2587 /* 1) sethi %hi(low_bits), %reg
2588 * or %reg, %lo(low_bits), %reg
2589 * 2) sethi %hi(~low_bits), %reg
2590 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2593 || high_bits
== 0xffffffff)
2595 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2596 (high_bits
== 0xffffffff));
2600 /* Now, try 3-insn sequences. */
2602 /* 1) sethi %hi(high_bits), %reg
2603 * or %reg, %lo(high_bits), %reg
2604 * sllx %reg, 32, %reg
2608 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2612 /* We may be able to do something quick
2613 when the constant is negated, so try that. */
2614 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2615 (~low_bits
) & 0xfffffc00))
2617 /* NOTE: The trailing bits get XOR'd so we need the
2618 non-negated bits, not the negated ones. */
2619 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2621 if ((((~high_bits
) & 0xffffffff) == 0
2622 && ((~low_bits
) & 0x80000000) == 0)
2623 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2624 && ((~low_bits
) & 0x80000000) != 0))
2626 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2628 if ((SPARC_SETHI_P (fast_int
)
2629 && (~high_bits
& 0xffffffff) == 0)
2630 || SPARC_SIMM13_P (fast_int
))
2631 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2633 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2638 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2639 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2640 sparc_emit_set_const64 (temp
, negated_const
);
2643 /* If we are XOR'ing with -1, then we should emit a one's complement
2644 instead. This way the combiner will notice logical operations
2645 such as ANDN later on and substitute. */
2646 if (trailing_bits
== 0x3ff)
2648 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2649 gen_rtx_NOT (DImode
, temp
)));
2653 emit_insn (gen_rtx_SET (VOIDmode
,
2655 gen_safe_XOR64 (temp
,
2656 (-0x400 | trailing_bits
))));
2661 /* 1) sethi %hi(xxx), %reg
2662 * or %reg, %lo(xxx), %reg
2663 * sllx %reg, yyy, %reg
2665 * ??? This is just a generalized version of the low_bits==0
2666 * thing above, FIXME...
2668 if ((highest_bit_set
- lowest_bit_set
) < 32)
2670 unsigned HOST_WIDE_INT focus_bits
=
2671 create_simple_focus_bits (high_bits
, low_bits
,
2674 /* We can't get here in this state. */
2675 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2677 /* So what we know is that the set bits straddle the
2678 middle of the 64-bit word. */
2679 sparc_emit_set_const64_quick2 (op0
, temp
,
2685 /* 1) sethi %hi(high_bits), %reg
2686 * or %reg, %lo(high_bits), %reg
2687 * sllx %reg, 32, %reg
2688 * or %reg, low_bits, %reg
2690 if (SPARC_SIMM13_P(low_bits
)
2691 && ((int)low_bits
> 0))
2693 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2697 /* The easiest way when all else fails, is full decomposition. */
2698 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2700 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2702 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2703 return the mode to be used for the comparison. For floating-point,
2704 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2705 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2706 processing is needed. */
2709 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2711 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2737 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2738 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2740 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2741 return CCX_NOOVmode
;
2747 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2754 /* Emit the compare insn and return the CC reg for a CODE comparison
2755 with operands X and Y. */
2758 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2760 enum machine_mode mode
;
2763 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2766 mode
= SELECT_CC_MODE (code
, x
, y
);
2768 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2769 fcc regs (cse can't tell they're really call clobbered regs and will
2770 remove a duplicate comparison even if there is an intervening function
2771 call - it will then try to reload the cc reg via an int reg which is why
2772 we need the movcc patterns). It is possible to provide the movcc
2773 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2774 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2775 to tell cse that CCFPE mode registers (even pseudos) are call
2778 /* ??? This is an experiment. Rather than making changes to cse which may
2779 or may not be easy/clean, we do our own cse. This is possible because
2780 we will generate hard registers. Cse knows they're call clobbered (it
2781 doesn't know the same thing about pseudos). If we guess wrong, no big
2782 deal, but if we win, great! */
2784 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2785 #if 1 /* experiment */
2788 /* We cycle through the registers to ensure they're all exercised. */
2789 static int next_fcc_reg
= 0;
2790 /* Previous x,y for each fcc reg. */
2791 static rtx prev_args
[4][2];
2793 /* Scan prev_args for x,y. */
2794 for (reg
= 0; reg
< 4; reg
++)
2795 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2800 prev_args
[reg
][0] = x
;
2801 prev_args
[reg
][1] = y
;
2802 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2804 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2807 cc_reg
= gen_reg_rtx (mode
);
2808 #endif /* ! experiment */
2809 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2810 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2812 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2814 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2815 will only result in an unrecognizable insn so no point in asserting. */
2816 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2822 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2825 gen_compare_reg (rtx cmp
)
2827 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2830 /* This function is used for v9 only.
2831 DEST is the target of the Scc insn.
2832 CODE is the code for an Scc's comparison.
2833 X and Y are the values we compare.
2835 This function is needed to turn
2838 (gt (reg:CCX 100 %icc)
2842 (gt:DI (reg:CCX 100 %icc)
2845 IE: The instruction recognizer needs to see the mode of the comparison to
2846 find the right instruction. We could use "gt:DI" right in the
2847 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2850 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2853 && (GET_MODE (x
) == DImode
2854 || GET_MODE (dest
) == DImode
))
2857 /* Try to use the movrCC insns. */
2859 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2861 && v9_regcmp_p (compare_code
))
2866 /* Special case for op0 != 0. This can be done with one instruction if
2869 if (compare_code
== NE
2870 && GET_MODE (dest
) == DImode
2871 && rtx_equal_p (op0
, dest
))
2873 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2874 gen_rtx_IF_THEN_ELSE (DImode
,
2875 gen_rtx_fmt_ee (compare_code
, DImode
,
2882 if (reg_overlap_mentioned_p (dest
, op0
))
2884 /* Handle the case where dest == x.
2885 We "early clobber" the result. */
2886 op0
= gen_reg_rtx (GET_MODE (x
));
2887 emit_move_insn (op0
, x
);
2890 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2891 if (GET_MODE (op0
) != DImode
)
2893 temp
= gen_reg_rtx (DImode
);
2894 convert_move (temp
, op0
, 0);
2898 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2899 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2900 gen_rtx_fmt_ee (compare_code
, DImode
,
2908 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2911 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2912 && GET_MODE (x
) != CCX_NOOVmode
);
2914 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2915 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2916 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2917 gen_rtx_fmt_ee (compare_code
,
2918 GET_MODE (x
), x
, y
),
2919 const1_rtx
, dest
)));
2925 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2926 without jumps using the addx/subx instructions. */
2929 emit_scc_insn (rtx operands
[])
2936 /* The quad-word fp compare library routines all return nonzero to indicate
2937 true, which is different from the equivalent libgcc routines, so we must
2938 handle them specially here. */
2939 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2941 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2942 GET_CODE (operands
[1]));
2943 operands
[2] = XEXP (operands
[1], 0);
2944 operands
[3] = XEXP (operands
[1], 1);
2947 code
= GET_CODE (operands
[1]);
2951 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2952 more applications). The exception to this is "reg != 0" which can
2953 be done in one instruction on v9 (so we do it). */
2956 if (GET_MODE (x
) == SImode
)
2960 pat
= gen_seqsidi_special (operands
[0], x
, y
);
2962 pat
= gen_seqsisi_special (operands
[0], x
, y
);
2966 else if (GET_MODE (x
) == DImode
)
2968 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2976 if (GET_MODE (x
) == SImode
)
2980 pat
= gen_snesidi_special (operands
[0], x
, y
);
2982 pat
= gen_snesisi_special (operands
[0], x
, y
);
2986 else if (GET_MODE (x
) == DImode
)
2990 pat
= gen_snedi_special_vis3 (operands
[0], x
, y
);
2992 pat
= gen_snedi_special (operands
[0], x
, y
);
3000 && GET_MODE (x
) == DImode
3002 && (code
== GTU
|| code
== LTU
))
3003 && gen_v9_scc (operands
[0], code
, x
, y
))
3006 /* We can do LTU and GEU using the addx/subx instructions too. And
3007 for GTU/LEU, if both operands are registers swap them and fall
3008 back to the easy case. */
3009 if (code
== GTU
|| code
== LEU
)
3011 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3012 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3017 code
= swap_condition (code
);
3022 || (!TARGET_VIS3
&& code
== GEU
))
3024 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
3025 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3026 gen_compare_reg_1 (code
, x
, y
),
3031 /* All the posibilities to use addx/subx based sequences has been
3032 exhausted, try for a 3 instruction sequence using v9 conditional
3034 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3037 /* Nope, do branches. */
3041 /* Emit a conditional jump insn for the v9 architecture using comparison code
3042 CODE and jump target LABEL.
3043 This function exists to take advantage of the v9 brxx insns. */
3046 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3048 emit_jump_insn (gen_rtx_SET (VOIDmode
,
3050 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3051 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3053 gen_rtx_LABEL_REF (VOIDmode
, label
),
3057 /* Emit a conditional jump insn for the UA2011 architecture using
3058 comparison code CODE and jump target LABEL. This function exists
3059 to take advantage of the UA2011 Compare and Branch insns. */
3062 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3066 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3067 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3069 gen_rtx_LABEL_REF (VOIDmode
, label
),
3072 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_then_else
));
3076 emit_conditional_branch_insn (rtx operands
[])
3078 /* The quad-word fp compare library routines all return nonzero to indicate
3079 true, which is different from the equivalent libgcc routines, so we must
3080 handle them specially here. */
3081 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3083 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3084 GET_CODE (operands
[0]));
3085 operands
[1] = XEXP (operands
[0], 0);
3086 operands
[2] = XEXP (operands
[0], 1);
3089 /* If we can tell early on that the comparison is against a constant
3090 that won't fit in the 5-bit signed immediate field of a cbcond,
3091 use one of the other v9 conditional branch sequences. */
3093 && GET_CODE (operands
[1]) == REG
3094 && (GET_MODE (operands
[1]) == SImode
3095 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3096 && (GET_CODE (operands
[2]) != CONST_INT
3097 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3099 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3103 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3104 && GET_CODE (operands
[1]) == REG
3105 && GET_MODE (operands
[1]) == DImode
)
3107 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3111 operands
[1] = gen_compare_reg (operands
[0]);
3112 operands
[2] = const0_rtx
;
3113 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3114 operands
[1], operands
[2]);
3115 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3120 /* Generate a DFmode part of a hard TFmode register.
3121 REG is the TFmode hard register, LOW is 1 for the
3122 low 64bit of the register and 0 otherwise.
3125 gen_df_reg (rtx reg
, int low
)
3127 int regno
= REGNO (reg
);
3129 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3130 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3131 return gen_rtx_REG (DFmode
, regno
);
3134 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3135 Unlike normal calls, TFmode operands are passed by reference. It is
3136 assumed that no more than 3 operands are required. */
3139 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3141 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3144 /* We only expect to be called for conversions, unary, and binary ops. */
3145 gcc_assert (nargs
== 2 || nargs
== 3);
3147 for (i
= 0; i
< nargs
; ++i
)
3149 rtx this_arg
= operands
[i
];
3152 /* TFmode arguments and return values are passed by reference. */
3153 if (GET_MODE (this_arg
) == TFmode
)
3155 int force_stack_temp
;
3157 force_stack_temp
= 0;
3158 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3159 force_stack_temp
= 1;
3161 if (GET_CODE (this_arg
) == MEM
3162 && ! force_stack_temp
)
3164 tree expr
= MEM_EXPR (this_arg
);
3166 mark_addressable (expr
);
3167 this_arg
= XEXP (this_arg
, 0);
3169 else if (CONSTANT_P (this_arg
)
3170 && ! force_stack_temp
)
3172 this_slot
= force_const_mem (TFmode
, this_arg
);
3173 this_arg
= XEXP (this_slot
, 0);
3177 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3179 /* Operand 0 is the return value. We'll copy it out later. */
3181 emit_move_insn (this_slot
, this_arg
);
3183 ret_slot
= this_slot
;
3185 this_arg
= XEXP (this_slot
, 0);
3192 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3194 if (GET_MODE (operands
[0]) == TFmode
)
3197 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
3198 arg
[0], GET_MODE (arg
[0]),
3199 arg
[1], GET_MODE (arg
[1]));
3201 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
3202 arg
[0], GET_MODE (arg
[0]),
3203 arg
[1], GET_MODE (arg
[1]),
3204 arg
[2], GET_MODE (arg
[2]));
3207 emit_move_insn (operands
[0], ret_slot
);
3213 gcc_assert (nargs
== 2);
3215 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3216 GET_MODE (operands
[0]), 1,
3217 arg
[1], GET_MODE (arg
[1]));
3219 if (ret
!= operands
[0])
3220 emit_move_insn (operands
[0], ret
);
3224 /* Expand soft-float TFmode calls to sparc abi routines. */
3227 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3249 emit_soft_tfmode_libcall (func
, 3, operands
);
3253 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3257 gcc_assert (code
== SQRT
);
3260 emit_soft_tfmode_libcall (func
, 2, operands
);
3264 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3271 switch (GET_MODE (operands
[1]))
3284 case FLOAT_TRUNCATE
:
3285 switch (GET_MODE (operands
[0]))
3299 switch (GET_MODE (operands
[1]))
3304 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3314 case UNSIGNED_FLOAT
:
3315 switch (GET_MODE (operands
[1]))
3320 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3331 switch (GET_MODE (operands
[0]))
3345 switch (GET_MODE (operands
[0]))
3362 emit_soft_tfmode_libcall (func
, 2, operands
);
3365 /* Expand a hard-float tfmode operation. All arguments must be in
3369 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3373 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3375 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3376 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3380 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3381 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3382 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3383 operands
[1], operands
[2]);
3386 if (register_operand (operands
[0], VOIDmode
))
3389 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3391 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
3393 if (dest
!= operands
[0])
3394 emit_move_insn (operands
[0], dest
);
3398 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3400 if (TARGET_HARD_QUAD
)
3401 emit_hard_tfmode_operation (code
, operands
);
3403 emit_soft_tfmode_binop (code
, operands
);
3407 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3409 if (TARGET_HARD_QUAD
)
3410 emit_hard_tfmode_operation (code
, operands
);
3412 emit_soft_tfmode_unop (code
, operands
);
3416 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3418 if (TARGET_HARD_QUAD
)
3419 emit_hard_tfmode_operation (code
, operands
);
3421 emit_soft_tfmode_cvt (code
, operands
);
3424 /* Return nonzero if a branch/jump/call instruction will be emitting
3425 nop into its delay slot. */
3428 empty_delay_slot (rtx insn
)
3432 /* If no previous instruction (should not happen), return true. */
3433 if (PREV_INSN (insn
) == NULL
)
3436 seq
= NEXT_INSN (PREV_INSN (insn
));
3437 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3443 /* Return nonzero if we should emit a nop after a cbcond instruction.
3444 The cbcond instruction does not have a delay slot, however there is
3445 a severe performance penalty if a control transfer appears right
3446 after a cbcond. Therefore we emit a nop when we detect this
3450 emit_cbcond_nop (rtx insn
)
3452 rtx next
= next_active_insn (insn
);
3457 if (NONJUMP_INSN_P (next
)
3458 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3459 next
= XVECEXP (PATTERN (next
), 0, 0);
3460 else if (CALL_P (next
)
3461 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3463 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3465 if (GET_CODE (delay
) == RETURN
)
3467 /* It's a sibling call. Do not emit the nop if we're going
3468 to emit something other than the jump itself as the first
3469 instruction of the sibcall sequence. */
3470 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3475 if (NONJUMP_INSN_P (next
))
3481 /* Return nonzero if TRIAL can go into the call delay slot. */
3484 eligible_for_call_delay (rtx trial
)
3488 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3492 call __tls_get_addr, %tgd_call (foo)
3493 add %l7, %o0, %o0, %tgd_add (foo)
3494 while Sun as/ld does not. */
3495 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3498 pat
= PATTERN (trial
);
3500 /* We must reject tgd_add{32|64}, i.e.
3501 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3502 and tldm_add{32|64}, i.e.
3503 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3505 if (GET_CODE (pat
) == SET
3506 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3508 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3510 if (GET_CODE (unspec
) == UNSPEC
3511 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3512 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3519 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3520 instruction. RETURN_P is true if the v9 variant 'return' is to be
3521 considered in the test too.
3523 TRIAL must be a SET whose destination is a REG appropriate for the
3524 'restore' instruction or, if RETURN_P is true, for the 'return'
3528 eligible_for_restore_insn (rtx trial
, bool return_p
)
3530 rtx pat
= PATTERN (trial
);
3531 rtx src
= SET_SRC (pat
);
3532 bool src_is_freg
= false;
3535 /* Since we now can do moves between float and integer registers when
3536 VIS3 is enabled, we have to catch this case. We can allow such
3537 moves when doing a 'return' however. */
3539 if (GET_CODE (src_reg
) == SUBREG
)
3540 src_reg
= SUBREG_REG (src_reg
);
3541 if (GET_CODE (src_reg
) == REG
3542 && SPARC_FP_REG_P (REGNO (src_reg
)))
3545 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3546 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3547 && arith_operand (src
, GET_MODE (src
))
3551 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3553 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3556 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3557 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3558 && arith_double_operand (src
, GET_MODE (src
))
3560 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3562 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3563 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3566 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3567 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3570 /* If we have the 'return' instruction, anything that does not use
3571 local or output registers and can go into a delay slot wins. */
3572 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
3575 /* The 'restore src1,src2,dest' pattern for SImode. */
3576 else if (GET_CODE (src
) == PLUS
3577 && register_operand (XEXP (src
, 0), SImode
)
3578 && arith_operand (XEXP (src
, 1), SImode
))
3581 /* The 'restore src1,src2,dest' pattern for DImode. */
3582 else if (GET_CODE (src
) == PLUS
3583 && register_operand (XEXP (src
, 0), DImode
)
3584 && arith_double_operand (XEXP (src
, 1), DImode
))
3587 /* The 'restore src1,%lo(src2),dest' pattern. */
3588 else if (GET_CODE (src
) == LO_SUM
3589 && ! TARGET_CM_MEDMID
3590 && ((register_operand (XEXP (src
, 0), SImode
)
3591 && immediate_operand (XEXP (src
, 1), SImode
))
3593 && register_operand (XEXP (src
, 0), DImode
)
3594 && immediate_operand (XEXP (src
, 1), DImode
))))
3597 /* The 'restore src,src,dest' pattern. */
3598 else if (GET_CODE (src
) == ASHIFT
3599 && (register_operand (XEXP (src
, 0), SImode
)
3600 || register_operand (XEXP (src
, 0), DImode
))
3601 && XEXP (src
, 1) == const1_rtx
)
3607 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3610 eligible_for_return_delay (rtx trial
)
3615 /* If the function uses __builtin_eh_return, the eh_return machinery
3616 occupies the delay slot. */
3617 if (crtl
->calls_eh_return
)
3620 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3623 /* In the case of a leaf or flat function, anything can go into the slot. */
3624 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3627 if (!NONJUMP_INSN_P (trial
))
3630 pat
= PATTERN (trial
);
3631 if (GET_CODE (pat
) == PARALLEL
)
3637 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3639 rtx expr
= XVECEXP (pat
, 0, i
);
3640 if (GET_CODE (expr
) != SET
)
3642 if (GET_CODE (SET_DEST (expr
)) != REG
)
3644 regno
= REGNO (SET_DEST (expr
));
3645 if (regno
>= 8 && regno
< 24)
3648 return !epilogue_renumber (&pat
, 1);
3651 if (GET_CODE (pat
) != SET
)
3654 if (GET_CODE (SET_DEST (pat
)) != REG
)
3657 regno
= REGNO (SET_DEST (pat
));
3659 /* Otherwise, only operations which can be done in tandem with
3660 a `restore' or `return' insn can go into the delay slot. */
3661 if (regno
>= 8 && regno
< 24)
3664 /* If this instruction sets up floating point register and we have a return
3665 instruction, it can probably go in. But restore will not work
3667 if (! SPARC_INT_REG_P (regno
))
3668 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
3670 return eligible_for_restore_insn (trial
, true);
3673 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3676 eligible_for_sibcall_delay (rtx trial
)
3680 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3683 if (!NONJUMP_INSN_P (trial
))
3686 pat
= PATTERN (trial
);
3688 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3690 /* If the tail call is done using the call instruction,
3691 we have to restore %o7 in the delay slot. */
3692 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3695 /* %g1 is used to build the function address */
3696 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3702 if (GET_CODE (pat
) != SET
)
3705 /* Otherwise, only operations which can be done in tandem with
3706 a `restore' insn can go into the delay slot. */
3707 if (GET_CODE (SET_DEST (pat
)) != REG
3708 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3709 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
3712 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3714 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3717 return eligible_for_restore_insn (trial
, false);
3720 /* Determine if it's legal to put X into the constant pool. This
3721 is not possible if X contains the address of a symbol that is
3722 not constant (TLS) or not known at final link time (PIC). */
3725 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
3727 switch (GET_CODE (x
))
3732 /* Accept all non-symbolic constants. */
3736 /* Labels are OK iff we are non-PIC. */
3737 return flag_pic
!= 0;
3740 /* 'Naked' TLS symbol references are never OK,
3741 non-TLS symbols are OK iff we are non-PIC. */
3742 if (SYMBOL_REF_TLS_MODEL (x
))
3745 return flag_pic
!= 0;
3748 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3751 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3752 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3760 /* Global Offset Table support. */
3761 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3762 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3764 /* Return the SYMBOL_REF for the Global Offset Table. */
3766 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3771 if (!sparc_got_symbol
)
3772 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3774 return sparc_got_symbol
;
3777 /* Ensure that we are not using patterns that are not OK with PIC. */
3787 op
= recog_data
.operand
[i
];
3788 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3789 && (GET_CODE (op
) != CONST
3790 || (GET_CODE (XEXP (op
, 0)) == MINUS
3791 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3792 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3799 /* Return true if X is an address which needs a temporary register when
3800 reloaded while generating PIC code. */
3803 pic_address_needs_scratch (rtx x
)
3805 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3806 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3807 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3808 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3809 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3815 /* Determine if a given RTX is a valid constant. We already know this
3816 satisfies CONSTANT_P. */
3819 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3821 switch (GET_CODE (x
))
3825 if (sparc_tls_referenced_p (x
))
3830 if (GET_MODE (x
) == VOIDmode
)
3833 /* Floating point constants are generally not ok.
3834 The only exception is 0.0 and all-ones in VIS. */
3836 && SCALAR_FLOAT_MODE_P (mode
)
3837 && (const_zero_operand (x
, mode
)
3838 || const_all_ones_operand (x
, mode
)))
3844 /* Vector constants are generally not ok.
3845 The only exception is 0 or -1 in VIS. */
3847 && (const_zero_operand (x
, mode
)
3848 || const_all_ones_operand (x
, mode
)))
3860 /* Determine if a given RTX is a valid constant address. */
3863 constant_address_p (rtx x
)
3865 switch (GET_CODE (x
))
3873 if (flag_pic
&& pic_address_needs_scratch (x
))
3875 return sparc_legitimate_constant_p (Pmode
, x
);
3878 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3885 /* Nonzero if the constant value X is a legitimate general operand
3886 when generating PIC code. It is given that flag_pic is on and
3887 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3890 legitimate_pic_operand_p (rtx x
)
3892 if (pic_address_needs_scratch (x
))
3894 if (sparc_tls_referenced_p (x
))
3899 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3901 && INTVAL (X) >= -0x1000 \
3902 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3904 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3906 && INTVAL (X) >= -0x1000 \
3907 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3909 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3911 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3912 ordinarily. This changes a bit when generating PIC. */
3915 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3917 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3919 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3921 else if (GET_CODE (addr
) == PLUS
)
3923 rs1
= XEXP (addr
, 0);
3924 rs2
= XEXP (addr
, 1);
3926 /* Canonicalize. REG comes first, if there are no regs,
3927 LO_SUM comes first. */
3929 && GET_CODE (rs1
) != SUBREG
3931 || GET_CODE (rs2
) == SUBREG
3932 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3934 rs1
= XEXP (addr
, 1);
3935 rs2
= XEXP (addr
, 0);
3939 && rs1
== pic_offset_table_rtx
3941 && GET_CODE (rs2
) != SUBREG
3942 && GET_CODE (rs2
) != LO_SUM
3943 && GET_CODE (rs2
) != MEM
3944 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3945 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3946 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3948 || GET_CODE (rs1
) == SUBREG
)
3949 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3954 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3955 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3957 /* We prohibit REG + REG for TFmode when there are no quad move insns
3958 and we consequently need to split. We do this because REG+REG
3959 is not an offsettable address. If we get the situation in reload
3960 where source and destination of a movtf pattern are both MEMs with
3961 REG+REG address, then only one of them gets converted to an
3962 offsettable address. */
3964 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3967 /* Likewise for TImode, but in all cases. */
3971 /* We prohibit REG + REG on ARCH32 if not optimizing for
3972 DFmode/DImode because then mem_min_alignment is likely to be zero
3973 after reload and the forced split would lack a matching splitter
3975 if (TARGET_ARCH32
&& !optimize
3976 && (mode
== DFmode
|| mode
== DImode
))
3979 else if (USE_AS_OFFSETABLE_LO10
3980 && GET_CODE (rs1
) == LO_SUM
3982 && ! TARGET_CM_MEDMID
3983 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3986 imm1
= XEXP (rs1
, 1);
3987 rs1
= XEXP (rs1
, 0);
3988 if (!CONSTANT_P (imm1
)
3989 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3993 else if (GET_CODE (addr
) == LO_SUM
)
3995 rs1
= XEXP (addr
, 0);
3996 imm1
= XEXP (addr
, 1);
3998 if (!CONSTANT_P (imm1
)
3999 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4002 /* We can't allow TFmode in 32-bit mode, because an offset greater
4003 than the alignment (8) may cause the LO_SUM to overflow. */
4004 if (mode
== TFmode
&& TARGET_ARCH32
)
4007 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4012 if (GET_CODE (rs1
) == SUBREG
)
4013 rs1
= SUBREG_REG (rs1
);
4019 if (GET_CODE (rs2
) == SUBREG
)
4020 rs2
= SUBREG_REG (rs2
);
4027 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4028 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4033 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4034 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4035 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4037 && (! SPARC_INT_REG_P (REGNO (rs2
))
4038 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4039 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4045 /* Return the SYMBOL_REF for the tls_get_addr function. */
4047 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4050 sparc_tls_get_addr (void)
4052 if (!sparc_tls_symbol
)
4053 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4055 return sparc_tls_symbol
;
4058 /* Return the Global Offset Table to be used in TLS mode. */
4061 sparc_tls_got (void)
4063 /* In PIC mode, this is just the PIC offset table. */
4066 crtl
->uses_pic_offset_table
= 1;
4067 return pic_offset_table_rtx
;
4070 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4071 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4072 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4074 load_got_register ();
4075 return global_offset_table_rtx
;
4078 /* In all other cases, we load a new pseudo with the GOT symbol. */
4079 return copy_to_reg (sparc_got ());
4082 /* Return true if X contains a thread-local symbol. */
4085 sparc_tls_referenced_p (rtx x
)
4087 if (!TARGET_HAVE_TLS
)
4090 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4091 x
= XEXP (XEXP (x
, 0), 0);
4093 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4096 /* That's all we handle in sparc_legitimize_tls_address for now. */
4100 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4101 this (thread-local) address. */
4104 sparc_legitimize_tls_address (rtx addr
)
4106 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4109 gcc_assert (can_create_pseudo_p ());
4111 if (GET_CODE (addr
) == SYMBOL_REF
)
4112 switch (SYMBOL_REF_TLS_MODEL (addr
))
4114 case TLS_MODEL_GLOBAL_DYNAMIC
:
4116 temp1
= gen_reg_rtx (SImode
);
4117 temp2
= gen_reg_rtx (SImode
);
4118 ret
= gen_reg_rtx (Pmode
);
4119 o0
= gen_rtx_REG (Pmode
, 8);
4120 got
= sparc_tls_got ();
4121 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4122 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4125 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4126 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4131 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4132 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4135 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4136 insn
= get_insns ();
4138 emit_libcall_block (insn
, ret
, o0
, addr
);
4141 case TLS_MODEL_LOCAL_DYNAMIC
:
4143 temp1
= gen_reg_rtx (SImode
);
4144 temp2
= gen_reg_rtx (SImode
);
4145 temp3
= gen_reg_rtx (Pmode
);
4146 ret
= gen_reg_rtx (Pmode
);
4147 o0
= gen_rtx_REG (Pmode
, 8);
4148 got
= sparc_tls_got ();
4149 emit_insn (gen_tldm_hi22 (temp1
));
4150 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4153 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4154 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4159 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4160 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4163 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4164 insn
= get_insns ();
4166 emit_libcall_block (insn
, temp3
, o0
,
4167 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4168 UNSPEC_TLSLD_BASE
));
4169 temp1
= gen_reg_rtx (SImode
);
4170 temp2
= gen_reg_rtx (SImode
);
4171 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4172 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4174 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4176 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4179 case TLS_MODEL_INITIAL_EXEC
:
4180 temp1
= gen_reg_rtx (SImode
);
4181 temp2
= gen_reg_rtx (SImode
);
4182 temp3
= gen_reg_rtx (Pmode
);
4183 got
= sparc_tls_got ();
4184 emit_insn (gen_tie_hi22 (temp1
, addr
));
4185 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4187 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4189 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4192 ret
= gen_reg_rtx (Pmode
);
4194 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4197 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4201 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4204 case TLS_MODEL_LOCAL_EXEC
:
4205 temp1
= gen_reg_rtx (Pmode
);
4206 temp2
= gen_reg_rtx (Pmode
);
4209 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4210 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4214 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4215 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4217 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4224 else if (GET_CODE (addr
) == CONST
)
4228 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4230 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4231 offset
= XEXP (XEXP (addr
, 0), 1);
4233 base
= force_operand (base
, NULL_RTX
);
4234 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4235 offset
= force_reg (Pmode
, offset
);
4236 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4240 gcc_unreachable (); /* for now ... */
4245 /* Legitimize PIC addresses. If the address is already position-independent,
4246 we return ORIG. Newly generated position-independent addresses go into a
4247 reg. This is REG if nonzero, otherwise we allocate register(s) as
4251 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4253 bool gotdata_op
= false;
4255 if (GET_CODE (orig
) == SYMBOL_REF
4256 /* See the comment in sparc_expand_move. */
4257 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4259 rtx pic_ref
, address
;
4264 gcc_assert (can_create_pseudo_p ());
4265 reg
= gen_reg_rtx (Pmode
);
4270 /* If not during reload, allocate another temp reg here for loading
4271 in the address, so that these instructions can be optimized
4273 rtx temp_reg
= (! can_create_pseudo_p ()
4274 ? reg
: gen_reg_rtx (Pmode
));
4276 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4277 won't get confused into thinking that these two instructions
4278 are loading in the true address of the symbol. If in the
4279 future a PIC rtx exists, that should be used instead. */
4282 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4283 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4287 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4288 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4296 crtl
->uses_pic_offset_table
= 1;
4300 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4301 pic_offset_table_rtx
,
4304 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4305 pic_offset_table_rtx
,
4311 = gen_const_mem (Pmode
,
4312 gen_rtx_PLUS (Pmode
,
4313 pic_offset_table_rtx
, address
));
4314 insn
= emit_move_insn (reg
, pic_ref
);
4317 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4319 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4322 else if (GET_CODE (orig
) == CONST
)
4326 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4327 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
4332 gcc_assert (can_create_pseudo_p ());
4333 reg
= gen_reg_rtx (Pmode
);
4336 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4337 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4338 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4339 base
== reg
? NULL_RTX
: reg
);
4341 if (GET_CODE (offset
) == CONST_INT
)
4343 if (SMALL_INT (offset
))
4344 return plus_constant (Pmode
, base
, INTVAL (offset
));
4345 else if (can_create_pseudo_p ())
4346 offset
= force_reg (Pmode
, offset
);
4348 /* If we reach here, then something is seriously wrong. */
4351 return gen_rtx_PLUS (Pmode
, base
, offset
);
4353 else if (GET_CODE (orig
) == LABEL_REF
)
4354 /* ??? We ought to be checking that the register is live instead, in case
4355 it is eliminated. */
4356 crtl
->uses_pic_offset_table
= 1;
4361 /* Try machine-dependent ways of modifying an illegitimate address X
4362 to be legitimate. If we find one, return the new, valid address.
4364 OLDX is the address as it was before break_out_memory_refs was called.
4365 In some cases it is useful to look at this to decide what needs to be done.
4367 MODE is the mode of the operand pointed to by X.
4369 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4372 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4373 enum machine_mode mode
)
4377 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4378 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4379 force_operand (XEXP (x
, 0), NULL_RTX
));
4380 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4381 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4382 force_operand (XEXP (x
, 1), NULL_RTX
));
4383 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4384 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4386 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4387 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4388 force_operand (XEXP (x
, 1), NULL_RTX
));
4390 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4393 if (sparc_tls_referenced_p (x
))
4394 x
= sparc_legitimize_tls_address (x
);
4396 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4397 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4398 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4399 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4400 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4401 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4402 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4403 else if (GET_CODE (x
) == SYMBOL_REF
4404 || GET_CODE (x
) == CONST
4405 || GET_CODE (x
) == LABEL_REF
)
4406 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4411 /* Delegitimize an address that was legitimized by the above function. */
4414 sparc_delegitimize_address (rtx x
)
4416 x
= delegitimize_mem_from_attrs (x
);
4418 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4419 switch (XINT (XEXP (x
, 1), 1))
4421 case UNSPEC_MOVE_PIC
:
4423 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4424 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4430 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4431 if (GET_CODE (x
) == MINUS
4432 && REG_P (XEXP (x
, 0))
4433 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4434 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4435 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4436 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4438 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4439 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4445 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4446 replace the input X, or the original X if no replacement is called for.
4447 The output parameter *WIN is 1 if the calling macro should goto WIN,
4450 For SPARC, we wish to handle addresses by splitting them into
4451 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4452 This cuts the number of extra insns by one.
4454 Do nothing when generating PIC code and the address is a symbolic
4455 operand or requires a scratch register. */
4458 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
4459 int opnum
, int type
,
4460 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4462 /* Decompose SImode constants into HIGH+LO_SUM. */
4464 && (mode
!= TFmode
|| TARGET_ARCH64
)
4465 && GET_MODE (x
) == SImode
4466 && GET_CODE (x
) != LO_SUM
4467 && GET_CODE (x
) != HIGH
4468 && sparc_cmodel
<= CM_MEDLOW
4470 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4472 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4473 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4474 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4475 opnum
, (enum reload_type
)type
);
4480 /* We have to recognize what we have already generated above. */
4481 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4483 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4484 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4485 opnum
, (enum reload_type
)type
);
4494 /* Return true if ADDR (a legitimate address expression)
4495 has an effect that depends on the machine mode it is used for.
4501 is not equivalent to
4503 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4505 because [%l7+a+1] is interpreted as the address of (a+1). */
4509 sparc_mode_dependent_address_p (const_rtx addr
,
4510 addr_space_t as ATTRIBUTE_UNUSED
)
4512 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4514 rtx op0
= XEXP (addr
, 0);
4515 rtx op1
= XEXP (addr
, 1);
4516 if (op0
== pic_offset_table_rtx
4517 && symbolic_operand (op1
, VOIDmode
))
4524 #ifdef HAVE_GAS_HIDDEN
4525 # define USE_HIDDEN_LINKONCE 1
4527 # define USE_HIDDEN_LINKONCE 0
4531 get_pc_thunk_name (char name
[32], unsigned int regno
)
4533 const char *reg_name
= reg_names
[regno
];
4535 /* Skip the leading '%' as that cannot be used in a
4539 if (USE_HIDDEN_LINKONCE
)
4540 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4542 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4545 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4548 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
4550 int orig_flag_pic
= flag_pic
;
4553 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4556 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
4558 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
4559 flag_pic
= orig_flag_pic
;
4564 /* Emit code to load the GOT register. */
4567 load_got_register (void)
4569 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4570 if (!global_offset_table_rtx
)
4571 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4573 if (TARGET_VXWORKS_RTP
)
4574 emit_insn (gen_vxworks_load_got ());
4577 /* The GOT symbol is subject to a PC-relative relocation so we need a
4578 helper function to add the PC value and thus get the final value. */
4579 if (!got_helper_rtx
)
4582 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4583 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4586 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4588 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4591 /* Need to emit this whether or not we obey regdecls,
4592 since setjmp/longjmp can cause life info to screw up.
4593 ??? In the case where we don't obey regdecls, this is not sufficient
4594 since we may not fall out the bottom. */
4595 emit_use (global_offset_table_rtx
);
4598 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4599 address of the call target. */
4602 sparc_emit_call_insn (rtx pat
, rtx addr
)
4606 insn
= emit_call_insn (pat
);
4608 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4609 if (TARGET_VXWORKS_RTP
4611 && GET_CODE (addr
) == SYMBOL_REF
4612 && (SYMBOL_REF_DECL (addr
)
4613 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4614 : !SYMBOL_REF_LOCAL_P (addr
)))
4616 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4617 crtl
->uses_pic_offset_table
= 1;
4621 /* Return 1 if RTX is a MEM which is known to be aligned to at
4622 least a DESIRED byte boundary. */
4625 mem_min_alignment (rtx mem
, int desired
)
4627 rtx addr
, base
, offset
;
4629 /* If it's not a MEM we can't accept it. */
4630 if (GET_CODE (mem
) != MEM
)
4634 if (!TARGET_UNALIGNED_DOUBLES
4635 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4638 /* ??? The rest of the function predates MEM_ALIGN so
4639 there is probably a bit of redundancy. */
4640 addr
= XEXP (mem
, 0);
4641 base
= offset
= NULL_RTX
;
4642 if (GET_CODE (addr
) == PLUS
)
4644 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4646 base
= XEXP (addr
, 0);
4648 /* What we are saying here is that if the base
4649 REG is aligned properly, the compiler will make
4650 sure any REG based index upon it will be so
4652 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4653 offset
= XEXP (addr
, 1);
4655 offset
= const0_rtx
;
4658 else if (GET_CODE (addr
) == REG
)
4661 offset
= const0_rtx
;
4664 if (base
!= NULL_RTX
)
4666 int regno
= REGNO (base
);
4668 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4670 /* Check if the compiler has recorded some information
4671 about the alignment of the base REG. If reload has
4672 completed, we already matched with proper alignments.
4673 If not running global_alloc, reload might give us
4674 unaligned pointer to local stack though. */
4676 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4677 || (optimize
&& reload_completed
))
4678 && (INTVAL (offset
) & (desired
- 1)) == 0)
4683 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4687 else if (! TARGET_UNALIGNED_DOUBLES
4688 || CONSTANT_P (addr
)
4689 || GET_CODE (addr
) == LO_SUM
)
4691 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4692 is true, in which case we can only assume that an access is aligned if
4693 it is to a constant address, or the address involves a LO_SUM. */
4697 /* An obviously unaligned address. */
4702 /* Vectors to keep interesting information about registers where it can easily
4703 be got. We used to use the actual mode value as the bit number, but there
4704 are more than 32 modes now. Instead we use two tables: one indexed by
4705 hard register number, and one indexed by mode. */
4707 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4708 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4709 mapped into one sparc_mode_class mode. */
4711 enum sparc_mode_class
{
4712 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4713 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4717 /* Modes for single-word and smaller quantities. */
4719 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4721 /* Modes for double-word and smaller quantities. */
4722 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4724 /* Modes for quad-word and smaller quantities. */
4725 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4727 /* Modes for 8-word and smaller quantities. */
4728 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4730 /* Modes for single-float quantities. */
4731 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4733 /* Modes for double-float and smaller quantities. */
4734 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4736 /* Modes for quad-float and smaller quantities. */
4737 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4739 /* Modes for quad-float pairs and smaller quantities. */
4740 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4742 /* Modes for double-float only quantities. */
4743 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4745 /* Modes for quad-float and double-float only quantities. */
4746 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4748 /* Modes for quad-float pairs and double-float only quantities. */
4749 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4751 /* Modes for condition codes. */
4752 #define CC_MODES (1 << (int) CC_MODE)
4753 #define CCFP_MODES (1 << (int) CCFP_MODE)
4755 /* Value is 1 if register/mode pair is acceptable on sparc.
4756 The funny mixture of D and T modes is because integer operations
4757 do not specially operate on tetra quantities, so non-quad-aligned
4758 registers can hold quadword quantities (except %o4 and %i4 because
4759 they cross fixed registers). */
4761 /* This points to either the 32 bit or the 64 bit version. */
4762 const int *hard_regno_mode_classes
;
4764 static const int hard_32bit_mode_classes
[] = {
4765 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4766 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4767 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4768 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4770 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4771 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4772 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4773 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4775 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4776 and none can hold SFmode/SImode values. */
4777 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4778 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4779 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4780 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4783 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4785 /* %icc, %sfp, %gsr */
4786 CC_MODES
, 0, D_MODES
4789 static const int hard_64bit_mode_classes
[] = {
4790 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4791 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4792 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4793 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4795 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4796 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4797 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4798 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4800 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4801 and none can hold SFmode/SImode values. */
4802 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4803 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4804 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4805 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4808 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4810 /* %icc, %sfp, %gsr */
4811 CC_MODES
, 0, D_MODES
4814 int sparc_mode_class
[NUM_MACHINE_MODES
];
4816 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4819 sparc_init_modes (void)
4823 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4825 enum machine_mode m
= (enum machine_mode
) i
;
4826 unsigned int size
= GET_MODE_SIZE (m
);
4828 switch (GET_MODE_CLASS (m
))
4831 case MODE_PARTIAL_INT
:
4832 case MODE_COMPLEX_INT
:
4834 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
4836 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4838 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4839 else if (size
== 16)
4840 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4841 else if (size
== 32)
4842 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4844 sparc_mode_class
[i
] = 0;
4846 case MODE_VECTOR_INT
:
4848 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4850 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4852 sparc_mode_class
[i
] = 0;
4855 case MODE_COMPLEX_FLOAT
:
4857 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4859 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4860 else if (size
== 16)
4861 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4862 else if (size
== 32)
4863 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4865 sparc_mode_class
[i
] = 0;
4868 if (m
== CCFPmode
|| m
== CCFPEmode
)
4869 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4871 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4874 sparc_mode_class
[i
] = 0;
4880 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4882 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4884 /* Initialize the array used by REGNO_REG_CLASS. */
4885 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4887 if (i
< 16 && TARGET_V8PLUS
)
4888 sparc_regno_reg_class
[i
] = I64_REGS
;
4889 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4890 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4892 sparc_regno_reg_class
[i
] = FP_REGS
;
4894 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4896 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4898 sparc_regno_reg_class
[i
] = NO_REGS
;
4902 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4905 save_global_or_fp_reg_p (unsigned int regno
,
4906 int leaf_function ATTRIBUTE_UNUSED
)
4908 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4911 /* Return whether the return address register (%i7) is needed. */
4914 return_addr_reg_needed_p (int leaf_function
)
4916 /* If it is live, for example because of __builtin_return_address (0). */
4917 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4920 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4922 /* Loading the GOT register clobbers %o7. */
4923 || crtl
->uses_pic_offset_table
4924 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4930 /* Return whether REGNO, a local or in register, must be saved/restored. */
4933 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4935 /* General case: call-saved registers live at some point. */
4936 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4939 /* Frame pointer register (%fp) if needed. */
4940 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4943 /* Return address register (%i7) if needed. */
4944 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4947 /* GOT register (%l7) if needed. */
4948 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4951 /* If the function accesses prior frames, the frame pointer and the return
4952 address of the previous frame must be saved on the stack. */
4953 if (crtl
->accesses_prior_frames
4954 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4960 /* Compute the frame size required by the function. This function is called
4961 during the reload pass and also by sparc_expand_prologue. */
4964 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4966 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4967 int args_size
, n_global_fp_regs
= 0;
4968 bool save_local_in_regs_p
= false;
4971 /* If the function allocates dynamic stack space, the dynamic offset is
4972 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4973 if (leaf_function
&& !cfun
->calls_alloca
)
4976 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4978 /* Calculate space needed for global registers. */
4980 for (i
= 0; i
< 8; i
++)
4981 if (save_global_or_fp_reg_p (i
, 0))
4982 n_global_fp_regs
+= 2;
4984 for (i
= 0; i
< 8; i
+= 2)
4985 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4986 n_global_fp_regs
+= 2;
4988 /* In the flat window model, find out which local and in registers need to
4989 be saved. We don't reserve space in the current frame for them as they
4990 will be spilled into the register window save area of the caller's frame.
4991 However, as soon as we use this register window save area, we must create
4992 that of the current frame to make it the live one. */
4994 for (i
= 16; i
< 32; i
++)
4995 if (save_local_or_in_reg_p (i
, leaf_function
))
4997 save_local_in_regs_p
= true;
5001 /* Calculate space needed for FP registers. */
5002 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5003 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5004 n_global_fp_regs
+= 2;
5007 && n_global_fp_regs
== 0
5009 && !save_local_in_regs_p
)
5010 frame_size
= apparent_frame_size
= 0;
5013 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
5014 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
5015 apparent_frame_size
+= n_global_fp_regs
* 4;
5017 /* We need to add the size of the outgoing argument area. */
5018 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
5020 /* And that of the register window save area. */
5021 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5023 /* Finally, bump to the appropriate alignment. */
5024 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5027 /* Set up values for use in prologue and epilogue. */
5028 sparc_frame_size
= frame_size
;
5029 sparc_apparent_frame_size
= apparent_frame_size
;
5030 sparc_n_global_fp_regs
= n_global_fp_regs
;
5031 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5036 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5039 sparc_initial_elimination_offset (int to
)
5043 if (to
== STACK_POINTER_REGNUM
)
5044 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5048 offset
+= SPARC_STACK_BIAS
;
5052 /* Output any necessary .register pseudo-ops. */
5055 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5057 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5063 /* Check if %g[2367] were used without
5064 .register being printed for them already. */
5065 for (i
= 2; i
< 8; i
++)
5067 if (df_regs_ever_live_p (i
)
5068 && ! sparc_hard_reg_printed
[i
])
5070 sparc_hard_reg_printed
[i
] = 1;
5071 /* %g7 is used as TLS base register, use #ignore
5072 for it instead of #scratch. */
5073 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5074 i
== 7 ? "ignore" : "scratch");
5081 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5083 #if PROBE_INTERVAL > 4096
5084 #error Cannot use indexed addressing mode for stack probing
5087 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5088 inclusive. These are offsets from the current stack pointer.
5090 Note that we don't use the REG+REG addressing mode for the probes because
5091 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5092 so the advantages of having a single code win here. */
5095 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5097 rtx g1
= gen_rtx_REG (Pmode
, 1);
5099 /* See if we have a constant small number of probes to generate. If so,
5100 that's the easy case. */
5101 if (size
<= PROBE_INTERVAL
)
5103 emit_move_insn (g1
, GEN_INT (first
));
5104 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5105 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5106 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5109 /* The run-time loop is made up of 10 insns in the generic case while the
5110 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5111 else if (size
<= 5 * PROBE_INTERVAL
)
5115 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5116 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5117 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5118 emit_stack_probe (g1
);
5120 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5121 it exceeds SIZE. If only two probes are needed, this will not
5122 generate any code. Then probe at FIRST + SIZE. */
5123 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5125 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5126 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5127 emit_stack_probe (g1
);
5130 emit_stack_probe (plus_constant (Pmode
, g1
,
5131 (i
- PROBE_INTERVAL
) - size
));
5134 /* Otherwise, do the same as above, but in a loop. Note that we must be
5135 extra careful with variables wrapping around because we might be at
5136 the very top (or the very bottom) of the address space and we have
5137 to be able to handle this case properly; in particular, we use an
5138 equality test for the loop condition. */
5141 HOST_WIDE_INT rounded_size
;
5142 rtx g4
= gen_rtx_REG (Pmode
, 4);
5144 emit_move_insn (g1
, GEN_INT (first
));
5147 /* Step 1: round SIZE to the previous multiple of the interval. */
5149 rounded_size
= size
& -PROBE_INTERVAL
;
5150 emit_move_insn (g4
, GEN_INT (rounded_size
));
5153 /* Step 2: compute initial and final value of the loop counter. */
5155 /* TEST_ADDR = SP + FIRST. */
5156 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5157 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5159 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5160 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5165 while (TEST_ADDR != LAST_ADDR)
5167 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5171 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5172 until it is equal to ROUNDED_SIZE. */
5175 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5177 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5180 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5181 that SIZE is equal to ROUNDED_SIZE. */
5183 if (size
!= rounded_size
)
5184 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5187 /* Make sure nothing is scheduled before we are done. */
5188 emit_insn (gen_blockage ());
5191 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5192 absolute addresses. */
5195 output_probe_stack_range (rtx reg1
, rtx reg2
)
5197 static int labelno
= 0;
5198 char loop_lab
[32], end_lab
[32];
5201 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
5202 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
5204 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5206 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
5209 output_asm_insn ("cmp\t%0, %1", xops
);
5211 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
5213 fputs ("\tbe\t", asm_out_file
);
5214 assemble_name_raw (asm_out_file
, end_lab
);
5215 fputc ('\n', asm_out_file
);
5217 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5218 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5219 output_asm_insn (" add\t%0, %1, %0", xops
);
5221 /* Probe at TEST_ADDR and branch. */
5223 fputs ("\tba,pt\t%xcc,", asm_out_file
);
5225 fputs ("\tba\t", asm_out_file
);
5226 assemble_name_raw (asm_out_file
, loop_lab
);
5227 fputc ('\n', asm_out_file
);
5228 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5229 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5231 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
5236 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5237 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5238 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5239 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5240 the action to be performed if it returns false. Return the new offset. */
5242 typedef bool (*sorr_pred_t
) (unsigned int, int);
5243 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5246 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5247 int offset
, int leaf_function
, sorr_pred_t save_p
,
5248 sorr_act_t action_true
, sorr_act_t action_false
)
5254 if (TARGET_ARCH64
&& high
<= 32)
5258 for (i
= low
; i
< high
; i
++)
5260 if (save_p (i
, leaf_function
))
5262 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5264 if (action_true
== SORR_SAVE
)
5266 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5267 RTX_FRAME_RELATED_P (insn
) = 1;
5269 else /* action_true == SORR_RESTORE */
5271 /* The frame pointer must be restored last since its old
5272 value may be used as base address for the frame. This
5273 is problematic in 64-bit mode only because of the lack
5274 of double-word load instruction. */
5275 if (i
== HARD_FRAME_POINTER_REGNUM
)
5278 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5282 else if (action_false
== SORR_ADVANCE
)
5288 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5289 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5294 for (i
= low
; i
< high
; i
+= 2)
5296 bool reg0
= save_p (i
, leaf_function
);
5297 bool reg1
= save_p (i
+ 1, leaf_function
);
5298 enum machine_mode mode
;
5303 mode
= SPARC_INT_REG_P (i
) ? DImode
: DFmode
;
5308 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5313 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5319 if (action_false
== SORR_ADVANCE
)
5324 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5325 if (action_true
== SORR_SAVE
)
5327 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5328 RTX_FRAME_RELATED_P (insn
) = 1;
5332 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5334 set1
= gen_rtx_SET (VOIDmode
, mem
,
5335 gen_rtx_REG (SImode
, regno
));
5336 RTX_FRAME_RELATED_P (set1
) = 1;
5338 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5340 set2
= gen_rtx_SET (VOIDmode
, mem
,
5341 gen_rtx_REG (SImode
, regno
+ 1));
5342 RTX_FRAME_RELATED_P (set2
) = 1;
5343 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5344 gen_rtx_PARALLEL (VOIDmode
,
5345 gen_rtvec (2, set1
, set2
)));
5348 else /* action_true == SORR_RESTORE */
5349 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5351 /* Always preserve double-word alignment. */
5352 offset
= (offset
+ 8) & -8;
5359 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5362 emit_adjust_base_to_offset (rtx base
, int offset
)
5364 /* ??? This might be optimized a little as %g1 might already have a
5365 value close enough that a single add insn will do. */
5366 /* ??? Although, all of this is probably only a temporary fix because
5367 if %g1 can hold a function result, then sparc_expand_epilogue will
5368 lose (the result will be clobbered). */
5369 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5370 emit_move_insn (new_base
, GEN_INT (offset
));
5371 emit_insn (gen_rtx_SET (VOIDmode
,
5372 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5376 /* Emit code to save/restore call-saved global and FP registers. */
5379 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5381 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5383 base
= emit_adjust_base_to_offset (base
, offset
);
5388 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5389 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5390 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5391 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5394 /* Emit code to save/restore call-saved local and in registers. */
5397 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5399 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5401 base
= emit_adjust_base_to_offset (base
, offset
);
5405 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5406 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5409 /* Emit a window_save insn. */
5412 emit_window_save (rtx increment
)
5414 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5415 RTX_FRAME_RELATED_P (insn
) = 1;
5417 /* The incoming return address (%o7) is saved in %i7. */
5418 add_reg_note (insn
, REG_CFA_REGISTER
,
5419 gen_rtx_SET (VOIDmode
,
5420 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5422 INCOMING_RETURN_ADDR_REGNUM
)));
5424 /* The window save event. */
5425 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5427 /* The CFA is %fp, the hard frame pointer. */
5428 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5429 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5430 INCOMING_FRAME_SP_OFFSET
));
5435 /* Generate an increment for the stack pointer. */
5438 gen_stack_pointer_inc (rtx increment
)
5440 return gen_rtx_SET (VOIDmode
,
5442 gen_rtx_PLUS (Pmode
,
5447 /* Expand the function prologue. The prologue is responsible for reserving
5448 storage for the frame, saving the call-saved registers and loading the
5449 GOT register if needed. */
5452 sparc_expand_prologue (void)
5457 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5458 on the final value of the flag means deferring the prologue/epilogue
5459 expansion until just before the second scheduling pass, which is too
5460 late to emit multiple epilogues or return insns.
5462 Of course we are making the assumption that the value of the flag
5463 will not change between now and its final value. Of the three parts
5464 of the formula, only the last one can reasonably vary. Let's take a
5465 closer look, after assuming that the first two ones are set to true
5466 (otherwise the last value is effectively silenced).
5468 If only_leaf_regs_used returns false, the global predicate will also
5469 be false so the actual frame size calculated below will be positive.
5470 As a consequence, the save_register_window insn will be emitted in
5471 the instruction stream; now this insn explicitly references %fp
5472 which is not a leaf register so only_leaf_regs_used will always
5473 return false subsequently.
5475 If only_leaf_regs_used returns true, we hope that the subsequent
5476 optimization passes won't cause non-leaf registers to pop up. For
5477 example, the regrename pass has special provisions to not rename to
5478 non-leaf registers in a leaf function. */
5479 sparc_leaf_function_p
5480 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5482 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5484 if (flag_stack_usage_info
)
5485 current_function_static_stack_size
= size
;
5487 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5489 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5491 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5492 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5493 size
- STACK_CHECK_PROTECT
);
5496 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5501 else if (sparc_leaf_function_p
)
5503 rtx size_int_rtx
= GEN_INT (-size
);
5506 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5507 else if (size
<= 8192)
5509 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5510 RTX_FRAME_RELATED_P (insn
) = 1;
5512 /* %sp is still the CFA register. */
5513 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5517 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5518 emit_move_insn (size_rtx
, size_int_rtx
);
5519 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5520 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5521 gen_stack_pointer_inc (size_int_rtx
));
5524 RTX_FRAME_RELATED_P (insn
) = 1;
5528 rtx size_int_rtx
= GEN_INT (-size
);
5531 emit_window_save (size_int_rtx
);
5532 else if (size
<= 8192)
5534 emit_window_save (GEN_INT (-4096));
5536 /* %sp is not the CFA register anymore. */
5537 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5539 /* Make sure no %fp-based store is issued until after the frame is
5540 established. The offset between the frame pointer and the stack
5541 pointer is calculated relative to the value of the stack pointer
5542 at the end of the function prologue, and moving instructions that
5543 access the stack via the frame pointer between the instructions
5544 that decrement the stack pointer could result in accessing the
5545 register window save area, which is volatile. */
5546 emit_insn (gen_frame_blockage ());
5550 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5551 emit_move_insn (size_rtx
, size_int_rtx
);
5552 emit_window_save (size_rtx
);
5556 if (sparc_leaf_function_p
)
5558 sparc_frame_base_reg
= stack_pointer_rtx
;
5559 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5563 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5564 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5567 if (sparc_n_global_fp_regs
> 0)
5568 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5569 sparc_frame_base_offset
5570 - sparc_apparent_frame_size
,
5573 /* Load the GOT register if needed. */
5574 if (crtl
->uses_pic_offset_table
)
5575 load_got_register ();
5577 /* Advertise that the data calculated just above are now valid. */
5578 sparc_prologue_data_valid_p
= true;
5581 /* Expand the function prologue. The prologue is responsible for reserving
5582 storage for the frame, saving the call-saved registers and loading the
5583 GOT register if needed. */
5586 sparc_flat_expand_prologue (void)
5591 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
5593 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5595 if (flag_stack_usage_info
)
5596 current_function_static_stack_size
= size
;
5598 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5600 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5602 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5603 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5604 size
- STACK_CHECK_PROTECT
);
5607 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5610 if (sparc_save_local_in_regs_p
)
5611 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
5618 rtx size_int_rtx
, size_rtx
;
5620 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5622 /* We establish the frame (i.e. decrement the stack pointer) first, even
5623 if we use a frame pointer, because we cannot clobber any call-saved
5624 registers, including the frame pointer, if we haven't created a new
5625 register save area, for the sake of compatibility with the ABI. */
5627 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5628 else if (size
<= 8192 && !frame_pointer_needed
)
5630 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5631 RTX_FRAME_RELATED_P (insn
) = 1;
5632 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5636 size_rtx
= gen_rtx_REG (Pmode
, 1);
5637 emit_move_insn (size_rtx
, size_int_rtx
);
5638 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5639 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5640 gen_stack_pointer_inc (size_int_rtx
));
5642 RTX_FRAME_RELATED_P (insn
) = 1;
5644 /* Ensure nothing is scheduled until after the frame is established. */
5645 emit_insn (gen_blockage ());
5647 if (frame_pointer_needed
)
5649 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5650 gen_rtx_MINUS (Pmode
,
5653 RTX_FRAME_RELATED_P (insn
) = 1;
5655 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5656 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5657 plus_constant (Pmode
, stack_pointer_rtx
,
5661 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5663 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5664 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5666 insn
= emit_move_insn (i7
, o7
);
5667 RTX_FRAME_RELATED_P (insn
) = 1;
5669 add_reg_note (insn
, REG_CFA_REGISTER
,
5670 gen_rtx_SET (VOIDmode
, i7
, o7
));
5672 /* Prevent this instruction from ever being considered dead,
5673 even if this function has no epilogue. */
5678 if (frame_pointer_needed
)
5680 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5681 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5685 sparc_frame_base_reg
= stack_pointer_rtx
;
5686 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5689 if (sparc_n_global_fp_regs
> 0)
5690 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5691 sparc_frame_base_offset
5692 - sparc_apparent_frame_size
,
5695 /* Load the GOT register if needed. */
5696 if (crtl
->uses_pic_offset_table
)
5697 load_got_register ();
5699 /* Advertise that the data calculated just above are now valid. */
5700 sparc_prologue_data_valid_p
= true;
5703 /* This function generates the assembly code for function entry, which boils
5704 down to emitting the necessary .register directives. */
5707 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5709 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5711 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
5713 sparc_output_scratch_registers (file
);
5716 /* Expand the function epilogue, either normal or part of a sibcall.
5717 We emit all the instructions except the return or the call. */
5720 sparc_expand_epilogue (bool for_eh
)
5722 HOST_WIDE_INT size
= sparc_frame_size
;
5724 if (sparc_n_global_fp_regs
> 0)
5725 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5726 sparc_frame_base_offset
5727 - sparc_apparent_frame_size
,
5730 if (size
== 0 || for_eh
)
5732 else if (sparc_leaf_function_p
)
5735 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5736 else if (size
<= 8192)
5738 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5739 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5743 rtx reg
= gen_rtx_REG (Pmode
, 1);
5744 emit_move_insn (reg
, GEN_INT (size
));
5745 emit_insn (gen_stack_pointer_inc (reg
));
5750 /* Expand the function epilogue, either normal or part of a sibcall.
5751 We emit all the instructions except the return or the call. */
5754 sparc_flat_expand_epilogue (bool for_eh
)
5756 HOST_WIDE_INT size
= sparc_frame_size
;
5758 if (sparc_n_global_fp_regs
> 0)
5759 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5760 sparc_frame_base_offset
5761 - sparc_apparent_frame_size
,
5764 /* If we have a frame pointer, we'll need both to restore it before the
5765 frame is destroyed and use its current value in destroying the frame.
5766 Since we don't have an atomic way to do that in the flat window model,
5767 we save the current value into a temporary register (%g1). */
5768 if (frame_pointer_needed
&& !for_eh
)
5769 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5771 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5772 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5773 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5775 if (sparc_save_local_in_regs_p
)
5776 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5777 sparc_frame_base_offset
,
5780 if (size
== 0 || for_eh
)
5782 else if (frame_pointer_needed
)
5784 /* Make sure the frame is destroyed after everything else is done. */
5785 emit_insn (gen_blockage ());
5787 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5792 emit_insn (gen_blockage ());
5795 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5796 else if (size
<= 8192)
5798 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5799 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5803 rtx reg
= gen_rtx_REG (Pmode
, 1);
5804 emit_move_insn (reg
, GEN_INT (size
));
5805 emit_insn (gen_stack_pointer_inc (reg
));
5810 /* Return true if it is appropriate to emit `return' instructions in the
5811 body of a function. */
5814 sparc_can_use_return_insn_p (void)
5816 return sparc_prologue_data_valid_p
5817 && sparc_n_global_fp_regs
== 0
5819 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5820 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5823 /* This function generates the assembly code for function exit. */
5826 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5828 /* If the last two instructions of a function are "call foo; dslot;"
5829 the return address might point to the first instruction in the next
5830 function and we have to output a dummy nop for the sake of sane
5831 backtraces in such cases. This is pointless for sibling calls since
5832 the return address is explicitly adjusted. */
5834 rtx insn
, last_real_insn
;
5836 insn
= get_last_insn ();
5838 last_real_insn
= prev_real_insn (insn
);
5840 && NONJUMP_INSN_P (last_real_insn
)
5841 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5842 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5845 && CALL_P (last_real_insn
)
5846 && !SIBLING_CALL_P (last_real_insn
))
5847 fputs("\tnop\n", file
);
5849 sparc_output_deferred_case_vectors ();
5852 /* Output a 'restore' instruction. */
5855 output_restore (rtx pat
)
5861 fputs ("\t restore\n", asm_out_file
);
5865 gcc_assert (GET_CODE (pat
) == SET
);
5867 operands
[0] = SET_DEST (pat
);
5868 pat
= SET_SRC (pat
);
5870 switch (GET_CODE (pat
))
5873 operands
[1] = XEXP (pat
, 0);
5874 operands
[2] = XEXP (pat
, 1);
5875 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5878 operands
[1] = XEXP (pat
, 0);
5879 operands
[2] = XEXP (pat
, 1);
5880 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5883 operands
[1] = XEXP (pat
, 0);
5884 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5885 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5889 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5894 /* Output a return. */
5897 output_return (rtx_insn
*insn
)
5899 if (crtl
->calls_eh_return
)
5901 /* If the function uses __builtin_eh_return, the eh_return
5902 machinery occupies the delay slot. */
5903 gcc_assert (!final_sequence
);
5905 if (flag_delayed_branch
)
5907 if (!TARGET_FLAT
&& TARGET_V9
)
5908 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5912 fputs ("\trestore\n", asm_out_file
);
5914 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5917 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5922 fputs ("\trestore\n", asm_out_file
);
5924 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5925 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5928 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5930 /* This is a leaf or flat function so we don't have to bother restoring
5931 the register window, which frees us from dealing with the convoluted
5932 semantics of restore/return. We simply output the jump to the
5933 return address and the insn in the delay slot (if any). */
5935 return "jmp\t%%o7+%)%#";
5939 /* This is a regular function so we have to restore the register window.
5940 We may have a pending insn for the delay slot, which will be either
5941 combined with the 'restore' instruction or put in the delay slot of
5942 the 'return' instruction. */
5948 delay
= NEXT_INSN (insn
);
5951 pat
= PATTERN (delay
);
5953 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5955 epilogue_renumber (&pat
, 0);
5956 return "return\t%%i7+%)%#";
5960 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5961 output_restore (pat
);
5962 PATTERN (delay
) = gen_blockage ();
5963 INSN_CODE (delay
) = -1;
5968 /* The delay slot is empty. */
5970 return "return\t%%i7+%)\n\t nop";
5971 else if (flag_delayed_branch
)
5972 return "jmp\t%%i7+%)\n\t restore";
5974 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5981 /* Output a sibling call. */
5984 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
5988 gcc_assert (flag_delayed_branch
);
5990 operands
[0] = call_operand
;
5992 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5994 /* This is a leaf or flat function so we don't have to bother restoring
5995 the register window. We simply output the jump to the function and
5996 the insn in the delay slot (if any). */
5998 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6001 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6004 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6005 it into branch if possible. */
6006 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6011 /* This is a regular function so we have to restore the register window.
6012 We may have a pending insn for the delay slot, which will be combined
6013 with the 'restore' instruction. */
6015 output_asm_insn ("call\t%a0, 0", operands
);
6019 rtx_insn
*delay
= NEXT_INSN (insn
);
6022 output_restore (PATTERN (delay
));
6024 PATTERN (delay
) = gen_blockage ();
6025 INSN_CODE (delay
) = -1;
6028 output_restore (NULL_RTX
);
6034 /* Functions for handling argument passing.
6036 For 32-bit, the first 6 args are normally in registers and the rest are
6037 pushed. Any arg that starts within the first 6 words is at least
6038 partially passed in a register unless its data type forbids.
6040 For 64-bit, the argument registers are laid out as an array of 16 elements
6041 and arguments are added sequentially. The first 6 int args and up to the
6042 first 16 fp args (depending on size) are passed in regs.
6044 Slot Stack Integral Float Float in structure Double Long Double
6045 ---- ----- -------- ----- ------------------ ------ -----------
6046 15 [SP+248] %f31 %f30,%f31 %d30
6047 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6048 13 [SP+232] %f27 %f26,%f27 %d26
6049 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6050 11 [SP+216] %f23 %f22,%f23 %d22
6051 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6052 9 [SP+200] %f19 %f18,%f19 %d18
6053 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6054 7 [SP+184] %f15 %f14,%f15 %d14
6055 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6056 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6057 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6058 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6059 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6060 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6061 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6063 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6065 Integral arguments are always passed as 64-bit quantities appropriately
6068 Passing of floating point values is handled as follows.
6069 If a prototype is in scope:
6070 If the value is in a named argument (i.e. not a stdarg function or a
6071 value not part of the `...') then the value is passed in the appropriate
6073 If the value is part of the `...' and is passed in one of the first 6
6074 slots then the value is passed in the appropriate int reg.
6075 If the value is part of the `...' and is not passed in one of the first 6
6076 slots then the value is passed in memory.
6077 If a prototype is not in scope:
6078 If the value is one of the first 6 arguments the value is passed in the
6079 appropriate integer reg and the appropriate fp reg.
6080 If the value is not one of the first 6 arguments the value is passed in
6081 the appropriate fp reg and in memory.
6084 Summary of the calling conventions implemented by GCC on the SPARC:
6087 size argument return value
6089 small integer <4 int. reg. int. reg.
6090 word 4 int. reg. int. reg.
6091 double word 8 int. reg. int. reg.
6093 _Complex small integer <8 int. reg. int. reg.
6094 _Complex word 8 int. reg. int. reg.
6095 _Complex double word 16 memory int. reg.
6097 vector integer <=8 int. reg. FP reg.
6098 vector integer >8 memory memory
6100 float 4 int. reg. FP reg.
6101 double 8 int. reg. FP reg.
6102 long double 16 memory memory
6104 _Complex float 8 memory FP reg.
6105 _Complex double 16 memory FP reg.
6106 _Complex long double 32 memory FP reg.
6108 vector float any memory memory
6110 aggregate any memory memory
6115 size argument return value
6117 small integer <8 int. reg. int. reg.
6118 word 8 int. reg. int. reg.
6119 double word 16 int. reg. int. reg.
6121 _Complex small integer <16 int. reg. int. reg.
6122 _Complex word 16 int. reg. int. reg.
6123 _Complex double word 32 memory int. reg.
6125 vector integer <=16 FP reg. FP reg.
6126 vector integer 16<s<=32 memory FP reg.
6127 vector integer >32 memory memory
6129 float 4 FP reg. FP reg.
6130 double 8 FP reg. FP reg.
6131 long double 16 FP reg. FP reg.
6133 _Complex float 8 FP reg. FP reg.
6134 _Complex double 16 FP reg. FP reg.
6135 _Complex long double 32 memory FP reg.
6137 vector float <=16 FP reg. FP reg.
6138 vector float 16<s<=32 memory FP reg.
6139 vector float >32 memory memory
6141 aggregate <=16 reg. reg.
6142 aggregate 16<s<=32 memory reg.
6143 aggregate >32 memory memory
6147 Note #1: complex floating-point types follow the extended SPARC ABIs as
6148 implemented by the Sun compiler.
6150 Note #2: integral vector types follow the scalar floating-point types
6151 conventions to match what is implemented by the Sun VIS SDK.
6153 Note #3: floating-point vector types follow the aggregate types
6157 /* Maximum number of int regs for args. */
6158 #define SPARC_INT_ARG_MAX 6
6159 /* Maximum number of fp regs for args. */
6160 #define SPARC_FP_ARG_MAX 16
6162 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6164 /* Handle the INIT_CUMULATIVE_ARGS macro.
6165 Initialize a variable CUM of type CUMULATIVE_ARGS
6166 for a call to a function whose data type is FNTYPE.
6167 For a library call, FNTYPE is 0. */
6170 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
6171 rtx libname ATTRIBUTE_UNUSED
,
6172 tree fndecl ATTRIBUTE_UNUSED
)
6175 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6176 cum
->libcall_p
= fntype
== 0;
6179 /* Handle promotion of pointer and integer arguments. */
6181 static enum machine_mode
6182 sparc_promote_function_mode (const_tree type
,
6183 enum machine_mode mode
,
6185 const_tree fntype ATTRIBUTE_UNUSED
,
6186 int for_return ATTRIBUTE_UNUSED
)
6188 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
6190 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6194 /* Integral arguments are passed as full words, as per the ABI. */
6195 if (GET_MODE_CLASS (mode
) == MODE_INT
6196 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6202 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6205 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6207 return TARGET_ARCH64
? true : false;
6210 /* Scan the record type TYPE and return the following predicates:
6211 - INTREGS_P: the record contains at least one field or sub-field
6212 that is eligible for promotion in integer registers.
6213 - FP_REGS_P: the record contains at least one field or sub-field
6214 that is eligible for promotion in floating-point registers.
6215 - PACKED_P: the record contains at least one field that is packed.
6217 Sub-fields are not taken into account for the PACKED_P predicate. */
6220 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
6225 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6227 if (TREE_CODE (field
) == FIELD_DECL
)
6229 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6230 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
6231 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6232 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6238 if (packed_p
&& DECL_PACKED (field
))
6244 /* Compute the slot number to pass an argument in.
6245 Return the slot number or -1 if passing on the stack.
6247 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6248 the preceding args and about the function being called.
6249 MODE is the argument's machine mode.
6250 TYPE is the data type of the argument (as a tree).
6251 This is null for libcalls where that information may
6253 NAMED is nonzero if this argument is a named parameter
6254 (otherwise it is an extra parameter matching an ellipsis).
6255 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6256 *PREGNO records the register number to use if scalar type.
6257 *PPADDING records the amount of padding needed in words. */
6260 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
6261 const_tree type
, bool named
, bool incoming_p
,
6262 int *pregno
, int *ppadding
)
6264 int regbase
= (incoming_p
6265 ? SPARC_INCOMING_INT_ARG_FIRST
6266 : SPARC_OUTGOING_INT_ARG_FIRST
);
6267 int slotno
= cum
->words
;
6268 enum mode_class mclass
;
6273 if (type
&& TREE_ADDRESSABLE (type
))
6279 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
6282 /* For SPARC64, objects requiring 16-byte alignment get it. */
6284 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6285 && (slotno
& 1) != 0)
6286 slotno
++, *ppadding
= 1;
6288 mclass
= GET_MODE_CLASS (mode
);
6289 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6291 /* Vector types deserve special treatment because they are
6292 polymorphic wrt their mode, depending upon whether VIS
6293 instructions are enabled. */
6294 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6296 /* The SPARC port defines no floating-point vector modes. */
6297 gcc_assert (mode
== BLKmode
);
6301 /* Integral vector types should either have a vector
6302 mode or an integral mode, because we are guaranteed
6303 by pass_by_reference that their size is not greater
6304 than 16 bytes and TImode is 16-byte wide. */
6305 gcc_assert (mode
!= BLKmode
);
6307 /* Vector integers are handled like floats according to
6309 mclass
= MODE_FLOAT
;
6316 case MODE_COMPLEX_FLOAT
:
6317 case MODE_VECTOR_INT
:
6318 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6320 if (slotno
>= SPARC_FP_ARG_MAX
)
6322 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6323 /* Arguments filling only one single FP register are
6324 right-justified in the outer double FP register. */
6325 if (GET_MODE_SIZE (mode
) <= 4)
6332 case MODE_COMPLEX_INT
:
6333 if (slotno
>= SPARC_INT_ARG_MAX
)
6335 regno
= regbase
+ slotno
;
6339 if (mode
== VOIDmode
)
6340 /* MODE is VOIDmode when generating the actual call. */
6343 gcc_assert (mode
== BLKmode
);
6347 || (TREE_CODE (type
) != VECTOR_TYPE
6348 && TREE_CODE (type
) != RECORD_TYPE
))
6350 if (slotno
>= SPARC_INT_ARG_MAX
)
6352 regno
= regbase
+ slotno
;
6354 else /* TARGET_ARCH64 && type */
6356 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
6358 /* First see what kinds of registers we would need. */
6359 if (TREE_CODE (type
) == VECTOR_TYPE
)
6362 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
6364 /* The ABI obviously doesn't specify how packed structures
6365 are passed. These are defined to be passed in int regs
6366 if possible, otherwise memory. */
6367 if (packed_p
|| !named
)
6368 fpregs_p
= 0, intregs_p
= 1;
6370 /* If all arg slots are filled, then must pass on stack. */
6371 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
6374 /* If there are only int args and all int arg slots are filled,
6375 then must pass on stack. */
6376 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
6379 /* Note that even if all int arg slots are filled, fp members may
6380 still be passed in regs if such regs are available.
6381 *PREGNO isn't set because there may be more than one, it's up
6382 to the caller to compute them. */
6395 /* Handle recursive register counting for structure field layout. */
6397 struct function_arg_record_value_parms
6399 rtx ret
; /* return expression being built. */
6400 int slotno
; /* slot number of the argument. */
6401 int named
; /* whether the argument is named. */
6402 int regbase
; /* regno of the base register. */
6403 int stack
; /* 1 if part of the argument is on the stack. */
6404 int intoffset
; /* offset of the first pending integer field. */
6405 unsigned int nregs
; /* number of words passed in registers. */
6408 static void function_arg_record_value_3
6409 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
6410 static void function_arg_record_value_2
6411 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
6412 static void function_arg_record_value_1
6413 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
6414 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
6415 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
6417 /* A subroutine of function_arg_record_value. Traverse the structure
6418 recursively and determine how many registers will be required. */
6421 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
6422 struct function_arg_record_value_parms
*parms
,
6427 /* We need to compute how many registers are needed so we can
6428 allocate the PARALLEL but before we can do that we need to know
6429 whether there are any packed fields. The ABI obviously doesn't
6430 specify how structures are passed in this case, so they are
6431 defined to be passed in int regs if possible, otherwise memory,
6432 regardless of whether there are fp values present. */
6435 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
6437 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6444 /* Compute how many registers we need. */
6445 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6447 if (TREE_CODE (field
) == FIELD_DECL
)
6449 HOST_WIDE_INT bitpos
= startbitpos
;
6451 if (DECL_SIZE (field
) != 0)
6453 if (integer_zerop (DECL_SIZE (field
)))
6456 if (tree_fits_uhwi_p (bit_position (field
)))
6457 bitpos
+= int_bit_position (field
);
6460 /* ??? FIXME: else assume zero offset. */
6462 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6463 function_arg_record_value_1 (TREE_TYPE (field
),
6467 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6468 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6473 if (parms
->intoffset
!= -1)
6475 unsigned int startbit
, endbit
;
6476 int intslots
, this_slotno
;
6478 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
6479 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6481 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6482 this_slotno
= parms
->slotno
+ parms
->intoffset
6485 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6487 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6488 /* We need to pass this field on the stack. */
6492 parms
->nregs
+= intslots
;
6493 parms
->intoffset
= -1;
6496 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
6497 If it wasn't true we wouldn't be here. */
6498 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6499 && DECL_MODE (field
) == BLKmode
)
6500 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6501 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6508 if (parms
->intoffset
== -1)
6509 parms
->intoffset
= bitpos
;
6515 /* A subroutine of function_arg_record_value. Assign the bits of the
6516 structure between parms->intoffset and bitpos to integer registers. */
6519 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
6520 struct function_arg_record_value_parms
*parms
)
6522 enum machine_mode mode
;
6524 unsigned int startbit
, endbit
;
6525 int this_slotno
, intslots
, intoffset
;
6528 if (parms
->intoffset
== -1)
6531 intoffset
= parms
->intoffset
;
6532 parms
->intoffset
= -1;
6534 startbit
= intoffset
& -BITS_PER_WORD
;
6535 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6536 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6537 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
6539 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
6543 /* If this is the trailing part of a word, only load that much into
6544 the register. Otherwise load the whole register. Note that in
6545 the latter case we may pick up unwanted bits. It's not a problem
6546 at the moment but may wish to revisit. */
6548 if (intoffset
% BITS_PER_WORD
!= 0)
6549 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
6554 intoffset
/= BITS_PER_UNIT
;
6557 regno
= parms
->regbase
+ this_slotno
;
6558 reg
= gen_rtx_REG (mode
, regno
);
6559 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6560 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6563 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
6568 while (intslots
> 0);
6571 /* A subroutine of function_arg_record_value. Traverse the structure
6572 recursively and assign bits to floating point registers. Track which
6573 bits in between need integer registers; invoke function_arg_record_value_3
6574 to make that happen. */
6577 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
6578 struct function_arg_record_value_parms
*parms
,
6584 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6586 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6593 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6595 if (TREE_CODE (field
) == FIELD_DECL
)
6597 HOST_WIDE_INT bitpos
= startbitpos
;
6599 if (DECL_SIZE (field
) != 0)
6601 if (integer_zerop (DECL_SIZE (field
)))
6604 if (tree_fits_uhwi_p (bit_position (field
)))
6605 bitpos
+= int_bit_position (field
);
6608 /* ??? FIXME: else assume zero offset. */
6610 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6611 function_arg_record_value_2 (TREE_TYPE (field
),
6615 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6616 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6621 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
6622 int regno
, nregs
, pos
;
6623 enum machine_mode mode
= DECL_MODE (field
);
6626 function_arg_record_value_3 (bitpos
, parms
);
6628 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6631 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6632 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6634 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6636 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6642 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6643 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6645 reg
= gen_rtx_REG (mode
, regno
);
6646 pos
= bitpos
/ BITS_PER_UNIT
;
6647 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6648 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6652 regno
+= GET_MODE_SIZE (mode
) / 4;
6653 reg
= gen_rtx_REG (mode
, regno
);
6654 pos
+= GET_MODE_SIZE (mode
);
6655 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6656 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6662 if (parms
->intoffset
== -1)
6663 parms
->intoffset
= bitpos
;
6669 /* Used by function_arg and sparc_function_value_1 to implement the complex
6670 conventions of the 64-bit ABI for passing and returning structures.
6671 Return an expression valid as a return value for the FUNCTION_ARG
6672 and TARGET_FUNCTION_VALUE.
6674 TYPE is the data type of the argument (as a tree).
6675 This is null for libcalls where that information may
6677 MODE is the argument's machine mode.
6678 SLOTNO is the index number of the argument's slot in the parameter array.
6679 NAMED is nonzero if this argument is a named parameter
6680 (otherwise it is an extra parameter matching an ellipsis).
6681 REGBASE is the regno of the base register for the parameter array. */
6684 function_arg_record_value (const_tree type
, enum machine_mode mode
,
6685 int slotno
, int named
, int regbase
)
6687 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6688 struct function_arg_record_value_parms parms
;
6691 parms
.ret
= NULL_RTX
;
6692 parms
.slotno
= slotno
;
6693 parms
.named
= named
;
6694 parms
.regbase
= regbase
;
6697 /* Compute how many registers we need. */
6699 parms
.intoffset
= 0;
6700 function_arg_record_value_1 (type
, 0, &parms
, false);
6702 /* Take into account pending integer fields. */
6703 if (parms
.intoffset
!= -1)
6705 unsigned int startbit
, endbit
;
6706 int intslots
, this_slotno
;
6708 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
6709 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6710 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6711 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
6713 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6715 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6716 /* We need to pass this field on the stack. */
6720 parms
.nregs
+= intslots
;
6722 nregs
= parms
.nregs
;
6724 /* Allocate the vector and handle some annoying special cases. */
6727 /* ??? Empty structure has no value? Duh? */
6730 /* Though there's nothing really to store, return a word register
6731 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6732 leads to breakage due to the fact that there are zero bytes to
6734 return gen_rtx_REG (mode
, regbase
);
6738 /* ??? C++ has structures with no fields, and yet a size. Give up
6739 for now and pass everything back in integer registers. */
6740 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6742 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6743 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6745 gcc_assert (nregs
!= 0);
6747 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
6749 /* If at least one field must be passed on the stack, generate
6750 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6751 also be passed on the stack. We can't do much better because the
6752 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6753 of structures for which the fields passed exclusively in registers
6754 are not at the beginning of the structure. */
6756 XVECEXP (parms
.ret
, 0, 0)
6757 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6759 /* Fill in the entries. */
6761 parms
.intoffset
= 0;
6762 function_arg_record_value_2 (type
, 0, &parms
, false);
6763 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
6765 gcc_assert (parms
.nregs
== nregs
);
6770 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6771 of the 64-bit ABI for passing and returning unions.
6772 Return an expression valid as a return value for the FUNCTION_ARG
6773 and TARGET_FUNCTION_VALUE.
6775 SIZE is the size in bytes of the union.
6776 MODE is the argument's machine mode.
6777 REGNO is the hard register the union will be passed in. */
6780 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
6783 int nwords
= ROUND_ADVANCE (size
), i
;
6786 /* See comment in previous function for empty structures. */
6788 return gen_rtx_REG (mode
, regno
);
6790 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6793 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6795 for (i
= 0; i
< nwords
; i
++)
6797 /* Unions are passed left-justified. */
6798 XVECEXP (regs
, 0, i
)
6799 = gen_rtx_EXPR_LIST (VOIDmode
,
6800 gen_rtx_REG (word_mode
, regno
),
6801 GEN_INT (UNITS_PER_WORD
* i
));
6808 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6809 for passing and returning large (BLKmode) vectors.
6810 Return an expression valid as a return value for the FUNCTION_ARG
6811 and TARGET_FUNCTION_VALUE.
6813 SIZE is the size in bytes of the vector (at least 8 bytes).
6814 REGNO is the FP hard register the vector will be passed in. */
6817 function_arg_vector_value (int size
, int regno
)
6819 int i
, nregs
= size
/ 8;
6822 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6824 for (i
= 0; i
< nregs
; i
++)
6826 XVECEXP (regs
, 0, i
)
6827 = gen_rtx_EXPR_LIST (VOIDmode
,
6828 gen_rtx_REG (DImode
, regno
+ 2*i
),
6835 /* Determine where to put an argument to a function.
6836 Value is zero to push the argument on the stack,
6837 or a hard register in which to store the argument.
6839 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6840 the preceding args and about the function being called.
6841 MODE is the argument's machine mode.
6842 TYPE is the data type of the argument (as a tree).
6843 This is null for libcalls where that information may
6845 NAMED is true if this argument is a named parameter
6846 (otherwise it is an extra parameter matching an ellipsis).
6847 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6848 TARGET_FUNCTION_INCOMING_ARG. */
6851 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6852 const_tree type
, bool named
, bool incoming_p
)
6854 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6856 int regbase
= (incoming_p
6857 ? SPARC_INCOMING_INT_ARG_FIRST
6858 : SPARC_OUTGOING_INT_ARG_FIRST
);
6859 int slotno
, regno
, padding
;
6860 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6862 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6867 /* Vector types deserve special treatment because they are polymorphic wrt
6868 their mode, depending upon whether VIS instructions are enabled. */
6869 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6871 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6872 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6873 || (TARGET_ARCH64
&& size
<= 16));
6875 if (mode
== BLKmode
)
6876 return function_arg_vector_value (size
,
6877 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6879 mclass
= MODE_FLOAT
;
6883 return gen_rtx_REG (mode
, regno
);
6885 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6886 and are promoted to registers if possible. */
6887 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6889 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6890 gcc_assert (size
<= 16);
6892 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6895 /* Unions up to 16 bytes in size are passed in integer registers. */
6896 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6898 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6899 gcc_assert (size
<= 16);
6901 return function_arg_union_value (size
, mode
, slotno
, regno
);
6904 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6905 but also have the slot allocated for them.
6906 If no prototype is in scope fp values in register slots get passed
6907 in two places, either fp regs and int regs or fp regs and memory. */
6908 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6909 && SPARC_FP_REG_P (regno
))
6911 rtx reg
= gen_rtx_REG (mode
, regno
);
6912 if (cum
->prototype_p
|| cum
->libcall_p
)
6914 /* "* 2" because fp reg numbers are recorded in 4 byte
6917 /* ??? This will cause the value to be passed in the fp reg and
6918 in the stack. When a prototype exists we want to pass the
6919 value in the reg but reserve space on the stack. That's an
6920 optimization, and is deferred [for a bit]. */
6921 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6922 return gen_rtx_PARALLEL (mode
,
6924 gen_rtx_EXPR_LIST (VOIDmode
,
6925 NULL_RTX
, const0_rtx
),
6926 gen_rtx_EXPR_LIST (VOIDmode
,
6930 /* ??? It seems that passing back a register even when past
6931 the area declared by REG_PARM_STACK_SPACE will allocate
6932 space appropriately, and will not copy the data onto the
6933 stack, exactly as we desire.
6935 This is due to locate_and_pad_parm being called in
6936 expand_call whenever reg_parm_stack_space > 0, which
6937 while beneficial to our example here, would seem to be
6938 in error from what had been intended. Ho hum... -- r~ */
6946 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6950 /* On incoming, we don't need to know that the value
6951 is passed in %f0 and %i0, and it confuses other parts
6952 causing needless spillage even on the simplest cases. */
6956 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6957 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6959 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6960 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6962 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6966 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6967 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6968 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6973 /* All other aggregate types are passed in an integer register in a mode
6974 corresponding to the size of the type. */
6975 else if (type
&& AGGREGATE_TYPE_P (type
))
6977 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6978 gcc_assert (size
<= 16);
6980 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6983 return gen_rtx_REG (mode
, regno
);
6986 /* Handle the TARGET_FUNCTION_ARG target hook. */
6989 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6990 const_tree type
, bool named
)
6992 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
6995 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
6998 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
6999 const_tree type
, bool named
)
7001 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
7004 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7007 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
7009 return ((TARGET_ARCH64
7010 && (GET_MODE_ALIGNMENT (mode
) == 128
7011 || (type
&& TYPE_ALIGN (type
) == 128)))
7016 /* For an arg passed partly in registers and partly in memory,
7017 this is the number of bytes of registers used.
7018 For args passed entirely in registers or entirely in memory, zero.
7020 Any arg that starts in the first 6 regs but won't entirely fit in them
7021 needs partial registers on v8. On v9, structures with integer
7022 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7023 values that begin in the last fp reg [where "last fp reg" varies with the
7024 mode] will be split between that reg and memory. */
7027 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
7028 tree type
, bool named
)
7030 int slotno
, regno
, padding
;
7032 /* We pass false for incoming_p here, it doesn't matter. */
7033 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7034 false, ®no
, &padding
);
7041 if ((slotno
+ (mode
== BLKmode
7042 ? ROUND_ADVANCE (int_size_in_bytes (type
))
7043 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
7044 > SPARC_INT_ARG_MAX
)
7045 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
7049 /* We are guaranteed by pass_by_reference that the size of the
7050 argument is not greater than 16 bytes, so we only need to return
7051 one word if the argument is partially passed in registers. */
7053 if (type
&& AGGREGATE_TYPE_P (type
))
7055 int size
= int_size_in_bytes (type
);
7057 if (size
> UNITS_PER_WORD
7058 && slotno
== SPARC_INT_ARG_MAX
- 1)
7059 return UNITS_PER_WORD
;
7061 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7062 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7063 && ! (TARGET_FPU
&& named
)))
7065 /* The complex types are passed as packed types. */
7066 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7067 && slotno
== SPARC_INT_ARG_MAX
- 1)
7068 return UNITS_PER_WORD
;
7070 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7072 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
7074 return UNITS_PER_WORD
;
7081 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7082 Specify whether to pass the argument by reference. */
7085 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
7086 enum machine_mode mode
, const_tree type
,
7087 bool named ATTRIBUTE_UNUSED
)
7090 /* Original SPARC 32-bit ABI says that structures and unions,
7091 and quad-precision floats are passed by reference. For Pascal,
7092 also pass arrays by reference. All other base types are passed
7095 Extended ABI (as implemented by the Sun compiler) says that all
7096 complex floats are passed by reference. Pass complex integers
7097 in registers up to 8 bytes. More generally, enforce the 2-word
7098 cap for passing arguments in registers.
7100 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7101 integers are passed like floats of the same size, that is in
7102 registers up to 8 bytes. Pass all vector floats by reference
7103 like structure and unions. */
7104 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7106 /* Catch CDImode, TFmode, DCmode and TCmode. */
7107 || GET_MODE_SIZE (mode
) > 8
7109 && TREE_CODE (type
) == VECTOR_TYPE
7110 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7112 /* Original SPARC 64-bit ABI says that structures and unions
7113 smaller than 16 bytes are passed in registers, as well as
7114 all other base types.
7116 Extended ABI (as implemented by the Sun compiler) says that
7117 complex floats are passed in registers up to 16 bytes. Pass
7118 all complex integers in registers up to 16 bytes. More generally,
7119 enforce the 2-word cap for passing arguments in registers.
7121 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7122 integers are passed like floats of the same size, that is in
7123 registers (up to 16 bytes). Pass all vector floats like structure
7126 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
7127 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
7128 /* Catch CTImode and TCmode. */
7129 || GET_MODE_SIZE (mode
) > 16);
7132 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7133 Update the data in CUM to advance over an argument
7134 of mode MODE and data type TYPE.
7135 TYPE is null for libcalls where that information may not be available. */
7138 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
7139 const_tree type
, bool named
)
7141 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7144 /* We pass false for incoming_p here, it doesn't matter. */
7145 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7147 /* If argument requires leading padding, add it. */
7148 cum
->words
+= padding
;
7152 cum
->words
+= (mode
!= BLKmode
7153 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
7154 : ROUND_ADVANCE (int_size_in_bytes (type
)));
7158 if (type
&& AGGREGATE_TYPE_P (type
))
7160 int size
= int_size_in_bytes (type
);
7164 else if (size
<= 16)
7166 else /* passed by reference */
7171 cum
->words
+= (mode
!= BLKmode
7172 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
7173 : ROUND_ADVANCE (int_size_in_bytes (type
)));
7178 /* Handle the FUNCTION_ARG_PADDING macro.
7179 For the 64 bit ABI structs are always stored left shifted in their
7183 function_arg_padding (enum machine_mode mode
, const_tree type
)
7185 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
7188 /* Fall back to the default. */
7189 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7192 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7193 Specify whether to return the return value in memory. */
7196 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7199 /* Original SPARC 32-bit ABI says that structures and unions,
7200 and quad-precision floats are returned in memory. All other
7201 base types are returned in registers.
7203 Extended ABI (as implemented by the Sun compiler) says that
7204 all complex floats are returned in registers (8 FP registers
7205 at most for '_Complex long double'). Return all complex integers
7206 in registers (4 at most for '_Complex long long').
7208 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7209 integers are returned like floats of the same size, that is in
7210 registers up to 8 bytes and in memory otherwise. Return all
7211 vector floats in memory like structure and unions; note that
7212 they always have BLKmode like the latter. */
7213 return (TYPE_MODE (type
) == BLKmode
7214 || TYPE_MODE (type
) == TFmode
7215 || (TREE_CODE (type
) == VECTOR_TYPE
7216 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7218 /* Original SPARC 64-bit ABI says that structures and unions
7219 smaller than 32 bytes are returned in registers, as well as
7220 all other base types.
7222 Extended ABI (as implemented by the Sun compiler) says that all
7223 complex floats are returned in registers (8 FP registers at most
7224 for '_Complex long double'). Return all complex integers in
7225 registers (4 at most for '_Complex TItype').
7227 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7228 integers are returned like floats of the same size, that is in
7229 registers. Return all vector floats like structure and unions;
7230 note that they always have BLKmode like the latter. */
7231 return (TYPE_MODE (type
) == BLKmode
7232 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7235 /* Handle the TARGET_STRUCT_VALUE target hook.
7236 Return where to find the structure return value address. */
7239 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7248 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7249 STRUCT_VALUE_OFFSET
));
7251 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7252 STRUCT_VALUE_OFFSET
));
7254 /* Only follow the SPARC ABI for fixed-size structure returns.
7255 Variable size structure returns are handled per the normal
7256 procedures in GCC. This is enabled by -mstd-struct-return */
7258 && sparc_std_struct_return
7259 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7260 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7262 /* We must check and adjust the return address, as it is
7263 optional as to whether the return object is really
7265 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
7266 rtx scratch
= gen_reg_rtx (SImode
);
7267 rtx endlab
= gen_label_rtx ();
7269 /* Calculate the return object size */
7270 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7271 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7272 /* Construct a temporary return value */
7274 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7276 /* Implement SPARC 32-bit psABI callee return struct checking:
7278 Fetch the instruction where we will return to and see if
7279 it's an unimp instruction (the most significant 10 bits
7281 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7282 plus_constant (Pmode
,
7284 /* Assume the size is valid and pre-adjust */
7285 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7286 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7288 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7289 /* Write the address of the memory pointed to by temp_val into
7290 the memory pointed to by mem */
7291 emit_move_insn (mem
, XEXP (temp_val
, 0));
7292 emit_label (endlab
);
7299 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7300 For v9, function return values are subject to the same rules as arguments,
7301 except that up to 32 bytes may be returned in registers. */
7304 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
7307 /* Beware that the two values are swapped here wrt function_arg. */
7308 int regbase
= (outgoing
7309 ? SPARC_INCOMING_INT_ARG_FIRST
7310 : SPARC_OUTGOING_INT_ARG_FIRST
);
7311 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7314 /* Vector types deserve special treatment because they are polymorphic wrt
7315 their mode, depending upon whether VIS instructions are enabled. */
7316 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7318 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7319 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7320 || (TARGET_ARCH64
&& size
<= 32));
7322 if (mode
== BLKmode
)
7323 return function_arg_vector_value (size
,
7324 SPARC_FP_ARG_FIRST
);
7326 mclass
= MODE_FLOAT
;
7329 if (TARGET_ARCH64
&& type
)
7331 /* Structures up to 32 bytes in size are returned in registers. */
7332 if (TREE_CODE (type
) == RECORD_TYPE
)
7334 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7335 gcc_assert (size
<= 32);
7337 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
7340 /* Unions up to 32 bytes in size are returned in integer registers. */
7341 else if (TREE_CODE (type
) == UNION_TYPE
)
7343 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7344 gcc_assert (size
<= 32);
7346 return function_arg_union_value (size
, mode
, 0, regbase
);
7349 /* Objects that require it are returned in FP registers. */
7350 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7353 /* All other aggregate types are returned in an integer register in a
7354 mode corresponding to the size of the type. */
7355 else if (AGGREGATE_TYPE_P (type
))
7357 /* All other aggregate types are passed in an integer register
7358 in a mode corresponding to the size of the type. */
7359 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7360 gcc_assert (size
<= 32);
7362 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7364 /* ??? We probably should have made the same ABI change in
7365 3.4.0 as the one we made for unions. The latter was
7366 required by the SCD though, while the former is not
7367 specified, so we favored compatibility and efficiency.
7369 Now we're stuck for aggregates larger than 16 bytes,
7370 because OImode vanished in the meantime. Let's not
7371 try to be unduly clever, and simply follow the ABI
7372 for unions in that case. */
7373 if (mode
== BLKmode
)
7374 return function_arg_union_value (size
, mode
, 0, regbase
);
7379 /* We should only have pointer and integer types at this point. This
7380 must match sparc_promote_function_mode. */
7381 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7385 /* We should only have pointer and integer types at this point. This must
7386 match sparc_promote_function_mode. */
7387 else if (TARGET_ARCH32
7388 && mclass
== MODE_INT
7389 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7392 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7393 regno
= SPARC_FP_ARG_FIRST
;
7397 return gen_rtx_REG (mode
, regno
);
7400 /* Handle TARGET_FUNCTION_VALUE.
7401 On the SPARC, the value is found in the first "output" register, but the
7402 called function leaves it in the first "input" register. */
7405 sparc_function_value (const_tree valtype
,
7406 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7409 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7412 /* Handle TARGET_LIBCALL_VALUE. */
7415 sparc_libcall_value (enum machine_mode mode
,
7416 const_rtx fun ATTRIBUTE_UNUSED
)
7418 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7421 /* Handle FUNCTION_VALUE_REGNO_P.
7422 On the SPARC, the first "output" reg is used for integer values, and the
7423 first floating point register is used for floating point values. */
7426 sparc_function_value_regno_p (const unsigned int regno
)
7428 return (regno
== 8 || regno
== 32);
7431 /* Do what is necessary for `va_start'. We look at the current function
7432 to determine if stdarg or varargs is used and return the address of
7433 the first unnamed parameter. */
7436 sparc_builtin_saveregs (void)
7438 int first_reg
= crtl
->args
.info
.words
;
7442 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7443 emit_move_insn (gen_rtx_MEM (word_mode
,
7444 gen_rtx_PLUS (Pmode
,
7446 GEN_INT (FIRST_PARM_OFFSET (0)
7449 gen_rtx_REG (word_mode
,
7450 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7452 address
= gen_rtx_PLUS (Pmode
,
7454 GEN_INT (FIRST_PARM_OFFSET (0)
7455 + UNITS_PER_WORD
* first_reg
));
7460 /* Implement `va_start' for stdarg. */
7463 sparc_va_start (tree valist
, rtx nextarg
)
7465 nextarg
= expand_builtin_saveregs ();
7466 std_expand_builtin_va_start (valist
, nextarg
);
7469 /* Implement `va_arg' for stdarg. */
7472 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7475 HOST_WIDE_INT size
, rsize
, align
;
7478 tree ptrtype
= build_pointer_type (type
);
7480 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7483 size
= rsize
= UNITS_PER_WORD
;
7489 size
= int_size_in_bytes (type
);
7490 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
7495 /* For SPARC64, objects requiring 16-byte alignment get it. */
7496 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7497 align
= 2 * UNITS_PER_WORD
;
7499 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7500 are left-justified in their slots. */
7501 if (AGGREGATE_TYPE_P (type
))
7504 size
= rsize
= UNITS_PER_WORD
;
7514 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7515 incr
= fold_convert (sizetype
, incr
);
7516 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7518 incr
= fold_convert (ptr_type_node
, incr
);
7521 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7524 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7525 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7529 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7530 addr
= build_va_arg_indirect_ref (addr
);
7533 /* If the address isn't aligned properly for the type, we need a temporary.
7534 FIXME: This is inefficient, usually we can do this in registers. */
7535 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7537 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7538 tree dest_addr
= build_fold_addr_expr (tmp
);
7539 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7540 3, dest_addr
, addr
, size_int (rsize
));
7541 TREE_ADDRESSABLE (tmp
) = 1;
7542 gimplify_and_add (copy
, pre_p
);
7547 addr
= fold_convert (ptrtype
, addr
);
7549 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7550 gimplify_assign (valist
, incr
, post_p
);
7552 return build_va_arg_indirect_ref (addr
);
7555 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7556 Specify whether the vector mode is supported by the hardware. */
7559 sparc_vector_mode_supported_p (enum machine_mode mode
)
7561 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7564 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7566 static enum machine_mode
7567 sparc_preferred_simd_mode (enum machine_mode mode
)
7585 /* Return the string to output an unconditional branch to LABEL, which is
7586 the operand number of the label.
7588 DEST is the destination insn (i.e. the label), INSN is the source. */
7591 output_ubranch (rtx dest
, rtx_insn
*insn
)
7593 static char string
[64];
7594 bool v9_form
= false;
7598 /* Even if we are trying to use cbcond for this, evaluate
7599 whether we can use V9 branches as our backup plan. */
7602 if (INSN_ADDRESSES_SET_P ())
7603 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7604 - INSN_ADDRESSES (INSN_UID (insn
)));
7606 /* Leave some instructions for "slop". */
7607 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
7612 bool emit_nop
= emit_cbcond_nop (insn
);
7616 if (delta
< -500 || delta
> 500)
7622 rval
= "ba,a,pt\t%%xcc, %l0";
7629 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
7631 rval
= "cwbe\t%%g0, %%g0, %l0";
7637 strcpy (string
, "ba%*,pt\t%%xcc, ");
7639 strcpy (string
, "b%*\t");
7641 p
= strchr (string
, '\0');
7652 /* Return the string to output a conditional branch to LABEL, which is
7653 the operand number of the label. OP is the conditional expression.
7654 XEXP (OP, 0) is assumed to be a condition code register (integer or
7655 floating point) and its mode specifies what kind of comparison we made.
7657 DEST is the destination insn (i.e. the label), INSN is the source.
7659 REVERSED is nonzero if we should reverse the sense of the comparison.
7661 ANNUL is nonzero if we should generate an annulling branch. */
7664 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7667 static char string
[64];
7668 enum rtx_code code
= GET_CODE (op
);
7669 rtx cc_reg
= XEXP (op
, 0);
7670 enum machine_mode mode
= GET_MODE (cc_reg
);
7671 const char *labelno
, *branch
;
7672 int spaces
= 8, far
;
7675 /* v9 branches are limited to +-1MB. If it is too far away,
7688 fbne,a,pn %fcc2, .LC29
7696 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7699 /* Reversal of FP compares takes care -- an ordered compare
7700 becomes an unordered compare and vice versa. */
7701 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7702 code
= reverse_condition_maybe_unordered (code
);
7704 code
= reverse_condition (code
);
7707 /* Start by writing the branch condition. */
7708 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7759 /* ??? !v9: FP branches cannot be preceded by another floating point
7760 insn. Because there is currently no concept of pre-delay slots,
7761 we can fix this only by always emitting a nop before a floating
7766 strcpy (string
, "nop\n\t");
7767 strcat (string
, branch
);
7780 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7792 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7813 strcpy (string
, branch
);
7815 spaces
-= strlen (branch
);
7816 p
= strchr (string
, '\0');
7818 /* Now add the annulling, the label, and a possible noop. */
7831 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7833 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7834 - INSN_ADDRESSES (INSN_UID (insn
)));
7835 /* Leave some instructions for "slop". */
7836 if (delta
< -260000 || delta
>= 260000)
7840 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7842 static char v9_fcc_labelno
[] = "%%fccX, ";
7843 /* Set the char indicating the number of the fcc reg to use. */
7844 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7845 labelno
= v9_fcc_labelno
;
7848 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7852 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7854 labelno
= "%%xcc, ";
7859 labelno
= "%%icc, ";
7864 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7867 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7880 strcpy (p
, labelno
);
7881 p
= strchr (p
, '\0');
7884 strcpy (p
, ".+12\n\t nop\n\tb\t");
7885 /* Skip the next insn if requested or
7886 if we know that it will be a nop. */
7887 if (annul
|| ! final_sequence
)
7901 /* Emit a library call comparison between floating point X and Y.
7902 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7903 Return the new operator to be used in the comparison sequence.
7905 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7906 values as arguments instead of the TFmode registers themselves,
7907 that's why we cannot call emit_float_lib_cmp. */
7910 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7913 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7914 enum machine_mode mode
;
7915 enum rtx_code new_comparison
;
7920 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7924 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7928 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7932 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7936 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7940 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7951 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7962 tree expr
= MEM_EXPR (x
);
7964 mark_addressable (expr
);
7969 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7970 emit_move_insn (slot0
, x
);
7975 tree expr
= MEM_EXPR (y
);
7977 mark_addressable (expr
);
7982 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7983 emit_move_insn (slot1
, y
);
7986 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7987 emit_library_call (libfunc
, LCT_NORMAL
,
7989 XEXP (slot0
, 0), Pmode
,
7990 XEXP (slot1
, 0), Pmode
);
7995 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7996 emit_library_call (libfunc
, LCT_NORMAL
,
7998 x
, TFmode
, y
, TFmode
);
8003 /* Immediately move the result of the libcall into a pseudo
8004 register so reload doesn't clobber the value if it needs
8005 the return register for a spill reg. */
8006 result
= gen_reg_rtx (mode
);
8007 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8012 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8015 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8016 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8019 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8020 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8022 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8024 tem
= gen_reg_rtx (mode
);
8026 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8028 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8029 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8032 tem
= gen_reg_rtx (mode
);
8034 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8036 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8037 tem2
= gen_reg_rtx (mode
);
8039 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8041 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8042 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8043 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8049 /* Generate an unsigned DImode to FP conversion. This is the same code
8050 optabs would emit if we didn't have TFmode patterns. */
8053 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
8055 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
8058 in
= force_reg (DImode
, operands
[1]);
8059 neglab
= gen_label_rtx ();
8060 donelab
= gen_label_rtx ();
8061 i0
= gen_reg_rtx (DImode
);
8062 i1
= gen_reg_rtx (DImode
);
8063 f0
= gen_reg_rtx (mode
);
8065 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8067 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
8068 emit_jump_insn (gen_jump (donelab
));
8071 emit_label (neglab
);
8073 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8074 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8075 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8076 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
8077 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8079 emit_label (donelab
);
8082 /* Generate an FP to unsigned DImode conversion. This is the same code
8083 optabs would emit if we didn't have TFmode patterns. */
8086 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
8088 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
, limit
;
8091 in
= force_reg (mode
, operands
[1]);
8092 neglab
= gen_label_rtx ();
8093 donelab
= gen_label_rtx ();
8094 i0
= gen_reg_rtx (DImode
);
8095 i1
= gen_reg_rtx (DImode
);
8096 limit
= gen_reg_rtx (mode
);
8097 f0
= gen_reg_rtx (mode
);
8099 emit_move_insn (limit
,
8100 CONST_DOUBLE_FROM_REAL_VALUE (
8101 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8102 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8104 emit_insn (gen_rtx_SET (VOIDmode
,
8106 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8107 emit_jump_insn (gen_jump (donelab
));
8110 emit_label (neglab
);
8112 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8113 emit_insn (gen_rtx_SET (VOIDmode
,
8115 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8116 emit_insn (gen_movdi (i1
, const1_rtx
));
8117 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8118 emit_insn (gen_xordi3 (out
, i0
, i1
));
8120 emit_label (donelab
);
8123 /* Return the string to output a compare and branch instruction to DEST.
8124 DEST is the destination insn (i.e. the label), INSN is the source,
8125 and OP is the conditional expression. */
8128 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8130 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
8131 enum rtx_code code
= GET_CODE (op
);
8132 const char *cond_str
, *tmpl
;
8133 int far
, emit_nop
, len
;
8134 static char string
[64];
8137 /* Compare and Branch is limited to +-2KB. If it is too far away,
8149 len
= get_attr_length (insn
);
8152 emit_nop
= len
== 2;
8155 code
= reverse_condition (code
);
8157 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8170 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8185 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8213 int veryfar
= 1, delta
;
8215 if (INSN_ADDRESSES_SET_P ())
8217 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8218 - INSN_ADDRESSES (INSN_UID (insn
)));
8219 /* Leave some instructions for "slop". */
8220 if (delta
>= -260000 && delta
< 260000)
8225 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8227 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8232 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8234 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8237 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8242 /* Return the string to output a conditional branch to LABEL, testing
8243 register REG. LABEL is the operand number of the label; REG is the
8244 operand number of the reg. OP is the conditional expression. The mode
8245 of REG says what kind of comparison we made.
8247 DEST is the destination insn (i.e. the label), INSN is the source.
8249 REVERSED is nonzero if we should reverse the sense of the comparison.
8251 ANNUL is nonzero if we should generate an annulling branch. */
8254 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8255 int annul
, rtx_insn
*insn
)
8257 static char string
[64];
8258 enum rtx_code code
= GET_CODE (op
);
8259 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
8264 /* branch on register are limited to +-128KB. If it is too far away,
8277 brgez,a,pn %o1, .LC29
8283 ba,pt %xcc, .LC29 */
8285 far
= get_attr_length (insn
) >= 3;
8287 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8289 code
= reverse_condition (code
);
8291 /* Only 64 bit versions of these instructions exist. */
8292 gcc_assert (mode
== DImode
);
8294 /* Start by writing the branch condition. */
8299 strcpy (string
, "brnz");
8303 strcpy (string
, "brz");
8307 strcpy (string
, "brgez");
8311 strcpy (string
, "brlz");
8315 strcpy (string
, "brlez");
8319 strcpy (string
, "brgz");
8326 p
= strchr (string
, '\0');
8328 /* Now add the annulling, reg, label, and nop. */
8335 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8338 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
8343 *p
= p
< string
+ 8 ? '\t' : ' ';
8351 int veryfar
= 1, delta
;
8353 if (INSN_ADDRESSES_SET_P ())
8355 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8356 - INSN_ADDRESSES (INSN_UID (insn
)));
8357 /* Leave some instructions for "slop". */
8358 if (delta
>= -260000 && delta
< 260000)
8362 strcpy (p
, ".+12\n\t nop\n\t");
8363 /* Skip the next insn if requested or
8364 if we know that it will be a nop. */
8365 if (annul
|| ! final_sequence
)
8375 strcpy (p
, "ba,pt\t%%xcc, ");
8389 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8390 Such instructions cannot be used in the delay slot of return insn on v9.
8391 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8395 epilogue_renumber (register rtx
*where
, int test
)
8397 register const char *fmt
;
8399 register enum rtx_code code
;
8404 code
= GET_CODE (*where
);
8409 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8411 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8412 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8420 /* Do not replace the frame pointer with the stack pointer because
8421 it can cause the delayed instruction to load below the stack.
8422 This occurs when instructions like:
8424 (set (reg/i:SI 24 %i0)
8425 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8426 (const_int -20 [0xffffffec])) 0))
8428 are in the return delayed slot. */
8430 if (GET_CODE (XEXP (*where
, 0)) == REG
8431 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8432 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8433 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8438 if (SPARC_STACK_BIAS
8439 && GET_CODE (XEXP (*where
, 0)) == REG
8440 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8448 fmt
= GET_RTX_FORMAT (code
);
8450 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8455 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8456 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8459 else if (fmt
[i
] == 'e'
8460 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8466 /* Leaf functions and non-leaf functions have different needs. */
8469 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8472 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8474 static const int *const reg_alloc_orders
[] = {
8475 reg_leaf_alloc_order
,
8476 reg_nonleaf_alloc_order
};
8479 order_regs_for_local_alloc (void)
8481 static int last_order_nonleaf
= 1;
8483 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8485 last_order_nonleaf
= !last_order_nonleaf
;
8486 memcpy ((char *) reg_alloc_order
,
8487 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8488 FIRST_PSEUDO_REGISTER
* sizeof (int));
8492 /* Return 1 if REG and MEM are legitimate enough to allow the various
8493 mem<-->reg splits to be run. */
8496 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
8498 /* Punt if we are here by mistake. */
8499 gcc_assert (reload_completed
);
8501 /* We must have an offsettable memory reference. */
8502 if (! offsettable_memref_p (mem
))
8505 /* If we have legitimate args for ldd/std, we do not want
8506 the split to happen. */
8507 if ((REGNO (reg
) % 2) == 0
8508 && mem_min_alignment (mem
, 8))
8515 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
8518 sparc_split_regreg_legitimate (rtx reg1
, rtx reg2
)
8522 if (GET_CODE (reg1
) == SUBREG
)
8523 reg1
= SUBREG_REG (reg1
);
8524 if (GET_CODE (reg1
) != REG
)
8526 regno1
= REGNO (reg1
);
8528 if (GET_CODE (reg2
) == SUBREG
)
8529 reg2
= SUBREG_REG (reg2
);
8530 if (GET_CODE (reg2
) != REG
)
8532 regno2
= REGNO (reg2
);
8534 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8539 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8540 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
8547 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8548 This makes them candidates for using ldd and std insns.
8550 Note reg1 and reg2 *must* be hard registers. */
8553 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
8555 /* We might have been passed a SUBREG. */
8556 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8559 if (REGNO (reg1
) % 2 != 0)
8562 /* Integer ldd is deprecated in SPARC V9 */
8563 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
8566 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8569 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8572 This can only happen when addr1 and addr2, the addresses in mem1
8573 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8574 addr1 must also be aligned on a 64-bit boundary.
8576 Also iff dependent_reg_rtx is not null it should not be used to
8577 compute the address for mem1, i.e. we cannot optimize a sequence
8589 But, note that the transformation from:
8594 is perfectly fine. Thus, the peephole2 patterns always pass us
8595 the destination register of the first load, never the second one.
8597 For stores we don't have a similar problem, so dependent_reg_rtx is
8601 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
8605 HOST_WIDE_INT offset1
;
8607 /* The mems cannot be volatile. */
8608 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8611 /* MEM1 should be aligned on a 64-bit boundary. */
8612 if (MEM_ALIGN (mem1
) < 64)
8615 addr1
= XEXP (mem1
, 0);
8616 addr2
= XEXP (mem2
, 0);
8618 /* Extract a register number and offset (if used) from the first addr. */
8619 if (GET_CODE (addr1
) == PLUS
)
8621 /* If not a REG, return zero. */
8622 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8626 reg1
= REGNO (XEXP (addr1
, 0));
8627 /* The offset must be constant! */
8628 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8630 offset1
= INTVAL (XEXP (addr1
, 1));
8633 else if (GET_CODE (addr1
) != REG
)
8637 reg1
= REGNO (addr1
);
8638 /* This was a simple (mem (reg)) expression. Offset is 0. */
8642 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8643 if (GET_CODE (addr2
) != PLUS
)
8646 if (GET_CODE (XEXP (addr2
, 0)) != REG
8647 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8650 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8653 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
8656 /* The first offset must be evenly divisible by 8 to ensure the
8657 address is 64 bit aligned. */
8658 if (offset1
% 8 != 0)
8661 /* The offset for the second addr must be 4 more than the first addr. */
8662 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
8665 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8670 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8673 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, enum machine_mode mode
)
8675 rtx x
= widen_memory_access (mem1
, mode
, 0);
8676 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
8680 /* Return 1 if reg is a pseudo, or is the first register in
8681 a hard register pair. This makes it suitable for use in
8682 ldd and std insns. */
8685 register_ok_for_ldd (rtx reg
)
8687 /* We might have been passed a SUBREG. */
8691 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
8692 return (REGNO (reg
) % 2 == 0);
8697 /* Return 1 if OP, a MEM, has an address which is known to be
8698 aligned to an 8-byte boundary. */
8701 memory_ok_for_ldd (rtx op
)
8703 /* In 64-bit mode, we assume that the address is word-aligned. */
8704 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
8707 if (! can_create_pseudo_p ()
8708 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
8714 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8717 sparc_print_operand_punct_valid_p (unsigned char code
)
8730 /* Implement TARGET_PRINT_OPERAND.
8731 Print operand X (an rtx) in assembler syntax to file FILE.
8732 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8733 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8736 sparc_print_operand (FILE *file
, rtx x
, int code
)
8741 /* Output an insn in a delay slot. */
8743 sparc_indent_opcode
= 1;
8745 fputs ("\n\t nop", file
);
8748 /* Output an annul flag if there's nothing for the delay slot and we
8749 are optimizing. This is always used with '(' below.
8750 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8751 this is a dbx bug. So, we only do this when optimizing.
8752 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8753 Always emit a nop in case the next instruction is a branch. */
8754 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8758 /* Output a 'nop' if there's nothing for the delay slot and we are
8759 not optimizing. This is always used with '*' above. */
8760 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8761 fputs ("\n\t nop", file
);
8762 else if (final_sequence
)
8763 sparc_indent_opcode
= 1;
8766 /* Output the right displacement from the saved PC on function return.
8767 The caller may have placed an "unimp" insn immediately after the call
8768 so we have to account for it. This insn is used in the 32-bit ABI
8769 when calling a function that returns a non zero-sized structure. The
8770 64-bit ABI doesn't have it. Be careful to have this test be the same
8771 as that for the call. The exception is when sparc_std_struct_return
8772 is enabled, the psABI is followed exactly and the adjustment is made
8773 by the code in sparc_struct_value_rtx. The call emitted is the same
8774 when sparc_std_struct_return is enabled. */
8776 && cfun
->returns_struct
8777 && !sparc_std_struct_return
8778 && DECL_SIZE (DECL_RESULT (current_function_decl
))
8779 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
8781 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
8787 /* Output the Embedded Medium/Anywhere code model base register. */
8788 fputs (EMBMEDANY_BASE_REG
, file
);
8791 /* Print some local dynamic TLS name. */
8792 assemble_name (file
, get_some_local_dynamic_name ());
8796 /* Adjust the operand to take into account a RESTORE operation. */
8797 if (GET_CODE (x
) == CONST_INT
)
8799 else if (GET_CODE (x
) != REG
)
8800 output_operand_lossage ("invalid %%Y operand");
8801 else if (REGNO (x
) < 8)
8802 fputs (reg_names
[REGNO (x
)], file
);
8803 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
8804 fputs (reg_names
[REGNO (x
)-16], file
);
8806 output_operand_lossage ("invalid %%Y operand");
8809 /* Print out the low order register name of a register pair. */
8810 if (WORDS_BIG_ENDIAN
)
8811 fputs (reg_names
[REGNO (x
)+1], file
);
8813 fputs (reg_names
[REGNO (x
)], file
);
8816 /* Print out the high order register name of a register pair. */
8817 if (WORDS_BIG_ENDIAN
)
8818 fputs (reg_names
[REGNO (x
)], file
);
8820 fputs (reg_names
[REGNO (x
)+1], file
);
8823 /* Print out the second register name of a register pair or quad.
8824 I.e., R (%o0) => %o1. */
8825 fputs (reg_names
[REGNO (x
)+1], file
);
8828 /* Print out the third register name of a register quad.
8829 I.e., S (%o0) => %o2. */
8830 fputs (reg_names
[REGNO (x
)+2], file
);
8833 /* Print out the fourth register name of a register quad.
8834 I.e., T (%o0) => %o3. */
8835 fputs (reg_names
[REGNO (x
)+3], file
);
8838 /* Print a condition code register. */
8839 if (REGNO (x
) == SPARC_ICC_REG
)
8841 /* We don't handle CC[X]_NOOVmode because they're not supposed
8843 if (GET_MODE (x
) == CCmode
)
8844 fputs ("%icc", file
);
8845 else if (GET_MODE (x
) == CCXmode
)
8846 fputs ("%xcc", file
);
8851 /* %fccN register */
8852 fputs (reg_names
[REGNO (x
)], file
);
8855 /* Print the operand's address only. */
8856 output_address (XEXP (x
, 0));
8859 /* In this case we need a register. Use %g0 if the
8860 operand is const0_rtx. */
8862 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
8864 fputs ("%g0", file
);
8871 switch (GET_CODE (x
))
8873 case IOR
: fputs ("or", file
); break;
8874 case AND
: fputs ("and", file
); break;
8875 case XOR
: fputs ("xor", file
); break;
8876 default: output_operand_lossage ("invalid %%A operand");
8881 switch (GET_CODE (x
))
8883 case IOR
: fputs ("orn", file
); break;
8884 case AND
: fputs ("andn", file
); break;
8885 case XOR
: fputs ("xnor", file
); break;
8886 default: output_operand_lossage ("invalid %%B operand");
8890 /* This is used by the conditional move instructions. */
8893 enum rtx_code rc
= GET_CODE (x
);
8897 case NE
: fputs ("ne", file
); break;
8898 case EQ
: fputs ("e", file
); break;
8899 case GE
: fputs ("ge", file
); break;
8900 case GT
: fputs ("g", file
); break;
8901 case LE
: fputs ("le", file
); break;
8902 case LT
: fputs ("l", file
); break;
8903 case GEU
: fputs ("geu", file
); break;
8904 case GTU
: fputs ("gu", file
); break;
8905 case LEU
: fputs ("leu", file
); break;
8906 case LTU
: fputs ("lu", file
); break;
8907 case LTGT
: fputs ("lg", file
); break;
8908 case UNORDERED
: fputs ("u", file
); break;
8909 case ORDERED
: fputs ("o", file
); break;
8910 case UNLT
: fputs ("ul", file
); break;
8911 case UNLE
: fputs ("ule", file
); break;
8912 case UNGT
: fputs ("ug", file
); break;
8913 case UNGE
: fputs ("uge", file
); break;
8914 case UNEQ
: fputs ("ue", file
); break;
8915 default: output_operand_lossage ("invalid %%C operand");
8920 /* This are used by the movr instruction pattern. */
8923 enum rtx_code rc
= GET_CODE (x
);
8926 case NE
: fputs ("ne", file
); break;
8927 case EQ
: fputs ("e", file
); break;
8928 case GE
: fputs ("gez", file
); break;
8929 case LT
: fputs ("lz", file
); break;
8930 case LE
: fputs ("lez", file
); break;
8931 case GT
: fputs ("gz", file
); break;
8932 default: output_operand_lossage ("invalid %%D operand");
8939 /* Print a sign-extended character. */
8940 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8941 fprintf (file
, "%d", i
);
8946 /* Operand must be a MEM; write its address. */
8947 if (GET_CODE (x
) != MEM
)
8948 output_operand_lossage ("invalid %%f operand");
8949 output_address (XEXP (x
, 0));
8954 /* Print a sign-extended 32-bit value. */
8956 if (GET_CODE(x
) == CONST_INT
)
8958 else if (GET_CODE(x
) == CONST_DOUBLE
)
8959 i
= CONST_DOUBLE_LOW (x
);
8962 output_operand_lossage ("invalid %%s operand");
8965 i
= trunc_int_for_mode (i
, SImode
);
8966 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8971 /* Do nothing special. */
8975 /* Undocumented flag. */
8976 output_operand_lossage ("invalid operand output code");
8979 if (GET_CODE (x
) == REG
)
8980 fputs (reg_names
[REGNO (x
)], file
);
8981 else if (GET_CODE (x
) == MEM
)
8984 /* Poor Sun assembler doesn't understand absolute addressing. */
8985 if (CONSTANT_P (XEXP (x
, 0)))
8986 fputs ("%g0+", file
);
8987 output_address (XEXP (x
, 0));
8990 else if (GET_CODE (x
) == HIGH
)
8992 fputs ("%hi(", file
);
8993 output_addr_const (file
, XEXP (x
, 0));
8996 else if (GET_CODE (x
) == LO_SUM
)
8998 sparc_print_operand (file
, XEXP (x
, 0), 0);
8999 if (TARGET_CM_MEDMID
)
9000 fputs ("+%l44(", file
);
9002 fputs ("+%lo(", file
);
9003 output_addr_const (file
, XEXP (x
, 1));
9006 else if (GET_CODE (x
) == CONST_DOUBLE
9007 && (GET_MODE (x
) == VOIDmode
9008 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
9010 if (CONST_DOUBLE_HIGH (x
) == 0)
9011 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
9012 else if (CONST_DOUBLE_HIGH (x
) == -1
9013 && CONST_DOUBLE_LOW (x
) < 0)
9014 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
9016 output_operand_lossage ("long long constant not a valid immediate operand");
9018 else if (GET_CODE (x
) == CONST_DOUBLE
)
9019 output_operand_lossage ("floating point constant not a valid immediate operand");
9020 else { output_addr_const (file
, x
); }
9023 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9026 sparc_print_operand_address (FILE *file
, rtx x
)
9028 register rtx base
, index
= 0;
9030 register rtx addr
= x
;
9033 fputs (reg_names
[REGNO (addr
)], file
);
9034 else if (GET_CODE (addr
) == PLUS
)
9036 if (CONST_INT_P (XEXP (addr
, 0)))
9037 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9038 else if (CONST_INT_P (XEXP (addr
, 1)))
9039 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9041 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9042 if (GET_CODE (base
) == LO_SUM
)
9044 gcc_assert (USE_AS_OFFSETABLE_LO10
9046 && ! TARGET_CM_MEDMID
);
9047 output_operand (XEXP (base
, 0), 0);
9048 fputs ("+%lo(", file
);
9049 output_address (XEXP (base
, 1));
9050 fprintf (file
, ")+%d", offset
);
9054 fputs (reg_names
[REGNO (base
)], file
);
9056 fprintf (file
, "%+d", offset
);
9057 else if (REG_P (index
))
9058 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9059 else if (GET_CODE (index
) == SYMBOL_REF
9060 || GET_CODE (index
) == LABEL_REF
9061 || GET_CODE (index
) == CONST
)
9062 fputc ('+', file
), output_addr_const (file
, index
);
9063 else gcc_unreachable ();
9066 else if (GET_CODE (addr
) == MINUS
9067 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9069 output_addr_const (file
, XEXP (addr
, 0));
9071 output_addr_const (file
, XEXP (addr
, 1));
9072 fputs ("-.)", file
);
9074 else if (GET_CODE (addr
) == LO_SUM
)
9076 output_operand (XEXP (addr
, 0), 0);
9077 if (TARGET_CM_MEDMID
)
9078 fputs ("+%l44(", file
);
9080 fputs ("+%lo(", file
);
9081 output_address (XEXP (addr
, 1));
9085 && GET_CODE (addr
) == CONST
9086 && GET_CODE (XEXP (addr
, 0)) == MINUS
9087 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9088 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9089 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9091 addr
= XEXP (addr
, 0);
9092 output_addr_const (file
, XEXP (addr
, 0));
9093 /* Group the args of the second CONST in parenthesis. */
9095 /* Skip past the second CONST--it does nothing for us. */
9096 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9097 /* Close the parenthesis. */
9102 output_addr_const (file
, addr
);
9106 /* Target hook for assembling integer objects. The sparc version has
9107 special handling for aligned DI-mode objects. */
9110 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9112 /* ??? We only output .xword's for symbols and only then in environments
9113 where the assembler can handle them. */
9114 if (aligned_p
&& size
== 8
9115 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
9119 assemble_integer_with_op ("\t.xword\t", x
);
9124 assemble_aligned_integer (4, const0_rtx
);
9125 assemble_aligned_integer (4, x
);
9129 return default_assemble_integer (x
, size
, aligned_p
);
9132 /* Return the value of a code used in the .proc pseudo-op that says
9133 what kind of result this function returns. For non-C types, we pick
9134 the closest C type. */
9136 #ifndef SHORT_TYPE_SIZE
9137 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9140 #ifndef INT_TYPE_SIZE
9141 #define INT_TYPE_SIZE BITS_PER_WORD
9144 #ifndef LONG_TYPE_SIZE
9145 #define LONG_TYPE_SIZE BITS_PER_WORD
9148 #ifndef LONG_LONG_TYPE_SIZE
9149 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9152 #ifndef FLOAT_TYPE_SIZE
9153 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9156 #ifndef DOUBLE_TYPE_SIZE
9157 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9160 #ifndef LONG_DOUBLE_TYPE_SIZE
9161 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9165 sparc_type_code (register tree type
)
9167 register unsigned long qualifiers
= 0;
9168 register unsigned shift
;
9170 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9171 setting more, since some assemblers will give an error for this. Also,
9172 we must be careful to avoid shifts of 32 bits or more to avoid getting
9173 unpredictable results. */
9175 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9177 switch (TREE_CODE (type
))
9183 qualifiers
|= (3 << shift
);
9188 qualifiers
|= (2 << shift
);
9192 case REFERENCE_TYPE
:
9194 qualifiers
|= (1 << shift
);
9198 return (qualifiers
| 8);
9201 case QUAL_UNION_TYPE
:
9202 return (qualifiers
| 9);
9205 return (qualifiers
| 10);
9208 return (qualifiers
| 16);
9211 /* If this is a range type, consider it to be the underlying
9213 if (TREE_TYPE (type
) != 0)
9216 /* Carefully distinguish all the standard types of C,
9217 without messing up if the language is not C. We do this by
9218 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9219 look at both the names and the above fields, but that's redundant.
9220 Any type whose size is between two C types will be considered
9221 to be the wider of the two types. Also, we do not have a
9222 special code to use for "long long", so anything wider than
9223 long is treated the same. Note that we can't distinguish
9224 between "int" and "long" in this code if they are the same
9225 size, but that's fine, since neither can the assembler. */
9227 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9228 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9230 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9231 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9233 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9234 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9237 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9240 /* If this is a range type, consider it to be the underlying
9242 if (TREE_TYPE (type
) != 0)
9245 /* Carefully distinguish all the standard types of C,
9246 without messing up if the language is not C. */
9248 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9249 return (qualifiers
| 6);
9252 return (qualifiers
| 7);
9254 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9255 /* ??? We need to distinguish between double and float complex types,
9256 but I don't know how yet because I can't reach this code from
9257 existing front-ends. */
9258 return (qualifiers
| 7); /* Who knows? */
9261 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9267 gcc_unreachable (); /* Not a type! */
9274 /* Nested function support. */
9276 /* Emit RTL insns to initialize the variable parts of a trampoline.
9277 FNADDR is an RTX for the address of the function's pure code.
9278 CXT is an RTX for the static chain value for the function.
9280 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9281 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9282 (to store insns). This is a bit excessive. Perhaps a different
9283 mechanism would be better here.
9285 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9288 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9290 /* SPARC 32-bit trampoline:
9293 sethi %hi(static), %g2
9295 or %g2, %lo(static), %g2
9297 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9298 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9302 (adjust_address (m_tramp
, SImode
, 0),
9303 expand_binop (SImode
, ior_optab
,
9304 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9305 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9306 NULL_RTX
, 1, OPTAB_DIRECT
));
9309 (adjust_address (m_tramp
, SImode
, 4),
9310 expand_binop (SImode
, ior_optab
,
9311 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9312 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9313 NULL_RTX
, 1, OPTAB_DIRECT
));
9316 (adjust_address (m_tramp
, SImode
, 8),
9317 expand_binop (SImode
, ior_optab
,
9318 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9319 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9320 NULL_RTX
, 1, OPTAB_DIRECT
));
9323 (adjust_address (m_tramp
, SImode
, 12),
9324 expand_binop (SImode
, ior_optab
,
9325 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9326 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9327 NULL_RTX
, 1, OPTAB_DIRECT
));
9329 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9330 aligned on a 16 byte boundary so one flush clears it all. */
9331 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9332 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9333 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9334 && sparc_cpu
!= PROCESSOR_NIAGARA
9335 && sparc_cpu
!= PROCESSOR_NIAGARA2
9336 && sparc_cpu
!= PROCESSOR_NIAGARA3
9337 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
9338 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9340 /* Call __enable_execute_stack after writing onto the stack to make sure
9341 the stack address is accessible. */
9342 #ifdef HAVE_ENABLE_EXECUTE_STACK
9343 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9344 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9349 /* The 64-bit version is simpler because it makes more sense to load the
9350 values as "immediate" data out of the trampoline. It's also easier since
9351 we can read the PC without clobbering a register. */
9354 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9356 /* SPARC 64-bit trampoline:
9365 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9366 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9367 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9368 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9369 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9370 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9371 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9372 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9373 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9374 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9375 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9377 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9378 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9379 && sparc_cpu
!= PROCESSOR_NIAGARA
9380 && sparc_cpu
!= PROCESSOR_NIAGARA2
9381 && sparc_cpu
!= PROCESSOR_NIAGARA3
9382 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
9383 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
9385 /* Call __enable_execute_stack after writing onto the stack to make sure
9386 the stack address is accessible. */
9387 #ifdef HAVE_ENABLE_EXECUTE_STACK
9388 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9389 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9393 /* Worker for TARGET_TRAMPOLINE_INIT. */
9396 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9398 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
9399 cxt
= force_reg (Pmode
, cxt
);
9401 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9403 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9406 /* Adjust the cost of a scheduling dependency. Return the new cost of
9407 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9410 supersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
9412 enum attr_type insn_type
;
9414 if (! recog_memoized (insn
))
9417 insn_type
= get_attr_type (insn
);
9419 if (REG_NOTE_KIND (link
) == 0)
9421 /* Data dependency; DEP_INSN writes a register that INSN reads some
9424 /* if a load, then the dependence must be on the memory address;
9425 add an extra "cycle". Note that the cost could be two cycles
9426 if the reg was written late in an instruction group; we ca not tell
9428 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
9431 /* Get the delay only if the address of the store is the dependence. */
9432 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
9434 rtx pat
= PATTERN(insn
);
9435 rtx dep_pat
= PATTERN (dep_insn
);
9437 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9438 return cost
; /* This should not happen! */
9440 /* The dependency between the two instructions was on the data that
9441 is being stored. Assume that this implies that the address of the
9442 store is not dependent. */
9443 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9446 return cost
+ 3; /* An approximation. */
9449 /* A shift instruction cannot receive its data from an instruction
9450 in the same cycle; add a one cycle penalty. */
9451 if (insn_type
== TYPE_SHIFT
)
9452 return cost
+ 3; /* Split before cascade into shift. */
9456 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9457 INSN writes some cycles later. */
9459 /* These are only significant for the fpu unit; writing a fp reg before
9460 the fpu has finished with it stalls the processor. */
9462 /* Reusing an integer register causes no problems. */
9463 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9471 hypersparc_adjust_cost (rtx insn
, rtx link
, rtx dep_insn
, int cost
)
9473 enum attr_type insn_type
, dep_type
;
9474 rtx pat
= PATTERN(insn
);
9475 rtx dep_pat
= PATTERN (dep_insn
);
9477 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
9480 insn_type
= get_attr_type (insn
);
9481 dep_type
= get_attr_type (dep_insn
);
9483 switch (REG_NOTE_KIND (link
))
9486 /* Data dependency; DEP_INSN writes a register that INSN reads some
9493 /* Get the delay iff the address of the store is the dependence. */
9494 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9497 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9504 /* If a load, then the dependence must be on the memory address. If
9505 the addresses aren't equal, then it might be a false dependency */
9506 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
9508 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
9509 || GET_CODE (SET_DEST (dep_pat
)) != MEM
9510 || GET_CODE (SET_SRC (pat
)) != MEM
9511 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
9512 XEXP (SET_SRC (pat
), 0)))
9520 /* Compare to branch latency is 0. There is no benefit from
9521 separating compare and branch. */
9522 if (dep_type
== TYPE_COMPARE
)
9524 /* Floating point compare to branch latency is less than
9525 compare to conditional move. */
9526 if (dep_type
== TYPE_FPCMP
)
9535 /* Anti-dependencies only penalize the fpu unit. */
9536 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9548 sparc_adjust_cost(rtx insn
, rtx link
, rtx dep
, int cost
)
9552 case PROCESSOR_SUPERSPARC
:
9553 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
9555 case PROCESSOR_HYPERSPARC
:
9556 case PROCESSOR_SPARCLITE86X
:
9557 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
9566 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
9567 int sched_verbose ATTRIBUTE_UNUSED
,
9568 int max_ready ATTRIBUTE_UNUSED
)
9572 sparc_use_sched_lookahead (void)
9574 if (sparc_cpu
== PROCESSOR_NIAGARA
9575 || sparc_cpu
== PROCESSOR_NIAGARA2
9576 || sparc_cpu
== PROCESSOR_NIAGARA3
)
9578 if (sparc_cpu
== PROCESSOR_NIAGARA4
)
9580 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9581 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
9583 if ((1 << sparc_cpu
) &
9584 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
9585 (1 << PROCESSOR_SPARCLITE86X
)))
9591 sparc_issue_rate (void)
9595 case PROCESSOR_NIAGARA
:
9596 case PROCESSOR_NIAGARA2
:
9597 case PROCESSOR_NIAGARA3
:
9600 case PROCESSOR_NIAGARA4
:
9602 /* Assume V9 processors are capable of at least dual-issue. */
9604 case PROCESSOR_SUPERSPARC
:
9606 case PROCESSOR_HYPERSPARC
:
9607 case PROCESSOR_SPARCLITE86X
:
9609 case PROCESSOR_ULTRASPARC
:
9610 case PROCESSOR_ULTRASPARC3
:
9616 set_extends (rtx insn
)
9618 register rtx pat
= PATTERN (insn
);
9620 switch (GET_CODE (SET_SRC (pat
)))
9622 /* Load and some shift instructions zero extend. */
9625 /* sethi clears the high bits */
9627 /* LO_SUM is used with sethi. sethi cleared the high
9628 bits and the values used with lo_sum are positive */
9630 /* Store flag stores 0 or 1 */
9640 rtx op0
= XEXP (SET_SRC (pat
), 0);
9641 rtx op1
= XEXP (SET_SRC (pat
), 1);
9642 if (GET_CODE (op1
) == CONST_INT
)
9643 return INTVAL (op1
) >= 0;
9644 if (GET_CODE (op0
) != REG
)
9646 if (sparc_check_64 (op0
, insn
) == 1)
9648 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9653 rtx op0
= XEXP (SET_SRC (pat
), 0);
9654 rtx op1
= XEXP (SET_SRC (pat
), 1);
9655 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
9657 if (GET_CODE (op1
) == CONST_INT
)
9658 return INTVAL (op1
) >= 0;
9659 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9662 return GET_MODE (SET_SRC (pat
)) == SImode
;
9663 /* Positive integers leave the high bits zero. */
9665 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
9667 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
9670 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
9672 return sparc_check_64 (SET_SRC (pat
), insn
);
9678 /* We _ought_ to have only one kind per function, but... */
9679 static GTY(()) rtx sparc_addr_diff_list
;
9680 static GTY(()) rtx sparc_addr_list
;
9683 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
9685 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9687 sparc_addr_diff_list
9688 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
9690 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
9694 sparc_output_addr_vec (rtx vec
)
9696 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9697 int idx
, vlen
= XVECLEN (body
, 0);
9699 #ifdef ASM_OUTPUT_ADDR_VEC_START
9700 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9703 #ifdef ASM_OUTPUT_CASE_LABEL
9704 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9707 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9710 for (idx
= 0; idx
< vlen
; idx
++)
9712 ASM_OUTPUT_ADDR_VEC_ELT
9713 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9716 #ifdef ASM_OUTPUT_ADDR_VEC_END
9717 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9722 sparc_output_addr_diff_vec (rtx vec
)
9724 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9725 rtx base
= XEXP (XEXP (body
, 0), 0);
9726 int idx
, vlen
= XVECLEN (body
, 1);
9728 #ifdef ASM_OUTPUT_ADDR_VEC_START
9729 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9732 #ifdef ASM_OUTPUT_CASE_LABEL
9733 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9736 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9739 for (idx
= 0; idx
< vlen
; idx
++)
9741 ASM_OUTPUT_ADDR_DIFF_ELT
9744 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
9745 CODE_LABEL_NUMBER (base
));
9748 #ifdef ASM_OUTPUT_ADDR_VEC_END
9749 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9754 sparc_output_deferred_case_vectors (void)
9759 if (sparc_addr_list
== NULL_RTX
9760 && sparc_addr_diff_list
== NULL_RTX
)
9763 /* Align to cache line in the function's code section. */
9764 switch_to_section (current_function_section ());
9766 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9768 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
9770 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
9771 sparc_output_addr_vec (XEXP (t
, 0));
9772 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
9773 sparc_output_addr_diff_vec (XEXP (t
, 0));
9775 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
9778 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9779 unknown. Return 1 if the high bits are zero, -1 if the register is
9782 sparc_check_64 (rtx x
, rtx insn
)
9784 /* If a register is set only once it is safe to ignore insns this
9785 code does not know how to handle. The loop will either recognize
9786 the single set and return the correct value or fail to recognize
9791 gcc_assert (GET_CODE (x
) == REG
);
9793 if (GET_MODE (x
) == DImode
)
9794 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
9796 if (flag_expensive_optimizations
9797 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
9803 insn
= get_last_insn_anywhere ();
9808 while ((insn
= PREV_INSN (insn
)))
9810 switch (GET_CODE (insn
))
9823 rtx pat
= PATTERN (insn
);
9824 if (GET_CODE (pat
) != SET
)
9826 if (rtx_equal_p (x
, SET_DEST (pat
)))
9827 return set_extends (insn
);
9828 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
9829 return set_extends (insn
);
9830 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
9838 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9839 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9842 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
9844 static char asm_code
[60];
9846 /* The scratch register is only required when the destination
9847 register is not a 64-bit global or out register. */
9848 if (which_alternative
!= 2)
9849 operands
[3] = operands
[0];
9851 /* We can only shift by constants <= 63. */
9852 if (GET_CODE (operands
[2]) == CONST_INT
)
9853 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
9855 if (GET_CODE (operands
[1]) == CONST_INT
)
9857 output_asm_insn ("mov\t%1, %3", operands
);
9861 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
9862 if (sparc_check_64 (operands
[1], insn
) <= 0)
9863 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
9864 output_asm_insn ("or\t%L1, %3, %3", operands
);
9867 strcpy (asm_code
, opcode
);
9869 if (which_alternative
!= 2)
9870 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9873 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9876 /* Output rtl to increment the profiler label LABELNO
9877 for profiling a function entry. */
9880 sparc_profile_hook (int labelno
)
9885 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
9886 if (NO_PROFILE_COUNTERS
)
9888 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
9892 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
9893 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
9894 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
9898 #ifdef TARGET_SOLARIS
9899 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9902 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
9903 tree decl ATTRIBUTE_UNUSED
)
9905 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
9907 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9911 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9913 if (!(flags
& SECTION_DEBUG
))
9914 fputs (",#alloc", asm_out_file
);
9915 if (flags
& SECTION_WRITE
)
9916 fputs (",#write", asm_out_file
);
9917 if (flags
& SECTION_TLS
)
9918 fputs (",#tls", asm_out_file
);
9919 if (flags
& SECTION_CODE
)
9920 fputs (",#execinstr", asm_out_file
);
9922 /* Sun as only supports #nobits/#progbits since Solaris 10. */
9923 if (HAVE_AS_SPARC_NOBITS
)
9925 if (flags
& SECTION_BSS
)
9926 fputs (",#nobits", asm_out_file
);
9928 fputs (",#progbits", asm_out_file
);
9931 fputc ('\n', asm_out_file
);
9933 #endif /* TARGET_SOLARIS */
9935 /* We do not allow indirect calls to be optimized into sibling calls.
9937 We cannot use sibling calls when delayed branches are disabled
9938 because they will likely require the call delay slot to be filled.
9940 Also, on SPARC 32-bit we cannot emit a sibling call when the
9941 current function returns a structure. This is because the "unimp
9942 after call" convention would cause the callee to return to the
9943 wrong place. The generic code already disallows cases where the
9944 function being called returns a structure.
9946 It may seem strange how this last case could occur. Usually there
9947 is code after the call which jumps to epilogue code which dumps the
9948 return value into the struct return area. That ought to invalidate
9949 the sibling call right? Well, in the C++ case we can end up passing
9950 the pointer to the struct return area to a constructor (which returns
9951 void) and then nothing else happens. Such a sibling call would look
9952 valid without the added check here.
9954 VxWorks PIC PLT entries require the global pointer to be initialized
9955 on entry. We therefore can't emit sibling calls to them. */
9957 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9960 && flag_delayed_branch
9961 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9962 && !(TARGET_VXWORKS_RTP
9964 && !targetm
.binds_local_p (decl
)));
9967 /* libfunc renaming. */
9970 sparc_init_libfuncs (void)
9974 /* Use the subroutines that Sun's library provides for integer
9975 multiply and divide. The `*' prevents an underscore from
9976 being prepended by the compiler. .umul is a little faster
9978 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9979 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9980 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9981 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9982 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9984 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9985 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9986 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9987 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9988 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9989 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
9991 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
9992 is because with soft-float, the SFmode and DFmode sqrt
9993 instructions will be absent, and the compiler will notice and
9994 try to use the TFmode sqrt instruction for calls to the
9995 builtin function sqrt, but this fails. */
9997 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
9999 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10000 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10001 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10002 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10003 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10004 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10006 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10007 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10008 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10009 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10011 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10012 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10013 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10014 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10016 if (DITF_CONVERSION_LIBFUNCS
)
10018 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10019 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10020 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10021 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10024 if (SUN_CONVERSION_LIBFUNCS
)
10026 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10027 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10028 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10029 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10034 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10035 do not exist in the library. Make sure the compiler does not
10036 emit calls to them by accident. (It should always use the
10037 hardware instructions.) */
10038 set_optab_libfunc (smul_optab
, SImode
, 0);
10039 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10040 set_optab_libfunc (udiv_optab
, SImode
, 0);
10041 set_optab_libfunc (smod_optab
, SImode
, 0);
10042 set_optab_libfunc (umod_optab
, SImode
, 0);
10044 if (SUN_INTEGER_MULTIPLY_64
)
10046 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10047 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10048 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10049 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10050 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10053 if (SUN_CONVERSION_LIBFUNCS
)
10055 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10056 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10057 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10058 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10063 /* SPARC builtins. */
10064 enum sparc_builtins
10066 /* FPU builtins. */
10067 SPARC_BUILTIN_LDFSR
,
10068 SPARC_BUILTIN_STFSR
,
10070 /* VIS 1.0 builtins. */
10071 SPARC_BUILTIN_FPACK16
,
10072 SPARC_BUILTIN_FPACK32
,
10073 SPARC_BUILTIN_FPACKFIX
,
10074 SPARC_BUILTIN_FEXPAND
,
10075 SPARC_BUILTIN_FPMERGE
,
10076 SPARC_BUILTIN_FMUL8X16
,
10077 SPARC_BUILTIN_FMUL8X16AU
,
10078 SPARC_BUILTIN_FMUL8X16AL
,
10079 SPARC_BUILTIN_FMUL8SUX16
,
10080 SPARC_BUILTIN_FMUL8ULX16
,
10081 SPARC_BUILTIN_FMULD8SUX16
,
10082 SPARC_BUILTIN_FMULD8ULX16
,
10083 SPARC_BUILTIN_FALIGNDATAV4HI
,
10084 SPARC_BUILTIN_FALIGNDATAV8QI
,
10085 SPARC_BUILTIN_FALIGNDATAV2SI
,
10086 SPARC_BUILTIN_FALIGNDATADI
,
10087 SPARC_BUILTIN_WRGSR
,
10088 SPARC_BUILTIN_RDGSR
,
10089 SPARC_BUILTIN_ALIGNADDR
,
10090 SPARC_BUILTIN_ALIGNADDRL
,
10091 SPARC_BUILTIN_PDIST
,
10092 SPARC_BUILTIN_EDGE8
,
10093 SPARC_BUILTIN_EDGE8L
,
10094 SPARC_BUILTIN_EDGE16
,
10095 SPARC_BUILTIN_EDGE16L
,
10096 SPARC_BUILTIN_EDGE32
,
10097 SPARC_BUILTIN_EDGE32L
,
10098 SPARC_BUILTIN_FCMPLE16
,
10099 SPARC_BUILTIN_FCMPLE32
,
10100 SPARC_BUILTIN_FCMPNE16
,
10101 SPARC_BUILTIN_FCMPNE32
,
10102 SPARC_BUILTIN_FCMPGT16
,
10103 SPARC_BUILTIN_FCMPGT32
,
10104 SPARC_BUILTIN_FCMPEQ16
,
10105 SPARC_BUILTIN_FCMPEQ32
,
10106 SPARC_BUILTIN_FPADD16
,
10107 SPARC_BUILTIN_FPADD16S
,
10108 SPARC_BUILTIN_FPADD32
,
10109 SPARC_BUILTIN_FPADD32S
,
10110 SPARC_BUILTIN_FPSUB16
,
10111 SPARC_BUILTIN_FPSUB16S
,
10112 SPARC_BUILTIN_FPSUB32
,
10113 SPARC_BUILTIN_FPSUB32S
,
10114 SPARC_BUILTIN_ARRAY8
,
10115 SPARC_BUILTIN_ARRAY16
,
10116 SPARC_BUILTIN_ARRAY32
,
10118 /* VIS 2.0 builtins. */
10119 SPARC_BUILTIN_EDGE8N
,
10120 SPARC_BUILTIN_EDGE8LN
,
10121 SPARC_BUILTIN_EDGE16N
,
10122 SPARC_BUILTIN_EDGE16LN
,
10123 SPARC_BUILTIN_EDGE32N
,
10124 SPARC_BUILTIN_EDGE32LN
,
10125 SPARC_BUILTIN_BMASK
,
10126 SPARC_BUILTIN_BSHUFFLEV4HI
,
10127 SPARC_BUILTIN_BSHUFFLEV8QI
,
10128 SPARC_BUILTIN_BSHUFFLEV2SI
,
10129 SPARC_BUILTIN_BSHUFFLEDI
,
10131 /* VIS 3.0 builtins. */
10132 SPARC_BUILTIN_CMASK8
,
10133 SPARC_BUILTIN_CMASK16
,
10134 SPARC_BUILTIN_CMASK32
,
10135 SPARC_BUILTIN_FCHKSM16
,
10136 SPARC_BUILTIN_FSLL16
,
10137 SPARC_BUILTIN_FSLAS16
,
10138 SPARC_BUILTIN_FSRL16
,
10139 SPARC_BUILTIN_FSRA16
,
10140 SPARC_BUILTIN_FSLL32
,
10141 SPARC_BUILTIN_FSLAS32
,
10142 SPARC_BUILTIN_FSRL32
,
10143 SPARC_BUILTIN_FSRA32
,
10144 SPARC_BUILTIN_PDISTN
,
10145 SPARC_BUILTIN_FMEAN16
,
10146 SPARC_BUILTIN_FPADD64
,
10147 SPARC_BUILTIN_FPSUB64
,
10148 SPARC_BUILTIN_FPADDS16
,
10149 SPARC_BUILTIN_FPADDS16S
,
10150 SPARC_BUILTIN_FPSUBS16
,
10151 SPARC_BUILTIN_FPSUBS16S
,
10152 SPARC_BUILTIN_FPADDS32
,
10153 SPARC_BUILTIN_FPADDS32S
,
10154 SPARC_BUILTIN_FPSUBS32
,
10155 SPARC_BUILTIN_FPSUBS32S
,
10156 SPARC_BUILTIN_FUCMPLE8
,
10157 SPARC_BUILTIN_FUCMPNE8
,
10158 SPARC_BUILTIN_FUCMPGT8
,
10159 SPARC_BUILTIN_FUCMPEQ8
,
10160 SPARC_BUILTIN_FHADDS
,
10161 SPARC_BUILTIN_FHADDD
,
10162 SPARC_BUILTIN_FHSUBS
,
10163 SPARC_BUILTIN_FHSUBD
,
10164 SPARC_BUILTIN_FNHADDS
,
10165 SPARC_BUILTIN_FNHADDD
,
10166 SPARC_BUILTIN_UMULXHI
,
10167 SPARC_BUILTIN_XMULX
,
10168 SPARC_BUILTIN_XMULXHI
,
10173 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10174 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10176 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10177 function decl or NULL_TREE if the builtin was not added. */
10180 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10184 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10188 sparc_builtins
[code
] = t
;
10189 sparc_builtins_icode
[code
] = icode
;
10195 /* Likewise, but also marks the function as "const". */
10198 def_builtin_const (const char *name
, enum insn_code icode
,
10199 enum sparc_builtins code
, tree type
)
10201 tree t
= def_builtin (name
, icode
, code
, type
);
10204 TREE_READONLY (t
) = 1;
10209 /* Implement the TARGET_INIT_BUILTINS target hook.
10210 Create builtin functions for special SPARC instructions. */
10213 sparc_init_builtins (void)
10216 sparc_fpu_init_builtins ();
10219 sparc_vis_init_builtins ();
10222 /* Create builtin functions for FPU instructions. */
10225 sparc_fpu_init_builtins (void)
10228 = build_function_type_list (void_type_node
,
10229 build_pointer_type (unsigned_type_node
), 0);
10230 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10231 SPARC_BUILTIN_LDFSR
, ftype
);
10232 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10233 SPARC_BUILTIN_STFSR
, ftype
);
10236 /* Create builtin functions for VIS instructions. */
10239 sparc_vis_init_builtins (void)
10241 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10242 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10243 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10244 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10245 tree v2si
= build_vector_type (intSI_type_node
, 2);
10246 tree v1si
= build_vector_type (intSI_type_node
, 1);
10248 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
10249 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
10250 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
10251 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
10252 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
10253 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
10254 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
10255 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
10256 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
10257 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
10258 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
10259 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
10260 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
10261 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
10262 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
10264 intDI_type_node
, 0);
10265 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
10267 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
10269 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
10271 intDI_type_node
, 0);
10272 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
10274 intSI_type_node
, 0);
10275 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
10277 intSI_type_node
, 0);
10278 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
10280 intDI_type_node
, 0);
10281 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
10284 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
10287 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
10289 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
10291 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
10293 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
10295 tree void_ftype_di
= build_function_type_list (void_type_node
,
10296 intDI_type_node
, 0);
10297 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
10298 void_type_node
, 0);
10299 tree void_ftype_si
= build_function_type_list (void_type_node
,
10300 intSI_type_node
, 0);
10301 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
10303 float_type_node
, 0);
10304 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
10306 double_type_node
, 0);
10308 /* Packing and expanding vectors. */
10309 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
10310 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
10311 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
10312 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
10313 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
10314 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
10315 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
10316 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
10317 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
10318 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
10320 /* Multiplications. */
10321 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
10322 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
10323 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
10324 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
10325 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
10326 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
10327 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
10328 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
10329 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
10330 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
10331 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
10332 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
10333 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
10334 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
10336 /* Data aligning. */
10337 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
10338 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
10339 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
10340 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
10341 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
10342 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
10343 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
10344 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
10346 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
10347 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
10348 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
10349 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
10353 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
10354 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
10355 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
10356 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
10360 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
10361 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
10362 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
10363 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
10366 /* Pixel distance. */
10367 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
10368 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
10370 /* Edge handling. */
10373 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
10374 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
10375 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
10376 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
10377 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
10378 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
10379 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
10380 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
10381 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
10382 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
10383 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
10384 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
10388 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
10389 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
10390 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
10391 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
10392 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
10393 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
10394 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
10395 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
10396 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
10397 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
10398 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
10399 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
10402 /* Pixel compare. */
10405 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
10406 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
10407 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
10408 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
10409 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
10410 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
10411 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
10412 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
10413 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
10414 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
10415 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
10416 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
10417 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
10418 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
10419 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
10420 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
10424 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
10425 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
10426 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
10427 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
10428 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
10429 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
10430 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
10431 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
10432 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
10433 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
10434 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
10435 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
10436 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
10437 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
10438 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
10439 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
10442 /* Addition and subtraction. */
10443 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
10444 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
10445 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
10446 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
10447 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
10448 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
10449 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
10450 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
10451 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
10452 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
10453 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
10454 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
10455 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
10456 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
10457 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
10458 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
10460 /* Three-dimensional array addressing. */
10463 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
10464 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
10465 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
10466 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
10467 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
10468 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
10472 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
10473 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
10474 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
10475 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
10476 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
10477 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
10482 /* Edge handling. */
10485 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
10486 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
10487 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
10488 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
10489 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
10490 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
10491 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
10492 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
10493 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
10494 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
10495 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
10496 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
10500 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
10501 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
10502 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
10503 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
10504 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
10505 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
10506 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
10507 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
10508 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
10509 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
10510 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
10511 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
10514 /* Byte mask and shuffle. */
10516 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
10517 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
10519 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
10520 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
10521 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
10522 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
10523 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
10524 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
10525 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
10526 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
10527 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
10528 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
10535 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
10536 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
10537 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
10538 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
10539 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
10540 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
10544 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
10545 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
10546 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
10547 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
10548 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
10549 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
10552 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
10553 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
10555 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
10556 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
10557 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
10558 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
10559 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
10560 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
10561 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
10562 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
10563 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
10564 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
10565 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
10566 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
10567 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
10568 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
10569 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
10570 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
10573 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
10574 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
10576 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
10577 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
10579 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
10580 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
10581 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
10582 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
10583 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
10584 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
10586 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
10587 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
10588 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
10589 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
10590 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
10591 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
10592 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
10593 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
10594 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
10595 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
10596 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
10597 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
10598 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
10599 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
10600 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
10601 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
10605 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
10606 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
10607 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
10608 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
10609 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
10610 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
10611 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
10612 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
10616 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
10617 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
10618 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
10619 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
10620 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
10621 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
10622 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
10623 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
10626 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
10627 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
10628 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
10629 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
10630 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
10631 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
10632 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
10633 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
10634 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
10635 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
10636 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
10637 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
10639 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
10640 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
10641 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
10642 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
10643 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
10644 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
10648 /* Implement TARGET_BUILTIN_DECL hook. */
10651 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10653 if (code
>= SPARC_BUILTIN_MAX
)
10654 return error_mark_node
;
10656 return sparc_builtins
[code
];
10659 /* Implemented TARGET_EXPAND_BUILTIN hook. */
10662 sparc_expand_builtin (tree exp
, rtx target
,
10663 rtx subtarget ATTRIBUTE_UNUSED
,
10664 enum machine_mode tmode ATTRIBUTE_UNUSED
,
10665 int ignore ATTRIBUTE_UNUSED
)
10667 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10668 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10669 enum insn_code icode
= sparc_builtins_icode
[code
];
10670 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
10671 call_expr_arg_iterator iter
;
10678 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10680 || GET_MODE (target
) != tmode
10681 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10682 op
[0] = gen_reg_rtx (tmode
);
10687 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
10689 const struct insn_operand_data
*insn_op
;
10692 if (arg
== error_mark_node
)
10696 idx
= arg_count
- !nonvoid
;
10697 insn_op
= &insn_data
[icode
].operand
[idx
];
10698 op
[arg_count
] = expand_normal (arg
);
10700 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
10702 if (!address_operand (op
[arg_count
], SImode
))
10704 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
10705 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
10707 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
10710 else if (insn_op
->mode
== V1DImode
10711 && GET_MODE (op
[arg_count
]) == DImode
)
10712 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
10714 else if (insn_op
->mode
== V1SImode
10715 && GET_MODE (op
[arg_count
]) == SImode
)
10716 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
10718 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
10720 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
10726 pat
= GEN_FCN (icode
) (op
[0]);
10730 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
10732 pat
= GEN_FCN (icode
) (op
[1]);
10735 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
10738 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
10741 gcc_unreachable ();
10749 return (nonvoid
? op
[0] : const0_rtx
);
10752 /* Return the upper 16 bits of the 8x16 multiplication. */
10755 sparc_vis_mul8x16 (int e8
, int e16
)
10757 return (e8
* e16
+ 128) / 256;
10760 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
10761 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
10764 sparc_handle_vis_mul8x16 (tree
*n_elts
, enum sparc_builtins fncode
,
10765 tree inner_type
, tree cst0
, tree cst1
)
10767 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
10772 case SPARC_BUILTIN_FMUL8X16
:
10773 for (i
= 0; i
< num
; ++i
)
10776 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10777 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
10778 n_elts
[i
] = build_int_cst (inner_type
, val
);
10782 case SPARC_BUILTIN_FMUL8X16AU
:
10783 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
10785 for (i
= 0; i
< num
; ++i
)
10788 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10790 n_elts
[i
] = build_int_cst (inner_type
, val
);
10794 case SPARC_BUILTIN_FMUL8X16AL
:
10795 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
10797 for (i
= 0; i
< num
; ++i
)
10800 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10802 n_elts
[i
] = build_int_cst (inner_type
, val
);
10807 gcc_unreachable ();
10811 /* Implement TARGET_FOLD_BUILTIN hook.
10813 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
10814 result of the function call is ignored. NULL_TREE is returned if the
10815 function could not be folded. */
10818 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
10819 tree
*args
, bool ignore
)
10821 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10822 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
10823 tree arg0
, arg1
, arg2
;
10828 case SPARC_BUILTIN_LDFSR
:
10829 case SPARC_BUILTIN_STFSR
:
10830 case SPARC_BUILTIN_ALIGNADDR
:
10831 case SPARC_BUILTIN_WRGSR
:
10832 case SPARC_BUILTIN_BMASK
:
10833 case SPARC_BUILTIN_CMASK8
:
10834 case SPARC_BUILTIN_CMASK16
:
10835 case SPARC_BUILTIN_CMASK32
:
10839 return build_zero_cst (rtype
);
10844 case SPARC_BUILTIN_FEXPAND
:
10848 if (TREE_CODE (arg0
) == VECTOR_CST
)
10850 tree inner_type
= TREE_TYPE (rtype
);
10854 n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10855 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10856 n_elts
[i
] = build_int_cst (inner_type
,
10858 (VECTOR_CST_ELT (arg0
, i
)) << 4);
10859 return build_vector (rtype
, n_elts
);
10863 case SPARC_BUILTIN_FMUL8X16
:
10864 case SPARC_BUILTIN_FMUL8X16AU
:
10865 case SPARC_BUILTIN_FMUL8X16AL
:
10871 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10873 tree inner_type
= TREE_TYPE (rtype
);
10874 tree
*n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10875 sparc_handle_vis_mul8x16 (n_elts
, code
, inner_type
, arg0
, arg1
);
10876 return build_vector (rtype
, n_elts
);
10880 case SPARC_BUILTIN_FPMERGE
:
10886 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10888 tree
*n_elts
= XALLOCAVEC (tree
, 2 * VECTOR_CST_NELTS (arg0
));
10890 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10892 n_elts
[2*i
] = VECTOR_CST_ELT (arg0
, i
);
10893 n_elts
[2*i
+1] = VECTOR_CST_ELT (arg1
, i
);
10896 return build_vector (rtype
, n_elts
);
10900 case SPARC_BUILTIN_PDIST
:
10901 case SPARC_BUILTIN_PDISTN
:
10906 if (code
== SPARC_BUILTIN_PDIST
)
10912 arg2
= integer_zero_node
;
10914 if (TREE_CODE (arg0
) == VECTOR_CST
10915 && TREE_CODE (arg1
) == VECTOR_CST
10916 && TREE_CODE (arg2
) == INTEGER_CST
)
10918 bool overflow
= false;
10919 widest_int result
= wi::to_widest (arg2
);
10923 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10925 tree e0
= VECTOR_CST_ELT (arg0
, i
);
10926 tree e1
= VECTOR_CST_ELT (arg1
, i
);
10928 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
10930 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
10931 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
10932 if (wi::neg_p (tmp
))
10933 tmp
= wi::neg (tmp
, &neg2_ovf
);
10936 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
10937 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
10940 gcc_assert (!overflow
);
10942 return wide_int_to_tree (rtype
, result
);
10952 /* ??? This duplicates information provided to the compiler by the
10953 ??? scheduler description. Some day, teach genautomata to output
10954 ??? the latencies and then CSE will just use that. */
10957 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
10958 int *total
, bool speed ATTRIBUTE_UNUSED
)
10960 enum machine_mode mode
= GET_MODE (x
);
10961 bool float_mode_p
= FLOAT_MODE_P (mode
);
10966 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
10984 if (GET_MODE (x
) == VOIDmode
10985 && ((CONST_DOUBLE_HIGH (x
) == 0
10986 && CONST_DOUBLE_LOW (x
) < 0x1000)
10987 || (CONST_DOUBLE_HIGH (x
) == -1
10988 && CONST_DOUBLE_LOW (x
) < 0
10989 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
10996 /* If outer-code was a sign or zero extension, a cost
10997 of COSTS_N_INSNS (1) was already added in. This is
10998 why we are subtracting it back out. */
10999 if (outer_code
== ZERO_EXTEND
)
11001 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
11003 else if (outer_code
== SIGN_EXTEND
)
11005 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
11007 else if (float_mode_p
)
11009 *total
= sparc_costs
->float_load
;
11013 *total
= sparc_costs
->int_load
;
11021 *total
= sparc_costs
->float_plusminus
;
11023 *total
= COSTS_N_INSNS (1);
11030 gcc_assert (float_mode_p
);
11031 *total
= sparc_costs
->float_mul
;
11034 if (GET_CODE (sub
) == NEG
)
11035 sub
= XEXP (sub
, 0);
11036 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
11039 if (GET_CODE (sub
) == NEG
)
11040 sub
= XEXP (sub
, 0);
11041 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
11047 *total
= sparc_costs
->float_mul
;
11048 else if (! TARGET_HARD_MUL
)
11049 *total
= COSTS_N_INSNS (25);
11055 if (sparc_costs
->int_mul_bit_factor
)
11059 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11061 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
11062 for (nbits
= 0; value
!= 0; value
&= value
- 1)
11065 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
11066 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
11068 rtx x1
= XEXP (x
, 1);
11069 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
11070 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
11072 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
11074 for (; value2
!= 0; value2
&= value2
- 1)
11082 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
11083 bit_cost
= COSTS_N_INSNS (bit_cost
);
11086 if (mode
== DImode
)
11087 *total
= sparc_costs
->int_mulX
+ bit_cost
;
11089 *total
= sparc_costs
->int_mul
+ bit_cost
;
11096 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
11105 if (mode
== DFmode
)
11106 *total
= sparc_costs
->float_div_df
;
11108 *total
= sparc_costs
->float_div_sf
;
11112 if (mode
== DImode
)
11113 *total
= sparc_costs
->int_divX
;
11115 *total
= sparc_costs
->int_div
;
11120 if (! float_mode_p
)
11122 *total
= COSTS_N_INSNS (1);
11129 case UNSIGNED_FLOAT
:
11133 case FLOAT_TRUNCATE
:
11134 *total
= sparc_costs
->float_move
;
11138 if (mode
== DFmode
)
11139 *total
= sparc_costs
->float_sqrt_df
;
11141 *total
= sparc_costs
->float_sqrt_sf
;
11146 *total
= sparc_costs
->float_cmp
;
11148 *total
= COSTS_N_INSNS (1);
11153 *total
= sparc_costs
->float_cmove
;
11155 *total
= sparc_costs
->int_cmove
;
11159 /* Handle the NAND vector patterns. */
11160 if (sparc_vector_mode_supported_p (GET_MODE (x
))
11161 && GET_CODE (XEXP (x
, 0)) == NOT
11162 && GET_CODE (XEXP (x
, 1)) == NOT
)
11164 *total
= COSTS_N_INSNS (1);
11175 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11178 general_or_i64_p (reg_class_t rclass
)
11180 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
11183 /* Implement TARGET_REGISTER_MOVE_COST. */
11186 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11187 reg_class_t from
, reg_class_t to
)
11189 bool need_memory
= false;
11191 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
11192 need_memory
= true;
11193 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
11194 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
11198 int size
= GET_MODE_SIZE (mode
);
11199 if (size
== 8 || size
== 4)
11201 if (! TARGET_ARCH32
|| size
== 4)
11207 need_memory
= true;
11212 if (sparc_cpu
== PROCESSOR_ULTRASPARC
11213 || sparc_cpu
== PROCESSOR_ULTRASPARC3
11214 || sparc_cpu
== PROCESSOR_NIAGARA
11215 || sparc_cpu
== PROCESSOR_NIAGARA2
11216 || sparc_cpu
== PROCESSOR_NIAGARA3
11217 || sparc_cpu
== PROCESSOR_NIAGARA4
)
11226 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11227 This is achieved by means of a manual dynamic stack space allocation in
11228 the current frame. We make the assumption that SEQ doesn't contain any
11229 function calls, with the possible exception of calls to the GOT helper. */
11232 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
11234 /* We must preserve the lowest 16 words for the register save area. */
11235 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
11236 /* We really need only 2 words of fresh stack space. */
11237 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
11240 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11241 SPARC_STACK_BIAS
+ offset
));
11243 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
11244 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
11246 emit_insn (gen_rtx_SET (VOIDmode
,
11247 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
11251 emit_insn (gen_rtx_SET (VOIDmode
,
11253 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
11254 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
11255 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
11258 /* Output the assembler code for a thunk function. THUNK_DECL is the
11259 declaration for the thunk function itself, FUNCTION is the decl for
11260 the target function. DELTA is an immediate constant offset to be
11261 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11262 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11265 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11266 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11269 rtx this_rtx
, funexp
;
11271 unsigned int int_arg_first
;
11273 reload_completed
= 1;
11274 epilogue_completed
= 1;
11276 emit_note (NOTE_INSN_PROLOGUE_END
);
11280 sparc_leaf_function_p
= 1;
11282 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11284 else if (flag_delayed_branch
)
11286 /* We will emit a regular sibcall below, so we need to instruct
11287 output_sibcall that we are in a leaf function. */
11288 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
11290 /* This will cause final.c to invoke leaf_renumber_regs so we
11291 must behave as if we were in a not-yet-leafified function. */
11292 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
11296 /* We will emit the sibcall manually below, so we will need to
11297 manually spill non-leaf registers. */
11298 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
11300 /* We really are in a leaf function. */
11301 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11304 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11305 returns a structure, the structure return pointer is there instead. */
11307 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11308 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
11310 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
11312 /* Add DELTA. When possible use a plain add, otherwise load it into
11313 a register first. */
11316 rtx delta_rtx
= GEN_INT (delta
);
11318 if (! SPARC_SIMM13_P (delta
))
11320 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11321 emit_move_insn (scratch
, delta_rtx
);
11322 delta_rtx
= scratch
;
11325 /* THIS_RTX += DELTA. */
11326 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
11329 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
11332 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
11333 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11335 gcc_assert (vcall_offset
< 0);
11337 /* SCRATCH = *THIS_RTX. */
11338 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
11340 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
11341 may not have any available scratch register at this point. */
11342 if (SPARC_SIMM13_P (vcall_offset
))
11344 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
11345 else if (! fixed_regs
[5]
11346 /* The below sequence is made up of at least 2 insns,
11347 while the default method may need only one. */
11348 && vcall_offset
< -8192)
11350 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
11351 emit_move_insn (scratch2
, vcall_offset_rtx
);
11352 vcall_offset_rtx
= scratch2
;
11356 rtx increment
= GEN_INT (-4096);
11358 /* VCALL_OFFSET is a negative number whose typical range can be
11359 estimated as -32768..0 in 32-bit mode. In almost all cases
11360 it is therefore cheaper to emit multiple add insns than
11361 spilling and loading the constant into a register (at least
11363 while (! SPARC_SIMM13_P (vcall_offset
))
11365 emit_insn (gen_add2_insn (scratch
, increment
));
11366 vcall_offset
+= 4096;
11368 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
11371 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
11372 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
11373 gen_rtx_PLUS (Pmode
,
11375 vcall_offset_rtx
)));
11377 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
11378 emit_insn (gen_add2_insn (this_rtx
, scratch
));
11381 /* Generate a tail call to the target function. */
11382 if (! TREE_USED (function
))
11384 assemble_external (function
);
11385 TREE_USED (function
) = 1;
11387 funexp
= XEXP (DECL_RTL (function
), 0);
11389 if (flag_delayed_branch
)
11391 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
11392 insn
= emit_call_insn (gen_sibcall (funexp
));
11393 SIBLING_CALL_P (insn
) = 1;
11397 /* The hoops we have to jump through in order to generate a sibcall
11398 without using delay slots... */
11399 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
11403 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
11405 load_got_register (); /* clobbers %o7 */
11406 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
11407 seq
= get_insns ();
11409 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
11411 else if (TARGET_ARCH32
)
11413 emit_insn (gen_rtx_SET (VOIDmode
,
11415 gen_rtx_HIGH (SImode
, funexp
)));
11416 emit_insn (gen_rtx_SET (VOIDmode
,
11418 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
11420 else /* TARGET_ARCH64 */
11422 switch (sparc_cmodel
)
11426 /* The destination can serve as a temporary. */
11427 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
11432 /* The destination cannot serve as a temporary. */
11433 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
11435 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
11436 seq
= get_insns ();
11438 emit_and_preserve (seq
, spill_reg
, 0);
11442 gcc_unreachable ();
11446 emit_jump_insn (gen_indirect_jump (scratch
));
11451 /* Run just enough of rest_of_compilation to get the insns emitted.
11452 There's not really enough bulk here to make other passes such as
11453 instruction scheduling worth while. Note that use_thunk calls
11454 assemble_start_function and assemble_end_function. */
11455 insn
= get_insns ();
11456 shorten_branches (insn
);
11457 final_start_function (insn
, file
, 1);
11458 final (insn
, file
, 1);
11459 final_end_function ();
11461 reload_completed
= 0;
11462 epilogue_completed
= 0;
11465 /* Return true if sparc_output_mi_thunk would be able to output the
11466 assembler code for the thunk function specified by the arguments
11467 it is passed, and false otherwise. */
11469 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
11470 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
11471 HOST_WIDE_INT vcall_offset
,
11472 const_tree function ATTRIBUTE_UNUSED
)
11474 /* Bound the loop used in the default method above. */
11475 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
11478 /* How to allocate a 'struct machine_function'. */
11480 static struct machine_function
*
11481 sparc_init_machine_status (void)
11483 return ggc_cleared_alloc
<machine_function
> ();
11486 /* Locate some local-dynamic symbol still in use by this function
11487 so that we can print its name in local-dynamic base patterns. */
11489 static const char *
11490 get_some_local_dynamic_name (void)
11494 if (cfun
->machine
->some_ld_name
)
11495 return cfun
->machine
->some_ld_name
;
11497 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
11499 && for_each_rtx (&PATTERN (insn
), get_some_local_dynamic_name_1
, 0))
11500 return cfun
->machine
->some_ld_name
;
11502 gcc_unreachable ();
11506 get_some_local_dynamic_name_1 (rtx
*px
, void *data ATTRIBUTE_UNUSED
)
11511 && GET_CODE (x
) == SYMBOL_REF
11512 && SYMBOL_REF_TLS_MODEL (x
) == TLS_MODEL_LOCAL_DYNAMIC
)
11514 cfun
->machine
->some_ld_name
= XSTR (x
, 0);
11521 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11522 We need to emit DTP-relative relocations. */
11525 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
11530 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
11533 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
11536 gcc_unreachable ();
11538 output_addr_const (file
, x
);
11542 /* Do whatever processing is required at the end of a file. */
11545 sparc_file_end (void)
11547 /* If we need to emit the special GOT helper function, do so now. */
11548 if (got_helper_rtx
)
11550 const char *name
= XSTR (got_helper_rtx
, 0);
11551 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
11552 #ifdef DWARF2_UNWIND_INFO
11556 if (USE_HIDDEN_LINKONCE
)
11558 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
11559 get_identifier (name
),
11560 build_function_type_list (void_type_node
,
11562 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
11563 NULL_TREE
, void_type_node
);
11564 TREE_PUBLIC (decl
) = 1;
11565 TREE_STATIC (decl
) = 1;
11566 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
11567 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
11568 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
11569 resolve_unique_section (decl
, 0, flag_function_sections
);
11570 allocate_struct_function (decl
, true);
11571 cfun
->is_thunk
= 1;
11572 current_function_decl
= decl
;
11573 init_varasm_status ();
11574 assemble_start_function (decl
, name
);
11578 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
11579 switch_to_section (text_section
);
11581 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
11582 ASM_OUTPUT_LABEL (asm_out_file
, name
);
11585 #ifdef DWARF2_UNWIND_INFO
11586 do_cfi
= dwarf2out_do_cfi_asm ();
11588 fprintf (asm_out_file
, "\t.cfi_startproc\n");
11590 if (flag_delayed_branch
)
11591 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
11592 reg_name
, reg_name
);
11594 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
11595 reg_name
, reg_name
);
11596 #ifdef DWARF2_UNWIND_INFO
11598 fprintf (asm_out_file
, "\t.cfi_endproc\n");
11602 if (NEED_INDICATE_EXEC_STACK
)
11603 file_end_indicate_exec_stack ();
11605 #ifdef TARGET_SOLARIS
11606 solaris_file_end ();
11610 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11611 /* Implement TARGET_MANGLE_TYPE. */
11613 static const char *
11614 sparc_mangle_type (const_tree type
)
11617 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
11618 && TARGET_LONG_DOUBLE_128
)
11621 /* For all other types, use normal C++ mangling. */
11626 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
11627 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
11628 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
11631 sparc_emit_membar_for_model (enum memmodel model
,
11632 int load_store
, int before_after
)
11634 /* Bits for the MEMBAR mmask field. */
11635 const int LoadLoad
= 1;
11636 const int StoreLoad
= 2;
11637 const int LoadStore
= 4;
11638 const int StoreStore
= 8;
11640 int mm
= 0, implied
= 0;
11642 switch (sparc_memory_model
)
11645 /* Sequential Consistency. All memory transactions are immediately
11646 visible in sequential execution order. No barriers needed. */
11647 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
11651 /* Total Store Ordering: all memory transactions with store semantics
11652 are followed by an implied StoreStore. */
11653 implied
|= StoreStore
;
11655 /* If we're not looking for a raw barrer (before+after), then atomic
11656 operations get the benefit of being both load and store. */
11657 if (load_store
== 3 && before_after
== 1)
11658 implied
|= StoreLoad
;
11662 /* Partial Store Ordering: all memory transactions with load semantics
11663 are followed by an implied LoadLoad | LoadStore. */
11664 implied
|= LoadLoad
| LoadStore
;
11666 /* If we're not looking for a raw barrer (before+after), then atomic
11667 operations get the benefit of being both load and store. */
11668 if (load_store
== 3 && before_after
== 2)
11669 implied
|= StoreLoad
| StoreStore
;
11673 /* Relaxed Memory Ordering: no implicit bits. */
11677 gcc_unreachable ();
11680 if (before_after
& 1)
11682 if (model
== MEMMODEL_RELEASE
11683 || model
== MEMMODEL_ACQ_REL
11684 || model
== MEMMODEL_SEQ_CST
)
11686 if (load_store
& 1)
11687 mm
|= LoadLoad
| StoreLoad
;
11688 if (load_store
& 2)
11689 mm
|= LoadStore
| StoreStore
;
11692 if (before_after
& 2)
11694 if (model
== MEMMODEL_ACQUIRE
11695 || model
== MEMMODEL_ACQ_REL
11696 || model
== MEMMODEL_SEQ_CST
)
11698 if (load_store
& 1)
11699 mm
|= LoadLoad
| LoadStore
;
11700 if (load_store
& 2)
11701 mm
|= StoreLoad
| StoreStore
;
11705 /* Remove the bits implied by the system memory model. */
11708 /* For raw barriers (before+after), always emit a barrier.
11709 This will become a compile-time barrier if needed. */
11710 if (mm
|| before_after
== 3)
11711 emit_insn (gen_membar (GEN_INT (mm
)));
11714 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
11715 compare and swap on the word containing the byte or half-word. */
11718 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
11719 rtx oldval
, rtx newval
)
11721 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
11722 rtx addr
= gen_reg_rtx (Pmode
);
11723 rtx off
= gen_reg_rtx (SImode
);
11724 rtx oldv
= gen_reg_rtx (SImode
);
11725 rtx newv
= gen_reg_rtx (SImode
);
11726 rtx oldvalue
= gen_reg_rtx (SImode
);
11727 rtx newvalue
= gen_reg_rtx (SImode
);
11728 rtx res
= gen_reg_rtx (SImode
);
11729 rtx resv
= gen_reg_rtx (SImode
);
11730 rtx memsi
, val
, mask
, end_label
, loop_label
, cc
;
11732 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
11733 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
11735 if (Pmode
!= SImode
)
11736 addr1
= gen_lowpart (SImode
, addr1
);
11737 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11738 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
11740 memsi
= gen_rtx_MEM (SImode
, addr
);
11741 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
11742 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
11744 val
= copy_to_reg (memsi
);
11746 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11747 gen_rtx_XOR (SImode
, off
,
11748 GEN_INT (GET_MODE (mem
) == QImode
11751 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11752 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
11754 if (GET_MODE (mem
) == QImode
)
11755 mask
= force_reg (SImode
, GEN_INT (0xff));
11757 mask
= force_reg (SImode
, GEN_INT (0xffff));
11759 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
11760 gen_rtx_ASHIFT (SImode
, mask
, off
)));
11762 emit_insn (gen_rtx_SET (VOIDmode
, val
,
11763 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11766 oldval
= gen_lowpart (SImode
, oldval
);
11767 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
11768 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
11770 newval
= gen_lowpart_common (SImode
, newval
);
11771 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
11772 gen_rtx_ASHIFT (SImode
, newval
, off
)));
11774 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
11775 gen_rtx_AND (SImode
, oldv
, mask
)));
11777 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
11778 gen_rtx_AND (SImode
, newv
, mask
)));
11780 end_label
= gen_label_rtx ();
11781 loop_label
= gen_label_rtx ();
11782 emit_label (loop_label
);
11784 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
11785 gen_rtx_IOR (SImode
, oldv
, val
)));
11787 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
11788 gen_rtx_IOR (SImode
, newv
, val
)));
11790 emit_move_insn (bool_result
, const1_rtx
);
11792 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
11794 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
11796 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
11797 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11800 emit_move_insn (bool_result
, const0_rtx
);
11802 cc
= gen_compare_reg_1 (NE
, resv
, val
);
11803 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
11805 /* Use cbranchcc4 to separate the compare and branch! */
11806 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
11807 cc
, const0_rtx
, loop_label
));
11809 emit_label (end_label
);
11811 emit_insn (gen_rtx_SET (VOIDmode
, res
,
11812 gen_rtx_AND (SImode
, res
, mask
)));
11814 emit_insn (gen_rtx_SET (VOIDmode
, res
,
11815 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
11817 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
11820 /* Expand code to perform a compare-and-swap. */
11823 sparc_expand_compare_and_swap (rtx operands
[])
11825 rtx bval
, retval
, mem
, oldval
, newval
;
11826 enum machine_mode mode
;
11827 enum memmodel model
;
11829 bval
= operands
[0];
11830 retval
= operands
[1];
11832 oldval
= operands
[3];
11833 newval
= operands
[4];
11834 model
= (enum memmodel
) INTVAL (operands
[6]);
11835 mode
= GET_MODE (mem
);
11837 sparc_emit_membar_for_model (model
, 3, 1);
11839 if (reg_overlap_mentioned_p (retval
, oldval
))
11840 oldval
= copy_to_reg (oldval
);
11842 if (mode
== QImode
|| mode
== HImode
)
11843 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
11846 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
11849 if (mode
== SImode
)
11850 gen
= gen_atomic_compare_and_swapsi_1
;
11852 gen
= gen_atomic_compare_and_swapdi_1
;
11853 emit_insn (gen (retval
, mem
, oldval
, newval
));
11855 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
11857 convert_move (bval
, x
, 1);
11860 sparc_emit_membar_for_model (model
, 3, 2);
11864 sparc_expand_vec_perm_bmask (enum machine_mode vmode
, rtx sel
)
11868 sel
= gen_lowpart (DImode
, sel
);
11872 /* inp = xxxxxxxAxxxxxxxB */
11873 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11874 NULL_RTX
, 1, OPTAB_DIRECT
);
11875 /* t_1 = ....xxxxxxxAxxx. */
11876 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11877 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
11878 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11879 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
11880 /* sel = .......B */
11881 /* t_1 = ...A.... */
11882 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11883 /* sel = ...A...B */
11884 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
11885 /* sel = AAAABBBB * 4 */
11886 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
11887 /* sel = { A*4, A*4+1, A*4+2, ... } */
11891 /* inp = xxxAxxxBxxxCxxxD */
11892 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11893 NULL_RTX
, 1, OPTAB_DIRECT
);
11894 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11895 NULL_RTX
, 1, OPTAB_DIRECT
);
11896 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
11897 NULL_RTX
, 1, OPTAB_DIRECT
);
11898 /* t_1 = ..xxxAxxxBxxxCxx */
11899 /* t_2 = ....xxxAxxxBxxxC */
11900 /* t_3 = ......xxxAxxxBxx */
11901 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11903 NULL_RTX
, 1, OPTAB_DIRECT
);
11904 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11906 NULL_RTX
, 1, OPTAB_DIRECT
);
11907 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
11908 GEN_INT (0x070000),
11909 NULL_RTX
, 1, OPTAB_DIRECT
);
11910 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
11911 GEN_INT (0x07000000),
11912 NULL_RTX
, 1, OPTAB_DIRECT
);
11913 /* sel = .......D */
11914 /* t_1 = .....C.. */
11915 /* t_2 = ...B.... */
11916 /* t_3 = .A...... */
11917 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11918 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
11919 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
11920 /* sel = .A.B.C.D */
11921 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
11922 /* sel = AABBCCDD * 2 */
11923 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
11924 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11928 /* input = xAxBxCxDxExFxGxH */
11929 sel
= expand_simple_binop (DImode
, AND
, sel
,
11930 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
11932 NULL_RTX
, 1, OPTAB_DIRECT
);
11933 /* sel = .A.B.C.D.E.F.G.H */
11934 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
11935 NULL_RTX
, 1, OPTAB_DIRECT
);
11936 /* t_1 = ..A.B.C.D.E.F.G. */
11937 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11938 NULL_RTX
, 1, OPTAB_DIRECT
);
11939 /* sel = .AABBCCDDEEFFGGH */
11940 sel
= expand_simple_binop (DImode
, AND
, sel
,
11941 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
11943 NULL_RTX
, 1, OPTAB_DIRECT
);
11944 /* sel = ..AB..CD..EF..GH */
11945 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11946 NULL_RTX
, 1, OPTAB_DIRECT
);
11947 /* t_1 = ....AB..CD..EF.. */
11948 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11949 NULL_RTX
, 1, OPTAB_DIRECT
);
11950 /* sel = ..ABABCDCDEFEFGH */
11951 sel
= expand_simple_binop (DImode
, AND
, sel
,
11952 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
11953 NULL_RTX
, 1, OPTAB_DIRECT
);
11954 /* sel = ....ABCD....EFGH */
11955 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11956 NULL_RTX
, 1, OPTAB_DIRECT
);
11957 /* t_1 = ........ABCD.... */
11958 sel
= gen_lowpart (SImode
, sel
);
11959 t_1
= gen_lowpart (SImode
, t_1
);
11963 gcc_unreachable ();
11966 /* Always perform the final addition/merge within the bmask insn. */
11967 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, t_1
));
11970 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11973 sparc_frame_pointer_required (void)
11975 /* If the stack pointer is dynamically modified in the function, it cannot
11976 serve as the frame pointer. */
11977 if (cfun
->calls_alloca
)
11980 /* If the function receives nonlocal gotos, it needs to save the frame
11981 pointer in the nonlocal_goto_save_area object. */
11982 if (cfun
->has_nonlocal_label
)
11985 /* In flat mode, that's it. */
11989 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11990 return !(crtl
->is_leaf
&& only_leaf_regs_used ());
11993 /* The way this is structured, we can't eliminate SFP in favor of SP
11994 if the frame pointer is required: we want to use the SFP->HFP elimination
11995 in that case. But the test in update_eliminables doesn't know we are
11996 assuming below that we only do the former elimination. */
11999 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
12001 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
12004 /* Return the hard frame pointer directly to bypass the stack bias. */
12007 sparc_builtin_setjmp_frame_value (void)
12009 return hard_frame_pointer_rtx
;
12012 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
12013 they won't be allocated. */
12016 sparc_conditional_register_usage (void)
12018 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
12020 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12021 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
12023 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
12024 /* then honor it. */
12025 if (TARGET_ARCH32
&& fixed_regs
[5])
12027 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
12032 for (regno
= SPARC_FIRST_V9_FP_REG
;
12033 regno
<= SPARC_LAST_V9_FP_REG
;
12035 fixed_regs
[regno
] = 1;
12036 /* %fcc0 is used by v8 and v9. */
12037 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
12038 regno
<= SPARC_LAST_V9_FCC_REG
;
12040 fixed_regs
[regno
] = 1;
12045 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
12046 fixed_regs
[regno
] = 1;
12048 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12049 /* then honor it. Likewise with g3 and g4. */
12050 if (fixed_regs
[2] == 2)
12051 fixed_regs
[2] = ! TARGET_APP_REGS
;
12052 if (fixed_regs
[3] == 2)
12053 fixed_regs
[3] = ! TARGET_APP_REGS
;
12054 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
12055 fixed_regs
[4] = ! TARGET_APP_REGS
;
12056 else if (TARGET_CM_EMBMEDANY
)
12058 else if (fixed_regs
[4] == 2)
12063 /* Disable leaf functions. */
12064 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
12065 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12066 leaf_reg_remap
[regno
] = regno
;
12069 global_regs
[SPARC_GSR_REG
] = 1;
12072 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12074 - We can't load constants into FP registers.
12075 - We can't load FP constants into integer registers when soft-float,
12076 because there is no soft-float pattern with a r/F constraint.
12077 - We can't load FP constants into integer registers for TFmode unless
12078 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12079 - Try and reload integer constants (symbolic or otherwise) back into
12080 registers directly, rather than having them dumped to memory. */
12083 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
12085 enum machine_mode mode
= GET_MODE (x
);
12086 if (CONSTANT_P (x
))
12088 if (FP_REG_CLASS_P (rclass
)
12089 || rclass
== GENERAL_OR_FP_REGS
12090 || rclass
== GENERAL_OR_EXTRA_FP_REGS
12091 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
12092 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
12095 if (GET_MODE_CLASS (mode
) == MODE_INT
)
12096 return GENERAL_REGS
;
12098 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
12100 if (! FP_REG_CLASS_P (rclass
)
12101 || !(const_zero_operand (x
, mode
)
12102 || const_all_ones_operand (x
, mode
)))
12109 && (rclass
== EXTRA_FP_REGS
12110 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
12112 int regno
= true_regnum (x
);
12114 if (SPARC_INT_REG_P (regno
))
12115 return (rclass
== EXTRA_FP_REGS
12116 ? FP_REGS
: GENERAL_OR_FP_REGS
);
12122 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
12123 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
12126 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
12130 gcc_assert (! TARGET_ARCH64
);
12132 if (sparc_check_64 (operands
[1], insn
) <= 0)
12133 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
12134 if (which_alternative
== 1)
12135 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
12136 if (GET_CODE (operands
[2]) == CONST_INT
)
12138 if (which_alternative
== 1)
12140 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12141 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
12142 output_asm_insn (mulstr
, operands
);
12143 return "srlx\t%L0, 32, %H0";
12147 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12148 output_asm_insn ("or\t%L1, %3, %3", operands
);
12149 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
12150 output_asm_insn (mulstr
, operands
);
12151 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12152 return "mov\t%3, %L0";
12155 else if (rtx_equal_p (operands
[1], operands
[2]))
12157 if (which_alternative
== 1)
12159 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12160 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
12161 output_asm_insn (mulstr
, operands
);
12162 return "srlx\t%L0, 32, %H0";
12166 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12167 output_asm_insn ("or\t%L1, %3, %3", operands
);
12168 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
12169 output_asm_insn (mulstr
, operands
);
12170 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12171 return "mov\t%3, %L0";
12174 if (sparc_check_64 (operands
[2], insn
) <= 0)
12175 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
12176 if (which_alternative
== 1)
12178 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12179 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
12180 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
12181 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
12182 output_asm_insn (mulstr
, operands
);
12183 return "srlx\t%L0, 32, %H0";
12187 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12188 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
12189 output_asm_insn ("or\t%L1, %3, %3", operands
);
12190 output_asm_insn ("or\t%L2, %4, %4", operands
);
12191 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
12192 output_asm_insn (mulstr
, operands
);
12193 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12194 return "mov\t%3, %L0";
12198 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12199 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
12200 and INNER_MODE are the modes describing TARGET. */
12203 vector_init_bshuffle (rtx target
, rtx elt
, enum machine_mode mode
,
12204 enum machine_mode inner_mode
)
12206 rtx t1
, final_insn
, sel
;
12209 t1
= gen_reg_rtx (mode
);
12211 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
12212 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
12217 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
12218 bmask
= 0x45674567;
12221 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
12222 bmask
= 0x67676767;
12225 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
12226 bmask
= 0x77777777;
12229 gcc_unreachable ();
12232 sel
= force_reg (SImode
, GEN_INT (bmask
));
12233 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, const0_rtx
));
12234 emit_insn (final_insn
);
12237 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12238 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12241 vector_init_fpmerge (rtx target
, rtx elt
)
12243 rtx t1
, t2
, t2_low
, t3
, t3_low
;
12245 t1
= gen_reg_rtx (V4QImode
);
12246 elt
= convert_modes (SImode
, QImode
, elt
, true);
12247 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12249 t2
= gen_reg_rtx (V8QImode
);
12250 t2_low
= gen_lowpart (V4QImode
, t2
);
12251 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
12253 t3
= gen_reg_rtx (V8QImode
);
12254 t3_low
= gen_lowpart (V4QImode
, t3
);
12255 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
12257 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
12260 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12261 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12264 vector_init_faligndata (rtx target
, rtx elt
)
12266 rtx t1
= gen_reg_rtx (V4HImode
);
12269 elt
= convert_modes (SImode
, HImode
, elt
, true);
12270 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12272 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
12273 force_reg (SImode
, GEN_INT (6)),
12276 for (i
= 0; i
< 4; i
++)
12277 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
12280 /* Emit code to initialize TARGET to values for individual fields VALS. */
12283 sparc_expand_vector_init (rtx target
, rtx vals
)
12285 const enum machine_mode mode
= GET_MODE (target
);
12286 const enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
12287 const int n_elts
= GET_MODE_NUNITS (mode
);
12293 for (i
= 0; i
< n_elts
; i
++)
12295 rtx x
= XVECEXP (vals
, 0, i
);
12296 if (!CONSTANT_P (x
))
12299 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
12305 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
12309 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
12311 if (GET_MODE_SIZE (inner_mode
) == 4)
12313 emit_move_insn (gen_lowpart (SImode
, target
),
12314 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
12317 else if (GET_MODE_SIZE (inner_mode
) == 8)
12319 emit_move_insn (gen_lowpart (DImode
, target
),
12320 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
12324 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
12325 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
12327 emit_move_insn (gen_highpart (word_mode
, target
),
12328 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
12329 emit_move_insn (gen_lowpart (word_mode
, target
),
12330 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
12334 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
12338 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
12341 if (mode
== V8QImode
)
12343 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
12346 if (mode
== V4HImode
)
12348 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
12353 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
12354 for (i
= 0; i
< n_elts
; i
++)
12355 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
12356 i
* GET_MODE_SIZE (inner_mode
)),
12357 XVECEXP (vals
, 0, i
));
12358 emit_move_insn (target
, mem
);
12361 /* Implement TARGET_SECONDARY_RELOAD. */
12364 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
12365 enum machine_mode mode
, secondary_reload_info
*sri
)
12367 enum reg_class rclass
= (enum reg_class
) rclass_i
;
12369 sri
->icode
= CODE_FOR_nothing
;
12370 sri
->extra_cost
= 0;
12372 /* We need a temporary when loading/storing a HImode/QImode value
12373 between memory and the FPU registers. This can happen when combine puts
12374 a paradoxical subreg in a float/fix conversion insn. */
12375 if (FP_REG_CLASS_P (rclass
)
12376 && (mode
== HImode
|| mode
== QImode
)
12377 && (GET_CODE (x
) == MEM
12378 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
12379 && true_regnum (x
) == -1)))
12380 return GENERAL_REGS
;
12382 /* On 32-bit we need a temporary when loading/storing a DFmode value
12383 between unaligned memory and the upper FPU registers. */
12385 && rclass
== EXTRA_FP_REGS
12387 && GET_CODE (x
) == MEM
12388 && ! mem_min_alignment (x
, 8))
12391 if (((TARGET_CM_MEDANY
12392 && symbolic_operand (x
, mode
))
12393 || (TARGET_CM_EMBMEDANY
12394 && text_segment_operand (x
, mode
)))
12398 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
12400 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
12404 if (TARGET_VIS3
&& TARGET_ARCH32
)
12406 int regno
= true_regnum (x
);
12408 /* When using VIS3 fp<-->int register moves, on 32-bit we have
12409 to move 8-byte values in 4-byte pieces. This only works via
12410 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
12411 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
12412 an FP_REGS intermediate move. */
12413 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
12414 || ((general_or_i64_p (rclass
)
12415 || rclass
== GENERAL_OR_FP_REGS
)
12416 && SPARC_FP_REG_P (regno
)))
12418 sri
->extra_cost
= 2;
12426 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
12427 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
12430 sparc_expand_conditional_move (enum machine_mode mode
, rtx
*operands
)
12432 enum rtx_code rc
= GET_CODE (operands
[1]);
12433 enum machine_mode cmp_mode
;
12434 rtx cc_reg
, dst
, cmp
;
12437 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
12440 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
12441 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
12443 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
12444 rc
= GET_CODE (cmp
);
12447 if (! rtx_equal_p (operands
[2], dst
)
12448 && ! rtx_equal_p (operands
[3], dst
))
12450 if (reg_overlap_mentioned_p (dst
, cmp
))
12451 dst
= gen_reg_rtx (mode
);
12453 emit_move_insn (dst
, operands
[3]);
12455 else if (operands
[2] == dst
)
12457 operands
[2] = operands
[3];
12459 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
12460 rc
= reverse_condition_maybe_unordered (rc
);
12462 rc
= reverse_condition (rc
);
12465 if (XEXP (cmp
, 1) == const0_rtx
12466 && GET_CODE (XEXP (cmp
, 0)) == REG
12467 && cmp_mode
== DImode
12468 && v9_regcmp_p (rc
))
12469 cc_reg
= XEXP (cmp
, 0);
12471 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
12473 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
12475 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
12476 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
12478 if (dst
!= operands
[0])
12479 emit_move_insn (operands
[0], dst
);
12484 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
12485 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
12486 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
12487 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
12488 code to be used for the condition mask. */
12491 sparc_expand_vcond (enum machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
12493 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
12494 enum rtx_code code
= GET_CODE (operands
[3]);
12496 mask
= gen_reg_rtx (Pmode
);
12497 cop0
= operands
[4];
12498 cop1
= operands
[5];
12499 if (code
== LT
|| code
== GE
)
12503 code
= swap_condition (code
);
12504 t
= cop0
; cop0
= cop1
; cop1
= t
;
12507 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
12509 fcmp
= gen_rtx_UNSPEC (Pmode
,
12510 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
12513 cmask
= gen_rtx_UNSPEC (DImode
,
12514 gen_rtvec (2, mask
, gsr
),
12517 bshuf
= gen_rtx_UNSPEC (mode
,
12518 gen_rtvec (3, operands
[1], operands
[2], gsr
),
12521 emit_insn (gen_rtx_SET (VOIDmode
, mask
, fcmp
));
12522 emit_insn (gen_rtx_SET (VOIDmode
, gsr
, cmask
));
12524 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], bshuf
));
12527 /* On sparc, any mode which naturally allocates into the float
12528 registers should return 4 here. */
12531 sparc_regmode_natural_size (enum machine_mode mode
)
12533 int size
= UNITS_PER_WORD
;
12537 enum mode_class mclass
= GET_MODE_CLASS (mode
);
12539 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
12546 /* Return TRUE if it is a good idea to tie two pseudo registers
12547 when one has mode MODE1 and one has mode MODE2.
12548 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
12549 for any hard reg, then this must be FALSE for correct output.
12551 For V9 we have to deal with the fact that only the lower 32 floating
12552 point registers are 32-bit addressable. */
12555 sparc_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
12557 enum mode_class mclass1
, mclass2
;
12558 unsigned short size1
, size2
;
12560 if (mode1
== mode2
)
12563 mclass1
= GET_MODE_CLASS (mode1
);
12564 mclass2
= GET_MODE_CLASS (mode2
);
12565 if (mclass1
!= mclass2
)
12571 /* Classes are the same and we are V9 so we have to deal with upper
12572 vs. lower floating point registers. If one of the modes is a
12573 4-byte mode, and the other is not, we have to mark them as not
12574 tieable because only the lower 32 floating point register are
12575 addressable 32-bits at a time.
12577 We can't just test explicitly for SFmode, otherwise we won't
12578 cover the vector mode cases properly. */
12580 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
12583 size1
= GET_MODE_SIZE (mode1
);
12584 size2
= GET_MODE_SIZE (mode2
);
12585 if ((size1
> 4 && size2
== 4)
12586 || (size2
> 4 && size1
== 4))
12592 /* Implement TARGET_CSTORE_MODE. */
12594 static enum machine_mode
12595 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
12597 return (TARGET_ARCH64
? DImode
: SImode
);
12600 /* Return the compound expression made of T1 and T2. */
12603 compound_expr (tree t1
, tree t2
)
12605 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
12608 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
12611 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
12616 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
12617 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
12619 /* We generate the equivalent of feholdexcept (&fenv_var):
12621 unsigned int fenv_var;
12622 __builtin_store_fsr (&fenv_var);
12624 unsigned int tmp1_var;
12625 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
12627 __builtin_load_fsr (&tmp1_var); */
12629 tree fenv_var
= create_tmp_var (unsigned_type_node
, NULL
);
12630 mark_addressable (fenv_var
);
12631 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
12632 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
12633 tree hold_stfsr
= build_call_expr (stfsr
, 1, fenv_addr
);
12635 tree tmp1_var
= create_tmp_var (unsigned_type_node
, NULL
);
12636 mark_addressable (tmp1_var
);
12637 tree masked_fenv_var
12638 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
12639 build_int_cst (unsigned_type_node
,
12640 ~(accrued_exception_mask
| trap_enable_mask
)));
12642 = build2 (MODIFY_EXPR
, void_type_node
, tmp1_var
, masked_fenv_var
);
12644 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
12645 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
12646 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12648 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
12650 /* We reload the value of tmp1_var to clear the exceptions:
12652 __builtin_load_fsr (&tmp1_var); */
12654 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12656 /* We generate the equivalent of feupdateenv (&fenv_var):
12658 unsigned int tmp2_var;
12659 __builtin_store_fsr (&tmp2_var);
12661 __builtin_load_fsr (&fenv_var);
12663 if (SPARC_LOW_FE_EXCEPT_VALUES)
12665 __atomic_feraiseexcept ((int) tmp2_var); */
12667 tree tmp2_var
= create_tmp_var (unsigned_type_node
, NULL
);
12668 mark_addressable (tmp2_var
);
12669 tree tmp3_addr
= build_fold_addr_expr (tmp2_var
);
12670 tree update_stfsr
= build_call_expr (stfsr
, 1, tmp3_addr
);
12672 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
12674 tree atomic_feraiseexcept
12675 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
12677 = build_call_expr (atomic_feraiseexcept
, 1,
12678 fold_convert (integer_type_node
, tmp2_var
));
12680 if (SPARC_LOW_FE_EXCEPT_VALUES
)
12682 tree shifted_tmp2_var
12683 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
12684 build_int_cst (unsigned_type_node
, 5));
12686 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
12687 update_call
= compound_expr (update_shift
, update_call
);
12691 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
12694 #include "gt-sparc.h"