1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
28 #include "stringpool.h"
29 #include "stor-layout.h"
34 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "insn-codes.h"
37 #include "conditions.h"
39 #include "insn-attr.h"
51 #include "diagnostic-core.h"
56 #include "target-def.h"
57 #include "common/common-target.h"
58 #include "hash-table.h"
59 #include "basic-block.h"
60 #include "tree-ssa-alias.h"
61 #include "internal-fn.h"
62 #include "gimple-fold.h"
64 #include "gimple-expr.h"
68 #include "langhooks.h"
73 #include "tree-pass.h"
81 struct processor_costs
{
85 /* Integer signed load */
88 /* Integer zeroed load */
94 /* fmov, fneg, fabs */
98 const int float_plusminus
;
104 const int float_cmove
;
110 const int float_div_sf
;
113 const int float_div_df
;
116 const int float_sqrt_sf
;
119 const int float_sqrt_df
;
127 /* integer multiply cost for each bit set past the most
128 significant 3, so the formula for multiply cost becomes:
131 highest_bit = highest_clear_bit(rs1);
133 highest_bit = highest_set_bit(rs1);
136 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor);
138 A value of zero indicates that the multiply costs is fixed,
140 const int int_mul_bit_factor
;
151 /* penalty for shifts, due to scheduling rules etc. */
152 const int shift_penalty
;
156 struct processor_costs cypress_costs
= {
157 COSTS_N_INSNS (2), /* int load */
158 COSTS_N_INSNS (2), /* int signed load */
159 COSTS_N_INSNS (2), /* int zeroed load */
160 COSTS_N_INSNS (2), /* float load */
161 COSTS_N_INSNS (5), /* fmov, fneg, fabs */
162 COSTS_N_INSNS (5), /* fadd, fsub */
163 COSTS_N_INSNS (1), /* fcmp */
164 COSTS_N_INSNS (1), /* fmov, fmovr */
165 COSTS_N_INSNS (7), /* fmul */
166 COSTS_N_INSNS (37), /* fdivs */
167 COSTS_N_INSNS (37), /* fdivd */
168 COSTS_N_INSNS (63), /* fsqrts */
169 COSTS_N_INSNS (63), /* fsqrtd */
170 COSTS_N_INSNS (1), /* imul */
171 COSTS_N_INSNS (1), /* imulX */
172 0, /* imul bit factor */
173 COSTS_N_INSNS (1), /* idiv */
174 COSTS_N_INSNS (1), /* idivX */
175 COSTS_N_INSNS (1), /* movcc/movr */
176 0, /* shift penalty */
180 struct processor_costs supersparc_costs
= {
181 COSTS_N_INSNS (1), /* int load */
182 COSTS_N_INSNS (1), /* int signed load */
183 COSTS_N_INSNS (1), /* int zeroed load */
184 COSTS_N_INSNS (0), /* float load */
185 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
186 COSTS_N_INSNS (3), /* fadd, fsub */
187 COSTS_N_INSNS (3), /* fcmp */
188 COSTS_N_INSNS (1), /* fmov, fmovr */
189 COSTS_N_INSNS (3), /* fmul */
190 COSTS_N_INSNS (6), /* fdivs */
191 COSTS_N_INSNS (9), /* fdivd */
192 COSTS_N_INSNS (12), /* fsqrts */
193 COSTS_N_INSNS (12), /* fsqrtd */
194 COSTS_N_INSNS (4), /* imul */
195 COSTS_N_INSNS (4), /* imulX */
196 0, /* imul bit factor */
197 COSTS_N_INSNS (4), /* idiv */
198 COSTS_N_INSNS (4), /* idivX */
199 COSTS_N_INSNS (1), /* movcc/movr */
200 1, /* shift penalty */
204 struct processor_costs hypersparc_costs
= {
205 COSTS_N_INSNS (1), /* int load */
206 COSTS_N_INSNS (1), /* int signed load */
207 COSTS_N_INSNS (1), /* int zeroed load */
208 COSTS_N_INSNS (1), /* float load */
209 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
210 COSTS_N_INSNS (1), /* fadd, fsub */
211 COSTS_N_INSNS (1), /* fcmp */
212 COSTS_N_INSNS (1), /* fmov, fmovr */
213 COSTS_N_INSNS (1), /* fmul */
214 COSTS_N_INSNS (8), /* fdivs */
215 COSTS_N_INSNS (12), /* fdivd */
216 COSTS_N_INSNS (17), /* fsqrts */
217 COSTS_N_INSNS (17), /* fsqrtd */
218 COSTS_N_INSNS (17), /* imul */
219 COSTS_N_INSNS (17), /* imulX */
220 0, /* imul bit factor */
221 COSTS_N_INSNS (17), /* idiv */
222 COSTS_N_INSNS (17), /* idivX */
223 COSTS_N_INSNS (1), /* movcc/movr */
224 0, /* shift penalty */
228 struct processor_costs leon_costs
= {
229 COSTS_N_INSNS (1), /* int load */
230 COSTS_N_INSNS (1), /* int signed load */
231 COSTS_N_INSNS (1), /* int zeroed load */
232 COSTS_N_INSNS (1), /* float load */
233 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
234 COSTS_N_INSNS (1), /* fadd, fsub */
235 COSTS_N_INSNS (1), /* fcmp */
236 COSTS_N_INSNS (1), /* fmov, fmovr */
237 COSTS_N_INSNS (1), /* fmul */
238 COSTS_N_INSNS (15), /* fdivs */
239 COSTS_N_INSNS (15), /* fdivd */
240 COSTS_N_INSNS (23), /* fsqrts */
241 COSTS_N_INSNS (23), /* fsqrtd */
242 COSTS_N_INSNS (5), /* imul */
243 COSTS_N_INSNS (5), /* imulX */
244 0, /* imul bit factor */
245 COSTS_N_INSNS (5), /* idiv */
246 COSTS_N_INSNS (5), /* idivX */
247 COSTS_N_INSNS (1), /* movcc/movr */
248 0, /* shift penalty */
252 struct processor_costs leon3_costs
= {
253 COSTS_N_INSNS (1), /* int load */
254 COSTS_N_INSNS (1), /* int signed load */
255 COSTS_N_INSNS (1), /* int zeroed load */
256 COSTS_N_INSNS (1), /* float load */
257 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
258 COSTS_N_INSNS (1), /* fadd, fsub */
259 COSTS_N_INSNS (1), /* fcmp */
260 COSTS_N_INSNS (1), /* fmov, fmovr */
261 COSTS_N_INSNS (1), /* fmul */
262 COSTS_N_INSNS (14), /* fdivs */
263 COSTS_N_INSNS (15), /* fdivd */
264 COSTS_N_INSNS (22), /* fsqrts */
265 COSTS_N_INSNS (23), /* fsqrtd */
266 COSTS_N_INSNS (5), /* imul */
267 COSTS_N_INSNS (5), /* imulX */
268 0, /* imul bit factor */
269 COSTS_N_INSNS (35), /* idiv */
270 COSTS_N_INSNS (35), /* idivX */
271 COSTS_N_INSNS (1), /* movcc/movr */
272 0, /* shift penalty */
276 struct processor_costs sparclet_costs
= {
277 COSTS_N_INSNS (3), /* int load */
278 COSTS_N_INSNS (3), /* int signed load */
279 COSTS_N_INSNS (1), /* int zeroed load */
280 COSTS_N_INSNS (1), /* float load */
281 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
282 COSTS_N_INSNS (1), /* fadd, fsub */
283 COSTS_N_INSNS (1), /* fcmp */
284 COSTS_N_INSNS (1), /* fmov, fmovr */
285 COSTS_N_INSNS (1), /* fmul */
286 COSTS_N_INSNS (1), /* fdivs */
287 COSTS_N_INSNS (1), /* fdivd */
288 COSTS_N_INSNS (1), /* fsqrts */
289 COSTS_N_INSNS (1), /* fsqrtd */
290 COSTS_N_INSNS (5), /* imul */
291 COSTS_N_INSNS (5), /* imulX */
292 0, /* imul bit factor */
293 COSTS_N_INSNS (5), /* idiv */
294 COSTS_N_INSNS (5), /* idivX */
295 COSTS_N_INSNS (1), /* movcc/movr */
296 0, /* shift penalty */
300 struct processor_costs ultrasparc_costs
= {
301 COSTS_N_INSNS (2), /* int load */
302 COSTS_N_INSNS (3), /* int signed load */
303 COSTS_N_INSNS (2), /* int zeroed load */
304 COSTS_N_INSNS (2), /* float load */
305 COSTS_N_INSNS (1), /* fmov, fneg, fabs */
306 COSTS_N_INSNS (4), /* fadd, fsub */
307 COSTS_N_INSNS (1), /* fcmp */
308 COSTS_N_INSNS (2), /* fmov, fmovr */
309 COSTS_N_INSNS (4), /* fmul */
310 COSTS_N_INSNS (13), /* fdivs */
311 COSTS_N_INSNS (23), /* fdivd */
312 COSTS_N_INSNS (13), /* fsqrts */
313 COSTS_N_INSNS (23), /* fsqrtd */
314 COSTS_N_INSNS (4), /* imul */
315 COSTS_N_INSNS (4), /* imulX */
316 2, /* imul bit factor */
317 COSTS_N_INSNS (37), /* idiv */
318 COSTS_N_INSNS (68), /* idivX */
319 COSTS_N_INSNS (2), /* movcc/movr */
320 2, /* shift penalty */
324 struct processor_costs ultrasparc3_costs
= {
325 COSTS_N_INSNS (2), /* int load */
326 COSTS_N_INSNS (3), /* int signed load */
327 COSTS_N_INSNS (3), /* int zeroed load */
328 COSTS_N_INSNS (2), /* float load */
329 COSTS_N_INSNS (3), /* fmov, fneg, fabs */
330 COSTS_N_INSNS (4), /* fadd, fsub */
331 COSTS_N_INSNS (5), /* fcmp */
332 COSTS_N_INSNS (3), /* fmov, fmovr */
333 COSTS_N_INSNS (4), /* fmul */
334 COSTS_N_INSNS (17), /* fdivs */
335 COSTS_N_INSNS (20), /* fdivd */
336 COSTS_N_INSNS (20), /* fsqrts */
337 COSTS_N_INSNS (29), /* fsqrtd */
338 COSTS_N_INSNS (6), /* imul */
339 COSTS_N_INSNS (6), /* imulX */
340 0, /* imul bit factor */
341 COSTS_N_INSNS (40), /* idiv */
342 COSTS_N_INSNS (71), /* idivX */
343 COSTS_N_INSNS (2), /* movcc/movr */
344 0, /* shift penalty */
348 struct processor_costs niagara_costs
= {
349 COSTS_N_INSNS (3), /* int load */
350 COSTS_N_INSNS (3), /* int signed load */
351 COSTS_N_INSNS (3), /* int zeroed load */
352 COSTS_N_INSNS (9), /* float load */
353 COSTS_N_INSNS (8), /* fmov, fneg, fabs */
354 COSTS_N_INSNS (8), /* fadd, fsub */
355 COSTS_N_INSNS (26), /* fcmp */
356 COSTS_N_INSNS (8), /* fmov, fmovr */
357 COSTS_N_INSNS (29), /* fmul */
358 COSTS_N_INSNS (54), /* fdivs */
359 COSTS_N_INSNS (83), /* fdivd */
360 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
361 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
362 COSTS_N_INSNS (11), /* imul */
363 COSTS_N_INSNS (11), /* imulX */
364 0, /* imul bit factor */
365 COSTS_N_INSNS (72), /* idiv */
366 COSTS_N_INSNS (72), /* idivX */
367 COSTS_N_INSNS (1), /* movcc/movr */
368 0, /* shift penalty */
372 struct processor_costs niagara2_costs
= {
373 COSTS_N_INSNS (3), /* int load */
374 COSTS_N_INSNS (3), /* int signed load */
375 COSTS_N_INSNS (3), /* int zeroed load */
376 COSTS_N_INSNS (3), /* float load */
377 COSTS_N_INSNS (6), /* fmov, fneg, fabs */
378 COSTS_N_INSNS (6), /* fadd, fsub */
379 COSTS_N_INSNS (6), /* fcmp */
380 COSTS_N_INSNS (6), /* fmov, fmovr */
381 COSTS_N_INSNS (6), /* fmul */
382 COSTS_N_INSNS (19), /* fdivs */
383 COSTS_N_INSNS (33), /* fdivd */
384 COSTS_N_INSNS (19), /* fsqrts */
385 COSTS_N_INSNS (33), /* fsqrtd */
386 COSTS_N_INSNS (5), /* imul */
387 COSTS_N_INSNS (5), /* imulX */
388 0, /* imul bit factor */
389 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */
390 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */
391 COSTS_N_INSNS (1), /* movcc/movr */
392 0, /* shift penalty */
396 struct processor_costs niagara3_costs
= {
397 COSTS_N_INSNS (3), /* int load */
398 COSTS_N_INSNS (3), /* int signed load */
399 COSTS_N_INSNS (3), /* int zeroed load */
400 COSTS_N_INSNS (3), /* float load */
401 COSTS_N_INSNS (9), /* fmov, fneg, fabs */
402 COSTS_N_INSNS (9), /* fadd, fsub */
403 COSTS_N_INSNS (9), /* fcmp */
404 COSTS_N_INSNS (9), /* fmov, fmovr */
405 COSTS_N_INSNS (9), /* fmul */
406 COSTS_N_INSNS (23), /* fdivs */
407 COSTS_N_INSNS (37), /* fdivd */
408 COSTS_N_INSNS (23), /* fsqrts */
409 COSTS_N_INSNS (37), /* fsqrtd */
410 COSTS_N_INSNS (9), /* imul */
411 COSTS_N_INSNS (9), /* imulX */
412 0, /* imul bit factor */
413 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */
414 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */
415 COSTS_N_INSNS (1), /* movcc/movr */
416 0, /* shift penalty */
420 struct processor_costs niagara4_costs
= {
421 COSTS_N_INSNS (5), /* int load */
422 COSTS_N_INSNS (5), /* int signed load */
423 COSTS_N_INSNS (5), /* int zeroed load */
424 COSTS_N_INSNS (5), /* float load */
425 COSTS_N_INSNS (11), /* fmov, fneg, fabs */
426 COSTS_N_INSNS (11), /* fadd, fsub */
427 COSTS_N_INSNS (11), /* fcmp */
428 COSTS_N_INSNS (11), /* fmov, fmovr */
429 COSTS_N_INSNS (11), /* fmul */
430 COSTS_N_INSNS (24), /* fdivs */
431 COSTS_N_INSNS (37), /* fdivd */
432 COSTS_N_INSNS (24), /* fsqrts */
433 COSTS_N_INSNS (37), /* fsqrtd */
434 COSTS_N_INSNS (12), /* imul */
435 COSTS_N_INSNS (12), /* imulX */
436 0, /* imul bit factor */
437 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */
438 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */
439 COSTS_N_INSNS (1), /* movcc/movr */
440 0, /* shift penalty */
443 static const struct processor_costs
*sparc_costs
= &cypress_costs
;
445 #ifdef HAVE_AS_RELAX_OPTION
446 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use
447 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized.
448 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if
449 somebody does not branch between the sethi and jmp. */
450 #define LEAF_SIBCALL_SLOT_RESERVED_P 1
452 #define LEAF_SIBCALL_SLOT_RESERVED_P \
453 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic)
456 /* Vector to say how input registers are mapped to output registers.
457 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
458 eliminate it. You must use -fomit-frame-pointer to get that. */
459 char leaf_reg_remap
[] =
460 { 0, 1, 2, 3, 4, 5, 6, 7,
461 -1, -1, -1, -1, -1, -1, 14, -1,
462 -1, -1, -1, -1, -1, -1, -1, -1,
463 8, 9, 10, 11, 12, 13, -1, 15,
465 32, 33, 34, 35, 36, 37, 38, 39,
466 40, 41, 42, 43, 44, 45, 46, 47,
467 48, 49, 50, 51, 52, 53, 54, 55,
468 56, 57, 58, 59, 60, 61, 62, 63,
469 64, 65, 66, 67, 68, 69, 70, 71,
470 72, 73, 74, 75, 76, 77, 78, 79,
471 80, 81, 82, 83, 84, 85, 86, 87,
472 88, 89, 90, 91, 92, 93, 94, 95,
473 96, 97, 98, 99, 100, 101, 102};
475 /* Vector, indexed by hard register number, which contains 1
476 for a register that is allowable in a candidate for leaf
477 function treatment. */
478 char sparc_leaf_regs
[] =
479 { 1, 1, 1, 1, 1, 1, 1, 1,
480 0, 0, 0, 0, 0, 0, 1, 0,
481 0, 0, 0, 0, 0, 0, 0, 0,
482 1, 1, 1, 1, 1, 1, 0, 1,
483 1, 1, 1, 1, 1, 1, 1, 1,
484 1, 1, 1, 1, 1, 1, 1, 1,
485 1, 1, 1, 1, 1, 1, 1, 1,
486 1, 1, 1, 1, 1, 1, 1, 1,
487 1, 1, 1, 1, 1, 1, 1, 1,
488 1, 1, 1, 1, 1, 1, 1, 1,
489 1, 1, 1, 1, 1, 1, 1, 1,
490 1, 1, 1, 1, 1, 1, 1, 1,
491 1, 1, 1, 1, 1, 1, 1};
493 struct GTY(()) machine_function
495 /* Size of the frame of the function. */
496 HOST_WIDE_INT frame_size
;
498 /* Size of the frame of the function minus the register window save area
499 and the outgoing argument area. */
500 HOST_WIDE_INT apparent_frame_size
;
502 /* Register we pretend the frame pointer is allocated to. Normally, this
503 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We
504 record "offset" separately as it may be too big for (reg + disp). */
506 HOST_WIDE_INT frame_base_offset
;
508 /* Number of global or FP registers to be saved (as 4-byte quantities). */
509 int n_global_fp_regs
;
511 /* True if the current function is leaf and uses only leaf regs,
512 so that the SPARC leaf function optimization can be applied.
513 Private version of crtl->uses_only_leaf_regs, see
514 sparc_expand_prologue for the rationale. */
517 /* True if the prologue saves local or in registers. */
518 bool save_local_in_regs_p
;
520 /* True if the data calculated by sparc_expand_prologue are valid. */
521 bool prologue_data_valid_p
;
524 #define sparc_frame_size cfun->machine->frame_size
525 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size
526 #define sparc_frame_base_reg cfun->machine->frame_base_reg
527 #define sparc_frame_base_offset cfun->machine->frame_base_offset
528 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs
529 #define sparc_leaf_function_p cfun->machine->leaf_function_p
530 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p
531 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p
533 /* 1 if the next opcode is to be specially indented. */
534 int sparc_indent_opcode
= 0;
536 static void sparc_option_override (void);
537 static void sparc_init_modes (void);
538 static void scan_record_type (const_tree
, int *, int *, int *);
539 static int function_arg_slotno (const CUMULATIVE_ARGS
*, enum machine_mode
,
540 const_tree
, bool, bool, int *, int *);
542 static int supersparc_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
543 static int hypersparc_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
545 static void sparc_emit_set_const32 (rtx
, rtx
);
546 static void sparc_emit_set_const64 (rtx
, rtx
);
547 static void sparc_output_addr_vec (rtx
);
548 static void sparc_output_addr_diff_vec (rtx
);
549 static void sparc_output_deferred_case_vectors (void);
550 static bool sparc_legitimate_address_p (enum machine_mode
, rtx
, bool);
551 static bool sparc_legitimate_constant_p (enum machine_mode
, rtx
);
552 static rtx
sparc_builtin_saveregs (void);
553 static int epilogue_renumber (rtx
*, int);
554 static bool sparc_assemble_integer (rtx
, unsigned int, int);
555 static int set_extends (rtx_insn
*);
556 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT
);
557 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT
);
558 #ifdef TARGET_SOLARIS
559 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int,
560 tree
) ATTRIBUTE_UNUSED
;
562 static int sparc_adjust_cost (rtx_insn
*, rtx
, rtx_insn
*, int);
563 static int sparc_issue_rate (void);
564 static void sparc_sched_init (FILE *, int, int);
565 static int sparc_use_sched_lookahead (void);
567 static void emit_soft_tfmode_libcall (const char *, int, rtx
*);
568 static void emit_soft_tfmode_binop (enum rtx_code
, rtx
*);
569 static void emit_soft_tfmode_unop (enum rtx_code
, rtx
*);
570 static void emit_soft_tfmode_cvt (enum rtx_code
, rtx
*);
571 static void emit_hard_tfmode_operation (enum rtx_code
, rtx
*);
573 static bool sparc_function_ok_for_sibcall (tree
, tree
);
574 static void sparc_init_libfuncs (void);
575 static void sparc_init_builtins (void);
576 static void sparc_fpu_init_builtins (void);
577 static void sparc_vis_init_builtins (void);
578 static tree
sparc_builtin_decl (unsigned, bool);
579 static rtx
sparc_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
580 static tree
sparc_fold_builtin (tree
, int, tree
*, bool);
581 static void sparc_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
582 HOST_WIDE_INT
, tree
);
583 static bool sparc_can_output_mi_thunk (const_tree
, HOST_WIDE_INT
,
584 HOST_WIDE_INT
, const_tree
);
585 static struct machine_function
* sparc_init_machine_status (void);
586 static bool sparc_cannot_force_const_mem (enum machine_mode
, rtx
);
587 static rtx
sparc_tls_get_addr (void);
588 static rtx
sparc_tls_got (void);
589 static int sparc_register_move_cost (enum machine_mode
,
590 reg_class_t
, reg_class_t
);
591 static bool sparc_rtx_costs (rtx
, int, int, int, int *, bool);
592 static rtx
sparc_function_value (const_tree
, const_tree
, bool);
593 static rtx
sparc_libcall_value (enum machine_mode
, const_rtx
);
594 static bool sparc_function_value_regno_p (const unsigned int);
595 static rtx
sparc_struct_value_rtx (tree
, int);
596 static enum machine_mode
sparc_promote_function_mode (const_tree
, enum machine_mode
,
597 int *, const_tree
, int);
598 static bool sparc_return_in_memory (const_tree
, const_tree
);
599 static bool sparc_strict_argument_naming (cumulative_args_t
);
600 static void sparc_va_start (tree
, rtx
);
601 static tree
sparc_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
602 static bool sparc_vector_mode_supported_p (enum machine_mode
);
603 static bool sparc_tls_referenced_p (rtx
);
604 static rtx
sparc_legitimize_tls_address (rtx
);
605 static rtx
sparc_legitimize_pic_address (rtx
, rtx
);
606 static rtx
sparc_legitimize_address (rtx
, rtx
, enum machine_mode
);
607 static rtx
sparc_delegitimize_address (rtx
);
608 static bool sparc_mode_dependent_address_p (const_rtx
, addr_space_t
);
609 static bool sparc_pass_by_reference (cumulative_args_t
,
610 enum machine_mode
, const_tree
, bool);
611 static void sparc_function_arg_advance (cumulative_args_t
,
612 enum machine_mode
, const_tree
, bool);
613 static rtx
sparc_function_arg_1 (cumulative_args_t
,
614 enum machine_mode
, const_tree
, bool, bool);
615 static rtx
sparc_function_arg (cumulative_args_t
,
616 enum machine_mode
, const_tree
, bool);
617 static rtx
sparc_function_incoming_arg (cumulative_args_t
,
618 enum machine_mode
, const_tree
, bool);
619 static unsigned int sparc_function_arg_boundary (enum machine_mode
,
621 static int sparc_arg_partial_bytes (cumulative_args_t
,
622 enum machine_mode
, tree
, bool);
623 static void sparc_output_dwarf_dtprel (FILE *, int, rtx
) ATTRIBUTE_UNUSED
;
624 static void sparc_file_end (void);
625 static bool sparc_frame_pointer_required (void);
626 static bool sparc_can_eliminate (const int, const int);
627 static rtx
sparc_builtin_setjmp_frame_value (void);
628 static void sparc_conditional_register_usage (void);
629 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
630 static const char *sparc_mangle_type (const_tree
);
632 static void sparc_trampoline_init (rtx
, tree
, rtx
);
633 static enum machine_mode
sparc_preferred_simd_mode (enum machine_mode
);
634 static reg_class_t
sparc_preferred_reload_class (rtx x
, reg_class_t rclass
);
635 static bool sparc_print_operand_punct_valid_p (unsigned char);
636 static void sparc_print_operand (FILE *, rtx
, int);
637 static void sparc_print_operand_address (FILE *, rtx
);
638 static reg_class_t
sparc_secondary_reload (bool, rtx
, reg_class_t
,
640 secondary_reload_info
*);
641 static enum machine_mode
sparc_cstore_mode (enum insn_code icode
);
642 static void sparc_atomic_assign_expand_fenv (tree
*, tree
*, tree
*);
644 #ifdef SUBTARGET_ATTRIBUTE_TABLE
645 /* Table of valid machine attributes. */
646 static const struct attribute_spec sparc_attribute_table
[] =
648 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
650 SUBTARGET_ATTRIBUTE_TABLE
,
651 { NULL
, 0, 0, false, false, false, NULL
, false }
655 /* Option handling. */
658 enum cmodel sparc_cmodel
;
660 char sparc_hard_reg_printed
[8];
662 /* Initialize the GCC target structure. */
664 /* The default is to use .half rather than .short for aligned HI objects. */
665 #undef TARGET_ASM_ALIGNED_HI_OP
666 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
668 #undef TARGET_ASM_UNALIGNED_HI_OP
669 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
670 #undef TARGET_ASM_UNALIGNED_SI_OP
671 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
672 #undef TARGET_ASM_UNALIGNED_DI_OP
673 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
675 /* The target hook has to handle DI-mode values. */
676 #undef TARGET_ASM_INTEGER
677 #define TARGET_ASM_INTEGER sparc_assemble_integer
679 #undef TARGET_ASM_FUNCTION_PROLOGUE
680 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue
681 #undef TARGET_ASM_FUNCTION_EPILOGUE
682 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue
684 #undef TARGET_SCHED_ADJUST_COST
685 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
686 #undef TARGET_SCHED_ISSUE_RATE
687 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
688 #undef TARGET_SCHED_INIT
689 #define TARGET_SCHED_INIT sparc_sched_init
690 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
691 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
693 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
694 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
696 #undef TARGET_INIT_LIBFUNCS
697 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
699 #undef TARGET_LEGITIMIZE_ADDRESS
700 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address
701 #undef TARGET_DELEGITIMIZE_ADDRESS
702 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address
703 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
704 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p
706 #undef TARGET_INIT_BUILTINS
707 #define TARGET_INIT_BUILTINS sparc_init_builtins
708 #undef TARGET_BUILTIN_DECL
709 #define TARGET_BUILTIN_DECL sparc_builtin_decl
710 #undef TARGET_EXPAND_BUILTIN
711 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin
712 #undef TARGET_FOLD_BUILTIN
713 #define TARGET_FOLD_BUILTIN sparc_fold_builtin
716 #undef TARGET_HAVE_TLS
717 #define TARGET_HAVE_TLS true
720 #undef TARGET_CANNOT_FORCE_CONST_MEM
721 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
723 #undef TARGET_ASM_OUTPUT_MI_THUNK
724 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
725 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
726 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk
728 #undef TARGET_RTX_COSTS
729 #define TARGET_RTX_COSTS sparc_rtx_costs
730 #undef TARGET_ADDRESS_COST
731 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
732 #undef TARGET_REGISTER_MOVE_COST
733 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost
735 #undef TARGET_PROMOTE_FUNCTION_MODE
736 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode
738 #undef TARGET_FUNCTION_VALUE
739 #define TARGET_FUNCTION_VALUE sparc_function_value
740 #undef TARGET_LIBCALL_VALUE
741 #define TARGET_LIBCALL_VALUE sparc_libcall_value
742 #undef TARGET_FUNCTION_VALUE_REGNO_P
743 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p
745 #undef TARGET_STRUCT_VALUE_RTX
746 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx
747 #undef TARGET_RETURN_IN_MEMORY
748 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory
749 #undef TARGET_MUST_PASS_IN_STACK
750 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
751 #undef TARGET_PASS_BY_REFERENCE
752 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference
753 #undef TARGET_ARG_PARTIAL_BYTES
754 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes
755 #undef TARGET_FUNCTION_ARG_ADVANCE
756 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance
757 #undef TARGET_FUNCTION_ARG
758 #define TARGET_FUNCTION_ARG sparc_function_arg
759 #undef TARGET_FUNCTION_INCOMING_ARG
760 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg
761 #undef TARGET_FUNCTION_ARG_BOUNDARY
762 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary
764 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
765 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs
766 #undef TARGET_STRICT_ARGUMENT_NAMING
767 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming
769 #undef TARGET_EXPAND_BUILTIN_VA_START
770 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start
771 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
772 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
774 #undef TARGET_VECTOR_MODE_SUPPORTED_P
775 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
777 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
778 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode
780 #ifdef SUBTARGET_INSERT_ATTRIBUTES
781 #undef TARGET_INSERT_ATTRIBUTES
782 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
785 #ifdef SUBTARGET_ATTRIBUTE_TABLE
786 #undef TARGET_ATTRIBUTE_TABLE
787 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table
790 #undef TARGET_RELAXED_ORDERING
791 #define TARGET_RELAXED_ORDERING SPARC_RELAXED_ORDERING
793 #undef TARGET_OPTION_OVERRIDE
794 #define TARGET_OPTION_OVERRIDE sparc_option_override
796 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL)
797 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
798 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel
801 #undef TARGET_ASM_FILE_END
802 #define TARGET_ASM_FILE_END sparc_file_end
804 #undef TARGET_FRAME_POINTER_REQUIRED
805 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required
807 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
808 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value
810 #undef TARGET_CAN_ELIMINATE
811 #define TARGET_CAN_ELIMINATE sparc_can_eliminate
813 #undef TARGET_PREFERRED_RELOAD_CLASS
814 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class
816 #undef TARGET_SECONDARY_RELOAD
817 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload
819 #undef TARGET_CONDITIONAL_REGISTER_USAGE
820 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage
822 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
823 #undef TARGET_MANGLE_TYPE
824 #define TARGET_MANGLE_TYPE sparc_mangle_type
827 #undef TARGET_LEGITIMATE_ADDRESS_P
828 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
830 #undef TARGET_LEGITIMATE_CONSTANT_P
831 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p
833 #undef TARGET_TRAMPOLINE_INIT
834 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init
836 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
837 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p
838 #undef TARGET_PRINT_OPERAND
839 #define TARGET_PRINT_OPERAND sparc_print_operand
840 #undef TARGET_PRINT_OPERAND_ADDRESS
841 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address
843 /* The value stored by LDSTUB. */
844 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
845 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff
847 #undef TARGET_CSTORE_MODE
848 #define TARGET_CSTORE_MODE sparc_cstore_mode
850 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
851 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv
853 struct gcc_target targetm
= TARGET_INITIALIZER
;
855 /* Return the memory reference contained in X if any, zero otherwise. */
860 if (GET_CODE (x
) == SIGN_EXTEND
|| GET_CODE (x
) == ZERO_EXTEND
)
869 /* We use a machine specific pass to enable workarounds for errata.
870 We need to have the (essentially) final form of the insn stream in order
871 to properly detect the various hazards. Therefore, this machine specific
872 pass runs as late as possible. The pass is inserted in the pass pipeline
873 at the end of sparc_option_override. */
876 sparc_do_work_around_errata (void)
878 rtx_insn
*insn
, *next
;
880 /* Force all instructions to be split into their final form. */
881 split_all_insns_noflow ();
883 /* Now look for specific patterns in the insn stream. */
884 for (insn
= get_insns (); insn
; insn
= next
)
886 bool insert_nop
= false;
889 /* Look into the instruction in a delay slot. */
890 if (NONJUMP_INSN_P (insn
))
891 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
892 insn
= seq
->insn (1);
894 /* Look for a single-word load into an odd-numbered FP register. */
896 && NONJUMP_INSN_P (insn
)
897 && (set
= single_set (insn
)) != NULL_RTX
898 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
899 && MEM_P (SET_SRC (set
))
900 && REG_P (SET_DEST (set
))
901 && REGNO (SET_DEST (set
)) > 31
902 && REGNO (SET_DEST (set
)) % 2 != 0)
904 /* The wrong dependency is on the enclosing double register. */
905 const unsigned int x
= REGNO (SET_DEST (set
)) - 1;
906 unsigned int src1
, src2
, dest
;
909 next
= next_active_insn (insn
);
912 /* If the insn is a branch, then it cannot be problematic. */
913 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
917 code
= INSN_CODE (next
);
921 case CODE_FOR_adddf3
:
922 case CODE_FOR_subdf3
:
923 case CODE_FOR_muldf3
:
924 case CODE_FOR_divdf3
:
925 dest
= REGNO (recog_data
.operand
[0]);
926 src1
= REGNO (recog_data
.operand
[1]);
927 src2
= REGNO (recog_data
.operand
[2]);
932 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */
933 if ((src1
== x
|| src2
== x
)
934 && (dest
== src1
|| dest
== src2
))
941 FPOPd %fx, %fx, %fx */
944 && (code
== CODE_FOR_adddf3
|| code
== CODE_FOR_muldf3
))
949 case CODE_FOR_sqrtdf2
:
950 dest
= REGNO (recog_data
.operand
[0]);
951 src1
= REGNO (recog_data
.operand
[1]);
955 if (src1
== x
&& dest
== src1
)
964 /* Look for a single-word load into an integer register. */
965 else if (sparc_fix_ut699
966 && NONJUMP_INSN_P (insn
)
967 && (set
= single_set (insn
)) != NULL_RTX
968 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) <= 4
969 && mem_ref (SET_SRC (set
)) != NULL_RTX
970 && REG_P (SET_DEST (set
))
971 && REGNO (SET_DEST (set
)) < 32)
973 /* There is no problem if the second memory access has a data
974 dependency on the first single-cycle load. */
975 rtx x
= SET_DEST (set
);
977 next
= next_active_insn (insn
);
980 /* If the insn is a branch, then it cannot be problematic. */
981 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
984 /* Look for a second memory access to/from an integer register. */
985 if ((set
= single_set (next
)) != NULL_RTX
)
987 rtx src
= SET_SRC (set
);
988 rtx dest
= SET_DEST (set
);
991 /* LDD is affected. */
992 if ((mem
= mem_ref (src
)) != NULL_RTX
995 && !reg_mentioned_p (x
, XEXP (mem
, 0)))
998 /* STD is *not* affected. */
999 else if (MEM_P (dest
)
1000 && GET_MODE_SIZE (GET_MODE (dest
)) <= 4
1001 && (src
== CONST0_RTX (GET_MODE (dest
))
1004 && REGNO (src
) != REGNO (x
)))
1005 && !reg_mentioned_p (x
, XEXP (dest
, 0)))
1010 /* Look for a single-word load/operation into an FP register. */
1011 else if (sparc_fix_ut699
1012 && NONJUMP_INSN_P (insn
)
1013 && (set
= single_set (insn
)) != NULL_RTX
1014 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1015 && REG_P (SET_DEST (set
))
1016 && REGNO (SET_DEST (set
)) > 31)
1018 /* Number of instructions in the problematic window. */
1019 const int n_insns
= 4;
1020 /* The problematic combination is with the sibling FP register. */
1021 const unsigned int x
= REGNO (SET_DEST (set
));
1022 const unsigned int y
= x
^ 1;
1026 next
= next_active_insn (insn
);
1029 /* If the insn is a branch, then it cannot be problematic. */
1030 if (!NONJUMP_INSN_P (next
) || GET_CODE (PATTERN (next
)) == SEQUENCE
)
1033 /* Look for a second load/operation into the sibling FP register. */
1034 if (!((set
= single_set (next
)) != NULL_RTX
1035 && GET_MODE_SIZE (GET_MODE (SET_SRC (set
))) == 4
1036 && REG_P (SET_DEST (set
))
1037 && REGNO (SET_DEST (set
)) == y
))
1040 /* Look for a (possible) store from the FP register in the next N
1041 instructions, but bail out if it is again modified or if there
1042 is a store from the sibling FP register before this store. */
1043 for (after
= next
, i
= 0; i
< n_insns
; i
++)
1047 after
= next_active_insn (after
);
1051 /* This is a branch with an empty delay slot. */
1052 if (!NONJUMP_INSN_P (after
))
1059 /* This is a branch with a filled delay slot. */
1060 else if (rtx_sequence
*seq
=
1061 dyn_cast
<rtx_sequence
*> (PATTERN (after
)))
1066 after
= seq
->insn (1);
1068 /* This is a regular instruction. */
1072 if (after
&& (set
= single_set (after
)) != NULL_RTX
)
1074 const rtx src
= SET_SRC (set
);
1075 const rtx dest
= SET_DEST (set
);
1076 const unsigned int size
= GET_MODE_SIZE (GET_MODE (dest
));
1078 /* If the FP register is again modified before the store,
1079 then the store isn't affected. */
1081 && (REGNO (dest
) == x
1082 || (REGNO (dest
) == y
&& size
== 8)))
1085 if (MEM_P (dest
) && REG_P (src
))
1087 /* If there is a store from the sibling FP register
1088 before the store, then the store is not affected. */
1089 if (REGNO (src
) == y
|| (REGNO (src
) == x
&& size
== 8))
1092 /* Otherwise, the store is affected. */
1093 if (REGNO (src
) == x
&& size
== 4)
1101 /* If we have a branch in the first M instructions, then we
1102 cannot see the (M+2)th instruction so we play safe. */
1103 if (branch_p
&& i
<= (n_insns
- 2))
1112 next
= NEXT_INSN (insn
);
1115 emit_insn_before (gen_nop (), next
);
1123 const pass_data pass_data_work_around_errata
=
1125 RTL_PASS
, /* type */
1126 "errata", /* name */
1127 OPTGROUP_NONE
, /* optinfo_flags */
1128 TV_MACH_DEP
, /* tv_id */
1129 0, /* properties_required */
1130 0, /* properties_provided */
1131 0, /* properties_destroyed */
1132 0, /* todo_flags_start */
1133 0, /* todo_flags_finish */
1136 class pass_work_around_errata
: public rtl_opt_pass
1139 pass_work_around_errata(gcc::context
*ctxt
)
1140 : rtl_opt_pass(pass_data_work_around_errata
, ctxt
)
1143 /* opt_pass methods: */
1144 virtual bool gate (function
*)
1146 /* The only errata we handle are those of the AT697F and UT699. */
1147 return sparc_fix_at697f
!= 0 || sparc_fix_ut699
!= 0;
1150 virtual unsigned int execute (function
*)
1152 return sparc_do_work_around_errata ();
1155 }; // class pass_work_around_errata
1160 make_pass_work_around_errata (gcc::context
*ctxt
)
1162 return new pass_work_around_errata (ctxt
);
1165 /* Helpers for TARGET_DEBUG_OPTIONS. */
1167 dump_target_flag_bits (const int flags
)
1169 if (flags
& MASK_64BIT
)
1170 fprintf (stderr
, "64BIT ");
1171 if (flags
& MASK_APP_REGS
)
1172 fprintf (stderr
, "APP_REGS ");
1173 if (flags
& MASK_FASTER_STRUCTS
)
1174 fprintf (stderr
, "FASTER_STRUCTS ");
1175 if (flags
& MASK_FLAT
)
1176 fprintf (stderr
, "FLAT ");
1177 if (flags
& MASK_FMAF
)
1178 fprintf (stderr
, "FMAF ");
1179 if (flags
& MASK_FPU
)
1180 fprintf (stderr
, "FPU ");
1181 if (flags
& MASK_HARD_QUAD
)
1182 fprintf (stderr
, "HARD_QUAD ");
1183 if (flags
& MASK_POPC
)
1184 fprintf (stderr
, "POPC ");
1185 if (flags
& MASK_PTR64
)
1186 fprintf (stderr
, "PTR64 ");
1187 if (flags
& MASK_STACK_BIAS
)
1188 fprintf (stderr
, "STACK_BIAS ");
1189 if (flags
& MASK_UNALIGNED_DOUBLES
)
1190 fprintf (stderr
, "UNALIGNED_DOUBLES ");
1191 if (flags
& MASK_V8PLUS
)
1192 fprintf (stderr
, "V8PLUS ");
1193 if (flags
& MASK_VIS
)
1194 fprintf (stderr
, "VIS ");
1195 if (flags
& MASK_VIS2
)
1196 fprintf (stderr
, "VIS2 ");
1197 if (flags
& MASK_VIS3
)
1198 fprintf (stderr
, "VIS3 ");
1199 if (flags
& MASK_CBCOND
)
1200 fprintf (stderr
, "CBCOND ");
1201 if (flags
& MASK_DEPRECATED_V8_INSNS
)
1202 fprintf (stderr
, "DEPRECATED_V8_INSNS ");
1203 if (flags
& MASK_SPARCLET
)
1204 fprintf (stderr
, "SPARCLET ");
1205 if (flags
& MASK_SPARCLITE
)
1206 fprintf (stderr
, "SPARCLITE ");
1207 if (flags
& MASK_V8
)
1208 fprintf (stderr
, "V8 ");
1209 if (flags
& MASK_V9
)
1210 fprintf (stderr
, "V9 ");
1214 dump_target_flags (const char *prefix
, const int flags
)
1216 fprintf (stderr
, "%s: (%08x) [ ", prefix
, flags
);
1217 dump_target_flag_bits (flags
);
1218 fprintf(stderr
, "]\n");
1221 /* Validate and override various options, and do some machine dependent
1225 sparc_option_override (void)
1227 static struct code_model
{
1228 const char *const name
;
1229 const enum cmodel value
;
1230 } const cmodels
[] = {
1232 { "medlow", CM_MEDLOW
},
1233 { "medmid", CM_MEDMID
},
1234 { "medany", CM_MEDANY
},
1235 { "embmedany", CM_EMBMEDANY
},
1236 { NULL
, (enum cmodel
) 0 }
1238 const struct code_model
*cmodel
;
1239 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */
1240 static struct cpu_default
{
1242 const enum processor_type processor
;
1243 } const cpu_default
[] = {
1244 /* There must be one entry here for each TARGET_CPU value. */
1245 { TARGET_CPU_sparc
, PROCESSOR_CYPRESS
},
1246 { TARGET_CPU_v8
, PROCESSOR_V8
},
1247 { TARGET_CPU_supersparc
, PROCESSOR_SUPERSPARC
},
1248 { TARGET_CPU_hypersparc
, PROCESSOR_HYPERSPARC
},
1249 { TARGET_CPU_leon
, PROCESSOR_LEON
},
1250 { TARGET_CPU_leon3
, PROCESSOR_LEON3
},
1251 { TARGET_CPU_leon3v7
, PROCESSOR_LEON3V7
},
1252 { TARGET_CPU_sparclite
, PROCESSOR_F930
},
1253 { TARGET_CPU_sparclite86x
, PROCESSOR_SPARCLITE86X
},
1254 { TARGET_CPU_sparclet
, PROCESSOR_TSC701
},
1255 { TARGET_CPU_v9
, PROCESSOR_V9
},
1256 { TARGET_CPU_ultrasparc
, PROCESSOR_ULTRASPARC
},
1257 { TARGET_CPU_ultrasparc3
, PROCESSOR_ULTRASPARC3
},
1258 { TARGET_CPU_niagara
, PROCESSOR_NIAGARA
},
1259 { TARGET_CPU_niagara2
, PROCESSOR_NIAGARA2
},
1260 { TARGET_CPU_niagara3
, PROCESSOR_NIAGARA3
},
1261 { TARGET_CPU_niagara4
, PROCESSOR_NIAGARA4
},
1262 { -1, PROCESSOR_V7
}
1264 const struct cpu_default
*def
;
1265 /* Table of values for -m{cpu,tune}=. This must match the order of
1266 the enum processor_type in sparc-opts.h. */
1267 static struct cpu_table
{
1268 const char *const name
;
1271 } const cpu_table
[] = {
1272 { "v7", MASK_ISA
, 0 },
1273 { "cypress", MASK_ISA
, 0 },
1274 { "v8", MASK_ISA
, MASK_V8
},
1275 /* TI TMS390Z55 supersparc */
1276 { "supersparc", MASK_ISA
, MASK_V8
},
1277 { "hypersparc", MASK_ISA
, MASK_V8
|MASK_FPU
},
1278 { "leon", MASK_ISA
, MASK_V8
|MASK_LEON
|MASK_FPU
},
1279 { "leon3", MASK_ISA
, MASK_V8
|MASK_LEON3
|MASK_FPU
},
1280 { "leon3v7", MASK_ISA
, MASK_LEON3
|MASK_FPU
},
1281 { "sparclite", MASK_ISA
, MASK_SPARCLITE
},
1282 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */
1283 { "f930", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1284 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */
1285 { "f934", MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
1286 { "sparclite86x", MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
1287 { "sparclet", MASK_ISA
, MASK_SPARCLET
},
1288 /* TEMIC sparclet */
1289 { "tsc701", MASK_ISA
, MASK_SPARCLET
},
1290 { "v9", MASK_ISA
, MASK_V9
},
1291 /* UltraSPARC I, II, IIi */
1292 { "ultrasparc", MASK_ISA
,
1293 /* Although insns using %y are deprecated, it is a clear win. */
1294 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1295 /* UltraSPARC III */
1296 /* ??? Check if %y issue still holds true. */
1297 { "ultrasparc3", MASK_ISA
,
1298 MASK_V9
|MASK_DEPRECATED_V8_INSNS
|MASK_VIS2
},
1300 { "niagara", MASK_ISA
,
1301 MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
1303 { "niagara2", MASK_ISA
,
1304 MASK_V9
|MASK_POPC
|MASK_VIS2
},
1306 { "niagara3", MASK_ISA
,
1307 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
},
1309 { "niagara4", MASK_ISA
,
1310 MASK_V9
|MASK_POPC
|MASK_VIS2
|MASK_VIS3
|MASK_FMAF
|MASK_CBCOND
},
1312 const struct cpu_table
*cpu
;
1316 if (sparc_debug_string
!= NULL
)
1321 p
= ASTRDUP (sparc_debug_string
);
1322 while ((q
= strtok (p
, ",")) != NULL
)
1336 if (! strcmp (q
, "all"))
1337 mask
= MASK_DEBUG_ALL
;
1338 else if (! strcmp (q
, "options"))
1339 mask
= MASK_DEBUG_OPTIONS
;
1341 error ("unknown -mdebug-%s switch", q
);
1344 sparc_debug
&= ~mask
;
1346 sparc_debug
|= mask
;
1350 if (TARGET_DEBUG_OPTIONS
)
1352 dump_target_flags("Initial target_flags", target_flags
);
1353 dump_target_flags("target_flags_explicit", target_flags_explicit
);
1356 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1357 SUBTARGET_OVERRIDE_OPTIONS
;
1360 #ifndef SPARC_BI_ARCH
1361 /* Check for unsupported architecture size. */
1362 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
1363 error ("%s is not supported by this configuration",
1364 DEFAULT_ARCH32_P
? "-m64" : "-m32");
1367 /* We force all 64bit archs to use 128 bit long double */
1368 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
1370 error ("-mlong-double-64 not allowed with -m64");
1371 target_flags
|= MASK_LONG_DOUBLE_128
;
1374 /* Code model selection. */
1375 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
1377 #ifdef SPARC_BI_ARCH
1379 sparc_cmodel
= CM_32
;
1382 if (sparc_cmodel_string
!= NULL
)
1386 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
1387 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
1389 if (cmodel
->name
== NULL
)
1390 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
1392 sparc_cmodel
= cmodel
->value
;
1395 error ("-mcmodel= is not supported on 32 bit systems");
1398 /* Check that -fcall-saved-REG wasn't specified for out registers. */
1399 for (i
= 8; i
< 16; i
++)
1400 if (!call_used_regs
[i
])
1402 error ("-fcall-saved-REG is not supported for out registers");
1403 call_used_regs
[i
] = 1;
1406 fpu
= target_flags
& MASK_FPU
; /* save current -mfpu status */
1408 /* Set the default CPU. */
1409 if (!global_options_set
.x_sparc_cpu_and_features
)
1411 for (def
= &cpu_default
[0]; def
->cpu
!= -1; ++def
)
1412 if (def
->cpu
== TARGET_CPU_DEFAULT
)
1414 gcc_assert (def
->cpu
!= -1);
1415 sparc_cpu_and_features
= def
->processor
;
1418 if (!global_options_set
.x_sparc_cpu
)
1419 sparc_cpu
= sparc_cpu_and_features
;
1421 cpu
= &cpu_table
[(int) sparc_cpu_and_features
];
1423 if (TARGET_DEBUG_OPTIONS
)
1425 fprintf (stderr
, "sparc_cpu_and_features: %s\n", cpu
->name
);
1426 fprintf (stderr
, "sparc_cpu: %s\n",
1427 cpu_table
[(int) sparc_cpu
].name
);
1428 dump_target_flags ("cpu->disable", cpu
->disable
);
1429 dump_target_flags ("cpu->enable", cpu
->enable
);
1432 target_flags
&= ~cpu
->disable
;
1433 target_flags
|= (cpu
->enable
1434 #ifndef HAVE_AS_FMAF_HPC_VIS3
1435 & ~(MASK_FMAF
| MASK_VIS3
)
1437 #ifndef HAVE_AS_SPARC4
1440 #ifndef HAVE_AS_LEON
1441 & ~(MASK_LEON
| MASK_LEON3
)
1445 /* If -mfpu or -mno-fpu was explicitly used, don't override with
1446 the processor default. */
1447 if (target_flags_explicit
& MASK_FPU
)
1448 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
1450 /* -mvis2 implies -mvis */
1452 target_flags
|= MASK_VIS
;
1454 /* -mvis3 implies -mvis2 and -mvis */
1456 target_flags
|= MASK_VIS2
| MASK_VIS
;
1458 /* Don't allow -mvis, -mvis2, -mvis3, or -mfmaf if FPU is
1461 target_flags
&= ~(MASK_VIS
| MASK_VIS2
| MASK_VIS3
| MASK_FMAF
);
1463 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
1465 -m64 also implies v9. */
1466 if (TARGET_VIS
|| TARGET_ARCH64
)
1468 target_flags
|= MASK_V9
;
1469 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
1472 /* -mvis also implies -mv8plus on 32-bit */
1473 if (TARGET_VIS
&& ! TARGET_ARCH64
)
1474 target_flags
|= MASK_V8PLUS
;
1476 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
1477 if (TARGET_V9
&& TARGET_ARCH32
)
1478 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
1480 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
1481 if (! TARGET_V9
|| TARGET_ARCH64
)
1482 target_flags
&= ~MASK_V8PLUS
;
1484 /* Don't use stack biasing in 32 bit mode. */
1486 target_flags
&= ~MASK_STACK_BIAS
;
1488 /* Supply a default value for align_functions. */
1489 if (align_functions
== 0
1490 && (sparc_cpu
== PROCESSOR_ULTRASPARC
1491 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1492 || sparc_cpu
== PROCESSOR_NIAGARA
1493 || sparc_cpu
== PROCESSOR_NIAGARA2
1494 || sparc_cpu
== PROCESSOR_NIAGARA3
1495 || sparc_cpu
== PROCESSOR_NIAGARA4
))
1496 align_functions
= 32;
1498 /* Validate PCC_STRUCT_RETURN. */
1499 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
1500 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
1502 /* Only use .uaxword when compiling for a 64-bit target. */
1504 targetm
.asm_out
.unaligned_op
.di
= NULL
;
1506 /* Do various machine dependent initializations. */
1507 sparc_init_modes ();
1509 /* Set up function hooks. */
1510 init_machine_status
= sparc_init_machine_status
;
1515 case PROCESSOR_CYPRESS
:
1516 sparc_costs
= &cypress_costs
;
1519 case PROCESSOR_SPARCLITE
:
1520 case PROCESSOR_SUPERSPARC
:
1521 sparc_costs
= &supersparc_costs
;
1523 case PROCESSOR_F930
:
1524 case PROCESSOR_F934
:
1525 case PROCESSOR_HYPERSPARC
:
1526 case PROCESSOR_SPARCLITE86X
:
1527 sparc_costs
= &hypersparc_costs
;
1529 case PROCESSOR_LEON
:
1530 sparc_costs
= &leon_costs
;
1532 case PROCESSOR_LEON3
:
1533 case PROCESSOR_LEON3V7
:
1534 sparc_costs
= &leon3_costs
;
1536 case PROCESSOR_SPARCLET
:
1537 case PROCESSOR_TSC701
:
1538 sparc_costs
= &sparclet_costs
;
1541 case PROCESSOR_ULTRASPARC
:
1542 sparc_costs
= &ultrasparc_costs
;
1544 case PROCESSOR_ULTRASPARC3
:
1545 sparc_costs
= &ultrasparc3_costs
;
1547 case PROCESSOR_NIAGARA
:
1548 sparc_costs
= &niagara_costs
;
1550 case PROCESSOR_NIAGARA2
:
1551 sparc_costs
= &niagara2_costs
;
1553 case PROCESSOR_NIAGARA3
:
1554 sparc_costs
= &niagara3_costs
;
1556 case PROCESSOR_NIAGARA4
:
1557 sparc_costs
= &niagara4_costs
;
1559 case PROCESSOR_NATIVE
:
1563 if (sparc_memory_model
== SMM_DEFAULT
)
1565 /* Choose the memory model for the operating system. */
1566 enum sparc_memory_model_type os_default
= SUBTARGET_DEFAULT_MEMORY_MODEL
;
1567 if (os_default
!= SMM_DEFAULT
)
1568 sparc_memory_model
= os_default
;
1569 /* Choose the most relaxed model for the processor. */
1571 sparc_memory_model
= SMM_RMO
;
1572 else if (TARGET_LEON3
)
1573 sparc_memory_model
= SMM_TSO
;
1574 else if (TARGET_LEON
)
1575 sparc_memory_model
= SMM_SC
;
1577 sparc_memory_model
= SMM_PSO
;
1579 sparc_memory_model
= SMM_SC
;
1582 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1583 if (!(target_flags_explicit
& MASK_LONG_DOUBLE_128
))
1584 target_flags
|= MASK_LONG_DOUBLE_128
;
1587 if (TARGET_DEBUG_OPTIONS
)
1588 dump_target_flags ("Final target_flags", target_flags
);
1590 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES
,
1591 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1592 || sparc_cpu
== PROCESSOR_NIAGARA
1593 || sparc_cpu
== PROCESSOR_NIAGARA2
1594 || sparc_cpu
== PROCESSOR_NIAGARA3
1595 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1597 : (sparc_cpu
== PROCESSOR_ULTRASPARC3
1599 global_options
.x_param_values
,
1600 global_options_set
.x_param_values
);
1601 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE
,
1602 ((sparc_cpu
== PROCESSOR_ULTRASPARC
1603 || sparc_cpu
== PROCESSOR_ULTRASPARC3
1604 || sparc_cpu
== PROCESSOR_NIAGARA
1605 || sparc_cpu
== PROCESSOR_NIAGARA2
1606 || sparc_cpu
== PROCESSOR_NIAGARA3
1607 || sparc_cpu
== PROCESSOR_NIAGARA4
)
1609 global_options
.x_param_values
,
1610 global_options_set
.x_param_values
);
1612 /* Disable save slot sharing for call-clobbered registers by default.
1613 The IRA sharing algorithm works on single registers only and this
1614 pessimizes for double floating-point registers. */
1615 if (!global_options_set
.x_flag_ira_share_save_slots
)
1616 flag_ira_share_save_slots
= 0;
1618 /* We register a machine specific pass to work around errata, if any.
1619 The pass mut be scheduled as late as possible so that we have the
1620 (essentially) final form of the insn stream to work on.
1621 Registering the pass must be done at start up. It's convenient to
1623 opt_pass
*errata_pass
= make_pass_work_around_errata (g
);
1624 struct register_pass_info insert_pass_work_around_errata
=
1626 errata_pass
, /* pass */
1627 "dbr", /* reference_pass_name */
1628 1, /* ref_pass_instance_number */
1629 PASS_POS_INSERT_AFTER
/* po_op */
1631 register_pass (&insert_pass_work_around_errata
);
1634 /* Miscellaneous utilities. */
1636 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
1637 or branch on register contents instructions. */
1640 v9_regcmp_p (enum rtx_code code
)
1642 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
1643 || code
== LE
|| code
== GT
);
1646 /* Nonzero if OP is a floating point constant which can
1647 be loaded into an integer register using a single
1648 sethi instruction. */
1653 if (GET_CODE (op
) == CONST_DOUBLE
)
1658 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1659 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1660 return !SPARC_SIMM13_P (i
) && SPARC_SETHI_P (i
);
1666 /* Nonzero if OP is a floating point constant which can
1667 be loaded into an integer register using a single
1673 if (GET_CODE (op
) == CONST_DOUBLE
)
1678 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1679 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1680 return SPARC_SIMM13_P (i
);
1686 /* Nonzero if OP is a floating point constant which can
1687 be loaded into an integer register using a high/losum
1688 instruction sequence. */
1691 fp_high_losum_p (rtx op
)
1693 /* The constraints calling this should only be in
1694 SFmode move insns, so any constant which cannot
1695 be moved using a single insn will do. */
1696 if (GET_CODE (op
) == CONST_DOUBLE
)
1701 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
1702 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1703 return !SPARC_SIMM13_P (i
) && !SPARC_SETHI_P (i
);
1709 /* Return true if the address of LABEL can be loaded by means of the
1710 mov{si,di}_pic_label_ref patterns in PIC mode. */
1713 can_use_mov_pic_label_ref (rtx label
)
1715 /* VxWorks does not impose a fixed gap between segments; the run-time
1716 gap can be different from the object-file gap. We therefore can't
1717 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we
1718 are absolutely sure that X is in the same segment as the GOT.
1719 Unfortunately, the flexibility of linker scripts means that we
1720 can't be sure of that in general, so assume that GOT-relative
1721 accesses are never valid on VxWorks. */
1722 if (TARGET_VXWORKS_RTP
)
1725 /* Similarly, if the label is non-local, it might end up being placed
1726 in a different section than the current one; now mov_pic_label_ref
1727 requires the label and the code to be in the same section. */
1728 if (LABEL_REF_NONLOCAL_P (label
))
1731 /* Finally, if we are reordering basic blocks and partition into hot
1732 and cold sections, this might happen for any label. */
1733 if (flag_reorder_blocks_and_partition
)
1739 /* Expand a move instruction. Return true if all work is done. */
1742 sparc_expand_move (enum machine_mode mode
, rtx
*operands
)
1744 /* Handle sets of MEM first. */
1745 if (GET_CODE (operands
[0]) == MEM
)
1747 /* 0 is a register (or a pair of registers) on SPARC. */
1748 if (register_or_zero_operand (operands
[1], mode
))
1751 if (!reload_in_progress
)
1753 operands
[0] = validize_mem (operands
[0]);
1754 operands
[1] = force_reg (mode
, operands
[1]);
1758 /* Fixup TLS cases. */
1760 && CONSTANT_P (operands
[1])
1761 && sparc_tls_referenced_p (operands
[1]))
1763 operands
[1] = sparc_legitimize_tls_address (operands
[1]);
1767 /* Fixup PIC cases. */
1768 if (flag_pic
&& CONSTANT_P (operands
[1]))
1770 if (pic_address_needs_scratch (operands
[1]))
1771 operands
[1] = sparc_legitimize_pic_address (operands
[1], NULL_RTX
);
1773 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
1774 if (GET_CODE (operands
[1]) == LABEL_REF
1775 && can_use_mov_pic_label_ref (operands
[1]))
1779 emit_insn (gen_movsi_pic_label_ref (operands
[0], operands
[1]));
1785 gcc_assert (TARGET_ARCH64
);
1786 emit_insn (gen_movdi_pic_label_ref (operands
[0], operands
[1]));
1791 if (symbolic_operand (operands
[1], mode
))
1794 = sparc_legitimize_pic_address (operands
[1],
1796 ? operands
[0] : NULL_RTX
);
1801 /* If we are trying to toss an integer constant into FP registers,
1802 or loading a FP or vector constant, force it into memory. */
1803 if (CONSTANT_P (operands
[1])
1804 && REG_P (operands
[0])
1805 && (SPARC_FP_REG_P (REGNO (operands
[0]))
1806 || SCALAR_FLOAT_MODE_P (mode
)
1807 || VECTOR_MODE_P (mode
)))
1809 /* emit_group_store will send such bogosity to us when it is
1810 not storing directly into memory. So fix this up to avoid
1811 crashes in output_constant_pool. */
1812 if (operands
[1] == const0_rtx
)
1813 operands
[1] = CONST0_RTX (mode
);
1815 /* We can clear or set to all-ones FP registers if TARGET_VIS, and
1816 always other regs. */
1817 if ((TARGET_VIS
|| REGNO (operands
[0]) < SPARC_FIRST_FP_REG
)
1818 && (const_zero_operand (operands
[1], mode
)
1819 || const_all_ones_operand (operands
[1], mode
)))
1822 if (REGNO (operands
[0]) < SPARC_FIRST_FP_REG
1823 /* We are able to build any SF constant in integer registers
1824 with at most 2 instructions. */
1826 /* And any DF constant in integer registers. */
1828 && ! can_create_pseudo_p ())))
1831 operands
[1] = force_const_mem (mode
, operands
[1]);
1832 if (!reload_in_progress
)
1833 operands
[1] = validize_mem (operands
[1]);
1837 /* Accept non-constants and valid constants unmodified. */
1838 if (!CONSTANT_P (operands
[1])
1839 || GET_CODE (operands
[1]) == HIGH
1840 || input_operand (operands
[1], mode
))
1846 /* All QImode constants require only one insn, so proceed. */
1851 sparc_emit_set_const32 (operands
[0], operands
[1]);
1855 /* input_operand should have filtered out 32-bit mode. */
1856 sparc_emit_set_const64 (operands
[0], operands
[1]);
1862 /* TImode isn't available in 32-bit mode. */
1863 split_double (operands
[1], &high
, &low
);
1864 emit_insn (gen_movdi (operand_subword (operands
[0], 0, 0, TImode
),
1866 emit_insn (gen_movdi (operand_subword (operands
[0], 1, 0, TImode
),
1878 /* Load OP1, a 32-bit constant, into OP0, a register.
1879 We know it can't be done in one insn when we get
1880 here, the move expander guarantees this. */
1883 sparc_emit_set_const32 (rtx op0
, rtx op1
)
1885 enum machine_mode mode
= GET_MODE (op0
);
1888 if (can_create_pseudo_p ())
1889 temp
= gen_reg_rtx (mode
);
1891 if (GET_CODE (op1
) == CONST_INT
)
1893 gcc_assert (!small_int_operand (op1
, mode
)
1894 && !const_high_operand (op1
, mode
));
1896 /* Emit them as real moves instead of a HIGH/LO_SUM,
1897 this way CSE can see everything and reuse intermediate
1898 values if it wants. */
1899 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1900 GEN_INT (INTVAL (op1
)
1901 & ~(HOST_WIDE_INT
)0x3ff)));
1903 emit_insn (gen_rtx_SET (VOIDmode
,
1905 gen_rtx_IOR (mode
, temp
,
1906 GEN_INT (INTVAL (op1
) & 0x3ff))));
1910 /* A symbol, emit in the traditional way. */
1911 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1912 gen_rtx_HIGH (mode
, op1
)));
1913 emit_insn (gen_rtx_SET (VOIDmode
,
1914 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1918 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1919 If TEMP is nonzero, we are forbidden to use any other scratch
1920 registers. Otherwise, we are allowed to generate them as needed.
1922 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1923 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1926 sparc_emit_set_symbolic_const64 (rtx op0
, rtx op1
, rtx temp
)
1928 rtx temp1
, temp2
, temp3
, temp4
, temp5
;
1931 if (temp
&& GET_MODE (temp
) == TImode
)
1934 temp
= gen_rtx_REG (DImode
, REGNO (temp
));
1937 /* SPARC-V9 code-model support. */
1938 switch (sparc_cmodel
)
1941 /* The range spanned by all instructions in the object is less
1942 than 2^31 bytes (2GB) and the distance from any instruction
1943 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1944 than 2^31 bytes (2GB).
1946 The executable must be in the low 4TB of the virtual address
1949 sethi %hi(symbol), %temp1
1950 or %temp1, %lo(symbol), %reg */
1952 temp1
= temp
; /* op0 is allowed. */
1954 temp1
= gen_reg_rtx (DImode
);
1956 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1957 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1961 /* The range spanned by all instructions in the object is less
1962 than 2^31 bytes (2GB) and the distance from any instruction
1963 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1964 than 2^31 bytes (2GB).
1966 The executable must be in the low 16TB of the virtual address
1969 sethi %h44(symbol), %temp1
1970 or %temp1, %m44(symbol), %temp2
1971 sllx %temp2, 12, %temp3
1972 or %temp3, %l44(symbol), %reg */
1977 temp3
= temp
; /* op0 is allowed. */
1981 temp1
= gen_reg_rtx (DImode
);
1982 temp2
= gen_reg_rtx (DImode
);
1983 temp3
= gen_reg_rtx (DImode
);
1986 emit_insn (gen_seth44 (temp1
, op1
));
1987 emit_insn (gen_setm44 (temp2
, temp1
, op1
));
1988 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1989 gen_rtx_ASHIFT (DImode
, temp2
, GEN_INT (12))));
1990 emit_insn (gen_setl44 (op0
, temp3
, op1
));
1994 /* The range spanned by all instructions in the object is less
1995 than 2^31 bytes (2GB) and the distance from any instruction
1996 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1997 than 2^31 bytes (2GB).
1999 The executable can be placed anywhere in the virtual address
2002 sethi %hh(symbol), %temp1
2003 sethi %lm(symbol), %temp2
2004 or %temp1, %hm(symbol), %temp3
2005 sllx %temp3, 32, %temp4
2006 or %temp4, %temp2, %temp5
2007 or %temp5, %lo(symbol), %reg */
2010 /* It is possible that one of the registers we got for operands[2]
2011 might coincide with that of operands[0] (which is why we made
2012 it TImode). Pick the other one to use as our scratch. */
2013 if (rtx_equal_p (temp
, op0
))
2015 gcc_assert (ti_temp
);
2016 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2019 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2026 temp1
= gen_reg_rtx (DImode
);
2027 temp2
= gen_reg_rtx (DImode
);
2028 temp3
= gen_reg_rtx (DImode
);
2029 temp4
= gen_reg_rtx (DImode
);
2030 temp5
= gen_reg_rtx (DImode
);
2033 emit_insn (gen_sethh (temp1
, op1
));
2034 emit_insn (gen_setlm (temp2
, op1
));
2035 emit_insn (gen_sethm (temp3
, temp1
, op1
));
2036 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2037 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2038 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
2039 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2040 emit_insn (gen_setlo (op0
, temp5
, op1
));
2044 /* Old old old backwards compatibility kruft here.
2045 Essentially it is MEDLOW with a fixed 64-bit
2046 virtual base added to all data segment addresses.
2047 Text-segment stuff is computed like MEDANY, we can't
2048 reuse the code above because the relocation knobs
2051 Data segment: sethi %hi(symbol), %temp1
2052 add %temp1, EMBMEDANY_BASE_REG, %temp2
2053 or %temp2, %lo(symbol), %reg */
2054 if (data_segment_operand (op1
, GET_MODE (op1
)))
2058 temp1
= temp
; /* op0 is allowed. */
2063 temp1
= gen_reg_rtx (DImode
);
2064 temp2
= gen_reg_rtx (DImode
);
2067 emit_insn (gen_embmedany_sethi (temp1
, op1
));
2068 emit_insn (gen_embmedany_brsum (temp2
, temp1
));
2069 emit_insn (gen_embmedany_losum (op0
, temp2
, op1
));
2072 /* Text segment: sethi %uhi(symbol), %temp1
2073 sethi %hi(symbol), %temp2
2074 or %temp1, %ulo(symbol), %temp3
2075 sllx %temp3, 32, %temp4
2076 or %temp4, %temp2, %temp5
2077 or %temp5, %lo(symbol), %reg */
2082 /* It is possible that one of the registers we got for operands[2]
2083 might coincide with that of operands[0] (which is why we made
2084 it TImode). Pick the other one to use as our scratch. */
2085 if (rtx_equal_p (temp
, op0
))
2087 gcc_assert (ti_temp
);
2088 temp
= gen_rtx_REG (DImode
, REGNO (temp
) + 1);
2091 temp2
= temp
; /* op0 is _not_ allowed, see above. */
2098 temp1
= gen_reg_rtx (DImode
);
2099 temp2
= gen_reg_rtx (DImode
);
2100 temp3
= gen_reg_rtx (DImode
);
2101 temp4
= gen_reg_rtx (DImode
);
2102 temp5
= gen_reg_rtx (DImode
);
2105 emit_insn (gen_embmedany_textuhi (temp1
, op1
));
2106 emit_insn (gen_embmedany_texthi (temp2
, op1
));
2107 emit_insn (gen_embmedany_textulo (temp3
, temp1
, op1
));
2108 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2109 gen_rtx_ASHIFT (DImode
, temp3
, GEN_INT (32))));
2110 emit_insn (gen_rtx_SET (VOIDmode
, temp5
,
2111 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2112 emit_insn (gen_embmedany_textlo (op0
, temp5
, op1
));
2121 #if HOST_BITS_PER_WIDE_INT == 32
2123 sparc_emit_set_const64 (rtx op0 ATTRIBUTE_UNUSED
, rtx op1 ATTRIBUTE_UNUSED
)
2128 /* These avoid problems when cross compiling. If we do not
2129 go through all this hair then the optimizer will see
2130 invalid REG_EQUAL notes or in some cases none at all. */
2131 static rtx
gen_safe_HIGH64 (rtx
, HOST_WIDE_INT
);
2132 static rtx
gen_safe_SET64 (rtx
, HOST_WIDE_INT
);
2133 static rtx
gen_safe_OR64 (rtx
, HOST_WIDE_INT
);
2134 static rtx
gen_safe_XOR64 (rtx
, HOST_WIDE_INT
);
2136 /* The optimizer is not to assume anything about exactly
2137 which bits are set for a HIGH, they are unspecified.
2138 Unfortunately this leads to many missed optimizations
2139 during CSE. We mask out the non-HIGH bits, and matches
2140 a plain movdi, to alleviate this problem. */
2142 gen_safe_HIGH64 (rtx dest
, HOST_WIDE_INT val
)
2144 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
& ~(HOST_WIDE_INT
)0x3ff));
2148 gen_safe_SET64 (rtx dest
, HOST_WIDE_INT val
)
2150 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT (val
));
2154 gen_safe_OR64 (rtx src
, HOST_WIDE_INT val
)
2156 return gen_rtx_IOR (DImode
, src
, GEN_INT (val
));
2160 gen_safe_XOR64 (rtx src
, HOST_WIDE_INT val
)
2162 return gen_rtx_XOR (DImode
, src
, GEN_INT (val
));
2165 /* Worker routines for 64-bit constant formation on arch64.
2166 One of the key things to be doing in these emissions is
2167 to create as many temp REGs as possible. This makes it
2168 possible for half-built constants to be used later when
2169 such values are similar to something required later on.
2170 Without doing this, the optimizer cannot see such
2173 static void sparc_emit_set_const64_quick1 (rtx
, rtx
,
2174 unsigned HOST_WIDE_INT
, int);
2177 sparc_emit_set_const64_quick1 (rtx op0
, rtx temp
,
2178 unsigned HOST_WIDE_INT low_bits
, int is_neg
)
2180 unsigned HOST_WIDE_INT high_bits
;
2183 high_bits
= (~low_bits
) & 0xffffffff;
2185 high_bits
= low_bits
;
2187 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2190 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2191 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2195 /* If we are XOR'ing with -1, then we should emit a one's complement
2196 instead. This way the combiner will notice logical operations
2197 such as ANDN later on and substitute. */
2198 if ((low_bits
& 0x3ff) == 0x3ff)
2200 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2201 gen_rtx_NOT (DImode
, temp
)));
2205 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2206 gen_safe_XOR64 (temp
,
2207 (-(HOST_WIDE_INT
)0x400
2208 | (low_bits
& 0x3ff)))));
2213 static void sparc_emit_set_const64_quick2 (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2214 unsigned HOST_WIDE_INT
, int);
2217 sparc_emit_set_const64_quick2 (rtx op0
, rtx temp
,
2218 unsigned HOST_WIDE_INT high_bits
,
2219 unsigned HOST_WIDE_INT low_immediate
,
2224 if ((high_bits
& 0xfffffc00) != 0)
2226 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2227 if ((high_bits
& ~0xfffffc00) != 0)
2228 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2229 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2235 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2239 /* Now shift it up into place. */
2240 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2241 gen_rtx_ASHIFT (DImode
, temp2
,
2242 GEN_INT (shift_count
))));
2244 /* If there is a low immediate part piece, finish up by
2245 putting that in as well. */
2246 if (low_immediate
!= 0)
2247 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2248 gen_safe_OR64 (op0
, low_immediate
)));
2251 static void sparc_emit_set_const64_longway (rtx
, rtx
, unsigned HOST_WIDE_INT
,
2252 unsigned HOST_WIDE_INT
);
2254 /* Full 64-bit constant decomposition. Even though this is the
2255 'worst' case, we still optimize a few things away. */
2257 sparc_emit_set_const64_longway (rtx op0
, rtx temp
,
2258 unsigned HOST_WIDE_INT high_bits
,
2259 unsigned HOST_WIDE_INT low_bits
)
2263 if (can_create_pseudo_p ())
2264 sub_temp
= gen_reg_rtx (DImode
);
2266 if ((high_bits
& 0xfffffc00) != 0)
2268 emit_insn (gen_safe_HIGH64 (temp
, high_bits
));
2269 if ((high_bits
& ~0xfffffc00) != 0)
2270 emit_insn (gen_rtx_SET (VOIDmode
,
2272 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
2278 emit_insn (gen_safe_SET64 (temp
, high_bits
));
2282 if (can_create_pseudo_p ())
2284 rtx temp2
= gen_reg_rtx (DImode
);
2285 rtx temp3
= gen_reg_rtx (DImode
);
2286 rtx temp4
= gen_reg_rtx (DImode
);
2288 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
2289 gen_rtx_ASHIFT (DImode
, sub_temp
,
2292 emit_insn (gen_safe_HIGH64 (temp2
, low_bits
));
2293 if ((low_bits
& ~0xfffffc00) != 0)
2295 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
2296 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
2297 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2298 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
2302 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2303 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
2308 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
2309 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
2310 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
2313 /* We are in the middle of reload, so this is really
2314 painful. However we do still make an attempt to
2315 avoid emitting truly stupid code. */
2316 if (low1
!= const0_rtx
)
2318 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2319 gen_rtx_ASHIFT (DImode
, sub_temp
,
2320 GEN_INT (to_shift
))));
2321 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2322 gen_rtx_IOR (DImode
, op0
, low1
)));
2330 if (low2
!= const0_rtx
)
2332 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2333 gen_rtx_ASHIFT (DImode
, sub_temp
,
2334 GEN_INT (to_shift
))));
2335 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2336 gen_rtx_IOR (DImode
, op0
, low2
)));
2344 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2345 gen_rtx_ASHIFT (DImode
, sub_temp
,
2346 GEN_INT (to_shift
))));
2347 if (low3
!= const0_rtx
)
2348 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2349 gen_rtx_IOR (DImode
, op0
, low3
)));
2354 /* Analyze a 64-bit constant for certain properties. */
2355 static void analyze_64bit_constant (unsigned HOST_WIDE_INT
,
2356 unsigned HOST_WIDE_INT
,
2357 int *, int *, int *);
2360 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits
,
2361 unsigned HOST_WIDE_INT low_bits
,
2362 int *hbsp
, int *lbsp
, int *abbasp
)
2364 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
2367 lowest_bit_set
= highest_bit_set
= -1;
2371 if ((lowest_bit_set
== -1)
2372 && ((low_bits
>> i
) & 1))
2374 if ((highest_bit_set
== -1)
2375 && ((high_bits
>> (32 - i
- 1)) & 1))
2376 highest_bit_set
= (64 - i
- 1);
2379 && ((highest_bit_set
== -1)
2380 || (lowest_bit_set
== -1)));
2386 if ((lowest_bit_set
== -1)
2387 && ((high_bits
>> i
) & 1))
2388 lowest_bit_set
= i
+ 32;
2389 if ((highest_bit_set
== -1)
2390 && ((low_bits
>> (32 - i
- 1)) & 1))
2391 highest_bit_set
= 32 - i
- 1;
2394 && ((highest_bit_set
== -1)
2395 || (lowest_bit_set
== -1)));
2397 /* If there are no bits set this should have gone out
2398 as one instruction! */
2399 gcc_assert (lowest_bit_set
!= -1 && highest_bit_set
!= -1);
2400 all_bits_between_are_set
= 1;
2401 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
2405 if ((low_bits
& (1 << i
)) != 0)
2410 if ((high_bits
& (1 << (i
- 32))) != 0)
2413 all_bits_between_are_set
= 0;
2416 *hbsp
= highest_bit_set
;
2417 *lbsp
= lowest_bit_set
;
2418 *abbasp
= all_bits_between_are_set
;
2421 static int const64_is_2insns (unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
);
2424 const64_is_2insns (unsigned HOST_WIDE_INT high_bits
,
2425 unsigned HOST_WIDE_INT low_bits
)
2427 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
2430 || high_bits
== 0xffffffff)
2433 analyze_64bit_constant (high_bits
, low_bits
,
2434 &highest_bit_set
, &lowest_bit_set
,
2435 &all_bits_between_are_set
);
2437 if ((highest_bit_set
== 63
2438 || lowest_bit_set
== 0)
2439 && all_bits_between_are_set
!= 0)
2442 if ((highest_bit_set
- lowest_bit_set
) < 21)
2448 static unsigned HOST_WIDE_INT
create_simple_focus_bits (unsigned HOST_WIDE_INT
,
2449 unsigned HOST_WIDE_INT
,
2452 static unsigned HOST_WIDE_INT
2453 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits
,
2454 unsigned HOST_WIDE_INT low_bits
,
2455 int lowest_bit_set
, int shift
)
2457 HOST_WIDE_INT hi
, lo
;
2459 if (lowest_bit_set
< 32)
2461 lo
= (low_bits
>> lowest_bit_set
) << shift
;
2462 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
2467 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
2469 gcc_assert (! (hi
& lo
));
2473 /* Here we are sure to be arch64 and this is an integer constant
2474 being loaded into a register. Emit the most efficient
2475 insn sequence possible. Detection of all the 1-insn cases
2476 has been done already. */
2478 sparc_emit_set_const64 (rtx op0
, rtx op1
)
2480 unsigned HOST_WIDE_INT high_bits
, low_bits
;
2481 int lowest_bit_set
, highest_bit_set
;
2482 int all_bits_between_are_set
;
2485 /* Sanity check that we know what we are working with. */
2486 gcc_assert (TARGET_ARCH64
2487 && (GET_CODE (op0
) == SUBREG
2488 || (REG_P (op0
) && ! SPARC_FP_REG_P (REGNO (op0
)))));
2490 if (! can_create_pseudo_p ())
2493 if (GET_CODE (op1
) != CONST_INT
)
2495 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
2500 temp
= gen_reg_rtx (DImode
);
2502 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
2503 low_bits
= (INTVAL (op1
) & 0xffffffff);
2505 /* low_bits bits 0 --> 31
2506 high_bits bits 32 --> 63 */
2508 analyze_64bit_constant (high_bits
, low_bits
,
2509 &highest_bit_set
, &lowest_bit_set
,
2510 &all_bits_between_are_set
);
2512 /* First try for a 2-insn sequence. */
2514 /* These situations are preferred because the optimizer can
2515 * do more things with them:
2517 * sllx %reg, shift, %reg
2519 * srlx %reg, shift, %reg
2520 * 3) mov some_small_const, %reg
2521 * sllx %reg, shift, %reg
2523 if (((highest_bit_set
== 63
2524 || lowest_bit_set
== 0)
2525 && all_bits_between_are_set
!= 0)
2526 || ((highest_bit_set
- lowest_bit_set
) < 12))
2528 HOST_WIDE_INT the_const
= -1;
2529 int shift
= lowest_bit_set
;
2531 if ((highest_bit_set
!= 63
2532 && lowest_bit_set
!= 0)
2533 || all_bits_between_are_set
== 0)
2536 create_simple_focus_bits (high_bits
, low_bits
,
2539 else if (lowest_bit_set
== 0)
2540 shift
= -(63 - highest_bit_set
);
2542 gcc_assert (SPARC_SIMM13_P (the_const
));
2543 gcc_assert (shift
!= 0);
2545 emit_insn (gen_safe_SET64 (temp
, the_const
));
2547 emit_insn (gen_rtx_SET (VOIDmode
,
2549 gen_rtx_ASHIFT (DImode
,
2553 emit_insn (gen_rtx_SET (VOIDmode
,
2555 gen_rtx_LSHIFTRT (DImode
,
2557 GEN_INT (-shift
))));
2561 /* Now a range of 22 or less bits set somewhere.
2562 * 1) sethi %hi(focus_bits), %reg
2563 * sllx %reg, shift, %reg
2564 * 2) sethi %hi(focus_bits), %reg
2565 * srlx %reg, shift, %reg
2567 if ((highest_bit_set
- lowest_bit_set
) < 21)
2569 unsigned HOST_WIDE_INT focus_bits
=
2570 create_simple_focus_bits (high_bits
, low_bits
,
2571 lowest_bit_set
, 10);
2573 gcc_assert (SPARC_SETHI_P (focus_bits
));
2574 gcc_assert (lowest_bit_set
!= 10);
2576 emit_insn (gen_safe_HIGH64 (temp
, focus_bits
));
2578 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2579 if (lowest_bit_set
< 10)
2580 emit_insn (gen_rtx_SET (VOIDmode
,
2582 gen_rtx_LSHIFTRT (DImode
, temp
,
2583 GEN_INT (10 - lowest_bit_set
))));
2584 else if (lowest_bit_set
> 10)
2585 emit_insn (gen_rtx_SET (VOIDmode
,
2587 gen_rtx_ASHIFT (DImode
, temp
,
2588 GEN_INT (lowest_bit_set
- 10))));
2592 /* 1) sethi %hi(low_bits), %reg
2593 * or %reg, %lo(low_bits), %reg
2594 * 2) sethi %hi(~low_bits), %reg
2595 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2598 || high_bits
== 0xffffffff)
2600 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2601 (high_bits
== 0xffffffff));
2605 /* Now, try 3-insn sequences. */
2607 /* 1) sethi %hi(high_bits), %reg
2608 * or %reg, %lo(high_bits), %reg
2609 * sllx %reg, 32, %reg
2613 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2617 /* We may be able to do something quick
2618 when the constant is negated, so try that. */
2619 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2620 (~low_bits
) & 0xfffffc00))
2622 /* NOTE: The trailing bits get XOR'd so we need the
2623 non-negated bits, not the negated ones. */
2624 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2626 if ((((~high_bits
) & 0xffffffff) == 0
2627 && ((~low_bits
) & 0x80000000) == 0)
2628 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2629 && ((~low_bits
) & 0x80000000) != 0))
2631 unsigned HOST_WIDE_INT fast_int
= (~low_bits
& 0xffffffff);
2633 if ((SPARC_SETHI_P (fast_int
)
2634 && (~high_bits
& 0xffffffff) == 0)
2635 || SPARC_SIMM13_P (fast_int
))
2636 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2638 sparc_emit_set_const64 (temp
, GEN_INT (fast_int
));
2643 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2644 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2645 sparc_emit_set_const64 (temp
, negated_const
);
2648 /* If we are XOR'ing with -1, then we should emit a one's complement
2649 instead. This way the combiner will notice logical operations
2650 such as ANDN later on and substitute. */
2651 if (trailing_bits
== 0x3ff)
2653 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2654 gen_rtx_NOT (DImode
, temp
)));
2658 emit_insn (gen_rtx_SET (VOIDmode
,
2660 gen_safe_XOR64 (temp
,
2661 (-0x400 | trailing_bits
))));
2666 /* 1) sethi %hi(xxx), %reg
2667 * or %reg, %lo(xxx), %reg
2668 * sllx %reg, yyy, %reg
2670 * ??? This is just a generalized version of the low_bits==0
2671 * thing above, FIXME...
2673 if ((highest_bit_set
- lowest_bit_set
) < 32)
2675 unsigned HOST_WIDE_INT focus_bits
=
2676 create_simple_focus_bits (high_bits
, low_bits
,
2679 /* We can't get here in this state. */
2680 gcc_assert (highest_bit_set
>= 32 && lowest_bit_set
< 32);
2682 /* So what we know is that the set bits straddle the
2683 middle of the 64-bit word. */
2684 sparc_emit_set_const64_quick2 (op0
, temp
,
2690 /* 1) sethi %hi(high_bits), %reg
2691 * or %reg, %lo(high_bits), %reg
2692 * sllx %reg, 32, %reg
2693 * or %reg, low_bits, %reg
2695 if (SPARC_SIMM13_P(low_bits
)
2696 && ((int)low_bits
> 0))
2698 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2702 /* The easiest way when all else fails, is full decomposition. */
2703 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2705 #endif /* HOST_BITS_PER_WIDE_INT == 32 */
2707 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2708 return the mode to be used for the comparison. For floating-point,
2709 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2710 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2711 processing is needed. */
2714 select_cc_mode (enum rtx_code op
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2716 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2742 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2743 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2745 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2746 return CCX_NOOVmode
;
2752 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2759 /* Emit the compare insn and return the CC reg for a CODE comparison
2760 with operands X and Y. */
2763 gen_compare_reg_1 (enum rtx_code code
, rtx x
, rtx y
)
2765 enum machine_mode mode
;
2768 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
)
2771 mode
= SELECT_CC_MODE (code
, x
, y
);
2773 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2774 fcc regs (cse can't tell they're really call clobbered regs and will
2775 remove a duplicate comparison even if there is an intervening function
2776 call - it will then try to reload the cc reg via an int reg which is why
2777 we need the movcc patterns). It is possible to provide the movcc
2778 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2779 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2780 to tell cse that CCFPE mode registers (even pseudos) are call
2783 /* ??? This is an experiment. Rather than making changes to cse which may
2784 or may not be easy/clean, we do our own cse. This is possible because
2785 we will generate hard registers. Cse knows they're call clobbered (it
2786 doesn't know the same thing about pseudos). If we guess wrong, no big
2787 deal, but if we win, great! */
2789 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2790 #if 1 /* experiment */
2793 /* We cycle through the registers to ensure they're all exercised. */
2794 static int next_fcc_reg
= 0;
2795 /* Previous x,y for each fcc reg. */
2796 static rtx prev_args
[4][2];
2798 /* Scan prev_args for x,y. */
2799 for (reg
= 0; reg
< 4; reg
++)
2800 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2805 prev_args
[reg
][0] = x
;
2806 prev_args
[reg
][1] = y
;
2807 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2809 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2812 cc_reg
= gen_reg_rtx (mode
);
2813 #endif /* ! experiment */
2814 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2815 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2817 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2819 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this
2820 will only result in an unrecognizable insn so no point in asserting. */
2821 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
, gen_rtx_COMPARE (mode
, x
, y
)));
2827 /* Emit the compare insn and return the CC reg for the comparison in CMP. */
2830 gen_compare_reg (rtx cmp
)
2832 return gen_compare_reg_1 (GET_CODE (cmp
), XEXP (cmp
, 0), XEXP (cmp
, 1));
2835 /* This function is used for v9 only.
2836 DEST is the target of the Scc insn.
2837 CODE is the code for an Scc's comparison.
2838 X and Y are the values we compare.
2840 This function is needed to turn
2843 (gt (reg:CCX 100 %icc)
2847 (gt:DI (reg:CCX 100 %icc)
2850 IE: The instruction recognizer needs to see the mode of the comparison to
2851 find the right instruction. We could use "gt:DI" right in the
2852 define_expand, but leaving it out allows us to handle DI, SI, etc. */
2855 gen_v9_scc (rtx dest
, enum rtx_code compare_code
, rtx x
, rtx y
)
2858 && (GET_MODE (x
) == DImode
2859 || GET_MODE (dest
) == DImode
))
2862 /* Try to use the movrCC insns. */
2864 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
2866 && v9_regcmp_p (compare_code
))
2871 /* Special case for op0 != 0. This can be done with one instruction if
2874 if (compare_code
== NE
2875 && GET_MODE (dest
) == DImode
2876 && rtx_equal_p (op0
, dest
))
2878 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2879 gen_rtx_IF_THEN_ELSE (DImode
,
2880 gen_rtx_fmt_ee (compare_code
, DImode
,
2887 if (reg_overlap_mentioned_p (dest
, op0
))
2889 /* Handle the case where dest == x.
2890 We "early clobber" the result. */
2891 op0
= gen_reg_rtx (GET_MODE (x
));
2892 emit_move_insn (op0
, x
);
2895 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2896 if (GET_MODE (op0
) != DImode
)
2898 temp
= gen_reg_rtx (DImode
);
2899 convert_move (temp
, op0
, 0);
2903 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2904 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2905 gen_rtx_fmt_ee (compare_code
, DImode
,
2913 x
= gen_compare_reg_1 (compare_code
, x
, y
);
2916 gcc_assert (GET_MODE (x
) != CC_NOOVmode
2917 && GET_MODE (x
) != CCX_NOOVmode
);
2919 emit_insn (gen_rtx_SET (VOIDmode
, dest
, const0_rtx
));
2920 emit_insn (gen_rtx_SET (VOIDmode
, dest
,
2921 gen_rtx_IF_THEN_ELSE (GET_MODE (dest
),
2922 gen_rtx_fmt_ee (compare_code
,
2923 GET_MODE (x
), x
, y
),
2924 const1_rtx
, dest
)));
2930 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this
2931 without jumps using the addx/subx instructions. */
2934 emit_scc_insn (rtx operands
[])
2941 /* The quad-word fp compare library routines all return nonzero to indicate
2942 true, which is different from the equivalent libgcc routines, so we must
2943 handle them specially here. */
2944 if (GET_MODE (operands
[2]) == TFmode
&& ! TARGET_HARD_QUAD
)
2946 operands
[1] = sparc_emit_float_lib_cmp (operands
[2], operands
[3],
2947 GET_CODE (operands
[1]));
2948 operands
[2] = XEXP (operands
[1], 0);
2949 operands
[3] = XEXP (operands
[1], 1);
2952 code
= GET_CODE (operands
[1]);
2956 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has
2957 more applications). The exception to this is "reg != 0" which can
2958 be done in one instruction on v9 (so we do it). */
2961 if (GET_MODE (x
) == SImode
)
2965 pat
= gen_seqsidi_special (operands
[0], x
, y
);
2967 pat
= gen_seqsisi_special (operands
[0], x
, y
);
2971 else if (GET_MODE (x
) == DImode
)
2973 rtx pat
= gen_seqdi_special (operands
[0], x
, y
);
2981 if (GET_MODE (x
) == SImode
)
2985 pat
= gen_snesidi_special (operands
[0], x
, y
);
2987 pat
= gen_snesisi_special (operands
[0], x
, y
);
2991 else if (GET_MODE (x
) == DImode
)
2995 pat
= gen_snedi_special_vis3 (operands
[0], x
, y
);
2997 pat
= gen_snedi_special (operands
[0], x
, y
);
3005 && GET_MODE (x
) == DImode
3007 && (code
== GTU
|| code
== LTU
))
3008 && gen_v9_scc (operands
[0], code
, x
, y
))
3011 /* We can do LTU and GEU using the addx/subx instructions too. And
3012 for GTU/LEU, if both operands are registers swap them and fall
3013 back to the easy case. */
3014 if (code
== GTU
|| code
== LEU
)
3016 if ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
3017 && (GET_CODE (y
) == REG
|| GET_CODE (y
) == SUBREG
))
3022 code
= swap_condition (code
);
3027 || (!TARGET_VIS3
&& code
== GEU
))
3029 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
3030 gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3031 gen_compare_reg_1 (code
, x
, y
),
3036 /* All the posibilities to use addx/subx based sequences has been
3037 exhausted, try for a 3 instruction sequence using v9 conditional
3039 if (TARGET_V9
&& gen_v9_scc (operands
[0], code
, x
, y
))
3042 /* Nope, do branches. */
3046 /* Emit a conditional jump insn for the v9 architecture using comparison code
3047 CODE and jump target LABEL.
3048 This function exists to take advantage of the v9 brxx insns. */
3051 emit_v9_brxx_insn (enum rtx_code code
, rtx op0
, rtx label
)
3053 emit_jump_insn (gen_rtx_SET (VOIDmode
,
3055 gen_rtx_IF_THEN_ELSE (VOIDmode
,
3056 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
3058 gen_rtx_LABEL_REF (VOIDmode
, label
),
3062 /* Emit a conditional jump insn for the UA2011 architecture using
3063 comparison code CODE and jump target LABEL. This function exists
3064 to take advantage of the UA2011 Compare and Branch insns. */
3067 emit_cbcond_insn (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
3071 if_then_else
= gen_rtx_IF_THEN_ELSE (VOIDmode
,
3072 gen_rtx_fmt_ee(code
, GET_MODE(op0
),
3074 gen_rtx_LABEL_REF (VOIDmode
, label
),
3077 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
, if_then_else
));
3081 emit_conditional_branch_insn (rtx operands
[])
3083 /* The quad-word fp compare library routines all return nonzero to indicate
3084 true, which is different from the equivalent libgcc routines, so we must
3085 handle them specially here. */
3086 if (GET_MODE (operands
[1]) == TFmode
&& ! TARGET_HARD_QUAD
)
3088 operands
[0] = sparc_emit_float_lib_cmp (operands
[1], operands
[2],
3089 GET_CODE (operands
[0]));
3090 operands
[1] = XEXP (operands
[0], 0);
3091 operands
[2] = XEXP (operands
[0], 1);
3094 /* If we can tell early on that the comparison is against a constant
3095 that won't fit in the 5-bit signed immediate field of a cbcond,
3096 use one of the other v9 conditional branch sequences. */
3098 && GET_CODE (operands
[1]) == REG
3099 && (GET_MODE (operands
[1]) == SImode
3100 || (TARGET_ARCH64
&& GET_MODE (operands
[1]) == DImode
))
3101 && (GET_CODE (operands
[2]) != CONST_INT
3102 || SPARC_SIMM5_P (INTVAL (operands
[2]))))
3104 emit_cbcond_insn (GET_CODE (operands
[0]), operands
[1], operands
[2], operands
[3]);
3108 if (TARGET_ARCH64
&& operands
[2] == const0_rtx
3109 && GET_CODE (operands
[1]) == REG
3110 && GET_MODE (operands
[1]) == DImode
)
3112 emit_v9_brxx_insn (GET_CODE (operands
[0]), operands
[1], operands
[3]);
3116 operands
[1] = gen_compare_reg (operands
[0]);
3117 operands
[2] = const0_rtx
;
3118 operands
[0] = gen_rtx_fmt_ee (GET_CODE (operands
[0]), VOIDmode
,
3119 operands
[1], operands
[2]);
3120 emit_jump_insn (gen_cbranchcc4 (operands
[0], operands
[1], operands
[2],
3125 /* Generate a DFmode part of a hard TFmode register.
3126 REG is the TFmode hard register, LOW is 1 for the
3127 low 64bit of the register and 0 otherwise.
3130 gen_df_reg (rtx reg
, int low
)
3132 int regno
= REGNO (reg
);
3134 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
3135 regno
+= (TARGET_ARCH64
&& SPARC_INT_REG_P (regno
)) ? 1 : 2;
3136 return gen_rtx_REG (DFmode
, regno
);
3139 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
3140 Unlike normal calls, TFmode operands are passed by reference. It is
3141 assumed that no more than 3 operands are required. */
3144 emit_soft_tfmode_libcall (const char *func_name
, int nargs
, rtx
*operands
)
3146 rtx ret_slot
= NULL
, arg
[3], func_sym
;
3149 /* We only expect to be called for conversions, unary, and binary ops. */
3150 gcc_assert (nargs
== 2 || nargs
== 3);
3152 for (i
= 0; i
< nargs
; ++i
)
3154 rtx this_arg
= operands
[i
];
3157 /* TFmode arguments and return values are passed by reference. */
3158 if (GET_MODE (this_arg
) == TFmode
)
3160 int force_stack_temp
;
3162 force_stack_temp
= 0;
3163 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
3164 force_stack_temp
= 1;
3166 if (GET_CODE (this_arg
) == MEM
3167 && ! force_stack_temp
)
3169 tree expr
= MEM_EXPR (this_arg
);
3171 mark_addressable (expr
);
3172 this_arg
= XEXP (this_arg
, 0);
3174 else if (CONSTANT_P (this_arg
)
3175 && ! force_stack_temp
)
3177 this_slot
= force_const_mem (TFmode
, this_arg
);
3178 this_arg
= XEXP (this_slot
, 0);
3182 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
));
3184 /* Operand 0 is the return value. We'll copy it out later. */
3186 emit_move_insn (this_slot
, this_arg
);
3188 ret_slot
= this_slot
;
3190 this_arg
= XEXP (this_slot
, 0);
3197 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
3199 if (GET_MODE (operands
[0]) == TFmode
)
3202 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
3203 arg
[0], GET_MODE (arg
[0]),
3204 arg
[1], GET_MODE (arg
[1]));
3206 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
3207 arg
[0], GET_MODE (arg
[0]),
3208 arg
[1], GET_MODE (arg
[1]),
3209 arg
[2], GET_MODE (arg
[2]));
3212 emit_move_insn (operands
[0], ret_slot
);
3218 gcc_assert (nargs
== 2);
3220 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
3221 GET_MODE (operands
[0]), 1,
3222 arg
[1], GET_MODE (arg
[1]));
3224 if (ret
!= operands
[0])
3225 emit_move_insn (operands
[0], ret
);
3229 /* Expand soft-float TFmode calls to sparc abi routines. */
3232 emit_soft_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3254 emit_soft_tfmode_libcall (func
, 3, operands
);
3258 emit_soft_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3262 gcc_assert (code
== SQRT
);
3265 emit_soft_tfmode_libcall (func
, 2, operands
);
3269 emit_soft_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3276 switch (GET_MODE (operands
[1]))
3289 case FLOAT_TRUNCATE
:
3290 switch (GET_MODE (operands
[0]))
3304 switch (GET_MODE (operands
[1]))
3309 operands
[1] = gen_rtx_SIGN_EXTEND (DImode
, operands
[1]);
3319 case UNSIGNED_FLOAT
:
3320 switch (GET_MODE (operands
[1]))
3325 operands
[1] = gen_rtx_ZERO_EXTEND (DImode
, operands
[1]);
3336 switch (GET_MODE (operands
[0]))
3350 switch (GET_MODE (operands
[0]))
3367 emit_soft_tfmode_libcall (func
, 2, operands
);
3370 /* Expand a hard-float tfmode operation. All arguments must be in
3374 emit_hard_tfmode_operation (enum rtx_code code
, rtx
*operands
)
3378 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
3380 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3381 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
3385 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
3386 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
3387 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
3388 operands
[1], operands
[2]);
3391 if (register_operand (operands
[0], VOIDmode
))
3394 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
3396 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
3398 if (dest
!= operands
[0])
3399 emit_move_insn (operands
[0], dest
);
3403 emit_tfmode_binop (enum rtx_code code
, rtx
*operands
)
3405 if (TARGET_HARD_QUAD
)
3406 emit_hard_tfmode_operation (code
, operands
);
3408 emit_soft_tfmode_binop (code
, operands
);
3412 emit_tfmode_unop (enum rtx_code code
, rtx
*operands
)
3414 if (TARGET_HARD_QUAD
)
3415 emit_hard_tfmode_operation (code
, operands
);
3417 emit_soft_tfmode_unop (code
, operands
);
3421 emit_tfmode_cvt (enum rtx_code code
, rtx
*operands
)
3423 if (TARGET_HARD_QUAD
)
3424 emit_hard_tfmode_operation (code
, operands
);
3426 emit_soft_tfmode_cvt (code
, operands
);
3429 /* Return nonzero if a branch/jump/call instruction will be emitting
3430 nop into its delay slot. */
3433 empty_delay_slot (rtx_insn
*insn
)
3437 /* If no previous instruction (should not happen), return true. */
3438 if (PREV_INSN (insn
) == NULL
)
3441 seq
= NEXT_INSN (PREV_INSN (insn
));
3442 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
3448 /* Return nonzero if we should emit a nop after a cbcond instruction.
3449 The cbcond instruction does not have a delay slot, however there is
3450 a severe performance penalty if a control transfer appears right
3451 after a cbcond. Therefore we emit a nop when we detect this
3455 emit_cbcond_nop (rtx insn
)
3457 rtx next
= next_active_insn (insn
);
3462 if (NONJUMP_INSN_P (next
)
3463 && GET_CODE (PATTERN (next
)) == SEQUENCE
)
3464 next
= XVECEXP (PATTERN (next
), 0, 0);
3465 else if (CALL_P (next
)
3466 && GET_CODE (PATTERN (next
)) == PARALLEL
)
3468 rtx delay
= XVECEXP (PATTERN (next
), 0, 1);
3470 if (GET_CODE (delay
) == RETURN
)
3472 /* It's a sibling call. Do not emit the nop if we're going
3473 to emit something other than the jump itself as the first
3474 instruction of the sibcall sequence. */
3475 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3480 if (NONJUMP_INSN_P (next
))
3486 /* Return nonzero if TRIAL can go into the call delay slot. */
3489 eligible_for_call_delay (rtx_insn
*trial
)
3493 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3497 call __tls_get_addr, %tgd_call (foo)
3498 add %l7, %o0, %o0, %tgd_add (foo)
3499 while Sun as/ld does not. */
3500 if (TARGET_GNU_TLS
|| !TARGET_TLS
)
3503 pat
= PATTERN (trial
);
3505 /* We must reject tgd_add{32|64}, i.e.
3506 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD)))
3507 and tldm_add{32|64}, i.e.
3508 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM)))
3510 if (GET_CODE (pat
) == SET
3511 && GET_CODE (SET_SRC (pat
)) == PLUS
)
3513 rtx unspec
= XEXP (SET_SRC (pat
), 1);
3515 if (GET_CODE (unspec
) == UNSPEC
3516 && (XINT (unspec
, 1) == UNSPEC_TLSGD
3517 || XINT (unspec
, 1) == UNSPEC_TLSLDM
))
3524 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore'
3525 instruction. RETURN_P is true if the v9 variant 'return' is to be
3526 considered in the test too.
3528 TRIAL must be a SET whose destination is a REG appropriate for the
3529 'restore' instruction or, if RETURN_P is true, for the 'return'
3533 eligible_for_restore_insn (rtx trial
, bool return_p
)
3535 rtx pat
= PATTERN (trial
);
3536 rtx src
= SET_SRC (pat
);
3537 bool src_is_freg
= false;
3540 /* Since we now can do moves between float and integer registers when
3541 VIS3 is enabled, we have to catch this case. We can allow such
3542 moves when doing a 'return' however. */
3544 if (GET_CODE (src_reg
) == SUBREG
)
3545 src_reg
= SUBREG_REG (src_reg
);
3546 if (GET_CODE (src_reg
) == REG
3547 && SPARC_FP_REG_P (REGNO (src_reg
)))
3550 /* The 'restore src,%g0,dest' pattern for word mode and below. */
3551 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3552 && arith_operand (src
, GET_MODE (src
))
3556 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3558 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
3561 /* The 'restore src,%g0,dest' pattern for double-word mode. */
3562 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
3563 && arith_double_operand (src
, GET_MODE (src
))
3565 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3567 /* The 'restore src,%g0,dest' pattern for float if no FPU. */
3568 else if (! TARGET_FPU
&& register_operand (src
, SFmode
))
3571 /* The 'restore src,%g0,dest' pattern for double if no FPU. */
3572 else if (! TARGET_FPU
&& TARGET_ARCH64
&& register_operand (src
, DFmode
))
3575 /* If we have the 'return' instruction, anything that does not use
3576 local or output registers and can go into a delay slot wins. */
3577 else if (return_p
&& TARGET_V9
&& !epilogue_renumber (&pat
, 1))
3580 /* The 'restore src1,src2,dest' pattern for SImode. */
3581 else if (GET_CODE (src
) == PLUS
3582 && register_operand (XEXP (src
, 0), SImode
)
3583 && arith_operand (XEXP (src
, 1), SImode
))
3586 /* The 'restore src1,src2,dest' pattern for DImode. */
3587 else if (GET_CODE (src
) == PLUS
3588 && register_operand (XEXP (src
, 0), DImode
)
3589 && arith_double_operand (XEXP (src
, 1), DImode
))
3592 /* The 'restore src1,%lo(src2),dest' pattern. */
3593 else if (GET_CODE (src
) == LO_SUM
3594 && ! TARGET_CM_MEDMID
3595 && ((register_operand (XEXP (src
, 0), SImode
)
3596 && immediate_operand (XEXP (src
, 1), SImode
))
3598 && register_operand (XEXP (src
, 0), DImode
)
3599 && immediate_operand (XEXP (src
, 1), DImode
))))
3602 /* The 'restore src,src,dest' pattern. */
3603 else if (GET_CODE (src
) == ASHIFT
3604 && (register_operand (XEXP (src
, 0), SImode
)
3605 || register_operand (XEXP (src
, 0), DImode
))
3606 && XEXP (src
, 1) == const1_rtx
)
3612 /* Return nonzero if TRIAL can go into the function return's delay slot. */
3615 eligible_for_return_delay (rtx_insn
*trial
)
3620 /* If the function uses __builtin_eh_return, the eh_return machinery
3621 occupies the delay slot. */
3622 if (crtl
->calls_eh_return
)
3625 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3628 /* In the case of a leaf or flat function, anything can go into the slot. */
3629 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3632 if (!NONJUMP_INSN_P (trial
))
3635 pat
= PATTERN (trial
);
3636 if (GET_CODE (pat
) == PARALLEL
)
3642 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
3644 rtx expr
= XVECEXP (pat
, 0, i
);
3645 if (GET_CODE (expr
) != SET
)
3647 if (GET_CODE (SET_DEST (expr
)) != REG
)
3649 regno
= REGNO (SET_DEST (expr
));
3650 if (regno
>= 8 && regno
< 24)
3653 return !epilogue_renumber (&pat
, 1);
3656 if (GET_CODE (pat
) != SET
)
3659 if (GET_CODE (SET_DEST (pat
)) != REG
)
3662 regno
= REGNO (SET_DEST (pat
));
3664 /* Otherwise, only operations which can be done in tandem with
3665 a `restore' or `return' insn can go into the delay slot. */
3666 if (regno
>= 8 && regno
< 24)
3669 /* If this instruction sets up floating point register and we have a return
3670 instruction, it can probably go in. But restore will not work
3672 if (! SPARC_INT_REG_P (regno
))
3673 return TARGET_V9
&& !epilogue_renumber (&pat
, 1);
3675 return eligible_for_restore_insn (trial
, true);
3678 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */
3681 eligible_for_sibcall_delay (rtx_insn
*trial
)
3685 if (get_attr_in_branch_delay (trial
) == IN_BRANCH_DELAY_FALSE
)
3688 if (!NONJUMP_INSN_P (trial
))
3691 pat
= PATTERN (trial
);
3693 if (sparc_leaf_function_p
|| TARGET_FLAT
)
3695 /* If the tail call is done using the call instruction,
3696 we have to restore %o7 in the delay slot. */
3697 if (LEAF_SIBCALL_SLOT_RESERVED_P
)
3700 /* %g1 is used to build the function address */
3701 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
3707 if (GET_CODE (pat
) != SET
)
3710 /* Otherwise, only operations which can be done in tandem with
3711 a `restore' insn can go into the delay slot. */
3712 if (GET_CODE (SET_DEST (pat
)) != REG
3713 || (REGNO (SET_DEST (pat
)) >= 8 && REGNO (SET_DEST (pat
)) < 24)
3714 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat
))))
3717 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3719 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
3722 return eligible_for_restore_insn (trial
, false);
3725 /* Determine if it's legal to put X into the constant pool. This
3726 is not possible if X contains the address of a symbol that is
3727 not constant (TLS) or not known at final link time (PIC). */
3730 sparc_cannot_force_const_mem (enum machine_mode mode
, rtx x
)
3732 switch (GET_CODE (x
))
3737 /* Accept all non-symbolic constants. */
3741 /* Labels are OK iff we are non-PIC. */
3742 return flag_pic
!= 0;
3745 /* 'Naked' TLS symbol references are never OK,
3746 non-TLS symbols are OK iff we are non-PIC. */
3747 if (SYMBOL_REF_TLS_MODEL (x
))
3750 return flag_pic
!= 0;
3753 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0));
3756 return sparc_cannot_force_const_mem (mode
, XEXP (x
, 0))
3757 || sparc_cannot_force_const_mem (mode
, XEXP (x
, 1));
3765 /* Global Offset Table support. */
3766 static GTY(()) rtx got_helper_rtx
= NULL_RTX
;
3767 static GTY(()) rtx global_offset_table_rtx
= NULL_RTX
;
3769 /* Return the SYMBOL_REF for the Global Offset Table. */
3771 static GTY(()) rtx sparc_got_symbol
= NULL_RTX
;
3776 if (!sparc_got_symbol
)
3777 sparc_got_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3779 return sparc_got_symbol
;
3782 /* Ensure that we are not using patterns that are not OK with PIC. */
3792 op
= recog_data
.operand
[i
];
3793 gcc_assert (GET_CODE (op
) != SYMBOL_REF
3794 && (GET_CODE (op
) != CONST
3795 || (GET_CODE (XEXP (op
, 0)) == MINUS
3796 && XEXP (XEXP (op
, 0), 0) == sparc_got ()
3797 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == CONST
)));
3804 /* Return true if X is an address which needs a temporary register when
3805 reloaded while generating PIC code. */
3808 pic_address_needs_scratch (rtx x
)
3810 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3811 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3812 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3813 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3814 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3820 /* Determine if a given RTX is a valid constant. We already know this
3821 satisfies CONSTANT_P. */
3824 sparc_legitimate_constant_p (enum machine_mode mode
, rtx x
)
3826 switch (GET_CODE (x
))
3830 if (sparc_tls_referenced_p (x
))
3835 if (GET_MODE (x
) == VOIDmode
)
3838 /* Floating point constants are generally not ok.
3839 The only exception is 0.0 and all-ones in VIS. */
3841 && SCALAR_FLOAT_MODE_P (mode
)
3842 && (const_zero_operand (x
, mode
)
3843 || const_all_ones_operand (x
, mode
)))
3849 /* Vector constants are generally not ok.
3850 The only exception is 0 or -1 in VIS. */
3852 && (const_zero_operand (x
, mode
)
3853 || const_all_ones_operand (x
, mode
)))
3865 /* Determine if a given RTX is a valid constant address. */
3868 constant_address_p (rtx x
)
3870 switch (GET_CODE (x
))
3878 if (flag_pic
&& pic_address_needs_scratch (x
))
3880 return sparc_legitimate_constant_p (Pmode
, x
);
3883 return !flag_pic
&& sparc_legitimate_constant_p (Pmode
, x
);
3890 /* Nonzero if the constant value X is a legitimate general operand
3891 when generating PIC code. It is given that flag_pic is on and
3892 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3895 legitimate_pic_operand_p (rtx x
)
3897 if (pic_address_needs_scratch (x
))
3899 if (sparc_tls_referenced_p (x
))
3904 #define RTX_OK_FOR_OFFSET_P(X, MODE) \
3906 && INTVAL (X) >= -0x1000 \
3907 && INTVAL (X) < (0x1000 - GET_MODE_SIZE (MODE)))
3909 #define RTX_OK_FOR_OLO10_P(X, MODE) \
3911 && INTVAL (X) >= -0x1000 \
3912 && INTVAL (X) < (0xc00 - GET_MODE_SIZE (MODE)))
3914 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook.
3916 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT
3917 ordinarily. This changes a bit when generating PIC. */
3920 sparc_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
3922 rtx rs1
= NULL
, rs2
= NULL
, imm1
= NULL
;
3924 if (REG_P (addr
) || GET_CODE (addr
) == SUBREG
)
3926 else if (GET_CODE (addr
) == PLUS
)
3928 rs1
= XEXP (addr
, 0);
3929 rs2
= XEXP (addr
, 1);
3931 /* Canonicalize. REG comes first, if there are no regs,
3932 LO_SUM comes first. */
3934 && GET_CODE (rs1
) != SUBREG
3936 || GET_CODE (rs2
) == SUBREG
3937 || (GET_CODE (rs2
) == LO_SUM
&& GET_CODE (rs1
) != LO_SUM
)))
3939 rs1
= XEXP (addr
, 1);
3940 rs2
= XEXP (addr
, 0);
3944 && rs1
== pic_offset_table_rtx
3946 && GET_CODE (rs2
) != SUBREG
3947 && GET_CODE (rs2
) != LO_SUM
3948 && GET_CODE (rs2
) != MEM
3949 && !(GET_CODE (rs2
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs2
))
3950 && (! symbolic_operand (rs2
, VOIDmode
) || mode
== Pmode
)
3951 && (GET_CODE (rs2
) != CONST_INT
|| SMALL_INT (rs2
)))
3953 || GET_CODE (rs1
) == SUBREG
)
3954 && RTX_OK_FOR_OFFSET_P (rs2
, mode
)))
3959 else if ((REG_P (rs1
) || GET_CODE (rs1
) == SUBREG
)
3960 && (REG_P (rs2
) || GET_CODE (rs2
) == SUBREG
))
3962 /* We prohibit REG + REG for TFmode when there are no quad move insns
3963 and we consequently need to split. We do this because REG+REG
3964 is not an offsettable address. If we get the situation in reload
3965 where source and destination of a movtf pattern are both MEMs with
3966 REG+REG address, then only one of them gets converted to an
3967 offsettable address. */
3969 && ! (TARGET_ARCH64
&& TARGET_HARD_QUAD
))
3972 /* Likewise for TImode, but in all cases. */
3976 /* We prohibit REG + REG on ARCH32 if not optimizing for
3977 DFmode/DImode because then mem_min_alignment is likely to be zero
3978 after reload and the forced split would lack a matching splitter
3980 if (TARGET_ARCH32
&& !optimize
3981 && (mode
== DFmode
|| mode
== DImode
))
3984 else if (USE_AS_OFFSETABLE_LO10
3985 && GET_CODE (rs1
) == LO_SUM
3987 && ! TARGET_CM_MEDMID
3988 && RTX_OK_FOR_OLO10_P (rs2
, mode
))
3991 imm1
= XEXP (rs1
, 1);
3992 rs1
= XEXP (rs1
, 0);
3993 if (!CONSTANT_P (imm1
)
3994 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
3998 else if (GET_CODE (addr
) == LO_SUM
)
4000 rs1
= XEXP (addr
, 0);
4001 imm1
= XEXP (addr
, 1);
4003 if (!CONSTANT_P (imm1
)
4004 || (GET_CODE (rs1
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (rs1
)))
4007 /* We can't allow TFmode in 32-bit mode, because an offset greater
4008 than the alignment (8) may cause the LO_SUM to overflow. */
4009 if (mode
== TFmode
&& TARGET_ARCH32
)
4012 else if (GET_CODE (addr
) == CONST_INT
&& SMALL_INT (addr
))
4017 if (GET_CODE (rs1
) == SUBREG
)
4018 rs1
= SUBREG_REG (rs1
);
4024 if (GET_CODE (rs2
) == SUBREG
)
4025 rs2
= SUBREG_REG (rs2
);
4032 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1
))
4033 || (rs2
&& !REGNO_OK_FOR_BASE_P (REGNO (rs2
))))
4038 if ((! SPARC_INT_REG_P (REGNO (rs1
))
4039 && REGNO (rs1
) != FRAME_POINTER_REGNUM
4040 && REGNO (rs1
) < FIRST_PSEUDO_REGISTER
)
4042 && (! SPARC_INT_REG_P (REGNO (rs2
))
4043 && REGNO (rs2
) != FRAME_POINTER_REGNUM
4044 && REGNO (rs2
) < FIRST_PSEUDO_REGISTER
)))
4050 /* Return the SYMBOL_REF for the tls_get_addr function. */
4052 static GTY(()) rtx sparc_tls_symbol
= NULL_RTX
;
4055 sparc_tls_get_addr (void)
4057 if (!sparc_tls_symbol
)
4058 sparc_tls_symbol
= gen_rtx_SYMBOL_REF (Pmode
, "__tls_get_addr");
4060 return sparc_tls_symbol
;
4063 /* Return the Global Offset Table to be used in TLS mode. */
4066 sparc_tls_got (void)
4068 /* In PIC mode, this is just the PIC offset table. */
4071 crtl
->uses_pic_offset_table
= 1;
4072 return pic_offset_table_rtx
;
4075 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for
4076 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */
4077 if (TARGET_SUN_TLS
&& TARGET_ARCH32
)
4079 load_got_register ();
4080 return global_offset_table_rtx
;
4083 /* In all other cases, we load a new pseudo with the GOT symbol. */
4084 return copy_to_reg (sparc_got ());
4087 /* Return true if X contains a thread-local symbol. */
4090 sparc_tls_referenced_p (rtx x
)
4092 if (!TARGET_HAVE_TLS
)
4095 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4096 x
= XEXP (XEXP (x
, 0), 0);
4098 if (GET_CODE (x
) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (x
))
4101 /* That's all we handle in sparc_legitimize_tls_address for now. */
4105 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
4106 this (thread-local) address. */
4109 sparc_legitimize_tls_address (rtx addr
)
4111 rtx temp1
, temp2
, temp3
, ret
, o0
, got
;
4114 gcc_assert (can_create_pseudo_p ());
4116 if (GET_CODE (addr
) == SYMBOL_REF
)
4117 switch (SYMBOL_REF_TLS_MODEL (addr
))
4119 case TLS_MODEL_GLOBAL_DYNAMIC
:
4121 temp1
= gen_reg_rtx (SImode
);
4122 temp2
= gen_reg_rtx (SImode
);
4123 ret
= gen_reg_rtx (Pmode
);
4124 o0
= gen_rtx_REG (Pmode
, 8);
4125 got
= sparc_tls_got ();
4126 emit_insn (gen_tgd_hi22 (temp1
, addr
));
4127 emit_insn (gen_tgd_lo10 (temp2
, temp1
, addr
));
4130 emit_insn (gen_tgd_add32 (o0
, got
, temp2
, addr
));
4131 insn
= emit_call_insn (gen_tgd_call32 (o0
, sparc_tls_get_addr (),
4136 emit_insn (gen_tgd_add64 (o0
, got
, temp2
, addr
));
4137 insn
= emit_call_insn (gen_tgd_call64 (o0
, sparc_tls_get_addr (),
4140 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4141 insn
= get_insns ();
4143 emit_libcall_block (insn
, ret
, o0
, addr
);
4146 case TLS_MODEL_LOCAL_DYNAMIC
:
4148 temp1
= gen_reg_rtx (SImode
);
4149 temp2
= gen_reg_rtx (SImode
);
4150 temp3
= gen_reg_rtx (Pmode
);
4151 ret
= gen_reg_rtx (Pmode
);
4152 o0
= gen_rtx_REG (Pmode
, 8);
4153 got
= sparc_tls_got ();
4154 emit_insn (gen_tldm_hi22 (temp1
));
4155 emit_insn (gen_tldm_lo10 (temp2
, temp1
));
4158 emit_insn (gen_tldm_add32 (o0
, got
, temp2
));
4159 insn
= emit_call_insn (gen_tldm_call32 (o0
, sparc_tls_get_addr (),
4164 emit_insn (gen_tldm_add64 (o0
, got
, temp2
));
4165 insn
= emit_call_insn (gen_tldm_call64 (o0
, sparc_tls_get_addr (),
4168 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), o0
);
4169 insn
= get_insns ();
4171 emit_libcall_block (insn
, temp3
, o0
,
4172 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, const0_rtx
),
4173 UNSPEC_TLSLD_BASE
));
4174 temp1
= gen_reg_rtx (SImode
);
4175 temp2
= gen_reg_rtx (SImode
);
4176 emit_insn (gen_tldo_hix22 (temp1
, addr
));
4177 emit_insn (gen_tldo_lox10 (temp2
, temp1
, addr
));
4179 emit_insn (gen_tldo_add32 (ret
, temp3
, temp2
, addr
));
4181 emit_insn (gen_tldo_add64 (ret
, temp3
, temp2
, addr
));
4184 case TLS_MODEL_INITIAL_EXEC
:
4185 temp1
= gen_reg_rtx (SImode
);
4186 temp2
= gen_reg_rtx (SImode
);
4187 temp3
= gen_reg_rtx (Pmode
);
4188 got
= sparc_tls_got ();
4189 emit_insn (gen_tie_hi22 (temp1
, addr
));
4190 emit_insn (gen_tie_lo10 (temp2
, temp1
, addr
));
4192 emit_insn (gen_tie_ld32 (temp3
, got
, temp2
, addr
));
4194 emit_insn (gen_tie_ld64 (temp3
, got
, temp2
, addr
));
4197 ret
= gen_reg_rtx (Pmode
);
4199 emit_insn (gen_tie_add32 (ret
, gen_rtx_REG (Pmode
, 7),
4202 emit_insn (gen_tie_add64 (ret
, gen_rtx_REG (Pmode
, 7),
4206 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp3
);
4209 case TLS_MODEL_LOCAL_EXEC
:
4210 temp1
= gen_reg_rtx (Pmode
);
4211 temp2
= gen_reg_rtx (Pmode
);
4214 emit_insn (gen_tle_hix22_sp32 (temp1
, addr
));
4215 emit_insn (gen_tle_lox10_sp32 (temp2
, temp1
, addr
));
4219 emit_insn (gen_tle_hix22_sp64 (temp1
, addr
));
4220 emit_insn (gen_tle_lox10_sp64 (temp2
, temp1
, addr
));
4222 ret
= gen_rtx_PLUS (Pmode
, gen_rtx_REG (Pmode
, 7), temp2
);
4229 else if (GET_CODE (addr
) == CONST
)
4233 gcc_assert (GET_CODE (XEXP (addr
, 0)) == PLUS
);
4235 base
= sparc_legitimize_tls_address (XEXP (XEXP (addr
, 0), 0));
4236 offset
= XEXP (XEXP (addr
, 0), 1);
4238 base
= force_operand (base
, NULL_RTX
);
4239 if (!(GET_CODE (offset
) == CONST_INT
&& SMALL_INT (offset
)))
4240 offset
= force_reg (Pmode
, offset
);
4241 ret
= gen_rtx_PLUS (Pmode
, base
, offset
);
4245 gcc_unreachable (); /* for now ... */
4250 /* Legitimize PIC addresses. If the address is already position-independent,
4251 we return ORIG. Newly generated position-independent addresses go into a
4252 reg. This is REG if nonzero, otherwise we allocate register(s) as
4256 sparc_legitimize_pic_address (rtx orig
, rtx reg
)
4258 bool gotdata_op
= false;
4260 if (GET_CODE (orig
) == SYMBOL_REF
4261 /* See the comment in sparc_expand_move. */
4262 || (GET_CODE (orig
) == LABEL_REF
&& !can_use_mov_pic_label_ref (orig
)))
4264 rtx pic_ref
, address
;
4269 gcc_assert (can_create_pseudo_p ());
4270 reg
= gen_reg_rtx (Pmode
);
4275 /* If not during reload, allocate another temp reg here for loading
4276 in the address, so that these instructions can be optimized
4278 rtx temp_reg
= (! can_create_pseudo_p ()
4279 ? reg
: gen_reg_rtx (Pmode
));
4281 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
4282 won't get confused into thinking that these two instructions
4283 are loading in the true address of the symbol. If in the
4284 future a PIC rtx exists, that should be used instead. */
4287 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
4288 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4292 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
4293 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
4301 crtl
->uses_pic_offset_table
= 1;
4305 insn
= emit_insn (gen_movdi_pic_gotdata_op (reg
,
4306 pic_offset_table_rtx
,
4309 insn
= emit_insn (gen_movsi_pic_gotdata_op (reg
,
4310 pic_offset_table_rtx
,
4316 = gen_const_mem (Pmode
,
4317 gen_rtx_PLUS (Pmode
,
4318 pic_offset_table_rtx
, address
));
4319 insn
= emit_move_insn (reg
, pic_ref
);
4322 /* Put a REG_EQUAL note on this insn, so that it can be optimized
4324 set_unique_reg_note (insn
, REG_EQUAL
, orig
);
4327 else if (GET_CODE (orig
) == CONST
)
4331 if (GET_CODE (XEXP (orig
, 0)) == PLUS
4332 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
4337 gcc_assert (can_create_pseudo_p ());
4338 reg
= gen_reg_rtx (Pmode
);
4341 gcc_assert (GET_CODE (XEXP (orig
, 0)) == PLUS
);
4342 base
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), reg
);
4343 offset
= sparc_legitimize_pic_address (XEXP (XEXP (orig
, 0), 1),
4344 base
== reg
? NULL_RTX
: reg
);
4346 if (GET_CODE (offset
) == CONST_INT
)
4348 if (SMALL_INT (offset
))
4349 return plus_constant (Pmode
, base
, INTVAL (offset
));
4350 else if (can_create_pseudo_p ())
4351 offset
= force_reg (Pmode
, offset
);
4353 /* If we reach here, then something is seriously wrong. */
4356 return gen_rtx_PLUS (Pmode
, base
, offset
);
4358 else if (GET_CODE (orig
) == LABEL_REF
)
4359 /* ??? We ought to be checking that the register is live instead, in case
4360 it is eliminated. */
4361 crtl
->uses_pic_offset_table
= 1;
4366 /* Try machine-dependent ways of modifying an illegitimate address X
4367 to be legitimate. If we find one, return the new, valid address.
4369 OLDX is the address as it was before break_out_memory_refs was called.
4370 In some cases it is useful to look at this to decide what needs to be done.
4372 MODE is the mode of the operand pointed to by X.
4374 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */
4377 sparc_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
4378 enum machine_mode mode
)
4382 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
)
4383 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4384 force_operand (XEXP (x
, 0), NULL_RTX
));
4385 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == MULT
)
4386 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4387 force_operand (XEXP (x
, 1), NULL_RTX
));
4388 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
)
4389 x
= gen_rtx_PLUS (Pmode
, force_operand (XEXP (x
, 0), NULL_RTX
),
4391 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == PLUS
)
4392 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4393 force_operand (XEXP (x
, 1), NULL_RTX
));
4395 if (x
!= orig_x
&& sparc_legitimate_address_p (mode
, x
, FALSE
))
4398 if (sparc_tls_referenced_p (x
))
4399 x
= sparc_legitimize_tls_address (x
);
4401 x
= sparc_legitimize_pic_address (x
, NULL_RTX
);
4402 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 1)))
4403 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 0),
4404 copy_to_mode_reg (Pmode
, XEXP (x
, 1)));
4405 else if (GET_CODE (x
) == PLUS
&& CONSTANT_ADDRESS_P (XEXP (x
, 0)))
4406 x
= gen_rtx_PLUS (Pmode
, XEXP (x
, 1),
4407 copy_to_mode_reg (Pmode
, XEXP (x
, 0)));
4408 else if (GET_CODE (x
) == SYMBOL_REF
4409 || GET_CODE (x
) == CONST
4410 || GET_CODE (x
) == LABEL_REF
)
4411 x
= copy_to_suggested_reg (x
, NULL_RTX
, Pmode
);
4416 /* Delegitimize an address that was legitimized by the above function. */
4419 sparc_delegitimize_address (rtx x
)
4421 x
= delegitimize_mem_from_attrs (x
);
4423 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 1)) == UNSPEC
)
4424 switch (XINT (XEXP (x
, 1), 1))
4426 case UNSPEC_MOVE_PIC
:
4428 x
= XVECEXP (XEXP (x
, 1), 0, 0);
4429 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
4435 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */
4436 if (GET_CODE (x
) == MINUS
4437 && REG_P (XEXP (x
, 0))
4438 && REGNO (XEXP (x
, 0)) == PIC_OFFSET_TABLE_REGNUM
4439 && GET_CODE (XEXP (x
, 1)) == LO_SUM
4440 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == UNSPEC
4441 && XINT (XEXP (XEXP (x
, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL
)
4443 x
= XVECEXP (XEXP (XEXP (x
, 1), 1), 0, 0);
4444 gcc_assert (GET_CODE (x
) == LABEL_REF
);
4450 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
4451 replace the input X, or the original X if no replacement is called for.
4452 The output parameter *WIN is 1 if the calling macro should goto WIN,
4455 For SPARC, we wish to handle addresses by splitting them into
4456 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference.
4457 This cuts the number of extra insns by one.
4459 Do nothing when generating PIC code and the address is a symbolic
4460 operand or requires a scratch register. */
4463 sparc_legitimize_reload_address (rtx x
, enum machine_mode mode
,
4464 int opnum
, int type
,
4465 int ind_levels ATTRIBUTE_UNUSED
, int *win
)
4467 /* Decompose SImode constants into HIGH+LO_SUM. */
4469 && (mode
!= TFmode
|| TARGET_ARCH64
)
4470 && GET_MODE (x
) == SImode
4471 && GET_CODE (x
) != LO_SUM
4472 && GET_CODE (x
) != HIGH
4473 && sparc_cmodel
<= CM_MEDLOW
4475 && (symbolic_operand (x
, Pmode
) || pic_address_needs_scratch (x
))))
4477 x
= gen_rtx_LO_SUM (GET_MODE (x
), gen_rtx_HIGH (GET_MODE (x
), x
), x
);
4478 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4479 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4480 opnum
, (enum reload_type
)type
);
4485 /* We have to recognize what we have already generated above. */
4486 if (GET_CODE (x
) == LO_SUM
&& GET_CODE (XEXP (x
, 0)) == HIGH
)
4488 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
4489 BASE_REG_CLASS
, GET_MODE (x
), VOIDmode
, 0, 0,
4490 opnum
, (enum reload_type
)type
);
4499 /* Return true if ADDR (a legitimate address expression)
4500 has an effect that depends on the machine mode it is used for.
4506 is not equivalent to
4508 (mem:QI [%l7+a]) (mem:QI [%l7+a+1])
4510 because [%l7+a+1] is interpreted as the address of (a+1). */
4514 sparc_mode_dependent_address_p (const_rtx addr
,
4515 addr_space_t as ATTRIBUTE_UNUSED
)
4517 if (flag_pic
&& GET_CODE (addr
) == PLUS
)
4519 rtx op0
= XEXP (addr
, 0);
4520 rtx op1
= XEXP (addr
, 1);
4521 if (op0
== pic_offset_table_rtx
4522 && symbolic_operand (op1
, VOIDmode
))
4529 #ifdef HAVE_GAS_HIDDEN
4530 # define USE_HIDDEN_LINKONCE 1
4532 # define USE_HIDDEN_LINKONCE 0
4536 get_pc_thunk_name (char name
[32], unsigned int regno
)
4538 const char *reg_name
= reg_names
[regno
];
4540 /* Skip the leading '%' as that cannot be used in a
4544 if (USE_HIDDEN_LINKONCE
)
4545 sprintf (name
, "__sparc_get_pc_thunk.%s", reg_name
);
4547 ASM_GENERATE_INTERNAL_LABEL (name
, "LADDPC", regno
);
4550 /* Wrapper around the load_pcrel_sym{si,di} patterns. */
4553 gen_load_pcrel_sym (rtx op0
, rtx op1
, rtx op2
, rtx op3
)
4555 int orig_flag_pic
= flag_pic
;
4558 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */
4561 insn
= gen_load_pcrel_symdi (op0
, op1
, op2
, op3
);
4563 insn
= gen_load_pcrel_symsi (op0
, op1
, op2
, op3
);
4564 flag_pic
= orig_flag_pic
;
4569 /* Emit code to load the GOT register. */
4572 load_got_register (void)
4574 /* In PIC mode, this will retrieve pic_offset_table_rtx. */
4575 if (!global_offset_table_rtx
)
4576 global_offset_table_rtx
= gen_rtx_REG (Pmode
, GLOBAL_OFFSET_TABLE_REGNUM
);
4578 if (TARGET_VXWORKS_RTP
)
4579 emit_insn (gen_vxworks_load_got ());
4582 /* The GOT symbol is subject to a PC-relative relocation so we need a
4583 helper function to add the PC value and thus get the final value. */
4584 if (!got_helper_rtx
)
4587 get_pc_thunk_name (name
, GLOBAL_OFFSET_TABLE_REGNUM
);
4588 got_helper_rtx
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (name
));
4591 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx
, sparc_got (),
4593 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM
)));
4596 /* Need to emit this whether or not we obey regdecls,
4597 since setjmp/longjmp can cause life info to screw up.
4598 ??? In the case where we don't obey regdecls, this is not sufficient
4599 since we may not fall out the bottom. */
4600 emit_use (global_offset_table_rtx
);
4603 /* Emit a call instruction with the pattern given by PAT. ADDR is the
4604 address of the call target. */
4607 sparc_emit_call_insn (rtx pat
, rtx addr
)
4611 insn
= emit_call_insn (pat
);
4613 /* The PIC register is live on entry to VxWorks PIC PLT entries. */
4614 if (TARGET_VXWORKS_RTP
4616 && GET_CODE (addr
) == SYMBOL_REF
4617 && (SYMBOL_REF_DECL (addr
)
4618 ? !targetm
.binds_local_p (SYMBOL_REF_DECL (addr
))
4619 : !SYMBOL_REF_LOCAL_P (addr
)))
4621 use_reg (&CALL_INSN_FUNCTION_USAGE (insn
), pic_offset_table_rtx
);
4622 crtl
->uses_pic_offset_table
= 1;
4626 /* Return 1 if RTX is a MEM which is known to be aligned to at
4627 least a DESIRED byte boundary. */
4630 mem_min_alignment (rtx mem
, int desired
)
4632 rtx addr
, base
, offset
;
4634 /* If it's not a MEM we can't accept it. */
4635 if (GET_CODE (mem
) != MEM
)
4639 if (!TARGET_UNALIGNED_DOUBLES
4640 && MEM_ALIGN (mem
) / BITS_PER_UNIT
>= (unsigned)desired
)
4643 /* ??? The rest of the function predates MEM_ALIGN so
4644 there is probably a bit of redundancy. */
4645 addr
= XEXP (mem
, 0);
4646 base
= offset
= NULL_RTX
;
4647 if (GET_CODE (addr
) == PLUS
)
4649 if (GET_CODE (XEXP (addr
, 0)) == REG
)
4651 base
= XEXP (addr
, 0);
4653 /* What we are saying here is that if the base
4654 REG is aligned properly, the compiler will make
4655 sure any REG based index upon it will be so
4657 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
4658 offset
= XEXP (addr
, 1);
4660 offset
= const0_rtx
;
4663 else if (GET_CODE (addr
) == REG
)
4666 offset
= const0_rtx
;
4669 if (base
!= NULL_RTX
)
4671 int regno
= REGNO (base
);
4673 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
4675 /* Check if the compiler has recorded some information
4676 about the alignment of the base REG. If reload has
4677 completed, we already matched with proper alignments.
4678 If not running global_alloc, reload might give us
4679 unaligned pointer to local stack though. */
4681 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
4682 || (optimize
&& reload_completed
))
4683 && (INTVAL (offset
) & (desired
- 1)) == 0)
4688 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
4692 else if (! TARGET_UNALIGNED_DOUBLES
4693 || CONSTANT_P (addr
)
4694 || GET_CODE (addr
) == LO_SUM
)
4696 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
4697 is true, in which case we can only assume that an access is aligned if
4698 it is to a constant address, or the address involves a LO_SUM. */
4702 /* An obviously unaligned address. */
4707 /* Vectors to keep interesting information about registers where it can easily
4708 be got. We used to use the actual mode value as the bit number, but there
4709 are more than 32 modes now. Instead we use two tables: one indexed by
4710 hard register number, and one indexed by mode. */
4712 /* The purpose of sparc_mode_class is to shrink the range of modes so that
4713 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is
4714 mapped into one sparc_mode_class mode. */
4716 enum sparc_mode_class
{
4717 H_MODE
, S_MODE
, D_MODE
, T_MODE
, O_MODE
,
4718 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
4722 /* Modes for single-word and smaller quantities. */
4724 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
4726 /* Modes for double-word and smaller quantities. */
4727 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4729 /* Modes for quad-word and smaller quantities. */
4730 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
4732 /* Modes for 8-word and smaller quantities. */
4733 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
4735 /* Modes for single-float quantities. */
4736 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
4738 /* Modes for double-float and smaller quantities. */
4739 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
4741 /* Modes for quad-float and smaller quantities. */
4742 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
4744 /* Modes for quad-float pairs and smaller quantities. */
4745 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE))
4747 /* Modes for double-float only quantities. */
4748 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
4750 /* Modes for quad-float and double-float only quantities. */
4751 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE))
4753 /* Modes for quad-float pairs and double-float only quantities. */
4754 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE))
4756 /* Modes for condition codes. */
4757 #define CC_MODES (1 << (int) CC_MODE)
4758 #define CCFP_MODES (1 << (int) CCFP_MODE)
4760 /* Value is 1 if register/mode pair is acceptable on sparc.
4761 The funny mixture of D and T modes is because integer operations
4762 do not specially operate on tetra quantities, so non-quad-aligned
4763 registers can hold quadword quantities (except %o4 and %i4 because
4764 they cross fixed registers). */
4766 /* This points to either the 32 bit or the 64 bit version. */
4767 const int *hard_regno_mode_classes
;
4769 static const int hard_32bit_mode_classes
[] = {
4770 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4771 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4772 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
4773 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
4775 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4776 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4777 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4778 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4780 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4781 and none can hold SFmode/SImode values. */
4782 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4783 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4784 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4785 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4788 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4790 /* %icc, %sfp, %gsr */
4791 CC_MODES
, 0, D_MODES
4794 static const int hard_64bit_mode_classes
[] = {
4795 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4796 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4797 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4798 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
4800 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4801 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4802 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4803 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
4805 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4806 and none can hold SFmode/SImode values. */
4807 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4808 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4809 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4810 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
4813 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
4815 /* %icc, %sfp, %gsr */
4816 CC_MODES
, 0, D_MODES
4819 int sparc_mode_class
[NUM_MACHINE_MODES
];
4821 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
4824 sparc_init_modes (void)
4828 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
4830 enum machine_mode m
= (enum machine_mode
) i
;
4831 unsigned int size
= GET_MODE_SIZE (m
);
4833 switch (GET_MODE_CLASS (m
))
4836 case MODE_PARTIAL_INT
:
4837 case MODE_COMPLEX_INT
:
4839 sparc_mode_class
[i
] = 1 << (int) H_MODE
;
4841 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
4843 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
4844 else if (size
== 16)
4845 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
4846 else if (size
== 32)
4847 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
4849 sparc_mode_class
[i
] = 0;
4851 case MODE_VECTOR_INT
:
4853 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4855 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4857 sparc_mode_class
[i
] = 0;
4860 case MODE_COMPLEX_FLOAT
:
4862 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
4864 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
4865 else if (size
== 16)
4866 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
4867 else if (size
== 32)
4868 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
4870 sparc_mode_class
[i
] = 0;
4873 if (m
== CCFPmode
|| m
== CCFPEmode
)
4874 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
4876 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
4879 sparc_mode_class
[i
] = 0;
4885 hard_regno_mode_classes
= hard_64bit_mode_classes
;
4887 hard_regno_mode_classes
= hard_32bit_mode_classes
;
4889 /* Initialize the array used by REGNO_REG_CLASS. */
4890 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4892 if (i
< 16 && TARGET_V8PLUS
)
4893 sparc_regno_reg_class
[i
] = I64_REGS
;
4894 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
4895 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
4897 sparc_regno_reg_class
[i
] = FP_REGS
;
4899 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
4901 sparc_regno_reg_class
[i
] = FPCC_REGS
;
4903 sparc_regno_reg_class
[i
] = NO_REGS
;
4907 /* Return whether REGNO, a global or FP register, must be saved/restored. */
4910 save_global_or_fp_reg_p (unsigned int regno
,
4911 int leaf_function ATTRIBUTE_UNUSED
)
4913 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
4916 /* Return whether the return address register (%i7) is needed. */
4919 return_addr_reg_needed_p (int leaf_function
)
4921 /* If it is live, for example because of __builtin_return_address (0). */
4922 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM
))
4925 /* Otherwise, it is needed as save register if %o7 is clobbered. */
4927 /* Loading the GOT register clobbers %o7. */
4928 || crtl
->uses_pic_offset_table
4929 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM
))
4935 /* Return whether REGNO, a local or in register, must be saved/restored. */
4938 save_local_or_in_reg_p (unsigned int regno
, int leaf_function
)
4940 /* General case: call-saved registers live at some point. */
4941 if (!call_used_regs
[regno
] && df_regs_ever_live_p (regno
))
4944 /* Frame pointer register (%fp) if needed. */
4945 if (regno
== HARD_FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
4948 /* Return address register (%i7) if needed. */
4949 if (regno
== RETURN_ADDR_REGNUM
&& return_addr_reg_needed_p (leaf_function
))
4952 /* GOT register (%l7) if needed. */
4953 if (regno
== PIC_OFFSET_TABLE_REGNUM
&& crtl
->uses_pic_offset_table
)
4956 /* If the function accesses prior frames, the frame pointer and the return
4957 address of the previous frame must be saved on the stack. */
4958 if (crtl
->accesses_prior_frames
4959 && (regno
== HARD_FRAME_POINTER_REGNUM
|| regno
== RETURN_ADDR_REGNUM
))
4965 /* Compute the frame size required by the function. This function is called
4966 during the reload pass and also by sparc_expand_prologue. */
4969 sparc_compute_frame_size (HOST_WIDE_INT size
, int leaf_function
)
4971 HOST_WIDE_INT frame_size
, apparent_frame_size
;
4972 int args_size
, n_global_fp_regs
= 0;
4973 bool save_local_in_regs_p
= false;
4976 /* If the function allocates dynamic stack space, the dynamic offset is
4977 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */
4978 if (leaf_function
&& !cfun
->calls_alloca
)
4981 args_size
= crtl
->outgoing_args_size
+ REG_PARM_STACK_SPACE (cfun
->decl
);
4983 /* Calculate space needed for global registers. */
4985 for (i
= 0; i
< 8; i
++)
4986 if (save_global_or_fp_reg_p (i
, 0))
4987 n_global_fp_regs
+= 2;
4989 for (i
= 0; i
< 8; i
+= 2)
4990 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
4991 n_global_fp_regs
+= 2;
4993 /* In the flat window model, find out which local and in registers need to
4994 be saved. We don't reserve space in the current frame for them as they
4995 will be spilled into the register window save area of the caller's frame.
4996 However, as soon as we use this register window save area, we must create
4997 that of the current frame to make it the live one. */
4999 for (i
= 16; i
< 32; i
++)
5000 if (save_local_or_in_reg_p (i
, leaf_function
))
5002 save_local_in_regs_p
= true;
5006 /* Calculate space needed for FP registers. */
5007 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
5008 if (save_global_or_fp_reg_p (i
, 0) || save_global_or_fp_reg_p (i
+ 1, 0))
5009 n_global_fp_regs
+= 2;
5012 && n_global_fp_regs
== 0
5014 && !save_local_in_regs_p
)
5015 frame_size
= apparent_frame_size
= 0;
5018 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
5019 apparent_frame_size
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
5020 apparent_frame_size
+= n_global_fp_regs
* 4;
5022 /* We need to add the size of the outgoing argument area. */
5023 frame_size
= apparent_frame_size
+ ((args_size
+ 7) & -8);
5025 /* And that of the register window save area. */
5026 frame_size
+= FIRST_PARM_OFFSET (cfun
->decl
);
5028 /* Finally, bump to the appropriate alignment. */
5029 frame_size
= SPARC_STACK_ALIGN (frame_size
);
5032 /* Set up values for use in prologue and epilogue. */
5033 sparc_frame_size
= frame_size
;
5034 sparc_apparent_frame_size
= apparent_frame_size
;
5035 sparc_n_global_fp_regs
= n_global_fp_regs
;
5036 sparc_save_local_in_regs_p
= save_local_in_regs_p
;
5041 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */
5044 sparc_initial_elimination_offset (int to
)
5048 if (to
== STACK_POINTER_REGNUM
)
5049 offset
= sparc_compute_frame_size (get_frame_size (), crtl
->is_leaf
);
5053 offset
+= SPARC_STACK_BIAS
;
5057 /* Output any necessary .register pseudo-ops. */
5060 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED
)
5062 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
5068 /* Check if %g[2367] were used without
5069 .register being printed for them already. */
5070 for (i
= 2; i
< 8; i
++)
5072 if (df_regs_ever_live_p (i
)
5073 && ! sparc_hard_reg_printed
[i
])
5075 sparc_hard_reg_printed
[i
] = 1;
5076 /* %g7 is used as TLS base register, use #ignore
5077 for it instead of #scratch. */
5078 fprintf (file
, "\t.register\t%%g%d, #%s\n", i
,
5079 i
== 7 ? "ignore" : "scratch");
5086 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
5088 #if PROBE_INTERVAL > 4096
5089 #error Cannot use indexed addressing mode for stack probing
5092 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
5093 inclusive. These are offsets from the current stack pointer.
5095 Note that we don't use the REG+REG addressing mode for the probes because
5096 of the stack bias in 64-bit mode. And it doesn't really buy us anything
5097 so the advantages of having a single code win here. */
5100 sparc_emit_probe_stack_range (HOST_WIDE_INT first
, HOST_WIDE_INT size
)
5102 rtx g1
= gen_rtx_REG (Pmode
, 1);
5104 /* See if we have a constant small number of probes to generate. If so,
5105 that's the easy case. */
5106 if (size
<= PROBE_INTERVAL
)
5108 emit_move_insn (g1
, GEN_INT (first
));
5109 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5110 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5111 emit_stack_probe (plus_constant (Pmode
, g1
, -size
));
5114 /* The run-time loop is made up of 10 insns in the generic case while the
5115 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
5116 else if (size
<= 5 * PROBE_INTERVAL
)
5120 emit_move_insn (g1
, GEN_INT (first
+ PROBE_INTERVAL
));
5121 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5122 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5123 emit_stack_probe (g1
);
5125 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
5126 it exceeds SIZE. If only two probes are needed, this will not
5127 generate any code. Then probe at FIRST + SIZE. */
5128 for (i
= 2 * PROBE_INTERVAL
; i
< size
; i
+= PROBE_INTERVAL
)
5130 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5131 plus_constant (Pmode
, g1
, -PROBE_INTERVAL
)));
5132 emit_stack_probe (g1
);
5135 emit_stack_probe (plus_constant (Pmode
, g1
,
5136 (i
- PROBE_INTERVAL
) - size
));
5139 /* Otherwise, do the same as above, but in a loop. Note that we must be
5140 extra careful with variables wrapping around because we might be at
5141 the very top (or the very bottom) of the address space and we have
5142 to be able to handle this case properly; in particular, we use an
5143 equality test for the loop condition. */
5146 HOST_WIDE_INT rounded_size
;
5147 rtx g4
= gen_rtx_REG (Pmode
, 4);
5149 emit_move_insn (g1
, GEN_INT (first
));
5152 /* Step 1: round SIZE to the previous multiple of the interval. */
5154 rounded_size
= size
& -PROBE_INTERVAL
;
5155 emit_move_insn (g4
, GEN_INT (rounded_size
));
5158 /* Step 2: compute initial and final value of the loop counter. */
5160 /* TEST_ADDR = SP + FIRST. */
5161 emit_insn (gen_rtx_SET (VOIDmode
, g1
,
5162 gen_rtx_MINUS (Pmode
, stack_pointer_rtx
, g1
)));
5164 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
5165 emit_insn (gen_rtx_SET (VOIDmode
, g4
, gen_rtx_MINUS (Pmode
, g1
, g4
)));
5170 while (TEST_ADDR != LAST_ADDR)
5172 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
5176 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
5177 until it is equal to ROUNDED_SIZE. */
5180 emit_insn (gen_probe_stack_rangedi (g1
, g1
, g4
));
5182 emit_insn (gen_probe_stack_rangesi (g1
, g1
, g4
));
5185 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
5186 that SIZE is equal to ROUNDED_SIZE. */
5188 if (size
!= rounded_size
)
5189 emit_stack_probe (plus_constant (Pmode
, g4
, rounded_size
- size
));
5192 /* Make sure nothing is scheduled before we are done. */
5193 emit_insn (gen_blockage ());
5196 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
5197 absolute addresses. */
5200 output_probe_stack_range (rtx reg1
, rtx reg2
)
5202 static int labelno
= 0;
5203 char loop_lab
[32], end_lab
[32];
5206 ASM_GENERATE_INTERNAL_LABEL (loop_lab
, "LPSRL", labelno
);
5207 ASM_GENERATE_INTERNAL_LABEL (end_lab
, "LPSRE", labelno
++);
5209 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, loop_lab
);
5211 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
5214 output_asm_insn ("cmp\t%0, %1", xops
);
5216 fputs ("\tbe,pn\t%xcc,", asm_out_file
);
5218 fputs ("\tbe\t", asm_out_file
);
5219 assemble_name_raw (asm_out_file
, end_lab
);
5220 fputc ('\n', asm_out_file
);
5222 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
5223 xops
[1] = GEN_INT (-PROBE_INTERVAL
);
5224 output_asm_insn (" add\t%0, %1, %0", xops
);
5226 /* Probe at TEST_ADDR and branch. */
5228 fputs ("\tba,pt\t%xcc,", asm_out_file
);
5230 fputs ("\tba\t", asm_out_file
);
5231 assemble_name_raw (asm_out_file
, loop_lab
);
5232 fputc ('\n', asm_out_file
);
5233 xops
[1] = GEN_INT (SPARC_STACK_BIAS
);
5234 output_asm_insn (" st\t%%g0, [%0+%1]", xops
);
5236 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, end_lab
);
5241 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as
5242 needed. LOW is supposed to be double-word aligned for 32-bit registers.
5243 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE
5244 is the action to be performed if SAVE_P returns true and ACTION_FALSE
5245 the action to be performed if it returns false. Return the new offset. */
5247 typedef bool (*sorr_pred_t
) (unsigned int, int);
5248 typedef enum { SORR_NONE
, SORR_ADVANCE
, SORR_SAVE
, SORR_RESTORE
} sorr_act_t
;
5251 emit_save_or_restore_regs (unsigned int low
, unsigned int high
, rtx base
,
5252 int offset
, int leaf_function
, sorr_pred_t save_p
,
5253 sorr_act_t action_true
, sorr_act_t action_false
)
5259 if (TARGET_ARCH64
&& high
<= 32)
5263 for (i
= low
; i
< high
; i
++)
5265 if (save_p (i
, leaf_function
))
5267 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
,
5269 if (action_true
== SORR_SAVE
)
5271 insn
= emit_move_insn (mem
, gen_rtx_REG (DImode
, i
));
5272 RTX_FRAME_RELATED_P (insn
) = 1;
5274 else /* action_true == SORR_RESTORE */
5276 /* The frame pointer must be restored last since its old
5277 value may be used as base address for the frame. This
5278 is problematic in 64-bit mode only because of the lack
5279 of double-word load instruction. */
5280 if (i
== HARD_FRAME_POINTER_REGNUM
)
5283 emit_move_insn (gen_rtx_REG (DImode
, i
), mem
);
5287 else if (action_false
== SORR_ADVANCE
)
5293 mem
= gen_frame_mem (DImode
, plus_constant (Pmode
, base
, fp_offset
));
5294 emit_move_insn (hard_frame_pointer_rtx
, mem
);
5299 for (i
= low
; i
< high
; i
+= 2)
5301 bool reg0
= save_p (i
, leaf_function
);
5302 bool reg1
= save_p (i
+ 1, leaf_function
);
5303 enum machine_mode mode
;
5308 mode
= SPARC_INT_REG_P (i
) ? DImode
: DFmode
;
5313 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5318 mode
= SPARC_INT_REG_P (i
) ? SImode
: SFmode
;
5324 if (action_false
== SORR_ADVANCE
)
5329 mem
= gen_frame_mem (mode
, plus_constant (Pmode
, base
, offset
));
5330 if (action_true
== SORR_SAVE
)
5332 insn
= emit_move_insn (mem
, gen_rtx_REG (mode
, regno
));
5333 RTX_FRAME_RELATED_P (insn
) = 1;
5337 mem
= gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5339 set1
= gen_rtx_SET (VOIDmode
, mem
,
5340 gen_rtx_REG (SImode
, regno
));
5341 RTX_FRAME_RELATED_P (set1
) = 1;
5343 = gen_frame_mem (SImode
, plus_constant (Pmode
, base
,
5345 set2
= gen_rtx_SET (VOIDmode
, mem
,
5346 gen_rtx_REG (SImode
, regno
+ 1));
5347 RTX_FRAME_RELATED_P (set2
) = 1;
5348 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5349 gen_rtx_PARALLEL (VOIDmode
,
5350 gen_rtvec (2, set1
, set2
)));
5353 else /* action_true == SORR_RESTORE */
5354 emit_move_insn (gen_rtx_REG (mode
, regno
), mem
);
5356 /* Always preserve double-word alignment. */
5357 offset
= (offset
+ 8) & -8;
5364 /* Emit code to adjust BASE to OFFSET. Return the new base. */
5367 emit_adjust_base_to_offset (rtx base
, int offset
)
5369 /* ??? This might be optimized a little as %g1 might already have a
5370 value close enough that a single add insn will do. */
5371 /* ??? Although, all of this is probably only a temporary fix because
5372 if %g1 can hold a function result, then sparc_expand_epilogue will
5373 lose (the result will be clobbered). */
5374 rtx new_base
= gen_rtx_REG (Pmode
, 1);
5375 emit_move_insn (new_base
, GEN_INT (offset
));
5376 emit_insn (gen_rtx_SET (VOIDmode
,
5377 new_base
, gen_rtx_PLUS (Pmode
, base
, new_base
)));
5381 /* Emit code to save/restore call-saved global and FP registers. */
5384 emit_save_or_restore_global_fp_regs (rtx base
, int offset
, sorr_act_t action
)
5386 if (offset
< -4096 || offset
+ sparc_n_global_fp_regs
* 4 > 4095)
5388 base
= emit_adjust_base_to_offset (base
, offset
);
5393 = emit_save_or_restore_regs (0, 8, base
, offset
, 0,
5394 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5395 emit_save_or_restore_regs (32, TARGET_V9
? 96 : 64, base
, offset
, 0,
5396 save_global_or_fp_reg_p
, action
, SORR_NONE
);
5399 /* Emit code to save/restore call-saved local and in registers. */
5402 emit_save_or_restore_local_in_regs (rtx base
, int offset
, sorr_act_t action
)
5404 if (offset
< -4096 || offset
+ 16 * UNITS_PER_WORD
> 4095)
5406 base
= emit_adjust_base_to_offset (base
, offset
);
5410 emit_save_or_restore_regs (16, 32, base
, offset
, sparc_leaf_function_p
,
5411 save_local_or_in_reg_p
, action
, SORR_ADVANCE
);
5414 /* Emit a window_save insn. */
5417 emit_window_save (rtx increment
)
5419 rtx_insn
*insn
= emit_insn (gen_window_save (increment
));
5420 RTX_FRAME_RELATED_P (insn
) = 1;
5422 /* The incoming return address (%o7) is saved in %i7. */
5423 add_reg_note (insn
, REG_CFA_REGISTER
,
5424 gen_rtx_SET (VOIDmode
,
5425 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
),
5427 INCOMING_RETURN_ADDR_REGNUM
)));
5429 /* The window save event. */
5430 add_reg_note (insn
, REG_CFA_WINDOW_SAVE
, const0_rtx
);
5432 /* The CFA is %fp, the hard frame pointer. */
5433 add_reg_note (insn
, REG_CFA_DEF_CFA
,
5434 plus_constant (Pmode
, hard_frame_pointer_rtx
,
5435 INCOMING_FRAME_SP_OFFSET
));
5440 /* Generate an increment for the stack pointer. */
5443 gen_stack_pointer_inc (rtx increment
)
5445 return gen_rtx_SET (VOIDmode
,
5447 gen_rtx_PLUS (Pmode
,
5452 /* Expand the function prologue. The prologue is responsible for reserving
5453 storage for the frame, saving the call-saved registers and loading the
5454 GOT register if needed. */
5457 sparc_expand_prologue (void)
5462 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying
5463 on the final value of the flag means deferring the prologue/epilogue
5464 expansion until just before the second scheduling pass, which is too
5465 late to emit multiple epilogues or return insns.
5467 Of course we are making the assumption that the value of the flag
5468 will not change between now and its final value. Of the three parts
5469 of the formula, only the last one can reasonably vary. Let's take a
5470 closer look, after assuming that the first two ones are set to true
5471 (otherwise the last value is effectively silenced).
5473 If only_leaf_regs_used returns false, the global predicate will also
5474 be false so the actual frame size calculated below will be positive.
5475 As a consequence, the save_register_window insn will be emitted in
5476 the instruction stream; now this insn explicitly references %fp
5477 which is not a leaf register so only_leaf_regs_used will always
5478 return false subsequently.
5480 If only_leaf_regs_used returns true, we hope that the subsequent
5481 optimization passes won't cause non-leaf registers to pop up. For
5482 example, the regrename pass has special provisions to not rename to
5483 non-leaf registers in a leaf function. */
5484 sparc_leaf_function_p
5485 = optimize
> 0 && crtl
->is_leaf
&& only_leaf_regs_used ();
5487 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5489 if (flag_stack_usage_info
)
5490 current_function_static_stack_size
= size
;
5492 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5494 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5496 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5497 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5498 size
- STACK_CHECK_PROTECT
);
5501 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5506 else if (sparc_leaf_function_p
)
5508 rtx size_int_rtx
= GEN_INT (-size
);
5511 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5512 else if (size
<= 8192)
5514 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5515 RTX_FRAME_RELATED_P (insn
) = 1;
5517 /* %sp is still the CFA register. */
5518 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5522 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5523 emit_move_insn (size_rtx
, size_int_rtx
);
5524 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5525 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
5526 gen_stack_pointer_inc (size_int_rtx
));
5529 RTX_FRAME_RELATED_P (insn
) = 1;
5533 rtx size_int_rtx
= GEN_INT (-size
);
5536 emit_window_save (size_int_rtx
);
5537 else if (size
<= 8192)
5539 emit_window_save (GEN_INT (-4096));
5541 /* %sp is not the CFA register anymore. */
5542 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5544 /* Make sure no %fp-based store is issued until after the frame is
5545 established. The offset between the frame pointer and the stack
5546 pointer is calculated relative to the value of the stack pointer
5547 at the end of the function prologue, and moving instructions that
5548 access the stack via the frame pointer between the instructions
5549 that decrement the stack pointer could result in accessing the
5550 register window save area, which is volatile. */
5551 emit_insn (gen_frame_blockage ());
5555 rtx size_rtx
= gen_rtx_REG (Pmode
, 1);
5556 emit_move_insn (size_rtx
, size_int_rtx
);
5557 emit_window_save (size_rtx
);
5561 if (sparc_leaf_function_p
)
5563 sparc_frame_base_reg
= stack_pointer_rtx
;
5564 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5568 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5569 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5572 if (sparc_n_global_fp_regs
> 0)
5573 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5574 sparc_frame_base_offset
5575 - sparc_apparent_frame_size
,
5578 /* Load the GOT register if needed. */
5579 if (crtl
->uses_pic_offset_table
)
5580 load_got_register ();
5582 /* Advertise that the data calculated just above are now valid. */
5583 sparc_prologue_data_valid_p
= true;
5586 /* Expand the function prologue. The prologue is responsible for reserving
5587 storage for the frame, saving the call-saved registers and loading the
5588 GOT register if needed. */
5591 sparc_flat_expand_prologue (void)
5596 sparc_leaf_function_p
= optimize
> 0 && crtl
->is_leaf
;
5598 size
= sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p
);
5600 if (flag_stack_usage_info
)
5601 current_function_static_stack_size
= size
;
5603 if (flag_stack_check
== STATIC_BUILTIN_STACK_CHECK
)
5605 if (crtl
->is_leaf
&& !cfun
->calls_alloca
)
5607 if (size
> PROBE_INTERVAL
&& size
> STACK_CHECK_PROTECT
)
5608 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
,
5609 size
- STACK_CHECK_PROTECT
);
5612 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT
, size
);
5615 if (sparc_save_local_in_regs_p
)
5616 emit_save_or_restore_local_in_regs (stack_pointer_rtx
, SPARC_STACK_BIAS
,
5623 rtx size_int_rtx
, size_rtx
;
5625 size_rtx
= size_int_rtx
= GEN_INT (-size
);
5627 /* We establish the frame (i.e. decrement the stack pointer) first, even
5628 if we use a frame pointer, because we cannot clobber any call-saved
5629 registers, including the frame pointer, if we haven't created a new
5630 register save area, for the sake of compatibility with the ABI. */
5632 insn
= emit_insn (gen_stack_pointer_inc (size_int_rtx
));
5633 else if (size
<= 8192 && !frame_pointer_needed
)
5635 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (-4096)));
5636 RTX_FRAME_RELATED_P (insn
) = 1;
5637 insn
= emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size
)));
5641 size_rtx
= gen_rtx_REG (Pmode
, 1);
5642 emit_move_insn (size_rtx
, size_int_rtx
);
5643 insn
= emit_insn (gen_stack_pointer_inc (size_rtx
));
5644 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5645 gen_stack_pointer_inc (size_int_rtx
));
5647 RTX_FRAME_RELATED_P (insn
) = 1;
5649 /* Ensure nothing is scheduled until after the frame is established. */
5650 emit_insn (gen_blockage ());
5652 if (frame_pointer_needed
)
5654 insn
= emit_insn (gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5655 gen_rtx_MINUS (Pmode
,
5658 RTX_FRAME_RELATED_P (insn
) = 1;
5660 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
5661 gen_rtx_SET (VOIDmode
, hard_frame_pointer_rtx
,
5662 plus_constant (Pmode
, stack_pointer_rtx
,
5666 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5668 rtx o7
= gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
);
5669 rtx i7
= gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
);
5671 insn
= emit_move_insn (i7
, o7
);
5672 RTX_FRAME_RELATED_P (insn
) = 1;
5674 add_reg_note (insn
, REG_CFA_REGISTER
,
5675 gen_rtx_SET (VOIDmode
, i7
, o7
));
5677 /* Prevent this instruction from ever being considered dead,
5678 even if this function has no epilogue. */
5683 if (frame_pointer_needed
)
5685 sparc_frame_base_reg
= hard_frame_pointer_rtx
;
5686 sparc_frame_base_offset
= SPARC_STACK_BIAS
;
5690 sparc_frame_base_reg
= stack_pointer_rtx
;
5691 sparc_frame_base_offset
= size
+ SPARC_STACK_BIAS
;
5694 if (sparc_n_global_fp_regs
> 0)
5695 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5696 sparc_frame_base_offset
5697 - sparc_apparent_frame_size
,
5700 /* Load the GOT register if needed. */
5701 if (crtl
->uses_pic_offset_table
)
5702 load_got_register ();
5704 /* Advertise that the data calculated just above are now valid. */
5705 sparc_prologue_data_valid_p
= true;
5708 /* This function generates the assembly code for function entry, which boils
5709 down to emitting the necessary .register directives. */
5712 sparc_asm_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5714 /* Check that the assumption we made in sparc_expand_prologue is valid. */
5716 gcc_assert (sparc_leaf_function_p
== crtl
->uses_only_leaf_regs
);
5718 sparc_output_scratch_registers (file
);
5721 /* Expand the function epilogue, either normal or part of a sibcall.
5722 We emit all the instructions except the return or the call. */
5725 sparc_expand_epilogue (bool for_eh
)
5727 HOST_WIDE_INT size
= sparc_frame_size
;
5729 if (sparc_n_global_fp_regs
> 0)
5730 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5731 sparc_frame_base_offset
5732 - sparc_apparent_frame_size
,
5735 if (size
== 0 || for_eh
)
5737 else if (sparc_leaf_function_p
)
5740 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5741 else if (size
<= 8192)
5743 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5744 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5748 rtx reg
= gen_rtx_REG (Pmode
, 1);
5749 emit_move_insn (reg
, GEN_INT (size
));
5750 emit_insn (gen_stack_pointer_inc (reg
));
5755 /* Expand the function epilogue, either normal or part of a sibcall.
5756 We emit all the instructions except the return or the call. */
5759 sparc_flat_expand_epilogue (bool for_eh
)
5761 HOST_WIDE_INT size
= sparc_frame_size
;
5763 if (sparc_n_global_fp_regs
> 0)
5764 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg
,
5765 sparc_frame_base_offset
5766 - sparc_apparent_frame_size
,
5769 /* If we have a frame pointer, we'll need both to restore it before the
5770 frame is destroyed and use its current value in destroying the frame.
5771 Since we don't have an atomic way to do that in the flat window model,
5772 we save the current value into a temporary register (%g1). */
5773 if (frame_pointer_needed
&& !for_eh
)
5774 emit_move_insn (gen_rtx_REG (Pmode
, 1), hard_frame_pointer_rtx
);
5776 if (return_addr_reg_needed_p (sparc_leaf_function_p
))
5777 emit_move_insn (gen_rtx_REG (Pmode
, INCOMING_RETURN_ADDR_REGNUM
),
5778 gen_rtx_REG (Pmode
, RETURN_ADDR_REGNUM
));
5780 if (sparc_save_local_in_regs_p
)
5781 emit_save_or_restore_local_in_regs (sparc_frame_base_reg
,
5782 sparc_frame_base_offset
,
5785 if (size
== 0 || for_eh
)
5787 else if (frame_pointer_needed
)
5789 /* Make sure the frame is destroyed after everything else is done. */
5790 emit_insn (gen_blockage ());
5792 emit_move_insn (stack_pointer_rtx
, gen_rtx_REG (Pmode
, 1));
5797 emit_insn (gen_blockage ());
5800 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
5801 else if (size
<= 8192)
5803 emit_insn (gen_stack_pointer_inc (GEN_INT (4096)));
5804 emit_insn (gen_stack_pointer_inc (GEN_INT (size
- 4096)));
5808 rtx reg
= gen_rtx_REG (Pmode
, 1);
5809 emit_move_insn (reg
, GEN_INT (size
));
5810 emit_insn (gen_stack_pointer_inc (reg
));
5815 /* Return true if it is appropriate to emit `return' instructions in the
5816 body of a function. */
5819 sparc_can_use_return_insn_p (void)
5821 return sparc_prologue_data_valid_p
5822 && sparc_n_global_fp_regs
== 0
5824 ? (sparc_frame_size
== 0 && !sparc_save_local_in_regs_p
)
5825 : (sparc_frame_size
== 0 || !sparc_leaf_function_p
);
5828 /* This function generates the assembly code for function exit. */
5831 sparc_asm_function_epilogue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
5833 /* If the last two instructions of a function are "call foo; dslot;"
5834 the return address might point to the first instruction in the next
5835 function and we have to output a dummy nop for the sake of sane
5836 backtraces in such cases. This is pointless for sibling calls since
5837 the return address is explicitly adjusted. */
5839 rtx insn
, last_real_insn
;
5841 insn
= get_last_insn ();
5843 last_real_insn
= prev_real_insn (insn
);
5845 && NONJUMP_INSN_P (last_real_insn
)
5846 && GET_CODE (PATTERN (last_real_insn
)) == SEQUENCE
)
5847 last_real_insn
= XVECEXP (PATTERN (last_real_insn
), 0, 0);
5850 && CALL_P (last_real_insn
)
5851 && !SIBLING_CALL_P (last_real_insn
))
5852 fputs("\tnop\n", file
);
5854 sparc_output_deferred_case_vectors ();
5857 /* Output a 'restore' instruction. */
5860 output_restore (rtx pat
)
5866 fputs ("\t restore\n", asm_out_file
);
5870 gcc_assert (GET_CODE (pat
) == SET
);
5872 operands
[0] = SET_DEST (pat
);
5873 pat
= SET_SRC (pat
);
5875 switch (GET_CODE (pat
))
5878 operands
[1] = XEXP (pat
, 0);
5879 operands
[2] = XEXP (pat
, 1);
5880 output_asm_insn (" restore %r1, %2, %Y0", operands
);
5883 operands
[1] = XEXP (pat
, 0);
5884 operands
[2] = XEXP (pat
, 1);
5885 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
5888 operands
[1] = XEXP (pat
, 0);
5889 gcc_assert (XEXP (pat
, 1) == const1_rtx
);
5890 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
5894 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
5899 /* Output a return. */
5902 output_return (rtx_insn
*insn
)
5904 if (crtl
->calls_eh_return
)
5906 /* If the function uses __builtin_eh_return, the eh_return
5907 machinery occupies the delay slot. */
5908 gcc_assert (!final_sequence
);
5910 if (flag_delayed_branch
)
5912 if (!TARGET_FLAT
&& TARGET_V9
)
5913 fputs ("\treturn\t%i7+8\n", asm_out_file
);
5917 fputs ("\trestore\n", asm_out_file
);
5919 fputs ("\tjmp\t%o7+8\n", asm_out_file
);
5922 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file
);
5927 fputs ("\trestore\n", asm_out_file
);
5929 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file
);
5930 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file
);
5933 else if (sparc_leaf_function_p
|| TARGET_FLAT
)
5935 /* This is a leaf or flat function so we don't have to bother restoring
5936 the register window, which frees us from dealing with the convoluted
5937 semantics of restore/return. We simply output the jump to the
5938 return address and the insn in the delay slot (if any). */
5940 return "jmp\t%%o7+%)%#";
5944 /* This is a regular function so we have to restore the register window.
5945 We may have a pending insn for the delay slot, which will be either
5946 combined with the 'restore' instruction or put in the delay slot of
5947 the 'return' instruction. */
5953 delay
= NEXT_INSN (insn
);
5956 pat
= PATTERN (delay
);
5958 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1))
5960 epilogue_renumber (&pat
, 0);
5961 return "return\t%%i7+%)%#";
5965 output_asm_insn ("jmp\t%%i7+%)", NULL
);
5966 output_restore (pat
);
5967 PATTERN (delay
) = gen_blockage ();
5968 INSN_CODE (delay
) = -1;
5973 /* The delay slot is empty. */
5975 return "return\t%%i7+%)\n\t nop";
5976 else if (flag_delayed_branch
)
5977 return "jmp\t%%i7+%)\n\t restore";
5979 return "restore\n\tjmp\t%%o7+%)\n\t nop";
5986 /* Output a sibling call. */
5989 output_sibcall (rtx_insn
*insn
, rtx call_operand
)
5993 gcc_assert (flag_delayed_branch
);
5995 operands
[0] = call_operand
;
5997 if (sparc_leaf_function_p
|| TARGET_FLAT
)
5999 /* This is a leaf or flat function so we don't have to bother restoring
6000 the register window. We simply output the jump to the function and
6001 the insn in the delay slot (if any). */
6003 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P
&& final_sequence
));
6006 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#",
6009 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
6010 it into branch if possible. */
6011 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7",
6016 /* This is a regular function so we have to restore the register window.
6017 We may have a pending insn for the delay slot, which will be combined
6018 with the 'restore' instruction. */
6020 output_asm_insn ("call\t%a0, 0", operands
);
6024 rtx_insn
*delay
= NEXT_INSN (insn
);
6027 output_restore (PATTERN (delay
));
6029 PATTERN (delay
) = gen_blockage ();
6030 INSN_CODE (delay
) = -1;
6033 output_restore (NULL_RTX
);
6039 /* Functions for handling argument passing.
6041 For 32-bit, the first 6 args are normally in registers and the rest are
6042 pushed. Any arg that starts within the first 6 words is at least
6043 partially passed in a register unless its data type forbids.
6045 For 64-bit, the argument registers are laid out as an array of 16 elements
6046 and arguments are added sequentially. The first 6 int args and up to the
6047 first 16 fp args (depending on size) are passed in regs.
6049 Slot Stack Integral Float Float in structure Double Long Double
6050 ---- ----- -------- ----- ------------------ ------ -----------
6051 15 [SP+248] %f31 %f30,%f31 %d30
6052 14 [SP+240] %f29 %f28,%f29 %d28 %q28
6053 13 [SP+232] %f27 %f26,%f27 %d26
6054 12 [SP+224] %f25 %f24,%f25 %d24 %q24
6055 11 [SP+216] %f23 %f22,%f23 %d22
6056 10 [SP+208] %f21 %f20,%f21 %d20 %q20
6057 9 [SP+200] %f19 %f18,%f19 %d18
6058 8 [SP+192] %f17 %f16,%f17 %d16 %q16
6059 7 [SP+184] %f15 %f14,%f15 %d14
6060 6 [SP+176] %f13 %f12,%f13 %d12 %q12
6061 5 [SP+168] %o5 %f11 %f10,%f11 %d10
6062 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
6063 3 [SP+152] %o3 %f7 %f6,%f7 %d6
6064 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
6065 1 [SP+136] %o1 %f3 %f2,%f3 %d2
6066 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
6068 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
6070 Integral arguments are always passed as 64-bit quantities appropriately
6073 Passing of floating point values is handled as follows.
6074 If a prototype is in scope:
6075 If the value is in a named argument (i.e. not a stdarg function or a
6076 value not part of the `...') then the value is passed in the appropriate
6078 If the value is part of the `...' and is passed in one of the first 6
6079 slots then the value is passed in the appropriate int reg.
6080 If the value is part of the `...' and is not passed in one of the first 6
6081 slots then the value is passed in memory.
6082 If a prototype is not in scope:
6083 If the value is one of the first 6 arguments the value is passed in the
6084 appropriate integer reg and the appropriate fp reg.
6085 If the value is not one of the first 6 arguments the value is passed in
6086 the appropriate fp reg and in memory.
6089 Summary of the calling conventions implemented by GCC on the SPARC:
6092 size argument return value
6094 small integer <4 int. reg. int. reg.
6095 word 4 int. reg. int. reg.
6096 double word 8 int. reg. int. reg.
6098 _Complex small integer <8 int. reg. int. reg.
6099 _Complex word 8 int. reg. int. reg.
6100 _Complex double word 16 memory int. reg.
6102 vector integer <=8 int. reg. FP reg.
6103 vector integer >8 memory memory
6105 float 4 int. reg. FP reg.
6106 double 8 int. reg. FP reg.
6107 long double 16 memory memory
6109 _Complex float 8 memory FP reg.
6110 _Complex double 16 memory FP reg.
6111 _Complex long double 32 memory FP reg.
6113 vector float any memory memory
6115 aggregate any memory memory
6120 size argument return value
6122 small integer <8 int. reg. int. reg.
6123 word 8 int. reg. int. reg.
6124 double word 16 int. reg. int. reg.
6126 _Complex small integer <16 int. reg. int. reg.
6127 _Complex word 16 int. reg. int. reg.
6128 _Complex double word 32 memory int. reg.
6130 vector integer <=16 FP reg. FP reg.
6131 vector integer 16<s<=32 memory FP reg.
6132 vector integer >32 memory memory
6134 float 4 FP reg. FP reg.
6135 double 8 FP reg. FP reg.
6136 long double 16 FP reg. FP reg.
6138 _Complex float 8 FP reg. FP reg.
6139 _Complex double 16 FP reg. FP reg.
6140 _Complex long double 32 memory FP reg.
6142 vector float <=16 FP reg. FP reg.
6143 vector float 16<s<=32 memory FP reg.
6144 vector float >32 memory memory
6146 aggregate <=16 reg. reg.
6147 aggregate 16<s<=32 memory reg.
6148 aggregate >32 memory memory
6152 Note #1: complex floating-point types follow the extended SPARC ABIs as
6153 implemented by the Sun compiler.
6155 Note #2: integral vector types follow the scalar floating-point types
6156 conventions to match what is implemented by the Sun VIS SDK.
6158 Note #3: floating-point vector types follow the aggregate types
6162 /* Maximum number of int regs for args. */
6163 #define SPARC_INT_ARG_MAX 6
6164 /* Maximum number of fp regs for args. */
6165 #define SPARC_FP_ARG_MAX 16
6167 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
6169 /* Handle the INIT_CUMULATIVE_ARGS macro.
6170 Initialize a variable CUM of type CUMULATIVE_ARGS
6171 for a call to a function whose data type is FNTYPE.
6172 For a library call, FNTYPE is 0. */
6175 init_cumulative_args (struct sparc_args
*cum
, tree fntype
,
6176 rtx libname ATTRIBUTE_UNUSED
,
6177 tree fndecl ATTRIBUTE_UNUSED
)
6180 cum
->prototype_p
= fntype
&& prototype_p (fntype
);
6181 cum
->libcall_p
= fntype
== 0;
6184 /* Handle promotion of pointer and integer arguments. */
6186 static enum machine_mode
6187 sparc_promote_function_mode (const_tree type
,
6188 enum machine_mode mode
,
6190 const_tree fntype ATTRIBUTE_UNUSED
,
6191 int for_return ATTRIBUTE_UNUSED
)
6193 if (type
!= NULL_TREE
&& POINTER_TYPE_P (type
))
6195 *punsignedp
= POINTERS_EXTEND_UNSIGNED
;
6199 /* Integral arguments are passed as full words, as per the ABI. */
6200 if (GET_MODE_CLASS (mode
) == MODE_INT
6201 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
6207 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */
6210 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED
)
6212 return TARGET_ARCH64
? true : false;
6215 /* Scan the record type TYPE and return the following predicates:
6216 - INTREGS_P: the record contains at least one field or sub-field
6217 that is eligible for promotion in integer registers.
6218 - FP_REGS_P: the record contains at least one field or sub-field
6219 that is eligible for promotion in floating-point registers.
6220 - PACKED_P: the record contains at least one field that is packed.
6222 Sub-fields are not taken into account for the PACKED_P predicate. */
6225 scan_record_type (const_tree type
, int *intregs_p
, int *fpregs_p
,
6230 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6232 if (TREE_CODE (field
) == FIELD_DECL
)
6234 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6235 scan_record_type (TREE_TYPE (field
), intregs_p
, fpregs_p
, 0);
6236 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6237 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6243 if (packed_p
&& DECL_PACKED (field
))
6249 /* Compute the slot number to pass an argument in.
6250 Return the slot number or -1 if passing on the stack.
6252 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6253 the preceding args and about the function being called.
6254 MODE is the argument's machine mode.
6255 TYPE is the data type of the argument (as a tree).
6256 This is null for libcalls where that information may
6258 NAMED is nonzero if this argument is a named parameter
6259 (otherwise it is an extra parameter matching an ellipsis).
6260 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
6261 *PREGNO records the register number to use if scalar type.
6262 *PPADDING records the amount of padding needed in words. */
6265 function_arg_slotno (const struct sparc_args
*cum
, enum machine_mode mode
,
6266 const_tree type
, bool named
, bool incoming_p
,
6267 int *pregno
, int *ppadding
)
6269 int regbase
= (incoming_p
6270 ? SPARC_INCOMING_INT_ARG_FIRST
6271 : SPARC_OUTGOING_INT_ARG_FIRST
);
6272 int slotno
= cum
->words
;
6273 enum mode_class mclass
;
6278 if (type
&& TREE_ADDRESSABLE (type
))
6284 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
6287 /* For SPARC64, objects requiring 16-byte alignment get it. */
6289 && (type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
)) >= 128
6290 && (slotno
& 1) != 0)
6291 slotno
++, *ppadding
= 1;
6293 mclass
= GET_MODE_CLASS (mode
);
6294 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6296 /* Vector types deserve special treatment because they are
6297 polymorphic wrt their mode, depending upon whether VIS
6298 instructions are enabled. */
6299 if (TREE_CODE (TREE_TYPE (type
)) == REAL_TYPE
)
6301 /* The SPARC port defines no floating-point vector modes. */
6302 gcc_assert (mode
== BLKmode
);
6306 /* Integral vector types should either have a vector
6307 mode or an integral mode, because we are guaranteed
6308 by pass_by_reference that their size is not greater
6309 than 16 bytes and TImode is 16-byte wide. */
6310 gcc_assert (mode
!= BLKmode
);
6312 /* Vector integers are handled like floats according to
6314 mclass
= MODE_FLOAT
;
6321 case MODE_COMPLEX_FLOAT
:
6322 case MODE_VECTOR_INT
:
6323 if (TARGET_ARCH64
&& TARGET_FPU
&& named
)
6325 if (slotno
>= SPARC_FP_ARG_MAX
)
6327 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
6328 /* Arguments filling only one single FP register are
6329 right-justified in the outer double FP register. */
6330 if (GET_MODE_SIZE (mode
) <= 4)
6337 case MODE_COMPLEX_INT
:
6338 if (slotno
>= SPARC_INT_ARG_MAX
)
6340 regno
= regbase
+ slotno
;
6344 if (mode
== VOIDmode
)
6345 /* MODE is VOIDmode when generating the actual call. */
6348 gcc_assert (mode
== BLKmode
);
6352 || (TREE_CODE (type
) != VECTOR_TYPE
6353 && TREE_CODE (type
) != RECORD_TYPE
))
6355 if (slotno
>= SPARC_INT_ARG_MAX
)
6357 regno
= regbase
+ slotno
;
6359 else /* TARGET_ARCH64 && type */
6361 int intregs_p
= 0, fpregs_p
= 0, packed_p
= 0;
6363 /* First see what kinds of registers we would need. */
6364 if (TREE_CODE (type
) == VECTOR_TYPE
)
6367 scan_record_type (type
, &intregs_p
, &fpregs_p
, &packed_p
);
6369 /* The ABI obviously doesn't specify how packed structures
6370 are passed. These are defined to be passed in int regs
6371 if possible, otherwise memory. */
6372 if (packed_p
|| !named
)
6373 fpregs_p
= 0, intregs_p
= 1;
6375 /* If all arg slots are filled, then must pass on stack. */
6376 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
6379 /* If there are only int args and all int arg slots are filled,
6380 then must pass on stack. */
6381 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
6384 /* Note that even if all int arg slots are filled, fp members may
6385 still be passed in regs if such regs are available.
6386 *PREGNO isn't set because there may be more than one, it's up
6387 to the caller to compute them. */
6400 /* Handle recursive register counting for structure field layout. */
6402 struct function_arg_record_value_parms
6404 rtx ret
; /* return expression being built. */
6405 int slotno
; /* slot number of the argument. */
6406 int named
; /* whether the argument is named. */
6407 int regbase
; /* regno of the base register. */
6408 int stack
; /* 1 if part of the argument is on the stack. */
6409 int intoffset
; /* offset of the first pending integer field. */
6410 unsigned int nregs
; /* number of words passed in registers. */
6413 static void function_arg_record_value_3
6414 (HOST_WIDE_INT
, struct function_arg_record_value_parms
*);
6415 static void function_arg_record_value_2
6416 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
6417 static void function_arg_record_value_1
6418 (const_tree
, HOST_WIDE_INT
, struct function_arg_record_value_parms
*, bool);
6419 static rtx
function_arg_record_value (const_tree
, enum machine_mode
, int, int, int);
6420 static rtx
function_arg_union_value (int, enum machine_mode
, int, int);
6422 /* A subroutine of function_arg_record_value. Traverse the structure
6423 recursively and determine how many registers will be required. */
6426 function_arg_record_value_1 (const_tree type
, HOST_WIDE_INT startbitpos
,
6427 struct function_arg_record_value_parms
*parms
,
6432 /* We need to compute how many registers are needed so we can
6433 allocate the PARALLEL but before we can do that we need to know
6434 whether there are any packed fields. The ABI obviously doesn't
6435 specify how structures are passed in this case, so they are
6436 defined to be passed in int regs if possible, otherwise memory,
6437 regardless of whether there are fp values present. */
6440 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
6442 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6449 /* Compute how many registers we need. */
6450 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6452 if (TREE_CODE (field
) == FIELD_DECL
)
6454 HOST_WIDE_INT bitpos
= startbitpos
;
6456 if (DECL_SIZE (field
) != 0)
6458 if (integer_zerop (DECL_SIZE (field
)))
6461 if (tree_fits_uhwi_p (bit_position (field
)))
6462 bitpos
+= int_bit_position (field
);
6465 /* ??? FIXME: else assume zero offset. */
6467 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6468 function_arg_record_value_1 (TREE_TYPE (field
),
6472 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6473 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6478 if (parms
->intoffset
!= -1)
6480 unsigned int startbit
, endbit
;
6481 int intslots
, this_slotno
;
6483 startbit
= parms
->intoffset
& -BITS_PER_WORD
;
6484 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6486 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6487 this_slotno
= parms
->slotno
+ parms
->intoffset
6490 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6492 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6493 /* We need to pass this field on the stack. */
6497 parms
->nregs
+= intslots
;
6498 parms
->intoffset
= -1;
6501 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
6502 If it wasn't true we wouldn't be here. */
6503 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6504 && DECL_MODE (field
) == BLKmode
)
6505 parms
->nregs
+= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6506 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6513 if (parms
->intoffset
== -1)
6514 parms
->intoffset
= bitpos
;
6520 /* A subroutine of function_arg_record_value. Assign the bits of the
6521 structure between parms->intoffset and bitpos to integer registers. */
6524 function_arg_record_value_3 (HOST_WIDE_INT bitpos
,
6525 struct function_arg_record_value_parms
*parms
)
6527 enum machine_mode mode
;
6529 unsigned int startbit
, endbit
;
6530 int this_slotno
, intslots
, intoffset
;
6533 if (parms
->intoffset
== -1)
6536 intoffset
= parms
->intoffset
;
6537 parms
->intoffset
= -1;
6539 startbit
= intoffset
& -BITS_PER_WORD
;
6540 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6541 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6542 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
6544 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
6548 /* If this is the trailing part of a word, only load that much into
6549 the register. Otherwise load the whole register. Note that in
6550 the latter case we may pick up unwanted bits. It's not a problem
6551 at the moment but may wish to revisit. */
6553 if (intoffset
% BITS_PER_WORD
!= 0)
6554 mode
= smallest_mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
6559 intoffset
/= BITS_PER_UNIT
;
6562 regno
= parms
->regbase
+ this_slotno
;
6563 reg
= gen_rtx_REG (mode
, regno
);
6564 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6565 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
6568 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
6573 while (intslots
> 0);
6576 /* A subroutine of function_arg_record_value. Traverse the structure
6577 recursively and assign bits to floating point registers. Track which
6578 bits in between need integer registers; invoke function_arg_record_value_3
6579 to make that happen. */
6582 function_arg_record_value_2 (const_tree type
, HOST_WIDE_INT startbitpos
,
6583 struct function_arg_record_value_parms
*parms
,
6589 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6591 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
6598 for (field
= TYPE_FIELDS (type
); field
; field
= DECL_CHAIN (field
))
6600 if (TREE_CODE (field
) == FIELD_DECL
)
6602 HOST_WIDE_INT bitpos
= startbitpos
;
6604 if (DECL_SIZE (field
) != 0)
6606 if (integer_zerop (DECL_SIZE (field
)))
6609 if (tree_fits_uhwi_p (bit_position (field
)))
6610 bitpos
+= int_bit_position (field
);
6613 /* ??? FIXME: else assume zero offset. */
6615 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
6616 function_arg_record_value_2 (TREE_TYPE (field
),
6620 else if ((FLOAT_TYPE_P (TREE_TYPE (field
))
6621 || TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
)
6626 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
6627 int regno
, nregs
, pos
;
6628 enum machine_mode mode
= DECL_MODE (field
);
6631 function_arg_record_value_3 (bitpos
, parms
);
6633 if (TREE_CODE (TREE_TYPE (field
)) == VECTOR_TYPE
6636 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6637 nregs
= TYPE_VECTOR_SUBPARTS (TREE_TYPE (field
));
6639 else if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
6641 mode
= TYPE_MODE (TREE_TYPE (TREE_TYPE (field
)));
6647 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2;
6648 if (GET_MODE_SIZE (mode
) <= 4 && (bitpos
& 32) != 0)
6650 reg
= gen_rtx_REG (mode
, regno
);
6651 pos
= bitpos
/ BITS_PER_UNIT
;
6652 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6653 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6657 regno
+= GET_MODE_SIZE (mode
) / 4;
6658 reg
= gen_rtx_REG (mode
, regno
);
6659 pos
+= GET_MODE_SIZE (mode
);
6660 XVECEXP (parms
->ret
, 0, parms
->stack
+ parms
->nregs
)
6661 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (pos
));
6667 if (parms
->intoffset
== -1)
6668 parms
->intoffset
= bitpos
;
6674 /* Used by function_arg and sparc_function_value_1 to implement the complex
6675 conventions of the 64-bit ABI for passing and returning structures.
6676 Return an expression valid as a return value for the FUNCTION_ARG
6677 and TARGET_FUNCTION_VALUE.
6679 TYPE is the data type of the argument (as a tree).
6680 This is null for libcalls where that information may
6682 MODE is the argument's machine mode.
6683 SLOTNO is the index number of the argument's slot in the parameter array.
6684 NAMED is nonzero if this argument is a named parameter
6685 (otherwise it is an extra parameter matching an ellipsis).
6686 REGBASE is the regno of the base register for the parameter array. */
6689 function_arg_record_value (const_tree type
, enum machine_mode mode
,
6690 int slotno
, int named
, int regbase
)
6692 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
6693 struct function_arg_record_value_parms parms
;
6696 parms
.ret
= NULL_RTX
;
6697 parms
.slotno
= slotno
;
6698 parms
.named
= named
;
6699 parms
.regbase
= regbase
;
6702 /* Compute how many registers we need. */
6704 parms
.intoffset
= 0;
6705 function_arg_record_value_1 (type
, 0, &parms
, false);
6707 /* Take into account pending integer fields. */
6708 if (parms
.intoffset
!= -1)
6710 unsigned int startbit
, endbit
;
6711 int intslots
, this_slotno
;
6713 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
6714 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
6715 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
6716 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
6718 if (intslots
> 0 && intslots
> SPARC_INT_ARG_MAX
- this_slotno
)
6720 intslots
= MAX (0, SPARC_INT_ARG_MAX
- this_slotno
);
6721 /* We need to pass this field on the stack. */
6725 parms
.nregs
+= intslots
;
6727 nregs
= parms
.nregs
;
6729 /* Allocate the vector and handle some annoying special cases. */
6732 /* ??? Empty structure has no value? Duh? */
6735 /* Though there's nothing really to store, return a word register
6736 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
6737 leads to breakage due to the fact that there are zero bytes to
6739 return gen_rtx_REG (mode
, regbase
);
6743 /* ??? C++ has structures with no fields, and yet a size. Give up
6744 for now and pass everything back in integer registers. */
6745 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6747 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
6748 nregs
= SPARC_INT_ARG_MAX
- slotno
;
6750 gcc_assert (nregs
!= 0);
6752 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (parms
.stack
+ nregs
));
6754 /* If at least one field must be passed on the stack, generate
6755 (parallel [(expr_list (nil) ...) ...]) so that all fields will
6756 also be passed on the stack. We can't do much better because the
6757 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case
6758 of structures for which the fields passed exclusively in registers
6759 are not at the beginning of the structure. */
6761 XVECEXP (parms
.ret
, 0, 0)
6762 = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6764 /* Fill in the entries. */
6766 parms
.intoffset
= 0;
6767 function_arg_record_value_2 (type
, 0, &parms
, false);
6768 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
6770 gcc_assert (parms
.nregs
== nregs
);
6775 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6776 of the 64-bit ABI for passing and returning unions.
6777 Return an expression valid as a return value for the FUNCTION_ARG
6778 and TARGET_FUNCTION_VALUE.
6780 SIZE is the size in bytes of the union.
6781 MODE is the argument's machine mode.
6782 REGNO is the hard register the union will be passed in. */
6785 function_arg_union_value (int size
, enum machine_mode mode
, int slotno
,
6788 int nwords
= ROUND_ADVANCE (size
), i
;
6791 /* See comment in previous function for empty structures. */
6793 return gen_rtx_REG (mode
, regno
);
6795 if (slotno
== SPARC_INT_ARG_MAX
- 1)
6798 regs
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nwords
));
6800 for (i
= 0; i
< nwords
; i
++)
6802 /* Unions are passed left-justified. */
6803 XVECEXP (regs
, 0, i
)
6804 = gen_rtx_EXPR_LIST (VOIDmode
,
6805 gen_rtx_REG (word_mode
, regno
),
6806 GEN_INT (UNITS_PER_WORD
* i
));
6813 /* Used by function_arg and sparc_function_value_1 to implement the conventions
6814 for passing and returning large (BLKmode) vectors.
6815 Return an expression valid as a return value for the FUNCTION_ARG
6816 and TARGET_FUNCTION_VALUE.
6818 SIZE is the size in bytes of the vector (at least 8 bytes).
6819 REGNO is the FP hard register the vector will be passed in. */
6822 function_arg_vector_value (int size
, int regno
)
6824 int i
, nregs
= size
/ 8;
6827 regs
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
));
6829 for (i
= 0; i
< nregs
; i
++)
6831 XVECEXP (regs
, 0, i
)
6832 = gen_rtx_EXPR_LIST (VOIDmode
,
6833 gen_rtx_REG (DImode
, regno
+ 2*i
),
6840 /* Determine where to put an argument to a function.
6841 Value is zero to push the argument on the stack,
6842 or a hard register in which to store the argument.
6844 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6845 the preceding args and about the function being called.
6846 MODE is the argument's machine mode.
6847 TYPE is the data type of the argument (as a tree).
6848 This is null for libcalls where that information may
6850 NAMED is true if this argument is a named parameter
6851 (otherwise it is an extra parameter matching an ellipsis).
6852 INCOMING_P is false for TARGET_FUNCTION_ARG, true for
6853 TARGET_FUNCTION_INCOMING_ARG. */
6856 sparc_function_arg_1 (cumulative_args_t cum_v
, enum machine_mode mode
,
6857 const_tree type
, bool named
, bool incoming_p
)
6859 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
6861 int regbase
= (incoming_p
6862 ? SPARC_INCOMING_INT_ARG_FIRST
6863 : SPARC_OUTGOING_INT_ARG_FIRST
);
6864 int slotno
, regno
, padding
;
6865 enum mode_class mclass
= GET_MODE_CLASS (mode
);
6867 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
6872 /* Vector types deserve special treatment because they are polymorphic wrt
6873 their mode, depending upon whether VIS instructions are enabled. */
6874 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
6876 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6877 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
6878 || (TARGET_ARCH64
&& size
<= 16));
6880 if (mode
== BLKmode
)
6881 return function_arg_vector_value (size
,
6882 SPARC_FP_ARG_FIRST
+ 2*slotno
);
6884 mclass
= MODE_FLOAT
;
6888 return gen_rtx_REG (mode
, regno
);
6890 /* Structures up to 16 bytes in size are passed in arg slots on the stack
6891 and are promoted to registers if possible. */
6892 if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
6894 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6895 gcc_assert (size
<= 16);
6897 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
6900 /* Unions up to 16 bytes in size are passed in integer registers. */
6901 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
6903 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6904 gcc_assert (size
<= 16);
6906 return function_arg_union_value (size
, mode
, slotno
, regno
);
6909 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
6910 but also have the slot allocated for them.
6911 If no prototype is in scope fp values in register slots get passed
6912 in two places, either fp regs and int regs or fp regs and memory. */
6913 else if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
6914 && SPARC_FP_REG_P (regno
))
6916 rtx reg
= gen_rtx_REG (mode
, regno
);
6917 if (cum
->prototype_p
|| cum
->libcall_p
)
6919 /* "* 2" because fp reg numbers are recorded in 4 byte
6922 /* ??? This will cause the value to be passed in the fp reg and
6923 in the stack. When a prototype exists we want to pass the
6924 value in the reg but reserve space on the stack. That's an
6925 optimization, and is deferred [for a bit]. */
6926 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
6927 return gen_rtx_PARALLEL (mode
,
6929 gen_rtx_EXPR_LIST (VOIDmode
,
6930 NULL_RTX
, const0_rtx
),
6931 gen_rtx_EXPR_LIST (VOIDmode
,
6935 /* ??? It seems that passing back a register even when past
6936 the area declared by REG_PARM_STACK_SPACE will allocate
6937 space appropriately, and will not copy the data onto the
6938 stack, exactly as we desire.
6940 This is due to locate_and_pad_parm being called in
6941 expand_call whenever reg_parm_stack_space > 0, which
6942 while beneficial to our example here, would seem to be
6943 in error from what had been intended. Ho hum... -- r~ */
6951 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
6955 /* On incoming, we don't need to know that the value
6956 is passed in %f0 and %i0, and it confuses other parts
6957 causing needless spillage even on the simplest cases. */
6961 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
6962 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
6964 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6965 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
6967 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6971 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
6972 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
6973 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
6978 /* All other aggregate types are passed in an integer register in a mode
6979 corresponding to the size of the type. */
6980 else if (type
&& AGGREGATE_TYPE_P (type
))
6982 HOST_WIDE_INT size
= int_size_in_bytes (type
);
6983 gcc_assert (size
<= 16);
6985 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
6988 return gen_rtx_REG (mode
, regno
);
6991 /* Handle the TARGET_FUNCTION_ARG target hook. */
6994 sparc_function_arg (cumulative_args_t cum
, enum machine_mode mode
,
6995 const_tree type
, bool named
)
6997 return sparc_function_arg_1 (cum
, mode
, type
, named
, false);
7000 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */
7003 sparc_function_incoming_arg (cumulative_args_t cum
, enum machine_mode mode
,
7004 const_tree type
, bool named
)
7006 return sparc_function_arg_1 (cum
, mode
, type
, named
, true);
7009 /* For sparc64, objects requiring 16 byte alignment are passed that way. */
7012 sparc_function_arg_boundary (enum machine_mode mode
, const_tree type
)
7014 return ((TARGET_ARCH64
7015 && (GET_MODE_ALIGNMENT (mode
) == 128
7016 || (type
&& TYPE_ALIGN (type
) == 128)))
7021 /* For an arg passed partly in registers and partly in memory,
7022 this is the number of bytes of registers used.
7023 For args passed entirely in registers or entirely in memory, zero.
7025 Any arg that starts in the first 6 regs but won't entirely fit in them
7026 needs partial registers on v8. On v9, structures with integer
7027 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
7028 values that begin in the last fp reg [where "last fp reg" varies with the
7029 mode] will be split between that reg and memory. */
7032 sparc_arg_partial_bytes (cumulative_args_t cum
, enum machine_mode mode
,
7033 tree type
, bool named
)
7035 int slotno
, regno
, padding
;
7037 /* We pass false for incoming_p here, it doesn't matter. */
7038 slotno
= function_arg_slotno (get_cumulative_args (cum
), mode
, type
, named
,
7039 false, ®no
, &padding
);
7046 if ((slotno
+ (mode
== BLKmode
7047 ? ROUND_ADVANCE (int_size_in_bytes (type
))
7048 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
7049 > SPARC_INT_ARG_MAX
)
7050 return (SPARC_INT_ARG_MAX
- slotno
) * UNITS_PER_WORD
;
7054 /* We are guaranteed by pass_by_reference that the size of the
7055 argument is not greater than 16 bytes, so we only need to return
7056 one word if the argument is partially passed in registers. */
7058 if (type
&& AGGREGATE_TYPE_P (type
))
7060 int size
= int_size_in_bytes (type
);
7062 if (size
> UNITS_PER_WORD
7063 && slotno
== SPARC_INT_ARG_MAX
- 1)
7064 return UNITS_PER_WORD
;
7066 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
7067 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
7068 && ! (TARGET_FPU
&& named
)))
7070 /* The complex types are passed as packed types. */
7071 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
7072 && slotno
== SPARC_INT_ARG_MAX
- 1)
7073 return UNITS_PER_WORD
;
7075 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
7077 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
7079 return UNITS_PER_WORD
;
7086 /* Handle the TARGET_PASS_BY_REFERENCE target hook.
7087 Specify whether to pass the argument by reference. */
7090 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
7091 enum machine_mode mode
, const_tree type
,
7092 bool named ATTRIBUTE_UNUSED
)
7095 /* Original SPARC 32-bit ABI says that structures and unions,
7096 and quad-precision floats are passed by reference. For Pascal,
7097 also pass arrays by reference. All other base types are passed
7100 Extended ABI (as implemented by the Sun compiler) says that all
7101 complex floats are passed by reference. Pass complex integers
7102 in registers up to 8 bytes. More generally, enforce the 2-word
7103 cap for passing arguments in registers.
7105 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7106 integers are passed like floats of the same size, that is in
7107 registers up to 8 bytes. Pass all vector floats by reference
7108 like structure and unions. */
7109 return ((type
&& (AGGREGATE_TYPE_P (type
) || VECTOR_FLOAT_TYPE_P (type
)))
7111 /* Catch CDImode, TFmode, DCmode and TCmode. */
7112 || GET_MODE_SIZE (mode
) > 8
7114 && TREE_CODE (type
) == VECTOR_TYPE
7115 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7117 /* Original SPARC 64-bit ABI says that structures and unions
7118 smaller than 16 bytes are passed in registers, as well as
7119 all other base types.
7121 Extended ABI (as implemented by the Sun compiler) says that
7122 complex floats are passed in registers up to 16 bytes. Pass
7123 all complex integers in registers up to 16 bytes. More generally,
7124 enforce the 2-word cap for passing arguments in registers.
7126 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7127 integers are passed like floats of the same size, that is in
7128 registers (up to 16 bytes). Pass all vector floats like structure
7131 && (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
)
7132 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16)
7133 /* Catch CTImode and TCmode. */
7134 || GET_MODE_SIZE (mode
) > 16);
7137 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook.
7138 Update the data in CUM to advance over an argument
7139 of mode MODE and data type TYPE.
7140 TYPE is null for libcalls where that information may not be available. */
7143 sparc_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
7144 const_tree type
, bool named
)
7146 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
7149 /* We pass false for incoming_p here, it doesn't matter. */
7150 function_arg_slotno (cum
, mode
, type
, named
, false, ®no
, &padding
);
7152 /* If argument requires leading padding, add it. */
7153 cum
->words
+= padding
;
7157 cum
->words
+= (mode
!= BLKmode
7158 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
7159 : ROUND_ADVANCE (int_size_in_bytes (type
)));
7163 if (type
&& AGGREGATE_TYPE_P (type
))
7165 int size
= int_size_in_bytes (type
);
7169 else if (size
<= 16)
7171 else /* passed by reference */
7176 cum
->words
+= (mode
!= BLKmode
7177 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
7178 : ROUND_ADVANCE (int_size_in_bytes (type
)));
7183 /* Handle the FUNCTION_ARG_PADDING macro.
7184 For the 64 bit ABI structs are always stored left shifted in their
7188 function_arg_padding (enum machine_mode mode
, const_tree type
)
7190 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
7193 /* Fall back to the default. */
7194 return DEFAULT_FUNCTION_ARG_PADDING (mode
, type
);
7197 /* Handle the TARGET_RETURN_IN_MEMORY target hook.
7198 Specify whether to return the return value in memory. */
7201 sparc_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
7204 /* Original SPARC 32-bit ABI says that structures and unions,
7205 and quad-precision floats are returned in memory. All other
7206 base types are returned in registers.
7208 Extended ABI (as implemented by the Sun compiler) says that
7209 all complex floats are returned in registers (8 FP registers
7210 at most for '_Complex long double'). Return all complex integers
7211 in registers (4 at most for '_Complex long long').
7213 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7214 integers are returned like floats of the same size, that is in
7215 registers up to 8 bytes and in memory otherwise. Return all
7216 vector floats in memory like structure and unions; note that
7217 they always have BLKmode like the latter. */
7218 return (TYPE_MODE (type
) == BLKmode
7219 || TYPE_MODE (type
) == TFmode
7220 || (TREE_CODE (type
) == VECTOR_TYPE
7221 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 8));
7223 /* Original SPARC 64-bit ABI says that structures and unions
7224 smaller than 32 bytes are returned in registers, as well as
7225 all other base types.
7227 Extended ABI (as implemented by the Sun compiler) says that all
7228 complex floats are returned in registers (8 FP registers at most
7229 for '_Complex long double'). Return all complex integers in
7230 registers (4 at most for '_Complex TItype').
7232 Vector ABI (as implemented by the Sun VIS SDK) says that vector
7233 integers are returned like floats of the same size, that is in
7234 registers. Return all vector floats like structure and unions;
7235 note that they always have BLKmode like the latter. */
7236 return (TYPE_MODE (type
) == BLKmode
7237 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 32);
7240 /* Handle the TARGET_STRUCT_VALUE target hook.
7241 Return where to find the structure return value address. */
7244 sparc_struct_value_rtx (tree fndecl
, int incoming
)
7253 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, frame_pointer_rtx
,
7254 STRUCT_VALUE_OFFSET
));
7256 mem
= gen_frame_mem (Pmode
, plus_constant (Pmode
, stack_pointer_rtx
,
7257 STRUCT_VALUE_OFFSET
));
7259 /* Only follow the SPARC ABI for fixed-size structure returns.
7260 Variable size structure returns are handled per the normal
7261 procedures in GCC. This is enabled by -mstd-struct-return */
7263 && sparc_std_struct_return
7264 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))
7265 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl
))) == INTEGER_CST
)
7267 /* We must check and adjust the return address, as it is
7268 optional as to whether the return object is really
7270 rtx ret_reg
= gen_rtx_REG (Pmode
, 31);
7271 rtx scratch
= gen_reg_rtx (SImode
);
7272 rtx_code_label
*endlab
= gen_label_rtx ();
7274 /* Calculate the return object size */
7275 tree size
= TYPE_SIZE_UNIT (TREE_TYPE (fndecl
));
7276 rtx size_rtx
= GEN_INT (TREE_INT_CST_LOW (size
) & 0xfff);
7277 /* Construct a temporary return value */
7279 = assign_stack_local (Pmode
, TREE_INT_CST_LOW (size
), 0);
7281 /* Implement SPARC 32-bit psABI callee return struct checking:
7283 Fetch the instruction where we will return to and see if
7284 it's an unimp instruction (the most significant 10 bits
7286 emit_move_insn (scratch
, gen_rtx_MEM (SImode
,
7287 plus_constant (Pmode
,
7289 /* Assume the size is valid and pre-adjust */
7290 emit_insn (gen_add3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7291 emit_cmp_and_jump_insns (scratch
, size_rtx
, EQ
, const0_rtx
, SImode
,
7293 emit_insn (gen_sub3_insn (ret_reg
, ret_reg
, GEN_INT (4)));
7294 /* Write the address of the memory pointed to by temp_val into
7295 the memory pointed to by mem */
7296 emit_move_insn (mem
, XEXP (temp_val
, 0));
7297 emit_label (endlab
);
7304 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook.
7305 For v9, function return values are subject to the same rules as arguments,
7306 except that up to 32 bytes may be returned in registers. */
7309 sparc_function_value_1 (const_tree type
, enum machine_mode mode
,
7312 /* Beware that the two values are swapped here wrt function_arg. */
7313 int regbase
= (outgoing
7314 ? SPARC_INCOMING_INT_ARG_FIRST
7315 : SPARC_OUTGOING_INT_ARG_FIRST
);
7316 enum mode_class mclass
= GET_MODE_CLASS (mode
);
7319 /* Vector types deserve special treatment because they are polymorphic wrt
7320 their mode, depending upon whether VIS instructions are enabled. */
7321 if (type
&& TREE_CODE (type
) == VECTOR_TYPE
)
7323 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7324 gcc_assert ((TARGET_ARCH32
&& size
<= 8)
7325 || (TARGET_ARCH64
&& size
<= 32));
7327 if (mode
== BLKmode
)
7328 return function_arg_vector_value (size
,
7329 SPARC_FP_ARG_FIRST
);
7331 mclass
= MODE_FLOAT
;
7334 if (TARGET_ARCH64
&& type
)
7336 /* Structures up to 32 bytes in size are returned in registers. */
7337 if (TREE_CODE (type
) == RECORD_TYPE
)
7339 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7340 gcc_assert (size
<= 32);
7342 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
7345 /* Unions up to 32 bytes in size are returned in integer registers. */
7346 else if (TREE_CODE (type
) == UNION_TYPE
)
7348 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7349 gcc_assert (size
<= 32);
7351 return function_arg_union_value (size
, mode
, 0, regbase
);
7354 /* Objects that require it are returned in FP registers. */
7355 else if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
7358 /* All other aggregate types are returned in an integer register in a
7359 mode corresponding to the size of the type. */
7360 else if (AGGREGATE_TYPE_P (type
))
7362 /* All other aggregate types are passed in an integer register
7363 in a mode corresponding to the size of the type. */
7364 HOST_WIDE_INT size
= int_size_in_bytes (type
);
7365 gcc_assert (size
<= 32);
7367 mode
= mode_for_size (size
* BITS_PER_UNIT
, MODE_INT
, 0);
7369 /* ??? We probably should have made the same ABI change in
7370 3.4.0 as the one we made for unions. The latter was
7371 required by the SCD though, while the former is not
7372 specified, so we favored compatibility and efficiency.
7374 Now we're stuck for aggregates larger than 16 bytes,
7375 because OImode vanished in the meantime. Let's not
7376 try to be unduly clever, and simply follow the ABI
7377 for unions in that case. */
7378 if (mode
== BLKmode
)
7379 return function_arg_union_value (size
, mode
, 0, regbase
);
7384 /* We should only have pointer and integer types at this point. This
7385 must match sparc_promote_function_mode. */
7386 else if (mclass
== MODE_INT
&& GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7390 /* We should only have pointer and integer types at this point. This must
7391 match sparc_promote_function_mode. */
7392 else if (TARGET_ARCH32
7393 && mclass
== MODE_INT
7394 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
7397 if ((mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
) && TARGET_FPU
)
7398 regno
= SPARC_FP_ARG_FIRST
;
7402 return gen_rtx_REG (mode
, regno
);
7405 /* Handle TARGET_FUNCTION_VALUE.
7406 On the SPARC, the value is found in the first "output" register, but the
7407 called function leaves it in the first "input" register. */
7410 sparc_function_value (const_tree valtype
,
7411 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
7414 return sparc_function_value_1 (valtype
, TYPE_MODE (valtype
), outgoing
);
7417 /* Handle TARGET_LIBCALL_VALUE. */
7420 sparc_libcall_value (enum machine_mode mode
,
7421 const_rtx fun ATTRIBUTE_UNUSED
)
7423 return sparc_function_value_1 (NULL_TREE
, mode
, false);
7426 /* Handle FUNCTION_VALUE_REGNO_P.
7427 On the SPARC, the first "output" reg is used for integer values, and the
7428 first floating point register is used for floating point values. */
7431 sparc_function_value_regno_p (const unsigned int regno
)
7433 return (regno
== 8 || regno
== 32);
7436 /* Do what is necessary for `va_start'. We look at the current function
7437 to determine if stdarg or varargs is used and return the address of
7438 the first unnamed parameter. */
7441 sparc_builtin_saveregs (void)
7443 int first_reg
= crtl
->args
.info
.words
;
7447 for (regno
= first_reg
; regno
< SPARC_INT_ARG_MAX
; regno
++)
7448 emit_move_insn (gen_rtx_MEM (word_mode
,
7449 gen_rtx_PLUS (Pmode
,
7451 GEN_INT (FIRST_PARM_OFFSET (0)
7454 gen_rtx_REG (word_mode
,
7455 SPARC_INCOMING_INT_ARG_FIRST
+ regno
));
7457 address
= gen_rtx_PLUS (Pmode
,
7459 GEN_INT (FIRST_PARM_OFFSET (0)
7460 + UNITS_PER_WORD
* first_reg
));
7465 /* Implement `va_start' for stdarg. */
7468 sparc_va_start (tree valist
, rtx nextarg
)
7470 nextarg
= expand_builtin_saveregs ();
7471 std_expand_builtin_va_start (valist
, nextarg
);
7474 /* Implement `va_arg' for stdarg. */
7477 sparc_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
7480 HOST_WIDE_INT size
, rsize
, align
;
7483 tree ptrtype
= build_pointer_type (type
);
7485 if (pass_by_reference (NULL
, TYPE_MODE (type
), type
, false))
7488 size
= rsize
= UNITS_PER_WORD
;
7494 size
= int_size_in_bytes (type
);
7495 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
7500 /* For SPARC64, objects requiring 16-byte alignment get it. */
7501 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
7502 align
= 2 * UNITS_PER_WORD
;
7504 /* SPARC-V9 ABI states that structures up to 16 bytes in size
7505 are left-justified in their slots. */
7506 if (AGGREGATE_TYPE_P (type
))
7509 size
= rsize
= UNITS_PER_WORD
;
7519 incr
= fold_build_pointer_plus_hwi (incr
, align
- 1);
7520 incr
= fold_convert (sizetype
, incr
);
7521 incr
= fold_build2 (BIT_AND_EXPR
, sizetype
, incr
,
7523 incr
= fold_convert (ptr_type_node
, incr
);
7526 gimplify_expr (&incr
, pre_p
, post_p
, is_gimple_val
, fb_rvalue
);
7529 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
7530 addr
= fold_build_pointer_plus_hwi (incr
, rsize
- size
);
7534 addr
= fold_convert (build_pointer_type (ptrtype
), addr
);
7535 addr
= build_va_arg_indirect_ref (addr
);
7538 /* If the address isn't aligned properly for the type, we need a temporary.
7539 FIXME: This is inefficient, usually we can do this in registers. */
7540 else if (align
== 0 && TYPE_ALIGN (type
) > BITS_PER_WORD
)
7542 tree tmp
= create_tmp_var (type
, "va_arg_tmp");
7543 tree dest_addr
= build_fold_addr_expr (tmp
);
7544 tree copy
= build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY
),
7545 3, dest_addr
, addr
, size_int (rsize
));
7546 TREE_ADDRESSABLE (tmp
) = 1;
7547 gimplify_and_add (copy
, pre_p
);
7552 addr
= fold_convert (ptrtype
, addr
);
7554 incr
= fold_build_pointer_plus_hwi (incr
, rsize
);
7555 gimplify_assign (valist
, incr
, post_p
);
7557 return build_va_arg_indirect_ref (addr
);
7560 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook.
7561 Specify whether the vector mode is supported by the hardware. */
7564 sparc_vector_mode_supported_p (enum machine_mode mode
)
7566 return TARGET_VIS
&& VECTOR_MODE_P (mode
) ? true : false;
7569 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */
7571 static enum machine_mode
7572 sparc_preferred_simd_mode (enum machine_mode mode
)
7590 /* Return the string to output an unconditional branch to LABEL, which is
7591 the operand number of the label.
7593 DEST is the destination insn (i.e. the label), INSN is the source. */
7596 output_ubranch (rtx dest
, rtx_insn
*insn
)
7598 static char string
[64];
7599 bool v9_form
= false;
7603 /* Even if we are trying to use cbcond for this, evaluate
7604 whether we can use V9 branches as our backup plan. */
7607 if (INSN_ADDRESSES_SET_P ())
7608 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7609 - INSN_ADDRESSES (INSN_UID (insn
)));
7611 /* Leave some instructions for "slop". */
7612 if (TARGET_V9
&& delta
>= -260000 && delta
< 260000)
7617 bool emit_nop
= emit_cbcond_nop (insn
);
7621 if (delta
< -500 || delta
> 500)
7627 rval
= "ba,a,pt\t%%xcc, %l0";
7634 rval
= "cwbe\t%%g0, %%g0, %l0\n\tnop";
7636 rval
= "cwbe\t%%g0, %%g0, %l0";
7642 strcpy (string
, "ba%*,pt\t%%xcc, ");
7644 strcpy (string
, "b%*\t");
7646 p
= strchr (string
, '\0');
7657 /* Return the string to output a conditional branch to LABEL, which is
7658 the operand number of the label. OP is the conditional expression.
7659 XEXP (OP, 0) is assumed to be a condition code register (integer or
7660 floating point) and its mode specifies what kind of comparison we made.
7662 DEST is the destination insn (i.e. the label), INSN is the source.
7664 REVERSED is nonzero if we should reverse the sense of the comparison.
7666 ANNUL is nonzero if we should generate an annulling branch. */
7669 output_cbranch (rtx op
, rtx dest
, int label
, int reversed
, int annul
,
7672 static char string
[64];
7673 enum rtx_code code
= GET_CODE (op
);
7674 rtx cc_reg
= XEXP (op
, 0);
7675 enum machine_mode mode
= GET_MODE (cc_reg
);
7676 const char *labelno
, *branch
;
7677 int spaces
= 8, far
;
7680 /* v9 branches are limited to +-1MB. If it is too far away,
7693 fbne,a,pn %fcc2, .LC29
7701 far
= TARGET_V9
&& (get_attr_length (insn
) >= 3);
7704 /* Reversal of FP compares takes care -- an ordered compare
7705 becomes an unordered compare and vice versa. */
7706 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7707 code
= reverse_condition_maybe_unordered (code
);
7709 code
= reverse_condition (code
);
7712 /* Start by writing the branch condition. */
7713 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7764 /* ??? !v9: FP branches cannot be preceded by another floating point
7765 insn. Because there is currently no concept of pre-delay slots,
7766 we can fix this only by always emitting a nop before a floating
7771 strcpy (string
, "nop\n\t");
7772 strcat (string
, branch
);
7785 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7797 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
7818 strcpy (string
, branch
);
7820 spaces
-= strlen (branch
);
7821 p
= strchr (string
, '\0');
7823 /* Now add the annulling, the label, and a possible noop. */
7836 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
7838 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
7839 - INSN_ADDRESSES (INSN_UID (insn
)));
7840 /* Leave some instructions for "slop". */
7841 if (delta
< -260000 || delta
>= 260000)
7845 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
7847 static char v9_fcc_labelno
[] = "%%fccX, ";
7848 /* Set the char indicating the number of the fcc reg to use. */
7849 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
7850 labelno
= v9_fcc_labelno
;
7853 gcc_assert (REGNO (cc_reg
) == SPARC_FCC_REG
);
7857 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
7859 labelno
= "%%xcc, ";
7864 labelno
= "%%icc, ";
7869 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
7872 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
7885 strcpy (p
, labelno
);
7886 p
= strchr (p
, '\0');
7889 strcpy (p
, ".+12\n\t nop\n\tb\t");
7890 /* Skip the next insn if requested or
7891 if we know that it will be a nop. */
7892 if (annul
|| ! final_sequence
)
7906 /* Emit a library call comparison between floating point X and Y.
7907 COMPARISON is the operator to compare with (EQ, NE, GT, etc).
7908 Return the new operator to be used in the comparison sequence.
7910 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
7911 values as arguments instead of the TFmode registers themselves,
7912 that's why we cannot call emit_float_lib_cmp. */
7915 sparc_emit_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
)
7918 rtx slot0
, slot1
, result
, tem
, tem2
, libfunc
;
7919 enum machine_mode mode
;
7920 enum rtx_code new_comparison
;
7925 qpfunc
= (TARGET_ARCH64
? "_Qp_feq" : "_Q_feq");
7929 qpfunc
= (TARGET_ARCH64
? "_Qp_fne" : "_Q_fne");
7933 qpfunc
= (TARGET_ARCH64
? "_Qp_fgt" : "_Q_fgt");
7937 qpfunc
= (TARGET_ARCH64
? "_Qp_fge" : "_Q_fge");
7941 qpfunc
= (TARGET_ARCH64
? "_Qp_flt" : "_Q_flt");
7945 qpfunc
= (TARGET_ARCH64
? "_Qp_fle" : "_Q_fle");
7956 qpfunc
= (TARGET_ARCH64
? "_Qp_cmp" : "_Q_cmp");
7967 tree expr
= MEM_EXPR (x
);
7969 mark_addressable (expr
);
7974 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7975 emit_move_insn (slot0
, x
);
7980 tree expr
= MEM_EXPR (y
);
7982 mark_addressable (expr
);
7987 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
));
7988 emit_move_insn (slot1
, y
);
7991 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
7992 emit_library_call (libfunc
, LCT_NORMAL
,
7994 XEXP (slot0
, 0), Pmode
,
7995 XEXP (slot1
, 0), Pmode
);
8000 libfunc
= gen_rtx_SYMBOL_REF (Pmode
, qpfunc
);
8001 emit_library_call (libfunc
, LCT_NORMAL
,
8003 x
, TFmode
, y
, TFmode
);
8008 /* Immediately move the result of the libcall into a pseudo
8009 register so reload doesn't clobber the value if it needs
8010 the return register for a spill reg. */
8011 result
= gen_reg_rtx (mode
);
8012 emit_move_insn (result
, hard_libcall_value (mode
, libfunc
));
8017 return gen_rtx_NE (VOIDmode
, result
, const0_rtx
);
8020 new_comparison
= (comparison
== UNORDERED
? EQ
: NE
);
8021 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, GEN_INT(3));
8024 new_comparison
= (comparison
== UNGT
? GT
: NE
);
8025 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, result
, const1_rtx
);
8027 return gen_rtx_NE (VOIDmode
, result
, const2_rtx
);
8029 tem
= gen_reg_rtx (mode
);
8031 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
8033 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
8034 return gen_rtx_NE (VOIDmode
, tem
, const0_rtx
);
8037 tem
= gen_reg_rtx (mode
);
8039 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
8041 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
8042 tem2
= gen_reg_rtx (mode
);
8044 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
8046 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
8047 new_comparison
= (comparison
== UNEQ
? EQ
: NE
);
8048 return gen_rtx_fmt_ee (new_comparison
, VOIDmode
, tem2
, const0_rtx
);
8054 /* Generate an unsigned DImode to FP conversion. This is the same code
8055 optabs would emit if we didn't have TFmode patterns. */
8058 sparc_emit_floatunsdi (rtx
*operands
, enum machine_mode mode
)
8060 rtx i0
, i1
, f0
, in
, out
;
8063 in
= force_reg (DImode
, operands
[1]);
8064 rtx_code_label
*neglab
= gen_label_rtx ();
8065 rtx_code_label
*donelab
= gen_label_rtx ();
8066 i0
= gen_reg_rtx (DImode
);
8067 i1
= gen_reg_rtx (DImode
);
8068 f0
= gen_reg_rtx (mode
);
8070 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
8072 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
8073 emit_jump_insn (gen_jump (donelab
));
8076 emit_label (neglab
);
8078 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
8079 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
8080 emit_insn (gen_iordi3 (i0
, i0
, i1
));
8081 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
8082 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
8084 emit_label (donelab
);
8087 /* Generate an FP to unsigned DImode conversion. This is the same code
8088 optabs would emit if we didn't have TFmode patterns. */
8091 sparc_emit_fixunsdi (rtx
*operands
, enum machine_mode mode
)
8093 rtx i0
, i1
, f0
, in
, out
, limit
;
8096 in
= force_reg (mode
, operands
[1]);
8097 rtx_code_label
*neglab
= gen_label_rtx ();
8098 rtx_code_label
*donelab
= gen_label_rtx ();
8099 i0
= gen_reg_rtx (DImode
);
8100 i1
= gen_reg_rtx (DImode
);
8101 limit
= gen_reg_rtx (mode
);
8102 f0
= gen_reg_rtx (mode
);
8104 emit_move_insn (limit
,
8105 CONST_DOUBLE_FROM_REAL_VALUE (
8106 REAL_VALUE_ATOF ("9223372036854775808.0", mode
), mode
));
8107 emit_cmp_and_jump_insns (in
, limit
, GE
, NULL_RTX
, mode
, 0, neglab
);
8109 emit_insn (gen_rtx_SET (VOIDmode
,
8111 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, in
))));
8112 emit_jump_insn (gen_jump (donelab
));
8115 emit_label (neglab
);
8117 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_MINUS (mode
, in
, limit
)));
8118 emit_insn (gen_rtx_SET (VOIDmode
,
8120 gen_rtx_FIX (DImode
, gen_rtx_FIX (mode
, f0
))));
8121 emit_insn (gen_movdi (i1
, const1_rtx
));
8122 emit_insn (gen_ashldi3 (i1
, i1
, GEN_INT (63)));
8123 emit_insn (gen_xordi3 (out
, i0
, i1
));
8125 emit_label (donelab
);
8128 /* Return the string to output a compare and branch instruction to DEST.
8129 DEST is the destination insn (i.e. the label), INSN is the source,
8130 and OP is the conditional expression. */
8133 output_cbcond (rtx op
, rtx dest
, rtx_insn
*insn
)
8135 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
8136 enum rtx_code code
= GET_CODE (op
);
8137 const char *cond_str
, *tmpl
;
8138 int far
, emit_nop
, len
;
8139 static char string
[64];
8142 /* Compare and Branch is limited to +-2KB. If it is too far away,
8154 len
= get_attr_length (insn
);
8157 emit_nop
= len
== 2;
8160 code
= reverse_condition (code
);
8162 size_char
= ((mode
== SImode
) ? 'w' : 'x');
8175 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8190 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
8218 int veryfar
= 1, delta
;
8220 if (INSN_ADDRESSES_SET_P ())
8222 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8223 - INSN_ADDRESSES (INSN_UID (insn
)));
8224 /* Leave some instructions for "slop". */
8225 if (delta
>= -260000 && delta
< 260000)
8230 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop";
8232 tmpl
= "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop";
8237 tmpl
= "c%cb%s\t%%1, %%2, %%3\n\tnop";
8239 tmpl
= "c%cb%s\t%%1, %%2, %%3";
8242 snprintf (string
, sizeof(string
), tmpl
, size_char
, cond_str
);
8247 /* Return the string to output a conditional branch to LABEL, testing
8248 register REG. LABEL is the operand number of the label; REG is the
8249 operand number of the reg. OP is the conditional expression. The mode
8250 of REG says what kind of comparison we made.
8252 DEST is the destination insn (i.e. the label), INSN is the source.
8254 REVERSED is nonzero if we should reverse the sense of the comparison.
8256 ANNUL is nonzero if we should generate an annulling branch. */
8259 output_v9branch (rtx op
, rtx dest
, int reg
, int label
, int reversed
,
8260 int annul
, rtx_insn
*insn
)
8262 static char string
[64];
8263 enum rtx_code code
= GET_CODE (op
);
8264 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
8269 /* branch on register are limited to +-128KB. If it is too far away,
8282 brgez,a,pn %o1, .LC29
8288 ba,pt %xcc, .LC29 */
8290 far
= get_attr_length (insn
) >= 3;
8292 /* If not floating-point or if EQ or NE, we can just reverse the code. */
8294 code
= reverse_condition (code
);
8296 /* Only 64 bit versions of these instructions exist. */
8297 gcc_assert (mode
== DImode
);
8299 /* Start by writing the branch condition. */
8304 strcpy (string
, "brnz");
8308 strcpy (string
, "brz");
8312 strcpy (string
, "brgez");
8316 strcpy (string
, "brlz");
8320 strcpy (string
, "brlez");
8324 strcpy (string
, "brgz");
8331 p
= strchr (string
, '\0');
8333 /* Now add the annulling, reg, label, and nop. */
8340 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
8343 ((XINT (note
, 0) >= REG_BR_PROB_BASE
/ 2) ^ far
)
8348 *p
= p
< string
+ 8 ? '\t' : ' ';
8356 int veryfar
= 1, delta
;
8358 if (INSN_ADDRESSES_SET_P ())
8360 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
8361 - INSN_ADDRESSES (INSN_UID (insn
)));
8362 /* Leave some instructions for "slop". */
8363 if (delta
>= -260000 && delta
< 260000)
8367 strcpy (p
, ".+12\n\t nop\n\t");
8368 /* Skip the next insn if requested or
8369 if we know that it will be a nop. */
8370 if (annul
|| ! final_sequence
)
8380 strcpy (p
, "ba,pt\t%%xcc, ");
8394 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
8395 Such instructions cannot be used in the delay slot of return insn on v9.
8396 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
8400 epilogue_renumber (register rtx
*where
, int test
)
8402 register const char *fmt
;
8404 register enum rtx_code code
;
8409 code
= GET_CODE (*where
);
8414 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
8416 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
8417 *where
= gen_rtx_REG (GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
8425 /* Do not replace the frame pointer with the stack pointer because
8426 it can cause the delayed instruction to load below the stack.
8427 This occurs when instructions like:
8429 (set (reg/i:SI 24 %i0)
8430 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
8431 (const_int -20 [0xffffffec])) 0))
8433 are in the return delayed slot. */
8435 if (GET_CODE (XEXP (*where
, 0)) == REG
8436 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
8437 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
8438 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
8443 if (SPARC_STACK_BIAS
8444 && GET_CODE (XEXP (*where
, 0)) == REG
8445 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
8453 fmt
= GET_RTX_FORMAT (code
);
8455 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8460 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
8461 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
8464 else if (fmt
[i
] == 'e'
8465 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
8471 /* Leaf functions and non-leaf functions have different needs. */
8474 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
8477 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
8479 static const int *const reg_alloc_orders
[] = {
8480 reg_leaf_alloc_order
,
8481 reg_nonleaf_alloc_order
};
8484 order_regs_for_local_alloc (void)
8486 static int last_order_nonleaf
= 1;
8488 if (df_regs_ever_live_p (15) != last_order_nonleaf
)
8490 last_order_nonleaf
= !last_order_nonleaf
;
8491 memcpy ((char *) reg_alloc_order
,
8492 (const char *) reg_alloc_orders
[last_order_nonleaf
],
8493 FIRST_PSEUDO_REGISTER
* sizeof (int));
8497 /* Return 1 if REG and MEM are legitimate enough to allow the various
8498 mem<-->reg splits to be run. */
8501 sparc_splitdi_legitimate (rtx reg
, rtx mem
)
8503 /* Punt if we are here by mistake. */
8504 gcc_assert (reload_completed
);
8506 /* We must have an offsettable memory reference. */
8507 if (! offsettable_memref_p (mem
))
8510 /* If we have legitimate args for ldd/std, we do not want
8511 the split to happen. */
8512 if ((REGNO (reg
) % 2) == 0
8513 && mem_min_alignment (mem
, 8))
8520 /* Like sparc_splitdi_legitimate but for REG <--> REG moves. */
8523 sparc_split_regreg_legitimate (rtx reg1
, rtx reg2
)
8527 if (GET_CODE (reg1
) == SUBREG
)
8528 reg1
= SUBREG_REG (reg1
);
8529 if (GET_CODE (reg1
) != REG
)
8531 regno1
= REGNO (reg1
);
8533 if (GET_CODE (reg2
) == SUBREG
)
8534 reg2
= SUBREG_REG (reg2
);
8535 if (GET_CODE (reg2
) != REG
)
8537 regno2
= REGNO (reg2
);
8539 if (SPARC_INT_REG_P (regno1
) && SPARC_INT_REG_P (regno2
))
8544 if ((SPARC_INT_REG_P (regno1
) && SPARC_FP_REG_P (regno2
))
8545 || (SPARC_FP_REG_P (regno1
) && SPARC_INT_REG_P (regno2
)))
8552 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
8553 This makes them candidates for using ldd and std insns.
8555 Note reg1 and reg2 *must* be hard registers. */
8558 registers_ok_for_ldd_peep (rtx reg1
, rtx reg2
)
8560 /* We might have been passed a SUBREG. */
8561 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
8564 if (REGNO (reg1
) % 2 != 0)
8567 /* Integer ldd is deprecated in SPARC V9 */
8568 if (TARGET_V9
&& SPARC_INT_REG_P (REGNO (reg1
)))
8571 return (REGNO (reg1
) == REGNO (reg2
) - 1);
8574 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
8577 This can only happen when addr1 and addr2, the addresses in mem1
8578 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
8579 addr1 must also be aligned on a 64-bit boundary.
8581 Also iff dependent_reg_rtx is not null it should not be used to
8582 compute the address for mem1, i.e. we cannot optimize a sequence
8594 But, note that the transformation from:
8599 is perfectly fine. Thus, the peephole2 patterns always pass us
8600 the destination register of the first load, never the second one.
8602 For stores we don't have a similar problem, so dependent_reg_rtx is
8606 mems_ok_for_ldd_peep (rtx mem1
, rtx mem2
, rtx dependent_reg_rtx
)
8610 HOST_WIDE_INT offset1
;
8612 /* The mems cannot be volatile. */
8613 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
8616 /* MEM1 should be aligned on a 64-bit boundary. */
8617 if (MEM_ALIGN (mem1
) < 64)
8620 addr1
= XEXP (mem1
, 0);
8621 addr2
= XEXP (mem2
, 0);
8623 /* Extract a register number and offset (if used) from the first addr. */
8624 if (GET_CODE (addr1
) == PLUS
)
8626 /* If not a REG, return zero. */
8627 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
8631 reg1
= REGNO (XEXP (addr1
, 0));
8632 /* The offset must be constant! */
8633 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
8635 offset1
= INTVAL (XEXP (addr1
, 1));
8638 else if (GET_CODE (addr1
) != REG
)
8642 reg1
= REGNO (addr1
);
8643 /* This was a simple (mem (reg)) expression. Offset is 0. */
8647 /* Make sure the second address is a (mem (plus (reg) (const_int). */
8648 if (GET_CODE (addr2
) != PLUS
)
8651 if (GET_CODE (XEXP (addr2
, 0)) != REG
8652 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
8655 if (reg1
!= REGNO (XEXP (addr2
, 0)))
8658 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
8661 /* The first offset must be evenly divisible by 8 to ensure the
8662 address is 64 bit aligned. */
8663 if (offset1
% 8 != 0)
8666 /* The offset for the second addr must be 4 more than the first addr. */
8667 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
8670 /* All the tests passed. addr1 and addr2 are valid for ldd and std
8675 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */
8678 widen_mem_for_ldd_peep (rtx mem1
, rtx mem2
, enum machine_mode mode
)
8680 rtx x
= widen_memory_access (mem1
, mode
, 0);
8681 MEM_NOTRAP_P (x
) = MEM_NOTRAP_P (mem1
) && MEM_NOTRAP_P (mem2
);
8685 /* Return 1 if reg is a pseudo, or is the first register in
8686 a hard register pair. This makes it suitable for use in
8687 ldd and std insns. */
8690 register_ok_for_ldd (rtx reg
)
8692 /* We might have been passed a SUBREG. */
8696 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
8697 return (REGNO (reg
) % 2 == 0);
8702 /* Return 1 if OP, a MEM, has an address which is known to be
8703 aligned to an 8-byte boundary. */
8706 memory_ok_for_ldd (rtx op
)
8708 /* In 64-bit mode, we assume that the address is word-aligned. */
8709 if (TARGET_ARCH32
&& !mem_min_alignment (op
, 8))
8712 if (! can_create_pseudo_p ()
8713 && !strict_memory_address_p (Pmode
, XEXP (op
, 0)))
8719 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
8722 sparc_print_operand_punct_valid_p (unsigned char code
)
8735 /* Implement TARGET_PRINT_OPERAND.
8736 Print operand X (an rtx) in assembler syntax to file FILE.
8737 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
8738 For `%' followed by punctuation, CODE is the punctuation and X is null. */
8741 sparc_print_operand (FILE *file
, rtx x
, int code
)
8746 /* Output an insn in a delay slot. */
8748 sparc_indent_opcode
= 1;
8750 fputs ("\n\t nop", file
);
8753 /* Output an annul flag if there's nothing for the delay slot and we
8754 are optimizing. This is always used with '(' below.
8755 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
8756 this is a dbx bug. So, we only do this when optimizing.
8757 On UltraSPARC, a branch in a delay slot causes a pipeline flush.
8758 Always emit a nop in case the next instruction is a branch. */
8759 if (! final_sequence
&& (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8763 /* Output a 'nop' if there's nothing for the delay slot and we are
8764 not optimizing. This is always used with '*' above. */
8765 if (! final_sequence
&& ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
8766 fputs ("\n\t nop", file
);
8767 else if (final_sequence
)
8768 sparc_indent_opcode
= 1;
8771 /* Output the right displacement from the saved PC on function return.
8772 The caller may have placed an "unimp" insn immediately after the call
8773 so we have to account for it. This insn is used in the 32-bit ABI
8774 when calling a function that returns a non zero-sized structure. The
8775 64-bit ABI doesn't have it. Be careful to have this test be the same
8776 as that for the call. The exception is when sparc_std_struct_return
8777 is enabled, the psABI is followed exactly and the adjustment is made
8778 by the code in sparc_struct_value_rtx. The call emitted is the same
8779 when sparc_std_struct_return is enabled. */
8781 && cfun
->returns_struct
8782 && !sparc_std_struct_return
8783 && DECL_SIZE (DECL_RESULT (current_function_decl
))
8784 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl
)))
8786 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl
))))
8792 /* Output the Embedded Medium/Anywhere code model base register. */
8793 fputs (EMBMEDANY_BASE_REG
, file
);
8796 /* Print some local dynamic TLS name. */
8797 if (const char *name
= get_some_local_dynamic_name ())
8798 assemble_name (file
, name
);
8800 output_operand_lossage ("'%%&' used without any "
8801 "local dynamic TLS references");
8805 /* Adjust the operand to take into account a RESTORE operation. */
8806 if (GET_CODE (x
) == CONST_INT
)
8808 else if (GET_CODE (x
) != REG
)
8809 output_operand_lossage ("invalid %%Y operand");
8810 else if (REGNO (x
) < 8)
8811 fputs (reg_names
[REGNO (x
)], file
);
8812 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
8813 fputs (reg_names
[REGNO (x
)-16], file
);
8815 output_operand_lossage ("invalid %%Y operand");
8818 /* Print out the low order register name of a register pair. */
8819 if (WORDS_BIG_ENDIAN
)
8820 fputs (reg_names
[REGNO (x
)+1], file
);
8822 fputs (reg_names
[REGNO (x
)], file
);
8825 /* Print out the high order register name of a register pair. */
8826 if (WORDS_BIG_ENDIAN
)
8827 fputs (reg_names
[REGNO (x
)], file
);
8829 fputs (reg_names
[REGNO (x
)+1], file
);
8832 /* Print out the second register name of a register pair or quad.
8833 I.e., R (%o0) => %o1. */
8834 fputs (reg_names
[REGNO (x
)+1], file
);
8837 /* Print out the third register name of a register quad.
8838 I.e., S (%o0) => %o2. */
8839 fputs (reg_names
[REGNO (x
)+2], file
);
8842 /* Print out the fourth register name of a register quad.
8843 I.e., T (%o0) => %o3. */
8844 fputs (reg_names
[REGNO (x
)+3], file
);
8847 /* Print a condition code register. */
8848 if (REGNO (x
) == SPARC_ICC_REG
)
8850 /* We don't handle CC[X]_NOOVmode because they're not supposed
8852 if (GET_MODE (x
) == CCmode
)
8853 fputs ("%icc", file
);
8854 else if (GET_MODE (x
) == CCXmode
)
8855 fputs ("%xcc", file
);
8860 /* %fccN register */
8861 fputs (reg_names
[REGNO (x
)], file
);
8864 /* Print the operand's address only. */
8865 output_address (XEXP (x
, 0));
8868 /* In this case we need a register. Use %g0 if the
8869 operand is const0_rtx. */
8871 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
8873 fputs ("%g0", file
);
8880 switch (GET_CODE (x
))
8882 case IOR
: fputs ("or", file
); break;
8883 case AND
: fputs ("and", file
); break;
8884 case XOR
: fputs ("xor", file
); break;
8885 default: output_operand_lossage ("invalid %%A operand");
8890 switch (GET_CODE (x
))
8892 case IOR
: fputs ("orn", file
); break;
8893 case AND
: fputs ("andn", file
); break;
8894 case XOR
: fputs ("xnor", file
); break;
8895 default: output_operand_lossage ("invalid %%B operand");
8899 /* This is used by the conditional move instructions. */
8902 enum rtx_code rc
= GET_CODE (x
);
8906 case NE
: fputs ("ne", file
); break;
8907 case EQ
: fputs ("e", file
); break;
8908 case GE
: fputs ("ge", file
); break;
8909 case GT
: fputs ("g", file
); break;
8910 case LE
: fputs ("le", file
); break;
8911 case LT
: fputs ("l", file
); break;
8912 case GEU
: fputs ("geu", file
); break;
8913 case GTU
: fputs ("gu", file
); break;
8914 case LEU
: fputs ("leu", file
); break;
8915 case LTU
: fputs ("lu", file
); break;
8916 case LTGT
: fputs ("lg", file
); break;
8917 case UNORDERED
: fputs ("u", file
); break;
8918 case ORDERED
: fputs ("o", file
); break;
8919 case UNLT
: fputs ("ul", file
); break;
8920 case UNLE
: fputs ("ule", file
); break;
8921 case UNGT
: fputs ("ug", file
); break;
8922 case UNGE
: fputs ("uge", file
); break;
8923 case UNEQ
: fputs ("ue", file
); break;
8924 default: output_operand_lossage ("invalid %%C operand");
8929 /* This are used by the movr instruction pattern. */
8932 enum rtx_code rc
= GET_CODE (x
);
8935 case NE
: fputs ("ne", file
); break;
8936 case EQ
: fputs ("e", file
); break;
8937 case GE
: fputs ("gez", file
); break;
8938 case LT
: fputs ("lz", file
); break;
8939 case LE
: fputs ("lez", file
); break;
8940 case GT
: fputs ("gz", file
); break;
8941 default: output_operand_lossage ("invalid %%D operand");
8948 /* Print a sign-extended character. */
8949 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
8950 fprintf (file
, "%d", i
);
8955 /* Operand must be a MEM; write its address. */
8956 if (GET_CODE (x
) != MEM
)
8957 output_operand_lossage ("invalid %%f operand");
8958 output_address (XEXP (x
, 0));
8963 /* Print a sign-extended 32-bit value. */
8965 if (GET_CODE(x
) == CONST_INT
)
8967 else if (GET_CODE(x
) == CONST_DOUBLE
)
8968 i
= CONST_DOUBLE_LOW (x
);
8971 output_operand_lossage ("invalid %%s operand");
8974 i
= trunc_int_for_mode (i
, SImode
);
8975 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, i
);
8980 /* Do nothing special. */
8984 /* Undocumented flag. */
8985 output_operand_lossage ("invalid operand output code");
8988 if (GET_CODE (x
) == REG
)
8989 fputs (reg_names
[REGNO (x
)], file
);
8990 else if (GET_CODE (x
) == MEM
)
8993 /* Poor Sun assembler doesn't understand absolute addressing. */
8994 if (CONSTANT_P (XEXP (x
, 0)))
8995 fputs ("%g0+", file
);
8996 output_address (XEXP (x
, 0));
8999 else if (GET_CODE (x
) == HIGH
)
9001 fputs ("%hi(", file
);
9002 output_addr_const (file
, XEXP (x
, 0));
9005 else if (GET_CODE (x
) == LO_SUM
)
9007 sparc_print_operand (file
, XEXP (x
, 0), 0);
9008 if (TARGET_CM_MEDMID
)
9009 fputs ("+%l44(", file
);
9011 fputs ("+%lo(", file
);
9012 output_addr_const (file
, XEXP (x
, 1));
9015 else if (GET_CODE (x
) == CONST_DOUBLE
9016 && (GET_MODE (x
) == VOIDmode
9017 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
9019 if (CONST_DOUBLE_HIGH (x
) == 0)
9020 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
9021 else if (CONST_DOUBLE_HIGH (x
) == -1
9022 && CONST_DOUBLE_LOW (x
) < 0)
9023 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
9025 output_operand_lossage ("long long constant not a valid immediate operand");
9027 else if (GET_CODE (x
) == CONST_DOUBLE
)
9028 output_operand_lossage ("floating point constant not a valid immediate operand");
9029 else { output_addr_const (file
, x
); }
9032 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
9035 sparc_print_operand_address (FILE *file
, rtx x
)
9037 register rtx base
, index
= 0;
9039 register rtx addr
= x
;
9042 fputs (reg_names
[REGNO (addr
)], file
);
9043 else if (GET_CODE (addr
) == PLUS
)
9045 if (CONST_INT_P (XEXP (addr
, 0)))
9046 offset
= INTVAL (XEXP (addr
, 0)), base
= XEXP (addr
, 1);
9047 else if (CONST_INT_P (XEXP (addr
, 1)))
9048 offset
= INTVAL (XEXP (addr
, 1)), base
= XEXP (addr
, 0);
9050 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
9051 if (GET_CODE (base
) == LO_SUM
)
9053 gcc_assert (USE_AS_OFFSETABLE_LO10
9055 && ! TARGET_CM_MEDMID
);
9056 output_operand (XEXP (base
, 0), 0);
9057 fputs ("+%lo(", file
);
9058 output_address (XEXP (base
, 1));
9059 fprintf (file
, ")+%d", offset
);
9063 fputs (reg_names
[REGNO (base
)], file
);
9065 fprintf (file
, "%+d", offset
);
9066 else if (REG_P (index
))
9067 fprintf (file
, "+%s", reg_names
[REGNO (index
)]);
9068 else if (GET_CODE (index
) == SYMBOL_REF
9069 || GET_CODE (index
) == LABEL_REF
9070 || GET_CODE (index
) == CONST
)
9071 fputc ('+', file
), output_addr_const (file
, index
);
9072 else gcc_unreachable ();
9075 else if (GET_CODE (addr
) == MINUS
9076 && GET_CODE (XEXP (addr
, 1)) == LABEL_REF
)
9078 output_addr_const (file
, XEXP (addr
, 0));
9080 output_addr_const (file
, XEXP (addr
, 1));
9081 fputs ("-.)", file
);
9083 else if (GET_CODE (addr
) == LO_SUM
)
9085 output_operand (XEXP (addr
, 0), 0);
9086 if (TARGET_CM_MEDMID
)
9087 fputs ("+%l44(", file
);
9089 fputs ("+%lo(", file
);
9090 output_address (XEXP (addr
, 1));
9094 && GET_CODE (addr
) == CONST
9095 && GET_CODE (XEXP (addr
, 0)) == MINUS
9096 && GET_CODE (XEXP (XEXP (addr
, 0), 1)) == CONST
9097 && GET_CODE (XEXP (XEXP (XEXP (addr
, 0), 1), 0)) == MINUS
9098 && XEXP (XEXP (XEXP (XEXP (addr
, 0), 1), 0), 1) == pc_rtx
)
9100 addr
= XEXP (addr
, 0);
9101 output_addr_const (file
, XEXP (addr
, 0));
9102 /* Group the args of the second CONST in parenthesis. */
9104 /* Skip past the second CONST--it does nothing for us. */
9105 output_addr_const (file
, XEXP (XEXP (addr
, 1), 0));
9106 /* Close the parenthesis. */
9111 output_addr_const (file
, addr
);
9115 /* Target hook for assembling integer objects. The sparc version has
9116 special handling for aligned DI-mode objects. */
9119 sparc_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
9121 /* ??? We only output .xword's for symbols and only then in environments
9122 where the assembler can handle them. */
9123 if (aligned_p
&& size
== 8
9124 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
9128 assemble_integer_with_op ("\t.xword\t", x
);
9133 assemble_aligned_integer (4, const0_rtx
);
9134 assemble_aligned_integer (4, x
);
9138 return default_assemble_integer (x
, size
, aligned_p
);
9141 /* Return the value of a code used in the .proc pseudo-op that says
9142 what kind of result this function returns. For non-C types, we pick
9143 the closest C type. */
9145 #ifndef SHORT_TYPE_SIZE
9146 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
9149 #ifndef INT_TYPE_SIZE
9150 #define INT_TYPE_SIZE BITS_PER_WORD
9153 #ifndef LONG_TYPE_SIZE
9154 #define LONG_TYPE_SIZE BITS_PER_WORD
9157 #ifndef LONG_LONG_TYPE_SIZE
9158 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
9161 #ifndef FLOAT_TYPE_SIZE
9162 #define FLOAT_TYPE_SIZE BITS_PER_WORD
9165 #ifndef DOUBLE_TYPE_SIZE
9166 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9169 #ifndef LONG_DOUBLE_TYPE_SIZE
9170 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
9174 sparc_type_code (register tree type
)
9176 register unsigned long qualifiers
= 0;
9177 register unsigned shift
;
9179 /* Only the first 30 bits of the qualifier are valid. We must refrain from
9180 setting more, since some assemblers will give an error for this. Also,
9181 we must be careful to avoid shifts of 32 bits or more to avoid getting
9182 unpredictable results. */
9184 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
9186 switch (TREE_CODE (type
))
9192 qualifiers
|= (3 << shift
);
9197 qualifiers
|= (2 << shift
);
9201 case REFERENCE_TYPE
:
9203 qualifiers
|= (1 << shift
);
9207 return (qualifiers
| 8);
9210 case QUAL_UNION_TYPE
:
9211 return (qualifiers
| 9);
9214 return (qualifiers
| 10);
9217 return (qualifiers
| 16);
9220 /* If this is a range type, consider it to be the underlying
9222 if (TREE_TYPE (type
) != 0)
9225 /* Carefully distinguish all the standard types of C,
9226 without messing up if the language is not C. We do this by
9227 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to
9228 look at both the names and the above fields, but that's redundant.
9229 Any type whose size is between two C types will be considered
9230 to be the wider of the two types. Also, we do not have a
9231 special code to use for "long long", so anything wider than
9232 long is treated the same. Note that we can't distinguish
9233 between "int" and "long" in this code if they are the same
9234 size, but that's fine, since neither can the assembler. */
9236 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
9237 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 12 : 2));
9239 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
9240 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 13 : 3));
9242 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
9243 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 14 : 4));
9246 return (qualifiers
| (TYPE_UNSIGNED (type
) ? 15 : 5));
9249 /* If this is a range type, consider it to be the underlying
9251 if (TREE_TYPE (type
) != 0)
9254 /* Carefully distinguish all the standard types of C,
9255 without messing up if the language is not C. */
9257 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
9258 return (qualifiers
| 6);
9261 return (qualifiers
| 7);
9263 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
9264 /* ??? We need to distinguish between double and float complex types,
9265 but I don't know how yet because I can't reach this code from
9266 existing front-ends. */
9267 return (qualifiers
| 7); /* Who knows? */
9270 case BOOLEAN_TYPE
: /* Boolean truth value type. */
9276 gcc_unreachable (); /* Not a type! */
9283 /* Nested function support. */
9285 /* Emit RTL insns to initialize the variable parts of a trampoline.
9286 FNADDR is an RTX for the address of the function's pure code.
9287 CXT is an RTX for the static chain value for the function.
9289 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
9290 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
9291 (to store insns). This is a bit excessive. Perhaps a different
9292 mechanism would be better here.
9294 Emit enough FLUSH insns to synchronize the data and instruction caches. */
9297 sparc32_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9299 /* SPARC 32-bit trampoline:
9302 sethi %hi(static), %g2
9304 or %g2, %lo(static), %g2
9306 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
9307 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
9311 (adjust_address (m_tramp
, SImode
, 0),
9312 expand_binop (SImode
, ior_optab
,
9313 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
, 10, 0, 1),
9314 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
9315 NULL_RTX
, 1, OPTAB_DIRECT
));
9318 (adjust_address (m_tramp
, SImode
, 4),
9319 expand_binop (SImode
, ior_optab
,
9320 expand_shift (RSHIFT_EXPR
, SImode
, cxt
, 10, 0, 1),
9321 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
9322 NULL_RTX
, 1, OPTAB_DIRECT
));
9325 (adjust_address (m_tramp
, SImode
, 8),
9326 expand_binop (SImode
, ior_optab
,
9327 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
9328 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
9329 NULL_RTX
, 1, OPTAB_DIRECT
));
9332 (adjust_address (m_tramp
, SImode
, 12),
9333 expand_binop (SImode
, ior_optab
,
9334 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
9335 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
9336 NULL_RTX
, 1, OPTAB_DIRECT
));
9338 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
9339 aligned on a 16 byte boundary so one flush clears it all. */
9340 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 0))));
9341 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9342 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9343 && sparc_cpu
!= PROCESSOR_NIAGARA
9344 && sparc_cpu
!= PROCESSOR_NIAGARA2
9345 && sparc_cpu
!= PROCESSOR_NIAGARA3
9346 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
9347 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp
, SImode
, 8))));
9349 /* Call __enable_execute_stack after writing onto the stack to make sure
9350 the stack address is accessible. */
9351 #ifdef HAVE_ENABLE_EXECUTE_STACK
9352 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9353 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9358 /* The 64-bit version is simpler because it makes more sense to load the
9359 values as "immediate" data out of the trampoline. It's also easier since
9360 we can read the PC without clobbering a register. */
9363 sparc64_initialize_trampoline (rtx m_tramp
, rtx fnaddr
, rtx cxt
)
9365 /* SPARC 64-bit trampoline:
9374 emit_move_insn (adjust_address (m_tramp
, SImode
, 0),
9375 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
9376 emit_move_insn (adjust_address (m_tramp
, SImode
, 4),
9377 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
9378 emit_move_insn (adjust_address (m_tramp
, SImode
, 8),
9379 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
9380 emit_move_insn (adjust_address (m_tramp
, SImode
, 12),
9381 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
9382 emit_move_insn (adjust_address (m_tramp
, DImode
, 16), cxt
);
9383 emit_move_insn (adjust_address (m_tramp
, DImode
, 24), fnaddr
);
9384 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 0))));
9386 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
9387 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
9388 && sparc_cpu
!= PROCESSOR_NIAGARA
9389 && sparc_cpu
!= PROCESSOR_NIAGARA2
9390 && sparc_cpu
!= PROCESSOR_NIAGARA3
9391 && sparc_cpu
!= PROCESSOR_NIAGARA4
)
9392 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp
, DImode
, 8))));
9394 /* Call __enable_execute_stack after writing onto the stack to make sure
9395 the stack address is accessible. */
9396 #ifdef HAVE_ENABLE_EXECUTE_STACK
9397 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__enable_execute_stack"),
9398 LCT_NORMAL
, VOIDmode
, 1, XEXP (m_tramp
, 0), Pmode
);
9402 /* Worker for TARGET_TRAMPOLINE_INIT. */
9405 sparc_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
9407 rtx fnaddr
= force_reg (Pmode
, XEXP (DECL_RTL (fndecl
), 0));
9408 cxt
= force_reg (Pmode
, cxt
);
9410 sparc64_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9412 sparc32_initialize_trampoline (m_tramp
, fnaddr
, cxt
);
9415 /* Adjust the cost of a scheduling dependency. Return the new cost of
9416 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
9419 supersparc_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
, int cost
)
9421 enum attr_type insn_type
;
9423 if (! recog_memoized (insn
))
9426 insn_type
= get_attr_type (insn
);
9428 if (REG_NOTE_KIND (link
) == 0)
9430 /* Data dependency; DEP_INSN writes a register that INSN reads some
9433 /* if a load, then the dependence must be on the memory address;
9434 add an extra "cycle". Note that the cost could be two cycles
9435 if the reg was written late in an instruction group; we ca not tell
9437 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
9440 /* Get the delay only if the address of the store is the dependence. */
9441 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
9443 rtx pat
= PATTERN(insn
);
9444 rtx dep_pat
= PATTERN (dep_insn
);
9446 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9447 return cost
; /* This should not happen! */
9449 /* The dependency between the two instructions was on the data that
9450 is being stored. Assume that this implies that the address of the
9451 store is not dependent. */
9452 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9455 return cost
+ 3; /* An approximation. */
9458 /* A shift instruction cannot receive its data from an instruction
9459 in the same cycle; add a one cycle penalty. */
9460 if (insn_type
== TYPE_SHIFT
)
9461 return cost
+ 3; /* Split before cascade into shift. */
9465 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
9466 INSN writes some cycles later. */
9468 /* These are only significant for the fpu unit; writing a fp reg before
9469 the fpu has finished with it stalls the processor. */
9471 /* Reusing an integer register causes no problems. */
9472 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9480 hypersparc_adjust_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep_insn
, int cost
)
9482 enum attr_type insn_type
, dep_type
;
9483 rtx pat
= PATTERN(insn
);
9484 rtx dep_pat
= PATTERN (dep_insn
);
9486 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
9489 insn_type
= get_attr_type (insn
);
9490 dep_type
= get_attr_type (dep_insn
);
9492 switch (REG_NOTE_KIND (link
))
9495 /* Data dependency; DEP_INSN writes a register that INSN reads some
9502 /* Get the delay iff the address of the store is the dependence. */
9503 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
9506 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
9513 /* If a load, then the dependence must be on the memory address. If
9514 the addresses aren't equal, then it might be a false dependency */
9515 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
9517 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
9518 || GET_CODE (SET_DEST (dep_pat
)) != MEM
9519 || GET_CODE (SET_SRC (pat
)) != MEM
9520 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
9521 XEXP (SET_SRC (pat
), 0)))
9529 /* Compare to branch latency is 0. There is no benefit from
9530 separating compare and branch. */
9531 if (dep_type
== TYPE_COMPARE
)
9533 /* Floating point compare to branch latency is less than
9534 compare to conditional move. */
9535 if (dep_type
== TYPE_FPCMP
)
9544 /* Anti-dependencies only penalize the fpu unit. */
9545 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
9557 sparc_adjust_cost(rtx_insn
*insn
, rtx link
, rtx_insn
*dep
, int cost
)
9561 case PROCESSOR_SUPERSPARC
:
9562 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
9564 case PROCESSOR_HYPERSPARC
:
9565 case PROCESSOR_SPARCLITE86X
:
9566 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
9575 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED
,
9576 int sched_verbose ATTRIBUTE_UNUSED
,
9577 int max_ready ATTRIBUTE_UNUSED
)
9581 sparc_use_sched_lookahead (void)
9583 if (sparc_cpu
== PROCESSOR_NIAGARA
9584 || sparc_cpu
== PROCESSOR_NIAGARA2
9585 || sparc_cpu
== PROCESSOR_NIAGARA3
)
9587 if (sparc_cpu
== PROCESSOR_NIAGARA4
)
9589 if (sparc_cpu
== PROCESSOR_ULTRASPARC
9590 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
9592 if ((1 << sparc_cpu
) &
9593 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
9594 (1 << PROCESSOR_SPARCLITE86X
)))
9600 sparc_issue_rate (void)
9604 case PROCESSOR_NIAGARA
:
9605 case PROCESSOR_NIAGARA2
:
9606 case PROCESSOR_NIAGARA3
:
9609 case PROCESSOR_NIAGARA4
:
9611 /* Assume V9 processors are capable of at least dual-issue. */
9613 case PROCESSOR_SUPERSPARC
:
9615 case PROCESSOR_HYPERSPARC
:
9616 case PROCESSOR_SPARCLITE86X
:
9618 case PROCESSOR_ULTRASPARC
:
9619 case PROCESSOR_ULTRASPARC3
:
9625 set_extends (rtx_insn
*insn
)
9627 register rtx pat
= PATTERN (insn
);
9629 switch (GET_CODE (SET_SRC (pat
)))
9631 /* Load and some shift instructions zero extend. */
9634 /* sethi clears the high bits */
9636 /* LO_SUM is used with sethi. sethi cleared the high
9637 bits and the values used with lo_sum are positive */
9639 /* Store flag stores 0 or 1 */
9649 rtx op0
= XEXP (SET_SRC (pat
), 0);
9650 rtx op1
= XEXP (SET_SRC (pat
), 1);
9651 if (GET_CODE (op1
) == CONST_INT
)
9652 return INTVAL (op1
) >= 0;
9653 if (GET_CODE (op0
) != REG
)
9655 if (sparc_check_64 (op0
, insn
) == 1)
9657 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9662 rtx op0
= XEXP (SET_SRC (pat
), 0);
9663 rtx op1
= XEXP (SET_SRC (pat
), 1);
9664 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
9666 if (GET_CODE (op1
) == CONST_INT
)
9667 return INTVAL (op1
) >= 0;
9668 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
9671 return GET_MODE (SET_SRC (pat
)) == SImode
;
9672 /* Positive integers leave the high bits zero. */
9674 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
9676 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
9679 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
9681 return sparc_check_64 (SET_SRC (pat
), insn
);
9687 /* We _ought_ to have only one kind per function, but... */
9688 static GTY(()) rtx sparc_addr_diff_list
;
9689 static GTY(()) rtx sparc_addr_list
;
9692 sparc_defer_case_vector (rtx lab
, rtx vec
, int diff
)
9694 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
9696 sparc_addr_diff_list
9697 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
9699 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
9703 sparc_output_addr_vec (rtx vec
)
9705 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9706 int idx
, vlen
= XVECLEN (body
, 0);
9708 #ifdef ASM_OUTPUT_ADDR_VEC_START
9709 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9712 #ifdef ASM_OUTPUT_CASE_LABEL
9713 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9716 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9719 for (idx
= 0; idx
< vlen
; idx
++)
9721 ASM_OUTPUT_ADDR_VEC_ELT
9722 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
9725 #ifdef ASM_OUTPUT_ADDR_VEC_END
9726 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9731 sparc_output_addr_diff_vec (rtx vec
)
9733 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
9734 rtx base
= XEXP (XEXP (body
, 0), 0);
9735 int idx
, vlen
= XVECLEN (body
, 1);
9737 #ifdef ASM_OUTPUT_ADDR_VEC_START
9738 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
9741 #ifdef ASM_OUTPUT_CASE_LABEL
9742 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
9745 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
9748 for (idx
= 0; idx
< vlen
; idx
++)
9750 ASM_OUTPUT_ADDR_DIFF_ELT
9753 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
9754 CODE_LABEL_NUMBER (base
));
9757 #ifdef ASM_OUTPUT_ADDR_VEC_END
9758 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
9763 sparc_output_deferred_case_vectors (void)
9768 if (sparc_addr_list
== NULL_RTX
9769 && sparc_addr_diff_list
== NULL_RTX
)
9772 /* Align to cache line in the function's code section. */
9773 switch_to_section (current_function_section ());
9775 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
9777 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
9779 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
9780 sparc_output_addr_vec (XEXP (t
, 0));
9781 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
9782 sparc_output_addr_diff_vec (XEXP (t
, 0));
9784 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
9787 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
9788 unknown. Return 1 if the high bits are zero, -1 if the register is
9791 sparc_check_64 (rtx x
, rtx_insn
*insn
)
9793 /* If a register is set only once it is safe to ignore insns this
9794 code does not know how to handle. The loop will either recognize
9795 the single set and return the correct value or fail to recognize
9800 gcc_assert (GET_CODE (x
) == REG
);
9802 if (GET_MODE (x
) == DImode
)
9803 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
9805 if (flag_expensive_optimizations
9806 && df
&& DF_REG_DEF_COUNT (REGNO (y
)) == 1)
9812 insn
= get_last_insn_anywhere ();
9817 while ((insn
= PREV_INSN (insn
)))
9819 switch (GET_CODE (insn
))
9832 rtx pat
= PATTERN (insn
);
9833 if (GET_CODE (pat
) != SET
)
9835 if (rtx_equal_p (x
, SET_DEST (pat
)))
9836 return set_extends (insn
);
9837 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
9838 return set_extends (insn
);
9839 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
9847 /* Output a wide shift instruction in V8+ mode. INSN is the instruction,
9848 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
9851 output_v8plus_shift (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
9853 static char asm_code
[60];
9855 /* The scratch register is only required when the destination
9856 register is not a 64-bit global or out register. */
9857 if (which_alternative
!= 2)
9858 operands
[3] = operands
[0];
9860 /* We can only shift by constants <= 63. */
9861 if (GET_CODE (operands
[2]) == CONST_INT
)
9862 operands
[2] = GEN_INT (INTVAL (operands
[2]) & 0x3f);
9864 if (GET_CODE (operands
[1]) == CONST_INT
)
9866 output_asm_insn ("mov\t%1, %3", operands
);
9870 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
9871 if (sparc_check_64 (operands
[1], insn
) <= 0)
9872 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
9873 output_asm_insn ("or\t%L1, %3, %3", operands
);
9876 strcpy (asm_code
, opcode
);
9878 if (which_alternative
!= 2)
9879 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
9882 strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
9885 /* Output rtl to increment the profiler label LABELNO
9886 for profiling a function entry. */
9889 sparc_profile_hook (int labelno
)
9894 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
9895 if (NO_PROFILE_COUNTERS
)
9897 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 0);
9901 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
9902 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
9903 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
9907 #ifdef TARGET_SOLARIS
9908 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
9911 sparc_solaris_elf_asm_named_section (const char *name
, unsigned int flags
,
9912 tree decl ATTRIBUTE_UNUSED
)
9914 if (HAVE_COMDAT_GROUP
&& flags
& SECTION_LINKONCE
)
9916 solaris_elf_asm_comdat_section (name
, flags
, decl
);
9920 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
9922 if (!(flags
& SECTION_DEBUG
))
9923 fputs (",#alloc", asm_out_file
);
9924 if (flags
& SECTION_WRITE
)
9925 fputs (",#write", asm_out_file
);
9926 if (flags
& SECTION_TLS
)
9927 fputs (",#tls", asm_out_file
);
9928 if (flags
& SECTION_CODE
)
9929 fputs (",#execinstr", asm_out_file
);
9931 /* Sun as only supports #nobits/#progbits since Solaris 10. */
9932 if (HAVE_AS_SPARC_NOBITS
)
9934 if (flags
& SECTION_BSS
)
9935 fputs (",#nobits", asm_out_file
);
9937 fputs (",#progbits", asm_out_file
);
9940 fputc ('\n', asm_out_file
);
9942 #endif /* TARGET_SOLARIS */
9944 /* We do not allow indirect calls to be optimized into sibling calls.
9946 We cannot use sibling calls when delayed branches are disabled
9947 because they will likely require the call delay slot to be filled.
9949 Also, on SPARC 32-bit we cannot emit a sibling call when the
9950 current function returns a structure. This is because the "unimp
9951 after call" convention would cause the callee to return to the
9952 wrong place. The generic code already disallows cases where the
9953 function being called returns a structure.
9955 It may seem strange how this last case could occur. Usually there
9956 is code after the call which jumps to epilogue code which dumps the
9957 return value into the struct return area. That ought to invalidate
9958 the sibling call right? Well, in the C++ case we can end up passing
9959 the pointer to the struct return area to a constructor (which returns
9960 void) and then nothing else happens. Such a sibling call would look
9961 valid without the added check here.
9963 VxWorks PIC PLT entries require the global pointer to be initialized
9964 on entry. We therefore can't emit sibling calls to them. */
9966 sparc_function_ok_for_sibcall (tree decl
, tree exp ATTRIBUTE_UNUSED
)
9969 && flag_delayed_branch
9970 && (TARGET_ARCH64
|| ! cfun
->returns_struct
)
9971 && !(TARGET_VXWORKS_RTP
9973 && !targetm
.binds_local_p (decl
)));
9976 /* libfunc renaming. */
9979 sparc_init_libfuncs (void)
9983 /* Use the subroutines that Sun's library provides for integer
9984 multiply and divide. The `*' prevents an underscore from
9985 being prepended by the compiler. .umul is a little faster
9987 set_optab_libfunc (smul_optab
, SImode
, "*.umul");
9988 set_optab_libfunc (sdiv_optab
, SImode
, "*.div");
9989 set_optab_libfunc (udiv_optab
, SImode
, "*.udiv");
9990 set_optab_libfunc (smod_optab
, SImode
, "*.rem");
9991 set_optab_libfunc (umod_optab
, SImode
, "*.urem");
9993 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
9994 set_optab_libfunc (add_optab
, TFmode
, "_Q_add");
9995 set_optab_libfunc (sub_optab
, TFmode
, "_Q_sub");
9996 set_optab_libfunc (neg_optab
, TFmode
, "_Q_neg");
9997 set_optab_libfunc (smul_optab
, TFmode
, "_Q_mul");
9998 set_optab_libfunc (sdiv_optab
, TFmode
, "_Q_div");
10000 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
10001 is because with soft-float, the SFmode and DFmode sqrt
10002 instructions will be absent, and the compiler will notice and
10003 try to use the TFmode sqrt instruction for calls to the
10004 builtin function sqrt, but this fails. */
10006 set_optab_libfunc (sqrt_optab
, TFmode
, "_Q_sqrt");
10008 set_optab_libfunc (eq_optab
, TFmode
, "_Q_feq");
10009 set_optab_libfunc (ne_optab
, TFmode
, "_Q_fne");
10010 set_optab_libfunc (gt_optab
, TFmode
, "_Q_fgt");
10011 set_optab_libfunc (ge_optab
, TFmode
, "_Q_fge");
10012 set_optab_libfunc (lt_optab
, TFmode
, "_Q_flt");
10013 set_optab_libfunc (le_optab
, TFmode
, "_Q_fle");
10015 set_conv_libfunc (sext_optab
, TFmode
, SFmode
, "_Q_stoq");
10016 set_conv_libfunc (sext_optab
, TFmode
, DFmode
, "_Q_dtoq");
10017 set_conv_libfunc (trunc_optab
, SFmode
, TFmode
, "_Q_qtos");
10018 set_conv_libfunc (trunc_optab
, DFmode
, TFmode
, "_Q_qtod");
10020 set_conv_libfunc (sfix_optab
, SImode
, TFmode
, "_Q_qtoi");
10021 set_conv_libfunc (ufix_optab
, SImode
, TFmode
, "_Q_qtou");
10022 set_conv_libfunc (sfloat_optab
, TFmode
, SImode
, "_Q_itoq");
10023 set_conv_libfunc (ufloat_optab
, TFmode
, SImode
, "_Q_utoq");
10025 if (DITF_CONVERSION_LIBFUNCS
)
10027 set_conv_libfunc (sfix_optab
, DImode
, TFmode
, "_Q_qtoll");
10028 set_conv_libfunc (ufix_optab
, DImode
, TFmode
, "_Q_qtoull");
10029 set_conv_libfunc (sfloat_optab
, TFmode
, DImode
, "_Q_lltoq");
10030 set_conv_libfunc (ufloat_optab
, TFmode
, DImode
, "_Q_ulltoq");
10033 if (SUN_CONVERSION_LIBFUNCS
)
10035 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
10036 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
10037 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
10038 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
10043 /* In the SPARC 64bit ABI, SImode multiply and divide functions
10044 do not exist in the library. Make sure the compiler does not
10045 emit calls to them by accident. (It should always use the
10046 hardware instructions.) */
10047 set_optab_libfunc (smul_optab
, SImode
, 0);
10048 set_optab_libfunc (sdiv_optab
, SImode
, 0);
10049 set_optab_libfunc (udiv_optab
, SImode
, 0);
10050 set_optab_libfunc (smod_optab
, SImode
, 0);
10051 set_optab_libfunc (umod_optab
, SImode
, 0);
10053 if (SUN_INTEGER_MULTIPLY_64
)
10055 set_optab_libfunc (smul_optab
, DImode
, "__mul64");
10056 set_optab_libfunc (sdiv_optab
, DImode
, "__div64");
10057 set_optab_libfunc (udiv_optab
, DImode
, "__udiv64");
10058 set_optab_libfunc (smod_optab
, DImode
, "__rem64");
10059 set_optab_libfunc (umod_optab
, DImode
, "__urem64");
10062 if (SUN_CONVERSION_LIBFUNCS
)
10064 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftol");
10065 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoul");
10066 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtol");
10067 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoul");
10072 /* SPARC builtins. */
10073 enum sparc_builtins
10075 /* FPU builtins. */
10076 SPARC_BUILTIN_LDFSR
,
10077 SPARC_BUILTIN_STFSR
,
10079 /* VIS 1.0 builtins. */
10080 SPARC_BUILTIN_FPACK16
,
10081 SPARC_BUILTIN_FPACK32
,
10082 SPARC_BUILTIN_FPACKFIX
,
10083 SPARC_BUILTIN_FEXPAND
,
10084 SPARC_BUILTIN_FPMERGE
,
10085 SPARC_BUILTIN_FMUL8X16
,
10086 SPARC_BUILTIN_FMUL8X16AU
,
10087 SPARC_BUILTIN_FMUL8X16AL
,
10088 SPARC_BUILTIN_FMUL8SUX16
,
10089 SPARC_BUILTIN_FMUL8ULX16
,
10090 SPARC_BUILTIN_FMULD8SUX16
,
10091 SPARC_BUILTIN_FMULD8ULX16
,
10092 SPARC_BUILTIN_FALIGNDATAV4HI
,
10093 SPARC_BUILTIN_FALIGNDATAV8QI
,
10094 SPARC_BUILTIN_FALIGNDATAV2SI
,
10095 SPARC_BUILTIN_FALIGNDATADI
,
10096 SPARC_BUILTIN_WRGSR
,
10097 SPARC_BUILTIN_RDGSR
,
10098 SPARC_BUILTIN_ALIGNADDR
,
10099 SPARC_BUILTIN_ALIGNADDRL
,
10100 SPARC_BUILTIN_PDIST
,
10101 SPARC_BUILTIN_EDGE8
,
10102 SPARC_BUILTIN_EDGE8L
,
10103 SPARC_BUILTIN_EDGE16
,
10104 SPARC_BUILTIN_EDGE16L
,
10105 SPARC_BUILTIN_EDGE32
,
10106 SPARC_BUILTIN_EDGE32L
,
10107 SPARC_BUILTIN_FCMPLE16
,
10108 SPARC_BUILTIN_FCMPLE32
,
10109 SPARC_BUILTIN_FCMPNE16
,
10110 SPARC_BUILTIN_FCMPNE32
,
10111 SPARC_BUILTIN_FCMPGT16
,
10112 SPARC_BUILTIN_FCMPGT32
,
10113 SPARC_BUILTIN_FCMPEQ16
,
10114 SPARC_BUILTIN_FCMPEQ32
,
10115 SPARC_BUILTIN_FPADD16
,
10116 SPARC_BUILTIN_FPADD16S
,
10117 SPARC_BUILTIN_FPADD32
,
10118 SPARC_BUILTIN_FPADD32S
,
10119 SPARC_BUILTIN_FPSUB16
,
10120 SPARC_BUILTIN_FPSUB16S
,
10121 SPARC_BUILTIN_FPSUB32
,
10122 SPARC_BUILTIN_FPSUB32S
,
10123 SPARC_BUILTIN_ARRAY8
,
10124 SPARC_BUILTIN_ARRAY16
,
10125 SPARC_BUILTIN_ARRAY32
,
10127 /* VIS 2.0 builtins. */
10128 SPARC_BUILTIN_EDGE8N
,
10129 SPARC_BUILTIN_EDGE8LN
,
10130 SPARC_BUILTIN_EDGE16N
,
10131 SPARC_BUILTIN_EDGE16LN
,
10132 SPARC_BUILTIN_EDGE32N
,
10133 SPARC_BUILTIN_EDGE32LN
,
10134 SPARC_BUILTIN_BMASK
,
10135 SPARC_BUILTIN_BSHUFFLEV4HI
,
10136 SPARC_BUILTIN_BSHUFFLEV8QI
,
10137 SPARC_BUILTIN_BSHUFFLEV2SI
,
10138 SPARC_BUILTIN_BSHUFFLEDI
,
10140 /* VIS 3.0 builtins. */
10141 SPARC_BUILTIN_CMASK8
,
10142 SPARC_BUILTIN_CMASK16
,
10143 SPARC_BUILTIN_CMASK32
,
10144 SPARC_BUILTIN_FCHKSM16
,
10145 SPARC_BUILTIN_FSLL16
,
10146 SPARC_BUILTIN_FSLAS16
,
10147 SPARC_BUILTIN_FSRL16
,
10148 SPARC_BUILTIN_FSRA16
,
10149 SPARC_BUILTIN_FSLL32
,
10150 SPARC_BUILTIN_FSLAS32
,
10151 SPARC_BUILTIN_FSRL32
,
10152 SPARC_BUILTIN_FSRA32
,
10153 SPARC_BUILTIN_PDISTN
,
10154 SPARC_BUILTIN_FMEAN16
,
10155 SPARC_BUILTIN_FPADD64
,
10156 SPARC_BUILTIN_FPSUB64
,
10157 SPARC_BUILTIN_FPADDS16
,
10158 SPARC_BUILTIN_FPADDS16S
,
10159 SPARC_BUILTIN_FPSUBS16
,
10160 SPARC_BUILTIN_FPSUBS16S
,
10161 SPARC_BUILTIN_FPADDS32
,
10162 SPARC_BUILTIN_FPADDS32S
,
10163 SPARC_BUILTIN_FPSUBS32
,
10164 SPARC_BUILTIN_FPSUBS32S
,
10165 SPARC_BUILTIN_FUCMPLE8
,
10166 SPARC_BUILTIN_FUCMPNE8
,
10167 SPARC_BUILTIN_FUCMPGT8
,
10168 SPARC_BUILTIN_FUCMPEQ8
,
10169 SPARC_BUILTIN_FHADDS
,
10170 SPARC_BUILTIN_FHADDD
,
10171 SPARC_BUILTIN_FHSUBS
,
10172 SPARC_BUILTIN_FHSUBD
,
10173 SPARC_BUILTIN_FNHADDS
,
10174 SPARC_BUILTIN_FNHADDD
,
10175 SPARC_BUILTIN_UMULXHI
,
10176 SPARC_BUILTIN_XMULX
,
10177 SPARC_BUILTIN_XMULXHI
,
10182 static GTY (()) tree sparc_builtins
[(int) SPARC_BUILTIN_MAX
];
10183 static enum insn_code sparc_builtins_icode
[(int) SPARC_BUILTIN_MAX
];
10185 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the
10186 function decl or NULL_TREE if the builtin was not added. */
10189 def_builtin (const char *name
, enum insn_code icode
, enum sparc_builtins code
,
10193 = add_builtin_function (name
, type
, code
, BUILT_IN_MD
, NULL
, NULL_TREE
);
10197 sparc_builtins
[code
] = t
;
10198 sparc_builtins_icode
[code
] = icode
;
10204 /* Likewise, but also marks the function as "const". */
10207 def_builtin_const (const char *name
, enum insn_code icode
,
10208 enum sparc_builtins code
, tree type
)
10210 tree t
= def_builtin (name
, icode
, code
, type
);
10213 TREE_READONLY (t
) = 1;
10218 /* Implement the TARGET_INIT_BUILTINS target hook.
10219 Create builtin functions for special SPARC instructions. */
10222 sparc_init_builtins (void)
10225 sparc_fpu_init_builtins ();
10228 sparc_vis_init_builtins ();
10231 /* Create builtin functions for FPU instructions. */
10234 sparc_fpu_init_builtins (void)
10237 = build_function_type_list (void_type_node
,
10238 build_pointer_type (unsigned_type_node
), 0);
10239 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr
,
10240 SPARC_BUILTIN_LDFSR
, ftype
);
10241 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr
,
10242 SPARC_BUILTIN_STFSR
, ftype
);
10245 /* Create builtin functions for VIS instructions. */
10248 sparc_vis_init_builtins (void)
10250 tree v4qi
= build_vector_type (unsigned_intQI_type_node
, 4);
10251 tree v8qi
= build_vector_type (unsigned_intQI_type_node
, 8);
10252 tree v4hi
= build_vector_type (intHI_type_node
, 4);
10253 tree v2hi
= build_vector_type (intHI_type_node
, 2);
10254 tree v2si
= build_vector_type (intSI_type_node
, 2);
10255 tree v1si
= build_vector_type (intSI_type_node
, 1);
10257 tree v4qi_ftype_v4hi
= build_function_type_list (v4qi
, v4hi
, 0);
10258 tree v8qi_ftype_v2si_v8qi
= build_function_type_list (v8qi
, v2si
, v8qi
, 0);
10259 tree v2hi_ftype_v2si
= build_function_type_list (v2hi
, v2si
, 0);
10260 tree v4hi_ftype_v4qi
= build_function_type_list (v4hi
, v4qi
, 0);
10261 tree v8qi_ftype_v4qi_v4qi
= build_function_type_list (v8qi
, v4qi
, v4qi
, 0);
10262 tree v4hi_ftype_v4qi_v4hi
= build_function_type_list (v4hi
, v4qi
, v4hi
, 0);
10263 tree v4hi_ftype_v4qi_v2hi
= build_function_type_list (v4hi
, v4qi
, v2hi
, 0);
10264 tree v2si_ftype_v4qi_v2hi
= build_function_type_list (v2si
, v4qi
, v2hi
, 0);
10265 tree v4hi_ftype_v8qi_v4hi
= build_function_type_list (v4hi
, v8qi
, v4hi
, 0);
10266 tree v4hi_ftype_v4hi_v4hi
= build_function_type_list (v4hi
, v4hi
, v4hi
, 0);
10267 tree v2si_ftype_v2si_v2si
= build_function_type_list (v2si
, v2si
, v2si
, 0);
10268 tree v8qi_ftype_v8qi_v8qi
= build_function_type_list (v8qi
, v8qi
, v8qi
, 0);
10269 tree v2hi_ftype_v2hi_v2hi
= build_function_type_list (v2hi
, v2hi
, v2hi
, 0);
10270 tree v1si_ftype_v1si_v1si
= build_function_type_list (v1si
, v1si
, v1si
, 0);
10271 tree di_ftype_v8qi_v8qi_di
= build_function_type_list (intDI_type_node
,
10273 intDI_type_node
, 0);
10274 tree di_ftype_v8qi_v8qi
= build_function_type_list (intDI_type_node
,
10276 tree si_ftype_v8qi_v8qi
= build_function_type_list (intSI_type_node
,
10278 tree di_ftype_di_di
= build_function_type_list (intDI_type_node
,
10280 intDI_type_node
, 0);
10281 tree si_ftype_si_si
= build_function_type_list (intSI_type_node
,
10283 intSI_type_node
, 0);
10284 tree ptr_ftype_ptr_si
= build_function_type_list (ptr_type_node
,
10286 intSI_type_node
, 0);
10287 tree ptr_ftype_ptr_di
= build_function_type_list (ptr_type_node
,
10289 intDI_type_node
, 0);
10290 tree si_ftype_ptr_ptr
= build_function_type_list (intSI_type_node
,
10293 tree di_ftype_ptr_ptr
= build_function_type_list (intDI_type_node
,
10296 tree si_ftype_v4hi_v4hi
= build_function_type_list (intSI_type_node
,
10298 tree si_ftype_v2si_v2si
= build_function_type_list (intSI_type_node
,
10300 tree di_ftype_v4hi_v4hi
= build_function_type_list (intDI_type_node
,
10302 tree di_ftype_v2si_v2si
= build_function_type_list (intDI_type_node
,
10304 tree void_ftype_di
= build_function_type_list (void_type_node
,
10305 intDI_type_node
, 0);
10306 tree di_ftype_void
= build_function_type_list (intDI_type_node
,
10307 void_type_node
, 0);
10308 tree void_ftype_si
= build_function_type_list (void_type_node
,
10309 intSI_type_node
, 0);
10310 tree sf_ftype_sf_sf
= build_function_type_list (float_type_node
,
10312 float_type_node
, 0);
10313 tree df_ftype_df_df
= build_function_type_list (double_type_node
,
10315 double_type_node
, 0);
10317 /* Packing and expanding vectors. */
10318 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis
,
10319 SPARC_BUILTIN_FPACK16
, v4qi_ftype_v4hi
);
10320 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis
,
10321 SPARC_BUILTIN_FPACK32
, v8qi_ftype_v2si_v8qi
);
10322 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis
,
10323 SPARC_BUILTIN_FPACKFIX
, v2hi_ftype_v2si
);
10324 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis
,
10325 SPARC_BUILTIN_FEXPAND
, v4hi_ftype_v4qi
);
10326 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis
,
10327 SPARC_BUILTIN_FPMERGE
, v8qi_ftype_v4qi_v4qi
);
10329 /* Multiplications. */
10330 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis
,
10331 SPARC_BUILTIN_FMUL8X16
, v4hi_ftype_v4qi_v4hi
);
10332 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis
,
10333 SPARC_BUILTIN_FMUL8X16AU
, v4hi_ftype_v4qi_v2hi
);
10334 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis
,
10335 SPARC_BUILTIN_FMUL8X16AL
, v4hi_ftype_v4qi_v2hi
);
10336 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis
,
10337 SPARC_BUILTIN_FMUL8SUX16
, v4hi_ftype_v8qi_v4hi
);
10338 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis
,
10339 SPARC_BUILTIN_FMUL8ULX16
, v4hi_ftype_v8qi_v4hi
);
10340 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis
,
10341 SPARC_BUILTIN_FMULD8SUX16
, v2si_ftype_v4qi_v2hi
);
10342 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis
,
10343 SPARC_BUILTIN_FMULD8ULX16
, v2si_ftype_v4qi_v2hi
);
10345 /* Data aligning. */
10346 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis
,
10347 SPARC_BUILTIN_FALIGNDATAV4HI
, v4hi_ftype_v4hi_v4hi
);
10348 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis
,
10349 SPARC_BUILTIN_FALIGNDATAV8QI
, v8qi_ftype_v8qi_v8qi
);
10350 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis
,
10351 SPARC_BUILTIN_FALIGNDATAV2SI
, v2si_ftype_v2si_v2si
);
10352 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis
,
10353 SPARC_BUILTIN_FALIGNDATADI
, di_ftype_di_di
);
10355 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis
,
10356 SPARC_BUILTIN_WRGSR
, void_ftype_di
);
10357 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis
,
10358 SPARC_BUILTIN_RDGSR
, di_ftype_void
);
10362 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis
,
10363 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_di
);
10364 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis
,
10365 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_di
);
10369 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis
,
10370 SPARC_BUILTIN_ALIGNADDR
, ptr_ftype_ptr_si
);
10371 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis
,
10372 SPARC_BUILTIN_ALIGNADDRL
, ptr_ftype_ptr_si
);
10375 /* Pixel distance. */
10376 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis
,
10377 SPARC_BUILTIN_PDIST
, di_ftype_v8qi_v8qi_di
);
10379 /* Edge handling. */
10382 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis
,
10383 SPARC_BUILTIN_EDGE8
, di_ftype_ptr_ptr
);
10384 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis
,
10385 SPARC_BUILTIN_EDGE8L
, di_ftype_ptr_ptr
);
10386 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis
,
10387 SPARC_BUILTIN_EDGE16
, di_ftype_ptr_ptr
);
10388 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis
,
10389 SPARC_BUILTIN_EDGE16L
, di_ftype_ptr_ptr
);
10390 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis
,
10391 SPARC_BUILTIN_EDGE32
, di_ftype_ptr_ptr
);
10392 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis
,
10393 SPARC_BUILTIN_EDGE32L
, di_ftype_ptr_ptr
);
10397 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis
,
10398 SPARC_BUILTIN_EDGE8
, si_ftype_ptr_ptr
);
10399 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis
,
10400 SPARC_BUILTIN_EDGE8L
, si_ftype_ptr_ptr
);
10401 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis
,
10402 SPARC_BUILTIN_EDGE16
, si_ftype_ptr_ptr
);
10403 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis
,
10404 SPARC_BUILTIN_EDGE16L
, si_ftype_ptr_ptr
);
10405 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis
,
10406 SPARC_BUILTIN_EDGE32
, si_ftype_ptr_ptr
);
10407 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis
,
10408 SPARC_BUILTIN_EDGE32L
, si_ftype_ptr_ptr
);
10411 /* Pixel compare. */
10414 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis
,
10415 SPARC_BUILTIN_FCMPLE16
, di_ftype_v4hi_v4hi
);
10416 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis
,
10417 SPARC_BUILTIN_FCMPLE32
, di_ftype_v2si_v2si
);
10418 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis
,
10419 SPARC_BUILTIN_FCMPNE16
, di_ftype_v4hi_v4hi
);
10420 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis
,
10421 SPARC_BUILTIN_FCMPNE32
, di_ftype_v2si_v2si
);
10422 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis
,
10423 SPARC_BUILTIN_FCMPGT16
, di_ftype_v4hi_v4hi
);
10424 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis
,
10425 SPARC_BUILTIN_FCMPGT32
, di_ftype_v2si_v2si
);
10426 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis
,
10427 SPARC_BUILTIN_FCMPEQ16
, di_ftype_v4hi_v4hi
);
10428 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis
,
10429 SPARC_BUILTIN_FCMPEQ32
, di_ftype_v2si_v2si
);
10433 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis
,
10434 SPARC_BUILTIN_FCMPLE16
, si_ftype_v4hi_v4hi
);
10435 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis
,
10436 SPARC_BUILTIN_FCMPLE32
, si_ftype_v2si_v2si
);
10437 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis
,
10438 SPARC_BUILTIN_FCMPNE16
, si_ftype_v4hi_v4hi
);
10439 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis
,
10440 SPARC_BUILTIN_FCMPNE32
, si_ftype_v2si_v2si
);
10441 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis
,
10442 SPARC_BUILTIN_FCMPGT16
, si_ftype_v4hi_v4hi
);
10443 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis
,
10444 SPARC_BUILTIN_FCMPGT32
, si_ftype_v2si_v2si
);
10445 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis
,
10446 SPARC_BUILTIN_FCMPEQ16
, si_ftype_v4hi_v4hi
);
10447 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis
,
10448 SPARC_BUILTIN_FCMPEQ32
, si_ftype_v2si_v2si
);
10451 /* Addition and subtraction. */
10452 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3
,
10453 SPARC_BUILTIN_FPADD16
, v4hi_ftype_v4hi_v4hi
);
10454 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3
,
10455 SPARC_BUILTIN_FPADD16S
, v2hi_ftype_v2hi_v2hi
);
10456 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3
,
10457 SPARC_BUILTIN_FPADD32
, v2si_ftype_v2si_v2si
);
10458 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3
,
10459 SPARC_BUILTIN_FPADD32S
, v1si_ftype_v1si_v1si
);
10460 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3
,
10461 SPARC_BUILTIN_FPSUB16
, v4hi_ftype_v4hi_v4hi
);
10462 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3
,
10463 SPARC_BUILTIN_FPSUB16S
, v2hi_ftype_v2hi_v2hi
);
10464 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3
,
10465 SPARC_BUILTIN_FPSUB32
, v2si_ftype_v2si_v2si
);
10466 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3
,
10467 SPARC_BUILTIN_FPSUB32S
, v1si_ftype_v1si_v1si
);
10469 /* Three-dimensional array addressing. */
10472 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis
,
10473 SPARC_BUILTIN_ARRAY8
, di_ftype_di_di
);
10474 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis
,
10475 SPARC_BUILTIN_ARRAY16
, di_ftype_di_di
);
10476 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis
,
10477 SPARC_BUILTIN_ARRAY32
, di_ftype_di_di
);
10481 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis
,
10482 SPARC_BUILTIN_ARRAY8
, si_ftype_si_si
);
10483 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis
,
10484 SPARC_BUILTIN_ARRAY16
, si_ftype_si_si
);
10485 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis
,
10486 SPARC_BUILTIN_ARRAY32
, si_ftype_si_si
);
10491 /* Edge handling. */
10494 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis
,
10495 SPARC_BUILTIN_EDGE8N
, di_ftype_ptr_ptr
);
10496 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis
,
10497 SPARC_BUILTIN_EDGE8LN
, di_ftype_ptr_ptr
);
10498 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis
,
10499 SPARC_BUILTIN_EDGE16N
, di_ftype_ptr_ptr
);
10500 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis
,
10501 SPARC_BUILTIN_EDGE16LN
, di_ftype_ptr_ptr
);
10502 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis
,
10503 SPARC_BUILTIN_EDGE32N
, di_ftype_ptr_ptr
);
10504 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis
,
10505 SPARC_BUILTIN_EDGE32LN
, di_ftype_ptr_ptr
);
10509 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis
,
10510 SPARC_BUILTIN_EDGE8N
, si_ftype_ptr_ptr
);
10511 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis
,
10512 SPARC_BUILTIN_EDGE8LN
, si_ftype_ptr_ptr
);
10513 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis
,
10514 SPARC_BUILTIN_EDGE16N
, si_ftype_ptr_ptr
);
10515 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis
,
10516 SPARC_BUILTIN_EDGE16LN
, si_ftype_ptr_ptr
);
10517 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis
,
10518 SPARC_BUILTIN_EDGE32N
, si_ftype_ptr_ptr
);
10519 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis
,
10520 SPARC_BUILTIN_EDGE32LN
, si_ftype_ptr_ptr
);
10523 /* Byte mask and shuffle. */
10525 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis
,
10526 SPARC_BUILTIN_BMASK
, di_ftype_di_di
);
10528 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis
,
10529 SPARC_BUILTIN_BMASK
, si_ftype_si_si
);
10530 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis
,
10531 SPARC_BUILTIN_BSHUFFLEV4HI
, v4hi_ftype_v4hi_v4hi
);
10532 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis
,
10533 SPARC_BUILTIN_BSHUFFLEV8QI
, v8qi_ftype_v8qi_v8qi
);
10534 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis
,
10535 SPARC_BUILTIN_BSHUFFLEV2SI
, v2si_ftype_v2si_v2si
);
10536 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis
,
10537 SPARC_BUILTIN_BSHUFFLEDI
, di_ftype_di_di
);
10544 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis
,
10545 SPARC_BUILTIN_CMASK8
, void_ftype_di
);
10546 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis
,
10547 SPARC_BUILTIN_CMASK16
, void_ftype_di
);
10548 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis
,
10549 SPARC_BUILTIN_CMASK32
, void_ftype_di
);
10553 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis
,
10554 SPARC_BUILTIN_CMASK8
, void_ftype_si
);
10555 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis
,
10556 SPARC_BUILTIN_CMASK16
, void_ftype_si
);
10557 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis
,
10558 SPARC_BUILTIN_CMASK32
, void_ftype_si
);
10561 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis
,
10562 SPARC_BUILTIN_FCHKSM16
, v4hi_ftype_v4hi_v4hi
);
10564 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3
,
10565 SPARC_BUILTIN_FSLL16
, v4hi_ftype_v4hi_v4hi
);
10566 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3
,
10567 SPARC_BUILTIN_FSLAS16
, v4hi_ftype_v4hi_v4hi
);
10568 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3
,
10569 SPARC_BUILTIN_FSRL16
, v4hi_ftype_v4hi_v4hi
);
10570 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3
,
10571 SPARC_BUILTIN_FSRA16
, v4hi_ftype_v4hi_v4hi
);
10572 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3
,
10573 SPARC_BUILTIN_FSLL32
, v2si_ftype_v2si_v2si
);
10574 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3
,
10575 SPARC_BUILTIN_FSLAS32
, v2si_ftype_v2si_v2si
);
10576 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3
,
10577 SPARC_BUILTIN_FSRL32
, v2si_ftype_v2si_v2si
);
10578 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3
,
10579 SPARC_BUILTIN_FSRA32
, v2si_ftype_v2si_v2si
);
10582 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis
,
10583 SPARC_BUILTIN_PDISTN
, di_ftype_v8qi_v8qi
);
10585 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis
,
10586 SPARC_BUILTIN_PDISTN
, si_ftype_v8qi_v8qi
);
10588 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis
,
10589 SPARC_BUILTIN_FMEAN16
, v4hi_ftype_v4hi_v4hi
);
10590 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis
,
10591 SPARC_BUILTIN_FPADD64
, di_ftype_di_di
);
10592 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis
,
10593 SPARC_BUILTIN_FPSUB64
, di_ftype_di_di
);
10595 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3
,
10596 SPARC_BUILTIN_FPADDS16
, v4hi_ftype_v4hi_v4hi
);
10597 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3
,
10598 SPARC_BUILTIN_FPADDS16S
, v2hi_ftype_v2hi_v2hi
);
10599 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3
,
10600 SPARC_BUILTIN_FPSUBS16
, v4hi_ftype_v4hi_v4hi
);
10601 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3
,
10602 SPARC_BUILTIN_FPSUBS16S
, v2hi_ftype_v2hi_v2hi
);
10603 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3
,
10604 SPARC_BUILTIN_FPADDS32
, v2si_ftype_v2si_v2si
);
10605 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3
,
10606 SPARC_BUILTIN_FPADDS32S
, v1si_ftype_v1si_v1si
);
10607 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3
,
10608 SPARC_BUILTIN_FPSUBS32
, v2si_ftype_v2si_v2si
);
10609 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3
,
10610 SPARC_BUILTIN_FPSUBS32S
, v1si_ftype_v1si_v1si
);
10614 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis
,
10615 SPARC_BUILTIN_FUCMPLE8
, di_ftype_v8qi_v8qi
);
10616 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis
,
10617 SPARC_BUILTIN_FUCMPNE8
, di_ftype_v8qi_v8qi
);
10618 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis
,
10619 SPARC_BUILTIN_FUCMPGT8
, di_ftype_v8qi_v8qi
);
10620 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis
,
10621 SPARC_BUILTIN_FUCMPEQ8
, di_ftype_v8qi_v8qi
);
10625 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis
,
10626 SPARC_BUILTIN_FUCMPLE8
, si_ftype_v8qi_v8qi
);
10627 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis
,
10628 SPARC_BUILTIN_FUCMPNE8
, si_ftype_v8qi_v8qi
);
10629 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis
,
10630 SPARC_BUILTIN_FUCMPGT8
, si_ftype_v8qi_v8qi
);
10631 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis
,
10632 SPARC_BUILTIN_FUCMPEQ8
, si_ftype_v8qi_v8qi
);
10635 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis
,
10636 SPARC_BUILTIN_FHADDS
, sf_ftype_sf_sf
);
10637 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis
,
10638 SPARC_BUILTIN_FHADDD
, df_ftype_df_df
);
10639 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis
,
10640 SPARC_BUILTIN_FHSUBS
, sf_ftype_sf_sf
);
10641 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis
,
10642 SPARC_BUILTIN_FHSUBD
, df_ftype_df_df
);
10643 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis
,
10644 SPARC_BUILTIN_FNHADDS
, sf_ftype_sf_sf
);
10645 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis
,
10646 SPARC_BUILTIN_FNHADDD
, df_ftype_df_df
);
10648 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis
,
10649 SPARC_BUILTIN_UMULXHI
, di_ftype_di_di
);
10650 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis
,
10651 SPARC_BUILTIN_XMULX
, di_ftype_di_di
);
10652 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis
,
10653 SPARC_BUILTIN_XMULXHI
, di_ftype_di_di
);
10657 /* Implement TARGET_BUILTIN_DECL hook. */
10660 sparc_builtin_decl (unsigned code
, bool initialize_p ATTRIBUTE_UNUSED
)
10662 if (code
>= SPARC_BUILTIN_MAX
)
10663 return error_mark_node
;
10665 return sparc_builtins
[code
];
10668 /* Implemented TARGET_EXPAND_BUILTIN hook. */
10671 sparc_expand_builtin (tree exp
, rtx target
,
10672 rtx subtarget ATTRIBUTE_UNUSED
,
10673 enum machine_mode tmode ATTRIBUTE_UNUSED
,
10674 int ignore ATTRIBUTE_UNUSED
)
10676 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
10677 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10678 enum insn_code icode
= sparc_builtins_icode
[code
];
10679 bool nonvoid
= TREE_TYPE (TREE_TYPE (fndecl
)) != void_type_node
;
10680 call_expr_arg_iterator iter
;
10687 enum machine_mode tmode
= insn_data
[icode
].operand
[0].mode
;
10689 || GET_MODE (target
) != tmode
10690 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
10691 op
[0] = gen_reg_rtx (tmode
);
10696 FOR_EACH_CALL_EXPR_ARG (arg
, iter
, exp
)
10698 const struct insn_operand_data
*insn_op
;
10701 if (arg
== error_mark_node
)
10705 idx
= arg_count
- !nonvoid
;
10706 insn_op
= &insn_data
[icode
].operand
[idx
];
10707 op
[arg_count
] = expand_normal (arg
);
10709 if (code
== SPARC_BUILTIN_LDFSR
|| code
== SPARC_BUILTIN_STFSR
)
10711 if (!address_operand (op
[arg_count
], SImode
))
10713 op
[arg_count
] = convert_memory_address (Pmode
, op
[arg_count
]);
10714 op
[arg_count
] = copy_addr_to_reg (op
[arg_count
]);
10716 op
[arg_count
] = gen_rtx_MEM (SImode
, op
[arg_count
]);
10719 else if (insn_op
->mode
== V1DImode
10720 && GET_MODE (op
[arg_count
]) == DImode
)
10721 op
[arg_count
] = gen_lowpart (V1DImode
, op
[arg_count
]);
10723 else if (insn_op
->mode
== V1SImode
10724 && GET_MODE (op
[arg_count
]) == SImode
)
10725 op
[arg_count
] = gen_lowpart (V1SImode
, op
[arg_count
]);
10727 if (! (*insn_data
[icode
].operand
[idx
].predicate
) (op
[arg_count
],
10729 op
[arg_count
] = copy_to_mode_reg (insn_op
->mode
, op
[arg_count
]);
10735 pat
= GEN_FCN (icode
) (op
[0]);
10739 pat
= GEN_FCN (icode
) (op
[0], op
[1]);
10741 pat
= GEN_FCN (icode
) (op
[1]);
10744 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2]);
10747 pat
= GEN_FCN (icode
) (op
[0], op
[1], op
[2], op
[3]);
10750 gcc_unreachable ();
10758 return (nonvoid
? op
[0] : const0_rtx
);
10761 /* Return the upper 16 bits of the 8x16 multiplication. */
10764 sparc_vis_mul8x16 (int e8
, int e16
)
10766 return (e8
* e16
+ 128) / 256;
10769 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put
10770 the result into the array N_ELTS, whose elements are of INNER_TYPE. */
10773 sparc_handle_vis_mul8x16 (tree
*n_elts
, enum sparc_builtins fncode
,
10774 tree inner_type
, tree cst0
, tree cst1
)
10776 unsigned i
, num
= VECTOR_CST_NELTS (cst0
);
10781 case SPARC_BUILTIN_FMUL8X16
:
10782 for (i
= 0; i
< num
; ++i
)
10785 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10786 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, i
)));
10787 n_elts
[i
] = build_int_cst (inner_type
, val
);
10791 case SPARC_BUILTIN_FMUL8X16AU
:
10792 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 0));
10794 for (i
= 0; i
< num
; ++i
)
10797 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10799 n_elts
[i
] = build_int_cst (inner_type
, val
);
10803 case SPARC_BUILTIN_FMUL8X16AL
:
10804 scale
= TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1
, 1));
10806 for (i
= 0; i
< num
; ++i
)
10809 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0
, i
)),
10811 n_elts
[i
] = build_int_cst (inner_type
, val
);
10816 gcc_unreachable ();
10820 /* Implement TARGET_FOLD_BUILTIN hook.
10822 Fold builtin functions for SPARC intrinsics. If IGNORE is true the
10823 result of the function call is ignored. NULL_TREE is returned if the
10824 function could not be folded. */
10827 sparc_fold_builtin (tree fndecl
, int n_args ATTRIBUTE_UNUSED
,
10828 tree
*args
, bool ignore
)
10830 enum sparc_builtins code
= (enum sparc_builtins
) DECL_FUNCTION_CODE (fndecl
);
10831 tree rtype
= TREE_TYPE (TREE_TYPE (fndecl
));
10832 tree arg0
, arg1
, arg2
;
10837 case SPARC_BUILTIN_LDFSR
:
10838 case SPARC_BUILTIN_STFSR
:
10839 case SPARC_BUILTIN_ALIGNADDR
:
10840 case SPARC_BUILTIN_WRGSR
:
10841 case SPARC_BUILTIN_BMASK
:
10842 case SPARC_BUILTIN_CMASK8
:
10843 case SPARC_BUILTIN_CMASK16
:
10844 case SPARC_BUILTIN_CMASK32
:
10848 return build_zero_cst (rtype
);
10853 case SPARC_BUILTIN_FEXPAND
:
10857 if (TREE_CODE (arg0
) == VECTOR_CST
)
10859 tree inner_type
= TREE_TYPE (rtype
);
10863 n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10864 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10865 n_elts
[i
] = build_int_cst (inner_type
,
10867 (VECTOR_CST_ELT (arg0
, i
)) << 4);
10868 return build_vector (rtype
, n_elts
);
10872 case SPARC_BUILTIN_FMUL8X16
:
10873 case SPARC_BUILTIN_FMUL8X16AU
:
10874 case SPARC_BUILTIN_FMUL8X16AL
:
10880 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10882 tree inner_type
= TREE_TYPE (rtype
);
10883 tree
*n_elts
= XALLOCAVEC (tree
, VECTOR_CST_NELTS (arg0
));
10884 sparc_handle_vis_mul8x16 (n_elts
, code
, inner_type
, arg0
, arg1
);
10885 return build_vector (rtype
, n_elts
);
10889 case SPARC_BUILTIN_FPMERGE
:
10895 if (TREE_CODE (arg0
) == VECTOR_CST
&& TREE_CODE (arg1
) == VECTOR_CST
)
10897 tree
*n_elts
= XALLOCAVEC (tree
, 2 * VECTOR_CST_NELTS (arg0
));
10899 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10901 n_elts
[2*i
] = VECTOR_CST_ELT (arg0
, i
);
10902 n_elts
[2*i
+1] = VECTOR_CST_ELT (arg1
, i
);
10905 return build_vector (rtype
, n_elts
);
10909 case SPARC_BUILTIN_PDIST
:
10910 case SPARC_BUILTIN_PDISTN
:
10915 if (code
== SPARC_BUILTIN_PDIST
)
10921 arg2
= integer_zero_node
;
10923 if (TREE_CODE (arg0
) == VECTOR_CST
10924 && TREE_CODE (arg1
) == VECTOR_CST
10925 && TREE_CODE (arg2
) == INTEGER_CST
)
10927 bool overflow
= false;
10928 widest_int result
= wi::to_widest (arg2
);
10932 for (i
= 0; i
< VECTOR_CST_NELTS (arg0
); ++i
)
10934 tree e0
= VECTOR_CST_ELT (arg0
, i
);
10935 tree e1
= VECTOR_CST_ELT (arg1
, i
);
10937 bool neg1_ovf
, neg2_ovf
, add1_ovf
, add2_ovf
;
10939 tmp
= wi::neg (wi::to_widest (e1
), &neg1_ovf
);
10940 tmp
= wi::add (wi::to_widest (e0
), tmp
, SIGNED
, &add1_ovf
);
10941 if (wi::neg_p (tmp
))
10942 tmp
= wi::neg (tmp
, &neg2_ovf
);
10945 result
= wi::add (result
, tmp
, SIGNED
, &add2_ovf
);
10946 overflow
|= neg1_ovf
| neg2_ovf
| add1_ovf
| add2_ovf
;
10949 gcc_assert (!overflow
);
10951 return wide_int_to_tree (rtype
, result
);
10961 /* ??? This duplicates information provided to the compiler by the
10962 ??? scheduler description. Some day, teach genautomata to output
10963 ??? the latencies and then CSE will just use that. */
10966 sparc_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
10967 int *total
, bool speed ATTRIBUTE_UNUSED
)
10969 enum machine_mode mode
= GET_MODE (x
);
10970 bool float_mode_p
= FLOAT_MODE_P (mode
);
10975 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
10993 if (GET_MODE (x
) == VOIDmode
10994 && ((CONST_DOUBLE_HIGH (x
) == 0
10995 && CONST_DOUBLE_LOW (x
) < 0x1000)
10996 || (CONST_DOUBLE_HIGH (x
) == -1
10997 && CONST_DOUBLE_LOW (x
) < 0
10998 && CONST_DOUBLE_LOW (x
) >= -0x1000)))
11005 /* If outer-code was a sign or zero extension, a cost
11006 of COSTS_N_INSNS (1) was already added in. This is
11007 why we are subtracting it back out. */
11008 if (outer_code
== ZERO_EXTEND
)
11010 *total
= sparc_costs
->int_zload
- COSTS_N_INSNS (1);
11012 else if (outer_code
== SIGN_EXTEND
)
11014 *total
= sparc_costs
->int_sload
- COSTS_N_INSNS (1);
11016 else if (float_mode_p
)
11018 *total
= sparc_costs
->float_load
;
11022 *total
= sparc_costs
->int_load
;
11030 *total
= sparc_costs
->float_plusminus
;
11032 *total
= COSTS_N_INSNS (1);
11039 gcc_assert (float_mode_p
);
11040 *total
= sparc_costs
->float_mul
;
11043 if (GET_CODE (sub
) == NEG
)
11044 sub
= XEXP (sub
, 0);
11045 *total
+= rtx_cost (sub
, FMA
, 0, speed
);
11048 if (GET_CODE (sub
) == NEG
)
11049 sub
= XEXP (sub
, 0);
11050 *total
+= rtx_cost (sub
, FMA
, 2, speed
);
11056 *total
= sparc_costs
->float_mul
;
11057 else if (! TARGET_HARD_MUL
)
11058 *total
= COSTS_N_INSNS (25);
11064 if (sparc_costs
->int_mul_bit_factor
)
11068 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
11070 unsigned HOST_WIDE_INT value
= INTVAL (XEXP (x
, 1));
11071 for (nbits
= 0; value
!= 0; value
&= value
- 1)
11074 else if (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
11075 && GET_MODE (XEXP (x
, 1)) == VOIDmode
)
11077 rtx x1
= XEXP (x
, 1);
11078 unsigned HOST_WIDE_INT value1
= CONST_DOUBLE_LOW (x1
);
11079 unsigned HOST_WIDE_INT value2
= CONST_DOUBLE_HIGH (x1
);
11081 for (nbits
= 0; value1
!= 0; value1
&= value1
- 1)
11083 for (; value2
!= 0; value2
&= value2
- 1)
11091 bit_cost
= (nbits
- 3) / sparc_costs
->int_mul_bit_factor
;
11092 bit_cost
= COSTS_N_INSNS (bit_cost
);
11095 if (mode
== DImode
)
11096 *total
= sparc_costs
->int_mulX
+ bit_cost
;
11098 *total
= sparc_costs
->int_mul
+ bit_cost
;
11105 *total
= COSTS_N_INSNS (1) + sparc_costs
->shift_penalty
;
11114 if (mode
== DFmode
)
11115 *total
= sparc_costs
->float_div_df
;
11117 *total
= sparc_costs
->float_div_sf
;
11121 if (mode
== DImode
)
11122 *total
= sparc_costs
->int_divX
;
11124 *total
= sparc_costs
->int_div
;
11129 if (! float_mode_p
)
11131 *total
= COSTS_N_INSNS (1);
11138 case UNSIGNED_FLOAT
:
11142 case FLOAT_TRUNCATE
:
11143 *total
= sparc_costs
->float_move
;
11147 if (mode
== DFmode
)
11148 *total
= sparc_costs
->float_sqrt_df
;
11150 *total
= sparc_costs
->float_sqrt_sf
;
11155 *total
= sparc_costs
->float_cmp
;
11157 *total
= COSTS_N_INSNS (1);
11162 *total
= sparc_costs
->float_cmove
;
11164 *total
= sparc_costs
->int_cmove
;
11168 /* Handle the NAND vector patterns. */
11169 if (sparc_vector_mode_supported_p (GET_MODE (x
))
11170 && GET_CODE (XEXP (x
, 0)) == NOT
11171 && GET_CODE (XEXP (x
, 1)) == NOT
)
11173 *total
= COSTS_N_INSNS (1);
11184 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */
11187 general_or_i64_p (reg_class_t rclass
)
11189 return (rclass
== GENERAL_REGS
|| rclass
== I64_REGS
);
11192 /* Implement TARGET_REGISTER_MOVE_COST. */
11195 sparc_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
11196 reg_class_t from
, reg_class_t to
)
11198 bool need_memory
= false;
11200 if (from
== FPCC_REGS
|| to
== FPCC_REGS
)
11201 need_memory
= true;
11202 else if ((FP_REG_CLASS_P (from
) && general_or_i64_p (to
))
11203 || (general_or_i64_p (from
) && FP_REG_CLASS_P (to
)))
11207 int size
= GET_MODE_SIZE (mode
);
11208 if (size
== 8 || size
== 4)
11210 if (! TARGET_ARCH32
|| size
== 4)
11216 need_memory
= true;
11221 if (sparc_cpu
== PROCESSOR_ULTRASPARC
11222 || sparc_cpu
== PROCESSOR_ULTRASPARC3
11223 || sparc_cpu
== PROCESSOR_NIAGARA
11224 || sparc_cpu
== PROCESSOR_NIAGARA2
11225 || sparc_cpu
== PROCESSOR_NIAGARA3
11226 || sparc_cpu
== PROCESSOR_NIAGARA4
)
11235 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2.
11236 This is achieved by means of a manual dynamic stack space allocation in
11237 the current frame. We make the assumption that SEQ doesn't contain any
11238 function calls, with the possible exception of calls to the GOT helper. */
11241 emit_and_preserve (rtx seq
, rtx reg
, rtx reg2
)
11243 /* We must preserve the lowest 16 words for the register save area. */
11244 HOST_WIDE_INT offset
= 16*UNITS_PER_WORD
;
11245 /* We really need only 2 words of fresh stack space. */
11246 HOST_WIDE_INT size
= SPARC_STACK_ALIGN (offset
+ 2*UNITS_PER_WORD
);
11249 = gen_rtx_MEM (word_mode
, plus_constant (Pmode
, stack_pointer_rtx
,
11250 SPARC_STACK_BIAS
+ offset
));
11252 emit_insn (gen_stack_pointer_inc (GEN_INT (-size
)));
11253 emit_insn (gen_rtx_SET (VOIDmode
, slot
, reg
));
11255 emit_insn (gen_rtx_SET (VOIDmode
,
11256 adjust_address (slot
, word_mode
, UNITS_PER_WORD
),
11260 emit_insn (gen_rtx_SET (VOIDmode
,
11262 adjust_address (slot
, word_mode
, UNITS_PER_WORD
)));
11263 emit_insn (gen_rtx_SET (VOIDmode
, reg
, slot
));
11264 emit_insn (gen_stack_pointer_inc (GEN_INT (size
)));
11267 /* Output the assembler code for a thunk function. THUNK_DECL is the
11268 declaration for the thunk function itself, FUNCTION is the decl for
11269 the target function. DELTA is an immediate constant offset to be
11270 added to THIS. If VCALL_OFFSET is nonzero, the word at address
11271 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */
11274 sparc_output_mi_thunk (FILE *file
, tree thunk_fndecl ATTRIBUTE_UNUSED
,
11275 HOST_WIDE_INT delta
, HOST_WIDE_INT vcall_offset
,
11278 rtx this_rtx
, funexp
;
11280 unsigned int int_arg_first
;
11282 reload_completed
= 1;
11283 epilogue_completed
= 1;
11285 emit_note (NOTE_INSN_PROLOGUE_END
);
11289 sparc_leaf_function_p
= 1;
11291 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11293 else if (flag_delayed_branch
)
11295 /* We will emit a regular sibcall below, so we need to instruct
11296 output_sibcall that we are in a leaf function. */
11297 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 1;
11299 /* This will cause final.c to invoke leaf_renumber_regs so we
11300 must behave as if we were in a not-yet-leafified function. */
11301 int_arg_first
= SPARC_INCOMING_INT_ARG_FIRST
;
11305 /* We will emit the sibcall manually below, so we will need to
11306 manually spill non-leaf registers. */
11307 sparc_leaf_function_p
= crtl
->uses_only_leaf_regs
= 0;
11309 /* We really are in a leaf function. */
11310 int_arg_first
= SPARC_OUTGOING_INT_ARG_FIRST
;
11313 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
11314 returns a structure, the structure return pointer is there instead. */
11316 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
11317 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
+ 1);
11319 this_rtx
= gen_rtx_REG (Pmode
, int_arg_first
);
11321 /* Add DELTA. When possible use a plain add, otherwise load it into
11322 a register first. */
11325 rtx delta_rtx
= GEN_INT (delta
);
11327 if (! SPARC_SIMM13_P (delta
))
11329 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11330 emit_move_insn (scratch
, delta_rtx
);
11331 delta_rtx
= scratch
;
11334 /* THIS_RTX += DELTA. */
11335 emit_insn (gen_add2_insn (this_rtx
, delta_rtx
));
11338 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */
11341 rtx vcall_offset_rtx
= GEN_INT (vcall_offset
);
11342 rtx scratch
= gen_rtx_REG (Pmode
, 1);
11344 gcc_assert (vcall_offset
< 0);
11346 /* SCRATCH = *THIS_RTX. */
11347 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
, this_rtx
));
11349 /* Prepare for adding VCALL_OFFSET. The difficulty is that we
11350 may not have any available scratch register at this point. */
11351 if (SPARC_SIMM13_P (vcall_offset
))
11353 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */
11354 else if (! fixed_regs
[5]
11355 /* The below sequence is made up of at least 2 insns,
11356 while the default method may need only one. */
11357 && vcall_offset
< -8192)
11359 rtx scratch2
= gen_rtx_REG (Pmode
, 5);
11360 emit_move_insn (scratch2
, vcall_offset_rtx
);
11361 vcall_offset_rtx
= scratch2
;
11365 rtx increment
= GEN_INT (-4096);
11367 /* VCALL_OFFSET is a negative number whose typical range can be
11368 estimated as -32768..0 in 32-bit mode. In almost all cases
11369 it is therefore cheaper to emit multiple add insns than
11370 spilling and loading the constant into a register (at least
11372 while (! SPARC_SIMM13_P (vcall_offset
))
11374 emit_insn (gen_add2_insn (scratch
, increment
));
11375 vcall_offset
+= 4096;
11377 vcall_offset_rtx
= GEN_INT (vcall_offset
); /* cannot be 0 */
11380 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */
11381 emit_move_insn (scratch
, gen_rtx_MEM (Pmode
,
11382 gen_rtx_PLUS (Pmode
,
11384 vcall_offset_rtx
)));
11386 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */
11387 emit_insn (gen_add2_insn (this_rtx
, scratch
));
11390 /* Generate a tail call to the target function. */
11391 if (! TREE_USED (function
))
11393 assemble_external (function
);
11394 TREE_USED (function
) = 1;
11396 funexp
= XEXP (DECL_RTL (function
), 0);
11398 if (flag_delayed_branch
)
11400 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
11401 insn
= emit_call_insn (gen_sibcall (funexp
));
11402 SIBLING_CALL_P (insn
) = 1;
11406 /* The hoops we have to jump through in order to generate a sibcall
11407 without using delay slots... */
11408 rtx spill_reg
, seq
, scratch
= gen_rtx_REG (Pmode
, 1);
11412 spill_reg
= gen_rtx_REG (word_mode
, 15); /* %o7 */
11414 load_got_register (); /* clobbers %o7 */
11415 scratch
= sparc_legitimize_pic_address (funexp
, scratch
);
11416 seq
= get_insns ();
11418 emit_and_preserve (seq
, spill_reg
, pic_offset_table_rtx
);
11420 else if (TARGET_ARCH32
)
11422 emit_insn (gen_rtx_SET (VOIDmode
,
11424 gen_rtx_HIGH (SImode
, funexp
)));
11425 emit_insn (gen_rtx_SET (VOIDmode
,
11427 gen_rtx_LO_SUM (SImode
, scratch
, funexp
)));
11429 else /* TARGET_ARCH64 */
11431 switch (sparc_cmodel
)
11435 /* The destination can serve as a temporary. */
11436 sparc_emit_set_symbolic_const64 (scratch
, funexp
, scratch
);
11441 /* The destination cannot serve as a temporary. */
11442 spill_reg
= gen_rtx_REG (DImode
, 15); /* %o7 */
11444 sparc_emit_set_symbolic_const64 (scratch
, funexp
, spill_reg
);
11445 seq
= get_insns ();
11447 emit_and_preserve (seq
, spill_reg
, 0);
11451 gcc_unreachable ();
11455 emit_jump_insn (gen_indirect_jump (scratch
));
11460 /* Run just enough of rest_of_compilation to get the insns emitted.
11461 There's not really enough bulk here to make other passes such as
11462 instruction scheduling worth while. Note that use_thunk calls
11463 assemble_start_function and assemble_end_function. */
11464 insn
= get_insns ();
11465 shorten_branches (insn
);
11466 final_start_function (insn
, file
, 1);
11467 final (insn
, file
, 1);
11468 final_end_function ();
11470 reload_completed
= 0;
11471 epilogue_completed
= 0;
11474 /* Return true if sparc_output_mi_thunk would be able to output the
11475 assembler code for the thunk function specified by the arguments
11476 it is passed, and false otherwise. */
11478 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
11479 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
11480 HOST_WIDE_INT vcall_offset
,
11481 const_tree function ATTRIBUTE_UNUSED
)
11483 /* Bound the loop used in the default method above. */
11484 return (vcall_offset
>= -32768 || ! fixed_regs
[5]);
11487 /* How to allocate a 'struct machine_function'. */
11489 static struct machine_function
*
11490 sparc_init_machine_status (void)
11492 return ggc_cleared_alloc
<machine_function
> ();
11495 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
11496 We need to emit DTP-relative relocations. */
11499 sparc_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
11504 fputs ("\t.word\t%r_tls_dtpoff32(", file
);
11507 fputs ("\t.xword\t%r_tls_dtpoff64(", file
);
11510 gcc_unreachable ();
11512 output_addr_const (file
, x
);
11516 /* Do whatever processing is required at the end of a file. */
11519 sparc_file_end (void)
11521 /* If we need to emit the special GOT helper function, do so now. */
11522 if (got_helper_rtx
)
11524 const char *name
= XSTR (got_helper_rtx
, 0);
11525 const char *reg_name
= reg_names
[GLOBAL_OFFSET_TABLE_REGNUM
];
11526 #ifdef DWARF2_UNWIND_INFO
11530 if (USE_HIDDEN_LINKONCE
)
11532 tree decl
= build_decl (BUILTINS_LOCATION
, FUNCTION_DECL
,
11533 get_identifier (name
),
11534 build_function_type_list (void_type_node
,
11536 DECL_RESULT (decl
) = build_decl (BUILTINS_LOCATION
, RESULT_DECL
,
11537 NULL_TREE
, void_type_node
);
11538 TREE_PUBLIC (decl
) = 1;
11539 TREE_STATIC (decl
) = 1;
11540 make_decl_one_only (decl
, DECL_ASSEMBLER_NAME (decl
));
11541 DECL_VISIBILITY (decl
) = VISIBILITY_HIDDEN
;
11542 DECL_VISIBILITY_SPECIFIED (decl
) = 1;
11543 resolve_unique_section (decl
, 0, flag_function_sections
);
11544 allocate_struct_function (decl
, true);
11545 cfun
->is_thunk
= 1;
11546 current_function_decl
= decl
;
11547 init_varasm_status ();
11548 assemble_start_function (decl
, name
);
11552 const int align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
11553 switch_to_section (text_section
);
11555 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
11556 ASM_OUTPUT_LABEL (asm_out_file
, name
);
11559 #ifdef DWARF2_UNWIND_INFO
11560 do_cfi
= dwarf2out_do_cfi_asm ();
11562 fprintf (asm_out_file
, "\t.cfi_startproc\n");
11564 if (flag_delayed_branch
)
11565 fprintf (asm_out_file
, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n",
11566 reg_name
, reg_name
);
11568 fprintf (asm_out_file
, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n",
11569 reg_name
, reg_name
);
11570 #ifdef DWARF2_UNWIND_INFO
11572 fprintf (asm_out_file
, "\t.cfi_endproc\n");
11576 if (NEED_INDICATE_EXEC_STACK
)
11577 file_end_indicate_exec_stack ();
11579 #ifdef TARGET_SOLARIS
11580 solaris_file_end ();
11584 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
11585 /* Implement TARGET_MANGLE_TYPE. */
11587 static const char *
11588 sparc_mangle_type (const_tree type
)
11591 && TYPE_MAIN_VARIANT (type
) == long_double_type_node
11592 && TARGET_LONG_DOUBLE_128
)
11595 /* For all other types, use normal C++ mangling. */
11600 /* Expand a membar instruction for various use cases. Both the LOAD_STORE
11601 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where
11602 bit 0 indicates that X is true, and bit 1 indicates Y is true. */
11605 sparc_emit_membar_for_model (enum memmodel model
,
11606 int load_store
, int before_after
)
11608 /* Bits for the MEMBAR mmask field. */
11609 const int LoadLoad
= 1;
11610 const int StoreLoad
= 2;
11611 const int LoadStore
= 4;
11612 const int StoreStore
= 8;
11614 int mm
= 0, implied
= 0;
11616 switch (sparc_memory_model
)
11619 /* Sequential Consistency. All memory transactions are immediately
11620 visible in sequential execution order. No barriers needed. */
11621 implied
= LoadLoad
| StoreLoad
| LoadStore
| StoreStore
;
11625 /* Total Store Ordering: all memory transactions with store semantics
11626 are followed by an implied StoreStore. */
11627 implied
|= StoreStore
;
11629 /* If we're not looking for a raw barrer (before+after), then atomic
11630 operations get the benefit of being both load and store. */
11631 if (load_store
== 3 && before_after
== 1)
11632 implied
|= StoreLoad
;
11636 /* Partial Store Ordering: all memory transactions with load semantics
11637 are followed by an implied LoadLoad | LoadStore. */
11638 implied
|= LoadLoad
| LoadStore
;
11640 /* If we're not looking for a raw barrer (before+after), then atomic
11641 operations get the benefit of being both load and store. */
11642 if (load_store
== 3 && before_after
== 2)
11643 implied
|= StoreLoad
| StoreStore
;
11647 /* Relaxed Memory Ordering: no implicit bits. */
11651 gcc_unreachable ();
11654 if (before_after
& 1)
11656 if (model
== MEMMODEL_RELEASE
11657 || model
== MEMMODEL_ACQ_REL
11658 || model
== MEMMODEL_SEQ_CST
)
11660 if (load_store
& 1)
11661 mm
|= LoadLoad
| StoreLoad
;
11662 if (load_store
& 2)
11663 mm
|= LoadStore
| StoreStore
;
11666 if (before_after
& 2)
11668 if (model
== MEMMODEL_ACQUIRE
11669 || model
== MEMMODEL_ACQ_REL
11670 || model
== MEMMODEL_SEQ_CST
)
11672 if (load_store
& 1)
11673 mm
|= LoadLoad
| LoadStore
;
11674 if (load_store
& 2)
11675 mm
|= StoreLoad
| StoreStore
;
11679 /* Remove the bits implied by the system memory model. */
11682 /* For raw barriers (before+after), always emit a barrier.
11683 This will become a compile-time barrier if needed. */
11684 if (mm
|| before_after
== 3)
11685 emit_insn (gen_membar (GEN_INT (mm
)));
11688 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit
11689 compare and swap on the word containing the byte or half-word. */
11692 sparc_expand_compare_and_swap_12 (rtx bool_result
, rtx result
, rtx mem
,
11693 rtx oldval
, rtx newval
)
11695 rtx addr1
= force_reg (Pmode
, XEXP (mem
, 0));
11696 rtx addr
= gen_reg_rtx (Pmode
);
11697 rtx off
= gen_reg_rtx (SImode
);
11698 rtx oldv
= gen_reg_rtx (SImode
);
11699 rtx newv
= gen_reg_rtx (SImode
);
11700 rtx oldvalue
= gen_reg_rtx (SImode
);
11701 rtx newvalue
= gen_reg_rtx (SImode
);
11702 rtx res
= gen_reg_rtx (SImode
);
11703 rtx resv
= gen_reg_rtx (SImode
);
11704 rtx memsi
, val
, mask
, cc
;
11706 emit_insn (gen_rtx_SET (VOIDmode
, addr
,
11707 gen_rtx_AND (Pmode
, addr1
, GEN_INT (-4))));
11709 if (Pmode
!= SImode
)
11710 addr1
= gen_lowpart (SImode
, addr1
);
11711 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11712 gen_rtx_AND (SImode
, addr1
, GEN_INT (3))));
11714 memsi
= gen_rtx_MEM (SImode
, addr
);
11715 set_mem_alias_set (memsi
, ALIAS_SET_MEMORY_BARRIER
);
11716 MEM_VOLATILE_P (memsi
) = MEM_VOLATILE_P (mem
);
11718 val
= copy_to_reg (memsi
);
11720 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11721 gen_rtx_XOR (SImode
, off
,
11722 GEN_INT (GET_MODE (mem
) == QImode
11725 emit_insn (gen_rtx_SET (VOIDmode
, off
,
11726 gen_rtx_ASHIFT (SImode
, off
, GEN_INT (3))));
11728 if (GET_MODE (mem
) == QImode
)
11729 mask
= force_reg (SImode
, GEN_INT (0xff));
11731 mask
= force_reg (SImode
, GEN_INT (0xffff));
11733 emit_insn (gen_rtx_SET (VOIDmode
, mask
,
11734 gen_rtx_ASHIFT (SImode
, mask
, off
)));
11736 emit_insn (gen_rtx_SET (VOIDmode
, val
,
11737 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11740 oldval
= gen_lowpart (SImode
, oldval
);
11741 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
11742 gen_rtx_ASHIFT (SImode
, oldval
, off
)));
11744 newval
= gen_lowpart_common (SImode
, newval
);
11745 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
11746 gen_rtx_ASHIFT (SImode
, newval
, off
)));
11748 emit_insn (gen_rtx_SET (VOIDmode
, oldv
,
11749 gen_rtx_AND (SImode
, oldv
, mask
)));
11751 emit_insn (gen_rtx_SET (VOIDmode
, newv
,
11752 gen_rtx_AND (SImode
, newv
, mask
)));
11754 rtx_code_label
*end_label
= gen_label_rtx ();
11755 rtx_code_label
*loop_label
= gen_label_rtx ();
11756 emit_label (loop_label
);
11758 emit_insn (gen_rtx_SET (VOIDmode
, oldvalue
,
11759 gen_rtx_IOR (SImode
, oldv
, val
)));
11761 emit_insn (gen_rtx_SET (VOIDmode
, newvalue
,
11762 gen_rtx_IOR (SImode
, newv
, val
)));
11764 emit_move_insn (bool_result
, const1_rtx
);
11766 emit_insn (gen_atomic_compare_and_swapsi_1 (res
, memsi
, oldvalue
, newvalue
));
11768 emit_cmp_and_jump_insns (res
, oldvalue
, EQ
, NULL
, SImode
, 0, end_label
);
11770 emit_insn (gen_rtx_SET (VOIDmode
, resv
,
11771 gen_rtx_AND (SImode
, gen_rtx_NOT (SImode
, mask
),
11774 emit_move_insn (bool_result
, const0_rtx
);
11776 cc
= gen_compare_reg_1 (NE
, resv
, val
);
11777 emit_insn (gen_rtx_SET (VOIDmode
, val
, resv
));
11779 /* Use cbranchcc4 to separate the compare and branch! */
11780 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode
, cc
, const0_rtx
),
11781 cc
, const0_rtx
, loop_label
));
11783 emit_label (end_label
);
11785 emit_insn (gen_rtx_SET (VOIDmode
, res
,
11786 gen_rtx_AND (SImode
, res
, mask
)));
11788 emit_insn (gen_rtx_SET (VOIDmode
, res
,
11789 gen_rtx_LSHIFTRT (SImode
, res
, off
)));
11791 emit_move_insn (result
, gen_lowpart (GET_MODE (result
), res
));
11794 /* Expand code to perform a compare-and-swap. */
11797 sparc_expand_compare_and_swap (rtx operands
[])
11799 rtx bval
, retval
, mem
, oldval
, newval
;
11800 enum machine_mode mode
;
11801 enum memmodel model
;
11803 bval
= operands
[0];
11804 retval
= operands
[1];
11806 oldval
= operands
[3];
11807 newval
= operands
[4];
11808 model
= (enum memmodel
) INTVAL (operands
[6]);
11809 mode
= GET_MODE (mem
);
11811 sparc_emit_membar_for_model (model
, 3, 1);
11813 if (reg_overlap_mentioned_p (retval
, oldval
))
11814 oldval
= copy_to_reg (oldval
);
11816 if (mode
== QImode
|| mode
== HImode
)
11817 sparc_expand_compare_and_swap_12 (bval
, retval
, mem
, oldval
, newval
);
11820 rtx (*gen
) (rtx
, rtx
, rtx
, rtx
);
11823 if (mode
== SImode
)
11824 gen
= gen_atomic_compare_and_swapsi_1
;
11826 gen
= gen_atomic_compare_and_swapdi_1
;
11827 emit_insn (gen (retval
, mem
, oldval
, newval
));
11829 x
= emit_store_flag (bval
, EQ
, retval
, oldval
, mode
, 1, 1);
11831 convert_move (bval
, x
, 1);
11834 sparc_emit_membar_for_model (model
, 3, 2);
11838 sparc_expand_vec_perm_bmask (enum machine_mode vmode
, rtx sel
)
11842 sel
= gen_lowpart (DImode
, sel
);
11846 /* inp = xxxxxxxAxxxxxxxB */
11847 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11848 NULL_RTX
, 1, OPTAB_DIRECT
);
11849 /* t_1 = ....xxxxxxxAxxx. */
11850 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11851 GEN_INT (3), NULL_RTX
, 1, OPTAB_DIRECT
);
11852 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11853 GEN_INT (0x30000), NULL_RTX
, 1, OPTAB_DIRECT
);
11854 /* sel = .......B */
11855 /* t_1 = ...A.... */
11856 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11857 /* sel = ...A...B */
11858 sel
= expand_mult (SImode
, sel
, GEN_INT (0x4444), sel
, 1);
11859 /* sel = AAAABBBB * 4 */
11860 t_1
= force_reg (SImode
, GEN_INT (0x01230123));
11861 /* sel = { A*4, A*4+1, A*4+2, ... } */
11865 /* inp = xxxAxxxBxxxCxxxD */
11866 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11867 NULL_RTX
, 1, OPTAB_DIRECT
);
11868 t_2
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11869 NULL_RTX
, 1, OPTAB_DIRECT
);
11870 t_3
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (24),
11871 NULL_RTX
, 1, OPTAB_DIRECT
);
11872 /* t_1 = ..xxxAxxxBxxxCxx */
11873 /* t_2 = ....xxxAxxxBxxxC */
11874 /* t_3 = ......xxxAxxxBxx */
11875 sel
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, sel
),
11877 NULL_RTX
, 1, OPTAB_DIRECT
);
11878 t_1
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_1
),
11880 NULL_RTX
, 1, OPTAB_DIRECT
);
11881 t_2
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_2
),
11882 GEN_INT (0x070000),
11883 NULL_RTX
, 1, OPTAB_DIRECT
);
11884 t_3
= expand_simple_binop (SImode
, AND
, gen_lowpart (SImode
, t_3
),
11885 GEN_INT (0x07000000),
11886 NULL_RTX
, 1, OPTAB_DIRECT
);
11887 /* sel = .......D */
11888 /* t_1 = .....C.. */
11889 /* t_2 = ...B.... */
11890 /* t_3 = .A...... */
11891 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_1
, sel
, 1, OPTAB_DIRECT
);
11892 t_2
= expand_simple_binop (SImode
, IOR
, t_2
, t_3
, t_2
, 1, OPTAB_DIRECT
);
11893 sel
= expand_simple_binop (SImode
, IOR
, sel
, t_2
, sel
, 1, OPTAB_DIRECT
);
11894 /* sel = .A.B.C.D */
11895 sel
= expand_mult (SImode
, sel
, GEN_INT (0x22), sel
, 1);
11896 /* sel = AABBCCDD * 2 */
11897 t_1
= force_reg (SImode
, GEN_INT (0x01010101));
11898 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */
11902 /* input = xAxBxCxDxExFxGxH */
11903 sel
= expand_simple_binop (DImode
, AND
, sel
,
11904 GEN_INT ((HOST_WIDE_INT
)0x0f0f0f0f << 32
11906 NULL_RTX
, 1, OPTAB_DIRECT
);
11907 /* sel = .A.B.C.D.E.F.G.H */
11908 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (4),
11909 NULL_RTX
, 1, OPTAB_DIRECT
);
11910 /* t_1 = ..A.B.C.D.E.F.G. */
11911 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11912 NULL_RTX
, 1, OPTAB_DIRECT
);
11913 /* sel = .AABBCCDDEEFFGGH */
11914 sel
= expand_simple_binop (DImode
, AND
, sel
,
11915 GEN_INT ((HOST_WIDE_INT
)0xff00ff << 32
11917 NULL_RTX
, 1, OPTAB_DIRECT
);
11918 /* sel = ..AB..CD..EF..GH */
11919 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (8),
11920 NULL_RTX
, 1, OPTAB_DIRECT
);
11921 /* t_1 = ....AB..CD..EF.. */
11922 sel
= expand_simple_binop (DImode
, IOR
, sel
, t_1
,
11923 NULL_RTX
, 1, OPTAB_DIRECT
);
11924 /* sel = ..ABABCDCDEFEFGH */
11925 sel
= expand_simple_binop (DImode
, AND
, sel
,
11926 GEN_INT ((HOST_WIDE_INT
)0xffff << 32 | 0xffff),
11927 NULL_RTX
, 1, OPTAB_DIRECT
);
11928 /* sel = ....ABCD....EFGH */
11929 t_1
= expand_simple_binop (DImode
, LSHIFTRT
, sel
, GEN_INT (16),
11930 NULL_RTX
, 1, OPTAB_DIRECT
);
11931 /* t_1 = ........ABCD.... */
11932 sel
= gen_lowpart (SImode
, sel
);
11933 t_1
= gen_lowpart (SImode
, t_1
);
11937 gcc_unreachable ();
11940 /* Always perform the final addition/merge within the bmask insn. */
11941 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, t_1
));
11944 /* Implement TARGET_FRAME_POINTER_REQUIRED. */
11947 sparc_frame_pointer_required (void)
11949 /* If the stack pointer is dynamically modified in the function, it cannot
11950 serve as the frame pointer. */
11951 if (cfun
->calls_alloca
)
11954 /* If the function receives nonlocal gotos, it needs to save the frame
11955 pointer in the nonlocal_goto_save_area object. */
11956 if (cfun
->has_nonlocal_label
)
11959 /* In flat mode, that's it. */
11963 /* Otherwise, the frame pointer is required if the function isn't leaf. */
11964 return !(crtl
->is_leaf
&& only_leaf_regs_used ());
11967 /* The way this is structured, we can't eliminate SFP in favor of SP
11968 if the frame pointer is required: we want to use the SFP->HFP elimination
11969 in that case. But the test in update_eliminables doesn't know we are
11970 assuming below that we only do the former elimination. */
11973 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED
, const int to
)
11975 return to
== HARD_FRAME_POINTER_REGNUM
|| !sparc_frame_pointer_required ();
11978 /* Return the hard frame pointer directly to bypass the stack bias. */
11981 sparc_builtin_setjmp_frame_value (void)
11983 return hard_frame_pointer_rtx
;
11986 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that
11987 they won't be allocated. */
11990 sparc_conditional_register_usage (void)
11992 if (PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
11994 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
11995 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
11997 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */
11998 /* then honor it. */
11999 if (TARGET_ARCH32
&& fixed_regs
[5])
12001 else if (TARGET_ARCH64
&& fixed_regs
[5] == 2)
12006 for (regno
= SPARC_FIRST_V9_FP_REG
;
12007 regno
<= SPARC_LAST_V9_FP_REG
;
12009 fixed_regs
[regno
] = 1;
12010 /* %fcc0 is used by v8 and v9. */
12011 for (regno
= SPARC_FIRST_V9_FCC_REG
+ 1;
12012 regno
<= SPARC_LAST_V9_FCC_REG
;
12014 fixed_regs
[regno
] = 1;
12019 for (regno
= 32; regno
< SPARC_LAST_V9_FCC_REG
; regno
++)
12020 fixed_regs
[regno
] = 1;
12022 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */
12023 /* then honor it. Likewise with g3 and g4. */
12024 if (fixed_regs
[2] == 2)
12025 fixed_regs
[2] = ! TARGET_APP_REGS
;
12026 if (fixed_regs
[3] == 2)
12027 fixed_regs
[3] = ! TARGET_APP_REGS
;
12028 if (TARGET_ARCH32
&& fixed_regs
[4] == 2)
12029 fixed_regs
[4] = ! TARGET_APP_REGS
;
12030 else if (TARGET_CM_EMBMEDANY
)
12032 else if (fixed_regs
[4] == 2)
12037 /* Disable leaf functions. */
12038 memset (sparc_leaf_regs
, 0, FIRST_PSEUDO_REGISTER
);
12039 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
12040 leaf_reg_remap
[regno
] = regno
;
12043 global_regs
[SPARC_GSR_REG
] = 1;
12046 /* Implement TARGET_PREFERRED_RELOAD_CLASS:
12048 - We can't load constants into FP registers.
12049 - We can't load FP constants into integer registers when soft-float,
12050 because there is no soft-float pattern with a r/F constraint.
12051 - We can't load FP constants into integer registers for TFmode unless
12052 it is 0.0L, because there is no movtf pattern with a r/F constraint.
12053 - Try and reload integer constants (symbolic or otherwise) back into
12054 registers directly, rather than having them dumped to memory. */
12057 sparc_preferred_reload_class (rtx x
, reg_class_t rclass
)
12059 enum machine_mode mode
= GET_MODE (x
);
12060 if (CONSTANT_P (x
))
12062 if (FP_REG_CLASS_P (rclass
)
12063 || rclass
== GENERAL_OR_FP_REGS
12064 || rclass
== GENERAL_OR_EXTRA_FP_REGS
12065 || (GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ! TARGET_FPU
)
12066 || (mode
== TFmode
&& ! const_zero_operand (x
, mode
)))
12069 if (GET_MODE_CLASS (mode
) == MODE_INT
)
12070 return GENERAL_REGS
;
12072 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
)
12074 if (! FP_REG_CLASS_P (rclass
)
12075 || !(const_zero_operand (x
, mode
)
12076 || const_all_ones_operand (x
, mode
)))
12083 && (rclass
== EXTRA_FP_REGS
12084 || rclass
== GENERAL_OR_EXTRA_FP_REGS
))
12086 int regno
= true_regnum (x
);
12088 if (SPARC_INT_REG_P (regno
))
12089 return (rclass
== EXTRA_FP_REGS
12090 ? FP_REGS
: GENERAL_OR_FP_REGS
);
12096 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction,
12097 OPERANDS are its operands and OPCODE is the mnemonic to be used. */
12100 output_v8plus_mult (rtx_insn
*insn
, rtx
*operands
, const char *opcode
)
12104 gcc_assert (! TARGET_ARCH64
);
12106 if (sparc_check_64 (operands
[1], insn
) <= 0)
12107 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
12108 if (which_alternative
== 1)
12109 output_asm_insn ("sllx\t%H1, 32, %H1", operands
);
12110 if (GET_CODE (operands
[2]) == CONST_INT
)
12112 if (which_alternative
== 1)
12114 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12115 sprintf (mulstr
, "%s\t%%H1, %%2, %%L0", opcode
);
12116 output_asm_insn (mulstr
, operands
);
12117 return "srlx\t%L0, 32, %H0";
12121 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12122 output_asm_insn ("or\t%L1, %3, %3", operands
);
12123 sprintf (mulstr
, "%s\t%%3, %%2, %%3", opcode
);
12124 output_asm_insn (mulstr
, operands
);
12125 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12126 return "mov\t%3, %L0";
12129 else if (rtx_equal_p (operands
[1], operands
[2]))
12131 if (which_alternative
== 1)
12133 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12134 sprintf (mulstr
, "%s\t%%H1, %%H1, %%L0", opcode
);
12135 output_asm_insn (mulstr
, operands
);
12136 return "srlx\t%L0, 32, %H0";
12140 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12141 output_asm_insn ("or\t%L1, %3, %3", operands
);
12142 sprintf (mulstr
, "%s\t%%3, %%3, %%3", opcode
);
12143 output_asm_insn (mulstr
, operands
);
12144 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12145 return "mov\t%3, %L0";
12148 if (sparc_check_64 (operands
[2], insn
) <= 0)
12149 output_asm_insn ("srl\t%L2, 0, %L2", operands
);
12150 if (which_alternative
== 1)
12152 output_asm_insn ("or\t%L1, %H1, %H1", operands
);
12153 output_asm_insn ("sllx\t%H2, 32, %L1", operands
);
12154 output_asm_insn ("or\t%L2, %L1, %L1", operands
);
12155 sprintf (mulstr
, "%s\t%%H1, %%L1, %%L0", opcode
);
12156 output_asm_insn (mulstr
, operands
);
12157 return "srlx\t%L0, 32, %H0";
12161 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
12162 output_asm_insn ("sllx\t%H2, 32, %4", operands
);
12163 output_asm_insn ("or\t%L1, %3, %3", operands
);
12164 output_asm_insn ("or\t%L2, %4, %4", operands
);
12165 sprintf (mulstr
, "%s\t%%3, %%4, %%3", opcode
);
12166 output_asm_insn (mulstr
, operands
);
12167 output_asm_insn ("srlx\t%3, 32, %H0", operands
);
12168 return "mov\t%3, %L0";
12172 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12173 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE
12174 and INNER_MODE are the modes describing TARGET. */
12177 vector_init_bshuffle (rtx target
, rtx elt
, enum machine_mode mode
,
12178 enum machine_mode inner_mode
)
12180 rtx t1
, final_insn
, sel
;
12183 t1
= gen_reg_rtx (mode
);
12185 elt
= convert_modes (SImode
, inner_mode
, elt
, true);
12186 emit_move_insn (gen_lowpart(SImode
, t1
), elt
);
12191 final_insn
= gen_bshufflev2si_vis (target
, t1
, t1
);
12192 bmask
= 0x45674567;
12195 final_insn
= gen_bshufflev4hi_vis (target
, t1
, t1
);
12196 bmask
= 0x67676767;
12199 final_insn
= gen_bshufflev8qi_vis (target
, t1
, t1
);
12200 bmask
= 0x77777777;
12203 gcc_unreachable ();
12206 sel
= force_reg (SImode
, GEN_INT (bmask
));
12207 emit_insn (gen_bmasksi_vis (gen_rtx_REG (SImode
, 0), sel
, const0_rtx
));
12208 emit_insn (final_insn
);
12211 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12212 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */
12215 vector_init_fpmerge (rtx target
, rtx elt
)
12217 rtx t1
, t2
, t2_low
, t3
, t3_low
;
12219 t1
= gen_reg_rtx (V4QImode
);
12220 elt
= convert_modes (SImode
, QImode
, elt
, true);
12221 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12223 t2
= gen_reg_rtx (V8QImode
);
12224 t2_low
= gen_lowpart (V4QImode
, t2
);
12225 emit_insn (gen_fpmerge_vis (t2
, t1
, t1
));
12227 t3
= gen_reg_rtx (V8QImode
);
12228 t3_low
= gen_lowpart (V4QImode
, t3
);
12229 emit_insn (gen_fpmerge_vis (t3
, t2_low
, t2_low
));
12231 emit_insn (gen_fpmerge_vis (target
, t3_low
, t3_low
));
12234 /* Subroutine of sparc_expand_vector_init. Emit code to initialize
12235 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */
12238 vector_init_faligndata (rtx target
, rtx elt
)
12240 rtx t1
= gen_reg_rtx (V4HImode
);
12243 elt
= convert_modes (SImode
, HImode
, elt
, true);
12244 emit_move_insn (gen_lowpart (SImode
, t1
), elt
);
12246 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode
),
12247 force_reg (SImode
, GEN_INT (6)),
12250 for (i
= 0; i
< 4; i
++)
12251 emit_insn (gen_faligndatav4hi_vis (target
, t1
, target
));
12254 /* Emit code to initialize TARGET to values for individual fields VALS. */
12257 sparc_expand_vector_init (rtx target
, rtx vals
)
12259 const enum machine_mode mode
= GET_MODE (target
);
12260 const enum machine_mode inner_mode
= GET_MODE_INNER (mode
);
12261 const int n_elts
= GET_MODE_NUNITS (mode
);
12267 for (i
= 0; i
< n_elts
; i
++)
12269 rtx x
= XVECEXP (vals
, 0, i
);
12270 if (!CONSTANT_P (x
))
12273 if (i
> 0 && !rtx_equal_p (x
, XVECEXP (vals
, 0, 0)))
12279 emit_move_insn (target
, gen_rtx_CONST_VECTOR (mode
, XVEC (vals
, 0)));
12283 if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (mode
))
12285 if (GET_MODE_SIZE (inner_mode
) == 4)
12287 emit_move_insn (gen_lowpart (SImode
, target
),
12288 gen_lowpart (SImode
, XVECEXP (vals
, 0, 0)));
12291 else if (GET_MODE_SIZE (inner_mode
) == 8)
12293 emit_move_insn (gen_lowpart (DImode
, target
),
12294 gen_lowpart (DImode
, XVECEXP (vals
, 0, 0)));
12298 else if (GET_MODE_SIZE (inner_mode
) == GET_MODE_SIZE (word_mode
)
12299 && GET_MODE_SIZE (mode
) == 2 * GET_MODE_SIZE (word_mode
))
12301 emit_move_insn (gen_highpart (word_mode
, target
),
12302 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 0)));
12303 emit_move_insn (gen_lowpart (word_mode
, target
),
12304 gen_lowpart (word_mode
, XVECEXP (vals
, 0, 1)));
12308 if (all_same
&& GET_MODE_SIZE (mode
) == 8)
12312 vector_init_bshuffle (target
, XVECEXP (vals
, 0, 0), mode
, inner_mode
);
12315 if (mode
== V8QImode
)
12317 vector_init_fpmerge (target
, XVECEXP (vals
, 0, 0));
12320 if (mode
== V4HImode
)
12322 vector_init_faligndata (target
, XVECEXP (vals
, 0, 0));
12327 mem
= assign_stack_temp (mode
, GET_MODE_SIZE (mode
));
12328 for (i
= 0; i
< n_elts
; i
++)
12329 emit_move_insn (adjust_address_nv (mem
, inner_mode
,
12330 i
* GET_MODE_SIZE (inner_mode
)),
12331 XVECEXP (vals
, 0, i
));
12332 emit_move_insn (target
, mem
);
12335 /* Implement TARGET_SECONDARY_RELOAD. */
12338 sparc_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
12339 enum machine_mode mode
, secondary_reload_info
*sri
)
12341 enum reg_class rclass
= (enum reg_class
) rclass_i
;
12343 sri
->icode
= CODE_FOR_nothing
;
12344 sri
->extra_cost
= 0;
12346 /* We need a temporary when loading/storing a HImode/QImode value
12347 between memory and the FPU registers. This can happen when combine puts
12348 a paradoxical subreg in a float/fix conversion insn. */
12349 if (FP_REG_CLASS_P (rclass
)
12350 && (mode
== HImode
|| mode
== QImode
)
12351 && (GET_CODE (x
) == MEM
12352 || ((GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
12353 && true_regnum (x
) == -1)))
12354 return GENERAL_REGS
;
12356 /* On 32-bit we need a temporary when loading/storing a DFmode value
12357 between unaligned memory and the upper FPU registers. */
12359 && rclass
== EXTRA_FP_REGS
12361 && GET_CODE (x
) == MEM
12362 && ! mem_min_alignment (x
, 8))
12365 if (((TARGET_CM_MEDANY
12366 && symbolic_operand (x
, mode
))
12367 || (TARGET_CM_EMBMEDANY
12368 && text_segment_operand (x
, mode
)))
12372 sri
->icode
= direct_optab_handler (reload_in_optab
, mode
);
12374 sri
->icode
= direct_optab_handler (reload_out_optab
, mode
);
12378 if (TARGET_VIS3
&& TARGET_ARCH32
)
12380 int regno
= true_regnum (x
);
12382 /* When using VIS3 fp<-->int register moves, on 32-bit we have
12383 to move 8-byte values in 4-byte pieces. This only works via
12384 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to
12385 move between EXTRA_FP_REGS and GENERAL_REGS, we will need
12386 an FP_REGS intermediate move. */
12387 if ((rclass
== EXTRA_FP_REGS
&& SPARC_INT_REG_P (regno
))
12388 || ((general_or_i64_p (rclass
)
12389 || rclass
== GENERAL_OR_FP_REGS
)
12390 && SPARC_FP_REG_P (regno
)))
12392 sri
->extra_cost
= 2;
12400 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into
12401 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */
12404 sparc_expand_conditional_move (enum machine_mode mode
, rtx
*operands
)
12406 enum rtx_code rc
= GET_CODE (operands
[1]);
12407 enum machine_mode cmp_mode
;
12408 rtx cc_reg
, dst
, cmp
;
12411 if (GET_MODE (XEXP (cmp
, 0)) == DImode
&& !TARGET_ARCH64
)
12414 if (GET_MODE (XEXP (cmp
, 0)) == TFmode
&& !TARGET_HARD_QUAD
)
12415 cmp
= sparc_emit_float_lib_cmp (XEXP (cmp
, 0), XEXP (cmp
, 1), rc
);
12417 cmp_mode
= GET_MODE (XEXP (cmp
, 0));
12418 rc
= GET_CODE (cmp
);
12421 if (! rtx_equal_p (operands
[2], dst
)
12422 && ! rtx_equal_p (operands
[3], dst
))
12424 if (reg_overlap_mentioned_p (dst
, cmp
))
12425 dst
= gen_reg_rtx (mode
);
12427 emit_move_insn (dst
, operands
[3]);
12429 else if (operands
[2] == dst
)
12431 operands
[2] = operands
[3];
12433 if (GET_MODE_CLASS (cmp_mode
) == MODE_FLOAT
)
12434 rc
= reverse_condition_maybe_unordered (rc
);
12436 rc
= reverse_condition (rc
);
12439 if (XEXP (cmp
, 1) == const0_rtx
12440 && GET_CODE (XEXP (cmp
, 0)) == REG
12441 && cmp_mode
== DImode
12442 && v9_regcmp_p (rc
))
12443 cc_reg
= XEXP (cmp
, 0);
12445 cc_reg
= gen_compare_reg_1 (rc
, XEXP (cmp
, 0), XEXP (cmp
, 1));
12447 cmp
= gen_rtx_fmt_ee (rc
, GET_MODE (cc_reg
), cc_reg
, const0_rtx
);
12449 emit_insn (gen_rtx_SET (VOIDmode
, dst
,
12450 gen_rtx_IF_THEN_ELSE (mode
, cmp
, operands
[2], dst
)));
12452 if (dst
!= operands
[0])
12453 emit_move_insn (operands
[0], dst
);
12458 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2]
12459 into OPERANDS[0] in MODE, depending on the outcome of the comparison of
12460 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition.
12461 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine
12462 code to be used for the condition mask. */
12465 sparc_expand_vcond (enum machine_mode mode
, rtx
*operands
, int ccode
, int fcode
)
12467 rtx mask
, cop0
, cop1
, fcmp
, cmask
, bshuf
, gsr
;
12468 enum rtx_code code
= GET_CODE (operands
[3]);
12470 mask
= gen_reg_rtx (Pmode
);
12471 cop0
= operands
[4];
12472 cop1
= operands
[5];
12473 if (code
== LT
|| code
== GE
)
12477 code
= swap_condition (code
);
12478 t
= cop0
; cop0
= cop1
; cop1
= t
;
12481 gsr
= gen_rtx_REG (DImode
, SPARC_GSR_REG
);
12483 fcmp
= gen_rtx_UNSPEC (Pmode
,
12484 gen_rtvec (1, gen_rtx_fmt_ee (code
, mode
, cop0
, cop1
)),
12487 cmask
= gen_rtx_UNSPEC (DImode
,
12488 gen_rtvec (2, mask
, gsr
),
12491 bshuf
= gen_rtx_UNSPEC (mode
,
12492 gen_rtvec (3, operands
[1], operands
[2], gsr
),
12495 emit_insn (gen_rtx_SET (VOIDmode
, mask
, fcmp
));
12496 emit_insn (gen_rtx_SET (VOIDmode
, gsr
, cmask
));
12498 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], bshuf
));
12501 /* On sparc, any mode which naturally allocates into the float
12502 registers should return 4 here. */
12505 sparc_regmode_natural_size (enum machine_mode mode
)
12507 int size
= UNITS_PER_WORD
;
12511 enum mode_class mclass
= GET_MODE_CLASS (mode
);
12513 if (mclass
== MODE_FLOAT
|| mclass
== MODE_VECTOR_INT
)
12520 /* Return TRUE if it is a good idea to tie two pseudo registers
12521 when one has mode MODE1 and one has mode MODE2.
12522 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
12523 for any hard reg, then this must be FALSE for correct output.
12525 For V9 we have to deal with the fact that only the lower 32 floating
12526 point registers are 32-bit addressable. */
12529 sparc_modes_tieable_p (enum machine_mode mode1
, enum machine_mode mode2
)
12531 enum mode_class mclass1
, mclass2
;
12532 unsigned short size1
, size2
;
12534 if (mode1
== mode2
)
12537 mclass1
= GET_MODE_CLASS (mode1
);
12538 mclass2
= GET_MODE_CLASS (mode2
);
12539 if (mclass1
!= mclass2
)
12545 /* Classes are the same and we are V9 so we have to deal with upper
12546 vs. lower floating point registers. If one of the modes is a
12547 4-byte mode, and the other is not, we have to mark them as not
12548 tieable because only the lower 32 floating point register are
12549 addressable 32-bits at a time.
12551 We can't just test explicitly for SFmode, otherwise we won't
12552 cover the vector mode cases properly. */
12554 if (mclass1
!= MODE_FLOAT
&& mclass1
!= MODE_VECTOR_INT
)
12557 size1
= GET_MODE_SIZE (mode1
);
12558 size2
= GET_MODE_SIZE (mode2
);
12559 if ((size1
> 4 && size2
== 4)
12560 || (size2
> 4 && size1
== 4))
12566 /* Implement TARGET_CSTORE_MODE. */
12568 static enum machine_mode
12569 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED
)
12571 return (TARGET_ARCH64
? DImode
: SImode
);
12574 /* Return the compound expression made of T1 and T2. */
12577 compound_expr (tree t1
, tree t2
)
12579 return build2 (COMPOUND_EXPR
, void_type_node
, t1
, t2
);
12582 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */
12585 sparc_atomic_assign_expand_fenv (tree
*hold
, tree
*clear
, tree
*update
)
12590 const unsigned HOST_WIDE_INT accrued_exception_mask
= 0x1f << 5;
12591 const unsigned HOST_WIDE_INT trap_enable_mask
= 0x1f << 23;
12593 /* We generate the equivalent of feholdexcept (&fenv_var):
12595 unsigned int fenv_var;
12596 __builtin_store_fsr (&fenv_var);
12598 unsigned int tmp1_var;
12599 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask);
12601 __builtin_load_fsr (&tmp1_var); */
12603 tree fenv_var
= create_tmp_var (unsigned_type_node
, NULL
);
12604 mark_addressable (fenv_var
);
12605 tree fenv_addr
= build_fold_addr_expr (fenv_var
);
12606 tree stfsr
= sparc_builtins
[SPARC_BUILTIN_STFSR
];
12607 tree hold_stfsr
= build_call_expr (stfsr
, 1, fenv_addr
);
12609 tree tmp1_var
= create_tmp_var (unsigned_type_node
, NULL
);
12610 mark_addressable (tmp1_var
);
12611 tree masked_fenv_var
12612 = build2 (BIT_AND_EXPR
, unsigned_type_node
, fenv_var
,
12613 build_int_cst (unsigned_type_node
,
12614 ~(accrued_exception_mask
| trap_enable_mask
)));
12616 = build2 (MODIFY_EXPR
, void_type_node
, tmp1_var
, masked_fenv_var
);
12618 tree tmp1_addr
= build_fold_addr_expr (tmp1_var
);
12619 tree ldfsr
= sparc_builtins
[SPARC_BUILTIN_LDFSR
];
12620 tree hold_ldfsr
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12622 *hold
= compound_expr (compound_expr (hold_stfsr
, hold_mask
), hold_ldfsr
);
12624 /* We reload the value of tmp1_var to clear the exceptions:
12626 __builtin_load_fsr (&tmp1_var); */
12628 *clear
= build_call_expr (ldfsr
, 1, tmp1_addr
);
12630 /* We generate the equivalent of feupdateenv (&fenv_var):
12632 unsigned int tmp2_var;
12633 __builtin_store_fsr (&tmp2_var);
12635 __builtin_load_fsr (&fenv_var);
12637 if (SPARC_LOW_FE_EXCEPT_VALUES)
12639 __atomic_feraiseexcept ((int) tmp2_var); */
12641 tree tmp2_var
= create_tmp_var (unsigned_type_node
, NULL
);
12642 mark_addressable (tmp2_var
);
12643 tree tmp3_addr
= build_fold_addr_expr (tmp2_var
);
12644 tree update_stfsr
= build_call_expr (stfsr
, 1, tmp3_addr
);
12646 tree update_ldfsr
= build_call_expr (ldfsr
, 1, fenv_addr
);
12648 tree atomic_feraiseexcept
12649 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT
);
12651 = build_call_expr (atomic_feraiseexcept
, 1,
12652 fold_convert (integer_type_node
, tmp2_var
));
12654 if (SPARC_LOW_FE_EXCEPT_VALUES
)
12656 tree shifted_tmp2_var
12657 = build2 (RSHIFT_EXPR
, unsigned_type_node
, tmp2_var
,
12658 build_int_cst (unsigned_type_node
, 5));
12660 = build2 (MODIFY_EXPR
, void_type_node
, tmp2_var
, shifted_tmp2_var
);
12661 update_call
= compound_expr (update_shift
, update_call
);
12665 = compound_expr (compound_expr (update_stfsr
, update_ldfsr
), update_call
);
12668 #include "gt-sparc.h"