1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
47 #include "target-def.h"
49 /* 1 if the caller has placed an "unimp" insn immediately after the call.
50 This is used in v8 code when calling a function that returns a structure.
51 v9 doesn't have this. Be careful to have this test be the same as that
54 #define SKIP_CALLERS_UNIMP_P \
55 (!TARGET_ARCH64 && current_function_returns_struct \
56 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
57 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 /* Global variables for machine-dependent things. */
62 /* Size of frame. Need to know this to emit return insns from leaf procedures.
63 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
64 reload pass. This is important as the value is later used in insn
65 scheduling (to see what can go in a delay slot).
66 APPARENT_FSIZE is the size of the stack less the register save area and less
67 the outgoing argument area. It is used when saving call preserved regs. */
68 static int apparent_fsize
;
69 static int actual_fsize
;
71 /* Number of live general or floating point registers needed to be
72 saved (as 4-byte quantities). */
73 static int num_gfregs
;
75 /* Save the operands last given to a compare for use when we
76 generate a scc or bcc insn. */
77 rtx sparc_compare_op0
, sparc_compare_op1
;
79 /* Coordinate with the md file wrt special insns created by
80 sparc_nonflat_function_epilogue. */
81 bool sparc_emitting_epilogue
;
83 /* Vector to say how input registers are mapped to output registers.
84 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
85 eliminate it. You must use -fomit-frame-pointer to get that. */
86 char leaf_reg_remap
[] =
87 { 0, 1, 2, 3, 4, 5, 6, 7,
88 -1, -1, -1, -1, -1, -1, 14, -1,
89 -1, -1, -1, -1, -1, -1, -1, -1,
90 8, 9, 10, 11, 12, 13, -1, 15,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 40, 41, 42, 43, 44, 45, 46, 47,
94 48, 49, 50, 51, 52, 53, 54, 55,
95 56, 57, 58, 59, 60, 61, 62, 63,
96 64, 65, 66, 67, 68, 69, 70, 71,
97 72, 73, 74, 75, 76, 77, 78, 79,
98 80, 81, 82, 83, 84, 85, 86, 87,
99 88, 89, 90, 91, 92, 93, 94, 95,
100 96, 97, 98, 99, 100};
102 /* Vector, indexed by hard register number, which contains 1
103 for a register that is allowable in a candidate for leaf
104 function treatment. */
105 char sparc_leaf_regs
[] =
106 { 1, 1, 1, 1, 1, 1, 1, 1,
107 0, 0, 0, 0, 0, 0, 1, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 1, 1, 1, 1, 1, 1, 0, 1,
110 1, 1, 1, 1, 1, 1, 1, 1,
111 1, 1, 1, 1, 1, 1, 1, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
120 /* Name of where we pretend to think the frame pointer points.
121 Normally, this is "%fp", but if we are in a leaf procedure,
122 this is "%sp+something". We record "something" separately as it may be
123 too big for reg+constant addressing. */
125 static const char *frame_base_name
;
126 static int frame_base_offset
;
128 static void sparc_init_modes
PARAMS ((void));
129 static int save_regs
PARAMS ((FILE *, int, int, const char *,
131 static int restore_regs
PARAMS ((FILE *, int, int, const char *, int, int));
132 static void build_big_number
PARAMS ((FILE *, int, const char *));
133 static int function_arg_slotno
PARAMS ((const CUMULATIVE_ARGS
*,
134 enum machine_mode
, tree
, int, int,
137 static int supersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
138 static int hypersparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
140 static void sparc_output_addr_vec
PARAMS ((rtx
));
141 static void sparc_output_addr_diff_vec
PARAMS ((rtx
));
142 static void sparc_output_deferred_case_vectors
PARAMS ((void));
143 static int check_return_regs
PARAMS ((rtx
));
144 static int epilogue_renumber
PARAMS ((rtx
*, int));
145 static bool sparc_assemble_integer
PARAMS ((rtx
, unsigned int, int));
146 static int set_extends
PARAMS ((rtx
));
147 static void output_restore_regs
PARAMS ((FILE *, int));
148 static void sparc_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
149 static void sparc_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
150 static void sparc_flat_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
151 static void sparc_flat_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
152 static void sparc_nonflat_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
,
154 static void sparc_nonflat_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
,
156 #ifdef OBJECT_FORMAT_ELF
157 static void sparc_elf_asm_named_section
PARAMS ((const char *, unsigned int));
159 static void sparc_aout_select_section
PARAMS ((tree
, int,
160 unsigned HOST_WIDE_INT
))
162 static void sparc_aout_select_rtx_section
PARAMS ((enum machine_mode
, rtx
,
163 unsigned HOST_WIDE_INT
))
166 static int sparc_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
167 static int sparc_issue_rate
PARAMS ((void));
168 static void sparc_sched_init
PARAMS ((FILE *, int, int));
169 static int sparc_use_dfa_pipeline_interface
PARAMS ((void));
170 static int sparc_use_sched_lookahead
PARAMS ((void));
172 static void emit_soft_tfmode_libcall
PARAMS ((const char *, int, rtx
*));
173 static void emit_soft_tfmode_binop
PARAMS ((enum rtx_code
, rtx
*));
174 static void emit_soft_tfmode_unop
PARAMS ((enum rtx_code
, rtx
*));
175 static void emit_soft_tfmode_cvt
PARAMS ((enum rtx_code
, rtx
*));
176 static void emit_hard_tfmode_operation
PARAMS ((enum rtx_code
, rtx
*));
178 static void sparc_encode_section_info
PARAMS ((tree
, int));
179 static void sparc_output_mi_thunk
PARAMS ((FILE *, tree
, HOST_WIDE_INT
,
180 HOST_WIDE_INT
, tree
));
182 /* Option handling. */
184 /* Code model option as passed by user. */
185 const char *sparc_cmodel_string
;
187 enum cmodel sparc_cmodel
;
189 char sparc_hard_reg_printed
[8];
191 struct sparc_cpu_select sparc_select
[] =
193 /* switch name, tune arch */
194 { (char *)0, "default", 1, 1 },
195 { (char *)0, "-mcpu=", 1, 1 },
196 { (char *)0, "-mtune=", 1, 0 },
200 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
201 enum processor_type sparc_cpu
;
203 /* Initialize the GCC target structure. */
205 /* The sparc default is to use .half rather than .short for aligned
206 HI objects. Use .word instead of .long on non-ELF systems. */
207 #undef TARGET_ASM_ALIGNED_HI_OP
208 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
209 #ifndef OBJECT_FORMAT_ELF
210 #undef TARGET_ASM_ALIGNED_SI_OP
211 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
214 #undef TARGET_ASM_UNALIGNED_HI_OP
215 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
216 #undef TARGET_ASM_UNALIGNED_SI_OP
217 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
218 #undef TARGET_ASM_UNALIGNED_DI_OP
219 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
221 /* The target hook has to handle DI-mode values. */
222 #undef TARGET_ASM_INTEGER
223 #define TARGET_ASM_INTEGER sparc_assemble_integer
225 #undef TARGET_ASM_FUNCTION_PROLOGUE
226 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
227 #undef TARGET_ASM_FUNCTION_EPILOGUE
228 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
230 #undef TARGET_SCHED_ADJUST_COST
231 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
232 #undef TARGET_SCHED_ISSUE_RATE
233 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
234 #undef TARGET_SCHED_INIT
235 #define TARGET_SCHED_INIT sparc_sched_init
236 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
237 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
238 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
239 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
241 #undef TARGET_ENCODE_SECTION_INFO
242 #define TARGET_ENCODE_SECTION_INFO sparc_encode_section_info
244 #undef TARGET_ASM_OUTPUT_MI_THUNK
245 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
246 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
247 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
249 struct gcc_target targetm
= TARGET_INITIALIZER
;
251 /* Validate and override various options, and do some machine dependent
255 sparc_override_options ()
257 static struct code_model
{
258 const char *const name
;
260 } const cmodels
[] = {
262 { "medlow", CM_MEDLOW
},
263 { "medmid", CM_MEDMID
},
264 { "medany", CM_MEDANY
},
265 { "embmedany", CM_EMBMEDANY
},
268 const struct code_model
*cmodel
;
269 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
270 static struct cpu_default
{
272 const char *const name
;
273 } const cpu_default
[] = {
274 /* There must be one entry here for each TARGET_CPU value. */
275 { TARGET_CPU_sparc
, "cypress" },
276 { TARGET_CPU_sparclet
, "tsc701" },
277 { TARGET_CPU_sparclite
, "f930" },
278 { TARGET_CPU_v8
, "v8" },
279 { TARGET_CPU_hypersparc
, "hypersparc" },
280 { TARGET_CPU_sparclite86x
, "sparclite86x" },
281 { TARGET_CPU_supersparc
, "supersparc" },
282 { TARGET_CPU_v9
, "v9" },
283 { TARGET_CPU_ultrasparc
, "ultrasparc" },
284 { TARGET_CPU_ultrasparc3
, "ultrasparc3" },
287 const struct cpu_default
*def
;
288 /* Table of values for -m{cpu,tune}=. */
289 static struct cpu_table
{
290 const char *const name
;
291 const enum processor_type processor
;
294 } const cpu_table
[] = {
295 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
296 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
297 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
298 /* TI TMS390Z55 supersparc */
299 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
300 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
301 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
302 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
303 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
304 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
305 { "hypersparc", PROCESSOR_HYPERSPARC
, MASK_ISA
, MASK_V8
|MASK_FPU
},
306 { "sparclite86x", PROCESSOR_SPARCLITE86X
, MASK_ISA
|MASK_FPU
,
308 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
310 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
311 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
312 /* TI ultrasparc I, II, IIi */
313 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
314 /* Although insns using %y are deprecated, it is a clear win on current
316 |MASK_DEPRECATED_V8_INSNS
},
317 /* TI ultrasparc III */
318 /* ??? Check if %y issue still holds true in ultra3. */
319 { "ultrasparc3", PROCESSOR_ULTRASPARC3
, MASK_ISA
, MASK_V9
|MASK_DEPRECATED_V8_INSNS
},
322 const struct cpu_table
*cpu
;
323 const struct sparc_cpu_select
*sel
;
326 #ifndef SPARC_BI_ARCH
327 /* Check for unsupported architecture size. */
328 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
329 error ("%s is not supported by this configuration",
330 DEFAULT_ARCH32_P
? "-m64" : "-m32");
333 /* We force all 64bit archs to use 128 bit long double */
334 if (TARGET_64BIT
&& ! TARGET_LONG_DOUBLE_128
)
336 error ("-mlong-double-64 not allowed with -m64");
337 target_flags
|= MASK_LONG_DOUBLE_128
;
340 /* Code model selection. */
341 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
345 sparc_cmodel
= CM_32
;
348 if (sparc_cmodel_string
!= NULL
)
352 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
353 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
355 if (cmodel
->name
== NULL
)
356 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
358 sparc_cmodel
= cmodel
->value
;
361 error ("-mcmodel= is not supported on 32 bit systems");
364 fpu
= TARGET_FPU
; /* save current -mfpu status */
366 /* Set the default CPU. */
367 for (def
= &cpu_default
[0]; def
->name
; ++def
)
368 if (def
->cpu
== TARGET_CPU_DEFAULT
)
372 sparc_select
[0].string
= def
->name
;
374 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
378 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
379 if (! strcmp (sel
->string
, cpu
->name
))
382 sparc_cpu
= cpu
->processor
;
386 target_flags
&= ~cpu
->disable
;
387 target_flags
|= cpu
->enable
;
393 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
397 /* If -mfpu or -mno-fpu was explicitly used, don't override with
398 the processor default. Clear MASK_FPU_SET to avoid confusing
399 the reverse mapping from switch values to names. */
402 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
403 target_flags
&= ~MASK_FPU_SET
;
406 /* Don't allow -mvis if FPU is disabled. */
408 target_flags
&= ~MASK_VIS
;
410 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
412 -m64 also implies v9. */
413 if (TARGET_VIS
|| TARGET_ARCH64
)
415 target_flags
|= MASK_V9
;
416 target_flags
&= ~(MASK_V8
| MASK_SPARCLET
| MASK_SPARCLITE
);
419 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
420 if (TARGET_V9
&& TARGET_ARCH32
)
421 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
423 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
424 if (! TARGET_V9
|| TARGET_ARCH64
)
425 target_flags
&= ~MASK_V8PLUS
;
427 /* Don't use stack biasing in 32 bit mode. */
429 target_flags
&= ~MASK_STACK_BIAS
;
431 /* Supply a default value for align_functions. */
432 if (align_functions
== 0
433 && (sparc_cpu
== PROCESSOR_ULTRASPARC
434 || sparc_cpu
== PROCESSOR_ULTRASPARC3
))
435 align_functions
= 32;
437 /* Validate PCC_STRUCT_RETURN. */
438 if (flag_pcc_struct_return
== DEFAULT_PCC_STRUCT_RETURN
)
439 flag_pcc_struct_return
= (TARGET_ARCH64
? 0 : 1);
441 /* Only use .uaxword when compiling for a 64-bit target. */
443 targetm
.asm_out
.unaligned_op
.di
= NULL
;
445 /* Do various machine dependent initializations. */
449 /* Miscellaneous utilities. */
451 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
452 or branch on register contents instructions. */
458 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
459 || code
== LE
|| code
== GT
);
463 /* Operand constraints. */
465 /* Return nonzero only if OP is a register of mode MODE,
469 reg_or_0_operand (op
, mode
)
471 enum machine_mode mode
;
473 if (register_operand (op
, mode
))
475 if (op
== const0_rtx
)
477 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
478 && CONST_DOUBLE_HIGH (op
) == 0
479 && CONST_DOUBLE_LOW (op
) == 0)
481 if (fp_zero_operand (op
, mode
))
486 /* Return nonzero only if OP is const1_rtx. */
489 const1_operand (op
, mode
)
491 enum machine_mode mode ATTRIBUTE_UNUSED
;
493 return op
== const1_rtx
;
496 /* Nonzero if OP is a floating point value with value 0.0. */
499 fp_zero_operand (op
, mode
)
501 enum machine_mode mode
;
503 if (GET_MODE_CLASS (GET_MODE (op
)) != MODE_FLOAT
)
505 return op
== CONST0_RTX (mode
);
508 /* Nonzero if OP is a register operand in floating point register. */
511 fp_register_operand (op
, mode
)
513 enum machine_mode mode
;
515 if (! register_operand (op
, mode
))
517 if (GET_CODE (op
) == SUBREG
)
518 op
= SUBREG_REG (op
);
519 return GET_CODE (op
) == REG
&& SPARC_FP_REG_P (REGNO (op
));
522 /* Nonzero if OP is a floating point constant which can
523 be loaded into an integer register using a single
524 sethi instruction. */
530 if (GET_CODE (op
) == CONST_DOUBLE
)
535 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
536 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
537 ! REAL_VALUE_MINUS_ZERO (r
))
539 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
540 if (SPARC_SETHI_P (i
))
547 /* Nonzero if OP is a floating point constant which can
548 be loaded into an integer register using a single
555 if (GET_CODE (op
) == CONST_DOUBLE
)
560 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
561 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
562 ! REAL_VALUE_MINUS_ZERO (r
))
564 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
565 if (SPARC_SIMM13_P (i
))
572 /* Nonzero if OP is a floating point constant which can
573 be loaded into an integer register using a high/losum
574 instruction sequence. */
580 /* The constraints calling this should only be in
581 SFmode move insns, so any constant which cannot
582 be moved using a single insn will do. */
583 if (GET_CODE (op
) == CONST_DOUBLE
)
588 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
589 if (REAL_VALUES_EQUAL (r
, dconst0
) &&
590 ! REAL_VALUE_MINUS_ZERO (r
))
592 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
593 if (! SPARC_SETHI_P (i
)
594 && ! SPARC_SIMM13_P (i
))
601 /* Nonzero if OP is an integer register. */
604 intreg_operand (op
, mode
)
606 enum machine_mode mode ATTRIBUTE_UNUSED
;
608 return (register_operand (op
, SImode
)
609 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
612 /* Nonzero if OP is a floating point condition code register. */
615 fcc_reg_operand (op
, mode
)
617 enum machine_mode mode
;
619 /* This can happen when recog is called from combine. Op may be a MEM.
620 Fail instead of calling abort in this case. */
621 if (GET_CODE (op
) != REG
)
624 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
627 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
630 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
631 if (reg_renumber
== 0)
632 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
633 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
635 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
639 /* Nonzero if OP is a floating point condition code fcc0 register. */
642 fcc0_reg_operand (op
, mode
)
644 enum machine_mode mode
;
646 /* This can happen when recog is called from combine. Op may be a MEM.
647 Fail instead of calling abort in this case. */
648 if (GET_CODE (op
) != REG
)
651 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
654 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
657 return REGNO (op
) == SPARC_FCC_REG
;
660 /* Nonzero if OP is an integer or floating point condition code register. */
663 icc_or_fcc_reg_operand (op
, mode
)
665 enum machine_mode mode
;
667 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
669 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
672 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
677 return fcc_reg_operand (op
, mode
);
680 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
682 restore_operand (op
, mode
)
684 enum machine_mode mode
;
686 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
687 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
690 /* Call insn on SPARC can take a PC-relative constant address, or any regular
694 call_operand (op
, mode
)
696 enum machine_mode mode
;
698 if (GET_CODE (op
) != MEM
)
701 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
705 call_operand_address (op
, mode
)
707 enum machine_mode mode
;
709 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
712 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
713 reference and a constant. */
716 symbolic_operand (op
, mode
)
718 enum machine_mode mode
;
720 enum machine_mode omode
= GET_MODE (op
);
722 if (omode
!= mode
&& omode
!= VOIDmode
&& mode
!= VOIDmode
)
725 switch (GET_CODE (op
))
733 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
734 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
735 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
742 /* Return truth value of statement that OP is a symbolic memory
743 operand of mode MODE. */
746 symbolic_memory_operand (op
, mode
)
748 enum machine_mode mode ATTRIBUTE_UNUSED
;
750 if (GET_CODE (op
) == SUBREG
)
751 op
= SUBREG_REG (op
);
752 if (GET_CODE (op
) != MEM
)
755 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
756 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
759 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
762 label_ref_operand (op
, mode
)
764 enum machine_mode mode
;
766 if (GET_CODE (op
) != LABEL_REF
)
768 if (GET_MODE (op
) != mode
)
773 /* Return 1 if the operand is an argument used in generating pic references
774 in either the medium/low or medium/anywhere code models of sparc64. */
777 sp64_medium_pic_operand (op
, mode
)
779 enum machine_mode mode ATTRIBUTE_UNUSED
;
781 /* Check for (const (minus (symbol_ref:GOT)
782 (const (minus (label) (pc))))). */
783 if (GET_CODE (op
) != CONST
)
786 if (GET_CODE (op
) != MINUS
)
788 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
790 /* ??? Ensure symbol is GOT. */
791 if (GET_CODE (XEXP (op
, 1)) != CONST
)
793 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
798 /* Return 1 if the operand is a data segment reference. This includes
799 the readonly data segment, or in other words anything but the text segment.
800 This is needed in the medium/anywhere code model on v9. These values
801 are accessed with EMBMEDANY_BASE_REG. */
804 data_segment_operand (op
, mode
)
806 enum machine_mode mode ATTRIBUTE_UNUSED
;
808 switch (GET_CODE (op
))
811 return ! SYMBOL_REF_FLAG (op
);
813 /* Assume canonical format of symbol + constant.
816 return data_segment_operand (XEXP (op
, 0), VOIDmode
);
822 /* Return 1 if the operand is a text segment reference.
823 This is needed in the medium/anywhere code model on v9. */
826 text_segment_operand (op
, mode
)
828 enum machine_mode mode ATTRIBUTE_UNUSED
;
830 switch (GET_CODE (op
))
835 return SYMBOL_REF_FLAG (op
);
837 /* Assume canonical format of symbol + constant.
840 return text_segment_operand (XEXP (op
, 0), VOIDmode
);
846 /* Return 1 if the operand is either a register or a memory operand that is
850 reg_or_nonsymb_mem_operand (op
, mode
)
852 enum machine_mode mode
;
854 if (register_operand (op
, mode
))
857 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
864 splittable_symbolic_memory_operand (op
, mode
)
866 enum machine_mode mode ATTRIBUTE_UNUSED
;
868 if (GET_CODE (op
) != MEM
)
870 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
876 splittable_immediate_memory_operand (op
, mode
)
878 enum machine_mode mode ATTRIBUTE_UNUSED
;
880 if (GET_CODE (op
) != MEM
)
882 if (! immediate_operand (XEXP (op
, 0), Pmode
))
887 /* Return truth value of whether OP is EQ or NE. */
892 enum machine_mode mode ATTRIBUTE_UNUSED
;
894 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
897 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
898 or LTU for non-floating-point. We handle those specially. */
901 normal_comp_operator (op
, mode
)
903 enum machine_mode mode ATTRIBUTE_UNUSED
;
905 enum rtx_code code
= GET_CODE (op
);
907 if (GET_RTX_CLASS (code
) != '<')
910 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
911 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
914 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
917 /* Return 1 if this is a comparison operator. This allows the use of
918 MATCH_OPERATOR to recognize all the branch insns. */
921 noov_compare_op (op
, mode
)
923 enum machine_mode mode ATTRIBUTE_UNUSED
;
925 enum rtx_code code
= GET_CODE (op
);
927 if (GET_RTX_CLASS (code
) != '<')
930 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
931 || GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
932 /* These are the only branches which work with CC_NOOVmode. */
933 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
937 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
938 MATCH_OPERATOR to recognize all the branch insns. */
941 noov_compare64_op (op
, mode
)
943 enum machine_mode mode ATTRIBUTE_UNUSED
;
945 enum rtx_code code
= GET_CODE (op
);
950 if (GET_RTX_CLASS (code
) != '<')
953 if (GET_MODE (XEXP (op
, 0)) == CCX_NOOVmode
)
954 /* These are the only branches which work with CCX_NOOVmode. */
955 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
956 return (GET_MODE (XEXP (op
, 0)) == CCXmode
);
959 /* Nonzero if OP is a comparison operator suitable for use in v9
960 conditional move or branch on register contents instructions. */
963 v9_regcmp_op (op
, mode
)
965 enum machine_mode mode ATTRIBUTE_UNUSED
;
967 enum rtx_code code
= GET_CODE (op
);
969 if (GET_RTX_CLASS (code
) != '<')
972 return v9_regcmp_p (code
);
975 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
980 enum machine_mode mode ATTRIBUTE_UNUSED
;
982 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
985 /* Return nonzero if OP is an operator of mode MODE which can set
986 the condition codes explicitly. We do not include PLUS and MINUS
987 because these require CC_NOOVmode, which we handle explicitly. */
990 cc_arithop (op
, mode
)
992 enum machine_mode mode ATTRIBUTE_UNUSED
;
994 if (GET_CODE (op
) == AND
995 || GET_CODE (op
) == IOR
996 || GET_CODE (op
) == XOR
)
1002 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1003 complement its second operand and set the condition codes explicitly. */
1006 cc_arithopn (op
, mode
)
1008 enum machine_mode mode ATTRIBUTE_UNUSED
;
1010 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1011 and (xor ... (not ...)) to (not (xor ...)). */
1012 return (GET_CODE (op
) == AND
1013 || GET_CODE (op
) == IOR
);
1016 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1017 signed 13 bit immediate field. This is an acceptable SImode operand for
1018 most 3 address instructions. */
1021 arith_operand (op
, mode
)
1023 enum machine_mode mode
;
1025 if (register_operand (op
, mode
))
1027 if (GET_CODE (op
) != CONST_INT
)
1029 return SMALL_INT32 (op
);
1032 /* Return true if OP is a constant 4096 */
1035 arith_4096_operand (op
, mode
)
1037 enum machine_mode mode ATTRIBUTE_UNUSED
;
1039 if (GET_CODE (op
) != CONST_INT
)
1042 return INTVAL (op
) == 4096;
1045 /* Return true if OP is suitable as second operand for add/sub */
1048 arith_add_operand (op
, mode
)
1050 enum machine_mode mode
;
1052 return arith_operand (op
, mode
) || arith_4096_operand (op
, mode
);
1055 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1056 immediate field of OR and XOR instructions. Used for 64-bit
1057 constant formation patterns. */
1059 const64_operand (op
, mode
)
1061 enum machine_mode mode ATTRIBUTE_UNUSED
;
1063 return ((GET_CODE (op
) == CONST_INT
1064 && SPARC_SIMM13_P (INTVAL (op
)))
1065 #if HOST_BITS_PER_WIDE_INT != 64
1066 || (GET_CODE (op
) == CONST_DOUBLE
1067 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1068 && (CONST_DOUBLE_HIGH (op
) ==
1069 ((CONST_DOUBLE_LOW (op
) & 0x80000000) != 0 ?
1070 (HOST_WIDE_INT
)-1 : 0)))
1075 /* The same, but only for sethi instructions. */
1077 const64_high_operand (op
, mode
)
1079 enum machine_mode mode
;
1081 return ((GET_CODE (op
) == CONST_INT
1082 && (INTVAL (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1083 && SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1085 || (GET_CODE (op
) == CONST_DOUBLE
1086 && CONST_DOUBLE_HIGH (op
) == 0
1087 && (CONST_DOUBLE_LOW (op
) & ~(HOST_WIDE_INT
)0x3ff) != 0
1088 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
))));
1091 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1092 signed 11 bit immediate field. This is an acceptable SImode operand for
1093 the movcc instructions. */
1096 arith11_operand (op
, mode
)
1098 enum machine_mode mode
;
1100 return (register_operand (op
, mode
)
1101 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
1104 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1105 signed 10 bit immediate field. This is an acceptable SImode operand for
1106 the movrcc instructions. */
1109 arith10_operand (op
, mode
)
1111 enum machine_mode mode
;
1113 return (register_operand (op
, mode
)
1114 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
1117 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1118 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1120 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1121 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1122 for most 3 address instructions. */
1125 arith_double_operand (op
, mode
)
1127 enum machine_mode mode
;
1129 return (register_operand (op
, mode
)
1130 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1132 && GET_CODE (op
) == CONST_DOUBLE
1133 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1134 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
1136 && GET_CODE (op
) == CONST_DOUBLE
1137 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
1138 && ((CONST_DOUBLE_HIGH (op
) == -1
1139 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
1140 || (CONST_DOUBLE_HIGH (op
) == 0
1141 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
1144 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1147 arith_double_4096_operand (op
, mode
)
1149 enum machine_mode mode ATTRIBUTE_UNUSED
;
1151 return (TARGET_ARCH64
&&
1152 ((GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 4096) ||
1153 (GET_CODE (op
) == CONST_DOUBLE
&&
1154 CONST_DOUBLE_LOW (op
) == 4096 &&
1155 CONST_DOUBLE_HIGH (op
) == 0)));
1158 /* Return true if OP is suitable as second operand for add/sub in DImode */
1161 arith_double_add_operand (op
, mode
)
1163 enum machine_mode mode
;
1165 return arith_double_operand (op
, mode
) || arith_double_4096_operand (op
, mode
);
1168 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1169 can fit in an 11 bit immediate field. This is an acceptable DImode
1170 operand for the movcc instructions. */
1171 /* ??? Replace with arith11_operand? */
1174 arith11_double_operand (op
, mode
)
1176 enum machine_mode mode
;
1178 return (register_operand (op
, mode
)
1179 || (GET_CODE (op
) == CONST_DOUBLE
1180 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1181 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
1182 && ((CONST_DOUBLE_HIGH (op
) == -1
1183 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
1184 || (CONST_DOUBLE_HIGH (op
) == 0
1185 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
1186 || (GET_CODE (op
) == CONST_INT
1187 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1188 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
1191 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1192 can fit in an 10 bit immediate field. This is an acceptable DImode
1193 operand for the movrcc instructions. */
1194 /* ??? Replace with arith10_operand? */
1197 arith10_double_operand (op
, mode
)
1199 enum machine_mode mode
;
1201 return (register_operand (op
, mode
)
1202 || (GET_CODE (op
) == CONST_DOUBLE
1203 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1204 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
1205 && ((CONST_DOUBLE_HIGH (op
) == -1
1206 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
1207 || (CONST_DOUBLE_HIGH (op
) == 0
1208 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
1209 || (GET_CODE (op
) == CONST_INT
1210 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
1211 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
1214 /* Return truth value of whether OP is an integer which fits the
1215 range constraining immediate operands in most three-address insns,
1216 which have a 13 bit immediate field. */
1219 small_int (op
, mode
)
1221 enum machine_mode mode ATTRIBUTE_UNUSED
;
1223 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
1227 small_int_or_double (op
, mode
)
1229 enum machine_mode mode ATTRIBUTE_UNUSED
;
1231 return ((GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
1232 || (GET_CODE (op
) == CONST_DOUBLE
1233 && CONST_DOUBLE_HIGH (op
) == 0
1234 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))));
1237 /* Recognize operand values for the umul instruction. That instruction sign
1238 extends immediate values just like all other sparc instructions, but
1239 interprets the extended result as an unsigned number. */
1242 uns_small_int (op
, mode
)
1244 enum machine_mode mode ATTRIBUTE_UNUSED
;
1246 #if HOST_BITS_PER_WIDE_INT > 32
1247 /* All allowed constants will fit a CONST_INT. */
1248 return (GET_CODE (op
) == CONST_INT
1249 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
1250 || (INTVAL (op
) >= 0xFFFFF000
1251 && INTVAL (op
) <= 0xFFFFFFFF)));
1253 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
1254 || (GET_CODE (op
) == CONST_DOUBLE
1255 && CONST_DOUBLE_HIGH (op
) == 0
1256 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
1261 uns_arith_operand (op
, mode
)
1263 enum machine_mode mode
;
1265 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
1268 /* Return truth value of statement that OP is a call-clobbered register. */
1270 clobbered_register (op
, mode
)
1272 enum machine_mode mode ATTRIBUTE_UNUSED
;
1274 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
1277 /* Return 1 if OP is a valid operand for the source of a move insn. */
1280 input_operand (op
, mode
)
1282 enum machine_mode mode
;
1284 /* If both modes are non-void they must be the same. */
1285 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& mode
!= GET_MODE (op
))
1288 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
1289 if (GET_CODE (op
) == CONST
&& GET_CODE (XEXP (op
, 0)) == CONSTANT_P_RTX
)
1292 /* Allow any one instruction integer constant, and all CONST_INT
1293 variants when we are working in DImode and !arch64. */
1294 if (GET_MODE_CLASS (mode
) == MODE_INT
1295 && ((GET_CODE (op
) == CONST_INT
1296 && (SPARC_SETHI_P (INTVAL (op
) & GET_MODE_MASK (mode
))
1297 || SPARC_SIMM13_P (INTVAL (op
))
1299 && ! TARGET_ARCH64
)))
1301 && GET_CODE (op
) == CONST_DOUBLE
1302 && ((CONST_DOUBLE_HIGH (op
) == 0
1303 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op
)))
1305 #if HOST_BITS_PER_WIDE_INT == 64
1306 (CONST_DOUBLE_HIGH (op
) == 0
1307 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
)))
1309 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op
))
1310 && (((CONST_DOUBLE_LOW (op
) & 0x80000000) == 0
1311 && CONST_DOUBLE_HIGH (op
) == 0)
1312 || (CONST_DOUBLE_HIGH (op
) == -1
1313 && CONST_DOUBLE_LOW (op
) & 0x80000000) != 0))
1318 /* If !arch64 and this is a DImode const, allow it so that
1319 the splits can be generated. */
1322 && GET_CODE (op
) == CONST_DOUBLE
)
1325 if (register_operand (op
, mode
))
1328 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
1329 && GET_CODE (op
) == CONST_DOUBLE
)
1332 /* If this is a SUBREG, look inside so that we handle
1333 paradoxical ones. */
1334 if (GET_CODE (op
) == SUBREG
)
1335 op
= SUBREG_REG (op
);
1337 /* Check for valid MEM forms. */
1338 if (GET_CODE (op
) == MEM
)
1340 rtx inside
= XEXP (op
, 0);
1342 if (GET_CODE (inside
) == LO_SUM
)
1344 /* We can't allow these because all of the splits
1345 (eventually as they trickle down into DFmode
1346 splits) require offsettable memory references. */
1348 && GET_MODE (op
) == TFmode
)
1351 return (register_operand (XEXP (inside
, 0), Pmode
)
1352 && CONSTANT_P (XEXP (inside
, 1)));
1354 return memory_address_p (mode
, inside
);
1361 /* We know it can't be done in one insn when we get here,
1362 the movsi expander guarentees this. */
1364 sparc_emit_set_const32 (op0
, op1
)
1368 enum machine_mode mode
= GET_MODE (op0
);
1371 if (GET_CODE (op1
) == CONST_INT
)
1373 HOST_WIDE_INT value
= INTVAL (op1
);
1375 if (SPARC_SETHI_P (value
& GET_MODE_MASK (mode
))
1376 || SPARC_SIMM13_P (value
))
1380 /* Full 2-insn decomposition is needed. */
1381 if (reload_in_progress
|| reload_completed
)
1384 temp
= gen_reg_rtx (mode
);
1386 if (GET_CODE (op1
) == CONST_INT
)
1388 /* Emit them as real moves instead of a HIGH/LO_SUM,
1389 this way CSE can see everything and reuse intermediate
1390 values if it wants. */
1392 && HOST_BITS_PER_WIDE_INT
!= 64
1393 && (INTVAL (op1
) & 0x80000000) != 0)
1394 emit_insn (gen_rtx_SET
1396 immed_double_const (INTVAL (op1
) & ~(HOST_WIDE_INT
)0x3ff,
1399 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1400 GEN_INT (INTVAL (op1
)
1401 & ~(HOST_WIDE_INT
)0x3ff)));
1403 emit_insn (gen_rtx_SET (VOIDmode
,
1405 gen_rtx_IOR (mode
, temp
,
1406 GEN_INT (INTVAL (op1
) & 0x3ff))));
1410 /* A symbol, emit in the traditional way. */
1411 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1412 gen_rtx_HIGH (mode
, op1
)));
1413 emit_insn (gen_rtx_SET (VOIDmode
,
1414 op0
, gen_rtx_LO_SUM (mode
, temp
, op1
)));
1420 /* SPARC-v9 code-model support. */
1422 sparc_emit_set_symbolic_const64 (op0
, op1
, temp1
)
1429 if (temp1
&& GET_MODE (temp1
) == TImode
)
1432 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
));
1435 switch (sparc_cmodel
)
1438 /* The range spanned by all instructions in the object is less
1439 than 2^31 bytes (2GB) and the distance from any instruction
1440 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1441 than 2^31 bytes (2GB).
1443 The executable must be in the low 4TB of the virtual address
1446 sethi %hi(symbol), %temp
1447 or %temp, %lo(symbol), %reg */
1448 emit_insn (gen_rtx_SET (VOIDmode
, temp1
, gen_rtx_HIGH (DImode
, op1
)));
1449 emit_insn (gen_rtx_SET (VOIDmode
, op0
, gen_rtx_LO_SUM (DImode
, temp1
, op1
)));
1453 /* The range spanned by all instructions in the object is less
1454 than 2^31 bytes (2GB) and the distance from any instruction
1455 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1456 than 2^31 bytes (2GB).
1458 The executable must be in the low 16TB of the virtual address
1461 sethi %h44(symbol), %temp1
1462 or %temp1, %m44(symbol), %temp2
1463 sllx %temp2, 12, %temp3
1464 or %temp3, %l44(symbol), %reg */
1465 emit_insn (gen_seth44 (op0
, op1
));
1466 emit_insn (gen_setm44 (op0
, op0
, op1
));
1467 emit_insn (gen_rtx_SET (VOIDmode
, temp1
,
1468 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (12))));
1469 emit_insn (gen_setl44 (op0
, temp1
, op1
));
1473 /* The range spanned by all instructions in the object is less
1474 than 2^31 bytes (2GB) and the distance from any instruction
1475 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1476 than 2^31 bytes (2GB).
1478 The executable can be placed anywhere in the virtual address
1481 sethi %hh(symbol), %temp1
1482 sethi %lm(symbol), %temp2
1483 or %temp1, %hm(symbol), %temp3
1484 or %temp2, %lo(symbol), %temp4
1485 sllx %temp3, 32, %temp5
1486 or %temp4, %temp5, %reg */
1488 /* It is possible that one of the registers we got for operands[2]
1489 might coincide with that of operands[0] (which is why we made
1490 it TImode). Pick the other one to use as our scratch. */
1491 if (rtx_equal_p (temp1
, op0
))
1494 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1499 emit_insn (gen_sethh (op0
, op1
));
1500 emit_insn (gen_setlm (temp1
, op1
));
1501 emit_insn (gen_sethm (op0
, op0
, op1
));
1502 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1503 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1504 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1505 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1506 emit_insn (gen_setlo (op0
, op0
, op1
));
1510 /* Old old old backwards compatibility kruft here.
1511 Essentially it is MEDLOW with a fixed 64-bit
1512 virtual base added to all data segment addresses.
1513 Text-segment stuff is computed like MEDANY, we can't
1514 reuse the code above because the relocation knobs
1517 Data segment: sethi %hi(symbol), %temp1
1518 or %temp1, %lo(symbol), %temp2
1519 add %temp2, EMBMEDANY_BASE_REG, %reg
1521 Text segment: sethi %uhi(symbol), %temp1
1522 sethi %hi(symbol), %temp2
1523 or %temp1, %ulo(symbol), %temp3
1524 or %temp2, %lo(symbol), %temp4
1525 sllx %temp3, 32, %temp5
1526 or %temp4, %temp5, %reg */
1527 if (data_segment_operand (op1
, GET_MODE (op1
)))
1529 emit_insn (gen_embmedany_sethi (temp1
, op1
));
1530 emit_insn (gen_embmedany_brsum (op0
, temp1
));
1531 emit_insn (gen_embmedany_losum (op0
, op0
, op1
));
1535 /* It is possible that one of the registers we got for operands[2]
1536 might coincide with that of operands[0] (which is why we made
1537 it TImode). Pick the other one to use as our scratch. */
1538 if (rtx_equal_p (temp1
, op0
))
1541 temp1
= gen_rtx_REG (DImode
, REGNO (temp1
) + 1);
1546 emit_insn (gen_embmedany_textuhi (op0
, op1
));
1547 emit_insn (gen_embmedany_texthi (temp1
, op1
));
1548 emit_insn (gen_embmedany_textulo (op0
, op0
, op1
));
1549 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1550 gen_rtx_ASHIFT (DImode
, op0
, GEN_INT (32))));
1551 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1552 gen_rtx_PLUS (DImode
, op0
, temp1
)));
1553 emit_insn (gen_embmedany_textlo (op0
, op0
, op1
));
1562 /* These avoid problems when cross compiling. If we do not
1563 go through all this hair then the optimizer will see
1564 invalid REG_EQUAL notes or in some cases none at all. */
1565 static void sparc_emit_set_safe_HIGH64
PARAMS ((rtx
, HOST_WIDE_INT
));
1566 static rtx gen_safe_SET64
PARAMS ((rtx
, HOST_WIDE_INT
));
1567 static rtx gen_safe_OR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1568 static rtx gen_safe_XOR64
PARAMS ((rtx
, HOST_WIDE_INT
));
1570 #if HOST_BITS_PER_WIDE_INT == 64
1571 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1572 #define GEN_INT64(__x) GEN_INT (__x)
1574 #define GEN_HIGHINT64(__x) \
1575 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1576 #define GEN_INT64(__x) \
1577 immed_double_const ((__x) & 0xffffffff, \
1578 ((__x) & 0x80000000 ? -1 : 0), DImode)
1581 /* The optimizer is not to assume anything about exactly
1582 which bits are set for a HIGH, they are unspecified.
1583 Unfortunately this leads to many missed optimizations
1584 during CSE. We mask out the non-HIGH bits, and matches
1585 a plain movdi, to alleviate this problem. */
1587 sparc_emit_set_safe_HIGH64 (dest
, val
)
1591 emit_insn (gen_rtx_SET (VOIDmode
, dest
, GEN_HIGHINT64 (val
)));
1595 gen_safe_SET64 (dest
, val
)
1599 return gen_rtx_SET (VOIDmode
, dest
, GEN_INT64 (val
));
1603 gen_safe_OR64 (src
, val
)
1607 return gen_rtx_IOR (DImode
, src
, GEN_INT64 (val
));
1611 gen_safe_XOR64 (src
, val
)
1615 return gen_rtx_XOR (DImode
, src
, GEN_INT64 (val
));
1618 /* Worker routines for 64-bit constant formation on arch64.
1619 One of the key things to be doing in these emissions is
1620 to create as many temp REGs as possible. This makes it
1621 possible for half-built constants to be used later when
1622 such values are similar to something required later on.
1623 Without doing this, the optimizer cannot see such
1626 static void sparc_emit_set_const64_quick1
1627 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, int));
1630 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
, is_neg
)
1633 unsigned HOST_WIDE_INT low_bits
;
1636 unsigned HOST_WIDE_INT high_bits
;
1639 high_bits
= (~low_bits
) & 0xffffffff;
1641 high_bits
= low_bits
;
1643 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1646 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1647 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1651 /* If we are XOR'ing with -1, then we should emit a one's complement
1652 instead. This way the combiner will notice logical operations
1653 such as ANDN later on and substitute. */
1654 if ((low_bits
& 0x3ff) == 0x3ff)
1656 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1657 gen_rtx_NOT (DImode
, temp
)));
1661 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1662 gen_safe_XOR64 (temp
,
1663 (-(HOST_WIDE_INT
)0x400
1664 | (low_bits
& 0x3ff)))));
1669 static void sparc_emit_set_const64_quick2
1670 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
,
1671 unsigned HOST_WIDE_INT
, int));
1674 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_immediate
, shift_count
)
1677 unsigned HOST_WIDE_INT high_bits
;
1678 unsigned HOST_WIDE_INT low_immediate
;
1683 if ((high_bits
& 0xfffffc00) != 0)
1685 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1686 if ((high_bits
& ~0xfffffc00) != 0)
1687 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1688 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1694 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1698 /* Now shift it up into place. */
1699 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1700 gen_rtx_ASHIFT (DImode
, temp2
,
1701 GEN_INT (shift_count
))));
1703 /* If there is a low immediate part piece, finish up by
1704 putting that in as well. */
1705 if (low_immediate
!= 0)
1706 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1707 gen_safe_OR64 (op0
, low_immediate
)));
1710 static void sparc_emit_set_const64_longway
1711 PARAMS ((rtx
, rtx
, unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1713 /* Full 64-bit constant decomposition. Even though this is the
1714 'worst' case, we still optimize a few things away. */
1716 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
)
1719 unsigned HOST_WIDE_INT high_bits
;
1720 unsigned HOST_WIDE_INT low_bits
;
1724 if (reload_in_progress
|| reload_completed
)
1727 sub_temp
= gen_reg_rtx (DImode
);
1729 if ((high_bits
& 0xfffffc00) != 0)
1731 sparc_emit_set_safe_HIGH64 (temp
, high_bits
);
1732 if ((high_bits
& ~0xfffffc00) != 0)
1733 emit_insn (gen_rtx_SET (VOIDmode
,
1735 gen_safe_OR64 (temp
, (high_bits
& 0x3ff))));
1741 emit_insn (gen_safe_SET64 (temp
, high_bits
));
1745 if (!reload_in_progress
&& !reload_completed
)
1747 rtx temp2
= gen_reg_rtx (DImode
);
1748 rtx temp3
= gen_reg_rtx (DImode
);
1749 rtx temp4
= gen_reg_rtx (DImode
);
1751 emit_insn (gen_rtx_SET (VOIDmode
, temp4
,
1752 gen_rtx_ASHIFT (DImode
, sub_temp
,
1755 sparc_emit_set_safe_HIGH64 (temp2
, low_bits
);
1756 if ((low_bits
& ~0xfffffc00) != 0)
1758 emit_insn (gen_rtx_SET (VOIDmode
, temp3
,
1759 gen_safe_OR64 (temp2
, (low_bits
& 0x3ff))));
1760 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1761 gen_rtx_PLUS (DImode
, temp4
, temp3
)));
1765 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1766 gen_rtx_PLUS (DImode
, temp4
, temp2
)));
1771 rtx low1
= GEN_INT ((low_bits
>> (32 - 12)) & 0xfff);
1772 rtx low2
= GEN_INT ((low_bits
>> (32 - 12 - 12)) & 0xfff);
1773 rtx low3
= GEN_INT ((low_bits
>> (32 - 12 - 12 - 8)) & 0x0ff);
1776 /* We are in the middle of reload, so this is really
1777 painful. However we do still make an attempt to
1778 avoid emitting truly stupid code. */
1779 if (low1
!= const0_rtx
)
1781 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1782 gen_rtx_ASHIFT (DImode
, sub_temp
,
1783 GEN_INT (to_shift
))));
1784 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1785 gen_rtx_IOR (DImode
, op0
, low1
)));
1793 if (low2
!= const0_rtx
)
1795 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1796 gen_rtx_ASHIFT (DImode
, sub_temp
,
1797 GEN_INT (to_shift
))));
1798 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1799 gen_rtx_IOR (DImode
, op0
, low2
)));
1807 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1808 gen_rtx_ASHIFT (DImode
, sub_temp
,
1809 GEN_INT (to_shift
))));
1810 if (low3
!= const0_rtx
)
1811 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
1812 gen_rtx_IOR (DImode
, op0
, low3
)));
1817 /* Analyze a 64-bit constant for certain properties. */
1818 static void analyze_64bit_constant
1819 PARAMS ((unsigned HOST_WIDE_INT
,
1820 unsigned HOST_WIDE_INT
,
1821 int *, int *, int *));
1824 analyze_64bit_constant (high_bits
, low_bits
, hbsp
, lbsp
, abbasp
)
1825 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1826 int *hbsp
, *lbsp
, *abbasp
;
1828 int lowest_bit_set
, highest_bit_set
, all_bits_between_are_set
;
1831 lowest_bit_set
= highest_bit_set
= -1;
1835 if ((lowest_bit_set
== -1)
1836 && ((low_bits
>> i
) & 1))
1838 if ((highest_bit_set
== -1)
1839 && ((high_bits
>> (32 - i
- 1)) & 1))
1840 highest_bit_set
= (64 - i
- 1);
1843 && ((highest_bit_set
== -1)
1844 || (lowest_bit_set
== -1)));
1850 if ((lowest_bit_set
== -1)
1851 && ((high_bits
>> i
) & 1))
1852 lowest_bit_set
= i
+ 32;
1853 if ((highest_bit_set
== -1)
1854 && ((low_bits
>> (32 - i
- 1)) & 1))
1855 highest_bit_set
= 32 - i
- 1;
1858 && ((highest_bit_set
== -1)
1859 || (lowest_bit_set
== -1)));
1861 /* If there are no bits set this should have gone out
1862 as one instruction! */
1863 if (lowest_bit_set
== -1
1864 || highest_bit_set
== -1)
1866 all_bits_between_are_set
= 1;
1867 for (i
= lowest_bit_set
; i
<= highest_bit_set
; i
++)
1871 if ((low_bits
& (1 << i
)) != 0)
1876 if ((high_bits
& (1 << (i
- 32))) != 0)
1879 all_bits_between_are_set
= 0;
1882 *hbsp
= highest_bit_set
;
1883 *lbsp
= lowest_bit_set
;
1884 *abbasp
= all_bits_between_are_set
;
1887 static int const64_is_2insns
1888 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
));
1891 const64_is_2insns (high_bits
, low_bits
)
1892 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1894 int highest_bit_set
, lowest_bit_set
, all_bits_between_are_set
;
1897 || high_bits
== 0xffffffff)
1900 analyze_64bit_constant (high_bits
, low_bits
,
1901 &highest_bit_set
, &lowest_bit_set
,
1902 &all_bits_between_are_set
);
1904 if ((highest_bit_set
== 63
1905 || lowest_bit_set
== 0)
1906 && all_bits_between_are_set
!= 0)
1909 if ((highest_bit_set
- lowest_bit_set
) < 21)
1915 static unsigned HOST_WIDE_INT create_simple_focus_bits
1916 PARAMS ((unsigned HOST_WIDE_INT
, unsigned HOST_WIDE_INT
,
1919 static unsigned HOST_WIDE_INT
1920 create_simple_focus_bits (high_bits
, low_bits
, lowest_bit_set
, shift
)
1921 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1922 int lowest_bit_set
, shift
;
1924 HOST_WIDE_INT hi
, lo
;
1926 if (lowest_bit_set
< 32)
1928 lo
= (low_bits
>> lowest_bit_set
) << shift
;
1929 hi
= ((high_bits
<< (32 - lowest_bit_set
)) << shift
);
1934 hi
= ((high_bits
>> (lowest_bit_set
- 32)) << shift
);
1941 /* Here we are sure to be arch64 and this is an integer constant
1942 being loaded into a register. Emit the most efficient
1943 insn sequence possible. Detection of all the 1-insn cases
1944 has been done already. */
1946 sparc_emit_set_const64 (op0
, op1
)
1950 unsigned HOST_WIDE_INT high_bits
, low_bits
;
1951 int lowest_bit_set
, highest_bit_set
;
1952 int all_bits_between_are_set
;
1955 /* Sanity check that we know what we are working with. */
1956 if (! TARGET_ARCH64
)
1959 if (GET_CODE (op0
) != SUBREG
)
1961 if (GET_CODE (op0
) != REG
1962 || (REGNO (op0
) >= SPARC_FIRST_FP_REG
1963 && REGNO (op0
) <= SPARC_LAST_V9_FP_REG
))
1967 if (reload_in_progress
|| reload_completed
)
1970 temp
= gen_reg_rtx (DImode
);
1972 if (GET_CODE (op1
) != CONST_DOUBLE
1973 && GET_CODE (op1
) != CONST_INT
)
1975 sparc_emit_set_symbolic_const64 (op0
, op1
, temp
);
1979 if (GET_CODE (op1
) == CONST_DOUBLE
)
1981 #if HOST_BITS_PER_WIDE_INT == 64
1982 high_bits
= (CONST_DOUBLE_LOW (op1
) >> 32) & 0xffffffff;
1983 low_bits
= CONST_DOUBLE_LOW (op1
) & 0xffffffff;
1985 high_bits
= CONST_DOUBLE_HIGH (op1
);
1986 low_bits
= CONST_DOUBLE_LOW (op1
);
1991 #if HOST_BITS_PER_WIDE_INT == 64
1992 high_bits
= ((INTVAL (op1
) >> 32) & 0xffffffff);
1993 low_bits
= (INTVAL (op1
) & 0xffffffff);
1995 high_bits
= ((INTVAL (op1
) < 0) ?
1998 low_bits
= INTVAL (op1
);
2002 /* low_bits bits 0 --> 31
2003 high_bits bits 32 --> 63 */
2005 analyze_64bit_constant (high_bits
, low_bits
,
2006 &highest_bit_set
, &lowest_bit_set
,
2007 &all_bits_between_are_set
);
2009 /* First try for a 2-insn sequence. */
2011 /* These situations are preferred because the optimizer can
2012 * do more things with them:
2014 * sllx %reg, shift, %reg
2016 * srlx %reg, shift, %reg
2017 * 3) mov some_small_const, %reg
2018 * sllx %reg, shift, %reg
2020 if (((highest_bit_set
== 63
2021 || lowest_bit_set
== 0)
2022 && all_bits_between_are_set
!= 0)
2023 || ((highest_bit_set
- lowest_bit_set
) < 12))
2025 HOST_WIDE_INT the_const
= -1;
2026 int shift
= lowest_bit_set
;
2028 if ((highest_bit_set
!= 63
2029 && lowest_bit_set
!= 0)
2030 || all_bits_between_are_set
== 0)
2033 create_simple_focus_bits (high_bits
, low_bits
,
2036 else if (lowest_bit_set
== 0)
2037 shift
= -(63 - highest_bit_set
);
2039 if (! SPARC_SIMM13_P (the_const
))
2042 emit_insn (gen_safe_SET64 (temp
, the_const
));
2044 emit_insn (gen_rtx_SET (VOIDmode
,
2046 gen_rtx_ASHIFT (DImode
,
2050 emit_insn (gen_rtx_SET (VOIDmode
,
2052 gen_rtx_LSHIFTRT (DImode
,
2054 GEN_INT (-shift
))));
2060 /* Now a range of 22 or less bits set somewhere.
2061 * 1) sethi %hi(focus_bits), %reg
2062 * sllx %reg, shift, %reg
2063 * 2) sethi %hi(focus_bits), %reg
2064 * srlx %reg, shift, %reg
2066 if ((highest_bit_set
- lowest_bit_set
) < 21)
2068 unsigned HOST_WIDE_INT focus_bits
=
2069 create_simple_focus_bits (high_bits
, low_bits
,
2070 lowest_bit_set
, 10);
2072 if (! SPARC_SETHI_P (focus_bits
))
2075 sparc_emit_set_safe_HIGH64 (temp
, focus_bits
);
2077 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2078 if (lowest_bit_set
< 10)
2079 emit_insn (gen_rtx_SET (VOIDmode
,
2081 gen_rtx_LSHIFTRT (DImode
, temp
,
2082 GEN_INT (10 - lowest_bit_set
))));
2083 else if (lowest_bit_set
> 10)
2084 emit_insn (gen_rtx_SET (VOIDmode
,
2086 gen_rtx_ASHIFT (DImode
, temp
,
2087 GEN_INT (lowest_bit_set
- 10))));
2093 /* 1) sethi %hi(low_bits), %reg
2094 * or %reg, %lo(low_bits), %reg
2095 * 2) sethi %hi(~low_bits), %reg
2096 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2099 || high_bits
== 0xffffffff)
2101 sparc_emit_set_const64_quick1 (op0
, temp
, low_bits
,
2102 (high_bits
== 0xffffffff));
2106 /* Now, try 3-insn sequences. */
2108 /* 1) sethi %hi(high_bits), %reg
2109 * or %reg, %lo(high_bits), %reg
2110 * sllx %reg, 32, %reg
2114 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, 0, 32);
2118 /* We may be able to do something quick
2119 when the constant is negated, so try that. */
2120 if (const64_is_2insns ((~high_bits
) & 0xffffffff,
2121 (~low_bits
) & 0xfffffc00))
2123 /* NOTE: The trailing bits get XOR'd so we need the
2124 non-negated bits, not the negated ones. */
2125 unsigned HOST_WIDE_INT trailing_bits
= low_bits
& 0x3ff;
2127 if ((((~high_bits
) & 0xffffffff) == 0
2128 && ((~low_bits
) & 0x80000000) == 0)
2129 || (((~high_bits
) & 0xffffffff) == 0xffffffff
2130 && ((~low_bits
) & 0x80000000) != 0))
2132 int fast_int
= (~low_bits
& 0xffffffff);
2134 if ((SPARC_SETHI_P (fast_int
)
2135 && (~high_bits
& 0xffffffff) == 0)
2136 || SPARC_SIMM13_P (fast_int
))
2137 emit_insn (gen_safe_SET64 (temp
, fast_int
));
2139 sparc_emit_set_const64 (temp
, GEN_INT64 (fast_int
));
2144 #if HOST_BITS_PER_WIDE_INT == 64
2145 negated_const
= GEN_INT (((~low_bits
) & 0xfffffc00) |
2146 (((HOST_WIDE_INT
)((~high_bits
) & 0xffffffff))<<32));
2148 negated_const
= immed_double_const ((~low_bits
) & 0xfffffc00,
2149 (~high_bits
) & 0xffffffff,
2152 sparc_emit_set_const64 (temp
, negated_const
);
2155 /* If we are XOR'ing with -1, then we should emit a one's complement
2156 instead. This way the combiner will notice logical operations
2157 such as ANDN later on and substitute. */
2158 if (trailing_bits
== 0x3ff)
2160 emit_insn (gen_rtx_SET (VOIDmode
, op0
,
2161 gen_rtx_NOT (DImode
, temp
)));
2165 emit_insn (gen_rtx_SET (VOIDmode
,
2167 gen_safe_XOR64 (temp
,
2168 (-0x400 | trailing_bits
))));
2173 /* 1) sethi %hi(xxx), %reg
2174 * or %reg, %lo(xxx), %reg
2175 * sllx %reg, yyy, %reg
2177 * ??? This is just a generalized version of the low_bits==0
2178 * thing above, FIXME...
2180 if ((highest_bit_set
- lowest_bit_set
) < 32)
2182 unsigned HOST_WIDE_INT focus_bits
=
2183 create_simple_focus_bits (high_bits
, low_bits
,
2186 /* We can't get here in this state. */
2187 if (highest_bit_set
< 32
2188 || lowest_bit_set
>= 32)
2191 /* So what we know is that the set bits straddle the
2192 middle of the 64-bit word. */
2193 sparc_emit_set_const64_quick2 (op0
, temp
,
2199 /* 1) sethi %hi(high_bits), %reg
2200 * or %reg, %lo(high_bits), %reg
2201 * sllx %reg, 32, %reg
2202 * or %reg, low_bits, %reg
2204 if (SPARC_SIMM13_P(low_bits
)
2205 && ((int)low_bits
> 0))
2207 sparc_emit_set_const64_quick2 (op0
, temp
, high_bits
, low_bits
, 32);
2211 /* The easiest way when all else fails, is full decomposition. */
2213 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2214 high_bits
, low_bits
, ~high_bits
, ~low_bits
);
2216 sparc_emit_set_const64_longway (op0
, temp
, high_bits
, low_bits
);
2219 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2220 return the mode to be used for the comparison. For floating-point,
2221 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2222 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2223 processing is needed. */
2226 select_cc_mode (op
, x
, y
)
2229 rtx y ATTRIBUTE_UNUSED
;
2231 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2257 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
2258 || GET_CODE (x
) == NEG
|| GET_CODE (x
) == ASHIFT
)
2260 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2261 return CCX_NOOVmode
;
2267 if (TARGET_ARCH64
&& GET_MODE (x
) == DImode
)
2274 /* X and Y are two things to compare using CODE. Emit the compare insn and
2275 return the rtx for the cc reg in the proper mode. */
2278 gen_compare_reg (code
, x
, y
)
2282 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
2285 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2286 fcc regs (cse can't tell they're really call clobbered regs and will
2287 remove a duplicate comparison even if there is an intervening function
2288 call - it will then try to reload the cc reg via an int reg which is why
2289 we need the movcc patterns). It is possible to provide the movcc
2290 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2291 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2292 to tell cse that CCFPE mode registers (even pseudos) are call
2295 /* ??? This is an experiment. Rather than making changes to cse which may
2296 or may not be easy/clean, we do our own cse. This is possible because
2297 we will generate hard registers. Cse knows they're call clobbered (it
2298 doesn't know the same thing about pseudos). If we guess wrong, no big
2299 deal, but if we win, great! */
2301 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2302 #if 1 /* experiment */
2305 /* We cycle through the registers to ensure they're all exercised. */
2306 static int next_fcc_reg
= 0;
2307 /* Previous x,y for each fcc reg. */
2308 static rtx prev_args
[4][2];
2310 /* Scan prev_args for x,y. */
2311 for (reg
= 0; reg
< 4; reg
++)
2312 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
2317 prev_args
[reg
][0] = x
;
2318 prev_args
[reg
][1] = y
;
2319 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
2321 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
2324 cc_reg
= gen_reg_rtx (mode
);
2325 #endif /* ! experiment */
2326 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2327 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
2329 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
2331 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
2332 gen_rtx_COMPARE (mode
, x
, y
)));
2337 /* This function is used for v9 only.
2338 CODE is the code for an Scc's comparison.
2339 OPERANDS[0] is the target of the Scc insn.
2340 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2341 been generated yet).
2343 This function is needed to turn
2346 (gt (reg:CCX 100 %icc)
2350 (gt:DI (reg:CCX 100 %icc)
2353 IE: The instruction recognizer needs to see the mode of the comparison to
2354 find the right instruction. We could use "gt:DI" right in the
2355 define_expand, but leaving it out allows us to handle DI, SI, etc.
2357 We refer to the global sparc compare operands sparc_compare_op0 and
2358 sparc_compare_op1. */
2361 gen_v9_scc (compare_code
, operands
)
2362 enum rtx_code compare_code
;
2363 register rtx
*operands
;
2368 && (GET_MODE (sparc_compare_op0
) == DImode
2369 || GET_MODE (operands
[0]) == DImode
))
2372 op0
= sparc_compare_op0
;
2373 op1
= sparc_compare_op1
;
2375 /* Try to use the movrCC insns. */
2377 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
2378 && op1
== const0_rtx
2379 && v9_regcmp_p (compare_code
))
2381 /* Special case for op0 != 0. This can be done with one instruction if
2382 operands[0] == sparc_compare_op0. */
2384 if (compare_code
== NE
2385 && GET_MODE (operands
[0]) == DImode
2386 && rtx_equal_p (op0
, operands
[0]))
2388 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2389 gen_rtx_IF_THEN_ELSE (DImode
,
2390 gen_rtx_fmt_ee (compare_code
, DImode
,
2397 if (reg_overlap_mentioned_p (operands
[0], op0
))
2399 /* Handle the case where operands[0] == sparc_compare_op0.
2400 We "early clobber" the result. */
2401 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
2402 emit_move_insn (op0
, sparc_compare_op0
);
2405 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2406 if (GET_MODE (op0
) != DImode
)
2408 temp
= gen_reg_rtx (DImode
);
2409 convert_move (temp
, op0
, 0);
2413 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2414 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2415 gen_rtx_fmt_ee (compare_code
, DImode
,
2423 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
2425 switch (GET_MODE (operands
[1]))
2435 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
2436 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
2437 gen_rtx_IF_THEN_ELSE (GET_MODE (operands
[0]),
2438 gen_rtx_fmt_ee (compare_code
,
2439 GET_MODE (operands
[1]),
2440 operands
[1], const0_rtx
),
2441 const1_rtx
, operands
[0])));
2446 /* Emit a conditional jump insn for the v9 architecture using comparison code
2447 CODE and jump target LABEL.
2448 This function exists to take advantage of the v9 brxx insns. */
2451 emit_v9_brxx_insn (code
, op0
, label
)
2455 emit_jump_insn (gen_rtx_SET (VOIDmode
,
2457 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2458 gen_rtx_fmt_ee (code
, GET_MODE (op0
),
2460 gen_rtx_LABEL_REF (VOIDmode
, label
),
2464 /* Generate a DFmode part of a hard TFmode register.
2465 REG is the TFmode hard register, LOW is 1 for the
2466 low 64bit of the register and 0 otherwise.
2469 gen_df_reg (reg
, low
)
2473 int regno
= REGNO (reg
);
2475 if ((WORDS_BIG_ENDIAN
== 0) ^ (low
!= 0))
2476 regno
+= (TARGET_ARCH64
&& regno
< 32) ? 1 : 2;
2477 return gen_rtx_REG (DFmode
, regno
);
2480 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2481 Unlike normal calls, TFmode operands are passed by reference. It is
2482 assumed that no more than 3 operands are required. */
2485 emit_soft_tfmode_libcall (func_name
, nargs
, operands
)
2486 const char *func_name
;
2490 rtx ret_slot
= NULL
, arg
[3], func_sym
;
2493 /* We only expect to be called for conversions, unary, and binary ops. */
2494 if (nargs
< 2 || nargs
> 3)
2497 for (i
= 0; i
< nargs
; ++i
)
2499 rtx this_arg
= operands
[i
];
2502 /* TFmode arguments and return values are passed by reference. */
2503 if (GET_MODE (this_arg
) == TFmode
)
2505 int force_stack_temp
;
2507 force_stack_temp
= 0;
2508 if (TARGET_BUGGY_QP_LIB
&& i
== 0)
2509 force_stack_temp
= 1;
2511 if (GET_CODE (this_arg
) == MEM
2512 && ! force_stack_temp
)
2513 this_arg
= XEXP (this_arg
, 0);
2514 else if (CONSTANT_P (this_arg
)
2515 && ! force_stack_temp
)
2517 this_slot
= force_const_mem (TFmode
, this_arg
);
2518 this_arg
= XEXP (this_slot
, 0);
2522 this_slot
= assign_stack_temp (TFmode
, GET_MODE_SIZE (TFmode
), 0);
2524 /* Operand 0 is the return value. We'll copy it out later. */
2526 emit_move_insn (this_slot
, this_arg
);
2528 ret_slot
= this_slot
;
2530 this_arg
= XEXP (this_slot
, 0);
2537 func_sym
= gen_rtx_SYMBOL_REF (Pmode
, func_name
);
2539 if (GET_MODE (operands
[0]) == TFmode
)
2542 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 2,
2543 arg
[0], GET_MODE (arg
[0]),
2544 arg
[1], GET_MODE (arg
[1]));
2546 emit_library_call (func_sym
, LCT_NORMAL
, VOIDmode
, 3,
2547 arg
[0], GET_MODE (arg
[0]),
2548 arg
[1], GET_MODE (arg
[1]),
2549 arg
[2], GET_MODE (arg
[2]));
2552 emit_move_insn (operands
[0], ret_slot
);
2561 ret
= emit_library_call_value (func_sym
, operands
[0], LCT_NORMAL
,
2562 GET_MODE (operands
[0]), 1,
2563 arg
[1], GET_MODE (arg
[1]));
2565 if (ret
!= operands
[0])
2566 emit_move_insn (operands
[0], ret
);
2570 /* Expand soft-float TFmode calls to sparc abi routines. */
2573 emit_soft_tfmode_binop (code
, operands
)
2597 emit_soft_tfmode_libcall (func
, 3, operands
);
2601 emit_soft_tfmode_unop (code
, operands
)
2616 emit_soft_tfmode_libcall (func
, 2, operands
);
2620 emit_soft_tfmode_cvt (code
, operands
)
2629 switch (GET_MODE (operands
[1]))
2642 case FLOAT_TRUNCATE
:
2643 switch (GET_MODE (operands
[0]))
2657 switch (GET_MODE (operands
[1]))
2670 case UNSIGNED_FLOAT
:
2671 switch (GET_MODE (operands
[1]))
2685 switch (GET_MODE (operands
[0]))
2699 switch (GET_MODE (operands
[0]))
2716 emit_soft_tfmode_libcall (func
, 2, operands
);
2719 /* Expand a hard-float tfmode operation. All arguments must be in
2723 emit_hard_tfmode_operation (code
, operands
)
2729 if (GET_RTX_CLASS (code
) == '1')
2731 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2732 op
= gen_rtx_fmt_e (code
, GET_MODE (operands
[0]), operands
[1]);
2736 operands
[1] = force_reg (GET_MODE (operands
[1]), operands
[1]);
2737 operands
[2] = force_reg (GET_MODE (operands
[2]), operands
[2]);
2738 op
= gen_rtx_fmt_ee (code
, GET_MODE (operands
[0]),
2739 operands
[1], operands
[2]);
2742 if (register_operand (operands
[0], VOIDmode
))
2745 dest
= gen_reg_rtx (GET_MODE (operands
[0]));
2747 emit_insn (gen_rtx_SET (VOIDmode
, dest
, op
));
2749 if (dest
!= operands
[0])
2750 emit_move_insn (operands
[0], dest
);
2754 emit_tfmode_binop (code
, operands
)
2758 if (TARGET_HARD_QUAD
)
2759 emit_hard_tfmode_operation (code
, operands
);
2761 emit_soft_tfmode_binop (code
, operands
);
2765 emit_tfmode_unop (code
, operands
)
2769 if (TARGET_HARD_QUAD
)
2770 emit_hard_tfmode_operation (code
, operands
);
2772 emit_soft_tfmode_unop (code
, operands
);
2776 emit_tfmode_cvt (code
, operands
)
2780 if (TARGET_HARD_QUAD
)
2781 emit_hard_tfmode_operation (code
, operands
);
2783 emit_soft_tfmode_cvt (code
, operands
);
2786 /* Return nonzero if a return peephole merging return with
2787 setting of output register is ok. */
2789 leaf_return_peephole_ok ()
2791 return (actual_fsize
== 0);
2794 /* Return nonzero if a branch/jump/call instruction will be emitting
2795 nop into its delay slot. */
2798 empty_delay_slot (insn
)
2803 /* If no previous instruction (should not happen), return true. */
2804 if (PREV_INSN (insn
) == NULL
)
2807 seq
= NEXT_INSN (PREV_INSN (insn
));
2808 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
2814 /* Return nonzero if TRIAL can go into the function epilogue's
2815 delay slot. SLOT is the slot we are trying to fill. */
2818 eligible_for_epilogue_delay (trial
, slot
)
2827 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2830 if (get_attr_length (trial
) != 1)
2833 /* If there are any call-saved registers, we should scan TRIAL if it
2834 does not reference them. For now just make it easy. */
2838 /* If the function uses __builtin_eh_return, the eh_return machinery
2839 occupies the delay slot. */
2840 if (current_function_calls_eh_return
)
2843 /* In the case of a true leaf function, anything can go into the delay slot.
2844 A delay slot only exists however if the frame size is zero, otherwise
2845 we will put an insn to adjust the stack after the return. */
2846 if (current_function_uses_only_leaf_regs
)
2848 if (leaf_return_peephole_ok ())
2849 return ((get_attr_in_uncond_branch_delay (trial
)
2850 == IN_BRANCH_DELAY_TRUE
));
2854 pat
= PATTERN (trial
);
2856 /* Otherwise, only operations which can be done in tandem with
2857 a `restore' or `return' insn can go into the delay slot. */
2858 if (GET_CODE (SET_DEST (pat
)) != REG
2859 || REGNO (SET_DEST (pat
)) < 24)
2862 /* If this instruction sets up floating point register and we have a return
2863 instruction, it can probably go in. But restore will not work
2865 if (REGNO (SET_DEST (pat
)) >= 32)
2867 if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2868 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2873 /* The set of insns matched here must agree precisely with the set of
2874 patterns paired with a RETURN in sparc.md. */
2876 src
= SET_SRC (pat
);
2878 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2879 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2880 && arith_operand (src
, GET_MODE (src
)))
2883 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2885 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2888 /* This matches "*return_di". */
2889 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2890 && arith_double_operand (src
, GET_MODE (src
)))
2891 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2893 /* This matches "*return_sf_no_fpu". */
2894 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
2895 && register_operand (src
, SFmode
))
2898 /* If we have return instruction, anything that does not use
2899 local or output registers and can go into a delay slot wins. */
2900 else if (TARGET_V9
&& ! epilogue_renumber (&pat
, 1)
2901 && (get_attr_in_uncond_branch_delay (trial
) == IN_BRANCH_DELAY_TRUE
))
2904 /* This matches "*return_addsi". */
2905 else if (GET_CODE (src
) == PLUS
2906 && arith_operand (XEXP (src
, 0), SImode
)
2907 && arith_operand (XEXP (src
, 1), SImode
)
2908 && (register_operand (XEXP (src
, 0), SImode
)
2909 || register_operand (XEXP (src
, 1), SImode
)))
2912 /* This matches "*return_adddi". */
2913 else if (GET_CODE (src
) == PLUS
2914 && arith_double_operand (XEXP (src
, 0), DImode
)
2915 && arith_double_operand (XEXP (src
, 1), DImode
)
2916 && (register_operand (XEXP (src
, 0), DImode
)
2917 || register_operand (XEXP (src
, 1), DImode
)))
2920 /* This can match "*return_losum_[sd]i".
2921 Catch only some cases, so that return_losum* don't have
2923 else if (GET_CODE (src
) == LO_SUM
2924 && ! TARGET_CM_MEDMID
2925 && ((register_operand (XEXP (src
, 0), SImode
)
2926 && immediate_operand (XEXP (src
, 1), SImode
))
2928 && register_operand (XEXP (src
, 0), DImode
)
2929 && immediate_operand (XEXP (src
, 1), DImode
))))
2932 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2933 else if (GET_CODE (src
) == ASHIFT
2934 && (register_operand (XEXP (src
, 0), SImode
)
2935 || register_operand (XEXP (src
, 0), DImode
))
2936 && XEXP (src
, 1) == const1_rtx
)
2942 /* Return nonzero if TRIAL can go into the sibling call
2946 eligible_for_sibcall_delay (trial
)
2951 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
2954 if (get_attr_length (trial
) != 1)
2957 pat
= PATTERN (trial
);
2959 if (current_function_uses_only_leaf_regs
)
2961 /* If the tail call is done using the call instruction,
2962 we have to restore %o7 in the delay slot. */
2963 if ((TARGET_ARCH64
&& ! TARGET_CM_MEDLOW
) || flag_pic
)
2966 /* %g1 is used to build the function address */
2967 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 1), pat
))
2973 /* Otherwise, only operations which can be done in tandem with
2974 a `restore' insn can go into the delay slot. */
2975 if (GET_CODE (SET_DEST (pat
)) != REG
2976 || REGNO (SET_DEST (pat
)) < 24
2977 || REGNO (SET_DEST (pat
)) >= 32)
2980 /* If it mentions %o7, it can't go in, because sibcall will clobber it
2982 if (reg_mentioned_p (gen_rtx_REG (Pmode
, 15), pat
))
2985 src
= SET_SRC (pat
);
2987 if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2988 && arith_operand (src
, GET_MODE (src
)))
2991 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
2993 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
2996 else if (GET_MODE_CLASS (GET_MODE (src
)) != MODE_FLOAT
2997 && arith_double_operand (src
, GET_MODE (src
)))
2998 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
3000 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
3001 && register_operand (src
, SFmode
))
3004 else if (GET_CODE (src
) == PLUS
3005 && arith_operand (XEXP (src
, 0), SImode
)
3006 && arith_operand (XEXP (src
, 1), SImode
)
3007 && (register_operand (XEXP (src
, 0), SImode
)
3008 || register_operand (XEXP (src
, 1), SImode
)))
3011 else if (GET_CODE (src
) == PLUS
3012 && arith_double_operand (XEXP (src
, 0), DImode
)
3013 && arith_double_operand (XEXP (src
, 1), DImode
)
3014 && (register_operand (XEXP (src
, 0), DImode
)
3015 || register_operand (XEXP (src
, 1), DImode
)))
3018 else if (GET_CODE (src
) == LO_SUM
3019 && ! TARGET_CM_MEDMID
3020 && ((register_operand (XEXP (src
, 0), SImode
)
3021 && immediate_operand (XEXP (src
, 1), SImode
))
3023 && register_operand (XEXP (src
, 0), DImode
)
3024 && immediate_operand (XEXP (src
, 1), DImode
))))
3027 else if (GET_CODE (src
) == ASHIFT
3028 && (register_operand (XEXP (src
, 0), SImode
)
3029 || register_operand (XEXP (src
, 0), DImode
))
3030 && XEXP (src
, 1) == const1_rtx
)
3037 check_return_regs (x
)
3040 switch (GET_CODE (x
))
3043 return IN_OR_GLOBAL_P (x
);
3058 if (check_return_regs (XEXP (x
, 1)) == 0)
3063 return check_return_regs (XEXP (x
, 0));
3072 short_branch (uid1
, uid2
)
3075 int delta
= INSN_ADDRESSES (uid1
) - INSN_ADDRESSES (uid2
);
3077 /* Leave a few words of "slop". */
3078 if (delta
>= -1023 && delta
<= 1022)
3084 /* Return nonzero if REG is not used after INSN.
3085 We assume REG is a reload reg, and therefore does
3086 not live past labels or calls or jumps. */
3088 reg_unused_after (reg
, insn
)
3092 enum rtx_code code
, prev_code
= UNKNOWN
;
3094 while ((insn
= NEXT_INSN (insn
)))
3096 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
3099 code
= GET_CODE (insn
);
3100 if (GET_CODE (insn
) == CODE_LABEL
)
3103 if (GET_RTX_CLASS (code
) == 'i')
3105 rtx set
= single_set (insn
);
3106 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
3109 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
3111 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
3119 /* The table we use to reference PIC data. */
3120 static GTY(()) rtx global_offset_table
;
3122 /* The function we use to get at it. */
3123 static GTY(()) rtx get_pc_symbol
;
3124 static char get_pc_symbol_name
[256];
3126 /* Ensure that we are not using patterns that are not OK with PIC. */
3135 if (GET_CODE (recog_data
.operand
[i
]) == SYMBOL_REF
3136 || (GET_CODE (recog_data
.operand
[i
]) == CONST
3137 && ! (GET_CODE (XEXP (recog_data
.operand
[i
], 0)) == MINUS
3138 && (XEXP (XEXP (recog_data
.operand
[i
], 0), 0)
3139 == global_offset_table
)
3140 && (GET_CODE (XEXP (XEXP (recog_data
.operand
[i
], 0), 1))
3149 /* Return true if X is an address which needs a temporary register when
3150 reloaded while generating PIC code. */
3153 pic_address_needs_scratch (x
)
3156 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3157 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
3158 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
3159 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3160 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
3166 /* Legitimize PIC addresses. If the address is already position-independent,
3167 we return ORIG. Newly generated position-independent addresses go into a
3168 reg. This is REG if nonzero, otherwise we allocate register(s) as
3172 legitimize_pic_address (orig
, mode
, reg
)
3174 enum machine_mode mode ATTRIBUTE_UNUSED
;
3177 if (GET_CODE (orig
) == SYMBOL_REF
)
3179 rtx pic_ref
, address
;
3184 if (reload_in_progress
|| reload_completed
)
3187 reg
= gen_reg_rtx (Pmode
);
3192 /* If not during reload, allocate another temp reg here for loading
3193 in the address, so that these instructions can be optimized
3195 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
3196 ? reg
: gen_reg_rtx (Pmode
));
3198 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3199 won't get confused into thinking that these two instructions
3200 are loading in the true address of the symbol. If in the
3201 future a PIC rtx exists, that should be used instead. */
3202 if (Pmode
== SImode
)
3204 emit_insn (gen_movsi_high_pic (temp_reg
, orig
));
3205 emit_insn (gen_movsi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3209 emit_insn (gen_movdi_high_pic (temp_reg
, orig
));
3210 emit_insn (gen_movdi_lo_sum_pic (temp_reg
, temp_reg
, orig
));
3217 pic_ref
= gen_rtx_MEM (Pmode
,
3218 gen_rtx_PLUS (Pmode
,
3219 pic_offset_table_rtx
, address
));
3220 current_function_uses_pic_offset_table
= 1;
3221 RTX_UNCHANGING_P (pic_ref
) = 1;
3222 insn
= emit_move_insn (reg
, pic_ref
);
3223 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3225 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
3229 else if (GET_CODE (orig
) == CONST
)
3233 if (GET_CODE (XEXP (orig
, 0)) == PLUS
3234 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
3239 if (reload_in_progress
|| reload_completed
)
3242 reg
= gen_reg_rtx (Pmode
);
3245 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
3247 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
3248 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
3249 base
== reg
? 0 : reg
);
3254 if (GET_CODE (offset
) == CONST_INT
)
3256 if (SMALL_INT (offset
))
3257 return plus_constant (base
, INTVAL (offset
));
3258 else if (! reload_in_progress
&& ! reload_completed
)
3259 offset
= force_reg (Pmode
, offset
);
3261 /* If we reach here, then something is seriously wrong. */
3264 return gen_rtx_PLUS (Pmode
, base
, offset
);
3266 else if (GET_CODE (orig
) == LABEL_REF
)
3267 /* ??? Why do we do this? */
3268 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3269 the register is live instead, in case it is eliminated. */
3270 current_function_uses_pic_offset_table
= 1;
3275 /* Emit special PIC prologues. */
3278 load_pic_register ()
3280 /* Labels to get the PC in the prologue of this function. */
3281 int orig_flag_pic
= flag_pic
;
3286 /* If we haven't emitted the special get_pc helper function, do so now. */
3287 if (get_pc_symbol_name
[0] == 0)
3291 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name
, "LGETPC", 0);
3294 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
3296 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
3297 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "LGETPC", 0);
3298 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file
);
3301 /* Initialize every time through, since we can't easily
3302 know this to be permanent. */
3303 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
3304 get_pc_symbol
= gen_rtx_SYMBOL_REF (Pmode
, get_pc_symbol_name
);
3307 emit_insn (gen_get_pc (pic_offset_table_rtx
, global_offset_table
,
3310 flag_pic
= orig_flag_pic
;
3312 /* Need to emit this whether or not we obey regdecls,
3313 since setjmp/longjmp can cause life info to screw up.
3314 ??? In the case where we don't obey regdecls, this is not sufficient
3315 since we may not fall out the bottom. */
3316 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
3319 /* Return 1 if RTX is a MEM which is known to be aligned to at
3320 least a DESIRED byte boundary. */
3323 mem_min_alignment (mem
, desired
)
3327 rtx addr
, base
, offset
;
3329 /* If it's not a MEM we can't accept it. */
3330 if (GET_CODE (mem
) != MEM
)
3333 addr
= XEXP (mem
, 0);
3334 base
= offset
= NULL_RTX
;
3335 if (GET_CODE (addr
) == PLUS
)
3337 if (GET_CODE (XEXP (addr
, 0)) == REG
)
3339 base
= XEXP (addr
, 0);
3341 /* What we are saying here is that if the base
3342 REG is aligned properly, the compiler will make
3343 sure any REG based index upon it will be so
3345 if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
3346 offset
= XEXP (addr
, 1);
3348 offset
= const0_rtx
;
3351 else if (GET_CODE (addr
) == REG
)
3354 offset
= const0_rtx
;
3357 if (base
!= NULL_RTX
)
3359 int regno
= REGNO (base
);
3361 if (regno
!= HARD_FRAME_POINTER_REGNUM
&& regno
!= STACK_POINTER_REGNUM
)
3363 /* Check if the compiler has recorded some information
3364 about the alignment of the base REG. If reload has
3365 completed, we already matched with proper alignments.
3366 If not running global_alloc, reload might give us
3367 unaligned pointer to local stack though. */
3369 && REGNO_POINTER_ALIGN (regno
) >= desired
* BITS_PER_UNIT
)
3370 || (optimize
&& reload_completed
))
3371 && (INTVAL (offset
) & (desired
- 1)) == 0)
3376 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & (desired
- 1)) == 0)
3380 else if (! TARGET_UNALIGNED_DOUBLES
3381 || CONSTANT_P (addr
)
3382 || GET_CODE (addr
) == LO_SUM
)
3384 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3385 is true, in which case we can only assume that an access is aligned if
3386 it is to a constant address, or the address involves a LO_SUM. */
3390 /* An obviously unaligned address. */
3395 /* Vectors to keep interesting information about registers where it can easily
3396 be got. We use to use the actual mode value as the bit number, but there
3397 are more than 32 modes now. Instead we use two tables: one indexed by
3398 hard register number, and one indexed by mode. */
3400 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3401 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3402 mapped into one sparc_mode_class mode. */
3404 enum sparc_mode_class
{
3405 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
3406 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
3410 /* Modes for single-word and smaller quantities. */
3411 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3413 /* Modes for double-word and smaller quantities. */
3414 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3416 /* Modes for quad-word and smaller quantities. */
3417 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3419 /* Modes for 8-word and smaller quantities. */
3420 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3422 /* Modes for single-float quantities. We must allow any single word or
3423 smaller quantity. This is because the fix/float conversion instructions
3424 take integer inputs/outputs from the float registers. */
3425 #define SF_MODES (S_MODES)
3427 /* Modes for double-float and smaller quantities. */
3428 #define DF_MODES (S_MODES | D_MODES)
3430 /* Modes for double-float only quantities. */
3431 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3433 /* Modes for quad-float only quantities. */
3434 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3436 /* Modes for quad-float and smaller quantities. */
3437 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3439 /* Modes for quad-float and double-float quantities. */
3440 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3442 /* Modes for quad-float pair only quantities. */
3443 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3445 /* Modes for quad-float pairs and smaller quantities. */
3446 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3448 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3450 /* Modes for condition codes. */
3451 #define CC_MODES (1 << (int) CC_MODE)
3452 #define CCFP_MODES (1 << (int) CCFP_MODE)
3454 /* Value is 1 if register/mode pair is acceptable on sparc.
3455 The funny mixture of D and T modes is because integer operations
3456 do not specially operate on tetra quantities, so non-quad-aligned
3457 registers can hold quadword quantities (except %o4 and %i4 because
3458 they cross fixed registers). */
3460 /* This points to either the 32 bit or the 64 bit version. */
3461 const int *hard_regno_mode_classes
;
3463 static const int hard_32bit_mode_classes
[] = {
3464 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3465 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3466 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
3467 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
3469 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3470 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3471 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3472 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3474 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3475 and none can hold SFmode/SImode values. */
3476 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3477 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3478 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3479 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3482 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3488 static const int hard_64bit_mode_classes
[] = {
3489 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3490 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3491 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3492 O_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3494 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3495 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3496 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3497 OF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
3499 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3500 and none can hold SFmode/SImode values. */
3501 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3502 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3503 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3504 OF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0, TF_MODES_NO_S
, 0, DF_MODES_NO_S
, 0,
3507 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3513 int sparc_mode_class
[NUM_MACHINE_MODES
];
3515 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3522 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3524 switch (GET_MODE_CLASS (i
))
3527 case MODE_PARTIAL_INT
:
3528 case MODE_COMPLEX_INT
:
3529 if (GET_MODE_SIZE (i
) <= 4)
3530 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3531 else if (GET_MODE_SIZE (i
) == 8)
3532 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3533 else if (GET_MODE_SIZE (i
) == 16)
3534 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3535 else if (GET_MODE_SIZE (i
) == 32)
3536 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3538 sparc_mode_class
[i
] = 0;
3541 case MODE_COMPLEX_FLOAT
:
3542 if (GET_MODE_SIZE (i
) <= 4)
3543 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3544 else if (GET_MODE_SIZE (i
) == 8)
3545 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3546 else if (GET_MODE_SIZE (i
) == 16)
3547 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3548 else if (GET_MODE_SIZE (i
) == 32)
3549 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3551 sparc_mode_class
[i
] = 0;
3555 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3556 we must explicitly check for them here. */
3557 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3558 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3559 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
3560 || i
== (int) CCXmode
|| i
== (int) CCX_NOOVmode
)
3561 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3563 sparc_mode_class
[i
] = 0;
3569 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3571 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3573 /* Initialize the array used by REGNO_REG_CLASS. */
3574 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3576 if (i
< 16 && TARGET_V8PLUS
)
3577 sparc_regno_reg_class
[i
] = I64_REGS
;
3578 else if (i
< 32 || i
== FRAME_POINTER_REGNUM
)
3579 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3581 sparc_regno_reg_class
[i
] = FP_REGS
;
3583 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3585 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3587 sparc_regno_reg_class
[i
] = NO_REGS
;
3591 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3592 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3593 v9 int regs as it simplifies the code. */
3596 save_regs (file
, low
, high
, base
, offset
, n_regs
, real_offset
)
3606 if (TARGET_ARCH64
&& high
<= 32)
3608 for (i
= low
; i
< high
; i
++)
3610 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3612 fprintf (file
, "\tstx\t%s, [%s+%d]\n",
3613 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3614 if (dwarf2out_do_frame ())
3615 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3622 for (i
= low
; i
< high
; i
+= 2)
3624 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3626 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3628 fprintf (file
, "\tstd\t%s, [%s+%d]\n",
3629 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3630 if (dwarf2out_do_frame ())
3632 char *l
= dwarf2out_cfi_label ();
3633 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
3634 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
3640 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3641 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3642 if (dwarf2out_do_frame ())
3643 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3649 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3651 fprintf (file
, "\tst\t%s, [%s+%d]\n",
3652 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
3653 if (dwarf2out_do_frame ())
3654 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
3663 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3665 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3666 v9 int regs as it simplifies the code. */
3669 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
3678 if (TARGET_ARCH64
&& high
<= 32)
3680 for (i
= low
; i
< high
; i
++)
3682 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3683 fprintf (file
, "\tldx\t[%s+%d], %s\n",
3684 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3690 for (i
= low
; i
< high
; i
+= 2)
3692 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3693 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3694 fprintf (file
, "\tldd\t[%s+%d], %s\n",
3695 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3698 fprintf (file
, "\tld\t[%s+%d], %s\n",
3699 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3701 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3702 fprintf (file
, "\tld\t[%s+%d], %s\n",
3703 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
3710 /* Compute the frame size required by the function. This function is called
3711 during the reload pass and also by output_function_prologue(). */
3714 compute_frame_size (size
, leaf_function
)
3719 int outgoing_args_size
= (current_function_outgoing_args_size
3720 + REG_PARM_STACK_SPACE (current_function_decl
));
3722 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3723 even to v9 int regs to be consistent with save_regs/restore_regs. */
3727 for (i
= 0; i
< 8; i
++)
3728 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3733 for (i
= 0; i
< 8; i
+= 2)
3734 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3735 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3739 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3740 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3741 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3744 /* Set up values for use in `function_epilogue'. */
3745 num_gfregs
= n_regs
;
3747 if (leaf_function
&& n_regs
== 0
3748 && size
== 0 && current_function_outgoing_args_size
== 0)
3750 actual_fsize
= apparent_fsize
= 0;
3754 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
3755 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ 7) & -8;
3756 apparent_fsize
+= n_regs
* 4;
3757 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3760 /* Make sure nothing can clobber our register windows.
3761 If a SAVE must be done, or there is a stack-local variable,
3762 the register window area must be allocated.
3763 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3764 if (leaf_function
== 0 || size
> 0)
3765 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
3767 return SPARC_STACK_ALIGN (actual_fsize
);
3770 /* Build a (32 bit) big number in a register. */
3771 /* ??? We may be able to use the set macro here too. */
3774 build_big_number (file
, num
, reg
)
3779 if (num
>= 0 || ! TARGET_ARCH64
)
3781 fprintf (file
, "\tsethi\t%%hi(%d), %s\n", num
, reg
);
3782 if ((num
& 0x3ff) != 0)
3783 fprintf (file
, "\tor\t%s, %%lo(%d), %s\n", reg
, num
, reg
);
3785 else /* num < 0 && TARGET_ARCH64 */
3787 /* Sethi does not sign extend, so we must use a little trickery
3788 to use it for negative numbers. Invert the constant before
3789 loading it in, then use xor immediate to invert the loaded bits
3790 (along with the upper 32 bits) to the desired constant. This
3791 works because the sethi and immediate fields overlap. */
3794 int low
= -0x400 + (asize
& 0x3FF);
3796 fprintf (file
, "\tsethi\t%%hi(%d), %s\n\txor\t%s, %d, %s\n",
3797 inv
, reg
, reg
, low
, reg
);
3801 /* Output any necessary .register pseudo-ops. */
3803 sparc_output_scratch_registers (file
)
3804 FILE *file ATTRIBUTE_UNUSED
;
3806 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
3812 /* Check if %g[2367] were used without
3813 .register being printed for them already. */
3814 for (i
= 2; i
< 8; i
++)
3816 if (regs_ever_live
[i
]
3817 && ! sparc_hard_reg_printed
[i
])
3819 sparc_hard_reg_printed
[i
] = 1;
3820 fprintf (file
, "\t.register\t%%g%d, #scratch\n", i
);
3827 /* This function generates the assembly code for function entry.
3828 FILE is a stdio stream to output the code to.
3829 SIZE is an int: how many units of temporary storage to allocate.
3830 Refer to the array `regs_ever_live' to determine which registers
3831 to save; `regs_ever_live[I]' is nonzero if register number I
3832 is ever used in the function. This macro is responsible for
3833 knowing which registers should not be saved even if used. */
3835 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
3836 of memory. If any fpu reg is used in the function, we allocate
3837 such a block here, at the bottom of the frame, just in case it's needed.
3839 If this function is a leaf procedure, then we may choose not
3840 to do a "save" insn. The decision about whether or not
3841 to do this is made in regclass.c. */
3844 sparc_output_function_prologue (file
, size
)
3849 sparc_flat_function_prologue (file
, size
);
3851 sparc_nonflat_function_prologue (file
, size
,
3852 current_function_uses_only_leaf_regs
);
3855 /* Output code for the function prologue. */
3858 sparc_nonflat_function_prologue (file
, size
, leaf_function
)
3863 sparc_output_scratch_registers (file
);
3865 /* Need to use actual_fsize, since we are also allocating
3866 space for our callee (and our own register save area). */
3867 actual_fsize
= compute_frame_size (size
, leaf_function
);
3871 frame_base_name
= "%sp";
3872 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3876 frame_base_name
= "%fp";
3877 frame_base_offset
= SPARC_STACK_BIAS
;
3880 /* This is only for the human reader. */
3881 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
3883 if (actual_fsize
== 0)
3885 else if (! leaf_function
)
3887 if (actual_fsize
<= 4096)
3888 fprintf (file
, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize
);
3889 else if (actual_fsize
<= 8192)
3891 fprintf (file
, "\tsave\t%%sp, -4096, %%sp\n");
3892 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3896 build_big_number (file
, -actual_fsize
, "%g1");
3897 fprintf (file
, "\tsave\t%%sp, %%g1, %%sp\n");
3900 else /* leaf function */
3902 if (actual_fsize
<= 4096)
3903 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
);
3904 else if (actual_fsize
<= 8192)
3906 fprintf (file
, "\tadd\t%%sp, -4096, %%sp\n");
3907 fprintf (file
, "\tadd\t%%sp, -%d, %%sp\n", actual_fsize
- 4096);
3911 build_big_number (file
, -actual_fsize
, "%g1");
3912 fprintf (file
, "\tadd\t%%sp, %%g1, %%sp\n");
3916 if (dwarf2out_do_frame () && actual_fsize
)
3918 char *label
= dwarf2out_cfi_label ();
3920 /* The canonical frame address refers to the top of the frame. */
3921 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
3922 : HARD_FRAME_POINTER_REGNUM
),
3925 if (! leaf_function
)
3927 /* Note the register window save. This tells the unwinder that
3928 it needs to restore the window registers from the previous
3929 frame's window save area at 0(cfa). */
3930 dwarf2out_window_save (label
);
3932 /* The return address (-8) is now in %i7. */
3933 dwarf2out_return_reg (label
, 31);
3937 /* If doing anything with PIC, do it now. */
3939 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
3941 /* Call saved registers are saved just above the outgoing argument area. */
3944 int offset
, real_offset
, n_regs
;
3947 real_offset
= -apparent_fsize
;
3948 offset
= -apparent_fsize
+ frame_base_offset
;
3949 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
3951 /* ??? This might be optimized a little as %g1 might already have a
3952 value close enough that a single add insn will do. */
3953 /* ??? Although, all of this is probably only a temporary fix
3954 because if %g1 can hold a function result, then
3955 output_function_epilogue will lose (the result will get
3957 build_big_number (file
, offset
, "%g1");
3958 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3964 base
= frame_base_name
;
3967 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3968 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
3973 /* Output code to restore any call saved registers. */
3976 output_restore_regs (file
, leaf_function
)
3978 int leaf_function ATTRIBUTE_UNUSED
;
3983 offset
= -apparent_fsize
+ frame_base_offset
;
3984 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
3986 build_big_number (file
, offset
, "%g1");
3987 fprintf (file
, "\tadd\t%s, %%g1, %%g1\n", frame_base_name
);
3993 base
= frame_base_name
;
3996 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3997 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
4000 /* This function generates the assembly code for function exit,
4001 on machines that need it.
4003 The function epilogue should not depend on the current stack pointer!
4004 It should use the frame pointer only. This is mandatory because
4005 of alloca; we also take advantage of it to omit stack adjustments
4006 before returning. */
4009 sparc_output_function_epilogue (file
, size
)
4014 sparc_flat_function_epilogue (file
, size
);
4016 sparc_nonflat_function_epilogue (file
, size
,
4017 current_function_uses_only_leaf_regs
);
4020 /* Output code for the function epilogue. */
4023 sparc_nonflat_function_epilogue (file
, size
, leaf_function
)
4025 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
4030 if (current_function_epilogue_delay_list
== 0)
4032 /* If code does not drop into the epilogue, we need
4033 do nothing except output pending case vectors.
4035 We have to still output a dummy nop for the sake of
4036 sane backtraces. Otherwise, if the last two instructions
4037 of a function were call foo; dslot; this can make the return
4038 PC of foo (ie. address of call instruction plus 8) point to
4039 the first instruction in the next function. */
4042 fputs("\tnop\n", file
);
4044 insn
= get_last_insn ();
4045 if (GET_CODE (insn
) == NOTE
)
4046 insn
= prev_nonnote_insn (insn
);
4047 if (insn
&& GET_CODE (insn
) == BARRIER
)
4048 goto output_vectors
;
4052 output_restore_regs (file
, leaf_function
);
4054 /* Work out how to skip the caller's unimp instruction if required. */
4056 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%o7+12" : "retl");
4058 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp\t%i7+12" : "ret");
4060 if (! leaf_function
)
4062 if (current_function_calls_eh_return
)
4064 if (current_function_epilogue_delay_list
)
4066 if (SKIP_CALLERS_UNIMP_P
)
4069 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file
);
4071 /* If we wound up with things in our delay slot, flush them here. */
4072 else if (current_function_epilogue_delay_list
)
4074 rtx delay
= PATTERN (XEXP (current_function_epilogue_delay_list
, 0));
4076 if (TARGET_V9
&& ! epilogue_renumber (&delay
, 1))
4078 epilogue_renumber (&delay
, 0);
4079 fputs (SKIP_CALLERS_UNIMP_P
4080 ? "\treturn\t%i7+12\n"
4081 : "\treturn\t%i7+8\n", file
);
4082 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4089 if (GET_CODE (delay
) != SET
)
4092 src
= SET_SRC (delay
);
4093 if (GET_CODE (src
) == ASHIFT
)
4095 if (XEXP (src
, 1) != const1_rtx
)
4098 = gen_rtx_PLUS (GET_MODE (src
), XEXP (src
, 0),
4102 insn
= gen_rtx_PARALLEL (VOIDmode
,
4103 gen_rtvec (2, delay
,
4104 gen_rtx_RETURN (VOIDmode
)));
4105 insn
= emit_jump_insn (insn
);
4107 sparc_emitting_epilogue
= true;
4108 final_scan_insn (insn
, file
, 1, 0, 1);
4109 sparc_emitting_epilogue
= false;
4112 else if (TARGET_V9
&& ! SKIP_CALLERS_UNIMP_P
)
4113 fputs ("\treturn\t%i7+8\n\tnop\n", file
);
4115 fprintf (file
, "\t%s\n\trestore\n", ret
);
4117 /* All of the following cases are for leaf functions. */
4118 else if (current_function_calls_eh_return
)
4120 else if (current_function_epilogue_delay_list
)
4122 /* eligible_for_epilogue_delay_slot ensures that if this is a
4123 leaf function, then we will only have insn in the delay slot
4124 if the frame size is zero, thus no adjust for the stack is
4126 if (actual_fsize
!= 0)
4128 fprintf (file
, "\t%s\n", ret
);
4129 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
4132 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4133 avoid generating confusing assembly language output. */
4134 else if (actual_fsize
== 0)
4135 fprintf (file
, "\t%s\n\tnop\n", ret
);
4136 else if (actual_fsize
<= 4096)
4137 fprintf (file
, "\t%s\n\tsub\t%%sp, -%d, %%sp\n", ret
, actual_fsize
);
4138 else if (actual_fsize
<= 8192)
4139 fprintf (file
, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -%d, %%sp\n",
4140 ret
, actual_fsize
- 4096);
4141 else if ((actual_fsize
& 0x3ff) == 0)
4142 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4145 fprintf (file
, "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n\t%s\n\tadd\t%%sp, %%g1, %%sp\n",
4146 actual_fsize
, actual_fsize
, ret
);
4149 sparc_output_deferred_case_vectors ();
4152 /* Output a sibling call. */
4155 output_sibcall (insn
, call_operand
)
4156 rtx insn
, call_operand
;
4158 int leaf_regs
= current_function_uses_only_leaf_regs
;
4160 int delay_slot
= dbr_sequence_length () > 0;
4164 /* Call to restore global regs might clobber
4165 the delay slot. Instead of checking for this
4166 output the delay slot now. */
4169 rtx delay
= NEXT_INSN (insn
);
4174 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
4175 PATTERN (delay
) = gen_blockage ();
4176 INSN_CODE (delay
) = -1;
4179 output_restore_regs (asm_out_file
, leaf_regs
);
4182 operands
[0] = call_operand
;
4186 #ifdef HAVE_AS_RELAX_OPTION
4187 /* If as and ld are relaxing tail call insns into branch always,
4188 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4189 be optimized. With sethi/jmpl as nor ld has no easy way how to
4190 find out if somebody does not branch between the sethi and jmpl. */
4193 int spare_slot
= ((TARGET_ARCH32
|| TARGET_CM_MEDLOW
) && ! flag_pic
);
4197 if ((actual_fsize
|| ! spare_slot
) && delay_slot
)
4199 rtx delay
= NEXT_INSN (insn
);
4204 final_scan_insn (delay
, asm_out_file
, 1, 0, 1);
4205 PATTERN (delay
) = gen_blockage ();
4206 INSN_CODE (delay
) = -1;
4211 if (actual_fsize
<= 4096)
4212 size
= actual_fsize
;
4213 else if (actual_fsize
<= 8192)
4215 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file
);
4216 size
= actual_fsize
- 4096;
4218 else if ((actual_fsize
& 0x3ff) == 0)
4219 fprintf (asm_out_file
,
4220 "\tsethi\t%%hi(%d), %%g1\n\tadd\t%%sp, %%g1, %%sp\n",
4224 fprintf (asm_out_file
,
4225 "\tsethi\t%%hi(%d), %%g1\n\tor\t%%g1, %%lo(%d), %%g1\n",
4226 actual_fsize
, actual_fsize
);
4227 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file
);
4232 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands
);
4233 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands
);
4235 fprintf (asm_out_file
, "\t sub\t%%sp, -%d, %%sp\n", size
);
4236 else if (! delay_slot
)
4237 fputs ("\t nop\n", asm_out_file
);
4242 fprintf (asm_out_file
, "\tsub\t%%sp, -%d, %%sp\n", size
);
4243 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4244 it into branch if possible. */
4245 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands
);
4246 output_asm_insn ("call\t%a0, 0", operands
);
4247 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands
);
4252 output_asm_insn ("call\t%a0, 0", operands
);
4255 rtx delay
= NEXT_INSN (insn
), pat
;
4260 pat
= PATTERN (delay
);
4261 if (GET_CODE (pat
) != SET
)
4264 operands
[0] = SET_DEST (pat
);
4265 pat
= SET_SRC (pat
);
4266 switch (GET_CODE (pat
))
4269 operands
[1] = XEXP (pat
, 0);
4270 operands
[2] = XEXP (pat
, 1);
4271 output_asm_insn (" restore %r1, %2, %Y0", operands
);
4274 operands
[1] = XEXP (pat
, 0);
4275 operands
[2] = XEXP (pat
, 1);
4276 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands
);
4279 operands
[1] = XEXP (pat
, 0);
4280 output_asm_insn (" restore %r1, %r1, %Y0", operands
);
4284 output_asm_insn (" restore %%g0, %1, %Y0", operands
);
4287 PATTERN (delay
) = gen_blockage ();
4288 INSN_CODE (delay
) = -1;
4291 fputs ("\t restore\n", asm_out_file
);
4295 /* Functions for handling argument passing.
4297 For v8 the first six args are normally in registers and the rest are
4298 pushed. Any arg that starts within the first 6 words is at least
4299 partially passed in a register unless its data type forbids.
4301 For v9, the argument registers are laid out as an array of 16 elements
4302 and arguments are added sequentially. The first 6 int args and up to the
4303 first 16 fp args (depending on size) are passed in regs.
4305 Slot Stack Integral Float Float in structure Double Long Double
4306 ---- ----- -------- ----- ------------------ ------ -----------
4307 15 [SP+248] %f31 %f30,%f31 %d30
4308 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4309 13 [SP+232] %f27 %f26,%f27 %d26
4310 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4311 11 [SP+216] %f23 %f22,%f23 %d22
4312 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4313 9 [SP+200] %f19 %f18,%f19 %d18
4314 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4315 7 [SP+184] %f15 %f14,%f15 %d14
4316 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4317 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4318 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4319 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4320 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4321 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4322 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4324 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4326 Integral arguments are always passed as 64 bit quantities appropriately
4329 Passing of floating point values is handled as follows.
4330 If a prototype is in scope:
4331 If the value is in a named argument (i.e. not a stdarg function or a
4332 value not part of the `...') then the value is passed in the appropriate
4334 If the value is part of the `...' and is passed in one of the first 6
4335 slots then the value is passed in the appropriate int reg.
4336 If the value is part of the `...' and is not passed in one of the first 6
4337 slots then the value is passed in memory.
4338 If a prototype is not in scope:
4339 If the value is one of the first 6 arguments the value is passed in the
4340 appropriate integer reg and the appropriate fp reg.
4341 If the value is not one of the first 6 arguments the value is passed in
4342 the appropriate fp reg and in memory.
4345 /* Maximum number of int regs for args. */
4346 #define SPARC_INT_ARG_MAX 6
4347 /* Maximum number of fp regs for args. */
4348 #define SPARC_FP_ARG_MAX 16
4350 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4352 /* Handle the INIT_CUMULATIVE_ARGS macro.
4353 Initialize a variable CUM of type CUMULATIVE_ARGS
4354 for a call to a function whose data type is FNTYPE.
4355 For a library call, FNTYPE is 0. */
4358 init_cumulative_args (cum
, fntype
, libname
, indirect
)
4359 CUMULATIVE_ARGS
*cum
;
4361 rtx libname ATTRIBUTE_UNUSED
;
4362 int indirect ATTRIBUTE_UNUSED
;
4365 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
4366 cum
->libcall_p
= fntype
== 0;
4369 /* Compute the slot number to pass an argument in.
4370 Returns the slot number or -1 if passing on the stack.
4372 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4373 the preceding args and about the function being called.
4374 MODE is the argument's machine mode.
4375 TYPE is the data type of the argument (as a tree).
4376 This is null for libcalls where that information may
4378 NAMED is nonzero if this argument is a named parameter
4379 (otherwise it is an extra parameter matching an ellipsis).
4380 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4381 *PREGNO records the register number to use if scalar type.
4382 *PPADDING records the amount of padding needed in words. */
4385 function_arg_slotno (cum
, mode
, type
, named
, incoming_p
, pregno
, ppadding
)
4386 const CUMULATIVE_ARGS
*cum
;
4387 enum machine_mode mode
;
4394 int regbase
= (incoming_p
4395 ? SPARC_INCOMING_INT_ARG_FIRST
4396 : SPARC_OUTGOING_INT_ARG_FIRST
);
4397 int slotno
= cum
->words
;
4402 if (type
!= 0 && TREE_ADDRESSABLE (type
))
4405 && type
!= 0 && mode
== BLKmode
4406 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
4412 /* MODE is VOIDmode when generating the actual call.
4416 case QImode
: case CQImode
:
4417 case HImode
: case CHImode
:
4418 case SImode
: case CSImode
:
4419 case DImode
: case CDImode
:
4420 case TImode
: case CTImode
:
4421 if (slotno
>= SPARC_INT_ARG_MAX
)
4423 regno
= regbase
+ slotno
;
4426 case SFmode
: case SCmode
:
4427 case DFmode
: case DCmode
:
4428 case TFmode
: case TCmode
:
4431 if (slotno
>= SPARC_INT_ARG_MAX
)
4433 regno
= regbase
+ slotno
;
4437 if ((mode
== TFmode
|| mode
== TCmode
)
4438 && (slotno
& 1) != 0)
4439 slotno
++, *ppadding
= 1;
4440 if (TARGET_FPU
&& named
)
4442 if (slotno
>= SPARC_FP_ARG_MAX
)
4444 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
4450 if (slotno
>= SPARC_INT_ARG_MAX
)
4452 regno
= regbase
+ slotno
;
4458 /* For sparc64, objects requiring 16 byte alignment get it. */
4461 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
4462 slotno
++, *ppadding
= 1;
4466 || (type
&& TREE_CODE (type
) == UNION_TYPE
))
4468 if (slotno
>= SPARC_INT_ARG_MAX
)
4470 regno
= regbase
+ slotno
;
4475 int intregs_p
= 0, fpregs_p
= 0;
4476 /* The ABI obviously doesn't specify how packed
4477 structures are passed. These are defined to be passed
4478 in int regs if possible, otherwise memory. */
4481 /* First see what kinds of registers we need. */
4482 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4484 if (TREE_CODE (field
) == FIELD_DECL
)
4486 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4491 if (DECL_PACKED (field
))
4495 if (packed_p
|| !named
)
4496 fpregs_p
= 0, intregs_p
= 1;
4498 /* If all arg slots are filled, then must pass on stack. */
4499 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
4501 /* If there are only int args and all int arg slots are filled,
4502 then must pass on stack. */
4503 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
4505 /* Note that even if all int arg slots are filled, fp members may
4506 still be passed in regs if such regs are available.
4507 *PREGNO isn't set because there may be more than one, it's up
4508 to the caller to compute them. */
4521 /* Handle recursive register counting for structure field layout. */
4523 struct function_arg_record_value_parms
4526 int slotno
, named
, regbase
;
4531 static void function_arg_record_value_3
4532 PARAMS ((HOST_WIDE_INT
, struct function_arg_record_value_parms
*));
4533 static void function_arg_record_value_2
4534 PARAMS ((tree
, HOST_WIDE_INT
,
4535 struct function_arg_record_value_parms
*));
4536 static void function_arg_record_value_1
4537 PARAMS ((tree
, HOST_WIDE_INT
,
4538 struct function_arg_record_value_parms
*));
4539 static rtx function_arg_record_value
4540 PARAMS ((tree
, enum machine_mode
, int, int, int));
4542 /* A subroutine of function_arg_record_value. Traverse the structure
4543 recusively and determine how many registers will be required. */
4546 function_arg_record_value_1 (type
, startbitpos
, parms
)
4548 HOST_WIDE_INT startbitpos
;
4549 struct function_arg_record_value_parms
*parms
;
4553 /* The ABI obviously doesn't specify how packed structures are
4554 passed. These are defined to be passed in int regs if possible,
4555 otherwise memory. */
4558 /* We need to compute how many registers are needed so we can
4559 allocate the PARALLEL but before we can do that we need to know
4560 whether there are any packed fields. If there are, int regs are
4561 used regardless of whether there are fp values present. */
4562 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4564 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4571 /* Compute how many registers we need. */
4572 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4574 if (TREE_CODE (field
) == FIELD_DECL
)
4576 HOST_WIDE_INT bitpos
= startbitpos
;
4578 if (DECL_SIZE (field
) != 0
4579 && host_integerp (bit_position (field
), 1))
4580 bitpos
+= int_bit_position (field
);
4582 /* ??? FIXME: else assume zero offset. */
4584 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4585 function_arg_record_value_1 (TREE_TYPE (field
), bitpos
, parms
);
4586 else if ((TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4587 || (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
4588 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field
)))
4594 if (parms
->intoffset
!= -1)
4596 int intslots
, this_slotno
;
4598 intslots
= (bitpos
- parms
->intoffset
+ BITS_PER_WORD
- 1)
4600 this_slotno
= parms
->slotno
+ parms
->intoffset
4603 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4604 intslots
= MAX (intslots
, 0);
4605 parms
->nregs
+= intslots
;
4606 parms
->intoffset
= -1;
4609 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
4610 If it wasn't true we wouldn't be here. */
4612 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4617 if (parms
->intoffset
== -1)
4618 parms
->intoffset
= bitpos
;
4624 /* A subroutine of function_arg_record_value. Assign the bits of the
4625 structure between parms->intoffset and bitpos to integer registers. */
4628 function_arg_record_value_3 (bitpos
, parms
)
4629 HOST_WIDE_INT bitpos
;
4630 struct function_arg_record_value_parms
*parms
;
4632 enum machine_mode mode
;
4634 unsigned int startbit
, endbit
;
4635 int this_slotno
, intslots
, intoffset
;
4638 if (parms
->intoffset
== -1)
4641 intoffset
= parms
->intoffset
;
4642 parms
->intoffset
= -1;
4644 startbit
= intoffset
& -BITS_PER_WORD
;
4645 endbit
= (bitpos
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4646 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4647 this_slotno
= parms
->slotno
+ intoffset
/ BITS_PER_WORD
;
4649 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4653 /* If this is the trailing part of a word, only load that much into
4654 the register. Otherwise load the whole register. Note that in
4655 the latter case we may pick up unwanted bits. It's not a problem
4656 at the moment but may wish to revisit. */
4658 if (intoffset
% BITS_PER_WORD
!= 0)
4659 mode
= mode_for_size (BITS_PER_WORD
- intoffset
% BITS_PER_WORD
,
4664 intoffset
/= BITS_PER_UNIT
;
4667 regno
= parms
->regbase
+ this_slotno
;
4668 reg
= gen_rtx_REG (mode
, regno
);
4669 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4670 = gen_rtx_EXPR_LIST (VOIDmode
, reg
, GEN_INT (intoffset
));
4673 intoffset
= (intoffset
| (UNITS_PER_WORD
-1)) + 1;
4677 while (intslots
> 0);
4680 /* A subroutine of function_arg_record_value. Traverse the structure
4681 recursively and assign bits to floating point registers. Track which
4682 bits in between need integer registers; invoke function_arg_record_value_3
4683 to make that happen. */
4686 function_arg_record_value_2 (type
, startbitpos
, parms
)
4688 HOST_WIDE_INT startbitpos
;
4689 struct function_arg_record_value_parms
*parms
;
4694 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4696 if (TREE_CODE (field
) == FIELD_DECL
&& DECL_PACKED (field
))
4703 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
4705 if (TREE_CODE (field
) == FIELD_DECL
)
4707 HOST_WIDE_INT bitpos
= startbitpos
;
4709 if (DECL_SIZE (field
) != 0
4710 && host_integerp (bit_position (field
), 1))
4711 bitpos
+= int_bit_position (field
);
4713 /* ??? FIXME: else assume zero offset. */
4715 if (TREE_CODE (TREE_TYPE (field
)) == RECORD_TYPE
)
4716 function_arg_record_value_2 (TREE_TYPE (field
), bitpos
, parms
);
4717 else if ((TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
4718 || (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
4719 && (TREE_CODE (TREE_TYPE (TREE_TYPE (field
)))
4725 int this_slotno
= parms
->slotno
+ bitpos
/ BITS_PER_WORD
;
4727 enum machine_mode mode
= DECL_MODE (field
);
4730 function_arg_record_value_3 (bitpos
, parms
);
4731 regno
= SPARC_FP_ARG_FIRST
+ this_slotno
* 2
4732 + ((mode
== SFmode
|| mode
== SCmode
)
4733 && (bitpos
& 32) != 0);
4736 case SCmode
: mode
= SFmode
; break;
4737 case DCmode
: mode
= DFmode
; break;
4738 case TCmode
: mode
= TFmode
; break;
4741 reg
= gen_rtx_REG (mode
, regno
);
4742 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4743 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4744 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4746 if (TREE_CODE (TREE_TYPE (field
)) == COMPLEX_TYPE
)
4748 regno
+= GET_MODE_SIZE (mode
) / 4;
4749 reg
= gen_rtx_REG (mode
, regno
);
4750 XVECEXP (parms
->ret
, 0, parms
->nregs
)
4751 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4752 GEN_INT ((bitpos
+ GET_MODE_BITSIZE (mode
))
4759 if (parms
->intoffset
== -1)
4760 parms
->intoffset
= bitpos
;
4766 /* Used by function_arg and function_value to implement the complex
4767 SPARC64 structure calling conventions. */
4770 function_arg_record_value (type
, mode
, slotno
, named
, regbase
)
4772 enum machine_mode mode
;
4773 int slotno
, named
, regbase
;
4775 HOST_WIDE_INT typesize
= int_size_in_bytes (type
);
4776 struct function_arg_record_value_parms parms
;
4779 parms
.ret
= NULL_RTX
;
4780 parms
.slotno
= slotno
;
4781 parms
.named
= named
;
4782 parms
.regbase
= regbase
;
4784 /* Compute how many registers we need. */
4786 parms
.intoffset
= 0;
4787 function_arg_record_value_1 (type
, 0, &parms
);
4789 if (parms
.intoffset
!= -1)
4791 unsigned int startbit
, endbit
;
4792 int intslots
, this_slotno
;
4794 startbit
= parms
.intoffset
& -BITS_PER_WORD
;
4795 endbit
= (typesize
*BITS_PER_UNIT
+ BITS_PER_WORD
- 1) & -BITS_PER_WORD
;
4796 intslots
= (endbit
- startbit
) / BITS_PER_WORD
;
4797 this_slotno
= slotno
+ parms
.intoffset
/ BITS_PER_WORD
;
4799 intslots
= MIN (intslots
, SPARC_INT_ARG_MAX
- this_slotno
);
4800 intslots
= MAX (intslots
, 0);
4802 parms
.nregs
+= intslots
;
4804 nregs
= parms
.nregs
;
4806 /* Allocate the vector and handle some annoying special cases. */
4809 /* ??? Empty structure has no value? Duh? */
4812 /* Though there's nothing really to store, return a word register
4813 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
4814 leads to breakage due to the fact that there are zero bytes to
4816 return gen_rtx_REG (mode
, regbase
);
4820 /* ??? C++ has structures with no fields, and yet a size. Give up
4821 for now and pass everything back in integer registers. */
4822 nregs
= (typesize
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
4824 if (nregs
+ slotno
> SPARC_INT_ARG_MAX
)
4825 nregs
= SPARC_INT_ARG_MAX
- slotno
;
4830 parms
.ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (nregs
));
4832 /* Fill in the entries. */
4834 parms
.intoffset
= 0;
4835 function_arg_record_value_2 (type
, 0, &parms
);
4836 function_arg_record_value_3 (typesize
* BITS_PER_UNIT
, &parms
);
4838 if (parms
.nregs
!= nregs
)
4844 /* Handle the FUNCTION_ARG macro.
4845 Determine where to put an argument to a function.
4846 Value is zero to push the argument on the stack,
4847 or a hard register in which to store the argument.
4849 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4850 the preceding args and about the function being called.
4851 MODE is the argument's machine mode.
4852 TYPE is the data type of the argument (as a tree).
4853 This is null for libcalls where that information may
4855 NAMED is nonzero if this argument is a named parameter
4856 (otherwise it is an extra parameter matching an ellipsis).
4857 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
4860 function_arg (cum
, mode
, type
, named
, incoming_p
)
4861 const CUMULATIVE_ARGS
*cum
;
4862 enum machine_mode mode
;
4867 int regbase
= (incoming_p
4868 ? SPARC_INCOMING_INT_ARG_FIRST
4869 : SPARC_OUTGOING_INT_ARG_FIRST
);
4870 int slotno
, regno
, padding
;
4873 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
4881 reg
= gen_rtx_REG (mode
, regno
);
4885 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
4886 but also have the slot allocated for them.
4887 If no prototype is in scope fp values in register slots get passed
4888 in two places, either fp regs and int regs or fp regs and memory. */
4889 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
4890 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4891 && SPARC_FP_REG_P (regno
))
4893 reg
= gen_rtx_REG (mode
, regno
);
4894 if (cum
->prototype_p
|| cum
->libcall_p
)
4896 /* "* 2" because fp reg numbers are recorded in 4 byte
4899 /* ??? This will cause the value to be passed in the fp reg and
4900 in the stack. When a prototype exists we want to pass the
4901 value in the reg but reserve space on the stack. That's an
4902 optimization, and is deferred [for a bit]. */
4903 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
4904 return gen_rtx_PARALLEL (mode
,
4906 gen_rtx_EXPR_LIST (VOIDmode
,
4907 NULL_RTX
, const0_rtx
),
4908 gen_rtx_EXPR_LIST (VOIDmode
,
4912 /* ??? It seems that passing back a register even when past
4913 the area declared by REG_PARM_STACK_SPACE will allocate
4914 space appropriately, and will not copy the data onto the
4915 stack, exactly as we desire.
4917 This is due to locate_and_pad_parm being called in
4918 expand_call whenever reg_parm_stack_space > 0, which
4919 while benefical to our example here, would seem to be
4920 in error from what had been intended. Ho hum... -- r~ */
4928 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
4932 /* On incoming, we don't need to know that the value
4933 is passed in %f0 and %i0, and it confuses other parts
4934 causing needless spillage even on the simplest cases. */
4938 intreg
= (SPARC_OUTGOING_INT_ARG_FIRST
4939 + (regno
- SPARC_FP_ARG_FIRST
) / 2);
4941 v0
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4942 v1
= gen_rtx_EXPR_LIST (VOIDmode
, gen_rtx_REG (mode
, intreg
),
4944 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4948 v0
= gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
4949 v1
= gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
);
4950 return gen_rtx_PARALLEL (mode
, gen_rtvec (2, v0
, v1
));
4954 else if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
4956 /* Structures up to 16 bytes in size are passed in arg slots on the
4957 stack and are promoted to registers where possible. */
4959 if (int_size_in_bytes (type
) > 16)
4960 abort (); /* shouldn't get here */
4962 return function_arg_record_value (type
, mode
, slotno
, named
, regbase
);
4964 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
4966 enum machine_mode mode
;
4967 int bytes
= int_size_in_bytes (type
);
4972 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4973 reg
= gen_rtx_REG (mode
, regno
);
4977 /* Scalar or complex int. */
4978 reg
= gen_rtx_REG (mode
, regno
);
4984 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4985 For an arg passed partly in registers and partly in memory,
4986 this is the number of registers used.
4987 For args passed entirely in registers or entirely in memory, zero.
4989 Any arg that starts in the first 6 regs but won't entirely fit in them
4990 needs partial registers on v8. On v9, structures with integer
4991 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4992 values that begin in the last fp reg [where "last fp reg" varies with the
4993 mode] will be split between that reg and memory. */
4996 function_arg_partial_nregs (cum
, mode
, type
, named
)
4997 const CUMULATIVE_ARGS
*cum
;
4998 enum machine_mode mode
;
5002 int slotno
, regno
, padding
;
5004 /* We pass 0 for incoming_p here, it doesn't matter. */
5005 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5012 if ((slotno
+ (mode
== BLKmode
5013 ? ROUND_ADVANCE (int_size_in_bytes (type
))
5014 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
5015 > NPARM_REGS (SImode
))
5016 return NPARM_REGS (SImode
) - slotno
;
5021 if (type
&& AGGREGATE_TYPE_P (type
))
5023 int size
= int_size_in_bytes (type
);
5024 int align
= TYPE_ALIGN (type
);
5027 slotno
+= slotno
& 1;
5028 if (size
> 8 && size
<= 16
5029 && slotno
== SPARC_INT_ARG_MAX
- 1)
5032 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
5033 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
5036 if (GET_MODE_ALIGNMENT (mode
) == 128)
5038 slotno
+= slotno
& 1;
5039 if (slotno
== SPARC_INT_ARG_MAX
- 2)
5044 if (slotno
== SPARC_INT_ARG_MAX
- 1)
5048 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5050 if (GET_MODE_ALIGNMENT (mode
) == 128)
5051 slotno
+= slotno
& 1;
5052 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
5060 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5061 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5062 quad-precision floats by invisible reference.
5063 v9: Aggregates greater than 16 bytes are passed by reference.
5064 For Pascal, also pass arrays by reference. */
5067 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5068 const CUMULATIVE_ARGS
*cum ATTRIBUTE_UNUSED
;
5069 enum machine_mode mode
;
5071 int named ATTRIBUTE_UNUSED
;
5075 return ((type
&& AGGREGATE_TYPE_P (type
))
5076 || mode
== TFmode
|| mode
== TCmode
);
5080 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
5081 /* Consider complex values as aggregates, so care for TCmode. */
5082 || GET_MODE_SIZE (mode
) > 16
5084 && AGGREGATE_TYPE_P (type
)
5085 && (unsigned HOST_WIDE_INT
) int_size_in_bytes (type
) > 16));
5089 /* Handle the FUNCTION_ARG_ADVANCE macro.
5090 Update the data in CUM to advance over an argument
5091 of mode MODE and data type TYPE.
5092 TYPE is null for libcalls where that information may not be available. */
5095 function_arg_advance (cum
, mode
, type
, named
)
5096 CUMULATIVE_ARGS
*cum
;
5097 enum machine_mode mode
;
5101 int slotno
, regno
, padding
;
5103 /* We pass 0 for incoming_p here, it doesn't matter. */
5104 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
5106 /* If register required leading padding, add it. */
5108 cum
->words
+= padding
;
5112 cum
->words
+= (mode
!= BLKmode
5113 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5114 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5118 if (type
&& AGGREGATE_TYPE_P (type
))
5120 int size
= int_size_in_bytes (type
);
5124 else if (size
<= 16)
5126 else /* passed by reference */
5129 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
5133 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
5135 cum
->words
+= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
5139 cum
->words
+= (mode
!= BLKmode
5140 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
5141 : ROUND_ADVANCE (int_size_in_bytes (type
)));
5146 /* Handle the FUNCTION_ARG_PADDING macro.
5147 For the 64 bit ABI structs are always stored left shifted in their
5151 function_arg_padding (mode
, type
)
5152 enum machine_mode mode
;
5155 if (TARGET_ARCH64
&& type
!= 0 && AGGREGATE_TYPE_P (type
))
5158 /* This is the default definition. */
5159 return (! BYTES_BIG_ENDIAN
5162 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
5163 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
5164 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
5165 ? downward
: upward
));
5168 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5169 For v9, function return values are subject to the same rules as arguments,
5170 except that up to 32-bytes may be returned in registers. */
5173 function_value (type
, mode
, incoming_p
)
5175 enum machine_mode mode
;
5179 int regbase
= (incoming_p
5180 ? SPARC_OUTGOING_INT_ARG_FIRST
5181 : SPARC_INCOMING_INT_ARG_FIRST
);
5183 if (TARGET_ARCH64
&& type
)
5185 if (TREE_CODE (type
) == RECORD_TYPE
)
5187 /* Structures up to 32 bytes in size are passed in registers,
5188 promoted to fp registers where possible. */
5190 if (int_size_in_bytes (type
) > 32)
5191 abort (); /* shouldn't get here */
5193 return function_arg_record_value (type
, mode
, 0, 1, regbase
);
5195 else if (AGGREGATE_TYPE_P (type
))
5197 /* All other aggregate types are passed in an integer register
5198 in a mode corresponding to the size of the type. */
5199 HOST_WIDE_INT bytes
= int_size_in_bytes (type
);
5204 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
5209 && GET_MODE_CLASS (mode
) == MODE_INT
5210 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5211 && type
&& ! AGGREGATE_TYPE_P (type
))
5215 regno
= BASE_RETURN_VALUE_REG (mode
);
5217 regno
= BASE_OUTGOING_VALUE_REG (mode
);
5219 return gen_rtx_REG (mode
, regno
);
5222 /* Do what is necessary for `va_start'. We look at the current function
5223 to determine if stdarg or varargs is used and return the address of
5224 the first unnamed parameter. */
5227 sparc_builtin_saveregs ()
5229 int first_reg
= current_function_args_info
.words
;
5233 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
5234 emit_move_insn (gen_rtx_MEM (word_mode
,
5235 gen_rtx_PLUS (Pmode
,
5237 GEN_INT (FIRST_PARM_OFFSET (0)
5240 gen_rtx_REG (word_mode
,
5241 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
5243 address
= gen_rtx_PLUS (Pmode
,
5245 GEN_INT (FIRST_PARM_OFFSET (0)
5246 + UNITS_PER_WORD
* first_reg
));
5251 /* Implement `va_start' for varargs and stdarg. */
5254 sparc_va_start (valist
, nextarg
)
5258 nextarg
= expand_builtin_saveregs ();
5259 std_expand_builtin_va_start (valist
, nextarg
);
5262 /* Implement `va_arg'. */
5265 sparc_va_arg (valist
, type
)
5268 HOST_WIDE_INT size
, rsize
, align
;
5273 /* Round up sizeof(type) to a word. */
5274 size
= int_size_in_bytes (type
);
5275 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
5280 if (TYPE_ALIGN (type
) >= 2 * (unsigned) BITS_PER_WORD
)
5281 align
= 2 * UNITS_PER_WORD
;
5283 if (AGGREGATE_TYPE_P (type
))
5285 if ((unsigned HOST_WIDE_INT
) size
> 16)
5288 size
= rsize
= UNITS_PER_WORD
;
5290 /* SPARC v9 ABI states that structures up to 8 bytes in size are
5291 given one 8 byte slot. */
5293 size
= rsize
= UNITS_PER_WORD
;
5300 if (AGGREGATE_TYPE_P (type
)
5301 || TYPE_MODE (type
) == TFmode
5302 || TYPE_MODE (type
) == TCmode
)
5305 size
= rsize
= UNITS_PER_WORD
;
5312 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5313 build_int_2 (align
- 1, 0)));
5314 incr
= fold (build (BIT_AND_EXPR
, ptr_type_node
, incr
,
5315 build_int_2 (-align
, -1)));
5318 addr
= incr
= save_expr (incr
);
5319 if (BYTES_BIG_ENDIAN
&& size
< rsize
)
5321 addr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5322 build_int_2 (rsize
- size
, 0)));
5324 incr
= fold (build (PLUS_EXPR
, ptr_type_node
, incr
,
5325 build_int_2 (rsize
, 0)));
5327 incr
= build (MODIFY_EXPR
, ptr_type_node
, valist
, incr
);
5328 TREE_SIDE_EFFECTS (incr
) = 1;
5329 expand_expr (incr
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
5331 addr_rtx
= expand_expr (addr
, NULL
, Pmode
, EXPAND_NORMAL
);
5333 /* If the address isn't aligned properly for the type,
5334 we may need to copy to a temporary.
5335 FIXME: This is inefficient. Usually we can do this
5338 && TYPE_ALIGN (type
) > BITS_PER_WORD
5341 /* FIXME: We really need to specify that the temporary is live
5342 for the whole function because expand_builtin_va_arg wants
5343 the alias set to be get_varargs_alias_set (), but in this
5344 case the alias set is that for TYPE and if the memory gets
5345 reused it will be reused with alias set TYPE. */
5346 rtx tmp
= assign_temp (type
, 0, 1, 0);
5349 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5350 addr_rtx
= gen_rtx_MEM (BLKmode
, addr_rtx
);
5351 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5352 set_mem_align (addr_rtx
, BITS_PER_WORD
);
5353 tmp
= shallow_copy_rtx (tmp
);
5354 PUT_MODE (tmp
, BLKmode
);
5355 set_mem_alias_set (tmp
, 0);
5357 dest_addr
= emit_block_move (tmp
, addr_rtx
, GEN_INT (rsize
),
5359 if (dest_addr
!= NULL_RTX
)
5360 addr_rtx
= dest_addr
;
5362 addr_rtx
= XCEXP (tmp
, 0, MEM
);
5367 addr_rtx
= force_reg (Pmode
, addr_rtx
);
5368 addr_rtx
= gen_rtx_MEM (Pmode
, addr_rtx
);
5369 set_mem_alias_set (addr_rtx
, get_varargs_alias_set ());
5375 /* Return the string to output a conditional branch to LABEL, which is
5376 the operand number of the label. OP is the conditional expression.
5377 XEXP (OP, 0) is assumed to be a condition code register (integer or
5378 floating point) and its mode specifies what kind of comparison we made.
5380 REVERSED is nonzero if we should reverse the sense of the comparison.
5382 ANNUL is nonzero if we should generate an annulling branch.
5384 NOOP is nonzero if we have to follow this branch by a noop.
5386 INSN, if set, is the insn. */
5389 output_cbranch (op
, dest
, label
, reversed
, annul
, noop
, insn
)
5392 int reversed
, annul
, noop
;
5395 static char string
[50];
5396 enum rtx_code code
= GET_CODE (op
);
5397 rtx cc_reg
= XEXP (op
, 0);
5398 enum machine_mode mode
= GET_MODE (cc_reg
);
5399 const char *labelno
, *branch
;
5400 int spaces
= 8, far
;
5403 /* v9 branches are limited to +-1MB. If it is too far away,
5416 fbne,a,pn %fcc2, .LC29
5424 far
= get_attr_length (insn
) >= 3;
5427 /* Reversal of FP compares takes care -- an ordered compare
5428 becomes an unordered compare and vice versa. */
5429 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5430 code
= reverse_condition_maybe_unordered (code
);
5432 code
= reverse_condition (code
);
5435 /* Start by writing the branch condition. */
5436 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5487 /* ??? !v9: FP branches cannot be preceded by another floating point
5488 insn. Because there is currently no concept of pre-delay slots,
5489 we can fix this only by always emitting a nop before a floating
5494 strcpy (string
, "nop\n\t");
5495 strcat (string
, branch
);
5508 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5520 if (mode
== CC_NOOVmode
|| mode
== CCX_NOOVmode
)
5541 strcpy (string
, branch
);
5543 spaces
-= strlen (branch
);
5544 p
= strchr (string
, '\0');
5546 /* Now add the annulling, the label, and a possible noop. */
5561 if (! far
&& insn
&& INSN_ADDRESSES_SET_P ())
5563 int delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5564 - INSN_ADDRESSES (INSN_UID (insn
)));
5565 /* Leave some instructions for "slop". */
5566 if (delta
< -260000 || delta
>= 260000)
5570 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
5572 static char v9_fcc_labelno
[] = "%%fccX, ";
5573 /* Set the char indicating the number of the fcc reg to use. */
5574 v9_fcc_labelno
[5] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
5575 labelno
= v9_fcc_labelno
;
5578 if (REGNO (cc_reg
) == SPARC_FCC_REG
)
5584 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
5586 labelno
= "%%xcc, ";
5592 labelno
= "%%icc, ";
5597 if (*labelno
&& insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5600 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5610 strcpy (p
, labelno
);
5611 p
= strchr (p
, '\0');
5614 strcpy (p
, ".+12\n\tnop\n\tb\t");
5621 /* Set the char indicating the number of the operand containing the
5626 strcpy (p
, "\n\tnop");
5631 /* Emit a library call comparison between floating point X and Y.
5632 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
5633 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
5634 values as arguments instead of the TFmode registers themselves,
5635 that's why we cannot call emit_float_lib_cmp. */
5637 sparc_emit_float_lib_cmp (x
, y
, comparison
)
5639 enum rtx_code comparison
;
5642 rtx slot0
, slot1
, result
, tem
, tem2
;
5643 enum machine_mode mode
;
5648 qpfunc
= (TARGET_ARCH64
) ? "_Qp_feq" : "_Q_feq";
5652 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fne" : "_Q_fne";
5656 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fgt" : "_Q_fgt";
5660 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fge" : "_Q_fge";
5664 qpfunc
= (TARGET_ARCH64
) ? "_Qp_flt" : "_Q_flt";
5668 qpfunc
= (TARGET_ARCH64
) ? "_Qp_fle" : "_Q_fle";
5679 qpfunc
= (TARGET_ARCH64
) ? "_Qp_cmp" : "_Q_cmp";
5689 if (GET_CODE (x
) != MEM
)
5691 slot0
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5692 emit_insn (gen_rtx_SET (VOIDmode
, slot0
, x
));
5697 if (GET_CODE (y
) != MEM
)
5699 slot1
= assign_stack_temp (TFmode
, GET_MODE_SIZE(TFmode
), 0);
5700 emit_insn (gen_rtx_SET (VOIDmode
, slot1
, y
));
5705 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5707 XEXP (slot0
, 0), Pmode
,
5708 XEXP (slot1
, 0), Pmode
);
5714 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, qpfunc
), LCT_NORMAL
,
5716 x
, TFmode
, y
, TFmode
);
5722 /* Immediately move the result of the libcall into a pseudo
5723 register so reload doesn't clobber the value if it needs
5724 the return register for a spill reg. */
5725 result
= gen_reg_rtx (mode
);
5726 emit_move_insn (result
, hard_libcall_value (mode
));
5731 emit_cmp_insn (result
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
5735 emit_cmp_insn (result
, GEN_INT(3), comparison
== UNORDERED
? EQ
: NE
,
5740 emit_cmp_insn (result
, const1_rtx
,
5741 comparison
== UNGT
? GT
: NE
, NULL_RTX
, mode
, 0);
5744 emit_cmp_insn (result
, const2_rtx
, NE
, NULL_RTX
, mode
, 0);
5747 tem
= gen_reg_rtx (mode
);
5749 emit_insn (gen_andsi3 (tem
, result
, const1_rtx
));
5751 emit_insn (gen_anddi3 (tem
, result
, const1_rtx
));
5752 emit_cmp_insn (tem
, const0_rtx
, NE
, NULL_RTX
, mode
, 0);
5756 tem
= gen_reg_rtx (mode
);
5758 emit_insn (gen_addsi3 (tem
, result
, const1_rtx
));
5760 emit_insn (gen_adddi3 (tem
, result
, const1_rtx
));
5761 tem2
= gen_reg_rtx (mode
);
5763 emit_insn (gen_andsi3 (tem2
, tem
, const2_rtx
));
5765 emit_insn (gen_anddi3 (tem2
, tem
, const2_rtx
));
5766 emit_cmp_insn (tem2
, const0_rtx
, comparison
== UNEQ
? EQ
: NE
,
5772 /* Generate an unsigned DImode to FP conversion. This is the same code
5773 optabs would emit if we didn't have TFmode patterns. */
5776 sparc_emit_floatunsdi (operands
)
5779 rtx neglab
, donelab
, i0
, i1
, f0
, in
, out
;
5780 enum machine_mode mode
;
5783 in
= force_reg (DImode
, operands
[1]);
5784 mode
= GET_MODE (out
);
5785 neglab
= gen_label_rtx ();
5786 donelab
= gen_label_rtx ();
5787 i0
= gen_reg_rtx (DImode
);
5788 i1
= gen_reg_rtx (DImode
);
5789 f0
= gen_reg_rtx (mode
);
5791 emit_cmp_and_jump_insns (in
, const0_rtx
, LT
, const0_rtx
, DImode
, 0, neglab
);
5793 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_FLOAT (mode
, in
)));
5794 emit_jump_insn (gen_jump (donelab
));
5797 emit_label (neglab
);
5799 emit_insn (gen_lshrdi3 (i0
, in
, const1_rtx
));
5800 emit_insn (gen_anddi3 (i1
, in
, const1_rtx
));
5801 emit_insn (gen_iordi3 (i0
, i0
, i1
));
5802 emit_insn (gen_rtx_SET (VOIDmode
, f0
, gen_rtx_FLOAT (mode
, i0
)));
5803 emit_insn (gen_rtx_SET (VOIDmode
, out
, gen_rtx_PLUS (mode
, f0
, f0
)));
5805 emit_label (donelab
);
5808 /* Return the string to output a conditional branch to LABEL, testing
5809 register REG. LABEL is the operand number of the label; REG is the
5810 operand number of the reg. OP is the conditional expression. The mode
5811 of REG says what kind of comparison we made.
5813 REVERSED is nonzero if we should reverse the sense of the comparison.
5815 ANNUL is nonzero if we should generate an annulling branch.
5817 NOOP is nonzero if we have to follow this branch by a noop. */
5820 output_v9branch (op
, dest
, reg
, label
, reversed
, annul
, noop
, insn
)
5823 int reversed
, annul
, noop
;
5826 static char string
[50];
5827 enum rtx_code code
= GET_CODE (op
);
5828 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
5833 /* branch on register are limited to +-128KB. If it is too far away,
5846 brgez,a,pn %o1, .LC29
5852 ba,pt %xcc, .LC29 */
5854 far
= get_attr_length (insn
) >= 3;
5856 /* If not floating-point or if EQ or NE, we can just reverse the code. */
5858 code
= reverse_condition (code
);
5860 /* Only 64 bit versions of these instructions exist. */
5864 /* Start by writing the branch condition. */
5869 strcpy (string
, "brnz");
5873 strcpy (string
, "brz");
5877 strcpy (string
, "brgez");
5881 strcpy (string
, "brlz");
5885 strcpy (string
, "brlez");
5889 strcpy (string
, "brgz");
5896 p
= strchr (string
, '\0');
5898 /* Now add the annulling, reg, label, and nop. */
5905 if (insn
&& (note
= find_reg_note (insn
, REG_BR_PROB
, NULL_RTX
)))
5908 ((INTVAL (XEXP (note
, 0)) >= REG_BR_PROB_BASE
/ 2) ^ far
)
5913 *p
= p
< string
+ 8 ? '\t' : ' ';
5921 int veryfar
= 1, delta
;
5923 if (INSN_ADDRESSES_SET_P ())
5925 delta
= (INSN_ADDRESSES (INSN_UID (dest
))
5926 - INSN_ADDRESSES (INSN_UID (insn
)));
5927 /* Leave some instructions for "slop". */
5928 if (delta
>= -260000 && delta
< 260000)
5932 strcpy (p
, ".+12\n\tnop\n\t");
5943 strcpy (p
, "ba,pt\t%%xcc, ");
5953 strcpy (p
, "\n\tnop");
5958 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
5959 Such instructions cannot be used in the delay slot of return insn on v9.
5960 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
5964 epilogue_renumber (where
, test
)
5965 register rtx
*where
;
5968 register const char *fmt
;
5970 register enum rtx_code code
;
5975 code
= GET_CODE (*where
);
5980 if (REGNO (*where
) >= 8 && REGNO (*where
) < 24) /* oX or lX */
5982 if (! test
&& REGNO (*where
) >= 24 && REGNO (*where
) < 32)
5983 *where
= gen_rtx (REG
, GET_MODE (*where
), OUTGOING_REGNO (REGNO(*where
)));
5991 /* Do not replace the frame pointer with the stack pointer because
5992 it can cause the delayed instruction to load below the stack.
5993 This occurs when instructions like:
5995 (set (reg/i:SI 24 %i0)
5996 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
5997 (const_int -20 [0xffffffec])) 0))
5999 are in the return delayed slot. */
6001 if (GET_CODE (XEXP (*where
, 0)) == REG
6002 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
6003 && (GET_CODE (XEXP (*where
, 1)) != CONST_INT
6004 || INTVAL (XEXP (*where
, 1)) < SPARC_STACK_BIAS
))
6009 if (SPARC_STACK_BIAS
6010 && GET_CODE (XEXP (*where
, 0)) == REG
6011 && REGNO (XEXP (*where
, 0)) == HARD_FRAME_POINTER_REGNUM
)
6019 fmt
= GET_RTX_FORMAT (code
);
6021 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6026 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
6027 if (epilogue_renumber (&(XVECEXP (*where
, i
, j
)), test
))
6030 else if (fmt
[i
] == 'e'
6031 && epilogue_renumber (&(XEXP (*where
, i
)), test
))
6037 /* Leaf functions and non-leaf functions have different needs. */
6040 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
6043 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
6045 static const int *const reg_alloc_orders
[] = {
6046 reg_leaf_alloc_order
,
6047 reg_nonleaf_alloc_order
};
6050 order_regs_for_local_alloc ()
6052 static int last_order_nonleaf
= 1;
6054 if (regs_ever_live
[15] != last_order_nonleaf
)
6056 last_order_nonleaf
= !last_order_nonleaf
;
6057 memcpy ((char *) reg_alloc_order
,
6058 (const char *) reg_alloc_orders
[last_order_nonleaf
],
6059 FIRST_PSEUDO_REGISTER
* sizeof (int));
6063 /* Return 1 if REG and MEM are legitimate enough to allow the various
6064 mem<-->reg splits to be run. */
6067 sparc_splitdi_legitimate (reg
, mem
)
6071 /* Punt if we are here by mistake. */
6072 if (! reload_completed
)
6075 /* We must have an offsettable memory reference. */
6076 if (! offsettable_memref_p (mem
))
6079 /* If we have legitimate args for ldd/std, we do not want
6080 the split to happen. */
6081 if ((REGNO (reg
) % 2) == 0
6082 && mem_min_alignment (mem
, 8))
6089 /* Return 1 if x and y are some kind of REG and they refer to
6090 different hard registers. This test is guarenteed to be
6091 run after reload. */
6094 sparc_absnegfloat_split_legitimate (x
, y
)
6097 if (GET_CODE (x
) != REG
)
6099 if (GET_CODE (y
) != REG
)
6101 if (REGNO (x
) == REGNO (y
))
6106 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6107 This makes them candidates for using ldd and std insns.
6109 Note reg1 and reg2 *must* be hard registers. */
6112 registers_ok_for_ldd_peep (reg1
, reg2
)
6115 /* We might have been passed a SUBREG. */
6116 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
6119 if (REGNO (reg1
) % 2 != 0)
6122 /* Integer ldd is deprecated in SPARC V9 */
6123 if (TARGET_V9
&& REGNO (reg1
) < 32)
6126 return (REGNO (reg1
) == REGNO (reg2
) - 1);
6129 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6132 This can only happen when addr1 and addr2, the addresses in mem1
6133 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6134 addr1 must also be aligned on a 64-bit boundary.
6136 Also iff dependent_reg_rtx is not null it should not be used to
6137 compute the address for mem1, i.e. we cannot optimize a sequence
6149 But, note that the transformation from:
6154 is perfectly fine. Thus, the peephole2 patterns always pass us
6155 the destination register of the first load, never the second one.
6157 For stores we don't have a similar problem, so dependent_reg_rtx is
6161 mems_ok_for_ldd_peep (mem1
, mem2
, dependent_reg_rtx
)
6162 rtx mem1
, mem2
, dependent_reg_rtx
;
6168 /* The mems cannot be volatile. */
6169 if (MEM_VOLATILE_P (mem1
) || MEM_VOLATILE_P (mem2
))
6172 /* MEM1 should be aligned on a 64-bit boundary. */
6173 if (MEM_ALIGN (mem1
) < 64)
6176 addr1
= XEXP (mem1
, 0);
6177 addr2
= XEXP (mem2
, 0);
6179 /* Extract a register number and offset (if used) from the first addr. */
6180 if (GET_CODE (addr1
) == PLUS
)
6182 /* If not a REG, return zero. */
6183 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
6187 reg1
= REGNO (XEXP (addr1
, 0));
6188 /* The offset must be constant! */
6189 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
6191 offset1
= INTVAL (XEXP (addr1
, 1));
6194 else if (GET_CODE (addr1
) != REG
)
6198 reg1
= REGNO (addr1
);
6199 /* This was a simple (mem (reg)) expression. Offset is 0. */
6203 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6204 if (GET_CODE (addr2
) != PLUS
)
6207 if (GET_CODE (XEXP (addr2
, 0)) != REG
6208 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
6211 if (reg1
!= REGNO (XEXP (addr2
, 0)))
6214 if (dependent_reg_rtx
!= NULL_RTX
&& reg1
== REGNO (dependent_reg_rtx
))
6217 /* The first offset must be evenly divisible by 8 to ensure the
6218 address is 64 bit aligned. */
6219 if (offset1
% 8 != 0)
6222 /* The offset for the second addr must be 4 more than the first addr. */
6223 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
6226 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6231 /* Return 1 if reg is a pseudo, or is the first register in
6232 a hard register pair. This makes it a candidate for use in
6233 ldd and std insns. */
6236 register_ok_for_ldd (reg
)
6239 /* We might have been passed a SUBREG. */
6240 if (GET_CODE (reg
) != REG
)
6243 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
6244 return (REGNO (reg
) % 2 == 0);
6249 /* Print operand X (an rtx) in assembler syntax to file FILE.
6250 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6251 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6254 print_operand (file
, x
, code
)
6262 /* Output a 'nop' if there's nothing for the delay slot. */
6263 if (dbr_sequence_length () == 0)
6264 fputs ("\n\t nop", file
);
6267 /* Output an annul flag if there's nothing for the delay slot and we
6268 are optimizing. This is always used with '(' below. */
6269 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6270 this is a dbx bug. So, we only do this when optimizing. */
6271 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6272 Always emit a nop in case the next instruction is a branch. */
6273 if (dbr_sequence_length () == 0
6274 && (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6278 /* Output a 'nop' if there's nothing for the delay slot and we are
6279 not optimizing. This is always used with '*' above. */
6280 if (dbr_sequence_length () == 0
6281 && ! (optimize
&& (int)sparc_cpu
< PROCESSOR_V9
))
6282 fputs ("\n\t nop", file
);
6285 /* Output the Embedded Medium/Anywhere code model base register. */
6286 fputs (EMBMEDANY_BASE_REG
, file
);
6289 /* Print out what we are using as the frame pointer. This might
6290 be %fp, or might be %sp+offset. */
6291 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6292 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
6295 /* Adjust the operand to take into account a RESTORE operation. */
6296 if (GET_CODE (x
) == CONST_INT
)
6298 else if (GET_CODE (x
) != REG
)
6299 output_operand_lossage ("invalid %%Y operand");
6300 else if (REGNO (x
) < 8)
6301 fputs (reg_names
[REGNO (x
)], file
);
6302 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
6303 fputs (reg_names
[REGNO (x
)-16], file
);
6305 output_operand_lossage ("invalid %%Y operand");
6308 /* Print out the low order register name of a register pair. */
6309 if (WORDS_BIG_ENDIAN
)
6310 fputs (reg_names
[REGNO (x
)+1], file
);
6312 fputs (reg_names
[REGNO (x
)], file
);
6315 /* Print out the high order register name of a register pair. */
6316 if (WORDS_BIG_ENDIAN
)
6317 fputs (reg_names
[REGNO (x
)], file
);
6319 fputs (reg_names
[REGNO (x
)+1], file
);
6322 /* Print out the second register name of a register pair or quad.
6323 I.e., R (%o0) => %o1. */
6324 fputs (reg_names
[REGNO (x
)+1], file
);
6327 /* Print out the third register name of a register quad.
6328 I.e., S (%o0) => %o2. */
6329 fputs (reg_names
[REGNO (x
)+2], file
);
6332 /* Print out the fourth register name of a register quad.
6333 I.e., T (%o0) => %o3. */
6334 fputs (reg_names
[REGNO (x
)+3], file
);
6337 /* Print a condition code register. */
6338 if (REGNO (x
) == SPARC_ICC_REG
)
6340 /* We don't handle CC[X]_NOOVmode because they're not supposed
6342 if (GET_MODE (x
) == CCmode
)
6343 fputs ("%icc", file
);
6344 else if (GET_MODE (x
) == CCXmode
)
6345 fputs ("%xcc", file
);
6350 /* %fccN register */
6351 fputs (reg_names
[REGNO (x
)], file
);
6354 /* Print the operand's address only. */
6355 output_address (XEXP (x
, 0));
6358 /* In this case we need a register. Use %g0 if the
6359 operand is const0_rtx. */
6361 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
6363 fputs ("%g0", file
);
6370 switch (GET_CODE (x
))
6372 case IOR
: fputs ("or", file
); break;
6373 case AND
: fputs ("and", file
); break;
6374 case XOR
: fputs ("xor", file
); break;
6375 default: output_operand_lossage ("invalid %%A operand");
6380 switch (GET_CODE (x
))
6382 case IOR
: fputs ("orn", file
); break;
6383 case AND
: fputs ("andn", file
); break;
6384 case XOR
: fputs ("xnor", file
); break;
6385 default: output_operand_lossage ("invalid %%B operand");
6389 /* These are used by the conditional move instructions. */
6393 enum rtx_code rc
= GET_CODE (x
);
6397 enum machine_mode mode
= GET_MODE (XEXP (x
, 0));
6398 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
6399 rc
= reverse_condition_maybe_unordered (GET_CODE (x
));
6401 rc
= reverse_condition (GET_CODE (x
));
6405 case NE
: fputs ("ne", file
); break;
6406 case EQ
: fputs ("e", file
); break;
6407 case GE
: fputs ("ge", file
); break;
6408 case GT
: fputs ("g", file
); break;
6409 case LE
: fputs ("le", file
); break;
6410 case LT
: fputs ("l", file
); break;
6411 case GEU
: fputs ("geu", file
); break;
6412 case GTU
: fputs ("gu", file
); break;
6413 case LEU
: fputs ("leu", file
); break;
6414 case LTU
: fputs ("lu", file
); break;
6415 case LTGT
: fputs ("lg", file
); break;
6416 case UNORDERED
: fputs ("u", file
); break;
6417 case ORDERED
: fputs ("o", file
); break;
6418 case UNLT
: fputs ("ul", file
); break;
6419 case UNLE
: fputs ("ule", file
); break;
6420 case UNGT
: fputs ("ug", file
); break;
6421 case UNGE
: fputs ("uge", file
); break;
6422 case UNEQ
: fputs ("ue", file
); break;
6423 default: output_operand_lossage (code
== 'c'
6424 ? "invalid %%c operand"
6425 : "invalid %%C operand");
6430 /* These are used by the movr instruction pattern. */
6434 enum rtx_code rc
= (code
== 'd'
6435 ? reverse_condition (GET_CODE (x
))
6439 case NE
: fputs ("ne", file
); break;
6440 case EQ
: fputs ("e", file
); break;
6441 case GE
: fputs ("gez", file
); break;
6442 case LT
: fputs ("lz", file
); break;
6443 case LE
: fputs ("lez", file
); break;
6444 case GT
: fputs ("gz", file
); break;
6445 default: output_operand_lossage (code
== 'd'
6446 ? "invalid %%d operand"
6447 : "invalid %%D operand");
6454 /* Print a sign-extended character. */
6455 int i
= trunc_int_for_mode (INTVAL (x
), QImode
);
6456 fprintf (file
, "%d", i
);
6461 /* Operand must be a MEM; write its address. */
6462 if (GET_CODE (x
) != MEM
)
6463 output_operand_lossage ("invalid %%f operand");
6464 output_address (XEXP (x
, 0));
6468 /* Do nothing special. */
6472 /* Undocumented flag. */
6473 output_operand_lossage ("invalid operand output code");
6476 if (GET_CODE (x
) == REG
)
6477 fputs (reg_names
[REGNO (x
)], file
);
6478 else if (GET_CODE (x
) == MEM
)
6481 /* Poor Sun assembler doesn't understand absolute addressing. */
6482 if (CONSTANT_P (XEXP (x
, 0)))
6483 fputs ("%g0+", file
);
6484 output_address (XEXP (x
, 0));
6487 else if (GET_CODE (x
) == HIGH
)
6489 fputs ("%hi(", file
);
6490 output_addr_const (file
, XEXP (x
, 0));
6493 else if (GET_CODE (x
) == LO_SUM
)
6495 print_operand (file
, XEXP (x
, 0), 0);
6496 if (TARGET_CM_MEDMID
)
6497 fputs ("+%l44(", file
);
6499 fputs ("+%lo(", file
);
6500 output_addr_const (file
, XEXP (x
, 1));
6503 else if (GET_CODE (x
) == CONST_DOUBLE
6504 && (GET_MODE (x
) == VOIDmode
6505 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
6507 if (CONST_DOUBLE_HIGH (x
) == 0)
6508 fprintf (file
, "%u", (unsigned int) CONST_DOUBLE_LOW (x
));
6509 else if (CONST_DOUBLE_HIGH (x
) == -1
6510 && CONST_DOUBLE_LOW (x
) < 0)
6511 fprintf (file
, "%d", (int) CONST_DOUBLE_LOW (x
));
6513 output_operand_lossage ("long long constant not a valid immediate operand");
6515 else if (GET_CODE (x
) == CONST_DOUBLE
)
6516 output_operand_lossage ("floating point constant not a valid immediate operand");
6517 else { output_addr_const (file
, x
); }
6520 /* Target hook for assembling integer objects. The sparc version has
6521 special handling for aligned DI-mode objects. */
6524 sparc_assemble_integer (x
, size
, aligned_p
)
6529 /* ??? We only output .xword's for symbols and only then in environments
6530 where the assembler can handle them. */
6531 if (aligned_p
&& size
== 8
6532 && (GET_CODE (x
) != CONST_INT
&& GET_CODE (x
) != CONST_DOUBLE
))
6536 assemble_integer_with_op ("\t.xword\t", x
);
6541 assemble_aligned_integer (4, const0_rtx
);
6542 assemble_aligned_integer (4, x
);
6546 return default_assemble_integer (x
, size
, aligned_p
);
6549 /* Return the value of a code used in the .proc pseudo-op that says
6550 what kind of result this function returns. For non-C types, we pick
6551 the closest C type. */
6553 #ifndef SHORT_TYPE_SIZE
6554 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
6557 #ifndef INT_TYPE_SIZE
6558 #define INT_TYPE_SIZE BITS_PER_WORD
6561 #ifndef LONG_TYPE_SIZE
6562 #define LONG_TYPE_SIZE BITS_PER_WORD
6565 #ifndef LONG_LONG_TYPE_SIZE
6566 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
6569 #ifndef FLOAT_TYPE_SIZE
6570 #define FLOAT_TYPE_SIZE BITS_PER_WORD
6573 #ifndef DOUBLE_TYPE_SIZE
6574 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6577 #ifndef LONG_DOUBLE_TYPE_SIZE
6578 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
6582 sparc_type_code (type
)
6585 register unsigned long qualifiers
= 0;
6586 register unsigned shift
;
6588 /* Only the first 30 bits of the qualifier are valid. We must refrain from
6589 setting more, since some assemblers will give an error for this. Also,
6590 we must be careful to avoid shifts of 32 bits or more to avoid getting
6591 unpredictable results. */
6593 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
6595 switch (TREE_CODE (type
))
6601 qualifiers
|= (3 << shift
);
6606 qualifiers
|= (2 << shift
);
6610 case REFERENCE_TYPE
:
6612 qualifiers
|= (1 << shift
);
6616 return (qualifiers
| 8);
6619 case QUAL_UNION_TYPE
:
6620 return (qualifiers
| 9);
6623 return (qualifiers
| 10);
6626 return (qualifiers
| 16);
6629 /* If this is a range type, consider it to be the underlying
6631 if (TREE_TYPE (type
) != 0)
6634 /* Carefully distinguish all the standard types of C,
6635 without messing up if the language is not C. We do this by
6636 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
6637 look at both the names and the above fields, but that's redundant.
6638 Any type whose size is between two C types will be considered
6639 to be the wider of the two types. Also, we do not have a
6640 special code to use for "long long", so anything wider than
6641 long is treated the same. Note that we can't distinguish
6642 between "int" and "long" in this code if they are the same
6643 size, but that's fine, since neither can the assembler. */
6645 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
6646 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
6648 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
6649 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
6651 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
6652 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
6655 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
6658 /* If this is a range type, consider it to be the underlying
6660 if (TREE_TYPE (type
) != 0)
6663 /* Carefully distinguish all the standard types of C,
6664 without messing up if the language is not C. */
6666 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
6667 return (qualifiers
| 6);
6670 return (qualifiers
| 7);
6672 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
6673 /* ??? We need to distinguish between double and float complex types,
6674 but I don't know how yet because I can't reach this code from
6675 existing front-ends. */
6676 return (qualifiers
| 7); /* Who knows? */
6678 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
6679 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
6680 case FILE_TYPE
: /* GNU Pascal FILE type. */
6681 case SET_TYPE
: /* GNU Pascal SET type. */
6682 case LANG_TYPE
: /* ? */
6686 abort (); /* Not a type! */
6693 /* Nested function support. */
6695 /* Emit RTL insns to initialize the variable parts of a trampoline.
6696 FNADDR is an RTX for the address of the function's pure code.
6697 CXT is an RTX for the static chain value for the function.
6699 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
6700 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
6701 (to store insns). This is a bit excessive. Perhaps a different
6702 mechanism would be better here.
6704 Emit enough FLUSH insns to synchronize the data and instruction caches. */
6707 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
6708 rtx tramp
, fnaddr
, cxt
;
6710 /* SPARC 32 bit trampoline:
6713 sethi %hi(static), %g2
6715 or %g2, %lo(static), %g2
6717 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
6718 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
6720 #ifdef TRANSFER_FROM_TRAMPOLINE
6721 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6722 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
6726 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)),
6727 expand_binop (SImode
, ior_optab
,
6728 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
6729 size_int (10), 0, 1),
6730 GEN_INT (trunc_int_for_mode (0x03000000, SImode
)),
6731 NULL_RTX
, 1, OPTAB_DIRECT
));
6734 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6735 expand_binop (SImode
, ior_optab
,
6736 expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
6737 size_int (10), 0, 1),
6738 GEN_INT (trunc_int_for_mode (0x05000000, SImode
)),
6739 NULL_RTX
, 1, OPTAB_DIRECT
));
6742 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6743 expand_binop (SImode
, ior_optab
,
6744 expand_and (SImode
, fnaddr
, GEN_INT (0x3ff), NULL_RTX
),
6745 GEN_INT (trunc_int_for_mode (0x81c06000, SImode
)),
6746 NULL_RTX
, 1, OPTAB_DIRECT
));
6749 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6750 expand_binop (SImode
, ior_optab
,
6751 expand_and (SImode
, cxt
, GEN_INT (0x3ff), NULL_RTX
),
6752 GEN_INT (trunc_int_for_mode (0x8410a000, SImode
)),
6753 NULL_RTX
, 1, OPTAB_DIRECT
));
6755 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
6756 aligned on a 16 byte boundary so one flush clears it all. */
6757 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
6758 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
6759 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
6760 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
,
6761 plus_constant (tramp
, 8)))));
6764 /* The 64 bit version is simpler because it makes more sense to load the
6765 values as "immediate" data out of the trampoline. It's also easier since
6766 we can read the PC without clobbering a register. */
6769 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
6770 rtx tramp
, fnaddr
, cxt
;
6772 #ifdef TRANSFER_FROM_TRAMPOLINE
6773 emit_library_call (gen_rtx (SYMBOL_REF
, Pmode
, "__enable_execute_stack"),
6774 LCT_NORMAL
, VOIDmode
, 1, tramp
, Pmode
);
6785 emit_move_insn (gen_rtx_MEM (SImode
, tramp
),
6786 GEN_INT (trunc_int_for_mode (0x83414000, SImode
)));
6787 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)),
6788 GEN_INT (trunc_int_for_mode (0xca586018, SImode
)));
6789 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)),
6790 GEN_INT (trunc_int_for_mode (0x81c14000, SImode
)));
6791 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 12)),
6792 GEN_INT (trunc_int_for_mode (0xca586010, SImode
)));
6793 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)), cxt
);
6794 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), fnaddr
);
6795 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
6797 if (sparc_cpu
!= PROCESSOR_ULTRASPARC
6798 && sparc_cpu
!= PROCESSOR_ULTRASPARC3
)
6799 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
6802 /* Subroutines to support a flat (single) register window calling
6805 /* Single-register window sparc stack frames look like:
6807 Before call After call
6808 +-----------------------+ +-----------------------+
6810 mem | caller's temps. | | caller's temps. |
6812 +-----------------------+ +-----------------------+
6814 | arguments on stack. | | arguments on stack. |
6816 +-----------------------+FP+92->+-----------------------+
6817 | 6 words to save | | 6 words to save |
6818 | arguments passed | | arguments passed |
6819 | in registers, even | | in registers, even |
6820 | if not passed. | | if not passed. |
6821 SP+68->+-----------------------+FP+68->+-----------------------+
6822 | 1 word struct addr | | 1 word struct addr |
6823 +-----------------------+FP+64->+-----------------------+
6825 | 16 word reg save area | | 16 word reg save area |
6827 SP->+-----------------------+ FP->+-----------------------+
6829 | fp/alu reg moves |
6830 FP-16->+-----------------------+
6834 +-----------------------+
6836 | fp register save |
6838 +-----------------------+
6840 | gp register save |
6842 +-----------------------+
6844 | alloca allocations |
6846 +-----------------------+
6848 | arguments on stack |
6850 SP+92->+-----------------------+
6852 | arguments passed |
6853 | in registers, even |
6854 low | if not passed. |
6855 memory SP+68->+-----------------------+
6856 | 1 word struct addr |
6857 SP+64->+-----------------------+
6859 I 16 word reg save area |
6861 SP->+-----------------------+ */
6863 /* Structure to be filled in by sparc_flat_compute_frame_size with register
6864 save masks, and offsets for the current function. */
6866 struct sparc_frame_info
6868 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6869 unsigned long var_size
; /* # bytes that variables take up. */
6870 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6871 unsigned long extra_size
; /* # bytes of extra gunk. */
6872 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6873 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6874 unsigned long gmask
; /* Mask of saved gp registers. */
6875 unsigned long fmask
; /* Mask of saved fp registers. */
6876 unsigned long reg_offset
; /* Offset from new sp to store regs. */
6877 int initialized
; /* Nonzero if frame size already calculated. */
6880 /* Current frame information calculated by sparc_flat_compute_frame_size. */
6881 struct sparc_frame_info current_frame_info
;
6883 /* Zero structure to initialize current_frame_info. */
6884 struct sparc_frame_info zero_frame_info
;
6886 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
6888 #define RETURN_ADDR_REGNUM 15
6889 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
6890 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
6892 #define MUST_SAVE_REGISTER(regno) \
6893 ((regs_ever_live[regno] && !call_used_regs[regno]) \
6894 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
6895 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
6897 /* Return the bytes needed to compute the frame pointer from the current
6901 sparc_flat_compute_frame_size (size
)
6902 int size
; /* # of var. bytes allocated. */
6905 unsigned long total_size
; /* # bytes that the entire frame takes up. */
6906 unsigned long var_size
; /* # bytes that variables take up. */
6907 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
6908 unsigned long extra_size
; /* # extra bytes. */
6909 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
6910 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
6911 unsigned long gmask
; /* Mask of saved gp registers. */
6912 unsigned long fmask
; /* Mask of saved fp registers. */
6913 unsigned long reg_offset
; /* Offset to register save area. */
6914 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
6916 /* This is the size of the 16 word reg save area, 1 word struct addr
6917 area, and 4 word fp/alu register copy area. */
6918 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
6928 if (!leaf_function_p ())
6930 /* Also include the size needed for the 6 parameter registers. */
6931 args_size
= current_function_outgoing_args_size
+ 24;
6933 total_size
= var_size
+ args_size
;
6935 /* Calculate space needed for gp registers. */
6936 for (regno
= 1; regno
<= 31; regno
++)
6938 if (MUST_SAVE_REGISTER (regno
))
6940 /* If we need to save two regs in a row, ensure there's room to bump
6941 up the address to align it to a doubleword boundary. */
6942 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
6944 if (gp_reg_size
% 8 != 0)
6946 gp_reg_size
+= 2 * UNITS_PER_WORD
;
6947 gmask
|= 3 << regno
;
6953 gp_reg_size
+= UNITS_PER_WORD
;
6954 gmask
|= 1 << regno
;
6959 /* Calculate space needed for fp registers. */
6960 for (regno
= 32; regno
<= 63; regno
++)
6962 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
6964 fp_reg_size
+= UNITS_PER_WORD
;
6965 fmask
|= 1 << (regno
- 32);
6972 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
6973 /* Ensure save area is 8 byte aligned if we need it. */
6975 if (need_aligned_p
&& n
!= 0)
6977 total_size
+= 8 - n
;
6978 reg_offset
+= 8 - n
;
6980 total_size
+= gp_reg_size
+ fp_reg_size
;
6983 /* If we must allocate a stack frame at all, we must also allocate
6984 room for register window spillage, so as to be binary compatible
6985 with libraries and operating systems that do not use -mflat. */
6987 total_size
+= extra_size
;
6991 total_size
= SPARC_STACK_ALIGN (total_size
);
6993 /* Save other computed information. */
6994 current_frame_info
.total_size
= total_size
;
6995 current_frame_info
.var_size
= var_size
;
6996 current_frame_info
.args_size
= args_size
;
6997 current_frame_info
.extra_size
= extra_size
;
6998 current_frame_info
.gp_reg_size
= gp_reg_size
;
6999 current_frame_info
.fp_reg_size
= fp_reg_size
;
7000 current_frame_info
.gmask
= gmask
;
7001 current_frame_info
.fmask
= fmask
;
7002 current_frame_info
.reg_offset
= reg_offset
;
7003 current_frame_info
.initialized
= reload_completed
;
7005 /* Ok, we're done. */
7009 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7012 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7013 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7014 [BASE_REG+OFFSET] will always be a valid address.
7016 WORD_OP is either "st" for save, "ld" for restore.
7017 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7020 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
,
7021 doubleword_op
, base_offset
)
7023 const char *base_reg
;
7024 unsigned int offset
;
7025 unsigned long gmask
;
7026 unsigned long fmask
;
7027 const char *word_op
;
7028 const char *doubleword_op
;
7029 unsigned long base_offset
;
7033 if (gmask
== 0 && fmask
== 0)
7036 /* Save registers starting from high to low. We've already saved the
7037 previous frame pointer and previous return address for the debugger's
7038 sake. The debugger allows us to not need a nop in the epilog if at least
7039 one register is reloaded in addition to return address. */
7043 for (regno
= 1; regno
<= 31; regno
++)
7045 if ((gmask
& (1L << regno
)) != 0)
7047 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
7049 /* We can save two registers in a row. If we're not at a
7050 double word boundary, move to one.
7051 sparc_flat_compute_frame_size ensures there's room to do
7053 if (offset
% 8 != 0)
7054 offset
+= UNITS_PER_WORD
;
7056 if (word_op
[0] == 's')
7058 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7059 doubleword_op
, reg_names
[regno
],
7061 if (dwarf2out_do_frame ())
7063 char *l
= dwarf2out_cfi_label ();
7064 dwarf2out_reg_save (l
, regno
, offset
+ base_offset
);
7066 (l
, regno
+1, offset
+base_offset
+ UNITS_PER_WORD
);
7070 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7071 doubleword_op
, base_reg
, offset
,
7074 offset
+= 2 * UNITS_PER_WORD
;
7079 if (word_op
[0] == 's')
7081 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7082 word_op
, reg_names
[regno
],
7084 if (dwarf2out_do_frame ())
7085 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
7088 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7089 word_op
, base_reg
, offset
, reg_names
[regno
]);
7091 offset
+= UNITS_PER_WORD
;
7099 for (regno
= 32; regno
<= 63; regno
++)
7101 if ((fmask
& (1L << (regno
- 32))) != 0)
7103 if (word_op
[0] == 's')
7105 fprintf (file
, "\t%s\t%s, [%s+%d]\n",
7106 word_op
, reg_names
[regno
],
7108 if (dwarf2out_do_frame ())
7109 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
7112 fprintf (file
, "\t%s\t[%s+%d], %s\n",
7113 word_op
, base_reg
, offset
, reg_names
[regno
]);
7115 offset
+= UNITS_PER_WORD
;
7121 /* Set up the stack and frame (if desired) for the function. */
7124 sparc_flat_function_prologue (file
, size
)
7128 const char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7129 unsigned long gmask
= current_frame_info
.gmask
;
7131 sparc_output_scratch_registers (file
);
7133 /* This is only for the human reader. */
7134 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
7135 fprintf (file
, "\t%s# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
7137 current_frame_info
.var_size
,
7138 current_frame_info
.gp_reg_size
/ 4,
7139 current_frame_info
.fp_reg_size
/ 4,
7140 current_function_outgoing_args_size
,
7141 current_frame_info
.extra_size
);
7143 size
= SPARC_STACK_ALIGN (size
);
7144 size
= (! current_frame_info
.initialized
7145 ? sparc_flat_compute_frame_size (size
)
7146 : current_frame_info
.total_size
);
7148 /* These cases shouldn't happen. Catch them now. */
7149 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
7152 /* Allocate our stack frame by decrementing %sp.
7153 At present, the only algorithm gdb can use to determine if this is a
7154 flat frame is if we always set %i7 if we set %sp. This can be optimized
7155 in the future by putting in some sort of debugging information that says
7156 this is a `flat' function. However, there is still the case of debugging
7157 code without such debugging information (including cases where most fns
7158 have such info, but there is one that doesn't). So, always do this now
7159 so we don't get a lot of code out there that gdb can't handle.
7160 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7161 distinguish us from a non-flat function but there won't (and shouldn't)
7162 be any differences anyway. The return pc is saved (if necessary) right
7163 after %i7 so gdb won't have to look too far to find it. */
7166 unsigned int reg_offset
= current_frame_info
.reg_offset
;
7167 const char *const fp_str
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
7168 static const char *const t1_str
= "%g1";
7170 /* Things get a little tricky if local variables take up more than ~4096
7171 bytes and outgoing arguments take up more than ~4096 bytes. When that
7172 happens, the register save area can't be accessed from either end of
7173 the frame. Handle this by decrementing %sp to the start of the gp
7174 register save area, save the regs, update %i7, and then set %sp to its
7175 final value. Given that we only have one scratch register to play
7176 with it is the cheapest solution, and it helps gdb out as it won't
7177 slow down recognition of flat functions.
7178 Don't change the order of insns emitted here without checking with
7179 the gdb folk first. */
7181 /* Is the entire register save area offsettable from %sp? */
7182 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
7186 fprintf (file
, "\tadd\t%s, %d, %s\n",
7187 sp_str
, (int) -size
, sp_str
);
7188 if (gmask
& HARD_FRAME_POINTER_MASK
)
7190 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7191 fp_str
, sp_str
, reg_offset
);
7192 fprintf (file
, "\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7193 sp_str
, (int) -size
, fp_str
, ASM_COMMENT_START
);
7199 fprintf (file
, "\tset\t");
7200 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7201 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7202 t1_str
, sp_str
, t1_str
, sp_str
);
7203 if (gmask
& HARD_FRAME_POINTER_MASK
)
7205 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7206 fp_str
, sp_str
, reg_offset
);
7207 fprintf (file
, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7208 sp_str
, t1_str
, fp_str
, ASM_COMMENT_START
);
7212 if (dwarf2out_do_frame ())
7214 char *l
= dwarf2out_cfi_label ();
7215 if (gmask
& HARD_FRAME_POINTER_MASK
)
7217 dwarf2out_reg_save (l
, HARD_FRAME_POINTER_REGNUM
,
7218 reg_offset
- 4 - size
);
7219 dwarf2out_def_cfa (l
, HARD_FRAME_POINTER_REGNUM
, 0);
7222 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size
);
7224 if (gmask
& RETURN_ADDR_MASK
)
7226 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7227 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
7228 if (dwarf2out_do_frame ())
7229 dwarf2out_return_save ("", reg_offset
- size
);
7232 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
7233 gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7234 current_frame_info
.fmask
,
7235 "st", "std", -size
);
7239 /* Subtract %sp in two steps, but make sure there is always a
7240 64 byte register save area, and %sp is properly aligned. */
7241 /* Amount to decrement %sp by, the first time. */
7242 unsigned HOST_WIDE_INT size1
= ((size
- reg_offset
+ 64) + 15) & -16;
7243 /* Offset to register save area from %sp. */
7244 unsigned HOST_WIDE_INT offset
= size1
- (size
- reg_offset
);
7248 fprintf (file
, "\tadd\t%s, %d, %s\n",
7249 sp_str
, (int) -size1
, sp_str
);
7250 if (gmask
& HARD_FRAME_POINTER_MASK
)
7252 fprintf (file
, "\tst\t%s, [%s+%d]\n\tsub\t%s, %d, %s\t%s# set up frame pointer\n",
7253 fp_str
, sp_str
, (int) offset
, sp_str
, (int) -size1
,
7254 fp_str
, ASM_COMMENT_START
);
7260 fprintf (file
, "\tset\t");
7261 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size1
);
7262 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7263 t1_str
, sp_str
, t1_str
, sp_str
);
7264 if (gmask
& HARD_FRAME_POINTER_MASK
)
7266 fprintf (file
, "\tst\t%s, [%s+%d]\n\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7267 fp_str
, sp_str
, (int) offset
, sp_str
, t1_str
,
7268 fp_str
, ASM_COMMENT_START
);
7272 if (dwarf2out_do_frame ())
7274 char *l
= dwarf2out_cfi_label ();
7275 if (gmask
& HARD_FRAME_POINTER_MASK
)
7277 dwarf2out_reg_save (l
, HARD_FRAME_POINTER_REGNUM
,
7278 offset
- 4 - size1
);
7279 dwarf2out_def_cfa (l
, HARD_FRAME_POINTER_REGNUM
, 0);
7282 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size1
);
7284 if (gmask
& RETURN_ADDR_MASK
)
7286 fprintf (file
, "\tst\t%s, [%s+%d]\n",
7287 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, (int) offset
);
7288 if (dwarf2out_do_frame ())
7289 /* offset - size1 == reg_offset - size
7290 if reg_offset were updated above like offset. */
7291 dwarf2out_return_save ("", offset
- size1
);
7294 sparc_flat_save_restore (file
, sp_str
, offset
,
7295 gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7296 current_frame_info
.fmask
,
7297 "st", "std", -size1
);
7298 fprintf (file
, "\tset\t");
7299 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
- size1
);
7300 fprintf (file
, ", %s\n\tsub\t%s, %s, %s\n",
7301 t1_str
, sp_str
, t1_str
, sp_str
);
7302 if (dwarf2out_do_frame ())
7303 if (! (gmask
& HARD_FRAME_POINTER_MASK
))
7304 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, size
);
7308 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
7311 /* Do any necessary cleanup after a function to restore stack, frame,
7315 sparc_flat_function_epilogue (file
, size
)
7319 rtx epilogue_delay
= current_function_epilogue_delay_list
;
7320 int noepilogue
= FALSE
;
7322 /* This is only for the human reader. */
7323 fprintf (file
, "\t%s#EPILOGUE#\n", ASM_COMMENT_START
);
7325 /* The epilogue does not depend on any registers, but the stack
7326 registers, so we assume that if we have 1 pending nop, it can be
7327 ignored, and 2 it must be filled (2 nops occur for integer
7328 multiply and divide). */
7330 size
= SPARC_STACK_ALIGN (size
);
7331 size
= (!current_frame_info
.initialized
7332 ? sparc_flat_compute_frame_size (size
)
7333 : current_frame_info
.total_size
);
7335 if (size
== 0 && epilogue_delay
== 0)
7337 rtx insn
= get_last_insn ();
7339 /* If the last insn was a BARRIER, we don't have to write any code
7340 because a jump (aka return) was put there. */
7341 if (GET_CODE (insn
) == NOTE
)
7342 insn
= prev_nonnote_insn (insn
);
7343 if (insn
&& GET_CODE (insn
) == BARRIER
)
7349 unsigned HOST_WIDE_INT reg_offset
= current_frame_info
.reg_offset
;
7350 unsigned HOST_WIDE_INT size1
;
7351 const char *const sp_str
= reg_names
[STACK_POINTER_REGNUM
];
7352 const char *const fp_str
= reg_names
[HARD_FRAME_POINTER_REGNUM
];
7353 static const char *const t1_str
= "%g1";
7355 /* In the reload sequence, we don't need to fill the load delay
7356 slots for most of the loads, also see if we can fill the final
7357 delay slot if not otherwise filled by the reload sequence. */
7361 fprintf (file
, "\tset\t");
7362 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7363 fprintf (file
, ", %s\n", t1_str
);
7366 if (frame_pointer_needed
)
7369 fprintf (file
,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
7370 fp_str
, t1_str
, sp_str
, ASM_COMMENT_START
);
7372 fprintf (file
,"\tsub\t%s, %d, %s\t\t%s# sp not trusted here\n",
7373 fp_str
, (int) size
, sp_str
, ASM_COMMENT_START
);
7376 /* Is the entire register save area offsettable from %sp? */
7377 if (reg_offset
< 4096 - 64 * (unsigned) UNITS_PER_WORD
)
7383 /* Restore %sp in two steps, but make sure there is always a
7384 64 byte register save area, and %sp is properly aligned. */
7385 /* Amount to increment %sp by, the first time. */
7386 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
7387 /* Offset to register save area from %sp. */
7388 reg_offset
= size1
- reg_offset
;
7390 fprintf (file
, "\tset\t");
7391 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size1
);
7392 fprintf (file
, ", %s\n\tadd\t%s, %s, %s\n",
7393 t1_str
, sp_str
, t1_str
, sp_str
);
7396 /* We must restore the frame pointer and return address reg first
7397 because they are treated specially by the prologue output code. */
7398 if (current_frame_info
.gmask
& HARD_FRAME_POINTER_MASK
)
7400 fprintf (file
, "\tld\t[%s+%d], %s\n",
7401 sp_str
, (int) reg_offset
, fp_str
);
7404 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
7406 fprintf (file
, "\tld\t[%s+%d], %s\n",
7407 sp_str
, (int) reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
7411 /* Restore any remaining saved registers. */
7412 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
7413 current_frame_info
.gmask
& ~(HARD_FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
7414 current_frame_info
.fmask
,
7417 /* If we had to increment %sp in two steps, record it so the second
7418 restoration in the epilogue finishes up. */
7424 fprintf (file
, "\tset\t");
7425 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, size
);
7426 fprintf (file
, ", %s\n", t1_str
);
7430 if (current_function_returns_struct
)
7431 fprintf (file
, "\tjmp\t%%o7+12\n");
7433 fprintf (file
, "\tretl\n");
7435 /* If the only register saved is the return address, we need a
7436 nop, unless we have an instruction to put into it. Otherwise
7437 we don't since reloading multiple registers doesn't reference
7438 the register being loaded. */
7444 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
7447 else if (size
> 4095)
7448 fprintf (file
, "\tadd\t%s, %s, %s\n", sp_str
, t1_str
, sp_str
);
7451 fprintf (file
, "\tadd\t%s, %d, %s\n", sp_str
, (int) size
, sp_str
);
7454 fprintf (file
, "\tnop\n");
7457 /* Reset state info for each function. */
7458 current_frame_info
= zero_frame_info
;
7460 sparc_output_deferred_case_vectors ();
7463 /* Define the number of delay slots needed for the function epilogue.
7465 On the sparc, we need a slot if either no stack has been allocated,
7466 or the only register saved is the return register. */
7469 sparc_flat_epilogue_delay_slots ()
7471 if (!current_frame_info
.initialized
)
7472 (void) sparc_flat_compute_frame_size (get_frame_size ());
7474 if (current_frame_info
.total_size
== 0)
7480 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
7481 Any single length instruction which doesn't reference the stack or frame
7485 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
7487 int slot ATTRIBUTE_UNUSED
;
7489 rtx pat
= PATTERN (trial
);
7491 if (get_attr_length (trial
) != 1)
7494 if (! reg_mentioned_p (stack_pointer_rtx
, pat
)
7495 && ! reg_mentioned_p (frame_pointer_rtx
, pat
))
7501 /* Adjust the cost of a scheduling dependency. Return the new cost of
7502 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
7505 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7511 enum attr_type insn_type
;
7513 if (! recog_memoized (insn
))
7516 insn_type
= get_attr_type (insn
);
7518 if (REG_NOTE_KIND (link
) == 0)
7520 /* Data dependency; DEP_INSN writes a register that INSN reads some
7523 /* if a load, then the dependence must be on the memory address;
7524 add an extra "cycle". Note that the cost could be two cycles
7525 if the reg was written late in an instruction group; we ca not tell
7527 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
7530 /* Get the delay only if the address of the store is the dependence. */
7531 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
7533 rtx pat
= PATTERN(insn
);
7534 rtx dep_pat
= PATTERN (dep_insn
);
7536 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7537 return cost
; /* This should not happen! */
7539 /* The dependency between the two instructions was on the data that
7540 is being stored. Assume that this implies that the address of the
7541 store is not dependent. */
7542 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7545 return cost
+ 3; /* An approximation. */
7548 /* A shift instruction cannot receive its data from an instruction
7549 in the same cycle; add a one cycle penalty. */
7550 if (insn_type
== TYPE_SHIFT
)
7551 return cost
+ 3; /* Split before cascade into shift. */
7555 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
7556 INSN writes some cycles later. */
7558 /* These are only significant for the fpu unit; writing a fp reg before
7559 the fpu has finished with it stalls the processor. */
7561 /* Reusing an integer register causes no problems. */
7562 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7570 hypersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
7576 enum attr_type insn_type
, dep_type
;
7577 rtx pat
= PATTERN(insn
);
7578 rtx dep_pat
= PATTERN (dep_insn
);
7580 if (recog_memoized (insn
) < 0 || recog_memoized (dep_insn
) < 0)
7583 insn_type
= get_attr_type (insn
);
7584 dep_type
= get_attr_type (dep_insn
);
7586 switch (REG_NOTE_KIND (link
))
7589 /* Data dependency; DEP_INSN writes a register that INSN reads some
7596 /* Get the delay iff the address of the store is the dependence. */
7597 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
7600 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
7607 /* If a load, then the dependence must be on the memory address. If
7608 the addresses aren't equal, then it might be a false dependency */
7609 if (dep_type
== TYPE_STORE
|| dep_type
== TYPE_FPSTORE
)
7611 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
7612 || GET_CODE (SET_DEST (dep_pat
)) != MEM
7613 || GET_CODE (SET_SRC (pat
)) != MEM
7614 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat
), 0),
7615 XEXP (SET_SRC (pat
), 0)))
7623 /* Compare to branch latency is 0. There is no benefit from
7624 separating compare and branch. */
7625 if (dep_type
== TYPE_COMPARE
)
7627 /* Floating point compare to branch latency is less than
7628 compare to conditional move. */
7629 if (dep_type
== TYPE_FPCMP
)
7638 /* Anti-dependencies only penalize the fpu unit. */
7639 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)
7651 sparc_adjust_cost(insn
, link
, dep
, cost
)
7659 case PROCESSOR_SUPERSPARC
:
7660 cost
= supersparc_adjust_cost (insn
, link
, dep
, cost
);
7662 case PROCESSOR_HYPERSPARC
:
7663 case PROCESSOR_SPARCLITE86X
:
7664 cost
= hypersparc_adjust_cost (insn
, link
, dep
, cost
);
7673 sparc_sched_init (dump
, sched_verbose
, max_ready
)
7674 FILE *dump ATTRIBUTE_UNUSED
;
7675 int sched_verbose ATTRIBUTE_UNUSED
;
7676 int max_ready ATTRIBUTE_UNUSED
;
7681 sparc_use_dfa_pipeline_interface ()
7683 if ((1 << sparc_cpu
) &
7684 ((1 << PROCESSOR_ULTRASPARC
) | (1 << PROCESSOR_CYPRESS
) |
7685 (1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7686 (1 << PROCESSOR_SPARCLITE86X
) | (1 << PROCESSOR_TSC701
) |
7687 (1 << PROCESSOR_ULTRASPARC3
)))
7693 sparc_use_sched_lookahead ()
7695 if (sparc_cpu
== PROCESSOR_ULTRASPARC
7696 || sparc_cpu
== PROCESSOR_ULTRASPARC3
)
7698 if ((1 << sparc_cpu
) &
7699 ((1 << PROCESSOR_SUPERSPARC
) | (1 << PROCESSOR_HYPERSPARC
) |
7700 (1 << PROCESSOR_SPARCLITE86X
)))
7713 /* Assume V9 processors are capable of at least dual-issue. */
7715 case PROCESSOR_SUPERSPARC
:
7717 case PROCESSOR_HYPERSPARC
:
7718 case PROCESSOR_SPARCLITE86X
:
7720 case PROCESSOR_ULTRASPARC
:
7721 case PROCESSOR_ULTRASPARC3
:
7730 register rtx pat
= PATTERN (insn
);
7732 switch (GET_CODE (SET_SRC (pat
)))
7734 /* Load and some shift instructions zero extend. */
7737 /* sethi clears the high bits */
7739 /* LO_SUM is used with sethi. sethi cleared the high
7740 bits and the values used with lo_sum are positive */
7742 /* Store flag stores 0 or 1 */
7752 rtx op0
= XEXP (SET_SRC (pat
), 0);
7753 rtx op1
= XEXP (SET_SRC (pat
), 1);
7754 if (GET_CODE (op1
) == CONST_INT
)
7755 return INTVAL (op1
) >= 0;
7756 if (GET_CODE (op0
) != REG
)
7758 if (sparc_check_64 (op0
, insn
) == 1)
7760 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7765 rtx op0
= XEXP (SET_SRC (pat
), 0);
7766 rtx op1
= XEXP (SET_SRC (pat
), 1);
7767 if (GET_CODE (op0
) != REG
|| sparc_check_64 (op0
, insn
) <= 0)
7769 if (GET_CODE (op1
) == CONST_INT
)
7770 return INTVAL (op1
) >= 0;
7771 return (GET_CODE (op1
) == REG
&& sparc_check_64 (op1
, insn
) == 1);
7774 return GET_MODE (SET_SRC (pat
)) == SImode
;
7775 /* Positive integers leave the high bits zero. */
7777 return ! (CONST_DOUBLE_LOW (SET_SRC (pat
)) & 0x80000000);
7779 return ! (INTVAL (SET_SRC (pat
)) & 0x80000000);
7782 return - (GET_MODE (SET_SRC (pat
)) == SImode
);
7784 return sparc_check_64 (SET_SRC (pat
), insn
);
7790 /* We _ought_ to have only one kind per function, but... */
7791 static GTY(()) rtx sparc_addr_diff_list
;
7792 static GTY(()) rtx sparc_addr_list
;
7795 sparc_defer_case_vector (lab
, vec
, diff
)
7799 vec
= gen_rtx_EXPR_LIST (VOIDmode
, lab
, vec
);
7801 sparc_addr_diff_list
7802 = gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_diff_list
);
7804 sparc_addr_list
= gen_rtx_EXPR_LIST (VOIDmode
, vec
, sparc_addr_list
);
7808 sparc_output_addr_vec (vec
)
7811 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7812 int idx
, vlen
= XVECLEN (body
, 0);
7814 #ifdef ASM_OUTPUT_ADDR_VEC_START
7815 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7818 #ifdef ASM_OUTPUT_CASE_LABEL
7819 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7822 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7825 for (idx
= 0; idx
< vlen
; idx
++)
7827 ASM_OUTPUT_ADDR_VEC_ELT
7828 (asm_out_file
, CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 0, idx
), 0)));
7831 #ifdef ASM_OUTPUT_ADDR_VEC_END
7832 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7837 sparc_output_addr_diff_vec (vec
)
7840 rtx lab
= XEXP (vec
, 0), body
= XEXP (vec
, 1);
7841 rtx base
= XEXP (XEXP (body
, 0), 0);
7842 int idx
, vlen
= XVECLEN (body
, 1);
7844 #ifdef ASM_OUTPUT_ADDR_VEC_START
7845 ASM_OUTPUT_ADDR_VEC_START (asm_out_file
);
7848 #ifdef ASM_OUTPUT_CASE_LABEL
7849 ASM_OUTPUT_CASE_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
),
7852 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "L", CODE_LABEL_NUMBER (lab
));
7855 for (idx
= 0; idx
< vlen
; idx
++)
7857 ASM_OUTPUT_ADDR_DIFF_ELT
7860 CODE_LABEL_NUMBER (XEXP (XVECEXP (body
, 1, idx
), 0)),
7861 CODE_LABEL_NUMBER (base
));
7864 #ifdef ASM_OUTPUT_ADDR_VEC_END
7865 ASM_OUTPUT_ADDR_VEC_END (asm_out_file
);
7870 sparc_output_deferred_case_vectors ()
7875 if (sparc_addr_list
== NULL_RTX
7876 && sparc_addr_diff_list
== NULL_RTX
)
7879 /* Align to cache line in the function's code section. */
7880 function_section (current_function_decl
);
7882 align
= floor_log2 (FUNCTION_BOUNDARY
/ BITS_PER_UNIT
);
7884 ASM_OUTPUT_ALIGN (asm_out_file
, align
);
7886 for (t
= sparc_addr_list
; t
; t
= XEXP (t
, 1))
7887 sparc_output_addr_vec (XEXP (t
, 0));
7888 for (t
= sparc_addr_diff_list
; t
; t
= XEXP (t
, 1))
7889 sparc_output_addr_diff_vec (XEXP (t
, 0));
7891 sparc_addr_list
= sparc_addr_diff_list
= NULL_RTX
;
7894 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
7895 unknown. Return 1 if the high bits are zero, -1 if the register is
7898 sparc_check_64 (x
, insn
)
7901 /* If a register is set only once it is safe to ignore insns this
7902 code does not know how to handle. The loop will either recognize
7903 the single set and return the correct value or fail to recognize
7908 if (GET_CODE (x
) != REG
)
7911 if (GET_MODE (x
) == DImode
)
7912 y
= gen_rtx_REG (SImode
, REGNO (x
) + WORDS_BIG_ENDIAN
);
7914 if (flag_expensive_optimizations
7915 && REG_N_SETS (REGNO (y
)) == 1)
7921 insn
= get_last_insn_anywhere ();
7926 while ((insn
= PREV_INSN (insn
)))
7928 switch (GET_CODE (insn
))
7941 rtx pat
= PATTERN (insn
);
7942 if (GET_CODE (pat
) != SET
)
7944 if (rtx_equal_p (x
, SET_DEST (pat
)))
7945 return set_extends (insn
);
7946 if (y
&& rtx_equal_p (y
, SET_DEST (pat
)))
7947 return set_extends (insn
);
7948 if (reg_overlap_mentioned_p (SET_DEST (pat
), y
))
7957 sparc_v8plus_shift (operands
, insn
, opcode
)
7962 static char asm_code
[60];
7964 if (GET_CODE (operands
[3]) == SCRATCH
)
7965 operands
[3] = operands
[0];
7966 if (GET_CODE (operands
[1]) == CONST_INT
)
7968 output_asm_insn ("mov\t%1, %3", operands
);
7972 output_asm_insn ("sllx\t%H1, 32, %3", operands
);
7973 if (sparc_check_64 (operands
[1], insn
) <= 0)
7974 output_asm_insn ("srl\t%L1, 0, %L1", operands
);
7975 output_asm_insn ("or\t%L1, %3, %3", operands
);
7978 strcpy(asm_code
, opcode
);
7979 if (which_alternative
!= 2)
7980 return strcat (asm_code
, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
7982 return strcat (asm_code
, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
7985 /* Output rtl to increment the profiler label LABELNO
7986 for profiling a function entry. */
7989 sparc_profile_hook (labelno
)
7995 ASM_GENERATE_INTERNAL_LABEL (buf
, "LP", labelno
);
7996 lab
= gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (buf
));
7997 fun
= gen_rtx_SYMBOL_REF (Pmode
, MCOUNT_FUNCTION
);
7999 emit_library_call (fun
, LCT_NORMAL
, VOIDmode
, 1, lab
, Pmode
);
8002 #ifdef OBJECT_FORMAT_ELF
8004 sparc_elf_asm_named_section (name
, flags
)
8008 if (flags
& SECTION_MERGE
)
8010 /* entsize cannot be expressed in this section attributes
8012 default_elf_asm_named_section (name
, flags
);
8016 fprintf (asm_out_file
, "\t.section\t\"%s\"", name
);
8018 if (!(flags
& SECTION_DEBUG
))
8019 fputs (",#alloc", asm_out_file
);
8020 if (flags
& SECTION_WRITE
)
8021 fputs (",#write", asm_out_file
);
8022 if (flags
& SECTION_CODE
)
8023 fputs (",#execinstr", asm_out_file
);
8025 /* ??? Handle SECTION_BSS. */
8027 fputc ('\n', asm_out_file
);
8029 #endif /* OBJECT_FORMAT_ELF */
8031 /* ??? Similar to the standard section selection, but force reloc-y-ness
8032 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8033 pretending PIC always on), but that's what the old code did. */
8036 sparc_aout_select_section (t
, reloc
, align
)
8039 unsigned HOST_WIDE_INT align
;
8041 default_select_section (t
, reloc
| SUNOS4_SHARED_LIBRARIES
, align
);
8044 /* Use text section for a constant unless we need more alignment than
8048 sparc_aout_select_rtx_section (mode
, x
, align
)
8049 enum machine_mode mode
;
8051 unsigned HOST_WIDE_INT align
;
8053 if (align
<= MAX_TEXT_ALIGN
8054 && ! (flag_pic
&& (symbolic_operand (x
, mode
)
8055 || SUNOS4_SHARED_LIBRARIES
)))
8056 readonly_data_section ();
8062 sparc_extra_constraint_check (op
, c
, strict
)
8070 && (c
== 'T' || c
== 'U'))
8076 return fp_sethi_p (op
);
8079 return fp_mov_p (op
);
8082 return fp_high_losum_p (op
);
8086 || (GET_CODE (op
) == REG
8087 && (REGNO (op
) < FIRST_PSEUDO_REGISTER
8088 || reg_renumber
[REGNO (op
)] >= 0)))
8089 return register_ok_for_ldd (op
);
8101 /* Our memory extra constraints have to emulate the
8102 behavior of 'm' and 'o' in order for reload to work
8104 if (GET_CODE (op
) == MEM
)
8107 if ((TARGET_ARCH64
|| mem_min_alignment (op
, 8))
8109 || strict_memory_address_p (Pmode
, XEXP (op
, 0))))
8114 reload_ok_mem
= (reload_in_progress
8115 && GET_CODE (op
) == REG
8116 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
8117 && reg_renumber
[REGNO (op
)] < 0);
8120 return reload_ok_mem
;
8123 /* ??? This duplicates information provided to the compiler by the
8124 ??? scheduler description. Some day, teach genautomata to output
8125 ??? the latencies and then CSE will just use that. */
8128 sparc_rtx_costs (x
, code
, outer_code
)
8130 enum rtx_code code
, outer_code
;
8134 case PLUS
: case MINUS
: case ABS
: case NEG
:
8135 case FLOAT
: case UNSIGNED_FLOAT
:
8136 case FIX
: case UNSIGNED_FIX
:
8137 case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
8138 if (FLOAT_MODE_P (GET_MODE (x
)))
8142 case PROCESSOR_ULTRASPARC
:
8143 case PROCESSOR_ULTRASPARC3
:
8144 return COSTS_N_INSNS (4);
8146 case PROCESSOR_SUPERSPARC
:
8147 return COSTS_N_INSNS (3);
8149 case PROCESSOR_CYPRESS
:
8150 return COSTS_N_INSNS (5);
8152 case PROCESSOR_HYPERSPARC
:
8153 case PROCESSOR_SPARCLITE86X
:
8155 return COSTS_N_INSNS (1);
8159 return COSTS_N_INSNS (1);
8164 case PROCESSOR_ULTRASPARC
:
8165 if (GET_MODE (x
) == SFmode
)
8166 return COSTS_N_INSNS (13);
8168 return COSTS_N_INSNS (23);
8170 case PROCESSOR_ULTRASPARC3
:
8171 if (GET_MODE (x
) == SFmode
)
8172 return COSTS_N_INSNS (20);
8174 return COSTS_N_INSNS (29);
8176 case PROCESSOR_SUPERSPARC
:
8177 return COSTS_N_INSNS (12);
8179 case PROCESSOR_CYPRESS
:
8180 return COSTS_N_INSNS (63);
8182 case PROCESSOR_HYPERSPARC
:
8183 case PROCESSOR_SPARCLITE86X
:
8184 return COSTS_N_INSNS (17);
8187 return COSTS_N_INSNS (30);
8191 if (FLOAT_MODE_P (GET_MODE (x
)))
8195 case PROCESSOR_ULTRASPARC
:
8196 case PROCESSOR_ULTRASPARC3
:
8197 return COSTS_N_INSNS (1);
8199 case PROCESSOR_SUPERSPARC
:
8200 return COSTS_N_INSNS (3);
8202 case PROCESSOR_CYPRESS
:
8203 return COSTS_N_INSNS (5);
8205 case PROCESSOR_HYPERSPARC
:
8206 case PROCESSOR_SPARCLITE86X
:
8208 return COSTS_N_INSNS (1);
8212 /* ??? Maybe mark integer compares as zero cost on
8213 ??? all UltraSPARC processors because the result
8214 ??? can be bypassed to a branch in the same group. */
8216 return COSTS_N_INSNS (1);
8219 if (FLOAT_MODE_P (GET_MODE (x
)))
8223 case PROCESSOR_ULTRASPARC
:
8224 case PROCESSOR_ULTRASPARC3
:
8225 return COSTS_N_INSNS (4);
8227 case PROCESSOR_SUPERSPARC
:
8228 return COSTS_N_INSNS (3);
8230 case PROCESSOR_CYPRESS
:
8231 return COSTS_N_INSNS (7);
8233 case PROCESSOR_HYPERSPARC
:
8234 case PROCESSOR_SPARCLITE86X
:
8235 return COSTS_N_INSNS (1);
8238 return COSTS_N_INSNS (5);
8242 /* The latency is actually variable for Ultra-I/II
8243 And if one of the inputs have a known constant
8244 value, we could calculate this precisely.
8246 However, for that to be useful we would need to
8247 add some machine description changes which would
8248 make sure small constants ended up in rs1 of the
8249 multiply instruction. This is because the multiply
8250 latency is determined by the number of clear (or
8251 set if the value is negative) bits starting from
8252 the most significant bit of the first input.
8254 The algorithm for computing num_cycles of a multiply
8258 highest_bit = highest_clear_bit(rs1);
8260 highest_bit = highest_set_bit(rs1);
8263 num_cycles = 4 + ((highest_bit - 3) / 2);
8265 If we did that we would have to also consider register
8266 allocation issues that would result from forcing such
8267 a value into a register.
8269 There are other similar tricks we could play if we
8270 knew, for example, that one input was an array index.
8272 Since we do not play any such tricks currently the
8273 safest thing to do is report the worst case latency. */
8274 if (sparc_cpu
== PROCESSOR_ULTRASPARC
)
8275 return (GET_MODE (x
) == DImode
?
8276 COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
8278 /* Multiply latency on Ultra-III, fortunately, is constant. */
8279 if (sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8280 return COSTS_N_INSNS (6);
8282 if (sparc_cpu
== PROCESSOR_HYPERSPARC
8283 || sparc_cpu
== PROCESSOR_SPARCLITE86X
)
8284 return COSTS_N_INSNS (17);
8286 return (TARGET_HARD_MUL
8288 : COSTS_N_INSNS (25));
8294 if (FLOAT_MODE_P (GET_MODE (x
)))
8298 case PROCESSOR_ULTRASPARC
:
8299 if (GET_MODE (x
) == SFmode
)
8300 return COSTS_N_INSNS (13);
8302 return COSTS_N_INSNS (23);
8304 case PROCESSOR_ULTRASPARC3
:
8305 if (GET_MODE (x
) == SFmode
)
8306 return COSTS_N_INSNS (17);
8308 return COSTS_N_INSNS (20);
8310 case PROCESSOR_SUPERSPARC
:
8311 if (GET_MODE (x
) == SFmode
)
8312 return COSTS_N_INSNS (6);
8314 return COSTS_N_INSNS (9);
8316 case PROCESSOR_HYPERSPARC
:
8317 case PROCESSOR_SPARCLITE86X
:
8318 if (GET_MODE (x
) == SFmode
)
8319 return COSTS_N_INSNS (8);
8321 return COSTS_N_INSNS (12);
8324 return COSTS_N_INSNS (7);
8328 if (sparc_cpu
== PROCESSOR_ULTRASPARC
)
8329 return (GET_MODE (x
) == DImode
?
8330 COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
8331 if (sparc_cpu
== PROCESSOR_ULTRASPARC3
)
8332 return (GET_MODE (x
) == DImode
?
8333 COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
8334 return COSTS_N_INSNS (25);
8337 /* Conditional moves. */
8340 case PROCESSOR_ULTRASPARC
:
8341 return COSTS_N_INSNS (2);
8343 case PROCESSOR_ULTRASPARC3
:
8344 if (FLOAT_MODE_P (GET_MODE (x
)))
8345 return COSTS_N_INSNS (3);
8347 return COSTS_N_INSNS (2);
8350 return COSTS_N_INSNS (1);
8354 /* If outer-code is SIGN/ZERO extension we have to subtract
8355 out COSTS_N_INSNS (1) from whatever we return in determining
8359 case PROCESSOR_ULTRASPARC
:
8360 if (outer_code
== ZERO_EXTEND
)
8361 return COSTS_N_INSNS (1);
8363 return COSTS_N_INSNS (2);
8365 case PROCESSOR_ULTRASPARC3
:
8366 if (outer_code
== ZERO_EXTEND
)
8368 if (GET_MODE (x
) == QImode
8369 || GET_MODE (x
) == HImode
8370 || outer_code
== SIGN_EXTEND
)
8371 return COSTS_N_INSNS (2);
8373 return COSTS_N_INSNS (1);
8377 /* This handles sign extension (3 cycles)
8378 and everything else (2 cycles). */
8379 return COSTS_N_INSNS (2);
8382 case PROCESSOR_SUPERSPARC
:
8383 if (FLOAT_MODE_P (GET_MODE (x
))
8384 || outer_code
== ZERO_EXTEND
8385 || outer_code
== SIGN_EXTEND
)
8386 return COSTS_N_INSNS (0);
8388 return COSTS_N_INSNS (1);
8390 case PROCESSOR_TSC701
:
8391 if (outer_code
== ZERO_EXTEND
8392 || outer_code
== SIGN_EXTEND
)
8393 return COSTS_N_INSNS (2);
8395 return COSTS_N_INSNS (3);
8397 case PROCESSOR_CYPRESS
:
8398 if (outer_code
== ZERO_EXTEND
8399 || outer_code
== SIGN_EXTEND
)
8400 return COSTS_N_INSNS (1);
8402 return COSTS_N_INSNS (2);
8404 case PROCESSOR_HYPERSPARC
:
8405 case PROCESSOR_SPARCLITE86X
:
8407 if (outer_code
== ZERO_EXTEND
8408 || outer_code
== SIGN_EXTEND
)
8409 return COSTS_N_INSNS (0);
8411 return COSTS_N_INSNS (1);
8415 if (INTVAL (x
) < 0x1000 && INTVAL (x
) >= -0x1000)
8428 if (GET_MODE (x
) == DImode
)
8429 if ((XINT (x
, 3) == 0
8430 && (unsigned) XINT (x
, 2) < 0x1000)
8431 || (XINT (x
, 3) == -1
8433 && XINT (x
, 2) >= -0x1000))
8442 /* If we are referencing a function make the SYMBOL_REF special. In
8443 the Embedded Medium/Anywhere code model, %g4 points to the data
8444 segment so we must not add it to function addresses. */
8447 sparc_encode_section_info (decl
, first
)
8449 int first ATTRIBUTE_UNUSED
;
8451 if (TARGET_CM_EMBMEDANY
&& TREE_CODE (decl
) == FUNCTION_DECL
)
8452 SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl
), 0)) = 1;
8455 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
8456 Used for C++ multiple inheritance. */
8459 sparc_output_mi_thunk (file
, thunk_fndecl
, delta
, vcall_offset
, function
)
8461 tree thunk_fndecl ATTRIBUTE_UNUSED
;
8462 HOST_WIDE_INT delta
;
8463 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
;
8466 rtx
this, insn
, funexp
, delta_rtx
, tmp
;
8468 reload_completed
= 1;
8470 current_function_uses_only_leaf_regs
= 1;
8472 emit_note (NULL
, NOTE_INSN_PROLOGUE_END
);
8474 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
8475 returns a structure, the structure return pointer is there instead. */
8476 if (TARGET_ARCH64
&& aggregate_value_p (TREE_TYPE (TREE_TYPE (function
))))
8477 this = gen_rtx_REG (Pmode
, SPARC_INCOMING_INT_ARG_FIRST
+ 1);
8479 this = gen_rtx_REG (Pmode
, SPARC_INCOMING_INT_ARG_FIRST
);
8481 /* Add DELTA. When possible use a plain add, otherwise load it into
8482 a register first. */
8483 delta_rtx
= GEN_INT (delta
);
8484 if (!SPARC_SIMM13_P (delta
))
8486 rtx scratch
= gen_rtx_REG (Pmode
, 1);
8488 sparc_emit_set_const64 (scratch
, delta_rtx
);
8490 sparc_emit_set_const32 (scratch
, delta_rtx
);
8491 delta_rtx
= scratch
;
8494 tmp
= gen_rtx_PLUS (Pmode
, this, delta_rtx
);
8495 emit_insn (gen_rtx_SET (VOIDmode
, this, tmp
));
8497 /* Generate a tail call to the target function. */
8498 if (! TREE_USED (function
))
8500 assemble_external (function
);
8501 TREE_USED (function
) = 1;
8503 funexp
= XEXP (DECL_RTL (function
), 0);
8504 funexp
= gen_rtx_MEM (FUNCTION_MODE
, funexp
);
8505 insn
= emit_call_insn (gen_sibcall (funexp
));
8506 SIBLING_CALL_P (insn
) = 1;
8509 /* Run just enough of rest_of_compilation to get the insns emitted.
8510 There's not really enough bulk here to make other passes such as
8511 instruction scheduling worth while. Note that use_thunk calls
8512 assemble_start_function and assemble_end_function. */
8513 insn
= get_insns ();
8514 shorten_branches (insn
);
8515 final_start_function (insn
, file
, 1);
8516 final (insn
, file
, 1, 0);
8517 final_end_function ();
8519 reload_completed
= 0;
8523 #include "gt-sparc.h"