gcc/config/xtensa/xtensa.md

   1 ;; GCC machine description for Tensilica's Xtensa architecture.
   2 ;; Copyright (C) 2001-2015 Free Software Foundation, Inc.
   3 ;; Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21
  22 (define_constants [
  23   (A0_REG               0)
  24   (A1_REG               1)
  25   (A7_REG               7)
  26   (A8_REG               8)
  27   (A9_REG               9)
  28
  29   (UNSPEC_NOP           2)
  30   (UNSPEC_PLT           3)
  31   (UNSPEC_RET_ADDR      4)
  32   (UNSPEC_TPOFF         5)
  33   (UNSPEC_DTPOFF        6)
  34   (UNSPEC_TLS_FUNC      7)
  35   (UNSPEC_TLS_ARG       8)
  36   (UNSPEC_TLS_CALL      9)
  37   (UNSPEC_TP            10)
  38   (UNSPEC_MEMW          11)
  39   (UNSPEC_LSETUP_START  12)
  40   (UNSPEC_LSETUP_END    13)
  41
  42   (UNSPECV_SET_FP       1)
  43   (UNSPECV_ENTRY        2)
  44   (UNSPECV_S32RI        4)
  45   (UNSPECV_S32C1I       5)
  46   (UNSPECV_EH_RETURN    6)
  47   (UNSPECV_SET_TP       7)
  48   (UNSPECV_BLOCKAGE     8)
  49 ])
  50
  51 ;; This code iterator allows signed and unsigned widening multiplications
  52 ;; to use the same template.
  53 (define_code_iterator any_extend [sign_extend zero_extend])
  54
  55 ;; <u> expands to an empty string when doing a signed operation and
  56 ;; "u" when doing an unsigned operation.
  57 (define_code_attr u [(sign_extend "") (zero_extend "u")])
  58
  59 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
  60 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
  61
  62 ;; This code iterator allows four integer min/max operations to be
  63 ;; generated from one template.
  64 (define_code_iterator any_minmax [smin umin smax umax])
  65
  66 ;; <minmax> expands to the opcode name for any_minmax operations.
  67 (define_code_attr minmax [(smin "min") (umin "minu")
  68                           (smax "max") (umax "maxu")])
  69
  70 ;; This code iterator is for floating-point comparisons.
  71 (define_code_iterator any_scc_sf [eq lt le uneq unlt unle unordered])
  72 (define_code_attr scc_sf [(eq "oeq") (lt "olt") (le "ole")
  73                           (uneq "ueq") (unlt "ult") (unle "ule")
  74                           (unordered "un")])
  75
  76 ;; This iterator and attribute allow to combine most atomic operations.
  77 (define_code_iterator ATOMIC [and ior xor plus minus mult])
  78 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
  79                           (plus "add") (minus "sub") (mult "nand")])
  80
  81 ;; This mode iterator allows the HI and QI patterns to be defined from
  82 ;; the same template.
  83 (define_mode_iterator HQI [HI QI])
  84
  85 \f
  86 ;; Attributes.
  87
  88 (define_attr "type"
  89   "unknown,jump,call,load,store,move,arith,multi,nop,farith,fmadd,fconv,fload,fstore,mul16,mul32,div32,mac16,rsr,wsr,entry"
  90   (const_string "unknown"))
  91
  92 (define_attr "mode"
  93   "unknown,none,QI,HI,SI,DI,SF,DF,BL"
  94   (const_string "unknown"))
  95
  96 (define_attr "length" "" (const_int 1))
  97
  98 ;; Describe a user's asm statement.
  99 (define_asm_attributes
 100   [(set_attr "type" "multi")])
 101
 102 \f
 103 ;; Pipeline model.
 104
 105 ;; The Xtensa basically has simple 5-stage RISC pipeline.
 106 ;; Most instructions complete in 1 cycle, and it is OK to assume that
 107 ;; everything is fully pipelined.  The exceptions have special insn
 108 ;; reservations in the pipeline description below.  The Xtensa can
 109 ;; issue one instruction per cycle, so defining CPU units is unnecessary.
 110
 111 (define_insn_reservation "xtensa_any_insn" 1
 112                          (eq_attr "type" "!load,fload,rsr,mul16,mul32,fmadd,fconv")
 113                          "nothing")
 114
 115 (define_insn_reservation "xtensa_memory" 2
 116                          (eq_attr "type" "load,fload")
 117                          "nothing")
 118
 119 (define_insn_reservation "xtensa_sreg" 2
 120                          (eq_attr "type" "rsr")
 121                          "nothing")
 122
 123 (define_insn_reservation "xtensa_mul16" 2
 124                          (eq_attr "type" "mul16")
 125                          "nothing")
 126
 127 (define_insn_reservation "xtensa_mul32" 2
 128                          (eq_attr "type" "mul32")
 129                          "nothing")
 130
 131 (define_insn_reservation "xtensa_fmadd" 4
 132                          (eq_attr "type" "fmadd")
 133                          "nothing")
 134
 135 (define_insn_reservation "xtensa_fconv" 2
 136                          (eq_attr "type" "fconv")
 137                          "nothing")
 138 \f
 139 ;; Include predicates and constraints.
 140
 141 (include "predicates.md")
 142 (include "constraints.md")
 143
 144 \f
 145 ;; Addition.
 146
 147 (define_insn "addsi3"
 148   [(set (match_operand:SI 0 "register_operand" "=D,D,a,a,a")
 149         (plus:SI (match_operand:SI 1 "register_operand" "%d,d,r,r,r")
 150                  (match_operand:SI 2 "add_operand" "d,O,r,J,N")))]
 151   ""
 152   "@
 153    add.n\t%0, %1, %2
 154    addi.n\t%0, %1, %d2
 155    add\t%0, %1, %2
 156    addi\t%0, %1, %d2
 157    addmi\t%0, %1, %x2"
 158   [(set_attr "type"     "arith,arith,arith,arith,arith")
 159    (set_attr "mode"     "SI")
 160    (set_attr "length"   "2,2,3,3,3")])
 161
 162 (define_insn "*addx"
 163   [(set (match_operand:SI 0 "register_operand" "=a")
 164         (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
 165                           (match_operand:SI 3 "addsubx_operand" "i"))
 166                  (match_operand:SI 2 "register_operand" "r")))]
 167   "TARGET_ADDX"
 168   "addx%3\t%0, %1, %2"
 169   [(set_attr "type"     "arith")
 170    (set_attr "mode"     "SI")
 171    (set_attr "length"   "3")])
 172
 173 (define_insn "addsf3"
 174   [(set (match_operand:SF 0 "register_operand" "=f")
 175         (plus:SF (match_operand:SF 1 "register_operand" "%f")
 176                  (match_operand:SF 2 "register_operand" "f")))]
 177   "TARGET_HARD_FLOAT"
 178   "add.s\t%0, %1, %2"
 179   [(set_attr "type"     "fmadd")
 180    (set_attr "mode"     "SF")
 181    (set_attr "length"   "3")])
 182
 183 \f
 184 ;; Subtraction.
 185
 186 (define_insn "subsi3"
 187   [(set (match_operand:SI 0 "register_operand" "=a")
 188         (minus:SI (match_operand:SI 1 "register_operand" "r")
 189                   (match_operand:SI 2 "register_operand" "r")))]
 190   ""
 191   "sub\t%0, %1, %2"
 192   [(set_attr "type"     "arith")
 193    (set_attr "mode"     "SI")
 194    (set_attr "length"   "3")])
 195
 196 (define_insn "*subx"
 197   [(set (match_operand:SI 0 "register_operand" "=a")
 198         (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
 199                            (match_operand:SI 3 "addsubx_operand" "i"))
 200                   (match_operand:SI 2 "register_operand" "r")))]
 201   "TARGET_ADDX"
 202   "subx%3\t%0, %1, %2"
 203   [(set_attr "type"     "arith")
 204    (set_attr "mode"     "SI")
 205    (set_attr "length"   "3")])
 206
 207 (define_insn "subsf3"
 208   [(set (match_operand:SF 0 "register_operand" "=f")
 209         (minus:SF (match_operand:SF 1 "register_operand" "f")
 210                   (match_operand:SF 2 "register_operand" "f")))]
 211   "TARGET_HARD_FLOAT"
 212   "sub.s\t%0, %1, %2"
 213   [(set_attr "type"     "fmadd")
 214    (set_attr "mode"     "SF")
 215    (set_attr "length"   "3")])
 216
 217 \f
 218 ;; Multiplication.
 219
 220 (define_expand "<u>mulsidi3"
 221   [(set (match_operand:DI 0 "register_operand")
 222         (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
 223                  (any_extend:DI (match_operand:SI 2 "register_operand"))))]
 224   "TARGET_MUL32_HIGH"
 225 {
 226   rtx temp = gen_reg_rtx (SImode);
 227   emit_insn (gen_mulsi3 (temp, operands[1], operands[2]));
 228   emit_insn (gen_<u>mulsi3_highpart (gen_highpart (SImode, operands[0]),
 229                                      operands[1], operands[2]));
 230   emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), temp));
 231   DONE;
 232 })
 233
 234 (define_insn "<u>mulsi3_highpart"
 235   [(set (match_operand:SI 0 "register_operand" "=a")
 236         (truncate:SI
 237          (lshiftrt:DI
 238           (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "%r"))
 239                    (any_extend:DI (match_operand:SI 2 "register_operand" "r")))
 240           (const_int 32))))]
 241   "TARGET_MUL32_HIGH"
 242   "mul<su>h\t%0, %1, %2"
 243   [(set_attr "type"     "mul32")
 244    (set_attr "mode"     "SI")
 245    (set_attr "length"   "3")])
 246
 247 (define_insn "mulsi3"
 248   [(set (match_operand:SI 0 "register_operand" "=a")
 249         (mult:SI (match_operand:SI 1 "register_operand" "%r")
 250                  (match_operand:SI 2 "register_operand" "r")))]
 251   "TARGET_MUL32"
 252   "mull\t%0, %1, %2"
 253   [(set_attr "type"     "mul32")
 254    (set_attr "mode"     "SI")
 255    (set_attr "length"   "3")])
 256
 257 (define_insn "mulhisi3"
 258   [(set (match_operand:SI 0 "register_operand" "=C,A")
 259         (mult:SI (sign_extend:SI
 260                   (match_operand:HI 1 "register_operand" "%r,r"))
 261                  (sign_extend:SI
 262                   (match_operand:HI 2 "register_operand" "r,r"))))]
 263   "TARGET_MUL16 || TARGET_MAC16"
 264   "@
 265    mul16s\t%0, %1, %2
 266    mul.aa.ll\t%1, %2"
 267   [(set_attr "type"     "mul16,mac16")
 268    (set_attr "mode"     "SI")
 269    (set_attr "length"   "3,3")])
 270
 271 (define_insn "umulhisi3"
 272   [(set (match_operand:SI 0 "register_operand" "=C,A")
 273         (mult:SI (zero_extend:SI
 274                   (match_operand:HI 1 "register_operand" "%r,r"))
 275                  (zero_extend:SI
 276                   (match_operand:HI 2 "register_operand" "r,r"))))]
 277   "TARGET_MUL16 || TARGET_MAC16"
 278   "@
 279    mul16u\t%0, %1, %2
 280    umul.aa.ll\t%1, %2"
 281   [(set_attr "type"     "mul16,mac16")
 282    (set_attr "mode"     "SI")
 283    (set_attr "length"   "3,3")])
 284
 285 (define_insn "muladdhisi"
 286   [(set (match_operand:SI 0 "register_operand" "=A")
 287         (plus:SI (mult:SI (sign_extend:SI
 288                            (match_operand:HI 1 "register_operand" "%r"))
 289                           (sign_extend:SI
 290                            (match_operand:HI 2 "register_operand" "r")))
 291                  (match_operand:SI 3 "register_operand" "0")))]
 292   "TARGET_MAC16"
 293   "mula.aa.ll\t%1, %2"
 294   [(set_attr "type"     "mac16")
 295    (set_attr "mode"     "SI")
 296    (set_attr "length"   "3")])
 297
 298 (define_insn "mulsubhisi"
 299   [(set (match_operand:SI 0 "register_operand" "=A")
 300         (minus:SI (match_operand:SI 1 "register_operand" "0")
 301                   (mult:SI (sign_extend:SI
 302                             (match_operand:HI 2 "register_operand" "%r"))
 303                            (sign_extend:SI
 304                             (match_operand:HI 3 "register_operand" "r")))))]
 305   "TARGET_MAC16"
 306   "muls.aa.ll\t%2, %3"
 307   [(set_attr "type"     "mac16")
 308    (set_attr "mode"     "SI")
 309    (set_attr "length"   "3")])
 310
 311 (define_insn "mulsf3"
 312   [(set (match_operand:SF 0 "register_operand" "=f")
 313         (mult:SF (match_operand:SF 1 "register_operand" "%f")
 314                  (match_operand:SF 2 "register_operand" "f")))]
 315   "TARGET_HARD_FLOAT"
 316   "mul.s\t%0, %1, %2"
 317   [(set_attr "type"     "fmadd")
 318    (set_attr "mode"     "SF")
 319    (set_attr "length"   "3")])
 320
 321 (define_insn "fmasf4"
 322   [(set (match_operand:SF 0 "register_operand" "=f")
 323         (fma:SF (match_operand:SF 1 "register_operand" "f")
 324                 (match_operand:SF 2 "register_operand" "f")
 325                 (match_operand:SF 3 "register_operand" "0")))]
 326   "TARGET_HARD_FLOAT"
 327   "madd.s\t%0, %1, %2"
 328   [(set_attr "type"     "fmadd")
 329    (set_attr "mode"     "SF")
 330    (set_attr "length"   "3")])
 331
 332 ;; Note that (C - A*B) = (-A*B + C)
 333 (define_insn "fnmasf4"
 334   [(set (match_operand:SF 0 "register_operand" "=f")
 335         (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
 336                 (match_operand:SF 2 "register_operand" "f")
 337                 (match_operand:SF 3 "register_operand" "0")))]
 338   "TARGET_HARD_FLOAT"
 339   "msub.s\t%0, %1, %2"
 340   [(set_attr "type"     "fmadd")
 341    (set_attr "mode"     "SF")
 342    (set_attr "length"   "3")])
 343
 344 \f
 345 ;; Division.
 346
 347 (define_insn "divsi3"
 348   [(set (match_operand:SI 0 "register_operand" "=a")
 349         (div:SI (match_operand:SI 1 "register_operand" "r")
 350                 (match_operand:SI 2 "register_operand" "r")))]
 351   "TARGET_DIV32"
 352   "quos\t%0, %1, %2"
 353   [(set_attr "type"     "div32")
 354    (set_attr "mode"     "SI")
 355    (set_attr "length"   "3")])
 356
 357 (define_insn "udivsi3"
 358   [(set (match_operand:SI 0 "register_operand" "=a")
 359         (udiv:SI (match_operand:SI 1 "register_operand" "r")
 360                  (match_operand:SI 2 "register_operand" "r")))]
 361   "TARGET_DIV32"
 362   "quou\t%0, %1, %2"
 363   [(set_attr "type"     "div32")
 364    (set_attr "mode"     "SI")
 365    (set_attr "length"   "3")])
 366
 367 \f
 368 ;; Remainders.
 369
 370 (define_insn "modsi3"
 371   [(set (match_operand:SI 0 "register_operand" "=a")
 372         (mod:SI (match_operand:SI 1 "register_operand" "r")
 373                 (match_operand:SI 2 "register_operand" "r")))]
 374   "TARGET_DIV32"
 375   "rems\t%0, %1, %2"
 376   [(set_attr "type"     "div32")
 377    (set_attr "mode"     "SI")
 378    (set_attr "length"   "3")])
 379
 380 (define_insn "umodsi3"
 381   [(set (match_operand:SI 0 "register_operand" "=a")
 382         (umod:SI (match_operand:SI 1 "register_operand" "r")
 383                  (match_operand:SI 2 "register_operand" "r")))]
 384   "TARGET_DIV32"
 385   "remu\t%0, %1, %2"
 386   [(set_attr "type"     "div32")
 387    (set_attr "mode"     "SI")
 388    (set_attr "length"   "3")])
 389
 390 \f
 391 ;; Absolute value.
 392
 393 (define_insn "abssi2"
 394   [(set (match_operand:SI 0 "register_operand" "=a")
 395         (abs:SI (match_operand:SI 1 "register_operand" "r")))]
 396   "TARGET_ABS"
 397   "abs\t%0, %1"
 398   [(set_attr "type"     "arith")
 399    (set_attr "mode"     "SI")
 400    (set_attr "length"   "3")])
 401
 402 (define_insn "abssf2"
 403   [(set (match_operand:SF 0 "register_operand" "=f")
 404         (abs:SF (match_operand:SF 1 "register_operand" "f")))]
 405   "TARGET_HARD_FLOAT"
 406   "abs.s\t%0, %1"
 407   [(set_attr "type"     "farith")
 408    (set_attr "mode"     "SF")
 409    (set_attr "length"   "3")])
 410
 411 \f
 412 ;; Min and max.
 413
 414 (define_insn "<code>si3"
 415   [(set (match_operand:SI 0 "register_operand" "=a")
 416         (any_minmax:SI (match_operand:SI 1 "register_operand" "%r")
 417                        (match_operand:SI 2 "register_operand" "r")))]
 418   "TARGET_MINMAX"
 419   "<minmax>\t%0, %1, %2"
 420   [(set_attr "type"     "arith")
 421    (set_attr "mode"     "SI")
 422    (set_attr "length"   "3")])
 423
 424 \f
 425 ;; Count leading/trailing zeros and find first bit.
 426
 427 (define_insn "clzsi2"
 428   [(set (match_operand:SI 0 "register_operand" "=a")
 429         (clz:SI (match_operand:SI 1 "register_operand" "r")))]
 430   "TARGET_NSA"
 431   "nsau\t%0, %1"
 432   [(set_attr "type"     "arith")
 433    (set_attr "mode"     "SI")
 434    (set_attr "length"   "3")])
 435
 436 (define_expand "ctzsi2"
 437   [(set (match_operand:SI 0 "register_operand" "")
 438         (ctz:SI (match_operand:SI 1 "register_operand" "")))]
 439   "TARGET_NSA"
 440 {
 441   rtx temp = gen_reg_rtx (SImode);
 442   emit_insn (gen_negsi2 (temp, operands[1]));
 443   emit_insn (gen_andsi3 (temp, temp, operands[1]));
 444   emit_insn (gen_clzsi2 (temp, temp));
 445   emit_insn (gen_negsi2 (temp, temp));
 446   emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (31)));
 447   DONE;
 448 })
 449
 450 (define_expand "ffssi2"
 451   [(set (match_operand:SI 0 "register_operand" "")
 452         (ffs:SI (match_operand:SI 1 "register_operand" "")))]
 453   "TARGET_NSA"
 454 {
 455   rtx temp = gen_reg_rtx (SImode);
 456   emit_insn (gen_negsi2 (temp, operands[1]));
 457   emit_insn (gen_andsi3 (temp, temp, operands[1]));
 458   emit_insn (gen_clzsi2 (temp, temp));
 459   emit_insn (gen_negsi2 (temp, temp));
 460   emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (32)));
 461   DONE;
 462 })
 463
 464 \f
 465 ;; Negation and one's complement.
 466
 467 (define_insn "negsi2"
 468   [(set (match_operand:SI 0 "register_operand" "=a")
 469         (neg:SI (match_operand:SI 1 "register_operand" "r")))]
 470   ""
 471   "neg\t%0, %1"
 472   [(set_attr "type"     "arith")
 473    (set_attr "mode"     "SI")
 474    (set_attr "length"   "3")])
 475
 476 (define_expand "one_cmplsi2"
 477   [(set (match_operand:SI 0 "register_operand" "")
 478         (not:SI (match_operand:SI 1 "register_operand" "")))]
 479   ""
 480 {
 481   rtx temp = gen_reg_rtx (SImode);
 482   emit_insn (gen_movsi (temp, constm1_rtx));
 483   emit_insn (gen_xorsi3 (operands[0], temp, operands[1]));
 484   DONE;
 485 })
 486
 487 (define_insn "negsf2"
 488   [(set (match_operand:SF 0 "register_operand" "=f")
 489         (neg:SF (match_operand:SF 1 "register_operand" "f")))]
 490   "TARGET_HARD_FLOAT"
 491   "neg.s\t%0, %1"
 492   [(set_attr "type"     "farith")
 493    (set_attr "mode"     "SF")
 494    (set_attr "length"   "3")])
 495
 496 \f
 497 ;; Logical instructions.
 498
 499 (define_insn "andsi3"
 500   [(set (match_operand:SI 0 "register_operand" "=a,a")
 501         (and:SI (match_operand:SI 1 "register_operand" "%r,r")
 502                 (match_operand:SI 2 "mask_operand" "P,r")))]
 503   ""
 504   "@
 505    extui\t%0, %1, 0, %K2
 506    and\t%0, %1, %2"
 507   [(set_attr "type"     "arith,arith")
 508    (set_attr "mode"     "SI")
 509    (set_attr "length"   "3,3")])
 510
 511 (define_insn "iorsi3"
 512   [(set (match_operand:SI 0 "register_operand" "=a")
 513         (ior:SI (match_operand:SI 1 "register_operand" "%r")
 514                 (match_operand:SI 2 "register_operand" "r")))]
 515   ""
 516   "or\t%0, %1, %2"
 517   [(set_attr "type"     "arith")
 518    (set_attr "mode"     "SI")
 519    (set_attr "length"   "3")])
 520
 521 (define_insn "xorsi3"
 522   [(set (match_operand:SI 0 "register_operand" "=a")
 523         (xor:SI (match_operand:SI 1 "register_operand" "%r")
 524                 (match_operand:SI 2 "register_operand" "r")))]
 525   ""
 526   "xor\t%0, %1, %2"
 527   [(set_attr "type"     "arith")
 528    (set_attr "mode"     "SI")
 529    (set_attr "length"   "3")])
 530
 531 \f
 532 ;; Zero-extend instructions.
 533
 534 (define_insn "zero_extendhisi2"
 535   [(set (match_operand:SI 0 "register_operand" "=a,a")
 536         (zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,U")))]
 537   ""
 538   "@
 539    extui\t%0, %1, 0, 16
 540    l16ui\t%0, %1"
 541   [(set_attr "type"     "arith,load")
 542    (set_attr "mode"     "SI")
 543    (set_attr "length"   "3,3")])
 544
 545 (define_insn "zero_extendqisi2"
 546   [(set (match_operand:SI 0 "register_operand" "=a,a")
 547         (zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,U")))]
 548   ""
 549   "@
 550    extui\t%0, %1, 0, 8
 551    l8ui\t%0, %1"
 552   [(set_attr "type"     "arith,load")
 553    (set_attr "mode"     "SI")
 554    (set_attr "length"   "3,3")])
 555
 556 \f
 557 ;; Sign-extend instructions.
 558
 559 (define_expand "extendhisi2"
 560   [(set (match_operand:SI 0 "register_operand" "")
 561         (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
 562   ""
 563 {
 564   if (sext_operand (operands[1], HImode))
 565     emit_insn (gen_extendhisi2_internal (operands[0], operands[1]));
 566   else
 567     xtensa_extend_reg (operands[0], operands[1]);
 568   DONE;
 569 })
 570
 571 (define_insn "extendhisi2_internal"
 572   [(set (match_operand:SI 0 "register_operand" "=B,a")
 573         (sign_extend:SI (match_operand:HI 1 "sext_operand" "r,U")))]
 574   ""
 575   "@
 576    sext\t%0, %1, 15
 577    l16si\t%0, %1"
 578   [(set_attr "type"     "arith,load")
 579    (set_attr "mode"     "SI")
 580    (set_attr "length"   "3,3")])
 581
 582 (define_expand "extendqisi2"
 583   [(set (match_operand:SI 0 "register_operand" "")
 584         (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
 585   ""
 586 {
 587   if (TARGET_SEXT)
 588     emit_insn (gen_extendqisi2_internal (operands[0], operands[1]));
 589   else
 590     xtensa_extend_reg (operands[0], operands[1]);
 591   DONE;
 592 })
 593
 594 (define_insn "extendqisi2_internal"
 595   [(set (match_operand:SI 0 "register_operand" "=B")
 596         (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
 597   "TARGET_SEXT"
 598   "sext\t%0, %1, 7"
 599   [(set_attr "type"     "arith")
 600    (set_attr "mode"     "SI")
 601    (set_attr "length"   "3")])
 602
 603 \f
 604 ;; Field extract instructions.
 605
 606 (define_expand "extv"
 607   [(set (match_operand:SI 0 "register_operand" "")
 608         (sign_extract:SI (match_operand:SI 1 "register_operand" "")
 609                          (match_operand:SI 2 "const_int_operand" "")
 610                          (match_operand:SI 3 "const_int_operand" "")))]
 611   "TARGET_SEXT"
 612 {
 613   if (!sext_fldsz_operand (operands[2], SImode))
 614     FAIL;
 615
 616   /* We could expand to a right shift followed by SEXT but that's
 617      no better than the standard left and right shift sequence.  */
 618   if (!lsbitnum_operand (operands[3], SImode))
 619     FAIL;
 620
 621   emit_insn (gen_extv_internal (operands[0], operands[1],
 622                                 operands[2], operands[3]));
 623   DONE;
 624 })
 625
 626 (define_insn "extv_internal"
 627   [(set (match_operand:SI 0 "register_operand" "=a")
 628         (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
 629                          (match_operand:SI 2 "sext_fldsz_operand" "i")
 630                          (match_operand:SI 3 "lsbitnum_operand" "i")))]
 631   "TARGET_SEXT"
 632 {
 633   int fldsz = INTVAL (operands[2]);
 634   operands[2] = GEN_INT (fldsz - 1);
 635   return "sext\t%0, %1, %2";
 636 }
 637   [(set_attr "type"     "arith")
 638    (set_attr "mode"     "SI")
 639    (set_attr "length"   "3")])
 640
 641 (define_expand "extzv"
 642   [(set (match_operand:SI 0 "register_operand" "")
 643         (zero_extract:SI (match_operand:SI 1 "register_operand" "")
 644                          (match_operand:SI 2 "const_int_operand" "")
 645                          (match_operand:SI 3 "const_int_operand" "")))]
 646   ""
 647 {
 648   if (!extui_fldsz_operand (operands[2], SImode))
 649     FAIL;
 650   emit_insn (gen_extzv_internal (operands[0], operands[1],
 651                                  operands[2], operands[3]));
 652   DONE;
 653 })
 654
 655 (define_insn "extzv_internal"
 656   [(set (match_operand:SI 0 "register_operand" "=a")
 657         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 658                          (match_operand:SI 2 "extui_fldsz_operand" "i")
 659                          (match_operand:SI 3 "const_int_operand" "i")))]
 660   ""
 661 {
 662   int shift;
 663   if (BITS_BIG_ENDIAN)
 664     shift = (32 - (INTVAL (operands[2]) + INTVAL (operands[3]))) & 0x1f;
 665   else
 666     shift = INTVAL (operands[3]) & 0x1f;
 667   operands[3] = GEN_INT (shift);
 668   return "extui\t%0, %1, %3, %2";
 669 }
 670   [(set_attr "type"     "arith")
 671    (set_attr "mode"     "SI")
 672    (set_attr "length"   "3")])
 673
 674 \f
 675 ;; Conversions.
 676
 677 (define_insn "fix_truncsfsi2"
 678   [(set (match_operand:SI 0 "register_operand" "=a")
 679         (fix:SI (match_operand:SF 1 "register_operand" "f")))]
 680   "TARGET_HARD_FLOAT"
 681   "trunc.s\t%0, %1, 0"
 682   [(set_attr "type"     "fconv")
 683    (set_attr "mode"     "SF")
 684    (set_attr "length"   "3")])
 685
 686 (define_insn "fixuns_truncsfsi2"
 687   [(set (match_operand:SI 0 "register_operand" "=a")
 688         (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
 689   "TARGET_HARD_FLOAT"
 690   "utrunc.s\t%0, %1, 0"
 691   [(set_attr "type"     "fconv")
 692    (set_attr "mode"     "SF")
 693    (set_attr "length"   "3")])
 694
 695 (define_insn "floatsisf2"
 696   [(set (match_operand:SF 0 "register_operand" "=f")
 697         (float:SF (match_operand:SI 1 "register_operand" "a")))]
 698   "TARGET_HARD_FLOAT"
 699   "float.s\t%0, %1, 0"
 700   [(set_attr "type"     "fconv")
 701    (set_attr "mode"     "SF")
 702    (set_attr "length"   "3")])
 703
 704 (define_insn "floatunssisf2"
 705   [(set (match_operand:SF 0 "register_operand" "=f")
 706         (unsigned_float:SF (match_operand:SI 1 "register_operand" "a")))]
 707   "TARGET_HARD_FLOAT"
 708   "ufloat.s\t%0, %1, 0"
 709   [(set_attr "type"     "fconv")
 710    (set_attr "mode"     "SF")
 711    (set_attr "length"   "3")])
 712
 713 \f
 714 ;; Data movement instructions.
 715
 716 ;; 64-bit Integer moves
 717
 718 (define_expand "movdi"
 719   [(set (match_operand:DI 0 "nonimmed_operand" "")
 720         (match_operand:DI 1 "general_operand" ""))]
 721   ""
 722 {
 723   if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
 724     operands[1] = force_const_mem (DImode, operands[1]);
 725
 726   if (!register_operand (operands[0], DImode)
 727       && !register_operand (operands[1], DImode))
 728     operands[1] = force_reg (DImode, operands[1]);
 729
 730   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
 731 })
 732
 733 (define_insn_and_split "movdi_internal"
 734   [(set (match_operand:DI 0 "nonimmed_operand" "=a,W,a,a,U")
 735         (match_operand:DI 1 "move_operand" "r,i,T,U,r"))]
 736   "register_operand (operands[0], DImode)
 737    || register_operand (operands[1], DImode)"
 738   "#"
 739   "reload_completed"
 740   [(set (match_dup 0) (match_dup 2))
 741    (set (match_dup 1) (match_dup 3))]
 742 {
 743   xtensa_split_operand_pair (operands, SImode);
 744   if (reg_overlap_mentioned_p (operands[0], operands[3]))
 745     {
 746       rtx tmp;
 747       tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
 748       tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
 749     }
 750 })
 751
 752 ;; 32-bit Integer moves
 753
 754 (define_expand "movsi"
 755   [(set (match_operand:SI 0 "nonimmed_operand" "")
 756         (match_operand:SI 1 "general_operand" ""))]
 757   ""
 758 {
 759   if (xtensa_emit_move_sequence (operands, SImode))
 760     DONE;
 761 })
 762
 763 (define_insn "movsi_internal"
 764   [(set (match_operand:SI 0 "nonimmed_operand" "=D,D,D,D,R,R,a,q,a,W,a,a,U,*a,*A")
 765         (match_operand:SI 1 "move_operand" "M,D,d,R,D,d,r,r,I,i,T,U,r,*A,*r"))]
 766   "xtensa_valid_move (SImode, operands)"
 767   "@
 768    movi.n\t%0, %x1
 769    mov.n\t%0, %1
 770    mov.n\t%0, %1
 771    %v1l32i.n\t%0, %1
 772    %v0s32i.n\t%1, %0
 773    %v0s32i.n\t%1, %0
 774    mov\t%0, %1
 775    movsp\t%0, %1
 776    movi\t%0, %x1
 777    const16\t%0, %t1\;const16\t%0, %b1
 778    %v1l32r\t%0, %1
 779    %v1l32i\t%0, %1
 780    %v0s32i\t%1, %0
 781    rsr\t%0, ACCLO
 782    wsr\t%1, ACCLO"
 783   [(set_attr "type" "move,move,move,load,store,store,move,move,move,move,load,load,store,rsr,wsr")
 784    (set_attr "mode"     "SI")
 785    (set_attr "length"   "2,2,2,2,2,2,3,3,3,6,3,3,3,3,3")])
 786
 787 ;; 16-bit Integer moves
 788
 789 (define_expand "movhi"
 790   [(set (match_operand:HI 0 "nonimmed_operand" "")
 791         (match_operand:HI 1 "general_operand" ""))]
 792   ""
 793 {
 794   if (xtensa_emit_move_sequence (operands, HImode))
 795     DONE;
 796 })
 797
 798 (define_insn "movhi_internal"
 799   [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
 800         (match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
 801   "xtensa_valid_move (HImode, operands)"
 802   "@
 803    movi.n\t%0, %x1
 804    mov.n\t%0, %1
 805    mov\t%0, %1
 806    movi\t%0, %x1
 807    %v1l16ui\t%0, %1
 808    %v0s16i\t%1, %0
 809    rsr\t%0, ACCLO
 810    wsr\t%1, ACCLO"
 811   [(set_attr "type"     "move,move,move,move,load,store,rsr,wsr")
 812    (set_attr "mode"     "HI")
 813    (set_attr "length"   "2,2,3,3,3,3,3,3")])
 814
 815 ;; 8-bit Integer moves
 816
 817 (define_expand "movqi"
 818   [(set (match_operand:QI 0 "nonimmed_operand" "")
 819         (match_operand:QI 1 "general_operand" ""))]
 820   ""
 821 {
 822   if (xtensa_emit_move_sequence (operands, QImode))
 823     DONE;
 824 })
 825
 826 (define_insn "movqi_internal"
 827   [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
 828         (match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
 829   "xtensa_valid_move (QImode, operands)"
 830   "@
 831    movi.n\t%0, %x1
 832    mov.n\t%0, %1
 833    mov\t%0, %1
 834    movi\t%0, %x1
 835    %v1l8ui\t%0, %1
 836    %v0s8i\t%1, %0
 837    rsr\t%0, ACCLO
 838    wsr\t%1, ACCLO"
 839   [(set_attr "type"     "move,move,move,move,load,store,rsr,wsr")
 840    (set_attr "mode"     "QI")
 841    (set_attr "length"   "2,2,3,3,3,3,3,3")])
 842
 843 ;; Sub-word reloads from the constant pool.
 844
 845 (define_expand "reload<mode>_literal"
 846   [(parallel [(match_operand:HQI 0 "register_operand" "=r")
 847               (match_operand:HQI 1 "constantpool_operand" "")
 848               (match_operand:SI 2 "register_operand" "=&r")])]
 849   ""
 850 {
 851   rtx lit, scratch;
 852   unsigned word_off, byte_off;
 853
 854   if (MEM_P (operands[1]))
 855     {
 856       lit = operands[1];
 857       word_off = 0;
 858       byte_off = 0;
 859     }
 860   else
 861     {
 862       gcc_assert (GET_CODE (operands[1]) == SUBREG);
 863       lit = SUBREG_REG (operands[1]);
 864       word_off = SUBREG_BYTE (operands[1]) & ~(UNITS_PER_WORD - 1);
 865       byte_off = SUBREG_BYTE (operands[1]) - word_off;
 866     }
 867
 868   lit = adjust_address (lit, SImode, word_off);
 869   scratch = operands[2];
 870   emit_insn (gen_movsi (scratch, lit));
 871   emit_insn (gen_mov<mode> (operands[0],
 872                             gen_rtx_SUBREG (<MODE>mode, scratch, byte_off)));
 873
 874   DONE;
 875 })
 876
 877 ;; 32-bit floating point moves
 878
 879 (define_expand "movsf"
 880   [(set (match_operand:SF 0 "nonimmed_operand" "")
 881         (match_operand:SF 1 "general_operand" ""))]
 882   ""
 883 {
 884   if (!TARGET_CONST16 && CONSTANT_P (operands[1]))
 885     operands[1] = force_const_mem (SFmode, operands[1]);
 886
 887   if ((!register_operand (operands[0], SFmode)
 888        && !register_operand (operands[1], SFmode))
 889       || (FP_REG_P (xt_true_regnum (operands[0]))
 890           && !(reload_in_progress | reload_completed)
 891           && (constantpool_mem_p (operands[1])
 892               || CONSTANT_P (operands[1]))))
 893     operands[1] = force_reg (SFmode, operands[1]);
 894
 895   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
 896 })
 897
 898 (define_insn "movsf_internal"
 899   [(set (match_operand:SF 0 "nonimmed_operand" "=f,f,U,D,D,R,a,f,a,W,a,a,U")
 900         (match_operand:SF 1 "move_operand" "f,U,f,d,R,d,r,r,f,iF,T,U,r"))]
 901   "((register_operand (operands[0], SFmode)
 902      || register_operand (operands[1], SFmode))
 903     && !(FP_REG_P (xt_true_regnum (operands[0]))
 904          && (constantpool_mem_p (operands[1]) || CONSTANT_P (operands[1]))))"
 905   "@
 906    mov.s\t%0, %1
 907    %v1lsi\t%0, %1
 908    %v0ssi\t%1, %0
 909    mov.n\t%0, %1
 910    %v1l32i.n\t%0, %1
 911    %v0s32i.n\t%1, %0
 912    mov\t%0, %1
 913    wfr\t%0, %1
 914    rfr\t%0, %1
 915    const16\t%0, %t1\;const16\t%0, %b1
 916    %v1l32r\t%0, %1
 917    %v1l32i\t%0, %1
 918    %v0s32i\t%1, %0"
 919   [(set_attr "type"     "farith,fload,fstore,move,load,store,move,farith,farith,move,load,load,store")
 920    (set_attr "mode"     "SF")
 921    (set_attr "length"   "3,3,3,2,2,2,3,3,3,6,3,3,3")])
 922
 923 (define_insn "*lsiu"
 924   [(set (match_operand:SF 0 "register_operand" "=f")
 925         (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "+a")
 926                          (match_operand:SI 2 "fpmem_offset_operand" "i"))))
 927    (set (match_dup 1)
 928         (plus:SI (match_dup 1) (match_dup 2)))]
 929   "TARGET_HARD_FLOAT && !TARGET_HARD_FLOAT_POSTINC"
 930 {
 931   if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
 932     output_asm_insn ("memw", operands);
 933   return "lsiu\t%0, %1, %2";
 934 }
 935   [(set_attr "type"     "fload")
 936    (set_attr "mode"     "SF")
 937    (set_attr "length"   "3")])
 938
 939 (define_insn "*ssiu"
 940   [(set (mem:SF (plus:SI (match_operand:SI 0 "register_operand" "+a")
 941                          (match_operand:SI 1 "fpmem_offset_operand" "i")))
 942         (match_operand:SF 2 "register_operand" "f"))
 943    (set (match_dup 0)
 944         (plus:SI (match_dup 0) (match_dup 1)))]
 945   "TARGET_HARD_FLOAT && !TARGET_HARD_FLOAT_POSTINC"
 946 {
 947   if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
 948     output_asm_insn ("memw", operands);
 949   return "ssiu\t%2, %0, %1";
 950 }
 951   [(set_attr "type"     "fstore")
 952    (set_attr "mode"     "SF")
 953    (set_attr "length"   "3")])
 954
 955 (define_insn "*lsip"
 956   [(set (match_operand:SF 0 "register_operand" "=f")
 957         (mem:SF (match_operand:SI 1 "register_operand" "+a")))
 958    (set (match_dup 1)
 959         (plus:SI (match_dup 1)
 960                  (match_operand:SI 2 "fpmem_offset_operand" "i")))]
 961   "TARGET_HARD_FLOAT && TARGET_HARD_FLOAT_POSTINC"
 962 {
 963   if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
 964     output_asm_insn ("memw", operands);
 965   return "lsip\t%0, %1, %2";
 966 }
 967   [(set_attr "type"     "fload")
 968    (set_attr "mode"     "SF")
 969    (set_attr "length"   "3")])
 970
 971 (define_insn "*ssip"
 972   [(set (mem:SF (match_operand:SI 0 "register_operand" "+a"))
 973         (match_operand:SF 1 "register_operand" "f"))
 974    (set (match_dup 0)
 975         (plus:SI (match_dup 0)
 976                  (match_operand:SI 2 "fpmem_offset_operand" "i")))]
 977   "TARGET_HARD_FLOAT && TARGET_HARD_FLOAT_POSTINC"
 978 {
 979   if (TARGET_SERIALIZE_VOLATILE && volatile_refs_p (PATTERN (insn)))
 980     output_asm_insn ("memw", operands);
 981   return "ssip\t%1, %0, %2";
 982 }
 983   [(set_attr "type"     "fstore")
 984    (set_attr "mode"     "SF")
 985    (set_attr "length"   "3")])
 986
 987 ;; 64-bit floating point moves
 988
 989 (define_expand "movdf"
 990   [(set (match_operand:DF 0 "nonimmed_operand" "")
 991         (match_operand:DF 1 "general_operand" ""))]
 992   ""
 993 {
 994   if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
 995     operands[1] = force_const_mem (DFmode, operands[1]);
 996
 997   if (!register_operand (operands[0], DFmode)
 998       && !register_operand (operands[1], DFmode))
 999     operands[1] = force_reg (DFmode, operands[1]);
1000
1001   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1002 })
1003
1004 (define_insn_and_split "movdf_internal"
1005   [(set (match_operand:DF 0 "nonimmed_operand" "=a,W,a,a,U")
1006         (match_operand:DF 1 "move_operand" "r,iF,T,U,r"))]
1007   "register_operand (operands[0], DFmode)
1008    || register_operand (operands[1], DFmode)"
1009   "#"
1010   "reload_completed"
1011   [(set (match_dup 0) (match_dup 2))
1012    (set (match_dup 1) (match_dup 3))]
1013 {
1014   xtensa_split_operand_pair (operands, SFmode);
1015   if (reg_overlap_mentioned_p (operands[0], operands[3]))
1016     {
1017       rtx tmp;
1018       tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
1019       tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
1020     }
1021 })
1022
1023 ;; Block moves
1024
1025 (define_expand "movmemsi"
1026   [(parallel [(set (match_operand:BLK 0 "" "")
1027                    (match_operand:BLK 1 "" ""))
1028               (use (match_operand:SI 2 "arith_operand" ""))
1029               (use (match_operand:SI 3 "const_int_operand" ""))])]
1030   ""
1031 {
1032   if (!xtensa_expand_block_move (operands))
1033     FAIL;
1034   DONE;
1035 })
1036
1037 \f
1038 ;; Shift instructions.
1039
1040 (define_expand "ashlsi3"
1041   [(set (match_operand:SI 0 "register_operand" "")
1042         (ashift:SI (match_operand:SI 1 "register_operand" "")
1043                    (match_operand:SI 2 "arith_operand" "")))]
1044   ""
1045 {
1046   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1047 })
1048
1049 (define_insn "ashlsi3_internal"
1050   [(set (match_operand:SI 0 "register_operand" "=a,a")
1051         (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
1052                    (match_operand:SI 2 "arith_operand" "J,r")))]
1053   ""
1054   "@
1055    slli\t%0, %1, %R2
1056    ssl\t%2\;sll\t%0, %1"
1057   [(set_attr "type"     "arith,arith")
1058    (set_attr "mode"     "SI")
1059    (set_attr "length"   "3,6")])
1060
1061 (define_insn "ashrsi3"
1062   [(set (match_operand:SI 0 "register_operand" "=a,a")
1063         (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
1064                      (match_operand:SI 2 "arith_operand" "J,r")))]
1065   ""
1066   "@
1067    srai\t%0, %1, %R2
1068    ssr\t%2\;sra\t%0, %1"
1069   [(set_attr "type"     "arith,arith")
1070    (set_attr "mode"     "SI")
1071    (set_attr "length"   "3,6")])
1072
1073 (define_insn "lshrsi3"
1074   [(set (match_operand:SI 0 "register_operand" "=a,a")
1075         (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
1076                      (match_operand:SI 2 "arith_operand" "J,r")))]
1077   ""
1078 {
1079   if (which_alternative == 0)
1080     {
1081       if ((INTVAL (operands[2]) & 0x1f) < 16)
1082         return "srli\t%0, %1, %R2";
1083       else
1084         return "extui\t%0, %1, %R2, %L2";
1085     }
1086   return "ssr\t%2\;srl\t%0, %1";
1087 }
1088   [(set_attr "type"     "arith,arith")
1089    (set_attr "mode"     "SI")
1090    (set_attr "length"   "3,6")])
1091
1092 (define_insn "rotlsi3"
1093   [(set (match_operand:SI 0 "register_operand" "=a,a")
1094         (rotate:SI (match_operand:SI 1 "register_operand" "r,r")
1095                      (match_operand:SI 2 "arith_operand" "J,r")))]
1096   ""
1097   "@
1098    ssai\t%L2\;src\t%0, %1, %1
1099    ssl\t%2\;src\t%0, %1, %1"
1100   [(set_attr "type"     "multi,multi")
1101    (set_attr "mode"     "SI")
1102    (set_attr "length"   "6,6")])
1103
1104 (define_insn "rotrsi3"
1105   [(set (match_operand:SI 0 "register_operand" "=a,a")
1106         (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
1107                      (match_operand:SI 2 "arith_operand" "J,r")))]
1108   ""
1109   "@
1110    ssai\t%R2\;src\t%0, %1, %1
1111    ssr\t%2\;src\t%0, %1, %1"
1112   [(set_attr "type"     "multi,multi")
1113    (set_attr "mode"     "SI")
1114    (set_attr "length"   "6,6")])
1115
1116 \f
1117 ;; Comparisons.
1118
1119 ;; Conditional branches.
1120
1121 (define_expand "cbranchsi4"
1122   [(match_operator 0 "comparison_operator"
1123     [(match_operand:SI 1 "register_operand")
1124      (match_operand:SI 2 "nonmemory_operand")])
1125    (match_operand 3 "")]
1126   ""
1127 {
1128   xtensa_expand_conditional_branch (operands, SImode);
1129   DONE;
1130 })
1131
1132 (define_expand "cbranchsf4"
1133   [(match_operator 0 "comparison_operator"
1134     [(match_operand:SF 1 "register_operand")
1135      (match_operand:SF 2 "register_operand")])
1136    (match_operand 3 "")]
1137   "TARGET_HARD_FLOAT"
1138 {
1139   xtensa_expand_conditional_branch (operands, SFmode);
1140   DONE;
1141 })
1142
1143 ;; Branch patterns for standard integer comparisons
1144
1145 (define_insn "*btrue"
1146   [(set (pc)
1147         (if_then_else (match_operator 3 "branch_operator"
1148                        [(match_operand:SI 0 "register_operand" "r,r")
1149                         (match_operand:SI 1 "branch_operand" "K,r")])
1150                       (label_ref (match_operand 2 "" ""))
1151                       (pc)))]
1152   ""
1153 {
1154   return xtensa_emit_branch (false, which_alternative == 0, operands);
1155 }
1156   [(set_attr "type"     "jump,jump")
1157    (set_attr "mode"     "none")
1158    (set_attr "length"   "3,3")])
1159
1160 (define_insn "*bfalse"
1161   [(set (pc)
1162         (if_then_else (match_operator 3 "branch_operator"
1163                        [(match_operand:SI 0 "register_operand" "r,r")
1164                         (match_operand:SI 1 "branch_operand" "K,r")])
1165                       (pc)
1166                       (label_ref (match_operand 2 "" ""))))]
1167   ""
1168 {
1169   return xtensa_emit_branch (true, which_alternative == 0, operands);
1170 }
1171   [(set_attr "type"     "jump,jump")
1172    (set_attr "mode"     "none")
1173    (set_attr "length"   "3,3")])
1174
1175 (define_insn "*ubtrue"
1176   [(set (pc)
1177         (if_then_else (match_operator 3 "ubranch_operator"
1178                        [(match_operand:SI 0 "register_operand" "r,r")
1179                         (match_operand:SI 1 "ubranch_operand" "L,r")])
1180                       (label_ref (match_operand 2 "" ""))
1181                       (pc)))]
1182   ""
1183 {
1184   return xtensa_emit_branch (false, which_alternative == 0, operands);
1185 }
1186   [(set_attr "type"     "jump,jump")
1187    (set_attr "mode"     "none")
1188    (set_attr "length"   "3,3")])
1189
1190 (define_insn "*ubfalse"
1191   [(set (pc)
1192         (if_then_else (match_operator 3 "ubranch_operator"
1193                          [(match_operand:SI 0 "register_operand" "r,r")
1194                           (match_operand:SI 1 "ubranch_operand" "L,r")])
1195                       (pc)
1196                       (label_ref (match_operand 2 "" ""))))]
1197   ""
1198 {
1199   return xtensa_emit_branch (true, which_alternative == 0, operands);
1200 }
1201   [(set_attr "type"     "jump,jump")
1202    (set_attr "mode"     "none")
1203    (set_attr "length"   "3,3")])
1204
1205 ;; Branch patterns for bit testing
1206
1207 (define_insn "*bittrue"
1208   [(set (pc)
1209         (if_then_else (match_operator 3 "boolean_operator"
1210                         [(zero_extract:SI
1211                             (match_operand:SI 0 "register_operand" "r,r")
1212                             (const_int 1)
1213                             (match_operand:SI 1 "arith_operand" "J,r"))
1214                          (const_int 0)])
1215                       (label_ref (match_operand 2 "" ""))
1216                       (pc)))]
1217   ""
1218 {
1219   return xtensa_emit_bit_branch (false, which_alternative == 0, operands);
1220 }
1221   [(set_attr "type"     "jump")
1222    (set_attr "mode"     "none")
1223    (set_attr "length"   "3")])
1224
1225 (define_insn "*bitfalse"
1226   [(set (pc)
1227         (if_then_else (match_operator 3 "boolean_operator"
1228                         [(zero_extract:SI
1229                             (match_operand:SI 0 "register_operand" "r,r")
1230                             (const_int 1)
1231                             (match_operand:SI 1 "arith_operand" "J,r"))
1232                          (const_int 0)])
1233                       (pc)
1234                       (label_ref (match_operand 2 "" ""))))]
1235   ""
1236 {
1237   return xtensa_emit_bit_branch (true, which_alternative == 0, operands);
1238 }
1239   [(set_attr "type"     "jump")
1240    (set_attr "mode"     "none")
1241    (set_attr "length"   "3")])
1242
1243 (define_insn "*masktrue"
1244   [(set (pc)
1245         (if_then_else (match_operator 3 "boolean_operator"
1246                  [(and:SI (match_operand:SI 0 "register_operand" "r")
1247                           (match_operand:SI 1 "register_operand" "r"))
1248                   (const_int 0)])
1249                       (label_ref (match_operand 2 "" ""))
1250                       (pc)))]
1251   ""
1252 {
1253   switch (GET_CODE (operands[3]))
1254     {
1255     case EQ:            return "bnone\t%0, %1, %2";
1256     case NE:            return "bany\t%0, %1, %2";
1257     default:            gcc_unreachable ();
1258     }
1259 }
1260   [(set_attr "type"     "jump")
1261    (set_attr "mode"     "none")
1262    (set_attr "length"   "3")])
1263
1264 (define_insn "*maskfalse"
1265   [(set (pc)
1266         (if_then_else (match_operator 3 "boolean_operator"
1267                  [(and:SI (match_operand:SI 0 "register_operand" "r")
1268                           (match_operand:SI 1 "register_operand" "r"))
1269                   (const_int 0)])
1270                       (pc)
1271                       (label_ref (match_operand 2 "" ""))))]
1272   ""
1273 {
1274   switch (GET_CODE (operands[3]))
1275     {
1276     case EQ:            return "bany\t%0, %1, %2";
1277     case NE:            return "bnone\t%0, %1, %2";
1278     default:            gcc_unreachable ();
1279     }
1280 }
1281   [(set_attr "type"     "jump")
1282    (set_attr "mode"     "none")
1283    (set_attr "length"   "3")])
1284
1285
1286 ;; Zero-overhead looping support.
1287
1288 ;; Define the loop insns used by bct optimization to represent the
1289 ;; start and end of a zero-overhead loop.  This start template generates
1290 ;; the loop insn; the end template doesn't generate any instructions since
1291 ;; loop end is handled in hardware.
1292
1293 (define_insn "zero_cost_loop_start"
1294   [(set (pc)
1295         (if_then_else (ne (match_operand:SI 2 "register_operand" "0")
1296                           (const_int 1))
1297                       (label_ref (match_operand 1 "" ""))
1298                       (pc)))
1299    (set (match_operand:SI 0 "register_operand" "=a")
1300         (plus (match_dup 0)
1301               (const_int -1)))
1302    (unspec [(const_int 0)] UNSPEC_LSETUP_START)]
1303   "TARGET_LOOPS && optimize"
1304   "loop\t%0, %l1_LEND"
1305   [(set_attr "type"     "jump")
1306    (set_attr "mode"     "none")
1307    (set_attr "length"   "3")])
1308
1309 (define_insn "zero_cost_loop_end"
1310   [(set (pc)
1311         (if_then_else (ne (match_operand:SI 2 "nonimmediate_operand" "0,0")
1312                           (const_int 1))
1313                       (label_ref (match_operand 1 "" ""))
1314                       (pc)))
1315    (set (match_operand:SI 0 "nonimmediate_operand" "=a,m")
1316         (plus (match_dup 0)
1317               (const_int -1)))
1318    (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1319    (clobber (match_scratch:SI 3 "=X,&r"))]
1320   "TARGET_LOOPS && optimize"
1321   "#"
1322   [(set_attr "type"     "jump")
1323    (set_attr "mode"     "none")
1324    (set_attr "length"   "0")])
1325
1326 (define_insn "loop_end"
1327   [(set (pc)
1328         (if_then_else (ne (match_operand:SI 2 "register_operand" "0")
1329                           (const_int 1))
1330                       (label_ref (match_operand 1 "" ""))
1331                       (pc)))
1332    (set (match_operand:SI 0 "register_operand" "=a")
1333         (plus (match_dup 0)
1334               (const_int -1)))
1335    (unspec [(const_int 0)] UNSPEC_LSETUP_END)]
1336   "TARGET_LOOPS && optimize"
1337 {
1338   xtensa_emit_loop_end (insn, operands);
1339   return "";
1340 }
1341   [(set_attr "type"     "jump")
1342    (set_attr "mode"     "none")
1343    (set_attr "length"   "0")])
1344
1345 (define_split
1346   [(set (pc)
1347         (if_then_else (ne (match_operand:SI 0 "nonimmediate_operand" "")
1348                           (const_int 1))
1349                       (label_ref (match_operand 1 "" ""))
1350                       (pc)))
1351    (set (match_operand:SI 2 "nonimmediate_operand" "")
1352         (plus:SI (match_dup 0)
1353                  (const_int -1)))
1354    (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1355    (clobber (match_scratch 3))]
1356   "TARGET_LOOPS && optimize && reload_completed"
1357   [(const_int 0)]
1358 {
1359   if (!REG_P (operands[0]))
1360     {
1361       rtx test;
1362
1363       /* Fallback into a normal conditional branch insn.  */
1364       emit_move_insn (operands[3], operands[0]);
1365       emit_insn (gen_addsi3 (operands[3], operands[3], constm1_rtx));
1366       emit_move_insn (operands[0], operands[3]);
1367       test = gen_rtx_NE (VOIDmode, operands[3], const0_rtx);
1368       emit_jump_insn (gen_cbranchsi4 (test, operands[3],
1369                                       const0_rtx, operands[1]));
1370     }
1371   else
1372     {
1373       emit_jump_insn (gen_loop_end (operands[0], operands[1], operands[2]));
1374     }
1375
1376   DONE;
1377 })
1378
1379 ; operand 0 is the loop count pseudo register
1380 ; operand 1 is the label to jump to at the top of the loop
1381 (define_expand "doloop_end"
1382   [(parallel [(set (pc) (if_then_else
1383                           (ne (match_operand:SI 0 "" "")
1384                               (const_int 1))
1385                           (label_ref (match_operand 1 "" ""))
1386                           (pc)))
1387               (set (match_dup 0)
1388                    (plus:SI (match_dup 0)
1389                             (const_int -1)))
1390               (unspec [(const_int 0)] UNSPEC_LSETUP_END)
1391               (clobber (match_dup 2))])] ; match_scratch
1392   "TARGET_LOOPS && optimize"
1393 {
1394   /* The loop optimizer doesn't check the predicates... */
1395   if (GET_MODE (operands[0]) != SImode)
1396     FAIL;
1397   operands[2] = gen_rtx_SCRATCH (SImode);
1398 })
1399
1400 \f
1401 ;; Setting a register from a comparison.
1402
1403 (define_expand "cstoresi4"
1404   [(match_operand:SI 0 "register_operand")
1405    (match_operator 1 "xtensa_cstoresi_operator"
1406     [(match_operand:SI 2 "register_operand")
1407      (match_operand:SI 3 "nonmemory_operand")])]
1408   ""
1409 {
1410   if (!xtensa_expand_scc (operands, SImode))
1411     FAIL;
1412   DONE;
1413 })
1414
1415 (define_expand "cstoresf4"
1416   [(match_operand:SI 0 "register_operand")
1417    (match_operator:SI 1 "comparison_operator"
1418     [(match_operand:SF 2 "register_operand")
1419      (match_operand:SF 3 "register_operand")])]
1420   "TARGET_HARD_FLOAT"
1421 {
1422   if (!xtensa_expand_scc (operands, SFmode))
1423     FAIL;
1424   DONE;
1425 })
1426
1427
1428 \f
1429 ;; Conditional moves.
1430
1431 (define_expand "movsicc"
1432   [(set (match_operand:SI 0 "register_operand" "")
1433         (if_then_else:SI (match_operand 1 "comparison_operator" "")
1434                          (match_operand:SI 2 "register_operand" "")
1435                          (match_operand:SI 3 "register_operand" "")))]
1436   ""
1437 {
1438   if (!xtensa_expand_conditional_move (operands, 0))
1439     FAIL;
1440   DONE;
1441 })
1442
1443 (define_expand "movsfcc"
1444   [(set (match_operand:SF 0 "register_operand" "")
1445         (if_then_else:SF (match_operand 1 "comparison_operator" "")
1446                          (match_operand:SF 2 "register_operand" "")
1447                          (match_operand:SF 3 "register_operand" "")))]
1448   ""
1449 {
1450   if (!xtensa_expand_conditional_move (operands, 1))
1451     FAIL;
1452   DONE;
1453 })
1454
1455 (define_insn "movsicc_internal0"
1456   [(set (match_operand:SI 0 "register_operand" "=a,a")
1457         (if_then_else:SI (match_operator 4 "branch_operator"
1458                            [(match_operand:SI 1 "register_operand" "r,r")
1459                             (const_int 0)])
1460                          (match_operand:SI 2 "register_operand" "r,0")
1461                          (match_operand:SI 3 "register_operand" "0,r")))]
1462   ""
1463 {
1464   return xtensa_emit_movcc (which_alternative == 1, false, false, operands);
1465 }
1466   [(set_attr "type"     "move,move")
1467    (set_attr "mode"     "SI")
1468    (set_attr "length"   "3,3")])
1469
1470 (define_insn "movsicc_internal1"
1471   [(set (match_operand:SI 0 "register_operand" "=a,a")
1472         (if_then_else:SI (match_operator 4 "boolean_operator"
1473                            [(match_operand:CC 1 "register_operand" "b,b")
1474                             (const_int 0)])
1475                          (match_operand:SI 2 "register_operand" "r,0")
1476                          (match_operand:SI 3 "register_operand" "0,r")))]
1477   "TARGET_BOOLEANS"
1478 {
1479   return xtensa_emit_movcc (which_alternative == 1, false, true, operands);
1480 }
1481   [(set_attr "type"     "move,move")
1482    (set_attr "mode"     "SI")
1483    (set_attr "length"   "3,3")])
1484
1485 (define_insn "movsfcc_internal0"
1486   [(set (match_operand:SF 0 "register_operand" "=a,a,f,f")
1487         (if_then_else:SF (match_operator 4 "branch_operator"
1488                            [(match_operand:SI 1 "register_operand" "r,r,r,r")
1489                             (const_int 0)])
1490                          (match_operand:SF 2 "register_operand" "r,0,f,0")
1491                          (match_operand:SF 3 "register_operand" "0,r,0,f")))]
1492   ""
1493 {
1494   return xtensa_emit_movcc ((which_alternative & 1) == 1,
1495                             which_alternative >= 2, false, operands);
1496 }
1497   [(set_attr "type"     "move,move,move,move")
1498    (set_attr "mode"     "SF")
1499    (set_attr "length"   "3,3,3,3")])
1500
1501 (define_insn "movsfcc_internal1"
1502   [(set (match_operand:SF 0 "register_operand" "=a,a,f,f")
1503         (if_then_else:SF (match_operator 4 "boolean_operator"
1504                            [(match_operand:CC 1 "register_operand" "b,b,b,b")
1505                             (const_int 0)])
1506                          (match_operand:SF 2 "register_operand" "r,0,f,0")
1507                          (match_operand:SF 3 "register_operand" "0,r,0,f")))]
1508   "TARGET_BOOLEANS"
1509 {
1510   return xtensa_emit_movcc ((which_alternative & 1) == 1,
1511                             which_alternative >= 2, true, operands);
1512 }
1513   [(set_attr "type"     "move,move,move,move")
1514    (set_attr "mode"     "SF")
1515    (set_attr "length"   "3,3,3,3")])
1516
1517 \f
1518 ;; Floating-point comparisons.
1519
1520 (define_insn "s<code>_sf"
1521   [(set (match_operand:CC 0 "register_operand" "=b")
1522         (any_scc_sf:CC (match_operand:SF 1 "register_operand" "f")
1523                        (match_operand:SF 2 "register_operand" "f")))]
1524   "TARGET_HARD_FLOAT"
1525   "<scc_sf>.s\t%0, %1, %2"
1526   [(set_attr "type"     "farith")
1527    (set_attr "mode"     "BL")
1528    (set_attr "length"   "3")])
1529
1530 \f
1531 ;; Unconditional branches.
1532
1533 (define_insn "jump"
1534   [(set (pc)
1535         (label_ref (match_operand 0 "" "")))]
1536   ""
1537   "j\t%l0"
1538   [(set_attr "type"     "jump")
1539    (set_attr "mode"     "none")
1540    (set_attr "length"   "3")])
1541
1542 (define_expand "indirect_jump"
1543   [(set (pc)
1544         (match_operand 0 "register_operand" ""))]
1545   ""
1546 {
1547   rtx dest = operands[0];
1548   if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1549     operands[0] = copy_to_mode_reg (Pmode, dest);
1550
1551   emit_jump_insn (gen_indirect_jump_internal (dest));
1552   DONE;
1553 })
1554
1555 (define_insn "indirect_jump_internal"
1556   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1557   ""
1558   "jx\t%0"
1559   [(set_attr "type"     "jump")
1560    (set_attr "mode"     "none")
1561    (set_attr "length"   "3")])
1562
1563
1564 (define_expand "tablejump"
1565   [(use (match_operand:SI 0 "register_operand" ""))
1566    (use (label_ref (match_operand 1 "" "")))]
1567    ""
1568 {
1569   rtx target = operands[0];
1570   if (flag_pic)
1571     {
1572       /* For PIC, the table entry is relative to the start of the table.  */
1573       rtx label = gen_reg_rtx (SImode);
1574       target = gen_reg_rtx (SImode);
1575       emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1]));
1576       emit_insn (gen_addsi3 (target, operands[0], label));
1577     }
1578   emit_jump_insn (gen_tablejump_internal (target, operands[1]));
1579   DONE;
1580 })
1581
1582 (define_insn "tablejump_internal"
1583   [(set (pc)
1584         (match_operand:SI 0 "register_operand" "r"))
1585    (use (label_ref (match_operand 1 "" "")))]
1586   ""
1587   "jx\t%0"
1588   [(set_attr "type"     "jump")
1589    (set_attr "mode"     "none")
1590    (set_attr "length"   "3")])
1591
1592 \f
1593 ;; Function calls.
1594
1595 (define_expand "sym_PLT"
1596   [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PLT))]
1597   ""
1598   "")
1599
1600 (define_expand "call"
1601   [(call (match_operand 0 "memory_operand" "")
1602          (match_operand 1 "" ""))]
1603   ""
1604 {
1605   rtx addr = XEXP (operands[0], 0);
1606   if (flag_pic && GET_CODE (addr) == SYMBOL_REF
1607       && (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
1608     addr = gen_sym_PLT (addr);
1609   if (!call_insn_operand (addr, VOIDmode))
1610     XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1611 })
1612
1613 (define_insn "call_internal"
1614   [(call (mem (match_operand:SI 0 "call_insn_operand" "nir"))
1615          (match_operand 1 "" "i"))]
1616   ""
1617 {
1618   return xtensa_emit_call (0, operands);
1619 }
1620   [(set_attr "type"     "call")
1621    (set_attr "mode"     "none")
1622    (set_attr "length"   "3")])
1623
1624 (define_expand "call_value"
1625   [(set (match_operand 0 "register_operand" "")
1626         (call (match_operand 1 "memory_operand" "")
1627               (match_operand 2 "" "")))]
1628   ""
1629 {
1630   rtx addr = XEXP (operands[1], 0);
1631   if (flag_pic && GET_CODE (addr) == SYMBOL_REF
1632       && (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
1633     addr = gen_sym_PLT (addr);
1634   if (!call_insn_operand (addr, VOIDmode))
1635     XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1636 })
1637
1638 (define_insn "call_value_internal"
1639   [(set (match_operand 0 "register_operand" "=a")
1640         (call (mem (match_operand:SI 1 "call_insn_operand" "nir"))
1641               (match_operand 2 "" "i")))]
1642   ""
1643 {
1644   return xtensa_emit_call (1, operands);
1645 }
1646   [(set_attr "type"     "call")
1647    (set_attr "mode"     "none")
1648    (set_attr "length"   "3")])
1649
1650 (define_insn "entry"
1651   [(set (reg:SI A1_REG)
1652         (unspec_volatile:SI [(match_operand:SI 0 "const_int_operand" "i")]
1653                             UNSPECV_ENTRY))]
1654   ""
1655   "entry\tsp, %0"
1656   [(set_attr "type"     "entry")
1657    (set_attr "mode"     "SI")
1658    (set_attr "length"   "3")])
1659
1660 (define_insn "return"
1661   [(return)
1662    (use (reg:SI A0_REG))]
1663   "(TARGET_WINDOWED_ABI || !xtensa_current_frame_size) && reload_completed"
1664 {
1665   return TARGET_WINDOWED_ABI ?
1666       (TARGET_DENSITY ? "retw.n" : "retw") :
1667       (TARGET_DENSITY ? "ret.n" : "ret");
1668 }
1669   [(set_attr "type"     "jump")
1670    (set_attr "mode"     "none")
1671    (set_attr "length"   "2")])
1672
1673 \f
1674 ;; Miscellaneous instructions.
1675
1676 (define_expand "prologue"
1677   [(const_int 0)]
1678   ""
1679 {
1680   xtensa_expand_prologue ();
1681   DONE;
1682 })
1683
1684 (define_expand "epilogue"
1685   [(return)]
1686   ""
1687 {
1688   xtensa_expand_epilogue ();
1689   DONE;
1690 })
1691
1692 (define_insn "nop"
1693   [(const_int 0)]
1694   ""
1695 {
1696   return (TARGET_DENSITY ? "nop.n" : "nop");
1697 }
1698   [(set_attr "type"     "nop")
1699    (set_attr "mode"     "none")
1700    (set_attr "length"   "3")])
1701
1702 (define_expand "nonlocal_goto"
1703   [(match_operand:SI 0 "general_operand" "")
1704    (match_operand:SI 1 "general_operand" "")
1705    (match_operand:SI 2 "general_operand" "")
1706    (match_operand:SI 3 "" "")]
1707   "TARGET_WINDOWED_ABI"
1708 {
1709   xtensa_expand_nonlocal_goto (operands);
1710   DONE;
1711 })
1712
1713 ;; Stuff an address into the return address register along with the window
1714 ;; size in the high bits.  Because we don't have the window size of the
1715 ;; previous frame, assume the function called out with a CALL8 since that
1716 ;; is what compilers always use.  Note: __builtin_frob_return_addr has
1717 ;; already been applied to the handler, but the generic version doesn't
1718 ;; allow us to frob it quite enough, so we just frob here.
1719
1720 (define_expand "eh_return"
1721   [(use (match_operand 0 "general_operand"))]
1722   ""
1723 {
1724   if (TARGET_WINDOWED_ABI)
1725     emit_insn (gen_eh_set_a0_windowed (operands[0]));
1726   else
1727     emit_insn (gen_eh_set_a0_call0 (operands[0]));
1728   DONE;
1729 })
1730
1731 (define_insn_and_split "eh_set_a0_windowed"
1732   [(set (reg:SI A0_REG)
1733         (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
1734                             UNSPECV_EH_RETURN))
1735    (clobber (match_scratch:SI 1 "=r"))]
1736   ""
1737   "#"
1738   "reload_completed"
1739   [(set (match_dup 1) (ashift:SI (match_dup 0) (const_int 2)))
1740    (set (match_dup 1) (plus:SI (match_dup 1) (const_int 2)))
1741    (set (reg:SI A0_REG) (rotatert:SI (match_dup 1) (const_int 2)))]
1742   "")
1743
1744 (define_insn_and_split "eh_set_a0_call0"
1745   [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
1746                     UNSPECV_EH_RETURN)
1747    (clobber (match_scratch:SI 1 "=r"))]
1748   ""
1749   "#"
1750   "reload_completed"
1751   [(const_int 0)]
1752 {
1753   xtensa_set_return_address (operands[0], operands[1]);
1754   DONE;
1755 })
1756
1757 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1758 ;; all of memory.  This blocks insns from being moved across this point.
1759
1760 (define_insn "blockage"
1761   [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
1762   ""
1763   ""
1764   [(set_attr "length" "0")
1765    (set_attr "type" "nop")])
1766
1767 ;; Setting up a frame pointer is tricky for Xtensa because GCC doesn't
1768 ;; know if a frame pointer is required until the reload pass, and
1769 ;; because there may be an incoming argument value in the hard frame
1770 ;; pointer register (a7).  If there is an incoming argument in that
1771 ;; register, the "set_frame_ptr" insn gets inserted immediately after
1772 ;; the insn that copies the incoming argument to a pseudo or to the
1773 ;; stack.  This serves several purposes here: (1) it keeps the
1774 ;; optimizer from copy-propagating or scheduling the use of a7 as an
1775 ;; incoming argument away from the beginning of the function; (2) we
1776 ;; can use a post-reload splitter to expand away the insn if a frame
1777 ;; pointer is not required, so that the post-reload scheduler can do
1778 ;; the right thing; and (3) it makes it easy for the prologue expander
1779 ;; to search for this insn to determine whether it should add a new insn
1780 ;; to set up the frame pointer.
1781
1782 (define_insn "set_frame_ptr"
1783   [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
1784   ""
1785 {
1786   if (frame_pointer_needed)
1787     return "mov\ta7, sp";
1788   return "";
1789 }
1790   [(set_attr "type"     "move")
1791    (set_attr "mode"     "SI")
1792    (set_attr "length"   "3")])
1793
1794 ;; Post-reload splitter to remove fp assignment when it's not needed.
1795 (define_split
1796   [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
1797   "reload_completed && !frame_pointer_needed"
1798   [(unspec [(const_int 0)] UNSPEC_NOP)]
1799   "")
1800
1801 ;; The preceding splitter needs something to split the insn into;
1802 ;; things start breaking if the result is just a "use" so instead we
1803 ;; generate the following insn.
1804 (define_insn "*unspec_nop"
1805   [(unspec [(const_int 0)] UNSPEC_NOP)]
1806   ""
1807   ""
1808   [(set_attr "type"     "nop")
1809    (set_attr "mode"     "none")
1810    (set_attr "length"   "0")])
1811
1812 \f
1813 ;; TLS support
1814
1815 (define_expand "sym_TPOFF"
1816   [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_TPOFF))]
1817   ""
1818   "")
1819
1820 (define_expand "sym_DTPOFF"
1821   [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_DTPOFF))]
1822   ""
1823   "")
1824
1825 (define_insn "get_thread_pointersi"
1826   [(set (match_operand:SI 0 "register_operand" "=a")
1827         (unspec:SI [(const_int 0)] UNSPEC_TP))]
1828   "TARGET_THREADPTR"
1829   "rur\t%0, THREADPTR"
1830   [(set_attr "type"     "rsr")
1831    (set_attr "mode"     "SI")
1832    (set_attr "length"   "3")])
1833
1834 (define_insn "set_thread_pointersi"
1835   [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
1836                     UNSPECV_SET_TP)]
1837   "TARGET_THREADPTR"
1838   "wur\t%0, THREADPTR"
1839   [(set_attr "type"     "wsr")
1840    (set_attr "mode"     "SI")
1841    (set_attr "length"   "3")])
1842
1843 (define_insn "tls_func"
1844   [(set (match_operand:SI 0 "register_operand" "=a")
1845         (unspec:SI [(match_operand:SI 1 "tls_symbol_operand" "")]
1846                    UNSPEC_TLS_FUNC))]
1847   "TARGET_THREADPTR && HAVE_AS_TLS"
1848   "movi\t%0, %1@TLSFUNC"
1849   [(set_attr "type"     "load")
1850    (set_attr "mode"     "SI")
1851    (set_attr "length"   "3")])
1852
1853 (define_insn "tls_arg"
1854   [(set (match_operand:SI 0 "register_operand" "=a")
1855         (unspec:SI [(match_operand:SI 1 "tls_symbol_operand" "")]
1856                    UNSPEC_TLS_ARG))]
1857   "TARGET_THREADPTR && HAVE_AS_TLS"
1858   "movi\t%0, %1@TLSARG"
1859   [(set_attr "type"     "load")
1860    (set_attr "mode"     "SI")
1861    (set_attr "length"   "3")])
1862
1863 (define_insn "tls_call"
1864   [(set (match_operand:SI 0 "register_operand" "=a")
1865         (call (mem:SI (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1866                                   (match_operand:SI 2 "tls_symbol_operand" "")]
1867                                   UNSPEC_TLS_CALL))
1868               (match_operand 3 "" "i")))]
1869   "TARGET_THREADPTR && HAVE_AS_TLS"
1870   "callx8.tls %1, %2@TLSCALL"
1871   [(set_attr "type"     "call")
1872    (set_attr "mode"     "none")
1873    (set_attr "length"   "3")])
1874
1875 \f
1876 ;; Instructions for the Xtensa "boolean" option.
1877
1878 (define_insn "*booltrue"
1879   [(set (pc)
1880         (if_then_else (match_operator 2 "boolean_operator"
1881                          [(match_operand:CC 0 "register_operand" "b")
1882                           (const_int 0)])
1883                       (label_ref (match_operand 1 "" ""))
1884                       (pc)))]
1885   "TARGET_BOOLEANS"
1886 {
1887   if (GET_CODE (operands[2]) == EQ)
1888     return "bf\t%0, %1";
1889   else
1890     return "bt\t%0, %1";
1891 }
1892   [(set_attr "type"     "jump")
1893    (set_attr "mode"     "none")
1894    (set_attr "length"   "3")])
1895
1896 (define_insn "*boolfalse"
1897   [(set (pc)
1898         (if_then_else (match_operator 2 "boolean_operator"
1899                          [(match_operand:CC 0 "register_operand" "b")
1900                           (const_int 0)])
1901                       (pc)
1902                       (label_ref (match_operand 1 "" ""))))]
1903   "TARGET_BOOLEANS"
1904 {
1905   if (GET_CODE (operands[2]) == EQ)
1906     return "bt\t%0, %1";
1907   else
1908     return "bf\t%0, %1";
1909 }
1910   [(set_attr "type"     "jump")
1911    (set_attr "mode"     "none")
1912    (set_attr "length"   "3")])
1913
1914 \f
1915 ;; Atomic operations
1916
1917 (define_expand "memory_barrier"
1918   [(set (match_dup 0)
1919         (unspec:BLK [(match_dup 0)] UNSPEC_MEMW))]
1920   ""
1921 {
1922   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
1923   MEM_VOLATILE_P (operands[0]) = 1;
1924 })
1925
1926 (define_insn "*memory_barrier"
1927   [(set (match_operand:BLK 0 "" "")
1928         (unspec:BLK [(match_dup 0)] UNSPEC_MEMW))]
1929   ""
1930   "memw"
1931   [(set_attr "type"     "unknown")
1932    (set_attr "mode"     "none")
1933    (set_attr "length"   "3")])
1934
1935 ;; sync_lock_release is only implemented for SImode.
1936 ;; For other modes, just use the default of a store with a memory_barrier.
1937 (define_insn "sync_lock_releasesi"
1938   [(set (match_operand:SI 0 "mem_operand" "=U")
1939         (unspec_volatile:SI
1940           [(match_operand:SI 1 "register_operand" "r")]
1941           UNSPECV_S32RI))]
1942   "TARGET_RELEASE_SYNC"
1943   "s32ri\t%1, %0"
1944   [(set_attr "type"     "store")
1945    (set_attr "mode"     "SI")
1946    (set_attr "length"   "3")])
1947
1948 (define_insn "sync_compare_and_swapsi"
1949   [(parallel
1950     [(set (match_operand:SI 0 "register_operand" "=a")
1951           (match_operand:SI 1 "mem_operand" "+U"))
1952      (set (match_dup 1)
1953           (unspec_volatile:SI
1954             [(match_dup 1)
1955              (match_operand:SI 2 "register_operand" "r")
1956              (match_operand:SI 3 "register_operand" "0")]
1957             UNSPECV_S32C1I))])]
1958   "TARGET_S32C1I"
1959   "wsr\t%2, SCOMPARE1\;s32c1i\t%3, %1"
1960   [(set_attr "type"     "multi")
1961    (set_attr "mode"     "SI")
1962    (set_attr "length"   "6")])
1963
1964 (define_expand "sync_compare_and_swap<mode>"
1965   [(parallel
1966     [(set (match_operand:HQI 0 "register_operand" "")
1967           (match_operand:HQI 1 "mem_operand" ""))
1968      (set (match_dup 1)
1969           (unspec_volatile:HQI
1970             [(match_dup 1)
1971              (match_operand:HQI 2 "register_operand" "")
1972              (match_operand:HQI 3 "register_operand" "")]
1973             UNSPECV_S32C1I))])]
1974   "TARGET_S32C1I"
1975 {
1976   xtensa_expand_compare_and_swap (operands[0], operands[1],
1977                                   operands[2], operands[3]);
1978   DONE;
1979 })
1980
1981 (define_expand "sync_lock_test_and_set<mode>"
1982   [(match_operand:HQI 0 "register_operand")
1983    (match_operand:HQI 1 "memory_operand")
1984    (match_operand:HQI 2 "register_operand")]
1985   "TARGET_S32C1I"
1986 {
1987   xtensa_expand_atomic (SET, operands[0], operands[1], operands[2], false);
1988   DONE;
1989 })
1990
1991 (define_expand "sync_<atomic><mode>"
1992   [(set (match_operand:HQI 0 "memory_operand")
1993         (ATOMIC:HQI (match_dup 0)
1994                     (match_operand:HQI 1 "register_operand")))]
1995   "TARGET_S32C1I"
1996 {
1997   xtensa_expand_atomic (<CODE>, NULL_RTX, operands[0], operands[1], false);
1998   DONE;
1999 })
2000
2001 (define_expand "sync_old_<atomic><mode>"
2002   [(set (match_operand:HQI 0 "register_operand")
2003         (match_operand:HQI 1 "memory_operand"))
2004    (set (match_dup 1)
2005         (ATOMIC:HQI (match_dup 1)
2006                     (match_operand:HQI 2 "register_operand")))]
2007   "TARGET_S32C1I"
2008 {
2009   xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], false);
2010   DONE;
2011 })
2012
2013 (define_expand "sync_new_<atomic><mode>"
2014   [(set (match_operand:HQI 0 "register_operand")
2015         (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
2016                     (match_operand:HQI 2 "register_operand")))
2017    (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
2018   "TARGET_S32C1I"
2019 {
2020   xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], true);
2021   DONE;
2022 })