1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006-2019 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* The integrated register allocator (IRA) is a
22 regional register allocator performing graph coloring on a top-down
23 traversal of nested regions. Graph coloring in a region is based
24 on Chaitin-Briggs algorithm. It is called integrated because
25 register coalescing, register live range splitting, and choosing a
26 better hard register are done on-the-fly during coloring. Register
27 coalescing and choosing a cheaper hard register is done by hard
28 register preferencing during hard register assigning. The live
29 range splitting is a byproduct of the regional register allocation.
31 Major IRA notions are:
33 o *Region* is a part of CFG where graph coloring based on
34 Chaitin-Briggs algorithm is done. IRA can work on any set of
35 nested CFG regions forming a tree. Currently the regions are
36 the entire function for the root region and natural loops for
37 the other regions. Therefore data structure representing a
38 region is called loop_tree_node.
40 o *Allocno class* is a register class used for allocation of
41 given allocno. It means that only hard register of given
42 register class can be assigned to given allocno. In reality,
43 even smaller subset of (*profitable*) hard registers can be
44 assigned. In rare cases, the subset can be even smaller
45 because our modification of Chaitin-Briggs algorithm requires
46 that sets of hard registers can be assigned to allocnos forms a
47 forest, i.e. the sets can be ordered in a way where any
48 previous set is not intersected with given set or is a superset
51 o *Pressure class* is a register class belonging to a set of
52 register classes containing all of the hard-registers available
53 for register allocation. The set of all pressure classes for a
54 target is defined in the corresponding machine-description file
55 according some criteria. Register pressure is calculated only
56 for pressure classes and it affects some IRA decisions as
57 forming allocation regions.
59 o *Allocno* represents the live range of a pseudo-register in a
60 region. Besides the obvious attributes like the corresponding
61 pseudo-register number, allocno class, conflicting allocnos and
62 conflicting hard-registers, there are a few allocno attributes
63 which are important for understanding the allocation algorithm:
65 - *Live ranges*. This is a list of ranges of *program points*
66 where the allocno lives. Program points represent places
67 where a pseudo can be born or become dead (there are
68 approximately two times more program points than the insns)
69 and they are represented by integers starting with 0. The
70 live ranges are used to find conflicts between allocnos.
71 They also play very important role for the transformation of
72 the IRA internal representation of several regions into a one
73 region representation. The later is used during the reload
74 pass work because each allocno represents all of the
75 corresponding pseudo-registers.
77 - *Hard-register costs*. This is a vector of size equal to the
78 number of available hard-registers of the allocno class. The
79 cost of a callee-clobbered hard-register for an allocno is
80 increased by the cost of save/restore code around the calls
81 through the given allocno's life. If the allocno is a move
82 instruction operand and another operand is a hard-register of
83 the allocno class, the cost of the hard-register is decreased
86 When an allocno is assigned, the hard-register with minimal
87 full cost is used. Initially, a hard-register's full cost is
88 the corresponding value from the hard-register's cost vector.
89 If the allocno is connected by a *copy* (see below) to
90 another allocno which has just received a hard-register, the
91 cost of the hard-register is decreased. Before choosing a
92 hard-register for an allocno, the allocno's current costs of
93 the hard-registers are modified by the conflict hard-register
94 costs of all of the conflicting allocnos which are not
97 - *Conflict hard-register costs*. This is a vector of the same
98 size as the hard-register costs vector. To permit an
99 unassigned allocno to get a better hard-register, IRA uses
100 this vector to calculate the final full cost of the
101 available hard-registers. Conflict hard-register costs of an
102 unassigned allocno are also changed with a change of the
103 hard-register cost of the allocno when a copy involving the
104 allocno is processed as described above. This is done to
105 show other unassigned allocnos that a given allocno prefers
106 some hard-registers in order to remove the move instruction
107 corresponding to the copy.
109 o *Cap*. If a pseudo-register does not live in a region but
110 lives in a nested region, IRA creates a special allocno called
111 a cap in the outer region. A region cap is also created for a
114 o *Copy*. Allocnos can be connected by copies. Copies are used
115 to modify hard-register costs for allocnos during coloring.
116 Such modifications reflects a preference to use the same
117 hard-register for the allocnos connected by copies. Usually
118 copies are created for move insns (in this case it results in
119 register coalescing). But IRA also creates copies for operands
120 of an insn which should be assigned to the same hard-register
121 due to constraints in the machine description (it usually
122 results in removing a move generated in reload to satisfy
123 the constraints) and copies referring to the allocno which is
124 the output operand of an instruction and the allocno which is
125 an input operand dying in the instruction (creation of such
126 copies results in less register shuffling). IRA *does not*
127 create copies between the same register allocnos from different
128 regions because we use another technique for propagating
129 hard-register preference on the borders of regions.
131 Allocnos (including caps) for the upper region in the region tree
132 *accumulate* information important for coloring from allocnos with
133 the same pseudo-register from nested regions. This includes
134 hard-register and memory costs, conflicts with hard-registers,
135 allocno conflicts, allocno copies and more. *Thus, attributes for
136 allocnos in a region have the same values as if the region had no
137 subregions*. It means that attributes for allocnos in the
138 outermost region corresponding to the function have the same values
139 as though the allocation used only one region which is the entire
140 function. It also means that we can look at IRA work as if the
141 first IRA did allocation for all function then it improved the
142 allocation for loops then their subloops and so on.
144 IRA major passes are:
146 o Building IRA internal representation which consists of the
149 * First, IRA builds regions and creates allocnos (file
150 ira-build.c) and initializes most of their attributes.
152 * Then IRA finds an allocno class for each allocno and
153 calculates its initial (non-accumulated) cost of memory and
154 each hard-register of its allocno class (file ira-cost.c).
156 * IRA creates live ranges of each allocno, calculates register
157 pressure for each pressure class in each region, sets up
158 conflict hard registers for each allocno and info about calls
159 the allocno lives through (file ira-lives.c).
161 * IRA removes low register pressure loops from the regions
162 mostly to speed IRA up (file ira-build.c).
164 * IRA propagates accumulated allocno info from lower region
165 allocnos to corresponding upper region allocnos (file
168 * IRA creates all caps (file ira-build.c).
170 * Having live-ranges of allocnos and their classes, IRA creates
171 conflicting allocnos for each allocno. Conflicting allocnos
172 are stored as a bit vector or array of pointers to the
173 conflicting allocnos whatever is more profitable (file
174 ira-conflicts.c). At this point IRA creates allocno copies.
176 o Coloring. Now IRA has all necessary info to start graph coloring
177 process. It is done in each region on top-down traverse of the
178 region tree (file ira-color.c). There are following subpasses:
180 * Finding profitable hard registers of corresponding allocno
181 class for each allocno. For example, only callee-saved hard
182 registers are frequently profitable for allocnos living
183 through colors. If the profitable hard register set of
184 allocno does not form a tree based on subset relation, we use
185 some approximation to form the tree. This approximation is
186 used to figure out trivial colorability of allocnos. The
187 approximation is a pretty rare case.
189 * Putting allocnos onto the coloring stack. IRA uses Briggs
190 optimistic coloring which is a major improvement over
191 Chaitin's coloring. Therefore IRA does not spill allocnos at
192 this point. There is some freedom in the order of putting
193 allocnos on the stack which can affect the final result of
194 the allocation. IRA uses some heuristics to improve the
195 order. The major one is to form *threads* from colorable
196 allocnos and push them on the stack by threads. Thread is a
197 set of non-conflicting colorable allocnos connected by
198 copies. The thread contains allocnos from the colorable
199 bucket or colorable allocnos already pushed onto the coloring
200 stack. Pushing thread allocnos one after another onto the
201 stack increases chances of removing copies when the allocnos
202 get the same hard reg.
204 We also use a modification of Chaitin-Briggs algorithm which
205 works for intersected register classes of allocnos. To
206 figure out trivial colorability of allocnos, the mentioned
207 above tree of hard register sets is used. To get an idea how
208 the algorithm works in i386 example, let us consider an
209 allocno to which any general hard register can be assigned.
210 If the allocno conflicts with eight allocnos to which only
211 EAX register can be assigned, given allocno is still
212 trivially colorable because all conflicting allocnos might be
213 assigned only to EAX and all other general hard registers are
216 To get an idea of the used trivial colorability criterion, it
217 is also useful to read article "Graph-Coloring Register
218 Allocation for Irregular Architectures" by Michael D. Smith
219 and Glen Holloway. Major difference between the article
220 approach and approach used in IRA is that Smith's approach
221 takes register classes only from machine description and IRA
222 calculate register classes from intermediate code too
223 (e.g. an explicit usage of hard registers in RTL code for
224 parameter passing can result in creation of additional
225 register classes which contain or exclude the hard
226 registers). That makes IRA approach useful for improving
227 coloring even for architectures with regular register files
228 and in fact some benchmarking shows the improvement for
229 regular class architectures is even bigger than for irregular
230 ones. Another difference is that Smith's approach chooses
231 intersection of classes of all insn operands in which a given
232 pseudo occurs. IRA can use bigger classes if it is still
233 more profitable than memory usage.
235 * Popping the allocnos from the stack and assigning them hard
236 registers. If IRA cannot assign a hard register to an
237 allocno and the allocno is coalesced, IRA undoes the
238 coalescing and puts the uncoalesced allocnos onto the stack in
239 the hope that some such allocnos will get a hard register
240 separately. If IRA fails to assign hard register or memory
241 is more profitable for it, IRA spills the allocno. IRA
242 assigns the allocno the hard-register with minimal full
243 allocation cost which reflects the cost of usage of the
244 hard-register for the allocno and cost of usage of the
245 hard-register for allocnos conflicting with given allocno.
247 * Chaitin-Briggs coloring assigns as many pseudos as possible
248 to hard registers. After coloring we try to improve
249 allocation with cost point of view. We improve the
250 allocation by spilling some allocnos and assigning the freed
251 hard registers to other allocnos if it decreases the overall
254 * After allocno assigning in the region, IRA modifies the hard
255 register and memory costs for the corresponding allocnos in
256 the subregions to reflect the cost of possible loads, stores,
257 or moves on the border of the region and its subregions.
258 When default regional allocation algorithm is used
259 (-fira-algorithm=mixed), IRA just propagates the assignment
260 for allocnos if the register pressure in the region for the
261 corresponding pressure class is less than number of available
262 hard registers for given pressure class.
264 o Spill/restore code moving. When IRA performs an allocation
265 by traversing regions in top-down order, it does not know what
266 happens below in the region tree. Therefore, sometimes IRA
267 misses opportunities to perform a better allocation. A simple
268 optimization tries to improve allocation in a region having
269 subregions and containing in another region. If the
270 corresponding allocnos in the subregion are spilled, it spills
271 the region allocno if it is profitable. The optimization
272 implements a simple iterative algorithm performing profitable
273 transformations while they are still possible. It is fast in
274 practice, so there is no real need for a better time complexity
277 o Code change. After coloring, two allocnos representing the
278 same pseudo-register outside and inside a region respectively
279 may be assigned to different locations (hard-registers or
280 memory). In this case IRA creates and uses a new
281 pseudo-register inside the region and adds code to move allocno
282 values on the region's borders. This is done during top-down
283 traversal of the regions (file ira-emit.c). In some
284 complicated cases IRA can create a new allocno to move allocno
285 values (e.g. when a swap of values stored in two hard-registers
286 is needed). At this stage, the new allocno is marked as
287 spilled. IRA still creates the pseudo-register and the moves
288 on the region borders even when both allocnos were assigned to
289 the same hard-register. If the reload pass spills a
290 pseudo-register for some reason, the effect will be smaller
291 because another allocno will still be in the hard-register. In
292 most cases, this is better then spilling both allocnos. If
293 reload does not change the allocation for the two
294 pseudo-registers, the trivial move will be removed by
295 post-reload optimizations. IRA does not generate moves for
296 allocnos assigned to the same hard register when the default
297 regional allocation algorithm is used and the register pressure
298 in the region for the corresponding pressure class is less than
299 number of available hard registers for given pressure class.
300 IRA also does some optimizations to remove redundant stores and
301 to reduce code duplication on the region borders.
303 o Flattening internal representation. After changing code, IRA
304 transforms its internal representation for several regions into
305 one region representation (file ira-build.c). This process is
306 called IR flattening. Such process is more complicated than IR
307 rebuilding would be, but is much faster.
309 o After IR flattening, IRA tries to assign hard registers to all
310 spilled allocnos. This is implemented by a simple and fast
311 priority coloring algorithm (see function
312 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
313 created during the code change pass can be assigned to hard
316 o At the end IRA calls the reload pass. The reload pass
317 communicates with IRA through several functions in file
318 ira-color.c to improve its decisions in
320 * sharing stack slots for the spilled pseudos based on IRA info
321 about pseudo-register conflicts.
323 * reassigning hard-registers to all spilled pseudos at the end
324 of each reload iteration.
326 * choosing a better hard-register to spill based on IRA info
327 about pseudo-register live ranges and the register pressure
328 in places where the pseudo-register lives.
330 IRA uses a lot of data representing the target processors. These
331 data are initialized in file ira.c.
333 If function has no loops (or the loops are ignored when
334 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
335 coloring (only instead of separate pass of coalescing, we use hard
336 register preferencing). In such case, IRA works much faster
337 because many things are not made (like IR flattening, the
338 spill/restore optimization, and the code change).
340 Literature is worth to read for better understanding the code:
342 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
343 Graph Coloring Register Allocation.
345 o David Callahan, Brian Koblenz. Register allocation via
346 hierarchical graph coloring.
348 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
349 Coloring Register Allocation: A Study of the Chaitin-Briggs and
350 Callahan-Koblenz Algorithms.
352 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
353 Register Allocation Based on Graph Fusion.
355 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
356 Allocation for Irregular Architectures
358 o Vladimir Makarov. The Integrated Register Allocator for GCC.
360 o Vladimir Makarov. The top-down register allocator for irregular
361 register file architectures.
368 #include "coretypes.h"
374 #include "memmodel.h"
376 #include "insn-config.h"
380 #include "diagnostic-core.h"
382 #include "cfgbuild.h"
383 #include "cfgcleanup.h"
385 #include "tree-pass.h"
392 #include "rtl-iter.h"
393 #include "shrink-wrap.h"
394 #include "print-rtl.h"
396 struct target_ira default_target_ira
;
397 class target_ira_int default_target_ira_int
;
398 #if SWITCHABLE_TARGET
399 struct target_ira
*this_target_ira
= &default_target_ira
;
400 class target_ira_int
*this_target_ira_int
= &default_target_ira_int
;
403 /* A modified value of flag `-fira-verbose' used internally. */
404 int internal_flag_ira_verbose
;
406 /* Dump file of the allocator if it is not NULL. */
409 /* The number of elements in the following array. */
410 int ira_spilled_reg_stack_slots_num
;
412 /* The following array contains info about spilled pseudo-registers
413 stack slots used in current function so far. */
414 class ira_spilled_reg_stack_slot
*ira_spilled_reg_stack_slots
;
416 /* Correspondingly overall cost of the allocation, overall cost before
417 reload, cost of the allocnos assigned to hard-registers, cost of
418 the allocnos assigned to memory, cost of loads, stores and register
419 move insns generated for pseudo-register live range splitting (see
421 int64_t ira_overall_cost
, overall_cost_before
;
422 int64_t ira_reg_cost
, ira_mem_cost
;
423 int64_t ira_load_cost
, ira_store_cost
, ira_shuffle_cost
;
424 int ira_move_loops_num
, ira_additional_jumps_num
;
426 /* All registers that can be eliminated. */
428 HARD_REG_SET eliminable_regset
;
430 /* Value of max_reg_num () before IRA work start. This value helps
431 us to recognize a situation when new pseudos were created during
433 static int max_regno_before_ira
;
435 /* Temporary hard reg set used for a different calculation. */
436 static HARD_REG_SET temp_hard_regset
;
438 #define last_mode_for_init_move_cost \
439 (this_target_ira_int->x_last_mode_for_init_move_cost)
442 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
444 setup_reg_mode_hard_regset (void)
446 int i
, m
, hard_regno
;
448 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
449 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
451 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset
[hard_regno
][m
]);
452 for (i
= hard_regno_nregs (hard_regno
, (machine_mode
) m
) - 1;
454 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
455 SET_HARD_REG_BIT (ira_reg_mode_hard_regset
[hard_regno
][m
],
461 #define no_unit_alloc_regs \
462 (this_target_ira_int->x_no_unit_alloc_regs)
464 /* The function sets up the three arrays declared above. */
466 setup_class_hard_regs (void)
468 int cl
, i
, hard_regno
, n
;
469 HARD_REG_SET processed_hard_reg_set
;
471 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
472 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
474 temp_hard_regset
= reg_class_contents
[cl
];
475 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
476 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
477 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
479 ira_non_ordered_class_hard_regs
[cl
][i
] = -1;
480 ira_class_hard_reg_index
[cl
][i
] = -1;
482 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
484 #ifdef REG_ALLOC_ORDER
485 hard_regno
= reg_alloc_order
[i
];
489 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
491 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
492 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
493 ira_class_hard_reg_index
[cl
][hard_regno
] = -1;
496 ira_class_hard_reg_index
[cl
][hard_regno
] = n
;
497 ira_class_hard_regs
[cl
][n
++] = hard_regno
;
500 ira_class_hard_regs_num
[cl
] = n
;
501 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
502 if (TEST_HARD_REG_BIT (temp_hard_regset
, i
))
503 ira_non_ordered_class_hard_regs
[cl
][n
++] = i
;
504 ira_assert (ira_class_hard_regs_num
[cl
] == n
);
508 /* Set up global variables defining info about hard registers for the
509 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
510 that we can use the hard frame pointer for the allocation. */
512 setup_alloc_regs (bool use_hard_frame_p
)
514 #ifdef ADJUST_REG_ALLOC_ORDER
515 ADJUST_REG_ALLOC_ORDER
;
517 no_unit_alloc_regs
= fixed_nonglobal_reg_set
;
518 if (! use_hard_frame_p
)
519 SET_HARD_REG_BIT (no_unit_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
520 setup_class_hard_regs ();
525 #define alloc_reg_class_subclasses \
526 (this_target_ira_int->x_alloc_reg_class_subclasses)
528 /* Initialize the table of subclasses of each reg class. */
530 setup_reg_subclasses (void)
533 HARD_REG_SET temp_hard_regset2
;
535 for (i
= 0; i
< N_REG_CLASSES
; i
++)
536 for (j
= 0; j
< N_REG_CLASSES
; j
++)
537 alloc_reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
539 for (i
= 0; i
< N_REG_CLASSES
; i
++)
541 if (i
== (int) NO_REGS
)
544 temp_hard_regset
= reg_class_contents
[i
];
545 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
546 if (hard_reg_set_empty_p (temp_hard_regset
))
548 for (j
= 0; j
< N_REG_CLASSES
; j
++)
553 temp_hard_regset2
= reg_class_contents
[j
];
554 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
555 if (! hard_reg_set_subset_p (temp_hard_regset
,
558 p
= &alloc_reg_class_subclasses
[j
][0];
559 while (*p
!= LIM_REG_CLASSES
) p
++;
560 *p
= (enum reg_class
) i
;
567 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
569 setup_class_subset_and_memory_move_costs (void)
571 int cl
, cl2
, mode
, cost
;
572 HARD_REG_SET temp_hard_regset2
;
574 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
575 ira_memory_move_cost
[mode
][NO_REGS
][0]
576 = ira_memory_move_cost
[mode
][NO_REGS
][1] = SHRT_MAX
;
577 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
579 if (cl
!= (int) NO_REGS
)
580 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
582 ira_max_memory_move_cost
[mode
][cl
][0]
583 = ira_memory_move_cost
[mode
][cl
][0]
584 = memory_move_cost ((machine_mode
) mode
,
585 (reg_class_t
) cl
, false);
586 ira_max_memory_move_cost
[mode
][cl
][1]
587 = ira_memory_move_cost
[mode
][cl
][1]
588 = memory_move_cost ((machine_mode
) mode
,
589 (reg_class_t
) cl
, true);
590 /* Costs for NO_REGS are used in cost calculation on the
591 1st pass when the preferred register classes are not
592 known yet. In this case we take the best scenario. */
593 if (ira_memory_move_cost
[mode
][NO_REGS
][0]
594 > ira_memory_move_cost
[mode
][cl
][0])
595 ira_max_memory_move_cost
[mode
][NO_REGS
][0]
596 = ira_memory_move_cost
[mode
][NO_REGS
][0]
597 = ira_memory_move_cost
[mode
][cl
][0];
598 if (ira_memory_move_cost
[mode
][NO_REGS
][1]
599 > ira_memory_move_cost
[mode
][cl
][1])
600 ira_max_memory_move_cost
[mode
][NO_REGS
][1]
601 = ira_memory_move_cost
[mode
][NO_REGS
][1]
602 = ira_memory_move_cost
[mode
][cl
][1];
605 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
606 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
608 temp_hard_regset
= reg_class_contents
[cl
];
609 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
610 temp_hard_regset2
= reg_class_contents
[cl2
];
611 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
612 ira_class_subset_p
[cl
][cl2
]
613 = hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
);
614 if (! hard_reg_set_empty_p (temp_hard_regset2
)
615 && hard_reg_set_subset_p (reg_class_contents
[cl2
],
616 reg_class_contents
[cl
]))
617 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
619 cost
= ira_memory_move_cost
[mode
][cl2
][0];
620 if (cost
> ira_max_memory_move_cost
[mode
][cl
][0])
621 ira_max_memory_move_cost
[mode
][cl
][0] = cost
;
622 cost
= ira_memory_move_cost
[mode
][cl2
][1];
623 if (cost
> ira_max_memory_move_cost
[mode
][cl
][1])
624 ira_max_memory_move_cost
[mode
][cl
][1] = cost
;
627 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
628 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
630 ira_memory_move_cost
[mode
][cl
][0]
631 = ira_max_memory_move_cost
[mode
][cl
][0];
632 ira_memory_move_cost
[mode
][cl
][1]
633 = ira_max_memory_move_cost
[mode
][cl
][1];
635 setup_reg_subclasses ();
640 /* Define the following macro if allocation through malloc if
642 #define IRA_NO_OBSTACK
644 #ifndef IRA_NO_OBSTACK
645 /* Obstack used for storing all dynamic data (except bitmaps) of the
647 static struct obstack ira_obstack
;
650 /* Obstack used for storing all bitmaps of the IRA. */
651 static struct bitmap_obstack ira_bitmap_obstack
;
653 /* Allocate memory of size LEN for IRA data. */
655 ira_allocate (size_t len
)
659 #ifndef IRA_NO_OBSTACK
660 res
= obstack_alloc (&ira_obstack
, len
);
667 /* Free memory ADDR allocated for IRA data. */
669 ira_free (void *addr ATTRIBUTE_UNUSED
)
671 #ifndef IRA_NO_OBSTACK
679 /* Allocate and returns bitmap for IRA. */
681 ira_allocate_bitmap (void)
683 return BITMAP_ALLOC (&ira_bitmap_obstack
);
686 /* Free bitmap B allocated for IRA. */
688 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
695 /* Output information about allocation of all allocnos (except for
696 caps) into file F. */
698 ira_print_disposition (FILE *f
)
704 fprintf (f
, "Disposition:");
705 max_regno
= max_reg_num ();
706 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
707 for (a
= ira_regno_allocno_map
[i
];
709 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
714 fprintf (f
, " %4d:r%-4d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
715 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
716 fprintf (f
, "b%-3d", bb
->index
);
718 fprintf (f
, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
719 if (ALLOCNO_HARD_REGNO (a
) >= 0)
720 fprintf (f
, " %3d", ALLOCNO_HARD_REGNO (a
));
727 /* Outputs information about allocation of all allocnos into
730 ira_debug_disposition (void)
732 ira_print_disposition (stderr
);
737 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
738 register class containing stack registers or NO_REGS if there are
739 no stack registers. To find this class, we iterate through all
740 register pressure classes and choose the first register pressure
741 class containing all the stack registers and having the biggest
744 setup_stack_reg_pressure_class (void)
746 ira_stack_reg_pressure_class
= NO_REGS
;
751 HARD_REG_SET temp_hard_regset2
;
753 CLEAR_HARD_REG_SET (temp_hard_regset
);
754 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
755 SET_HARD_REG_BIT (temp_hard_regset
, i
);
757 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
759 cl
= ira_pressure_classes
[i
];
760 temp_hard_regset2
= temp_hard_regset
;
761 AND_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
762 size
= hard_reg_set_size (temp_hard_regset2
);
766 ira_stack_reg_pressure_class
= cl
;
773 /* Find pressure classes which are register classes for which we
774 calculate register pressure in IRA, register pressure sensitive
775 insn scheduling, and register pressure sensitive loop invariant
778 To make register pressure calculation easy, we always use
779 non-intersected register pressure classes. A move of hard
780 registers from one register pressure class is not more expensive
781 than load and store of the hard registers. Most likely an allocno
782 class will be a subset of a register pressure class and in many
783 cases a register pressure class. That makes usage of register
784 pressure classes a good approximation to find a high register
787 setup_pressure_classes (void)
789 int cost
, i
, n
, curr
;
791 enum reg_class pressure_classes
[N_REG_CLASSES
];
793 HARD_REG_SET temp_hard_regset2
;
796 if (targetm
.compute_pressure_classes
)
797 n
= targetm
.compute_pressure_classes (pressure_classes
);
801 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
803 if (ira_class_hard_regs_num
[cl
] == 0)
805 if (ira_class_hard_regs_num
[cl
] != 1
806 /* A register class without subclasses may contain a few
807 hard registers and movement between them is costly
808 (e.g. SPARC FPCC registers). We still should consider it
809 as a candidate for a pressure class. */
810 && alloc_reg_class_subclasses
[cl
][0] < cl
)
812 /* Check that the moves between any hard registers of the
813 current class are not more expensive for a legal mode
814 than load/store of the hard registers of the current
815 class. Such class is a potential candidate to be a
816 register pressure class. */
817 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
819 temp_hard_regset
= reg_class_contents
[cl
];
820 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
821 AND_COMPL_HARD_REG_SET (temp_hard_regset
,
822 ira_prohibited_class_mode_regs
[cl
][m
]);
823 if (hard_reg_set_empty_p (temp_hard_regset
))
825 ira_init_register_move_cost_if_necessary ((machine_mode
) m
);
826 cost
= ira_register_move_cost
[m
][cl
][cl
];
827 if (cost
<= ira_max_memory_move_cost
[m
][cl
][1]
828 || cost
<= ira_max_memory_move_cost
[m
][cl
][0])
831 if (m
>= NUM_MACHINE_MODES
)
836 temp_hard_regset
= reg_class_contents
[cl
];
837 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
838 /* Remove so far added pressure classes which are subset of the
839 current candidate class. Prefer GENERAL_REGS as a pressure
840 register class to another class containing the same
841 allocatable hard registers. We do this because machine
842 dependent cost hooks might give wrong costs for the latter
843 class but always give the right cost for the former class
845 for (i
= 0; i
< n
; i
++)
847 cl2
= pressure_classes
[i
];
848 temp_hard_regset2
= reg_class_contents
[cl2
];
849 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
850 if (hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
)
851 && (! hard_reg_set_equal_p (temp_hard_regset
,
853 || cl2
== (int) GENERAL_REGS
))
855 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
859 if (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
)
860 && (! hard_reg_set_equal_p (temp_hard_regset2
,
862 || cl
== (int) GENERAL_REGS
))
864 if (hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
))
866 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
868 /* If the current candidate is a subset of a so far added
869 pressure class, don't add it to the list of the pressure
872 pressure_classes
[curr
++] = (enum reg_class
) cl
;
876 #ifdef ENABLE_IRA_CHECKING
878 HARD_REG_SET ignore_hard_regs
;
880 /* Check pressure classes correctness: here we check that hard
881 registers from all register pressure classes contains all hard
882 registers available for the allocation. */
883 CLEAR_HARD_REG_SET (temp_hard_regset
);
884 CLEAR_HARD_REG_SET (temp_hard_regset2
);
885 ignore_hard_regs
= no_unit_alloc_regs
;
886 for (cl
= 0; cl
< LIM_REG_CLASSES
; cl
++)
888 /* For some targets (like MIPS with MD_REGS), there are some
889 classes with hard registers available for allocation but
890 not able to hold value of any mode. */
891 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
892 if (contains_reg_of_mode
[cl
][m
])
894 if (m
>= NUM_MACHINE_MODES
)
896 IOR_HARD_REG_SET (ignore_hard_regs
, reg_class_contents
[cl
]);
899 for (i
= 0; i
< n
; i
++)
900 if ((int) pressure_classes
[i
] == cl
)
902 IOR_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
904 IOR_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
906 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
907 /* Some targets (like SPARC with ICC reg) have allocatable regs
908 for which no reg class is defined. */
909 if (REGNO_REG_CLASS (i
) == NO_REGS
)
910 SET_HARD_REG_BIT (ignore_hard_regs
, i
);
911 AND_COMPL_HARD_REG_SET (temp_hard_regset
, ignore_hard_regs
);
912 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, ignore_hard_regs
);
913 ira_assert (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
));
916 ira_pressure_classes_num
= 0;
917 for (i
= 0; i
< n
; i
++)
919 cl
= (int) pressure_classes
[i
];
920 ira_reg_pressure_class_p
[cl
] = true;
921 ira_pressure_classes
[ira_pressure_classes_num
++] = (enum reg_class
) cl
;
923 setup_stack_reg_pressure_class ();
926 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class
927 whose register move cost between any registers of the class is the
928 same as for all its subclasses. We use the data to speed up the
929 2nd pass of calculations of allocno costs. */
931 setup_uniform_class_p (void)
935 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
937 ira_uniform_class_p
[cl
] = false;
938 if (ira_class_hard_regs_num
[cl
] == 0)
940 /* We cannot use alloc_reg_class_subclasses here because move
941 cost hooks does not take into account that some registers are
942 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS
943 is element of alloc_reg_class_subclasses for GENERAL_REGS
944 because SSE regs are unavailable. */
945 for (i
= 0; (cl2
= reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
; i
++)
947 if (ira_class_hard_regs_num
[cl2
] == 0)
949 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
950 if (contains_reg_of_mode
[cl
][m
] && contains_reg_of_mode
[cl2
][m
])
952 ira_init_register_move_cost_if_necessary ((machine_mode
) m
);
953 if (ira_register_move_cost
[m
][cl
][cl
]
954 != ira_register_move_cost
[m
][cl2
][cl2
])
957 if (m
< NUM_MACHINE_MODES
)
960 if (cl2
== LIM_REG_CLASSES
)
961 ira_uniform_class_p
[cl
] = true;
965 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
966 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
968 Target may have many subtargets and not all target hard registers can
969 be used for allocation, e.g. x86 port in 32-bit mode cannot use
970 hard registers introduced in x86-64 like r8-r15). Some classes
971 might have the same allocatable hard registers, e.g. INDEX_REGS
972 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
973 calculations efforts we introduce allocno classes which contain
974 unique non-empty sets of allocatable hard-registers.
976 Pseudo class cost calculation in ira-costs.c is very expensive.
977 Therefore we are trying to decrease number of classes involved in
978 such calculation. Register classes used in the cost calculation
979 are called important classes. They are allocno classes and other
980 non-empty classes whose allocatable hard register sets are inside
981 of an allocno class hard register set. From the first sight, it
982 looks like that they are just allocno classes. It is not true. In
983 example of x86-port in 32-bit mode, allocno classes will contain
984 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
985 registers are the same for the both classes). The important
986 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
987 because a machine description insn constraint may refers for
988 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
989 of the insn constraints. */
991 setup_allocno_and_important_classes (void)
995 HARD_REG_SET temp_hard_regset2
;
996 static enum reg_class classes
[LIM_REG_CLASSES
+ 1];
999 /* Collect classes which contain unique sets of allocatable hard
1000 registers. Prefer GENERAL_REGS to other classes containing the
1001 same set of hard registers. */
1002 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
1004 temp_hard_regset
= reg_class_contents
[i
];
1005 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1006 for (j
= 0; j
< n
; j
++)
1009 temp_hard_regset2
= reg_class_contents
[cl
];
1010 AND_COMPL_HARD_REG_SET (temp_hard_regset2
,
1011 no_unit_alloc_regs
);
1012 if (hard_reg_set_equal_p (temp_hard_regset
,
1016 if (j
>= n
|| targetm
.additional_allocno_class_p (i
))
1017 classes
[n
++] = (enum reg_class
) i
;
1018 else if (i
== GENERAL_REGS
)
1019 /* Prefer general regs. For i386 example, it means that
1020 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
1021 (all of them consists of the same available hard
1023 classes
[j
] = (enum reg_class
) i
;
1025 classes
[n
] = LIM_REG_CLASSES
;
1027 /* Set up classes which can be used for allocnos as classes
1028 containing non-empty unique sets of allocatable hard
1030 ira_allocno_classes_num
= 0;
1031 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
1032 if (ira_class_hard_regs_num
[cl
] > 0)
1033 ira_allocno_classes
[ira_allocno_classes_num
++] = (enum reg_class
) cl
;
1034 ira_important_classes_num
= 0;
1035 /* Add non-allocno classes containing to non-empty set of
1036 allocatable hard regs. */
1037 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1038 if (ira_class_hard_regs_num
[cl
] > 0)
1040 temp_hard_regset
= reg_class_contents
[cl
];
1041 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1043 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1045 temp_hard_regset2
= reg_class_contents
[ira_allocno_classes
[j
]];
1046 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
1047 if ((enum reg_class
) cl
== ira_allocno_classes
[j
])
1049 else if (hard_reg_set_subset_p (temp_hard_regset
,
1053 if (set_p
&& j
>= ira_allocno_classes_num
)
1054 ira_important_classes
[ira_important_classes_num
++]
1055 = (enum reg_class
) cl
;
1057 /* Now add allocno classes to the important classes. */
1058 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1059 ira_important_classes
[ira_important_classes_num
++]
1060 = ira_allocno_classes
[j
];
1061 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1063 ira_reg_allocno_class_p
[cl
] = false;
1064 ira_reg_pressure_class_p
[cl
] = false;
1066 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1067 ira_reg_allocno_class_p
[ira_allocno_classes
[j
]] = true;
1068 setup_pressure_classes ();
1069 setup_uniform_class_p ();
1072 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1073 given by array CLASSES of length CLASSES_NUM. The function is used
1074 make translation any reg class to an allocno class or to an
1075 pressure class. This translation is necessary for some
1076 calculations when we can use only allocno or pressure classes and
1077 such translation represents an approximate representation of all
1080 The translation in case when allocatable hard register set of a
1081 given class is subset of allocatable hard register set of a class
1082 in CLASSES is pretty simple. We use smallest classes from CLASSES
1083 containing a given class. If allocatable hard register set of a
1084 given class is not a subset of any corresponding set of a class
1085 from CLASSES, we use the cheapest (with load/store point of view)
1086 class from CLASSES whose set intersects with given class set. */
1088 setup_class_translate_array (enum reg_class
*class_translate
,
1089 int classes_num
, enum reg_class
*classes
)
1092 enum reg_class aclass
, best_class
, *cl_ptr
;
1093 int i
, cost
, min_cost
, best_cost
;
1095 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1096 class_translate
[cl
] = NO_REGS
;
1098 for (i
= 0; i
< classes_num
; i
++)
1100 aclass
= classes
[i
];
1101 for (cl_ptr
= &alloc_reg_class_subclasses
[aclass
][0];
1102 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
1104 if (class_translate
[cl
] == NO_REGS
)
1105 class_translate
[cl
] = aclass
;
1106 class_translate
[aclass
] = aclass
;
1108 /* For classes which are not fully covered by one of given classes
1109 (in other words covered by more one given class), use the
1111 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1113 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
1115 best_class
= NO_REGS
;
1116 best_cost
= INT_MAX
;
1117 for (i
= 0; i
< classes_num
; i
++)
1119 aclass
= classes
[i
];
1120 temp_hard_regset
= reg_class_contents
[aclass
];
1121 AND_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1122 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1123 if (! hard_reg_set_empty_p (temp_hard_regset
))
1126 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1128 cost
= (ira_memory_move_cost
[mode
][aclass
][0]
1129 + ira_memory_move_cost
[mode
][aclass
][1]);
1130 if (min_cost
> cost
)
1133 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
1135 best_class
= aclass
;
1136 best_cost
= min_cost
;
1140 class_translate
[cl
] = best_class
;
1144 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1145 IRA_PRESSURE_CLASS_TRANSLATE. */
1147 setup_class_translate (void)
1149 setup_class_translate_array (ira_allocno_class_translate
,
1150 ira_allocno_classes_num
, ira_allocno_classes
);
1151 setup_class_translate_array (ira_pressure_class_translate
,
1152 ira_pressure_classes_num
, ira_pressure_classes
);
1155 /* Order numbers of allocno classes in original target allocno class
1156 array, -1 for non-allocno classes. */
1157 static int allocno_class_order
[N_REG_CLASSES
];
1159 /* The function used to sort the important classes. */
1161 comp_reg_classes_func (const void *v1p
, const void *v2p
)
1163 enum reg_class cl1
= *(const enum reg_class
*) v1p
;
1164 enum reg_class cl2
= *(const enum reg_class
*) v2p
;
1165 enum reg_class tcl1
, tcl2
;
1168 tcl1
= ira_allocno_class_translate
[cl1
];
1169 tcl2
= ira_allocno_class_translate
[cl2
];
1170 if (tcl1
!= NO_REGS
&& tcl2
!= NO_REGS
1171 && (diff
= allocno_class_order
[tcl1
] - allocno_class_order
[tcl2
]) != 0)
1173 return (int) cl1
- (int) cl2
;
1176 /* For correct work of function setup_reg_class_relation we need to
1177 reorder important classes according to the order of their allocno
1178 classes. It places important classes containing the same
1179 allocatable hard register set adjacent to each other and allocno
1180 class with the allocatable hard register set right after the other
1181 important classes with the same set.
1183 In example from comments of function
1184 setup_allocno_and_important_classes, it places LEGACY_REGS and
1185 GENERAL_REGS close to each other and GENERAL_REGS is after
1188 reorder_important_classes (void)
1192 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1193 allocno_class_order
[i
] = -1;
1194 for (i
= 0; i
< ira_allocno_classes_num
; i
++)
1195 allocno_class_order
[ira_allocno_classes
[i
]] = i
;
1196 qsort (ira_important_classes
, ira_important_classes_num
,
1197 sizeof (enum reg_class
), comp_reg_classes_func
);
1198 for (i
= 0; i
< ira_important_classes_num
; i
++)
1199 ira_important_class_nums
[ira_important_classes
[i
]] = i
;
1202 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1203 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1204 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1205 please see corresponding comments in ira-int.h. */
1207 setup_reg_class_relations (void)
1209 int i
, cl1
, cl2
, cl3
;
1210 HARD_REG_SET intersection_set
, union_set
, temp_set2
;
1211 bool important_class_p
[N_REG_CLASSES
];
1213 memset (important_class_p
, 0, sizeof (important_class_p
));
1214 for (i
= 0; i
< ira_important_classes_num
; i
++)
1215 important_class_p
[ira_important_classes
[i
]] = true;
1216 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1218 ira_reg_class_super_classes
[cl1
][0] = LIM_REG_CLASSES
;
1219 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1221 ira_reg_classes_intersect_p
[cl1
][cl2
] = false;
1222 ira_reg_class_intersect
[cl1
][cl2
] = NO_REGS
;
1223 ira_reg_class_subset
[cl1
][cl2
] = NO_REGS
;
1224 temp_hard_regset
= reg_class_contents
[cl1
];
1225 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1226 temp_set2
= reg_class_contents
[cl2
];
1227 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1228 if (hard_reg_set_empty_p (temp_hard_regset
)
1229 && hard_reg_set_empty_p (temp_set2
))
1231 /* The both classes have no allocatable hard registers
1232 -- take all class hard registers into account and use
1233 reg_class_subunion and reg_class_superunion. */
1236 cl3
= reg_class_subclasses
[cl1
][i
];
1237 if (cl3
== LIM_REG_CLASSES
)
1239 if (reg_class_subset_p (ira_reg_class_intersect
[cl1
][cl2
],
1240 (enum reg_class
) cl3
))
1241 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1243 ira_reg_class_subunion
[cl1
][cl2
] = reg_class_subunion
[cl1
][cl2
];
1244 ira_reg_class_superunion
[cl1
][cl2
] = reg_class_superunion
[cl1
][cl2
];
1247 ira_reg_classes_intersect_p
[cl1
][cl2
]
1248 = hard_reg_set_intersect_p (temp_hard_regset
, temp_set2
);
1249 if (important_class_p
[cl1
] && important_class_p
[cl2
]
1250 && hard_reg_set_subset_p (temp_hard_regset
, temp_set2
))
1252 /* CL1 and CL2 are important classes and CL1 allocatable
1253 hard register set is inside of CL2 allocatable hard
1254 registers -- make CL1 a superset of CL2. */
1257 p
= &ira_reg_class_super_classes
[cl1
][0];
1258 while (*p
!= LIM_REG_CLASSES
)
1260 *p
++ = (enum reg_class
) cl2
;
1261 *p
= LIM_REG_CLASSES
;
1263 ira_reg_class_subunion
[cl1
][cl2
] = NO_REGS
;
1264 ira_reg_class_superunion
[cl1
][cl2
] = NO_REGS
;
1265 intersection_set
= reg_class_contents
[cl1
];
1266 AND_HARD_REG_SET (intersection_set
, reg_class_contents
[cl2
]);
1267 AND_COMPL_HARD_REG_SET (intersection_set
, no_unit_alloc_regs
);
1268 union_set
= reg_class_contents
[cl1
];
1269 IOR_HARD_REG_SET (union_set
, reg_class_contents
[cl2
]);
1270 AND_COMPL_HARD_REG_SET (union_set
, no_unit_alloc_regs
);
1271 for (cl3
= 0; cl3
< N_REG_CLASSES
; cl3
++)
1273 temp_hard_regset
= reg_class_contents
[cl3
];
1274 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1275 if (hard_reg_set_subset_p (temp_hard_regset
, intersection_set
))
1277 /* CL3 allocatable hard register set is inside of
1278 intersection of allocatable hard register sets
1280 if (important_class_p
[cl3
])
1283 = (reg_class_contents
1284 [ira_reg_class_intersect
[cl1
][cl2
]]);
1285 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1286 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1287 /* If the allocatable hard register sets are
1288 the same, prefer GENERAL_REGS or the
1289 smallest class for debugging
1291 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1292 && (cl3
== GENERAL_REGS
1293 || ((ira_reg_class_intersect
[cl1
][cl2
]
1295 && hard_reg_set_subset_p
1296 (reg_class_contents
[cl3
],
1299 ira_reg_class_intersect
[cl1
][cl2
]])))))
1300 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1303 = reg_class_contents
[ira_reg_class_subset
[cl1
][cl2
]];
1304 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1305 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1306 /* Ignore unavailable hard registers and prefer
1307 smallest class for debugging purposes. */
1308 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1309 && hard_reg_set_subset_p
1310 (reg_class_contents
[cl3
],
1312 [(int) ira_reg_class_subset
[cl1
][cl2
]])))
1313 ira_reg_class_subset
[cl1
][cl2
] = (enum reg_class
) cl3
;
1315 if (important_class_p
[cl3
]
1316 && hard_reg_set_subset_p (temp_hard_regset
, union_set
))
1318 /* CL3 allocatable hard register set is inside of
1319 union of allocatable hard register sets of CL1
1322 = reg_class_contents
[ira_reg_class_subunion
[cl1
][cl2
]];
1323 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1324 if (ira_reg_class_subunion
[cl1
][cl2
] == NO_REGS
1325 || (hard_reg_set_subset_p (temp_set2
, temp_hard_regset
)
1327 && (! hard_reg_set_equal_p (temp_set2
,
1329 || cl3
== GENERAL_REGS
1330 /* If the allocatable hard register sets are the
1331 same, prefer GENERAL_REGS or the smallest
1332 class for debugging purposes. */
1333 || (ira_reg_class_subunion
[cl1
][cl2
] != GENERAL_REGS
1334 && hard_reg_set_subset_p
1335 (reg_class_contents
[cl3
],
1337 [(int) ira_reg_class_subunion
[cl1
][cl2
]])))))
1338 ira_reg_class_subunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1340 if (hard_reg_set_subset_p (union_set
, temp_hard_regset
))
1342 /* CL3 allocatable hard register set contains union
1343 of allocatable hard register sets of CL1 and
1346 = reg_class_contents
[ira_reg_class_superunion
[cl1
][cl2
]];
1347 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1348 if (ira_reg_class_superunion
[cl1
][cl2
] == NO_REGS
1349 || (hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1351 && (! hard_reg_set_equal_p (temp_set2
,
1353 || cl3
== GENERAL_REGS
1354 /* If the allocatable hard register sets are the
1355 same, prefer GENERAL_REGS or the smallest
1356 class for debugging purposes. */
1357 || (ira_reg_class_superunion
[cl1
][cl2
] != GENERAL_REGS
1358 && hard_reg_set_subset_p
1359 (reg_class_contents
[cl3
],
1361 [(int) ira_reg_class_superunion
[cl1
][cl2
]])))))
1362 ira_reg_class_superunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1369 /* Output all uniform and important classes into file F. */
1371 print_uniform_and_important_classes (FILE *f
)
1375 fprintf (f
, "Uniform classes:\n");
1376 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1377 if (ira_uniform_class_p
[cl
])
1378 fprintf (f
, " %s", reg_class_names
[cl
]);
1379 fprintf (f
, "\nImportant classes:\n");
1380 for (i
= 0; i
< ira_important_classes_num
; i
++)
1381 fprintf (f
, " %s", reg_class_names
[ira_important_classes
[i
]]);
1385 /* Output all possible allocno or pressure classes and their
1386 translation map into file F. */
1388 print_translated_classes (FILE *f
, bool pressure_p
)
1390 int classes_num
= (pressure_p
1391 ? ira_pressure_classes_num
: ira_allocno_classes_num
);
1392 enum reg_class
*classes
= (pressure_p
1393 ? ira_pressure_classes
: ira_allocno_classes
);
1394 enum reg_class
*class_translate
= (pressure_p
1395 ? ira_pressure_class_translate
1396 : ira_allocno_class_translate
);
1399 fprintf (f
, "%s classes:\n", pressure_p
? "Pressure" : "Allocno");
1400 for (i
= 0; i
< classes_num
; i
++)
1401 fprintf (f
, " %s", reg_class_names
[classes
[i
]]);
1402 fprintf (f
, "\nClass translation:\n");
1403 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1404 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
1405 reg_class_names
[class_translate
[i
]]);
1408 /* Output all possible allocno and translation classes and the
1409 translation maps into stderr. */
1411 ira_debug_allocno_classes (void)
1413 print_uniform_and_important_classes (stderr
);
1414 print_translated_classes (stderr
, false);
1415 print_translated_classes (stderr
, true);
1418 /* Set up different arrays concerning class subsets, allocno and
1419 important classes. */
1421 find_reg_classes (void)
1423 setup_allocno_and_important_classes ();
1424 setup_class_translate ();
1425 reorder_important_classes ();
1426 setup_reg_class_relations ();
1431 /* Set up the array above. */
1433 setup_hard_regno_aclass (void)
1437 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1440 ira_hard_regno_allocno_class
[i
]
1441 = (TEST_HARD_REG_BIT (no_unit_alloc_regs
, i
)
1443 : ira_allocno_class_translate
[REGNO_REG_CLASS (i
)]);
1447 ira_hard_regno_allocno_class
[i
] = NO_REGS
;
1448 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1450 cl
= ira_allocno_classes
[j
];
1451 if (ira_class_hard_reg_index
[cl
][i
] >= 0)
1453 ira_hard_regno_allocno_class
[i
] = cl
;
1463 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1465 setup_reg_class_nregs (void)
1469 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
1471 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1472 ira_reg_class_max_nregs
[cl
][m
]
1473 = ira_reg_class_min_nregs
[cl
][m
]
1474 = targetm
.class_max_nregs ((reg_class_t
) cl
, (machine_mode
) m
);
1475 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1477 (cl2
= alloc_reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
;
1479 if (ira_reg_class_min_nregs
[cl2
][m
]
1480 < ira_reg_class_min_nregs
[cl
][m
])
1481 ira_reg_class_min_nregs
[cl
][m
] = ira_reg_class_min_nregs
[cl2
][m
];
1487 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON.
1488 This function is called once IRA_CLASS_HARD_REGS has been initialized. */
1490 setup_prohibited_class_mode_regs (void)
1492 int j
, k
, hard_regno
, cl
, last_hard_regno
, count
;
1494 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1496 temp_hard_regset
= reg_class_contents
[cl
];
1497 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1498 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1501 last_hard_regno
= -1;
1502 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs
[cl
][j
]);
1503 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1505 hard_regno
= ira_class_hard_regs
[cl
][k
];
1506 if (!targetm
.hard_regno_mode_ok (hard_regno
, (machine_mode
) j
))
1507 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1509 else if (in_hard_reg_set_p (temp_hard_regset
,
1510 (machine_mode
) j
, hard_regno
))
1512 last_hard_regno
= hard_regno
;
1516 ira_class_singleton
[cl
][j
] = (count
== 1 ? last_hard_regno
: -1);
1521 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1522 spanning from one register pressure class to another one. It is
1523 called after defining the pressure classes. */
1525 clarify_prohibited_class_mode_regs (void)
1527 int j
, k
, hard_regno
, cl
, pclass
, nregs
;
1529 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1530 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1532 CLEAR_HARD_REG_SET (ira_useful_class_mode_regs
[cl
][j
]);
1533 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1535 hard_regno
= ira_class_hard_regs
[cl
][k
];
1536 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
], hard_regno
))
1538 nregs
= hard_regno_nregs (hard_regno
, (machine_mode
) j
);
1539 if (hard_regno
+ nregs
> FIRST_PSEUDO_REGISTER
)
1541 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1545 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1546 for (nregs
-- ;nregs
>= 0; nregs
--)
1547 if (((enum reg_class
) pclass
1548 != ira_pressure_class_translate
[REGNO_REG_CLASS
1549 (hard_regno
+ nregs
)]))
1551 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1555 if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1557 add_to_hard_reg_set (&ira_useful_class_mode_regs
[cl
][j
],
1558 (machine_mode
) j
, hard_regno
);
1563 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST
1564 and IRA_MAY_MOVE_OUT_COST for MODE. */
1566 ira_init_register_move_cost (machine_mode mode
)
1568 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
1569 bool all_match
= true;
1570 unsigned int i
, cl1
, cl2
;
1571 HARD_REG_SET ok_regs
;
1573 ira_assert (ira_register_move_cost
[mode
] == NULL
1574 && ira_may_move_in_cost
[mode
] == NULL
1575 && ira_may_move_out_cost
[mode
] == NULL
);
1576 CLEAR_HARD_REG_SET (ok_regs
);
1577 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1578 if (targetm
.hard_regno_mode_ok (i
, mode
))
1579 SET_HARD_REG_BIT (ok_regs
, i
);
1581 /* Note that we might be asked about the move costs of modes that
1582 cannot be stored in any hard register, for example if an inline
1583 asm tries to create a register operand with an impossible mode.
1584 We therefore can't assert have_regs_of_mode[mode] here. */
1585 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1586 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1589 if (!hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[cl1
])
1590 || !hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[cl2
]))
1592 if ((ira_reg_class_max_nregs
[cl1
][mode
]
1593 > ira_class_hard_regs_num
[cl1
])
1594 || (ira_reg_class_max_nregs
[cl2
][mode
]
1595 > ira_class_hard_regs_num
[cl2
]))
1598 cost
= (ira_memory_move_cost
[mode
][cl1
][0]
1599 + ira_memory_move_cost
[mode
][cl2
][1]) * 2;
1603 cost
= register_move_cost (mode
, (enum reg_class
) cl1
,
1604 (enum reg_class
) cl2
);
1605 ira_assert (cost
< 65535);
1607 all_match
&= (last_move_cost
[cl1
][cl2
] == cost
);
1608 last_move_cost
[cl1
][cl2
] = cost
;
1610 if (all_match
&& last_mode_for_init_move_cost
!= -1)
1612 ira_register_move_cost
[mode
]
1613 = ira_register_move_cost
[last_mode_for_init_move_cost
];
1614 ira_may_move_in_cost
[mode
]
1615 = ira_may_move_in_cost
[last_mode_for_init_move_cost
];
1616 ira_may_move_out_cost
[mode
]
1617 = ira_may_move_out_cost
[last_mode_for_init_move_cost
];
1620 last_mode_for_init_move_cost
= mode
;
1621 ira_register_move_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1622 ira_may_move_in_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1623 ira_may_move_out_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1624 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1625 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1628 enum reg_class
*p1
, *p2
;
1630 if (last_move_cost
[cl1
][cl2
] == 65535)
1632 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1633 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1634 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1638 cost
= last_move_cost
[cl1
][cl2
];
1640 for (p2
= ®_class_subclasses
[cl2
][0];
1641 *p2
!= LIM_REG_CLASSES
; p2
++)
1642 if (ira_class_hard_regs_num
[*p2
] > 0
1643 && (ira_reg_class_max_nregs
[*p2
][mode
]
1644 <= ira_class_hard_regs_num
[*p2
]))
1645 cost
= MAX (cost
, ira_register_move_cost
[mode
][cl1
][*p2
]);
1647 for (p1
= ®_class_subclasses
[cl1
][0];
1648 *p1
!= LIM_REG_CLASSES
; p1
++)
1649 if (ira_class_hard_regs_num
[*p1
] > 0
1650 && (ira_reg_class_max_nregs
[*p1
][mode
]
1651 <= ira_class_hard_regs_num
[*p1
]))
1652 cost
= MAX (cost
, ira_register_move_cost
[mode
][*p1
][cl2
]);
1654 ira_assert (cost
<= 65535);
1655 ira_register_move_cost
[mode
][cl1
][cl2
] = cost
;
1657 if (ira_class_subset_p
[cl1
][cl2
])
1658 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 0;
1660 ira_may_move_in_cost
[mode
][cl1
][cl2
] = cost
;
1662 if (ira_class_subset_p
[cl2
][cl1
])
1663 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 0;
1665 ira_may_move_out_cost
[mode
][cl1
][cl2
] = cost
;
1672 /* This is called once during compiler work. It sets up
1673 different arrays whose values don't depend on the compiled
1676 ira_init_once (void)
1678 ira_init_costs_once ();
1681 ira_use_lra_p
= targetm
.lra_p ();
1684 /* Free ira_max_register_move_cost, ira_may_move_in_cost and
1685 ira_may_move_out_cost for each mode. */
1687 target_ira_int::free_register_move_costs (void)
1691 /* Reset move_cost and friends, making sure we only free shared
1692 table entries once. */
1693 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1694 if (x_ira_register_move_cost
[mode
])
1697 i
< mode
&& (x_ira_register_move_cost
[i
]
1698 != x_ira_register_move_cost
[mode
]);
1703 free (x_ira_register_move_cost
[mode
]);
1704 free (x_ira_may_move_in_cost
[mode
]);
1705 free (x_ira_may_move_out_cost
[mode
]);
1708 memset (x_ira_register_move_cost
, 0, sizeof x_ira_register_move_cost
);
1709 memset (x_ira_may_move_in_cost
, 0, sizeof x_ira_may_move_in_cost
);
1710 memset (x_ira_may_move_out_cost
, 0, sizeof x_ira_may_move_out_cost
);
1711 last_mode_for_init_move_cost
= -1;
1714 target_ira_int::~target_ira_int ()
1717 free_register_move_costs ();
1720 /* This is called every time when register related information is
1725 this_target_ira_int
->free_register_move_costs ();
1726 setup_reg_mode_hard_regset ();
1727 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
1728 setup_class_subset_and_memory_move_costs ();
1729 setup_reg_class_nregs ();
1730 setup_prohibited_class_mode_regs ();
1731 find_reg_classes ();
1732 clarify_prohibited_class_mode_regs ();
1733 setup_hard_regno_aclass ();
1738 #define ira_prohibited_mode_move_regs_initialized_p \
1739 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1741 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1743 setup_prohibited_mode_move_regs (void)
1746 rtx test_reg1
, test_reg2
, move_pat
;
1747 rtx_insn
*move_insn
;
1749 if (ira_prohibited_mode_move_regs_initialized_p
)
1751 ira_prohibited_mode_move_regs_initialized_p
= true;
1752 test_reg1
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
1753 test_reg2
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 2);
1754 move_pat
= gen_rtx_SET (test_reg1
, test_reg2
);
1755 move_insn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, move_pat
, 0, -1, 0);
1756 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1758 SET_HARD_REG_SET (ira_prohibited_mode_move_regs
[i
]);
1759 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1761 if (!targetm
.hard_regno_mode_ok (j
, (machine_mode
) i
))
1763 set_mode_and_regno (test_reg1
, (machine_mode
) i
, j
);
1764 set_mode_and_regno (test_reg2
, (machine_mode
) i
, j
);
1765 INSN_CODE (move_insn
) = -1;
1766 recog_memoized (move_insn
);
1767 if (INSN_CODE (move_insn
) < 0)
1769 extract_insn (move_insn
);
1770 /* We don't know whether the move will be in code that is optimized
1771 for size or speed, so consider all enabled alternatives. */
1772 if (! constrain_operands (1, get_enabled_alternatives (move_insn
)))
1774 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs
[i
], j
);
1781 /* Extract INSN and return the set of alternatives that we should consider.
1782 This excludes any alternatives whose constraints are obviously impossible
1783 to meet (e.g. because the constraint requires a constant and the operand
1784 is nonconstant). It also excludes alternatives that are bound to need
1785 a spill or reload, as long as we have other alternatives that match
1788 ira_setup_alts (rtx_insn
*insn
)
1793 int commutative
= -1;
1795 extract_insn (insn
);
1796 preprocess_constraints (insn
);
1797 alternative_mask preferred
= get_preferred_alternatives (insn
);
1798 alternative_mask alts
= 0;
1799 alternative_mask exact_alts
= 0;
1800 /* Check that the hard reg set is enough for holding all
1801 alternatives. It is hard to imagine the situation when the
1802 assertion is wrong. */
1803 ira_assert (recog_data
.n_alternatives
1804 <= (int) MAX (sizeof (HARD_REG_ELT_TYPE
) * CHAR_BIT
,
1805 FIRST_PSEUDO_REGISTER
));
1806 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1807 if (recog_data
.constraints
[nop
][0] == '%')
1812 for (curr_swapped
= false;; curr_swapped
= true)
1814 for (nalt
= 0; nalt
< recog_data
.n_alternatives
; nalt
++)
1816 if (!TEST_BIT (preferred
, nalt
) || TEST_BIT (exact_alts
, nalt
))
1819 const operand_alternative
*op_alt
1820 = &recog_op_alt
[nalt
* recog_data
.n_operands
];
1821 int this_reject
= 0;
1822 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1826 this_reject
+= op_alt
[nop
].reject
;
1828 rtx op
= recog_data
.operand
[nop
];
1829 p
= op_alt
[nop
].constraint
;
1830 if (*p
== 0 || *p
== ',')
1835 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
1846 /* The commutative modifier is handled above. */
1849 case '0': case '1': case '2': case '3': case '4':
1850 case '5': case '6': case '7': case '8': case '9':
1852 rtx other
= recog_data
.operand
[c
- '0'];
1854 ? rtx_equal_p (other
, op
)
1855 : REG_P (op
) || SUBREG_P (op
))
1867 enum constraint_num cn
= lookup_constraint (p
);
1868 switch (get_constraint_type (cn
))
1871 if (reg_class_for_constraint (cn
) != NO_REGS
)
1873 if (REG_P (op
) || SUBREG_P (op
))
1880 if (CONST_INT_P (op
)
1881 && (insn_const_int_ok_for_constraint
1890 case CT_SPECIAL_MEMORY
:
1897 if (constraint_satisfied_p (op
, cn
))
1904 while (p
+= len
, c
);
1907 /* We can make the alternative match by spilling a register
1908 to memory or loading something into a register. Count a
1909 cost of one reload (the equivalent of the '?' constraint). */
1915 if (nop
>= recog_data
.n_operands
)
1917 alts
|= ALTERNATIVE_BIT (nalt
);
1918 if (this_reject
== 0)
1919 exact_alts
|= ALTERNATIVE_BIT (nalt
);
1922 if (commutative
< 0)
1924 /* Swap forth and back to avoid changing recog_data. */
1925 std::swap (recog_data
.operand
[commutative
],
1926 recog_data
.operand
[commutative
+ 1]);
1930 return exact_alts
? exact_alts
: alts
;
1933 /* Return the number of the output non-early clobber operand which
1934 should be the same in any case as operand with number OP_NUM (or
1935 negative value if there is no such operand). ALTS is the mask
1936 of alternatives that we should consider. */
1938 ira_get_dup_out_num (int op_num
, alternative_mask alts
)
1940 int curr_alt
, c
, original
, dup
;
1941 bool ignore_p
, use_commut_op_p
;
1944 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
1946 /* We should find duplications only for input operands. */
1947 if (recog_data
.operand_type
[op_num
] != OP_IN
)
1949 str
= recog_data
.constraints
[op_num
];
1950 use_commut_op_p
= false;
1953 rtx op
= recog_data
.operand
[op_num
];
1955 for (curr_alt
= 0, ignore_p
= !TEST_BIT (alts
, curr_alt
),
1966 ignore_p
= !TEST_BIT (alts
, curr_alt
);
1968 else if (! ignore_p
)
1975 enum constraint_num cn
= lookup_constraint (str
);
1976 enum reg_class cl
= reg_class_for_constraint (cn
);
1978 && !targetm
.class_likely_spilled_p (cl
))
1980 if (constraint_satisfied_p (op
, cn
))
1985 case '0': case '1': case '2': case '3': case '4':
1986 case '5': case '6': case '7': case '8': case '9':
1987 if (original
!= -1 && original
!= c
)
1992 str
+= CONSTRAINT_LEN (c
, str
);
1996 dup
= original
- '0';
1997 if (recog_data
.operand_type
[dup
] == OP_OUT
)
2000 if (use_commut_op_p
)
2002 use_commut_op_p
= true;
2003 if (recog_data
.constraints
[op_num
][0] == '%')
2004 str
= recog_data
.constraints
[op_num
+ 1];
2005 else if (op_num
> 0 && recog_data
.constraints
[op_num
- 1][0] == '%')
2006 str
= recog_data
.constraints
[op_num
- 1];
2015 /* Search forward to see if the source register of a copy insn dies
2016 before either it or the destination register is modified, but don't
2017 scan past the end of the basic block. If so, we can replace the
2018 source with the destination and let the source die in the copy
2021 This will reduce the number of registers live in that range and may
2022 enable the destination and the source coalescing, thus often saving
2023 one register in addition to a register-register copy. */
2026 decrease_live_ranges_number (void)
2030 rtx set
, src
, dest
, dest_death
, note
;
2034 if (! flag_expensive_optimizations
)
2038 fprintf (ira_dump_file
, "Starting decreasing number of live ranges...\n");
2040 FOR_EACH_BB_FN (bb
, cfun
)
2041 FOR_BB_INSNS (bb
, insn
)
2043 set
= single_set (insn
);
2046 src
= SET_SRC (set
);
2047 dest
= SET_DEST (set
);
2048 if (! REG_P (src
) || ! REG_P (dest
)
2049 || find_reg_note (insn
, REG_DEAD
, src
))
2051 sregno
= REGNO (src
);
2052 dregno
= REGNO (dest
);
2054 /* We don't want to mess with hard regs if register classes
2056 if (sregno
== dregno
2057 || (targetm
.small_register_classes_for_mode_p (GET_MODE (src
))
2058 && (sregno
< FIRST_PSEUDO_REGISTER
2059 || dregno
< FIRST_PSEUDO_REGISTER
))
2060 /* We don't see all updates to SP if they are in an
2061 auto-inc memory reference, so we must disallow this
2062 optimization on them. */
2063 || sregno
== STACK_POINTER_REGNUM
2064 || dregno
== STACK_POINTER_REGNUM
)
2067 dest_death
= NULL_RTX
;
2069 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
2073 if (BLOCK_FOR_INSN (p
) != bb
)
2076 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
2077 /* If SRC is an asm-declared register, it must not be
2078 replaced in any asm. Unfortunately, the REG_EXPR
2079 tree for the asm variable may be absent in the SRC
2080 rtx, so we can't check the actual register
2081 declaration easily (the asm operand will have it,
2082 though). To avoid complicating the test for a rare
2083 case, we just don't perform register replacement
2084 for a hard reg mentioned in an asm. */
2085 || (sregno
< FIRST_PSEUDO_REGISTER
2086 && asm_noperands (PATTERN (p
)) >= 0
2087 && reg_overlap_mentioned_p (src
, PATTERN (p
)))
2088 /* Don't change hard registers used by a call. */
2089 || (CALL_P (p
) && sregno
< FIRST_PSEUDO_REGISTER
2090 && find_reg_fusage (p
, USE
, src
))
2091 /* Don't change a USE of a register. */
2092 || (GET_CODE (PATTERN (p
)) == USE
2093 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
2096 /* See if all of SRC dies in P. This test is slightly
2097 more conservative than it needs to be. */
2098 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
))
2099 && GET_MODE (XEXP (note
, 0)) == GET_MODE (src
))
2103 /* We can do the optimization. Scan forward from INSN
2104 again, replacing regs as we go. Set FAILED if a
2105 replacement can't be done. In that case, we can't
2106 move the death note for SRC. This should be
2109 /* Set to stop at next insn. */
2110 for (q
= next_real_insn (insn
);
2111 q
!= next_real_insn (p
);
2112 q
= next_real_insn (q
))
2114 if (reg_overlap_mentioned_p (src
, PATTERN (q
)))
2116 /* If SRC is a hard register, we might miss
2117 some overlapping registers with
2118 validate_replace_rtx, so we would have to
2119 undo it. We can't if DEST is present in
2120 the insn, so fail in that combination of
2122 if (sregno
< FIRST_PSEUDO_REGISTER
2123 && reg_mentioned_p (dest
, PATTERN (q
)))
2126 /* Attempt to replace all uses. */
2127 else if (!validate_replace_rtx (src
, dest
, q
))
2130 /* If this succeeded, but some part of the
2131 register is still present, undo the
2133 else if (sregno
< FIRST_PSEUDO_REGISTER
2134 && reg_overlap_mentioned_p (src
, PATTERN (q
)))
2136 validate_replace_rtx (dest
, src
, q
);
2141 /* If DEST dies here, remove the death note and
2142 save it for later. Make sure ALL of DEST dies
2143 here; again, this is overly conservative. */
2145 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)))
2147 if (GET_MODE (XEXP (dest_death
, 0)) == GET_MODE (dest
))
2148 remove_note (q
, dest_death
);
2159 /* Move death note of SRC from P to INSN. */
2160 remove_note (p
, note
);
2161 XEXP (note
, 1) = REG_NOTES (insn
);
2162 REG_NOTES (insn
) = note
;
2165 /* DEST is also dead if INSN has a REG_UNUSED note for
2169 = find_regno_note (insn
, REG_UNUSED
, dregno
)))
2171 PUT_REG_NOTE_KIND (dest_death
, REG_DEAD
);
2172 remove_note (insn
, dest_death
);
2175 /* Put death note of DEST on P if we saw it die. */
2178 XEXP (dest_death
, 1) = REG_NOTES (p
);
2179 REG_NOTES (p
) = dest_death
;
2184 /* If SRC is a hard register which is set or killed in
2185 some other way, we can't do this optimization. */
2186 else if (sregno
< FIRST_PSEUDO_REGISTER
&& dead_or_set_p (p
, src
))
2194 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
2196 ira_bad_reload_regno_1 (int regno
, rtx x
)
2200 enum reg_class pref
;
2202 /* We only deal with pseudo regs. */
2203 if (! x
|| GET_CODE (x
) != REG
)
2206 x_regno
= REGNO (x
);
2207 if (x_regno
< FIRST_PSEUDO_REGISTER
)
2210 /* If the pseudo prefers REGNO explicitly, then do not consider
2211 REGNO a bad spill choice. */
2212 pref
= reg_preferred_class (x_regno
);
2213 if (reg_class_size
[pref
] == 1)
2214 return !TEST_HARD_REG_BIT (reg_class_contents
[pref
], regno
);
2216 /* If the pseudo conflicts with REGNO, then we consider REGNO a
2217 poor choice for a reload regno. */
2218 a
= ira_regno_allocno_map
[x_regno
];
2219 n
= ALLOCNO_NUM_OBJECTS (a
);
2220 for (i
= 0; i
< n
; i
++)
2222 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2223 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
2229 /* Return nonzero if REGNO is a particularly bad choice for reloading
2232 ira_bad_reload_regno (int regno
, rtx in
, rtx out
)
2234 return (ira_bad_reload_regno_1 (regno
, in
)
2235 || ira_bad_reload_regno_1 (regno
, out
));
2238 /* Add register clobbers from asm statements. */
2240 compute_regs_asm_clobbered (void)
2244 FOR_EACH_BB_FN (bb
, cfun
)
2247 FOR_BB_INSNS_REVERSE (bb
, insn
)
2251 if (NONDEBUG_INSN_P (insn
) && asm_noperands (PATTERN (insn
)) >= 0)
2252 FOR_EACH_INSN_DEF (def
, insn
)
2254 unsigned int dregno
= DF_REF_REGNO (def
);
2255 if (HARD_REGISTER_NUM_P (dregno
))
2256 add_to_hard_reg_set (&crtl
->asm_clobbers
,
2257 GET_MODE (DF_REF_REAL_REG (def
)),
2265 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and
2268 ira_setup_eliminable_regset (void)
2271 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2273 /* Setup is_leaf as frame_pointer_required may use it. This function
2274 is called by sched_init before ira if scheduling is enabled. */
2275 crtl
->is_leaf
= leaf_function_p ();
2277 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
2278 sp for alloca. So we can't eliminate the frame pointer in that
2279 case. At some point, we should improve this by emitting the
2280 sp-adjusting insns for this case. */
2281 frame_pointer_needed
2282 = (! flag_omit_frame_pointer
2283 || (cfun
->calls_alloca
&& EXIT_IGNORE_STACK
)
2284 /* We need the frame pointer to catch stack overflow exceptions if
2285 the stack pointer is moving (as for the alloca case just above). */
2286 || (STACK_CHECK_MOVING_SP
2289 && cfun
->can_throw_non_call_exceptions
)
2290 || crtl
->accesses_prior_frames
2291 || (SUPPORTS_STACK_ALIGNMENT
&& crtl
->stack_realign_needed
)
2292 || targetm
.frame_pointer_required ());
2294 /* The chance that FRAME_POINTER_NEEDED is changed from inspecting
2295 RTL is very small. So if we use frame pointer for RA and RTL
2296 actually prevents this, we will spill pseudos assigned to the
2297 frame pointer in LRA. */
2299 if (frame_pointer_needed
)
2300 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2302 ira_no_alloc_regs
= no_unit_alloc_regs
;
2303 CLEAR_HARD_REG_SET (eliminable_regset
);
2305 compute_regs_asm_clobbered ();
2307 /* Build the regset of all eliminable registers and show we can't
2308 use those that we already know won't be eliminated. */
2309 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2312 = (! targetm
.can_eliminate (eliminables
[i
].from
, eliminables
[i
].to
)
2313 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
2315 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, eliminables
[i
].from
))
2317 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
2320 SET_HARD_REG_BIT (ira_no_alloc_regs
, eliminables
[i
].from
);
2322 else if (cannot_elim
)
2323 error ("%s cannot be used in %<asm%> here",
2324 reg_names
[eliminables
[i
].from
]);
2326 df_set_regs_ever_live (eliminables
[i
].from
, true);
2328 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
)
2330 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
2332 SET_HARD_REG_BIT (eliminable_regset
, HARD_FRAME_POINTER_REGNUM
);
2333 if (frame_pointer_needed
)
2334 SET_HARD_REG_BIT (ira_no_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
2336 else if (frame_pointer_needed
)
2337 error ("%s cannot be used in %<asm%> here",
2338 reg_names
[HARD_FRAME_POINTER_REGNUM
]);
2340 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2346 /* Vector of substitutions of register numbers,
2347 used to map pseudo regs into hardware regs.
2348 This is set up as a result of register allocation.
2349 Element N is the hard reg assigned to pseudo reg N,
2350 or is -1 if no hard reg was assigned.
2351 If N is a hard reg number, element N is N. */
2352 short *reg_renumber
;
2354 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
2355 the allocation found by IRA. */
2357 setup_reg_renumber (void)
2359 int regno
, hard_regno
;
2361 ira_allocno_iterator ai
;
2363 caller_save_needed
= 0;
2364 FOR_EACH_ALLOCNO (a
, ai
)
2366 if (ira_use_lra_p
&& ALLOCNO_CAP_MEMBER (a
) != NULL
)
2368 /* There are no caps at this point. */
2369 ira_assert (ALLOCNO_CAP_MEMBER (a
) == NULL
);
2370 if (! ALLOCNO_ASSIGNED_P (a
))
2371 /* It can happen if A is not referenced but partially anticipated
2372 somewhere in a region. */
2373 ALLOCNO_ASSIGNED_P (a
) = true;
2374 ira_free_allocno_updated_costs (a
);
2375 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2376 regno
= ALLOCNO_REGNO (a
);
2377 reg_renumber
[regno
] = (hard_regno
< 0 ? -1 : hard_regno
);
2378 if (hard_regno
>= 0)
2381 enum reg_class pclass
;
2384 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
2385 nwords
= ALLOCNO_NUM_OBJECTS (a
);
2386 for (i
= 0; i
< nwords
; i
++)
2388 obj
= ALLOCNO_OBJECT (a
, i
);
2389 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
2390 reg_class_contents
[pclass
]);
2392 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0
2393 && ira_hard_reg_set_intersection_p (hard_regno
, ALLOCNO_MODE (a
),
2396 ira_assert (!optimize
|| flag_caller_saves
2397 || (ALLOCNO_CALLS_CROSSED_NUM (a
)
2398 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2399 || regno
>= ira_reg_equiv_len
2400 || ira_equiv_no_lvalue_p (regno
));
2401 caller_save_needed
= 1;
2407 /* Set up allocno assignment flags for further allocation
2410 setup_allocno_assignment_flags (void)
2414 ira_allocno_iterator ai
;
2416 FOR_EACH_ALLOCNO (a
, ai
)
2418 if (! ALLOCNO_ASSIGNED_P (a
))
2419 /* It can happen if A is not referenced but partially anticipated
2420 somewhere in a region. */
2421 ira_free_allocno_updated_costs (a
);
2422 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2423 /* Don't assign hard registers to allocnos which are destination
2424 of removed store at the end of loop. It has no sense to keep
2425 the same value in different hard registers. It is also
2426 impossible to assign hard registers correctly to such
2427 allocnos because the cost info and info about intersected
2428 calls are incorrect for them. */
2429 ALLOCNO_ASSIGNED_P (a
) = (hard_regno
>= 0
2430 || ALLOCNO_EMIT_DATA (a
)->mem_optimized_dest_p
2431 || (ALLOCNO_MEMORY_COST (a
)
2432 - ALLOCNO_CLASS_COST (a
)) < 0);
2435 || ira_hard_reg_in_set_p (hard_regno
, ALLOCNO_MODE (a
),
2436 reg_class_contents
[ALLOCNO_CLASS (a
)]));
2440 /* Evaluate overall allocation cost and the costs for using hard
2441 registers and memory for allocnos. */
2443 calculate_allocation_cost (void)
2445 int hard_regno
, cost
;
2447 ira_allocno_iterator ai
;
2449 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
2450 FOR_EACH_ALLOCNO (a
, ai
)
2452 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2453 ira_assert (hard_regno
< 0
2454 || (ira_hard_reg_in_set_p
2455 (hard_regno
, ALLOCNO_MODE (a
),
2456 reg_class_contents
[ALLOCNO_CLASS (a
)])));
2459 cost
= ALLOCNO_MEMORY_COST (a
);
2460 ira_mem_cost
+= cost
;
2462 else if (ALLOCNO_HARD_REG_COSTS (a
) != NULL
)
2464 cost
= (ALLOCNO_HARD_REG_COSTS (a
)
2465 [ira_class_hard_reg_index
2466 [ALLOCNO_CLASS (a
)][hard_regno
]]);
2467 ira_reg_cost
+= cost
;
2471 cost
= ALLOCNO_CLASS_COST (a
);
2472 ira_reg_cost
+= cost
;
2474 ira_overall_cost
+= cost
;
2477 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
2479 fprintf (ira_dump_file
,
2480 "+++Costs: overall %" PRId64
2486 ira_overall_cost
, ira_reg_cost
, ira_mem_cost
,
2487 ira_load_cost
, ira_store_cost
, ira_shuffle_cost
);
2488 fprintf (ira_dump_file
, "\n+++ move loops %d, new jumps %d\n",
2489 ira_move_loops_num
, ira_additional_jumps_num
);
2494 #ifdef ENABLE_IRA_CHECKING
2495 /* Check the correctness of the allocation. We do need this because
2496 of complicated code to transform more one region internal
2497 representation into one region representation. */
2499 check_allocation (void)
2502 int hard_regno
, nregs
, conflict_nregs
;
2503 ira_allocno_iterator ai
;
2505 FOR_EACH_ALLOCNO (a
, ai
)
2507 int n
= ALLOCNO_NUM_OBJECTS (a
);
2510 if (ALLOCNO_CAP_MEMBER (a
) != NULL
2511 || (hard_regno
= ALLOCNO_HARD_REGNO (a
)) < 0)
2513 nregs
= hard_regno_nregs (hard_regno
, ALLOCNO_MODE (a
));
2515 /* We allocated a single hard register. */
2518 /* We allocated multiple hard registers, and we will test
2519 conflicts in a granularity of single hard regs. */
2522 for (i
= 0; i
< n
; i
++)
2524 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2525 ira_object_t conflict_obj
;
2526 ira_object_conflict_iterator oci
;
2527 int this_regno
= hard_regno
;
2530 if (REG_WORDS_BIG_ENDIAN
)
2531 this_regno
+= n
- i
- 1;
2535 FOR_EACH_OBJECT_CONFLICT (obj
, conflict_obj
, oci
)
2537 ira_allocno_t conflict_a
= OBJECT_ALLOCNO (conflict_obj
);
2538 int conflict_hard_regno
= ALLOCNO_HARD_REGNO (conflict_a
);
2539 if (conflict_hard_regno
< 0)
2542 conflict_nregs
= hard_regno_nregs (conflict_hard_regno
,
2543 ALLOCNO_MODE (conflict_a
));
2545 if (ALLOCNO_NUM_OBJECTS (conflict_a
) > 1
2546 && conflict_nregs
== ALLOCNO_NUM_OBJECTS (conflict_a
))
2548 if (REG_WORDS_BIG_ENDIAN
)
2549 conflict_hard_regno
+= (ALLOCNO_NUM_OBJECTS (conflict_a
)
2550 - OBJECT_SUBWORD (conflict_obj
) - 1);
2552 conflict_hard_regno
+= OBJECT_SUBWORD (conflict_obj
);
2556 if ((conflict_hard_regno
<= this_regno
2557 && this_regno
< conflict_hard_regno
+ conflict_nregs
)
2558 || (this_regno
<= conflict_hard_regno
2559 && conflict_hard_regno
< this_regno
+ nregs
))
2561 fprintf (stderr
, "bad allocation for %d and %d\n",
2562 ALLOCNO_REGNO (a
), ALLOCNO_REGNO (conflict_a
));
2571 /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should
2572 be already calculated. */
2574 setup_reg_equiv_init (void)
2577 int max_regno
= max_reg_num ();
2579 for (i
= 0; i
< max_regno
; i
++)
2580 reg_equiv_init (i
) = ira_reg_equiv
[i
].init_insns
;
2583 /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS
2584 are insns which were generated for such movement. It is assumed
2585 that FROM_REGNO and TO_REGNO always have the same value at the
2586 point of any move containing such registers. This function is used
2587 to update equiv info for register shuffles on the region borders
2588 and for caller save/restore insns. */
2590 ira_update_equiv_info_by_shuffle_insn (int to_regno
, int from_regno
, rtx_insn
*insns
)
2595 if (! ira_reg_equiv
[from_regno
].defined_p
2596 && (! ira_reg_equiv
[to_regno
].defined_p
2597 || ((x
= ira_reg_equiv
[to_regno
].memory
) != NULL_RTX
2598 && ! MEM_READONLY_P (x
))))
2601 if (NEXT_INSN (insn
) != NULL_RTX
)
2603 if (! ira_reg_equiv
[to_regno
].defined_p
)
2605 ira_assert (ira_reg_equiv
[to_regno
].init_insns
== NULL_RTX
);
2608 ira_reg_equiv
[to_regno
].defined_p
= false;
2609 ira_reg_equiv
[to_regno
].memory
2610 = ira_reg_equiv
[to_regno
].constant
2611 = ira_reg_equiv
[to_regno
].invariant
2612 = ira_reg_equiv
[to_regno
].init_insns
= NULL
;
2613 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2614 fprintf (ira_dump_file
,
2615 " Invalidating equiv info for reg %d\n", to_regno
);
2618 /* It is possible that FROM_REGNO still has no equivalence because
2619 in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd
2620 insn was not processed yet. */
2621 if (ira_reg_equiv
[from_regno
].defined_p
)
2623 ira_reg_equiv
[to_regno
].defined_p
= true;
2624 if ((x
= ira_reg_equiv
[from_regno
].memory
) != NULL_RTX
)
2626 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
2627 && ira_reg_equiv
[from_regno
].constant
== NULL_RTX
);
2628 ira_assert (ira_reg_equiv
[to_regno
].memory
== NULL_RTX
2629 || rtx_equal_p (ira_reg_equiv
[to_regno
].memory
, x
));
2630 ira_reg_equiv
[to_regno
].memory
= x
;
2631 if (! MEM_READONLY_P (x
))
2632 /* We don't add the insn to insn init list because memory
2633 equivalence is just to say what memory is better to use
2634 when the pseudo is spilled. */
2637 else if ((x
= ira_reg_equiv
[from_regno
].constant
) != NULL_RTX
)
2639 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
);
2640 ira_assert (ira_reg_equiv
[to_regno
].constant
== NULL_RTX
2641 || rtx_equal_p (ira_reg_equiv
[to_regno
].constant
, x
));
2642 ira_reg_equiv
[to_regno
].constant
= x
;
2646 x
= ira_reg_equiv
[from_regno
].invariant
;
2647 ira_assert (x
!= NULL_RTX
);
2648 ira_assert (ira_reg_equiv
[to_regno
].invariant
== NULL_RTX
2649 || rtx_equal_p (ira_reg_equiv
[to_regno
].invariant
, x
));
2650 ira_reg_equiv
[to_regno
].invariant
= x
;
2652 if (find_reg_note (insn
, REG_EQUIV
, x
) == NULL_RTX
)
2654 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (x
));
2655 gcc_assert (note
!= NULL_RTX
);
2656 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2658 fprintf (ira_dump_file
,
2659 " Adding equiv note to insn %u for reg %d ",
2660 INSN_UID (insn
), to_regno
);
2661 dump_value_slim (ira_dump_file
, x
, 1);
2662 fprintf (ira_dump_file
, "\n");
2666 ira_reg_equiv
[to_regno
].init_insns
2667 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
2668 ira_reg_equiv
[to_regno
].init_insns
);
2669 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2670 fprintf (ira_dump_file
,
2671 " Adding equiv init move insn %u to reg %d\n",
2672 INSN_UID (insn
), to_regno
);
2675 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2678 fix_reg_equiv_init (void)
2680 int max_regno
= max_reg_num ();
2681 int i
, new_regno
, max
;
2683 rtx_insn_list
*x
, *next
, *prev
;
2686 if (max_regno_before_ira
< max_regno
)
2688 max
= vec_safe_length (reg_equivs
);
2690 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; i
++)
2691 for (prev
= NULL
, x
= reg_equiv_init (i
);
2697 set
= single_set (insn
);
2698 ira_assert (set
!= NULL_RTX
2699 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
2700 if (REG_P (SET_DEST (set
))
2701 && ((int) REGNO (SET_DEST (set
)) == i
2702 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
2703 new_regno
= REGNO (SET_DEST (set
));
2704 else if (REG_P (SET_SRC (set
))
2705 && ((int) REGNO (SET_SRC (set
)) == i
2706 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
2707 new_regno
= REGNO (SET_SRC (set
));
2714 /* Remove the wrong list element. */
2715 if (prev
== NULL_RTX
)
2716 reg_equiv_init (i
) = next
;
2718 XEXP (prev
, 1) = next
;
2719 XEXP (x
, 1) = reg_equiv_init (new_regno
);
2720 reg_equiv_init (new_regno
) = x
;
2726 #ifdef ENABLE_IRA_CHECKING
2727 /* Print redundant memory-memory copies. */
2729 print_redundant_copies (void)
2733 ira_copy_t cp
, next_cp
;
2734 ira_allocno_iterator ai
;
2736 FOR_EACH_ALLOCNO (a
, ai
)
2738 if (ALLOCNO_CAP_MEMBER (a
) != NULL
)
2741 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2742 if (hard_regno
>= 0)
2744 for (cp
= ALLOCNO_COPIES (a
); cp
!= NULL
; cp
= next_cp
)
2746 next_cp
= cp
->next_first_allocno_copy
;
2749 next_cp
= cp
->next_second_allocno_copy
;
2750 if (internal_flag_ira_verbose
> 4 && ira_dump_file
!= NULL
2751 && cp
->insn
!= NULL_RTX
2752 && ALLOCNO_HARD_REGNO (cp
->first
) == hard_regno
)
2753 fprintf (ira_dump_file
,
2754 " Redundant move from %d(freq %d):%d\n",
2755 INSN_UID (cp
->insn
), cp
->freq
, hard_regno
);
2761 /* Setup preferred and alternative classes for new pseudo-registers
2762 created by IRA starting with START. */
2764 setup_preferred_alternate_classes_for_new_pseudos (int start
)
2767 int max_regno
= max_reg_num ();
2769 for (i
= start
; i
< max_regno
; i
++)
2771 old_regno
= ORIGINAL_REGNO (regno_reg_rtx
[i
]);
2772 ira_assert (i
!= old_regno
);
2773 setup_reg_classes (i
, reg_preferred_class (old_regno
),
2774 reg_alternate_class (old_regno
),
2775 reg_allocno_class (old_regno
));
2776 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
2777 fprintf (ira_dump_file
,
2778 " New r%d: setting preferred %s, alternative %s\n",
2779 i
, reg_class_names
[reg_preferred_class (old_regno
)],
2780 reg_class_names
[reg_alternate_class (old_regno
)]);
2785 /* The number of entries allocated in reg_info. */
2786 static int allocated_reg_info_size
;
2788 /* Regional allocation can create new pseudo-registers. This function
2789 expands some arrays for pseudo-registers. */
2791 expand_reg_info (void)
2794 int size
= max_reg_num ();
2797 for (i
= allocated_reg_info_size
; i
< size
; i
++)
2798 setup_reg_classes (i
, GENERAL_REGS
, ALL_REGS
, GENERAL_REGS
);
2799 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size
);
2800 allocated_reg_info_size
= size
;
2803 /* Return TRUE if there is too high register pressure in the function.
2804 It is used to decide when stack slot sharing is worth to do. */
2806 too_high_register_pressure_p (void)
2809 enum reg_class pclass
;
2811 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
2813 pclass
= ira_pressure_classes
[i
];
2814 if (ira_loop_tree_root
->reg_pressure
[pclass
] > 10000)
2822 /* Indicate that hard register number FROM was eliminated and replaced with
2823 an offset from hard register number TO. The status of hard registers live
2824 at the start of a basic block is updated by replacing a use of FROM with
2828 mark_elimination (int from
, int to
)
2833 FOR_EACH_BB_FN (bb
, cfun
)
2836 if (bitmap_bit_p (r
, from
))
2838 bitmap_clear_bit (r
, from
);
2839 bitmap_set_bit (r
, to
);
2843 r
= DF_LIVE_IN (bb
);
2844 if (bitmap_bit_p (r
, from
))
2846 bitmap_clear_bit (r
, from
);
2847 bitmap_set_bit (r
, to
);
2854 /* The length of the following array. */
2855 int ira_reg_equiv_len
;
2857 /* Info about equiv. info for each register. */
2858 struct ira_reg_equiv_s
*ira_reg_equiv
;
2860 /* Expand ira_reg_equiv if necessary. */
2862 ira_expand_reg_equiv (void)
2864 int old
= ira_reg_equiv_len
;
2866 if (ira_reg_equiv_len
> max_reg_num ())
2868 ira_reg_equiv_len
= max_reg_num () * 3 / 2 + 1;
2870 = (struct ira_reg_equiv_s
*) xrealloc (ira_reg_equiv
,
2872 * sizeof (struct ira_reg_equiv_s
));
2873 gcc_assert (old
< ira_reg_equiv_len
);
2874 memset (ira_reg_equiv
+ old
, 0,
2875 sizeof (struct ira_reg_equiv_s
) * (ira_reg_equiv_len
- old
));
2879 init_reg_equiv (void)
2881 ira_reg_equiv_len
= 0;
2882 ira_reg_equiv
= NULL
;
2883 ira_expand_reg_equiv ();
2887 finish_reg_equiv (void)
2889 free (ira_reg_equiv
);
2896 /* Set when a REG_EQUIV note is found or created. Use to
2897 keep track of what memory accesses might be created later,
2902 /* The list of each instruction which initializes this register.
2904 NULL indicates we know nothing about this register's equivalence
2907 An INSN_LIST with a NULL insn indicates this pseudo is already
2908 known to not have a valid equivalence. */
2909 rtx_insn_list
*init_insns
;
2911 /* Loop depth is used to recognize equivalences which appear
2912 to be present within the same loop (or in an inner loop). */
2914 /* Nonzero if this had a preexisting REG_EQUIV note. */
2915 unsigned char is_arg_equivalence
: 1;
2916 /* Set when an attempt should be made to replace a register
2917 with the associated src_p entry. */
2918 unsigned char replace
: 1;
2919 /* Set if this register has no known equivalence. */
2920 unsigned char no_equiv
: 1;
2921 /* Set if this register is mentioned in a paradoxical subreg. */
2922 unsigned char pdx_subregs
: 1;
2925 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2926 structure for that register. */
2927 static struct equivalence
*reg_equiv
;
2929 /* Used for communication between the following two functions. */
2930 struct equiv_mem_data
2932 /* A MEM that we wish to ensure remains unchanged. */
2935 /* Set true if EQUIV_MEM is modified. */
2936 bool equiv_mem_modified
;
2939 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2940 Called via note_stores. */
2942 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
2945 struct equiv_mem_data
*info
= (struct equiv_mem_data
*) data
;
2948 && reg_overlap_mentioned_p (dest
, info
->equiv_mem
))
2950 && anti_dependence (info
->equiv_mem
, dest
)))
2951 info
->equiv_mem_modified
= true;
2954 enum valid_equiv
{ valid_none
, valid_combine
, valid_reload
};
2956 /* Verify that no store between START and the death of REG invalidates
2957 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2958 by storing into an overlapping memory location, or with a non-const
2961 Return VALID_RELOAD if MEMREF remains valid for both reload and
2962 combine_and_move insns, VALID_COMBINE if only valid for
2963 combine_and_move_insns, and VALID_NONE otherwise. */
2964 static enum valid_equiv
2965 validate_equiv_mem (rtx_insn
*start
, rtx reg
, rtx memref
)
2969 struct equiv_mem_data info
= { memref
, false };
2970 enum valid_equiv ret
= valid_reload
;
2972 /* If the memory reference has side effects or is volatile, it isn't a
2973 valid equivalence. */
2974 if (side_effects_p (memref
))
2977 for (insn
= start
; insn
; insn
= NEXT_INSN (insn
))
2982 if (find_reg_note (insn
, REG_DEAD
, reg
))
2987 /* We can combine a reg def from one insn into a reg use in
2988 another over a call if the memory is readonly or the call
2989 const/pure. However, we can't set reg_equiv notes up for
2990 reload over any call. The problem is the equivalent form
2991 may reference a pseudo which gets assigned a call
2992 clobbered hard reg. When we later replace REG with its
2993 equivalent form, the value in the call-clobbered reg has
2994 been changed and all hell breaks loose. */
2995 ret
= valid_combine
;
2996 if (!MEM_READONLY_P (memref
)
2997 && !RTL_CONST_OR_PURE_CALL_P (insn
))
3001 note_stores (insn
, validate_equiv_mem_from_store
, &info
);
3002 if (info
.equiv_mem_modified
)
3005 /* If a register mentioned in MEMREF is modified via an
3006 auto-increment, we lose the equivalence. Do the same if one
3007 dies; although we could extend the life, it doesn't seem worth
3010 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3011 if ((REG_NOTE_KIND (note
) == REG_INC
3012 || REG_NOTE_KIND (note
) == REG_DEAD
)
3013 && REG_P (XEXP (note
, 0))
3014 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
3021 /* Returns zero if X is known to be invariant. */
3023 equiv_init_varies_p (rtx x
)
3025 RTX_CODE code
= GET_CODE (x
);
3032 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
3041 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
3044 if (MEM_VOLATILE_P (x
))
3053 fmt
= GET_RTX_FORMAT (code
);
3054 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3057 if (equiv_init_varies_p (XEXP (x
, i
)))
3060 else if (fmt
[i
] == 'E')
3063 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3064 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
3071 /* Returns nonzero if X (used to initialize register REGNO) is movable.
3072 X is only movable if the registers it uses have equivalent initializations
3073 which appear to be within the same loop (or in an inner loop) and movable
3074 or if they are not candidates for local_alloc and don't vary. */
3076 equiv_init_movable_p (rtx x
, int regno
)
3080 enum rtx_code code
= GET_CODE (x
);
3085 return equiv_init_movable_p (SET_SRC (x
), regno
);
3101 return ((reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
3102 && reg_equiv
[REGNO (x
)].replace
)
3103 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
3104 && ! rtx_varies_p (x
, 0)));
3106 case UNSPEC_VOLATILE
:
3110 if (MEM_VOLATILE_P (x
))
3119 fmt
= GET_RTX_FORMAT (code
);
3120 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3124 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
3128 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3129 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
3137 static bool memref_referenced_p (rtx memref
, rtx x
, bool read_p
);
3139 /* Auxiliary function for memref_referenced_p. Process setting X for
3142 process_set_for_memref_referenced_p (rtx memref
, rtx x
)
3144 /* If we are setting a MEM, it doesn't count (its address does), but any
3145 other SET_DEST that has a MEM in it is referencing the MEM. */
3148 if (memref_referenced_p (memref
, XEXP (x
, 0), true))
3151 else if (memref_referenced_p (memref
, x
, false))
3157 /* TRUE if X references a memory location (as a read if READ_P) that
3158 would be affected by a store to MEMREF. */
3160 memref_referenced_p (rtx memref
, rtx x
, bool read_p
)
3164 enum rtx_code code
= GET_CODE (x
);
3179 return (reg_equiv
[REGNO (x
)].replacement
3180 && memref_referenced_p (memref
,
3181 reg_equiv
[REGNO (x
)].replacement
, read_p
));
3184 /* Memory X might have another effective type than MEMREF. */
3185 if (read_p
|| true_dependence (memref
, VOIDmode
, x
))
3190 if (process_set_for_memref_referenced_p (memref
, SET_DEST (x
)))
3193 return memref_referenced_p (memref
, SET_SRC (x
), true);
3197 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3206 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3209 return memref_referenced_p (memref
, XEXP (x
, 0), true);
3213 /* op0 = op0 + op1 */
3214 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3217 if (memref_referenced_p (memref
, XEXP (x
, 0), true))
3220 return memref_referenced_p (memref
, XEXP (x
, 1), true);
3226 fmt
= GET_RTX_FORMAT (code
);
3227 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3231 if (memref_referenced_p (memref
, XEXP (x
, i
), read_p
))
3235 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3236 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
), read_p
))
3244 /* TRUE if some insn in the range (START, END] references a memory location
3245 that would be affected by a store to MEMREF.
3247 Callers should not call this routine if START is after END in the
3251 memref_used_between_p (rtx memref
, rtx_insn
*start
, rtx_insn
*end
)
3255 for (insn
= NEXT_INSN (start
);
3256 insn
&& insn
!= NEXT_INSN (end
);
3257 insn
= NEXT_INSN (insn
))
3259 if (!NONDEBUG_INSN_P (insn
))
3262 if (memref_referenced_p (memref
, PATTERN (insn
), false))
3265 /* Nonconst functions may access memory. */
3266 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
3270 gcc_assert (insn
== NEXT_INSN (end
));
3274 /* Mark REG as having no known equivalence.
3275 Some instructions might have been processed before and furnished
3276 with REG_EQUIV notes for this register; these notes will have to be
3278 STORE is the piece of RTL that does the non-constant / conflicting
3279 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
3280 but needs to be there because this function is called from note_stores. */
3282 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
,
3283 void *data ATTRIBUTE_UNUSED
)
3286 rtx_insn_list
*list
;
3290 regno
= REGNO (reg
);
3291 reg_equiv
[regno
].no_equiv
= 1;
3292 list
= reg_equiv
[regno
].init_insns
;
3293 if (list
&& list
->insn () == NULL
)
3295 reg_equiv
[regno
].init_insns
= gen_rtx_INSN_LIST (VOIDmode
, NULL_RTX
, NULL
);
3296 reg_equiv
[regno
].replacement
= NULL_RTX
;
3297 /* This doesn't matter for equivalences made for argument registers, we
3298 should keep their initialization insns. */
3299 if (reg_equiv
[regno
].is_arg_equivalence
)
3301 ira_reg_equiv
[regno
].defined_p
= false;
3302 ira_reg_equiv
[regno
].init_insns
= NULL
;
3303 for (; list
; list
= list
->next ())
3305 rtx_insn
*insn
= list
->insn ();
3306 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
3310 /* Check whether the SUBREG is a paradoxical subreg and set the result
3314 set_paradoxical_subreg (rtx_insn
*insn
)
3316 subrtx_iterator::array_type array
;
3317 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
3319 const_rtx subreg
= *iter
;
3320 if (GET_CODE (subreg
) == SUBREG
)
3322 const_rtx reg
= SUBREG_REG (subreg
);
3323 if (REG_P (reg
) && paradoxical_subreg_p (subreg
))
3324 reg_equiv
[REGNO (reg
)].pdx_subregs
= true;
3329 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
3330 equivalent replacement. */
3333 adjust_cleared_regs (rtx loc
, const_rtx old_rtx ATTRIBUTE_UNUSED
, void *data
)
3337 bitmap cleared_regs
= (bitmap
) data
;
3338 if (bitmap_bit_p (cleared_regs
, REGNO (loc
)))
3339 return simplify_replace_fn_rtx (copy_rtx (*reg_equiv
[REGNO (loc
)].src_p
),
3340 NULL_RTX
, adjust_cleared_regs
, data
);
3345 /* Given register REGNO is set only once, return true if the defining
3346 insn dominates all uses. */
3349 def_dominates_uses (int regno
)
3351 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3353 struct df_insn_info
*def_info
= DF_REF_INSN_INFO (def
);
3354 /* If this is an artificial def (eh handler regs, hard frame pointer
3355 for non-local goto, regs defined on function entry) then def_info
3356 is NULL and the reg is always live before any use. We might
3357 reasonably return true in that case, but since the only call
3358 of this function is currently here in ira.c when we are looking
3359 at a defining insn we can't have an artificial def as that would
3360 bump DF_REG_DEF_COUNT. */
3361 gcc_assert (DF_REG_DEF_COUNT (regno
) == 1 && def_info
!= NULL
);
3363 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3364 basic_block def_bb
= BLOCK_FOR_INSN (def_insn
);
3366 for (df_ref use
= DF_REG_USE_CHAIN (regno
);
3368 use
= DF_REF_NEXT_REG (use
))
3370 struct df_insn_info
*use_info
= DF_REF_INSN_INFO (use
);
3371 /* Only check real uses, not artificial ones. */
3374 rtx_insn
*use_insn
= DF_REF_INSN (use
);
3375 if (!DEBUG_INSN_P (use_insn
))
3377 basic_block use_bb
= BLOCK_FOR_INSN (use_insn
);
3378 if (use_bb
!= def_bb
3379 ? !dominated_by_p (CDI_DOMINATORS
, use_bb
, def_bb
)
3380 : DF_INSN_INFO_LUID (use_info
) < DF_INSN_INFO_LUID (def_info
))
3388 /* Find registers that are equivalent to a single value throughout the
3389 compilation (either because they can be referenced in memory or are
3390 set once from a single constant). Lower their priority for a
3393 If such a register is only referenced once, try substituting its
3394 value into the using insn. If it succeeds, we can eliminate the
3395 register completely.
3397 Initialize init_insns in ira_reg_equiv array. */
3399 update_equiv_regs (void)
3404 /* Scan insns and set pdx_subregs if the reg is used in a
3405 paradoxical subreg. Don't set such reg equivalent to a mem,
3406 because lra will not substitute such equiv memory in order to
3407 prevent access beyond allocated memory for paradoxical memory subreg. */
3408 FOR_EACH_BB_FN (bb
, cfun
)
3409 FOR_BB_INSNS (bb
, insn
)
3410 if (NONDEBUG_INSN_P (insn
))
3411 set_paradoxical_subreg (insn
);
3413 /* Scan the insns and find which registers have equivalences. Do this
3414 in a separate scan of the insns because (due to -fcse-follow-jumps)
3415 a register can be set below its use. */
3416 bitmap setjmp_crosses
= regstat_get_setjmp_crosses ();
3417 FOR_EACH_BB_FN (bb
, cfun
)
3419 int loop_depth
= bb_loop_depth (bb
);
3421 for (insn
= BB_HEAD (bb
);
3422 insn
!= NEXT_INSN (BB_END (bb
));
3423 insn
= NEXT_INSN (insn
))
3430 if (! INSN_P (insn
))
3433 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3434 if (REG_NOTE_KIND (note
) == REG_INC
)
3435 no_equiv (XEXP (note
, 0), note
, NULL
);
3437 set
= single_set (insn
);
3439 /* If this insn contains more (or less) than a single SET,
3440 only mark all destinations as having no known equivalence. */
3442 || side_effects_p (SET_SRC (set
)))
3444 note_pattern_stores (PATTERN (insn
), no_equiv
, NULL
);
3447 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3451 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
3453 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
3455 note_pattern_stores (part
, no_equiv
, NULL
);
3459 dest
= SET_DEST (set
);
3460 src
= SET_SRC (set
);
3462 /* See if this is setting up the equivalence between an argument
3463 register and its stack slot. */
3464 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3467 gcc_assert (REG_P (dest
));
3468 regno
= REGNO (dest
);
3470 /* Note that we don't want to clear init_insns in
3471 ira_reg_equiv even if there are multiple sets of this
3473 reg_equiv
[regno
].is_arg_equivalence
= 1;
3475 /* The insn result can have equivalence memory although
3476 the equivalence is not set up by the insn. We add
3477 this insn to init insns as it is a flag for now that
3478 regno has an equivalence. We will remove the insn
3479 from init insn list later. */
3480 if (rtx_equal_p (src
, XEXP (note
, 0)) || MEM_P (XEXP (note
, 0)))
3481 ira_reg_equiv
[regno
].init_insns
3482 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3483 ira_reg_equiv
[regno
].init_insns
);
3485 /* Continue normally in case this is a candidate for
3492 /* We only handle the case of a pseudo register being set
3493 once, or always to the same value. */
3494 /* ??? The mn10200 port breaks if we add equivalences for
3495 values that need an ADDRESS_REGS register and set them equivalent
3496 to a MEM of a pseudo. The actual problem is in the over-conservative
3497 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
3498 calculate_needs, but we traditionally work around this problem
3499 here by rejecting equivalences when the destination is in a register
3500 that's likely spilled. This is fragile, of course, since the
3501 preferred class of a pseudo depends on all instructions that set
3505 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
3506 || (reg_equiv
[regno
].init_insns
3507 && reg_equiv
[regno
].init_insns
->insn () == NULL
)
3508 || (targetm
.class_likely_spilled_p (reg_preferred_class (regno
))
3509 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
3511 /* This might be setting a SUBREG of a pseudo, a pseudo that is
3512 also set somewhere else to a constant. */
3513 note_pattern_stores (set
, no_equiv
, NULL
);
3517 /* Don't set reg mentioned in a paradoxical subreg
3518 equivalent to a mem. */
3519 if (MEM_P (src
) && reg_equiv
[regno
].pdx_subregs
)
3521 note_pattern_stores (set
, no_equiv
, NULL
);
3525 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
3527 /* cse sometimes generates function invariants, but doesn't put a
3528 REG_EQUAL note on the insn. Since this note would be redundant,
3529 there's no point creating it earlier than here. */
3530 if (! note
&& ! rtx_varies_p (src
, 0))
3531 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
3533 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
3534 since it represents a function call. */
3535 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
3538 if (DF_REG_DEF_COUNT (regno
) != 1)
3540 bool equal_p
= true;
3541 rtx_insn_list
*list
;
3543 /* If we have already processed this pseudo and determined it
3544 cannot have an equivalence, then honor that decision. */
3545 if (reg_equiv
[regno
].no_equiv
)
3549 || rtx_varies_p (XEXP (note
, 0), 0)
3550 || (reg_equiv
[regno
].replacement
3551 && ! rtx_equal_p (XEXP (note
, 0),
3552 reg_equiv
[regno
].replacement
)))
3554 no_equiv (dest
, set
, NULL
);
3558 list
= reg_equiv
[regno
].init_insns
;
3559 for (; list
; list
= list
->next ())
3564 insn_tmp
= list
->insn ();
3565 note_tmp
= find_reg_note (insn_tmp
, REG_EQUAL
, NULL_RTX
);
3566 gcc_assert (note_tmp
);
3567 if (! rtx_equal_p (XEXP (note
, 0), XEXP (note_tmp
, 0)))
3576 no_equiv (dest
, set
, NULL
);
3581 /* Record this insn as initializing this register. */
3582 reg_equiv
[regno
].init_insns
3583 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
3585 /* If this register is known to be equal to a constant, record that
3586 it is always equivalent to the constant.
3587 Note that it is possible to have a register use before
3588 the def in loops (see gcc.c-torture/execute/pr79286.c)
3589 where the reg is undefined on first use. If the def insn
3590 won't trap we can use it as an equivalence, effectively
3591 choosing the "undefined" value for the reg to be the
3592 same as the value set by the def. */
3593 if (DF_REG_DEF_COUNT (regno
) == 1
3595 && !rtx_varies_p (XEXP (note
, 0), 0)
3596 && (!may_trap_or_fault_p (XEXP (note
, 0))
3597 || def_dominates_uses (regno
)))
3599 rtx note_value
= XEXP (note
, 0);
3600 remove_note (insn
, note
);
3601 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
3604 /* If this insn introduces a "constant" register, decrease the priority
3605 of that register. Record this insn if the register is only used once
3606 more and the equivalence value is the same as our source.
3608 The latter condition is checked for two reasons: First, it is an
3609 indication that it may be more efficient to actually emit the insn
3610 as written (if no registers are available, reload will substitute
3611 the equivalence). Secondly, it avoids problems with any registers
3612 dying in this insn whose death notes would be missed.
3614 If we don't have a REG_EQUIV note, see if this insn is loading
3615 a register used only in one basic block from a MEM. If so, and the
3616 MEM remains unchanged for the life of the register, add a REG_EQUIV
3618 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3620 rtx replacement
= NULL_RTX
;
3622 replacement
= XEXP (note
, 0);
3623 else if (REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3624 && MEM_P (SET_SRC (set
)))
3626 enum valid_equiv validity
;
3627 validity
= validate_equiv_mem (insn
, dest
, SET_SRC (set
));
3628 if (validity
!= valid_none
)
3630 replacement
= copy_rtx (SET_SRC (set
));
3631 if (validity
== valid_reload
)
3632 note
= set_unique_reg_note (insn
, REG_EQUIV
, replacement
);
3636 /* If we haven't done so, record for reload that this is an
3637 equivalencing insn. */
3638 if (note
&& !reg_equiv
[regno
].is_arg_equivalence
)
3639 ira_reg_equiv
[regno
].init_insns
3640 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3641 ira_reg_equiv
[regno
].init_insns
);
3645 reg_equiv
[regno
].replacement
= replacement
;
3646 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
3647 reg_equiv
[regno
].loop_depth
= (short) loop_depth
;
3649 /* Don't mess with things live during setjmp. */
3650 if (optimize
&& !bitmap_bit_p (setjmp_crosses
, regno
))
3652 /* If the register is referenced exactly twice, meaning it is
3653 set once and used once, indicate that the reference may be
3654 replaced by the equivalence we computed above. Do this
3655 even if the register is only used in one block so that
3656 dependencies can be handled where the last register is
3657 used in a different block (i.e. HIGH / LO_SUM sequences)
3658 and to reduce the number of registers alive across
3661 if (REG_N_REFS (regno
) == 2
3662 && (rtx_equal_p (replacement
, src
)
3663 || ! equiv_init_varies_p (src
))
3664 && NONJUMP_INSN_P (insn
)
3665 && equiv_init_movable_p (PATTERN (insn
), regno
))
3666 reg_equiv
[regno
].replace
= 1;
3673 /* For insns that set a MEM to the contents of a REG that is only used
3674 in a single basic block, see if the register is always equivalent
3675 to that memory location and if moving the store from INSN to the
3676 insn that sets REG is safe. If so, put a REG_EQUIV note on the
3677 initializing insn. */
3679 add_store_equivs (void)
3681 auto_bitmap seen_insns
;
3683 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3687 rtx_insn
*init_insn
;
3689 bitmap_set_bit (seen_insns
, INSN_UID (insn
));
3691 if (! INSN_P (insn
))
3694 set
= single_set (insn
);
3698 dest
= SET_DEST (set
);
3699 src
= SET_SRC (set
);
3701 /* Don't add a REG_EQUIV note if the insn already has one. The existing
3702 REG_EQUIV is likely more useful than the one we are adding. */
3703 if (MEM_P (dest
) && REG_P (src
)
3704 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
3705 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3706 && DF_REG_DEF_COUNT (regno
) == 1
3707 && ! reg_equiv
[regno
].pdx_subregs
3708 && reg_equiv
[regno
].init_insns
!= NULL
3709 && (init_insn
= reg_equiv
[regno
].init_insns
->insn ()) != 0
3710 && bitmap_bit_p (seen_insns
, INSN_UID (init_insn
))
3711 && ! find_reg_note (init_insn
, REG_EQUIV
, NULL_RTX
)
3712 && validate_equiv_mem (init_insn
, src
, dest
) == valid_reload
3713 && ! memref_used_between_p (dest
, init_insn
, insn
)
3714 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
3716 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
3718 /* This insn makes the equivalence, not the one initializing
3720 ira_reg_equiv
[regno
].init_insns
3721 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
3722 df_notes_rescan (init_insn
);
3725 "Adding REG_EQUIV to insn %d for source of insn %d\n",
3726 INSN_UID (init_insn
),
3732 /* Scan all regs killed in an insn to see if any of them are registers
3733 only used that once. If so, see if we can replace the reference
3734 with the equivalent form. If we can, delete the initializing
3735 reference and this register will go away. If we can't replace the
3736 reference, and the initializing reference is within the same loop
3737 (or in an inner loop), then move the register initialization just
3738 before the use, so that they are in the same basic block. */
3740 combine_and_move_insns (void)
3742 auto_bitmap cleared_regs
;
3743 int max
= max_reg_num ();
3745 for (int regno
= FIRST_PSEUDO_REGISTER
; regno
< max
; regno
++)
3747 if (!reg_equiv
[regno
].replace
)
3750 rtx_insn
*use_insn
= 0;
3751 for (df_ref use
= DF_REG_USE_CHAIN (regno
);
3753 use
= DF_REF_NEXT_REG (use
))
3754 if (DF_REF_INSN_INFO (use
))
3756 if (DEBUG_INSN_P (DF_REF_INSN (use
)))
3758 gcc_assert (!use_insn
);
3759 use_insn
= DF_REF_INSN (use
);
3761 gcc_assert (use_insn
);
3763 /* Don't substitute into jumps. indirect_jump_optimize does
3764 this for anything we are prepared to handle. */
3765 if (JUMP_P (use_insn
))
3768 /* Also don't substitute into a conditional trap insn -- it can become
3769 an unconditional trap, and that is a flow control insn. */
3770 if (GET_CODE (PATTERN (use_insn
)) == TRAP_IF
)
3773 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3774 gcc_assert (DF_REG_DEF_COUNT (regno
) == 1 && DF_REF_INSN_INFO (def
));
3775 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3777 /* We may not move instructions that can throw, since that
3778 changes basic block boundaries and we are not prepared to
3779 adjust the CFG to match. */
3780 if (can_throw_internal (def_insn
))
3783 basic_block use_bb
= BLOCK_FOR_INSN (use_insn
);
3784 basic_block def_bb
= BLOCK_FOR_INSN (def_insn
);
3785 if (bb_loop_depth (use_bb
) > bb_loop_depth (def_bb
))
3788 if (asm_noperands (PATTERN (def_insn
)) < 0
3789 && validate_replace_rtx (regno_reg_rtx
[regno
],
3790 *reg_equiv
[regno
].src_p
, use_insn
))
3793 /* Append the REG_DEAD notes from def_insn. */
3794 for (rtx
*p
= ®_NOTES (def_insn
); (link
= *p
) != 0; )
3796 if (REG_NOTE_KIND (XEXP (link
, 0)) == REG_DEAD
)
3798 *p
= XEXP (link
, 1);
3799 XEXP (link
, 1) = REG_NOTES (use_insn
);
3800 REG_NOTES (use_insn
) = link
;
3803 p
= &XEXP (link
, 1);
3806 remove_death (regno
, use_insn
);
3807 SET_REG_N_REFS (regno
, 0);
3808 REG_FREQ (regno
) = 0;
3810 FOR_EACH_INSN_USE (use
, def_insn
)
3812 unsigned int use_regno
= DF_REF_REGNO (use
);
3813 if (!HARD_REGISTER_NUM_P (use_regno
))
3814 reg_equiv
[use_regno
].replace
= 0;
3817 delete_insn (def_insn
);
3819 reg_equiv
[regno
].init_insns
= NULL
;
3820 ira_reg_equiv
[regno
].init_insns
= NULL
;
3821 bitmap_set_bit (cleared_regs
, regno
);
3824 /* Move the initialization of the register to just before
3825 USE_INSN. Update the flow information. */
3826 else if (prev_nondebug_insn (use_insn
) != def_insn
)
3830 new_insn
= emit_insn_before (PATTERN (def_insn
), use_insn
);
3831 REG_NOTES (new_insn
) = REG_NOTES (def_insn
);
3832 REG_NOTES (def_insn
) = 0;
3833 /* Rescan it to process the notes. */
3834 df_insn_rescan (new_insn
);
3836 /* Make sure this insn is recognized before reload begins,
3837 otherwise eliminate_regs_in_insn will die. */
3838 INSN_CODE (new_insn
) = INSN_CODE (def_insn
);
3840 delete_insn (def_insn
);
3842 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
3844 REG_BASIC_BLOCK (regno
) = use_bb
->index
;
3845 REG_N_CALLS_CROSSED (regno
) = 0;
3847 if (use_insn
== BB_HEAD (use_bb
))
3848 BB_HEAD (use_bb
) = new_insn
;
3850 /* We know regno dies in use_insn, but inside a loop
3851 REG_DEAD notes might be missing when def_insn was in
3852 another basic block. However, when we move def_insn into
3853 this bb we'll definitely get a REG_DEAD note and reload
3854 will see the death. It's possible that update_equiv_regs
3855 set up an equivalence referencing regno for a reg set by
3856 use_insn, when regno was seen as non-local. Now that
3857 regno is local to this block, and dies, such an
3858 equivalence is invalid. */
3859 if (find_reg_note (use_insn
, REG_EQUIV
, regno_reg_rtx
[regno
]))
3861 rtx set
= single_set (use_insn
);
3862 if (set
&& REG_P (SET_DEST (set
)))
3863 no_equiv (SET_DEST (set
), set
, NULL
);
3866 ira_reg_equiv
[regno
].init_insns
3867 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
3868 bitmap_set_bit (cleared_regs
, regno
);
3872 if (!bitmap_empty_p (cleared_regs
))
3876 FOR_EACH_BB_FN (bb
, cfun
)
3878 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
3879 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
3882 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
3883 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
3886 /* Last pass - adjust debug insns referencing cleared regs. */
3887 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3888 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3889 if (DEBUG_BIND_INSN_P (insn
))
3891 rtx old_loc
= INSN_VAR_LOCATION_LOC (insn
);
3892 INSN_VAR_LOCATION_LOC (insn
)
3893 = simplify_replace_fn_rtx (old_loc
, NULL_RTX
,
3894 adjust_cleared_regs
,
3895 (void *) cleared_regs
);
3896 if (old_loc
!= INSN_VAR_LOCATION_LOC (insn
))
3897 df_insn_rescan (insn
);
3902 /* A pass over indirect jumps, converting simple cases to direct jumps.
3903 Combine does this optimization too, but only within a basic block. */
3905 indirect_jump_optimize (void)
3908 bool rebuild_p
= false;
3910 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3912 rtx_insn
*insn
= BB_END (bb
);
3914 || find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
3917 rtx x
= pc_set (insn
);
3918 if (!x
|| !REG_P (SET_SRC (x
)))
3921 int regno
= REGNO (SET_SRC (x
));
3922 if (DF_REG_DEF_COUNT (regno
) == 1)
3924 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3925 if (!DF_REF_IS_ARTIFICIAL (def
))
3927 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3929 rtx set
= single_set (def_insn
);
3930 if (set
&& GET_CODE (SET_SRC (set
)) == LABEL_REF
)
3931 lab
= SET_SRC (set
);
3934 rtx eqnote
= find_reg_note (def_insn
, REG_EQUAL
, NULL_RTX
);
3935 if (eqnote
&& GET_CODE (XEXP (eqnote
, 0)) == LABEL_REF
)
3936 lab
= XEXP (eqnote
, 0);
3938 if (lab
&& validate_replace_rtx (SET_SRC (x
), lab
, insn
))
3946 timevar_push (TV_JUMP
);
3947 rebuild_jump_labels (get_insns ());
3948 if (purge_all_dead_edges ())
3949 delete_unreachable_blocks ();
3950 timevar_pop (TV_JUMP
);
3954 /* Set up fields memory, constant, and invariant from init_insns in
3955 the structures of array ira_reg_equiv. */
3957 setup_reg_equiv (void)
3960 rtx_insn_list
*elem
, *prev_elem
, *next_elem
;
3964 for (i
= FIRST_PSEUDO_REGISTER
; i
< ira_reg_equiv_len
; i
++)
3965 for (prev_elem
= NULL
, elem
= ira_reg_equiv
[i
].init_insns
;
3967 prev_elem
= elem
, elem
= next_elem
)
3969 next_elem
= elem
->next ();
3970 insn
= elem
->insn ();
3971 set
= single_set (insn
);
3973 /* Init insns can set up equivalence when the reg is a destination or
3974 a source (in this case the destination is memory). */
3975 if (set
!= 0 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))))
3977 if ((x
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL
)
3980 if (REG_P (SET_DEST (set
))
3981 && REGNO (SET_DEST (set
)) == (unsigned int) i
3982 && ! rtx_equal_p (SET_SRC (set
), x
) && MEM_P (x
))
3984 /* This insn reporting the equivalence but
3985 actually not setting it. Remove it from the
3987 if (prev_elem
== NULL
)
3988 ira_reg_equiv
[i
].init_insns
= next_elem
;
3990 XEXP (prev_elem
, 1) = next_elem
;
3994 else if (REG_P (SET_DEST (set
))
3995 && REGNO (SET_DEST (set
)) == (unsigned int) i
)
3999 gcc_assert (REG_P (SET_SRC (set
))
4000 && REGNO (SET_SRC (set
)) == (unsigned int) i
);
4003 if (! function_invariant_p (x
)
4005 /* A function invariant is often CONSTANT_P but may
4006 include a register. We promise to only pass
4007 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
4008 || (CONSTANT_P (x
) && LEGITIMATE_PIC_OPERAND_P (x
)))
4010 /* It can happen that a REG_EQUIV note contains a MEM
4011 that is not a legitimate memory operand. As later
4012 stages of reload assume that all addresses found in
4013 the lra_regno_equiv_* arrays were originally
4014 legitimate, we ignore such REG_EQUIV notes. */
4015 if (memory_operand (x
, VOIDmode
))
4017 ira_reg_equiv
[i
].defined_p
= true;
4018 ira_reg_equiv
[i
].memory
= x
;
4021 else if (function_invariant_p (x
))
4025 mode
= GET_MODE (SET_DEST (set
));
4026 if (GET_CODE (x
) == PLUS
4027 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4028 /* This is PLUS of frame pointer and a constant,
4030 ira_reg_equiv
[i
].invariant
= x
;
4031 else if (targetm
.legitimate_constant_p (mode
, x
))
4032 ira_reg_equiv
[i
].constant
= x
;
4035 ira_reg_equiv
[i
].memory
= force_const_mem (mode
, x
);
4036 if (ira_reg_equiv
[i
].memory
== NULL_RTX
)
4038 ira_reg_equiv
[i
].defined_p
= false;
4039 ira_reg_equiv
[i
].init_insns
= NULL
;
4043 ira_reg_equiv
[i
].defined_p
= true;
4048 ira_reg_equiv
[i
].defined_p
= false;
4049 ira_reg_equiv
[i
].init_insns
= NULL
;
4056 /* Print chain C to FILE. */
4058 print_insn_chain (FILE *file
, class insn_chain
*c
)
4060 fprintf (file
, "insn=%d, ", INSN_UID (c
->insn
));
4061 bitmap_print (file
, &c
->live_throughout
, "live_throughout: ", ", ");
4062 bitmap_print (file
, &c
->dead_or_set
, "dead_or_set: ", "\n");
4066 /* Print all reload_insn_chains to FILE. */
4068 print_insn_chains (FILE *file
)
4070 class insn_chain
*c
;
4071 for (c
= reload_insn_chain
; c
; c
= c
->next
)
4072 print_insn_chain (file
, c
);
4075 /* Return true if pseudo REGNO should be added to set live_throughout
4076 or dead_or_set of the insn chains for reload consideration. */
4078 pseudo_for_reload_consideration_p (int regno
)
4080 /* Consider spilled pseudos too for IRA because they still have a
4081 chance to get hard-registers in the reload when IRA is used. */
4082 return (reg_renumber
[regno
] >= 0 || ira_conflicts_p
);
4085 /* Return true if we can track the individual bytes of subreg X.
4086 When returning true, set *OUTER_SIZE to the number of bytes in
4087 X itself, *INNER_SIZE to the number of bytes in the inner register
4088 and *START to the offset of the first byte. */
4090 get_subreg_tracking_sizes (rtx x
, HOST_WIDE_INT
*outer_size
,
4091 HOST_WIDE_INT
*inner_size
, HOST_WIDE_INT
*start
)
4093 rtx reg
= regno_reg_rtx
[REGNO (SUBREG_REG (x
))];
4094 return (GET_MODE_SIZE (GET_MODE (x
)).is_constant (outer_size
)
4095 && GET_MODE_SIZE (GET_MODE (reg
)).is_constant (inner_size
)
4096 && SUBREG_BYTE (x
).is_constant (start
));
4099 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] for
4100 a register with SIZE bytes, making the register live if INIT_VALUE. */
4102 init_live_subregs (bool init_value
, sbitmap
*live_subregs
,
4103 bitmap live_subregs_used
, int allocnum
, int size
)
4105 gcc_assert (size
> 0);
4107 /* Been there, done that. */
4108 if (bitmap_bit_p (live_subregs_used
, allocnum
))
4111 /* Create a new one. */
4112 if (live_subregs
[allocnum
] == NULL
)
4113 live_subregs
[allocnum
] = sbitmap_alloc (size
);
4115 /* If the entire reg was live before blasting into subregs, we need
4116 to init all of the subregs to ones else init to 0. */
4118 bitmap_ones (live_subregs
[allocnum
]);
4120 bitmap_clear (live_subregs
[allocnum
]);
4122 bitmap_set_bit (live_subregs_used
, allocnum
);
4125 /* Walk the insns of the current function and build reload_insn_chain,
4126 and record register life information. */
4128 build_insn_chain (void)
4131 class insn_chain
**p
= &reload_insn_chain
;
4133 class insn_chain
*c
= NULL
;
4134 class insn_chain
*next
= NULL
;
4135 auto_bitmap live_relevant_regs
;
4136 auto_bitmap elim_regset
;
4137 /* live_subregs is a vector used to keep accurate information about
4138 which hardregs are live in multiword pseudos. live_subregs and
4139 live_subregs_used are indexed by pseudo number. The live_subreg
4140 entry for a particular pseudo is only used if the corresponding
4141 element is non zero in live_subregs_used. The sbitmap size of
4142 live_subreg[allocno] is number of bytes that the pseudo can
4144 sbitmap
*live_subregs
= XCNEWVEC (sbitmap
, max_regno
);
4145 auto_bitmap live_subregs_used
;
4147 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4148 if (TEST_HARD_REG_BIT (eliminable_regset
, i
))
4149 bitmap_set_bit (elim_regset
, i
);
4150 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
4155 CLEAR_REG_SET (live_relevant_regs
);
4156 bitmap_clear (live_subregs_used
);
4158 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
), 0, i
, bi
)
4160 if (i
>= FIRST_PSEUDO_REGISTER
)
4162 bitmap_set_bit (live_relevant_regs
, i
);
4165 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
),
4166 FIRST_PSEUDO_REGISTER
, i
, bi
)
4168 if (pseudo_for_reload_consideration_p (i
))
4169 bitmap_set_bit (live_relevant_regs
, i
);
4172 FOR_BB_INSNS_REVERSE (bb
, insn
)
4174 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4176 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4179 c
= new_insn_chain ();
4186 c
->block
= bb
->index
;
4188 if (NONDEBUG_INSN_P (insn
))
4189 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4191 unsigned int regno
= DF_REF_REGNO (def
);
4193 /* Ignore may clobbers because these are generated
4194 from calls. However, every other kind of def is
4195 added to dead_or_set. */
4196 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
4198 if (regno
< FIRST_PSEUDO_REGISTER
)
4200 if (!fixed_regs
[regno
])
4201 bitmap_set_bit (&c
->dead_or_set
, regno
);
4203 else if (pseudo_for_reload_consideration_p (regno
))
4204 bitmap_set_bit (&c
->dead_or_set
, regno
);
4207 if ((regno
< FIRST_PSEUDO_REGISTER
4208 || reg_renumber
[regno
] >= 0
4210 && (!DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
)))
4212 rtx reg
= DF_REF_REG (def
);
4213 HOST_WIDE_INT outer_size
, inner_size
, start
;
4215 /* We can usually track the liveness of individual
4216 bytes within a subreg. The only exceptions are
4217 subregs wrapped in ZERO_EXTRACTs and subregs whose
4218 size is not known; in those cases we need to be
4219 conservative and treat the definition as a partial
4220 definition of the full register rather than a full
4221 definition of a specific part of the register. */
4222 if (GET_CODE (reg
) == SUBREG
4223 && !DF_REF_FLAGS_IS_SET (def
, DF_REF_ZERO_EXTRACT
)
4224 && get_subreg_tracking_sizes (reg
, &outer_size
,
4225 &inner_size
, &start
))
4227 HOST_WIDE_INT last
= start
+ outer_size
;
4230 (bitmap_bit_p (live_relevant_regs
, regno
),
4231 live_subregs
, live_subregs_used
, regno
,
4234 if (!DF_REF_FLAGS_IS_SET
4235 (def
, DF_REF_STRICT_LOW_PART
))
4237 /* Expand the range to cover entire words.
4238 Bytes added here are "don't care". */
4240 = start
/ UNITS_PER_WORD
* UNITS_PER_WORD
;
4241 last
= ((last
+ UNITS_PER_WORD
- 1)
4242 / UNITS_PER_WORD
* UNITS_PER_WORD
);
4245 /* Ignore the paradoxical bits. */
4246 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4247 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4249 while (start
< last
)
4251 bitmap_clear_bit (live_subregs
[regno
], start
);
4255 if (bitmap_empty_p (live_subregs
[regno
]))
4257 bitmap_clear_bit (live_subregs_used
, regno
);
4258 bitmap_clear_bit (live_relevant_regs
, regno
);
4261 /* Set live_relevant_regs here because
4262 that bit has to be true to get us to
4263 look at the live_subregs fields. */
4264 bitmap_set_bit (live_relevant_regs
, regno
);
4268 /* DF_REF_PARTIAL is generated for
4269 subregs, STRICT_LOW_PART, and
4270 ZERO_EXTRACT. We handle the subreg
4271 case above so here we have to keep from
4272 modeling the def as a killing def. */
4273 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
))
4275 bitmap_clear_bit (live_subregs_used
, regno
);
4276 bitmap_clear_bit (live_relevant_regs
, regno
);
4282 bitmap_and_compl_into (live_relevant_regs
, elim_regset
);
4283 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4285 if (NONDEBUG_INSN_P (insn
))
4286 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4288 unsigned int regno
= DF_REF_REGNO (use
);
4289 rtx reg
= DF_REF_REG (use
);
4291 /* DF_REF_READ_WRITE on a use means that this use
4292 is fabricated from a def that is a partial set
4293 to a multiword reg. Here, we only model the
4294 subreg case that is not wrapped in ZERO_EXTRACT
4295 precisely so we do not need to look at the
4297 if (DF_REF_FLAGS_IS_SET (use
, DF_REF_READ_WRITE
)
4298 && !DF_REF_FLAGS_IS_SET (use
, DF_REF_ZERO_EXTRACT
)
4299 && DF_REF_FLAGS_IS_SET (use
, DF_REF_SUBREG
))
4302 /* Add the last use of each var to dead_or_set. */
4303 if (!bitmap_bit_p (live_relevant_regs
, regno
))
4305 if (regno
< FIRST_PSEUDO_REGISTER
)
4307 if (!fixed_regs
[regno
])
4308 bitmap_set_bit (&c
->dead_or_set
, regno
);
4310 else if (pseudo_for_reload_consideration_p (regno
))
4311 bitmap_set_bit (&c
->dead_or_set
, regno
);
4314 if (regno
< FIRST_PSEUDO_REGISTER
4315 || pseudo_for_reload_consideration_p (regno
))
4317 HOST_WIDE_INT outer_size
, inner_size
, start
;
4318 if (GET_CODE (reg
) == SUBREG
4319 && !DF_REF_FLAGS_IS_SET (use
,
4321 | DF_REF_ZERO_EXTRACT
)
4322 && get_subreg_tracking_sizes (reg
, &outer_size
,
4323 &inner_size
, &start
))
4325 HOST_WIDE_INT last
= start
+ outer_size
;
4328 (bitmap_bit_p (live_relevant_regs
, regno
),
4329 live_subregs
, live_subregs_used
, regno
,
4332 /* Ignore the paradoxical bits. */
4333 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4334 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4336 while (start
< last
)
4338 bitmap_set_bit (live_subregs
[regno
], start
);
4343 /* Resetting the live_subregs_used is
4344 effectively saying do not use the subregs
4345 because we are reading the whole
4347 bitmap_clear_bit (live_subregs_used
, regno
);
4348 bitmap_set_bit (live_relevant_regs
, regno
);
4354 /* FIXME!! The following code is a disaster. Reload needs to see the
4355 labels and jump tables that are just hanging out in between
4356 the basic blocks. See pr33676. */
4357 insn
= BB_HEAD (bb
);
4359 /* Skip over the barriers and cruft. */
4360 while (insn
&& (BARRIER_P (insn
) || NOTE_P (insn
)
4361 || BLOCK_FOR_INSN (insn
) == bb
))
4362 insn
= PREV_INSN (insn
);
4364 /* While we add anything except barriers and notes, the focus is
4365 to get the labels and jump tables into the
4366 reload_insn_chain. */
4369 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4371 if (BLOCK_FOR_INSN (insn
))
4374 c
= new_insn_chain ();
4380 /* The block makes no sense here, but it is what the old
4382 c
->block
= bb
->index
;
4384 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4386 insn
= PREV_INSN (insn
);
4390 reload_insn_chain
= c
;
4393 for (i
= 0; i
< (unsigned int) max_regno
; i
++)
4394 if (live_subregs
[i
] != NULL
)
4395 sbitmap_free (live_subregs
[i
]);
4396 free (live_subregs
);
4399 print_insn_chains (dump_file
);
4402 /* Examine the rtx found in *LOC, which is read or written to as determined
4403 by TYPE. Return false if we find a reason why an insn containing this
4404 rtx should not be moved (such as accesses to non-constant memory), true
4407 rtx_moveable_p (rtx
*loc
, enum op_type type
)
4413 enum rtx_code code
= GET_CODE (x
);
4423 return type
== OP_IN
;
4429 if (x
== frame_pointer_rtx
)
4431 if (HARD_REGISTER_P (x
))
4437 if (type
== OP_IN
&& MEM_READONLY_P (x
))
4438 return rtx_moveable_p (&XEXP (x
, 0), OP_IN
);
4442 return (rtx_moveable_p (&SET_SRC (x
), OP_IN
)
4443 && rtx_moveable_p (&SET_DEST (x
), OP_OUT
));
4445 case STRICT_LOW_PART
:
4446 return rtx_moveable_p (&XEXP (x
, 0), OP_OUT
);
4450 return (rtx_moveable_p (&XEXP (x
, 0), type
)
4451 && rtx_moveable_p (&XEXP (x
, 1), OP_IN
)
4452 && rtx_moveable_p (&XEXP (x
, 2), OP_IN
));
4456 return rtx_moveable_p (&SET_DEST (x
), OP_OUT
);
4458 case UNSPEC_VOLATILE
:
4459 /* It is a bad idea to consider insns with such rtl
4460 as moveable ones. The insn scheduler also considers them as barrier
4465 /* The same is true for volatile asm: it has unknown side effects, it
4466 cannot be moved at will. */
4467 if (MEM_VOLATILE_P (x
))
4474 fmt
= GET_RTX_FORMAT (code
);
4475 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4479 if (!rtx_moveable_p (&XEXP (x
, i
), type
))
4482 else if (fmt
[i
] == 'E')
4483 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4485 if (!rtx_moveable_p (&XVECEXP (x
, i
, j
), type
))
4492 /* A wrapper around dominated_by_p, which uses the information in UID_LUID
4493 to give dominance relationships between two insns I1 and I2. */
4495 insn_dominated_by_p (rtx i1
, rtx i2
, int *uid_luid
)
4497 basic_block bb1
= BLOCK_FOR_INSN (i1
);
4498 basic_block bb2
= BLOCK_FOR_INSN (i2
);
4501 return uid_luid
[INSN_UID (i2
)] < uid_luid
[INSN_UID (i1
)];
4502 return dominated_by_p (CDI_DOMINATORS
, bb1
, bb2
);
4505 /* Record the range of register numbers added by find_moveable_pseudos. */
4506 int first_moveable_pseudo
, last_moveable_pseudo
;
4508 /* These two vectors hold data for every register added by
4509 find_movable_pseudos, with index 0 holding data for the
4510 first_moveable_pseudo. */
4511 /* The original home register. */
4512 static vec
<rtx
> pseudo_replaced_reg
;
4514 /* Look for instances where we have an instruction that is known to increase
4515 register pressure, and whose result is not used immediately. If it is
4516 possible to move the instruction downwards to just before its first use,
4517 split its lifetime into two ranges. We create a new pseudo to compute the
4518 value, and emit a move instruction just before the first use. If, after
4519 register allocation, the new pseudo remains unallocated, the function
4520 move_unallocated_pseudos then deletes the move instruction and places
4521 the computation just before the first use.
4523 Such a move is safe and profitable if all the input registers remain live
4524 and unchanged between the original computation and its first use. In such
4525 a situation, the computation is known to increase register pressure, and
4526 moving it is known to at least not worsen it.
4528 We restrict moves to only those cases where a register remains unallocated,
4529 in order to avoid interfering too much with the instruction schedule. As
4530 an exception, we may move insns which only modify their input register
4531 (typically induction variables), as this increases the freedom for our
4532 intended transformation, and does not limit the second instruction
4536 find_moveable_pseudos (void)
4539 int max_regs
= max_reg_num ();
4540 int max_uid
= get_max_uid ();
4542 int *uid_luid
= XNEWVEC (int, max_uid
);
4543 rtx_insn
**closest_uses
= XNEWVEC (rtx_insn
*, max_regs
);
4544 /* A set of registers which are live but not modified throughout a block. */
4545 bitmap_head
*bb_transp_live
= XNEWVEC (bitmap_head
,
4546 last_basic_block_for_fn (cfun
));
4547 /* A set of registers which only exist in a given basic block. */
4548 bitmap_head
*bb_local
= XNEWVEC (bitmap_head
,
4549 last_basic_block_for_fn (cfun
));
4550 /* A set of registers which are set once, in an instruction that can be
4551 moved freely downwards, but are otherwise transparent to a block. */
4552 bitmap_head
*bb_moveable_reg_sets
= XNEWVEC (bitmap_head
,
4553 last_basic_block_for_fn (cfun
));
4554 auto_bitmap live
, used
, set
, interesting
, unusable_as_input
;
4557 first_moveable_pseudo
= max_regs
;
4558 pseudo_replaced_reg
.release ();
4559 pseudo_replaced_reg
.safe_grow_cleared (max_regs
);
4562 calculate_dominance_info (CDI_DOMINATORS
);
4565 FOR_EACH_BB_FN (bb
, cfun
)
4568 bitmap transp
= bb_transp_live
+ bb
->index
;
4569 bitmap moveable
= bb_moveable_reg_sets
+ bb
->index
;
4570 bitmap local
= bb_local
+ bb
->index
;
4572 bitmap_initialize (local
, 0);
4573 bitmap_initialize (transp
, 0);
4574 bitmap_initialize (moveable
, 0);
4575 bitmap_copy (live
, df_get_live_out (bb
));
4576 bitmap_and_into (live
, df_get_live_in (bb
));
4577 bitmap_copy (transp
, live
);
4578 bitmap_clear (moveable
);
4579 bitmap_clear (live
);
4580 bitmap_clear (used
);
4582 FOR_BB_INSNS (bb
, insn
)
4583 if (NONDEBUG_INSN_P (insn
))
4585 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4588 uid_luid
[INSN_UID (insn
)] = i
++;
4590 def
= df_single_def (insn_info
);
4591 use
= df_single_use (insn_info
);
4594 && DF_REF_REGNO (use
) == DF_REF_REGNO (def
)
4595 && !bitmap_bit_p (set
, DF_REF_REGNO (use
))
4596 && rtx_moveable_p (&PATTERN (insn
), OP_IN
))
4598 unsigned regno
= DF_REF_REGNO (use
);
4599 bitmap_set_bit (moveable
, regno
);
4600 bitmap_set_bit (set
, regno
);
4601 bitmap_set_bit (used
, regno
);
4602 bitmap_clear_bit (transp
, regno
);
4605 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4607 unsigned regno
= DF_REF_REGNO (use
);
4608 bitmap_set_bit (used
, regno
);
4609 if (bitmap_clear_bit (moveable
, regno
))
4610 bitmap_clear_bit (transp
, regno
);
4613 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4615 unsigned regno
= DF_REF_REGNO (def
);
4616 bitmap_set_bit (set
, regno
);
4617 bitmap_clear_bit (transp
, regno
);
4618 bitmap_clear_bit (moveable
, regno
);
4623 FOR_EACH_BB_FN (bb
, cfun
)
4625 bitmap local
= bb_local
+ bb
->index
;
4628 FOR_BB_INSNS (bb
, insn
)
4629 if (NONDEBUG_INSN_P (insn
))
4631 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4633 rtx closest_use
, note
;
4636 bool all_dominated
, all_local
;
4639 def
= df_single_def (insn_info
);
4640 /* There must be exactly one def in this insn. */
4641 if (!def
|| !single_set (insn
))
4643 /* This must be the only definition of the reg. We also limit
4644 which modes we deal with so that we can assume we can generate
4645 move instructions. */
4646 regno
= DF_REF_REGNO (def
);
4647 mode
= GET_MODE (DF_REF_REG (def
));
4648 if (DF_REG_DEF_COUNT (regno
) != 1
4649 || !DF_REF_INSN_INFO (def
)
4650 || HARD_REGISTER_NUM_P (regno
)
4651 || DF_REG_EQ_USE_COUNT (regno
) > 0
4652 || (!INTEGRAL_MODE_P (mode
) && !FLOAT_MODE_P (mode
)))
4654 def_insn
= DF_REF_INSN (def
);
4656 for (note
= REG_NOTES (def_insn
); note
; note
= XEXP (note
, 1))
4657 if (REG_NOTE_KIND (note
) == REG_EQUIV
&& MEM_P (XEXP (note
, 0)))
4663 fprintf (dump_file
, "Ignoring reg %d, has equiv memory\n",
4665 bitmap_set_bit (unusable_as_input
, regno
);
4669 use
= DF_REG_USE_CHAIN (regno
);
4670 all_dominated
= true;
4672 closest_use
= NULL_RTX
;
4673 for (; use
; use
= DF_REF_NEXT_REG (use
))
4676 if (!DF_REF_INSN_INFO (use
))
4678 all_dominated
= false;
4682 insn
= DF_REF_INSN (use
);
4683 if (DEBUG_INSN_P (insn
))
4685 if (BLOCK_FOR_INSN (insn
) != BLOCK_FOR_INSN (def_insn
))
4687 if (!insn_dominated_by_p (insn
, def_insn
, uid_luid
))
4688 all_dominated
= false;
4689 if (closest_use
!= insn
&& closest_use
!= const0_rtx
)
4691 if (closest_use
== NULL_RTX
)
4693 else if (insn_dominated_by_p (closest_use
, insn
, uid_luid
))
4695 else if (!insn_dominated_by_p (insn
, closest_use
, uid_luid
))
4696 closest_use
= const0_rtx
;
4702 fprintf (dump_file
, "Reg %d not all uses dominated by set\n",
4707 bitmap_set_bit (local
, regno
);
4708 if (closest_use
== const0_rtx
|| closest_use
== NULL
4709 || next_nonnote_nondebug_insn (def_insn
) == closest_use
)
4712 fprintf (dump_file
, "Reg %d uninteresting%s\n", regno
,
4713 closest_use
== const0_rtx
|| closest_use
== NULL
4714 ? " (no unique first use)" : "");
4717 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (closest_use
)))
4720 fprintf (dump_file
, "Reg %d: closest user uses cc0\n",
4725 bitmap_set_bit (interesting
, regno
);
4726 /* If we get here, we know closest_use is a non-NULL insn
4727 (as opposed to const_0_rtx). */
4728 closest_uses
[regno
] = as_a
<rtx_insn
*> (closest_use
);
4730 if (dump_file
&& (all_local
|| all_dominated
))
4732 fprintf (dump_file
, "Reg %u:", regno
);
4734 fprintf (dump_file
, " local to bb %d", bb
->index
);
4736 fprintf (dump_file
, " def dominates all uses");
4737 if (closest_use
!= const0_rtx
)
4738 fprintf (dump_file
, " has unique first use");
4739 fputs ("\n", dump_file
);
4744 EXECUTE_IF_SET_IN_BITMAP (interesting
, 0, i
, bi
)
4746 df_ref def
= DF_REG_DEF_CHAIN (i
);
4747 rtx_insn
*def_insn
= DF_REF_INSN (def
);
4748 basic_block def_block
= BLOCK_FOR_INSN (def_insn
);
4749 bitmap def_bb_local
= bb_local
+ def_block
->index
;
4750 bitmap def_bb_moveable
= bb_moveable_reg_sets
+ def_block
->index
;
4751 bitmap def_bb_transp
= bb_transp_live
+ def_block
->index
;
4752 bool local_to_bb_p
= bitmap_bit_p (def_bb_local
, i
);
4753 rtx_insn
*use_insn
= closest_uses
[i
];
4756 bool all_transp
= true;
4758 if (!REG_P (DF_REF_REG (def
)))
4764 fprintf (dump_file
, "Reg %u not local to one basic block\n",
4768 if (reg_equiv_init (i
) != NULL_RTX
)
4771 fprintf (dump_file
, "Ignoring reg %u with equiv init insn\n",
4775 if (!rtx_moveable_p (&PATTERN (def_insn
), OP_IN
))
4778 fprintf (dump_file
, "Found def insn %d for %d to be not moveable\n",
4779 INSN_UID (def_insn
), i
);
4783 fprintf (dump_file
, "Examining insn %d, def for %d\n",
4784 INSN_UID (def_insn
), i
);
4785 FOR_EACH_INSN_USE (use
, def_insn
)
4787 unsigned regno
= DF_REF_REGNO (use
);
4788 if (bitmap_bit_p (unusable_as_input
, regno
))
4792 fprintf (dump_file
, " found unusable input reg %u.\n", regno
);
4795 if (!bitmap_bit_p (def_bb_transp
, regno
))
4797 if (bitmap_bit_p (def_bb_moveable
, regno
)
4798 && !control_flow_insn_p (use_insn
)
4799 && (!HAVE_cc0
|| !sets_cc0_p (use_insn
)))
4801 if (modified_between_p (DF_REF_REG (use
), def_insn
, use_insn
))
4803 rtx_insn
*x
= NEXT_INSN (def_insn
);
4804 while (!modified_in_p (DF_REF_REG (use
), x
))
4806 gcc_assert (x
!= use_insn
);
4810 fprintf (dump_file
, " input reg %u modified but insn %d moveable\n",
4811 regno
, INSN_UID (x
));
4812 emit_insn_after (PATTERN (x
), use_insn
);
4813 set_insn_deleted (x
);
4818 fprintf (dump_file
, " input reg %u modified between def and use\n",
4829 if (!dbg_cnt (ira_move
))
4832 fprintf (dump_file
, " all ok%s\n", all_transp
? " and transp" : "");
4836 rtx def_reg
= DF_REF_REG (def
);
4837 rtx newreg
= ira_create_new_reg (def_reg
);
4838 if (validate_change (def_insn
, DF_REF_REAL_LOC (def
), newreg
, 0))
4840 unsigned nregno
= REGNO (newreg
);
4841 emit_insn_before (gen_move_insn (def_reg
, newreg
), use_insn
);
4843 pseudo_replaced_reg
[nregno
] = def_reg
;
4848 FOR_EACH_BB_FN (bb
, cfun
)
4850 bitmap_clear (bb_local
+ bb
->index
);
4851 bitmap_clear (bb_transp_live
+ bb
->index
);
4852 bitmap_clear (bb_moveable_reg_sets
+ bb
->index
);
4855 free (closest_uses
);
4857 free (bb_transp_live
);
4858 free (bb_moveable_reg_sets
);
4860 last_moveable_pseudo
= max_reg_num ();
4862 fix_reg_equiv_init ();
4864 regstat_free_n_sets_and_refs ();
4866 regstat_init_n_sets_and_refs ();
4867 regstat_compute_ri ();
4868 free_dominance_info (CDI_DOMINATORS
);
4871 /* If SET pattern SET is an assignment from a hard register to a pseudo which
4872 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return
4873 the destination. Otherwise return NULL. */
4876 interesting_dest_for_shprep_1 (rtx set
, basic_block call_dom
)
4878 rtx src
= SET_SRC (set
);
4879 rtx dest
= SET_DEST (set
);
4880 if (!REG_P (src
) || !HARD_REGISTER_P (src
)
4881 || !REG_P (dest
) || HARD_REGISTER_P (dest
)
4882 || (call_dom
&& !bitmap_bit_p (df_get_live_in (call_dom
), REGNO (dest
))))
4887 /* If insn is interesting for parameter range-splitting shrink-wrapping
4888 preparation, i.e. it is a single set from a hard register to a pseudo, which
4889 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a
4890 parallel statement with only one such statement, return the destination.
4891 Otherwise return NULL. */
4894 interesting_dest_for_shprep (rtx_insn
*insn
, basic_block call_dom
)
4898 rtx pat
= PATTERN (insn
);
4899 if (GET_CODE (pat
) == SET
)
4900 return interesting_dest_for_shprep_1 (pat
, call_dom
);
4902 if (GET_CODE (pat
) != PARALLEL
)
4905 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
4907 rtx sub
= XVECEXP (pat
, 0, i
);
4908 if (GET_CODE (sub
) == USE
4909 || GET_CODE (sub
) == CLOBBER
4910 || GET_CODE (sub
) == CLOBBER_HIGH
)
4912 if (GET_CODE (sub
) != SET
4913 || side_effects_p (sub
))
4915 rtx dest
= interesting_dest_for_shprep_1 (sub
, call_dom
);
4924 /* Split live ranges of pseudos that are loaded from hard registers in the
4925 first BB in a BB that dominates all non-sibling call if such a BB can be
4926 found and is not in a loop. Return true if the function has made any
4930 split_live_ranges_for_shrink_wrap (void)
4932 basic_block bb
, call_dom
= NULL
;
4933 basic_block first
= single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
4934 rtx_insn
*insn
, *last_interesting_insn
= NULL
;
4935 auto_bitmap need_new
, reachable
;
4936 vec
<basic_block
> queue
;
4938 if (!SHRINK_WRAPPING_ENABLED
)
4941 queue
.create (n_basic_blocks_for_fn (cfun
));
4943 FOR_EACH_BB_FN (bb
, cfun
)
4944 FOR_BB_INSNS (bb
, insn
)
4945 if (CALL_P (insn
) && !SIBLING_CALL_P (insn
))
4953 bitmap_set_bit (need_new
, bb
->index
);
4954 bitmap_set_bit (reachable
, bb
->index
);
4955 queue
.quick_push (bb
);
4959 if (queue
.is_empty ())
4965 while (!queue
.is_empty ())
4971 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
4972 if (e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
)
4973 && bitmap_set_bit (reachable
, e
->dest
->index
))
4974 queue
.quick_push (e
->dest
);
4978 FOR_BB_INSNS (first
, insn
)
4980 rtx dest
= interesting_dest_for_shprep (insn
, NULL
);
4984 if (DF_REG_DEF_COUNT (REGNO (dest
)) > 1)
4987 for (df_ref use
= DF_REG_USE_CHAIN (REGNO(dest
));
4989 use
= DF_REF_NEXT_REG (use
))
4991 int ubbi
= DF_REF_BB (use
)->index
;
4992 if (bitmap_bit_p (reachable
, ubbi
))
4993 bitmap_set_bit (need_new
, ubbi
);
4995 last_interesting_insn
= insn
;
4998 if (!last_interesting_insn
)
5001 call_dom
= nearest_common_dominator_for_set (CDI_DOMINATORS
, need_new
);
5002 if (call_dom
== first
)
5005 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
5006 while (bb_loop_depth (call_dom
) > 0)
5007 call_dom
= get_immediate_dominator (CDI_DOMINATORS
, call_dom
);
5008 loop_optimizer_finalize ();
5010 if (call_dom
== first
)
5013 calculate_dominance_info (CDI_POST_DOMINATORS
);
5014 if (dominated_by_p (CDI_POST_DOMINATORS
, first
, call_dom
))
5016 free_dominance_info (CDI_POST_DOMINATORS
);
5019 free_dominance_info (CDI_POST_DOMINATORS
);
5022 fprintf (dump_file
, "Will split live ranges of parameters at BB %i\n",
5026 FOR_BB_INSNS (first
, insn
)
5028 rtx dest
= interesting_dest_for_shprep (insn
, call_dom
);
5029 if (!dest
|| dest
== pic_offset_table_rtx
)
5032 bool need_newreg
= false;
5034 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
5036 rtx_insn
*uin
= DF_REF_INSN (use
);
5037 next
= DF_REF_NEXT_REG (use
);
5039 if (DEBUG_INSN_P (uin
))
5042 basic_block ubb
= BLOCK_FOR_INSN (uin
);
5044 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
5053 rtx newreg
= ira_create_new_reg (dest
);
5055 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
5057 rtx_insn
*uin
= DF_REF_INSN (use
);
5058 next
= DF_REF_NEXT_REG (use
);
5060 basic_block ubb
= BLOCK_FOR_INSN (uin
);
5062 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
5063 validate_change (uin
, DF_REF_REAL_LOC (use
), newreg
, true);
5066 rtx_insn
*new_move
= gen_move_insn (newreg
, dest
);
5067 emit_insn_after (new_move
, bb_note (call_dom
));
5070 fprintf (dump_file
, "Split live-range of register ");
5071 print_rtl_single (dump_file
, dest
);
5076 if (insn
== last_interesting_insn
)
5079 apply_change_group ();
5083 /* Perform the second half of the transformation started in
5084 find_moveable_pseudos. We look for instances where the newly introduced
5085 pseudo remains unallocated, and remove it by moving the definition to
5086 just before its use, replacing the move instruction generated by
5087 find_moveable_pseudos. */
5089 move_unallocated_pseudos (void)
5092 for (i
= first_moveable_pseudo
; i
< last_moveable_pseudo
; i
++)
5093 if (reg_renumber
[i
] < 0)
5095 int idx
= i
- first_moveable_pseudo
;
5096 rtx other_reg
= pseudo_replaced_reg
[idx
];
5097 rtx_insn
*def_insn
= DF_REF_INSN (DF_REG_DEF_CHAIN (i
));
5098 /* The use must follow all definitions of OTHER_REG, so we can
5099 insert the new definition immediately after any of them. */
5100 df_ref other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
));
5101 rtx_insn
*move_insn
= DF_REF_INSN (other_def
);
5102 rtx_insn
*newinsn
= emit_insn_after (PATTERN (def_insn
), move_insn
);
5107 fprintf (dump_file
, "moving def of %d (insn %d now) ",
5108 REGNO (other_reg
), INSN_UID (def_insn
));
5110 delete_insn (move_insn
);
5111 while ((other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
))))
5112 delete_insn (DF_REF_INSN (other_def
));
5113 delete_insn (def_insn
);
5115 set
= single_set (newinsn
);
5116 success
= validate_change (newinsn
, &SET_DEST (set
), other_reg
, 0);
5117 gcc_assert (success
);
5119 fprintf (dump_file
, " %d) rather than keep unallocated replacement %d\n",
5120 INSN_UID (newinsn
), i
);
5121 SET_REG_N_REFS (i
, 0);
5125 /* If the backend knows where to allocate pseudos for hard
5126 register initial values, register these allocations now. */
5128 allocate_initial_values (void)
5130 if (targetm
.allocate_initial_value
)
5135 for (i
= 0; HARD_REGISTER_NUM_P (i
); i
++)
5137 if (! initial_value_entry (i
, &hreg
, &preg
))
5140 x
= targetm
.allocate_initial_value (hreg
);
5141 regno
= REGNO (preg
);
5142 if (x
&& REG_N_SETS (regno
) <= 1)
5145 reg_equiv_memory_loc (regno
) = x
;
5151 gcc_assert (REG_P (x
));
5152 new_regno
= REGNO (x
);
5153 reg_renumber
[regno
] = new_regno
;
5154 /* Poke the regno right into regno_reg_rtx so that even
5155 fixed regs are accepted. */
5156 SET_REGNO (preg
, new_regno
);
5157 /* Update global register liveness information. */
5158 FOR_EACH_BB_FN (bb
, cfun
)
5160 if (REGNO_REG_SET_P (df_get_live_in (bb
), regno
))
5161 SET_REGNO_REG_SET (df_get_live_in (bb
), new_regno
);
5162 if (REGNO_REG_SET_P (df_get_live_out (bb
), regno
))
5163 SET_REGNO_REG_SET (df_get_live_out (bb
), new_regno
);
5169 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER
,
5175 /* True when we use LRA instead of reload pass for the current
5179 /* True if we have allocno conflicts. It is false for non-optimized
5180 mode or when the conflict table is too big. */
5181 bool ira_conflicts_p
;
5183 /* Saved between IRA and reload. */
5184 static int saved_flag_ira_share_spill_slots
;
5186 /* This is the main entry of IRA. */
5191 int ira_max_point_before_emit
;
5192 bool saved_flag_caller_saves
= flag_caller_saves
;
5193 enum ira_region saved_flag_ira_region
= flag_ira_region
;
5195 int num_used_regs
= 0;
5199 /* Determine if the current function is a leaf before running IRA
5200 since this can impact optimizations done by the prologue and
5201 epilogue thus changing register elimination offsets.
5202 Other target callbacks may use crtl->is_leaf too, including
5203 SHRINK_WRAPPING_ENABLED, so initialize as early as possible. */
5204 crtl
->is_leaf
= leaf_function_p ();
5206 /* Perform target specific PIC register initialization. */
5207 targetm
.init_pic_reg ();
5209 ira_conflicts_p
= optimize
> 0;
5211 /* Determine the number of pseudos actually requiring coloring. */
5212 for (i
= FIRST_PSEUDO_REGISTER
; i
< DF_REG_SIZE (df
); i
++)
5213 num_used_regs
+= !!(DF_REG_USE_COUNT (i
) + DF_REG_DEF_COUNT (i
));
5215 /* If there are too many pseudos and/or basic blocks (e.g. 10K
5216 pseudos and 10K blocks or 100K pseudos and 1K blocks), we will
5217 use simplified and faster algorithms in LRA. */
5220 && num_used_regs
>= (1 << 26) / last_basic_block_for_fn (cfun
));
5224 /* It permits to skip live range splitting in LRA. */
5225 flag_caller_saves
= false;
5226 /* There is no sense to do regional allocation when we use
5228 flag_ira_region
= IRA_REGION_ONE
;
5229 ira_conflicts_p
= false;
5232 #ifndef IRA_NO_OBSTACK
5233 gcc_obstack_init (&ira_obstack
);
5235 bitmap_obstack_initialize (&ira_bitmap_obstack
);
5237 /* LRA uses its own infrastructure to handle caller save registers. */
5238 if (flag_caller_saves
&& !ira_use_lra_p
)
5239 init_caller_save ();
5241 if (flag_ira_verbose
< 10)
5243 internal_flag_ira_verbose
= flag_ira_verbose
;
5248 internal_flag_ira_verbose
= flag_ira_verbose
- 10;
5249 ira_dump_file
= stderr
;
5252 setup_prohibited_mode_move_regs ();
5253 decrease_live_ranges_number ();
5254 df_note_add_problem ();
5256 /* DF_LIVE can't be used in the register allocator, too many other
5257 parts of the compiler depend on using the "classic" liveness
5258 interpretation of the DF_LR problem. See PR38711.
5259 Remove the problem, so that we don't spend time updating it in
5260 any of the df_analyze() calls during IRA/LRA. */
5262 df_remove_problem (df_live
);
5263 gcc_checking_assert (df_live
== NULL
);
5266 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
5271 if (ira_conflicts_p
)
5273 calculate_dominance_info (CDI_DOMINATORS
);
5275 if (split_live_ranges_for_shrink_wrap ())
5278 free_dominance_info (CDI_DOMINATORS
);
5281 df_clear_flags (DF_NO_INSN_RESCAN
);
5283 indirect_jump_optimize ();
5284 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
5287 regstat_init_n_sets_and_refs ();
5288 regstat_compute_ri ();
5290 /* If we are not optimizing, then this is the only place before
5291 register allocation where dataflow is done. And that is needed
5292 to generate these warnings. */
5294 generate_setjmp_warnings ();
5296 if (resize_reg_info () && flag_ira_loop_pressure
)
5297 ira_set_pseudo_classes (true, ira_dump_file
);
5299 init_alias_analysis ();
5300 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
5301 reg_equiv
= XCNEWVEC (struct equivalence
, max_reg_num ());
5302 update_equiv_regs ();
5304 /* Don't move insns if live range shrinkage or register
5305 pressure-sensitive scheduling were done because it will not
5306 improve allocation but likely worsen insn scheduling. */
5308 && !flag_live_range_shrinkage
5309 && !(flag_sched_pressure
&& flag_schedule_insns
))
5310 combine_and_move_insns ();
5312 /* Gather additional equivalences with memory. */
5314 add_store_equivs ();
5316 loop_optimizer_finalize ();
5317 free_dominance_info (CDI_DOMINATORS
);
5318 end_alias_analysis ();
5323 setup_reg_equiv_init ();
5325 allocated_reg_info_size
= max_reg_num ();
5327 /* It is not worth to do such improvement when we use a simple
5328 allocation because of -O0 usage or because the function is too
5330 if (ira_conflicts_p
)
5331 find_moveable_pseudos ();
5333 max_regno_before_ira
= max_reg_num ();
5334 ira_setup_eliminable_regset ();
5336 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
5337 ira_load_cost
= ira_store_cost
= ira_shuffle_cost
= 0;
5338 ira_move_loops_num
= ira_additional_jumps_num
= 0;
5340 ira_assert (current_loops
== NULL
);
5341 if (flag_ira_region
== IRA_REGION_ALL
|| flag_ira_region
== IRA_REGION_MIXED
)
5342 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
| LOOPS_HAVE_RECORDED_EXITS
);
5344 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5345 fprintf (ira_dump_file
, "Building IRA IR\n");
5346 loops_p
= ira_build ();
5348 ira_assert (ira_conflicts_p
|| !loops_p
);
5350 saved_flag_ira_share_spill_slots
= flag_ira_share_spill_slots
;
5351 if (too_high_register_pressure_p () || cfun
->calls_setjmp
)
5352 /* It is just wasting compiler's time to pack spilled pseudos into
5353 stack slots in this case -- prohibit it. We also do this if
5354 there is setjmp call because a variable not modified between
5355 setjmp and longjmp the compiler is required to preserve its
5356 value and sharing slots does not guarantee it. */
5357 flag_ira_share_spill_slots
= FALSE
;
5361 ira_max_point_before_emit
= ira_max_point
;
5363 ira_initiate_emit_data ();
5367 max_regno
= max_reg_num ();
5368 if (ira_conflicts_p
)
5372 if (! ira_use_lra_p
)
5373 ira_initiate_assign ();
5382 ira_allocno_iterator ai
;
5384 FOR_EACH_ALLOCNO (a
, ai
)
5386 int old_regno
= ALLOCNO_REGNO (a
);
5387 int new_regno
= REGNO (ALLOCNO_EMIT_DATA (a
)->reg
);
5389 ALLOCNO_REGNO (a
) = new_regno
;
5391 if (old_regno
!= new_regno
)
5392 setup_reg_classes (new_regno
, reg_preferred_class (old_regno
),
5393 reg_alternate_class (old_regno
),
5394 reg_allocno_class (old_regno
));
5399 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5400 fprintf (ira_dump_file
, "Flattening IR\n");
5401 ira_flattening (max_regno_before_ira
, ira_max_point_before_emit
);
5403 /* New insns were generated: add notes and recalculate live
5407 /* ??? Rebuild the loop tree, but why? Does the loop tree
5408 change if new insns were generated? Can that be handled
5409 by updating the loop tree incrementally? */
5410 loop_optimizer_finalize ();
5411 free_dominance_info (CDI_DOMINATORS
);
5412 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
5413 | LOOPS_HAVE_RECORDED_EXITS
);
5415 if (! ira_use_lra_p
)
5417 setup_allocno_assignment_flags ();
5418 ira_initiate_assign ();
5419 ira_reassign_conflict_allocnos (max_regno
);
5424 ira_finish_emit_data ();
5426 setup_reg_renumber ();
5428 calculate_allocation_cost ();
5430 #ifdef ENABLE_IRA_CHECKING
5431 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5432 /* Opposite to reload pass, LRA does not use any conflict info
5433 from IRA. We don't rebuild conflict info for LRA (through
5434 ira_flattening call) and cannot use the check here. We could
5435 rebuild this info for LRA in the check mode but there is a risk
5436 that code generated with the check and without it will be a bit
5437 different. Calling ira_flattening in any mode would be a
5438 wasting CPU time. So do not check the allocation for LRA. */
5439 check_allocation ();
5442 if (max_regno
!= max_regno_before_ira
)
5444 regstat_free_n_sets_and_refs ();
5446 regstat_init_n_sets_and_refs ();
5447 regstat_compute_ri ();
5450 overall_cost_before
= ira_overall_cost
;
5451 if (! ira_conflicts_p
)
5455 fix_reg_equiv_init ();
5457 #ifdef ENABLE_IRA_CHECKING
5458 print_redundant_copies ();
5460 if (! ira_use_lra_p
)
5462 ira_spilled_reg_stack_slots_num
= 0;
5463 ira_spilled_reg_stack_slots
5464 = ((class ira_spilled_reg_stack_slot
*)
5465 ira_allocate (max_regno
5466 * sizeof (class ira_spilled_reg_stack_slot
)));
5467 memset ((void *)ira_spilled_reg_stack_slots
, 0,
5468 max_regno
* sizeof (class ira_spilled_reg_stack_slot
));
5471 allocate_initial_values ();
5473 /* See comment for find_moveable_pseudos call. */
5474 if (ira_conflicts_p
)
5475 move_unallocated_pseudos ();
5477 /* Restore original values. */
5480 flag_caller_saves
= saved_flag_caller_saves
;
5481 flag_ira_region
= saved_flag_ira_region
;
5490 unsigned pic_offset_table_regno
= INVALID_REGNUM
;
5492 if (flag_ira_verbose
< 10)
5493 ira_dump_file
= dump_file
;
5495 /* If pic_offset_table_rtx is a pseudo register, then keep it so
5496 after reload to avoid possible wrong usages of hard reg assigned
5498 if (pic_offset_table_rtx
5499 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
5500 pic_offset_table_regno
= REGNO (pic_offset_table_rtx
);
5502 timevar_push (TV_RELOAD
);
5505 if (current_loops
!= NULL
)
5507 loop_optimizer_finalize ();
5508 free_dominance_info (CDI_DOMINATORS
);
5510 FOR_ALL_BB_FN (bb
, cfun
)
5511 bb
->loop_father
= NULL
;
5512 current_loops
= NULL
;
5516 lra (ira_dump_file
);
5517 /* ???!!! Move it before lra () when we use ira_reg_equiv in
5519 vec_free (reg_equivs
);
5525 df_set_flags (DF_NO_INSN_RESCAN
);
5526 build_insn_chain ();
5528 need_dce
= reload (get_insns (), ira_conflicts_p
);
5531 timevar_pop (TV_RELOAD
);
5533 timevar_push (TV_IRA
);
5535 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5537 ira_free (ira_spilled_reg_stack_slots
);
5538 ira_finish_assign ();
5541 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
5542 && overall_cost_before
!= ira_overall_cost
)
5543 fprintf (ira_dump_file
, "+++Overall after reload %" PRId64
"\n",
5546 flag_ira_share_spill_slots
= saved_flag_ira_share_spill_slots
;
5548 if (! ira_use_lra_p
)
5551 if (current_loops
!= NULL
)
5553 loop_optimizer_finalize ();
5554 free_dominance_info (CDI_DOMINATORS
);
5556 FOR_ALL_BB_FN (bb
, cfun
)
5557 bb
->loop_father
= NULL
;
5558 current_loops
= NULL
;
5561 regstat_free_n_sets_and_refs ();
5565 cleanup_cfg (CLEANUP_EXPENSIVE
);
5567 finish_reg_equiv ();
5569 bitmap_obstack_release (&ira_bitmap_obstack
);
5570 #ifndef IRA_NO_OBSTACK
5571 obstack_free (&ira_obstack
, NULL
);
5574 /* The code after the reload has changed so much that at this point
5575 we might as well just rescan everything. Note that
5576 df_rescan_all_insns is not going to help here because it does not
5577 touch the artificial uses and defs. */
5578 df_finish_pass (true);
5579 df_scan_alloc (NULL
);
5584 df_live_add_problem ();
5585 df_live_set_all_dirty ();
5591 if (need_dce
&& optimize
)
5594 /* Diagnose uses of the hard frame pointer when it is used as a global
5595 register. Often we can get away with letting the user appropriate
5596 the frame pointer, but we should let them know when code generation
5597 makes that impossible. */
5598 if (global_regs
[HARD_FRAME_POINTER_REGNUM
] && frame_pointer_needed
)
5600 tree decl
= global_regs_decl
[HARD_FRAME_POINTER_REGNUM
];
5601 error_at (DECL_SOURCE_LOCATION (current_function_decl
),
5602 "frame pointer required, but reserved");
5603 inform (DECL_SOURCE_LOCATION (decl
), "for %qD", decl
);
5606 /* If we are doing generic stack checking, give a warning if this
5607 function's frame size is larger than we expect. */
5608 if (flag_stack_check
== GENERIC_STACK_CHECK
)
5610 poly_int64 size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
5612 for (int i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5613 if (df_regs_ever_live_p (i
) && !fixed_regs
[i
] && call_used_regs
[i
])
5614 size
+= UNITS_PER_WORD
;
5616 if (constant_lower_bound (size
) > STACK_CHECK_MAX_FRAME_SIZE
)
5617 warning (0, "frame size too large for reliable stack checking");
5620 if (pic_offset_table_regno
!= INVALID_REGNUM
)
5621 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, pic_offset_table_regno
);
5623 timevar_pop (TV_IRA
);
5626 /* Run the integrated register allocator. */
5630 const pass_data pass_data_ira
=
5632 RTL_PASS
, /* type */
5634 OPTGROUP_NONE
, /* optinfo_flags */
5636 0, /* properties_required */
5637 0, /* properties_provided */
5638 0, /* properties_destroyed */
5639 0, /* todo_flags_start */
5640 TODO_do_not_ggc_collect
, /* todo_flags_finish */
5643 class pass_ira
: public rtl_opt_pass
5646 pass_ira (gcc::context
*ctxt
)
5647 : rtl_opt_pass (pass_data_ira
, ctxt
)
5650 /* opt_pass methods: */
5651 virtual bool gate (function
*)
5653 return !targetm
.no_register_allocation
;
5655 virtual unsigned int execute (function
*)
5661 }; // class pass_ira
5666 make_pass_ira (gcc::context
*ctxt
)
5668 return new pass_ira (ctxt
);
5673 const pass_data pass_data_reload
=
5675 RTL_PASS
, /* type */
5676 "reload", /* name */
5677 OPTGROUP_NONE
, /* optinfo_flags */
5678 TV_RELOAD
, /* tv_id */
5679 0, /* properties_required */
5680 0, /* properties_provided */
5681 0, /* properties_destroyed */
5682 0, /* todo_flags_start */
5683 0, /* todo_flags_finish */
5686 class pass_reload
: public rtl_opt_pass
5689 pass_reload (gcc::context
*ctxt
)
5690 : rtl_opt_pass (pass_data_reload
, ctxt
)
5693 /* opt_pass methods: */
5694 virtual bool gate (function
*)
5696 return !targetm
.no_register_allocation
;
5698 virtual unsigned int execute (function
*)
5704 }; // class pass_reload
5709 make_pass_reload (gcc::context
*ctxt
)
5711 return new pass_reload (ctxt
);