1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 88, 91-97, 1998 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This file contains two passes of the compiler: reg_scan and reg_class.
23 It also defines some tables of information about the hardware registers
24 and a function init_reg_sets to initialize the tables. */
29 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "insn-config.h"
38 #ifndef REGISTER_MOVE_COST
39 #define REGISTER_MOVE_COST(x, y) 2
42 /* If we have auto-increment or auto-decrement and we can have secondary
43 reloads, we are not allowed to use classes requiring secondary
44 reloads for pseudos auto-incremented since reload can't handle it. */
47 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
48 #define FORBIDDEN_INC_DEC_CLASSES
52 /* Register tables used by many passes. */
54 /* Indexed by hard register number, contains 1 for registers
55 that are fixed use (stack pointer, pc, frame pointer, etc.).
56 These are the registers that cannot be used to allocate
57 a pseudo reg whose life does not cross calls. */
59 char fixed_regs
[FIRST_PSEUDO_REGISTER
];
61 /* Same info as a HARD_REG_SET. */
63 HARD_REG_SET fixed_reg_set
;
65 /* Data for initializing the above. */
67 static char initial_fixed_regs
[] = FIXED_REGISTERS
;
69 /* Indexed by hard register number, contains 1 for registers
70 that are fixed use or are clobbered by function calls.
71 These are the registers that cannot be used to allocate
72 a pseudo reg whose life crosses calls. */
74 char call_used_regs
[FIRST_PSEUDO_REGISTER
];
76 /* Same info as a HARD_REG_SET. */
78 HARD_REG_SET call_used_reg_set
;
80 /* HARD_REG_SET of registers we want to avoid caller saving. */
81 HARD_REG_SET losing_caller_save_reg_set
;
83 /* Data for initializing the above. */
85 static char initial_call_used_regs
[] = CALL_USED_REGISTERS
;
87 /* Indexed by hard register number, contains 1 for registers that are
88 fixed use -- i.e. in fixed_regs -- or a function value return register
89 or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the
90 registers that cannot hold quantities across calls even if we are
91 willing to save and restore them. */
93 char call_fixed_regs
[FIRST_PSEUDO_REGISTER
];
95 /* The same info as a HARD_REG_SET. */
97 HARD_REG_SET call_fixed_reg_set
;
99 /* Number of non-fixed registers. */
101 int n_non_fixed_regs
;
103 /* Indexed by hard register number, contains 1 for registers
104 that are being used for global register decls.
105 These must be exempt from ordinary flow analysis
106 and are also considered fixed. */
108 char global_regs
[FIRST_PSEUDO_REGISTER
];
110 /* Table of register numbers in the order in which to try to use them. */
111 #ifdef REG_ALLOC_ORDER
112 int reg_alloc_order
[FIRST_PSEUDO_REGISTER
] = REG_ALLOC_ORDER
;
115 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
117 HARD_REG_SET reg_class_contents
[N_REG_CLASSES
];
119 /* The same information, but as an array of unsigned ints. We copy from
120 these unsigned ints to the table above. We do this so the tm.h files
121 do not have to be aware of the wordsize for machines with <= 64 regs. */
124 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
126 static unsigned int_reg_class_contents
[N_REG_CLASSES
][N_REG_INTS
]
127 = REG_CLASS_CONTENTS
;
129 /* For each reg class, number of regs it contains. */
131 int reg_class_size
[N_REG_CLASSES
];
133 /* For each reg class, table listing all the containing classes. */
135 enum reg_class reg_class_superclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
137 /* For each reg class, table listing all the classes contained in it. */
139 enum reg_class reg_class_subclasses
[N_REG_CLASSES
][N_REG_CLASSES
];
141 /* For each pair of reg classes,
142 a largest reg class contained in their union. */
144 enum reg_class reg_class_subunion
[N_REG_CLASSES
][N_REG_CLASSES
];
146 /* For each pair of reg classes,
147 the smallest reg class containing their union. */
149 enum reg_class reg_class_superunion
[N_REG_CLASSES
][N_REG_CLASSES
];
151 /* Array containing all of the register names */
153 char *reg_names
[] = REGISTER_NAMES
;
155 /* For each hard register, the widest mode object that it can contain.
156 This will be a MODE_INT mode if the register can hold integers. Otherwise
157 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
160 enum machine_mode reg_raw_mode
[FIRST_PSEUDO_REGISTER
];
162 /* Maximum cost of moving from a register in one class to a register in
163 another class. Based on REGISTER_MOVE_COST. */
165 static int move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
167 /* Similar, but here we don't have to move if the first index is a subset
168 of the second so in that case the cost is zero. */
170 static int may_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
172 #ifdef FORBIDDEN_INC_DEC_CLASSES
174 /* These are the classes that regs which are auto-incremented or decremented
177 static int forbidden_inc_dec_class
[N_REG_CLASSES
];
179 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
182 static char *in_inc_dec
;
184 #endif /* FORBIDDEN_INC_DEC_CLASSES */
186 #ifdef HAVE_SECONDARY_RELOADS
188 /* Sample MEM values for use by memory_move_secondary_cost. */
190 static rtx top_of_stack
[MAX_MACHINE_MODE
];
192 #endif /* HAVE_SECONDARY_RELOADS */
194 /* Function called only once to initialize the above data on reg usage.
195 Once this is done, various switches may override. */
202 /* First copy the register information from the initial int form into
205 for (i
= 0; i
< N_REG_CLASSES
; i
++)
207 CLEAR_HARD_REG_SET (reg_class_contents
[i
]);
209 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
210 if (int_reg_class_contents
[i
][j
/ HOST_BITS_PER_INT
]
211 & ((unsigned) 1 << (j
% HOST_BITS_PER_INT
)))
212 SET_HARD_REG_BIT (reg_class_contents
[i
], j
);
215 bcopy (initial_fixed_regs
, fixed_regs
, sizeof fixed_regs
);
216 bcopy (initial_call_used_regs
, call_used_regs
, sizeof call_used_regs
);
217 bzero (global_regs
, sizeof global_regs
);
219 /* Compute number of hard regs in each class. */
221 bzero ((char *) reg_class_size
, sizeof reg_class_size
);
222 for (i
= 0; i
< N_REG_CLASSES
; i
++)
223 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
224 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
227 /* Initialize the table of subunions.
228 reg_class_subunion[I][J] gets the largest-numbered reg-class
229 that is contained in the union of classes I and J. */
231 for (i
= 0; i
< N_REG_CLASSES
; i
++)
233 for (j
= 0; j
< N_REG_CLASSES
; j
++)
236 register /* Declare it register if it's a scalar. */
241 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
242 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
243 for (k
= 0; k
< N_REG_CLASSES
; k
++)
245 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
], c
,
250 /* keep the largest subclass */ /* SPEE 900308 */
251 GO_IF_HARD_REG_SUBSET (reg_class_contents
[k
],
252 reg_class_contents
[(int) reg_class_subunion
[i
][j
]],
254 reg_class_subunion
[i
][j
] = (enum reg_class
) k
;
261 /* Initialize the table of superunions.
262 reg_class_superunion[I][J] gets the smallest-numbered reg-class
263 containing the union of classes I and J. */
265 for (i
= 0; i
< N_REG_CLASSES
; i
++)
267 for (j
= 0; j
< N_REG_CLASSES
; j
++)
270 register /* Declare it register if it's a scalar. */
275 COPY_HARD_REG_SET (c
, reg_class_contents
[i
]);
276 IOR_HARD_REG_SET (c
, reg_class_contents
[j
]);
277 for (k
= 0; k
< N_REG_CLASSES
; k
++)
278 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[k
], superclass
);
281 reg_class_superunion
[i
][j
] = (enum reg_class
) k
;
285 /* Initialize the tables of subclasses and superclasses of each reg class.
286 First clear the whole table, then add the elements as they are found. */
288 for (i
= 0; i
< N_REG_CLASSES
; i
++)
290 for (j
= 0; j
< N_REG_CLASSES
; j
++)
292 reg_class_superclasses
[i
][j
] = LIM_REG_CLASSES
;
293 reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
297 for (i
= 0; i
< N_REG_CLASSES
; i
++)
299 if (i
== (int) NO_REGS
)
302 for (j
= i
+ 1; j
< N_REG_CLASSES
; j
++)
306 GO_IF_HARD_REG_SUBSET (reg_class_contents
[i
], reg_class_contents
[j
],
310 /* Reg class I is a subclass of J.
311 Add J to the table of superclasses of I. */
312 p
= ®_class_superclasses
[i
][0];
313 while (*p
!= LIM_REG_CLASSES
) p
++;
314 *p
= (enum reg_class
) j
;
315 /* Add I to the table of superclasses of J. */
316 p
= ®_class_subclasses
[j
][0];
317 while (*p
!= LIM_REG_CLASSES
) p
++;
318 *p
= (enum reg_class
) i
;
322 /* Do any additional initialization regsets may need */
323 INIT_ONCE_REG_SET ();
326 /* After switches have been processed, which perhaps alter
327 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
332 register unsigned int i
, j
;
334 /* This macro allows the fixed or call-used registers
335 to depend on target flags. */
337 #ifdef CONDITIONAL_REGISTER_USAGE
338 CONDITIONAL_REGISTER_USAGE
;
341 /* Initialize "constant" tables. */
343 CLEAR_HARD_REG_SET (fixed_reg_set
);
344 CLEAR_HARD_REG_SET (call_used_reg_set
);
345 CLEAR_HARD_REG_SET (call_fixed_reg_set
);
347 bcopy (fixed_regs
, call_fixed_regs
, sizeof call_fixed_regs
);
349 n_non_fixed_regs
= 0;
351 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
354 SET_HARD_REG_BIT (fixed_reg_set
, i
);
358 if (call_used_regs
[i
])
359 SET_HARD_REG_BIT (call_used_reg_set
, i
);
360 if (call_fixed_regs
[i
])
361 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
362 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i
)))
363 SET_HARD_REG_BIT (losing_caller_save_reg_set
, i
);
366 /* Initialize the move cost table. Find every subset of each class
367 and take the maximum cost of moving any subset to any other. */
369 for (i
= 0; i
< N_REG_CLASSES
; i
++)
370 for (j
= 0; j
< N_REG_CLASSES
; j
++)
372 int cost
= i
== j
? 2 : REGISTER_MOVE_COST (i
, j
);
373 enum reg_class
*p1
, *p2
;
375 for (p2
= ®_class_subclasses
[j
][0]; *p2
!= LIM_REG_CLASSES
; p2
++)
377 cost
= MAX (cost
, REGISTER_MOVE_COST (i
, *p2
));
379 for (p1
= ®_class_subclasses
[i
][0]; *p1
!= LIM_REG_CLASSES
; p1
++)
382 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, j
));
384 for (p2
= ®_class_subclasses
[j
][0];
385 *p2
!= LIM_REG_CLASSES
; p2
++)
387 cost
= MAX (cost
, REGISTER_MOVE_COST (*p1
, *p2
));
390 move_cost
[i
][j
] = cost
;
392 if (reg_class_subset_p (i
, j
))
395 may_move_cost
[i
][j
] = cost
;
399 /* Compute the table of register modes.
400 These values are used to record death information for individual registers
401 (as opposed to a multi-register mode). */
408 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
410 reg_raw_mode
[i
] = choose_hard_reg_mode (i
, 1);
412 /* If we couldn't find a valid mode, just use the previous mode.
413 ??? One situation in which we need to do this is on the mips where
414 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
415 to use DF mode for the even registers and VOIDmode for the odd
416 (for the cpu models where the odd ones are inaccessible). */
417 if (reg_raw_mode
[i
] == VOIDmode
)
418 reg_raw_mode
[i
] = i
== 0 ? word_mode
: reg_raw_mode
[i
-1];
422 /* Finish initializing the register sets and
423 initialize the register modes. */
428 /* This finishes what was started by init_reg_sets, but couldn't be done
429 until after register usage was specified. */
434 #ifdef HAVE_SECONDARY_RELOADS
436 /* Make some fake stack-frame MEM references for use in
437 memory_move_secondary_cost. */
439 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
440 top_of_stack
[i
] = gen_rtx (MEM
, i
, stack_pointer_rtx
);
445 #ifdef HAVE_SECONDARY_RELOADS
447 /* Compute extra cost of moving registers to/from memory due to reloads.
448 Only needed if secondary reloads are required for memory moves. */
451 memory_move_secondary_cost (mode
, class, in
)
452 enum machine_mode mode
;
453 enum reg_class
class;
456 enum reg_class altclass
;
457 int partial_cost
= 0;
458 /* We need a memory reference to feed to SECONDARY... macros. */
459 rtx mem
= top_of_stack
[(int) mode
];
463 #ifdef SECONDARY_INPUT_RELOAD_CLASS
464 altclass
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, mem
);
471 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
472 altclass
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, mem
);
478 if (altclass
== NO_REGS
)
482 partial_cost
= REGISTER_MOVE_COST (altclass
, class);
484 partial_cost
= REGISTER_MOVE_COST (class, altclass
);
486 if (class == altclass
)
487 /* This isn't simply a copy-to-temporary situation. Can't guess
488 what it is, so MEMORY_MOVE_COST really ought not to be calling
491 I'm tempted to put in an abort here, but returning this will
492 probably only give poor estimates, which is what we would've
493 had before this code anyways. */
496 /* Check if the secondary reload register will also need a
498 return memory_move_secondary_cost (mode
, altclass
, in
) + partial_cost
;
502 /* Return a machine mode that is legitimate for hard reg REGNO and large
503 enough to save nregs. If we can't find one, return VOIDmode. */
506 choose_hard_reg_mode (regno
, nregs
)
510 enum machine_mode found_mode
= VOIDmode
, mode
;
512 /* We first look for the largest integer mode that can be validly
513 held in REGNO. If none, we look for the largest floating-point mode.
514 If we still didn't find a valid mode, try CCmode. */
516 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
518 mode
= GET_MODE_WIDER_MODE (mode
))
519 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
520 && HARD_REGNO_MODE_OK (regno
, mode
))
523 if (found_mode
!= VOIDmode
)
526 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_FLOAT
);
528 mode
= GET_MODE_WIDER_MODE (mode
))
529 if (HARD_REGNO_NREGS (regno
, mode
) == nregs
530 && HARD_REGNO_MODE_OK (regno
, mode
))
533 if (found_mode
!= VOIDmode
)
536 if (HARD_REGNO_NREGS (regno
, CCmode
) == nregs
537 && HARD_REGNO_MODE_OK (regno
, CCmode
))
540 /* We can't find a mode valid for this register. */
544 /* Specify the usage characteristics of the register named NAME.
545 It should be a fixed register if FIXED and a
546 call-used register if CALL_USED. */
549 fix_register (name
, fixed
, call_used
)
551 int fixed
, call_used
;
555 /* Decode the name and update the primary form of
556 the register info. */
558 if ((i
= decode_reg_name (name
)) >= 0)
560 fixed_regs
[i
] = fixed
;
561 call_used_regs
[i
] = call_used
;
565 warning ("unknown register name: %s", name
);
569 /* Mark register number I as global. */
577 warning ("register used for two global register variables");
581 if (call_used_regs
[i
] && ! fixed_regs
[i
])
582 warning ("call-clobbered register used for global register variable");
586 /* If already fixed, nothing else to do. */
590 fixed_regs
[i
] = call_used_regs
[i
] = call_fixed_regs
[i
] = 1;
593 SET_HARD_REG_BIT (fixed_reg_set
, i
);
594 SET_HARD_REG_BIT (call_used_reg_set
, i
);
595 SET_HARD_REG_BIT (call_fixed_reg_set
, i
);
598 /* Now the data and code for the `regclass' pass, which happens
599 just before local-alloc. */
601 /* The `costs' struct records the cost of using a hard register of each class
602 and of using memory for each pseudo. We use this data to set up
603 register class preferences. */
607 int cost
[N_REG_CLASSES
];
611 /* Record the cost of each class for each pseudo. */
613 static struct costs
*costs
;
615 /* Record the same data by operand number, accumulated for each alternative
616 in an insn. The contribution to a pseudo is that of the minimum-cost
619 static struct costs op_costs
[MAX_RECOG_OPERANDS
];
621 /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R.
622 This is available after `regclass' is run. */
624 static char *prefclass
;
626 /* altclass[R] is a register class that we should use for allocating
627 pseudo number R if no register in the preferred class is available.
628 If no register in this class is available, memory is preferred.
630 It might appear to be more general to have a bitmask of classes here,
631 but since it is recommended that there be a class corresponding to the
632 union of most major pair of classes, that generality is not required.
634 This is available after `regclass' is run. */
636 static char *altclass
;
638 /* Record the depth of loops that we are in. */
640 static int loop_depth
;
642 /* Account for the fact that insns within a loop are executed very commonly,
643 but don't keep doing this as loops go too deep. */
645 static int loop_cost
;
647 static void record_reg_classes
PROTO((int, int, rtx
*, enum machine_mode
*,
649 static int copy_cost
PROTO((rtx
, enum machine_mode
,
650 enum reg_class
, int));
651 static void record_address_regs
PROTO((rtx
, enum reg_class
, int));
652 #ifdef FORBIDDEN_INC_DEC_CLASSES
653 static int auto_inc_dec_reg_p
PROTO((rtx
, enum machine_mode
));
655 static void reg_scan_mark_refs
PROTO((rtx
, rtx
, int));
657 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
658 This function is sometimes called before the info has been computed.
659 When that happens, just return GENERAL_REGS, which is innocuous. */
662 reg_preferred_class (regno
)
667 return (enum reg_class
) prefclass
[regno
];
671 reg_alternate_class (regno
)
677 return (enum reg_class
) altclass
[regno
];
680 /* This prevents dump_flow_info from losing if called
681 before regclass is run. */
689 /* This is a pass of the compiler that scans all instructions
690 and calculates the preferred class for each pseudo-register.
691 This information can be accessed later by calling `reg_preferred_class'.
692 This pass comes just before local register allocation. */
699 #ifdef REGISTER_CONSTRAINTS
702 struct costs init_cost
;
708 costs
= (struct costs
*) alloca (nregs
* sizeof (struct costs
));
710 #ifdef FORBIDDEN_INC_DEC_CLASSES
712 in_inc_dec
= (char *) alloca (nregs
);
714 /* Initialize information about which register classes can be used for
715 pseudos that are auto-incremented or auto-decremented. It would
716 seem better to put this in init_reg_sets, but we need to be able
717 to allocate rtx, which we can't do that early. */
719 for (i
= 0; i
< N_REG_CLASSES
; i
++)
721 rtx r
= gen_rtx_REG (VOIDmode
, 0);
724 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
725 if (TEST_HARD_REG_BIT (reg_class_contents
[i
], j
))
729 for (m
= VOIDmode
; (int) m
< (int) MAX_MACHINE_MODE
;
730 m
= (enum machine_mode
) ((int) m
+ 1))
731 if (HARD_REGNO_MODE_OK (j
, m
))
735 /* If a register is not directly suitable for an
736 auto-increment or decrement addressing mode and
737 requires secondary reloads, disallow its class from
738 being used in such addresses. */
741 #ifdef SECONDARY_RELOAD_CLASS
742 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
745 #ifdef SECONDARY_INPUT_RELOAD_CLASS
746 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
749 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
750 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS
, m
, r
)
755 && ! auto_inc_dec_reg_p (r
, m
))
756 forbidden_inc_dec_class
[i
] = 1;
760 #endif /* FORBIDDEN_INC_DEC_CLASSES */
762 init_cost
.mem_cost
= 10000;
763 for (i
= 0; i
< N_REG_CLASSES
; i
++)
764 init_cost
.cost
[i
] = 10000;
766 /* Normally we scan the insns once and determine the best class to use for
767 each register. However, if -fexpensive_optimizations are on, we do so
768 twice, the second time using the tentative best classes to guide the
771 for (pass
= 0; pass
<= flag_expensive_optimizations
; pass
++)
773 /* Zero out our accumulation of the cost of each class for each reg. */
775 bzero ((char *) costs
, nregs
* sizeof (struct costs
));
777 #ifdef FORBIDDEN_INC_DEC_CLASSES
778 bzero (in_inc_dec
, nregs
);
781 loop_depth
= 0, loop_cost
= 1;
783 /* Scan the instructions and record each time it would
784 save code to put a certain register in a certain class. */
786 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
788 char *constraints
[MAX_RECOG_OPERANDS
];
789 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
793 /* Show that an insn inside a loop is likely to be executed three
794 times more than insns outside a loop. This is much more aggressive
795 than the assumptions made elsewhere and is being tried as an
798 if (GET_CODE (insn
) == NOTE
799 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_BEG
)
800 loop_depth
++, loop_cost
= 1 << (2 * MIN (loop_depth
, 5));
801 else if (GET_CODE (insn
) == NOTE
802 && NOTE_LINE_NUMBER (insn
) == NOTE_INSN_LOOP_END
)
803 loop_depth
--, loop_cost
= 1 << (2 * MIN (loop_depth
, 5));
805 else if ((GET_CODE (insn
) == INSN
806 && GET_CODE (PATTERN (insn
)) != USE
807 && GET_CODE (PATTERN (insn
)) != CLOBBER
808 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
809 || (GET_CODE (insn
) == JUMP_INSN
810 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
811 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
)
812 || GET_CODE (insn
) == CALL_INSN
)
814 if (GET_CODE (insn
) == INSN
815 && (noperands
= asm_noperands (PATTERN (insn
))) >= 0)
817 decode_asm_operands (PATTERN (insn
), recog_operand
, NULL_PTR
,
819 nalternatives
= (noperands
== 0 ? 0
820 : n_occurrences (',', constraints
[0]) + 1);
824 int insn_code_number
= recog_memoized (insn
);
827 set
= single_set (insn
);
830 nalternatives
= insn_n_alternatives
[insn_code_number
];
831 noperands
= insn_n_operands
[insn_code_number
];
833 /* If this insn loads a parameter from its stack slot, then
834 it represents a savings, rather than a cost, if the
835 parameter is stored in memory. Record this fact. */
837 if (set
!= 0 && GET_CODE (SET_DEST (set
)) == REG
838 && GET_CODE (SET_SRC (set
)) == MEM
839 && (note
= find_reg_note (insn
, REG_EQUIV
,
841 && GET_CODE (XEXP (note
, 0)) == MEM
)
843 costs
[REGNO (SET_DEST (set
))].mem_cost
844 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set
)),
847 record_address_regs (XEXP (SET_SRC (set
), 0),
848 BASE_REG_CLASS
, loop_cost
* 2);
852 /* Improve handling of two-address insns such as
853 (set X (ashift CONST Y)) where CONST must be made to
854 match X. Change it into two insns: (set X CONST)
855 (set X (ashift X Y)). If we left this for reloading, it
856 would probably get three insns because X and Y might go
857 in the same place. This prevents X and Y from receiving
860 We can only do this if the modes of operands 0 and 1
861 (which might not be the same) are tieable and we only need
862 do this during our first pass. */
864 if (pass
== 0 && optimize
866 && insn_operand_constraint
[insn_code_number
][1][0] == '0'
867 && insn_operand_constraint
[insn_code_number
][1][1] == 0
868 && CONSTANT_P (recog_operand
[1])
869 && ! rtx_equal_p (recog_operand
[0], recog_operand
[1])
870 && ! rtx_equal_p (recog_operand
[0], recog_operand
[2])
871 && GET_CODE (recog_operand
[0]) == REG
872 && MODES_TIEABLE_P (GET_MODE (recog_operand
[0]),
873 insn_operand_mode
[insn_code_number
][1]))
875 rtx previnsn
= prev_real_insn (insn
);
877 = gen_lowpart (insn_operand_mode
[insn_code_number
][1],
880 = emit_insn_before (gen_move_insn (dest
,
884 /* If this insn was the start of a basic block,
885 include the new insn in that block.
886 We need not check for code_label here;
887 while a basic block can start with a code_label,
888 INSN could not be at the beginning of that block. */
889 if (previnsn
== 0 || GET_CODE (previnsn
) == JUMP_INSN
)
892 for (b
= 0; b
< n_basic_blocks
; b
++)
893 if (insn
== basic_block_head
[b
])
894 basic_block_head
[b
] = newinsn
;
897 /* This makes one more setting of new insns's dest. */
898 REG_N_SETS (REGNO (recog_operand
[0]))++;
900 *recog_operand_loc
[1] = recog_operand
[0];
901 for (i
= insn_n_dups
[insn_code_number
] - 1; i
>= 0; i
--)
902 if (recog_dup_num
[i
] == 1)
903 *recog_dup_loc
[i
] = recog_operand
[0];
905 insn
= PREV_INSN (newinsn
);
909 for (i
= 0; i
< noperands
; i
++)
912 = insn_operand_constraint
[insn_code_number
][i
];
913 modes
[i
] = insn_operand_mode
[insn_code_number
][i
];
917 /* If we get here, we are set up to record the costs of all the
918 operands for this insn. Start by initializing the costs.
919 Then handle any address registers. Finally record the desired
920 classes for any pseudos, doing it twice if some pair of
921 operands are commutative. */
923 for (i
= 0; i
< noperands
; i
++)
925 op_costs
[i
] = init_cost
;
927 if (GET_CODE (recog_operand
[i
]) == SUBREG
)
928 recog_operand
[i
] = SUBREG_REG (recog_operand
[i
]);
930 if (GET_CODE (recog_operand
[i
]) == MEM
)
931 record_address_regs (XEXP (recog_operand
[i
], 0),
932 BASE_REG_CLASS
, loop_cost
* 2);
933 else if (constraints
[i
][0] == 'p')
934 record_address_regs (recog_operand
[i
],
935 BASE_REG_CLASS
, loop_cost
* 2);
938 /* Check for commutative in a separate loop so everything will
939 have been initialized. We must do this even if one operand
940 is a constant--see addsi3 in m68k.md. */
942 for (i
= 0; i
< noperands
- 1; i
++)
943 if (constraints
[i
][0] == '%')
945 char *xconstraints
[MAX_RECOG_OPERANDS
];
948 /* Handle commutative operands by swapping the constraints.
949 We assume the modes are the same. */
951 for (j
= 0; j
< noperands
; j
++)
952 xconstraints
[j
] = constraints
[j
];
954 xconstraints
[i
] = constraints
[i
+1];
955 xconstraints
[i
+1] = constraints
[i
];
956 record_reg_classes (nalternatives
, noperands
,
957 recog_operand
, modes
, xconstraints
,
961 record_reg_classes (nalternatives
, noperands
, recog_operand
,
962 modes
, constraints
, insn
);
964 /* Now add the cost for each operand to the total costs for
967 for (i
= 0; i
< noperands
; i
++)
968 if (GET_CODE (recog_operand
[i
]) == REG
969 && REGNO (recog_operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
971 int regno
= REGNO (recog_operand
[i
]);
972 struct costs
*p
= &costs
[regno
], *q
= &op_costs
[i
];
974 p
->mem_cost
+= q
->mem_cost
* loop_cost
;
975 for (j
= 0; j
< N_REG_CLASSES
; j
++)
976 p
->cost
[j
] += q
->cost
[j
] * loop_cost
;
981 /* Now for each register look at how desirable each class is
982 and find which class is preferred. Store that in
983 `prefclass[REGNO]'. Record in `altclass[REGNO]' the largest register
984 class any of whose registers is better than memory. */
988 prefclass
= (char *) oballoc (nregs
);
989 altclass
= (char *) oballoc (nregs
);
992 for (i
= FIRST_PSEUDO_REGISTER
; i
< nregs
; i
++)
994 register int best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
995 enum reg_class best
= ALL_REGS
, alt
= NO_REGS
;
996 /* This is an enum reg_class, but we call it an int
997 to save lots of casts. */
999 register struct costs
*p
= &costs
[i
];
1001 for (class = (int) ALL_REGS
- 1; class > 0; class--)
1003 /* Ignore classes that are too small for this operand or
1004 invalid for a operand that was auto-incremented. */
1005 if (CLASS_MAX_NREGS (class, PSEUDO_REGNO_MODE (i
))
1006 > reg_class_size
[class]
1007 #ifdef FORBIDDEN_INC_DEC_CLASSES
1008 || (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1012 else if (p
->cost
[class] < best_cost
)
1014 best_cost
= p
->cost
[class];
1015 best
= (enum reg_class
) class;
1017 else if (p
->cost
[class] == best_cost
)
1018 best
= reg_class_subunion
[(int)best
][class];
1021 /* Record the alternate register class; i.e., a class for which
1022 every register in it is better than using memory. If adding a
1023 class would make a smaller class (i.e., no union of just those
1024 classes exists), skip that class. The major unions of classes
1025 should be provided as a register class. Don't do this if we
1026 will be doing it again later. */
1028 if (pass
== 1 || ! flag_expensive_optimizations
)
1029 for (class = 0; class < N_REG_CLASSES
; class++)
1030 if (p
->cost
[class] < p
->mem_cost
1031 && (reg_class_size
[(int) reg_class_subunion
[(int) alt
][class]]
1032 > reg_class_size
[(int) alt
])
1033 #ifdef FORBIDDEN_INC_DEC_CLASSES
1034 && ! (in_inc_dec
[i
] && forbidden_inc_dec_class
[class])
1037 alt
= reg_class_subunion
[(int) alt
][class];
1039 /* If we don't add any classes, nothing to try. */
1043 /* We cast to (int) because (char) hits bugs in some compilers. */
1044 prefclass
[i
] = (int) best
;
1045 altclass
[i
] = (int) alt
;
1048 #endif /* REGISTER_CONSTRAINTS */
1051 #ifdef REGISTER_CONSTRAINTS
1053 /* Record the cost of using memory or registers of various classes for
1054 the operands in INSN.
1056 N_ALTS is the number of alternatives.
1058 N_OPS is the number of operands.
1060 OPS is an array of the operands.
1062 MODES are the modes of the operands, in case any are VOIDmode.
1064 CONSTRAINTS are the constraints to use for the operands. This array
1065 is modified by this procedure.
1067 This procedure works alternative by alternative. For each alternative
1068 we assume that we will be able to allocate all pseudos to their ideal
1069 register class and calculate the cost of using that alternative. Then
1070 we compute for each operand that is a pseudo-register, the cost of
1071 having the pseudo allocated to each register class and using it in that
1072 alternative. To this cost is added the cost of the alternative.
1074 The cost of each class for this insn is its lowest cost among all the
1078 record_reg_classes (n_alts
, n_ops
, ops
, modes
, constraints
, insn
)
1082 enum machine_mode
*modes
;
1087 enum op_type
{OP_READ
, OP_WRITE
, OP_READ_WRITE
} op_types
[MAX_RECOG_OPERANDS
];
1091 /* By default, each operand is an input operand. */
1093 for (i
= 0; i
< n_ops
; i
++)
1094 op_types
[i
] = OP_READ
;
1096 /* Process each alternative, each time minimizing an operand's cost with
1097 the cost for each operand in that alternative. */
1099 for (alt
= 0; alt
< n_alts
; alt
++)
1101 struct costs this_op_costs
[MAX_RECOG_OPERANDS
];
1104 enum reg_class classes
[MAX_RECOG_OPERANDS
];
1107 for (i
= 0; i
< n_ops
; i
++)
1109 char *p
= constraints
[i
];
1111 enum machine_mode mode
= modes
[i
];
1116 /* If this operand has no constraints at all, we can conclude
1117 nothing about it since anything is valid. */
1121 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1122 bzero ((char *) &this_op_costs
[i
], sizeof this_op_costs
[i
]);
1130 /* If this alternative is only relevant when this operand
1131 matches a previous operand, we do different things depending
1132 on whether this operand is a pseudo-reg or not. */
1134 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
1137 classes
[i
] = classes
[j
];
1139 if (GET_CODE (op
) != REG
|| REGNO (op
) < FIRST_PSEUDO_REGISTER
)
1141 /* If this matches the other operand, we have no added
1143 if (rtx_equal_p (ops
[j
], op
))
1146 /* If we can put the other operand into a register, add to
1147 the cost of this alternative the cost to copy this
1148 operand to the register used for the other operand. */
1150 else if (classes
[j
] != NO_REGS
)
1151 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1), win
= 1;
1153 else if (GET_CODE (ops
[j
]) != REG
1154 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
1156 /* This op is a pseudo but the one it matches is not. */
1158 /* If we can't put the other operand into a register, this
1159 alternative can't be used. */
1161 if (classes
[j
] == NO_REGS
)
1164 /* Otherwise, add to the cost of this alternative the cost
1165 to copy the other operand to the register used for this
1169 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1);
1173 /* The costs of this operand are the same as that of the
1174 other operand. However, if we cannot tie them, this
1175 alternative needs to do a copy, which is one
1178 this_op_costs
[i
] = this_op_costs
[j
];
1179 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
1180 && ! find_reg_note (insn
, REG_DEAD
, op
))
1183 /* This is in place of ordinary cost computation
1184 for this operand, so skip to the end of the
1185 alternative (should be just one character). */
1186 while (*p
&& *p
++ != ',')
1194 /* Scan all the constraint letters. See if the operand matches
1195 any of the constraints. Collect the valid register classes
1196 and see if this operand accepts memory. */
1198 classes
[i
] = NO_REGS
;
1199 while (*p
&& (c
= *p
++) != ',')
1203 op_types
[i
] = OP_WRITE
;
1207 op_types
[i
] = OP_READ_WRITE
;
1211 /* Ignore the next letter for this pass. */
1220 case '0': case '1': case '2': case '3': case '4':
1224 case 'm': case 'o': case 'V':
1225 /* It doesn't seem worth distinguishing between offsettable
1226 and non-offsettable addresses here. */
1228 if (GET_CODE (op
) == MEM
)
1233 if (GET_CODE (op
) == MEM
1234 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1235 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1240 if (GET_CODE (op
) == MEM
1241 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1242 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1247 #ifndef REAL_ARITHMETIC
1248 /* Match any floating double constant, but only if
1249 we can examine the bits of it reliably. */
1250 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1251 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1252 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1255 if (GET_CODE (op
) == CONST_DOUBLE
)
1260 if (GET_CODE (op
) == CONST_DOUBLE
)
1266 if (GET_CODE (op
) == CONST_DOUBLE
1267 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
1272 if (GET_CODE (op
) == CONST_INT
1273 || (GET_CODE (op
) == CONST_DOUBLE
1274 && GET_MODE (op
) == VOIDmode
))
1278 #ifdef LEGITIMATE_PIC_OPERAND_P
1279 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1286 if (GET_CODE (op
) == CONST_INT
1287 || (GET_CODE (op
) == CONST_DOUBLE
1288 && GET_MODE (op
) == VOIDmode
))
1300 if (GET_CODE (op
) == CONST_INT
1301 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
1309 #ifdef EXTRA_CONSTRAINT
1315 if (EXTRA_CONSTRAINT (op
, c
))
1321 if (GET_CODE (op
) == MEM
1323 #ifdef LEGITIMATE_PIC_OPERAND_P
1324 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1331 = reg_class_subunion
[(int) classes
[i
]][(int) GENERAL_REGS
];
1336 = reg_class_subunion
[(int) classes
[i
]]
1337 [(int) REG_CLASS_FROM_LETTER (c
)];
1342 /* How we account for this operand now depends on whether it is a
1343 pseudo register or not. If it is, we first check if any
1344 register classes are valid. If not, we ignore this alternative,
1345 since we want to assume that all pseudos get allocated for
1346 register preferencing. If some register class is valid, compute
1347 the costs of moving the pseudo into that class. */
1349 if (GET_CODE (op
) == REG
&& REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
1351 if (classes
[i
] == NO_REGS
)
1355 struct costs
*pp
= &this_op_costs
[i
];
1357 for (class = 0; class < N_REG_CLASSES
; class++)
1358 pp
->cost
[class] = may_move_cost
[class][(int) classes
[i
]];
1360 /* If the alternative actually allows memory, make things
1361 a bit cheaper since we won't need an extra insn to
1364 pp
->mem_cost
= (MEMORY_MOVE_COST (mode
, classes
[i
], 1)
1367 /* If we have assigned a class to this register in our
1368 first pass, add a cost to this alternative corresponding
1369 to what we would add if this register were not in the
1370 appropriate class. */
1374 += may_move_cost
[prefclass
[REGNO (op
)]][(int) classes
[i
]];
1378 /* Otherwise, if this alternative wins, either because we
1379 have already determined that or if we have a hard register of
1380 the proper class, there is no cost for this alternative. */
1383 || (GET_CODE (op
) == REG
1384 && reg_fits_class_p (op
, classes
[i
], 0, GET_MODE (op
))))
1387 /* If registers are valid, the cost of this alternative includes
1388 copying the object to and/or from a register. */
1390 else if (classes
[i
] != NO_REGS
)
1392 if (op_types
[i
] != OP_WRITE
)
1393 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1);
1395 if (op_types
[i
] != OP_READ
)
1396 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0);
1399 /* The only other way this alternative can be used is if this is a
1400 constant that could be placed into memory. */
1402 else if (CONSTANT_P (op
) && allows_mem
)
1403 alt_cost
+= MEMORY_MOVE_COST (mode
, classes
[i
], 1);
1411 /* Finally, update the costs with the information we've calculated
1412 about this alternative. */
1414 for (i
= 0; i
< n_ops
; i
++)
1415 if (GET_CODE (ops
[i
]) == REG
1416 && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1418 struct costs
*pp
= &op_costs
[i
], *qq
= &this_op_costs
[i
];
1419 int scale
= 1 + (op_types
[i
] == OP_READ_WRITE
);
1421 pp
->mem_cost
= MIN (pp
->mem_cost
,
1422 (qq
->mem_cost
+ alt_cost
) * scale
);
1424 for (class = 0; class < N_REG_CLASSES
; class++)
1425 pp
->cost
[class] = MIN (pp
->cost
[class],
1426 (qq
->cost
[class] + alt_cost
) * scale
);
1430 /* If this insn is a single set copying operand 1 to operand 0
1431 and one is a pseudo with the other a hard reg that is in its
1432 own register class, set the cost of that register class to -1. */
1434 if ((set
= single_set (insn
)) != 0
1435 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
)
1436 && GET_CODE (ops
[0]) == REG
&& GET_CODE (ops
[1]) == REG
)
1437 for (i
= 0; i
<= 1; i
++)
1438 if (REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
1440 int regno
= REGNO (ops
[!i
]);
1441 enum machine_mode mode
= GET_MODE (ops
[!i
]);
1445 if (regno
>= FIRST_PSEUDO_REGISTER
&& prefclass
!= 0
1446 && (reg_class_size
[prefclass
[regno
]]
1447 == CLASS_MAX_NREGS (prefclass
[regno
], mode
)))
1448 op_costs
[i
].cost
[prefclass
[regno
]] = -1;
1449 else if (regno
< FIRST_PSEUDO_REGISTER
)
1450 for (class = 0; class < N_REG_CLASSES
; class++)
1451 if (TEST_HARD_REG_BIT (reg_class_contents
[class], regno
)
1452 && reg_class_size
[class] == CLASS_MAX_NREGS (class, mode
))
1454 if (reg_class_size
[class] == 1)
1455 op_costs
[i
].cost
[class] = -1;
1458 for (nr
= 0; nr
< HARD_REGNO_NREGS(regno
, mode
); nr
++)
1460 if (!TEST_HARD_REG_BIT (reg_class_contents
[class], regno
+ nr
))
1464 if (nr
== HARD_REGNO_NREGS(regno
,mode
))
1465 op_costs
[i
].cost
[class] = -1;
1471 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1472 TO_P is zero) a register of class CLASS in mode MODE.
1474 X must not be a pseudo. */
1477 copy_cost (x
, mode
, class, to_p
)
1479 enum machine_mode mode
;
1480 enum reg_class
class;
1483 #ifdef HAVE_SECONDARY_RELOADS
1484 enum reg_class secondary_class
= NO_REGS
;
1487 /* If X is a SCRATCH, there is actually nothing to move since we are
1488 assuming optimal allocation. */
1490 if (GET_CODE (x
) == SCRATCH
)
1493 /* Get the class we will actually use for a reload. */
1494 class = PREFERRED_RELOAD_CLASS (x
, class);
1496 #ifdef HAVE_SECONDARY_RELOADS
1497 /* If we need a secondary reload (we assume here that we are using
1498 the secondary reload as an intermediate, not a scratch register), the
1499 cost is that to load the input into the intermediate register, then
1500 to copy them. We use a special value of TO_P to avoid recursion. */
1502 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1504 secondary_class
= SECONDARY_INPUT_RELOAD_CLASS (class, mode
, x
);
1507 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1509 secondary_class
= SECONDARY_OUTPUT_RELOAD_CLASS (class, mode
, x
);
1512 if (secondary_class
!= NO_REGS
)
1513 return (move_cost
[(int) secondary_class
][(int) class]
1514 + copy_cost (x
, mode
, secondary_class
, 2));
1515 #endif /* HAVE_SECONDARY_RELOADS */
1517 /* For memory, use the memory move cost, for (hard) registers, use the
1518 cost to move between the register classes, and use 2 for everything
1519 else (constants). */
1521 if (GET_CODE (x
) == MEM
|| class == NO_REGS
)
1522 return MEMORY_MOVE_COST (mode
, class, to_p
);
1524 else if (GET_CODE (x
) == REG
)
1525 return move_cost
[(int) REGNO_REG_CLASS (REGNO (x
))][(int) class];
1528 /* If this is a constant, we may eventually want to call rtx_cost here. */
1532 /* Record the pseudo registers we must reload into hard registers
1533 in a subexpression of a memory address, X.
1535 CLASS is the class that the register needs to be in and is either
1536 BASE_REG_CLASS or INDEX_REG_CLASS.
1538 SCALE is twice the amount to multiply the cost by (it is twice so we
1539 can represent half-cost adjustments). */
1542 record_address_regs (x
, class, scale
)
1544 enum reg_class
class;
1547 register enum rtx_code code
= GET_CODE (x
);
1560 /* When we have an address that is a sum,
1561 we must determine whether registers are "base" or "index" regs.
1562 If there is a sum of two registers, we must choose one to be
1563 the "base". Luckily, we can use the REGNO_POINTER_FLAG
1564 to make a good choice most of the time. We only need to do this
1565 on machines that can have two registers in an address and where
1566 the base and index register classes are different.
1568 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1569 that seems bogus since it should only be set when we are sure
1570 the register is being used as a pointer. */
1573 rtx arg0
= XEXP (x
, 0);
1574 rtx arg1
= XEXP (x
, 1);
1575 register enum rtx_code code0
= GET_CODE (arg0
);
1576 register enum rtx_code code1
= GET_CODE (arg1
);
1578 /* Look inside subregs. */
1579 if (code0
== SUBREG
)
1580 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1581 if (code1
== SUBREG
)
1582 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1584 /* If this machine only allows one register per address, it must
1585 be in the first operand. */
1587 if (MAX_REGS_PER_ADDRESS
== 1)
1588 record_address_regs (arg0
, class, scale
);
1590 /* If index and base registers are the same on this machine, just
1591 record registers in any non-constant operands. We assume here,
1592 as well as in the tests below, that all addresses are in
1595 else if (INDEX_REG_CLASS
== BASE_REG_CLASS
)
1597 record_address_regs (arg0
, class, scale
);
1598 if (! CONSTANT_P (arg1
))
1599 record_address_regs (arg1
, class, scale
);
1602 /* If the second operand is a constant integer, it doesn't change
1603 what class the first operand must be. */
1605 else if (code1
== CONST_INT
|| code1
== CONST_DOUBLE
)
1606 record_address_regs (arg0
, class, scale
);
1608 /* If the second operand is a symbolic constant, the first operand
1609 must be an index register. */
1611 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1612 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1614 /* If both operands are registers but one is already a hard register
1615 of index or base class, give the other the class that the hard
1618 #ifdef REG_OK_FOR_BASE_P
1619 else if (code0
== REG
&& code1
== REG
1620 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1621 && (REG_OK_FOR_BASE_P (arg0
) || REG_OK_FOR_INDEX_P (arg0
)))
1622 record_address_regs (arg1
,
1623 REG_OK_FOR_BASE_P (arg0
)
1624 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1626 else if (code0
== REG
&& code1
== REG
1627 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1628 && (REG_OK_FOR_BASE_P (arg1
) || REG_OK_FOR_INDEX_P (arg1
)))
1629 record_address_regs (arg0
,
1630 REG_OK_FOR_BASE_P (arg1
)
1631 ? INDEX_REG_CLASS
: BASE_REG_CLASS
,
1635 /* If one operand is known to be a pointer, it must be the base
1636 with the other operand the index. Likewise if the other operand
1639 else if ((code0
== REG
&& REGNO_POINTER_FLAG (REGNO (arg0
)))
1642 record_address_regs (arg0
, BASE_REG_CLASS
, scale
);
1643 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
);
1645 else if ((code1
== REG
&& REGNO_POINTER_FLAG (REGNO (arg1
)))
1648 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
);
1649 record_address_regs (arg1
, BASE_REG_CLASS
, scale
);
1652 /* Otherwise, count equal chances that each might be a base
1653 or index register. This case should be rare. */
1657 record_address_regs (arg0
, BASE_REG_CLASS
, scale
/ 2);
1658 record_address_regs (arg0
, INDEX_REG_CLASS
, scale
/ 2);
1659 record_address_regs (arg1
, BASE_REG_CLASS
, scale
/ 2);
1660 record_address_regs (arg1
, INDEX_REG_CLASS
, scale
/ 2);
1669 /* Double the importance of a pseudo register that is incremented
1670 or decremented, since it would take two extra insns
1671 if it ends up in the wrong place. If the operand is a pseudo,
1672 show it is being used in an INC_DEC context. */
1674 #ifdef FORBIDDEN_INC_DEC_CLASSES
1675 if (GET_CODE (XEXP (x
, 0)) == REG
1676 && REGNO (XEXP (x
, 0)) >= FIRST_PSEUDO_REGISTER
)
1677 in_inc_dec
[REGNO (XEXP (x
, 0))] = 1;
1680 record_address_regs (XEXP (x
, 0), class, 2 * scale
);
1685 register struct costs
*pp
= &costs
[REGNO (x
)];
1688 pp
->mem_cost
+= (MEMORY_MOVE_COST (Pmode
, class, 1) * scale
) / 2;
1690 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1691 pp
->cost
[i
] += (may_move_cost
[i
][(int) class] * scale
) / 2;
1697 register char *fmt
= GET_RTX_FORMAT (code
);
1699 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1701 record_address_regs (XEXP (x
, i
), class, scale
);
1706 #ifdef FORBIDDEN_INC_DEC_CLASSES
1708 /* Return 1 if REG is valid as an auto-increment memory reference
1709 to an object of MODE. */
1712 auto_inc_dec_reg_p (reg
, mode
)
1714 enum machine_mode mode
;
1716 #ifdef HAVE_POST_INCREMENT
1717 if (memory_address_p (mode
, gen_rtx_POST_INC (Pmode
, reg
)))
1721 #ifdef HAVE_POST_DECREMENT
1722 if (memory_address_p (mode
, gen_rtx_POST_DEC (Pmode
, reg
)))
1726 #ifdef HAVE_PRE_INCREMENT
1727 if (memory_address_p (mode
, gen_rtx_PRE_INC (Pmode
, reg
)))
1731 #ifdef HAVE_PRE_DECREMENT
1732 if (memory_address_p (mode
, gen_rtx_PRE_DEC (Pmode
, reg
)))
1740 #endif /* REGISTER_CONSTRAINTS */
1742 /* Allocate enough space to hold NUM_REGS registers for the tables used for
1743 reg_scan and flow_analysis that are indexed by the register number. If
1744 NEW_P is non zero, initialize all of the registers, otherwise only
1745 initialize the new registers allocated. The same table is kept from
1746 function to function, only reallocating it when we need more room. If
1747 RENUMBER_P is non zero, allocate the reg_renumber array also. */
1750 allocate_reg_info (num_regs
, new_p
, renumber_p
)
1755 static int regno_allocated
= 0;
1756 static int regno_max
= 0;
1757 static short *renumber
= (short *)0;
1761 int min
= (new_p
) ? 0 : regno_max
;
1763 /* If this message come up, and you want to fix it, then all of the tables
1764 like reg_renumber, etc. that use short will have to be found and lengthed
1765 to int or HOST_WIDE_INT. */
1767 /* Free up all storage allocated */
1772 free ((char *)reg_n_info
);
1773 free ((char *)renumber
);
1774 reg_n_info
= (reg_info
*)0;
1775 renumber
= (short *)0;
1777 regno_allocated
= 0;
1782 if (num_regs
> regno_allocated
)
1784 regno_allocated
= num_regs
+ (num_regs
/ 20); /* add some slop space */
1785 size_info
= regno_allocated
* sizeof (reg_info
);
1786 size_renumber
= regno_allocated
* sizeof (short);
1790 reg_n_info
= (reg_info
*) xmalloc (size_info
);
1791 renumber
= (short *) xmalloc (size_renumber
);
1794 else if (new_p
) /* if we're zapping everything, no need to realloc */
1796 free ((char *)reg_n_info
);
1797 free ((char *)renumber
);
1798 reg_n_info
= (reg_info
*) xmalloc (size_info
);
1799 renumber
= (short *) xmalloc (size_renumber
);
1804 reg_n_info
= (reg_info
*) xrealloc ((char *)reg_n_info
, size_info
);
1805 renumber
= (short *) xrealloc ((char *)renumber
, size_renumber
);
1811 bzero ((char *) ®_n_info
[min
], (num_regs
- min
) * sizeof (reg_info
));
1812 for (i
= min
; i
< num_regs
; i
++)
1814 REG_BASIC_BLOCK (i
) = REG_BLOCK_UNKNOWN
;
1820 reg_renumber
= renumber
;
1822 /* Tell the regset code about the new number of registers */
1823 MAX_REGNO_REG_SET (num_regs
, new_p
, renumber_p
);
1825 regno_max
= num_regs
;
1829 /* This is the `regscan' pass of the compiler, run just before cse
1830 and again just before loop.
1832 It finds the first and last use of each pseudo-register
1833 and records them in the vectors regno_first_uid, regno_last_uid
1834 and counts the number of sets in the vector reg_n_sets.
1836 REPEAT is nonzero the second time this is called. */
1838 /* Maximum number of parallel sets and clobbers in any insn in this fn.
1839 Always at least 3, since the combiner could put that many together
1840 and we want this to remain correct for all the remaining passes. */
1845 reg_scan (f
, nregs
, repeat
)
1852 allocate_reg_info (nregs
, TRUE
, FALSE
);
1855 for (insn
= f
; insn
; insn
= NEXT_INSN (insn
))
1856 if (GET_CODE (insn
) == INSN
1857 || GET_CODE (insn
) == CALL_INSN
1858 || GET_CODE (insn
) == JUMP_INSN
)
1860 if (GET_CODE (PATTERN (insn
)) == PARALLEL
1861 && XVECLEN (PATTERN (insn
), 0) > max_parallel
)
1862 max_parallel
= XVECLEN (PATTERN (insn
), 0);
1863 reg_scan_mark_refs (PATTERN (insn
), insn
, 0);
1865 if (REG_NOTES (insn
))
1866 reg_scan_mark_refs (REG_NOTES (insn
), insn
, 1);
1870 /* X is the expression to scan. INSN is the insn it appears in.
1871 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body. */
1874 reg_scan_mark_refs (x
, insn
, note_flag
)
1879 register enum rtx_code code
= GET_CODE (x
);
1898 register int regno
= REGNO (x
);
1900 REGNO_LAST_NOTE_UID (regno
) = INSN_UID (insn
);
1902 REGNO_LAST_UID (regno
) = INSN_UID (insn
);
1903 if (REGNO_FIRST_UID (regno
) == 0)
1904 REGNO_FIRST_UID (regno
) = INSN_UID (insn
);
1910 reg_scan_mark_refs (XEXP (x
, 0), insn
, note_flag
);
1912 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
);
1917 reg_scan_mark_refs (XEXP (x
, 1), insn
, note_flag
);
1921 /* Count a set of the destination if it is a register. */
1922 for (dest
= SET_DEST (x
);
1923 GET_CODE (dest
) == SUBREG
|| GET_CODE (dest
) == STRICT_LOW_PART
1924 || GET_CODE (dest
) == ZERO_EXTEND
;
1925 dest
= XEXP (dest
, 0))
1928 if (GET_CODE (dest
) == REG
)
1929 REG_N_SETS (REGNO (dest
))++;
1931 /* If this is setting a pseudo from another pseudo or the sum of a
1932 pseudo and a constant integer and the other pseudo is known to be
1933 a pointer, set the destination to be a pointer as well.
1935 Likewise if it is setting the destination from an address or from a
1936 value equivalent to an address or to the sum of an address and
1939 But don't do any of this if the pseudo corresponds to a user
1940 variable since it should have already been set as a pointer based
1943 if (GET_CODE (SET_DEST (x
)) == REG
1944 && REGNO (SET_DEST (x
)) >= FIRST_PSEUDO_REGISTER
1945 /* If the destination pseudo is set more than once, then other
1946 sets might not be to a pointer value (consider access to a
1947 union in two threads of control in the presense of global
1948 optimizations). So only set REGNO_POINTER_FLAG on the destination
1949 pseudo if this is the only set of that pseudo. */
1950 && REG_N_SETS (REGNO (SET_DEST (x
))) == 1
1951 && ! REG_USERVAR_P (SET_DEST (x
))
1952 && ! REGNO_POINTER_FLAG (REGNO (SET_DEST (x
)))
1953 && ((GET_CODE (SET_SRC (x
)) == REG
1954 && REGNO_POINTER_FLAG (REGNO (SET_SRC (x
))))
1955 || ((GET_CODE (SET_SRC (x
)) == PLUS
1956 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
1957 && GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
1958 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
1959 && REGNO_POINTER_FLAG (REGNO (XEXP (SET_SRC (x
), 0))))
1960 || GET_CODE (SET_SRC (x
)) == CONST
1961 || GET_CODE (SET_SRC (x
)) == SYMBOL_REF
1962 || GET_CODE (SET_SRC (x
)) == LABEL_REF
1963 || (GET_CODE (SET_SRC (x
)) == HIGH
1964 && (GET_CODE (XEXP (SET_SRC (x
), 0)) == CONST
1965 || GET_CODE (XEXP (SET_SRC (x
), 0)) == SYMBOL_REF
1966 || GET_CODE (XEXP (SET_SRC (x
), 0)) == LABEL_REF
))
1967 || ((GET_CODE (SET_SRC (x
)) == PLUS
1968 || GET_CODE (SET_SRC (x
)) == LO_SUM
)
1969 && (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST
1970 || GET_CODE (XEXP (SET_SRC (x
), 1)) == SYMBOL_REF
1971 || GET_CODE (XEXP (SET_SRC (x
), 1)) == LABEL_REF
))
1972 || ((note
= find_reg_note (insn
, REG_EQUAL
, 0)) != 0
1973 && (GET_CODE (XEXP (note
, 0)) == CONST
1974 || GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
1975 || GET_CODE (XEXP (note
, 0)) == LABEL_REF
))))
1976 REGNO_POINTER_FLAG (REGNO (SET_DEST (x
))) = 1;
1978 /* ... fall through ... */
1982 register char *fmt
= GET_RTX_FORMAT (code
);
1984 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1987 reg_scan_mark_refs (XEXP (x
, i
), insn
, note_flag
);
1988 else if (fmt
[i
] == 'E' && XVEC (x
, i
) != 0)
1991 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1992 reg_scan_mark_refs (XVECEXP (x
, i
, j
), insn
, note_flag
);
1999 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2003 reg_class_subset_p (c1
, c2
)
2004 register enum reg_class c1
;
2005 register enum reg_class c2
;
2007 if (c1
== c2
) return 1;
2012 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int)c1
],
2013 reg_class_contents
[(int)c2
],
2018 /* Return nonzero if there is a register that is in both C1 and C2. */
2021 reg_classes_intersect_p (c1
, c2
)
2022 register enum reg_class c1
;
2023 register enum reg_class c2
;
2030 if (c1
== c2
) return 1;
2032 if (c1
== ALL_REGS
|| c2
== ALL_REGS
)
2035 COPY_HARD_REG_SET (c
, reg_class_contents
[(int) c1
]);
2036 AND_HARD_REG_SET (c
, reg_class_contents
[(int) c2
]);
2038 GO_IF_HARD_REG_SUBSET (c
, reg_class_contents
[(int) NO_REGS
], lose
);
2045 /* Release any memory allocated by register sets. */
2048 regset_release_memory ()
2050 if (basic_block_live_at_start
)
2052 free_regset_vector (basic_block_live_at_start
, n_basic_blocks
);
2053 basic_block_live_at_start
= 0;
2056 FREE_REG_SET (regs_live_at_setjmp
);
2057 bitmap_release_memory ();