1 /* Move registers around to reduce number of move instructions needed.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This module makes some simple RTL code transformations which
24 improve the subsequent register allocation. */
28 #include "coretypes.h"
30 #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */
32 #include "insn-config.h"
36 #include "hard-reg-set.h"
40 #include "basic-block.h"
45 #include "tree-pass.h"
49 static int optimize_reg_copy_1 (rtx
, rtx
, rtx
);
50 static void optimize_reg_copy_2 (rtx
, rtx
, rtx
);
51 static void optimize_reg_copy_3 (rtx
, rtx
, rtx
);
52 static void copy_src_to_dest (rtx
, rtx
, rtx
);
62 int with
[MAX_RECOG_OPERANDS
];
63 enum match_use use
[MAX_RECOG_OPERANDS
];
64 int commutative
[MAX_RECOG_OPERANDS
];
65 int early_clobber
[MAX_RECOG_OPERANDS
];
68 static int find_matches (rtx
, struct match
*);
69 static int fixup_match_2 (rtx
, rtx
, rtx
, rtx
);
71 /* Return nonzero if registers with CLASS1 and CLASS2 can be merged without
72 causing too much register allocation problems. */
74 regclass_compatible_p (enum reg_class class0
, enum reg_class class1
)
76 return (class0
== class1
77 || (reg_class_subset_p (class0
, class1
)
78 && ! CLASS_LIKELY_SPILLED_P (class0
))
79 || (reg_class_subset_p (class1
, class0
)
80 && ! CLASS_LIKELY_SPILLED_P (class1
)));
86 /* Find the place in the rtx X where REG is used as a memory address.
87 Return the MEM rtx that so uses it.
88 If PLUSCONST is nonzero, search instead for a memory address equivalent to
89 (plus REG (const_int PLUSCONST)).
91 If such an address does not appear, return 0.
92 If REG appears more than once, or is used other than in such an address,
96 find_use_as_address (rtx x
, rtx reg
, HOST_WIDE_INT plusconst
)
98 enum rtx_code code
= GET_CODE (x
);
99 const char * const fmt
= GET_RTX_FORMAT (code
);
104 if (code
== MEM
&& XEXP (x
, 0) == reg
&& plusconst
== 0)
107 if (code
== MEM
&& GET_CODE (XEXP (x
, 0)) == PLUS
108 && XEXP (XEXP (x
, 0), 0) == reg
109 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
110 && INTVAL (XEXP (XEXP (x
, 0), 1)) == plusconst
)
113 if (code
== SIGN_EXTRACT
|| code
== ZERO_EXTRACT
)
115 /* If REG occurs inside a MEM used in a bit-field reference,
116 that is unacceptable. */
117 if (find_use_as_address (XEXP (x
, 0), reg
, 0) != 0)
118 return (rtx
) (size_t) 1;
122 return (rtx
) (size_t) 1;
124 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
128 tem
= find_use_as_address (XEXP (x
, i
), reg
, plusconst
);
132 return (rtx
) (size_t) 1;
134 else if (fmt
[i
] == 'E')
137 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
139 tem
= find_use_as_address (XVECEXP (x
, i
, j
), reg
, plusconst
);
143 return (rtx
) (size_t) 1;
152 /* INC_INSN is an instruction that adds INCREMENT to REG.
153 Try to fold INC_INSN as a post/pre in/decrement into INSN.
154 Iff INC_INSN_SET is nonzero, inc_insn has a destination different from src.
155 Return nonzero for success. */
157 try_auto_increment (rtx insn
, rtx inc_insn
, rtx inc_insn_set
, rtx reg
,
158 HOST_WIDE_INT increment
, int pre
)
160 enum rtx_code inc_code
;
162 rtx pset
= single_set (insn
);
165 /* Can't use the size of SET_SRC, we might have something like
166 (sign_extend:SI (mem:QI ... */
167 rtx use
= find_use_as_address (pset
, reg
, 0);
168 if (use
!= 0 && use
!= (rtx
) (size_t) 1)
170 int size
= GET_MODE_SIZE (GET_MODE (use
));
172 || (HAVE_POST_INCREMENT
173 && pre
== 0 && (inc_code
= POST_INC
, increment
== size
))
174 || (HAVE_PRE_INCREMENT
175 && pre
== 1 && (inc_code
= PRE_INC
, increment
== size
))
176 || (HAVE_POST_DECREMENT
177 && pre
== 0 && (inc_code
= POST_DEC
, increment
== -size
))
178 || (HAVE_PRE_DECREMENT
179 && pre
== 1 && (inc_code
= PRE_DEC
, increment
== -size
))
185 &SET_SRC (inc_insn_set
),
186 XEXP (SET_SRC (inc_insn_set
), 0), 1);
187 validate_change (insn
, &XEXP (use
, 0),
188 gen_rtx_fmt_e (inc_code
, Pmode
, reg
), 1);
189 if (apply_change_group ())
191 /* If there is a REG_DEAD note on this insn, we must
192 change this not to REG_UNUSED meaning that the register
193 is set, but the value is dead. Failure to do so will
194 result in sched1 dying -- when it recomputes lifetime
195 information, the number of REG_DEAD notes will have
197 rtx note
= find_reg_note (insn
, REG_DEAD
, reg
);
199 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
201 add_reg_note (insn
, REG_INC
, reg
);
204 delete_insn (inc_insn
);
215 static int *regno_src_regno
;
217 /* INSN is a copy from SRC to DEST, both registers, and SRC does not die
220 Search forward to see if SRC dies before either it or DEST is modified,
221 but don't scan past the end of a basic block. If so, we can replace SRC
222 with DEST and let SRC die in INSN.
224 This will reduce the number of registers live in that range and may enable
225 DEST to be tied to SRC, thus often saving one register in addition to a
226 register-register copy. */
229 optimize_reg_copy_1 (rtx insn
, rtx dest
, rtx src
)
234 int sregno
= REGNO (src
);
235 int dregno
= REGNO (dest
);
236 basic_block bb
= BLOCK_FOR_INSN (insn
);
238 /* We don't want to mess with hard regs if register classes are small. */
240 || (SMALL_REGISTER_CLASSES
241 && (sregno
< FIRST_PSEUDO_REGISTER
242 || dregno
< FIRST_PSEUDO_REGISTER
))
243 /* We don't see all updates to SP if they are in an auto-inc memory
244 reference, so we must disallow this optimization on them. */
245 || sregno
== STACK_POINTER_REGNUM
|| dregno
== STACK_POINTER_REGNUM
)
248 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
252 if (BLOCK_FOR_INSN (p
) != bb
)
255 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
256 /* If SRC is an asm-declared register, it must not be replaced
257 in any asm. Unfortunately, the REG_EXPR tree for the asm
258 variable may be absent in the SRC rtx, so we can't check the
259 actual register declaration easily (the asm operand will have
260 it, though). To avoid complicating the test for a rare case,
261 we just don't perform register replacement for a hard reg
262 mentioned in an asm. */
263 || (sregno
< FIRST_PSEUDO_REGISTER
264 && asm_noperands (PATTERN (p
)) >= 0
265 && reg_overlap_mentioned_p (src
, PATTERN (p
)))
266 /* Don't change hard registers used by a call. */
267 || (CALL_P (p
) && sregno
< FIRST_PSEUDO_REGISTER
268 && find_reg_fusage (p
, USE
, src
))
269 /* Don't change a USE of a register. */
270 || (GET_CODE (PATTERN (p
)) == USE
271 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
274 /* See if all of SRC dies in P. This test is slightly more
275 conservative than it needs to be. */
276 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
)) != 0
277 && GET_MODE (XEXP (note
, 0)) == GET_MODE (src
))
284 int s_freq_calls
= 0;
285 int d_freq_calls
= 0;
287 /* We can do the optimization. Scan forward from INSN again,
288 replacing regs as we go. Set FAILED if a replacement can't
289 be done. In that case, we can't move the death note for SRC.
290 This should be rare. */
292 /* Set to stop at next insn. */
293 for (q
= next_real_insn (insn
);
294 q
!= next_real_insn (p
);
295 q
= next_real_insn (q
))
297 if (reg_overlap_mentioned_p (src
, PATTERN (q
)))
299 /* If SRC is a hard register, we might miss some
300 overlapping registers with validate_replace_rtx,
301 so we would have to undo it. We can't if DEST is
302 present in the insn, so fail in that combination
304 if (sregno
< FIRST_PSEUDO_REGISTER
305 && reg_mentioned_p (dest
, PATTERN (q
)))
308 /* Attempt to replace all uses. */
309 else if (!validate_replace_rtx (src
, dest
, q
))
312 /* If this succeeded, but some part of the register
313 is still present, undo the replacement. */
314 else if (sregno
< FIRST_PSEUDO_REGISTER
315 && reg_overlap_mentioned_p (src
, PATTERN (q
)))
317 validate_replace_rtx (dest
, src
, q
);
322 /* For SREGNO, count the total number of insns scanned.
323 For DREGNO, count the total number of insns scanned after
324 passing the death note for DREGNO. */
325 if (!DEBUG_INSN_P (p
))
332 /* If the insn in which SRC dies is a CALL_INSN, don't count it
333 as a call that has been crossed. Otherwise, count it. */
334 if (q
!= p
&& CALL_P (q
))
336 /* Similarly, total calls for SREGNO, total calls beyond
337 the death note for DREGNO. */
339 s_freq_calls
+= REG_FREQ_FROM_BB (BLOCK_FOR_INSN (q
));
343 d_freq_calls
+= REG_FREQ_FROM_BB (BLOCK_FOR_INSN (q
));
347 /* If DEST dies here, remove the death note and save it for
348 later. Make sure ALL of DEST dies here; again, this is
349 overly conservative. */
351 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)) != 0)
353 if (GET_MODE (XEXP (dest_death
, 0)) != GET_MODE (dest
))
354 failed
= 1, dest_death
= 0;
356 remove_note (q
, dest_death
);
362 /* These counters need to be updated if and only if we are
363 going to move the REG_DEAD note. */
364 if (sregno
>= FIRST_PSEUDO_REGISTER
)
366 if (REG_LIVE_LENGTH (sregno
) >= 0)
368 REG_LIVE_LENGTH (sregno
) -= s_length
;
369 /* REG_LIVE_LENGTH is only an approximation after
370 combine if sched is not run, so make sure that we
371 still have a reasonable value. */
372 if (REG_LIVE_LENGTH (sregno
) < 2)
373 REG_LIVE_LENGTH (sregno
) = 2;
376 REG_N_CALLS_CROSSED (sregno
) -= s_n_calls
;
377 REG_FREQ_CALLS_CROSSED (sregno
) -= s_freq_calls
;
380 /* Move death note of SRC from P to INSN. */
381 remove_note (p
, note
);
382 XEXP (note
, 1) = REG_NOTES (insn
);
383 REG_NOTES (insn
) = note
;
386 /* DEST is also dead if INSN has a REG_UNUSED note for DEST. */
388 && (dest_death
= find_regno_note (insn
, REG_UNUSED
, dregno
)))
390 PUT_REG_NOTE_KIND (dest_death
, REG_DEAD
);
391 remove_note (insn
, dest_death
);
394 /* Put death note of DEST on P if we saw it die. */
397 XEXP (dest_death
, 1) = REG_NOTES (p
);
398 REG_NOTES (p
) = dest_death
;
400 if (dregno
>= FIRST_PSEUDO_REGISTER
)
402 /* If and only if we are moving the death note for DREGNO,
403 then we need to update its counters. */
404 if (REG_LIVE_LENGTH (dregno
) >= 0)
405 REG_LIVE_LENGTH (dregno
) += d_length
;
406 REG_N_CALLS_CROSSED (dregno
) += d_n_calls
;
407 REG_FREQ_CALLS_CROSSED (dregno
) += d_freq_calls
;
414 /* If SRC is a hard register which is set or killed in some other
415 way, we can't do this optimization. */
416 else if (sregno
< FIRST_PSEUDO_REGISTER
417 && dead_or_set_p (p
, src
))
423 /* INSN is a copy of SRC to DEST, in which SRC dies. See if we now have
424 a sequence of insns that modify DEST followed by an insn that sets
425 SRC to DEST in which DEST dies, with no prior modification of DEST.
426 (There is no need to check if the insns in between actually modify
427 DEST. We should not have cases where DEST is not modified, but
428 the optimization is safe if no such modification is detected.)
429 In that case, we can replace all uses of DEST, starting with INSN and
430 ending with the set of SRC to DEST, with SRC. We do not do this
431 optimization if a CALL_INSN is crossed unless SRC already crosses a
432 call or if DEST dies before the copy back to SRC.
434 It is assumed that DEST and SRC are pseudos; it is too complicated to do
435 this for hard registers since the substitutions we may make might fail. */
438 optimize_reg_copy_2 (rtx insn
, rtx dest
, rtx src
)
442 int sregno
= REGNO (src
);
443 int dregno
= REGNO (dest
);
444 basic_block bb
= BLOCK_FOR_INSN (insn
);
446 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
450 if (BLOCK_FOR_INSN (p
) != bb
)
453 set
= single_set (p
);
454 if (set
&& SET_SRC (set
) == dest
&& SET_DEST (set
) == src
455 && find_reg_note (p
, REG_DEAD
, dest
))
457 /* We can do the optimization. Scan forward from INSN again,
458 replacing regs as we go. */
460 /* Set to stop at next insn. */
461 for (q
= insn
; q
!= NEXT_INSN (p
); q
= NEXT_INSN (q
))
464 if (reg_mentioned_p (dest
, PATTERN (q
)))
468 PATTERN (q
) = replace_rtx (PATTERN (q
), dest
, src
);
469 note
= FIND_REG_INC_NOTE (q
, dest
);
472 remove_note (q
, note
);
473 add_reg_note (q
, REG_INC
, src
);
480 int freq
= REG_FREQ_FROM_BB (BLOCK_FOR_INSN (q
));
481 REG_N_CALLS_CROSSED (dregno
)--;
482 REG_N_CALLS_CROSSED (sregno
)++;
483 REG_FREQ_CALLS_CROSSED (dregno
) -= freq
;
484 REG_FREQ_CALLS_CROSSED (sregno
) += freq
;
488 remove_note (p
, find_reg_note (p
, REG_DEAD
, dest
));
489 REG_N_DEATHS (dregno
)--;
490 remove_note (insn
, find_reg_note (insn
, REG_DEAD
, src
));
491 REG_N_DEATHS (sregno
)--;
495 if (reg_set_p (src
, p
)
496 || find_reg_note (p
, REG_DEAD
, dest
)
497 || (CALL_P (p
) && REG_N_CALLS_CROSSED (sregno
) == 0))
502 /* INSN is a ZERO_EXTEND or SIGN_EXTEND of SRC to DEST.
503 Look if SRC dies there, and if it is only set once, by loading
504 it from memory. If so, try to incorporate the zero/sign extension
505 into the memory read, change SRC to the mode of DEST, and alter
506 the remaining accesses to use the appropriate SUBREG. This allows
507 SRC and DEST to be tied later. */
509 optimize_reg_copy_3 (rtx insn
, rtx dest
, rtx src
)
511 rtx src_reg
= XEXP (src
, 0);
512 int src_no
= REGNO (src_reg
);
513 int dst_no
= REGNO (dest
);
515 enum machine_mode old_mode
;
516 basic_block bb
= BLOCK_FOR_INSN (insn
);
518 if (src_no
< FIRST_PSEUDO_REGISTER
519 || dst_no
< FIRST_PSEUDO_REGISTER
520 || ! find_reg_note (insn
, REG_DEAD
, src_reg
)
521 || REG_N_DEATHS (src_no
) != 1
522 || REG_N_SETS (src_no
) != 1)
525 for (p
= PREV_INSN (insn
); p
&& ! reg_set_p (src_reg
, p
); p
= PREV_INSN (p
))
526 if (INSN_P (p
) && BLOCK_FOR_INSN (p
) != bb
)
529 if (! p
|| BLOCK_FOR_INSN (p
) != bb
)
532 if (! (set
= single_set (p
))
533 || !MEM_P (SET_SRC (set
))
534 /* If there's a REG_EQUIV note, this must be an insn that loads an
535 argument. Prefer keeping the note over doing this optimization. */
536 || find_reg_note (p
, REG_EQUIV
, NULL_RTX
)
537 || SET_DEST (set
) != src_reg
)
540 /* Be conservative: although this optimization is also valid for
541 volatile memory references, that could cause trouble in later passes. */
542 if (MEM_VOLATILE_P (SET_SRC (set
)))
545 /* Do not use a SUBREG to truncate from one mode to another if truncation
547 if (GET_MODE_BITSIZE (GET_MODE (src_reg
)) <= GET_MODE_BITSIZE (GET_MODE (src
))
548 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (src
)),
549 GET_MODE_BITSIZE (GET_MODE (src_reg
))))
552 old_mode
= GET_MODE (src_reg
);
553 PUT_MODE (src_reg
, GET_MODE (src
));
554 XEXP (src
, 0) = SET_SRC (set
);
556 /* Include this change in the group so that it's easily undone if
557 one of the changes in the group is invalid. */
558 validate_change (p
, &SET_SRC (set
), src
, 1);
560 /* Now walk forward making additional replacements. We want to be able
561 to undo all the changes if a later substitution fails. */
562 while (p
= NEXT_INSN (p
), p
!= insn
)
567 /* Make a tentative change. */
568 validate_replace_rtx_group (src_reg
,
569 gen_lowpart_SUBREG (old_mode
, src_reg
),
573 validate_replace_rtx_group (src
, src_reg
, insn
);
575 /* Now see if all the changes are valid. */
576 if (! apply_change_group ())
578 /* One or more changes were no good. Back out everything. */
579 PUT_MODE (src_reg
, old_mode
);
580 XEXP (src
, 0) = src_reg
;
584 rtx note
= find_reg_note (p
, REG_EQUAL
, NULL_RTX
);
586 remove_note (p
, note
);
591 /* If we were not able to update the users of src to use dest directly, try
592 instead moving the value to dest directly before the operation. */
595 copy_src_to_dest (rtx insn
, rtx src
, rtx dest
)
609 /* A REG_LIVE_LENGTH of -1 indicates the register is equivalent to a constant
610 or memory location and is used infrequently; a REG_LIVE_LENGTH of -2 is
611 parameter when there is no frame pointer that is not allocated a register.
612 For now, we just reject them, rather than incrementing the live length. */
615 && REG_LIVE_LENGTH (REGNO (src
)) > 0
617 && REG_LIVE_LENGTH (REGNO (dest
)) > 0
618 && (set
= single_set (insn
)) != NULL_RTX
619 && !reg_mentioned_p (dest
, SET_SRC (set
))
620 && GET_MODE (src
) == GET_MODE (dest
))
622 int old_num_regs
= reg_rtx_no
;
624 /* Generate the src->dest move. */
626 emit_move_insn (dest
, src
);
629 /* If this sequence uses new registers, we may not use it. */
630 if (old_num_regs
!= reg_rtx_no
631 || ! validate_replace_rtx (src
, dest
, insn
))
633 /* We have to restore reg_rtx_no to its old value, lest
634 recompute_reg_usage will try to compute the usage of the
635 new regs, yet reg_n_info is not valid for them. */
636 reg_rtx_no
= old_num_regs
;
639 emit_insn_before (seq
, insn
);
640 move_insn
= PREV_INSN (insn
);
641 p_move_notes
= ®_NOTES (move_insn
);
642 p_insn_notes
= ®_NOTES (insn
);
644 /* Move any notes mentioning src to the move instruction. */
645 for (link
= REG_NOTES (insn
); link
!= NULL_RTX
; link
= next
)
647 next
= XEXP (link
, 1);
648 if (XEXP (link
, 0) == src
)
650 *p_move_notes
= link
;
651 p_move_notes
= &XEXP (link
, 1);
655 *p_insn_notes
= link
;
656 p_insn_notes
= &XEXP (link
, 1);
660 *p_move_notes
= NULL_RTX
;
661 *p_insn_notes
= NULL_RTX
;
663 insn_uid
= INSN_UID (insn
);
664 move_uid
= INSN_UID (move_insn
);
666 /* Update the various register tables. */
667 dest_regno
= REGNO (dest
);
668 INC_REG_N_SETS (dest_regno
, 1);
669 REG_LIVE_LENGTH (dest_regno
)++;
670 src_regno
= REGNO (src
);
671 if (! find_reg_note (move_insn
, REG_DEAD
, src
))
672 REG_LIVE_LENGTH (src_regno
)++;
676 /* reg_set_in_bb[REGNO] points to basic block iff the register is set
677 only once in the given block and has REG_EQUAL note. */
679 static basic_block
*reg_set_in_bb
;
681 /* Size of reg_set_in_bb array. */
682 static unsigned int max_reg_computed
;
685 /* Return whether REG is set in only one location, and is set to a
686 constant, but is set in a different basic block from INSN (an
687 instructions which uses REG). In this case REG is equivalent to a
688 constant, and we don't want to break that equivalence, because that
689 may increase register pressure and make reload harder. If REG is
690 set in the same basic block as INSN, we don't worry about it,
691 because we'll probably need a register anyhow (??? but what if REG
692 is used in a different basic block as well as this one?). */
695 reg_is_remote_constant_p (rtx reg
, rtx insn
)
703 max_reg_computed
= max
= max_reg_num ();
704 reg_set_in_bb
= XCNEWVEC (basic_block
, max
);
714 /* This is the instruction which sets REG. If there is a
715 REG_EQUAL note, then REG is equivalent to a constant. */
717 && REG_P (SET_DEST (s
))
718 && REG_N_SETS (REGNO (SET_DEST (s
))) == 1
719 && find_reg_note (p
, REG_EQUAL
, NULL_RTX
))
720 reg_set_in_bb
[REGNO (SET_DEST (s
))] = bb
;
724 gcc_assert (REGNO (reg
) < max_reg_computed
);
725 if (reg_set_in_bb
[REGNO (reg
)] == NULL
)
727 return (reg_set_in_bb
[REGNO (reg
)] != BLOCK_FOR_INSN (insn
));
730 /* INSN is adding a CONST_INT to a REG. We search backwards looking for
731 another add immediate instruction with the same source and dest registers,
732 and if we find one, we change INSN to an increment, and return 1. If
733 no changes are made, we return 0.
736 (set (reg100) (plus reg1 offset1))
738 (set (reg100) (plus reg1 offset2))
740 (set (reg100) (plus reg1 offset1))
742 (set (reg100) (plus reg100 offset2-offset1)) */
744 /* ??? What does this comment mean? */
745 /* cse disrupts preincrement / postdecrement sequences when it finds a
746 hard register as ultimate source, like the frame pointer. */
749 fixup_match_2 (rtx insn
, rtx dst
, rtx src
, rtx offset
)
751 rtx p
, dst_death
= 0;
752 int length
, num_calls
= 0, freq_calls
= 0;
753 basic_block bb
= BLOCK_FOR_INSN (insn
);
755 /* If SRC dies in INSN, we'd have to move the death note. This is
756 considered to be very unlikely, so we just skip the optimization
758 if (find_regno_note (insn
, REG_DEAD
, REGNO (src
)))
761 /* Scan backward to find the first instruction that sets DST. */
763 for (length
= 0, p
= PREV_INSN (insn
); p
; p
= PREV_INSN (p
))
769 if (BLOCK_FOR_INSN (p
) != bb
)
772 if (find_regno_note (p
, REG_DEAD
, REGNO (dst
)))
774 if (! dst_death
&& !DEBUG_INSN_P (p
))
777 pset
= single_set (p
);
778 if (pset
&& SET_DEST (pset
) == dst
779 && GET_CODE (SET_SRC (pset
)) == PLUS
780 && XEXP (SET_SRC (pset
), 0) == src
781 && CONST_INT_P (XEXP (SET_SRC (pset
), 1)))
783 HOST_WIDE_INT newconst
784 = INTVAL (offset
) - INTVAL (XEXP (SET_SRC (pset
), 1));
785 rtx add
= gen_add3_insn (dst
, dst
, GEN_INT (newconst
));
787 if (add
&& validate_change (insn
, &PATTERN (insn
), add
, 0))
789 /* Remove the death note for DST from DST_DEATH. */
792 remove_death (REGNO (dst
), dst_death
);
793 REG_LIVE_LENGTH (REGNO (dst
)) += length
;
794 REG_N_CALLS_CROSSED (REGNO (dst
)) += num_calls
;
795 REG_FREQ_CALLS_CROSSED (REGNO (dst
)) += freq_calls
;
800 "Fixed operand of insn %d.\n",
804 for (p
= PREV_INSN (insn
); p
; p
= PREV_INSN (p
))
808 if (BLOCK_FOR_INSN (p
) != bb
)
810 if (reg_overlap_mentioned_p (dst
, PATTERN (p
)))
812 if (try_auto_increment (p
, insn
, 0, dst
, newconst
, 0))
817 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
821 if (BLOCK_FOR_INSN (p
) != bb
)
823 if (reg_overlap_mentioned_p (dst
, PATTERN (p
)))
825 try_auto_increment (p
, insn
, 0, dst
, newconst
, 1);
834 if (reg_set_p (dst
, PATTERN (p
)))
837 /* If we have passed a call instruction, and the
838 pseudo-reg SRC is not already live across a call,
839 then don't perform the optimization. */
840 /* reg_set_p is overly conservative for CALL_INSNS, thinks that all
841 hard regs are clobbered. Thus, we only use it for src for
848 freq_calls
+= REG_FREQ_FROM_BB (BLOCK_FOR_INSN (p
));
851 if (REG_N_CALLS_CROSSED (REGNO (src
)) == 0)
854 if (call_used_regs
[REGNO (dst
)]
855 || find_reg_fusage (p
, CLOBBER
, dst
))
858 else if (reg_set_p (src
, PATTERN (p
)))
865 /* A forward pass. Replace output operands with input operands. */
868 regmove_forward_pass (void)
873 if (! flag_expensive_optimizations
)
877 fprintf (dump_file
, "Starting forward pass...\n");
881 FOR_BB_INSNS (bb
, insn
)
883 rtx set
= single_set (insn
);
887 if ((GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
888 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
)
889 && REG_P (XEXP (SET_SRC (set
), 0))
890 && REG_P (SET_DEST (set
)))
891 optimize_reg_copy_3 (insn
, SET_DEST (set
), SET_SRC (set
));
893 if (REG_P (SET_SRC (set
))
894 && REG_P (SET_DEST (set
)))
896 /* If this is a register-register copy where SRC is not dead,
897 see if we can optimize it. If this optimization succeeds,
898 it will become a copy where SRC is dead. */
899 if ((find_reg_note (insn
, REG_DEAD
, SET_SRC (set
))
900 || optimize_reg_copy_1 (insn
, SET_DEST (set
), SET_SRC (set
)))
901 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
903 /* Similarly for a pseudo-pseudo copy when SRC is dead. */
904 if (REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
905 optimize_reg_copy_2 (insn
, SET_DEST (set
), SET_SRC (set
));
906 if (regno_src_regno
[REGNO (SET_DEST (set
))] < 0
907 && SET_SRC (set
) != SET_DEST (set
))
909 int srcregno
= REGNO (SET_SRC (set
));
910 if (regno_src_regno
[srcregno
] >= 0)
911 srcregno
= regno_src_regno
[srcregno
];
912 regno_src_regno
[REGNO (SET_DEST (set
))] = srcregno
;
920 /* A backward pass. Replace input operands with output operands. */
923 regmove_backward_pass (void)
929 fprintf (dump_file
, "Starting backward pass...\n");
931 FOR_EACH_BB_REVERSE (bb
)
933 /* ??? Use the safe iterator because fixup_match_2 can remove
934 insns via try_auto_increment. */
935 FOR_BB_INSNS_REVERSE_SAFE (bb
, insn
, prev
)
938 rtx copy_src
, copy_dst
;
945 if (! find_matches (insn
, &match
))
948 /* Now scan through the operands looking for a destination operand
949 which is supposed to match a source operand.
950 Then scan backward for an instruction which sets the source
951 operand. If safe, then replace the source operand with the
952 dest operand in both instructions. */
956 for (op_no
= 0; op_no
< recog_data
.n_operands
; op_no
++)
958 rtx set
, p
, src
, dst
;
959 rtx src_note
, dst_note
;
960 int num_calls
= 0, freq_calls
= 0;
961 enum reg_class src_class
, dst_class
;
964 match_no
= match
.with
[op_no
];
966 /* Nothing to do if the two operands aren't supposed to match. */
970 dst
= recog_data
.operand
[match_no
];
971 src
= recog_data
.operand
[op_no
];
977 || REGNO (dst
) < FIRST_PSEUDO_REGISTER
978 || REG_LIVE_LENGTH (REGNO (dst
)) < 0
979 || GET_MODE (src
) != GET_MODE (dst
))
982 /* If the operands already match, then there is nothing to do. */
983 if (operands_match_p (src
, dst
))
986 if (match
.commutative
[op_no
] >= 0)
988 rtx comm
= recog_data
.operand
[match
.commutative
[op_no
]];
989 if (operands_match_p (comm
, dst
))
993 set
= single_set (insn
);
997 /* Note that single_set ignores parts of a parallel set for
998 which one of the destinations is REG_UNUSED. We can't
999 handle that here, since we can wind up rewriting things
1000 such that a single register is set twice within a single
1002 if (reg_set_p (src
, insn
))
1005 /* match_no/dst must be a write-only operand, and
1006 operand_operand/src must be a read-only operand. */
1007 if (match
.use
[op_no
] != READ
1008 || match
.use
[match_no
] != WRITE
)
1011 if (match
.early_clobber
[match_no
]
1012 && count_occurrences (PATTERN (insn
), src
, 0) > 1)
1015 /* Make sure match_no is the destination. */
1016 if (recog_data
.operand
[match_no
] != SET_DEST (set
))
1019 if (REGNO (src
) < FIRST_PSEUDO_REGISTER
)
1021 if (GET_CODE (SET_SRC (set
)) == PLUS
1022 && CONST_INT_P (XEXP (SET_SRC (set
), 1))
1023 && XEXP (SET_SRC (set
), 0) == src
1024 && fixup_match_2 (insn
, dst
, src
,
1025 XEXP (SET_SRC (set
), 1)))
1029 src_class
= reg_preferred_class (REGNO (src
));
1030 dst_class
= reg_preferred_class (REGNO (dst
));
1032 if (! (src_note
= find_reg_note (insn
, REG_DEAD
, src
)))
1034 /* We used to force the copy here like in other cases, but
1035 it produces worse code, as it eliminates no copy
1036 instructions and the copy emitted will be produced by
1037 reload anyway. On patterns with multiple alternatives,
1038 there may be better solution available.
1040 In particular this change produced slower code for numeric
1046 if (! regclass_compatible_p (src_class
, dst_class
))
1056 /* Can not modify an earlier insn to set dst if this insn
1057 uses an old value in the source. */
1058 if (reg_overlap_mentioned_p (dst
, SET_SRC (set
)))
1068 /* If src is set once in a different basic block,
1069 and is set equal to a constant, then do not use
1070 it for this optimization, as this would make it
1071 no longer equivalent to a constant. */
1073 if (reg_is_remote_constant_p (src
, insn
))
1086 "Could fix operand %d of insn %d matching operand %d.\n",
1087 op_no
, INSN_UID (insn
), match_no
);
1089 /* Scan backward to find the first instruction that uses
1090 the input operand. If the operand is set here, then
1091 replace it in both instructions with match_no. */
1093 for (length
= 0, p
= PREV_INSN (insn
); p
; p
= PREV_INSN (p
))
1099 if (BLOCK_FOR_INSN (p
) != bb
)
1102 if (!DEBUG_INSN_P (p
))
1105 /* ??? See if all of SRC is set in P. This test is much
1106 more conservative than it needs to be. */
1107 pset
= single_set (p
);
1108 if (pset
&& SET_DEST (pset
) == src
)
1110 /* We use validate_replace_rtx, in case there
1111 are multiple identical source operands. All
1112 of them have to be changed at the same time:
1113 when validate_replace_rtx() calls
1114 apply_change_group(). */
1115 validate_change (p
, &SET_DEST (pset
), dst
, 1);
1116 if (validate_replace_rtx (src
, dst
, insn
))
1121 /* We can't make this change if DST is mentioned at
1122 all in P, since we are going to change its value.
1123 We can't make this change if SRC is read or
1124 partially written in P, since we are going to
1125 eliminate SRC. However, if it's a debug insn, we
1126 can't refrain from making the change, for this
1127 would cause codegen differences, so instead we
1128 invalidate debug expressions that reference DST,
1129 and adjust references to SRC in them so that they
1130 become references to DST. */
1131 if (reg_mentioned_p (dst
, PATTERN (p
)))
1133 if (DEBUG_INSN_P (p
))
1134 validate_change (p
, &INSN_VAR_LOCATION_LOC (p
),
1135 gen_rtx_UNKNOWN_VAR_LOC (), 1);
1139 if (reg_overlap_mentioned_p (src
, PATTERN (p
)))
1141 if (DEBUG_INSN_P (p
))
1142 validate_replace_rtx_group (src
, dst
, p
);
1147 /* If we have passed a call instruction, and the
1148 pseudo-reg DST is not already live across a call,
1149 then don't perform the optimization. */
1153 freq_calls
+= REG_FREQ_FROM_BB (BLOCK_FOR_INSN (p
));
1155 if (REG_N_CALLS_CROSSED (REGNO (dst
)) == 0)
1164 /* Remove the death note for SRC from INSN. */
1165 remove_note (insn
, src_note
);
1166 /* Move the death note for SRC to P if it is used
1168 if (reg_overlap_mentioned_p (src
, PATTERN (p
)))
1170 XEXP (src_note
, 1) = REG_NOTES (p
);
1171 REG_NOTES (p
) = src_note
;
1173 /* If there is a REG_DEAD note for DST on P, then remove
1174 it, because DST is now set there. */
1175 if ((dst_note
= find_reg_note (p
, REG_DEAD
, dst
)))
1176 remove_note (p
, dst_note
);
1178 dstno
= REGNO (dst
);
1179 srcno
= REGNO (src
);
1181 INC_REG_N_SETS (dstno
, 1);
1182 INC_REG_N_SETS (srcno
, -1);
1184 REG_N_CALLS_CROSSED (dstno
) += num_calls
;
1185 REG_N_CALLS_CROSSED (srcno
) -= num_calls
;
1186 REG_FREQ_CALLS_CROSSED (dstno
) += freq_calls
;
1187 REG_FREQ_CALLS_CROSSED (srcno
) -= freq_calls
;
1189 REG_LIVE_LENGTH (dstno
) += length
;
1190 if (REG_LIVE_LENGTH (srcno
) >= 0)
1192 REG_LIVE_LENGTH (srcno
) -= length
;
1193 /* REG_LIVE_LENGTH is only an approximation after
1194 combine if sched is not run, so make sure that we
1195 still have a reasonable value. */
1196 if (REG_LIVE_LENGTH (srcno
) < 2)
1197 REG_LIVE_LENGTH (srcno
) = 2;
1202 "Fixed operand %d of insn %d matching operand %d.\n",
1203 op_no
, INSN_UID (insn
), match_no
);
1207 else if (num_changes_pending () > 0)
1211 /* If we weren't able to replace any of the alternatives, try an
1212 alternative approach of copying the source to the destination. */
1213 if (!success
&& copy_src
!= NULL_RTX
)
1214 copy_src_to_dest (insn
, copy_src
, copy_dst
);
1219 /* Main entry for the register move optimization. */
1222 regmove_optimize (void)
1225 int nregs
= max_reg_num ();
1227 df_note_add_problem ();
1230 if (flag_ira_loop_pressure
)
1231 ira_set_pseudo_classes (dump_file
);
1233 regstat_init_n_sets_and_refs ();
1234 regstat_compute_ri ();
1236 regno_src_regno
= XNEWVEC (int, nregs
);
1237 for (i
= nregs
; --i
>= 0; )
1238 regno_src_regno
[i
] = -1;
1240 /* A forward pass. Replace output operands with input operands. */
1241 regmove_forward_pass ();
1243 /* A backward pass. Replace input operands with output operands. */
1244 regmove_backward_pass ();
1247 free (regno_src_regno
);
1250 free (reg_set_in_bb
);
1251 reg_set_in_bb
= NULL
;
1253 regstat_free_n_sets_and_refs ();
1255 if (flag_ira_loop_pressure
)
1260 /* Returns nonzero if INSN's pattern has matching constraints for any operand.
1261 Returns 0 if INSN can't be recognized, or if the alternative can't be
1264 Initialize the info in MATCHP based on the constraints. */
1267 find_matches (rtx insn
, struct match
*matchp
)
1269 int likely_spilled
[MAX_RECOG_OPERANDS
];
1271 int any_matches
= 0;
1273 extract_insn (insn
);
1274 if (! constrain_operands (0))
1277 /* Must initialize this before main loop, because the code for
1278 the commutative case may set matches for operands other than
1280 for (op_no
= recog_data
.n_operands
; --op_no
>= 0; )
1281 matchp
->with
[op_no
] = matchp
->commutative
[op_no
] = -1;
1283 for (op_no
= 0; op_no
< recog_data
.n_operands
; op_no
++)
1289 p
= recog_data
.constraints
[op_no
];
1291 likely_spilled
[op_no
] = 0;
1292 matchp
->use
[op_no
] = READ
;
1293 matchp
->early_clobber
[op_no
] = 0;
1295 matchp
->use
[op_no
] = WRITE
;
1297 matchp
->use
[op_no
] = READWRITE
;
1299 for (;*p
&& i
< which_alternative
; p
++)
1303 while ((c
= *p
) != '\0' && c
!= ',')
1312 matchp
->early_clobber
[op_no
] = 1;
1315 matchp
->commutative
[op_no
] = op_no
+ 1;
1316 matchp
->commutative
[op_no
+ 1] = op_no
;
1319 case '0': case '1': case '2': case '3': case '4':
1320 case '5': case '6': case '7': case '8': case '9':
1323 unsigned long match_ul
= strtoul (p
, &end
, 10);
1324 int match
= match_ul
;
1328 if (match
< op_no
&& likely_spilled
[match
])
1330 matchp
->with
[op_no
] = match
;
1332 if (matchp
->commutative
[op_no
] >= 0)
1333 matchp
->with
[matchp
->commutative
[op_no
]] = match
;
1337 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': case 'h':
1338 case 'j': case 'k': case 'l': case 'p': case 'q': case 't': case 'u':
1339 case 'v': case 'w': case 'x': case 'y': case 'z': case 'A': case 'B':
1340 case 'C': case 'D': case 'W': case 'Y': case 'Z':
1341 if (CLASS_LIKELY_SPILLED_P (REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
) ))
1342 likely_spilled
[op_no
] = 1;
1345 p
+= CONSTRAINT_LEN (c
, p
);
1354 gate_handle_regmove (void)
1356 return (optimize
> 0 && flag_regmove
);
1360 struct rtl_opt_pass pass_regmove
=
1364 "regmove", /* name */
1365 gate_handle_regmove
, /* gate */
1366 regmove_optimize
, /* execute */
1369 0, /* static_pass_number */
1370 TV_REGMOVE
, /* tv_id */
1371 0, /* properties_required */
1372 0, /* properties_provided */
1373 0, /* properties_destroyed */
1374 0, /* todo_flags_start */
1375 TODO_df_finish
| TODO_verify_rtl_sharing
|
1377 TODO_ggc_collect
/* todo_flags_finish */