gdb/aarch64-linux-nat.c

   1 /* Native-dependent code for GNU/Linux AArch64.
   2
   3    Copyright (C) 2011-2023 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22
  23 #include "inferior.h"
  24 #include "gdbcore.h"
  25 #include "regcache.h"
  26 #include "linux-nat.h"
  27 #include "target-descriptions.h"
  28 #include "auxv.h"
  29 #include "gdbcmd.h"
  30 #include "aarch64-nat.h"
  31 #include "aarch64-tdep.h"
  32 #include "aarch64-linux-tdep.h"
  33 #include "aarch32-linux-nat.h"
  34 #include "aarch32-tdep.h"
  35 #include "arch/arm.h"
  36 #include "nat/aarch64-linux.h"
  37 #include "nat/aarch64-linux-hw-point.h"
  38 #include "nat/aarch64-scalable-linux-ptrace.h"
  39
  40 #include "elf/external.h"
  41 #include "elf/common.h"
  42
  43 #include "nat/gdb_ptrace.h"
  44 #include <sys/utsname.h>
  45 #include <asm/ptrace.h>
  46
  47 #include "gregset.h"
  48 #include "linux-tdep.h"
  49 #include "arm-tdep.h"
  50
  51 /* Defines ps_err_e, struct ps_prochandle.  */
  52 #include "gdb_proc_service.h"
  53 #include "arch-utils.h"
  54
  55 #include "arch/aarch64-mte-linux.h"
  56
  57 #include "nat/aarch64-mte-linux-ptrace.h"
  58
  59 #include <string.h>
  60
  61 #ifndef TRAP_HWBKPT
  62 #define TRAP_HWBKPT 0x0004
  63 #endif
  64
  65 class aarch64_linux_nat_target final
  66   : public aarch64_nat_target<linux_nat_target>
  67 {
  68 public:
  69   /* Add our register access methods.  */
  70   void fetch_registers (struct regcache *, int) override;
  71   void store_registers (struct regcache *, int) override;
  72
  73   const struct target_desc *read_description () override;
  74
  75   /* Add our hardware breakpoint and watchpoint implementation.  */
  76   bool stopped_by_watchpoint () override;
  77   bool stopped_data_address (CORE_ADDR *) override;
  78
  79   int can_do_single_step () override;
  80
  81   /* Override the GNU/Linux inferior startup hook.  */
  82   void post_startup_inferior (ptid_t) override;
  83
  84   /* Override the GNU/Linux post attach hook.  */
  85   void post_attach (int pid) override;
  86
  87   /* These three defer to common nat/ code.  */
  88   void low_new_thread (struct lwp_info *lp) override
  89   { aarch64_linux_new_thread (lp); }
  90   void low_delete_thread (struct arch_lwp_info *lp) override
  91   { aarch64_linux_delete_thread (lp); }
  92   void low_prepare_to_resume (struct lwp_info *lp) override
  93   { aarch64_linux_prepare_to_resume (lp); }
  94
  95   void low_new_fork (struct lwp_info *parent, pid_t child_pid) override;
  96   void low_forget_process (pid_t pid) override;
  97
  98   /* Add our siginfo layout converter.  */
  99   bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
 100     override;
 101
 102   struct gdbarch *thread_architecture (ptid_t) override;
 103
 104   bool supports_memory_tagging () override;
 105
 106   /* Read memory allocation tags from memory via PTRACE.  */
 107   bool fetch_memtags (CORE_ADDR address, size_t len,
 108                       gdb::byte_vector &tags, int type) override;
 109
 110   /* Write allocation tags to memory via PTRACE.  */
 111   bool store_memtags (CORE_ADDR address, size_t len,
 112                       const gdb::byte_vector &tags, int type) override;
 113 };
 114
 115 static aarch64_linux_nat_target the_aarch64_linux_nat_target;
 116
 117 /* Called whenever GDB is no longer debugging process PID.  It deletes
 118    data structures that keep track of debug register state.  */
 119
 120 void
 121 aarch64_linux_nat_target::low_forget_process (pid_t pid)
 122 {
 123   aarch64_remove_debug_reg_state (pid);
 124 }
 125
 126 /* Fill GDB's register array with the general-purpose register values
 127    from the current thread.  */
 128
 129 static void
 130 fetch_gregs_from_thread (struct regcache *regcache)
 131 {
 132   int ret, tid;
 133   struct gdbarch *gdbarch = regcache->arch ();
 134   elf_gregset_t regs;
 135   struct iovec iovec;
 136
 137   /* Make sure REGS can hold all registers contents on both aarch64
 138      and arm.  */
 139   gdb_static_assert (sizeof (regs) >= 18 * 4);
 140
 141   tid = regcache->ptid ().lwp ();
 142
 143   iovec.iov_base = &regs;
 144   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 145     iovec.iov_len = 18 * 4;
 146   else
 147     iovec.iov_len = sizeof (regs);
 148
 149   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
 150   if (ret < 0)
 151     perror_with_name (_("Unable to fetch general registers"));
 152
 153   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 154     aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1);
 155   else
 156     {
 157       int regno;
 158
 159       for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
 160         regcache->raw_supply (regno, &regs[regno - AARCH64_X0_REGNUM]);
 161     }
 162 }
 163
 164 /* Store to the current thread the valid general-purpose register
 165    values in the GDB's register array.  */
 166
 167 static void
 168 store_gregs_to_thread (const struct regcache *regcache)
 169 {
 170   int ret, tid;
 171   elf_gregset_t regs;
 172   struct iovec iovec;
 173   struct gdbarch *gdbarch = regcache->arch ();
 174
 175   /* Make sure REGS can hold all registers contents on both aarch64
 176      and arm.  */
 177   gdb_static_assert (sizeof (regs) >= 18 * 4);
 178   tid = regcache->ptid ().lwp ();
 179
 180   iovec.iov_base = &regs;
 181   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 182     iovec.iov_len = 18 * 4;
 183   else
 184     iovec.iov_len = sizeof (regs);
 185
 186   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
 187   if (ret < 0)
 188     perror_with_name (_("Unable to fetch general registers"));
 189
 190   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 191     aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1);
 192   else
 193     {
 194       int regno;
 195
 196       for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
 197         if (REG_VALID == regcache->get_register_status (regno))
 198           regcache->raw_collect (regno, &regs[regno - AARCH64_X0_REGNUM]);
 199     }
 200
 201   ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
 202   if (ret < 0)
 203     perror_with_name (_("Unable to store general registers"));
 204 }
 205
 206 /* Fill GDB's register array with the fp/simd register values
 207    from the current thread.  */
 208
 209 static void
 210 fetch_fpregs_from_thread (struct regcache *regcache)
 211 {
 212   int ret, tid;
 213   elf_fpregset_t regs;
 214   struct iovec iovec;
 215   struct gdbarch *gdbarch = regcache->arch ();
 216
 217   /* Make sure REGS can hold all VFP registers contents on both aarch64
 218      and arm.  */
 219   gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
 220
 221   tid = regcache->ptid ().lwp ();
 222
 223   iovec.iov_base = &regs;
 224
 225   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 226     {
 227       iovec.iov_len = ARM_VFP3_REGS_SIZE;
 228
 229       ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 230       if (ret < 0)
 231         perror_with_name (_("Unable to fetch VFP registers"));
 232
 233       aarch32_vfp_regcache_supply (regcache, (gdb_byte *) &regs, 32);
 234     }
 235   else
 236     {
 237       int regno;
 238
 239       iovec.iov_len = sizeof (regs);
 240
 241       ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
 242       if (ret < 0)
 243         perror_with_name (_("Unable to fetch vFP/SIMD registers"));
 244
 245       for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
 246         regcache->raw_supply (regno, &regs.vregs[regno - AARCH64_V0_REGNUM]);
 247
 248       regcache->raw_supply (AARCH64_FPSR_REGNUM, &regs.fpsr);
 249       regcache->raw_supply (AARCH64_FPCR_REGNUM, &regs.fpcr);
 250     }
 251 }
 252
 253 /* Store to the current thread the valid fp/simd register
 254    values in the GDB's register array.  */
 255
 256 static void
 257 store_fpregs_to_thread (const struct regcache *regcache)
 258 {
 259   int ret, tid;
 260   elf_fpregset_t regs;
 261   struct iovec iovec;
 262   struct gdbarch *gdbarch = regcache->arch ();
 263
 264   /* Make sure REGS can hold all VFP registers contents on both aarch64
 265      and arm.  */
 266   gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
 267   tid = regcache->ptid ().lwp ();
 268
 269   iovec.iov_base = &regs;
 270
 271   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 272     {
 273       iovec.iov_len = ARM_VFP3_REGS_SIZE;
 274
 275       ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 276       if (ret < 0)
 277         perror_with_name (_("Unable to fetch VFP registers"));
 278
 279       aarch32_vfp_regcache_collect (regcache, (gdb_byte *) &regs, 32);
 280     }
 281   else
 282     {
 283       int regno;
 284
 285       iovec.iov_len = sizeof (regs);
 286
 287       ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
 288       if (ret < 0)
 289         perror_with_name (_("Unable to fetch FP/SIMD registers"));
 290
 291       for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
 292         if (REG_VALID == regcache->get_register_status (regno))
 293           regcache->raw_collect
 294             (regno, (char *) &regs.vregs[regno - AARCH64_V0_REGNUM]);
 295
 296       if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM))
 297         regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) &regs.fpsr);
 298       if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM))
 299         regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) &regs.fpcr);
 300     }
 301
 302   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 303     {
 304       ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec);
 305       if (ret < 0)
 306         perror_with_name (_("Unable to store VFP registers"));
 307     }
 308   else
 309     {
 310       ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
 311       if (ret < 0)
 312         perror_with_name (_("Unable to store FP/SIMD registers"));
 313     }
 314 }
 315
 316 /* Fill GDB's register array with the sve register values
 317    from the current thread.  */
 318
 319 static void
 320 fetch_sveregs_from_thread (struct regcache *regcache)
 321 {
 322   /* Fetch SVE state from the thread and copy it into the register cache.  */
 323   aarch64_sve_regs_copy_to_reg_buf (regcache->ptid ().lwp (), regcache);
 324 }
 325
 326 /* Store to the current thread the valid sve register
 327    values in the GDB's register array.  */
 328
 329 static void
 330 store_sveregs_to_thread (struct regcache *regcache)
 331 {
 332   /* Fetch SVE state from the register cache and update the thread TID with
 333      it.  */
 334   aarch64_sve_regs_copy_from_reg_buf (regcache->ptid ().lwp (), regcache);
 335 }
 336
 337 /* Fill GDB's register array with the pointer authentication mask values from
 338    the current thread.  */
 339
 340 static void
 341 fetch_pauth_masks_from_thread (struct regcache *regcache)
 342 {
 343   aarch64_gdbarch_tdep *tdep
 344     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 345   int ret;
 346   struct iovec iovec;
 347   uint64_t pauth_regset[2] = {0, 0};
 348   int tid = regcache->ptid ().lwp ();
 349
 350   iovec.iov_base = &pauth_regset;
 351   iovec.iov_len = sizeof (pauth_regset);
 352
 353   ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec);
 354   if (ret != 0)
 355     perror_with_name (_("unable to fetch pauth registers"));
 356
 357   regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base),
 358                         &pauth_regset[0]);
 359   regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base),
 360                         &pauth_regset[1]);
 361 }
 362
 363 /* Fill GDB's register array with the MTE register values from
 364    the current thread.  */
 365
 366 static void
 367 fetch_mteregs_from_thread (struct regcache *regcache)
 368 {
 369   aarch64_gdbarch_tdep *tdep
 370     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 371   int regno = tdep->mte_reg_base;
 372
 373   gdb_assert (regno != -1);
 374
 375   uint64_t tag_ctl = 0;
 376   struct iovec iovec;
 377
 378   iovec.iov_base = &tag_ctl;
 379   iovec.iov_len = sizeof (tag_ctl);
 380
 381   int tid = get_ptrace_pid (regcache->ptid ());
 382   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
 383       perror_with_name (_("unable to fetch MTE registers"));
 384
 385   regcache->raw_supply (regno, &tag_ctl);
 386 }
 387
 388 /* Store to the current thread the valid MTE register set in the GDB's
 389    register array.  */
 390
 391 static void
 392 store_mteregs_to_thread (struct regcache *regcache)
 393 {
 394   aarch64_gdbarch_tdep *tdep
 395     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 396   int regno = tdep->mte_reg_base;
 397
 398   gdb_assert (regno != -1);
 399
 400   uint64_t tag_ctl = 0;
 401
 402   if (REG_VALID != regcache->get_register_status (regno))
 403     return;
 404
 405   regcache->raw_collect (regno, (char *) &tag_ctl);
 406
 407   struct iovec iovec;
 408
 409   iovec.iov_base = &tag_ctl;
 410   iovec.iov_len = sizeof (tag_ctl);
 411
 412   int tid = get_ptrace_pid (regcache->ptid ());
 413   if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
 414     perror_with_name (_("unable to store MTE registers"));
 415 }
 416
 417 /* Fill GDB's register array with the TLS register values from
 418    the current thread.  */
 419
 420 static void
 421 fetch_tlsregs_from_thread (struct regcache *regcache)
 422 {
 423   aarch64_gdbarch_tdep *tdep
 424     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 425   int regno = tdep->tls_regnum_base;
 426
 427   gdb_assert (regno != -1);
 428   gdb_assert (tdep->tls_register_count > 0);
 429
 430   uint64_t tpidrs[tdep->tls_register_count];
 431   memset(tpidrs, 0, sizeof(tpidrs));
 432
 433   struct iovec iovec;
 434   iovec.iov_base = tpidrs;
 435   iovec.iov_len = sizeof (tpidrs);
 436
 437   int tid = get_ptrace_pid (regcache->ptid ());
 438   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
 439       perror_with_name (_("unable to fetch TLS registers"));
 440
 441   for (int i = 0; i < tdep->tls_register_count; i++)
 442     regcache->raw_supply (regno + i, &tpidrs[i]);
 443 }
 444
 445 /* Store to the current thread the valid TLS register set in GDB's
 446    register array.  */
 447
 448 static void
 449 store_tlsregs_to_thread (struct regcache *regcache)
 450 {
 451   aarch64_gdbarch_tdep *tdep
 452     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 453   int regno = tdep->tls_regnum_base;
 454
 455   gdb_assert (regno != -1);
 456   gdb_assert (tdep->tls_register_count > 0);
 457
 458   uint64_t tpidrs[tdep->tls_register_count];
 459   memset(tpidrs, 0, sizeof(tpidrs));
 460
 461   for (int i = 0; i < tdep->tls_register_count; i++)
 462     {
 463       if (REG_VALID != regcache->get_register_status (regno + i))
 464         continue;
 465
 466       regcache->raw_collect (regno + i, (char *) &tpidrs[i]);
 467     }
 468
 469   struct iovec iovec;
 470   iovec.iov_base = &tpidrs;
 471   iovec.iov_len = sizeof (tpidrs);
 472
 473   int tid = get_ptrace_pid (regcache->ptid ());
 474   if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
 475     perror_with_name (_("unable to store TLS register"));
 476 }
 477
 478 /* The AArch64 version of the "fetch_registers" target_ops method.  Fetch
 479    REGNO from the target and place the result into REGCACHE.  */
 480
 481 static void
 482 aarch64_fetch_registers (struct regcache *regcache, int regno)
 483 {
 484   aarch64_gdbarch_tdep *tdep
 485     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 486
 487   /* Do we need to fetch all registers?  */
 488   if (regno == -1)
 489     {
 490       fetch_gregs_from_thread (regcache);
 491       if (tdep->has_sve ())
 492         fetch_sveregs_from_thread (regcache);
 493       else
 494         fetch_fpregs_from_thread (regcache);
 495
 496       if (tdep->has_pauth ())
 497         fetch_pauth_masks_from_thread (regcache);
 498
 499       if (tdep->has_mte ())
 500         fetch_mteregs_from_thread (regcache);
 501
 502       if (tdep->has_tls ())
 503         fetch_tlsregs_from_thread (regcache);
 504     }
 505   /* General purpose register?  */
 506   else if (regno < AARCH64_V0_REGNUM)
 507     fetch_gregs_from_thread (regcache);
 508   /* SVE register?  */
 509   else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM)
 510     fetch_sveregs_from_thread (regcache);
 511   /* FPSIMD register?  */
 512   else if (regno <= AARCH64_FPCR_REGNUM)
 513     fetch_fpregs_from_thread (regcache);
 514   /* PAuth register?  */
 515   else if (tdep->has_pauth ()
 516            && (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
 517                || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)))
 518     fetch_pauth_masks_from_thread (regcache);
 519   /* MTE register?  */
 520   else if (tdep->has_mte ()
 521            && (regno == tdep->mte_reg_base))
 522     fetch_mteregs_from_thread (regcache);
 523   /* TLS register?  */
 524   else if (tdep->has_tls ()
 525            && regno >= tdep->tls_regnum_base
 526            && regno < tdep->tls_regnum_base + tdep->tls_register_count)
 527     fetch_tlsregs_from_thread (regcache);
 528 }
 529
 530 /* A version of the "fetch_registers" target_ops method used when running
 531    32-bit ARM code on an AArch64 target.  Fetch REGNO from the target and
 532    place the result into REGCACHE.  */
 533
 534 static void
 535 aarch32_fetch_registers (struct regcache *regcache, int regno)
 536 {
 537   arm_gdbarch_tdep *tdep
 538     = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ());
 539
 540   if (regno == -1)
 541     {
 542       fetch_gregs_from_thread (regcache);
 543       if (tdep->vfp_register_count > 0)
 544         fetch_fpregs_from_thread (regcache);
 545     }
 546   else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
 547     fetch_gregs_from_thread (regcache);
 548   else if (tdep->vfp_register_count > 0
 549            && regno >= ARM_D0_REGNUM
 550            && (regno < ARM_D0_REGNUM + tdep->vfp_register_count
 551                || regno == ARM_FPSCR_REGNUM))
 552     fetch_fpregs_from_thread (regcache);
 553 }
 554
 555 /* Implement the "fetch_registers" target_ops method.  */
 556
 557 void
 558 aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
 559                                            int regno)
 560 {
 561   if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
 562     aarch32_fetch_registers (regcache, regno);
 563   else
 564     aarch64_fetch_registers (regcache, regno);
 565 }
 566
 567 /* The AArch64 version of the "store_registers" target_ops method.  Copy
 568    the value of register REGNO from REGCACHE into the the target.  */
 569
 570 static void
 571 aarch64_store_registers (struct regcache *regcache, int regno)
 572 {
 573   aarch64_gdbarch_tdep *tdep
 574     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 575
 576   /* Do we need to store all registers?  */
 577   if (regno == -1)
 578     {
 579       store_gregs_to_thread (regcache);
 580       if (tdep->has_sve ())
 581         store_sveregs_to_thread (regcache);
 582       else
 583         store_fpregs_to_thread (regcache);
 584
 585       if (tdep->has_mte ())
 586         store_mteregs_to_thread (regcache);
 587
 588       if (tdep->has_tls ())
 589         store_tlsregs_to_thread (regcache);
 590     }
 591   /* General purpose register?  */
 592   else if (regno < AARCH64_V0_REGNUM)
 593     store_gregs_to_thread (regcache);
 594   /* SVE register?  */
 595   else if (tdep->has_sve () && regno <= AARCH64_SVE_VG_REGNUM)
 596     store_sveregs_to_thread (regcache);
 597   /* FPSIMD register?  */
 598   else if (regno <= AARCH64_FPCR_REGNUM)
 599     store_fpregs_to_thread (regcache);
 600   /* MTE register?  */
 601   else if (tdep->has_mte ()
 602            && (regno == tdep->mte_reg_base))
 603     store_mteregs_to_thread (regcache);
 604   /* TLS register?  */
 605   else if (tdep->has_tls ()
 606            && regno >= tdep->tls_regnum_base
 607            && regno < tdep->tls_regnum_base + tdep->tls_register_count)
 608     store_tlsregs_to_thread (regcache);
 609
 610   /* PAuth registers are read-only.  */
 611 }
 612
 613 /* A version of the "store_registers" target_ops method used when running
 614    32-bit ARM code on an AArch64 target.  Copy the value of register REGNO
 615    from REGCACHE into the the target.  */
 616
 617 static void
 618 aarch32_store_registers (struct regcache *regcache, int regno)
 619 {
 620   arm_gdbarch_tdep *tdep
 621     = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ());
 622
 623   if (regno == -1)
 624     {
 625       store_gregs_to_thread (regcache);
 626       if (tdep->vfp_register_count > 0)
 627         store_fpregs_to_thread (regcache);
 628     }
 629   else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
 630     store_gregs_to_thread (regcache);
 631   else if (tdep->vfp_register_count > 0
 632            && regno >= ARM_D0_REGNUM
 633            && (regno < ARM_D0_REGNUM + tdep->vfp_register_count
 634                || regno == ARM_FPSCR_REGNUM))
 635     store_fpregs_to_thread (regcache);
 636 }
 637
 638 /* Implement the "store_registers" target_ops method.  */
 639
 640 void
 641 aarch64_linux_nat_target::store_registers (struct regcache *regcache,
 642                                            int regno)
 643 {
 644   if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
 645     aarch32_store_registers (regcache, regno);
 646   else
 647     aarch64_store_registers (regcache, regno);
 648 }
 649
 650 /* Fill register REGNO (if it is a general-purpose register) in
 651    *GREGSETPS with the value in GDB's register array.  If REGNO is -1,
 652    do this for all registers.  */
 653
 654 void
 655 fill_gregset (const struct regcache *regcache,
 656               gdb_gregset_t *gregsetp, int regno)
 657 {
 658   regcache_collect_regset (&aarch64_linux_gregset, regcache,
 659                            regno, (gdb_byte *) gregsetp,
 660                            AARCH64_LINUX_SIZEOF_GREGSET);
 661 }
 662
 663 /* Fill GDB's register array with the general-purpose register values
 664    in *GREGSETP.  */
 665
 666 void
 667 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
 668 {
 669   regcache_supply_regset (&aarch64_linux_gregset, regcache, -1,
 670                           (const gdb_byte *) gregsetp,
 671                           AARCH64_LINUX_SIZEOF_GREGSET);
 672 }
 673
 674 /* Fill register REGNO (if it is a floating-point register) in
 675    *FPREGSETP with the value in GDB's register array.  If REGNO is -1,
 676    do this for all registers.  */
 677
 678 void
 679 fill_fpregset (const struct regcache *regcache,
 680                gdb_fpregset_t *fpregsetp, int regno)
 681 {
 682   regcache_collect_regset (&aarch64_linux_fpregset, regcache,
 683                            regno, (gdb_byte *) fpregsetp,
 684                            AARCH64_LINUX_SIZEOF_FPREGSET);
 685 }
 686
 687 /* Fill GDB's register array with the floating-point register values
 688    in *FPREGSETP.  */
 689
 690 void
 691 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
 692 {
 693   regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1,
 694                           (const gdb_byte *) fpregsetp,
 695                           AARCH64_LINUX_SIZEOF_FPREGSET);
 696 }
 697
 698 /* linux_nat_new_fork hook.   */
 699
 700 void
 701 aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent,
 702                                         pid_t child_pid)
 703 {
 704   pid_t parent_pid;
 705   struct aarch64_debug_reg_state *parent_state;
 706   struct aarch64_debug_reg_state *child_state;
 707
 708   /* NULL means no watchpoint has ever been set in the parent.  In
 709      that case, there's nothing to do.  */
 710   if (parent->arch_private == NULL)
 711     return;
 712
 713   /* GDB core assumes the child inherits the watchpoints/hw
 714      breakpoints of the parent, and will remove them all from the
 715      forked off process.  Copy the debug registers mirrors into the
 716      new process so that all breakpoints and watchpoints can be
 717      removed together.  */
 718
 719   parent_pid = parent->ptid.pid ();
 720   parent_state = aarch64_get_debug_reg_state (parent_pid);
 721   child_state = aarch64_get_debug_reg_state (child_pid);
 722   *child_state = *parent_state;
 723 }
 724 \f
 725
 726 /* Called by libthread_db.  Returns a pointer to the thread local
 727    storage (or its descriptor).  */
 728
 729 ps_err_e
 730 ps_get_thread_area (struct ps_prochandle *ph,
 731                     lwpid_t lwpid, int idx, void **base)
 732 {
 733   int is_64bit_p
 734     = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64);
 735
 736   return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p);
 737 }
 738 \f
 739
 740 /* Implement the virtual inf_ptrace_target::post_startup_inferior method.  */
 741
 742 void
 743 aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid)
 744 {
 745   low_forget_process (ptid.pid ());
 746   aarch64_linux_get_debug_reg_capacity (ptid.pid ());
 747   linux_nat_target::post_startup_inferior (ptid);
 748 }
 749
 750 /* Implement the "post_attach" target_ops method.  */
 751
 752 void
 753 aarch64_linux_nat_target::post_attach (int pid)
 754 {
 755   low_forget_process (pid);
 756   /* Set the hardware debug register capacity.  If
 757      aarch64_linux_get_debug_reg_capacity is not called
 758      (as it is in aarch64_linux_child_post_startup_inferior) then
 759      software watchpoints will be used instead of hardware
 760      watchpoints when attaching to a target.  */
 761   aarch64_linux_get_debug_reg_capacity (pid);
 762   linux_nat_target::post_attach (pid);
 763 }
 764
 765 /* Implement the "read_description" target_ops method.  */
 766
 767 const struct target_desc *
 768 aarch64_linux_nat_target::read_description ()
 769 {
 770   int ret, tid;
 771   gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
 772   struct iovec iovec;
 773
 774   if (inferior_ptid == null_ptid)
 775     return this->beneath ()->read_description ();
 776
 777   tid = inferior_ptid.pid ();
 778
 779   iovec.iov_base = regbuf;
 780   iovec.iov_len = ARM_VFP3_REGS_SIZE;
 781
 782   ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 783   if (ret == 0)
 784     return aarch32_read_description ();
 785
 786   CORE_ADDR hwcap = linux_get_hwcap ();
 787   CORE_ADDR hwcap2 = linux_get_hwcap2 ();
 788
 789   aarch64_features features;
 790   features.vq = aarch64_sve_get_vq (tid);
 791   features.pauth = hwcap & AARCH64_HWCAP_PACA;
 792   features.mte = hwcap2 & HWCAP2_MTE;
 793   features.tls = aarch64_tls_register_count (tid);
 794
 795   return aarch64_read_description (features);
 796 }
 797
 798 /* Convert a native/host siginfo object, into/from the siginfo in the
 799    layout of the inferiors' architecture.  Returns true if any
 800    conversion was done; false otherwise.  If DIRECTION is 1, then copy
 801    from INF to NATIVE.  If DIRECTION is 0, copy from NATIVE to
 802    INF.  */
 803
 804 bool
 805 aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf,
 806                                              int direction)
 807 {
 808   struct gdbarch *gdbarch = get_frame_arch (get_current_frame ());
 809
 810   /* Is the inferior 32-bit?  If so, then do fixup the siginfo
 811      object.  */
 812   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 813     {
 814       if (direction == 0)
 815         aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf,
 816                                              native);
 817       else
 818         aarch64_siginfo_from_compat_siginfo (native,
 819                                              (struct compat_siginfo *) inf);
 820
 821       return true;
 822     }
 823
 824   return false;
 825 }
 826
 827 /* Implement the "stopped_data_address" target_ops method.  */
 828
 829 bool
 830 aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
 831 {
 832   siginfo_t siginfo;
 833   struct aarch64_debug_reg_state *state;
 834
 835   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
 836     return false;
 837
 838   /* This must be a hardware breakpoint.  */
 839   if (siginfo.si_signo != SIGTRAP
 840       || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
 841     return false;
 842
 843   /* Make sure to ignore the top byte, otherwise we may not recognize a
 844      hardware watchpoint hit.  The stopped data addresses coming from the
 845      kernel can potentially be tagged addresses.  */
 846   struct gdbarch *gdbarch = thread_architecture (inferior_ptid);
 847   const CORE_ADDR addr_trap
 848     = gdbarch_remove_non_address_bits (gdbarch, (CORE_ADDR) siginfo.si_addr);
 849
 850   /* Check if the address matches any watched address.  */
 851   state = aarch64_get_debug_reg_state (inferior_ptid.pid ());
 852   return aarch64_stopped_data_address (state, addr_trap, addr_p);
 853 }
 854
 855 /* Implement the "stopped_by_watchpoint" target_ops method.  */
 856
 857 bool
 858 aarch64_linux_nat_target::stopped_by_watchpoint ()
 859 {
 860   CORE_ADDR addr;
 861
 862   return stopped_data_address (&addr);
 863 }
 864
 865 /* Implement the "can_do_single_step" target_ops method.  */
 866
 867 int
 868 aarch64_linux_nat_target::can_do_single_step ()
 869 {
 870   return 1;
 871 }
 872
 873 /* Implement the "thread_architecture" target_ops method.
 874
 875    Returns the gdbarch for the thread identified by PTID.  If the thread in
 876    question is a 32-bit ARM thread, then the architecture returned will be
 877    that of the process itself.
 878
 879    If the thread is an AArch64 thread then we need to check the current
 880    vector length; if the vector length has changed then we need to lookup a
 881    new gdbarch that matches the new vector length.  */
 882
 883 struct gdbarch *
 884 aarch64_linux_nat_target::thread_architecture (ptid_t ptid)
 885 {
 886   /* Find the current gdbarch the same way as process_stratum_target.  */
 887   inferior *inf = find_inferior_ptid (this, ptid);
 888   gdb_assert (inf != NULL);
 889
 890   /* If this is a 32-bit architecture, then this is ARM, not AArch64.
 891      There's no SVE vectors here, so just return the inferior
 892      architecture.  */
 893   if (gdbarch_bfd_arch_info (inf->gdbarch)->bits_per_word == 32)
 894     return inf->gdbarch;
 895
 896   /* Only return it if the current vector length matches the one in the tdep.  */
 897   aarch64_gdbarch_tdep *tdep
 898     = gdbarch_tdep<aarch64_gdbarch_tdep> (inf->gdbarch);
 899   uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
 900   if (vq == tdep->vq)
 901     return inf->gdbarch;
 902
 903   /* We reach here if the vector length for the thread is different from its
 904      value at process start.  Lookup gdbarch via info (potentially creating a
 905      new one) by using a target description that corresponds to the new vq value
 906      and the current architecture features.  */
 907
 908   const struct target_desc *tdesc = gdbarch_target_desc (inf->gdbarch);
 909   aarch64_features features = aarch64_features_from_target_desc (tdesc);
 910   features.vq = vq;
 911
 912   struct gdbarch_info info;
 913   info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
 914   info.target_desc = aarch64_read_description (features);
 915   return gdbarch_find_by_info (info);
 916 }
 917
 918 /* Implement the "supports_memory_tagging" target_ops method.  */
 919
 920 bool
 921 aarch64_linux_nat_target::supports_memory_tagging ()
 922 {
 923   return (linux_get_hwcap2 () & HWCAP2_MTE) != 0;
 924 }
 925
 926 /* Implement the "fetch_memtags" target_ops method.  */
 927
 928 bool
 929 aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address, size_t len,
 930                                          gdb::byte_vector &tags, int type)
 931 {
 932   int tid = get_ptrace_pid (inferior_ptid);
 933
 934   /* Allocation tags?  */
 935   if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
 936     return aarch64_mte_fetch_memtags (tid, address, len, tags);
 937
 938   return false;
 939 }
 940
 941 /* Implement the "store_memtags" target_ops method.  */
 942
 943 bool
 944 aarch64_linux_nat_target::store_memtags (CORE_ADDR address, size_t len,
 945                                          const gdb::byte_vector &tags, int type)
 946 {
 947   int tid = get_ptrace_pid (inferior_ptid);
 948
 949   /* Allocation tags?  */
 950   if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
 951     return aarch64_mte_store_memtags (tid, address, len, tags);
 952
 953   return false;
 954 }
 955
 956 void _initialize_aarch64_linux_nat ();
 957 void
 958 _initialize_aarch64_linux_nat ()
 959 {
 960   aarch64_initialize_hw_point ();
 961
 962   /* Register the target.  */
 963   linux_target = &the_aarch64_linux_nat_target;
 964   add_inf_child_target (&the_aarch64_linux_nat_target);
 965 }