1 /* Common target dependent code for GDB on AArch64 systems.
3 Copyright (C) 2009-2021 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
28 #include "reggroups.h"
30 #include "arch-utils.h"
32 #include "frame-unwind.h"
33 #include "frame-base.h"
34 #include "trad-frame.h"
37 #include "dwarf2/frame.h"
39 #include "prologue-value.h"
40 #include "target-descriptions.h"
41 #include "user-regs.h"
43 #include "gdbsupport/selftest.h"
45 #include "aarch64-tdep.h"
46 #include "aarch64-ravenscar-thread.h"
49 #include "record-full.h"
50 #include "arch/aarch64-insn.h"
53 #include "opcode/aarch64.h"
56 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most
58 #define HA_MAX_NUM_FLDS 4
60 /* All possible aarch64 target descriptors. */
61 static target_desc
*tdesc_aarch64_list
[AARCH64_MAX_SVE_VQ
+ 1][2/*pauth*/][2 /* mte */];
63 /* The standard register names, and all the valid aliases for them. */
66 const char *const name
;
68 } aarch64_register_aliases
[] =
70 /* 64-bit register names. */
71 {"fp", AARCH64_FP_REGNUM
},
72 {"lr", AARCH64_LR_REGNUM
},
73 {"sp", AARCH64_SP_REGNUM
},
75 /* 32-bit register names. */
76 {"w0", AARCH64_X0_REGNUM
+ 0},
77 {"w1", AARCH64_X0_REGNUM
+ 1},
78 {"w2", AARCH64_X0_REGNUM
+ 2},
79 {"w3", AARCH64_X0_REGNUM
+ 3},
80 {"w4", AARCH64_X0_REGNUM
+ 4},
81 {"w5", AARCH64_X0_REGNUM
+ 5},
82 {"w6", AARCH64_X0_REGNUM
+ 6},
83 {"w7", AARCH64_X0_REGNUM
+ 7},
84 {"w8", AARCH64_X0_REGNUM
+ 8},
85 {"w9", AARCH64_X0_REGNUM
+ 9},
86 {"w10", AARCH64_X0_REGNUM
+ 10},
87 {"w11", AARCH64_X0_REGNUM
+ 11},
88 {"w12", AARCH64_X0_REGNUM
+ 12},
89 {"w13", AARCH64_X0_REGNUM
+ 13},
90 {"w14", AARCH64_X0_REGNUM
+ 14},
91 {"w15", AARCH64_X0_REGNUM
+ 15},
92 {"w16", AARCH64_X0_REGNUM
+ 16},
93 {"w17", AARCH64_X0_REGNUM
+ 17},
94 {"w18", AARCH64_X0_REGNUM
+ 18},
95 {"w19", AARCH64_X0_REGNUM
+ 19},
96 {"w20", AARCH64_X0_REGNUM
+ 20},
97 {"w21", AARCH64_X0_REGNUM
+ 21},
98 {"w22", AARCH64_X0_REGNUM
+ 22},
99 {"w23", AARCH64_X0_REGNUM
+ 23},
100 {"w24", AARCH64_X0_REGNUM
+ 24},
101 {"w25", AARCH64_X0_REGNUM
+ 25},
102 {"w26", AARCH64_X0_REGNUM
+ 26},
103 {"w27", AARCH64_X0_REGNUM
+ 27},
104 {"w28", AARCH64_X0_REGNUM
+ 28},
105 {"w29", AARCH64_X0_REGNUM
+ 29},
106 {"w30", AARCH64_X0_REGNUM
+ 30},
109 {"ip0", AARCH64_X0_REGNUM
+ 16},
110 {"ip1", AARCH64_X0_REGNUM
+ 17}
113 /* The required core 'R' registers. */
114 static const char *const aarch64_r_register_names
[] =
116 /* These registers must appear in consecutive RAW register number
117 order and they must begin with AARCH64_X0_REGNUM! */
118 "x0", "x1", "x2", "x3",
119 "x4", "x5", "x6", "x7",
120 "x8", "x9", "x10", "x11",
121 "x12", "x13", "x14", "x15",
122 "x16", "x17", "x18", "x19",
123 "x20", "x21", "x22", "x23",
124 "x24", "x25", "x26", "x27",
125 "x28", "x29", "x30", "sp",
129 /* The FP/SIMD 'V' registers. */
130 static const char *const aarch64_v_register_names
[] =
132 /* These registers must appear in consecutive RAW register number
133 order and they must begin with AARCH64_V0_REGNUM! */
134 "v0", "v1", "v2", "v3",
135 "v4", "v5", "v6", "v7",
136 "v8", "v9", "v10", "v11",
137 "v12", "v13", "v14", "v15",
138 "v16", "v17", "v18", "v19",
139 "v20", "v21", "v22", "v23",
140 "v24", "v25", "v26", "v27",
141 "v28", "v29", "v30", "v31",
146 /* The SVE 'Z' and 'P' registers. */
147 static const char *const aarch64_sve_register_names
[] =
149 /* These registers must appear in consecutive RAW register number
150 order and they must begin with AARCH64_SVE_Z0_REGNUM! */
151 "z0", "z1", "z2", "z3",
152 "z4", "z5", "z6", "z7",
153 "z8", "z9", "z10", "z11",
154 "z12", "z13", "z14", "z15",
155 "z16", "z17", "z18", "z19",
156 "z20", "z21", "z22", "z23",
157 "z24", "z25", "z26", "z27",
158 "z28", "z29", "z30", "z31",
160 "p0", "p1", "p2", "p3",
161 "p4", "p5", "p6", "p7",
162 "p8", "p9", "p10", "p11",
163 "p12", "p13", "p14", "p15",
167 static const char *const aarch64_pauth_register_names
[] =
169 /* Authentication mask for data pointer. */
171 /* Authentication mask for code pointer. */
175 static const char *const aarch64_mte_register_names
[] =
177 /* Tag Control Register. */
181 /* AArch64 prologue cache structure. */
182 struct aarch64_prologue_cache
184 /* The program counter at the start of the function. It is used to
185 identify this frame as a prologue frame. */
188 /* The program counter at the time this frame was created; i.e. where
189 this function was called from. It is used to identify this frame as a
193 /* The stack pointer at the time this frame was created; i.e. the
194 caller's stack pointer when this function was called. It is used
195 to identify this frame. */
198 /* Is the target available to read from? */
201 /* The frame base for this frame is just prev_sp - frame size.
202 FRAMESIZE is the distance from the frame pointer to the
203 initial stack pointer. */
206 /* The register used to hold the frame pointer for this frame. */
209 /* Saved register offsets. */
210 trad_frame_saved_reg
*saved_regs
;
214 show_aarch64_debug (struct ui_file
*file
, int from_tty
,
215 struct cmd_list_element
*c
, const char *value
)
217 fprintf_filtered (file
, _("AArch64 debugging is %s.\n"), value
);
222 /* Abstract instruction reader. */
224 class abstract_instruction_reader
227 /* Read in one instruction. */
228 virtual ULONGEST
read (CORE_ADDR memaddr
, int len
,
229 enum bfd_endian byte_order
) = 0;
232 /* Instruction reader from real target. */
234 class instruction_reader
: public abstract_instruction_reader
237 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
240 return read_code_unsigned_integer (memaddr
, len
, byte_order
);
246 /* If address signing is enabled, mask off the signature bits from the link
247 register, which is passed by value in ADDR, using the register values in
251 aarch64_frame_unmask_lr (struct gdbarch_tdep
*tdep
,
252 struct frame_info
*this_frame
, CORE_ADDR addr
)
254 if (tdep
->has_pauth ()
255 && frame_unwind_register_unsigned (this_frame
,
256 tdep
->pauth_ra_state_regnum
))
258 int cmask_num
= AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
);
259 CORE_ADDR cmask
= frame_unwind_register_unsigned (this_frame
, cmask_num
);
260 addr
= addr
& ~cmask
;
262 /* Record in the frame that the link register required unmasking. */
263 set_frame_previous_pc_masked (this_frame
);
269 /* Implement the "get_pc_address_flags" gdbarch method. */
272 aarch64_get_pc_address_flags (frame_info
*frame
, CORE_ADDR pc
)
274 if (pc
!= 0 && get_frame_pc_masked (frame
))
280 /* Analyze a prologue, looking for a recognizable stack frame
281 and frame pointer. Scan until we encounter a store that could
282 clobber the stack frame unexpectedly, or an unknown instruction. */
285 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
286 CORE_ADDR start
, CORE_ADDR limit
,
287 struct aarch64_prologue_cache
*cache
,
288 abstract_instruction_reader
& reader
)
290 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
293 /* Whether the stack has been set. This should be true when we notice a SP
294 to FP move or if we are using the SP as the base register for storing
295 data, in case the FP is ommitted. */
296 bool seen_stack_set
= false;
298 /* Track X registers and D registers in prologue. */
299 pv_t regs
[AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
];
301 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
+ AARCH64_D_REGISTER_COUNT
; i
++)
302 regs
[i
] = pv_register (i
, 0);
303 pv_area
stack (AARCH64_SP_REGNUM
, gdbarch_addr_bit (gdbarch
));
305 for (; start
< limit
; start
+= 4)
310 insn
= reader
.read (start
, 4, byte_order_for_code
);
312 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
315 if (inst
.opcode
->iclass
== addsub_imm
316 && (inst
.opcode
->op
== OP_ADD
317 || strcmp ("sub", inst
.opcode
->name
) == 0))
319 unsigned rd
= inst
.operands
[0].reg
.regno
;
320 unsigned rn
= inst
.operands
[1].reg
.regno
;
322 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 3);
323 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd_SP
);
324 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn_SP
);
325 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_AIMM
);
327 if (inst
.opcode
->op
== OP_ADD
)
329 regs
[rd
] = pv_add_constant (regs
[rn
],
330 inst
.operands
[2].imm
.value
);
334 regs
[rd
] = pv_add_constant (regs
[rn
],
335 -inst
.operands
[2].imm
.value
);
338 /* Did we move SP to FP? */
339 if (rn
== AARCH64_SP_REGNUM
&& rd
== AARCH64_FP_REGNUM
)
340 seen_stack_set
= true;
342 else if (inst
.opcode
->iclass
== pcreladdr
343 && inst
.operands
[1].type
== AARCH64_OPND_ADDR_ADRP
)
345 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
346 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
348 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
350 else if (inst
.opcode
->iclass
== branch_imm
)
352 /* Stop analysis on branch. */
355 else if (inst
.opcode
->iclass
== condbranch
)
357 /* Stop analysis on branch. */
360 else if (inst
.opcode
->iclass
== branch_reg
)
362 /* Stop analysis on branch. */
365 else if (inst
.opcode
->iclass
== compbranch
)
367 /* Stop analysis on branch. */
370 else if (inst
.opcode
->op
== OP_MOVZ
)
372 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
374 /* If this shows up before we set the stack, keep going. Otherwise
375 stop the analysis. */
379 regs
[inst
.operands
[0].reg
.regno
] = pv_unknown ();
381 else if (inst
.opcode
->iclass
== log_shift
382 && strcmp (inst
.opcode
->name
, "orr") == 0)
384 unsigned rd
= inst
.operands
[0].reg
.regno
;
385 unsigned rn
= inst
.operands
[1].reg
.regno
;
386 unsigned rm
= inst
.operands
[2].reg
.regno
;
388 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rd
);
389 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rn
);
390 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_Rm_SFT
);
392 if (inst
.operands
[2].shifter
.amount
== 0
393 && rn
== AARCH64_SP_REGNUM
)
397 aarch64_debug_printf ("prologue analysis gave up "
398 "addr=%s opcode=0x%x (orr x register)",
399 core_addr_to_string_nz (start
), insn
);
404 else if (inst
.opcode
->op
== OP_STUR
)
406 unsigned rt
= inst
.operands
[0].reg
.regno
;
407 unsigned rn
= inst
.operands
[1].addr
.base_regno
;
408 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
410 gdb_assert (aarch64_num_of_operands (inst
.opcode
) == 2);
411 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
);
412 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_ADDR_SIMM9
);
413 gdb_assert (!inst
.operands
[1].addr
.offset
.is_reg
);
416 (pv_add_constant (regs
[rn
], inst
.operands
[1].addr
.offset
.imm
),
419 /* Are we storing with SP as a base? */
420 if (rn
== AARCH64_SP_REGNUM
)
421 seen_stack_set
= true;
423 else if ((inst
.opcode
->iclass
== ldstpair_off
424 || (inst
.opcode
->iclass
== ldstpair_indexed
425 && inst
.operands
[2].addr
.preind
))
426 && strcmp ("stp", inst
.opcode
->name
) == 0)
428 /* STP with addressing mode Pre-indexed and Base register. */
431 unsigned rn
= inst
.operands
[2].addr
.base_regno
;
432 int32_t imm
= inst
.operands
[2].addr
.offset
.imm
;
433 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
435 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
436 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
437 gdb_assert (inst
.operands
[1].type
== AARCH64_OPND_Rt2
438 || inst
.operands
[1].type
== AARCH64_OPND_Ft2
);
439 gdb_assert (inst
.operands
[2].type
== AARCH64_OPND_ADDR_SIMM7
);
440 gdb_assert (!inst
.operands
[2].addr
.offset
.is_reg
);
442 /* If recording this store would invalidate the store area
443 (perhaps because rn is not known) then we should abandon
444 further prologue analysis. */
445 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
)))
448 if (stack
.store_would_trash (pv_add_constant (regs
[rn
], imm
+ 8)))
451 rt1
= inst
.operands
[0].reg
.regno
;
452 rt2
= inst
.operands
[1].reg
.regno
;
453 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
455 rt1
+= AARCH64_X_REGISTER_COUNT
;
456 rt2
+= AARCH64_X_REGISTER_COUNT
;
459 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt1
]);
460 stack
.store (pv_add_constant (regs
[rn
], imm
+ size
), size
, regs
[rt2
]);
462 if (inst
.operands
[2].addr
.writeback
)
463 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
465 /* Ignore the instruction that allocates stack space and sets
467 if (rn
== AARCH64_SP_REGNUM
&& !inst
.operands
[2].addr
.writeback
)
468 seen_stack_set
= true;
470 else if ((inst
.opcode
->iclass
== ldst_imm9
/* Signed immediate. */
471 || (inst
.opcode
->iclass
== ldst_pos
/* Unsigned immediate. */
472 && (inst
.opcode
->op
== OP_STR_POS
473 || inst
.opcode
->op
== OP_STRF_POS
)))
474 && inst
.operands
[1].addr
.base_regno
== AARCH64_SP_REGNUM
475 && strcmp ("str", inst
.opcode
->name
) == 0)
477 /* STR (immediate) */
478 unsigned int rt
= inst
.operands
[0].reg
.regno
;
479 int32_t imm
= inst
.operands
[1].addr
.offset
.imm
;
480 unsigned int rn
= inst
.operands
[1].addr
.base_regno
;
481 int size
= aarch64_get_qualifier_esize (inst
.operands
[0].qualifier
);
482 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_Rt
483 || inst
.operands
[0].type
== AARCH64_OPND_Ft
);
485 if (inst
.operands
[0].type
== AARCH64_OPND_Ft
)
486 rt
+= AARCH64_X_REGISTER_COUNT
;
488 stack
.store (pv_add_constant (regs
[rn
], imm
), size
, regs
[rt
]);
489 if (inst
.operands
[1].addr
.writeback
)
490 regs
[rn
] = pv_add_constant (regs
[rn
], imm
);
492 /* Are we storing with SP as a base? */
493 if (rn
== AARCH64_SP_REGNUM
)
494 seen_stack_set
= true;
496 else if (inst
.opcode
->iclass
== testbranch
)
498 /* Stop analysis on branch. */
501 else if (inst
.opcode
->iclass
== ic_system
)
503 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
504 int ra_state_val
= 0;
506 if (insn
== 0xd503233f /* paciasp. */
507 || insn
== 0xd503237f /* pacibsp. */)
509 /* Return addresses are mangled. */
512 else if (insn
== 0xd50323bf /* autiasp. */
513 || insn
== 0xd50323ff /* autibsp. */)
515 /* Return addresses are not mangled. */
520 aarch64_debug_printf ("prologue analysis gave up addr=%s"
521 " opcode=0x%x (iclass)",
522 core_addr_to_string_nz (start
), insn
);
526 if (tdep
->has_pauth () && cache
!= nullptr)
528 int regnum
= tdep
->pauth_ra_state_regnum
;
529 cache
->saved_regs
[regnum
].set_value (ra_state_val
);
534 aarch64_debug_printf ("prologue analysis gave up addr=%s"
536 core_addr_to_string_nz (start
), insn
);
545 if (pv_is_register (regs
[AARCH64_FP_REGNUM
], AARCH64_SP_REGNUM
))
547 /* Frame pointer is fp. Frame size is constant. */
548 cache
->framereg
= AARCH64_FP_REGNUM
;
549 cache
->framesize
= -regs
[AARCH64_FP_REGNUM
].k
;
551 else if (pv_is_register (regs
[AARCH64_SP_REGNUM
], AARCH64_SP_REGNUM
))
553 /* Try the stack pointer. */
554 cache
->framesize
= -regs
[AARCH64_SP_REGNUM
].k
;
555 cache
->framereg
= AARCH64_SP_REGNUM
;
559 /* We're just out of luck. We don't know where the frame is. */
560 cache
->framereg
= -1;
561 cache
->framesize
= 0;
564 for (i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
568 if (stack
.find_reg (gdbarch
, i
, &offset
))
569 cache
->saved_regs
[i
].set_addr (offset
);
572 for (i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
574 int regnum
= gdbarch_num_regs (gdbarch
);
577 if (stack
.find_reg (gdbarch
, i
+ AARCH64_X_REGISTER_COUNT
,
579 cache
->saved_regs
[i
+ regnum
+ AARCH64_D0_REGNUM
].set_addr (offset
);
586 aarch64_analyze_prologue (struct gdbarch
*gdbarch
,
587 CORE_ADDR start
, CORE_ADDR limit
,
588 struct aarch64_prologue_cache
*cache
)
590 instruction_reader reader
;
592 return aarch64_analyze_prologue (gdbarch
, start
, limit
, cache
,
598 namespace selftests
{
600 /* Instruction reader from manually cooked instruction sequences. */
602 class instruction_reader_test
: public abstract_instruction_reader
605 template<size_t SIZE
>
606 explicit instruction_reader_test (const uint32_t (&insns
)[SIZE
])
607 : m_insns (insns
), m_insns_size (SIZE
)
610 ULONGEST
read (CORE_ADDR memaddr
, int len
, enum bfd_endian byte_order
)
613 SELF_CHECK (len
== 4);
614 SELF_CHECK (memaddr
% 4 == 0);
615 SELF_CHECK (memaddr
/ 4 < m_insns_size
);
617 return m_insns
[memaddr
/ 4];
621 const uint32_t *m_insns
;
626 aarch64_analyze_prologue_test (void)
628 struct gdbarch_info info
;
630 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
632 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
633 SELF_CHECK (gdbarch
!= NULL
);
635 struct aarch64_prologue_cache cache
;
636 cache
.saved_regs
= trad_frame_alloc_saved_regs (gdbarch
);
638 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
640 /* Test the simple prologue in which frame pointer is used. */
642 static const uint32_t insns
[] = {
643 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */
644 0x910003fd, /* mov x29, sp */
645 0x97ffffe6, /* bl 0x400580 */
647 instruction_reader_test
reader (insns
);
649 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
650 SELF_CHECK (end
== 4 * 2);
652 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
653 SELF_CHECK (cache
.framesize
== 272);
655 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
657 if (i
== AARCH64_FP_REGNUM
)
658 SELF_CHECK (cache
.saved_regs
[i
].addr () == -272);
659 else if (i
== AARCH64_LR_REGNUM
)
660 SELF_CHECK (cache
.saved_regs
[i
].addr () == -264);
662 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
663 && cache
.saved_regs
[i
].realreg () == i
);
666 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
668 int num_regs
= gdbarch_num_regs (gdbarch
);
669 int regnum
= i
+ num_regs
+ AARCH64_D0_REGNUM
;
671 SELF_CHECK (cache
.saved_regs
[regnum
].is_realreg ()
672 && cache
.saved_regs
[regnum
].realreg () == regnum
);
676 /* Test a prologue in which STR is used and frame pointer is not
679 static const uint32_t insns
[] = {
680 0xf81d0ff3, /* str x19, [sp, #-48]! */
681 0xb9002fe0, /* str w0, [sp, #44] */
682 0xf90013e1, /* str x1, [sp, #32]*/
683 0xfd000fe0, /* str d0, [sp, #24] */
684 0xaa0203f3, /* mov x19, x2 */
685 0xf94013e0, /* ldr x0, [sp, #32] */
687 instruction_reader_test
reader (insns
);
689 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
690 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
692 SELF_CHECK (end
== 4 * 5);
694 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
695 SELF_CHECK (cache
.framesize
== 48);
697 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
700 SELF_CHECK (cache
.saved_regs
[i
].addr () == -16);
702 SELF_CHECK (cache
.saved_regs
[i
].addr () == -48);
704 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
705 && cache
.saved_regs
[i
].realreg () == i
);
708 for (int i
= 0; i
< AARCH64_D_REGISTER_COUNT
; i
++)
710 int num_regs
= gdbarch_num_regs (gdbarch
);
711 int regnum
= i
+ num_regs
+ AARCH64_D0_REGNUM
;
715 SELF_CHECK (cache
.saved_regs
[regnum
].addr () == -24);
717 SELF_CHECK (cache
.saved_regs
[regnum
].is_realreg ()
718 && cache
.saved_regs
[regnum
].realreg () == regnum
);
722 /* Test handling of movz before setting the frame pointer. */
724 static const uint32_t insns
[] = {
725 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
726 0x52800020, /* mov w0, #0x1 */
727 0x910003fd, /* mov x29, sp */
728 0x528000a2, /* mov w2, #0x5 */
729 0x97fffff8, /* bl 6e4 */
732 instruction_reader_test
reader (insns
);
734 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
735 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
737 /* We should stop at the 4th instruction. */
738 SELF_CHECK (end
== (4 - 1) * 4);
739 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
740 SELF_CHECK (cache
.framesize
== 16);
743 /* Test handling of movz/stp when using the stack pointer as frame
746 static const uint32_t insns
[] = {
747 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
748 0x52800020, /* mov w0, #0x1 */
749 0x290207e0, /* stp w0, w1, [sp, #16] */
750 0xa9018fe2, /* stp x2, x3, [sp, #24] */
751 0x528000a2, /* mov w2, #0x5 */
752 0x97fffff8, /* bl 6e4 */
755 instruction_reader_test
reader (insns
);
757 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
758 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
760 /* We should stop at the 5th instruction. */
761 SELF_CHECK (end
== (5 - 1) * 4);
762 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
763 SELF_CHECK (cache
.framesize
== 64);
766 /* Test handling of movz/str when using the stack pointer as frame
769 static const uint32_t insns
[] = {
770 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
771 0x52800020, /* mov w0, #0x1 */
772 0xb9002be4, /* str w4, [sp, #40] */
773 0xf9001be5, /* str x5, [sp, #48] */
774 0x528000a2, /* mov w2, #0x5 */
775 0x97fffff8, /* bl 6e4 */
778 instruction_reader_test
reader (insns
);
780 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
781 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
783 /* We should stop at the 5th instruction. */
784 SELF_CHECK (end
== (5 - 1) * 4);
785 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
786 SELF_CHECK (cache
.framesize
== 64);
789 /* Test handling of movz/stur when using the stack pointer as frame
792 static const uint32_t insns
[] = {
793 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */
794 0x52800020, /* mov w0, #0x1 */
795 0xb80343e6, /* stur w6, [sp, #52] */
796 0xf80383e7, /* stur x7, [sp, #56] */
797 0x528000a2, /* mov w2, #0x5 */
798 0x97fffff8, /* bl 6e4 */
801 instruction_reader_test
reader (insns
);
803 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
804 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
806 /* We should stop at the 5th instruction. */
807 SELF_CHECK (end
== (5 - 1) * 4);
808 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
809 SELF_CHECK (cache
.framesize
== 64);
812 /* Test handling of movz when there is no frame pointer set or no stack
815 static const uint32_t insns
[] = {
816 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */
817 0x52800020, /* mov w0, #0x1 */
818 0x528000a2, /* mov w2, #0x5 */
819 0x97fffff8, /* bl 6e4 */
822 instruction_reader_test
reader (insns
);
824 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
825 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
, reader
);
827 /* We should stop at the 4th instruction. */
828 SELF_CHECK (end
== (4 - 1) * 4);
829 SELF_CHECK (cache
.framereg
== AARCH64_SP_REGNUM
);
830 SELF_CHECK (cache
.framesize
== 16);
833 /* Test a prologue in which there is a return address signing instruction. */
834 if (tdep
->has_pauth ())
836 static const uint32_t insns
[] = {
837 0xd503233f, /* paciasp */
838 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */
839 0x910003fd, /* mov x29, sp */
840 0xf801c3f3, /* str x19, [sp, #28] */
841 0xb9401fa0, /* ldr x19, [x29, #28] */
843 instruction_reader_test
reader (insns
);
845 trad_frame_reset_saved_regs (gdbarch
, cache
.saved_regs
);
846 CORE_ADDR end
= aarch64_analyze_prologue (gdbarch
, 0, 128, &cache
,
849 SELF_CHECK (end
== 4 * 4);
850 SELF_CHECK (cache
.framereg
== AARCH64_FP_REGNUM
);
851 SELF_CHECK (cache
.framesize
== 48);
853 for (int i
= 0; i
< AARCH64_X_REGISTER_COUNT
; i
++)
856 SELF_CHECK (cache
.saved_regs
[i
].addr () == -20);
857 else if (i
== AARCH64_FP_REGNUM
)
858 SELF_CHECK (cache
.saved_regs
[i
].addr () == -48);
859 else if (i
== AARCH64_LR_REGNUM
)
860 SELF_CHECK (cache
.saved_regs
[i
].addr () == -40);
862 SELF_CHECK (cache
.saved_regs
[i
].is_realreg ()
863 && cache
.saved_regs
[i
].realreg () == i
);
866 if (tdep
->has_pauth ())
868 int regnum
= tdep
->pauth_ra_state_regnum
;
869 SELF_CHECK (cache
.saved_regs
[regnum
].is_value ());
873 } // namespace selftests
874 #endif /* GDB_SELF_TEST */
876 /* Implement the "skip_prologue" gdbarch method. */
879 aarch64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
881 CORE_ADDR func_addr
, limit_pc
;
883 /* See if we can determine the end of the prologue via the symbol
884 table. If so, then return either PC, or the PC after the
885 prologue, whichever is greater. */
886 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
888 CORE_ADDR post_prologue_pc
889 = skip_prologue_using_sal (gdbarch
, func_addr
);
891 if (post_prologue_pc
!= 0)
892 return std::max (pc
, post_prologue_pc
);
895 /* Can't determine prologue from the symbol table, need to examine
898 /* Find an upper limit on the function prologue using the debug
899 information. If the debug information could not be used to
900 provide that bound, then use an arbitrary large number as the
902 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
904 limit_pc
= pc
+ 128; /* Magic. */
906 /* Try disassembling prologue. */
907 return aarch64_analyze_prologue (gdbarch
, pc
, limit_pc
, NULL
);
910 /* Scan the function prologue for THIS_FRAME and populate the prologue
914 aarch64_scan_prologue (struct frame_info
*this_frame
,
915 struct aarch64_prologue_cache
*cache
)
917 CORE_ADDR block_addr
= get_frame_address_in_block (this_frame
);
918 CORE_ADDR prologue_start
;
919 CORE_ADDR prologue_end
;
920 CORE_ADDR prev_pc
= get_frame_pc (this_frame
);
921 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
923 cache
->prev_pc
= prev_pc
;
925 /* Assume we do not find a frame. */
926 cache
->framereg
= -1;
927 cache
->framesize
= 0;
929 if (find_pc_partial_function (block_addr
, NULL
, &prologue_start
,
932 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
936 /* No line info so use the current PC. */
937 prologue_end
= prev_pc
;
939 else if (sal
.end
< prologue_end
)
941 /* The next line begins after the function end. */
942 prologue_end
= sal
.end
;
945 prologue_end
= std::min (prologue_end
, prev_pc
);
946 aarch64_analyze_prologue (gdbarch
, prologue_start
, prologue_end
, cache
);
952 frame_loc
= get_frame_register_unsigned (this_frame
, AARCH64_FP_REGNUM
);
956 cache
->framereg
= AARCH64_FP_REGNUM
;
957 cache
->framesize
= 16;
958 cache
->saved_regs
[29].set_addr (0);
959 cache
->saved_regs
[30].set_addr (8);
963 /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This
964 function may throw an exception if the inferior's registers or memory is
968 aarch64_make_prologue_cache_1 (struct frame_info
*this_frame
,
969 struct aarch64_prologue_cache
*cache
)
971 CORE_ADDR unwound_fp
;
974 aarch64_scan_prologue (this_frame
, cache
);
976 if (cache
->framereg
== -1)
979 unwound_fp
= get_frame_register_unsigned (this_frame
, cache
->framereg
);
983 cache
->prev_sp
= unwound_fp
+ cache
->framesize
;
985 /* Calculate actual addresses of saved registers using offsets
986 determined by aarch64_analyze_prologue. */
987 for (reg
= 0; reg
< gdbarch_num_regs (get_frame_arch (this_frame
)); reg
++)
988 if (cache
->saved_regs
[reg
].is_addr ())
989 cache
->saved_regs
[reg
].set_addr (cache
->saved_regs
[reg
].addr ()
992 cache
->func
= get_frame_func (this_frame
);
994 cache
->available_p
= 1;
997 /* Allocate and fill in *THIS_CACHE with information about the prologue of
998 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
999 Return a pointer to the current aarch64_prologue_cache in
1002 static struct aarch64_prologue_cache
*
1003 aarch64_make_prologue_cache (struct frame_info
*this_frame
, void **this_cache
)
1005 struct aarch64_prologue_cache
*cache
;
1007 if (*this_cache
!= NULL
)
1008 return (struct aarch64_prologue_cache
*) *this_cache
;
1010 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1011 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1012 *this_cache
= cache
;
1016 aarch64_make_prologue_cache_1 (this_frame
, cache
);
1018 catch (const gdb_exception_error
&ex
)
1020 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1027 /* Implement the "stop_reason" frame_unwind method. */
1029 static enum unwind_stop_reason
1030 aarch64_prologue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1033 struct aarch64_prologue_cache
*cache
1034 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1036 if (!cache
->available_p
)
1037 return UNWIND_UNAVAILABLE
;
1039 /* Halt the backtrace at "_start". */
1040 if (cache
->prev_pc
<= gdbarch_tdep (get_frame_arch (this_frame
))->lowest_pc
)
1041 return UNWIND_OUTERMOST
;
1043 /* We've hit a wall, stop. */
1044 if (cache
->prev_sp
== 0)
1045 return UNWIND_OUTERMOST
;
1047 return UNWIND_NO_REASON
;
1050 /* Our frame ID for a normal frame is the current function's starting
1051 PC and the caller's SP when we were called. */
1054 aarch64_prologue_this_id (struct frame_info
*this_frame
,
1055 void **this_cache
, struct frame_id
*this_id
)
1057 struct aarch64_prologue_cache
*cache
1058 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1060 if (!cache
->available_p
)
1061 *this_id
= frame_id_build_unavailable_stack (cache
->func
);
1063 *this_id
= frame_id_build (cache
->prev_sp
, cache
->func
);
1066 /* Implement the "prev_register" frame_unwind method. */
1068 static struct value
*
1069 aarch64_prologue_prev_register (struct frame_info
*this_frame
,
1070 void **this_cache
, int prev_regnum
)
1072 struct aarch64_prologue_cache
*cache
1073 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1075 /* If we are asked to unwind the PC, then we need to return the LR
1076 instead. The prologue may save PC, but it will point into this
1077 frame's prologue, not the next frame's resume location. */
1078 if (prev_regnum
== AARCH64_PC_REGNUM
)
1081 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1082 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1084 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1086 if (tdep
->has_pauth ()
1087 && cache
->saved_regs
[tdep
->pauth_ra_state_regnum
].is_value ())
1088 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1090 return frame_unwind_got_constant (this_frame
, prev_regnum
, lr
);
1093 /* SP is generally not saved to the stack, but this frame is
1094 identified by the next frame's stack pointer at the time of the
1095 call. The value was already reconstructed into PREV_SP. */
1101 | | | <- Previous SP
1104 +--| saved fp |<- FP
1108 if (prev_regnum
== AARCH64_SP_REGNUM
)
1109 return frame_unwind_got_constant (this_frame
, prev_regnum
,
1112 return trad_frame_get_prev_register (this_frame
, cache
->saved_regs
,
1116 /* AArch64 prologue unwinder. */
1117 static frame_unwind aarch64_prologue_unwind
=
1120 aarch64_prologue_frame_unwind_stop_reason
,
1121 aarch64_prologue_this_id
,
1122 aarch64_prologue_prev_register
,
1124 default_frame_sniffer
1127 /* Allocate and fill in *THIS_CACHE with information about the prologue of
1128 *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated.
1129 Return a pointer to the current aarch64_prologue_cache in
1132 static struct aarch64_prologue_cache
*
1133 aarch64_make_stub_cache (struct frame_info
*this_frame
, void **this_cache
)
1135 struct aarch64_prologue_cache
*cache
;
1137 if (*this_cache
!= NULL
)
1138 return (struct aarch64_prologue_cache
*) *this_cache
;
1140 cache
= FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache
);
1141 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1142 *this_cache
= cache
;
1146 cache
->prev_sp
= get_frame_register_unsigned (this_frame
,
1148 cache
->prev_pc
= get_frame_pc (this_frame
);
1149 cache
->available_p
= 1;
1151 catch (const gdb_exception_error
&ex
)
1153 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
1160 /* Implement the "stop_reason" frame_unwind method. */
1162 static enum unwind_stop_reason
1163 aarch64_stub_frame_unwind_stop_reason (struct frame_info
*this_frame
,
1166 struct aarch64_prologue_cache
*cache
1167 = aarch64_make_stub_cache (this_frame
, this_cache
);
1169 if (!cache
->available_p
)
1170 return UNWIND_UNAVAILABLE
;
1172 return UNWIND_NO_REASON
;
1175 /* Our frame ID for a stub frame is the current SP and LR. */
1178 aarch64_stub_this_id (struct frame_info
*this_frame
,
1179 void **this_cache
, struct frame_id
*this_id
)
1181 struct aarch64_prologue_cache
*cache
1182 = aarch64_make_stub_cache (this_frame
, this_cache
);
1184 if (cache
->available_p
)
1185 *this_id
= frame_id_build (cache
->prev_sp
, cache
->prev_pc
);
1187 *this_id
= frame_id_build_unavailable_stack (cache
->prev_pc
);
1190 /* Implement the "sniffer" frame_unwind method. */
1193 aarch64_stub_unwind_sniffer (const struct frame_unwind
*self
,
1194 struct frame_info
*this_frame
,
1195 void **this_prologue_cache
)
1197 CORE_ADDR addr_in_block
;
1200 addr_in_block
= get_frame_address_in_block (this_frame
);
1201 if (in_plt_section (addr_in_block
)
1202 /* We also use the stub winder if the target memory is unreadable
1203 to avoid having the prologue unwinder trying to read it. */
1204 || target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
1210 /* AArch64 stub unwinder. */
1211 static frame_unwind aarch64_stub_unwind
=
1214 aarch64_stub_frame_unwind_stop_reason
,
1215 aarch64_stub_this_id
,
1216 aarch64_prologue_prev_register
,
1218 aarch64_stub_unwind_sniffer
1221 /* Return the frame base address of *THIS_FRAME. */
1224 aarch64_normal_frame_base (struct frame_info
*this_frame
, void **this_cache
)
1226 struct aarch64_prologue_cache
*cache
1227 = aarch64_make_prologue_cache (this_frame
, this_cache
);
1229 return cache
->prev_sp
- cache
->framesize
;
1232 /* AArch64 default frame base information. */
1233 static frame_base aarch64_normal_base
=
1235 &aarch64_prologue_unwind
,
1236 aarch64_normal_frame_base
,
1237 aarch64_normal_frame_base
,
1238 aarch64_normal_frame_base
1241 /* Return the value of the REGNUM register in the previous frame of
1244 static struct value
*
1245 aarch64_dwarf2_prev_register (struct frame_info
*this_frame
,
1246 void **this_cache
, int regnum
)
1248 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
1253 case AARCH64_PC_REGNUM
:
1254 lr
= frame_unwind_register_unsigned (this_frame
, AARCH64_LR_REGNUM
);
1255 lr
= aarch64_frame_unmask_lr (tdep
, this_frame
, lr
);
1256 return frame_unwind_got_constant (this_frame
, regnum
, lr
);
1259 internal_error (__FILE__
, __LINE__
,
1260 _("Unexpected register %d"), regnum
);
1264 static const unsigned char op_lit0
= DW_OP_lit0
;
1265 static const unsigned char op_lit1
= DW_OP_lit1
;
1267 /* Implement the "init_reg" dwarf2_frame_ops method. */
1270 aarch64_dwarf2_frame_init_reg (struct gdbarch
*gdbarch
, int regnum
,
1271 struct dwarf2_frame_state_reg
*reg
,
1272 struct frame_info
*this_frame
)
1274 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1278 case AARCH64_PC_REGNUM
:
1279 reg
->how
= DWARF2_FRAME_REG_FN
;
1280 reg
->loc
.fn
= aarch64_dwarf2_prev_register
;
1283 case AARCH64_SP_REGNUM
:
1284 reg
->how
= DWARF2_FRAME_REG_CFA
;
1288 /* Init pauth registers. */
1289 if (tdep
->has_pauth ())
1291 if (regnum
== tdep
->pauth_ra_state_regnum
)
1293 /* Initialize RA_STATE to zero. */
1294 reg
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1295 reg
->loc
.exp
.start
= &op_lit0
;
1296 reg
->loc
.exp
.len
= 1;
1299 else if (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
1300 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
))
1302 reg
->how
= DWARF2_FRAME_REG_SAME_VALUE
;
1308 /* Implement the execute_dwarf_cfa_vendor_op method. */
1311 aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch
*gdbarch
, gdb_byte op
,
1312 struct dwarf2_frame_state
*fs
)
1314 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1315 struct dwarf2_frame_state_reg
*ra_state
;
1317 if (op
== DW_CFA_AARCH64_negate_ra_state
)
1319 /* On systems without pauth, treat as a nop. */
1320 if (!tdep
->has_pauth ())
1323 /* Allocate RA_STATE column if it's not allocated yet. */
1324 fs
->regs
.alloc_regs (AARCH64_DWARF_PAUTH_RA_STATE
+ 1);
1326 /* Toggle the status of RA_STATE between 0 and 1. */
1327 ra_state
= &(fs
->regs
.reg
[AARCH64_DWARF_PAUTH_RA_STATE
]);
1328 ra_state
->how
= DWARF2_FRAME_REG_SAVED_VAL_EXP
;
1330 if (ra_state
->loc
.exp
.start
== nullptr
1331 || ra_state
->loc
.exp
.start
== &op_lit0
)
1332 ra_state
->loc
.exp
.start
= &op_lit1
;
1334 ra_state
->loc
.exp
.start
= &op_lit0
;
1336 ra_state
->loc
.exp
.len
= 1;
1344 /* Used for matching BRK instructions for AArch64. */
1345 static constexpr uint32_t BRK_INSN_MASK
= 0xffe0001f;
1346 static constexpr uint32_t BRK_INSN_BASE
= 0xd4200000;
1348 /* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */
1351 aarch64_program_breakpoint_here_p (gdbarch
*gdbarch
, CORE_ADDR address
)
1353 const uint32_t insn_len
= 4;
1354 gdb_byte target_mem
[4];
1356 /* Enable the automatic memory restoration from breakpoints while
1357 we read the memory. Otherwise we may find temporary breakpoints, ones
1358 inserted by GDB, and flag them as permanent breakpoints. */
1359 scoped_restore restore_memory
1360 = make_scoped_restore_show_memory_breakpoints (0);
1362 if (target_read_memory (address
, target_mem
, insn_len
) == 0)
1365 (uint32_t) extract_unsigned_integer (target_mem
, insn_len
,
1366 gdbarch_byte_order_for_code (gdbarch
));
1368 /* Check if INSN is a BRK instruction pattern. There are multiple choices
1369 of such instructions with different immediate values. Different OS'
1370 may use a different variation, but they have the same outcome. */
1371 return ((insn
& BRK_INSN_MASK
) == BRK_INSN_BASE
);
1377 /* When arguments must be pushed onto the stack, they go on in reverse
1378 order. The code below implements a FILO (stack) to do this. */
1382 /* Value to pass on stack. It can be NULL if this item is for stack
1384 const gdb_byte
*data
;
1386 /* Size in bytes of value to pass on stack. */
1390 /* Implement the gdbarch type alignment method, overrides the generic
1391 alignment algorithm for anything that is aarch64 specific. */
1394 aarch64_type_align (gdbarch
*gdbarch
, struct type
*t
)
1396 t
= check_typedef (t
);
1397 if (t
->code () == TYPE_CODE_ARRAY
&& t
->is_vector ())
1399 /* Use the natural alignment for vector types (the same for
1400 scalar type), but the maximum alignment is 128-bit. */
1401 if (TYPE_LENGTH (t
) > 16)
1404 return TYPE_LENGTH (t
);
1407 /* Allow the common code to calculate the alignment. */
1411 /* Worker function for aapcs_is_vfp_call_or_return_candidate.
1413 Return the number of register required, or -1 on failure.
1415 When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it
1416 to the element, else fail if the type of this element does not match the
1420 aapcs_is_vfp_call_or_return_candidate_1 (struct type
*type
,
1421 struct type
**fundamental_type
)
1423 if (type
== nullptr)
1426 switch (type
->code ())
1429 if (TYPE_LENGTH (type
) > 16)
1432 if (*fundamental_type
== nullptr)
1433 *fundamental_type
= type
;
1434 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1435 || type
->code () != (*fundamental_type
)->code ())
1440 case TYPE_CODE_COMPLEX
:
1442 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (type
));
1443 if (TYPE_LENGTH (target_type
) > 16)
1446 if (*fundamental_type
== nullptr)
1447 *fundamental_type
= target_type
;
1448 else if (TYPE_LENGTH (target_type
) != TYPE_LENGTH (*fundamental_type
)
1449 || target_type
->code () != (*fundamental_type
)->code ())
1455 case TYPE_CODE_ARRAY
:
1457 if (type
->is_vector ())
1459 if (TYPE_LENGTH (type
) != 8 && TYPE_LENGTH (type
) != 16)
1462 if (*fundamental_type
== nullptr)
1463 *fundamental_type
= type
;
1464 else if (TYPE_LENGTH (type
) != TYPE_LENGTH (*fundamental_type
)
1465 || type
->code () != (*fundamental_type
)->code ())
1472 struct type
*target_type
= TYPE_TARGET_TYPE (type
);
1473 int count
= aapcs_is_vfp_call_or_return_candidate_1
1474 (target_type
, fundamental_type
);
1479 count
*= (TYPE_LENGTH (type
) / TYPE_LENGTH (target_type
));
1484 case TYPE_CODE_STRUCT
:
1485 case TYPE_CODE_UNION
:
1489 for (int i
= 0; i
< type
->num_fields (); i
++)
1491 /* Ignore any static fields. */
1492 if (field_is_static (&type
->field (i
)))
1495 struct type
*member
= check_typedef (type
->field (i
).type ());
1497 int sub_count
= aapcs_is_vfp_call_or_return_candidate_1
1498 (member
, fundamental_type
);
1499 if (sub_count
== -1)
1504 /* Ensure there is no padding between the fields (allowing for empty
1505 zero length structs) */
1506 int ftype_length
= (*fundamental_type
== nullptr)
1507 ? 0 : TYPE_LENGTH (*fundamental_type
);
1508 if (count
* ftype_length
!= TYPE_LENGTH (type
))
1521 /* Return true if an argument, whose type is described by TYPE, can be passed or
1522 returned in simd/fp registers, providing enough parameter passing registers
1523 are available. This is as described in the AAPCS64.
1525 Upon successful return, *COUNT returns the number of needed registers,
1526 *FUNDAMENTAL_TYPE contains the type of those registers.
1528 Candidate as per the AAPCS64 5.4.2.C is either a:
1531 - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where
1532 all the members are floats and has at most 4 members.
1533 - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where
1534 all the members are short vectors and has at most 4 members.
1537 Note that HFAs and HVAs can include nested structures and arrays. */
1540 aapcs_is_vfp_call_or_return_candidate (struct type
*type
, int *count
,
1541 struct type
**fundamental_type
)
1543 if (type
== nullptr)
1546 *fundamental_type
= nullptr;
1548 int ag_count
= aapcs_is_vfp_call_or_return_candidate_1 (type
,
1551 if (ag_count
> 0 && ag_count
<= HA_MAX_NUM_FLDS
)
1560 /* AArch64 function call information structure. */
1561 struct aarch64_call_info
1563 /* the current argument number. */
1564 unsigned argnum
= 0;
1566 /* The next general purpose register number, equivalent to NGRN as
1567 described in the AArch64 Procedure Call Standard. */
1570 /* The next SIMD and floating point register number, equivalent to
1571 NSRN as described in the AArch64 Procedure Call Standard. */
1574 /* The next stacked argument address, equivalent to NSAA as
1575 described in the AArch64 Procedure Call Standard. */
1578 /* Stack item vector. */
1579 std::vector
<stack_item_t
> si
;
1582 /* Pass a value in a sequence of consecutive X registers. The caller
1583 is responsible for ensuring sufficient registers are available. */
1586 pass_in_x (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1587 struct aarch64_call_info
*info
, struct type
*type
,
1590 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1591 int len
= TYPE_LENGTH (type
);
1592 enum type_code typecode
= type
->code ();
1593 int regnum
= AARCH64_X0_REGNUM
+ info
->ngrn
;
1594 const bfd_byte
*buf
= value_contents (arg
);
1600 int partial_len
= len
< X_REGISTER_SIZE
? len
: X_REGISTER_SIZE
;
1601 CORE_ADDR regval
= extract_unsigned_integer (buf
, partial_len
,
1605 /* Adjust sub-word struct/union args when big-endian. */
1606 if (byte_order
== BFD_ENDIAN_BIG
1607 && partial_len
< X_REGISTER_SIZE
1608 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
1609 regval
<<= ((X_REGISTER_SIZE
- partial_len
) * TARGET_CHAR_BIT
);
1611 aarch64_debug_printf ("arg %d in %s = 0x%s", info
->argnum
,
1612 gdbarch_register_name (gdbarch
, regnum
),
1613 phex (regval
, X_REGISTER_SIZE
));
1615 regcache_cooked_write_unsigned (regcache
, regnum
, regval
);
1622 /* Attempt to marshall a value in a V register. Return 1 if
1623 successful, or 0 if insufficient registers are available. This
1624 function, unlike the equivalent pass_in_x() function does not
1625 handle arguments spread across multiple registers. */
1628 pass_in_v (struct gdbarch
*gdbarch
,
1629 struct regcache
*regcache
,
1630 struct aarch64_call_info
*info
,
1631 int len
, const bfd_byte
*buf
)
1635 int regnum
= AARCH64_V0_REGNUM
+ info
->nsrn
;
1636 /* Enough space for a full vector register. */
1637 gdb_byte reg
[register_size (gdbarch
, regnum
)];
1638 gdb_assert (len
<= sizeof (reg
));
1643 memset (reg
, 0, sizeof (reg
));
1644 /* PCS C.1, the argument is allocated to the least significant
1645 bits of V register. */
1646 memcpy (reg
, buf
, len
);
1647 regcache
->cooked_write (regnum
, reg
);
1649 aarch64_debug_printf ("arg %d in %s", info
->argnum
,
1650 gdbarch_register_name (gdbarch
, regnum
));
1658 /* Marshall an argument onto the stack. */
1661 pass_on_stack (struct aarch64_call_info
*info
, struct type
*type
,
1664 const bfd_byte
*buf
= value_contents (arg
);
1665 int len
= TYPE_LENGTH (type
);
1671 align
= type_align (type
);
1673 /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the
1674 Natural alignment of the argument's type. */
1675 align
= align_up (align
, 8);
1677 /* The AArch64 PCS requires at most doubleword alignment. */
1681 aarch64_debug_printf ("arg %d len=%d @ sp + %d\n", info
->argnum
, len
,
1686 info
->si
.push_back (item
);
1689 if (info
->nsaa
& (align
- 1))
1691 /* Push stack alignment padding. */
1692 int pad
= align
- (info
->nsaa
& (align
- 1));
1697 info
->si
.push_back (item
);
1702 /* Marshall an argument into a sequence of one or more consecutive X
1703 registers or, if insufficient X registers are available then onto
1707 pass_in_x_or_stack (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1708 struct aarch64_call_info
*info
, struct type
*type
,
1711 int len
= TYPE_LENGTH (type
);
1712 int nregs
= (len
+ X_REGISTER_SIZE
- 1) / X_REGISTER_SIZE
;
1714 /* PCS C.13 - Pass in registers if we have enough spare */
1715 if (info
->ngrn
+ nregs
<= 8)
1717 pass_in_x (gdbarch
, regcache
, info
, type
, arg
);
1718 info
->ngrn
+= nregs
;
1723 pass_on_stack (info
, type
, arg
);
1727 /* Pass a value, which is of type arg_type, in a V register. Assumes value is a
1728 aapcs_is_vfp_call_or_return_candidate and there are enough spare V
1729 registers. A return value of false is an error state as the value will have
1730 been partially passed to the stack. */
1732 pass_in_v_vfp_candidate (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1733 struct aarch64_call_info
*info
, struct type
*arg_type
,
1736 switch (arg_type
->code ())
1739 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1740 value_contents (arg
));
1743 case TYPE_CODE_COMPLEX
:
1745 const bfd_byte
*buf
= value_contents (arg
);
1746 struct type
*target_type
= check_typedef (TYPE_TARGET_TYPE (arg_type
));
1748 if (!pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1752 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (target_type
),
1753 buf
+ TYPE_LENGTH (target_type
));
1756 case TYPE_CODE_ARRAY
:
1757 if (arg_type
->is_vector ())
1758 return pass_in_v (gdbarch
, regcache
, info
, TYPE_LENGTH (arg_type
),
1759 value_contents (arg
));
1762 case TYPE_CODE_STRUCT
:
1763 case TYPE_CODE_UNION
:
1764 for (int i
= 0; i
< arg_type
->num_fields (); i
++)
1766 /* Don't include static fields. */
1767 if (field_is_static (&arg_type
->field (i
)))
1770 struct value
*field
= value_primitive_field (arg
, 0, i
, arg_type
);
1771 struct type
*field_type
= check_typedef (value_type (field
));
1773 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, info
, field_type
,
1784 /* Implement the "push_dummy_call" gdbarch method. */
1787 aarch64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1788 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1790 struct value
**args
, CORE_ADDR sp
,
1791 function_call_return_method return_method
,
1792 CORE_ADDR struct_addr
)
1795 struct aarch64_call_info info
;
1797 /* We need to know what the type of the called function is in order
1798 to determine the number of named/anonymous arguments for the
1799 actual argument placement, and the return type in order to handle
1800 return value correctly.
1802 The generic code above us views the decision of return in memory
1803 or return in registers as a two stage processes. The language
1804 handler is consulted first and may decide to return in memory (eg
1805 class with copy constructor returned by value), this will cause
1806 the generic code to allocate space AND insert an initial leading
1809 If the language code does not decide to pass in memory then the
1810 target code is consulted.
1812 If the language code decides to pass in memory we want to move
1813 the pointer inserted as the initial argument from the argument
1814 list and into X8, the conventional AArch64 struct return pointer
1817 /* Set the return address. For the AArch64, the return breakpoint
1818 is always at BP_ADDR. */
1819 regcache_cooked_write_unsigned (regcache
, AARCH64_LR_REGNUM
, bp_addr
);
1821 /* If we were given an initial argument for the return slot, lose it. */
1822 if (return_method
== return_method_hidden_param
)
1828 /* The struct_return pointer occupies X8. */
1829 if (return_method
!= return_method_normal
)
1831 aarch64_debug_printf ("struct return in %s = 0x%s",
1832 gdbarch_register_name
1833 (gdbarch
, AARCH64_STRUCT_RETURN_REGNUM
),
1834 paddress (gdbarch
, struct_addr
));
1836 regcache_cooked_write_unsigned (regcache
, AARCH64_STRUCT_RETURN_REGNUM
,
1840 for (argnum
= 0; argnum
< nargs
; argnum
++)
1842 struct value
*arg
= args
[argnum
];
1843 struct type
*arg_type
, *fundamental_type
;
1846 arg_type
= check_typedef (value_type (arg
));
1847 len
= TYPE_LENGTH (arg_type
);
1849 /* If arg can be passed in v registers as per the AAPCS64, then do so if
1850 if there are enough spare registers. */
1851 if (aapcs_is_vfp_call_or_return_candidate (arg_type
, &elements
,
1854 if (info
.nsrn
+ elements
<= 8)
1856 /* We know that we have sufficient registers available therefore
1857 this will never need to fallback to the stack. */
1858 if (!pass_in_v_vfp_candidate (gdbarch
, regcache
, &info
, arg_type
,
1860 gdb_assert_not_reached ("Failed to push args");
1865 pass_on_stack (&info
, arg_type
, arg
);
1870 switch (arg_type
->code ())
1873 case TYPE_CODE_BOOL
:
1874 case TYPE_CODE_CHAR
:
1875 case TYPE_CODE_RANGE
:
1876 case TYPE_CODE_ENUM
:
1879 /* Promote to 32 bit integer. */
1880 if (arg_type
->is_unsigned ())
1881 arg_type
= builtin_type (gdbarch
)->builtin_uint32
;
1883 arg_type
= builtin_type (gdbarch
)->builtin_int32
;
1884 arg
= value_cast (arg_type
, arg
);
1886 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1889 case TYPE_CODE_STRUCT
:
1890 case TYPE_CODE_ARRAY
:
1891 case TYPE_CODE_UNION
:
1894 /* PCS B.7 Aggregates larger than 16 bytes are passed by
1895 invisible reference. */
1897 /* Allocate aligned storage. */
1898 sp
= align_down (sp
- len
, 16);
1900 /* Write the real data into the stack. */
1901 write_memory (sp
, value_contents (arg
), len
);
1903 /* Construct the indirection. */
1904 arg_type
= lookup_pointer_type (arg_type
);
1905 arg
= value_from_pointer (arg_type
, sp
);
1906 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1909 /* PCS C.15 / C.18 multiple values pass. */
1910 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1914 pass_in_x_or_stack (gdbarch
, regcache
, &info
, arg_type
, arg
);
1919 /* Make sure stack retains 16 byte alignment. */
1921 sp
-= 16 - (info
.nsaa
& 15);
1923 while (!info
.si
.empty ())
1925 const stack_item_t
&si
= info
.si
.back ();
1928 if (si
.data
!= NULL
)
1929 write_memory (sp
, si
.data
, si
.len
);
1930 info
.si
.pop_back ();
1933 /* Finally, update the SP register. */
1934 regcache_cooked_write_unsigned (regcache
, AARCH64_SP_REGNUM
, sp
);
1939 /* Implement the "frame_align" gdbarch method. */
1942 aarch64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1944 /* Align the stack to sixteen bytes. */
1945 return sp
& ~(CORE_ADDR
) 15;
1948 /* Return the type for an AdvSISD Q register. */
1950 static struct type
*
1951 aarch64_vnq_type (struct gdbarch
*gdbarch
)
1953 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1955 if (tdep
->vnq_type
== NULL
)
1960 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
1963 elem
= builtin_type (gdbarch
)->builtin_uint128
;
1964 append_composite_type_field (t
, "u", elem
);
1966 elem
= builtin_type (gdbarch
)->builtin_int128
;
1967 append_composite_type_field (t
, "s", elem
);
1972 return tdep
->vnq_type
;
1975 /* Return the type for an AdvSISD D register. */
1977 static struct type
*
1978 aarch64_vnd_type (struct gdbarch
*gdbarch
)
1980 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
1982 if (tdep
->vnd_type
== NULL
)
1987 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
1990 elem
= builtin_type (gdbarch
)->builtin_double
;
1991 append_composite_type_field (t
, "f", elem
);
1993 elem
= builtin_type (gdbarch
)->builtin_uint64
;
1994 append_composite_type_field (t
, "u", elem
);
1996 elem
= builtin_type (gdbarch
)->builtin_int64
;
1997 append_composite_type_field (t
, "s", elem
);
2002 return tdep
->vnd_type
;
2005 /* Return the type for an AdvSISD S register. */
2007 static struct type
*
2008 aarch64_vns_type (struct gdbarch
*gdbarch
)
2010 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2012 if (tdep
->vns_type
== NULL
)
2017 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
2020 elem
= builtin_type (gdbarch
)->builtin_float
;
2021 append_composite_type_field (t
, "f", elem
);
2023 elem
= builtin_type (gdbarch
)->builtin_uint32
;
2024 append_composite_type_field (t
, "u", elem
);
2026 elem
= builtin_type (gdbarch
)->builtin_int32
;
2027 append_composite_type_field (t
, "s", elem
);
2032 return tdep
->vns_type
;
2035 /* Return the type for an AdvSISD H register. */
2037 static struct type
*
2038 aarch64_vnh_type (struct gdbarch
*gdbarch
)
2040 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2042 if (tdep
->vnh_type
== NULL
)
2047 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2050 elem
= builtin_type (gdbarch
)->builtin_bfloat16
;
2051 append_composite_type_field (t
, "bf", elem
);
2053 elem
= builtin_type (gdbarch
)->builtin_half
;
2054 append_composite_type_field (t
, "f", elem
);
2056 elem
= builtin_type (gdbarch
)->builtin_uint16
;
2057 append_composite_type_field (t
, "u", elem
);
2059 elem
= builtin_type (gdbarch
)->builtin_int16
;
2060 append_composite_type_field (t
, "s", elem
);
2065 return tdep
->vnh_type
;
2068 /* Return the type for an AdvSISD B register. */
2070 static struct type
*
2071 aarch64_vnb_type (struct gdbarch
*gdbarch
)
2073 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2075 if (tdep
->vnb_type
== NULL
)
2080 t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2083 elem
= builtin_type (gdbarch
)->builtin_uint8
;
2084 append_composite_type_field (t
, "u", elem
);
2086 elem
= builtin_type (gdbarch
)->builtin_int8
;
2087 append_composite_type_field (t
, "s", elem
);
2092 return tdep
->vnb_type
;
2095 /* Return the type for an AdvSISD V register. */
2097 static struct type
*
2098 aarch64_vnv_type (struct gdbarch
*gdbarch
)
2100 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2102 if (tdep
->vnv_type
== NULL
)
2104 /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value
2105 slice from the non-pseudo vector registers. However NEON V registers
2106 are always vector registers, and need constructing as such. */
2107 const struct builtin_type
*bt
= builtin_type (gdbarch
);
2109 struct type
*t
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnv",
2112 struct type
*sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnd",
2114 append_composite_type_field (sub
, "f",
2115 init_vector_type (bt
->builtin_double
, 2));
2116 append_composite_type_field (sub
, "u",
2117 init_vector_type (bt
->builtin_uint64
, 2));
2118 append_composite_type_field (sub
, "s",
2119 init_vector_type (bt
->builtin_int64
, 2));
2120 append_composite_type_field (t
, "d", sub
);
2122 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vns",
2124 append_composite_type_field (sub
, "f",
2125 init_vector_type (bt
->builtin_float
, 4));
2126 append_composite_type_field (sub
, "u",
2127 init_vector_type (bt
->builtin_uint32
, 4));
2128 append_composite_type_field (sub
, "s",
2129 init_vector_type (bt
->builtin_int32
, 4));
2130 append_composite_type_field (t
, "s", sub
);
2132 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnh",
2134 append_composite_type_field (sub
, "bf",
2135 init_vector_type (bt
->builtin_bfloat16
, 8));
2136 append_composite_type_field (sub
, "f",
2137 init_vector_type (bt
->builtin_half
, 8));
2138 append_composite_type_field (sub
, "u",
2139 init_vector_type (bt
->builtin_uint16
, 8));
2140 append_composite_type_field (sub
, "s",
2141 init_vector_type (bt
->builtin_int16
, 8));
2142 append_composite_type_field (t
, "h", sub
);
2144 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnb",
2146 append_composite_type_field (sub
, "u",
2147 init_vector_type (bt
->builtin_uint8
, 16));
2148 append_composite_type_field (sub
, "s",
2149 init_vector_type (bt
->builtin_int8
, 16));
2150 append_composite_type_field (t
, "b", sub
);
2152 sub
= arch_composite_type (gdbarch
, "__gdb_builtin_type_vnq",
2154 append_composite_type_field (sub
, "u",
2155 init_vector_type (bt
->builtin_uint128
, 1));
2156 append_composite_type_field (sub
, "s",
2157 init_vector_type (bt
->builtin_int128
, 1));
2158 append_composite_type_field (t
, "q", sub
);
2163 return tdep
->vnv_type
;
2166 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
2169 aarch64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
2171 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2173 if (reg
>= AARCH64_DWARF_X0
&& reg
<= AARCH64_DWARF_X0
+ 30)
2174 return AARCH64_X0_REGNUM
+ reg
- AARCH64_DWARF_X0
;
2176 if (reg
== AARCH64_DWARF_SP
)
2177 return AARCH64_SP_REGNUM
;
2179 if (reg
>= AARCH64_DWARF_V0
&& reg
<= AARCH64_DWARF_V0
+ 31)
2180 return AARCH64_V0_REGNUM
+ reg
- AARCH64_DWARF_V0
;
2182 if (reg
== AARCH64_DWARF_SVE_VG
)
2183 return AARCH64_SVE_VG_REGNUM
;
2185 if (reg
== AARCH64_DWARF_SVE_FFR
)
2186 return AARCH64_SVE_FFR_REGNUM
;
2188 if (reg
>= AARCH64_DWARF_SVE_P0
&& reg
<= AARCH64_DWARF_SVE_P0
+ 15)
2189 return AARCH64_SVE_P0_REGNUM
+ reg
- AARCH64_DWARF_SVE_P0
;
2191 if (reg
>= AARCH64_DWARF_SVE_Z0
&& reg
<= AARCH64_DWARF_SVE_Z0
+ 15)
2192 return AARCH64_SVE_Z0_REGNUM
+ reg
- AARCH64_DWARF_SVE_Z0
;
2194 if (tdep
->has_pauth ())
2196 if (reg
>= AARCH64_DWARF_PAUTH_DMASK
&& reg
<= AARCH64_DWARF_PAUTH_CMASK
)
2197 return tdep
->pauth_reg_base
+ reg
- AARCH64_DWARF_PAUTH_DMASK
;
2199 if (reg
== AARCH64_DWARF_PAUTH_RA_STATE
)
2200 return tdep
->pauth_ra_state_regnum
;
2206 /* Implement the "print_insn" gdbarch method. */
2209 aarch64_gdb_print_insn (bfd_vma memaddr
, disassemble_info
*info
)
2211 info
->symbols
= NULL
;
2212 return default_print_insn (memaddr
, info
);
2215 /* AArch64 BRK software debug mode instruction.
2216 Note that AArch64 code is always little-endian.
2217 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */
2218 constexpr gdb_byte aarch64_default_breakpoint
[] = {0x00, 0x00, 0x20, 0xd4};
2220 typedef BP_MANIPULATION (aarch64_default_breakpoint
) aarch64_breakpoint
;
2222 /* Extract from an array REGS containing the (raw) register state a
2223 function return value of type TYPE, and copy that, in virtual
2224 format, into VALBUF. */
2227 aarch64_extract_return_value (struct type
*type
, struct regcache
*regs
,
2230 struct gdbarch
*gdbarch
= regs
->arch ();
2231 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2233 struct type
*fundamental_type
;
2235 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2238 int len
= TYPE_LENGTH (fundamental_type
);
2240 for (int i
= 0; i
< elements
; i
++)
2242 int regno
= AARCH64_V0_REGNUM
+ i
;
2243 /* Enough space for a full vector register. */
2244 gdb_byte buf
[register_size (gdbarch
, regno
)];
2245 gdb_assert (len
<= sizeof (buf
));
2247 aarch64_debug_printf
2248 ("read HFA or HVA return value element %d from %s",
2249 i
+ 1, gdbarch_register_name (gdbarch
, regno
));
2251 regs
->cooked_read (regno
, buf
);
2253 memcpy (valbuf
, buf
, len
);
2257 else if (type
->code () == TYPE_CODE_INT
2258 || type
->code () == TYPE_CODE_CHAR
2259 || type
->code () == TYPE_CODE_BOOL
2260 || type
->code () == TYPE_CODE_PTR
2261 || TYPE_IS_REFERENCE (type
)
2262 || type
->code () == TYPE_CODE_ENUM
)
2264 /* If the type is a plain integer, then the access is
2265 straight-forward. Otherwise we have to play around a bit
2267 int len
= TYPE_LENGTH (type
);
2268 int regno
= AARCH64_X0_REGNUM
;
2273 /* By using store_unsigned_integer we avoid having to do
2274 anything special for small big-endian values. */
2275 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2276 store_unsigned_integer (valbuf
,
2277 (len
> X_REGISTER_SIZE
2278 ? X_REGISTER_SIZE
: len
), byte_order
, tmp
);
2279 len
-= X_REGISTER_SIZE
;
2280 valbuf
+= X_REGISTER_SIZE
;
2285 /* For a structure or union the behaviour is as if the value had
2286 been stored to word-aligned memory and then loaded into
2287 registers with 64-bit load instruction(s). */
2288 int len
= TYPE_LENGTH (type
);
2289 int regno
= AARCH64_X0_REGNUM
;
2290 bfd_byte buf
[X_REGISTER_SIZE
];
2294 regs
->cooked_read (regno
++, buf
);
2295 memcpy (valbuf
, buf
, len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2296 len
-= X_REGISTER_SIZE
;
2297 valbuf
+= X_REGISTER_SIZE
;
2303 /* Will a function return an aggregate type in memory or in a
2304 register? Return 0 if an aggregate type can be returned in a
2305 register, 1 if it must be returned in memory. */
2308 aarch64_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2310 type
= check_typedef (type
);
2312 struct type
*fundamental_type
;
2314 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2317 /* v0-v7 are used to return values and one register is allocated
2318 for one member. However, HFA or HVA has at most four members. */
2322 if (TYPE_LENGTH (type
) > 16)
2324 /* PCS B.6 Aggregates larger than 16 bytes are passed by
2325 invisible reference. */
2333 /* Write into appropriate registers a function return value of type
2334 TYPE, given in virtual format. */
2337 aarch64_store_return_value (struct type
*type
, struct regcache
*regs
,
2338 const gdb_byte
*valbuf
)
2340 struct gdbarch
*gdbarch
= regs
->arch ();
2341 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2343 struct type
*fundamental_type
;
2345 if (aapcs_is_vfp_call_or_return_candidate (type
, &elements
,
2348 int len
= TYPE_LENGTH (fundamental_type
);
2350 for (int i
= 0; i
< elements
; i
++)
2352 int regno
= AARCH64_V0_REGNUM
+ i
;
2353 /* Enough space for a full vector register. */
2354 gdb_byte tmpbuf
[register_size (gdbarch
, regno
)];
2355 gdb_assert (len
<= sizeof (tmpbuf
));
2357 aarch64_debug_printf
2358 ("write HFA or HVA return value element %d to %s",
2359 i
+ 1, gdbarch_register_name (gdbarch
, regno
));
2361 memcpy (tmpbuf
, valbuf
,
2362 len
> V_REGISTER_SIZE
? V_REGISTER_SIZE
: len
);
2363 regs
->cooked_write (regno
, tmpbuf
);
2367 else if (type
->code () == TYPE_CODE_INT
2368 || type
->code () == TYPE_CODE_CHAR
2369 || type
->code () == TYPE_CODE_BOOL
2370 || type
->code () == TYPE_CODE_PTR
2371 || TYPE_IS_REFERENCE (type
)
2372 || type
->code () == TYPE_CODE_ENUM
)
2374 if (TYPE_LENGTH (type
) <= X_REGISTER_SIZE
)
2376 /* Values of one word or less are zero/sign-extended and
2378 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2379 LONGEST val
= unpack_long (type
, valbuf
);
2381 store_signed_integer (tmpbuf
, X_REGISTER_SIZE
, byte_order
, val
);
2382 regs
->cooked_write (AARCH64_X0_REGNUM
, tmpbuf
);
2386 /* Integral values greater than one word are stored in
2387 consecutive registers starting with r0. This will always
2388 be a multiple of the regiser size. */
2389 int len
= TYPE_LENGTH (type
);
2390 int regno
= AARCH64_X0_REGNUM
;
2394 regs
->cooked_write (regno
++, valbuf
);
2395 len
-= X_REGISTER_SIZE
;
2396 valbuf
+= X_REGISTER_SIZE
;
2402 /* For a structure or union the behaviour is as if the value had
2403 been stored to word-aligned memory and then loaded into
2404 registers with 64-bit load instruction(s). */
2405 int len
= TYPE_LENGTH (type
);
2406 int regno
= AARCH64_X0_REGNUM
;
2407 bfd_byte tmpbuf
[X_REGISTER_SIZE
];
2411 memcpy (tmpbuf
, valbuf
,
2412 len
> X_REGISTER_SIZE
? X_REGISTER_SIZE
: len
);
2413 regs
->cooked_write (regno
++, tmpbuf
);
2414 len
-= X_REGISTER_SIZE
;
2415 valbuf
+= X_REGISTER_SIZE
;
2420 /* Implement the "return_value" gdbarch method. */
2422 static enum return_value_convention
2423 aarch64_return_value (struct gdbarch
*gdbarch
, struct value
*func_value
,
2424 struct type
*valtype
, struct regcache
*regcache
,
2425 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2428 if (valtype
->code () == TYPE_CODE_STRUCT
2429 || valtype
->code () == TYPE_CODE_UNION
2430 || valtype
->code () == TYPE_CODE_ARRAY
)
2432 if (aarch64_return_in_memory (gdbarch
, valtype
))
2434 aarch64_debug_printf ("return value in memory");
2435 return RETURN_VALUE_STRUCT_CONVENTION
;
2440 aarch64_store_return_value (valtype
, regcache
, writebuf
);
2443 aarch64_extract_return_value (valtype
, regcache
, readbuf
);
2445 aarch64_debug_printf ("return value in registers");
2447 return RETURN_VALUE_REGISTER_CONVENTION
;
2450 /* Implement the "get_longjmp_target" gdbarch method. */
2453 aarch64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2456 gdb_byte buf
[X_REGISTER_SIZE
];
2457 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2458 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2459 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2461 jb_addr
= get_frame_register_unsigned (frame
, AARCH64_X0_REGNUM
);
2463 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2467 *pc
= extract_unsigned_integer (buf
, X_REGISTER_SIZE
, byte_order
);
2471 /* Implement the "gen_return_address" gdbarch method. */
2474 aarch64_gen_return_address (struct gdbarch
*gdbarch
,
2475 struct agent_expr
*ax
, struct axs_value
*value
,
2478 value
->type
= register_type (gdbarch
, AARCH64_LR_REGNUM
);
2479 value
->kind
= axs_lvalue_register
;
2480 value
->u
.reg
= AARCH64_LR_REGNUM
;
2484 /* Return the pseudo register name corresponding to register regnum. */
2487 aarch64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
2489 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2491 static const char *const q_name
[] =
2493 "q0", "q1", "q2", "q3",
2494 "q4", "q5", "q6", "q7",
2495 "q8", "q9", "q10", "q11",
2496 "q12", "q13", "q14", "q15",
2497 "q16", "q17", "q18", "q19",
2498 "q20", "q21", "q22", "q23",
2499 "q24", "q25", "q26", "q27",
2500 "q28", "q29", "q30", "q31",
2503 static const char *const d_name
[] =
2505 "d0", "d1", "d2", "d3",
2506 "d4", "d5", "d6", "d7",
2507 "d8", "d9", "d10", "d11",
2508 "d12", "d13", "d14", "d15",
2509 "d16", "d17", "d18", "d19",
2510 "d20", "d21", "d22", "d23",
2511 "d24", "d25", "d26", "d27",
2512 "d28", "d29", "d30", "d31",
2515 static const char *const s_name
[] =
2517 "s0", "s1", "s2", "s3",
2518 "s4", "s5", "s6", "s7",
2519 "s8", "s9", "s10", "s11",
2520 "s12", "s13", "s14", "s15",
2521 "s16", "s17", "s18", "s19",
2522 "s20", "s21", "s22", "s23",
2523 "s24", "s25", "s26", "s27",
2524 "s28", "s29", "s30", "s31",
2527 static const char *const h_name
[] =
2529 "h0", "h1", "h2", "h3",
2530 "h4", "h5", "h6", "h7",
2531 "h8", "h9", "h10", "h11",
2532 "h12", "h13", "h14", "h15",
2533 "h16", "h17", "h18", "h19",
2534 "h20", "h21", "h22", "h23",
2535 "h24", "h25", "h26", "h27",
2536 "h28", "h29", "h30", "h31",
2539 static const char *const b_name
[] =
2541 "b0", "b1", "b2", "b3",
2542 "b4", "b5", "b6", "b7",
2543 "b8", "b9", "b10", "b11",
2544 "b12", "b13", "b14", "b15",
2545 "b16", "b17", "b18", "b19",
2546 "b20", "b21", "b22", "b23",
2547 "b24", "b25", "b26", "b27",
2548 "b28", "b29", "b30", "b31",
2551 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2553 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2554 return q_name
[p_regnum
- AARCH64_Q0_REGNUM
];
2556 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2557 return d_name
[p_regnum
- AARCH64_D0_REGNUM
];
2559 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2560 return s_name
[p_regnum
- AARCH64_S0_REGNUM
];
2562 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2563 return h_name
[p_regnum
- AARCH64_H0_REGNUM
];
2565 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2566 return b_name
[p_regnum
- AARCH64_B0_REGNUM
];
2568 if (tdep
->has_sve ())
2570 static const char *const sve_v_name
[] =
2572 "v0", "v1", "v2", "v3",
2573 "v4", "v5", "v6", "v7",
2574 "v8", "v9", "v10", "v11",
2575 "v12", "v13", "v14", "v15",
2576 "v16", "v17", "v18", "v19",
2577 "v20", "v21", "v22", "v23",
2578 "v24", "v25", "v26", "v27",
2579 "v28", "v29", "v30", "v31",
2582 if (p_regnum
>= AARCH64_SVE_V0_REGNUM
2583 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2584 return sve_v_name
[p_regnum
- AARCH64_SVE_V0_REGNUM
];
2587 /* RA_STATE is used for unwinding only. Do not assign it a name - this
2588 prevents it from being read by methods such as
2589 mi_cmd_trace_frame_collected. */
2590 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2593 internal_error (__FILE__
, __LINE__
,
2594 _("aarch64_pseudo_register_name: bad register number %d"),
2598 /* Implement the "pseudo_register_type" tdesc_arch_data method. */
2600 static struct type
*
2601 aarch64_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
2603 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2605 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2607 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2608 return aarch64_vnq_type (gdbarch
);
2610 if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2611 return aarch64_vnd_type (gdbarch
);
2613 if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2614 return aarch64_vns_type (gdbarch
);
2616 if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2617 return aarch64_vnh_type (gdbarch
);
2619 if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2620 return aarch64_vnb_type (gdbarch
);
2622 if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2623 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2624 return aarch64_vnv_type (gdbarch
);
2626 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2627 return builtin_type (gdbarch
)->builtin_uint64
;
2629 internal_error (__FILE__
, __LINE__
,
2630 _("aarch64_pseudo_register_type: bad register number %d"),
2634 /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */
2637 aarch64_pseudo_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
2638 struct reggroup
*group
)
2640 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2642 int p_regnum
= regnum
- gdbarch_num_regs (gdbarch
);
2644 if (p_regnum
>= AARCH64_Q0_REGNUM
&& p_regnum
< AARCH64_Q0_REGNUM
+ 32)
2645 return group
== all_reggroup
|| group
== vector_reggroup
;
2646 else if (p_regnum
>= AARCH64_D0_REGNUM
&& p_regnum
< AARCH64_D0_REGNUM
+ 32)
2647 return (group
== all_reggroup
|| group
== vector_reggroup
2648 || group
== float_reggroup
);
2649 else if (p_regnum
>= AARCH64_S0_REGNUM
&& p_regnum
< AARCH64_S0_REGNUM
+ 32)
2650 return (group
== all_reggroup
|| group
== vector_reggroup
2651 || group
== float_reggroup
);
2652 else if (p_regnum
>= AARCH64_H0_REGNUM
&& p_regnum
< AARCH64_H0_REGNUM
+ 32)
2653 return group
== all_reggroup
|| group
== vector_reggroup
;
2654 else if (p_regnum
>= AARCH64_B0_REGNUM
&& p_regnum
< AARCH64_B0_REGNUM
+ 32)
2655 return group
== all_reggroup
|| group
== vector_reggroup
;
2656 else if (tdep
->has_sve () && p_regnum
>= AARCH64_SVE_V0_REGNUM
2657 && p_regnum
< AARCH64_SVE_V0_REGNUM
+ AARCH64_V_REGS_NUM
)
2658 return group
== all_reggroup
|| group
== vector_reggroup
;
2659 /* RA_STATE is used for unwinding only. Do not assign it to any groups. */
2660 if (tdep
->has_pauth () && regnum
== tdep
->pauth_ra_state_regnum
)
2663 return group
== all_reggroup
;
2666 /* Helper for aarch64_pseudo_read_value. */
2668 static struct value
*
2669 aarch64_pseudo_read_value_1 (struct gdbarch
*gdbarch
,
2670 readable_regcache
*regcache
, int regnum_offset
,
2671 int regsize
, struct value
*result_value
)
2673 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2675 /* Enough space for a full vector register. */
2676 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2677 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2679 if (regcache
->raw_read (v_regnum
, reg_buf
) != REG_VALID
)
2680 mark_value_bytes_unavailable (result_value
, 0,
2681 TYPE_LENGTH (value_type (result_value
)));
2683 memcpy (value_contents_raw (result_value
), reg_buf
, regsize
);
2685 return result_value
;
2688 /* Implement the "pseudo_register_read_value" gdbarch method. */
2690 static struct value
*
2691 aarch64_pseudo_read_value (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
2694 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2695 struct value
*result_value
= allocate_value (register_type (gdbarch
, regnum
));
2697 VALUE_LVAL (result_value
) = lval_register
;
2698 VALUE_REGNUM (result_value
) = regnum
;
2700 regnum
-= gdbarch_num_regs (gdbarch
);
2702 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2703 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2704 regnum
- AARCH64_Q0_REGNUM
,
2705 Q_REGISTER_SIZE
, result_value
);
2707 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2708 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2709 regnum
- AARCH64_D0_REGNUM
,
2710 D_REGISTER_SIZE
, result_value
);
2712 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2713 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2714 regnum
- AARCH64_S0_REGNUM
,
2715 S_REGISTER_SIZE
, result_value
);
2717 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2718 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2719 regnum
- AARCH64_H0_REGNUM
,
2720 H_REGISTER_SIZE
, result_value
);
2722 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2723 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2724 regnum
- AARCH64_B0_REGNUM
,
2725 B_REGISTER_SIZE
, result_value
);
2727 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2728 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2729 return aarch64_pseudo_read_value_1 (gdbarch
, regcache
,
2730 regnum
- AARCH64_SVE_V0_REGNUM
,
2731 V_REGISTER_SIZE
, result_value
);
2733 gdb_assert_not_reached ("regnum out of bound");
2736 /* Helper for aarch64_pseudo_write. */
2739 aarch64_pseudo_write_1 (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2740 int regnum_offset
, int regsize
, const gdb_byte
*buf
)
2742 unsigned v_regnum
= AARCH64_V0_REGNUM
+ regnum_offset
;
2744 /* Enough space for a full vector register. */
2745 gdb_byte reg_buf
[register_size (gdbarch
, AARCH64_V0_REGNUM
)];
2746 gdb_static_assert (AARCH64_V0_REGNUM
== AARCH64_SVE_Z0_REGNUM
);
2748 /* Ensure the register buffer is zero, we want gdb writes of the
2749 various 'scalar' pseudo registers to behavior like architectural
2750 writes, register width bytes are written the remainder are set to
2752 memset (reg_buf
, 0, register_size (gdbarch
, AARCH64_V0_REGNUM
));
2754 memcpy (reg_buf
, buf
, regsize
);
2755 regcache
->raw_write (v_regnum
, reg_buf
);
2758 /* Implement the "pseudo_register_write" gdbarch method. */
2761 aarch64_pseudo_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
2762 int regnum
, const gdb_byte
*buf
)
2764 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2765 regnum
-= gdbarch_num_regs (gdbarch
);
2767 if (regnum
>= AARCH64_Q0_REGNUM
&& regnum
< AARCH64_Q0_REGNUM
+ 32)
2768 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2769 regnum
- AARCH64_Q0_REGNUM
, Q_REGISTER_SIZE
,
2772 if (regnum
>= AARCH64_D0_REGNUM
&& regnum
< AARCH64_D0_REGNUM
+ 32)
2773 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2774 regnum
- AARCH64_D0_REGNUM
, D_REGISTER_SIZE
,
2777 if (regnum
>= AARCH64_S0_REGNUM
&& regnum
< AARCH64_S0_REGNUM
+ 32)
2778 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2779 regnum
- AARCH64_S0_REGNUM
, S_REGISTER_SIZE
,
2782 if (regnum
>= AARCH64_H0_REGNUM
&& regnum
< AARCH64_H0_REGNUM
+ 32)
2783 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2784 regnum
- AARCH64_H0_REGNUM
, H_REGISTER_SIZE
,
2787 if (regnum
>= AARCH64_B0_REGNUM
&& regnum
< AARCH64_B0_REGNUM
+ 32)
2788 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2789 regnum
- AARCH64_B0_REGNUM
, B_REGISTER_SIZE
,
2792 if (tdep
->has_sve () && regnum
>= AARCH64_SVE_V0_REGNUM
2793 && regnum
< AARCH64_SVE_V0_REGNUM
+ 32)
2794 return aarch64_pseudo_write_1 (gdbarch
, regcache
,
2795 regnum
- AARCH64_SVE_V0_REGNUM
,
2796 V_REGISTER_SIZE
, buf
);
2798 gdb_assert_not_reached ("regnum out of bound");
2801 /* Callback function for user_reg_add. */
2803 static struct value
*
2804 value_of_aarch64_user_reg (struct frame_info
*frame
, const void *baton
)
2806 const int *reg_p
= (const int *) baton
;
2808 return value_of_register (*reg_p
, frame
);
2812 /* Implement the "software_single_step" gdbarch method, needed to
2813 single step through atomic sequences on AArch64. */
2815 static std::vector
<CORE_ADDR
>
2816 aarch64_software_single_step (struct regcache
*regcache
)
2818 struct gdbarch
*gdbarch
= regcache
->arch ();
2819 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
2820 const int insn_size
= 4;
2821 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
2822 CORE_ADDR pc
= regcache_read_pc (regcache
);
2823 CORE_ADDR breaks
[2] = { CORE_ADDR_MAX
, CORE_ADDR_MAX
};
2825 CORE_ADDR closing_insn
= 0;
2826 uint32_t insn
= read_memory_unsigned_integer (loc
, insn_size
,
2827 byte_order_for_code
);
2830 int bc_insn_count
= 0; /* Conditional branch instruction count. */
2831 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
2834 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2837 /* Look for a Load Exclusive instruction which begins the sequence. */
2838 if (inst
.opcode
->iclass
!= ldstexcl
|| bit (insn
, 22) == 0)
2841 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
2844 insn
= read_memory_unsigned_integer (loc
, insn_size
,
2845 byte_order_for_code
);
2847 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
2849 /* Check if the instruction is a conditional branch. */
2850 if (inst
.opcode
->iclass
== condbranch
)
2852 gdb_assert (inst
.operands
[0].type
== AARCH64_OPND_ADDR_PCREL19
);
2854 if (bc_insn_count
>= 1)
2857 /* It is, so we'll try to set a breakpoint at the destination. */
2858 breaks
[1] = loc
+ inst
.operands
[0].imm
.value
;
2864 /* Look for the Store Exclusive which closes the atomic sequence. */
2865 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22) == 0)
2872 /* We didn't find a closing Store Exclusive instruction, fall back. */
2876 /* Insert breakpoint after the end of the atomic sequence. */
2877 breaks
[0] = loc
+ insn_size
;
2879 /* Check for duplicated breakpoints, and also check that the second
2880 breakpoint is not within the atomic sequence. */
2882 && (breaks
[1] == breaks
[0]
2883 || (breaks
[1] >= pc
&& breaks
[1] <= closing_insn
)))
2884 last_breakpoint
= 0;
2886 std::vector
<CORE_ADDR
> next_pcs
;
2888 /* Insert the breakpoint at the end of the sequence, and one at the
2889 destination of the conditional branch, if it exists. */
2890 for (index
= 0; index
<= last_breakpoint
; index
++)
2891 next_pcs
.push_back (breaks
[index
]);
2896 struct aarch64_displaced_step_copy_insn_closure
2897 : public displaced_step_copy_insn_closure
2899 /* It is true when condition instruction, such as B.CON, TBZ, etc,
2900 is being displaced stepping. */
2903 /* PC adjustment offset after displaced stepping. If 0, then we don't
2904 write the PC back, assuming the PC is already the right address. */
2905 int32_t pc_adjust
= 0;
2908 /* Data when visiting instructions for displaced stepping. */
2910 struct aarch64_displaced_step_data
2912 struct aarch64_insn_data base
;
2914 /* The address where the instruction will be executed at. */
2916 /* Buffer of instructions to be copied to NEW_ADDR to execute. */
2917 uint32_t insn_buf
[AARCH64_DISPLACED_MODIFIED_INSNS
];
2918 /* Number of instructions in INSN_BUF. */
2919 unsigned insn_count
;
2920 /* Registers when doing displaced stepping. */
2921 struct regcache
*regs
;
2923 aarch64_displaced_step_copy_insn_closure
*dsc
;
2926 /* Implementation of aarch64_insn_visitor method "b". */
2929 aarch64_displaced_step_b (const int is_bl
, const int32_t offset
,
2930 struct aarch64_insn_data
*data
)
2932 struct aarch64_displaced_step_data
*dsd
2933 = (struct aarch64_displaced_step_data
*) data
;
2934 int64_t new_offset
= data
->insn_addr
- dsd
->new_addr
+ offset
;
2936 if (can_encode_int32 (new_offset
, 28))
2938 /* Emit B rather than BL, because executing BL on a new address
2939 will get the wrong address into LR. In order to avoid this,
2940 we emit B, and update LR if the instruction is BL. */
2941 emit_b (dsd
->insn_buf
, 0, new_offset
);
2947 emit_nop (dsd
->insn_buf
);
2949 dsd
->dsc
->pc_adjust
= offset
;
2955 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
2956 data
->insn_addr
+ 4);
2960 /* Implementation of aarch64_insn_visitor method "b_cond". */
2963 aarch64_displaced_step_b_cond (const unsigned cond
, const int32_t offset
,
2964 struct aarch64_insn_data
*data
)
2966 struct aarch64_displaced_step_data
*dsd
2967 = (struct aarch64_displaced_step_data
*) data
;
2969 /* GDB has to fix up PC after displaced step this instruction
2970 differently according to the condition is true or false. Instead
2971 of checking COND against conditional flags, we can use
2972 the following instructions, and GDB can tell how to fix up PC
2973 according to the PC value.
2975 B.COND TAKEN ; If cond is true, then jump to TAKEN.
2981 emit_bcond (dsd
->insn_buf
, cond
, 8);
2982 dsd
->dsc
->cond
= true;
2983 dsd
->dsc
->pc_adjust
= offset
;
2984 dsd
->insn_count
= 1;
2987 /* Dynamically allocate a new register. If we know the register
2988 statically, we should make it a global as above instead of using this
2991 static struct aarch64_register
2992 aarch64_register (unsigned num
, int is64
)
2994 return (struct aarch64_register
) { num
, is64
};
2997 /* Implementation of aarch64_insn_visitor method "cb". */
3000 aarch64_displaced_step_cb (const int32_t offset
, const int is_cbnz
,
3001 const unsigned rn
, int is64
,
3002 struct aarch64_insn_data
*data
)
3004 struct aarch64_displaced_step_data
*dsd
3005 = (struct aarch64_displaced_step_data
*) data
;
3007 /* The offset is out of range for a compare and branch
3008 instruction. We can use the following instructions instead:
3010 CBZ xn, TAKEN ; xn == 0, then jump to TAKEN.
3015 emit_cb (dsd
->insn_buf
, is_cbnz
, aarch64_register (rn
, is64
), 8);
3016 dsd
->insn_count
= 1;
3017 dsd
->dsc
->cond
= true;
3018 dsd
->dsc
->pc_adjust
= offset
;
3021 /* Implementation of aarch64_insn_visitor method "tb". */
3024 aarch64_displaced_step_tb (const int32_t offset
, int is_tbnz
,
3025 const unsigned rt
, unsigned bit
,
3026 struct aarch64_insn_data
*data
)
3028 struct aarch64_displaced_step_data
*dsd
3029 = (struct aarch64_displaced_step_data
*) data
;
3031 /* The offset is out of range for a test bit and branch
3032 instruction We can use the following instructions instead:
3034 TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN.
3040 emit_tb (dsd
->insn_buf
, is_tbnz
, bit
, aarch64_register (rt
, 1), 8);
3041 dsd
->insn_count
= 1;
3042 dsd
->dsc
->cond
= true;
3043 dsd
->dsc
->pc_adjust
= offset
;
3046 /* Implementation of aarch64_insn_visitor method "adr". */
3049 aarch64_displaced_step_adr (const int32_t offset
, const unsigned rd
,
3050 const int is_adrp
, struct aarch64_insn_data
*data
)
3052 struct aarch64_displaced_step_data
*dsd
3053 = (struct aarch64_displaced_step_data
*) data
;
3054 /* We know exactly the address the ADR{P,} instruction will compute.
3055 We can just write it to the destination register. */
3056 CORE_ADDR address
= data
->insn_addr
+ offset
;
3060 /* Clear the lower 12 bits of the offset to get the 4K page. */
3061 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
3065 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rd
,
3068 dsd
->dsc
->pc_adjust
= 4;
3069 emit_nop (dsd
->insn_buf
);
3070 dsd
->insn_count
= 1;
3073 /* Implementation of aarch64_insn_visitor method "ldr_literal". */
3076 aarch64_displaced_step_ldr_literal (const int32_t offset
, const int is_sw
,
3077 const unsigned rt
, const int is64
,
3078 struct aarch64_insn_data
*data
)
3080 struct aarch64_displaced_step_data
*dsd
3081 = (struct aarch64_displaced_step_data
*) data
;
3082 CORE_ADDR address
= data
->insn_addr
+ offset
;
3083 struct aarch64_memory_operand zero
= { MEMORY_OPERAND_OFFSET
, 0 };
3085 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_X0_REGNUM
+ rt
,
3089 dsd
->insn_count
= emit_ldrsw (dsd
->insn_buf
, aarch64_register (rt
, 1),
3090 aarch64_register (rt
, 1), zero
);
3092 dsd
->insn_count
= emit_ldr (dsd
->insn_buf
, aarch64_register (rt
, is64
),
3093 aarch64_register (rt
, 1), zero
);
3095 dsd
->dsc
->pc_adjust
= 4;
3098 /* Implementation of aarch64_insn_visitor method "others". */
3101 aarch64_displaced_step_others (const uint32_t insn
,
3102 struct aarch64_insn_data
*data
)
3104 struct aarch64_displaced_step_data
*dsd
3105 = (struct aarch64_displaced_step_data
*) data
;
3107 uint32_t masked_insn
= (insn
& CLEAR_Rn_MASK
);
3108 if (masked_insn
== BLR
)
3110 /* Emit a BR to the same register and then update LR to the original
3111 address (similar to aarch64_displaced_step_b). */
3112 aarch64_emit_insn (dsd
->insn_buf
, insn
& 0xffdfffff);
3113 regcache_cooked_write_unsigned (dsd
->regs
, AARCH64_LR_REGNUM
,
3114 data
->insn_addr
+ 4);
3117 aarch64_emit_insn (dsd
->insn_buf
, insn
);
3118 dsd
->insn_count
= 1;
3120 if (masked_insn
== RET
|| masked_insn
== BR
|| masked_insn
== BLR
)
3121 dsd
->dsc
->pc_adjust
= 0;
3123 dsd
->dsc
->pc_adjust
= 4;
3126 static const struct aarch64_insn_visitor visitor
=
3128 aarch64_displaced_step_b
,
3129 aarch64_displaced_step_b_cond
,
3130 aarch64_displaced_step_cb
,
3131 aarch64_displaced_step_tb
,
3132 aarch64_displaced_step_adr
,
3133 aarch64_displaced_step_ldr_literal
,
3134 aarch64_displaced_step_others
,
3137 /* Implement the "displaced_step_copy_insn" gdbarch method. */
3139 displaced_step_copy_insn_closure_up
3140 aarch64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
3141 CORE_ADDR from
, CORE_ADDR to
,
3142 struct regcache
*regs
)
3144 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
3145 uint32_t insn
= read_memory_unsigned_integer (from
, 4, byte_order_for_code
);
3146 struct aarch64_displaced_step_data dsd
;
3149 if (aarch64_decode_insn (insn
, &inst
, 1, NULL
) != 0)
3152 /* Look for a Load Exclusive instruction which begins the sequence. */
3153 if (inst
.opcode
->iclass
== ldstexcl
&& bit (insn
, 22))
3155 /* We can't displaced step atomic sequences. */
3159 std::unique_ptr
<aarch64_displaced_step_copy_insn_closure
> dsc
3160 (new aarch64_displaced_step_copy_insn_closure
);
3161 dsd
.base
.insn_addr
= from
;
3164 dsd
.dsc
= dsc
.get ();
3166 aarch64_relocate_instruction (insn
, &visitor
,
3167 (struct aarch64_insn_data
*) &dsd
);
3168 gdb_assert (dsd
.insn_count
<= AARCH64_DISPLACED_MODIFIED_INSNS
);
3170 if (dsd
.insn_count
!= 0)
3174 /* Instruction can be relocated to scratch pad. Copy
3175 relocated instruction(s) there. */
3176 for (i
= 0; i
< dsd
.insn_count
; i
++)
3178 displaced_debug_printf ("writing insn %.8x at %s",
3180 paddress (gdbarch
, to
+ i
* 4));
3182 write_memory_unsigned_integer (to
+ i
* 4, 4, byte_order_for_code
,
3183 (ULONGEST
) dsd
.insn_buf
[i
]);
3191 /* This is a work around for a problem with g++ 4.8. */
3192 return displaced_step_copy_insn_closure_up (dsc
.release ());
3195 /* Implement the "displaced_step_fixup" gdbarch method. */
3198 aarch64_displaced_step_fixup (struct gdbarch
*gdbarch
,
3199 struct displaced_step_copy_insn_closure
*dsc_
,
3200 CORE_ADDR from
, CORE_ADDR to
,
3201 struct regcache
*regs
)
3203 aarch64_displaced_step_copy_insn_closure
*dsc
3204 = (aarch64_displaced_step_copy_insn_closure
*) dsc_
;
3208 regcache_cooked_read_unsigned (regs
, AARCH64_PC_REGNUM
, &pc
);
3210 displaced_debug_printf ("PC after stepping: %s (was %s).",
3211 paddress (gdbarch
, pc
), paddress (gdbarch
, to
));
3215 displaced_debug_printf ("[Conditional] pc_adjust before: %d",
3220 /* Condition is true. */
3222 else if (pc
- to
== 4)
3224 /* Condition is false. */
3228 gdb_assert_not_reached ("Unexpected PC value after displaced stepping");
3230 displaced_debug_printf ("[Conditional] pc_adjust after: %d",
3234 displaced_debug_printf ("%s PC by %d",
3235 dsc
->pc_adjust
? "adjusting" : "not adjusting",
3238 if (dsc
->pc_adjust
!= 0)
3240 /* Make sure the previous instruction was executed (that is, the PC
3241 has changed). If the PC didn't change, then discard the adjustment
3242 offset. Otherwise we may skip an instruction before its execution
3246 displaced_debug_printf ("PC did not move. Discarding PC adjustment.");
3250 displaced_debug_printf ("fixup: set PC to %s:%d",
3251 paddress (gdbarch
, from
), dsc
->pc_adjust
);
3253 regcache_cooked_write_unsigned (regs
, AARCH64_PC_REGNUM
,
3254 from
+ dsc
->pc_adjust
);
3258 /* Implement the "displaced_step_hw_singlestep" gdbarch method. */
3261 aarch64_displaced_step_hw_singlestep (struct gdbarch
*gdbarch
)
3266 /* Get the correct target description for the given VQ value.
3267 If VQ is zero then it is assumed SVE is not supported.
3268 (It is not possible to set VQ to zero on an SVE system).
3270 MTE_P indicates the presence of the Memory Tagging Extension feature. */
3273 aarch64_read_description (uint64_t vq
, bool pauth_p
, bool mte_p
)
3275 if (vq
> AARCH64_MAX_SVE_VQ
)
3276 error (_("VQ is %" PRIu64
", maximum supported value is %d"), vq
,
3277 AARCH64_MAX_SVE_VQ
);
3279 struct target_desc
*tdesc
= tdesc_aarch64_list
[vq
][pauth_p
][mte_p
];
3283 tdesc
= aarch64_create_target_description (vq
, pauth_p
, mte_p
);
3284 tdesc_aarch64_list
[vq
][pauth_p
][mte_p
] = tdesc
;
3290 /* Return the VQ used when creating the target description TDESC. */
3293 aarch64_get_tdesc_vq (const struct target_desc
*tdesc
)
3295 const struct tdesc_feature
*feature_sve
;
3297 if (!tdesc_has_registers (tdesc
))
3300 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3302 if (feature_sve
== nullptr)
3305 uint64_t vl
= tdesc_register_bitsize (feature_sve
,
3306 aarch64_sve_register_names
[0]) / 8;
3307 return sve_vq_from_vl (vl
);
3310 /* Add all the expected register sets into GDBARCH. */
3313 aarch64_add_reggroups (struct gdbarch
*gdbarch
)
3315 reggroup_add (gdbarch
, general_reggroup
);
3316 reggroup_add (gdbarch
, float_reggroup
);
3317 reggroup_add (gdbarch
, system_reggroup
);
3318 reggroup_add (gdbarch
, vector_reggroup
);
3319 reggroup_add (gdbarch
, all_reggroup
);
3320 reggroup_add (gdbarch
, save_reggroup
);
3321 reggroup_add (gdbarch
, restore_reggroup
);
3324 /* Implement the "cannot_store_register" gdbarch method. */
3327 aarch64_cannot_store_register (struct gdbarch
*gdbarch
, int regnum
)
3329 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3331 if (!tdep
->has_pauth ())
3334 /* Pointer authentication registers are read-only. */
3335 return (regnum
== AARCH64_PAUTH_DMASK_REGNUM (tdep
->pauth_reg_base
)
3336 || regnum
== AARCH64_PAUTH_CMASK_REGNUM (tdep
->pauth_reg_base
));
3339 /* Initialize the current architecture based on INFO. If possible,
3340 re-use an architecture from ARCHES, which is a list of
3341 architectures already created during this debugging session.
3343 Called e.g. at program startup, when reading a core file, and when
3344 reading a binary file. */
3346 static struct gdbarch
*
3347 aarch64_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
3349 const struct tdesc_feature
*feature_core
, *feature_fpu
, *feature_sve
;
3350 const struct tdesc_feature
*feature_pauth
;
3351 bool valid_p
= true;
3352 int i
, num_regs
= 0, num_pseudo_regs
= 0;
3353 int first_pauth_regnum
= -1, pauth_ra_state_offset
= -1;
3354 int first_mte_regnum
= -1;
3356 /* Use the vector length passed via the target info. Here -1 is used for no
3357 SVE, and 0 is unset. If unset then use the vector length from the existing
3360 if (info
.id
== (int *) -1)
3362 else if (info
.id
!= 0)
3363 vq
= (uint64_t) info
.id
;
3365 vq
= aarch64_get_tdesc_vq (info
.target_desc
);
3367 if (vq
> AARCH64_MAX_SVE_VQ
)
3368 internal_error (__FILE__
, __LINE__
, _("VQ out of bounds: %s (max %d)"),
3369 pulongest (vq
), AARCH64_MAX_SVE_VQ
);
3371 /* If there is already a candidate, use it. */
3372 for (gdbarch_list
*best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
3373 best_arch
!= nullptr;
3374 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
3376 struct gdbarch_tdep
*tdep
= gdbarch_tdep (best_arch
->gdbarch
);
3377 if (tdep
&& tdep
->vq
== vq
)
3378 return best_arch
->gdbarch
;
3381 /* Ensure we always have a target descriptor, and that it is for the given VQ
3383 const struct target_desc
*tdesc
= info
.target_desc
;
3384 if (!tdesc_has_registers (tdesc
) || vq
!= aarch64_get_tdesc_vq (tdesc
))
3385 tdesc
= aarch64_read_description (vq
, false, false);
3388 feature_core
= tdesc_find_feature (tdesc
,"org.gnu.gdb.aarch64.core");
3389 feature_fpu
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.fpu");
3390 feature_sve
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.sve");
3391 feature_pauth
= tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.pauth");
3392 const struct tdesc_feature
*feature_mte
3393 = tdesc_find_feature (tdesc
, "org.gnu.gdb.aarch64.mte");
3395 if (feature_core
== nullptr)
3398 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
3400 /* Validate the description provides the mandatory core R registers
3401 and allocate their numbers. */
3402 for (i
= 0; i
< ARRAY_SIZE (aarch64_r_register_names
); i
++)
3403 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
.get (),
3404 AARCH64_X0_REGNUM
+ i
,
3405 aarch64_r_register_names
[i
]);
3407 num_regs
= AARCH64_X0_REGNUM
+ i
;
3409 /* Add the V registers. */
3410 if (feature_fpu
!= nullptr)
3412 if (feature_sve
!= nullptr)
3413 error (_("Program contains both fpu and SVE features."));
3415 /* Validate the description provides the mandatory V registers
3416 and allocate their numbers. */
3417 for (i
= 0; i
< ARRAY_SIZE (aarch64_v_register_names
); i
++)
3418 valid_p
&= tdesc_numbered_register (feature_fpu
, tdesc_data
.get (),
3419 AARCH64_V0_REGNUM
+ i
,
3420 aarch64_v_register_names
[i
]);
3422 num_regs
= AARCH64_V0_REGNUM
+ i
;
3425 /* Add the SVE registers. */
3426 if (feature_sve
!= nullptr)
3428 /* Validate the description provides the mandatory SVE registers
3429 and allocate their numbers. */
3430 for (i
= 0; i
< ARRAY_SIZE (aarch64_sve_register_names
); i
++)
3431 valid_p
&= tdesc_numbered_register (feature_sve
, tdesc_data
.get (),
3432 AARCH64_SVE_Z0_REGNUM
+ i
,
3433 aarch64_sve_register_names
[i
]);
3435 num_regs
= AARCH64_SVE_Z0_REGNUM
+ i
;
3436 num_pseudo_regs
+= 32; /* add the Vn register pseudos. */
3439 if (feature_fpu
!= nullptr || feature_sve
!= nullptr)
3441 num_pseudo_regs
+= 32; /* add the Qn scalar register pseudos */
3442 num_pseudo_regs
+= 32; /* add the Dn scalar register pseudos */
3443 num_pseudo_regs
+= 32; /* add the Sn scalar register pseudos */
3444 num_pseudo_regs
+= 32; /* add the Hn scalar register pseudos */
3445 num_pseudo_regs
+= 32; /* add the Bn scalar register pseudos */
3448 /* Add the pauth registers. */
3449 if (feature_pauth
!= NULL
)
3451 first_pauth_regnum
= num_regs
;
3452 pauth_ra_state_offset
= num_pseudo_regs
;
3453 /* Validate the descriptor provides the mandatory PAUTH registers and
3454 allocate their numbers. */
3455 for (i
= 0; i
< ARRAY_SIZE (aarch64_pauth_register_names
); i
++)
3456 valid_p
&= tdesc_numbered_register (feature_pauth
, tdesc_data
.get (),
3457 first_pauth_regnum
+ i
,
3458 aarch64_pauth_register_names
[i
]);
3461 num_pseudo_regs
+= 1; /* Count RA_STATE pseudo register. */
3464 /* Add the MTE registers. */
3465 if (feature_mte
!= NULL
)
3467 first_mte_regnum
= num_regs
;
3468 /* Validate the descriptor provides the mandatory MTE registers and
3469 allocate their numbers. */
3470 for (i
= 0; i
< ARRAY_SIZE (aarch64_mte_register_names
); i
++)
3471 valid_p
&= tdesc_numbered_register (feature_mte
, tdesc_data
.get (),
3472 first_mte_regnum
+ i
,
3473 aarch64_mte_register_names
[i
]);
3481 /* AArch64 code is always little-endian. */
3482 info
.byte_order_for_code
= BFD_ENDIAN_LITTLE
;
3484 struct gdbarch_tdep
*tdep
= XCNEW (struct gdbarch_tdep
);
3485 struct gdbarch
*gdbarch
= gdbarch_alloc (&info
, tdep
);
3487 /* This should be low enough for everything. */
3488 tdep
->lowest_pc
= 0x20;
3489 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
3490 tdep
->jb_elt_size
= 8;
3492 tdep
->pauth_reg_base
= first_pauth_regnum
;
3493 tdep
->pauth_ra_state_regnum
= (feature_pauth
== NULL
) ? -1
3494 : pauth_ra_state_offset
+ num_regs
;
3495 tdep
->mte_reg_base
= first_mte_regnum
;
3497 set_gdbarch_push_dummy_call (gdbarch
, aarch64_push_dummy_call
);
3498 set_gdbarch_frame_align (gdbarch
, aarch64_frame_align
);
3500 /* Advance PC across function entry code. */
3501 set_gdbarch_skip_prologue (gdbarch
, aarch64_skip_prologue
);
3503 /* The stack grows downward. */
3504 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
3506 /* Breakpoint manipulation. */
3507 set_gdbarch_breakpoint_kind_from_pc (gdbarch
,
3508 aarch64_breakpoint::kind_from_pc
);
3509 set_gdbarch_sw_breakpoint_from_kind (gdbarch
,
3510 aarch64_breakpoint::bp_from_kind
);
3511 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
3512 set_gdbarch_software_single_step (gdbarch
, aarch64_software_single_step
);
3514 /* Information about registers, etc. */
3515 set_gdbarch_sp_regnum (gdbarch
, AARCH64_SP_REGNUM
);
3516 set_gdbarch_pc_regnum (gdbarch
, AARCH64_PC_REGNUM
);
3517 set_gdbarch_num_regs (gdbarch
, num_regs
);
3519 set_gdbarch_num_pseudo_regs (gdbarch
, num_pseudo_regs
);
3520 set_gdbarch_pseudo_register_read_value (gdbarch
, aarch64_pseudo_read_value
);
3521 set_gdbarch_pseudo_register_write (gdbarch
, aarch64_pseudo_write
);
3522 set_tdesc_pseudo_register_name (gdbarch
, aarch64_pseudo_register_name
);
3523 set_tdesc_pseudo_register_type (gdbarch
, aarch64_pseudo_register_type
);
3524 set_tdesc_pseudo_register_reggroup_p (gdbarch
,
3525 aarch64_pseudo_register_reggroup_p
);
3526 set_gdbarch_cannot_store_register (gdbarch
, aarch64_cannot_store_register
);
3529 set_gdbarch_short_bit (gdbarch
, 16);
3530 set_gdbarch_int_bit (gdbarch
, 32);
3531 set_gdbarch_float_bit (gdbarch
, 32);
3532 set_gdbarch_double_bit (gdbarch
, 64);
3533 set_gdbarch_long_double_bit (gdbarch
, 128);
3534 set_gdbarch_long_bit (gdbarch
, 64);
3535 set_gdbarch_long_long_bit (gdbarch
, 64);
3536 set_gdbarch_ptr_bit (gdbarch
, 64);
3537 set_gdbarch_char_signed (gdbarch
, 0);
3538 set_gdbarch_wchar_signed (gdbarch
, 0);
3539 set_gdbarch_float_format (gdbarch
, floatformats_ieee_single
);
3540 set_gdbarch_double_format (gdbarch
, floatformats_ieee_double
);
3541 set_gdbarch_long_double_format (gdbarch
, floatformats_ia64_quad
);
3542 set_gdbarch_type_align (gdbarch
, aarch64_type_align
);
3544 /* Internal <-> external register number maps. */
3545 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, aarch64_dwarf_reg_to_regnum
);
3547 /* Returning results. */
3548 set_gdbarch_return_value (gdbarch
, aarch64_return_value
);
3551 set_gdbarch_print_insn (gdbarch
, aarch64_gdb_print_insn
);
3553 /* Virtual tables. */
3554 set_gdbarch_vbit_in_delta (gdbarch
, 1);
3556 /* Register architecture. */
3557 aarch64_add_reggroups (gdbarch
);
3559 /* Hook in the ABI-specific overrides, if they have been registered. */
3560 info
.target_desc
= tdesc
;
3561 info
.tdesc_data
= tdesc_data
.get ();
3562 gdbarch_init_osabi (info
, gdbarch
);
3564 dwarf2_frame_set_init_reg (gdbarch
, aarch64_dwarf2_frame_init_reg
);
3565 /* Register DWARF CFA vendor handler. */
3566 set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch
,
3567 aarch64_execute_dwarf_cfa_vendor_op
);
3569 /* Permanent/Program breakpoint handling. */
3570 set_gdbarch_program_breakpoint_here_p (gdbarch
,
3571 aarch64_program_breakpoint_here_p
);
3573 /* Add some default predicates. */
3574 frame_unwind_append_unwinder (gdbarch
, &aarch64_stub_unwind
);
3575 dwarf2_append_unwinders (gdbarch
);
3576 frame_unwind_append_unwinder (gdbarch
, &aarch64_prologue_unwind
);
3578 frame_base_set_default (gdbarch
, &aarch64_normal_base
);
3580 /* Now we have tuned the configuration, set a few final things,
3581 based on what the OS ABI has told us. */
3583 if (tdep
->jb_pc
>= 0)
3584 set_gdbarch_get_longjmp_target (gdbarch
, aarch64_get_longjmp_target
);
3586 set_gdbarch_gen_return_address (gdbarch
, aarch64_gen_return_address
);
3588 set_gdbarch_get_pc_address_flags (gdbarch
, aarch64_get_pc_address_flags
);
3590 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
3592 /* Add standard register aliases. */
3593 for (i
= 0; i
< ARRAY_SIZE (aarch64_register_aliases
); i
++)
3594 user_reg_add (gdbarch
, aarch64_register_aliases
[i
].name
,
3595 value_of_aarch64_user_reg
,
3596 &aarch64_register_aliases
[i
].regnum
);
3598 register_aarch64_ravenscar_ops (gdbarch
);
3604 aarch64_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
3606 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3611 fprintf_unfiltered (file
, _("aarch64_dump_tdep: Lowest pc = 0x%s"),
3612 paddress (gdbarch
, tdep
->lowest_pc
));
3618 static void aarch64_process_record_test (void);
3622 void _initialize_aarch64_tdep ();
3624 _initialize_aarch64_tdep ()
3626 gdbarch_register (bfd_arch_aarch64
, aarch64_gdbarch_init
,
3629 /* Debug this file's internals. */
3630 add_setshow_boolean_cmd ("aarch64", class_maintenance
, &aarch64_debug
, _("\
3631 Set AArch64 debugging."), _("\
3632 Show AArch64 debugging."), _("\
3633 When on, AArch64 specific debugging is enabled."),
3636 &setdebuglist
, &showdebuglist
);
3639 selftests::register_test ("aarch64-analyze-prologue",
3640 selftests::aarch64_analyze_prologue_test
);
3641 selftests::register_test ("aarch64-process-record",
3642 selftests::aarch64_process_record_test
);
3646 /* AArch64 process record-replay related structures, defines etc. */
3648 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \
3651 unsigned int reg_len = LENGTH; \
3654 REGS = XNEWVEC (uint32_t, reg_len); \
3655 memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \
3660 #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \
3663 unsigned int mem_len = LENGTH; \
3666 MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \
3667 memcpy(&MEMS->len, &RECORD_BUF[0], \
3668 sizeof(struct aarch64_mem_r) * LENGTH); \
3673 /* AArch64 record/replay structures and enumerations. */
3675 struct aarch64_mem_r
3677 uint64_t len
; /* Record length. */
3678 uint64_t addr
; /* Memory address. */
3681 enum aarch64_record_result
3683 AARCH64_RECORD_SUCCESS
,
3684 AARCH64_RECORD_UNSUPPORTED
,
3685 AARCH64_RECORD_UNKNOWN
3688 typedef struct insn_decode_record_t
3690 struct gdbarch
*gdbarch
;
3691 struct regcache
*regcache
;
3692 CORE_ADDR this_addr
; /* Address of insn to be recorded. */
3693 uint32_t aarch64_insn
; /* Insn to be recorded. */
3694 uint32_t mem_rec_count
; /* Count of memory records. */
3695 uint32_t reg_rec_count
; /* Count of register records. */
3696 uint32_t *aarch64_regs
; /* Registers to be recorded. */
3697 struct aarch64_mem_r
*aarch64_mems
; /* Memory locations to be recorded. */
3698 } insn_decode_record
;
3700 /* Record handler for data processing - register instructions. */
3703 aarch64_record_data_proc_reg (insn_decode_record
*aarch64_insn_r
)
3705 uint8_t reg_rd
, insn_bits24_27
, insn_bits21_23
;
3706 uint32_t record_buf
[4];
3708 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3709 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3710 insn_bits21_23
= bits (aarch64_insn_r
->aarch64_insn
, 21, 23);
3712 if (!bit (aarch64_insn_r
->aarch64_insn
, 28))
3716 /* Logical (shifted register). */
3717 if (insn_bits24_27
== 0x0a)
3718 setflags
= (bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03);
3720 else if (insn_bits24_27
== 0x0b)
3721 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3723 return AARCH64_RECORD_UNKNOWN
;
3725 record_buf
[0] = reg_rd
;
3726 aarch64_insn_r
->reg_rec_count
= 1;
3728 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3732 if (insn_bits24_27
== 0x0b)
3734 /* Data-processing (3 source). */
3735 record_buf
[0] = reg_rd
;
3736 aarch64_insn_r
->reg_rec_count
= 1;
3738 else if (insn_bits24_27
== 0x0a)
3740 if (insn_bits21_23
== 0x00)
3742 /* Add/subtract (with carry). */
3743 record_buf
[0] = reg_rd
;
3744 aarch64_insn_r
->reg_rec_count
= 1;
3745 if (bit (aarch64_insn_r
->aarch64_insn
, 29))
3747 record_buf
[1] = AARCH64_CPSR_REGNUM
;
3748 aarch64_insn_r
->reg_rec_count
= 2;
3751 else if (insn_bits21_23
== 0x02)
3753 /* Conditional compare (register) and conditional compare
3754 (immediate) instructions. */
3755 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3756 aarch64_insn_r
->reg_rec_count
= 1;
3758 else if (insn_bits21_23
== 0x04 || insn_bits21_23
== 0x06)
3760 /* Conditional select. */
3761 /* Data-processing (2 source). */
3762 /* Data-processing (1 source). */
3763 record_buf
[0] = reg_rd
;
3764 aarch64_insn_r
->reg_rec_count
= 1;
3767 return AARCH64_RECORD_UNKNOWN
;
3771 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3773 return AARCH64_RECORD_SUCCESS
;
3776 /* Record handler for data processing - immediate instructions. */
3779 aarch64_record_data_proc_imm (insn_decode_record
*aarch64_insn_r
)
3781 uint8_t reg_rd
, insn_bit23
, insn_bits24_27
, setflags
;
3782 uint32_t record_buf
[4];
3784 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3785 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
3786 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3788 if (insn_bits24_27
== 0x00 /* PC rel addressing. */
3789 || insn_bits24_27
== 0x03 /* Bitfield and Extract. */
3790 || (insn_bits24_27
== 0x02 && insn_bit23
)) /* Move wide (immediate). */
3792 record_buf
[0] = reg_rd
;
3793 aarch64_insn_r
->reg_rec_count
= 1;
3795 else if (insn_bits24_27
== 0x01)
3797 /* Add/Subtract (immediate). */
3798 setflags
= bit (aarch64_insn_r
->aarch64_insn
, 29);
3799 record_buf
[0] = reg_rd
;
3800 aarch64_insn_r
->reg_rec_count
= 1;
3802 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3804 else if (insn_bits24_27
== 0x02 && !insn_bit23
)
3806 /* Logical (immediate). */
3807 setflags
= bits (aarch64_insn_r
->aarch64_insn
, 29, 30) == 0x03;
3808 record_buf
[0] = reg_rd
;
3809 aarch64_insn_r
->reg_rec_count
= 1;
3811 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_CPSR_REGNUM
;
3814 return AARCH64_RECORD_UNKNOWN
;
3816 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3818 return AARCH64_RECORD_SUCCESS
;
3821 /* Record handler for branch, exception generation and system instructions. */
3824 aarch64_record_branch_except_sys (insn_decode_record
*aarch64_insn_r
)
3826 struct gdbarch_tdep
*tdep
= gdbarch_tdep (aarch64_insn_r
->gdbarch
);
3827 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits22_23
;
3828 uint32_t record_buf
[4];
3830 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
3831 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
3832 insn_bits22_23
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
3834 if (insn_bits28_31
== 0x0d)
3836 /* Exception generation instructions. */
3837 if (insn_bits24_27
== 0x04)
3839 if (!bits (aarch64_insn_r
->aarch64_insn
, 2, 4)
3840 && !bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
3841 && bits (aarch64_insn_r
->aarch64_insn
, 0, 1) == 0x01)
3843 ULONGEST svc_number
;
3845 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, 8,
3847 return tdep
->aarch64_syscall_record (aarch64_insn_r
->regcache
,
3851 return AARCH64_RECORD_UNSUPPORTED
;
3853 /* System instructions. */
3854 else if (insn_bits24_27
== 0x05 && insn_bits22_23
== 0x00)
3856 uint32_t reg_rt
, reg_crn
;
3858 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3859 reg_crn
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3861 /* Record rt in case of sysl and mrs instructions. */
3862 if (bit (aarch64_insn_r
->aarch64_insn
, 21))
3864 record_buf
[0] = reg_rt
;
3865 aarch64_insn_r
->reg_rec_count
= 1;
3867 /* Record cpsr for hint and msr(immediate) instructions. */
3868 else if (reg_crn
== 0x02 || reg_crn
== 0x04)
3870 record_buf
[0] = AARCH64_CPSR_REGNUM
;
3871 aarch64_insn_r
->reg_rec_count
= 1;
3874 /* Unconditional branch (register). */
3875 else if((insn_bits24_27
& 0x0e) == 0x06)
3877 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3878 if (bits (aarch64_insn_r
->aarch64_insn
, 21, 22) == 0x01)
3879 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3882 return AARCH64_RECORD_UNKNOWN
;
3884 /* Unconditional branch (immediate). */
3885 else if ((insn_bits28_31
& 0x07) == 0x01 && (insn_bits24_27
& 0x0c) == 0x04)
3887 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3888 if (bit (aarch64_insn_r
->aarch64_insn
, 31))
3889 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_LR_REGNUM
;
3892 /* Compare & branch (immediate), Test & branch (immediate) and
3893 Conditional branch (immediate). */
3894 record_buf
[aarch64_insn_r
->reg_rec_count
++] = AARCH64_PC_REGNUM
;
3896 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
3898 return AARCH64_RECORD_SUCCESS
;
3901 /* Record handler for advanced SIMD load and store instructions. */
3904 aarch64_record_asimd_load_store (insn_decode_record
*aarch64_insn_r
)
3907 uint64_t addr_offset
= 0;
3908 uint32_t record_buf
[24];
3909 uint64_t record_buf_mem
[24];
3910 uint32_t reg_rn
, reg_rt
;
3911 uint32_t reg_index
= 0, mem_index
= 0;
3912 uint8_t opcode_bits
, size_bits
;
3914 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
3915 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
3916 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
3917 opcode_bits
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
3918 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
, &address
);
3921 debug_printf ("Process record: Advanced SIMD load/store\n");
3923 /* Load/store single structure. */
3924 if (bit (aarch64_insn_r
->aarch64_insn
, 24))
3926 uint8_t sindex
, scale
, selem
, esize
, replicate
= 0;
3927 scale
= opcode_bits
>> 2;
3928 selem
= ((opcode_bits
& 0x02) |
3929 bit (aarch64_insn_r
->aarch64_insn
, 21)) + 1;
3933 if (size_bits
& 0x01)
3934 return AARCH64_RECORD_UNKNOWN
;
3937 if ((size_bits
>> 1) & 0x01)
3938 return AARCH64_RECORD_UNKNOWN
;
3939 if (size_bits
& 0x01)
3941 if (!((opcode_bits
>> 1) & 0x01))
3944 return AARCH64_RECORD_UNKNOWN
;
3948 if (bit (aarch64_insn_r
->aarch64_insn
, 22) && !(opcode_bits
& 0x01))
3955 return AARCH64_RECORD_UNKNOWN
;
3961 for (sindex
= 0; sindex
< selem
; sindex
++)
3963 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3964 reg_rt
= (reg_rt
+ 1) % 32;
3968 for (sindex
= 0; sindex
< selem
; sindex
++)
3970 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
3971 record_buf
[reg_index
++] = reg_rt
+ AARCH64_V0_REGNUM
;
3974 record_buf_mem
[mem_index
++] = esize
/ 8;
3975 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
3977 addr_offset
= addr_offset
+ (esize
/ 8);
3978 reg_rt
= (reg_rt
+ 1) % 32;
3982 /* Load/store multiple structure. */
3985 uint8_t selem
, esize
, rpt
, elements
;
3986 uint8_t eindex
, rindex
;
3988 esize
= 8 << size_bits
;
3989 if (bit (aarch64_insn_r
->aarch64_insn
, 30))
3990 elements
= 128 / esize
;
3992 elements
= 64 / esize
;
3994 switch (opcode_bits
)
3996 /*LD/ST4 (4 Registers). */
4001 /*LD/ST1 (4 Registers). */
4006 /*LD/ST3 (3 Registers). */
4011 /*LD/ST1 (3 Registers). */
4016 /*LD/ST1 (1 Register). */
4021 /*LD/ST2 (2 Registers). */
4026 /*LD/ST1 (2 Registers). */
4032 return AARCH64_RECORD_UNSUPPORTED
;
4035 for (rindex
= 0; rindex
< rpt
; rindex
++)
4036 for (eindex
= 0; eindex
< elements
; eindex
++)
4038 uint8_t reg_tt
, sindex
;
4039 reg_tt
= (reg_rt
+ rindex
) % 32;
4040 for (sindex
= 0; sindex
< selem
; sindex
++)
4042 if (bit (aarch64_insn_r
->aarch64_insn
, 22))
4043 record_buf
[reg_index
++] = reg_tt
+ AARCH64_V0_REGNUM
;
4046 record_buf_mem
[mem_index
++] = esize
/ 8;
4047 record_buf_mem
[mem_index
++] = address
+ addr_offset
;
4049 addr_offset
= addr_offset
+ (esize
/ 8);
4050 reg_tt
= (reg_tt
+ 1) % 32;
4055 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4056 record_buf
[reg_index
++] = reg_rn
;
4058 aarch64_insn_r
->reg_rec_count
= reg_index
;
4059 aarch64_insn_r
->mem_rec_count
= mem_index
/ 2;
4060 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4062 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4064 return AARCH64_RECORD_SUCCESS
;
4067 /* Record handler for load and store instructions. */
4070 aarch64_record_load_store (insn_decode_record
*aarch64_insn_r
)
4072 uint8_t insn_bits24_27
, insn_bits28_29
, insn_bits10_11
;
4073 uint8_t insn_bit23
, insn_bit21
;
4074 uint8_t opc
, size_bits
, ld_flag
, vector_flag
;
4075 uint32_t reg_rn
, reg_rt
, reg_rt2
;
4076 uint64_t datasize
, offset
;
4077 uint32_t record_buf
[8];
4078 uint64_t record_buf_mem
[8];
4081 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4082 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4083 insn_bits28_29
= bits (aarch64_insn_r
->aarch64_insn
, 28, 29);
4084 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4085 insn_bit23
= bit (aarch64_insn_r
->aarch64_insn
, 23);
4086 ld_flag
= bit (aarch64_insn_r
->aarch64_insn
, 22);
4087 vector_flag
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4088 reg_rt
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4089 reg_rn
= bits (aarch64_insn_r
->aarch64_insn
, 5, 9);
4090 reg_rt2
= bits (aarch64_insn_r
->aarch64_insn
, 10, 14);
4091 size_bits
= bits (aarch64_insn_r
->aarch64_insn
, 30, 31);
4093 /* Load/store exclusive. */
4094 if (insn_bits24_27
== 0x08 && insn_bits28_29
== 0x00)
4097 debug_printf ("Process record: load/store exclusive\n");
4101 record_buf
[0] = reg_rt
;
4102 aarch64_insn_r
->reg_rec_count
= 1;
4105 record_buf
[1] = reg_rt2
;
4106 aarch64_insn_r
->reg_rec_count
= 2;
4112 datasize
= (8 << size_bits
) * 2;
4114 datasize
= (8 << size_bits
);
4115 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4117 record_buf_mem
[0] = datasize
/ 8;
4118 record_buf_mem
[1] = address
;
4119 aarch64_insn_r
->mem_rec_count
= 1;
4122 /* Save register rs. */
4123 record_buf
[0] = bits (aarch64_insn_r
->aarch64_insn
, 16, 20);
4124 aarch64_insn_r
->reg_rec_count
= 1;
4128 /* Load register (literal) instructions decoding. */
4129 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x01)
4132 debug_printf ("Process record: load register (literal)\n");
4134 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4136 record_buf
[0] = reg_rt
;
4137 aarch64_insn_r
->reg_rec_count
= 1;
4139 /* All types of load/store pair instructions decoding. */
4140 else if ((insn_bits24_27
& 0x0a) == 0x08 && insn_bits28_29
== 0x02)
4143 debug_printf ("Process record: load/store pair\n");
4149 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4150 record_buf
[1] = reg_rt2
+ AARCH64_V0_REGNUM
;
4154 record_buf
[0] = reg_rt
;
4155 record_buf
[1] = reg_rt2
;
4157 aarch64_insn_r
->reg_rec_count
= 2;
4162 imm7_off
= bits (aarch64_insn_r
->aarch64_insn
, 15, 21);
4164 size_bits
= size_bits
>> 1;
4165 datasize
= 8 << (2 + size_bits
);
4166 offset
= (imm7_off
& 0x40) ? (~imm7_off
& 0x007f) + 1 : imm7_off
;
4167 offset
= offset
<< (2 + size_bits
);
4168 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4170 if (!((insn_bits24_27
& 0x0b) == 0x08 && insn_bit23
))
4172 if (imm7_off
& 0x40)
4173 address
= address
- offset
;
4175 address
= address
+ offset
;
4178 record_buf_mem
[0] = datasize
/ 8;
4179 record_buf_mem
[1] = address
;
4180 record_buf_mem
[2] = datasize
/ 8;
4181 record_buf_mem
[3] = address
+ (datasize
/ 8);
4182 aarch64_insn_r
->mem_rec_count
= 2;
4184 if (bit (aarch64_insn_r
->aarch64_insn
, 23))
4185 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4187 /* Load/store register (unsigned immediate) instructions. */
4188 else if ((insn_bits24_27
& 0x0b) == 0x09 && insn_bits28_29
== 0x03)
4190 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4200 if (size_bits
== 0x3 && vector_flag
== 0x0 && opc
== 0x2)
4202 /* PRFM (immediate) */
4203 return AARCH64_RECORD_SUCCESS
;
4205 else if (size_bits
== 0x2 && vector_flag
== 0x0 && opc
== 0x2)
4207 /* LDRSW (immediate) */
4221 debug_printf ("Process record: load/store (unsigned immediate):"
4222 " size %x V %d opc %x\n", size_bits
, vector_flag
,
4228 offset
= bits (aarch64_insn_r
->aarch64_insn
, 10, 21);
4229 datasize
= 8 << size_bits
;
4230 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4232 offset
= offset
<< size_bits
;
4233 address
= address
+ offset
;
4235 record_buf_mem
[0] = datasize
>> 3;
4236 record_buf_mem
[1] = address
;
4237 aarch64_insn_r
->mem_rec_count
= 1;
4242 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4244 record_buf
[0] = reg_rt
;
4245 aarch64_insn_r
->reg_rec_count
= 1;
4248 /* Load/store register (register offset) instructions. */
4249 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4250 && insn_bits10_11
== 0x02 && insn_bit21
)
4253 debug_printf ("Process record: load/store (register offset)\n");
4254 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4261 if (size_bits
!= 0x03)
4264 return AARCH64_RECORD_UNKNOWN
;
4268 ULONGEST reg_rm_val
;
4270 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
,
4271 bits (aarch64_insn_r
->aarch64_insn
, 16, 20), ®_rm_val
);
4272 if (bit (aarch64_insn_r
->aarch64_insn
, 12))
4273 offset
= reg_rm_val
<< size_bits
;
4275 offset
= reg_rm_val
;
4276 datasize
= 8 << size_bits
;
4277 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4279 address
= address
+ offset
;
4280 record_buf_mem
[0] = datasize
>> 3;
4281 record_buf_mem
[1] = address
;
4282 aarch64_insn_r
->mem_rec_count
= 1;
4287 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4289 record_buf
[0] = reg_rt
;
4290 aarch64_insn_r
->reg_rec_count
= 1;
4293 /* Load/store register (immediate and unprivileged) instructions. */
4294 else if ((insn_bits24_27
& 0x0b) == 0x08 && insn_bits28_29
== 0x03
4299 debug_printf ("Process record: load/store "
4300 "(immediate and unprivileged)\n");
4302 opc
= bits (aarch64_insn_r
->aarch64_insn
, 22, 23);
4309 if (size_bits
!= 0x03)
4312 return AARCH64_RECORD_UNKNOWN
;
4317 imm9_off
= bits (aarch64_insn_r
->aarch64_insn
, 12, 20);
4318 offset
= (imm9_off
& 0x0100) ? (((~imm9_off
) & 0x01ff) + 1) : imm9_off
;
4319 datasize
= 8 << size_bits
;
4320 regcache_raw_read_unsigned (aarch64_insn_r
->regcache
, reg_rn
,
4322 if (insn_bits10_11
!= 0x01)
4324 if (imm9_off
& 0x0100)
4325 address
= address
- offset
;
4327 address
= address
+ offset
;
4329 record_buf_mem
[0] = datasize
>> 3;
4330 record_buf_mem
[1] = address
;
4331 aarch64_insn_r
->mem_rec_count
= 1;
4336 record_buf
[0] = reg_rt
+ AARCH64_V0_REGNUM
;
4338 record_buf
[0] = reg_rt
;
4339 aarch64_insn_r
->reg_rec_count
= 1;
4341 if (insn_bits10_11
== 0x01 || insn_bits10_11
== 0x03)
4342 record_buf
[aarch64_insn_r
->reg_rec_count
++] = reg_rn
;
4344 /* Advanced SIMD load/store instructions. */
4346 return aarch64_record_asimd_load_store (aarch64_insn_r
);
4348 MEM_ALLOC (aarch64_insn_r
->aarch64_mems
, aarch64_insn_r
->mem_rec_count
,
4350 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4352 return AARCH64_RECORD_SUCCESS
;
4355 /* Record handler for data processing SIMD and floating point instructions. */
4358 aarch64_record_data_proc_simd_fp (insn_decode_record
*aarch64_insn_r
)
4360 uint8_t insn_bit21
, opcode
, rmode
, reg_rd
;
4361 uint8_t insn_bits24_27
, insn_bits28_31
, insn_bits10_11
, insn_bits12_15
;
4362 uint8_t insn_bits11_14
;
4363 uint32_t record_buf
[2];
4365 insn_bits24_27
= bits (aarch64_insn_r
->aarch64_insn
, 24, 27);
4366 insn_bits28_31
= bits (aarch64_insn_r
->aarch64_insn
, 28, 31);
4367 insn_bits10_11
= bits (aarch64_insn_r
->aarch64_insn
, 10, 11);
4368 insn_bits12_15
= bits (aarch64_insn_r
->aarch64_insn
, 12, 15);
4369 insn_bits11_14
= bits (aarch64_insn_r
->aarch64_insn
, 11, 14);
4370 opcode
= bits (aarch64_insn_r
->aarch64_insn
, 16, 18);
4371 rmode
= bits (aarch64_insn_r
->aarch64_insn
, 19, 20);
4372 reg_rd
= bits (aarch64_insn_r
->aarch64_insn
, 0, 4);
4373 insn_bit21
= bit (aarch64_insn_r
->aarch64_insn
, 21);
4376 debug_printf ("Process record: data processing SIMD/FP: ");
4378 if ((insn_bits28_31
& 0x05) == 0x01 && insn_bits24_27
== 0x0e)
4380 /* Floating point - fixed point conversion instructions. */
4384 debug_printf ("FP - fixed point conversion");
4386 if ((opcode
>> 1) == 0x0 && rmode
== 0x03)
4387 record_buf
[0] = reg_rd
;
4389 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4391 /* Floating point - conditional compare instructions. */
4392 else if (insn_bits10_11
== 0x01)
4395 debug_printf ("FP - conditional compare");
4397 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4399 /* Floating point - data processing (2-source) and
4400 conditional select instructions. */
4401 else if (insn_bits10_11
== 0x02 || insn_bits10_11
== 0x03)
4404 debug_printf ("FP - DP (2-source)");
4406 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4408 else if (insn_bits10_11
== 0x00)
4410 /* Floating point - immediate instructions. */
4411 if ((insn_bits12_15
& 0x01) == 0x01
4412 || (insn_bits12_15
& 0x07) == 0x04)
4415 debug_printf ("FP - immediate");
4416 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4418 /* Floating point - compare instructions. */
4419 else if ((insn_bits12_15
& 0x03) == 0x02)
4422 debug_printf ("FP - immediate");
4423 record_buf
[0] = AARCH64_CPSR_REGNUM
;
4425 /* Floating point - integer conversions instructions. */
4426 else if (insn_bits12_15
== 0x00)
4428 /* Convert float to integer instruction. */
4429 if (!(opcode
>> 1) || ((opcode
>> 1) == 0x02 && !rmode
))
4432 debug_printf ("float to int conversion");
4434 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4436 /* Convert integer to float instruction. */
4437 else if ((opcode
>> 1) == 0x01 && !rmode
)
4440 debug_printf ("int to float conversion");
4442 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4444 /* Move float to integer instruction. */
4445 else if ((opcode
>> 1) == 0x03)
4448 debug_printf ("move float to int");
4450 if (!(opcode
& 0x01))
4451 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4453 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4456 return AARCH64_RECORD_UNKNOWN
;
4459 return AARCH64_RECORD_UNKNOWN
;
4462 return AARCH64_RECORD_UNKNOWN
;
4464 else if ((insn_bits28_31
& 0x09) == 0x00 && insn_bits24_27
== 0x0e)
4467 debug_printf ("SIMD copy");
4469 /* Advanced SIMD copy instructions. */
4470 if (!bits (aarch64_insn_r
->aarch64_insn
, 21, 23)
4471 && !bit (aarch64_insn_r
->aarch64_insn
, 15)
4472 && bit (aarch64_insn_r
->aarch64_insn
, 10))
4474 if (insn_bits11_14
== 0x05 || insn_bits11_14
== 0x07)
4475 record_buf
[0] = reg_rd
+ AARCH64_X0_REGNUM
;
4477 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4480 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4482 /* All remaining floating point or advanced SIMD instructions. */
4486 debug_printf ("all remain");
4488 record_buf
[0] = reg_rd
+ AARCH64_V0_REGNUM
;
4492 debug_printf ("\n");
4494 /* Record the V/X register. */
4495 aarch64_insn_r
->reg_rec_count
++;
4497 /* Some of these instructions may set bits in the FPSR, so record it
4499 record_buf
[1] = AARCH64_FPSR_REGNUM
;
4500 aarch64_insn_r
->reg_rec_count
++;
4502 gdb_assert (aarch64_insn_r
->reg_rec_count
== 2);
4503 REG_ALLOC (aarch64_insn_r
->aarch64_regs
, aarch64_insn_r
->reg_rec_count
,
4505 return AARCH64_RECORD_SUCCESS
;
4508 /* Decodes insns type and invokes its record handler. */
4511 aarch64_record_decode_insn_handler (insn_decode_record
*aarch64_insn_r
)
4513 uint32_t ins_bit25
, ins_bit26
, ins_bit27
, ins_bit28
;
4515 ins_bit25
= bit (aarch64_insn_r
->aarch64_insn
, 25);
4516 ins_bit26
= bit (aarch64_insn_r
->aarch64_insn
, 26);
4517 ins_bit27
= bit (aarch64_insn_r
->aarch64_insn
, 27);
4518 ins_bit28
= bit (aarch64_insn_r
->aarch64_insn
, 28);
4520 /* Data processing - immediate instructions. */
4521 if (!ins_bit26
&& !ins_bit27
&& ins_bit28
)
4522 return aarch64_record_data_proc_imm (aarch64_insn_r
);
4524 /* Branch, exception generation and system instructions. */
4525 if (ins_bit26
&& !ins_bit27
&& ins_bit28
)
4526 return aarch64_record_branch_except_sys (aarch64_insn_r
);
4528 /* Load and store instructions. */
4529 if (!ins_bit25
&& ins_bit27
)
4530 return aarch64_record_load_store (aarch64_insn_r
);
4532 /* Data processing - register instructions. */
4533 if (ins_bit25
&& !ins_bit26
&& ins_bit27
)
4534 return aarch64_record_data_proc_reg (aarch64_insn_r
);
4536 /* Data processing - SIMD and floating point instructions. */
4537 if (ins_bit25
&& ins_bit26
&& ins_bit27
)
4538 return aarch64_record_data_proc_simd_fp (aarch64_insn_r
);
4540 return AARCH64_RECORD_UNSUPPORTED
;
4543 /* Cleans up local record registers and memory allocations. */
4546 deallocate_reg_mem (insn_decode_record
*record
)
4548 xfree (record
->aarch64_regs
);
4549 xfree (record
->aarch64_mems
);
4553 namespace selftests
{
4556 aarch64_process_record_test (void)
4558 struct gdbarch_info info
;
4561 info
.bfd_arch_info
= bfd_scan_arch ("aarch64");
4563 struct gdbarch
*gdbarch
= gdbarch_find_by_info (info
);
4564 SELF_CHECK (gdbarch
!= NULL
);
4566 insn_decode_record aarch64_record
;
4568 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4569 aarch64_record
.regcache
= NULL
;
4570 aarch64_record
.this_addr
= 0;
4571 aarch64_record
.gdbarch
= gdbarch
;
4573 /* 20 00 80 f9 prfm pldl1keep, [x1] */
4574 aarch64_record
.aarch64_insn
= 0xf9800020;
4575 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4576 SELF_CHECK (ret
== AARCH64_RECORD_SUCCESS
);
4577 SELF_CHECK (aarch64_record
.reg_rec_count
== 0);
4578 SELF_CHECK (aarch64_record
.mem_rec_count
== 0);
4580 deallocate_reg_mem (&aarch64_record
);
4583 } // namespace selftests
4584 #endif /* GDB_SELF_TEST */
4586 /* Parse the current instruction and record the values of the registers and
4587 memory that will be changed in current instruction to record_arch_list
4588 return -1 if something is wrong. */
4591 aarch64_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
4592 CORE_ADDR insn_addr
)
4594 uint32_t rec_no
= 0;
4595 uint8_t insn_size
= 4;
4597 gdb_byte buf
[insn_size
];
4598 insn_decode_record aarch64_record
;
4600 memset (&buf
[0], 0, insn_size
);
4601 memset (&aarch64_record
, 0, sizeof (insn_decode_record
));
4602 target_read_memory (insn_addr
, &buf
[0], insn_size
);
4603 aarch64_record
.aarch64_insn
4604 = (uint32_t) extract_unsigned_integer (&buf
[0],
4606 gdbarch_byte_order (gdbarch
));
4607 aarch64_record
.regcache
= regcache
;
4608 aarch64_record
.this_addr
= insn_addr
;
4609 aarch64_record
.gdbarch
= gdbarch
;
4611 ret
= aarch64_record_decode_insn_handler (&aarch64_record
);
4612 if (ret
== AARCH64_RECORD_UNSUPPORTED
)
4614 printf_unfiltered (_("Process record does not support instruction "
4615 "0x%0x at address %s.\n"),
4616 aarch64_record
.aarch64_insn
,
4617 paddress (gdbarch
, insn_addr
));
4623 /* Record registers. */
4624 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4626 /* Always record register CPSR. */
4627 record_full_arch_list_add_reg (aarch64_record
.regcache
,
4628 AARCH64_CPSR_REGNUM
);
4629 if (aarch64_record
.aarch64_regs
)
4630 for (rec_no
= 0; rec_no
< aarch64_record
.reg_rec_count
; rec_no
++)
4631 if (record_full_arch_list_add_reg (aarch64_record
.regcache
,
4632 aarch64_record
.aarch64_regs
[rec_no
]))
4635 /* Record memories. */
4636 if (aarch64_record
.aarch64_mems
)
4637 for (rec_no
= 0; rec_no
< aarch64_record
.mem_rec_count
; rec_no
++)
4638 if (record_full_arch_list_add_mem
4639 ((CORE_ADDR
)aarch64_record
.aarch64_mems
[rec_no
].addr
,
4640 aarch64_record
.aarch64_mems
[rec_no
].len
))
4643 if (record_full_arch_list_add_end ())
4647 deallocate_reg_mem (&aarch64_record
);