1 /* Target-dependent code for AMD64.
3 Copyright (C) 2001-2017 Free Software Foundation, Inc.
5 Contributed by Jiri Smid, SuSE Labs.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "opcode/i386.h"
25 #include "arch-utils.h"
27 #include "dummy-frame.h"
29 #include "frame-base.h"
30 #include "frame-unwind.h"
40 #include "amd64-tdep.h"
41 #include "i387-tdep.h"
42 #include "x86-xstate.h"
45 #include "features/i386/amd64.c"
46 #include "features/i386/amd64-avx.c"
47 #include "features/i386/amd64-mpx.c"
48 #include "features/i386/amd64-avx-mpx.c"
49 #include "features/i386/amd64-avx-avx512.c"
50 #include "features/i386/amd64-avx-mpx-avx512.c"
52 #include "features/i386/x32.c"
53 #include "features/i386/x32-avx.c"
54 #include "features/i386/x32-avx-avx512.c"
59 /* Note that the AMD64 architecture was previously known as x86-64.
60 The latter is (forever) engraved into the canonical system name as
61 returned by config.guess, and used as the name for the AMD64 port
62 of GNU/Linux. The BSD's have renamed their ports to amd64; they
63 don't like to shout. For GDB we prefer the amd64_-prefix over the
64 x86_64_-prefix since it's so much easier to type. */
66 /* Register information. */
68 static const char *amd64_register_names
[] =
70 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp",
72 /* %r8 is indeed register number 8. */
73 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
74 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs",
76 /* %st0 is register number 24. */
77 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7",
78 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop",
80 /* %xmm0 is register number 40. */
81 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
82 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
86 static const char *amd64_ymm_names
[] =
88 "ymm0", "ymm1", "ymm2", "ymm3",
89 "ymm4", "ymm5", "ymm6", "ymm7",
90 "ymm8", "ymm9", "ymm10", "ymm11",
91 "ymm12", "ymm13", "ymm14", "ymm15"
94 static const char *amd64_ymm_avx512_names
[] =
96 "ymm16", "ymm17", "ymm18", "ymm19",
97 "ymm20", "ymm21", "ymm22", "ymm23",
98 "ymm24", "ymm25", "ymm26", "ymm27",
99 "ymm28", "ymm29", "ymm30", "ymm31"
102 static const char *amd64_ymmh_names
[] =
104 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
105 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
106 "ymm8h", "ymm9h", "ymm10h", "ymm11h",
107 "ymm12h", "ymm13h", "ymm14h", "ymm15h"
110 static const char *amd64_ymmh_avx512_names
[] =
112 "ymm16h", "ymm17h", "ymm18h", "ymm19h",
113 "ymm20h", "ymm21h", "ymm22h", "ymm23h",
114 "ymm24h", "ymm25h", "ymm26h", "ymm27h",
115 "ymm28h", "ymm29h", "ymm30h", "ymm31h"
118 static const char *amd64_mpx_names
[] =
120 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
123 static const char *amd64_k_names
[] =
125 "k0", "k1", "k2", "k3",
126 "k4", "k5", "k6", "k7"
129 static const char *amd64_zmmh_names
[] =
131 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
132 "zmm4h", "zmm5h", "zmm6h", "zmm7h",
133 "zmm8h", "zmm9h", "zmm10h", "zmm11h",
134 "zmm12h", "zmm13h", "zmm14h", "zmm15h",
135 "zmm16h", "zmm17h", "zmm18h", "zmm19h",
136 "zmm20h", "zmm21h", "zmm22h", "zmm23h",
137 "zmm24h", "zmm25h", "zmm26h", "zmm27h",
138 "zmm28h", "zmm29h", "zmm30h", "zmm31h"
141 static const char *amd64_zmm_names
[] =
143 "zmm0", "zmm1", "zmm2", "zmm3",
144 "zmm4", "zmm5", "zmm6", "zmm7",
145 "zmm8", "zmm9", "zmm10", "zmm11",
146 "zmm12", "zmm13", "zmm14", "zmm15",
147 "zmm16", "zmm17", "zmm18", "zmm19",
148 "zmm20", "zmm21", "zmm22", "zmm23",
149 "zmm24", "zmm25", "zmm26", "zmm27",
150 "zmm28", "zmm29", "zmm30", "zmm31"
153 static const char *amd64_xmm_avx512_names
[] = {
154 "xmm16", "xmm17", "xmm18", "xmm19",
155 "xmm20", "xmm21", "xmm22", "xmm23",
156 "xmm24", "xmm25", "xmm26", "xmm27",
157 "xmm28", "xmm29", "xmm30", "xmm31"
160 /* DWARF Register Number Mapping as defined in the System V psABI,
163 static int amd64_dwarf_regmap
[] =
165 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */
166 AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
,
167 AMD64_RCX_REGNUM
, AMD64_RBX_REGNUM
,
168 AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
170 /* Frame Pointer Register RBP. */
173 /* Stack Pointer Register RSP. */
176 /* Extended Integer Registers 8 - 15. */
177 AMD64_R8_REGNUM
, /* %r8 */
178 AMD64_R9_REGNUM
, /* %r9 */
179 AMD64_R10_REGNUM
, /* %r10 */
180 AMD64_R11_REGNUM
, /* %r11 */
181 AMD64_R12_REGNUM
, /* %r12 */
182 AMD64_R13_REGNUM
, /* %r13 */
183 AMD64_R14_REGNUM
, /* %r14 */
184 AMD64_R15_REGNUM
, /* %r15 */
186 /* Return Address RA. Mapped to RIP. */
189 /* SSE Registers 0 - 7. */
190 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
191 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
192 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
193 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
195 /* Extended SSE Registers 8 - 15. */
196 AMD64_XMM0_REGNUM
+ 8, AMD64_XMM0_REGNUM
+ 9,
197 AMD64_XMM0_REGNUM
+ 10, AMD64_XMM0_REGNUM
+ 11,
198 AMD64_XMM0_REGNUM
+ 12, AMD64_XMM0_REGNUM
+ 13,
199 AMD64_XMM0_REGNUM
+ 14, AMD64_XMM0_REGNUM
+ 15,
201 /* Floating Point Registers 0-7. */
202 AMD64_ST0_REGNUM
+ 0, AMD64_ST0_REGNUM
+ 1,
203 AMD64_ST0_REGNUM
+ 2, AMD64_ST0_REGNUM
+ 3,
204 AMD64_ST0_REGNUM
+ 4, AMD64_ST0_REGNUM
+ 5,
205 AMD64_ST0_REGNUM
+ 6, AMD64_ST0_REGNUM
+ 7,
207 /* MMX Registers 0 - 7.
208 We have to handle those registers specifically, as their register
209 number within GDB depends on the target (or they may even not be
210 available at all). */
211 -1, -1, -1, -1, -1, -1, -1, -1,
213 /* Control and Status Flags Register. */
216 /* Selector Registers. */
226 /* Segment Base Address Registers. */
232 /* Special Selector Registers. */
236 /* Floating Point Control Registers. */
242 static const int amd64_dwarf_regmap_len
=
243 (sizeof (amd64_dwarf_regmap
) / sizeof (amd64_dwarf_regmap
[0]));
245 /* Convert DWARF register number REG to the appropriate register
246 number used by GDB. */
249 amd64_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
251 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
252 int ymm0_regnum
= tdep
->ymm0_regnum
;
255 if (reg
>= 0 && reg
< amd64_dwarf_regmap_len
)
256 regnum
= amd64_dwarf_regmap
[reg
];
259 && i386_xmm_regnum_p (gdbarch
, regnum
))
260 regnum
+= ymm0_regnum
- I387_XMM0_REGNUM (tdep
);
265 /* Map architectural register numbers to gdb register numbers. */
267 static const int amd64_arch_regmap
[16] =
269 AMD64_RAX_REGNUM
, /* %rax */
270 AMD64_RCX_REGNUM
, /* %rcx */
271 AMD64_RDX_REGNUM
, /* %rdx */
272 AMD64_RBX_REGNUM
, /* %rbx */
273 AMD64_RSP_REGNUM
, /* %rsp */
274 AMD64_RBP_REGNUM
, /* %rbp */
275 AMD64_RSI_REGNUM
, /* %rsi */
276 AMD64_RDI_REGNUM
, /* %rdi */
277 AMD64_R8_REGNUM
, /* %r8 */
278 AMD64_R9_REGNUM
, /* %r9 */
279 AMD64_R10_REGNUM
, /* %r10 */
280 AMD64_R11_REGNUM
, /* %r11 */
281 AMD64_R12_REGNUM
, /* %r12 */
282 AMD64_R13_REGNUM
, /* %r13 */
283 AMD64_R14_REGNUM
, /* %r14 */
284 AMD64_R15_REGNUM
/* %r15 */
287 static const int amd64_arch_regmap_len
=
288 (sizeof (amd64_arch_regmap
) / sizeof (amd64_arch_regmap
[0]));
290 /* Convert architectural register number REG to the appropriate register
291 number used by GDB. */
294 amd64_arch_reg_to_regnum (int reg
)
296 gdb_assert (reg
>= 0 && reg
< amd64_arch_regmap_len
);
298 return amd64_arch_regmap
[reg
];
301 /* Register names for byte pseudo-registers. */
303 static const char *amd64_byte_names
[] =
305 "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl",
306 "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l",
307 "ah", "bh", "ch", "dh"
310 /* Number of lower byte registers. */
311 #define AMD64_NUM_LOWER_BYTE_REGS 16
313 /* Register names for word pseudo-registers. */
315 static const char *amd64_word_names
[] =
317 "ax", "bx", "cx", "dx", "si", "di", "bp", "",
318 "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
321 /* Register names for dword pseudo-registers. */
323 static const char *amd64_dword_names
[] =
325 "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp",
326 "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d",
330 /* Return the name of register REGNUM. */
333 amd64_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
335 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
336 if (i386_byte_regnum_p (gdbarch
, regnum
))
337 return amd64_byte_names
[regnum
- tdep
->al_regnum
];
338 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
339 return amd64_zmm_names
[regnum
- tdep
->zmm0_regnum
];
340 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
341 return amd64_ymm_names
[regnum
- tdep
->ymm0_regnum
];
342 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
343 return amd64_ymm_avx512_names
[regnum
- tdep
->ymm16_regnum
];
344 else if (i386_word_regnum_p (gdbarch
, regnum
))
345 return amd64_word_names
[regnum
- tdep
->ax_regnum
];
346 else if (i386_dword_regnum_p (gdbarch
, regnum
))
347 return amd64_dword_names
[regnum
- tdep
->eax_regnum
];
349 return i386_pseudo_register_name (gdbarch
, regnum
);
352 static struct value
*
353 amd64_pseudo_register_read_value (struct gdbarch
*gdbarch
,
354 struct regcache
*regcache
,
357 gdb_byte
*raw_buf
= (gdb_byte
*) alloca (register_size (gdbarch
, regnum
));
358 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
359 enum register_status status
;
360 struct value
*result_value
;
363 result_value
= allocate_value (register_type (gdbarch
, regnum
));
364 VALUE_LVAL (result_value
) = lval_register
;
365 VALUE_REGNUM (result_value
) = regnum
;
366 buf
= value_contents_raw (result_value
);
368 if (i386_byte_regnum_p (gdbarch
, regnum
))
370 int gpnum
= regnum
- tdep
->al_regnum
;
372 /* Extract (always little endian). */
373 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
375 /* Special handling for AH, BH, CH, DH. */
376 status
= regcache_raw_read (regcache
,
377 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
,
379 if (status
== REG_VALID
)
380 memcpy (buf
, raw_buf
+ 1, 1);
382 mark_value_bytes_unavailable (result_value
, 0,
383 TYPE_LENGTH (value_type (result_value
)));
387 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
388 if (status
== REG_VALID
)
389 memcpy (buf
, raw_buf
, 1);
391 mark_value_bytes_unavailable (result_value
, 0,
392 TYPE_LENGTH (value_type (result_value
)));
395 else if (i386_dword_regnum_p (gdbarch
, regnum
))
397 int gpnum
= regnum
- tdep
->eax_regnum
;
398 /* Extract (always little endian). */
399 status
= regcache_raw_read (regcache
, gpnum
, raw_buf
);
400 if (status
== REG_VALID
)
401 memcpy (buf
, raw_buf
, 4);
403 mark_value_bytes_unavailable (result_value
, 0,
404 TYPE_LENGTH (value_type (result_value
)));
407 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
,
414 amd64_pseudo_register_write (struct gdbarch
*gdbarch
,
415 struct regcache
*regcache
,
416 int regnum
, const gdb_byte
*buf
)
418 gdb_byte
*raw_buf
= (gdb_byte
*) alloca (register_size (gdbarch
, regnum
));
419 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
421 if (i386_byte_regnum_p (gdbarch
, regnum
))
423 int gpnum
= regnum
- tdep
->al_regnum
;
425 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
427 /* Read ... AH, BH, CH, DH. */
428 regcache_raw_read (regcache
,
429 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
430 /* ... Modify ... (always little endian). */
431 memcpy (raw_buf
+ 1, buf
, 1);
433 regcache_raw_write (regcache
,
434 gpnum
- AMD64_NUM_LOWER_BYTE_REGS
, raw_buf
);
439 regcache_raw_read (regcache
, gpnum
, raw_buf
);
440 /* ... Modify ... (always little endian). */
441 memcpy (raw_buf
, buf
, 1);
443 regcache_raw_write (regcache
, gpnum
, raw_buf
);
446 else if (i386_dword_regnum_p (gdbarch
, regnum
))
448 int gpnum
= regnum
- tdep
->eax_regnum
;
451 regcache_raw_read (regcache
, gpnum
, raw_buf
);
452 /* ... Modify ... (always little endian). */
453 memcpy (raw_buf
, buf
, 4);
455 regcache_raw_write (regcache
, gpnum
, raw_buf
);
458 i386_pseudo_register_write (gdbarch
, regcache
, regnum
, buf
);
461 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
464 amd64_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
465 struct agent_expr
*ax
, int regnum
)
467 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
469 if (i386_byte_regnum_p (gdbarch
, regnum
))
471 int gpnum
= regnum
- tdep
->al_regnum
;
473 if (gpnum
>= AMD64_NUM_LOWER_BYTE_REGS
)
474 ax_reg_mask (ax
, gpnum
- AMD64_NUM_LOWER_BYTE_REGS
);
476 ax_reg_mask (ax
, gpnum
);
479 else if (i386_dword_regnum_p (gdbarch
, regnum
))
481 int gpnum
= regnum
- tdep
->eax_regnum
;
483 ax_reg_mask (ax
, gpnum
);
487 return i386_ax_pseudo_register_collect (gdbarch
, ax
, regnum
);
492 /* Register classes as defined in the psABI. */
506 /* Return the union class of CLASS1 and CLASS2. See the psABI for
509 static enum amd64_reg_class
510 amd64_merge_classes (enum amd64_reg_class class1
, enum amd64_reg_class class2
)
512 /* Rule (a): If both classes are equal, this is the resulting class. */
513 if (class1
== class2
)
516 /* Rule (b): If one of the classes is NO_CLASS, the resulting class
517 is the other class. */
518 if (class1
== AMD64_NO_CLASS
)
520 if (class2
== AMD64_NO_CLASS
)
523 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */
524 if (class1
== AMD64_MEMORY
|| class2
== AMD64_MEMORY
)
527 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */
528 if (class1
== AMD64_INTEGER
|| class2
== AMD64_INTEGER
)
529 return AMD64_INTEGER
;
531 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class,
532 MEMORY is used as class. */
533 if (class1
== AMD64_X87
|| class1
== AMD64_X87UP
534 || class1
== AMD64_COMPLEX_X87
|| class2
== AMD64_X87
535 || class2
== AMD64_X87UP
|| class2
== AMD64_COMPLEX_X87
)
538 /* Rule (f): Otherwise class SSE is used. */
542 static void amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2]);
544 /* Return non-zero if TYPE is a non-POD structure or union type. */
547 amd64_non_pod_p (struct type
*type
)
549 /* ??? A class with a base class certainly isn't POD, but does this
550 catch all non-POD structure types? */
551 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
&& TYPE_N_BASECLASSES (type
) > 0)
557 /* Classify TYPE according to the rules for aggregate (structures and
558 arrays) and union types, and store the result in CLASS. */
561 amd64_classify_aggregate (struct type
*type
, enum amd64_reg_class theclass
[2])
563 /* 1. If the size of an object is larger than two eightbytes, or in
564 C++, is a non-POD structure or union type, or contains
565 unaligned fields, it has class memory. */
566 if (TYPE_LENGTH (type
) > 16 || amd64_non_pod_p (type
))
568 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
572 /* 2. Both eightbytes get initialized to class NO_CLASS. */
573 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
575 /* 3. Each field of an object is classified recursively so that
576 always two fields are considered. The resulting class is
577 calculated according to the classes of the fields in the
580 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
582 struct type
*subtype
= check_typedef (TYPE_TARGET_TYPE (type
));
584 /* All fields in an array have the same type. */
585 amd64_classify (subtype
, theclass
);
586 if (TYPE_LENGTH (type
) > 8 && theclass
[1] == AMD64_NO_CLASS
)
587 theclass
[1] = theclass
[0];
593 /* Structure or union. */
594 gdb_assert (TYPE_CODE (type
) == TYPE_CODE_STRUCT
595 || TYPE_CODE (type
) == TYPE_CODE_UNION
);
597 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
599 struct type
*subtype
= check_typedef (TYPE_FIELD_TYPE (type
, i
));
600 int pos
= TYPE_FIELD_BITPOS (type
, i
) / 64;
601 enum amd64_reg_class subclass
[2];
602 int bitsize
= TYPE_FIELD_BITSIZE (type
, i
);
606 bitsize
= TYPE_LENGTH (subtype
) * 8;
607 endpos
= (TYPE_FIELD_BITPOS (type
, i
) + bitsize
- 1) / 64;
609 /* Ignore static fields. */
610 if (field_is_static (&TYPE_FIELD (type
, i
)))
613 gdb_assert (pos
== 0 || pos
== 1);
615 amd64_classify (subtype
, subclass
);
616 theclass
[pos
] = amd64_merge_classes (theclass
[pos
], subclass
[0]);
617 if (bitsize
<= 64 && pos
== 0 && endpos
== 1)
618 /* This is a bit of an odd case: We have a field that would
619 normally fit in one of the two eightbytes, except that
620 it is placed in a way that this field straddles them.
621 This has been seen with a structure containing an array.
623 The ABI is a bit unclear in this case, but we assume that
624 this field's class (stored in subclass[0]) must also be merged
625 into class[1]. In other words, our field has a piece stored
626 in the second eight-byte, and thus its class applies to
627 the second eight-byte as well.
629 In the case where the field length exceeds 8 bytes,
630 it should not be necessary to merge the field class
631 into class[1]. As LEN > 8, subclass[1] is necessarily
632 different from AMD64_NO_CLASS. If subclass[1] is equal
633 to subclass[0], then the normal class[1]/subclass[1]
634 merging will take care of everything. For subclass[1]
635 to be different from subclass[0], I can only see the case
636 where we have a SSE/SSEUP or X87/X87UP pair, which both
637 use up all 16 bytes of the aggregate, and are already
638 handled just fine (because each portion sits on its own
640 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[0]);
642 theclass
[1] = amd64_merge_classes (theclass
[1], subclass
[1]);
646 /* 4. Then a post merger cleanup is done: */
648 /* Rule (a): If one of the classes is MEMORY, the whole argument is
650 if (theclass
[0] == AMD64_MEMORY
|| theclass
[1] == AMD64_MEMORY
)
651 theclass
[0] = theclass
[1] = AMD64_MEMORY
;
653 /* Rule (b): If SSEUP is not preceded by SSE, it is converted to
655 if (theclass
[0] == AMD64_SSEUP
)
656 theclass
[0] = AMD64_SSE
;
657 if (theclass
[1] == AMD64_SSEUP
&& theclass
[0] != AMD64_SSE
)
658 theclass
[1] = AMD64_SSE
;
661 /* Classify TYPE, and store the result in CLASS. */
664 amd64_classify (struct type
*type
, enum amd64_reg_class theclass
[2])
666 enum type_code code
= TYPE_CODE (type
);
667 int len
= TYPE_LENGTH (type
);
669 theclass
[0] = theclass
[1] = AMD64_NO_CLASS
;
671 /* Arguments of types (signed and unsigned) _Bool, char, short, int,
672 long, long long, and pointers are in the INTEGER class. Similarly,
673 range types, used by languages such as Ada, are also in the INTEGER
675 if ((code
== TYPE_CODE_INT
|| code
== TYPE_CODE_ENUM
676 || code
== TYPE_CODE_BOOL
|| code
== TYPE_CODE_RANGE
677 || code
== TYPE_CODE_CHAR
678 || code
== TYPE_CODE_PTR
|| code
== TYPE_CODE_REF
)
679 && (len
== 1 || len
== 2 || len
== 4 || len
== 8))
680 theclass
[0] = AMD64_INTEGER
;
682 /* Arguments of types float, double, _Decimal32, _Decimal64 and __m64
684 else if ((code
== TYPE_CODE_FLT
|| code
== TYPE_CODE_DECFLOAT
)
685 && (len
== 4 || len
== 8))
687 theclass
[0] = AMD64_SSE
;
689 /* Arguments of types __float128, _Decimal128 and __m128 are split into
690 two halves. The least significant ones belong to class SSE, the most
691 significant one to class SSEUP. */
692 else if (code
== TYPE_CODE_DECFLOAT
&& len
== 16)
693 /* FIXME: __float128, __m128. */
694 theclass
[0] = AMD64_SSE
, theclass
[1] = AMD64_SSEUP
;
696 /* The 64-bit mantissa of arguments of type long double belongs to
697 class X87, the 16-bit exponent plus 6 bytes of padding belongs to
699 else if (code
== TYPE_CODE_FLT
&& len
== 16)
700 /* Class X87 and X87UP. */
701 theclass
[0] = AMD64_X87
, theclass
[1] = AMD64_X87UP
;
703 /* Arguments of complex T where T is one of the types float or
704 double get treated as if they are implemented as:
712 else if (code
== TYPE_CODE_COMPLEX
&& len
== 8)
713 theclass
[0] = AMD64_SSE
;
714 else if (code
== TYPE_CODE_COMPLEX
&& len
== 16)
715 theclass
[0] = theclass
[1] = AMD64_SSE
;
717 /* A variable of type complex long double is classified as type
719 else if (code
== TYPE_CODE_COMPLEX
&& len
== 32)
720 theclass
[0] = AMD64_COMPLEX_X87
;
723 else if (code
== TYPE_CODE_ARRAY
|| code
== TYPE_CODE_STRUCT
724 || code
== TYPE_CODE_UNION
)
725 amd64_classify_aggregate (type
, theclass
);
728 static enum return_value_convention
729 amd64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
730 struct type
*type
, struct regcache
*regcache
,
731 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
733 enum amd64_reg_class theclass
[2];
734 int len
= TYPE_LENGTH (type
);
735 static int integer_regnum
[] = { AMD64_RAX_REGNUM
, AMD64_RDX_REGNUM
};
736 static int sse_regnum
[] = { AMD64_XMM0_REGNUM
, AMD64_XMM1_REGNUM
};
741 gdb_assert (!(readbuf
&& writebuf
));
743 /* 1. Classify the return type with the classification algorithm. */
744 amd64_classify (type
, theclass
);
746 /* 2. If the type has class MEMORY, then the caller provides space
747 for the return value and passes the address of this storage in
748 %rdi as if it were the first argument to the function. In effect,
749 this address becomes a hidden first argument.
751 On return %rax will contain the address that has been passed in
752 by the caller in %rdi. */
753 if (theclass
[0] == AMD64_MEMORY
)
755 /* As indicated by the comment above, the ABI guarantees that we
756 can always find the return value just after the function has
763 regcache_raw_read_unsigned (regcache
, AMD64_RAX_REGNUM
, &addr
);
764 read_memory (addr
, readbuf
, TYPE_LENGTH (type
));
767 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
770 /* 8. If the class is COMPLEX_X87, the real part of the value is
771 returned in %st0 and the imaginary part in %st1. */
772 if (theclass
[0] == AMD64_COMPLEX_X87
)
776 regcache_raw_read (regcache
, AMD64_ST0_REGNUM
, readbuf
);
777 regcache_raw_read (regcache
, AMD64_ST1_REGNUM
, readbuf
+ 16);
782 i387_return_value (gdbarch
, regcache
);
783 regcache_raw_write (regcache
, AMD64_ST0_REGNUM
, writebuf
);
784 regcache_raw_write (regcache
, AMD64_ST1_REGNUM
, writebuf
+ 16);
786 /* Fix up the tag word such that both %st(0) and %st(1) are
788 regcache_raw_write_unsigned (regcache
, AMD64_FTAG_REGNUM
, 0xfff);
791 return RETURN_VALUE_REGISTER_CONVENTION
;
794 gdb_assert (theclass
[1] != AMD64_MEMORY
);
795 gdb_assert (len
<= 16);
797 for (i
= 0; len
> 0; i
++, len
-= 8)
805 /* 3. If the class is INTEGER, the next available register
806 of the sequence %rax, %rdx is used. */
807 regnum
= integer_regnum
[integer_reg
++];
811 /* 4. If the class is SSE, the next available SSE register
812 of the sequence %xmm0, %xmm1 is used. */
813 regnum
= sse_regnum
[sse_reg
++];
817 /* 5. If the class is SSEUP, the eightbyte is passed in the
818 upper half of the last used SSE register. */
819 gdb_assert (sse_reg
> 0);
820 regnum
= sse_regnum
[sse_reg
- 1];
825 /* 6. If the class is X87, the value is returned on the X87
826 stack in %st0 as 80-bit x87 number. */
827 regnum
= AMD64_ST0_REGNUM
;
829 i387_return_value (gdbarch
, regcache
);
833 /* 7. If the class is X87UP, the value is returned together
834 with the previous X87 value in %st0. */
835 gdb_assert (i
> 0 && theclass
[0] == AMD64_X87
);
836 regnum
= AMD64_ST0_REGNUM
;
845 gdb_assert (!"Unexpected register class.");
848 gdb_assert (regnum
!= -1);
851 regcache_raw_read_part (regcache
, regnum
, offset
, std::min (len
, 8),
854 regcache_raw_write_part (regcache
, regnum
, offset
, std::min (len
, 8),
858 return RETURN_VALUE_REGISTER_CONVENTION
;
863 amd64_push_arguments (struct regcache
*regcache
, int nargs
,
864 struct value
**args
, CORE_ADDR sp
, int struct_return
)
866 static int integer_regnum
[] =
868 AMD64_RDI_REGNUM
, /* %rdi */
869 AMD64_RSI_REGNUM
, /* %rsi */
870 AMD64_RDX_REGNUM
, /* %rdx */
871 AMD64_RCX_REGNUM
, /* %rcx */
872 AMD64_R8_REGNUM
, /* %r8 */
873 AMD64_R9_REGNUM
/* %r9 */
875 static int sse_regnum
[] =
877 /* %xmm0 ... %xmm7 */
878 AMD64_XMM0_REGNUM
+ 0, AMD64_XMM1_REGNUM
,
879 AMD64_XMM0_REGNUM
+ 2, AMD64_XMM0_REGNUM
+ 3,
880 AMD64_XMM0_REGNUM
+ 4, AMD64_XMM0_REGNUM
+ 5,
881 AMD64_XMM0_REGNUM
+ 6, AMD64_XMM0_REGNUM
+ 7,
883 struct value
**stack_args
= XALLOCAVEC (struct value
*, nargs
);
884 int num_stack_args
= 0;
885 int num_elements
= 0;
891 /* Reserve a register for the "hidden" argument. */
895 for (i
= 0; i
< nargs
; i
++)
897 struct type
*type
= value_type (args
[i
]);
898 int len
= TYPE_LENGTH (type
);
899 enum amd64_reg_class theclass
[2];
900 int needed_integer_regs
= 0;
901 int needed_sse_regs
= 0;
904 /* Classify argument. */
905 amd64_classify (type
, theclass
);
907 /* Calculate the number of integer and SSE registers needed for
909 for (j
= 0; j
< 2; j
++)
911 if (theclass
[j
] == AMD64_INTEGER
)
912 needed_integer_regs
++;
913 else if (theclass
[j
] == AMD64_SSE
)
917 /* Check whether enough registers are available, and if the
918 argument should be passed in registers at all. */
919 if (integer_reg
+ needed_integer_regs
> ARRAY_SIZE (integer_regnum
)
920 || sse_reg
+ needed_sse_regs
> ARRAY_SIZE (sse_regnum
)
921 || (needed_integer_regs
== 0 && needed_sse_regs
== 0))
923 /* The argument will be passed on the stack. */
924 num_elements
+= ((len
+ 7) / 8);
925 stack_args
[num_stack_args
++] = args
[i
];
929 /* The argument will be passed in registers. */
930 const gdb_byte
*valbuf
= value_contents (args
[i
]);
933 gdb_assert (len
<= 16);
935 for (j
= 0; len
> 0; j
++, len
-= 8)
943 regnum
= integer_regnum
[integer_reg
++];
947 regnum
= sse_regnum
[sse_reg
++];
951 gdb_assert (sse_reg
> 0);
952 regnum
= sse_regnum
[sse_reg
- 1];
957 gdb_assert (!"Unexpected register class.");
960 gdb_assert (regnum
!= -1);
961 memset (buf
, 0, sizeof buf
);
962 memcpy (buf
, valbuf
+ j
* 8, std::min (len
, 8));
963 regcache_raw_write_part (regcache
, regnum
, offset
, 8, buf
);
968 /* Allocate space for the arguments on the stack. */
969 sp
-= num_elements
* 8;
971 /* The psABI says that "The end of the input argument area shall be
972 aligned on a 16 byte boundary." */
975 /* Write out the arguments to the stack. */
976 for (i
= 0; i
< num_stack_args
; i
++)
978 struct type
*type
= value_type (stack_args
[i
]);
979 const gdb_byte
*valbuf
= value_contents (stack_args
[i
]);
980 int len
= TYPE_LENGTH (type
);
982 write_memory (sp
+ element
* 8, valbuf
, len
);
983 element
+= ((len
+ 7) / 8);
986 /* The psABI says that "For calls that may call functions that use
987 varargs or stdargs (prototype-less calls or calls to functions
988 containing ellipsis (...) in the declaration) %al is used as
989 hidden argument to specify the number of SSE registers used. */
990 regcache_raw_write_unsigned (regcache
, AMD64_RAX_REGNUM
, sse_reg
);
995 amd64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
996 struct regcache
*regcache
, CORE_ADDR bp_addr
,
997 int nargs
, struct value
**args
, CORE_ADDR sp
,
998 int struct_return
, CORE_ADDR struct_addr
)
1000 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1003 /* Pass arguments. */
1004 sp
= amd64_push_arguments (regcache
, nargs
, args
, sp
, struct_return
);
1006 /* Pass "hidden" argument". */
1009 store_unsigned_integer (buf
, 8, byte_order
, struct_addr
);
1010 regcache_cooked_write (regcache
, AMD64_RDI_REGNUM
, buf
);
1013 /* Store return address. */
1015 store_unsigned_integer (buf
, 8, byte_order
, bp_addr
);
1016 write_memory (sp
, buf
, 8);
1018 /* Finally, update the stack pointer... */
1019 store_unsigned_integer (buf
, 8, byte_order
, sp
);
1020 regcache_cooked_write (regcache
, AMD64_RSP_REGNUM
, buf
);
1022 /* ...and fake a frame pointer. */
1023 regcache_cooked_write (regcache
, AMD64_RBP_REGNUM
, buf
);
1028 /* Displaced instruction handling. */
1030 /* A partially decoded instruction.
1031 This contains enough details for displaced stepping purposes. */
1035 /* The number of opcode bytes. */
1037 /* The offset of the rex prefix or -1 if not present. */
1039 /* The offset to the first opcode byte. */
1041 /* The offset to the modrm byte or -1 if not present. */
1044 /* The raw instruction. */
1048 struct displaced_step_closure
1050 /* For rip-relative insns, saved copy of the reg we use instead of %rip. */
1055 /* Details of the instruction. */
1056 struct amd64_insn insn_details
;
1058 /* Amount of space allocated to insn_buf. */
1061 /* The possibly modified insn.
1062 This is a variable-length field. */
1063 gdb_byte insn_buf
[1];
1066 /* WARNING: Keep onebyte_has_modrm, twobyte_has_modrm in sync with
1067 ../opcodes/i386-dis.c (until libopcodes exports them, or an alternative,
1068 at which point delete these in favor of libopcodes' versions). */
1070 static const unsigned char onebyte_has_modrm
[256] = {
1071 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1072 /* ------------------------------- */
1073 /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
1074 /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
1075 /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
1076 /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
1077 /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
1078 /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
1079 /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
1080 /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
1081 /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
1082 /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
1083 /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
1084 /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
1085 /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
1086 /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
1087 /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
1088 /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */
1089 /* ------------------------------- */
1090 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1093 static const unsigned char twobyte_has_modrm
[256] = {
1094 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1095 /* ------------------------------- */
1096 /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
1097 /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
1098 /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
1099 /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
1100 /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
1101 /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
1102 /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
1103 /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
1104 /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
1105 /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
1106 /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
1107 /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
1108 /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
1109 /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
1110 /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
1111 /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
1112 /* ------------------------------- */
1113 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
1116 static int amd64_syscall_p (const struct amd64_insn
*insn
, int *lengthp
);
1119 rex_prefix_p (gdb_byte pfx
)
1121 return REX_PREFIX_P (pfx
);
1124 /* Skip the legacy instruction prefixes in INSN.
1125 We assume INSN is properly sentineled so we don't have to worry
1126 about falling off the end of the buffer. */
1129 amd64_skip_prefixes (gdb_byte
*insn
)
1135 case DATA_PREFIX_OPCODE
:
1136 case ADDR_PREFIX_OPCODE
:
1137 case CS_PREFIX_OPCODE
:
1138 case DS_PREFIX_OPCODE
:
1139 case ES_PREFIX_OPCODE
:
1140 case FS_PREFIX_OPCODE
:
1141 case GS_PREFIX_OPCODE
:
1142 case SS_PREFIX_OPCODE
:
1143 case LOCK_PREFIX_OPCODE
:
1144 case REPE_PREFIX_OPCODE
:
1145 case REPNE_PREFIX_OPCODE
:
1157 /* Return an integer register (other than RSP) that is unused as an input
1159 In order to not require adding a rex prefix if the insn doesn't already
1160 have one, the result is restricted to RAX ... RDI, sans RSP.
1161 The register numbering of the result follows architecture ordering,
1165 amd64_get_unused_input_int_reg (const struct amd64_insn
*details
)
1167 /* 1 bit for each reg */
1168 int used_regs_mask
= 0;
1170 /* There can be at most 3 int regs used as inputs in an insn, and we have
1171 7 to choose from (RAX ... RDI, sans RSP).
1172 This allows us to take a conservative approach and keep things simple.
1173 E.g. By avoiding RAX, we don't have to specifically watch for opcodes
1174 that implicitly specify RAX. */
1177 used_regs_mask
|= 1 << EAX_REG_NUM
;
1178 /* Similarily avoid RDX, implicit operand in divides. */
1179 used_regs_mask
|= 1 << EDX_REG_NUM
;
1181 used_regs_mask
|= 1 << ESP_REG_NUM
;
1183 /* If the opcode is one byte long and there's no ModRM byte,
1184 assume the opcode specifies a register. */
1185 if (details
->opcode_len
== 1 && details
->modrm_offset
== -1)
1186 used_regs_mask
|= 1 << (details
->raw_insn
[details
->opcode_offset
] & 7);
1188 /* Mark used regs in the modrm/sib bytes. */
1189 if (details
->modrm_offset
!= -1)
1191 int modrm
= details
->raw_insn
[details
->modrm_offset
];
1192 int mod
= MODRM_MOD_FIELD (modrm
);
1193 int reg
= MODRM_REG_FIELD (modrm
);
1194 int rm
= MODRM_RM_FIELD (modrm
);
1195 int have_sib
= mod
!= 3 && rm
== 4;
1197 /* Assume the reg field of the modrm byte specifies a register. */
1198 used_regs_mask
|= 1 << reg
;
1202 int base
= SIB_BASE_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1203 int idx
= SIB_INDEX_FIELD (details
->raw_insn
[details
->modrm_offset
+ 1]);
1204 used_regs_mask
|= 1 << base
;
1205 used_regs_mask
|= 1 << idx
;
1209 used_regs_mask
|= 1 << rm
;
1213 gdb_assert (used_regs_mask
< 256);
1214 gdb_assert (used_regs_mask
!= 255);
1216 /* Finally, find a free reg. */
1220 for (i
= 0; i
< 8; ++i
)
1222 if (! (used_regs_mask
& (1 << i
)))
1226 /* We shouldn't get here. */
1227 internal_error (__FILE__
, __LINE__
, _("unable to find free reg"));
1231 /* Extract the details of INSN that we need. */
1234 amd64_get_insn_details (gdb_byte
*insn
, struct amd64_insn
*details
)
1236 gdb_byte
*start
= insn
;
1239 details
->raw_insn
= insn
;
1241 details
->opcode_len
= -1;
1242 details
->rex_offset
= -1;
1243 details
->opcode_offset
= -1;
1244 details
->modrm_offset
= -1;
1246 /* Skip legacy instruction prefixes. */
1247 insn
= amd64_skip_prefixes (insn
);
1249 /* Skip REX instruction prefix. */
1250 if (rex_prefix_p (*insn
))
1252 details
->rex_offset
= insn
- start
;
1256 details
->opcode_offset
= insn
- start
;
1258 if (*insn
== TWO_BYTE_OPCODE_ESCAPE
)
1260 /* Two or three-byte opcode. */
1262 need_modrm
= twobyte_has_modrm
[*insn
];
1264 /* Check for three-byte opcode. */
1274 details
->opcode_len
= 3;
1277 details
->opcode_len
= 2;
1283 /* One-byte opcode. */
1284 need_modrm
= onebyte_has_modrm
[*insn
];
1285 details
->opcode_len
= 1;
1291 details
->modrm_offset
= insn
- start
;
1295 /* Update %rip-relative addressing in INSN.
1297 %rip-relative addressing only uses a 32-bit displacement.
1298 32 bits is not enough to be guaranteed to cover the distance between where
1299 the real instruction is and where its copy is.
1300 Convert the insn to use base+disp addressing.
1301 We set base = pc + insn_length so we can leave disp unchanged. */
1304 fixup_riprel (struct gdbarch
*gdbarch
, struct displaced_step_closure
*dsc
,
1305 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1307 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1308 int modrm_offset
= insn_details
->modrm_offset
;
1309 gdb_byte
*insn
= insn_details
->raw_insn
+ modrm_offset
;
1312 int arch_tmp_regno
, tmp_regno
;
1313 ULONGEST orig_value
;
1315 /* %rip+disp32 addressing mode, displacement follows ModRM byte. */
1318 /* Compute the rip-relative address. */
1319 insn_length
= gdb_buffered_insn_length (gdbarch
, dsc
->insn_buf
,
1320 dsc
->max_len
, from
);
1321 rip_base
= from
+ insn_length
;
1323 /* We need a register to hold the address.
1324 Pick one not used in the insn.
1325 NOTE: arch_tmp_regno uses architecture ordering, e.g. RDI = 7. */
1326 arch_tmp_regno
= amd64_get_unused_input_int_reg (insn_details
);
1327 tmp_regno
= amd64_arch_reg_to_regnum (arch_tmp_regno
);
1329 /* REX.B should be unset as we were using rip-relative addressing,
1330 but ensure it's unset anyway, tmp_regno is not r8-r15. */
1331 if (insn_details
->rex_offset
!= -1)
1332 dsc
->insn_buf
[insn_details
->rex_offset
] &= ~REX_B
;
1334 regcache_cooked_read_unsigned (regs
, tmp_regno
, &orig_value
);
1335 dsc
->tmp_regno
= tmp_regno
;
1336 dsc
->tmp_save
= orig_value
;
1339 /* Convert the ModRM field to be base+disp. */
1340 dsc
->insn_buf
[modrm_offset
] &= ~0xc7;
1341 dsc
->insn_buf
[modrm_offset
] |= 0x80 + arch_tmp_regno
;
1343 regcache_cooked_write_unsigned (regs
, tmp_regno
, rip_base
);
1345 if (debug_displaced
)
1346 fprintf_unfiltered (gdb_stdlog
, "displaced: %%rip-relative addressing used.\n"
1347 "displaced: using temp reg %d, old value %s, new value %s\n",
1348 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
),
1349 paddress (gdbarch
, rip_base
));
1353 fixup_displaced_copy (struct gdbarch
*gdbarch
,
1354 struct displaced_step_closure
*dsc
,
1355 CORE_ADDR from
, CORE_ADDR to
, struct regcache
*regs
)
1357 const struct amd64_insn
*details
= &dsc
->insn_details
;
1359 if (details
->modrm_offset
!= -1)
1361 gdb_byte modrm
= details
->raw_insn
[details
->modrm_offset
];
1363 if ((modrm
& 0xc7) == 0x05)
1365 /* The insn uses rip-relative addressing.
1367 fixup_riprel (gdbarch
, dsc
, from
, to
, regs
);
1372 struct displaced_step_closure
*
1373 amd64_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
1374 CORE_ADDR from
, CORE_ADDR to
,
1375 struct regcache
*regs
)
1377 int len
= gdbarch_max_insn_length (gdbarch
);
1378 /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to
1379 continually watch for running off the end of the buffer. */
1380 int fixup_sentinel_space
= len
;
1381 struct displaced_step_closure
*dsc
1382 = ((struct displaced_step_closure
*)
1383 xmalloc (sizeof (*dsc
) + len
+ fixup_sentinel_space
));
1384 gdb_byte
*buf
= &dsc
->insn_buf
[0];
1385 struct amd64_insn
*details
= &dsc
->insn_details
;
1388 dsc
->max_len
= len
+ fixup_sentinel_space
;
1390 read_memory (from
, buf
, len
);
1392 /* Set up the sentinel space so we don't have to worry about running
1393 off the end of the buffer. An excessive number of leading prefixes
1394 could otherwise cause this. */
1395 memset (buf
+ len
, 0, fixup_sentinel_space
);
1397 amd64_get_insn_details (buf
, details
);
1399 /* GDB may get control back after the insn after the syscall.
1400 Presumably this is a kernel bug.
1401 If this is a syscall, make sure there's a nop afterwards. */
1405 if (amd64_syscall_p (details
, &syscall_length
))
1406 buf
[details
->opcode_offset
+ syscall_length
] = NOP_OPCODE
;
1409 /* Modify the insn to cope with the address where it will be executed from.
1410 In particular, handle any rip-relative addressing. */
1411 fixup_displaced_copy (gdbarch
, dsc
, from
, to
, regs
);
1413 write_memory (to
, buf
, len
);
1415 if (debug_displaced
)
1417 fprintf_unfiltered (gdb_stdlog
, "displaced: copy %s->%s: ",
1418 paddress (gdbarch
, from
), paddress (gdbarch
, to
));
1419 displaced_step_dump_bytes (gdb_stdlog
, buf
, len
);
1426 amd64_absolute_jmp_p (const struct amd64_insn
*details
)
1428 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1430 if (insn
[0] == 0xff)
1432 /* jump near, absolute indirect (/4) */
1433 if ((insn
[1] & 0x38) == 0x20)
1436 /* jump far, absolute indirect (/5) */
1437 if ((insn
[1] & 0x38) == 0x28)
1444 /* Return non-zero if the instruction DETAILS is a jump, zero otherwise. */
1447 amd64_jmp_p (const struct amd64_insn
*details
)
1449 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1451 /* jump short, relative. */
1452 if (insn
[0] == 0xeb)
1455 /* jump near, relative. */
1456 if (insn
[0] == 0xe9)
1459 return amd64_absolute_jmp_p (details
);
1463 amd64_absolute_call_p (const struct amd64_insn
*details
)
1465 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1467 if (insn
[0] == 0xff)
1469 /* Call near, absolute indirect (/2) */
1470 if ((insn
[1] & 0x38) == 0x10)
1473 /* Call far, absolute indirect (/3) */
1474 if ((insn
[1] & 0x38) == 0x18)
1482 amd64_ret_p (const struct amd64_insn
*details
)
1484 /* NOTE: gcc can emit "repz ; ret". */
1485 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1489 case 0xc2: /* ret near, pop N bytes */
1490 case 0xc3: /* ret near */
1491 case 0xca: /* ret far, pop N bytes */
1492 case 0xcb: /* ret far */
1493 case 0xcf: /* iret */
1502 amd64_call_p (const struct amd64_insn
*details
)
1504 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1506 if (amd64_absolute_call_p (details
))
1509 /* call near, relative */
1510 if (insn
[0] == 0xe8)
1516 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
1517 length in bytes. Otherwise, return zero. */
1520 amd64_syscall_p (const struct amd64_insn
*details
, int *lengthp
)
1522 const gdb_byte
*insn
= &details
->raw_insn
[details
->opcode_offset
];
1524 if (insn
[0] == 0x0f && insn
[1] == 0x05)
1533 /* Classify the instruction at ADDR using PRED.
1534 Throw an error if the memory can't be read. */
1537 amd64_classify_insn_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1538 int (*pred
) (const struct amd64_insn
*))
1540 struct amd64_insn details
;
1542 int len
, classification
;
1544 len
= gdbarch_max_insn_length (gdbarch
);
1545 buf
= (gdb_byte
*) alloca (len
);
1547 read_code (addr
, buf
, len
);
1548 amd64_get_insn_details (buf
, &details
);
1550 classification
= pred (&details
);
1552 return classification
;
1555 /* The gdbarch insn_is_call method. */
1558 amd64_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1560 return amd64_classify_insn_at (gdbarch
, addr
, amd64_call_p
);
1563 /* The gdbarch insn_is_ret method. */
1566 amd64_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1568 return amd64_classify_insn_at (gdbarch
, addr
, amd64_ret_p
);
1571 /* The gdbarch insn_is_jump method. */
1574 amd64_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
1576 return amd64_classify_insn_at (gdbarch
, addr
, amd64_jmp_p
);
1579 /* Fix up the state of registers and memory after having single-stepped
1580 a displaced instruction. */
1583 amd64_displaced_step_fixup (struct gdbarch
*gdbarch
,
1584 struct displaced_step_closure
*dsc
,
1585 CORE_ADDR from
, CORE_ADDR to
,
1586 struct regcache
*regs
)
1588 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1589 /* The offset we applied to the instruction's address. */
1590 ULONGEST insn_offset
= to
- from
;
1591 gdb_byte
*insn
= dsc
->insn_buf
;
1592 const struct amd64_insn
*insn_details
= &dsc
->insn_details
;
1594 if (debug_displaced
)
1595 fprintf_unfiltered (gdb_stdlog
,
1596 "displaced: fixup (%s, %s), "
1597 "insn = 0x%02x 0x%02x ...\n",
1598 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
1601 /* If we used a tmp reg, restore it. */
1605 if (debug_displaced
)
1606 fprintf_unfiltered (gdb_stdlog
, "displaced: restoring reg %d to %s\n",
1607 dsc
->tmp_regno
, paddress (gdbarch
, dsc
->tmp_save
));
1608 regcache_cooked_write_unsigned (regs
, dsc
->tmp_regno
, dsc
->tmp_save
);
1611 /* The list of issues to contend with here is taken from
1612 resume_execution in arch/x86/kernel/kprobes.c, Linux 2.6.28.
1613 Yay for Free Software! */
1615 /* Relocate the %rip back to the program's instruction stream,
1618 /* Except in the case of absolute or indirect jump or call
1619 instructions, or a return instruction, the new rip is relative to
1620 the displaced instruction; make it relative to the original insn.
1621 Well, signal handler returns don't need relocation either, but we use the
1622 value of %rip to recognize those; see below. */
1623 if (! amd64_absolute_jmp_p (insn_details
)
1624 && ! amd64_absolute_call_p (insn_details
)
1625 && ! amd64_ret_p (insn_details
))
1630 regcache_cooked_read_unsigned (regs
, AMD64_RIP_REGNUM
, &orig_rip
);
1632 /* A signal trampoline system call changes the %rip, resuming
1633 execution of the main program after the signal handler has
1634 returned. That makes them like 'return' instructions; we
1635 shouldn't relocate %rip.
1637 But most system calls don't, and we do need to relocate %rip.
1639 Our heuristic for distinguishing these cases: if stepping
1640 over the system call instruction left control directly after
1641 the instruction, the we relocate --- control almost certainly
1642 doesn't belong in the displaced copy. Otherwise, we assume
1643 the instruction has put control where it belongs, and leave
1644 it unrelocated. Goodness help us if there are PC-relative
1646 if (amd64_syscall_p (insn_details
, &insn_len
)
1647 && orig_rip
!= to
+ insn_len
1648 /* GDB can get control back after the insn after the syscall.
1649 Presumably this is a kernel bug.
1650 Fixup ensures its a nop, we add one to the length for it. */
1651 && orig_rip
!= to
+ insn_len
+ 1)
1653 if (debug_displaced
)
1654 fprintf_unfiltered (gdb_stdlog
,
1655 "displaced: syscall changed %%rip; "
1656 "not relocating\n");
1660 ULONGEST rip
= orig_rip
- insn_offset
;
1662 /* If we just stepped over a breakpoint insn, we don't backup
1663 the pc on purpose; this is to match behaviour without
1666 regcache_cooked_write_unsigned (regs
, AMD64_RIP_REGNUM
, rip
);
1668 if (debug_displaced
)
1669 fprintf_unfiltered (gdb_stdlog
,
1671 "relocated %%rip from %s to %s\n",
1672 paddress (gdbarch
, orig_rip
),
1673 paddress (gdbarch
, rip
));
1677 /* If the instruction was PUSHFL, then the TF bit will be set in the
1678 pushed value, and should be cleared. We'll leave this for later,
1679 since GDB already messes up the TF flag when stepping over a
1682 /* If the instruction was a call, the return address now atop the
1683 stack is the address following the copied instruction. We need
1684 to make it the address following the original instruction. */
1685 if (amd64_call_p (insn_details
))
1689 const ULONGEST retaddr_len
= 8;
1691 regcache_cooked_read_unsigned (regs
, AMD64_RSP_REGNUM
, &rsp
);
1692 retaddr
= read_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
);
1693 retaddr
= (retaddr
- insn_offset
) & 0xffffffffffffffffULL
;
1694 write_memory_unsigned_integer (rsp
, retaddr_len
, byte_order
, retaddr
);
1696 if (debug_displaced
)
1697 fprintf_unfiltered (gdb_stdlog
,
1698 "displaced: relocated return addr at %s "
1700 paddress (gdbarch
, rsp
),
1701 paddress (gdbarch
, retaddr
));
1705 /* If the instruction INSN uses RIP-relative addressing, return the
1706 offset into the raw INSN where the displacement to be adjusted is
1707 found. Returns 0 if the instruction doesn't use RIP-relative
1711 rip_relative_offset (struct amd64_insn
*insn
)
1713 if (insn
->modrm_offset
!= -1)
1715 gdb_byte modrm
= insn
->raw_insn
[insn
->modrm_offset
];
1717 if ((modrm
& 0xc7) == 0x05)
1719 /* The displacement is found right after the ModRM byte. */
1720 return insn
->modrm_offset
+ 1;
1728 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
1730 target_write_memory (*to
, buf
, len
);
1735 amd64_relocate_instruction (struct gdbarch
*gdbarch
,
1736 CORE_ADDR
*to
, CORE_ADDR oldloc
)
1738 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1739 int len
= gdbarch_max_insn_length (gdbarch
);
1740 /* Extra space for sentinels. */
1741 int fixup_sentinel_space
= len
;
1742 gdb_byte
*buf
= (gdb_byte
*) xmalloc (len
+ fixup_sentinel_space
);
1743 struct amd64_insn insn_details
;
1745 LONGEST rel32
, newrel
;
1749 read_memory (oldloc
, buf
, len
);
1751 /* Set up the sentinel space so we don't have to worry about running
1752 off the end of the buffer. An excessive number of leading prefixes
1753 could otherwise cause this. */
1754 memset (buf
+ len
, 0, fixup_sentinel_space
);
1757 amd64_get_insn_details (insn
, &insn_details
);
1759 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
, len
, oldloc
);
1761 /* Skip legacy instruction prefixes. */
1762 insn
= amd64_skip_prefixes (insn
);
1764 /* Adjust calls with 32-bit relative addresses as push/jump, with
1765 the address pushed being the location where the original call in
1766 the user program would return to. */
1767 if (insn
[0] == 0xe8)
1769 gdb_byte push_buf
[32];
1773 /* Where "ret" in the original code will return to. */
1774 ret_addr
= oldloc
+ insn_length
;
1776 /* If pushing an address higher than or equal to 0x80000000,
1777 avoid 'pushq', as that sign extends its 32-bit operand, which
1778 would be incorrect. */
1779 if (ret_addr
<= 0x7fffffff)
1781 push_buf
[0] = 0x68; /* pushq $... */
1782 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
1787 push_buf
[i
++] = 0x48; /* sub $0x8,%rsp */
1788 push_buf
[i
++] = 0x83;
1789 push_buf
[i
++] = 0xec;
1790 push_buf
[i
++] = 0x08;
1792 push_buf
[i
++] = 0xc7; /* movl $imm,(%rsp) */
1793 push_buf
[i
++] = 0x04;
1794 push_buf
[i
++] = 0x24;
1795 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1796 ret_addr
& 0xffffffff);
1799 push_buf
[i
++] = 0xc7; /* movl $imm,4(%rsp) */
1800 push_buf
[i
++] = 0x44;
1801 push_buf
[i
++] = 0x24;
1802 push_buf
[i
++] = 0x04;
1803 store_unsigned_integer (&push_buf
[i
], 4, byte_order
,
1807 gdb_assert (i
<= sizeof (push_buf
));
1808 /* Push the push. */
1809 append_insns (to
, i
, push_buf
);
1811 /* Convert the relative call to a relative jump. */
1814 /* Adjust the destination offset. */
1815 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1816 newrel
= (oldloc
- *to
) + rel32
;
1817 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1819 if (debug_displaced
)
1820 fprintf_unfiltered (gdb_stdlog
,
1821 "Adjusted insn rel32=%s at %s to"
1822 " rel32=%s at %s\n",
1823 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1824 hex_string (newrel
), paddress (gdbarch
, *to
));
1826 /* Write the adjusted jump into its displaced location. */
1827 append_insns (to
, 5, insn
);
1831 offset
= rip_relative_offset (&insn_details
);
1834 /* Adjust jumps with 32-bit relative addresses. Calls are
1835 already handled above. */
1836 if (insn
[0] == 0xe9)
1838 /* Adjust conditional jumps. */
1839 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1845 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1846 newrel
= (oldloc
- *to
) + rel32
;
1847 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1848 if (debug_displaced
)
1849 fprintf_unfiltered (gdb_stdlog
,
1850 "Adjusted insn rel32=%s at %s to"
1851 " rel32=%s at %s\n",
1852 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1853 hex_string (newrel
), paddress (gdbarch
, *to
));
1856 /* Write the adjusted instruction into its displaced location. */
1857 append_insns (to
, insn_length
, buf
);
1861 /* The maximum number of saved registers. This should include %rip. */
1862 #define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS
1864 struct amd64_frame_cache
1869 CORE_ADDR sp_offset
;
1872 /* Saved registers. */
1873 CORE_ADDR saved_regs
[AMD64_NUM_SAVED_REGS
];
1877 /* Do we have a frame? */
1881 /* Initialize a frame cache. */
1884 amd64_init_frame_cache (struct amd64_frame_cache
*cache
)
1891 cache
->sp_offset
= -8;
1894 /* Saved registers. We initialize these to -1 since zero is a valid
1895 offset (that's where %rbp is supposed to be stored).
1896 The values start out as being offsets, and are later converted to
1897 addresses (at which point -1 is interpreted as an address, still meaning
1899 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
1900 cache
->saved_regs
[i
] = -1;
1901 cache
->saved_sp
= 0;
1902 cache
->saved_sp_reg
= -1;
1904 /* Frameless until proven otherwise. */
1905 cache
->frameless_p
= 1;
1908 /* Allocate and initialize a frame cache. */
1910 static struct amd64_frame_cache
*
1911 amd64_alloc_frame_cache (void)
1913 struct amd64_frame_cache
*cache
;
1915 cache
= FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache
);
1916 amd64_init_frame_cache (cache
);
1920 /* GCC 4.4 and later, can put code in the prologue to realign the
1921 stack pointer. Check whether PC points to such code, and update
1922 CACHE accordingly. Return the first instruction after the code
1923 sequence or CURRENT_PC, whichever is smaller. If we don't
1924 recognize the code, return PC. */
1927 amd64_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1928 struct amd64_frame_cache
*cache
)
1930 /* There are 2 code sequences to re-align stack before the frame
1933 1. Use a caller-saved saved register:
1939 2. Use a callee-saved saved register:
1946 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
1948 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
1949 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
1954 int offset
, offset_and
;
1956 if (target_read_code (pc
, buf
, sizeof buf
))
1959 /* Check caller-saved saved register. The first instruction has
1960 to be "leaq 8(%rsp), %reg". */
1961 if ((buf
[0] & 0xfb) == 0x48
1966 /* MOD must be binary 10 and R/M must be binary 100. */
1967 if ((buf
[2] & 0xc7) != 0x44)
1970 /* REG has register number. */
1971 reg
= (buf
[2] >> 3) & 7;
1973 /* Check the REX.R bit. */
1981 /* Check callee-saved saved register. The first instruction
1982 has to be "pushq %reg". */
1984 if ((buf
[0] & 0xf8) == 0x50)
1986 else if ((buf
[0] & 0xf6) == 0x40
1987 && (buf
[1] & 0xf8) == 0x50)
1989 /* Check the REX.B bit. */
1990 if ((buf
[0] & 1) != 0)
1999 reg
+= buf
[offset
] & 0x7;
2003 /* The next instruction has to be "leaq 16(%rsp), %reg". */
2004 if ((buf
[offset
] & 0xfb) != 0x48
2005 || buf
[offset
+ 1] != 0x8d
2006 || buf
[offset
+ 3] != 0x24
2007 || buf
[offset
+ 4] != 0x10)
2010 /* MOD must be binary 10 and R/M must be binary 100. */
2011 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2014 /* REG has register number. */
2015 r
= (buf
[offset
+ 2] >> 3) & 7;
2017 /* Check the REX.R bit. */
2018 if (buf
[offset
] == 0x4c)
2021 /* Registers in pushq and leaq have to be the same. */
2028 /* Rigister can't be %rsp nor %rbp. */
2029 if (reg
== 4 || reg
== 5)
2032 /* The next instruction has to be "andq $-XXX, %rsp". */
2033 if (buf
[offset
] != 0x48
2034 || buf
[offset
+ 2] != 0xe4
2035 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2038 offset_and
= offset
;
2039 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2041 /* The next instruction has to be "pushq -8(%reg)". */
2043 if (buf
[offset
] == 0xff)
2045 else if ((buf
[offset
] & 0xf6) == 0x40
2046 && buf
[offset
+ 1] == 0xff)
2048 /* Check the REX.B bit. */
2049 if ((buf
[offset
] & 0x1) != 0)
2056 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2058 if (buf
[offset
+ 1] != 0xf8
2059 || (buf
[offset
] & 0xf8) != 0x70)
2062 /* R/M has register. */
2063 r
+= buf
[offset
] & 7;
2065 /* Registers in leaq and pushq have to be the same. */
2069 if (current_pc
> pc
+ offset_and
)
2070 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2072 return std::min (pc
+ offset
+ 2, current_pc
);
2075 /* Similar to amd64_analyze_stack_align for x32. */
2078 amd64_x32_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
2079 struct amd64_frame_cache
*cache
)
2081 /* There are 2 code sequences to re-align stack before the frame
2084 1. Use a caller-saved saved register:
2092 [addr32] leal 8(%rsp), %reg
2094 [addr32] pushq -8(%reg)
2096 2. Use a callee-saved saved register:
2106 [addr32] leal 16(%rsp), %reg
2108 [addr32] pushq -8(%reg)
2110 "andq $-XXX, %rsp" can be either 4 bytes or 7 bytes:
2112 0x48 0x83 0xe4 0xf0 andq $-16, %rsp
2113 0x48 0x81 0xe4 0x00 0xff 0xff 0xff andq $-256, %rsp
2115 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
2117 0x83 0xe4 0xf0 andl $-16, %esp
2118 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
2123 int offset
, offset_and
;
2125 if (target_read_memory (pc
, buf
, sizeof buf
))
2128 /* Skip optional addr32 prefix. */
2129 offset
= buf
[0] == 0x67 ? 1 : 0;
2131 /* Check caller-saved saved register. The first instruction has
2132 to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */
2133 if (((buf
[offset
] & 0xfb) == 0x48 || (buf
[offset
] & 0xfb) == 0x40)
2134 && buf
[offset
+ 1] == 0x8d
2135 && buf
[offset
+ 3] == 0x24
2136 && buf
[offset
+ 4] == 0x8)
2138 /* MOD must be binary 10 and R/M must be binary 100. */
2139 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2142 /* REG has register number. */
2143 reg
= (buf
[offset
+ 2] >> 3) & 7;
2145 /* Check the REX.R bit. */
2146 if ((buf
[offset
] & 0x4) != 0)
2153 /* Check callee-saved saved register. The first instruction
2154 has to be "pushq %reg". */
2156 if ((buf
[offset
] & 0xf6) == 0x40
2157 && (buf
[offset
+ 1] & 0xf8) == 0x50)
2159 /* Check the REX.B bit. */
2160 if ((buf
[offset
] & 1) != 0)
2165 else if ((buf
[offset
] & 0xf8) != 0x50)
2169 reg
+= buf
[offset
] & 0x7;
2173 /* Skip optional addr32 prefix. */
2174 if (buf
[offset
] == 0x67)
2177 /* The next instruction has to be "leaq 16(%rsp), %reg" or
2178 "leal 16(%rsp), %reg". */
2179 if (((buf
[offset
] & 0xfb) != 0x48 && (buf
[offset
] & 0xfb) != 0x40)
2180 || buf
[offset
+ 1] != 0x8d
2181 || buf
[offset
+ 3] != 0x24
2182 || buf
[offset
+ 4] != 0x10)
2185 /* MOD must be binary 10 and R/M must be binary 100. */
2186 if ((buf
[offset
+ 2] & 0xc7) != 0x44)
2189 /* REG has register number. */
2190 r
= (buf
[offset
+ 2] >> 3) & 7;
2192 /* Check the REX.R bit. */
2193 if ((buf
[offset
] & 0x4) != 0)
2196 /* Registers in pushq and leaq have to be the same. */
2203 /* Rigister can't be %rsp nor %rbp. */
2204 if (reg
== 4 || reg
== 5)
2207 /* The next instruction may be "andq $-XXX, %rsp" or
2208 "andl $-XXX, %esp". */
2209 if (buf
[offset
] != 0x48)
2212 if (buf
[offset
+ 2] != 0xe4
2213 || (buf
[offset
+ 1] != 0x81 && buf
[offset
+ 1] != 0x83))
2216 offset_and
= offset
;
2217 offset
+= buf
[offset
+ 1] == 0x81 ? 7 : 4;
2219 /* Skip optional addr32 prefix. */
2220 if (buf
[offset
] == 0x67)
2223 /* The next instruction has to be "pushq -8(%reg)". */
2225 if (buf
[offset
] == 0xff)
2227 else if ((buf
[offset
] & 0xf6) == 0x40
2228 && buf
[offset
+ 1] == 0xff)
2230 /* Check the REX.B bit. */
2231 if ((buf
[offset
] & 0x1) != 0)
2238 /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary
2240 if (buf
[offset
+ 1] != 0xf8
2241 || (buf
[offset
] & 0xf8) != 0x70)
2244 /* R/M has register. */
2245 r
+= buf
[offset
] & 7;
2247 /* Registers in leaq and pushq have to be the same. */
2251 if (current_pc
> pc
+ offset_and
)
2252 cache
->saved_sp_reg
= amd64_arch_reg_to_regnum (reg
);
2254 return std::min (pc
+ offset
+ 2, current_pc
);
2257 /* Do a limited analysis of the prologue at PC and update CACHE
2258 accordingly. Bail out early if CURRENT_PC is reached. Return the
2259 address where the analysis stopped.
2261 We will handle only functions beginning with:
2264 movq %rsp, %rbp 0x48 0x89 0xe5 (or 0x48 0x8b 0xec)
2266 or (for the X32 ABI):
2269 movl %esp, %ebp 0x89 0xe5 (or 0x8b 0xec)
2271 Any function that doesn't start with one of these sequences will be
2272 assumed to have no prologue and thus no valid frame pointer in
2276 amd64_analyze_prologue (struct gdbarch
*gdbarch
,
2277 CORE_ADDR pc
, CORE_ADDR current_pc
,
2278 struct amd64_frame_cache
*cache
)
2280 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2281 /* There are two variations of movq %rsp, %rbp. */
2282 static const gdb_byte mov_rsp_rbp_1
[3] = { 0x48, 0x89, 0xe5 };
2283 static const gdb_byte mov_rsp_rbp_2
[3] = { 0x48, 0x8b, 0xec };
2284 /* Ditto for movl %esp, %ebp. */
2285 static const gdb_byte mov_esp_ebp_1
[2] = { 0x89, 0xe5 };
2286 static const gdb_byte mov_esp_ebp_2
[2] = { 0x8b, 0xec };
2291 if (current_pc
<= pc
)
2294 if (gdbarch_ptr_bit (gdbarch
) == 32)
2295 pc
= amd64_x32_analyze_stack_align (pc
, current_pc
, cache
);
2297 pc
= amd64_analyze_stack_align (pc
, current_pc
, cache
);
2299 op
= read_code_unsigned_integer (pc
, 1, byte_order
);
2301 if (op
== 0x55) /* pushq %rbp */
2303 /* Take into account that we've executed the `pushq %rbp' that
2304 starts this instruction sequence. */
2305 cache
->saved_regs
[AMD64_RBP_REGNUM
] = 0;
2306 cache
->sp_offset
+= 8;
2308 /* If that's all, return now. */
2309 if (current_pc
<= pc
+ 1)
2312 read_code (pc
+ 1, buf
, 3);
2314 /* Check for `movq %rsp, %rbp'. */
2315 if (memcmp (buf
, mov_rsp_rbp_1
, 3) == 0
2316 || memcmp (buf
, mov_rsp_rbp_2
, 3) == 0)
2318 /* OK, we actually have a frame. */
2319 cache
->frameless_p
= 0;
2323 /* For X32, also check for `movq %esp, %ebp'. */
2324 if (gdbarch_ptr_bit (gdbarch
) == 32)
2326 if (memcmp (buf
, mov_esp_ebp_1
, 2) == 0
2327 || memcmp (buf
, mov_esp_ebp_2
, 2) == 0)
2329 /* OK, we actually have a frame. */
2330 cache
->frameless_p
= 0;
2341 /* Work around false termination of prologue - GCC PR debug/48827.
2343 START_PC is the first instruction of a function, PC is its minimal already
2344 determined advanced address. Function returns PC if it has nothing to do.
2348 <-- here is 0 lines advance - the false prologue end marker.
2349 0f 29 85 70 ff ff ff movaps %xmm0,-0x90(%rbp)
2350 0f 29 4d 80 movaps %xmm1,-0x80(%rbp)
2351 0f 29 55 90 movaps %xmm2,-0x70(%rbp)
2352 0f 29 5d a0 movaps %xmm3,-0x60(%rbp)
2353 0f 29 65 b0 movaps %xmm4,-0x50(%rbp)
2354 0f 29 6d c0 movaps %xmm5,-0x40(%rbp)
2355 0f 29 75 d0 movaps %xmm6,-0x30(%rbp)
2356 0f 29 7d e0 movaps %xmm7,-0x20(%rbp)
2360 amd64_skip_xmm_prologue (CORE_ADDR pc
, CORE_ADDR start_pc
)
2362 struct symtab_and_line start_pc_sal
, next_sal
;
2363 gdb_byte buf
[4 + 8 * 7];
2369 start_pc_sal
= find_pc_sect_line (start_pc
, NULL
, 0);
2370 if (start_pc_sal
.symtab
== NULL
2371 || producer_is_gcc_ge_4 (COMPUNIT_PRODUCER
2372 (SYMTAB_COMPUNIT (start_pc_sal
.symtab
))) < 6
2373 || start_pc_sal
.pc
!= start_pc
|| pc
>= start_pc_sal
.end
)
2376 next_sal
= find_pc_sect_line (start_pc_sal
.end
, NULL
, 0);
2377 if (next_sal
.line
!= start_pc_sal
.line
)
2380 /* START_PC can be from overlayed memory, ignored here. */
2381 if (target_read_code (next_sal
.pc
- 4, buf
, sizeof (buf
)) != 0)
2385 if (buf
[0] != 0x84 || buf
[1] != 0xc0)
2392 for (xmmreg
= 0; xmmreg
< 8; xmmreg
++)
2394 /* 0x0f 0x29 0b??000101 movaps %xmmreg?,-0x??(%rbp) */
2395 if (buf
[offset
] != 0x0f || buf
[offset
+ 1] != 0x29
2396 || (buf
[offset
+ 2] & 0x3f) != (xmmreg
<< 3 | 0x5))
2400 if ((buf
[offset
+ 2] & 0xc0) == 0x40)
2402 /* 8-bit displacement. */
2406 else if ((buf
[offset
+ 2] & 0xc0) == 0x80)
2408 /* 32-bit displacement. */
2416 if (offset
- 4 != buf
[3])
2419 return next_sal
.end
;
2422 /* Return PC of first real instruction. */
2425 amd64_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
2427 struct amd64_frame_cache cache
;
2429 CORE_ADDR func_addr
;
2431 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
2433 CORE_ADDR post_prologue_pc
2434 = skip_prologue_using_sal (gdbarch
, func_addr
);
2435 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
2437 /* Clang always emits a line note before the prologue and another
2438 one after. We trust clang to emit usable line notes. */
2439 if (post_prologue_pc
2441 && COMPUNIT_PRODUCER (cust
) != NULL
2442 && startswith (COMPUNIT_PRODUCER (cust
), "clang ")))
2443 return std::max (start_pc
, post_prologue_pc
);
2446 amd64_init_frame_cache (&cache
);
2447 pc
= amd64_analyze_prologue (gdbarch
, start_pc
, 0xffffffffffffffffLL
,
2449 if (cache
.frameless_p
)
2452 return amd64_skip_xmm_prologue (pc
, start_pc
);
2456 /* Normal frames. */
2459 amd64_frame_cache_1 (struct frame_info
*this_frame
,
2460 struct amd64_frame_cache
*cache
)
2462 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2463 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2467 cache
->pc
= get_frame_func (this_frame
);
2469 amd64_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2472 if (cache
->frameless_p
)
2474 /* We didn't find a valid frame. If we're at the start of a
2475 function, or somewhere half-way its prologue, the function's
2476 frame probably hasn't been fully setup yet. Try to
2477 reconstruct the base address for the stack frame by looking
2478 at the stack pointer. For truly "frameless" functions this
2481 if (cache
->saved_sp_reg
!= -1)
2483 /* Stack pointer has been saved. */
2484 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2485 cache
->saved_sp
= extract_unsigned_integer (buf
, 8, byte_order
);
2487 /* We're halfway aligning the stack. */
2488 cache
->base
= ((cache
->saved_sp
- 8) & 0xfffffffffffffff0LL
) - 8;
2489 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->saved_sp
- 8;
2491 /* This will be added back below. */
2492 cache
->saved_regs
[AMD64_RIP_REGNUM
] -= cache
->base
;
2496 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2497 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
)
2503 get_frame_register (this_frame
, AMD64_RBP_REGNUM
, buf
);
2504 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
);
2507 /* Now that we have the base address for the stack frame we can
2508 calculate the value of %rsp in the calling frame. */
2509 cache
->saved_sp
= cache
->base
+ 16;
2511 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a
2512 frame we find it at the same offset from the reconstructed base
2513 address. If we're halfway aligning the stack, %rip is handled
2514 differently (see above). */
2515 if (!cache
->frameless_p
|| cache
->saved_sp_reg
== -1)
2516 cache
->saved_regs
[AMD64_RIP_REGNUM
] = 8;
2518 /* Adjust all the saved registers such that they contain addresses
2519 instead of offsets. */
2520 for (i
= 0; i
< AMD64_NUM_SAVED_REGS
; i
++)
2521 if (cache
->saved_regs
[i
] != -1)
2522 cache
->saved_regs
[i
] += cache
->base
;
2527 static struct amd64_frame_cache
*
2528 amd64_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2530 struct amd64_frame_cache
*cache
;
2533 return (struct amd64_frame_cache
*) *this_cache
;
2535 cache
= amd64_alloc_frame_cache ();
2536 *this_cache
= cache
;
2540 amd64_frame_cache_1 (this_frame
, cache
);
2542 CATCH (ex
, RETURN_MASK_ERROR
)
2544 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2545 throw_exception (ex
);
2552 static enum unwind_stop_reason
2553 amd64_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2556 struct amd64_frame_cache
*cache
=
2557 amd64_frame_cache (this_frame
, this_cache
);
2560 return UNWIND_UNAVAILABLE
;
2562 /* This marks the outermost frame. */
2563 if (cache
->base
== 0)
2564 return UNWIND_OUTERMOST
;
2566 return UNWIND_NO_REASON
;
2570 amd64_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2571 struct frame_id
*this_id
)
2573 struct amd64_frame_cache
*cache
=
2574 amd64_frame_cache (this_frame
, this_cache
);
2577 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2578 else if (cache
->base
== 0)
2580 /* This marks the outermost frame. */
2584 (*this_id
) = frame_id_build (cache
->base
+ 16, cache
->pc
);
2587 static struct value
*
2588 amd64_frame_prev_register (struct frame_info
*this_frame
, void **this_cache
,
2591 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2592 struct amd64_frame_cache
*cache
=
2593 amd64_frame_cache (this_frame
, this_cache
);
2595 gdb_assert (regnum
>= 0);
2597 if (regnum
== gdbarch_sp_regnum (gdbarch
) && cache
->saved_sp
)
2598 return frame_unwind_got_constant (this_frame
, regnum
, cache
->saved_sp
);
2600 if (regnum
< AMD64_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2601 return frame_unwind_got_memory (this_frame
, regnum
,
2602 cache
->saved_regs
[regnum
]);
2604 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2607 static const struct frame_unwind amd64_frame_unwind
=
2610 amd64_frame_unwind_stop_reason
,
2611 amd64_frame_this_id
,
2612 amd64_frame_prev_register
,
2614 default_frame_sniffer
2617 /* Generate a bytecode expression to get the value of the saved PC. */
2620 amd64_gen_return_address (struct gdbarch
*gdbarch
,
2621 struct agent_expr
*ax
, struct axs_value
*value
,
2624 /* The following sequence assumes the traditional use of the base
2626 ax_reg (ax
, AMD64_RBP_REGNUM
);
2628 ax_simple (ax
, aop_add
);
2629 value
->type
= register_type (gdbarch
, AMD64_RIP_REGNUM
);
2630 value
->kind
= axs_lvalue_memory
;
2634 /* Signal trampolines. */
2636 /* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and
2637 64-bit variants. This would require using identical frame caches
2638 on both platforms. */
2640 static struct amd64_frame_cache
*
2641 amd64_sigtramp_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2643 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2644 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2645 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2646 struct amd64_frame_cache
*cache
;
2652 return (struct amd64_frame_cache
*) *this_cache
;
2654 cache
= amd64_alloc_frame_cache ();
2658 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2659 cache
->base
= extract_unsigned_integer (buf
, 8, byte_order
) - 8;
2661 addr
= tdep
->sigcontext_addr (this_frame
);
2662 gdb_assert (tdep
->sc_reg_offset
);
2663 gdb_assert (tdep
->sc_num_regs
<= AMD64_NUM_SAVED_REGS
);
2664 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2665 if (tdep
->sc_reg_offset
[i
] != -1)
2666 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2670 CATCH (ex
, RETURN_MASK_ERROR
)
2672 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2673 throw_exception (ex
);
2677 *this_cache
= cache
;
2681 static enum unwind_stop_reason
2682 amd64_sigtramp_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2685 struct amd64_frame_cache
*cache
=
2686 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2689 return UNWIND_UNAVAILABLE
;
2691 return UNWIND_NO_REASON
;
2695 amd64_sigtramp_frame_this_id (struct frame_info
*this_frame
,
2696 void **this_cache
, struct frame_id
*this_id
)
2698 struct amd64_frame_cache
*cache
=
2699 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2702 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2703 else if (cache
->base
== 0)
2705 /* This marks the outermost frame. */
2709 (*this_id
) = frame_id_build (cache
->base
+ 16, get_frame_pc (this_frame
));
2712 static struct value
*
2713 amd64_sigtramp_frame_prev_register (struct frame_info
*this_frame
,
2714 void **this_cache
, int regnum
)
2716 /* Make sure we've initialized the cache. */
2717 amd64_sigtramp_frame_cache (this_frame
, this_cache
);
2719 return amd64_frame_prev_register (this_frame
, this_cache
, regnum
);
2723 amd64_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2724 struct frame_info
*this_frame
,
2727 struct gdbarch_tdep
*tdep
= gdbarch_tdep (get_frame_arch (this_frame
));
2729 /* We shouldn't even bother if we don't have a sigcontext_addr
2731 if (tdep
->sigcontext_addr
== NULL
)
2734 if (tdep
->sigtramp_p
!= NULL
)
2736 if (tdep
->sigtramp_p (this_frame
))
2740 if (tdep
->sigtramp_start
!= 0)
2742 CORE_ADDR pc
= get_frame_pc (this_frame
);
2744 gdb_assert (tdep
->sigtramp_end
!= 0);
2745 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2752 static const struct frame_unwind amd64_sigtramp_frame_unwind
=
2755 amd64_sigtramp_frame_unwind_stop_reason
,
2756 amd64_sigtramp_frame_this_id
,
2757 amd64_sigtramp_frame_prev_register
,
2759 amd64_sigtramp_frame_sniffer
2764 amd64_frame_base_address (struct frame_info
*this_frame
, void **this_cache
)
2766 struct amd64_frame_cache
*cache
=
2767 amd64_frame_cache (this_frame
, this_cache
);
2772 static const struct frame_base amd64_frame_base
=
2774 &amd64_frame_unwind
,
2775 amd64_frame_base_address
,
2776 amd64_frame_base_address
,
2777 amd64_frame_base_address
2780 /* Normal frames, but in a function epilogue. */
2782 /* Implement the stack_frame_destroyed_p gdbarch method.
2784 The epilogue is defined here as the 'ret' instruction, which will
2785 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2786 the function's stack frame. */
2789 amd64_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2792 struct compunit_symtab
*cust
;
2794 cust
= find_pc_compunit_symtab (pc
);
2795 if (cust
!= NULL
&& COMPUNIT_EPILOGUE_UNWIND_VALID (cust
))
2798 if (target_read_memory (pc
, &insn
, 1))
2799 return 0; /* Can't read memory at pc. */
2801 if (insn
!= 0xc3) /* 'ret' instruction. */
2808 amd64_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2809 struct frame_info
*this_frame
,
2810 void **this_prologue_cache
)
2812 if (frame_relative_level (this_frame
) == 0)
2813 return amd64_stack_frame_destroyed_p (get_frame_arch (this_frame
),
2814 get_frame_pc (this_frame
));
2819 static struct amd64_frame_cache
*
2820 amd64_epilogue_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2822 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2823 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2824 struct amd64_frame_cache
*cache
;
2828 return (struct amd64_frame_cache
*) *this_cache
;
2830 cache
= amd64_alloc_frame_cache ();
2831 *this_cache
= cache
;
2835 /* Cache base will be %esp plus cache->sp_offset (-8). */
2836 get_frame_register (this_frame
, AMD64_RSP_REGNUM
, buf
);
2837 cache
->base
= extract_unsigned_integer (buf
, 8,
2838 byte_order
) + cache
->sp_offset
;
2840 /* Cache pc will be the frame func. */
2841 cache
->pc
= get_frame_pc (this_frame
);
2843 /* The saved %esp will be at cache->base plus 16. */
2844 cache
->saved_sp
= cache
->base
+ 16;
2846 /* The saved %eip will be at cache->base plus 8. */
2847 cache
->saved_regs
[AMD64_RIP_REGNUM
] = cache
->base
+ 8;
2851 CATCH (ex
, RETURN_MASK_ERROR
)
2853 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2854 throw_exception (ex
);
2861 static enum unwind_stop_reason
2862 amd64_epilogue_frame_unwind_stop_reason (struct frame_info
*this_frame
,
2865 struct amd64_frame_cache
*cache
2866 = amd64_epilogue_frame_cache (this_frame
, this_cache
);
2869 return UNWIND_UNAVAILABLE
;
2871 return UNWIND_NO_REASON
;
2875 amd64_epilogue_frame_this_id (struct frame_info
*this_frame
,
2877 struct frame_id
*this_id
)
2879 struct amd64_frame_cache
*cache
= amd64_epilogue_frame_cache (this_frame
,
2883 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2885 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2888 static const struct frame_unwind amd64_epilogue_frame_unwind
=
2891 amd64_epilogue_frame_unwind_stop_reason
,
2892 amd64_epilogue_frame_this_id
,
2893 amd64_frame_prev_register
,
2895 amd64_epilogue_frame_sniffer
2898 static struct frame_id
2899 amd64_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
2903 fp
= get_frame_register_unsigned (this_frame
, AMD64_RBP_REGNUM
);
2905 return frame_id_build (fp
+ 16, get_frame_pc (this_frame
));
2908 /* 16 byte align the SP per frame requirements. */
2911 amd64_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2913 return sp
& -(CORE_ADDR
)16;
2917 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
2918 in the floating-point register set REGSET to register cache
2919 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
2922 amd64_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
2923 int regnum
, const void *fpregs
, size_t len
)
2925 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2926 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2928 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2929 amd64_supply_fxsave (regcache
, regnum
, fpregs
);
2932 /* Collect register REGNUM from the register cache REGCACHE and store
2933 it in the buffer specified by FPREGS and LEN as described by the
2934 floating-point register set REGSET. If REGNUM is -1, do this for
2935 all registers in REGSET. */
2938 amd64_collect_fpregset (const struct regset
*regset
,
2939 const struct regcache
*regcache
,
2940 int regnum
, void *fpregs
, size_t len
)
2942 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
2943 const struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2945 gdb_assert (len
>= tdep
->sizeof_fpregset
);
2946 amd64_collect_fxsave (regcache
, regnum
, fpregs
);
2949 const struct regset amd64_fpregset
=
2951 NULL
, amd64_supply_fpregset
, amd64_collect_fpregset
2955 /* Figure out where the longjmp will land. Slurp the jmp_buf out of
2956 %rdi. We expect its value to be a pointer to the jmp_buf structure
2957 from which we extract the address that we will land at. This
2958 address is copied into PC. This routine returns non-zero on
2962 amd64_get_longjmp_target (struct frame_info
*frame
, CORE_ADDR
*pc
)
2966 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2967 int jb_pc_offset
= gdbarch_tdep (gdbarch
)->jb_pc_offset
;
2968 int len
= TYPE_LENGTH (builtin_type (gdbarch
)->builtin_func_ptr
);
2970 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2971 longjmp will land. */
2972 if (jb_pc_offset
== -1)
2975 get_frame_register (frame
, AMD64_RDI_REGNUM
, buf
);
2976 jb_addr
= extract_typed_address
2977 (buf
, builtin_type (gdbarch
)->builtin_data_ptr
);
2978 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, len
))
2981 *pc
= extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
2986 static const int amd64_record_regmap
[] =
2988 AMD64_RAX_REGNUM
, AMD64_RCX_REGNUM
, AMD64_RDX_REGNUM
, AMD64_RBX_REGNUM
,
2989 AMD64_RSP_REGNUM
, AMD64_RBP_REGNUM
, AMD64_RSI_REGNUM
, AMD64_RDI_REGNUM
,
2990 AMD64_R8_REGNUM
, AMD64_R9_REGNUM
, AMD64_R10_REGNUM
, AMD64_R11_REGNUM
,
2991 AMD64_R12_REGNUM
, AMD64_R13_REGNUM
, AMD64_R14_REGNUM
, AMD64_R15_REGNUM
,
2992 AMD64_RIP_REGNUM
, AMD64_EFLAGS_REGNUM
, AMD64_CS_REGNUM
, AMD64_SS_REGNUM
,
2993 AMD64_DS_REGNUM
, AMD64_ES_REGNUM
, AMD64_FS_REGNUM
, AMD64_GS_REGNUM
2997 amd64_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
2999 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3000 const struct target_desc
*tdesc
= info
.target_desc
;
3001 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
3002 static const char *const stap_register_prefixes
[] = { "%", NULL
};
3003 static const char *const stap_register_indirection_prefixes
[] = { "(",
3005 static const char *const stap_register_indirection_suffixes
[] = { ")",
3008 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its
3009 floating-point registers. */
3010 tdep
->sizeof_fpregset
= I387_SIZEOF_FXSAVE
;
3011 tdep
->fpregset
= &amd64_fpregset
;
3013 if (! tdesc_has_registers (tdesc
))
3014 tdesc
= tdesc_amd64
;
3015 tdep
->tdesc
= tdesc
;
3017 tdep
->num_core_regs
= AMD64_NUM_GREGS
+ I387_NUM_REGS
;
3018 tdep
->register_names
= amd64_register_names
;
3020 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512") != NULL
)
3022 tdep
->zmmh_register_names
= amd64_zmmh_names
;
3023 tdep
->k_register_names
= amd64_k_names
;
3024 tdep
->xmm_avx512_register_names
= amd64_xmm_avx512_names
;
3025 tdep
->ymm16h_register_names
= amd64_ymmh_avx512_names
;
3027 tdep
->num_zmm_regs
= 32;
3028 tdep
->num_xmm_avx512_regs
= 16;
3029 tdep
->num_ymm_avx512_regs
= 16;
3031 tdep
->zmm0h_regnum
= AMD64_ZMM0H_REGNUM
;
3032 tdep
->k0_regnum
= AMD64_K0_REGNUM
;
3033 tdep
->xmm16_regnum
= AMD64_XMM16_REGNUM
;
3034 tdep
->ymm16h_regnum
= AMD64_YMM16H_REGNUM
;
3037 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx") != NULL
)
3039 tdep
->ymmh_register_names
= amd64_ymmh_names
;
3040 tdep
->num_ymm_regs
= 16;
3041 tdep
->ymm0h_regnum
= AMD64_YMM0H_REGNUM
;
3044 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
)
3046 tdep
->mpx_register_names
= amd64_mpx_names
;
3047 tdep
->bndcfgu_regnum
= AMD64_BNDCFGU_REGNUM
;
3048 tdep
->bnd0r_regnum
= AMD64_BND0R_REGNUM
;
3051 if (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments") != NULL
)
3053 const struct tdesc_feature
*feature
=
3054 tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
3055 struct tdesc_arch_data
*tdesc_data_segments
=
3056 (struct tdesc_arch_data
*) info
.tdep_info
;
3058 tdesc_numbered_register (feature
, tdesc_data_segments
,
3059 AMD64_FSBASE_REGNUM
, "fs_base");
3060 tdesc_numbered_register (feature
, tdesc_data_segments
,
3061 AMD64_GSBASE_REGNUM
, "gs_base");
3064 tdep
->num_byte_regs
= 20;
3065 tdep
->num_word_regs
= 16;
3066 tdep
->num_dword_regs
= 16;
3067 /* Avoid wiring in the MMX registers for now. */
3068 tdep
->num_mmx_regs
= 0;
3070 set_gdbarch_pseudo_register_read_value (gdbarch
,
3071 amd64_pseudo_register_read_value
);
3072 set_gdbarch_pseudo_register_write (gdbarch
,
3073 amd64_pseudo_register_write
);
3074 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
3075 amd64_ax_pseudo_register_collect
);
3077 set_tdesc_pseudo_register_name (gdbarch
, amd64_pseudo_register_name
);
3079 /* AMD64 has an FPU and 16 SSE registers. */
3080 tdep
->st0_regnum
= AMD64_ST0_REGNUM
;
3081 tdep
->num_xmm_regs
= 16;
3083 /* This is what all the fuss is about. */
3084 set_gdbarch_long_bit (gdbarch
, 64);
3085 set_gdbarch_long_long_bit (gdbarch
, 64);
3086 set_gdbarch_ptr_bit (gdbarch
, 64);
3088 /* In contrast to the i386, on AMD64 a `long double' actually takes
3089 up 128 bits, even though it's still based on the i387 extended
3090 floating-point format which has only 80 significant bits. */
3091 set_gdbarch_long_double_bit (gdbarch
, 128);
3093 set_gdbarch_num_regs (gdbarch
, AMD64_NUM_REGS
);
3095 /* Register numbers of various important registers. */
3096 set_gdbarch_sp_regnum (gdbarch
, AMD64_RSP_REGNUM
); /* %rsp */
3097 set_gdbarch_pc_regnum (gdbarch
, AMD64_RIP_REGNUM
); /* %rip */
3098 set_gdbarch_ps_regnum (gdbarch
, AMD64_EFLAGS_REGNUM
); /* %eflags */
3099 set_gdbarch_fp0_regnum (gdbarch
, AMD64_ST0_REGNUM
); /* %st(0) */
3101 /* The "default" register numbering scheme for AMD64 is referred to
3102 as the "DWARF Register Number Mapping" in the System V psABI.
3103 The preferred debugging format for all known AMD64 targets is
3104 actually DWARF2, and GCC doesn't seem to support DWARF (that is
3105 DWARF-1), but we provide the same mapping just in case. This
3106 mapping is also used for stabs, which GCC does support. */
3107 set_gdbarch_stab_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3108 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, amd64_dwarf_reg_to_regnum
);
3110 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to
3111 be in use on any of the supported AMD64 targets. */
3113 /* Call dummy code. */
3114 set_gdbarch_push_dummy_call (gdbarch
, amd64_push_dummy_call
);
3115 set_gdbarch_frame_align (gdbarch
, amd64_frame_align
);
3116 set_gdbarch_frame_red_zone_size (gdbarch
, 128);
3118 set_gdbarch_convert_register_p (gdbarch
, i387_convert_register_p
);
3119 set_gdbarch_register_to_value (gdbarch
, i387_register_to_value
);
3120 set_gdbarch_value_to_register (gdbarch
, i387_value_to_register
);
3122 set_gdbarch_return_value (gdbarch
, amd64_return_value
);
3124 set_gdbarch_skip_prologue (gdbarch
, amd64_skip_prologue
);
3126 tdep
->record_regmap
= amd64_record_regmap
;
3128 set_gdbarch_dummy_id (gdbarch
, amd64_dummy_id
);
3130 /* Hook the function epilogue frame unwinder. This unwinder is
3131 appended to the list first, so that it supercedes the other
3132 unwinders in function epilogues. */
3133 frame_unwind_prepend_unwinder (gdbarch
, &amd64_epilogue_frame_unwind
);
3135 /* Hook the prologue-based frame unwinders. */
3136 frame_unwind_append_unwinder (gdbarch
, &amd64_sigtramp_frame_unwind
);
3137 frame_unwind_append_unwinder (gdbarch
, &amd64_frame_unwind
);
3138 frame_base_set_default (gdbarch
, &amd64_frame_base
);
3140 set_gdbarch_get_longjmp_target (gdbarch
, amd64_get_longjmp_target
);
3142 set_gdbarch_relocate_instruction (gdbarch
, amd64_relocate_instruction
);
3144 set_gdbarch_gen_return_address (gdbarch
, amd64_gen_return_address
);
3146 /* SystemTap variables and functions. */
3147 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
3148 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
3149 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
3150 stap_register_indirection_prefixes
);
3151 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
3152 stap_register_indirection_suffixes
);
3153 set_gdbarch_stap_is_single_operand (gdbarch
,
3154 i386_stap_is_single_operand
);
3155 set_gdbarch_stap_parse_special_token (gdbarch
,
3156 i386_stap_parse_special_token
);
3157 set_gdbarch_insn_is_call (gdbarch
, amd64_insn_is_call
);
3158 set_gdbarch_insn_is_ret (gdbarch
, amd64_insn_is_ret
);
3159 set_gdbarch_insn_is_jump (gdbarch
, amd64_insn_is_jump
);
3163 static struct type
*
3164 amd64_x32_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3166 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3168 switch (regnum
- tdep
->eax_regnum
)
3170 case AMD64_RBP_REGNUM
: /* %ebp */
3171 case AMD64_RSP_REGNUM
: /* %esp */
3172 return builtin_type (gdbarch
)->builtin_data_ptr
;
3173 case AMD64_RIP_REGNUM
: /* %eip */
3174 return builtin_type (gdbarch
)->builtin_func_ptr
;
3177 return i386_pseudo_register_type (gdbarch
, regnum
);
3181 amd64_x32_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
3183 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3184 const struct target_desc
*tdesc
= info
.target_desc
;
3186 amd64_init_abi (info
, gdbarch
);
3188 if (! tdesc_has_registers (tdesc
))
3190 tdep
->tdesc
= tdesc
;
3192 tdep
->num_dword_regs
= 17;
3193 set_tdesc_pseudo_register_type (gdbarch
, amd64_x32_pseudo_register_type
);
3195 set_gdbarch_long_bit (gdbarch
, 32);
3196 set_gdbarch_ptr_bit (gdbarch
, 32);
3199 /* Return the target description for a specified XSAVE feature mask. */
3201 const struct target_desc
*
3202 amd64_target_description (uint64_t xcr0
)
3204 switch (xcr0
& X86_XSTATE_ALL_MASK
)
3206 case X86_XSTATE_AVX_MPX_AVX512_MASK
:
3207 return tdesc_amd64_avx_mpx_avx512
;
3208 case X86_XSTATE_AVX_AVX512_MASK
:
3209 return tdesc_amd64_avx_avx512
;
3210 case X86_XSTATE_MPX_MASK
:
3211 return tdesc_amd64_mpx
;
3212 case X86_XSTATE_AVX_MPX_MASK
:
3213 return tdesc_amd64_avx_mpx
;
3214 case X86_XSTATE_AVX_MASK
:
3215 return tdesc_amd64_avx
;
3221 /* Provide a prototype to silence -Wmissing-prototypes. */
3222 void _initialize_amd64_tdep (void);
3225 _initialize_amd64_tdep (void)
3227 initialize_tdesc_amd64 ();
3228 initialize_tdesc_amd64_avx ();
3229 initialize_tdesc_amd64_mpx ();
3230 initialize_tdesc_amd64_avx_mpx ();
3231 initialize_tdesc_amd64_avx_avx512 ();
3232 initialize_tdesc_amd64_avx_mpx_avx512 ();
3234 initialize_tdesc_x32 ();
3235 initialize_tdesc_x32_avx ();
3236 initialize_tdesc_x32_avx_avx512 ();
3240 /* The 64-bit FXSAVE format differs from the 32-bit format in the
3241 sense that the instruction pointer and data pointer are simply
3242 64-bit offsets into the code segment and the data segment instead
3243 of a selector offset pair. The functions below store the upper 32
3244 bits of these pointers (instead of just the 16-bits of the segment
3247 /* Fill register REGNUM in REGCACHE with the appropriate
3248 floating-point or SSE register value from *FXSAVE. If REGNUM is
3249 -1, do this for all registers. This function masks off any of the
3250 reserved bits in *FXSAVE. */
3253 amd64_supply_fxsave (struct regcache
*regcache
, int regnum
,
3256 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3257 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3259 i387_supply_fxsave (regcache
, regnum
, fxsave
);
3262 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3264 const gdb_byte
*regs
= (const gdb_byte
*) fxsave
;
3266 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3267 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3268 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3269 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3273 /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */
3276 amd64_supply_xsave (struct regcache
*regcache
, int regnum
,
3279 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3280 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3282 i387_supply_xsave (regcache
, regnum
, xsave
);
3285 && gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3287 const gdb_byte
*regs
= (const gdb_byte
*) xsave
;
3289 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3290 regcache_raw_supply (regcache
, I387_FISEG_REGNUM (tdep
),
3292 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3293 regcache_raw_supply (regcache
, I387_FOSEG_REGNUM (tdep
),
3298 /* Fill register REGNUM (if it is a floating-point or SSE register) in
3299 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for
3300 all registers. This function doesn't touch any of the reserved
3304 amd64_collect_fxsave (const struct regcache
*regcache
, int regnum
,
3307 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3308 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3309 gdb_byte
*regs
= (gdb_byte
*) fxsave
;
3311 i387_collect_fxsave (regcache
, regnum
, fxsave
);
3313 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3315 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3316 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
), regs
+ 12);
3317 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3318 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
), regs
+ 20);
3322 /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */
3325 amd64_collect_xsave (const struct regcache
*regcache
, int regnum
,
3326 void *xsave
, int gcore
)
3328 struct gdbarch
*gdbarch
= get_regcache_arch (regcache
);
3329 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3330 gdb_byte
*regs
= (gdb_byte
*) xsave
;
3332 i387_collect_xsave (regcache
, regnum
, xsave
, gcore
);
3334 if (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
== 64)
3336 if (regnum
== -1 || regnum
== I387_FISEG_REGNUM (tdep
))
3337 regcache_raw_collect (regcache
, I387_FISEG_REGNUM (tdep
),
3339 if (regnum
== -1 || regnum
== I387_FOSEG_REGNUM (tdep
))
3340 regcache_raw_collect (regcache
, I387_FOSEG_REGNUM (tdep
),