1 /* Common target dependent code for GDB on ARM systems.
3 Copyright (C) 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1998, 1999,
4 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
23 #include <ctype.h> /* XXX for isupper () */
30 #include "gdb_string.h"
31 #include "dis-asm.h" /* For register styles. */
35 #include "arch-utils.h"
37 #include "frame-unwind.h"
38 #include "frame-base.h"
39 #include "trad-frame.h"
41 #include "dwarf2-frame.h"
44 #include "gdb/sim-arm.h"
47 #include "coff/internal.h"
50 #include "gdb_assert.h"
54 /* Macros for setting and testing a bit in a minimal symbol that marks
55 it as Thumb function. The MSB of the minimal symbol's "info" field
56 is used for this purpose.
58 MSYMBOL_SET_SPECIAL Actually sets the "special" bit.
59 MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. */
61 #define MSYMBOL_SET_SPECIAL(msym) \
62 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) \
65 #define MSYMBOL_IS_SPECIAL(msym) \
66 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
68 /* The list of available "set arm ..." and "show arm ..." commands. */
69 static struct cmd_list_element
*setarmcmdlist
= NULL
;
70 static struct cmd_list_element
*showarmcmdlist
= NULL
;
72 /* The type of floating-point to use. Keep this in sync with enum
73 arm_float_model, and the help string in _initialize_arm_tdep. */
74 static const char *fp_model_strings
[] =
84 /* A variable that can be configured by the user. */
85 static enum arm_float_model arm_fp_model
= ARM_FLOAT_AUTO
;
86 static const char *current_fp_model
= "auto";
88 /* The ABI to use. Keep this in sync with arm_abi_kind. */
89 static const char *arm_abi_strings
[] =
97 /* A variable that can be configured by the user. */
98 static enum arm_abi_kind arm_abi_global
= ARM_ABI_AUTO
;
99 static const char *arm_abi_string
= "auto";
101 /* Number of different reg name sets (options). */
102 static int num_disassembly_options
;
104 /* We have more registers than the disassembler as gdb can print the value
105 of special registers as well.
106 The general register names are overwritten by whatever is being used by
107 the disassembler at the moment. We also adjust the case of cpsr and fps. */
109 /* Initial value: Register names used in ARM's ISA documentation. */
110 static char * arm_register_name_strings
[] =
111 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
112 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
113 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
114 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
115 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
116 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
117 "fps", "cpsr" }; /* 24 25 */
118 static char **arm_register_names
= arm_register_name_strings
;
120 /* Valid register name styles. */
121 static const char **valid_disassembly_styles
;
123 /* Disassembly style to use. Default to "std" register names. */
124 static const char *disassembly_style
;
125 /* Index to that option in the opcodes table. */
126 static int current_option
;
128 /* This is used to keep the bfd arch_info in sync with the disassembly
130 static void set_disassembly_style_sfunc(char *, int,
131 struct cmd_list_element
*);
132 static void set_disassembly_style (void);
134 static void convert_from_extended (const struct floatformat
*, const void *,
136 static void convert_to_extended (const struct floatformat
*, void *,
139 struct arm_prologue_cache
141 /* The stack pointer at the time this frame was created; i.e. the
142 caller's stack pointer when this function was called. It is used
143 to identify this frame. */
146 /* The frame base for this frame is just prev_sp + frame offset -
147 frame size. FRAMESIZE is the size of this stack frame, and
148 FRAMEOFFSET if the initial offset from the stack pointer (this
149 frame's stack pointer, not PREV_SP) to the frame base. */
154 /* The register used to hold the frame pointer for this frame. */
157 /* Saved register offsets. */
158 struct trad_frame_saved_reg
*saved_regs
;
161 /* Addresses for calling Thumb functions have the bit 0 set.
162 Here are some macros to test, set, or clear bit 0 of addresses. */
163 #define IS_THUMB_ADDR(addr) ((addr) & 1)
164 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
165 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
167 /* Set to true if the 32-bit mode is in use. */
171 /* Determine if the program counter specified in MEMADDR is in a Thumb
175 arm_pc_is_thumb (CORE_ADDR memaddr
)
177 struct minimal_symbol
*sym
;
179 /* If bit 0 of the address is set, assume this is a Thumb address. */
180 if (IS_THUMB_ADDR (memaddr
))
183 /* Thumb functions have a "special" bit set in minimal symbols. */
184 sym
= lookup_minimal_symbol_by_pc (memaddr
);
187 return (MSYMBOL_IS_SPECIAL (sym
));
195 /* Remove useless bits from addresses in a running program. */
197 arm_addr_bits_remove (CORE_ADDR val
)
200 return (val
& (arm_pc_is_thumb (val
) ? 0xfffffffe : 0xfffffffc));
202 return (val
& 0x03fffffc);
205 /* When reading symbols, we need to zap the low bit of the address,
206 which may be set to 1 for Thumb functions. */
208 arm_smash_text_address (CORE_ADDR val
)
213 /* Immediately after a function call, return the saved pc. Can't
214 always go through the frames for this because on some machines the
215 new frame is not set up until the new function executes some
219 arm_saved_pc_after_call (struct frame_info
*frame
)
221 return ADDR_BITS_REMOVE (read_register (ARM_LR_REGNUM
));
224 /* A typical Thumb prologue looks like this:
228 Sometimes the latter instruction may be replaced by:
236 or, on tpcs, like this:
243 There is always one instruction of three classes:
248 When we have found at least one of each class we are done with the prolog.
249 Note that the "sub sp, #NN" before the push does not count.
253 thumb_skip_prologue (CORE_ADDR pc
, CORE_ADDR func_end
)
255 CORE_ADDR current_pc
;
257 bit 0 - push { rlist }
258 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
259 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
263 for (current_pc
= pc
;
264 current_pc
+ 2 < func_end
&& current_pc
< pc
+ 40;
267 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
269 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
271 findmask
|= 1; /* push found */
273 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
276 if ((findmask
& 1) == 0) /* before push ? */
279 findmask
|= 4; /* add/sub sp found */
281 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
283 findmask
|= 2; /* setting of r7 found */
285 else if (insn
== 0x466f) /* mov r7, sp */
287 findmask
|= 2; /* setting of r7 found */
289 else if (findmask
== (4+2+1))
291 /* We have found one of each type of prologue instruction */
295 /* Something in the prolog that we don't care about or some
296 instruction from outside the prolog scheduled here for
304 /* Advance the PC across any function entry prologue instructions to
305 reach some "real" code.
307 The APCS (ARM Procedure Call Standard) defines the following
311 [stmfd sp!, {a1,a2,a3,a4}]
312 stmfd sp!, {...,fp,ip,lr,pc}
313 [stfe f7, [sp, #-12]!]
314 [stfe f6, [sp, #-12]!]
315 [stfe f5, [sp, #-12]!]
316 [stfe f4, [sp, #-12]!]
317 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
320 arm_skip_prologue (CORE_ADDR pc
)
324 CORE_ADDR func_addr
, func_end
= 0;
326 struct symtab_and_line sal
;
328 /* If we're in a dummy frame, don't even try to skip the prologue. */
329 if (deprecated_pc_in_call_dummy (pc
))
332 /* See what the symbol table says. */
334 if (find_pc_partial_function (pc
, &func_name
, &func_addr
, &func_end
))
338 /* Found a function. */
339 sym
= lookup_symbol (func_name
, NULL
, VAR_DOMAIN
, NULL
, NULL
);
340 if (sym
&& SYMBOL_LANGUAGE (sym
) != language_asm
)
342 /* Don't use this trick for assembly source files. */
343 sal
= find_pc_line (func_addr
, 0);
344 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
349 /* Check if this is Thumb code. */
350 if (arm_pc_is_thumb (pc
))
351 return thumb_skip_prologue (pc
, func_end
);
353 /* Can't find the prologue end in the symbol table, try it the hard way
354 by disassembling the instructions. */
356 /* Like arm_scan_prologue, stop no later than pc + 64. */
357 if (func_end
== 0 || func_end
> pc
+ 64)
360 for (skip_pc
= pc
; skip_pc
< func_end
; skip_pc
+= 4)
362 inst
= read_memory_integer (skip_pc
, 4);
364 /* "mov ip, sp" is no longer a required part of the prologue. */
365 if (inst
== 0xe1a0c00d) /* mov ip, sp */
368 if ((inst
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
371 if ((inst
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
374 /* Some prologues begin with "str lr, [sp, #-4]!". */
375 if (inst
== 0xe52de004) /* str lr, [sp, #-4]! */
378 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
381 if ((inst
& 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */
384 /* Any insns after this point may float into the code, if it makes
385 for better instruction scheduling, so we skip them only if we
386 find them, but still consider the function to be frame-ful. */
388 /* We may have either one sfmfd instruction here, or several stfe
389 insns, depending on the version of floating point code we
391 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
394 if ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
397 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
400 if ((inst
& 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */
403 if ((inst
& 0xffffc000) == 0xe54b0000 || /* strb r(0123),[r11,#-nn] */
404 (inst
& 0xffffc0f0) == 0xe14b00b0 || /* strh r(0123),[r11,#-nn] */
405 (inst
& 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */
408 if ((inst
& 0xffffc000) == 0xe5cd0000 || /* strb r(0123),[sp,#nn] */
409 (inst
& 0xffffc0f0) == 0xe1cd00b0 || /* strh r(0123),[sp,#nn] */
410 (inst
& 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */
413 /* Un-recognized instruction; stop scanning. */
417 return skip_pc
; /* End of prologue */
421 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
422 This function decodes a Thumb function prologue to determine:
423 1) the size of the stack frame
424 2) which registers are saved on it
425 3) the offsets of saved regs
426 4) the offset from the stack pointer to the frame pointer
428 A typical Thumb function prologue would create this stack frame
429 (offsets relative to FP)
430 old SP -> 24 stack parameters
433 R7 -> 0 local variables (16 bytes)
434 SP -> -12 additional stack space (12 bytes)
435 The frame size would thus be 36 bytes, and the frame offset would be
436 12 bytes. The frame register is R7.
438 The comments for thumb_skip_prolog() describe the algorithm we use
439 to detect the end of the prolog. */
443 thumb_scan_prologue (CORE_ADDR prev_pc
, struct arm_prologue_cache
*cache
)
445 CORE_ADDR prologue_start
;
446 CORE_ADDR prologue_end
;
447 CORE_ADDR current_pc
;
448 /* Which register has been copied to register n? */
451 bit 0 - push { rlist }
452 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
453 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
458 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
460 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
462 if (sal
.line
== 0) /* no line info, use current PC */
463 prologue_end
= prev_pc
;
464 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
465 prologue_end
= sal
.end
; /* (probably means no prologue) */
468 /* We're in the boondocks: allow for
469 16 pushes, an add, and "mv fp,sp". */
470 prologue_end
= prologue_start
+ 40;
472 prologue_end
= min (prologue_end
, prev_pc
);
474 /* Initialize the saved register map. When register H is copied to
475 register L, we will put H in saved_reg[L]. */
476 for (i
= 0; i
< 16; i
++)
479 /* Search the prologue looking for instructions that set up the
480 frame pointer, adjust the stack pointer, and save registers.
481 Do this until all basic prolog instructions are found. */
483 cache
->framesize
= 0;
484 for (current_pc
= prologue_start
;
485 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
492 insn
= read_memory_unsigned_integer (current_pc
, 2);
494 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
497 findmask
|= 1; /* push found */
498 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
499 whether to save LR (R14). */
500 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
502 /* Calculate offsets of saved R0-R7 and LR. */
503 for (regno
= ARM_LR_REGNUM
; regno
>= 0; regno
--)
504 if (mask
& (1 << regno
))
506 cache
->framesize
+= 4;
507 cache
->saved_regs
[saved_reg
[regno
]].addr
= -cache
->framesize
;
508 /* Reset saved register map. */
509 saved_reg
[regno
] = regno
;
512 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR
515 if ((findmask
& 1) == 0) /* before push? */
518 findmask
|= 4; /* add/sub sp found */
520 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
521 if (insn
& 0x80) /* is it signed? (==subtracting) */
523 cache
->frameoffset
+= offset
;
526 cache
->framesize
-= offset
;
528 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
530 findmask
|= 2; /* setting of r7 found */
531 cache
->framereg
= THUMB_FP_REGNUM
;
532 /* get scaled offset */
533 cache
->frameoffset
= (insn
& 0xff) << 2;
535 else if (insn
== 0x466f) /* mov r7, sp */
537 findmask
|= 2; /* setting of r7 found */
538 cache
->framereg
= THUMB_FP_REGNUM
;
539 cache
->frameoffset
= 0;
540 saved_reg
[THUMB_FP_REGNUM
] = ARM_SP_REGNUM
;
542 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
544 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
545 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
546 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
549 /* Something in the prolog that we don't care about or some
550 instruction from outside the prolog scheduled here for
556 /* This function decodes an ARM function prologue to determine:
557 1) the size of the stack frame
558 2) which registers are saved on it
559 3) the offsets of saved regs
560 4) the offset from the stack pointer to the frame pointer
561 This information is stored in the "extra" fields of the frame_info.
563 There are two basic forms for the ARM prologue. The fixed argument
564 function call will look like:
567 stmfd sp!, {fp, ip, lr, pc}
571 Which would create this stack frame (offsets relative to FP):
572 IP -> 4 (caller's stack)
573 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
574 -4 LR (return address in caller)
575 -8 IP (copy of caller's SP)
577 SP -> -28 Local variables
579 The frame size would thus be 32 bytes, and the frame offset would be
580 28 bytes. The stmfd call can also save any of the vN registers it
581 plans to use, which increases the frame size accordingly.
583 Note: The stored PC is 8 off of the STMFD instruction that stored it
584 because the ARM Store instructions always store PC + 8 when you read
587 A variable argument function call will look like:
590 stmfd sp!, {a1, a2, a3, a4}
591 stmfd sp!, {fp, ip, lr, pc}
594 Which would create this stack frame (offsets relative to FP):
595 IP -> 20 (caller's stack)
600 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
601 -4 LR (return address in caller)
602 -8 IP (copy of caller's SP)
604 SP -> -28 Local variables
606 The frame size would thus be 48 bytes, and the frame offset would be
609 There is another potential complication, which is that the optimizer
610 will try to separate the store of fp in the "stmfd" instruction from
611 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
612 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
614 Also, note, the original version of the ARM toolchain claimed that there
617 instruction at the end of the prologue. I have never seen GCC produce
618 this, and the ARM docs don't mention it. We still test for it below in
624 arm_scan_prologue (struct frame_info
*next_frame
, struct arm_prologue_cache
*cache
)
626 int regno
, sp_offset
, fp_offset
, ip_offset
;
627 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
628 CORE_ADDR prev_pc
= frame_pc_unwind (next_frame
);
630 /* Assume there is no frame until proven otherwise. */
631 cache
->framereg
= ARM_SP_REGNUM
;
632 cache
->framesize
= 0;
633 cache
->frameoffset
= 0;
635 /* Check for Thumb prologue. */
636 if (arm_pc_is_thumb (prev_pc
))
638 thumb_scan_prologue (prev_pc
, cache
);
642 /* Find the function prologue. If we can't find the function in
643 the symbol table, peek in the stack frame to find the PC. */
644 if (find_pc_partial_function (prev_pc
, NULL
, &prologue_start
, &prologue_end
))
646 /* One way to find the end of the prologue (which works well
647 for unoptimized code) is to do the following:
649 struct symtab_and_line sal = find_pc_line (prologue_start, 0);
652 prologue_end = prev_pc;
653 else if (sal.end < prologue_end)
654 prologue_end = sal.end;
656 This mechanism is very accurate so long as the optimizer
657 doesn't move any instructions from the function body into the
658 prologue. If this happens, sal.end will be the last
659 instruction in the first hunk of prologue code just before
660 the first instruction that the scheduler has moved from
661 the body to the prologue.
663 In order to make sure that we scan all of the prologue
664 instructions, we use a slightly less accurate mechanism which
665 may scan more than necessary. To help compensate for this
666 lack of accuracy, the prologue scanning loop below contains
667 several clauses which'll cause the loop to terminate early if
668 an implausible prologue instruction is encountered.
674 is a suitable endpoint since it accounts for the largest
675 possible prologue plus up to five instructions inserted by
678 if (prologue_end
> prologue_start
+ 64)
680 prologue_end
= prologue_start
+ 64; /* See above. */
685 /* We have no symbol information. Our only option is to assume this
686 function has a standard stack frame and the normal frame register.
687 Then, we can find the value of our frame pointer on entrance to
688 the callee (or at the present moment if this is the innermost frame).
689 The value stored there should be the address of the stmfd + 8. */
691 LONGEST return_value
;
693 frame_loc
= frame_unwind_register_unsigned (next_frame
, ARM_FP_REGNUM
);
694 if (!safe_read_memory_integer (frame_loc
, 4, &return_value
))
698 prologue_start
= ADDR_BITS_REMOVE (return_value
) - 8;
699 prologue_end
= prologue_start
+ 64; /* See above. */
703 if (prev_pc
< prologue_end
)
704 prologue_end
= prev_pc
;
706 /* Now search the prologue looking for instructions that set up the
707 frame pointer, adjust the stack pointer, and save registers.
709 Be careful, however, and if it doesn't look like a prologue,
710 don't try to scan it. If, for instance, a frameless function
711 begins with stmfd sp!, then we will tell ourselves there is
712 a frame, which will confuse stack traceback, as well as "finish"
713 and other operations that rely on a knowledge of the stack
716 In the APCS, the prologue should start with "mov ip, sp" so
717 if we don't see this as the first insn, we will stop.
719 [Note: This doesn't seem to be true any longer, so it's now an
720 optional part of the prologue. - Kevin Buettner, 2001-11-20]
722 [Note further: The "mov ip,sp" only seems to be missing in
723 frameless functions at optimization level "-O2" or above,
724 in which case it is often (but not always) replaced by
725 "str lr, [sp, #-4]!". - Michael Snyder, 2002-04-23] */
727 sp_offset
= fp_offset
= ip_offset
= 0;
729 for (current_pc
= prologue_start
;
730 current_pc
< prologue_end
;
733 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
735 if (insn
== 0xe1a0c00d) /* mov ip, sp */
740 else if ((insn
& 0xfffff000) == 0xe28dc000) /* add ip, sp #n */
742 unsigned imm
= insn
& 0xff; /* immediate value */
743 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
744 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
748 else if ((insn
& 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */
750 unsigned imm
= insn
& 0xff; /* immediate value */
751 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
752 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
756 else if (insn
== 0xe52de004) /* str lr, [sp, #-4]! */
759 cache
->saved_regs
[ARM_LR_REGNUM
].addr
= sp_offset
;
762 else if ((insn
& 0xffff0000) == 0xe92d0000)
763 /* stmfd sp!, {..., fp, ip, lr, pc}
765 stmfd sp!, {a1, a2, a3, a4} */
767 int mask
= insn
& 0xffff;
769 /* Calculate offsets of saved registers. */
770 for (regno
= ARM_PC_REGNUM
; regno
>= 0; regno
--)
771 if (mask
& (1 << regno
))
774 cache
->saved_regs
[regno
].addr
= sp_offset
;
777 else if ((insn
& 0xffffc000) == 0xe54b0000 || /* strb rx,[r11,#-n] */
778 (insn
& 0xffffc0f0) == 0xe14b00b0 || /* strh rx,[r11,#-n] */
779 (insn
& 0xffffc000) == 0xe50b0000) /* str rx,[r11,#-n] */
781 /* No need to add this to saved_regs -- it's just an arg reg. */
784 else if ((insn
& 0xffffc000) == 0xe5cd0000 || /* strb rx,[sp,#n] */
785 (insn
& 0xffffc0f0) == 0xe1cd00b0 || /* strh rx,[sp,#n] */
786 (insn
& 0xffffc000) == 0xe58d0000) /* str rx,[sp,#n] */
788 /* No need to add this to saved_regs -- it's just an arg reg. */
791 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
793 unsigned imm
= insn
& 0xff; /* immediate value */
794 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
795 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
796 fp_offset
= -imm
+ ip_offset
;
797 cache
->framereg
= ARM_FP_REGNUM
;
799 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
801 unsigned imm
= insn
& 0xff; /* immediate value */
802 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
803 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
806 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
809 regno
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x07);
810 cache
->saved_regs
[regno
].addr
= sp_offset
;
812 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
815 unsigned int fp_start_reg
, fp_bound_reg
;
817 if ((insn
& 0x800) == 0x800) /* N0 is set */
819 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
826 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
832 fp_start_reg
= ARM_F0_REGNUM
+ ((insn
>> 12) & 0x7);
833 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
834 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
837 cache
->saved_regs
[fp_start_reg
++].addr
= sp_offset
;
840 else if ((insn
& 0xf0000000) != 0xe0000000)
841 break; /* Condition not true, exit early */
842 else if ((insn
& 0xfe200000) == 0xe8200000) /* ldm? */
843 break; /* Don't scan past a block load */
845 /* The optimizer might shove anything into the prologue,
846 so we just skip what we don't recognize. */
850 /* The frame size is just the negative of the offset (from the
851 original SP) of the last thing thing we pushed on the stack.
852 The frame offset is [new FP] - [new SP]. */
853 cache
->framesize
= -sp_offset
;
854 if (cache
->framereg
== ARM_FP_REGNUM
)
855 cache
->frameoffset
= fp_offset
- sp_offset
;
857 cache
->frameoffset
= 0;
860 static struct arm_prologue_cache
*
861 arm_make_prologue_cache (struct frame_info
*next_frame
)
864 struct arm_prologue_cache
*cache
;
865 CORE_ADDR unwound_fp
;
867 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
868 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
870 arm_scan_prologue (next_frame
, cache
);
872 unwound_fp
= frame_unwind_register_unsigned (next_frame
, cache
->framereg
);
876 cache
->prev_sp
= unwound_fp
+ cache
->framesize
- cache
->frameoffset
;
878 /* Calculate actual addresses of saved registers using offsets
879 determined by arm_scan_prologue. */
880 for (reg
= 0; reg
< NUM_REGS
; reg
++)
881 if (trad_frame_addr_p (cache
->saved_regs
, reg
))
882 cache
->saved_regs
[reg
].addr
+= cache
->prev_sp
;
887 /* Our frame ID for a normal frame is the current function's starting PC
888 and the caller's SP when we were called. */
891 arm_prologue_this_id (struct frame_info
*next_frame
,
893 struct frame_id
*this_id
)
895 struct arm_prologue_cache
*cache
;
899 if (*this_cache
== NULL
)
900 *this_cache
= arm_make_prologue_cache (next_frame
);
903 func
= frame_func_unwind (next_frame
);
905 /* This is meant to halt the backtrace at "_start". Make sure we
906 don't halt it at a generic dummy frame. */
907 if (func
<= LOWEST_PC
)
910 /* If we've hit a wall, stop. */
911 if (cache
->prev_sp
== 0)
914 id
= frame_id_build (cache
->prev_sp
, func
);
919 arm_prologue_prev_register (struct frame_info
*next_frame
,
923 enum lval_type
*lvalp
,
928 struct arm_prologue_cache
*cache
;
930 if (*this_cache
== NULL
)
931 *this_cache
= arm_make_prologue_cache (next_frame
);
934 /* If we are asked to unwind the PC, then we need to return the LR
935 instead. The saved value of PC points into this frame's
936 prologue, not the next frame's resume location. */
937 if (prev_regnum
== ARM_PC_REGNUM
)
938 prev_regnum
= ARM_LR_REGNUM
;
940 /* SP is generally not saved to the stack, but this frame is
941 identified by NEXT_FRAME's stack pointer at the time of the call.
942 The value was already reconstructed into PREV_SP. */
943 if (prev_regnum
== ARM_SP_REGNUM
)
947 store_unsigned_integer (valuep
, 4, cache
->prev_sp
);
951 trad_frame_get_prev_register (next_frame
, cache
->saved_regs
, prev_regnum
,
952 optimized
, lvalp
, addrp
, realnump
, valuep
);
955 struct frame_unwind arm_prologue_unwind
= {
957 arm_prologue_this_id
,
958 arm_prologue_prev_register
961 static const struct frame_unwind
*
962 arm_prologue_unwind_sniffer (struct frame_info
*next_frame
)
964 return &arm_prologue_unwind
;
967 static struct arm_prologue_cache
*
968 arm_make_stub_cache (struct frame_info
*next_frame
)
971 struct arm_prologue_cache
*cache
;
972 CORE_ADDR unwound_fp
;
974 cache
= frame_obstack_zalloc (sizeof (struct arm_prologue_cache
));
975 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
977 cache
->prev_sp
= frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
);
982 /* Our frame ID for a stub frame is the current SP and LR. */
985 arm_stub_this_id (struct frame_info
*next_frame
,
987 struct frame_id
*this_id
)
989 struct arm_prologue_cache
*cache
;
991 if (*this_cache
== NULL
)
992 *this_cache
= arm_make_stub_cache (next_frame
);
995 *this_id
= frame_id_build (cache
->prev_sp
,
996 frame_pc_unwind (next_frame
));
999 struct frame_unwind arm_stub_unwind
= {
1002 arm_prologue_prev_register
1005 static const struct frame_unwind
*
1006 arm_stub_unwind_sniffer (struct frame_info
*next_frame
)
1010 if (in_plt_section (frame_unwind_address_in_block (next_frame
), NULL
)
1011 || target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
1012 return &arm_stub_unwind
;
1018 arm_normal_frame_base (struct frame_info
*next_frame
, void **this_cache
)
1020 struct arm_prologue_cache
*cache
;
1022 if (*this_cache
== NULL
)
1023 *this_cache
= arm_make_prologue_cache (next_frame
);
1024 cache
= *this_cache
;
1026 return cache
->prev_sp
+ cache
->frameoffset
- cache
->framesize
;
1029 struct frame_base arm_normal_base
= {
1030 &arm_prologue_unwind
,
1031 arm_normal_frame_base
,
1032 arm_normal_frame_base
,
1033 arm_normal_frame_base
1036 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
1037 dummy frame. The frame ID's base needs to match the TOS value
1038 saved by save_dummy_frame_tos() and returned from
1039 arm_push_dummy_call, and the PC needs to match the dummy frame's
1042 static struct frame_id
1043 arm_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1045 return frame_id_build (frame_unwind_register_unsigned (next_frame
, ARM_SP_REGNUM
),
1046 frame_pc_unwind (next_frame
));
1049 /* Given THIS_FRAME, find the previous frame's resume PC (which will
1050 be used to construct the previous frame's ID, after looking up the
1051 containing function). */
1054 arm_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1057 pc
= frame_unwind_register_unsigned (this_frame
, ARM_PC_REGNUM
);
1058 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1062 arm_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1064 return frame_unwind_register_unsigned (this_frame
, ARM_SP_REGNUM
);
1067 /* When arguments must be pushed onto the stack, they go on in reverse
1068 order. The code below implements a FILO (stack) to do this. */
1073 struct stack_item
*prev
;
1077 static struct stack_item
*
1078 push_stack_item (struct stack_item
*prev
, void *contents
, int len
)
1080 struct stack_item
*si
;
1081 si
= xmalloc (sizeof (struct stack_item
));
1082 si
->data
= xmalloc (len
);
1085 memcpy (si
->data
, contents
, len
);
1089 static struct stack_item
*
1090 pop_stack_item (struct stack_item
*si
)
1092 struct stack_item
*dead
= si
;
1100 /* Return the alignment (in bytes) of the given type. */
1103 arm_type_align (struct type
*t
)
1109 t
= check_typedef (t
);
1110 switch (TYPE_CODE (t
))
1113 /* Should never happen. */
1114 internal_error (__FILE__
, __LINE__
, _("unknown type alignment"));
1118 case TYPE_CODE_ENUM
:
1122 case TYPE_CODE_RANGE
:
1123 case TYPE_CODE_BITSTRING
:
1125 case TYPE_CODE_CHAR
:
1126 case TYPE_CODE_BOOL
:
1127 return TYPE_LENGTH (t
);
1129 case TYPE_CODE_ARRAY
:
1130 case TYPE_CODE_COMPLEX
:
1131 /* TODO: What about vector types? */
1132 return arm_type_align (TYPE_TARGET_TYPE (t
));
1134 case TYPE_CODE_STRUCT
:
1135 case TYPE_CODE_UNION
:
1137 for (n
= 0; n
< TYPE_NFIELDS (t
); n
++)
1139 falign
= arm_type_align (TYPE_FIELD_TYPE (t
, n
));
1147 /* We currently only support passing parameters in integer registers. This
1148 conforms with GCC's default model. Several other variants exist and
1149 we should probably support some of them based on the selected ABI. */
1152 arm_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1153 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
1154 struct value
**args
, CORE_ADDR sp
, int struct_return
,
1155 CORE_ADDR struct_addr
)
1160 struct stack_item
*si
= NULL
;
1162 /* Set the return address. For the ARM, the return breakpoint is
1163 always at BP_ADDR. */
1164 /* XXX Fix for Thumb. */
1165 regcache_cooked_write_unsigned (regcache
, ARM_LR_REGNUM
, bp_addr
);
1167 /* Walk through the list of args and determine how large a temporary
1168 stack is required. Need to take care here as structs may be
1169 passed on the stack, and we have to to push them. */
1172 argreg
= ARM_A1_REGNUM
;
1175 /* Some platforms require a double-word aligned stack. Make sure sp
1176 is correctly aligned before we start. We always do this even if
1177 it isn't really needed -- it can never hurt things. */
1178 sp
&= ~(CORE_ADDR
)(2 * DEPRECATED_REGISTER_SIZE
- 1);
1180 /* The struct_return pointer occupies the first parameter
1181 passing register. */
1185 fprintf_unfiltered (gdb_stdlog
, "struct return in %s = 0x%s\n",
1186 REGISTER_NAME (argreg
), paddr (struct_addr
));
1187 regcache_cooked_write_unsigned (regcache
, argreg
, struct_addr
);
1191 for (argnum
= 0; argnum
< nargs
; argnum
++)
1194 struct type
*arg_type
;
1195 struct type
*target_type
;
1196 enum type_code typecode
;
1200 arg_type
= check_typedef (value_type (args
[argnum
]));
1201 len
= TYPE_LENGTH (arg_type
);
1202 target_type
= TYPE_TARGET_TYPE (arg_type
);
1203 typecode
= TYPE_CODE (arg_type
);
1204 val
= value_contents_writeable (args
[argnum
]);
1206 align
= arm_type_align (arg_type
);
1207 /* Round alignment up to a whole number of words. */
1208 align
= (align
+ INT_REGISTER_SIZE
- 1) & ~(INT_REGISTER_SIZE
- 1);
1209 /* Different ABIs have different maximum alignments. */
1210 if (gdbarch_tdep (gdbarch
)->arm_abi
== ARM_ABI_APCS
)
1212 /* The APCS ABI only requires word alignment. */
1213 align
= INT_REGISTER_SIZE
;
1217 /* The AAPCS requires at most doubleword alignment. */
1218 if (align
> INT_REGISTER_SIZE
* 2)
1219 align
= INT_REGISTER_SIZE
* 2;
1222 /* Push stack padding for dowubleword alignment. */
1223 if (nstack
& (align
- 1))
1225 si
= push_stack_item (si
, val
, INT_REGISTER_SIZE
);
1226 nstack
+= INT_REGISTER_SIZE
;
1229 /* Doubleword aligned quantities must go in even register pairs. */
1230 if (argreg
<= ARM_LAST_ARG_REGNUM
1231 && align
> INT_REGISTER_SIZE
1235 /* If the argument is a pointer to a function, and it is a
1236 Thumb function, create a LOCAL copy of the value and set
1237 the THUMB bit in it. */
1238 if (TYPE_CODE_PTR
== typecode
1239 && target_type
!= NULL
1240 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1242 CORE_ADDR regval
= extract_unsigned_integer (val
, len
);
1243 if (arm_pc_is_thumb (regval
))
1246 store_unsigned_integer (val
, len
, MAKE_THUMB_ADDR (regval
));
1250 /* Copy the argument to general registers or the stack in
1251 register-sized pieces. Large arguments are split between
1252 registers and stack. */
1255 int partial_len
= len
< DEPRECATED_REGISTER_SIZE
? len
: DEPRECATED_REGISTER_SIZE
;
1257 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1259 /* The argument is being passed in a general purpose
1261 CORE_ADDR regval
= extract_unsigned_integer (val
, partial_len
);
1263 fprintf_unfiltered (gdb_stdlog
, "arg %d in %s = 0x%s\n",
1264 argnum
, REGISTER_NAME (argreg
),
1265 phex (regval
, DEPRECATED_REGISTER_SIZE
));
1266 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1271 /* Push the arguments onto the stack. */
1273 fprintf_unfiltered (gdb_stdlog
, "arg %d @ sp + %d\n",
1275 si
= push_stack_item (si
, val
, DEPRECATED_REGISTER_SIZE
);
1276 nstack
+= DEPRECATED_REGISTER_SIZE
;
1283 /* If we have an odd number of words to push, then decrement the stack
1284 by one word now, so first stack argument will be dword aligned. */
1291 write_memory (sp
, si
->data
, si
->len
);
1292 si
= pop_stack_item (si
);
1295 /* Finally, update teh SP register. */
1296 regcache_cooked_write_unsigned (regcache
, ARM_SP_REGNUM
, sp
);
1302 print_fpu_flags (int flags
)
1304 if (flags
& (1 << 0))
1305 fputs ("IVO ", stdout
);
1306 if (flags
& (1 << 1))
1307 fputs ("DVZ ", stdout
);
1308 if (flags
& (1 << 2))
1309 fputs ("OFL ", stdout
);
1310 if (flags
& (1 << 3))
1311 fputs ("UFL ", stdout
);
1312 if (flags
& (1 << 4))
1313 fputs ("INX ", stdout
);
1317 /* Print interesting information about the floating point processor
1318 (if present) or emulator. */
1320 arm_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
1321 struct frame_info
*frame
, const char *args
)
1323 unsigned long status
= read_register (ARM_FPS_REGNUM
);
1326 type
= (status
>> 24) & 127;
1327 if (status
& (1 << 31))
1328 printf (_("Hardware FPU type %d\n"), type
);
1330 printf (_("Software FPU type %d\n"), type
);
1331 /* i18n: [floating point unit] mask */
1332 fputs (_("mask: "), stdout
);
1333 print_fpu_flags (status
>> 16);
1334 /* i18n: [floating point unit] flags */
1335 fputs (_("flags: "), stdout
);
1336 print_fpu_flags (status
);
1339 /* Return the GDB type object for the "standard" data type of data in
1342 static struct type
*
1343 arm_register_type (struct gdbarch
*gdbarch
, int regnum
)
1345 if (regnum
>= ARM_F0_REGNUM
&& regnum
< ARM_F0_REGNUM
+ NUM_FREGS
)
1347 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1348 return builtin_type_arm_ext_big
;
1350 return builtin_type_arm_ext_littlebyte_bigword
;
1353 return builtin_type_int32
;
1356 /* Index within `registers' of the first byte of the space for
1360 arm_register_byte (int regnum
)
1362 if (regnum
< ARM_F0_REGNUM
)
1363 return regnum
* INT_REGISTER_SIZE
;
1364 else if (regnum
< ARM_PS_REGNUM
)
1365 return (NUM_GREGS
* INT_REGISTER_SIZE
1366 + (regnum
- ARM_F0_REGNUM
) * FP_REGISTER_SIZE
);
1368 return (NUM_GREGS
* INT_REGISTER_SIZE
1369 + NUM_FREGS
* FP_REGISTER_SIZE
1370 + (regnum
- ARM_FPS_REGNUM
) * STATUS_REGISTER_SIZE
);
1373 /* Map GDB internal REGNUM onto the Arm simulator register numbers. */
1375 arm_register_sim_regno (int regnum
)
1378 gdb_assert (reg
>= 0 && reg
< NUM_REGS
);
1380 if (reg
< NUM_GREGS
)
1381 return SIM_ARM_R0_REGNUM
+ reg
;
1384 if (reg
< NUM_FREGS
)
1385 return SIM_ARM_FP0_REGNUM
+ reg
;
1388 if (reg
< NUM_SREGS
)
1389 return SIM_ARM_FPS_REGNUM
+ reg
;
1392 internal_error (__FILE__
, __LINE__
, _("Bad REGNUM %d"), regnum
);
1395 /* NOTE: cagney/2001-08-20: Both convert_from_extended() and
1396 convert_to_extended() use floatformat_arm_ext_littlebyte_bigword.
1397 It is thought that this is is the floating-point register format on
1398 little-endian systems. */
1401 convert_from_extended (const struct floatformat
*fmt
, const void *ptr
,
1405 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1406 floatformat_to_doublest (&floatformat_arm_ext_big
, ptr
, &d
);
1408 floatformat_to_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1410 floatformat_from_doublest (fmt
, &d
, dbl
);
1414 convert_to_extended (const struct floatformat
*fmt
, void *dbl
, const void *ptr
)
1417 floatformat_to_doublest (fmt
, ptr
, &d
);
1418 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1419 floatformat_from_doublest (&floatformat_arm_ext_big
, &d
, dbl
);
1421 floatformat_from_doublest (&floatformat_arm_ext_littlebyte_bigword
,
1426 condition_true (unsigned long cond
, unsigned long status_reg
)
1428 if (cond
== INST_AL
|| cond
== INST_NV
)
1434 return ((status_reg
& FLAG_Z
) != 0);
1436 return ((status_reg
& FLAG_Z
) == 0);
1438 return ((status_reg
& FLAG_C
) != 0);
1440 return ((status_reg
& FLAG_C
) == 0);
1442 return ((status_reg
& FLAG_N
) != 0);
1444 return ((status_reg
& FLAG_N
) == 0);
1446 return ((status_reg
& FLAG_V
) != 0);
1448 return ((status_reg
& FLAG_V
) == 0);
1450 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1452 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1454 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1456 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1458 return (((status_reg
& FLAG_Z
) == 0) &&
1459 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1461 return (((status_reg
& FLAG_Z
) != 0) ||
1462 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1467 /* Support routines for single stepping. Calculate the next PC value. */
1468 #define submask(x) ((1L << ((x) + 1)) - 1)
1469 #define bit(obj,st) (((obj) >> (st)) & 1)
1470 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1471 #define sbits(obj,st,fn) \
1472 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1473 #define BranchDest(addr,instr) \
1474 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1477 static unsigned long
1478 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1479 unsigned long status_reg
)
1481 unsigned long res
, shift
;
1482 int rm
= bits (inst
, 0, 3);
1483 unsigned long shifttype
= bits (inst
, 5, 6);
1487 int rs
= bits (inst
, 8, 11);
1488 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1491 shift
= bits (inst
, 7, 11);
1494 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1495 + (bit (inst
, 4) ? 12 : 8))
1496 : read_register (rm
));
1501 res
= shift
>= 32 ? 0 : res
<< shift
;
1505 res
= shift
>= 32 ? 0 : res
>> shift
;
1511 res
= ((res
& 0x80000000L
)
1512 ? ~((~res
) >> shift
) : res
>> shift
);
1515 case 3: /* ROR/RRX */
1518 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1520 res
= (res
>> shift
) | (res
<< (32 - shift
));
1524 return res
& 0xffffffff;
1527 /* Return number of 1-bits in VAL. */
1530 bitcount (unsigned long val
)
1533 for (nbits
= 0; val
!= 0; nbits
++)
1534 val
&= val
- 1; /* delete rightmost 1-bit in val */
1539 thumb_get_next_pc (CORE_ADDR pc
)
1541 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1542 unsigned short inst1
= read_memory_integer (pc
, 2);
1543 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1544 unsigned long offset
;
1546 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1550 /* Fetch the saved PC from the stack. It's stored above
1551 all of the other registers. */
1552 offset
= bitcount (bits (inst1
, 0, 7)) * DEPRECATED_REGISTER_SIZE
;
1553 sp
= read_register (ARM_SP_REGNUM
);
1554 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1555 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1557 error (_("Infinite loop detected"));
1559 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1561 unsigned long status
= read_register (ARM_PS_REGNUM
);
1562 unsigned long cond
= bits (inst1
, 8, 11);
1563 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1564 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1566 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1568 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1570 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link, and blx */
1572 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1573 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1574 nextpc
= pc_val
+ offset
;
1575 /* For BLX make sure to clear the low bits. */
1576 if (bits (inst2
, 11, 12) == 1)
1577 nextpc
= nextpc
& 0xfffffffc;
1579 else if ((inst1
& 0xff00) == 0x4700) /* bx REG, blx REG */
1581 if (bits (inst1
, 3, 6) == 0x0f)
1584 nextpc
= read_register (bits (inst1
, 3, 6));
1586 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1588 error (_("Infinite loop detected"));
1595 arm_get_next_pc (CORE_ADDR pc
)
1597 unsigned long pc_val
;
1598 unsigned long this_instr
;
1599 unsigned long status
;
1602 if (arm_pc_is_thumb (pc
))
1603 return thumb_get_next_pc (pc
);
1605 pc_val
= (unsigned long) pc
;
1606 this_instr
= read_memory_integer (pc
, 4);
1607 status
= read_register (ARM_PS_REGNUM
);
1608 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1610 if (condition_true (bits (this_instr
, 28, 31), status
))
1612 switch (bits (this_instr
, 24, 27))
1615 case 0x1: /* data processing */
1619 unsigned long operand1
, operand2
, result
= 0;
1623 if (bits (this_instr
, 12, 15) != 15)
1626 if (bits (this_instr
, 22, 25) == 0
1627 && bits (this_instr
, 4, 7) == 9) /* multiply */
1628 error (_("Invalid update to pc in instruction"));
1630 /* BX <reg>, BLX <reg> */
1631 if (bits (this_instr
, 4, 28) == 0x12fff1
1632 || bits (this_instr
, 4, 28) == 0x12fff3)
1634 rn
= bits (this_instr
, 0, 3);
1635 result
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1636 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1639 error (_("Infinite loop detected"));
1644 /* Multiply into PC */
1645 c
= (status
& FLAG_C
) ? 1 : 0;
1646 rn
= bits (this_instr
, 16, 19);
1647 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1649 if (bit (this_instr
, 25))
1651 unsigned long immval
= bits (this_instr
, 0, 7);
1652 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1653 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1656 else /* operand 2 is a shifted register */
1657 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1659 switch (bits (this_instr
, 21, 24))
1662 result
= operand1
& operand2
;
1666 result
= operand1
^ operand2
;
1670 result
= operand1
- operand2
;
1674 result
= operand2
- operand1
;
1678 result
= operand1
+ operand2
;
1682 result
= operand1
+ operand2
+ c
;
1686 result
= operand1
- operand2
+ c
;
1690 result
= operand2
- operand1
+ c
;
1696 case 0xb: /* tst, teq, cmp, cmn */
1697 result
= (unsigned long) nextpc
;
1701 result
= operand1
| operand2
;
1705 /* Always step into a function. */
1710 result
= operand1
& ~operand2
;
1717 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1720 error (_("Infinite loop detected"));
1725 case 0x5: /* data transfer */
1728 if (bit (this_instr
, 20))
1731 if (bits (this_instr
, 12, 15) == 15)
1737 if (bit (this_instr
, 22))
1738 error (_("Invalid update to pc in instruction"));
1740 /* byte write to PC */
1741 rn
= bits (this_instr
, 16, 19);
1742 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1743 if (bit (this_instr
, 24))
1746 int c
= (status
& FLAG_C
) ? 1 : 0;
1747 unsigned long offset
=
1748 (bit (this_instr
, 25)
1749 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1750 : bits (this_instr
, 0, 11));
1752 if (bit (this_instr
, 23))
1757 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1760 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1763 error (_("Infinite loop detected"));
1769 case 0x9: /* block transfer */
1770 if (bit (this_instr
, 20))
1773 if (bit (this_instr
, 15))
1778 if (bit (this_instr
, 23))
1781 unsigned long reglist
= bits (this_instr
, 0, 14);
1782 offset
= bitcount (reglist
) * 4;
1783 if (bit (this_instr
, 24)) /* pre */
1786 else if (bit (this_instr
, 24))
1790 unsigned long rn_val
=
1791 read_register (bits (this_instr
, 16, 19));
1793 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1797 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1799 error (_("Infinite loop detected"));
1804 case 0xb: /* branch & link */
1805 case 0xa: /* branch */
1807 nextpc
= BranchDest (pc
, this_instr
);
1810 if (bits (this_instr
, 28, 31) == INST_NV
)
1811 nextpc
|= bit (this_instr
, 24) << 1;
1813 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1815 error (_("Infinite loop detected"));
1821 case 0xe: /* coproc ops */
1826 fprintf_filtered (gdb_stderr
, _("Bad bit-field extraction\n"));
1834 /* single_step() is called just before we want to resume the inferior,
1835 if we want to single-step it but there is no hardware or kernel
1836 single-step support. We find the target of the coming instruction
1839 single_step() is also called just after the inferior stops. If we
1840 had set up a simulated single-step, we undo our damage. */
1843 arm_software_single_step (enum target_signal sig
, int insert_bpt
)
1845 static int next_pc
; /* State between setting and unsetting. */
1846 static char break_mem
[BREAKPOINT_MAX
]; /* Temporary storage for mem@bpt */
1850 next_pc
= arm_get_next_pc (read_register (ARM_PC_REGNUM
));
1851 target_insert_breakpoint (next_pc
, break_mem
);
1854 target_remove_breakpoint (next_pc
, break_mem
);
1857 #include "bfd-in2.h"
1858 #include "libcoff.h"
1861 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1863 if (arm_pc_is_thumb (memaddr
))
1865 static asymbol
*asym
;
1866 static combined_entry_type ce
;
1867 static struct coff_symbol_struct csym
;
1868 static struct bfd fake_bfd
;
1869 static bfd_target fake_target
;
1871 if (csym
.native
== NULL
)
1873 /* Create a fake symbol vector containing a Thumb symbol.
1874 This is solely so that the code in print_insn_little_arm()
1875 and print_insn_big_arm() in opcodes/arm-dis.c will detect
1876 the presence of a Thumb symbol and switch to decoding
1877 Thumb instructions. */
1879 fake_target
.flavour
= bfd_target_coff_flavour
;
1880 fake_bfd
.xvec
= &fake_target
;
1881 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1883 csym
.symbol
.the_bfd
= &fake_bfd
;
1884 csym
.symbol
.name
= "fake";
1885 asym
= (asymbol
*) & csym
;
1888 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1889 info
->symbols
= &asym
;
1892 info
->symbols
= NULL
;
1894 if (TARGET_BYTE_ORDER
== BFD_ENDIAN_BIG
)
1895 return print_insn_big_arm (memaddr
, info
);
1897 return print_insn_little_arm (memaddr
, info
);
1900 /* The following define instruction sequences that will cause ARM
1901 cpu's to take an undefined instruction trap. These are used to
1902 signal a breakpoint to GDB.
1904 The newer ARMv4T cpu's are capable of operating in ARM or Thumb
1905 modes. A different instruction is required for each mode. The ARM
1906 cpu's can also be big or little endian. Thus four different
1907 instructions are needed to support all cases.
1909 Note: ARMv4 defines several new instructions that will take the
1910 undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does
1911 not in fact add the new instructions. The new undefined
1912 instructions in ARMv4 are all instructions that had no defined
1913 behaviour in earlier chips. There is no guarantee that they will
1914 raise an exception, but may be treated as NOP's. In practice, it
1915 may only safe to rely on instructions matching:
1917 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1918 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
1919 C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x
1921 Even this may only true if the condition predicate is true. The
1922 following use a condition predicate of ALWAYS so it is always TRUE.
1924 There are other ways of forcing a breakpoint. GNU/Linux, RISC iX,
1925 and NetBSD all use a software interrupt rather than an undefined
1926 instruction to force a trap. This can be handled by by the
1927 abi-specific code during establishment of the gdbarch vector. */
1930 /* NOTE rearnsha 2002-02-18: for now we allow a non-multi-arch gdb to
1931 override these definitions. */
1932 #ifndef ARM_LE_BREAKPOINT
1933 #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7}
1935 #ifndef ARM_BE_BREAKPOINT
1936 #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE}
1938 #ifndef THUMB_LE_BREAKPOINT
1939 #define THUMB_LE_BREAKPOINT {0xfe,0xdf}
1941 #ifndef THUMB_BE_BREAKPOINT
1942 #define THUMB_BE_BREAKPOINT {0xdf,0xfe}
1945 static const char arm_default_arm_le_breakpoint
[] = ARM_LE_BREAKPOINT
;
1946 static const char arm_default_arm_be_breakpoint
[] = ARM_BE_BREAKPOINT
;
1947 static const char arm_default_thumb_le_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1948 static const char arm_default_thumb_be_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1950 /* Determine the type and size of breakpoint to insert at PCPTR. Uses
1951 the program counter value to determine whether a 16-bit or 32-bit
1952 breakpoint should be used. It returns a pointer to a string of
1953 bytes that encode a breakpoint instruction, stores the length of
1954 the string to *lenptr, and adjusts the program counter (if
1955 necessary) to point to the actual memory location where the
1956 breakpoint should be inserted. */
1958 /* XXX ??? from old tm-arm.h: if we're using RDP, then we're inserting
1959 breakpoints and storing their handles instread of what was in
1960 memory. It is nice that this is the same size as a handle -
1961 otherwise remote-rdp will have to change. */
1963 static const unsigned char *
1964 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1966 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
1968 if (arm_pc_is_thumb (*pcptr
))
1970 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1971 *lenptr
= tdep
->thumb_breakpoint_size
;
1972 return tdep
->thumb_breakpoint
;
1976 *lenptr
= tdep
->arm_breakpoint_size
;
1977 return tdep
->arm_breakpoint
;
1981 /* Extract from an array REGBUF containing the (raw) register state a
1982 function return value of type TYPE, and copy that, in virtual
1983 format, into VALBUF. */
1986 arm_extract_return_value (struct type
*type
, struct regcache
*regs
,
1989 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1991 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
1995 /* The value is in register F0 in internal format. We need to
1996 extract the raw value and then convert it to the desired
1998 bfd_byte tmpbuf
[FP_REGISTER_SIZE
];
2000 regcache_cooked_read (regs
, ARM_F0_REGNUM
, tmpbuf
);
2001 convert_from_extended (floatformat_from_type (type
), tmpbuf
,
2006 case ARM_FLOAT_SOFT_FPA
:
2007 case ARM_FLOAT_SOFT_VFP
:
2008 regcache_cooked_read (regs
, ARM_A1_REGNUM
, valbuf
);
2009 if (TYPE_LENGTH (type
) > 4)
2010 regcache_cooked_read (regs
, ARM_A1_REGNUM
+ 1,
2011 valbuf
+ INT_REGISTER_SIZE
);
2016 (__FILE__
, __LINE__
,
2017 _("arm_extract_return_value: Floating point model not supported"));
2021 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2022 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2023 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2024 || TYPE_CODE (type
) == TYPE_CODE_PTR
2025 || TYPE_CODE (type
) == TYPE_CODE_REF
2026 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2028 /* If the the type is a plain integer, then the access is
2029 straight-forward. Otherwise we have to play around a bit more. */
2030 int len
= TYPE_LENGTH (type
);
2031 int regno
= ARM_A1_REGNUM
;
2036 /* By using store_unsigned_integer we avoid having to do
2037 anything special for small big-endian values. */
2038 regcache_cooked_read_unsigned (regs
, regno
++, &tmp
);
2039 store_unsigned_integer (valbuf
,
2040 (len
> INT_REGISTER_SIZE
2041 ? INT_REGISTER_SIZE
: len
),
2043 len
-= INT_REGISTER_SIZE
;
2044 valbuf
+= INT_REGISTER_SIZE
;
2049 /* For a structure or union the behaviour is as if the value had
2050 been stored to word-aligned memory and then loaded into
2051 registers with 32-bit load instruction(s). */
2052 int len
= TYPE_LENGTH (type
);
2053 int regno
= ARM_A1_REGNUM
;
2054 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2058 regcache_cooked_read (regs
, regno
++, tmpbuf
);
2059 memcpy (valbuf
, tmpbuf
,
2060 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2061 len
-= INT_REGISTER_SIZE
;
2062 valbuf
+= INT_REGISTER_SIZE
;
2068 /* Will a function return an aggregate type in memory or in a
2069 register? Return 0 if an aggregate type can be returned in a
2070 register, 1 if it must be returned in memory. */
2073 arm_return_in_memory (struct gdbarch
*gdbarch
, struct type
*type
)
2076 enum type_code code
;
2078 CHECK_TYPEDEF (type
);
2080 /* In the ARM ABI, "integer" like aggregate types are returned in
2081 registers. For an aggregate type to be integer like, its size
2082 must be less than or equal to DEPRECATED_REGISTER_SIZE and the
2083 offset of each addressable subfield must be zero. Note that bit
2084 fields are not addressable, and all addressable subfields of
2085 unions always start at offset zero.
2087 This function is based on the behaviour of GCC 2.95.1.
2088 See: gcc/arm.c: arm_return_in_memory() for details.
2090 Note: All versions of GCC before GCC 2.95.2 do not set up the
2091 parameters correctly for a function returning the following
2092 structure: struct { float f;}; This should be returned in memory,
2093 not a register. Richard Earnshaw sent me a patch, but I do not
2094 know of any way to detect if a function like the above has been
2095 compiled with the correct calling convention. */
2097 /* All aggregate types that won't fit in a register must be returned
2099 if (TYPE_LENGTH (type
) > DEPRECATED_REGISTER_SIZE
)
2104 /* The AAPCS says all aggregates not larger than a word are returned
2106 if (gdbarch_tdep (gdbarch
)->arm_abi
!= ARM_ABI_APCS
)
2109 /* The only aggregate types that can be returned in a register are
2110 structs and unions. Arrays must be returned in memory. */
2111 code
= TYPE_CODE (type
);
2112 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
2117 /* Assume all other aggregate types can be returned in a register.
2118 Run a check for structures, unions and arrays. */
2121 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
2124 /* Need to check if this struct/union is "integer" like. For
2125 this to be true, its size must be less than or equal to
2126 DEPRECATED_REGISTER_SIZE and the offset of each addressable
2127 subfield must be zero. Note that bit fields are not
2128 addressable, and unions always start at offset zero. If any
2129 of the subfields is a floating point type, the struct/union
2130 cannot be an integer type. */
2132 /* For each field in the object, check:
2133 1) Is it FP? --> yes, nRc = 1;
2134 2) Is it addressable (bitpos != 0) and
2135 not packed (bitsize == 0)?
2139 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
2141 enum type_code field_type_code
;
2142 field_type_code
= TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, i
)));
2144 /* Is it a floating point type field? */
2145 if (field_type_code
== TYPE_CODE_FLT
)
2151 /* If bitpos != 0, then we have to care about it. */
2152 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
2154 /* Bitfields are not addressable. If the field bitsize is
2155 zero, then the field is not packed. Hence it cannot be
2156 a bitfield or any other packed type. */
2157 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
2169 /* Write into appropriate registers a function return value of type
2170 TYPE, given in virtual format. */
2173 arm_store_return_value (struct type
*type
, struct regcache
*regs
,
2174 const gdb_byte
*valbuf
)
2176 if (TYPE_CODE (type
) == TYPE_CODE_FLT
)
2178 char buf
[MAX_REGISTER_SIZE
];
2180 switch (gdbarch_tdep (current_gdbarch
)->fp_model
)
2184 convert_to_extended (floatformat_from_type (type
), buf
, valbuf
);
2185 regcache_cooked_write (regs
, ARM_F0_REGNUM
, buf
);
2188 case ARM_FLOAT_SOFT_FPA
:
2189 case ARM_FLOAT_SOFT_VFP
:
2190 regcache_cooked_write (regs
, ARM_A1_REGNUM
, valbuf
);
2191 if (TYPE_LENGTH (type
) > 4)
2192 regcache_cooked_write (regs
, ARM_A1_REGNUM
+ 1,
2193 valbuf
+ INT_REGISTER_SIZE
);
2198 (__FILE__
, __LINE__
,
2199 _("arm_store_return_value: Floating point model not supported"));
2203 else if (TYPE_CODE (type
) == TYPE_CODE_INT
2204 || TYPE_CODE (type
) == TYPE_CODE_CHAR
2205 || TYPE_CODE (type
) == TYPE_CODE_BOOL
2206 || TYPE_CODE (type
) == TYPE_CODE_PTR
2207 || TYPE_CODE (type
) == TYPE_CODE_REF
2208 || TYPE_CODE (type
) == TYPE_CODE_ENUM
)
2210 if (TYPE_LENGTH (type
) <= 4)
2212 /* Values of one word or less are zero/sign-extended and
2214 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2215 LONGEST val
= unpack_long (type
, valbuf
);
2217 store_signed_integer (tmpbuf
, INT_REGISTER_SIZE
, val
);
2218 regcache_cooked_write (regs
, ARM_A1_REGNUM
, tmpbuf
);
2222 /* Integral values greater than one word are stored in consecutive
2223 registers starting with r0. This will always be a multiple of
2224 the regiser size. */
2225 int len
= TYPE_LENGTH (type
);
2226 int regno
= ARM_A1_REGNUM
;
2230 regcache_cooked_write (regs
, regno
++, valbuf
);
2231 len
-= INT_REGISTER_SIZE
;
2232 valbuf
+= INT_REGISTER_SIZE
;
2238 /* For a structure or union the behaviour is as if the value had
2239 been stored to word-aligned memory and then loaded into
2240 registers with 32-bit load instruction(s). */
2241 int len
= TYPE_LENGTH (type
);
2242 int regno
= ARM_A1_REGNUM
;
2243 bfd_byte tmpbuf
[INT_REGISTER_SIZE
];
2247 memcpy (tmpbuf
, valbuf
,
2248 len
> INT_REGISTER_SIZE
? INT_REGISTER_SIZE
: len
);
2249 regcache_cooked_write (regs
, regno
++, tmpbuf
);
2250 len
-= INT_REGISTER_SIZE
;
2251 valbuf
+= INT_REGISTER_SIZE
;
2257 /* Handle function return values. */
2259 static enum return_value_convention
2260 arm_return_value (struct gdbarch
*gdbarch
, struct type
*valtype
,
2261 struct regcache
*regcache
, void *readbuf
,
2262 const void *writebuf
)
2264 if (TYPE_CODE (valtype
) == TYPE_CODE_STRUCT
2265 || TYPE_CODE (valtype
) == TYPE_CODE_UNION
2266 || TYPE_CODE (valtype
) == TYPE_CODE_ARRAY
)
2268 if (arm_return_in_memory (gdbarch
, valtype
))
2269 return RETURN_VALUE_STRUCT_CONVENTION
;
2273 arm_store_return_value (valtype
, regcache
, writebuf
);
2276 arm_extract_return_value (valtype
, regcache
, readbuf
);
2278 return RETURN_VALUE_REGISTER_CONVENTION
;
2283 arm_get_longjmp_target (CORE_ADDR
*pc
)
2286 char buf
[INT_REGISTER_SIZE
];
2287 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2289 jb_addr
= read_register (ARM_A1_REGNUM
);
2291 if (target_read_memory (jb_addr
+ tdep
->jb_pc
* tdep
->jb_elt_size
, buf
,
2295 *pc
= extract_unsigned_integer (buf
, INT_REGISTER_SIZE
);
2299 /* Return non-zero if the PC is inside a thumb call thunk. */
2302 arm_in_call_stub (CORE_ADDR pc
, char *name
)
2304 CORE_ADDR start_addr
;
2306 /* Find the starting address of the function containing the PC. If
2307 the caller didn't give us a name, look it up at the same time. */
2308 if (0 == find_pc_partial_function (pc
, name
? NULL
: &name
,
2312 return strncmp (name
, "_call_via_r", 11) == 0;
2315 /* If PC is in a Thumb call or return stub, return the address of the
2316 target PC, which is in a register. The thunk functions are called
2317 _called_via_xx, where x is the register name. The possible names
2318 are r0-r9, sl, fp, ip, sp, and lr. */
2321 arm_skip_stub (CORE_ADDR pc
)
2324 CORE_ADDR start_addr
;
2326 /* Find the starting address and name of the function containing the PC. */
2327 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
2330 /* Call thunks always start with "_call_via_". */
2331 if (strncmp (name
, "_call_via_", 10) == 0)
2333 /* Use the name suffix to determine which register contains the
2335 static char *table
[15] =
2336 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
2337 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
2341 for (regno
= 0; regno
<= 14; regno
++)
2342 if (strcmp (&name
[10], table
[regno
]) == 0)
2343 return read_register (regno
);
2346 return 0; /* not a stub */
2350 set_arm_command (char *args
, int from_tty
)
2352 printf_unfiltered (_("\
2353 \"set arm\" must be followed by an apporpriate subcommand.\n"));
2354 help_list (setarmcmdlist
, "set arm ", all_commands
, gdb_stdout
);
2358 show_arm_command (char *args
, int from_tty
)
2360 cmd_show_list (showarmcmdlist
, from_tty
, "");
2364 arm_update_current_architecture (void)
2366 struct gdbarch_info info
;
2368 /* If the current architecture is not ARM, we have nothing to do. */
2369 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_arm
)
2372 /* Update the architecture. */
2373 gdbarch_info_init (&info
);
2375 if (!gdbarch_update_p (info
))
2376 internal_error (__FILE__
, __LINE__
, "could not update architecture");
2380 set_fp_model_sfunc (char *args
, int from_tty
,
2381 struct cmd_list_element
*c
)
2383 enum arm_float_model fp_model
;
2385 for (fp_model
= ARM_FLOAT_AUTO
; fp_model
!= ARM_FLOAT_LAST
; fp_model
++)
2386 if (strcmp (current_fp_model
, fp_model_strings
[fp_model
]) == 0)
2388 arm_fp_model
= fp_model
;
2392 if (fp_model
== ARM_FLOAT_LAST
)
2393 internal_error (__FILE__
, __LINE__
, _("Invalid fp model accepted: %s."),
2396 arm_update_current_architecture ();
2400 show_fp_model (struct ui_file
*file
, int from_tty
,
2401 struct cmd_list_element
*c
, const char *value
)
2403 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2405 if (arm_fp_model
== ARM_FLOAT_AUTO
2406 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2407 fprintf_filtered (file
, _("\
2408 The current ARM floating point model is \"auto\" (currently \"%s\").\n"),
2409 fp_model_strings
[tdep
->fp_model
]);
2411 fprintf_filtered (file
, _("\
2412 The current ARM floating point model is \"%s\".\n"),
2413 fp_model_strings
[arm_fp_model
]);
2417 arm_set_abi (char *args
, int from_tty
,
2418 struct cmd_list_element
*c
)
2420 enum arm_abi_kind arm_abi
;
2422 for (arm_abi
= ARM_ABI_AUTO
; arm_abi
!= ARM_ABI_LAST
; arm_abi
++)
2423 if (strcmp (arm_abi_string
, arm_abi_strings
[arm_abi
]) == 0)
2425 arm_abi_global
= arm_abi
;
2429 if (arm_abi
== ARM_ABI_LAST
)
2430 internal_error (__FILE__
, __LINE__
, _("Invalid ABI accepted: %s."),
2433 arm_update_current_architecture ();
2437 arm_show_abi (struct ui_file
*file
, int from_tty
,
2438 struct cmd_list_element
*c
, const char *value
)
2440 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2442 if (arm_abi_global
== ARM_ABI_AUTO
2443 && gdbarch_bfd_arch_info (current_gdbarch
)->arch
== bfd_arch_arm
)
2444 fprintf_filtered (file
, _("\
2445 The current ARM ABI is \"auto\" (currently \"%s\").\n"),
2446 arm_abi_strings
[tdep
->arm_abi
]);
2448 fprintf_filtered (file
, _("The current ARM ABI is \"%s\".\n"),
2452 /* If the user changes the register disassembly style used for info
2453 register and other commands, we have to also switch the style used
2454 in opcodes for disassembly output. This function is run in the "set
2455 arm disassembly" command, and does that. */
2458 set_disassembly_style_sfunc (char *args
, int from_tty
,
2459 struct cmd_list_element
*c
)
2461 set_disassembly_style ();
2464 /* Return the ARM register name corresponding to register I. */
2466 arm_register_name (int i
)
2468 return arm_register_names
[i
];
2472 set_disassembly_style (void)
2474 const char *setname
, *setdesc
, *const *regnames
;
2477 /* Find the style that the user wants in the opcodes table. */
2479 numregs
= get_arm_regnames (current
, &setname
, &setdesc
, ®names
);
2480 while ((disassembly_style
!= setname
)
2481 && (current
< num_disassembly_options
))
2482 get_arm_regnames (++current
, &setname
, &setdesc
, ®names
);
2483 current_option
= current
;
2485 /* Fill our copy. */
2486 for (j
= 0; j
< numregs
; j
++)
2487 arm_register_names
[j
] = (char *) regnames
[j
];
2490 if (isupper (*regnames
[ARM_PC_REGNUM
]))
2492 arm_register_names
[ARM_FPS_REGNUM
] = "FPS";
2493 arm_register_names
[ARM_PS_REGNUM
] = "CPSR";
2497 arm_register_names
[ARM_FPS_REGNUM
] = "fps";
2498 arm_register_names
[ARM_PS_REGNUM
] = "cpsr";
2501 /* Synchronize the disassembler. */
2502 set_arm_regname_option (current
);
2505 /* Test whether the coff symbol specific value corresponds to a Thumb
2509 coff_sym_is_thumb (int val
)
2511 return (val
== C_THUMBEXT
||
2512 val
== C_THUMBSTAT
||
2513 val
== C_THUMBEXTFUNC
||
2514 val
== C_THUMBSTATFUNC
||
2515 val
== C_THUMBLABEL
);
2518 /* arm_coff_make_msymbol_special()
2519 arm_elf_make_msymbol_special()
2521 These functions test whether the COFF or ELF symbol corresponds to
2522 an address in thumb code, and set a "special" bit in a minimal
2523 symbol to indicate that it does. */
2526 arm_elf_make_msymbol_special(asymbol
*sym
, struct minimal_symbol
*msym
)
2528 /* Thumb symbols are of type STT_LOPROC, (synonymous with
2530 if (ELF_ST_TYPE (((elf_symbol_type
*)sym
)->internal_elf_sym
.st_info
)
2532 MSYMBOL_SET_SPECIAL (msym
);
2536 arm_coff_make_msymbol_special(int val
, struct minimal_symbol
*msym
)
2538 if (coff_sym_is_thumb (val
))
2539 MSYMBOL_SET_SPECIAL (msym
);
2543 arm_write_pc (CORE_ADDR pc
, ptid_t ptid
)
2545 write_register_pid (ARM_PC_REGNUM
, pc
, ptid
);
2547 /* If necessary, set the T bit. */
2550 CORE_ADDR val
= read_register_pid (ARM_PS_REGNUM
, ptid
);
2551 if (arm_pc_is_thumb (pc
))
2552 write_register_pid (ARM_PS_REGNUM
, val
| 0x20, ptid
);
2554 write_register_pid (ARM_PS_REGNUM
, val
& ~(CORE_ADDR
) 0x20, ptid
);
2558 static enum gdb_osabi
2559 arm_elf_osabi_sniffer (bfd
*abfd
)
2561 unsigned int elfosabi
;
2562 enum gdb_osabi osabi
= GDB_OSABI_UNKNOWN
;
2564 elfosabi
= elf_elfheader (abfd
)->e_ident
[EI_OSABI
];
2566 if (elfosabi
== ELFOSABI_ARM
)
2567 /* GNU tools use this value. Check note sections in this case,
2569 bfd_map_over_sections (abfd
,
2570 generic_elf_osabi_sniff_abi_tag_sections
,
2573 /* Anything else will be handled by the generic ELF sniffer. */
2578 /* Initialize the current architecture based on INFO. If possible,
2579 re-use an architecture from ARCHES, which is a list of
2580 architectures already created during this debugging session.
2582 Called e.g. at program startup, when reading a core file, and when
2583 reading a binary file. */
2585 static struct gdbarch
*
2586 arm_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
2588 struct gdbarch_tdep
*tdep
;
2589 struct gdbarch
*gdbarch
;
2590 struct gdbarch_list
*best_arch
;
2591 enum arm_abi_kind arm_abi
= arm_abi_global
;
2592 enum arm_float_model fp_model
= arm_fp_model
;
2594 /* If we have an object to base this architecture on, try to determine
2597 if (arm_abi
== ARM_ABI_AUTO
&& info
.abfd
!= NULL
)
2601 switch (bfd_get_flavour (info
.abfd
))
2603 case bfd_target_aout_flavour
:
2604 /* Assume it's an old APCS-style ABI. */
2605 arm_abi
= ARM_ABI_APCS
;
2608 case bfd_target_coff_flavour
:
2609 /* Assume it's an old APCS-style ABI. */
2611 arm_abi
= ARM_ABI_APCS
;
2614 case bfd_target_elf_flavour
:
2615 ei_osabi
= elf_elfheader (info
.abfd
)->e_ident
[EI_OSABI
];
2616 if (ei_osabi
== ELFOSABI_ARM
)
2618 /* GNU tools used to use this value, but do not for EABI
2619 objects. There's nowhere to tag an EABI version anyway,
2621 arm_abi
= ARM_ABI_APCS
;
2623 else if (ei_osabi
== ELFOSABI_NONE
)
2625 int e_flags
, eabi_ver
;
2627 e_flags
= elf_elfheader (info
.abfd
)->e_flags
;
2628 eabi_ver
= EF_ARM_EABI_VERSION (e_flags
);
2632 case EF_ARM_EABI_UNKNOWN
:
2633 /* Assume GNU tools. */
2634 arm_abi
= ARM_ABI_APCS
;
2637 case EF_ARM_EABI_VER4
:
2638 arm_abi
= ARM_ABI_AAPCS
;
2639 /* EABI binaries default to VFP float ordering. */
2640 if (fp_model
== ARM_FLOAT_AUTO
)
2641 fp_model
= ARM_FLOAT_SOFT_VFP
;
2645 warning (_("unknown ARM EABI version 0x%x"), eabi_ver
);
2646 arm_abi
= ARM_ABI_APCS
;
2653 /* Leave it as "auto". */
2658 /* Now that we have inferred any architecture settings that we
2659 can, try to inherit from the last ARM ABI. */
2662 if (arm_abi
== ARM_ABI_AUTO
)
2663 arm_abi
= gdbarch_tdep (arches
->gdbarch
)->arm_abi
;
2665 if (fp_model
== ARM_FLOAT_AUTO
)
2666 fp_model
= gdbarch_tdep (arches
->gdbarch
)->fp_model
;
2670 /* There was no prior ARM architecture; fill in default values. */
2672 if (arm_abi
== ARM_ABI_AUTO
)
2673 arm_abi
= ARM_ABI_APCS
;
2675 /* We used to default to FPA for generic ARM, but almost nobody
2676 uses that now, and we now provide a way for the user to force
2677 the model. So default to the most useful variant. */
2678 if (fp_model
== ARM_FLOAT_AUTO
)
2679 fp_model
= ARM_FLOAT_SOFT_FPA
;
2682 /* If there is already a candidate, use it. */
2683 for (best_arch
= gdbarch_list_lookup_by_info (arches
, &info
);
2685 best_arch
= gdbarch_list_lookup_by_info (best_arch
->next
, &info
))
2687 if (arm_abi
!= gdbarch_tdep (best_arch
->gdbarch
)->arm_abi
)
2690 if (fp_model
!= gdbarch_tdep (best_arch
->gdbarch
)->fp_model
)
2693 /* Found a match. */
2697 if (best_arch
!= NULL
)
2698 return best_arch
->gdbarch
;
2700 tdep
= xcalloc (1, sizeof (struct gdbarch_tdep
));
2701 gdbarch
= gdbarch_alloc (&info
, tdep
);
2703 /* Record additional information about the architecture we are defining.
2704 These are gdbarch discriminators, like the OSABI. */
2705 tdep
->arm_abi
= arm_abi
;
2706 tdep
->fp_model
= fp_model
;
2709 switch (info
.byte_order
)
2711 case BFD_ENDIAN_BIG
:
2712 tdep
->arm_breakpoint
= arm_default_arm_be_breakpoint
;
2713 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_be_breakpoint
);
2714 tdep
->thumb_breakpoint
= arm_default_thumb_be_breakpoint
;
2715 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_be_breakpoint
);
2719 case BFD_ENDIAN_LITTLE
:
2720 tdep
->arm_breakpoint
= arm_default_arm_le_breakpoint
;
2721 tdep
->arm_breakpoint_size
= sizeof (arm_default_arm_le_breakpoint
);
2722 tdep
->thumb_breakpoint
= arm_default_thumb_le_breakpoint
;
2723 tdep
->thumb_breakpoint_size
= sizeof (arm_default_thumb_le_breakpoint
);
2728 internal_error (__FILE__
, __LINE__
,
2729 _("arm_gdbarch_init: bad byte order for float format"));
2732 /* On ARM targets char defaults to unsigned. */
2733 set_gdbarch_char_signed (gdbarch
, 0);
2735 /* This should be low enough for everything. */
2736 tdep
->lowest_pc
= 0x20;
2737 tdep
->jb_pc
= -1; /* Longjump support not enabled by default. */
2739 set_gdbarch_push_dummy_call (gdbarch
, arm_push_dummy_call
);
2741 set_gdbarch_write_pc (gdbarch
, arm_write_pc
);
2743 /* Frame handling. */
2744 set_gdbarch_unwind_dummy_id (gdbarch
, arm_unwind_dummy_id
);
2745 set_gdbarch_unwind_pc (gdbarch
, arm_unwind_pc
);
2746 set_gdbarch_unwind_sp (gdbarch
, arm_unwind_sp
);
2748 frame_base_set_default (gdbarch
, &arm_normal_base
);
2750 /* Address manipulation. */
2751 set_gdbarch_smash_text_address (gdbarch
, arm_smash_text_address
);
2752 set_gdbarch_addr_bits_remove (gdbarch
, arm_addr_bits_remove
);
2754 /* Advance PC across function entry code. */
2755 set_gdbarch_skip_prologue (gdbarch
, arm_skip_prologue
);
2757 /* Get the PC when a frame might not be available. */
2758 set_gdbarch_deprecated_saved_pc_after_call (gdbarch
, arm_saved_pc_after_call
);
2760 /* The stack grows downward. */
2761 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
2763 /* Breakpoint manipulation. */
2764 set_gdbarch_breakpoint_from_pc (gdbarch
, arm_breakpoint_from_pc
);
2766 /* Information about registers, etc. */
2767 set_gdbarch_print_float_info (gdbarch
, arm_print_float_info
);
2768 set_gdbarch_deprecated_fp_regnum (gdbarch
, ARM_FP_REGNUM
); /* ??? */
2769 set_gdbarch_sp_regnum (gdbarch
, ARM_SP_REGNUM
);
2770 set_gdbarch_pc_regnum (gdbarch
, ARM_PC_REGNUM
);
2771 set_gdbarch_deprecated_register_byte (gdbarch
, arm_register_byte
);
2772 set_gdbarch_num_regs (gdbarch
, NUM_GREGS
+ NUM_FREGS
+ NUM_SREGS
);
2773 set_gdbarch_register_type (gdbarch
, arm_register_type
);
2775 /* Internal <-> external register number maps. */
2776 set_gdbarch_register_sim_regno (gdbarch
, arm_register_sim_regno
);
2778 /* Integer registers are 4 bytes. */
2779 set_gdbarch_deprecated_register_size (gdbarch
, 4);
2780 set_gdbarch_register_name (gdbarch
, arm_register_name
);
2782 /* Returning results. */
2783 set_gdbarch_return_value (gdbarch
, arm_return_value
);
2785 /* Single stepping. */
2786 /* XXX For an RDI target we should ask the target if it can single-step. */
2787 set_gdbarch_software_single_step (gdbarch
, arm_software_single_step
);
2790 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_arm
);
2792 /* Minsymbol frobbing. */
2793 set_gdbarch_elf_make_msymbol_special (gdbarch
, arm_elf_make_msymbol_special
);
2794 set_gdbarch_coff_make_msymbol_special (gdbarch
,
2795 arm_coff_make_msymbol_special
);
2797 /* Hook in the ABI-specific overrides, if they have been registered. */
2798 gdbarch_init_osabi (info
, gdbarch
);
2800 /* Add some default predicates. */
2801 frame_unwind_append_sniffer (gdbarch
, arm_stub_unwind_sniffer
);
2802 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
2803 frame_unwind_append_sniffer (gdbarch
, arm_prologue_unwind_sniffer
);
2805 /* Now we have tuned the configuration, set a few final things,
2806 based on what the OS ABI has told us. */
2808 if (tdep
->jb_pc
>= 0)
2809 set_gdbarch_get_longjmp_target (gdbarch
, arm_get_longjmp_target
);
2811 /* Floating point sizes and format. */
2812 switch (info
.byte_order
)
2814 case BFD_ENDIAN_BIG
:
2815 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_big
);
2816 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_big
);
2817 set_gdbarch_long_double_format (gdbarch
, &floatformat_ieee_double_big
);
2820 case BFD_ENDIAN_LITTLE
:
2821 set_gdbarch_float_format (gdbarch
, &floatformat_ieee_single_little
);
2822 if (fp_model
== ARM_FLOAT_SOFT_FPA
|| fp_model
== ARM_FLOAT_FPA
)
2824 set_gdbarch_double_format
2825 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2826 set_gdbarch_long_double_format
2827 (gdbarch
, &floatformat_ieee_double_littlebyte_bigword
);
2831 set_gdbarch_double_format (gdbarch
, &floatformat_ieee_double_little
);
2832 set_gdbarch_long_double_format (gdbarch
,
2833 &floatformat_ieee_double_little
);
2838 internal_error (__FILE__
, __LINE__
,
2839 _("arm_gdbarch_init: bad byte order for float format"));
2846 arm_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
2848 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2853 fprintf_unfiltered (file
, _("arm_dump_tdep: Lowest pc = 0x%lx"),
2854 (unsigned long) tdep
->lowest_pc
);
2857 extern initialize_file_ftype _initialize_arm_tdep
; /* -Wmissing-prototypes */
2860 _initialize_arm_tdep (void)
2862 struct ui_file
*stb
;
2864 struct cmd_list_element
*new_set
, *new_show
;
2865 const char *setname
;
2866 const char *setdesc
;
2867 const char *const *regnames
;
2869 static char *helptext
;
2870 char regdesc
[1024], *rdptr
= regdesc
;
2871 size_t rest
= sizeof (regdesc
);
2873 gdbarch_register (bfd_arch_arm
, arm_gdbarch_init
, arm_dump_tdep
);
2875 /* Register an ELF OS ABI sniffer for ARM binaries. */
2876 gdbarch_register_osabi_sniffer (bfd_arch_arm
,
2877 bfd_target_elf_flavour
,
2878 arm_elf_osabi_sniffer
);
2880 /* Get the number of possible sets of register names defined in opcodes. */
2881 num_disassembly_options
= get_arm_regname_num_options ();
2883 /* Add root prefix command for all "set arm"/"show arm" commands. */
2884 add_prefix_cmd ("arm", no_class
, set_arm_command
,
2885 _("Various ARM-specific commands."),
2886 &setarmcmdlist
, "set arm ", 0, &setlist
);
2888 add_prefix_cmd ("arm", no_class
, show_arm_command
,
2889 _("Various ARM-specific commands."),
2890 &showarmcmdlist
, "show arm ", 0, &showlist
);
2892 /* Sync the opcode insn printer with our register viewer. */
2893 parse_arm_disassembler_option ("reg-names-std");
2895 /* Initialize the array that will be passed to
2896 add_setshow_enum_cmd(). */
2897 valid_disassembly_styles
2898 = xmalloc ((num_disassembly_options
+ 1) * sizeof (char *));
2899 for (i
= 0; i
< num_disassembly_options
; i
++)
2901 numregs
= get_arm_regnames (i
, &setname
, &setdesc
, ®names
);
2902 valid_disassembly_styles
[i
] = setname
;
2903 length
= snprintf (rdptr
, rest
, "%s - %s\n", setname
, setdesc
);
2906 /* Copy the default names (if found) and synchronize disassembler. */
2907 if (!strcmp (setname
, "std"))
2909 disassembly_style
= setname
;
2911 for (j
= 0; j
< numregs
; j
++)
2912 arm_register_names
[j
] = (char *) regnames
[j
];
2913 set_arm_regname_option (i
);
2916 /* Mark the end of valid options. */
2917 valid_disassembly_styles
[num_disassembly_options
] = NULL
;
2919 /* Create the help text. */
2920 stb
= mem_fileopen ();
2921 fprintf_unfiltered (stb
, "%s%s%s",
2922 _("The valid values are:\n"),
2924 _("The default is \"std\"."));
2925 helptext
= ui_file_xstrdup (stb
, &length
);
2926 ui_file_delete (stb
);
2928 add_setshow_enum_cmd("disassembler", no_class
,
2929 valid_disassembly_styles
, &disassembly_style
,
2930 _("Set the disassembly style."),
2931 _("Show the disassembly style."),
2933 set_disassembly_style_sfunc
,
2934 NULL
, /* FIXME: i18n: The disassembly style is \"%s\". */
2935 &setarmcmdlist
, &showarmcmdlist
);
2937 add_setshow_boolean_cmd ("apcs32", no_class
, &arm_apcs_32
,
2938 _("Set usage of ARM 32-bit mode."),
2939 _("Show usage of ARM 32-bit mode."),
2940 _("When off, a 26-bit PC will be used."),
2942 NULL
, /* FIXME: i18n: Usage of ARM 32-bit mode is %s. */
2943 &setarmcmdlist
, &showarmcmdlist
);
2945 /* Add a command to allow the user to force the FPU model. */
2946 add_setshow_enum_cmd ("fpu", no_class
, fp_model_strings
, ¤t_fp_model
,
2947 _("Set the floating point type."),
2948 _("Show the floating point type."),
2949 _("auto - Determine the FP typefrom the OS-ABI.\n\
2950 softfpa - Software FP, mixed-endian doubles on little-endian ARMs.\n\
2951 fpa - FPA co-processor (GCC compiled).\n\
2952 softvfp - Software FP with pure-endian doubles.\n\
2953 vfp - VFP co-processor."),
2954 set_fp_model_sfunc
, show_fp_model
,
2955 &setarmcmdlist
, &showarmcmdlist
);
2957 /* Add a command to allow the user to force the ABI. */
2958 add_setshow_enum_cmd ("abi", class_support
, arm_abi_strings
, &arm_abi_string
,
2961 NULL
, arm_set_abi
, arm_show_abi
,
2962 &setarmcmdlist
, &showarmcmdlist
);
2964 /* Debugging flag. */
2965 add_setshow_boolean_cmd ("arm", class_maintenance
, &arm_debug
,
2966 _("Set ARM debugging."),
2967 _("Show ARM debugging."),
2968 _("When on, arm-specific debugging is enabled."),
2970 NULL
, /* FIXME: i18n: "ARM debugging is %s. */
2971 &setdebuglist
, &showdebuglist
);