1 /* Common target dependent code for GDB on ARM systems.
2 Copyright 1988, 1989, 1991, 1992, 1993, 1995, 1996, 1997, 1998, 1999, 2000
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
28 #include "gdb_string.h"
29 #include "coff/internal.h" /* Internal format of COFF symbols in BFD */
31 extern void _initialize_arm_tdep (void);
34 The following macros are actually wrong. Neither arm nor thumb can
35 or should set the lsb on addr.
36 The thumb addresses are mod 2, so (addr & 2) would be a good heuristic
37 to use when checking for thumb (see arm_pc_is_thumb() below).
38 Unfortunately, something else depends on these (incorrect) macros, so
39 fixing them actually breaks gdb. I didn't have time to investigate. Z.R.
41 /* Thumb function addresses are odd (bit 0 is set). Here are some
42 macros to test, set, or clear bit 0 of addresses. */
43 #define IS_THUMB_ADDR(addr) ((addr) & 1)
44 #define MAKE_THUMB_ADDR(addr) ((addr) | 1)
45 #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1)
47 /* Default register names as specified by APCS. */
48 static char * atpcs_register_names
[] =
49 {"a1", "a2", "a3", "a4", /* 0 1 2 3 */
50 "v1", "v2", "v3", "v4", /* 4 5 6 7 */
51 "v5", "v6", "v7", "v8", /* 8 9 10 11 */
52 "IP", "SP", "LR", "PC", /* 12 13 14 15 */
53 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
54 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
55 "FPS", "PS" }; /* 24 25 */
57 /* Alternate set of registers names used by GCC. */
58 static char * additional_register_names
[] =
59 {"r0", "r1", "r2", "r3", /* 0 1 2 3 */
60 "r4", "r5", "r6", "r7", /* 4 5 6 7 */
61 "r8", "r9", "r10", "r11", /* 8 9 10 11 */
62 "r12", "sp", "lr", "pc", /* 12 13 14 15 */
63 "f0", "f1", "f2", "f3", /* 16 17 18 19 */
64 "f4", "f5", "f6", "f7", /* 20 21 22 23 */
65 "fps", "ps" }; /* 24 25 */
67 /* This is the variable that is set with "set disassembly-flavor".
68 By default use the APCS registers names. */
69 char ** arm_register_names
= atpcs_register_names
;
71 /* Valid register name flavours. */
72 static char apcs_flavor
[] = "apcs";
73 static char r_prefix_flavor
[] = "r-prefix";
74 static char * valid_flavors
[] =
81 /* Disassembly flavor to use. */
82 static char *disassembly_flavor
= apcs_flavor
;
84 /* This is used to keep the bfd arch_info in sync with the disassembly
86 static void set_disassembly_flavor_sfunc(char *, int,
87 struct cmd_list_element
*);
88 static void set_disassembly_flavor (void);
90 static void convert_from_extended (void *ptr
, void *dbl
);
92 /* Define other aspects of the stack frame. We keep the offsets of
93 all saved registers, 'cause we need 'em a lot! We also keep the
94 current size of the stack frame, and the offset of the frame
95 pointer from the stack pointer (for frameless functions, and when
96 we're still in the prologue of a function with a frame) */
98 struct frame_extra_info
100 struct frame_saved_regs fsr
;
106 /* Will a function return an aggregate type in memory or in a
107 register? Return 0 if an aggregate type can be returned in a
108 register, 1 if it must be returned in memory. */
111 arm_use_struct_convention (int gcc_p
, struct type
*type
)
114 register enum type_code code
;
116 /* In the ARM ABI, "integer" like aggregate types are returned in
117 registers. For an aggregate type to be integer like, its size
118 must be less than or equal to REGISTER_SIZE and the offset of
119 each addressable subfield must be zero. Note that bit fields are
120 not addressable, and all addressable subfields of unions always
121 start at offset zero.
123 This function is based on the behaviour of GCC 2.95.1.
124 See: gcc/arm.c: arm_return_in_memory() for details.
126 Note: All versions of GCC before GCC 2.95.2 do not set up the
127 parameters correctly for a function returning the following
128 structure: struct { float f;}; This should be returned in memory,
129 not a register. Richard Earnshaw sent me a patch, but I do not
130 know of any way to detect if a function like the above has been
131 compiled with the correct calling convention. */
133 /* All aggregate types that won't fit in a register must be returned
135 if (TYPE_LENGTH (type
) > REGISTER_SIZE
)
140 /* The only aggregate types that can be returned in a register are
141 structs and unions. Arrays must be returned in memory. */
142 code
= TYPE_CODE (type
);
143 if ((TYPE_CODE_STRUCT
!= code
) && (TYPE_CODE_UNION
!= code
))
148 /* Assume all other aggregate types can be returned in a register.
149 Run a check for structures, unions and arrays. */
152 if ((TYPE_CODE_STRUCT
== code
) || (TYPE_CODE_UNION
== code
))
155 /* Need to check if this struct/union is "integer" like. For
156 this to be true, its size must be less than or equal to
157 REGISTER_SIZE and the offset of each addressable subfield
158 must be zero. Note that bit fields are not addressable, and
159 unions always start at offset zero. If any of the subfields
160 is a floating point type, the struct/union cannot be an
163 /* For each field in the object, check:
164 1) Is it FP? --> yes, nRc = 1;
165 2) Is it addressable (bitpos != 0) and
166 not packed (bitsize == 0)?
170 for (i
= 0; i
< TYPE_NFIELDS (type
); i
++)
172 enum type_code field_type_code
;
173 field_type_code
= TYPE_CODE (TYPE_FIELD_TYPE (type
, i
));
175 /* Is it a floating point type field? */
176 if (field_type_code
== TYPE_CODE_FLT
)
182 /* If bitpos != 0, then we have to care about it. */
183 if (TYPE_FIELD_BITPOS (type
, i
) != 0)
185 /* Bitfields are not addressable. If the field bitsize is
186 zero, then the field is not packed. Hence it cannot be
187 a bitfield or any other packed type. */
188 if (TYPE_FIELD_BITSIZE (type
, i
) == 0)
201 arm_frame_chain_valid (CORE_ADDR chain
, struct frame_info
*thisframe
)
203 return (chain
!= 0 && (FRAME_SAVED_PC (thisframe
) >= LOWEST_PC
));
206 /* Set to true if the 32-bit mode is in use. */
210 /* Flag set by arm_fix_call_dummy that tells whether the target
211 function is a Thumb function. This flag is checked by
212 arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and
213 its use in valops.c) to pass the function address as an additional
216 static int target_is_thumb
;
218 /* Flag set by arm_fix_call_dummy that tells whether the calling
219 function is a Thumb function. This flag is checked by
220 arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */
222 static int caller_is_thumb
;
224 /* Determine if the program counter specified in MEMADDR is in a Thumb
228 arm_pc_is_thumb (bfd_vma memaddr
)
230 struct minimal_symbol
*sym
;
232 /* If bit 0 of the address is set, assume this is a Thumb address. */
233 if (IS_THUMB_ADDR (memaddr
))
236 /* Thumb functions have a "special" bit set in minimal symbols. */
237 sym
= lookup_minimal_symbol_by_pc (memaddr
);
240 return (MSYMBOL_IS_SPECIAL (sym
));
248 /* Determine if the program counter specified in MEMADDR is in a call
249 dummy being called from a Thumb function. */
252 arm_pc_is_thumb_dummy (bfd_vma memaddr
)
254 CORE_ADDR sp
= read_sp ();
256 if (PC_IN_CALL_DUMMY (memaddr
, sp
, sp
+ 64))
257 return caller_is_thumb
;
263 arm_addr_bits_remove (CORE_ADDR val
)
265 if (arm_pc_is_thumb (val
))
266 return (val
& (arm_apcs_32
? 0xfffffffe : 0x03fffffe));
268 return (val
& (arm_apcs_32
? 0xfffffffc : 0x03fffffc));
272 arm_saved_pc_after_call (struct frame_info
*frame
)
274 return ADDR_BITS_REMOVE (read_register (LR_REGNUM
));
278 arm_frameless_function_invocation (struct frame_info
*fi
)
280 CORE_ADDR func_start
, after_prologue
;
283 func_start
= (get_pc_function_start ((fi
)->pc
) + FUNCTION_START_OFFSET
);
284 after_prologue
= SKIP_PROLOGUE (func_start
);
286 /* There are some frameless functions whose first two instructions
287 follow the standard APCS form, in which case after_prologue will
288 be func_start + 8. */
290 frameless
= (after_prologue
< func_start
+ 12);
294 /* A typical Thumb prologue looks like this:
298 Sometimes the latter instruction may be replaced by:
306 or, on tpcs, like this:
313 There is always one instruction of three classes:
318 When we have found at least one of each class we are done with the prolog.
319 Note that the "sub sp, #NN" before the push does not count.
323 thumb_skip_prologue (CORE_ADDR pc
)
325 CORE_ADDR current_pc
;
326 int findmask
= 0; /* findmask:
327 bit 0 - push { rlist }
328 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
329 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
332 for (current_pc
= pc
; current_pc
< pc
+ 40; current_pc
+= 2)
334 unsigned short insn
= read_memory_unsigned_integer (current_pc
, 2);
336 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
338 findmask
|= 1; /* push found */
340 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
342 if ((findmask
& 1) == 0) /* before push ? */
345 findmask
|= 4; /* add/sub sp found */
347 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
349 findmask
|= 2; /* setting of r7 found */
351 else if (insn
== 0x466f) /* mov r7, sp */
353 findmask
|= 2; /* setting of r7 found */
356 continue; /* something in the prolog that we don't care about or some
357 instruction from outside the prolog scheduled here for optimization */
363 /* The APCS (ARM Procedure Call Standard) defines the following
367 [stmfd sp!, {a1,a2,a3,a4}]
368 stmfd sp!, {...,fp,ip,lr,pc}
369 [stfe f7, [sp, #-12]!]
370 [stfe f6, [sp, #-12]!]
371 [stfe f5, [sp, #-12]!]
372 [stfe f4, [sp, #-12]!]
373 sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */
376 arm_skip_prologue (CORE_ADDR pc
)
380 CORE_ADDR func_addr
, func_end
;
381 struct symtab_and_line sal
;
383 /* See what the symbol table says. */
385 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
387 sal
= find_pc_line (func_addr
, 0);
388 if ((sal
.line
!= 0) && (sal
.end
< func_end
))
392 /* Check if this is Thumb code. */
393 if (arm_pc_is_thumb (pc
))
394 return thumb_skip_prologue (pc
);
396 /* Can't find the prologue end in the symbol table, try it the hard way
397 by disassembling the instructions. */
399 inst
= read_memory_integer (skip_pc
, 4);
400 if (inst
!= 0xe1a0c00d) /* mov ip, sp */
404 inst
= read_memory_integer (skip_pc
, 4);
405 if ((inst
& 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */
408 inst
= read_memory_integer (skip_pc
, 4);
411 if ((inst
& 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */
415 inst
= read_memory_integer (skip_pc
, 4);
417 /* Any insns after this point may float into the code, if it makes
418 for better instruction scheduling, so we skip them only if we
419 find them, but still consdier the function to be frame-ful. */
421 /* We may have either one sfmfd instruction here, or several stfe
422 insns, depending on the version of floating point code we
424 if ((inst
& 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */
427 inst
= read_memory_integer (skip_pc
, 4);
431 while ((inst
& 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */
434 inst
= read_memory_integer (skip_pc
, 4);
438 if ((inst
& 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */
444 /* Function: thumb_scan_prologue (helper function for arm_scan_prologue)
445 This function decodes a Thumb function prologue to determine:
446 1) the size of the stack frame
447 2) which registers are saved on it
448 3) the offsets of saved regs
449 4) the offset from the stack pointer to the frame pointer
450 This information is stored in the "extra" fields of the frame_info.
452 A typical Thumb function prologue would create this stack frame
453 (offsets relative to FP)
454 old SP -> 24 stack parameters
457 R7 -> 0 local variables (16 bytes)
458 SP -> -12 additional stack space (12 bytes)
459 The frame size would thus be 36 bytes, and the frame offset would be
460 12 bytes. The frame register is R7.
462 The comments for thumb_skip_prolog() describe the algorithm we use to detect
463 the end of the prolog */
467 thumb_scan_prologue (struct frame_info
*fi
)
469 CORE_ADDR prologue_start
;
470 CORE_ADDR prologue_end
;
471 CORE_ADDR current_pc
;
472 int saved_reg
[16]; /* which register has been copied to register n? */
473 int findmask
= 0; /* findmask:
474 bit 0 - push { rlist }
475 bit 1 - mov r7, sp OR add r7, sp, #imm (setting of r7)
476 bit 2 - sub sp, #simm OR add sp, #simm (adjusting of sp)
480 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
482 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
484 if (sal
.line
== 0) /* no line info, use current PC */
485 prologue_end
= fi
->pc
;
486 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
487 prologue_end
= sal
.end
; /* (probably means no prologue) */
490 prologue_end
= prologue_start
+ 40; /* We're in the boondocks: allow for */
491 /* 16 pushes, an add, and "mv fp,sp" */
493 prologue_end
= min (prologue_end
, fi
->pc
);
495 /* Initialize the saved register map. When register H is copied to
496 register L, we will put H in saved_reg[L]. */
497 for (i
= 0; i
< 16; i
++)
500 /* Search the prologue looking for instructions that set up the
501 frame pointer, adjust the stack pointer, and save registers.
502 Do this until all basic prolog instructions are found. */
505 for (current_pc
= prologue_start
;
506 (current_pc
< prologue_end
) && ((findmask
& 7) != 7);
513 insn
= read_memory_unsigned_integer (current_pc
, 2);
515 if ((insn
& 0xfe00) == 0xb400) /* push { rlist } */
518 findmask
|= 1; /* push found */
519 /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says
520 whether to save LR (R14). */
521 mask
= (insn
& 0xff) | ((insn
& 0x100) << 6);
523 /* Calculate offsets of saved R0-R7 and LR. */
524 for (regno
= LR_REGNUM
; regno
>= 0; regno
--)
525 if (mask
& (1 << regno
))
528 fi
->fsr
.regs
[saved_reg
[regno
]] = -(fi
->framesize
);
529 saved_reg
[regno
] = regno
; /* reset saved register map */
532 else if ((insn
& 0xff00) == 0xb000) /* add sp, #simm OR sub sp, #simm */
534 if ((findmask
& 1) == 0) /* before push ? */
537 findmask
|= 4; /* add/sub sp found */
539 offset
= (insn
& 0x7f) << 2; /* get scaled offset */
540 if (insn
& 0x80) /* is it signed? (==subtracting) */
542 fi
->frameoffset
+= offset
;
545 fi
->framesize
-= offset
;
547 else if ((insn
& 0xff00) == 0xaf00) /* add r7, sp, #imm */
549 findmask
|= 2; /* setting of r7 found */
550 fi
->framereg
= THUMB_FP_REGNUM
;
551 fi
->frameoffset
= (insn
& 0xff) << 2; /* get scaled offset */
553 else if (insn
== 0x466f) /* mov r7, sp */
555 findmask
|= 2; /* setting of r7 found */
556 fi
->framereg
= THUMB_FP_REGNUM
;
558 saved_reg
[THUMB_FP_REGNUM
] = SP_REGNUM
;
560 else if ((insn
& 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */
562 int lo_reg
= insn
& 7; /* dest. register (r0-r7) */
563 int hi_reg
= ((insn
>> 3) & 7) + 8; /* source register (r8-15) */
564 saved_reg
[lo_reg
] = hi_reg
; /* remember hi reg was saved */
567 continue; /* something in the prolog that we don't care about or some
568 instruction from outside the prolog scheduled here for optimization */
572 /* Check if prologue for this frame's PC has already been scanned. If
573 it has, copy the relevant information about that prologue and
574 return non-zero. Otherwise do not copy anything and return zero.
576 The information saved in the cache includes:
577 * the frame register number;
578 * the size of the stack frame;
579 * the offsets of saved regs (relative to the old SP); and
580 * the offset from the stack pointer to the frame pointer
582 The cache contains only one entry, since this is adequate for the
583 typical sequence of prologue scan requests we get. When performing
584 a backtrace, GDB will usually ask to scan the same function twice
585 in a row (once to get the frame chain, and once to fill in the
586 extra frame information). */
588 static struct frame_info prologue_cache
;
591 check_prologue_cache (struct frame_info
*fi
)
595 if (fi
->pc
== prologue_cache
.pc
)
597 fi
->framereg
= prologue_cache
.framereg
;
598 fi
->framesize
= prologue_cache
.framesize
;
599 fi
->frameoffset
= prologue_cache
.frameoffset
;
600 for (i
= 0; i
<= NUM_REGS
; i
++)
601 fi
->fsr
.regs
[i
] = prologue_cache
.fsr
.regs
[i
];
609 /* Copy the prologue information from fi to the prologue cache. */
612 save_prologue_cache (struct frame_info
*fi
)
616 prologue_cache
.pc
= fi
->pc
;
617 prologue_cache
.framereg
= fi
->framereg
;
618 prologue_cache
.framesize
= fi
->framesize
;
619 prologue_cache
.frameoffset
= fi
->frameoffset
;
621 for (i
= 0; i
<= NUM_REGS
; i
++)
622 prologue_cache
.fsr
.regs
[i
] = fi
->fsr
.regs
[i
];
626 /* This function decodes an ARM function prologue to determine:
627 1) the size of the stack frame
628 2) which registers are saved on it
629 3) the offsets of saved regs
630 4) the offset from the stack pointer to the frame pointer
631 This information is stored in the "extra" fields of the frame_info.
633 There are two basic forms for the ARM prologue. The fixed argument
634 function call will look like:
637 stmfd sp!, {fp, ip, lr, pc}
641 Which would create this stack frame (offsets relative to FP):
642 IP -> 4 (caller's stack)
643 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
644 -4 LR (return address in caller)
645 -8 IP (copy of caller's SP)
647 SP -> -28 Local variables
649 The frame size would thus be 32 bytes, and the frame offset would be
650 28 bytes. The stmfd call can also save any of the vN registers it
651 plans to use, which increases the frame size accordingly.
653 Note: The stored PC is 8 off of the STMFD instruction that stored it
654 because the ARM Store instructions always store PC + 8 when you read
657 A variable argument function call will look like:
660 stmfd sp!, {a1, a2, a3, a4}
661 stmfd sp!, {fp, ip, lr, pc}
664 Which would create this stack frame (offsets relative to FP):
665 IP -> 20 (caller's stack)
670 FP -> 0 PC (points to address of stmfd instruction + 8 in callee)
671 -4 LR (return address in caller)
672 -8 IP (copy of caller's SP)
674 SP -> -28 Local variables
676 The frame size would thus be 48 bytes, and the frame offset would be
679 There is another potential complication, which is that the optimizer
680 will try to separate the store of fp in the "stmfd" instruction from
681 the "sub fp, ip, #NN" instruction. Almost anything can be there, so
682 we just key on the stmfd, and then scan for the "sub fp, ip, #NN"...
684 Also, note, the original version of the ARM toolchain claimed that there
687 instruction at the end of the prologue. I have never seen GCC produce
688 this, and the ARM docs don't mention it. We still test for it below in
694 arm_scan_prologue (struct frame_info
*fi
)
696 int regno
, sp_offset
, fp_offset
;
697 CORE_ADDR prologue_start
, prologue_end
, current_pc
;
699 /* Check if this function is already in the cache of frame information. */
700 if (check_prologue_cache (fi
))
703 /* Assume there is no frame until proven otherwise. */
704 fi
->framereg
= SP_REGNUM
;
708 /* Check for Thumb prologue. */
709 if (arm_pc_is_thumb (fi
->pc
))
711 thumb_scan_prologue (fi
);
712 save_prologue_cache (fi
);
716 /* Find the function prologue. If we can't find the function in
717 the symbol table, peek in the stack frame to find the PC. */
718 if (find_pc_partial_function (fi
->pc
, NULL
, &prologue_start
, &prologue_end
))
720 /* Assume the prologue is everything between the first instruction
721 in the function and the first source line. */
722 struct symtab_and_line sal
= find_pc_line (prologue_start
, 0);
724 if (sal
.line
== 0) /* no line info, use current PC */
725 prologue_end
= fi
->pc
;
726 else if (sal
.end
< prologue_end
) /* next line begins after fn end */
727 prologue_end
= sal
.end
; /* (probably means no prologue) */
731 /* Get address of the stmfd in the prologue of the callee; the saved
732 PC is the address of the stmfd + 8. */
733 prologue_start
= ADDR_BITS_REMOVE (read_memory_integer (fi
->frame
, 4))
735 prologue_end
= prologue_start
+ 64; /* This is all the insn's
736 that could be in the prologue,
737 plus room for 5 insn's inserted
741 /* Now search the prologue looking for instructions that set up the
742 frame pointer, adjust the stack pointer, and save registers.
744 Be careful, however, and if it doesn't look like a prologue,
745 don't try to scan it. If, for instance, a frameless function
746 begins with stmfd sp!, then we will tell ourselves there is
747 a frame, which will confuse stack traceback, as well ad"finish"
748 and other operations that rely on a knowledge of the stack
751 In the APCS, the prologue should start with "mov ip, sp" so
752 if we don't see this as the first insn, we will stop. */
754 sp_offset
= fp_offset
= 0;
756 if (read_memory_unsigned_integer (prologue_start
, 4)
757 == 0xe1a0c00d) /* mov ip, sp */
759 for (current_pc
= prologue_start
+ 4; current_pc
< prologue_end
;
762 unsigned int insn
= read_memory_unsigned_integer (current_pc
, 4);
764 if ((insn
& 0xffff0000) == 0xe92d0000)
765 /* stmfd sp!, {..., fp, ip, lr, pc}
767 stmfd sp!, {a1, a2, a3, a4} */
769 int mask
= insn
& 0xffff;
771 /* Calculate offsets of saved registers. */
772 for (regno
= PC_REGNUM
; regno
>= 0; regno
--)
773 if (mask
& (1 << regno
))
776 fi
->fsr
.regs
[regno
] = sp_offset
;
779 else if ((insn
& 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */
781 unsigned imm
= insn
& 0xff; /* immediate value */
782 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
783 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
785 fi
->framereg
= FP_REGNUM
;
787 else if ((insn
& 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */
789 unsigned imm
= insn
& 0xff; /* immediate value */
790 unsigned rot
= (insn
& 0xf00) >> 7; /* rotate amount */
791 imm
= (imm
>> rot
) | (imm
<< (32 - rot
));
794 else if ((insn
& 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */
797 regno
= F0_REGNUM
+ ((insn
>> 12) & 0x07);
798 fi
->fsr
.regs
[regno
] = sp_offset
;
800 else if ((insn
& 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */
803 unsigned int fp_start_reg
, fp_bound_reg
;
805 if ((insn
& 0x800) == 0x800) /* N0 is set */
807 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
814 if ((insn
& 0x40000) == 0x40000) /* N1 is set */
820 fp_start_reg
= F0_REGNUM
+ ((insn
>> 12) & 0x7);
821 fp_bound_reg
= fp_start_reg
+ n_saved_fp_regs
;
822 for (; fp_start_reg
< fp_bound_reg
; fp_start_reg
++)
825 fi
->fsr
.regs
[fp_start_reg
++] = sp_offset
;
829 /* The optimizer might shove anything into the prologue,
830 so we just skip what we don't recognize. */
835 /* The frame size is just the negative of the offset (from the original SP)
836 of the last thing thing we pushed on the stack. The frame offset is
837 [new FP] - [new SP]. */
838 fi
->framesize
= -sp_offset
;
839 fi
->frameoffset
= fp_offset
- sp_offset
;
841 save_prologue_cache (fi
);
844 /* Find REGNUM on the stack. Otherwise, it's in an active register.
845 One thing we might want to do here is to check REGNUM against the
846 clobber mask, and somehow flag it as invalid if it isn't saved on
847 the stack somewhere. This would provide a graceful failure mode
848 when trying to get the value of caller-saves registers for an inner
852 arm_find_callers_reg (struct frame_info
*fi
, int regnum
)
854 for (; fi
; fi
= fi
->next
)
856 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
857 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
858 return generic_read_register_dummy (fi
->pc
, fi
->frame
, regnum
);
861 if (fi
->fsr
.regs
[regnum
] != 0)
862 return read_memory_integer (fi
->fsr
.regs
[regnum
],
863 REGISTER_RAW_SIZE (regnum
));
864 return read_register (regnum
);
867 /* Function: frame_chain
868 Given a GDB frame, determine the address of the calling function's frame.
869 This will be used to create a new GDB frame struct, and then
870 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
871 For ARM, we save the frame size when we initialize the frame_info.
873 The original definition of this function was a macro in tm-arm.h:
874 { In the case of the ARM, the frame's nominal address is the FP value,
875 and 12 bytes before comes the saved previous FP value as a 4-byte word. }
877 #define FRAME_CHAIN(thisframe) \
878 ((thisframe)->pc >= LOWEST_PC ? \
879 read_memory_integer ((thisframe)->frame - 12, 4) :\
885 arm_frame_chain (struct frame_info
*fi
)
887 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
888 CORE_ADDR fn_start
, callers_pc
, fp
;
890 /* is this a dummy frame? */
891 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
892 return fi
->frame
; /* dummy frame same as caller's frame */
894 /* is caller-of-this a dummy frame? */
895 callers_pc
= FRAME_SAVED_PC (fi
); /* find out who called us: */
896 fp
= arm_find_callers_reg (fi
, FP_REGNUM
);
897 if (PC_IN_CALL_DUMMY (callers_pc
, fp
, fp
))
898 return fp
; /* dummy frame's frame may bear no relation to ours */
900 if (find_pc_partial_function (fi
->pc
, 0, &fn_start
, 0))
901 if (fn_start
== entry_point_address ())
902 return 0; /* in _start fn, don't chain further */
904 CORE_ADDR caller_pc
, fn_start
;
905 struct frame_info caller_fi
;
906 int framereg
= fi
->framereg
;
908 if (fi
->pc
< LOWEST_PC
)
911 /* If the caller is the startup code, we're at the end of the chain. */
912 caller_pc
= FRAME_SAVED_PC (fi
);
913 if (find_pc_partial_function (caller_pc
, 0, &fn_start
, 0))
914 if (fn_start
== entry_point_address ())
917 /* If the caller is Thumb and the caller is ARM, or vice versa,
918 the frame register of the caller is different from ours.
919 So we must scan the prologue of the caller to determine its
920 frame register number. */
921 if (arm_pc_is_thumb (caller_pc
) != arm_pc_is_thumb (fi
->pc
))
923 memset (&caller_fi
, 0, sizeof (caller_fi
));
924 caller_fi
.pc
= caller_pc
;
925 arm_scan_prologue (&caller_fi
);
926 framereg
= caller_fi
.framereg
;
929 /* If the caller used a frame register, return its value.
930 Otherwise, return the caller's stack pointer. */
931 if (framereg
== FP_REGNUM
|| framereg
== THUMB_FP_REGNUM
)
932 return arm_find_callers_reg (fi
, framereg
);
934 return fi
->frame
+ fi
->framesize
;
937 /* This function actually figures out the frame address for a given pc
938 and sp. This is tricky because we sometimes don't use an explicit
939 frame pointer, and the previous stack pointer isn't necessarily
940 recorded on the stack. The only reliable way to get this info is
941 to examine the prologue. FROMLEAF is a little confusing, it means
942 this is the next frame up the chain AFTER a frameless function. If
943 this is true, then the frame value for this frame is still in the
947 arm_init_extra_frame_info (int fromleaf
, struct frame_info
*fi
)
952 fi
->pc
= FRAME_SAVED_PC (fi
->next
);
954 memset (fi
->fsr
.regs
, '\000', sizeof fi
->fsr
.regs
);
956 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
957 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
959 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
960 by assuming it's always FP. */
961 fi
->frame
= generic_read_register_dummy (fi
->pc
, fi
->frame
, SP_REGNUM
);
969 arm_scan_prologue (fi
);
972 /* this is the innermost frame? */
973 fi
->frame
= read_register (fi
->framereg
);
974 else if (fi
->framereg
== FP_REGNUM
|| fi
->framereg
== THUMB_FP_REGNUM
)
976 /* not the innermost frame */
977 /* If we have an FP, the callee saved it. */
978 if (fi
->next
->fsr
.regs
[fi
->framereg
] != 0)
980 read_memory_integer (fi
->next
->fsr
.regs
[fi
->framereg
], 4);
982 /* If we were called by a frameless fn. then our frame is
983 still in the frame pointer register on the board... */
984 fi
->frame
= read_fp ();
987 /* Calculate actual addresses of saved registers using offsets
988 determined by arm_scan_prologue. */
989 for (reg
= 0; reg
< NUM_REGS
; reg
++)
990 if (fi
->fsr
.regs
[reg
] != 0)
991 fi
->fsr
.regs
[reg
] += fi
->frame
+ fi
->framesize
- fi
->frameoffset
;
996 /* Find the caller of this frame. We do this by seeing if LR_REGNUM
997 is saved in the stack anywhere, otherwise we get it from the
1000 The old definition of this function was a macro:
1001 #define FRAME_SAVED_PC(FRAME) \
1002 ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */
1005 arm_frame_saved_pc (struct frame_info
*fi
)
1007 #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */
1008 if (PC_IN_CALL_DUMMY (fi
->pc
, fi
->frame
, fi
->frame
))
1009 return generic_read_register_dummy (fi
->pc
, fi
->frame
, PC_REGNUM
);
1013 CORE_ADDR pc
= arm_find_callers_reg (fi
, LR_REGNUM
);
1014 return IS_THUMB_ADDR (pc
) ? UNMAKE_THUMB_ADDR (pc
) : pc
;
1018 /* Return the frame address. On ARM, it is R11; on Thumb it is R7.
1019 Examine the Program Status Register to decide which state we're in. */
1022 arm_target_read_fp (void)
1024 if (read_register (PS_REGNUM
) & 0x20) /* Bit 5 is Thumb state bit */
1025 return read_register (THUMB_FP_REGNUM
); /* R7 if Thumb */
1027 return read_register (FP_REGNUM
); /* R11 if ARM */
1030 /* Calculate the frame offsets of the saved registers (ARM version). */
1033 arm_frame_find_saved_regs (struct frame_info
*fi
,
1034 struct frame_saved_regs
*regaddr
)
1036 memcpy (regaddr
, &fi
->fsr
, sizeof (struct frame_saved_regs
));
1040 arm_push_dummy_frame (void)
1042 CORE_ADDR old_sp
= read_register (SP_REGNUM
);
1043 CORE_ADDR sp
= old_sp
;
1044 CORE_ADDR fp
, prologue_start
;
1047 /* Push the two dummy prologue instructions in reverse order,
1048 so that they'll be in the correct low-to-high order in memory. */
1049 /* sub fp, ip, #4 */
1050 sp
= push_word (sp
, 0xe24cb004);
1051 /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */
1052 prologue_start
= sp
= push_word (sp
, 0xe92ddfff);
1054 /* Push a pointer to the dummy prologue + 12, because when stm
1055 instruction stores the PC, it stores the address of the stm
1056 instruction itself plus 12. */
1057 fp
= sp
= push_word (sp
, prologue_start
+ 12);
1058 sp
= push_word (sp
, read_register (PC_REGNUM
)); /* FIXME: was PS_REGNUM */
1059 sp
= push_word (sp
, old_sp
);
1060 sp
= push_word (sp
, read_register (FP_REGNUM
));
1062 for (regnum
= 10; regnum
>= 0; regnum
--)
1063 sp
= push_word (sp
, read_register (regnum
));
1065 write_register (FP_REGNUM
, fp
);
1066 write_register (THUMB_FP_REGNUM
, fp
);
1067 write_register (SP_REGNUM
, sp
);
1070 /* Fix up the call dummy, based on whether the processor is currently
1071 in Thumb or ARM mode, and whether the target function is Thumb or
1072 ARM. There are three different situations requiring three
1075 * ARM calling ARM: uses the call dummy in tm-arm.h, which has already
1076 been copied into the dummy parameter to this function.
1077 * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the
1078 "mov pc,r4" instruction patched to be a "bx r4" instead.
1079 * Thumb calling anything: uses the Thumb dummy defined below, which
1080 works for calling both ARM and Thumb functions.
1082 All three call dummies expect to receive the target function
1083 address in R4, with the low bit set if it's a Thumb function. */
1086 arm_fix_call_dummy (char *dummy
, CORE_ADDR pc
, CORE_ADDR fun
, int nargs
,
1087 value_ptr
*args
, struct type
*type
, int gcc_p
)
1089 static short thumb_dummy
[4] =
1091 0xf000, 0xf801, /* bl label */
1092 0xdf18, /* swi 24 */
1093 0x4720, /* label: bx r4 */
1095 static unsigned long arm_bx_r4
= 0xe12fff14; /* bx r4 instruction */
1097 /* Set flag indicating whether the current PC is in a Thumb function. */
1098 caller_is_thumb
= arm_pc_is_thumb (read_pc ());
1100 /* If the target function is Thumb, set the low bit of the function
1101 address. And if the CPU is currently in ARM mode, patch the
1102 second instruction of call dummy to use a BX instruction to
1103 switch to Thumb mode. */
1104 target_is_thumb
= arm_pc_is_thumb (fun
);
1105 if (target_is_thumb
)
1108 if (!caller_is_thumb
)
1109 store_unsigned_integer (dummy
+ 4, sizeof (arm_bx_r4
), arm_bx_r4
);
1112 /* If the CPU is currently in Thumb mode, use the Thumb call dummy
1113 instead of the ARM one that's already been copied. This will
1114 work for both Thumb and ARM target functions. */
1115 if (caller_is_thumb
)
1119 int len
= sizeof (thumb_dummy
) / sizeof (thumb_dummy
[0]);
1121 for (i
= 0; i
< len
; i
++)
1123 store_unsigned_integer (p
, sizeof (thumb_dummy
[0]), thumb_dummy
[i
]);
1124 p
+= sizeof (thumb_dummy
[0]);
1128 /* Put the target address in r4; the call dummy will copy this to
1130 write_register (4, fun
);
1133 /* Return the offset in the call dummy of the instruction that needs
1134 to have a breakpoint placed on it. This is the offset of the 'swi
1135 24' instruction, which is no longer actually used, but simply acts
1136 as a place-holder now.
1138 This implements the CALL_DUMMY_BREAK_OFFSET macro. */
1141 arm_call_dummy_breakpoint_offset (void)
1143 if (caller_is_thumb
)
1151 This function does not support passing parameters using the FPA
1152 variant of the APCS. It passes any floating point arguments in the
1153 general registers and/or on the stack. */
1156 arm_push_arguments (int nargs
, value_ptr
* args
, CORE_ADDR sp
,
1157 int struct_return
, CORE_ADDR struct_addr
)
1160 int argnum
, argreg
, nstack_size
;
1162 /* Walk through the list of args and determine how large a temporary
1163 stack is required. Need to take care here as structs may be
1164 passed on the stack, and we have to to push them. */
1165 nstack_size
= -4 * REGISTER_SIZE
; /* Some arguments go into A1-A4. */
1166 if (struct_return
) /* The struct address goes in A1. */
1167 nstack_size
+= REGISTER_SIZE
;
1169 /* Walk through the arguments and add their size to nstack_size. */
1170 for (argnum
= 0; argnum
< nargs
; argnum
++)
1173 struct type
*arg_type
;
1175 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1176 len
= TYPE_LENGTH (arg_type
);
1178 /* ANSI C code passes float arguments as integers, K&R code
1179 passes float arguments as doubles. Correct for this here. */
1180 if (TYPE_CODE_FLT
== TYPE_CODE (arg_type
) && REGISTER_SIZE
== len
)
1181 nstack_size
+= FP_REGISTER_VIRTUAL_SIZE
;
1186 /* Allocate room on the stack, and initialize our stack frame
1189 if (nstack_size
> 0)
1195 /* Initialize the integer argument register pointer. */
1198 /* The struct_return pointer occupies the first parameter passing
1201 write_register (argreg
++, struct_addr
);
1203 /* Process arguments from left to right. Store as many as allowed
1204 in the parameter passing registers (A1-A4), and save the rest on
1205 the temporary stack. */
1206 for (argnum
= 0; argnum
< nargs
; argnum
++)
1212 enum type_code typecode
;
1213 struct type
*arg_type
, *target_type
;
1215 arg_type
= check_typedef (VALUE_TYPE (args
[argnum
]));
1216 target_type
= TYPE_TARGET_TYPE (arg_type
);
1217 len
= TYPE_LENGTH (arg_type
);
1218 typecode
= TYPE_CODE (arg_type
);
1219 val
= (char *) VALUE_CONTENTS (args
[argnum
]);
1221 /* ANSI C code passes float arguments as integers, K&R code
1222 passes float arguments as doubles. The .stabs record for
1223 for ANSI prototype floating point arguments records the
1224 type as FP_INTEGER, while a K&R style (no prototype)
1225 .stabs records the type as FP_FLOAT. In this latter case
1226 the compiler converts the float arguments to double before
1227 calling the function. */
1228 if (TYPE_CODE_FLT
== typecode
&& REGISTER_SIZE
== len
)
1230 float f
= *(float *) val
;
1232 val
= (char *) &dbl_arg
;
1233 len
= sizeof (double);
1236 /* I don't know why this code was disable. The only logical use
1237 for a function pointer is to call that function, so setting
1238 the mode bit is perfectly fine. FN */
1239 /* If the argument is a pointer to a function, and it is a Thumb
1240 function, set the low bit of the pointer. */
1241 if (TYPE_CODE_PTR
== typecode
1242 && NULL
!= target_type
1243 && TYPE_CODE_FUNC
== TYPE_CODE (target_type
))
1245 CORE_ADDR regval
= extract_address (val
, len
);
1246 if (arm_pc_is_thumb (regval
))
1247 store_address (val
, len
, MAKE_THUMB_ADDR (regval
));
1250 /* Copy the argument to general registers or the stack in
1251 register-sized pieces. Large arguments are split between
1252 registers and stack. */
1255 int partial_len
= len
< REGISTER_SIZE
? len
: REGISTER_SIZE
;
1257 if (argreg
<= ARM_LAST_ARG_REGNUM
)
1259 /* It's an argument being passed in a general register. */
1260 regval
= extract_address (val
, partial_len
);
1261 write_register (argreg
++, regval
);
1265 /* Push the arguments onto the stack. */
1266 write_memory ((CORE_ADDR
) fp
, val
, REGISTER_SIZE
);
1267 fp
+= REGISTER_SIZE
;
1275 /* Return adjusted stack pointer. */
1280 arm_pop_frame (void)
1282 struct frame_info
*frame
= get_current_frame ();
1286 old_SP
= read_register (frame
->framereg
);
1287 for (regnum
= 0; regnum
< NUM_REGS
; regnum
++)
1288 if (frame
->fsr
.regs
[regnum
] != 0)
1289 write_register (regnum
,
1290 read_memory_integer (frame
->fsr
.regs
[regnum
], 4));
1292 write_register (PC_REGNUM
, FRAME_SAVED_PC (frame
));
1293 write_register (SP_REGNUM
, old_SP
);
1295 flush_cached_frames ();
1299 print_fpu_flags (int flags
)
1301 if (flags
& (1 << 0))
1302 fputs ("IVO ", stdout
);
1303 if (flags
& (1 << 1))
1304 fputs ("DVZ ", stdout
);
1305 if (flags
& (1 << 2))
1306 fputs ("OFL ", stdout
);
1307 if (flags
& (1 << 3))
1308 fputs ("UFL ", stdout
);
1309 if (flags
& (1 << 4))
1310 fputs ("INX ", stdout
);
1315 arm_float_info (void)
1317 register unsigned long status
= read_register (FPS_REGNUM
);
1320 type
= (status
>> 24) & 127;
1321 printf ("%s FPU type %d\n",
1322 (status
& (1 << 31)) ? "Hardware" : "Software",
1324 fputs ("mask: ", stdout
);
1325 print_fpu_flags (status
>> 16);
1326 fputs ("flags: ", stdout
);
1327 print_fpu_flags (status
);
1330 /* If the disassembly mode is APCS, we have to also switch the
1331 bfd mach_type. This function is run in the set disassembly_flavor
1332 command, and does that. */
1335 set_disassembly_flavor_sfunc (char *args
, int from_tty
,
1336 struct cmd_list_element
*c
)
1338 set_disassembly_flavor ();
1342 set_disassembly_flavor (void)
1344 if (disassembly_flavor
== apcs_flavor
)
1346 parse_arm_disassembler_option ("reg-names-atpcs");
1347 arm_register_names
= atpcs_register_names
;
1349 else if (disassembly_flavor
== r_prefix_flavor
)
1351 parse_arm_disassembler_option ("reg-names-std");
1352 arm_register_names
= additional_register_names
;
1356 /* arm_othernames implements the "othernames" command. This is kind
1357 of hacky, and I prefer the set-show disassembly-flavor which is
1358 also used for the x86 gdb. I will keep this around, however, in
1359 case anyone is actually using it. */
1362 arm_othernames (char *names
, int n
)
1364 if (disassembly_flavor
== r_prefix_flavor
)
1366 disassembly_flavor
= apcs_flavor
;
1367 set_disassembly_flavor ();
1371 disassembly_flavor
= r_prefix_flavor
;
1372 set_disassembly_flavor ();
1377 /* FIXME: The generated assembler works but sucks. Instead of using
1378 r0, r1 it pushes them on the stack, then loads them into r3, r4 and
1379 uses those registers. I must be missing something. ScottB */
1382 convert_from_extended (void *ptr
, void *dbl
)
1388 : "r" (ptr
), "r" (dbl
));
1392 convert_to_extended (void *dbl
, void *ptr
)
1398 : "r" (dbl
), "r" (ptr
));
1402 convert_from_extended (void *ptr
, void *dbl
)
1404 *(double *) dbl
= *(double *) ptr
;
1408 convert_to_extended (void *dbl
, void *ptr
)
1410 *(double *) ptr
= *(double *) dbl
;
1414 /* Nonzero if register N requires conversion from raw format to
1418 arm_register_convertible (unsigned int regnum
)
1420 return ((regnum
- F0_REGNUM
) < 8);
1423 /* Convert data from raw format for register REGNUM in buffer FROM to
1424 virtual format with type TYPE in buffer TO. */
1427 arm_register_convert_to_virtual (unsigned int regnum
, struct type
*type
,
1428 void *from
, void *to
)
1432 convert_from_extended (from
, &val
);
1433 store_floating (to
, TYPE_LENGTH (type
), val
);
1436 /* Convert data from virtual format with type TYPE in buffer FROM to
1437 raw format for register REGNUM in buffer TO. */
1440 arm_register_convert_to_raw (unsigned int regnum
, struct type
*type
,
1441 void *from
, void *to
)
1443 double val
= extract_floating (from
, TYPE_LENGTH (type
));
1445 convert_to_extended (&val
, to
);
1449 condition_true (unsigned long cond
, unsigned long status_reg
)
1451 if (cond
== INST_AL
|| cond
== INST_NV
)
1457 return ((status_reg
& FLAG_Z
) != 0);
1459 return ((status_reg
& FLAG_Z
) == 0);
1461 return ((status_reg
& FLAG_C
) != 0);
1463 return ((status_reg
& FLAG_C
) == 0);
1465 return ((status_reg
& FLAG_N
) != 0);
1467 return ((status_reg
& FLAG_N
) == 0);
1469 return ((status_reg
& FLAG_V
) != 0);
1471 return ((status_reg
& FLAG_V
) == 0);
1473 return ((status_reg
& (FLAG_C
| FLAG_Z
)) == FLAG_C
);
1475 return ((status_reg
& (FLAG_C
| FLAG_Z
)) != FLAG_C
);
1477 return (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0));
1479 return (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0));
1481 return (((status_reg
& FLAG_Z
) == 0) &&
1482 (((status_reg
& FLAG_N
) == 0) == ((status_reg
& FLAG_V
) == 0)));
1484 return (((status_reg
& FLAG_Z
) != 0) ||
1485 (((status_reg
& FLAG_N
) == 0) != ((status_reg
& FLAG_V
) == 0)));
1490 #define submask(x) ((1L << ((x) + 1)) - 1)
1491 #define bit(obj,st) (((obj) >> (st)) & 1)
1492 #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st)))
1493 #define sbits(obj,st,fn) \
1494 ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st))))
1495 #define BranchDest(addr,instr) \
1496 ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2)))
1499 static unsigned long
1500 shifted_reg_val (unsigned long inst
, int carry
, unsigned long pc_val
,
1501 unsigned long status_reg
)
1503 unsigned long res
, shift
;
1504 int rm
= bits (inst
, 0, 3);
1505 unsigned long shifttype
= bits (inst
, 5, 6);
1509 int rs
= bits (inst
, 8, 11);
1510 shift
= (rs
== 15 ? pc_val
+ 8 : read_register (rs
)) & 0xFF;
1513 shift
= bits (inst
, 7, 11);
1516 ? ((pc_val
| (ARM_PC_32
? 0 : status_reg
))
1517 + (bit (inst
, 4) ? 12 : 8))
1518 : read_register (rm
));
1523 res
= shift
>= 32 ? 0 : res
<< shift
;
1527 res
= shift
>= 32 ? 0 : res
>> shift
;
1533 res
= ((res
& 0x80000000L
)
1534 ? ~((~res
) >> shift
) : res
>> shift
);
1537 case 3: /* ROR/RRX */
1540 res
= (res
>> 1) | (carry
? 0x80000000L
: 0);
1542 res
= (res
>> shift
) | (res
<< (32 - shift
));
1546 return res
& 0xffffffff;
1549 /* Return number of 1-bits in VAL. */
1552 bitcount (unsigned long val
)
1555 for (nbits
= 0; val
!= 0; nbits
++)
1556 val
&= val
- 1; /* delete rightmost 1-bit in val */
1561 thumb_get_next_pc (CORE_ADDR pc
)
1563 unsigned long pc_val
= ((unsigned long) pc
) + 4; /* PC after prefetch */
1564 unsigned short inst1
= read_memory_integer (pc
, 2);
1565 CORE_ADDR nextpc
= pc
+ 2; /* default is next instruction */
1566 unsigned long offset
;
1568 if ((inst1
& 0xff00) == 0xbd00) /* pop {rlist, pc} */
1572 /* Fetch the saved PC from the stack. It's stored above
1573 all of the other registers. */
1574 offset
= bitcount (bits (inst1
, 0, 7)) * REGISTER_SIZE
;
1575 sp
= read_register (SP_REGNUM
);
1576 nextpc
= (CORE_ADDR
) read_memory_integer (sp
+ offset
, 4);
1577 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1579 error ("Infinite loop detected");
1581 else if ((inst1
& 0xf000) == 0xd000) /* conditional branch */
1583 unsigned long status
= read_register (PS_REGNUM
);
1584 unsigned long cond
= bits (inst1
, 8, 11);
1585 if (cond
!= 0x0f && condition_true (cond
, status
)) /* 0x0f = SWI */
1586 nextpc
= pc_val
+ (sbits (inst1
, 0, 7) << 1);
1588 else if ((inst1
& 0xf800) == 0xe000) /* unconditional branch */
1590 nextpc
= pc_val
+ (sbits (inst1
, 0, 10) << 1);
1592 else if ((inst1
& 0xf800) == 0xf000) /* long branch with link */
1594 unsigned short inst2
= read_memory_integer (pc
+ 2, 2);
1595 offset
= (sbits (inst1
, 0, 10) << 12) + (bits (inst2
, 0, 10) << 1);
1596 nextpc
= pc_val
+ offset
;
1603 arm_get_next_pc (CORE_ADDR pc
)
1605 unsigned long pc_val
;
1606 unsigned long this_instr
;
1607 unsigned long status
;
1610 if (arm_pc_is_thumb (pc
))
1611 return thumb_get_next_pc (pc
);
1613 pc_val
= (unsigned long) pc
;
1614 this_instr
= read_memory_integer (pc
, 4);
1615 status
= read_register (PS_REGNUM
);
1616 nextpc
= (CORE_ADDR
) (pc_val
+ 4); /* Default case */
1618 if (condition_true (bits (this_instr
, 28, 31), status
))
1620 switch (bits (this_instr
, 24, 27))
1623 case 0x1: /* data processing */
1627 unsigned long operand1
, operand2
, result
= 0;
1631 if (bits (this_instr
, 12, 15) != 15)
1634 if (bits (this_instr
, 22, 25) == 0
1635 && bits (this_instr
, 4, 7) == 9) /* multiply */
1636 error ("Illegal update to pc in instruction");
1638 /* Multiply into PC */
1639 c
= (status
& FLAG_C
) ? 1 : 0;
1640 rn
= bits (this_instr
, 16, 19);
1641 operand1
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1643 if (bit (this_instr
, 25))
1645 unsigned long immval
= bits (this_instr
, 0, 7);
1646 unsigned long rotate
= 2 * bits (this_instr
, 8, 11);
1647 operand2
= ((immval
>> rotate
) | (immval
<< (32 - rotate
)))
1650 else /* operand 2 is a shifted register */
1651 operand2
= shifted_reg_val (this_instr
, c
, pc_val
, status
);
1653 switch (bits (this_instr
, 21, 24))
1656 result
= operand1
& operand2
;
1660 result
= operand1
^ operand2
;
1664 result
= operand1
- operand2
;
1668 result
= operand2
- operand1
;
1672 result
= operand1
+ operand2
;
1676 result
= operand1
+ operand2
+ c
;
1680 result
= operand1
- operand2
+ c
;
1684 result
= operand2
- operand1
+ c
;
1690 case 0xb: /* tst, teq, cmp, cmn */
1691 result
= (unsigned long) nextpc
;
1695 result
= operand1
| operand2
;
1699 /* Always step into a function. */
1704 result
= operand1
& ~operand2
;
1711 nextpc
= (CORE_ADDR
) ADDR_BITS_REMOVE (result
);
1714 error ("Infinite loop detected");
1719 case 0x5: /* data transfer */
1722 if (bit (this_instr
, 20))
1725 if (bits (this_instr
, 12, 15) == 15)
1731 if (bit (this_instr
, 22))
1732 error ("Illegal update to pc in instruction");
1734 /* byte write to PC */
1735 rn
= bits (this_instr
, 16, 19);
1736 base
= (rn
== 15) ? pc_val
+ 8 : read_register (rn
);
1737 if (bit (this_instr
, 24))
1740 int c
= (status
& FLAG_C
) ? 1 : 0;
1741 unsigned long offset
=
1742 (bit (this_instr
, 25)
1743 ? shifted_reg_val (this_instr
, c
, pc_val
, status
)
1744 : bits (this_instr
, 0, 11));
1746 if (bit (this_instr
, 23))
1751 nextpc
= (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) base
,
1754 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1757 error ("Infinite loop detected");
1763 case 0x9: /* block transfer */
1764 if (bit (this_instr
, 20))
1767 if (bit (this_instr
, 15))
1772 if (bit (this_instr
, 23))
1775 unsigned long reglist
= bits (this_instr
, 0, 14);
1776 offset
= bitcount (reglist
) * 4;
1777 if (bit (this_instr
, 24)) /* pre */
1780 else if (bit (this_instr
, 24))
1784 unsigned long rn_val
=
1785 read_register (bits (this_instr
, 16, 19));
1787 (CORE_ADDR
) read_memory_integer ((CORE_ADDR
) (rn_val
1791 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1793 error ("Infinite loop detected");
1798 case 0xb: /* branch & link */
1799 case 0xa: /* branch */
1801 nextpc
= BranchDest (pc
, this_instr
);
1803 nextpc
= ADDR_BITS_REMOVE (nextpc
);
1805 error ("Infinite loop detected");
1811 case 0xe: /* coproc ops */
1816 fprintf (stderr
, "Bad bit-field extraction\n");
1824 #include "bfd-in2.h"
1825 #include "libcoff.h"
1828 gdb_print_insn_arm (bfd_vma memaddr
, disassemble_info
*info
)
1830 if (arm_pc_is_thumb (memaddr
))
1832 static asymbol
*asym
;
1833 static combined_entry_type ce
;
1834 static struct coff_symbol_struct csym
;
1835 static struct _bfd fake_bfd
;
1836 static bfd_target fake_target
;
1838 if (csym
.native
== NULL
)
1840 /* Create a fake symbol vector containing a Thumb symbol. This is
1841 solely so that the code in print_insn_little_arm() and
1842 print_insn_big_arm() in opcodes/arm-dis.c will detect the presence
1843 of a Thumb symbol and switch to decoding Thumb instructions. */
1845 fake_target
.flavour
= bfd_target_coff_flavour
;
1846 fake_bfd
.xvec
= &fake_target
;
1847 ce
.u
.syment
.n_sclass
= C_THUMBEXTFUNC
;
1849 csym
.symbol
.the_bfd
= &fake_bfd
;
1850 csym
.symbol
.name
= "fake";
1851 asym
= (asymbol
*) & csym
;
1854 memaddr
= UNMAKE_THUMB_ADDR (memaddr
);
1855 info
->symbols
= &asym
;
1858 info
->symbols
= NULL
;
1860 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1861 return print_insn_big_arm (memaddr
, info
);
1863 return print_insn_little_arm (memaddr
, info
);
1866 /* This function implements the BREAKPOINT_FROM_PC macro. It uses the
1867 program counter value to determine whether a 16-bit or 32-bit
1868 breakpoint should be used. It returns a pointer to a string of
1869 bytes that encode a breakpoint instruction, stores the length of
1870 the string to *lenptr, and adjusts the program counter (if
1871 necessary) to point to the actual memory location where the
1872 breakpoint should be inserted. */
1875 arm_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
1877 if (arm_pc_is_thumb (*pcptr
) || arm_pc_is_thumb_dummy (*pcptr
))
1879 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1881 static char thumb_breakpoint
[] = THUMB_BE_BREAKPOINT
;
1882 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1883 *lenptr
= sizeof (thumb_breakpoint
);
1884 return thumb_breakpoint
;
1888 static char thumb_breakpoint
[] = THUMB_LE_BREAKPOINT
;
1889 *pcptr
= UNMAKE_THUMB_ADDR (*pcptr
);
1890 *lenptr
= sizeof (thumb_breakpoint
);
1891 return thumb_breakpoint
;
1896 if (TARGET_BYTE_ORDER
== BIG_ENDIAN
)
1898 static char arm_breakpoint
[] = ARM_BE_BREAKPOINT
;
1899 *lenptr
= sizeof (arm_breakpoint
);
1900 return arm_breakpoint
;
1904 static char arm_breakpoint
[] = ARM_LE_BREAKPOINT
;
1905 *lenptr
= sizeof (arm_breakpoint
);
1906 return arm_breakpoint
;
1911 /* Extract from an array REGBUF containing the (raw) register state a
1912 function return value of type TYPE, and copy that, in virtual
1913 format, into VALBUF. */
1916 arm_extract_return_value (struct type
*type
,
1917 char regbuf
[REGISTER_BYTES
],
1920 if (TYPE_CODE_FLT
== TYPE_CODE (type
))
1921 convert_from_extended (®buf
[REGISTER_BYTE (F0_REGNUM
)], valbuf
);
1923 memcpy (valbuf
, ®buf
[REGISTER_BYTE (A1_REGNUM
)], TYPE_LENGTH (type
));
1926 /* Return non-zero if the PC is inside a thumb call thunk. */
1929 arm_in_call_stub (CORE_ADDR pc
, char *name
)
1931 CORE_ADDR start_addr
;
1933 /* Find the starting address of the function containing the PC. If
1934 the caller didn't give us a name, look it up at the same time. */
1935 if (find_pc_partial_function (pc
, name
? NULL
: &name
, &start_addr
, NULL
) == 0)
1938 return strncmp (name
, "_call_via_r", 11) == 0;
1941 /* If PC is in a Thumb call or return stub, return the address of the
1942 target PC, which is in a register. The thunk functions are called
1943 _called_via_xx, where x is the register name. The possible names
1944 are r0-r9, sl, fp, ip, sp, and lr. */
1947 arm_skip_stub (CORE_ADDR pc
)
1950 CORE_ADDR start_addr
;
1952 /* Find the starting address and name of the function containing the PC. */
1953 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1956 /* Call thunks always start with "_call_via_". */
1957 if (strncmp (name
, "_call_via_", 10) == 0)
1959 /* Use the name suffix to determine which register contains the
1961 static char *table
[15] =
1962 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1963 "r8", "r9", "sl", "fp", "ip", "sp", "lr"
1967 for (regno
= 0; regno
<= 14; regno
++)
1968 if (strcmp (&name
[10], table
[regno
]) == 0)
1969 return read_register (regno
);
1972 return 0; /* not a stub */
1976 _initialize_arm_tdep (void)
1978 struct cmd_list_element
*new_cmd
;
1980 tm_print_insn
= gdb_print_insn_arm
;
1982 /* Sync the opcode insn printer with our register viewer: */
1983 parse_arm_disassembler_option ("reg-names-atpcs");
1985 /* Add the deprecated "othernames" command */
1987 add_com ("othernames", class_obscure
, arm_othernames
,
1988 "Switch to the other set of register names.");
1990 /* Add the disassembly-flavor command */
1992 new_cmd
= add_set_enum_cmd ("disassembly-flavor", no_class
,
1994 (char *) &disassembly_flavor
,
1995 "Set the disassembly flavor, \
1996 the valid values are \"apcs\" and \"r-prefix\", \
1997 and the default value is \"apcs\".",
1999 new_cmd
->function
.sfunc
= set_disassembly_flavor_sfunc
;
2000 add_show_from_set (new_cmd
, &showlist
);
2002 /* ??? Maybe this should be a boolean. */
2003 add_show_from_set (add_set_cmd ("apcs32", no_class
,
2004 var_zinteger
, (char *) &arm_apcs_32
,
2005 "Set usage of ARM 32-bit mode.\n", &setlist
),
2010 /* Test whether the coff symbol specific value corresponds to a Thumb
2014 coff_sym_is_thumb (int val
)
2016 return (val
== C_THUMBEXT
||
2017 val
== C_THUMBSTAT
||
2018 val
== C_THUMBEXTFUNC
||
2019 val
== C_THUMBSTATFUNC
||
2020 val
== C_THUMBLABEL
);