1 /* Definitions to make GDB run on a mips box under 4.3bsd.
2 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995
3 Free Software Foundation, Inc.
4 Contributed by Per Bothner (bothner@cs.wisc.edu) at U.Wisconsin
5 and by Alessandro Forin (af@cs.cmu.edu) at CMU..
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
31 #include "coff/sym.h" /* Needed for PDR below. */
32 #include "coff/symconst.h"
34 #if !defined (TARGET_BYTE_ORDER)
35 #define TARGET_BYTE_ORDER LITTLE_ENDIAN
38 #if !defined (GDB_TARGET_IS_MIPS64)
39 #define GDB_TARGET_IS_MIPS64 0
42 #if !defined (TARGET_MONITOR_PROMPT)
43 #define TARGET_MONITOR_PROMPT "<IDT>"
46 /* Floating point is IEEE compliant */
49 /* Some MIPS boards are provided both with and without a floating
50 point coprocessor. The MIPS R4650 chip has only single precision
51 floating point. We provide a user settable variable to tell gdb
52 what type of floating point to use. */
56 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
57 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
58 MIPS_FPU_NONE
/* No floating point. */
61 extern enum mips_fpu_type mips_fpu
;
63 /* The name of the usual type of MIPS processor that is in the target
66 #define DEFAULT_MIPS_TYPE "generic"
68 /* Offset from address of function to start of its code.
69 Zero on most machines. */
71 #define FUNCTION_START_OFFSET 0
73 /* Advance PC across any function entry prologue instructions
74 to reach some "real" code. */
76 #define SKIP_PROLOGUE(pc) pc = mips_skip_prologue (pc, 0)
77 extern CORE_ADDR mips_skip_prologue
PARAMS ((CORE_ADDR addr
, int lenient
));
79 /* Return non-zero if PC points to an instruction which will cause a step
80 to execute both the instruction at PC and an instruction at PC+4. */
81 #define STEP_SKIPS_DELAY(pc) (mips_step_skips_delay (pc))
82 extern int mips_step_skips_delay
PARAMS ((CORE_ADDR
));
84 /* Immediately after a function call, return the saved pc.
85 Can't always go through the frames for this because on some machines
86 the new frame is not set up until the new function executes
89 #define SAVED_PC_AFTER_CALL(frame) read_register(RA_REGNUM)
91 /* Are we currently handling a signal */
93 extern int in_sigtramp
PARAMS ((CORE_ADDR
, char *));
94 #define IN_SIGTRAMP(pc, name) in_sigtramp(pc, name)
96 /* Stack grows downward. */
100 #define BIG_ENDIAN 4321
101 #if TARGET_BYTE_ORDER == BIG_ENDIAN
102 #define BREAKPOINT {0, 0x5, 0, 0xd}
104 #define BREAKPOINT {0xd, 0, 0x5, 0}
107 /* Amount PC must be decremented by after a breakpoint.
108 This is often the number of bytes in BREAKPOINT
111 #define DECR_PC_AFTER_BREAK 0
113 /* Nonzero if instruction at PC is a return instruction. "j ra" on mips. */
115 #define ABOUT_TO_RETURN(pc) (read_memory_integer (pc, 4) == 0x3e00008)
117 /* Say how long (ordinary) registers are. This is a piece of bogosity
118 used in push_word and a few other places; REGISTER_RAW_SIZE is the
119 real way to know how big a register is. */
121 #define REGISTER_SIZE 4
123 /* The size of a register. This is predefined in tm-mips64.h. We
124 can't use REGISTER_SIZE because that is used for various other
128 #define MIPS_REGSIZE 4
131 /* Number of machine registers */
135 /* Initializer for an array of names of registers.
136 There should be NUM_REGS strings in this initializer. */
138 #define REGISTER_NAMES \
139 { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
140 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
141 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
142 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", \
143 "sr", "lo", "hi", "bad", "cause","pc", \
144 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
145 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
146 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",\
147 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",\
148 "fsr", "fir", "fp", "", \
149 "", "", "", "", "", "", "", "", \
150 "", "", "", "", "", "", "", "", \
153 /* Register numbers of various important registers.
154 Note that some of these values are "real" register numbers,
155 and correspond to the general registers of the machine,
156 and some are "phony" register numbers which are too large
157 to be actual register numbers as far as the user is concerned
158 but do serve to get the desired values when passed to read_register. */
160 #define ZERO_REGNUM 0 /* read-only register, always 0 */
161 #define V0_REGNUM 2 /* Function integer return value */
162 #define A0_REGNUM 4 /* Loc of first arg during a subr call */
163 #define SP_REGNUM 29 /* Contains address of top of stack */
164 #define RA_REGNUM 31 /* Contains return address value */
165 #define PS_REGNUM 32 /* Contains processor status */
166 #define HI_REGNUM 34 /* Multiple/divide temp */
167 #define LO_REGNUM 33 /* ... */
168 #define BADVADDR_REGNUM 35 /* bad vaddr for addressing exception */
169 #define CAUSE_REGNUM 36 /* describes last exception */
170 #define PC_REGNUM 37 /* Contains program counter */
171 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */
172 #define FCRCS_REGNUM 70 /* FP control/status */
173 #define FCRIR_REGNUM 71 /* FP implementation/revision */
174 #define FP_REGNUM 72 /* Pseudo register that contains true address of executing stack frame */
175 #define UNUSED_REGNUM 73 /* Never used, FIXME */
176 #define FIRST_EMBED_REGNUM 74 /* First CP0 register for embedded use */
177 #define PRID_REGNUM 89 /* Processor ID */
178 #define LAST_EMBED_REGNUM 89 /* Last one */
180 /* Define DO_REGISTERS_INFO() to do machine-specific formatting
181 of register dumps. */
183 #define DO_REGISTERS_INFO(_regnum, fp) mips_do_registers_info(_regnum, fp)
184 extern void mips_do_registers_info
PARAMS ((int, int));
186 /* Total amount of space needed to store our copies of the machine's
187 register state, the array `registers'. */
189 #define REGISTER_BYTES (NUM_REGS*MIPS_REGSIZE)
191 /* Index within `registers' of the first byte of the space for
194 #define REGISTER_BYTE(N) ((N) * MIPS_REGSIZE)
196 /* Number of bytes of storage in the actual machine representation
197 for register N. On mips, all regs are the same size. */
199 #define REGISTER_RAW_SIZE(N) MIPS_REGSIZE
201 /* Number of bytes of storage in the program's representation
202 for register N. On mips, all regs are the same size. */
204 #define REGISTER_VIRTUAL_SIZE(N) MIPS_REGSIZE
206 /* Largest value REGISTER_RAW_SIZE can have. */
208 #define MAX_REGISTER_RAW_SIZE 8
210 /* Largest value REGISTER_VIRTUAL_SIZE can have. */
212 #define MAX_REGISTER_VIRTUAL_SIZE 8
214 /* Return the GDB type object for the "standard" data type
215 of data in register N. */
217 #ifndef REGISTER_VIRTUAL_TYPE
218 #define REGISTER_VIRTUAL_TYPE(N) \
219 (((N) >= FP0_REGNUM && (N) < FP0_REGNUM+32) \
220 ? builtin_type_float : builtin_type_int)
223 #if HOST_BYTE_ORDER == BIG_ENDIAN
224 /* All mips targets store doubles in a register pair with the least
225 significant register in the lower numbered register.
226 If the host is big endian, double register values need conversion between
227 memory and register formats. */
229 #define REGISTER_CONVERT_TO_TYPE(n, type, buffer) \
230 do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
231 TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
233 memcpy (__temp, ((char *)(buffer))+4, 4); \
234 memcpy (((char *)(buffer))+4, (buffer), 4); \
235 memcpy (((char *)(buffer)), __temp, 4); }} while (0)
237 #define REGISTER_CONVERT_FROM_TYPE(n, type, buffer) \
238 do {if ((n) >= FP0_REGNUM && (n) < FP0_REGNUM + 32 && \
239 TYPE_CODE(type) == TYPE_CODE_FLT && TYPE_LENGTH(type) == 8) { \
241 memcpy (__temp, ((char *)(buffer))+4, 4); \
242 memcpy (((char *)(buffer))+4, (buffer), 4); \
243 memcpy (((char *)(buffer)), __temp, 4); }} while (0)
246 /* Store the address of the place in which to copy the structure the
247 subroutine will return. Handled by mips_push_arguments. */
249 #define STORE_STRUCT_RETURN(addr, sp) /**/
251 /* Extract from an array REGBUF containing the (raw) register state
252 a function return value of type TYPE, and copy that, in virtual format,
253 into VALBUF. XXX floats */
255 #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
256 mips_extract_return_value(TYPE, REGBUF, VALBUF)
258 mips_extract_return_value
PARAMS ((struct type
*, char [], char *));
260 /* Write into appropriate registers a function return value
261 of type TYPE, given in virtual format. */
263 #define STORE_RETURN_VALUE(TYPE,VALBUF) \
264 mips_store_return_value(TYPE, VALBUF)
265 extern void mips_store_return_value
PARAMS ((struct type
*, char *));
267 /* Extract from an array REGBUF containing the (raw) register state
268 the address in which a function should return its structure value,
269 as a CORE_ADDR (or an expression that can be used as one). */
270 /* The address is passed in a0 upon entry to the function, but when
271 the function exits, the compiler has copied the value to v0. This
272 convention is specified by the System V ABI, so I think we can rely
275 #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \
276 (extract_address (REGBUF + REGISTER_BYTE (V0_REGNUM), \
277 REGISTER_RAW_SIZE (V0_REGNUM)))
279 /* Structures are returned by ref in extra arg0 */
280 #define USE_STRUCT_CONVENTION(gcc_p, type) 1
283 /* Describe the pointer in each stack frame to the previous stack frame
286 /* FRAME_CHAIN takes a frame's nominal address
287 and produces the frame's chain-pointer. */
289 #define FRAME_CHAIN(thisframe) (CORE_ADDR) mips_frame_chain (thisframe)
290 extern CORE_ADDR mips_frame_chain
PARAMS ((struct frame_info
*));
292 /* Define other aspects of the stack frame. */
295 /* A macro that tells us whether the function invocation represented
296 by FI does not have a frame on the stack associated with it. If it
297 does not, FRAMELESS is set to 1, else 0. */
298 /* We handle this differently for mips, and maybe we should not */
300 #define FRAMELESS_FUNCTION_INVOCATION(FI, FRAMELESS) {(FRAMELESS) = 0;}
304 #define FRAME_SAVED_PC(FRAME) (mips_frame_saved_pc(FRAME))
305 extern int mips_frame_saved_pc
PARAMS ((struct frame_info
*));
307 #define FRAME_ARGS_ADDRESS(fi) (fi)->frame
309 #define FRAME_LOCALS_ADDRESS(fi) (fi)->frame
311 /* Return number of args passed to a frame.
312 Can return -1, meaning no way to tell. */
314 #define FRAME_NUM_ARGS(num, fi) (num = mips_frame_num_args(fi))
315 extern int mips_frame_num_args
PARAMS ((struct frame_info
*));
317 /* Return number of bytes at start of arglist that are not really args. */
319 #define FRAME_ARGS_SKIP 0
321 /* Put here the code to store, into a struct frame_saved_regs,
322 the addresses of the saved registers of frame described by FRAME_INFO.
323 This includes special registers such as pc and fp saved in special
324 ways in the stack frame. sp is even more special:
325 the address we return for it IS the sp for the next frame. */
327 #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \
329 if ((frame_info)->saved_regs == NULL) \
330 mips_find_saved_regs (frame_info); \
331 (frame_saved_regs) = *(frame_info)->saved_regs; \
332 (frame_saved_regs).regs[SP_REGNUM] = (frame_info)->frame; \
334 extern void mips_find_saved_regs
PARAMS ((struct frame_info
*));
337 /* Things needed for making the inferior call functions. */
339 /* Stack has strict alignment. However, use PUSH_ARGUMENTS
340 to take care of it. */
341 /*#define STACK_ALIGN(addr) (((addr)+3)&~3)*/
343 #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \
344 sp = mips_push_arguments(nargs, args, sp, struct_return, struct_addr)
346 mips_push_arguments
PARAMS ((int, struct value
**, CORE_ADDR
, int, CORE_ADDR
));
348 /* Push an empty stack frame, to record the current PC, etc. */
350 #define PUSH_DUMMY_FRAME mips_push_dummy_frame()
351 extern void mips_push_dummy_frame
PARAMS ((void));
353 /* Discard from the stack the innermost frame, restoring all registers. */
355 #define POP_FRAME mips_pop_frame()
356 extern void mips_pop_frame
PARAMS ((void));
358 #define MK_OP(op,rs,rt,offset) (((op)<<26)|((rs)<<21)|((rt)<<16)|(offset))
360 #define OP_LDFPR 061 /* lwc1 */
363 #define OP_LDGPR 043 /* lw */
365 #define CALL_DUMMY_SIZE (16*4)
367 #define CALL_DUMMY {\
368 MK_OP(0,RA_REGNUM,0,8), /* jr $ra # Fake ABOUT_TO_RETURN ...*/\
369 0, /* nop # ... to stop raw backtrace*/\
370 0x27bd0000, /* addu sp,?0 # Pseudo prologue */\
371 /* Start here; reload FP regs, then GP regs: */\
372 MK_OP(OP_LDFPR,SP_REGNUM,12,0 ), /* l[wd]c1 $f12,0(sp) */\
373 MK_OP(OP_LDFPR,SP_REGNUM,13, MIPS_REGSIZE), /* l[wd]c1 $f13,{4,8}(sp) */\
374 MK_OP(OP_LDFPR,SP_REGNUM,14,2*MIPS_REGSIZE), /* l[wd]c1 $f14,{8,16}(sp) */\
375 MK_OP(OP_LDFPR,SP_REGNUM,15,3*MIPS_REGSIZE), /* l[wd]c1 $f15,{12,24}(sp) */\
376 MK_OP(OP_LDGPR,SP_REGNUM, 4,0 ), /* l[wd] $r4,0(sp) */\
377 MK_OP(OP_LDGPR,SP_REGNUM, 5, MIPS_REGSIZE), /* l[wd] $r5,{4,8}(sp) */\
378 MK_OP(OP_LDGPR,SP_REGNUM, 6,2*MIPS_REGSIZE), /* l[wd] $r6,{8,16}(sp) */\
379 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
380 (017<<26)| (Dest_Reg << 16), /* lui $r31,<target upper 16 bits>*/\
381 MK_OP(13,Dest_Reg,Dest_Reg,0), /* ori $r31,$r31,<lower 16 bits>*/ \
382 (Dest_Reg<<21) | (31<<11) | 9, /* jalr $r31 */\
383 MK_OP(OP_LDGPR,SP_REGNUM, 7,3*MIPS_REGSIZE), /* l[wd] $r7,{12,24}(sp) */\
387 #define CALL_DUMMY_START_OFFSET 12
389 #define CALL_DUMMY_BREAKPOINT_OFFSET (CALL_DUMMY_START_OFFSET + (12 * 4))
391 /* Insert the specified number of args and function address
392 into a call sequence of the above form stored at DUMMYNAME. */
394 /* For big endian mips machines we need to switch the order of the
395 words with a floating-point value (it was already coerced to a double
396 by mips_push_arguments). */
397 #define FIX_CALL_DUMMY(dummyname, start_sp, fun, nargs, args, rettype, gcc_p) \
400 store_unsigned_integer \
401 (dummyname + 11 * 4, 4, \
402 (extract_unsigned_integer (dummyname + 11 * 4, 4) \
403 | (((fun) >> 16) & 0xffff))); \
404 store_unsigned_integer \
405 (dummyname + 12 * 4, 4, \
406 (extract_unsigned_integer (dummyname + 12 * 4, 4) \
407 | ((fun) & 0xffff))); \
408 if (mips_fpu == MIPS_FPU_NONE) \
410 store_unsigned_integer (dummyname + 3 * 4, 4, \
411 (unsigned LONGEST) 0); \
412 store_unsigned_integer (dummyname + 4 * 4, 4, \
413 (unsigned LONGEST) 0); \
414 store_unsigned_integer (dummyname + 5 * 4, 4, \
415 (unsigned LONGEST) 0); \
416 store_unsigned_integer (dummyname + 6 * 4, 4, \
417 (unsigned LONGEST) 0); \
419 else if (mips_fpu == MIPS_FPU_SINGLE) \
421 /* This isn't right. mips_push_arguments will call \
422 value_arg_coerce, which will convert all float arguments \
423 to doubles. If the function prototype is float, though, \
424 it will be expecting a float argument in a float \
426 store_unsigned_integer (dummyname + 4 * 4, 4, \
427 (unsigned LONGEST) 0); \
428 store_unsigned_integer (dummyname + 6 * 4, 4, \
429 (unsigned LONGEST) 0); \
431 else if (TARGET_BYTE_ORDER == BIG_ENDIAN \
432 && ! GDB_TARGET_IS_MIPS64) \
435 && TYPE_CODE (VALUE_TYPE (args[0])) == TYPE_CODE_FLT) \
437 if (TYPE_LENGTH (VALUE_TYPE (args[0])) > 8) \
438 error ("floating point value too large to pass to function");\
439 store_unsigned_integer \
440 (dummyname + 3 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 12, 4));\
441 store_unsigned_integer \
442 (dummyname + 4 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 13, 0));\
445 && TYPE_CODE (VALUE_TYPE (args[1])) == TYPE_CODE_FLT) \
447 if (TYPE_LENGTH (VALUE_TYPE (args[1])) > 8) \
448 error ("floating point value too large to pass to function");\
449 store_unsigned_integer \
450 (dummyname + 5 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 14, 12));\
451 store_unsigned_integer \
452 (dummyname + 6 * 4, 4, MK_OP (OP_LDFPR, SP_REGNUM, 15, 8));\
458 /* There's a mess in stack frame creation. See comments in blockframe.c
459 near reference to INIT_FRAME_PC_FIRST. */
461 #define INIT_FRAME_PC(fromleaf, prev) /* nada */
463 #define INIT_FRAME_PC_FIRST(fromleaf, prev) \
464 (prev)->pc = ((fromleaf) ? SAVED_PC_AFTER_CALL ((prev)->next) : \
465 (prev)->next ? FRAME_SAVED_PC ((prev)->next) : read_pc ());
467 /* Special symbol found in blocks associated with routines. We can hang
468 mips_extra_func_info_t's off of this. */
470 #define MIPS_EFI_SYMBOL_NAME "__GDB_EFI_INFO__"
471 extern void ecoff_relocate_efi
PARAMS ((struct symbol
*, CORE_ADDR
));
473 /* Specific information about a procedure.
474 This overlays the MIPS's PDR records,
475 mipsread.c (ab)uses this to save memory */
477 typedef struct mips_extra_func_info
{
478 long numargs
; /* number of args to procedure (was iopt) */
479 PDR pdr
; /* Procedure descriptor record */
480 } *mips_extra_func_info_t
;
482 #define EXTRA_FRAME_INFO \
483 mips_extra_func_info_t proc_desc; \
485 struct frame_saved_regs *saved_regs;
487 #define INIT_EXTRA_FRAME_INFO(fromleaf, fci) init_extra_frame_info(fci)
488 extern void init_extra_frame_info
PARAMS ((struct frame_info
*));
490 #define PRINT_EXTRA_FRAME_INFO(fi) \
492 if (fi && fi->proc_desc && fi->proc_desc->pdr.framereg < NUM_REGS) \
493 printf_filtered (" frame pointer is at %s+%d\n", \
494 reg_names[fi->proc_desc->pdr.framereg], \
495 fi->proc_desc->pdr.frameoffset); \
498 /* It takes two values to specify a frame on the MIPS.
500 In fact, the *PC* is the primary value that sets up a frame. The
501 PC is looked up to see what function it's in; symbol information
502 from that function tells us which register is the frame pointer
503 base, and what offset from there is the "virtual frame pointer".
504 (This is usually an offset from SP.) On most non-MIPS machines,
505 the primary value is the SP, and the PC, if needed, disambiguates
506 multiple functions with the same SP. But on the MIPS we can't do
507 that since the PC is not stored in the same part of the frame every
508 time. This does not seem to be a very clever way to set up frames,
509 but there is nothing we can do about that). */
511 #define SETUP_ARBITRARY_FRAME(argc, argv) setup_arbitrary_frame (argc, argv)
512 extern struct frame_info
*setup_arbitrary_frame
PARAMS ((int, CORE_ADDR
*));
514 /* Convert a dbx stab register number (from `r' declaration) to a gdb REGNUM */
516 #define STAB_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-38)
518 /* Convert a ecoff register number to a gdb REGNUM */
520 #define ECOFF_REG_TO_REGNUM(num) ((num) < 32 ? (num) : (num)+FP0_REGNUM-32)
522 /* If the current gcc for for this target does not produce correct debugging
523 information for float parameters, both prototyped and unprototyped, then
524 define this macro. This forces gdb to always assume that floats are
525 passed as doubles and then converted in the callee.
527 For the mips chip, it appears that the debug info marks the parameters as
528 floats regardless of whether the function is prototyped, but the actual
529 values are passed as doubles for the non-prototyped case and floats for
530 the prototyped case. Thus we choose to make the non-prototyped case work
531 for C and break the prototyped case, since the non-prototyped case is
532 probably much more common. (FIXME). */
534 #define COERCE_FLOAT_TO_DOUBLE (current_language -> la_language == language_c)
536 /* These are defined in mdebugread.c and are used in mips-tdep.c */
537 extern CORE_ADDR sigtramp_address
, sigtramp_end
;
538 extern void fixup_sigtramp
PARAMS ((void));