1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2021 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->regnum
;
234 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
236 return mips_regnum (gdbarch
)->fp0
+ 12;
239 /* Return 1 if REGNUM refers to a floating-point general register, raw
240 or cooked. Otherwise return 0. */
243 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
245 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
247 return (rawnum
>= mips_regnum (gdbarch
)->fp0
248 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
251 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
253 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
255 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
256 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
258 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
259 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
261 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
263 /* Return the MIPS ABI associated with GDBARCH. */
265 mips_abi (struct gdbarch
*gdbarch
)
267 return gdbarch_tdep (gdbarch
)->mips_abi
;
271 mips_isa_regsize (struct gdbarch
*gdbarch
)
273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
275 /* If we know how big the registers are, use that size. */
276 if (tdep
->register_size_valid_p
)
277 return tdep
->register_size
;
279 /* Fall back to the previous behavior. */
280 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
281 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
284 /* Max saved register size. */
285 #define MAX_MIPS_ABI_REGSIZE 8
287 /* Return the currently configured (or set) saved register size. */
290 mips_abi_regsize (struct gdbarch
*gdbarch
)
292 switch (mips_abi (gdbarch
))
294 case MIPS_ABI_EABI32
:
300 case MIPS_ABI_EABI64
:
302 case MIPS_ABI_UNKNOWN
:
305 internal_error (__FILE__
, __LINE__
, _("bad switch"));
309 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
310 are some functions to handle addresses associated with compressed
311 code including but not limited to testing, setting, or clearing
312 bit 0 of such addresses. */
314 /* Return one iff compressed code is the MIPS16 instruction set. */
317 is_mips16_isa (struct gdbarch
*gdbarch
)
319 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
322 /* Return one iff compressed code is the microMIPS instruction set. */
325 is_micromips_isa (struct gdbarch
*gdbarch
)
327 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
330 /* Return one iff ADDR denotes compressed code. */
333 is_compact_addr (CORE_ADDR addr
)
338 /* Return one iff ADDR denotes standard ISA code. */
341 is_mips_addr (CORE_ADDR addr
)
343 return !is_compact_addr (addr
);
346 /* Return one iff ADDR denotes MIPS16 code. */
349 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
351 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
354 /* Return one iff ADDR denotes microMIPS code. */
357 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
359 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
362 /* Strip the ISA (compression) bit off from ADDR. */
365 unmake_compact_addr (CORE_ADDR addr
)
367 return ((addr
) & ~(CORE_ADDR
) 1);
370 /* Add the ISA (compression) bit to ADDR. */
373 make_compact_addr (CORE_ADDR addr
)
375 return ((addr
) | (CORE_ADDR
) 1);
378 /* Extern version of unmake_compact_addr; we use a separate function
379 so that unmake_compact_addr can be inlined throughout this file. */
382 mips_unmake_compact_addr (CORE_ADDR addr
)
384 return unmake_compact_addr (addr
);
387 /* Functions for setting and testing a bit in a minimal symbol that
388 marks it as MIPS16 or microMIPS function. The MSB of the minimal
389 symbol's "info" field is used for this purpose.
391 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
392 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
393 one of the "special" bits in a minimal symbol to mark it accordingly.
394 The test checks an ELF-private flag that is valid for true function
395 symbols only; for synthetic symbols such as for PLT stubs that have
396 no ELF-private part at all the MIPS BFD backend arranges for this
397 information to be carried in the asymbol's udata field instead.
399 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
400 in a minimal symbol. */
403 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
405 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
406 unsigned char st_other
;
408 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
409 st_other
= elfsym
->internal_elf_sym
.st_other
;
410 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
411 st_other
= sym
->udata
.i
;
415 if (ELF_ST_IS_MICROMIPS (st_other
))
417 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
418 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
420 else if (ELF_ST_IS_MIPS16 (st_other
))
422 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
423 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
427 /* Return one iff MSYM refers to standard ISA code. */
430 msymbol_is_mips (struct minimal_symbol
*msym
)
432 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
433 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
436 /* Return one iff MSYM refers to MIPS16 code. */
439 msymbol_is_mips16 (struct minimal_symbol
*msym
)
441 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
444 /* Return one iff MSYM refers to microMIPS code. */
447 msymbol_is_micromips (struct minimal_symbol
*msym
)
449 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
452 /* Set the ISA bit in the main symbol too, complementing the corresponding
453 minimal symbol setting and reflecting the run-time value of the symbol.
454 The need for comes from the ISA bit having been cleared as code in
455 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
456 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
457 of symbols referring to compressed code different in GDB to the values
458 used by actual code. That in turn makes them evaluate incorrectly in
459 expressions, producing results different to what the same expressions
460 yield when compiled into the program being debugged. */
463 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
465 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
467 /* We are in symbol reading so it is OK to cast away constness. */
468 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
469 CORE_ADDR compact_block_start
;
470 struct bound_minimal_symbol msym
;
472 compact_block_start
= BLOCK_START (block
) | 1;
473 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
474 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
476 BLOCK_START (block
) = compact_block_start
;
481 /* XFER a value from the big/little/left end of the register.
482 Depending on the size of the value it might occupy the entire
483 register or just part of it. Make an allowance for this, aligning
484 things accordingly. */
487 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
488 int reg_num
, int length
,
489 enum bfd_endian endian
, gdb_byte
*in
,
490 const gdb_byte
*out
, int buf_offset
)
494 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
495 /* Need to transfer the left or right part of the register, based on
496 the targets byte order. */
500 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
502 case BFD_ENDIAN_LITTLE
:
505 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
509 internal_error (__FILE__
, __LINE__
, _("bad switch"));
512 fprintf_unfiltered (gdb_stderr
,
513 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
514 reg_num
, reg_offset
, buf_offset
, length
);
515 if (mips_debug
&& out
!= NULL
)
518 fprintf_unfiltered (gdb_stdlog
, "out ");
519 for (i
= 0; i
< length
; i
++)
520 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
523 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
525 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
526 if (mips_debug
&& in
!= NULL
)
529 fprintf_unfiltered (gdb_stdlog
, "in ");
530 for (i
= 0; i
< length
; i
++)
531 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
534 fprintf_unfiltered (gdb_stdlog
, "\n");
537 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
538 compatiblity mode. A return value of 1 means that we have
539 physical 64-bit registers, but should treat them as 32-bit registers. */
542 mips2_fp_compat (struct frame_info
*frame
)
544 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
545 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
547 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
551 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
552 in all the places we deal with FP registers. PR gdb/413. */
553 /* Otherwise check the FR bit in the status register - it controls
554 the FP compatiblity mode. If it is clear we are in compatibility
556 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
563 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
565 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
567 /* The list of available "set mips " and "show mips " commands. */
569 static struct cmd_list_element
*setmipscmdlist
= NULL
;
570 static struct cmd_list_element
*showmipscmdlist
= NULL
;
572 /* Integer registers 0 thru 31 are handled explicitly by
573 mips_register_name(). Processor specific registers 32 and above
574 are listed in the following tables. */
577 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
581 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
582 "sr", "lo", "hi", "bad", "cause", "pc",
583 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
584 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
585 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
586 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
590 /* Names of tx39 registers. */
592 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
593 "sr", "lo", "hi", "bad", "cause", "pc",
594 "", "", "", "", "", "", "", "",
595 "", "", "", "", "", "", "", "",
596 "", "", "", "", "", "", "", "",
597 "", "", "", "", "", "", "", "",
599 "", "", "", "", "", "", "", "",
600 "", "", "config", "cache", "debug", "depc", "epc",
603 /* Names of registers with Linux kernels. */
604 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
605 "sr", "lo", "hi", "bad", "cause", "pc",
606 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
607 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
608 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
609 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
614 /* Return the name of the register corresponding to REGNO. */
616 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
618 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
619 /* GPR names for all ABIs other than n32/n64. */
620 static const char *mips_gpr_names
[] = {
621 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
622 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
623 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
624 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
627 /* GPR names for n32 and n64 ABIs. */
628 static const char *mips_n32_n64_gpr_names
[] = {
629 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
630 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
631 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
632 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
635 enum mips_abi abi
= mips_abi (gdbarch
);
637 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
638 but then don't make the raw register names visible. This (upper)
639 range of user visible register numbers are the pseudo-registers.
641 This approach was adopted accommodate the following scenario:
642 It is possible to debug a 64-bit device using a 32-bit
643 programming model. In such instances, the raw registers are
644 configured to be 64-bits wide, while the pseudo registers are
645 configured to be 32-bits wide. The registers that the user
646 sees - the pseudo registers - match the users expectations
647 given the programming model being used. */
648 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
649 if (regno
< gdbarch_num_regs (gdbarch
))
652 /* The MIPS integer registers are always mapped from 0 to 31. The
653 names of the registers (which reflects the conventions regarding
654 register use) vary depending on the ABI. */
655 if (0 <= rawnum
&& rawnum
< 32)
657 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
658 return mips_n32_n64_gpr_names
[rawnum
];
660 return mips_gpr_names
[rawnum
];
662 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
663 return tdesc_register_name (gdbarch
, rawnum
);
664 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
666 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
667 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
668 return tdep
->mips_processor_reg_names
[rawnum
- 32];
672 internal_error (__FILE__
, __LINE__
,
673 _("mips_register_name: bad register number %d"), rawnum
);
676 /* Return the groups that a MIPS register can be categorised into. */
679 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
680 struct reggroup
*reggroup
)
685 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
686 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
687 if (reggroup
== all_reggroup
)
689 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
690 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
691 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
692 (gdbarch), as not all architectures are multi-arch. */
693 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
694 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
695 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
697 if (reggroup
== float_reggroup
)
698 return float_p
&& pseudo
;
699 if (reggroup
== vector_reggroup
)
700 return vector_p
&& pseudo
;
701 if (reggroup
== general_reggroup
)
702 return (!vector_p
&& !float_p
) && pseudo
;
703 /* Save the pseudo registers. Need to make certain that any code
704 extracting register values from a saved register cache also uses
706 if (reggroup
== save_reggroup
)
707 return raw_p
&& pseudo
;
708 /* Restore the same pseudo register. */
709 if (reggroup
== restore_reggroup
)
710 return raw_p
&& pseudo
;
714 /* Return the groups that a MIPS register can be categorised into.
715 This version is only used if we have a target description which
716 describes real registers (and their groups). */
719 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
720 struct reggroup
*reggroup
)
722 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
723 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
726 /* Only save, restore, and display the pseudo registers. Need to
727 make certain that any code extracting register values from a
728 saved register cache also uses pseudo registers.
730 Note: saving and restoring the pseudo registers is slightly
731 strange; if we have 64 bits, we should save and restore all
732 64 bits. But this is hard and has little benefit. */
736 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
740 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
743 /* Map the symbol table registers which live in the range [1 *
744 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
745 registers. Take care of alignment and size problems. */
747 static enum register_status
748 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
749 int cookednum
, gdb_byte
*buf
)
751 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
752 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
753 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
754 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
755 return regcache
->raw_read (rawnum
, buf
);
756 else if (register_size (gdbarch
, rawnum
) >
757 register_size (gdbarch
, cookednum
))
759 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
760 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
763 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
765 enum register_status status
;
767 status
= regcache
->raw_read (rawnum
, ®val
);
768 if (status
== REG_VALID
)
769 store_signed_integer (buf
, 4, byte_order
, regval
);
774 internal_error (__FILE__
, __LINE__
, _("bad register size"));
778 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
779 struct regcache
*regcache
, int cookednum
,
782 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
783 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
784 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
785 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
786 regcache
->raw_write (rawnum
, buf
);
787 else if (register_size (gdbarch
, rawnum
) >
788 register_size (gdbarch
, cookednum
))
790 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
791 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
794 /* Sign extend the shortened version of the register prior
795 to placing it in the raw register. This is required for
796 some mips64 parts in order to avoid unpredictable behavior. */
797 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
798 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
799 regcache_raw_write_signed (regcache
, rawnum
, regval
);
803 internal_error (__FILE__
, __LINE__
, _("bad register size"));
807 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
808 struct agent_expr
*ax
, int reg
)
810 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
811 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
812 && reg
< 2 * gdbarch_num_regs (gdbarch
));
814 ax_reg_mask (ax
, rawnum
);
820 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
821 struct agent_expr
*ax
, int reg
)
823 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
824 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
825 && reg
< 2 * gdbarch_num_regs (gdbarch
));
826 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
830 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
832 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
833 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
836 ax_simple (ax
, aop_lsh
);
839 ax_simple (ax
, aop_rsh_signed
);
843 internal_error (__FILE__
, __LINE__
, _("bad register size"));
848 /* Table to translate 3-bit register field to actual register number. */
849 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
851 /* Heuristic_proc_start may hunt through the text section for a long
852 time across a 2400 baud serial line. Allows the user to limit this
855 static int heuristic_fence_post
= 0;
857 /* Number of bytes of storage in the actual machine representation for
858 register N. NOTE: This defines the pseudo register type so need to
859 rebuild the architecture vector. */
861 static bool mips64_transfers_32bit_regs_p
= false;
864 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
865 struct cmd_list_element
*c
)
867 struct gdbarch_info info
;
868 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
869 instead of relying on globals. Doing that would let generic code
870 handle the search for this specific architecture. */
871 if (!gdbarch_update_p (info
))
873 mips64_transfers_32bit_regs_p
= 0;
874 error (_("32-bit compatibility mode not supported"));
878 /* Convert to/from a register and the corresponding memory value. */
880 /* This predicate tests for the case of an 8 byte floating point
881 value that is being transferred to or from a pair of floating point
882 registers each of which are (or are considered to be) only 4 bytes
885 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
888 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
889 && register_size (gdbarch
, regnum
) == 4
890 && mips_float_register_p (gdbarch
, regnum
)
891 && type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
894 /* This predicate tests for the case of a value of less than 8
895 bytes in width that is being transfered to or from an 8 byte
896 general purpose register. */
898 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
901 int num_regs
= gdbarch_num_regs (gdbarch
);
903 return (register_size (gdbarch
, regnum
) == 8
904 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
905 && TYPE_LENGTH (type
) < 8);
909 mips_convert_register_p (struct gdbarch
*gdbarch
,
910 int regnum
, struct type
*type
)
912 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
913 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
917 mips_register_to_value (struct frame_info
*frame
, int regnum
,
918 struct type
*type
, gdb_byte
*to
,
919 int *optimizedp
, int *unavailablep
)
921 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
923 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
925 get_frame_register (frame
, regnum
+ 0, to
+ 4);
926 get_frame_register (frame
, regnum
+ 1, to
+ 0);
928 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
929 optimizedp
, unavailablep
))
932 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
933 optimizedp
, unavailablep
))
935 *optimizedp
= *unavailablep
= 0;
938 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
940 size_t len
= TYPE_LENGTH (type
);
943 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
944 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
945 optimizedp
, unavailablep
))
948 *optimizedp
= *unavailablep
= 0;
953 internal_error (__FILE__
, __LINE__
,
954 _("mips_register_to_value: unrecognized case"));
959 mips_value_to_register (struct frame_info
*frame
, int regnum
,
960 struct type
*type
, const gdb_byte
*from
)
962 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
964 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
966 put_frame_register (frame
, regnum
+ 0, from
+ 4);
967 put_frame_register (frame
, regnum
+ 1, from
+ 0);
969 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
972 size_t len
= TYPE_LENGTH (type
);
974 /* Sign extend values, irrespective of type, that are stored to
975 a 64-bit general purpose register. (32-bit unsigned values
976 are stored as signed quantities within a 64-bit register.
977 When performing an operation, in compiled code, that combines
978 a 32-bit unsigned value with a signed 64-bit value, a type
979 conversion is first performed that zeroes out the high 32 bits.) */
980 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
983 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
985 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
986 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
987 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
991 if (from
[len
-1] & 0x80)
992 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
994 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
995 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
996 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1001 internal_error (__FILE__
, __LINE__
,
1002 _("mips_value_to_register: unrecognized case"));
1006 /* Return the GDB type object for the "standard" data type of data in
1009 static struct type
*
1010 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1012 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1013 if (mips_float_register_p (gdbarch
, regnum
))
1015 /* The floating-point registers raw, or cooked, always match
1016 mips_isa_regsize(), and also map 1:1, byte for byte. */
1017 if (mips_isa_regsize (gdbarch
) == 4)
1018 return builtin_type (gdbarch
)->builtin_float
;
1020 return builtin_type (gdbarch
)->builtin_double
;
1022 else if (regnum
< gdbarch_num_regs (gdbarch
))
1024 /* The raw or ISA registers. These are all sized according to
1026 if (mips_isa_regsize (gdbarch
) == 4)
1027 return builtin_type (gdbarch
)->builtin_int32
;
1029 return builtin_type (gdbarch
)->builtin_int64
;
1033 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1035 /* The cooked or ABI registers. These are sized according to
1036 the ABI (with a few complications). */
1037 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1038 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1039 return builtin_type (gdbarch
)->builtin_int32
;
1040 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1041 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1042 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1043 /* The pseudo/cooked view of the embedded registers is always
1044 32-bit. The raw view is handled below. */
1045 return builtin_type (gdbarch
)->builtin_int32
;
1046 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1047 /* The target, while possibly using a 64-bit register buffer,
1048 is only transfering 32-bits of each integer register.
1049 Reflect this in the cooked/pseudo (ABI) register value. */
1050 return builtin_type (gdbarch
)->builtin_int32
;
1051 else if (mips_abi_regsize (gdbarch
) == 4)
1052 /* The ABI is restricted to 32-bit registers (the ISA could be
1054 return builtin_type (gdbarch
)->builtin_int32
;
1057 return builtin_type (gdbarch
)->builtin_int64
;
1061 /* Return the GDB type for the pseudo register REGNUM, which is the
1062 ABI-level view. This function is only called if there is a target
1063 description which includes registers, so we know precisely the
1064 types of hardware registers. */
1066 static struct type
*
1067 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1069 const int num_regs
= gdbarch_num_regs (gdbarch
);
1070 int rawnum
= regnum
% num_regs
;
1071 struct type
*rawtype
;
1073 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1075 /* Absent registers are still absent. */
1076 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1077 if (TYPE_LENGTH (rawtype
) == 0)
1080 /* Present the floating point registers however the hardware did;
1081 do not try to convert between FPU layouts. */
1082 if (mips_float_register_p (gdbarch
, rawnum
))
1085 /* Floating-point control registers are always 32-bit even though for
1086 backwards compatibility reasons 64-bit targets will transfer them
1087 as 64-bit quantities even if using XML descriptions. */
1088 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1089 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1090 return builtin_type (gdbarch
)->builtin_int32
;
1092 /* Use pointer types for registers if we can. For n32 we can not,
1093 since we do not have a 64-bit pointer type. */
1094 if (mips_abi_regsize (gdbarch
)
1095 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1097 if (rawnum
== MIPS_SP_REGNUM
1098 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1099 return builtin_type (gdbarch
)->builtin_data_ptr
;
1100 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1101 return builtin_type (gdbarch
)->builtin_func_ptr
;
1104 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1105 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1106 || rawnum
== mips_regnum (gdbarch
)->lo
1107 || rawnum
== mips_regnum (gdbarch
)->hi
1108 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1109 || rawnum
== mips_regnum (gdbarch
)->cause
1110 || rawnum
== mips_regnum (gdbarch
)->pc
1111 || (mips_regnum (gdbarch
)->dspacc
!= -1
1112 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1113 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1114 return builtin_type (gdbarch
)->builtin_int32
;
1116 /* The pseudo/cooked view of embedded registers is always
1117 32-bit, even if the target transfers 64-bit values for them.
1118 New targets relying on XML descriptions should only transfer
1119 the necessary 32 bits, but older versions of GDB expected 64,
1120 so allow the target to provide 64 bits without interfering
1121 with the displayed type. */
1122 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1123 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1124 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1125 return builtin_type (gdbarch
)->builtin_int32
;
1127 /* For all other registers, pass through the hardware type. */
1131 /* Should the upper word of 64-bit addresses be zeroed? */
1132 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1135 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1137 switch (mask_address_var
)
1139 case AUTO_BOOLEAN_TRUE
:
1141 case AUTO_BOOLEAN_FALSE
:
1144 case AUTO_BOOLEAN_AUTO
:
1145 return tdep
->default_mask_address_p
;
1147 internal_error (__FILE__
, __LINE__
,
1148 _("mips_mask_address_p: bad switch"));
1154 show_mask_address (struct ui_file
*file
, int from_tty
,
1155 struct cmd_list_element
*c
, const char *value
)
1157 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1159 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1160 switch (mask_address_var
)
1162 case AUTO_BOOLEAN_TRUE
:
1163 printf_filtered ("The 32 bit mips address mask is enabled\n");
1165 case AUTO_BOOLEAN_FALSE
:
1166 printf_filtered ("The 32 bit mips address mask is disabled\n");
1168 case AUTO_BOOLEAN_AUTO
:
1170 ("The 32 bit address mask is set automatically. Currently %s\n",
1171 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1174 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1179 /* Tell if the program counter value in MEMADDR is in a standard ISA
1183 mips_pc_is_mips (CORE_ADDR memaddr
)
1185 struct bound_minimal_symbol sym
;
1187 /* Flags indicating that this is a MIPS16 or microMIPS function is
1188 stored by elfread.c in the high bit of the info field. Use this
1189 to decide if the function is standard MIPS. Otherwise if bit 0
1190 of the address is clear, then this is a standard MIPS function. */
1191 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1193 return msymbol_is_mips (sym
.minsym
);
1195 return is_mips_addr (memaddr
);
1198 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1201 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1203 struct bound_minimal_symbol sym
;
1205 /* A flag indicating that this is a MIPS16 function is stored by
1206 elfread.c in the high bit of the info field. Use this to decide
1207 if the function is MIPS16. Otherwise if bit 0 of the address is
1208 set, then ELF file flags will tell if this is a MIPS16 function. */
1209 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1211 return msymbol_is_mips16 (sym
.minsym
);
1213 return is_mips16_addr (gdbarch
, memaddr
);
1216 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1219 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1221 struct bound_minimal_symbol sym
;
1223 /* A flag indicating that this is a microMIPS function is stored by
1224 elfread.c in the high bit of the info field. Use this to decide
1225 if the function is microMIPS. Otherwise if bit 0 of the address
1226 is set, then ELF file flags will tell if this is a microMIPS
1228 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1230 return msymbol_is_micromips (sym
.minsym
);
1232 return is_micromips_addr (gdbarch
, memaddr
);
1235 /* Tell the ISA type of the function the program counter value in MEMADDR
1238 static enum mips_isa
1239 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1241 struct bound_minimal_symbol sym
;
1243 /* A flag indicating that this is a MIPS16 or a microMIPS function
1244 is stored by elfread.c in the high bit of the info field. Use
1245 this to decide if the function is MIPS16 or microMIPS or normal
1246 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1247 flags will tell if this is a MIPS16 or a microMIPS function. */
1248 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1251 if (msymbol_is_micromips (sym
.minsym
))
1252 return ISA_MICROMIPS
;
1253 else if (msymbol_is_mips16 (sym
.minsym
))
1260 if (is_mips_addr (memaddr
))
1262 else if (is_micromips_addr (gdbarch
, memaddr
))
1263 return ISA_MICROMIPS
;
1269 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1270 The need for comes from the ISA bit having been cleared, making
1271 addresses in FDE, range records, etc. referring to compressed code
1272 different to those in line information, the symbol table and finally
1273 the PC register. That in turn confuses many operations. */
1276 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1278 pc
= unmake_compact_addr (pc
);
1279 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1282 /* Recalculate the line record requested so that the resulting PC has
1283 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1284 this adjustment comes from some records associated with compressed
1285 code having the ISA bit cleared, most notably at function prologue
1286 ends. The ISA bit is in this context retrieved from the minimal
1287 symbol covering the address requested, which in turn has been
1288 constructed from the binary's symbol table rather than DWARF-2
1289 information. The correct setting of the ISA bit is required for
1290 breakpoint addresses to correctly match against the stop PC.
1292 As line entries can specify relative address adjustments we need to
1293 keep track of the absolute value of the last line address recorded
1294 in line information, so that we can calculate the actual address to
1295 apply the ISA bit adjustment to. We use PC for this tracking and
1296 keep the original address there.
1298 As such relative address adjustments can be odd within compressed
1299 code we need to keep track of the last line address with the ISA
1300 bit adjustment applied too, as the original address may or may not
1301 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1302 the adjusted address there.
1304 For relative address adjustments we then use these variables to
1305 calculate the address intended by line information, which will be
1306 PC-relative, and return an updated adjustment carrying ISA bit
1307 information, which will be ADJ_PC-relative. For absolute address
1308 adjustments we just return the same address that we store in ADJ_PC
1311 As the first line entry can be relative to an implied address value
1312 of 0 we need to have the initial address set up that we store in PC
1313 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1314 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1317 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1319 static CORE_ADDR adj_pc
;
1320 static CORE_ADDR pc
;
1323 pc
= rel
? pc
+ addr
: addr
;
1324 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1325 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1330 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1332 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1333 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1334 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1335 static const char mips_str_call_stub
[] = "__call_stub_";
1336 static const char mips_str_fn_stub
[] = "__fn_stub_";
1338 /* This is used as a PIC thunk prefix. */
1340 static const char mips_str_pic
[] = ".pic.";
1342 /* Return non-zero if the PC is inside a call thunk (aka stub or
1343 trampoline) that should be treated as a temporary frame. */
1346 mips_in_frame_stub (CORE_ADDR pc
)
1348 CORE_ADDR start_addr
;
1351 /* Find the starting address of the function containing the PC. */
1352 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1355 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1356 if (startswith (name
, mips_str_mips16_call_stub
))
1358 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1359 if (startswith (name
, mips_str_call_stub
))
1361 /* If the PC is in __fn_stub_*, this is a call stub. */
1362 if (startswith (name
, mips_str_fn_stub
))
1365 return 0; /* Not a stub. */
1368 /* MIPS believes that the PC has a sign extended value. Perhaps the
1369 all registers should be sign extended for simplicity? */
1372 mips_read_pc (readable_regcache
*regcache
)
1374 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1377 regcache
->cooked_read (regnum
, &pc
);
1382 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1386 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1387 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1388 intermediate frames. In this case we can get the caller's address
1389 from $ra, or if $ra contains an address within a thunk as well, then
1390 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1391 and thus the caller's address is in $s2. */
1392 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1394 pc
= frame_unwind_register_signed
1395 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1396 if (mips_in_frame_stub (pc
))
1397 pc
= frame_unwind_register_signed
1398 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1404 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1406 return frame_unwind_register_signed
1407 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1410 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1411 dummy frame. The frame ID's base needs to match the TOS value
1412 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1415 static struct frame_id
1416 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1418 return frame_id_build
1419 (get_frame_register_signed (this_frame
,
1420 gdbarch_num_regs (gdbarch
)
1422 get_frame_pc (this_frame
));
1425 /* Implement the "write_pc" gdbarch method. */
1428 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1430 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1432 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1435 /* Fetch and return instruction from the specified location. Handle
1436 MIPS16/microMIPS as appropriate. */
1439 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1440 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1442 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1443 gdb_byte buf
[MIPS_INSN32_SIZE
];
1451 instlen
= MIPS_INSN16_SIZE
;
1452 addr
= unmake_compact_addr (addr
);
1455 instlen
= MIPS_INSN32_SIZE
;
1458 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1461 err
= target_read_memory (addr
, buf
, instlen
);
1467 memory_error (TARGET_XFER_E_IO
, addr
);
1470 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1473 /* These are the fields of 32 bit mips instructions. */
1474 #define mips32_op(x) (x >> 26)
1475 #define itype_op(x) (x >> 26)
1476 #define itype_rs(x) ((x >> 21) & 0x1f)
1477 #define itype_rt(x) ((x >> 16) & 0x1f)
1478 #define itype_immediate(x) (x & 0xffff)
1480 #define jtype_op(x) (x >> 26)
1481 #define jtype_target(x) (x & 0x03ffffff)
1483 #define rtype_op(x) (x >> 26)
1484 #define rtype_rs(x) ((x >> 21) & 0x1f)
1485 #define rtype_rt(x) ((x >> 16) & 0x1f)
1486 #define rtype_rd(x) ((x >> 11) & 0x1f)
1487 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1488 #define rtype_funct(x) (x & 0x3f)
1490 /* MicroMIPS instruction fields. */
1491 #define micromips_op(x) ((x) >> 10)
1493 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1494 bit and the size respectively of the field extracted. */
1495 #define b0s4_imm(x) ((x) & 0xf)
1496 #define b0s5_imm(x) ((x) & 0x1f)
1497 #define b0s5_reg(x) ((x) & 0x1f)
1498 #define b0s7_imm(x) ((x) & 0x7f)
1499 #define b0s10_imm(x) ((x) & 0x3ff)
1500 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1501 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1502 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1503 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1504 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1505 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1506 #define b6s4_op(x) (((x) >> 6) & 0xf)
1507 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1509 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1510 respectively of the field extracted. */
1511 #define b0s6_op(x) ((x) & 0x3f)
1512 #define b0s11_op(x) ((x) & 0x7ff)
1513 #define b0s12_imm(x) ((x) & 0xfff)
1514 #define b0s16_imm(x) ((x) & 0xffff)
1515 #define b0s26_imm(x) ((x) & 0x3ffffff)
1516 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1517 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1518 #define b12s4_op(x) (((x) >> 12) & 0xf)
1520 /* Return the size in bytes of the instruction INSN encoded in the ISA
1524 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1529 if ((micromips_op (insn
) & 0x4) == 0x4
1530 || (micromips_op (insn
) & 0x7) == 0x0)
1531 return 2 * MIPS_INSN16_SIZE
;
1533 return MIPS_INSN16_SIZE
;
1535 if ((insn
& 0xf800) == 0xf000)
1536 return 2 * MIPS_INSN16_SIZE
;
1538 return MIPS_INSN16_SIZE
;
1540 return MIPS_INSN32_SIZE
;
1542 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1546 mips32_relative_offset (ULONGEST inst
)
1548 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1551 /* Determine the address of the next instruction executed after the INST
1552 floating condition branch instruction at PC. COUNT specifies the
1553 number of the floating condition bits tested by the branch. */
1556 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1557 ULONGEST inst
, CORE_ADDR pc
, int count
)
1559 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1560 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1561 int tf
= itype_rt (inst
) & 1;
1562 int mask
= (1 << count
) - 1;
1567 /* No way to handle; it'll most likely trap anyway. */
1570 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1571 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1573 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1574 pc
+= mips32_relative_offset (inst
);
1581 /* Return nonzero if the gdbarch is an Octeon series. */
1584 is_octeon (struct gdbarch
*gdbarch
)
1586 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1588 return (info
->mach
== bfd_mach_mips_octeon
1589 || info
->mach
== bfd_mach_mips_octeonp
1590 || info
->mach
== bfd_mach_mips_octeon2
);
1593 /* Return true if the OP represents the Octeon's BBIT instruction. */
1596 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1598 if (!is_octeon (gdbarch
))
1600 /* BBIT0 is encoded as LWC2: 110 010. */
1601 /* BBIT032 is encoded as LDC2: 110 110. */
1602 /* BBIT1 is encoded as SWC2: 111 010. */
1603 /* BBIT132 is encoded as SDC2: 111 110. */
1604 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1610 /* Determine where to set a single step breakpoint while considering
1611 branch prediction. */
1614 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1616 struct gdbarch
*gdbarch
= regcache
->arch ();
1619 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1620 op
= itype_op (inst
);
1621 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1625 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1636 goto greater_branch
;
1641 else if (op
== 17 && itype_rs (inst
) == 8)
1642 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1643 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1644 else if (op
== 17 && itype_rs (inst
) == 9
1645 && (itype_rt (inst
) & 2) == 0)
1646 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1647 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1648 else if (op
== 17 && itype_rs (inst
) == 10
1649 && (itype_rt (inst
) & 2) == 0)
1650 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1651 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1654 /* The new PC will be alternate mode. */
1658 reg
= jtype_target (inst
) << 2;
1659 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1660 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1662 else if (is_octeon_bbit_op (op
, gdbarch
))
1666 branch_if
= op
== 58 || op
== 62;
1667 bit
= itype_rt (inst
);
1669 /* Take into account the *32 instructions. */
1670 if (op
== 54 || op
== 62)
1673 if (((regcache_raw_get_signed (regcache
,
1674 itype_rs (inst
)) >> bit
) & 1)
1676 pc
+= mips32_relative_offset (inst
) + 4;
1678 pc
+= 8; /* After the delay slot. */
1682 pc
+= 4; /* Not a branch, next instruction is easy. */
1685 { /* This gets way messy. */
1687 /* Further subdivide into SPECIAL, REGIMM and other. */
1688 switch (op
& 0x07) /* Extract bits 28,27,26. */
1690 case 0: /* SPECIAL */
1691 op
= rtype_funct (inst
);
1696 /* Set PC to that address. */
1697 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1699 case 12: /* SYSCALL */
1701 struct gdbarch_tdep
*tdep
;
1703 tdep
= gdbarch_tdep (gdbarch
);
1704 if (tdep
->syscall_next_pc
!= NULL
)
1705 pc
= tdep
->syscall_next_pc (get_current_frame ());
1714 break; /* end SPECIAL */
1715 case 1: /* REGIMM */
1717 op
= itype_rt (inst
); /* branch condition */
1722 case 16: /* BLTZAL */
1723 case 18: /* BLTZALL */
1725 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1726 pc
+= mips32_relative_offset (inst
) + 4;
1728 pc
+= 8; /* after the delay slot */
1732 case 17: /* BGEZAL */
1733 case 19: /* BGEZALL */
1734 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1735 pc
+= mips32_relative_offset (inst
) + 4;
1737 pc
+= 8; /* after the delay slot */
1739 case 0x1c: /* BPOSGE32 */
1740 case 0x1e: /* BPOSGE64 */
1742 if (itype_rs (inst
) == 0)
1744 unsigned int pos
= (op
& 2) ? 64 : 32;
1745 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1748 /* No way to handle; it'll most likely trap anyway. */
1751 if ((regcache_raw_get_unsigned (regcache
,
1752 dspctl
) & 0x7f) >= pos
)
1753 pc
+= mips32_relative_offset (inst
);
1758 /* All of the other instructions in the REGIMM category */
1763 break; /* end REGIMM */
1768 reg
= jtype_target (inst
) << 2;
1769 /* Upper four bits get never changed... */
1770 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1773 case 4: /* BEQ, BEQL */
1775 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1776 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1777 pc
+= mips32_relative_offset (inst
) + 4;
1781 case 5: /* BNE, BNEL */
1783 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1784 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1785 pc
+= mips32_relative_offset (inst
) + 4;
1789 case 6: /* BLEZ, BLEZL */
1790 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1791 pc
+= mips32_relative_offset (inst
) + 4;
1797 greater_branch
: /* BGTZ, BGTZL */
1798 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1799 pc
+= mips32_relative_offset (inst
) + 4;
1806 } /* mips32_next_pc */
1808 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1812 micromips_relative_offset7 (ULONGEST insn
)
1814 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1817 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1821 micromips_relative_offset10 (ULONGEST insn
)
1823 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1826 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1830 micromips_relative_offset16 (ULONGEST insn
)
1832 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1835 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1838 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1842 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1843 return mips_insn_size (ISA_MICROMIPS
, insn
);
1846 /* Calculate the address of the next microMIPS instruction to execute
1847 after the INSN coprocessor 1 conditional branch instruction at the
1848 address PC. COUNT denotes the number of coprocessor condition bits
1849 examined by the branch. */
1852 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1853 ULONGEST insn
, CORE_ADDR pc
, int count
)
1855 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1856 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1857 int tf
= b5s5_op (insn
>> 16) & 1;
1858 int mask
= (1 << count
) - 1;
1863 /* No way to handle; it'll most likely trap anyway. */
1866 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1867 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1869 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1870 pc
+= micromips_relative_offset16 (insn
);
1872 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1877 /* Calculate the address of the next microMIPS instruction to execute
1878 after the instruction at the address PC. */
1881 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1883 struct gdbarch
*gdbarch
= regcache
->arch ();
1886 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1887 pc
+= MIPS_INSN16_SIZE
;
1888 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1890 /* 32-bit instructions. */
1891 case 2 * MIPS_INSN16_SIZE
:
1893 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1894 pc
+= MIPS_INSN16_SIZE
;
1895 switch (micromips_op (insn
>> 16))
1897 case 0x00: /* POOL32A: bits 000000 */
1898 switch (b0s6_op (insn
))
1900 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1901 switch (b6s10_ext (insn
))
1903 case 0x3c: /* JALR: 000000 0000111100 111100 */
1904 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1905 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1906 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1907 pc
= regcache_raw_get_signed (regcache
,
1908 b0s5_reg (insn
>> 16));
1910 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1912 struct gdbarch_tdep
*tdep
;
1914 tdep
= gdbarch_tdep (gdbarch
);
1915 if (tdep
->syscall_next_pc
!= NULL
)
1916 pc
= tdep
->syscall_next_pc (get_current_frame ());
1924 case 0x10: /* POOL32I: bits 010000 */
1925 switch (b5s5_op (insn
>> 16))
1927 case 0x00: /* BLTZ: bits 010000 00000 */
1928 case 0x01: /* BLTZAL: bits 010000 00001 */
1929 case 0x11: /* BLTZALS: bits 010000 10001 */
1930 if (regcache_raw_get_signed (regcache
,
1931 b0s5_reg (insn
>> 16)) < 0)
1932 pc
+= micromips_relative_offset16 (insn
);
1934 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1937 case 0x02: /* BGEZ: bits 010000 00010 */
1938 case 0x03: /* BGEZAL: bits 010000 00011 */
1939 case 0x13: /* BGEZALS: bits 010000 10011 */
1940 if (regcache_raw_get_signed (regcache
,
1941 b0s5_reg (insn
>> 16)) >= 0)
1942 pc
+= micromips_relative_offset16 (insn
);
1944 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1947 case 0x04: /* BLEZ: bits 010000 00100 */
1948 if (regcache_raw_get_signed (regcache
,
1949 b0s5_reg (insn
>> 16)) <= 0)
1950 pc
+= micromips_relative_offset16 (insn
);
1952 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1955 case 0x05: /* BNEZC: bits 010000 00101 */
1956 if (regcache_raw_get_signed (regcache
,
1957 b0s5_reg (insn
>> 16)) != 0)
1958 pc
+= micromips_relative_offset16 (insn
);
1961 case 0x06: /* BGTZ: bits 010000 00110 */
1962 if (regcache_raw_get_signed (regcache
,
1963 b0s5_reg (insn
>> 16)) > 0)
1964 pc
+= micromips_relative_offset16 (insn
);
1966 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1969 case 0x07: /* BEQZC: bits 010000 00111 */
1970 if (regcache_raw_get_signed (regcache
,
1971 b0s5_reg (insn
>> 16)) == 0)
1972 pc
+= micromips_relative_offset16 (insn
);
1975 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1976 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1977 if (((insn
>> 16) & 0x3) == 0x0)
1978 /* BC2F, BC2T: don't know how to handle these. */
1982 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1983 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1985 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1986 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1989 /* No way to handle; it'll most likely trap anyway. */
1992 if ((regcache_raw_get_unsigned (regcache
,
1993 dspctl
) & 0x7f) >= pos
)
1994 pc
+= micromips_relative_offset16 (insn
);
1996 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2000 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2001 /* BC1ANY2F: bits 010000 11100 xxx01 */
2002 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2003 /* BC1ANY2T: bits 010000 11101 xxx01 */
2004 if (((insn
>> 16) & 0x2) == 0x0)
2005 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2006 ((insn
>> 16) & 0x1) + 1);
2009 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2010 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2011 if (((insn
>> 16) & 0x3) == 0x1)
2012 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2017 case 0x1d: /* JALS: bits 011101 */
2018 case 0x35: /* J: bits 110101 */
2019 case 0x3d: /* JAL: bits 111101 */
2020 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2023 case 0x25: /* BEQ: bits 100101 */
2024 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2025 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2026 pc
+= micromips_relative_offset16 (insn
);
2028 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2031 case 0x2d: /* BNE: bits 101101 */
2032 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2033 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2034 pc
+= micromips_relative_offset16 (insn
);
2036 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2039 case 0x3c: /* JALX: bits 111100 */
2040 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2045 /* 16-bit instructions. */
2046 case MIPS_INSN16_SIZE
:
2047 switch (micromips_op (insn
))
2049 case 0x11: /* POOL16C: bits 010001 */
2050 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2051 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2052 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2053 else if (b5s5_op (insn
) == 0x18)
2054 /* JRADDIUSP: bits 010001 11000 */
2055 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2058 case 0x23: /* BEQZ16: bits 100011 */
2060 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2062 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2063 pc
+= micromips_relative_offset7 (insn
);
2065 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2069 case 0x2b: /* BNEZ16: bits 101011 */
2071 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2073 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2074 pc
+= micromips_relative_offset7 (insn
);
2076 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2080 case 0x33: /* B16: bits 110011 */
2081 pc
+= micromips_relative_offset10 (insn
);
2090 /* Decoding the next place to set a breakpoint is irregular for the
2091 mips 16 variant, but fortunately, there fewer instructions. We have
2092 to cope ith extensions for 16 bit instructions and a pair of actual
2093 32 bit instructions. We dont want to set a single step instruction
2094 on the extend instruction either. */
2096 /* Lots of mips16 instruction formats */
2097 /* Predicting jumps requires itype,ritype,i8type
2098 and their extensions extItype,extritype,extI8type. */
2099 enum mips16_inst_fmts
2101 itype
, /* 0 immediate 5,10 */
2102 ritype
, /* 1 5,3,8 */
2103 rrtype
, /* 2 5,3,3,5 */
2104 rritype
, /* 3 5,3,3,5 */
2105 rrrtype
, /* 4 5,3,3,3,2 */
2106 rriatype
, /* 5 5,3,3,1,4 */
2107 shifttype
, /* 6 5,3,3,3,2 */
2108 i8type
, /* 7 5,3,8 */
2109 i8movtype
, /* 8 5,3,3,5 */
2110 i8mov32rtype
, /* 9 5,3,5,3 */
2111 i64type
, /* 10 5,3,8 */
2112 ri64type
, /* 11 5,3,3,5 */
2113 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2114 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2115 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2116 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2117 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2118 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2119 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2120 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2121 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2122 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2124 /* I am heaping all the fields of the formats into one structure and
2125 then, only the fields which are involved in instruction extension. */
2129 unsigned int regx
; /* Function in i8 type. */
2134 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2135 for the bits which make up the immediate extension. */
2138 extended_offset (unsigned int extension
)
2142 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2144 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2146 value
|= extension
& 0x1f; /* Extract 4:0. */
2151 /* Only call this function if you know that this is an extendable
2152 instruction. It won't malfunction, but why make excess remote memory
2153 references? If the immediate operands get sign extended or something,
2154 do it after the extension is performed. */
2155 /* FIXME: Every one of these cases needs to worry about sign extension
2156 when the offset is to be used in relative addressing. */
2159 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2161 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2164 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2165 target_read_memory (pc
, buf
, 2);
2166 return extract_unsigned_integer (buf
, 2, byte_order
);
2170 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2171 unsigned int extension
,
2173 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2178 switch (insn_format
)
2185 value
= extended_offset ((extension
<< 16) | inst
);
2186 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2190 value
= inst
& 0x7ff;
2191 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2200 { /* A register identifier and an offset. */
2201 /* Most of the fields are the same as I type but the
2202 immediate value is of a different length. */
2206 value
= extended_offset ((extension
<< 16) | inst
);
2207 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2211 value
= inst
& 0xff; /* 8 bits */
2212 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2215 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2221 unsigned long value
;
2222 unsigned int nexthalf
;
2223 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2224 value
= value
<< 16;
2225 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2226 /* Low bit still set. */
2234 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2236 upk
->offset
= offset
;
2242 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2243 and having a signed 16-bit OFFSET. */
2246 add_offset_16 (CORE_ADDR pc
, int offset
)
2248 return pc
+ (offset
<< 1) + 2;
2252 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2253 unsigned int extension
, unsigned int insn
)
2255 struct gdbarch
*gdbarch
= regcache
->arch ();
2256 int op
= (insn
>> 11);
2259 case 2: /* Branch */
2261 struct upk_mips16 upk
;
2262 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2263 pc
= add_offset_16 (pc
, upk
.offset
);
2266 case 3: /* JAL , JALX - Watch out, these are 32 bit
2269 struct upk_mips16 upk
;
2270 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2271 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2272 if ((insn
>> 10) & 0x01) /* Exchange mode */
2273 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2280 struct upk_mips16 upk
;
2282 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2283 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2285 pc
= add_offset_16 (pc
, upk
.offset
);
2292 struct upk_mips16 upk
;
2294 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2295 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2297 pc
= add_offset_16 (pc
, upk
.offset
);
2302 case 12: /* I8 Formats btez btnez */
2304 struct upk_mips16 upk
;
2306 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2307 /* upk.regx contains the opcode */
2308 /* Test register is 24 */
2309 reg
= regcache_raw_get_signed (regcache
, 24);
2310 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2311 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2312 pc
= add_offset_16 (pc
, upk
.offset
);
2317 case 29: /* RR Formats JR, JALR, JALR-RA */
2319 struct upk_mips16 upk
;
2320 /* upk.fmt = rrtype; */
2325 upk
.regx
= (insn
>> 8) & 0x07;
2326 upk
.regy
= (insn
>> 5) & 0x07;
2327 if ((upk
.regy
& 1) == 0)
2328 reg
= mips_reg3_to_reg
[upk
.regx
];
2330 reg
= 31; /* Function return instruction. */
2331 pc
= regcache_raw_get_signed (regcache
, reg
);
2338 /* This is an instruction extension. Fetch the real instruction
2339 (which follows the extension) and decode things based on
2343 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2344 fetch_mips_16 (gdbarch
, pc
));
2357 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2359 struct gdbarch
*gdbarch
= regcache
->arch ();
2360 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2361 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2364 /* The mips_next_pc function supports single_step when the remote
2365 target monitor or stub is not developed enough to do a single_step.
2366 It works by decoding the current instruction and predicting where a
2367 branch will go. This isn't hard because all the data is available.
2368 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2370 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2372 struct gdbarch
*gdbarch
= regcache
->arch ();
2374 if (mips_pc_is_mips16 (gdbarch
, pc
))
2375 return mips16_next_pc (regcache
, pc
);
2376 else if (mips_pc_is_micromips (gdbarch
, pc
))
2377 return micromips_next_pc (regcache
, pc
);
2379 return mips32_next_pc (regcache
, pc
);
2382 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2386 mips16_instruction_is_compact_branch (unsigned short insn
)
2388 switch (insn
& 0xf800)
2391 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2393 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2394 case 0x2800: /* BNEZ */
2395 case 0x2000: /* BEQZ */
2396 case 0x1000: /* B */
2403 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2407 micromips_instruction_is_compact_branch (unsigned short insn
)
2409 switch (micromips_op (insn
))
2411 case 0x11: /* POOL16C: bits 010001 */
2412 return (b5s5_op (insn
) == 0x18
2413 /* JRADDIUSP: bits 010001 11000 */
2414 || b5s5_op (insn
) == 0xd);
2415 /* JRC: bits 010011 01101 */
2416 case 0x10: /* POOL32I: bits 010000 */
2417 return (b5s5_op (insn
) & 0x1d) == 0x5;
2418 /* BEQZC/BNEZC: bits 010000 001x1 */
2424 struct mips_frame_cache
2427 trad_frame_saved_reg
*saved_regs
;
2430 /* Set a register's saved stack address in temp_saved_regs. If an
2431 address has already been set for this register, do nothing; this
2432 way we will only recognize the first save of a given register in a
2435 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2436 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2437 Strictly speaking, only the second range is used as it is only second
2438 range (the ABI instead of ISA registers) that comes into play when finding
2439 saved registers in a frame. */
2442 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2443 int regnum
, CORE_ADDR offset
)
2445 if (this_cache
!= NULL
2446 && this_cache
->saved_regs
[regnum
].is_realreg ()
2447 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2449 this_cache
->saved_regs
[regnum
+ 0
2450 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2451 this_cache
->saved_regs
[regnum
+ 1
2452 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2457 /* Fetch the immediate value from a MIPS16 instruction.
2458 If the previous instruction was an EXTEND, use it to extend
2459 the upper bits of the immediate value. This is a helper function
2460 for mips16_scan_prologue. */
2463 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2464 unsigned short inst
, /* current instruction */
2465 int nbits
, /* number of bits in imm field */
2466 int scale
, /* scale factor to be applied to imm */
2467 int is_signed
) /* is the imm field signed? */
2471 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2473 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2474 if (offset
& 0x8000) /* check for negative extend */
2475 offset
= 0 - (0x10000 - (offset
& 0xffff));
2476 return offset
| (inst
& 0x1f);
2480 int max_imm
= 1 << nbits
;
2481 int mask
= max_imm
- 1;
2482 int sign_bit
= max_imm
>> 1;
2484 offset
= inst
& mask
;
2485 if (is_signed
&& (offset
& sign_bit
))
2486 offset
= 0 - (max_imm
- offset
);
2487 return offset
* scale
;
2492 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2493 the associated FRAME_CACHE if not null.
2494 Return the address of the first instruction past the prologue. */
2497 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2498 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2499 struct frame_info
*this_frame
,
2500 struct mips_frame_cache
*this_cache
)
2502 int prev_non_prologue_insn
= 0;
2503 int this_non_prologue_insn
;
2504 int non_prologue_insns
= 0;
2507 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2509 long frame_offset
= 0; /* Size of stack frame. */
2510 long frame_adjust
= 0; /* Offset of FP from SP. */
2511 int frame_reg
= MIPS_SP_REGNUM
;
2512 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2513 unsigned inst
= 0; /* current instruction */
2514 unsigned entry_inst
= 0; /* the entry instruction */
2515 unsigned save_inst
= 0; /* the save instruction */
2516 int prev_delay_slot
= 0;
2520 int extend_bytes
= 0;
2521 int prev_extend_bytes
= 0;
2522 CORE_ADDR end_prologue_addr
;
2524 /* Can be called when there's no process, and hence when there's no
2526 if (this_frame
!= NULL
)
2527 sp
= get_frame_register_signed (this_frame
,
2528 gdbarch_num_regs (gdbarch
)
2533 if (limit_pc
> start_pc
+ 200)
2534 limit_pc
= start_pc
+ 200;
2537 /* Permit at most one non-prologue non-control-transfer instruction
2538 in the middle which may have been reordered by the compiler for
2540 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2542 this_non_prologue_insn
= 0;
2545 /* Save the previous instruction. If it's an EXTEND, we'll extract
2546 the immediate offset extension from it in mips16_get_imm. */
2549 /* Fetch and decode the instruction. */
2550 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2553 /* Normally we ignore extend instructions. However, if it is
2554 not followed by a valid prologue instruction, then this
2555 instruction is not part of the prologue either. We must
2556 remember in this case to adjust the end_prologue_addr back
2558 if ((inst
& 0xf800) == 0xf000) /* extend */
2560 extend_bytes
= MIPS_INSN16_SIZE
;
2564 prev_extend_bytes
= extend_bytes
;
2567 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2568 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2570 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2571 if (offset
< 0) /* Negative stack adjustment? */
2572 frame_offset
-= offset
;
2574 /* Exit loop if a positive stack adjustment is found, which
2575 usually means that the stack cleanup code in the function
2576 epilogue is reached. */
2579 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2581 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2582 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2583 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2585 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2587 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2588 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2589 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2591 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2593 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2594 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2596 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2598 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2599 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2601 else if (inst
== 0x673d) /* move $s1, $sp */
2606 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2608 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2609 frame_addr
= sp
+ offset
;
2611 frame_adjust
= offset
;
2613 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2615 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2616 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2617 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2619 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2621 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2622 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2623 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2625 else if ((inst
& 0xf81f) == 0xe809
2626 && (inst
& 0x700) != 0x700) /* entry */
2627 entry_inst
= inst
; /* Save for later processing. */
2628 else if ((inst
& 0xff80) == 0x6480) /* save */
2630 save_inst
= inst
; /* Save for later processing. */
2631 if (prev_extend_bytes
) /* extend */
2632 save_inst
|= prev_inst
<< 16;
2634 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2636 /* This instruction is part of the prologue, but we don't
2637 need to do anything special to handle it. */
2639 else if (mips16_instruction_has_delay_slot (inst
, 0))
2640 /* JAL/JALR/JALX/JR */
2642 /* The instruction in the delay slot can be a part
2643 of the prologue, so move forward once more. */
2645 if (mips16_instruction_has_delay_slot (inst
, 1))
2648 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2649 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2654 this_non_prologue_insn
= 1;
2657 non_prologue_insns
+= this_non_prologue_insn
;
2659 /* A jump or branch, or enough non-prologue insns seen? If so,
2660 then we must have reached the end of the prologue by now. */
2661 if (prev_delay_slot
|| non_prologue_insns
> 1
2662 || mips16_instruction_is_compact_branch (inst
))
2665 prev_non_prologue_insn
= this_non_prologue_insn
;
2666 prev_delay_slot
= in_delay_slot
;
2667 prev_pc
= cur_pc
- prev_extend_bytes
;
2670 /* The entry instruction is typically the first instruction in a function,
2671 and it stores registers at offsets relative to the value of the old SP
2672 (before the prologue). But the value of the sp parameter to this
2673 function is the new SP (after the prologue has been executed). So we
2674 can't calculate those offsets until we've seen the entire prologue,
2675 and can calculate what the old SP must have been. */
2676 if (entry_inst
!= 0)
2678 int areg_count
= (entry_inst
>> 8) & 7;
2679 int sreg_count
= (entry_inst
>> 6) & 3;
2681 /* The entry instruction always subtracts 32 from the SP. */
2684 /* Now we can calculate what the SP must have been at the
2685 start of the function prologue. */
2688 /* Check if a0-a3 were saved in the caller's argument save area. */
2689 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2691 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2692 offset
+= mips_abi_regsize (gdbarch
);
2695 /* Check if the ra register was pushed on the stack. */
2697 if (entry_inst
& 0x20)
2699 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2700 offset
-= mips_abi_regsize (gdbarch
);
2703 /* Check if the s0 and s1 registers were pushed on the stack. */
2704 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2706 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2707 offset
-= mips_abi_regsize (gdbarch
);
2711 /* The SAVE instruction is similar to ENTRY, except that defined by the
2712 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2713 size of the frame is specified as an immediate field of instruction
2714 and an extended variation exists which lets additional registers and
2715 frame space to be specified. The instruction always treats registers
2716 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2717 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2719 static int args_table
[16] = {
2720 0, 0, 0, 0, 1, 1, 1, 1,
2721 2, 2, 2, 0, 3, 3, 4, -1,
2723 static int astatic_table
[16] = {
2724 0, 1, 2, 3, 0, 1, 2, 3,
2725 0, 1, 2, 4, 0, 1, 0, -1,
2727 int aregs
= (save_inst
>> 16) & 0xf;
2728 int xsregs
= (save_inst
>> 24) & 0x7;
2729 int args
= args_table
[aregs
];
2730 int astatic
= astatic_table
[aregs
];
2735 warning (_("Invalid number of argument registers encoded in SAVE."));
2740 warning (_("Invalid number of static registers encoded in SAVE."));
2744 /* For standard SAVE the frame size of 0 means 128. */
2745 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2746 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2749 frame_offset
+= frame_size
;
2751 /* Now we can calculate what the SP must have been at the
2752 start of the function prologue. */
2755 /* Check if A0-A3 were saved in the caller's argument save area. */
2756 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2758 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2759 offset
+= mips_abi_regsize (gdbarch
);
2764 /* Check if the RA register was pushed on the stack. */
2765 if (save_inst
& 0x40)
2767 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2768 offset
-= mips_abi_regsize (gdbarch
);
2771 /* Check if the S8 register was pushed on the stack. */
2774 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2775 offset
-= mips_abi_regsize (gdbarch
);
2778 /* Check if S2-S7 were pushed on the stack. */
2779 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2781 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2782 offset
-= mips_abi_regsize (gdbarch
);
2785 /* Check if the S1 register was pushed on the stack. */
2786 if (save_inst
& 0x10)
2788 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2789 offset
-= mips_abi_regsize (gdbarch
);
2791 /* Check if the S0 register was pushed on the stack. */
2792 if (save_inst
& 0x20)
2794 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2795 offset
-= mips_abi_regsize (gdbarch
);
2798 /* Check if A0-A3 were pushed on the stack. */
2799 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2801 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2802 offset
-= mips_abi_regsize (gdbarch
);
2806 if (this_cache
!= NULL
)
2809 (get_frame_register_signed (this_frame
,
2810 gdbarch_num_regs (gdbarch
) + frame_reg
)
2811 + frame_offset
- frame_adjust
);
2812 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2813 be able to get rid of the assignment below, evetually. But it's
2814 still needed for now. */
2815 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2816 + mips_regnum (gdbarch
)->pc
]
2817 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2820 /* Set end_prologue_addr to the address of the instruction immediately
2821 after the last one we scanned. Unless the last one looked like a
2822 non-prologue instruction (and we looked ahead), in which case use
2823 its address instead. */
2824 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2825 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2827 return end_prologue_addr
;
2830 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2831 Procedures that use the 32-bit instruction set are handled by the
2832 mips_insn32 unwinder. */
2834 static struct mips_frame_cache
*
2835 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2837 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2838 struct mips_frame_cache
*cache
;
2840 if ((*this_cache
) != NULL
)
2841 return (struct mips_frame_cache
*) (*this_cache
);
2842 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2843 (*this_cache
) = cache
;
2844 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2846 /* Analyze the function prologue. */
2848 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2849 CORE_ADDR start_addr
;
2851 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2852 if (start_addr
== 0)
2853 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2854 /* We can't analyze the prologue if we couldn't find the begining
2856 if (start_addr
== 0)
2859 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2860 (struct mips_frame_cache
*) *this_cache
);
2863 /* gdbarch_sp_regnum contains the value and not the address. */
2864 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2865 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2867 return (struct mips_frame_cache
*) (*this_cache
);
2871 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2872 struct frame_id
*this_id
)
2874 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2876 /* This marks the outermost frame. */
2877 if (info
->base
== 0)
2879 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2882 static struct value
*
2883 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2884 void **this_cache
, int regnum
)
2886 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2888 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2892 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2893 struct frame_info
*this_frame
, void **this_cache
)
2895 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2896 CORE_ADDR pc
= get_frame_pc (this_frame
);
2897 if (mips_pc_is_mips16 (gdbarch
, pc
))
2902 static const struct frame_unwind mips_insn16_frame_unwind
=
2905 default_frame_unwind_stop_reason
,
2906 mips_insn16_frame_this_id
,
2907 mips_insn16_frame_prev_register
,
2909 mips_insn16_frame_sniffer
2913 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2916 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2921 static const struct frame_base mips_insn16_frame_base
=
2923 &mips_insn16_frame_unwind
,
2924 mips_insn16_frame_base_address
,
2925 mips_insn16_frame_base_address
,
2926 mips_insn16_frame_base_address
2929 static const struct frame_base
*
2930 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2932 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2933 CORE_ADDR pc
= get_frame_pc (this_frame
);
2934 if (mips_pc_is_mips16 (gdbarch
, pc
))
2935 return &mips_insn16_frame_base
;
2940 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2941 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2942 interpreted directly, and then multiplied by 4. */
2945 micromips_decode_imm9 (int imm
)
2947 imm
= (imm
^ 0x100) - 0x100;
2948 if (imm
> -3 && imm
< 2)
2953 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2954 the address of the first instruction past the prologue. */
2957 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2958 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2959 struct frame_info
*this_frame
,
2960 struct mips_frame_cache
*this_cache
)
2962 CORE_ADDR end_prologue_addr
;
2963 int prev_non_prologue_insn
= 0;
2964 int frame_reg
= MIPS_SP_REGNUM
;
2965 int this_non_prologue_insn
;
2966 int non_prologue_insns
= 0;
2967 long frame_offset
= 0; /* Size of stack frame. */
2968 long frame_adjust
= 0; /* Offset of FP from SP. */
2969 int prev_delay_slot
= 0;
2973 ULONGEST insn
; /* current instruction */
2977 long v1_off
= 0; /* The assumption is LUI will replace it. */
2988 /* Can be called when there's no process, and hence when there's no
2990 if (this_frame
!= NULL
)
2991 sp
= get_frame_register_signed (this_frame
,
2992 gdbarch_num_regs (gdbarch
)
2997 if (limit_pc
> start_pc
+ 200)
2998 limit_pc
= start_pc
+ 200;
3001 /* Permit at most one non-prologue non-control-transfer instruction
3002 in the middle which may have been reordered by the compiler for
3004 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3006 this_non_prologue_insn
= 0;
3010 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3011 loc
+= MIPS_INSN16_SIZE
;
3012 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3014 /* 32-bit instructions. */
3015 case 2 * MIPS_INSN16_SIZE
:
3017 insn
|= mips_fetch_instruction (gdbarch
,
3018 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3019 loc
+= MIPS_INSN16_SIZE
;
3020 switch (micromips_op (insn
>> 16))
3022 /* Record $sp/$fp adjustment. */
3023 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3024 case 0x0: /* POOL32A: bits 000000 */
3025 case 0x16: /* POOL32S: bits 010110 */
3026 op
= b0s11_op (insn
);
3027 sreg
= b0s5_reg (insn
>> 16);
3028 treg
= b5s5_reg (insn
>> 16);
3029 dreg
= b11s5_reg (insn
);
3031 /* SUBU: bits 000000 00111010000 */
3032 /* DSUBU: bits 010110 00111010000 */
3033 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3035 /* (D)SUBU $sp, $v1 */
3037 else if (op
!= 0x150
3038 /* ADDU: bits 000000 00101010000 */
3039 /* DADDU: bits 010110 00101010000 */
3040 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3041 this_non_prologue_insn
= 1;
3044 case 0x8: /* POOL32B: bits 001000 */
3045 op
= b12s4_op (insn
);
3046 breg
= b0s5_reg (insn
>> 16);
3047 reglist
= sreg
= b5s5_reg (insn
>> 16);
3048 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3049 if ((op
== 0x9 || op
== 0xc)
3050 /* SWP: bits 001000 1001 */
3051 /* SDP: bits 001000 1100 */
3052 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3053 /* S[DW]P reg,offset($sp) */
3055 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3056 set_reg_offset (gdbarch
, this_cache
,
3058 set_reg_offset (gdbarch
, this_cache
,
3059 sreg
+ 1, sp
+ offset
+ s
);
3061 else if ((op
== 0xd || op
== 0xf)
3062 /* SWM: bits 001000 1101 */
3063 /* SDM: bits 001000 1111 */
3064 && breg
== MIPS_SP_REGNUM
3065 /* SWM reglist,offset($sp) */
3066 && ((reglist
>= 1 && reglist
<= 9)
3067 || (reglist
>= 16 && reglist
<= 25)))
3069 int sreglist
= std::min(reglist
& 0xf, 8);
3071 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3072 for (i
= 0; i
< sreglist
; i
++)
3073 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3074 if ((reglist
& 0xf) > 8)
3075 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3076 if ((reglist
& 0x10) == 0x10)
3077 set_reg_offset (gdbarch
, this_cache
,
3078 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3081 this_non_prologue_insn
= 1;
3084 /* Record $sp/$fp adjustment. */
3085 /* Discard (D)ADDIU $gp used for PIC code. */
3086 case 0xc: /* ADDIU: bits 001100 */
3087 case 0x17: /* DADDIU: bits 010111 */
3088 sreg
= b0s5_reg (insn
>> 16);
3089 dreg
= b5s5_reg (insn
>> 16);
3090 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3091 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3092 /* (D)ADDIU $sp, imm */
3094 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3095 /* (D)ADDIU $fp, $sp, imm */
3097 frame_adjust
= offset
;
3100 else if (sreg
!= 28 || dreg
!= 28)
3101 /* (D)ADDIU $gp, imm */
3102 this_non_prologue_insn
= 1;
3105 /* LUI $v1 is used for larger $sp adjustments. */
3106 /* Discard LUI $gp used for PIC code. */
3107 case 0x10: /* POOL32I: bits 010000 */
3108 if (b5s5_op (insn
>> 16) == 0xd
3109 /* LUI: bits 010000 001101 */
3110 && b0s5_reg (insn
>> 16) == 3)
3112 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3113 else if (b5s5_op (insn
>> 16) != 0xd
3114 /* LUI: bits 010000 001101 */
3115 || b0s5_reg (insn
>> 16) != 28)
3117 this_non_prologue_insn
= 1;
3120 /* ORI $v1 is used for larger $sp adjustments. */
3121 case 0x14: /* ORI: bits 010100 */
3122 sreg
= b0s5_reg (insn
>> 16);
3123 dreg
= b5s5_reg (insn
>> 16);
3124 if (sreg
== 3 && dreg
== 3)
3126 v1_off
|= b0s16_imm (insn
);
3128 this_non_prologue_insn
= 1;
3131 case 0x26: /* SWC1: bits 100110 */
3132 case 0x2e: /* SDC1: bits 101110 */
3133 breg
= b0s5_reg (insn
>> 16);
3134 if (breg
!= MIPS_SP_REGNUM
)
3135 /* S[DW]C1 reg,offset($sp) */
3136 this_non_prologue_insn
= 1;
3139 case 0x36: /* SD: bits 110110 */
3140 case 0x3e: /* SW: bits 111110 */
3141 breg
= b0s5_reg (insn
>> 16);
3142 sreg
= b5s5_reg (insn
>> 16);
3143 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3144 if (breg
== MIPS_SP_REGNUM
)
3145 /* S[DW] reg,offset($sp) */
3146 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3148 this_non_prologue_insn
= 1;
3152 /* The instruction in the delay slot can be a part
3153 of the prologue, so move forward once more. */
3154 if (micromips_instruction_has_delay_slot (insn
, 0))
3157 this_non_prologue_insn
= 1;
3163 /* 16-bit instructions. */
3164 case MIPS_INSN16_SIZE
:
3165 switch (micromips_op (insn
))
3167 case 0x3: /* MOVE: bits 000011 */
3168 sreg
= b0s5_reg (insn
);
3169 dreg
= b5s5_reg (insn
);
3170 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3173 else if ((sreg
& 0x1c) != 0x4)
3174 /* MOVE reg, $a0-$a3 */
3175 this_non_prologue_insn
= 1;
3178 case 0x11: /* POOL16C: bits 010001 */
3179 if (b6s4_op (insn
) == 0x5)
3180 /* SWM: bits 010001 0101 */
3182 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3183 reglist
= b4s2_regl (insn
);
3184 for (i
= 0; i
<= reglist
; i
++)
3185 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3186 set_reg_offset (gdbarch
, this_cache
,
3187 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3190 this_non_prologue_insn
= 1;
3193 case 0x13: /* POOL16D: bits 010011 */
3194 if ((insn
& 0x1) == 0x1)
3195 /* ADDIUSP: bits 010011 1 */
3196 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3197 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3198 /* ADDIUS5: bits 010011 0 */
3199 /* ADDIUS5 $sp, imm */
3200 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3202 this_non_prologue_insn
= 1;
3205 case 0x32: /* SWSP: bits 110010 */
3206 offset
= b0s5_imm (insn
) << 2;
3207 sreg
= b5s5_reg (insn
);
3208 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3212 /* The instruction in the delay slot can be a part
3213 of the prologue, so move forward once more. */
3214 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3217 this_non_prologue_insn
= 1;
3223 frame_offset
-= sp_adj
;
3225 non_prologue_insns
+= this_non_prologue_insn
;
3227 /* A jump or branch, enough non-prologue insns seen or positive
3228 stack adjustment? If so, then we must have reached the end
3229 of the prologue by now. */
3230 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3231 || micromips_instruction_is_compact_branch (insn
))
3234 prev_non_prologue_insn
= this_non_prologue_insn
;
3235 prev_delay_slot
= in_delay_slot
;
3239 if (this_cache
!= NULL
)
3242 (get_frame_register_signed (this_frame
,
3243 gdbarch_num_regs (gdbarch
) + frame_reg
)
3244 + frame_offset
- frame_adjust
);
3245 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3246 be able to get rid of the assignment below, evetually. But it's
3247 still needed for now. */
3248 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3249 + mips_regnum (gdbarch
)->pc
]
3250 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3253 /* Set end_prologue_addr to the address of the instruction immediately
3254 after the last one we scanned. Unless the last one looked like a
3255 non-prologue instruction (and we looked ahead), in which case use
3256 its address instead. */
3258 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3260 return end_prologue_addr
;
3263 /* Heuristic unwinder for procedures using microMIPS instructions.
3264 Procedures that use the 32-bit instruction set are handled by the
3265 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3267 static struct mips_frame_cache
*
3268 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3270 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3271 struct mips_frame_cache
*cache
;
3273 if ((*this_cache
) != NULL
)
3274 return (struct mips_frame_cache
*) (*this_cache
);
3276 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3277 (*this_cache
) = cache
;
3278 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3280 /* Analyze the function prologue. */
3282 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3283 CORE_ADDR start_addr
;
3285 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3286 if (start_addr
== 0)
3287 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3288 /* We can't analyze the prologue if we couldn't find the begining
3290 if (start_addr
== 0)
3293 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3294 (struct mips_frame_cache
*) *this_cache
);
3297 /* gdbarch_sp_regnum contains the value and not the address. */
3298 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3299 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3301 return (struct mips_frame_cache
*) (*this_cache
);
3305 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3306 struct frame_id
*this_id
)
3308 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3310 /* This marks the outermost frame. */
3311 if (info
->base
== 0)
3313 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3316 static struct value
*
3317 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3318 void **this_cache
, int regnum
)
3320 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3322 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3326 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3327 struct frame_info
*this_frame
, void **this_cache
)
3329 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3330 CORE_ADDR pc
= get_frame_pc (this_frame
);
3332 if (mips_pc_is_micromips (gdbarch
, pc
))
3337 static const struct frame_unwind mips_micro_frame_unwind
=
3340 default_frame_unwind_stop_reason
,
3341 mips_micro_frame_this_id
,
3342 mips_micro_frame_prev_register
,
3344 mips_micro_frame_sniffer
3348 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3351 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3356 static const struct frame_base mips_micro_frame_base
=
3358 &mips_micro_frame_unwind
,
3359 mips_micro_frame_base_address
,
3360 mips_micro_frame_base_address
,
3361 mips_micro_frame_base_address
3364 static const struct frame_base
*
3365 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3367 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3368 CORE_ADDR pc
= get_frame_pc (this_frame
);
3370 if (mips_pc_is_micromips (gdbarch
, pc
))
3371 return &mips_micro_frame_base
;
3376 /* Mark all the registers as unset in the saved_regs array
3377 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3380 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3382 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3386 const int num_regs
= gdbarch_num_regs (gdbarch
);
3389 /* Reset the register values to their default state. Register i's value
3390 is in register i. */
3391 for (i
= 0; i
< num_regs
; i
++)
3392 this_cache
->saved_regs
[i
].set_realreg (i
);
3396 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3397 the associated FRAME_CACHE if not null.
3398 Return the address of the first instruction past the prologue. */
3401 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3402 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3403 struct frame_info
*this_frame
,
3404 struct mips_frame_cache
*this_cache
)
3406 int prev_non_prologue_insn
;
3407 int this_non_prologue_insn
;
3408 int non_prologue_insns
;
3409 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3411 int prev_delay_slot
;
3416 int frame_reg
= MIPS_SP_REGNUM
;
3418 CORE_ADDR end_prologue_addr
;
3419 int seen_sp_adjust
= 0;
3420 int load_immediate_bytes
= 0;
3422 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3424 /* Can be called when there's no process, and hence when there's no
3426 if (this_frame
!= NULL
)
3427 sp
= get_frame_register_signed (this_frame
,
3428 gdbarch_num_regs (gdbarch
)
3433 if (limit_pc
> start_pc
+ 200)
3434 limit_pc
= start_pc
+ 200;
3437 prev_non_prologue_insn
= 0;
3438 non_prologue_insns
= 0;
3439 prev_delay_slot
= 0;
3442 /* Permit at most one non-prologue non-control-transfer instruction
3443 in the middle which may have been reordered by the compiler for
3446 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3448 unsigned long inst
, high_word
;
3452 this_non_prologue_insn
= 0;
3455 /* Fetch the instruction. */
3456 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3459 /* Save some code by pre-extracting some useful fields. */
3460 high_word
= (inst
>> 16) & 0xffff;
3461 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3462 reg
= high_word
& 0x1f;
3464 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3465 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3466 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3468 if (offset
< 0) /* Negative stack adjustment? */
3469 frame_offset
-= offset
;
3471 /* Exit loop if a positive stack adjustment is found, which
3472 usually means that the stack cleanup code in the function
3473 epilogue is reached. */
3477 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3478 && !regsize_is_64_bits
)
3480 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3482 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3483 && regsize_is_64_bits
)
3485 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3486 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3488 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3490 /* Old gcc frame, r30 is virtual frame pointer. */
3491 if (offset
!= frame_offset
)
3492 frame_addr
= sp
+ offset
;
3493 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3495 unsigned alloca_adjust
;
3498 frame_addr
= get_frame_register_signed
3499 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3502 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3503 if (alloca_adjust
> 0)
3505 /* FP > SP + frame_size. This may be because of
3506 an alloca or somethings similar. Fix sp to
3507 "pre-alloca" value, and try again. */
3508 sp
+= alloca_adjust
;
3509 /* Need to reset the status of all registers. Otherwise,
3510 we will hit a guard that prevents the new address
3511 for each register to be recomputed during the second
3513 reset_saved_regs (gdbarch
, this_cache
);
3518 /* move $30,$sp. With different versions of gas this will be either
3519 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3520 Accept any one of these. */
3521 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3523 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3524 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3526 unsigned alloca_adjust
;
3529 frame_addr
= get_frame_register_signed
3530 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3532 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3533 if (alloca_adjust
> 0)
3535 /* FP > SP + frame_size. This may be because of
3536 an alloca or somethings similar. Fix sp to
3537 "pre-alloca" value, and try again. */
3539 /* Need to reset the status of all registers. Otherwise,
3540 we will hit a guard that prevents the new address
3541 for each register to be recomputed during the second
3543 reset_saved_regs (gdbarch
, this_cache
);
3548 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3549 && !regsize_is_64_bits
)
3551 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3553 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3554 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3555 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3556 || high_word
== 0x3c1c /* lui $gp,n */
3557 || high_word
== 0x279c /* addiu $gp,$gp,n */
3558 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3559 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3562 /* These instructions are part of the prologue, but we don't
3563 need to do anything special to handle them. */
3565 /* The instructions below load $at or $t0 with an immediate
3566 value in preparation for a stack adjustment via
3567 subu $sp,$sp,[$at,$t0]. These instructions could also
3568 initialize a local variable, so we accept them only before
3569 a stack adjustment instruction was seen. */
3570 else if (!seen_sp_adjust
3572 && (high_word
== 0x3c01 /* lui $at,n */
3573 || high_word
== 0x3c08 /* lui $t0,n */
3574 || high_word
== 0x3421 /* ori $at,$at,n */
3575 || high_word
== 0x3508 /* ori $t0,$t0,n */
3576 || high_word
== 0x3401 /* ori $at,$zero,n */
3577 || high_word
== 0x3408 /* ori $t0,$zero,n */
3580 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3582 /* Check for branches and jumps. The instruction in the delay
3583 slot can be a part of the prologue, so move forward once more. */
3584 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3588 /* This instruction is not an instruction typically found
3589 in a prologue, so we must have reached the end of the
3593 this_non_prologue_insn
= 1;
3596 non_prologue_insns
+= this_non_prologue_insn
;
3598 /* A jump or branch, or enough non-prologue insns seen? If so,
3599 then we must have reached the end of the prologue by now. */
3600 if (prev_delay_slot
|| non_prologue_insns
> 1)
3603 prev_non_prologue_insn
= this_non_prologue_insn
;
3604 prev_delay_slot
= in_delay_slot
;
3608 if (this_cache
!= NULL
)
3611 (get_frame_register_signed (this_frame
,
3612 gdbarch_num_regs (gdbarch
) + frame_reg
)
3614 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3615 this assignment below, eventually. But it's still needed
3617 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3618 + mips_regnum (gdbarch
)->pc
]
3619 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3623 /* Set end_prologue_addr to the address of the instruction immediately
3624 after the last one we scanned. Unless the last one looked like a
3625 non-prologue instruction (and we looked ahead), in which case use
3626 its address instead. */
3628 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3630 /* In a frameless function, we might have incorrectly
3631 skipped some load immediate instructions. Undo the skipping
3632 if the load immediate was not followed by a stack adjustment. */
3633 if (load_immediate_bytes
&& !seen_sp_adjust
)
3634 end_prologue_addr
-= load_immediate_bytes
;
3636 return end_prologue_addr
;
3639 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3640 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3641 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3642 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3644 static struct mips_frame_cache
*
3645 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3647 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3648 struct mips_frame_cache
*cache
;
3650 if ((*this_cache
) != NULL
)
3651 return (struct mips_frame_cache
*) (*this_cache
);
3653 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3654 (*this_cache
) = cache
;
3655 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3657 /* Analyze the function prologue. */
3659 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3660 CORE_ADDR start_addr
;
3662 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3663 if (start_addr
== 0)
3664 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3665 /* We can't analyze the prologue if we couldn't find the begining
3667 if (start_addr
== 0)
3670 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3671 (struct mips_frame_cache
*) *this_cache
);
3674 /* gdbarch_sp_regnum contains the value and not the address. */
3675 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3676 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3678 return (struct mips_frame_cache
*) (*this_cache
);
3682 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3683 struct frame_id
*this_id
)
3685 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3687 /* This marks the outermost frame. */
3688 if (info
->base
== 0)
3690 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3693 static struct value
*
3694 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3695 void **this_cache
, int regnum
)
3697 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3699 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3703 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3704 struct frame_info
*this_frame
, void **this_cache
)
3706 CORE_ADDR pc
= get_frame_pc (this_frame
);
3707 if (mips_pc_is_mips (pc
))
3712 static const struct frame_unwind mips_insn32_frame_unwind
=
3715 default_frame_unwind_stop_reason
,
3716 mips_insn32_frame_this_id
,
3717 mips_insn32_frame_prev_register
,
3719 mips_insn32_frame_sniffer
3723 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3726 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3731 static const struct frame_base mips_insn32_frame_base
=
3733 &mips_insn32_frame_unwind
,
3734 mips_insn32_frame_base_address
,
3735 mips_insn32_frame_base_address
,
3736 mips_insn32_frame_base_address
3739 static const struct frame_base
*
3740 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3742 CORE_ADDR pc
= get_frame_pc (this_frame
);
3743 if (mips_pc_is_mips (pc
))
3744 return &mips_insn32_frame_base
;
3749 static struct trad_frame_cache
*
3750 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3753 CORE_ADDR start_addr
;
3754 CORE_ADDR stack_addr
;
3755 struct trad_frame_cache
*this_trad_cache
;
3756 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3757 int num_regs
= gdbarch_num_regs (gdbarch
);
3759 if ((*this_cache
) != NULL
)
3760 return (struct trad_frame_cache
*) (*this_cache
);
3761 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3762 (*this_cache
) = this_trad_cache
;
3764 /* The return address is in the link register. */
3765 trad_frame_set_reg_realreg (this_trad_cache
,
3766 gdbarch_pc_regnum (gdbarch
),
3767 num_regs
+ MIPS_RA_REGNUM
);
3769 /* Frame ID, since it's a frameless / stackless function, no stack
3770 space is allocated and SP on entry is the current SP. */
3771 pc
= get_frame_pc (this_frame
);
3772 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3773 stack_addr
= get_frame_register_signed (this_frame
,
3774 num_regs
+ MIPS_SP_REGNUM
);
3775 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3777 /* Assume that the frame's base is the same as the
3779 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3781 return this_trad_cache
;
3785 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3786 struct frame_id
*this_id
)
3788 struct trad_frame_cache
*this_trad_cache
3789 = mips_stub_frame_cache (this_frame
, this_cache
);
3790 trad_frame_get_id (this_trad_cache
, this_id
);
3793 static struct value
*
3794 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3795 void **this_cache
, int regnum
)
3797 struct trad_frame_cache
*this_trad_cache
3798 = mips_stub_frame_cache (this_frame
, this_cache
);
3799 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3803 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3804 struct frame_info
*this_frame
, void **this_cache
)
3807 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3808 struct bound_minimal_symbol msym
;
3810 /* Use the stub unwinder for unreadable code. */
3811 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3814 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3817 /* Calling a PIC function from a non-PIC function passes through a
3818 stub. The stub for foo is named ".pic.foo". */
3819 msym
= lookup_minimal_symbol_by_pc (pc
);
3820 if (msym
.minsym
!= NULL
3821 && msym
.minsym
->linkage_name () != NULL
3822 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3828 static const struct frame_unwind mips_stub_frame_unwind
=
3831 default_frame_unwind_stop_reason
,
3832 mips_stub_frame_this_id
,
3833 mips_stub_frame_prev_register
,
3835 mips_stub_frame_sniffer
3839 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3842 struct trad_frame_cache
*this_trad_cache
3843 = mips_stub_frame_cache (this_frame
, this_cache
);
3844 return trad_frame_get_this_base (this_trad_cache
);
3847 static const struct frame_base mips_stub_frame_base
=
3849 &mips_stub_frame_unwind
,
3850 mips_stub_frame_base_address
,
3851 mips_stub_frame_base_address
,
3852 mips_stub_frame_base_address
3855 static const struct frame_base
*
3856 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3858 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3859 return &mips_stub_frame_base
;
3864 /* mips_addr_bits_remove - remove useless address bits */
3867 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3869 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3871 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3872 /* This hack is a work-around for existing boards using PMON, the
3873 simulator, and any other 64-bit targets that doesn't have true
3874 64-bit addressing. On these targets, the upper 32 bits of
3875 addresses are ignored by the hardware. Thus, the PC or SP are
3876 likely to have been sign extended to all 1s by instruction
3877 sequences that load 32-bit addresses. For example, a typical
3878 piece of code that loads an address is this:
3880 lui $r2, <upper 16 bits>
3881 ori $r2, <lower 16 bits>
3883 But the lui sign-extends the value such that the upper 32 bits
3884 may be all 1s. The workaround is simply to mask off these
3885 bits. In the future, gcc may be changed to support true 64-bit
3886 addressing, and this masking will have to be disabled. */
3887 return addr
&= 0xffffffffUL
;
3893 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3894 instruction and ending with a SC/SCD instruction. If such a sequence
3895 is found, attempt to step through it. A breakpoint is placed at the end of
3898 /* Instructions used during single-stepping of atomic sequences, standard
3900 #define LL_OPCODE 0x30
3901 #define LLD_OPCODE 0x34
3902 #define SC_OPCODE 0x38
3903 #define SCD_OPCODE 0x3c
3905 static std::vector
<CORE_ADDR
>
3906 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3908 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3910 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3914 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3915 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3917 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3918 /* Assume all atomic sequences start with a ll/lld instruction. */
3919 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3922 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3924 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3927 loc
+= MIPS_INSN32_SIZE
;
3928 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3930 /* Assume that there is at most one branch in the atomic
3931 sequence. If a branch is found, put a breakpoint in its
3932 destination address. */
3933 switch (itype_op (insn
))
3935 case 0: /* SPECIAL */
3936 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3937 return {}; /* fallback to the standard single-step code. */
3939 case 1: /* REGIMM */
3940 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3941 || ((itype_rt (insn
) & 0x1e) == 0
3942 && itype_rs (insn
) == 0)); /* BPOSGE* */
3946 return {}; /* fallback to the standard single-step code. */
3953 case 22: /* BLEZL */
3954 case 23: /* BGTTL */
3958 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3959 && (itype_rt (insn
) & 0x2) == 0);
3960 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3965 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3970 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3971 if (last_breakpoint
>= 1)
3972 return {}; /* More than one branch found, fallback to the
3973 standard single-step code. */
3974 breaks
[1] = branch_bp
;
3978 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3982 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3983 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3986 loc
+= MIPS_INSN32_SIZE
;
3988 /* Insert a breakpoint right after the end of the atomic sequence. */
3991 /* Check for duplicated breakpoints. Check also for a breakpoint
3992 placed (branch instruction's destination) in the atomic sequence. */
3993 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3994 last_breakpoint
= 0;
3996 std::vector
<CORE_ADDR
> next_pcs
;
3998 /* Effectively inserts the breakpoints. */
3999 for (index
= 0; index
<= last_breakpoint
; index
++)
4000 next_pcs
.push_back (breaks
[index
]);
4005 static std::vector
<CORE_ADDR
>
4006 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4009 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4010 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4011 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4012 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4020 /* Assume all atomic sequences start with a ll/lld instruction. */
4021 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4022 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4024 loc
+= MIPS_INSN16_SIZE
;
4026 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4027 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4029 loc
+= MIPS_INSN16_SIZE
;
4031 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4032 that no atomic sequence is longer than "atomic_sequence_length"
4034 for (insn_count
= 0;
4035 !sc_found
&& insn_count
< atomic_sequence_length
;
4040 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4041 loc
+= MIPS_INSN16_SIZE
;
4043 /* Assume that there is at most one conditional branch in the
4044 atomic sequence. If a branch is found, put a breakpoint in
4045 its destination address. */
4046 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4048 /* 32-bit instructions. */
4049 case 2 * MIPS_INSN16_SIZE
:
4050 switch (micromips_op (insn
))
4052 case 0x10: /* POOL32I: bits 010000 */
4053 if ((b5s5_op (insn
) & 0x18) != 0x0
4054 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4055 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4056 && (b5s5_op (insn
) & 0x1d) != 0x11
4057 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4058 && ((b5s5_op (insn
) & 0x1e) != 0x14
4059 || (insn
& 0x3) != 0x0)
4060 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4061 && (b5s5_op (insn
) & 0x1e) != 0x1a
4062 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4063 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4064 || (insn
& 0x3) != 0x0)
4065 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4066 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4067 || (insn
& 0x3) != 0x1))
4068 /* BC1ANY*: bits 010000 111xx xxx01 */
4072 case 0x25: /* BEQ: bits 100101 */
4073 case 0x2d: /* BNE: bits 101101 */
4075 insn
|= mips_fetch_instruction (gdbarch
,
4076 ISA_MICROMIPS
, loc
, NULL
);
4077 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4078 + micromips_relative_offset16 (insn
));
4082 case 0x00: /* POOL32A: bits 000000 */
4084 insn
|= mips_fetch_instruction (gdbarch
,
4085 ISA_MICROMIPS
, loc
, NULL
);
4086 if (b0s6_op (insn
) != 0x3c
4087 /* POOL32Axf: bits 000000 ... 111100 */
4088 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4089 /* JALR, JALR.HB: 000000 000x111100 111100 */
4090 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4094 case 0x1d: /* JALS: bits 011101 */
4095 case 0x35: /* J: bits 110101 */
4096 case 0x3d: /* JAL: bits 111101 */
4097 case 0x3c: /* JALX: bits 111100 */
4098 return {}; /* Fall back to the standard single-step code. */
4100 case 0x18: /* POOL32C: bits 011000 */
4101 if ((b12s4_op (insn
) & 0xb) == 0xb)
4102 /* SC, SCD: bits 011000 1x11 */
4106 loc
+= MIPS_INSN16_SIZE
;
4109 /* 16-bit instructions. */
4110 case MIPS_INSN16_SIZE
:
4111 switch (micromips_op (insn
))
4113 case 0x23: /* BEQZ16: bits 100011 */
4114 case 0x2b: /* BNEZ16: bits 101011 */
4115 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4119 case 0x11: /* POOL16C: bits 010001 */
4120 if ((b5s5_op (insn
) & 0x1c) != 0xc
4121 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4122 && b5s5_op (insn
) != 0x18)
4123 /* JRADDIUSP: bits 010001 11000 */
4125 return {}; /* Fall back to the standard single-step code. */
4127 case 0x33: /* B16: bits 110011 */
4128 return {}; /* Fall back to the standard single-step code. */
4134 if (last_breakpoint
>= 1)
4135 return {}; /* More than one branch found, fallback to the
4136 standard single-step code. */
4137 breaks
[1] = branch_bp
;
4144 /* Insert a breakpoint right after the end of the atomic sequence. */
4147 /* Check for duplicated breakpoints. Check also for a breakpoint
4148 placed (branch instruction's destination) in the atomic sequence */
4149 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4150 last_breakpoint
= 0;
4152 std::vector
<CORE_ADDR
> next_pcs
;
4154 /* Effectively inserts the breakpoints. */
4155 for (index
= 0; index
<= last_breakpoint
; index
++)
4156 next_pcs
.push_back (breaks
[index
]);
4161 static std::vector
<CORE_ADDR
>
4162 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4164 if (mips_pc_is_mips (pc
))
4165 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4166 else if (mips_pc_is_micromips (gdbarch
, pc
))
4167 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4172 /* mips_software_single_step() is called just before we want to resume
4173 the inferior, if we want to single-step it but there is no hardware
4174 or kernel single-step support (MIPS on GNU/Linux for example). We find
4175 the target of the coming instruction and breakpoint it. */
4177 std::vector
<CORE_ADDR
>
4178 mips_software_single_step (struct regcache
*regcache
)
4180 struct gdbarch
*gdbarch
= regcache
->arch ();
4181 CORE_ADDR pc
, next_pc
;
4183 pc
= regcache_read_pc (regcache
);
4184 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4186 if (!next_pcs
.empty ())
4189 next_pc
= mips_next_pc (regcache
, pc
);
4194 /* Test whether the PC points to the return instruction at the
4195 end of a function. */
4198 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4203 /* This used to check for MIPS16, but this piece of code is never
4204 called for MIPS16 functions. And likewise microMIPS ones. */
4205 gdb_assert (mips_pc_is_mips (pc
));
4207 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4209 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4213 /* This fencepost looks highly suspicious to me. Removing it also
4214 seems suspicious as it could affect remote debugging across serial
4218 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4224 struct inferior
*inf
;
4226 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4228 fence
= start_pc
- heuristic_fence_post
;
4232 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4233 fence
= VM_MIN_ADDRESS
;
4235 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4237 inf
= current_inferior ();
4239 /* Search back for previous return. */
4240 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4241 if (start_pc
< fence
)
4243 /* It's not clear to me why we reach this point when
4244 stop_soon, but with this test, at least we
4245 don't print out warnings for every child forked (eg, on
4246 decstation). 22apr93 rich@cygnus.com. */
4247 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4249 static int blurb_printed
= 0;
4251 warning (_("GDB can't find the start of the function at %s."),
4252 paddress (gdbarch
, pc
));
4256 /* This actually happens frequently in embedded
4257 development, when you first connect to a board
4258 and your stack pointer and pc are nowhere in
4259 particular. This message needs to give people
4260 in that situation enough information to
4261 determine that it's no big deal. */
4262 printf_filtered ("\n\
4263 GDB is unable to find the start of the function at %s\n\
4264 and thus can't determine the size of that function's stack frame.\n\
4265 This means that GDB may be unable to access that stack frame, or\n\
4266 the frames below it.\n\
4267 This problem is most likely caused by an invalid program counter or\n\
4269 However, if you think GDB should simply search farther back\n\
4270 from %s for code which looks like the beginning of a\n\
4271 function, you can increase the range of the search using the `set\n\
4272 heuristic-fence-post' command.\n",
4273 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4280 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4282 unsigned short inst
;
4284 /* On MIPS16, any one of the following is likely to be the
4285 start of a function:
4291 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4292 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4293 if ((inst
& 0xff80) == 0x6480) /* save */
4295 if (start_pc
- instlen
>= fence
)
4297 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4298 start_pc
- instlen
, NULL
);
4299 if ((inst
& 0xf800) == 0xf000) /* extend */
4300 start_pc
-= instlen
;
4304 else if (((inst
& 0xf81f) == 0xe809
4305 && (inst
& 0x700) != 0x700) /* entry */
4306 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4307 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4308 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4310 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4311 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4316 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4324 /* On microMIPS, any one of the following is likely to be the
4325 start of a function:
4329 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4330 switch (micromips_op (insn
))
4332 case 0xc: /* ADDIU: bits 001100 */
4333 case 0x17: /* DADDIU: bits 010111 */
4334 sreg
= b0s5_reg (insn
);
4335 dreg
= b5s5_reg (insn
);
4337 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4338 pc
+ MIPS_INSN16_SIZE
, NULL
);
4339 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4340 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4341 /* (D)ADDIU $sp, imm */
4346 case 0x10: /* POOL32I: bits 010000 */
4347 if (b5s5_op (insn
) == 0xd
4348 /* LUI: bits 010000 001101 */
4349 && b0s5_reg (insn
>> 16) == 28)
4354 case 0x13: /* POOL16D: bits 010011 */
4355 if ((insn
& 0x1) == 0x1)
4356 /* ADDIUSP: bits 010011 1 */
4358 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4364 /* ADDIUS5: bits 010011 0 */
4366 dreg
= b5s5_reg (insn
);
4367 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4368 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4369 /* ADDIUS5 $sp, -imm */
4377 else if (mips_about_to_return (gdbarch
, start_pc
))
4379 /* Skip return and its delay slot. */
4380 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4387 struct mips_objfile_private
4393 /* According to the current ABI, should the type be passed in a
4394 floating-point register (assuming that there is space)? When there
4395 is no FPU, FP are not even considered as possible candidates for
4396 FP registers and, consequently this returns false - forces FP
4397 arguments into integer registers. */
4400 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4401 struct type
*arg_type
)
4403 return ((typecode
== TYPE_CODE_FLT
4404 || (MIPS_EABI (gdbarch
)
4405 && (typecode
== TYPE_CODE_STRUCT
4406 || typecode
== TYPE_CODE_UNION
)
4407 && arg_type
->num_fields () == 1
4408 && check_typedef (arg_type
->field (0).type ())->code ()
4410 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4413 /* On o32, argument passing in GPRs depends on the alignment of the type being
4414 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4417 mips_type_needs_double_align (struct type
*type
)
4419 enum type_code typecode
= type
->code ();
4421 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4423 else if (typecode
== TYPE_CODE_STRUCT
)
4425 if (type
->num_fields () < 1)
4427 return mips_type_needs_double_align (type
->field (0).type ());
4429 else if (typecode
== TYPE_CODE_UNION
)
4433 n
= type
->num_fields ();
4434 for (i
= 0; i
< n
; i
++)
4435 if (mips_type_needs_double_align (type
->field (i
).type ()))
4442 /* Adjust the address downward (direction of stack growth) so that it
4443 is correctly aligned for a new stack frame. */
4445 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4447 return align_down (addr
, 16);
4450 /* Implement the "push_dummy_code" gdbarch method. */
4453 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4454 CORE_ADDR funaddr
, struct value
**args
,
4455 int nargs
, struct type
*value_type
,
4456 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4457 struct regcache
*regcache
)
4459 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4463 /* Reserve enough room on the stack for our breakpoint instruction. */
4464 bp_slot
= sp
- sizeof (nop_insn
);
4466 /* Return to microMIPS mode if calling microMIPS code to avoid
4467 triggering an address error exception on processors that only
4468 support microMIPS execution. */
4469 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4470 ? make_compact_addr (bp_slot
) : bp_slot
);
4472 /* The breakpoint layer automatically adjusts the address of
4473 breakpoints inserted in a branch delay slot. With enough
4474 bad luck, the 4 bytes located just before our breakpoint
4475 instruction could look like a branch instruction, and thus
4476 trigger the adjustement, and break the function call entirely.
4477 So, we reserve those 4 bytes and write a nop instruction
4478 to prevent that from happening. */
4479 nop_addr
= bp_slot
- sizeof (nop_insn
);
4480 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4481 sp
= mips_frame_align (gdbarch
, nop_addr
);
4483 /* Inferior resumes at the function entry point. */
4490 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4491 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4492 int nargs
, struct value
**args
, CORE_ADDR sp
,
4493 function_call_return_method return_method
,
4494 CORE_ADDR struct_addr
)
4500 int stack_offset
= 0;
4501 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4502 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4503 int abi_regsize
= mips_abi_regsize (gdbarch
);
4505 /* For shared libraries, "t9" needs to point at the function
4507 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4509 /* Set the return address register to point to the entry point of
4510 the program, where a breakpoint lies in wait. */
4511 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4513 /* First ensure that the stack and structure return address (if any)
4514 are properly aligned. The stack has to be at least 64-bit
4515 aligned even on 32-bit machines, because doubles must be 64-bit
4516 aligned. For n32 and n64, stack frames need to be 128-bit
4517 aligned, so we round to this widest known alignment. */
4519 sp
= align_down (sp
, 16);
4520 struct_addr
= align_down (struct_addr
, 16);
4522 /* Now make space on the stack for the args. We allocate more
4523 than necessary for EABI, because the first few arguments are
4524 passed in registers, but that's OK. */
4525 for (argnum
= 0; argnum
< nargs
; argnum
++)
4526 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4527 sp
-= align_up (arg_space
, 16);
4530 fprintf_unfiltered (gdb_stdlog
,
4531 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4532 paddress (gdbarch
, sp
),
4533 (long) align_up (arg_space
, 16));
4535 /* Initialize the integer and float register pointers. */
4536 argreg
= MIPS_A0_REGNUM
;
4537 float_argreg
= mips_fpa0_regnum (gdbarch
);
4539 /* The struct_return pointer occupies the first parameter-passing reg. */
4540 if (return_method
== return_method_struct
)
4543 fprintf_unfiltered (gdb_stdlog
,
4544 "mips_eabi_push_dummy_call: "
4545 "struct_return reg=%d %s\n",
4546 argreg
, paddress (gdbarch
, struct_addr
));
4547 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4550 /* Now load as many as possible of the first arguments into
4551 registers, and push the rest onto the stack. Loop thru args
4552 from first to last. */
4553 for (argnum
= 0; argnum
< nargs
; argnum
++)
4555 const gdb_byte
*val
;
4556 /* This holds the address of structures that are passed by
4558 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4559 struct value
*arg
= args
[argnum
];
4560 struct type
*arg_type
= check_typedef (value_type (arg
));
4561 int len
= TYPE_LENGTH (arg_type
);
4562 enum type_code typecode
= arg_type
->code ();
4565 fprintf_unfiltered (gdb_stdlog
,
4566 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4567 argnum
+ 1, len
, (int) typecode
);
4569 /* The EABI passes structures that do not fit in a register by
4571 if (len
> abi_regsize
4572 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4574 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4575 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4576 value_address (arg
));
4577 typecode
= TYPE_CODE_PTR
;
4581 fprintf_unfiltered (gdb_stdlog
, " push");
4584 val
= value_contents (arg
);
4586 /* 32-bit ABIs always start floating point arguments in an
4587 even-numbered floating point register. Round the FP register
4588 up before the check to see if there are any FP registers
4589 left. Non MIPS_EABI targets also pass the FP in the integer
4590 registers so also round up normal registers. */
4591 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4593 if ((float_argreg
& 1))
4597 /* Floating point arguments passed in registers have to be
4598 treated specially. On 32-bit architectures, doubles
4599 are passed in register pairs; the even register gets
4600 the low word, and the odd register gets the high word.
4601 On non-EABI processors, the first two floating point arguments are
4602 also copied to general registers, because MIPS16 functions
4603 don't use float registers for arguments. This duplication of
4604 arguments in general registers can't hurt non-MIPS16 functions
4605 because those registers are normally skipped. */
4606 /* MIPS_EABI squeezes a struct that contains a single floating
4607 point value into an FP register instead of pushing it onto the
4609 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4610 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4612 /* EABI32 will pass doubles in consecutive registers, even on
4613 64-bit cores. At one time, we used to check the size of
4614 `float_argreg' to determine whether or not to pass doubles
4615 in consecutive registers, but this is not sufficient for
4616 making the ABI determination. */
4617 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4619 int low_offset
= gdbarch_byte_order (gdbarch
)
4620 == BFD_ENDIAN_BIG
? 4 : 0;
4623 /* Write the low word of the double to the even register(s). */
4624 regval
= extract_signed_integer (val
+ low_offset
,
4627 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4628 float_argreg
, phex (regval
, 4));
4629 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4631 /* Write the high word of the double to the odd register(s). */
4632 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4635 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4636 float_argreg
, phex (regval
, 4));
4637 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4641 /* This is a floating point value that fits entirely
4642 in a single register. */
4643 /* On 32 bit ABI's the float_argreg is further adjusted
4644 above to ensure that it is even register aligned. */
4645 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4647 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4648 float_argreg
, phex (regval
, len
));
4649 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4654 /* Copy the argument to general registers or the stack in
4655 register-sized pieces. Large arguments are split between
4656 registers and stack. */
4657 /* Note: structs whose size is not a multiple of abi_regsize
4658 are treated specially: Irix cc passes
4659 them in registers where gcc sometimes puts them on the
4660 stack. For maximum compatibility, we will put them in
4662 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4664 /* Note: Floating-point values that didn't fit into an FP
4665 register are only written to memory. */
4668 /* Remember if the argument was written to the stack. */
4669 int stack_used_p
= 0;
4670 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4673 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4676 /* Write this portion of the argument to the stack. */
4677 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4679 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4681 /* Should shorter than int integer values be
4682 promoted to int before being stored? */
4683 int longword_offset
= 0;
4686 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4688 if (abi_regsize
== 8
4689 && (typecode
== TYPE_CODE_INT
4690 || typecode
== TYPE_CODE_PTR
4691 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4692 longword_offset
= abi_regsize
- len
;
4693 else if ((typecode
== TYPE_CODE_STRUCT
4694 || typecode
== TYPE_CODE_UNION
)
4695 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4696 longword_offset
= abi_regsize
- len
;
4701 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4702 paddress (gdbarch
, stack_offset
));
4703 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4704 paddress (gdbarch
, longword_offset
));
4707 addr
= sp
+ stack_offset
+ longword_offset
;
4712 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4713 paddress (gdbarch
, addr
));
4714 for (i
= 0; i
< partial_len
; i
++)
4716 fprintf_unfiltered (gdb_stdlog
, "%02x",
4720 write_memory (addr
, val
, partial_len
);
4723 /* Note!!! This is NOT an else clause. Odd sized
4724 structs may go thru BOTH paths. Floating point
4725 arguments will not. */
4726 /* Write this portion of the argument to a general
4727 purpose register. */
4728 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4729 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4732 extract_signed_integer (val
, partial_len
, byte_order
);
4735 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4737 phex (regval
, abi_regsize
));
4738 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4745 /* Compute the offset into the stack at which we will
4746 copy the next parameter.
4748 In the new EABI (and the NABI32), the stack_offset
4749 only needs to be adjusted when it has been used. */
4752 stack_offset
+= align_up (partial_len
, abi_regsize
);
4756 fprintf_unfiltered (gdb_stdlog
, "\n");
4759 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4761 /* Return adjusted stack pointer. */
4765 /* Determine the return value convention being used. */
4767 static enum return_value_convention
4768 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4769 struct type
*type
, struct regcache
*regcache
,
4770 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4772 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4773 int fp_return_type
= 0;
4774 int offset
, regnum
, xfer
;
4776 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4777 return RETURN_VALUE_STRUCT_CONVENTION
;
4779 /* Floating point type? */
4780 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4782 if (type
->code () == TYPE_CODE_FLT
)
4784 /* Structs with a single field of float type
4785 are returned in a floating point register. */
4786 if ((type
->code () == TYPE_CODE_STRUCT
4787 || type
->code () == TYPE_CODE_UNION
)
4788 && type
->num_fields () == 1)
4790 struct type
*fieldtype
= type
->field (0).type ();
4792 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4799 /* A floating-point value belongs in the least significant part
4802 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4803 regnum
= mips_regnum (gdbarch
)->fp0
;
4807 /* An integer value goes in V0/V1. */
4809 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4810 regnum
= MIPS_V0_REGNUM
;
4813 offset
< TYPE_LENGTH (type
);
4814 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4816 xfer
= mips_abi_regsize (gdbarch
);
4817 if (offset
+ xfer
> TYPE_LENGTH (type
))
4818 xfer
= TYPE_LENGTH (type
) - offset
;
4819 mips_xfer_register (gdbarch
, regcache
,
4820 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4821 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4825 return RETURN_VALUE_REGISTER_CONVENTION
;
4829 /* N32/N64 ABI stuff. */
4831 /* Search for a naturally aligned double at OFFSET inside a struct
4832 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4836 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4841 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4844 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4847 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4850 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4853 struct type
*field_type
;
4855 /* We're only looking at normal fields. */
4856 if (field_is_static (&arg_type
->field (i
))
4857 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4860 /* If we have gone past the offset, there is no double to pass. */
4861 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4865 field_type
= check_typedef (arg_type
->field (i
).type ());
4867 /* If this field is entirely before the requested offset, go
4868 on to the next one. */
4869 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4872 /* If this is our special aligned double, we can stop. */
4873 if (field_type
->code () == TYPE_CODE_FLT
4874 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4877 /* This field starts at or before the requested offset, and
4878 overlaps it. If it is a structure, recurse inwards. */
4879 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4886 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4887 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4888 int nargs
, struct value
**args
, CORE_ADDR sp
,
4889 function_call_return_method return_method
,
4890 CORE_ADDR struct_addr
)
4896 int stack_offset
= 0;
4897 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4898 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4900 /* For shared libraries, "t9" needs to point at the function
4902 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4904 /* Set the return address register to point to the entry point of
4905 the program, where a breakpoint lies in wait. */
4906 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4908 /* First ensure that the stack and structure return address (if any)
4909 are properly aligned. The stack has to be at least 64-bit
4910 aligned even on 32-bit machines, because doubles must be 64-bit
4911 aligned. For n32 and n64, stack frames need to be 128-bit
4912 aligned, so we round to this widest known alignment. */
4914 sp
= align_down (sp
, 16);
4915 struct_addr
= align_down (struct_addr
, 16);
4917 /* Now make space on the stack for the args. */
4918 for (argnum
= 0; argnum
< nargs
; argnum
++)
4919 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4920 sp
-= align_up (arg_space
, 16);
4923 fprintf_unfiltered (gdb_stdlog
,
4924 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4925 paddress (gdbarch
, sp
),
4926 (long) align_up (arg_space
, 16));
4928 /* Initialize the integer and float register pointers. */
4929 argreg
= MIPS_A0_REGNUM
;
4930 float_argreg
= mips_fpa0_regnum (gdbarch
);
4932 /* The struct_return pointer occupies the first parameter-passing reg. */
4933 if (return_method
== return_method_struct
)
4936 fprintf_unfiltered (gdb_stdlog
,
4937 "mips_n32n64_push_dummy_call: "
4938 "struct_return reg=%d %s\n",
4939 argreg
, paddress (gdbarch
, struct_addr
));
4940 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4943 /* Now load as many as possible of the first arguments into
4944 registers, and push the rest onto the stack. Loop thru args
4945 from first to last. */
4946 for (argnum
= 0; argnum
< nargs
; argnum
++)
4948 const gdb_byte
*val
;
4949 struct value
*arg
= args
[argnum
];
4950 struct type
*arg_type
= check_typedef (value_type (arg
));
4951 int len
= TYPE_LENGTH (arg_type
);
4952 enum type_code typecode
= arg_type
->code ();
4955 fprintf_unfiltered (gdb_stdlog
,
4956 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4957 argnum
+ 1, len
, (int) typecode
);
4959 val
= value_contents (arg
);
4961 /* A 128-bit long double value requires an even-odd pair of
4962 floating-point registers. */
4964 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4965 && (float_argreg
& 1))
4971 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4972 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4974 /* This is a floating point value that fits entirely
4975 in a single register or a pair of registers. */
4976 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4977 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4979 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4980 float_argreg
, phex (regval
, reglen
));
4981 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4984 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4985 argreg
, phex (regval
, reglen
));
4986 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4991 regval
= extract_unsigned_integer (val
+ reglen
,
4992 reglen
, byte_order
);
4994 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4995 float_argreg
, phex (regval
, reglen
));
4996 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4999 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5000 argreg
, phex (regval
, reglen
));
5001 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5008 /* Copy the argument to general registers or the stack in
5009 register-sized pieces. Large arguments are split between
5010 registers and stack. */
5011 /* For N32/N64, structs, unions, or other composite types are
5012 treated as a sequence of doublewords, and are passed in integer
5013 or floating point registers as though they were simple scalar
5014 parameters to the extent that they fit, with any excess on the
5015 stack packed according to the normal memory layout of the
5017 The caller does not reserve space for the register arguments;
5018 the callee is responsible for reserving it if required. */
5019 /* Note: Floating-point values that didn't fit into an FP
5020 register are only written to memory. */
5023 /* Remember if the argument was written to the stack. */
5024 int stack_used_p
= 0;
5025 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5028 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5031 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5032 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5034 /* Write this portion of the argument to the stack. */
5035 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5037 /* Should shorter than int integer values be
5038 promoted to int before being stored? */
5039 int longword_offset
= 0;
5042 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5044 if ((typecode
== TYPE_CODE_INT
5045 || typecode
== TYPE_CODE_PTR
)
5047 longword_offset
= MIPS64_REGSIZE
- len
;
5052 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5053 paddress (gdbarch
, stack_offset
));
5054 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5055 paddress (gdbarch
, longword_offset
));
5058 addr
= sp
+ stack_offset
+ longword_offset
;
5063 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5064 paddress (gdbarch
, addr
));
5065 for (i
= 0; i
< partial_len
; i
++)
5067 fprintf_unfiltered (gdb_stdlog
, "%02x",
5071 write_memory (addr
, val
, partial_len
);
5074 /* Note!!! This is NOT an else clause. Odd sized
5075 structs may go thru BOTH paths. */
5076 /* Write this portion of the argument to a general
5077 purpose register. */
5078 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5082 /* Sign extend pointers, 32-bit integers and signed
5083 16-bit and 8-bit integers; everything else is taken
5086 if ((partial_len
== 4
5087 && (typecode
== TYPE_CODE_PTR
5088 || typecode
== TYPE_CODE_INT
))
5090 && typecode
== TYPE_CODE_INT
5091 && !arg_type
->is_unsigned ()))
5092 regval
= extract_signed_integer (val
, partial_len
,
5095 regval
= extract_unsigned_integer (val
, partial_len
,
5098 /* A non-floating-point argument being passed in a
5099 general register. If a struct or union, and if
5100 the remaining length is smaller than the register
5101 size, we have to adjust the register value on
5104 It does not seem to be necessary to do the
5105 same for integral types. */
5107 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5108 && partial_len
< MIPS64_REGSIZE
5109 && (typecode
== TYPE_CODE_STRUCT
5110 || typecode
== TYPE_CODE_UNION
))
5111 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5115 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5117 phex (regval
, MIPS64_REGSIZE
));
5118 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5120 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5121 TYPE_LENGTH (arg_type
) - len
))
5124 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5126 phex (regval
, MIPS64_REGSIZE
));
5127 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5138 /* Compute the offset into the stack at which we will
5139 copy the next parameter.
5141 In N32 (N64?), the stack_offset only needs to be
5142 adjusted when it has been used. */
5145 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5149 fprintf_unfiltered (gdb_stdlog
, "\n");
5152 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5154 /* Return adjusted stack pointer. */
5158 static enum return_value_convention
5159 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5160 struct type
*type
, struct regcache
*regcache
,
5161 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5163 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5165 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5167 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5168 if needed), as appropriate for the type. Composite results (struct,
5169 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5172 * A struct with only one or two floating point fields is returned in $f0
5173 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5176 * Any other composite results of at most 128 bits are returned in
5177 $2 (first 64 bits) and $3 (remainder, if necessary).
5179 * Larger composite results are handled by converting the function to a
5180 procedure with an implicit first parameter, which is a pointer to an area
5181 reserved by the caller to receive the result. [The o32-bit ABI requires
5182 that all composite results be handled by conversion to implicit first
5183 parameters. The MIPS/SGI Fortran implementation has always made a
5184 specific exception to return COMPLEX results in the floating point
5187 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5188 return RETURN_VALUE_STRUCT_CONVENTION
;
5189 else if (type
->code () == TYPE_CODE_FLT
5190 && TYPE_LENGTH (type
) == 16
5191 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5193 /* A 128-bit floating-point value fills both $f0 and $f2. The
5194 two registers are used in the same as memory order, so the
5195 eight bytes with the lower memory address are in $f0. */
5197 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5198 mips_xfer_register (gdbarch
, regcache
,
5199 (gdbarch_num_regs (gdbarch
)
5200 + mips_regnum (gdbarch
)->fp0
),
5201 8, gdbarch_byte_order (gdbarch
),
5202 readbuf
, writebuf
, 0);
5203 mips_xfer_register (gdbarch
, regcache
,
5204 (gdbarch_num_regs (gdbarch
)
5205 + mips_regnum (gdbarch
)->fp0
+ 2),
5206 8, gdbarch_byte_order (gdbarch
),
5207 readbuf
? readbuf
+ 8 : readbuf
,
5208 writebuf
? writebuf
+ 8 : writebuf
, 0);
5209 return RETURN_VALUE_REGISTER_CONVENTION
;
5211 else if (type
->code () == TYPE_CODE_FLT
5212 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5214 /* A single or double floating-point value that fits in FP0. */
5216 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5217 mips_xfer_register (gdbarch
, regcache
,
5218 (gdbarch_num_regs (gdbarch
)
5219 + mips_regnum (gdbarch
)->fp0
),
5221 gdbarch_byte_order (gdbarch
),
5222 readbuf
, writebuf
, 0);
5223 return RETURN_VALUE_REGISTER_CONVENTION
;
5225 else if (type
->code () == TYPE_CODE_STRUCT
5226 && type
->num_fields () <= 2
5227 && type
->num_fields () >= 1
5228 && ((type
->num_fields () == 1
5229 && (check_typedef (type
->field (0).type ())->code ()
5231 || (type
->num_fields () == 2
5232 && (check_typedef (type
->field (0).type ())->code ()
5234 && (check_typedef (type
->field (1).type ())->code ()
5235 == TYPE_CODE_FLT
))))
5237 /* A struct that contains one or two floats. Each value is part
5238 in the least significant part of their floating point
5239 register (or GPR, for soft float). */
5242 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5243 ? mips_regnum (gdbarch
)->fp0
5245 field
< type
->num_fields (); field
++, regnum
+= 2)
5247 int offset
= (FIELD_BITPOS (type
->field (field
))
5250 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5252 if (TYPE_LENGTH (type
->field (field
).type ()) == 16)
5254 /* A 16-byte long double field goes in two consecutive
5256 mips_xfer_register (gdbarch
, regcache
,
5257 gdbarch_num_regs (gdbarch
) + regnum
,
5259 gdbarch_byte_order (gdbarch
),
5260 readbuf
, writebuf
, offset
);
5261 mips_xfer_register (gdbarch
, regcache
,
5262 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5264 gdbarch_byte_order (gdbarch
),
5265 readbuf
, writebuf
, offset
+ 8);
5268 mips_xfer_register (gdbarch
, regcache
,
5269 gdbarch_num_regs (gdbarch
) + regnum
,
5270 TYPE_LENGTH (type
->field (field
).type ()),
5271 gdbarch_byte_order (gdbarch
),
5272 readbuf
, writebuf
, offset
);
5274 return RETURN_VALUE_REGISTER_CONVENTION
;
5276 else if (type
->code () == TYPE_CODE_STRUCT
5277 || type
->code () == TYPE_CODE_UNION
5278 || type
->code () == TYPE_CODE_ARRAY
)
5280 /* A composite type. Extract the left justified value,
5281 regardless of the byte order. I.e. DO NOT USE
5285 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5286 offset
< TYPE_LENGTH (type
);
5287 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5289 int xfer
= register_size (gdbarch
, regnum
);
5290 if (offset
+ xfer
> TYPE_LENGTH (type
))
5291 xfer
= TYPE_LENGTH (type
) - offset
;
5293 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5294 offset
, xfer
, regnum
);
5295 mips_xfer_register (gdbarch
, regcache
,
5296 gdbarch_num_regs (gdbarch
) + regnum
,
5297 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5300 return RETURN_VALUE_REGISTER_CONVENTION
;
5304 /* A scalar extract each part but least-significant-byte
5308 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5309 offset
< TYPE_LENGTH (type
);
5310 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5312 int xfer
= register_size (gdbarch
, regnum
);
5313 if (offset
+ xfer
> TYPE_LENGTH (type
))
5314 xfer
= TYPE_LENGTH (type
) - offset
;
5316 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5317 offset
, xfer
, regnum
);
5318 mips_xfer_register (gdbarch
, regcache
,
5319 gdbarch_num_regs (gdbarch
) + regnum
,
5320 xfer
, gdbarch_byte_order (gdbarch
),
5321 readbuf
, writebuf
, offset
);
5323 return RETURN_VALUE_REGISTER_CONVENTION
;
5327 /* Which registers to use for passing floating-point values between
5328 function calls, one of floating-point, general and both kinds of
5329 registers. O32 and O64 use different register kinds for standard
5330 MIPS and MIPS16 code; to make the handling of cases where we may
5331 not know what kind of code is being used (e.g. no debug information)
5332 easier we sometimes use both kinds. */
5341 /* O32 ABI stuff. */
5344 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5345 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5346 int nargs
, struct value
**args
, CORE_ADDR sp
,
5347 function_call_return_method return_method
,
5348 CORE_ADDR struct_addr
)
5354 int stack_offset
= 0;
5355 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5356 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5358 /* For shared libraries, "t9" needs to point at the function
5360 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5362 /* Set the return address register to point to the entry point of
5363 the program, where a breakpoint lies in wait. */
5364 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5366 /* First ensure that the stack and structure return address (if any)
5367 are properly aligned. The stack has to be at least 64-bit
5368 aligned even on 32-bit machines, because doubles must be 64-bit
5369 aligned. For n32 and n64, stack frames need to be 128-bit
5370 aligned, so we round to this widest known alignment. */
5372 sp
= align_down (sp
, 16);
5373 struct_addr
= align_down (struct_addr
, 16);
5375 /* Now make space on the stack for the args. */
5376 for (argnum
= 0; argnum
< nargs
; argnum
++)
5378 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5380 /* Align to double-word if necessary. */
5381 if (mips_type_needs_double_align (arg_type
))
5382 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5383 /* Allocate space on the stack. */
5384 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5386 sp
-= align_up (arg_space
, 16);
5389 fprintf_unfiltered (gdb_stdlog
,
5390 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5391 paddress (gdbarch
, sp
),
5392 (long) align_up (arg_space
, 16));
5394 /* Initialize the integer and float register pointers. */
5395 argreg
= MIPS_A0_REGNUM
;
5396 float_argreg
= mips_fpa0_regnum (gdbarch
);
5398 /* The struct_return pointer occupies the first parameter-passing reg. */
5399 if (return_method
== return_method_struct
)
5402 fprintf_unfiltered (gdb_stdlog
,
5403 "mips_o32_push_dummy_call: "
5404 "struct_return reg=%d %s\n",
5405 argreg
, paddress (gdbarch
, struct_addr
));
5406 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5407 stack_offset
+= MIPS32_REGSIZE
;
5410 /* Now load as many as possible of the first arguments into
5411 registers, and push the rest onto the stack. Loop thru args
5412 from first to last. */
5413 for (argnum
= 0; argnum
< nargs
; argnum
++)
5415 const gdb_byte
*val
;
5416 struct value
*arg
= args
[argnum
];
5417 struct type
*arg_type
= check_typedef (value_type (arg
));
5418 int len
= TYPE_LENGTH (arg_type
);
5419 enum type_code typecode
= arg_type
->code ();
5422 fprintf_unfiltered (gdb_stdlog
,
5423 "mips_o32_push_dummy_call: %d len=%d type=%d",
5424 argnum
+ 1, len
, (int) typecode
);
5426 val
= value_contents (arg
);
5428 /* 32-bit ABIs always start floating point arguments in an
5429 even-numbered floating point register. Round the FP register
5430 up before the check to see if there are any FP registers
5431 left. O32 targets also pass the FP in the integer registers
5432 so also round up normal registers. */
5433 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5435 if ((float_argreg
& 1))
5439 /* Floating point arguments passed in registers have to be
5440 treated specially. On 32-bit architectures, doubles are
5441 passed in register pairs; the even FP register gets the
5442 low word, and the odd FP register gets the high word.
5443 On O32, the first two floating point arguments are also
5444 copied to general registers, following their memory order,
5445 because MIPS16 functions don't use float registers for
5446 arguments. This duplication of arguments in general
5447 registers can't hurt non-MIPS16 functions, because those
5448 registers are normally skipped. */
5450 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5451 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5453 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5455 int freg_offset
= gdbarch_byte_order (gdbarch
)
5456 == BFD_ENDIAN_BIG
? 1 : 0;
5457 unsigned long regval
;
5460 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5462 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5463 float_argreg
+ freg_offset
,
5465 regcache_cooked_write_unsigned (regcache
,
5466 float_argreg
++ + freg_offset
,
5469 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5470 argreg
, phex (regval
, 4));
5471 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5474 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5476 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5477 float_argreg
- freg_offset
,
5479 regcache_cooked_write_unsigned (regcache
,
5480 float_argreg
++ - freg_offset
,
5483 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5484 argreg
, phex (regval
, 4));
5485 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5489 /* This is a floating point value that fits entirely
5490 in a single register. */
5491 /* On 32 bit ABI's the float_argreg is further adjusted
5492 above to ensure that it is even register aligned. */
5493 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5495 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5496 float_argreg
, phex (regval
, len
));
5497 regcache_cooked_write_unsigned (regcache
,
5498 float_argreg
++, regval
);
5499 /* Although two FP registers are reserved for each
5500 argument, only one corresponding integer register is
5503 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5504 argreg
, phex (regval
, len
));
5505 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5507 /* Reserve space for the FP register. */
5508 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5512 /* Copy the argument to general registers or the stack in
5513 register-sized pieces. Large arguments are split between
5514 registers and stack. */
5515 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5516 are treated specially: Irix cc passes
5517 them in registers where gcc sometimes puts them on the
5518 stack. For maximum compatibility, we will put them in
5520 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5521 && len
% MIPS32_REGSIZE
!= 0);
5522 /* Structures should be aligned to eight bytes (even arg registers)
5523 on MIPS_ABI_O32, if their first member has double precision. */
5524 if (mips_type_needs_double_align (arg_type
))
5529 stack_offset
+= MIPS32_REGSIZE
;
5534 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5537 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5540 /* Write this portion of the argument to the stack. */
5541 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5542 || odd_sized_struct
)
5544 /* Should shorter than int integer values be
5545 promoted to int before being stored? */
5546 int longword_offset
= 0;
5551 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5552 paddress (gdbarch
, stack_offset
));
5553 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5554 paddress (gdbarch
, longword_offset
));
5557 addr
= sp
+ stack_offset
+ longword_offset
;
5562 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5563 paddress (gdbarch
, addr
));
5564 for (i
= 0; i
< partial_len
; i
++)
5566 fprintf_unfiltered (gdb_stdlog
, "%02x",
5570 write_memory (addr
, val
, partial_len
);
5573 /* Note!!! This is NOT an else clause. Odd sized
5574 structs may go thru BOTH paths. */
5575 /* Write this portion of the argument to a general
5576 purpose register. */
5577 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5579 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5581 /* Value may need to be sign extended, because
5582 mips_isa_regsize() != mips_abi_regsize(). */
5584 /* A non-floating-point argument being passed in a
5585 general register. If a struct or union, and if
5586 the remaining length is smaller than the register
5587 size, we have to adjust the register value on
5590 It does not seem to be necessary to do the
5591 same for integral types.
5593 Also don't do this adjustment on O64 binaries.
5595 cagney/2001-07-23: gdb/179: Also, GCC, when
5596 outputting LE O32 with sizeof (struct) <
5597 mips_abi_regsize(), generates a left shift
5598 as part of storing the argument in a register
5599 (the left shift isn't generated when
5600 sizeof (struct) >= mips_abi_regsize()). Since
5601 it is quite possible that this is GCC
5602 contradicting the LE/O32 ABI, GDB has not been
5603 adjusted to accommodate this. Either someone
5604 needs to demonstrate that the LE/O32 ABI
5605 specifies such a left shift OR this new ABI gets
5606 identified as such and GDB gets tweaked
5609 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5610 && partial_len
< MIPS32_REGSIZE
5611 && (typecode
== TYPE_CODE_STRUCT
5612 || typecode
== TYPE_CODE_UNION
))
5613 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5617 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5619 phex (regval
, MIPS32_REGSIZE
));
5620 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5623 /* Prevent subsequent floating point arguments from
5624 being passed in floating point registers. */
5625 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5631 /* Compute the offset into the stack at which we will
5632 copy the next parameter.
5634 In older ABIs, the caller reserved space for
5635 registers that contained arguments. This was loosely
5636 refered to as their "home". Consequently, space is
5637 always allocated. */
5639 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5643 fprintf_unfiltered (gdb_stdlog
, "\n");
5646 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5648 /* Return adjusted stack pointer. */
5652 static enum return_value_convention
5653 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5654 struct type
*type
, struct regcache
*regcache
,
5655 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5657 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5658 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5659 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5660 enum mips_fval_reg fval_reg
;
5662 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5663 if (type
->code () == TYPE_CODE_STRUCT
5664 || type
->code () == TYPE_CODE_UNION
5665 || type
->code () == TYPE_CODE_ARRAY
)
5666 return RETURN_VALUE_STRUCT_CONVENTION
;
5667 else if (type
->code () == TYPE_CODE_FLT
5668 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5670 /* A single-precision floating-point value. If reading in or copying,
5671 then we get it from/put it to FP0 for standard MIPS code or GPR2
5672 for MIPS16 code. If writing out only, then we put it to both FP0
5673 and GPR2. We do not support reading in with no function known, if
5674 this safety check ever triggers, then we'll have to try harder. */
5675 gdb_assert (function
|| !readbuf
);
5680 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5683 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5685 case mips_fval_both
:
5686 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5689 if (fval_reg
!= mips_fval_gpr
)
5690 mips_xfer_register (gdbarch
, regcache
,
5691 (gdbarch_num_regs (gdbarch
)
5692 + mips_regnum (gdbarch
)->fp0
),
5694 gdbarch_byte_order (gdbarch
),
5695 readbuf
, writebuf
, 0);
5696 if (fval_reg
!= mips_fval_fpr
)
5697 mips_xfer_register (gdbarch
, regcache
,
5698 gdbarch_num_regs (gdbarch
) + 2,
5700 gdbarch_byte_order (gdbarch
),
5701 readbuf
, writebuf
, 0);
5702 return RETURN_VALUE_REGISTER_CONVENTION
;
5704 else if (type
->code () == TYPE_CODE_FLT
5705 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5707 /* A double-precision floating-point value. If reading in or copying,
5708 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5709 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5710 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5711 no function known, if this safety check ever triggers, then we'll
5712 have to try harder. */
5713 gdb_assert (function
|| !readbuf
);
5718 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5721 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5723 case mips_fval_both
:
5724 fprintf_unfiltered (gdb_stderr
,
5725 "Return float in $fp1/$fp0 and $2/$3\n");
5728 if (fval_reg
!= mips_fval_gpr
)
5730 /* The most significant part goes in FP1, and the least significant
5732 switch (gdbarch_byte_order (gdbarch
))
5734 case BFD_ENDIAN_LITTLE
:
5735 mips_xfer_register (gdbarch
, regcache
,
5736 (gdbarch_num_regs (gdbarch
)
5737 + mips_regnum (gdbarch
)->fp0
+ 0),
5738 4, gdbarch_byte_order (gdbarch
),
5739 readbuf
, writebuf
, 0);
5740 mips_xfer_register (gdbarch
, regcache
,
5741 (gdbarch_num_regs (gdbarch
)
5742 + mips_regnum (gdbarch
)->fp0
+ 1),
5743 4, gdbarch_byte_order (gdbarch
),
5744 readbuf
, writebuf
, 4);
5746 case BFD_ENDIAN_BIG
:
5747 mips_xfer_register (gdbarch
, regcache
,
5748 (gdbarch_num_regs (gdbarch
)
5749 + mips_regnum (gdbarch
)->fp0
+ 1),
5750 4, gdbarch_byte_order (gdbarch
),
5751 readbuf
, writebuf
, 0);
5752 mips_xfer_register (gdbarch
, regcache
,
5753 (gdbarch_num_regs (gdbarch
)
5754 + mips_regnum (gdbarch
)->fp0
+ 0),
5755 4, gdbarch_byte_order (gdbarch
),
5756 readbuf
, writebuf
, 4);
5759 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5762 if (fval_reg
!= mips_fval_fpr
)
5764 /* The two 32-bit parts are always placed in GPR2 and GPR3
5765 following these registers' memory order. */
5766 mips_xfer_register (gdbarch
, regcache
,
5767 gdbarch_num_regs (gdbarch
) + 2,
5768 4, gdbarch_byte_order (gdbarch
),
5769 readbuf
, writebuf
, 0);
5770 mips_xfer_register (gdbarch
, regcache
,
5771 gdbarch_num_regs (gdbarch
) + 3,
5772 4, gdbarch_byte_order (gdbarch
),
5773 readbuf
, writebuf
, 4);
5775 return RETURN_VALUE_REGISTER_CONVENTION
;
5778 else if (type
->code () == TYPE_CODE_STRUCT
5779 && type
->num_fields () <= 2
5780 && type
->num_fields () >= 1
5781 && ((type
->num_fields () == 1
5782 && (TYPE_CODE (type
->field (0).type ())
5784 || (type
->num_fields () == 2
5785 && (TYPE_CODE (type
->field (0).type ())
5787 && (TYPE_CODE (type
->field (1).type ())
5789 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5791 /* A struct that contains one or two floats. Each value is part
5792 in the least significant part of their floating point
5796 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5797 field
< type
->num_fields (); field
++, regnum
+= 2)
5799 int offset
= (FIELD_BITPOS (type
->fields ()[field
])
5802 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5804 mips_xfer_register (gdbarch
, regcache
,
5805 gdbarch_num_regs (gdbarch
) + regnum
,
5806 TYPE_LENGTH (type
->field (field
).type ()),
5807 gdbarch_byte_order (gdbarch
),
5808 readbuf
, writebuf
, offset
);
5810 return RETURN_VALUE_REGISTER_CONVENTION
;
5814 else if (type
->code () == TYPE_CODE_STRUCT
5815 || type
->code () == TYPE_CODE_UNION
)
5817 /* A structure or union. Extract the left justified value,
5818 regardless of the byte order. I.e. DO NOT USE
5822 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5823 offset
< TYPE_LENGTH (type
);
5824 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5826 int xfer
= register_size (gdbarch
, regnum
);
5827 if (offset
+ xfer
> TYPE_LENGTH (type
))
5828 xfer
= TYPE_LENGTH (type
) - offset
;
5830 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5831 offset
, xfer
, regnum
);
5832 mips_xfer_register (gdbarch
, regcache
,
5833 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5834 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5836 return RETURN_VALUE_REGISTER_CONVENTION
;
5841 /* A scalar extract each part but least-significant-byte
5842 justified. o32 thinks registers are 4 byte, regardless of
5846 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5847 offset
< TYPE_LENGTH (type
);
5848 offset
+= MIPS32_REGSIZE
, regnum
++)
5850 int xfer
= MIPS32_REGSIZE
;
5851 if (offset
+ xfer
> TYPE_LENGTH (type
))
5852 xfer
= TYPE_LENGTH (type
) - offset
;
5854 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5855 offset
, xfer
, regnum
);
5856 mips_xfer_register (gdbarch
, regcache
,
5857 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5858 gdbarch_byte_order (gdbarch
),
5859 readbuf
, writebuf
, offset
);
5861 return RETURN_VALUE_REGISTER_CONVENTION
;
5865 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5869 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5870 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5872 struct value
**args
, CORE_ADDR sp
,
5873 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5879 int stack_offset
= 0;
5880 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5881 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5883 /* For shared libraries, "t9" needs to point at the function
5885 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5887 /* Set the return address register to point to the entry point of
5888 the program, where a breakpoint lies in wait. */
5889 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5891 /* First ensure that the stack and structure return address (if any)
5892 are properly aligned. The stack has to be at least 64-bit
5893 aligned even on 32-bit machines, because doubles must be 64-bit
5894 aligned. For n32 and n64, stack frames need to be 128-bit
5895 aligned, so we round to this widest known alignment. */
5897 sp
= align_down (sp
, 16);
5898 struct_addr
= align_down (struct_addr
, 16);
5900 /* Now make space on the stack for the args. */
5901 for (argnum
= 0; argnum
< nargs
; argnum
++)
5903 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5905 /* Allocate space on the stack. */
5906 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5908 sp
-= align_up (arg_space
, 16);
5911 fprintf_unfiltered (gdb_stdlog
,
5912 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5913 paddress (gdbarch
, sp
),
5914 (long) align_up (arg_space
, 16));
5916 /* Initialize the integer and float register pointers. */
5917 argreg
= MIPS_A0_REGNUM
;
5918 float_argreg
= mips_fpa0_regnum (gdbarch
);
5920 /* The struct_return pointer occupies the first parameter-passing reg. */
5921 if (return_method
== return_method_struct
)
5924 fprintf_unfiltered (gdb_stdlog
,
5925 "mips_o64_push_dummy_call: "
5926 "struct_return reg=%d %s\n",
5927 argreg
, paddress (gdbarch
, struct_addr
));
5928 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5929 stack_offset
+= MIPS64_REGSIZE
;
5932 /* Now load as many as possible of the first arguments into
5933 registers, and push the rest onto the stack. Loop thru args
5934 from first to last. */
5935 for (argnum
= 0; argnum
< nargs
; argnum
++)
5937 const gdb_byte
*val
;
5938 struct value
*arg
= args
[argnum
];
5939 struct type
*arg_type
= check_typedef (value_type (arg
));
5940 int len
= TYPE_LENGTH (arg_type
);
5941 enum type_code typecode
= arg_type
->code ();
5944 fprintf_unfiltered (gdb_stdlog
,
5945 "mips_o64_push_dummy_call: %d len=%d type=%d",
5946 argnum
+ 1, len
, (int) typecode
);
5948 val
= value_contents (arg
);
5950 /* Floating point arguments passed in registers have to be
5951 treated specially. On 32-bit architectures, doubles are
5952 passed in register pairs; the even FP register gets the
5953 low word, and the odd FP register gets the high word.
5954 On O64, the first two floating point arguments are also
5955 copied to general registers, because MIPS16 functions
5956 don't use float registers for arguments. This duplication
5957 of arguments in general registers can't hurt non-MIPS16
5958 functions because those registers are normally skipped. */
5960 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5961 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5963 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5965 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5966 float_argreg
, phex (regval
, len
));
5967 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5969 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5970 argreg
, phex (regval
, len
));
5971 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5973 /* Reserve space for the FP register. */
5974 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5978 /* Copy the argument to general registers or the stack in
5979 register-sized pieces. Large arguments are split between
5980 registers and stack. */
5981 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5982 are treated specially: Irix cc passes them in registers
5983 where gcc sometimes puts them on the stack. For maximum
5984 compatibility, we will put them in both places. */
5985 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5986 && len
% MIPS64_REGSIZE
!= 0);
5989 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5992 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5995 /* Write this portion of the argument to the stack. */
5996 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5997 || odd_sized_struct
)
5999 /* Should shorter than int integer values be
6000 promoted to int before being stored? */
6001 int longword_offset
= 0;
6003 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6005 if ((typecode
== TYPE_CODE_INT
6006 || typecode
== TYPE_CODE_PTR
6007 || typecode
== TYPE_CODE_FLT
)
6009 longword_offset
= MIPS64_REGSIZE
- len
;
6014 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
6015 paddress (gdbarch
, stack_offset
));
6016 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
6017 paddress (gdbarch
, longword_offset
));
6020 addr
= sp
+ stack_offset
+ longword_offset
;
6025 fprintf_unfiltered (gdb_stdlog
, " @%s ",
6026 paddress (gdbarch
, addr
));
6027 for (i
= 0; i
< partial_len
; i
++)
6029 fprintf_unfiltered (gdb_stdlog
, "%02x",
6033 write_memory (addr
, val
, partial_len
);
6036 /* Note!!! This is NOT an else clause. Odd sized
6037 structs may go thru BOTH paths. */
6038 /* Write this portion of the argument to a general
6039 purpose register. */
6040 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6042 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6044 /* Value may need to be sign extended, because
6045 mips_isa_regsize() != mips_abi_regsize(). */
6047 /* A non-floating-point argument being passed in a
6048 general register. If a struct or union, and if
6049 the remaining length is smaller than the register
6050 size, we have to adjust the register value on
6053 It does not seem to be necessary to do the
6054 same for integral types. */
6056 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6057 && partial_len
< MIPS64_REGSIZE
6058 && (typecode
== TYPE_CODE_STRUCT
6059 || typecode
== TYPE_CODE_UNION
))
6060 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6064 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6066 phex (regval
, MIPS64_REGSIZE
));
6067 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6070 /* Prevent subsequent floating point arguments from
6071 being passed in floating point registers. */
6072 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6078 /* Compute the offset into the stack at which we will
6079 copy the next parameter.
6081 In older ABIs, the caller reserved space for
6082 registers that contained arguments. This was loosely
6083 refered to as their "home". Consequently, space is
6084 always allocated. */
6086 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6090 fprintf_unfiltered (gdb_stdlog
, "\n");
6093 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6095 /* Return adjusted stack pointer. */
6099 static enum return_value_convention
6100 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6101 struct type
*type
, struct regcache
*regcache
,
6102 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6104 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6105 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6106 enum mips_fval_reg fval_reg
;
6108 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6109 if (type
->code () == TYPE_CODE_STRUCT
6110 || type
->code () == TYPE_CODE_UNION
6111 || type
->code () == TYPE_CODE_ARRAY
)
6112 return RETURN_VALUE_STRUCT_CONVENTION
;
6113 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6115 /* A floating-point value. If reading in or copying, then we get it
6116 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6117 If writing out only, then we put it to both FP0 and GPR2. We do
6118 not support reading in with no function known, if this safety
6119 check ever triggers, then we'll have to try harder. */
6120 gdb_assert (function
|| !readbuf
);
6125 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6128 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6130 case mips_fval_both
:
6131 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6134 if (fval_reg
!= mips_fval_gpr
)
6135 mips_xfer_register (gdbarch
, regcache
,
6136 (gdbarch_num_regs (gdbarch
)
6137 + mips_regnum (gdbarch
)->fp0
),
6139 gdbarch_byte_order (gdbarch
),
6140 readbuf
, writebuf
, 0);
6141 if (fval_reg
!= mips_fval_fpr
)
6142 mips_xfer_register (gdbarch
, regcache
,
6143 gdbarch_num_regs (gdbarch
) + 2,
6145 gdbarch_byte_order (gdbarch
),
6146 readbuf
, writebuf
, 0);
6147 return RETURN_VALUE_REGISTER_CONVENTION
;
6151 /* A scalar extract each part but least-significant-byte
6155 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6156 offset
< TYPE_LENGTH (type
);
6157 offset
+= MIPS64_REGSIZE
, regnum
++)
6159 int xfer
= MIPS64_REGSIZE
;
6160 if (offset
+ xfer
> TYPE_LENGTH (type
))
6161 xfer
= TYPE_LENGTH (type
) - offset
;
6163 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6164 offset
, xfer
, regnum
);
6165 mips_xfer_register (gdbarch
, regcache
,
6166 gdbarch_num_regs (gdbarch
) + regnum
,
6167 xfer
, gdbarch_byte_order (gdbarch
),
6168 readbuf
, writebuf
, offset
);
6170 return RETURN_VALUE_REGISTER_CONVENTION
;
6174 /* Floating point register management.
6176 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6177 64bit operations, these early MIPS cpus treat fp register pairs
6178 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6179 registers and offer a compatibility mode that emulates the MIPS2 fp
6180 model. When operating in MIPS2 fp compat mode, later cpu's split
6181 double precision floats into two 32-bit chunks and store them in
6182 consecutive fp regs. To display 64-bit floats stored in this
6183 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6184 Throw in user-configurable endianness and you have a real mess.
6186 The way this works is:
6187 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6188 double-precision value will be split across two logical registers.
6189 The lower-numbered logical register will hold the low-order bits,
6190 regardless of the processor's endianness.
6191 - If we are on a 64-bit processor, and we are looking for a
6192 single-precision value, it will be in the low ordered bits
6193 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6194 save slot in memory.
6195 - If we are in 64-bit mode, everything is straightforward.
6197 Note that this code only deals with "live" registers at the top of the
6198 stack. We will attempt to deal with saved registers later, when
6199 the raw/cooked register interface is in place. (We need a general
6200 interface that can deal with dynamic saved register sizes -- fp
6201 regs could be 32 bits wide in one frame and 64 on the frame above
6204 /* Copy a 32-bit single-precision value from the current frame
6205 into rare_buffer. */
6208 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6209 gdb_byte
*rare_buffer
)
6211 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6212 int raw_size
= register_size (gdbarch
, regno
);
6213 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6215 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6216 error (_("can't read register %d (%s)"),
6217 regno
, gdbarch_register_name (gdbarch
, regno
));
6220 /* We have a 64-bit value for this register. Find the low-order
6224 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6229 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6233 memcpy (rare_buffer
, raw_buffer
, 4);
6237 /* Copy a 64-bit double-precision value from the current frame into
6238 rare_buffer. This may include getting half of it from the next
6242 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6243 gdb_byte
*rare_buffer
)
6245 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6246 int raw_size
= register_size (gdbarch
, regno
);
6248 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6250 /* We have a 64-bit value for this register, and we should use
6252 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6253 error (_("can't read register %d (%s)"),
6254 regno
, gdbarch_register_name (gdbarch
, regno
));
6258 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6260 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6261 internal_error (__FILE__
, __LINE__
,
6262 _("mips_read_fp_register_double: bad access to "
6263 "odd-numbered FP register"));
6265 /* mips_read_fp_register_single will find the correct 32 bits from
6267 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6269 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6270 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6274 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6275 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6281 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6283 { /* Do values for FP (float) regs. */
6284 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6285 gdb_byte
*raw_buffer
;
6286 std::string flt_str
, dbl_str
;
6288 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6289 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6293 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6295 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6296 fprintf_filtered (file
, "%*s",
6297 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6300 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6302 struct value_print_options opts
;
6304 /* 4-byte registers: Print hex and floating. Also print even
6305 numbered registers as doubles. */
6306 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6307 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6309 get_formatted_print_options (&opts
, 'x');
6310 print_scalar_formatted (raw_buffer
,
6311 builtin_type (gdbarch
)->builtin_uint32
,
6314 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6316 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6318 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6319 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6321 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6326 struct value_print_options opts
;
6328 /* Eight byte registers: print each one as hex, float and double. */
6329 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6330 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6332 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6333 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6335 get_formatted_print_options (&opts
, 'x');
6336 print_scalar_formatted (raw_buffer
,
6337 builtin_type (gdbarch
)->builtin_uint64
,
6340 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6341 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6346 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6349 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6350 struct value_print_options opts
;
6353 if (mips_float_register_p (gdbarch
, regnum
))
6355 mips_print_fp_register (file
, frame
, regnum
);
6359 val
= get_frame_register_value (frame
, regnum
);
6361 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6363 /* The problem with printing numeric register names (r26, etc.) is that
6364 the user can't use them on input. Probably the best solution is to
6365 fix it so that either the numeric or the funky (a2, etc.) names
6366 are accepted on input. */
6367 if (regnum
< MIPS_NUMREGS
)
6368 fprintf_filtered (file
, "(r%d): ", regnum
);
6370 fprintf_filtered (file
, ": ");
6372 get_formatted_print_options (&opts
, 'x');
6373 value_print_scalar_formatted (val
, &opts
, 0, file
);
6376 /* Print IEEE exception condition bits in FLAGS. */
6379 print_fpu_flags (struct ui_file
*file
, int flags
)
6381 if (flags
& (1 << 0))
6382 fputs_filtered (" inexact", file
);
6383 if (flags
& (1 << 1))
6384 fputs_filtered (" uflow", file
);
6385 if (flags
& (1 << 2))
6386 fputs_filtered (" oflow", file
);
6387 if (flags
& (1 << 3))
6388 fputs_filtered (" div0", file
);
6389 if (flags
& (1 << 4))
6390 fputs_filtered (" inval", file
);
6391 if (flags
& (1 << 5))
6392 fputs_filtered (" unimp", file
);
6393 fputc_filtered ('\n', file
);
6396 /* Print interesting information about the floating point processor
6397 (if present) or emulator. */
6400 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6401 struct frame_info
*frame
, const char *args
)
6403 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6404 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6408 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6409 type
= MIPS_FPU_NONE
;
6411 fprintf_filtered (file
, "fpu type: %s\n",
6412 type
== MIPS_FPU_DOUBLE
? "double-precision"
6413 : type
== MIPS_FPU_SINGLE
? "single-precision"
6416 if (type
== MIPS_FPU_NONE
)
6419 fprintf_filtered (file
, "reg size: %d bits\n",
6420 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6422 fputs_filtered ("cond :", file
);
6423 if (fcs
& (1 << 23))
6424 fputs_filtered (" 0", file
);
6425 for (i
= 1; i
<= 7; i
++)
6426 if (fcs
& (1 << (24 + i
)))
6427 fprintf_filtered (file
, " %d", i
);
6428 fputc_filtered ('\n', file
);
6430 fputs_filtered ("cause :", file
);
6431 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6432 fputs ("mask :", stdout
);
6433 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6434 fputs ("flags :", stdout
);
6435 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6437 fputs_filtered ("rounding: ", file
);
6440 case 0: fputs_filtered ("nearest\n", file
); break;
6441 case 1: fputs_filtered ("zero\n", file
); break;
6442 case 2: fputs_filtered ("+inf\n", file
); break;
6443 case 3: fputs_filtered ("-inf\n", file
); break;
6446 fputs_filtered ("flush :", file
);
6447 if (fcs
& (1 << 21))
6448 fputs_filtered (" nearest", file
);
6449 if (fcs
& (1 << 22))
6450 fputs_filtered (" override", file
);
6451 if (fcs
& (1 << 24))
6452 fputs_filtered (" zero", file
);
6453 if ((fcs
& (0xb << 21)) == 0)
6454 fputs_filtered (" no", file
);
6455 fputc_filtered ('\n', file
);
6457 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6458 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6459 fputc_filtered ('\n', file
);
6461 default_print_float_info (gdbarch
, file
, frame
, args
);
6464 /* Replacement for generic do_registers_info.
6465 Print regs in pretty columns. */
6468 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6471 fprintf_filtered (file
, " ");
6472 mips_print_fp_register (file
, frame
, regnum
);
6473 fprintf_filtered (file
, "\n");
6478 /* Print a row's worth of GP (int) registers, with name labels above. */
6481 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6484 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6485 /* Do values for GP (int) regs. */
6486 const gdb_byte
*raw_buffer
;
6487 struct value
*value
;
6488 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6493 /* For GP registers, we print a separate row of names above the vals. */
6494 for (col
= 0, regnum
= start_regnum
;
6495 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6498 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6499 continue; /* unused register */
6500 if (mips_float_register_p (gdbarch
, regnum
))
6501 break; /* End the row: reached FP register. */
6502 /* Large registers are handled separately. */
6503 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6506 break; /* End the row before this register. */
6508 /* Print this register on a row by itself. */
6509 mips_print_register (file
, frame
, regnum
);
6510 fprintf_filtered (file
, "\n");
6514 fprintf_filtered (file
, " ");
6515 fprintf_filtered (file
,
6516 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6517 gdbarch_register_name (gdbarch
, regnum
));
6524 /* Print the R0 to R31 names. */
6525 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6526 fprintf_filtered (file
, "\n R%-4d",
6527 start_regnum
% gdbarch_num_regs (gdbarch
));
6529 fprintf_filtered (file
, "\n ");
6531 /* Now print the values in hex, 4 or 8 to the row. */
6532 for (col
= 0, regnum
= start_regnum
;
6533 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6536 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6537 continue; /* unused register */
6538 if (mips_float_register_p (gdbarch
, regnum
))
6539 break; /* End row: reached FP register. */
6540 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6541 break; /* End row: large register. */
6543 /* OK: get the data in raw format. */
6544 value
= get_frame_register_value (frame
, regnum
);
6545 if (value_optimized_out (value
)
6546 || !value_entirely_available (value
))
6548 fprintf_filtered (file
, "%*s ",
6549 (int) mips_abi_regsize (gdbarch
) * 2,
6550 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6551 : "<unavailable>"));
6555 raw_buffer
= value_contents_all (value
);
6556 /* pad small registers */
6558 byte
< (mips_abi_regsize (gdbarch
)
6559 - register_size (gdbarch
, regnum
)); byte
++)
6560 fprintf_filtered (file
, " ");
6561 /* Now print the register value in hex, endian order. */
6562 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6564 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6565 byte
< register_size (gdbarch
, regnum
); byte
++)
6566 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6568 for (byte
= register_size (gdbarch
, regnum
) - 1;
6570 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6571 fprintf_filtered (file
, " ");
6574 if (col
> 0) /* ie. if we actually printed anything... */
6575 fprintf_filtered (file
, "\n");
6580 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6583 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6584 struct frame_info
*frame
, int regnum
, int all
)
6586 if (regnum
!= -1) /* Do one specified register. */
6588 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6589 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6590 error (_("Not a valid register for the current processor type"));
6592 mips_print_register (file
, frame
, regnum
);
6593 fprintf_filtered (file
, "\n");
6596 /* Do all (or most) registers. */
6598 regnum
= gdbarch_num_regs (gdbarch
);
6599 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6601 if (mips_float_register_p (gdbarch
, regnum
))
6603 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6604 regnum
= print_fp_register_row (file
, frame
, regnum
);
6606 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6609 regnum
= print_gp_register_row (file
, frame
, regnum
);
6615 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6616 struct frame_info
*frame
)
6618 CORE_ADDR pc
= get_frame_pc (frame
);
6623 if ((mips_pc_is_mips (pc
)
6624 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6625 || (mips_pc_is_micromips (gdbarch
, pc
)
6626 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6627 || (mips_pc_is_mips16 (gdbarch
, pc
)
6628 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6631 isa
= mips_pc_isa (gdbarch
, pc
);
6632 /* _has_delay_slot above will have validated the read. */
6633 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6634 size
= mips_insn_size (isa
, insn
);
6636 const address_space
*aspace
= get_frame_address_space (frame
);
6638 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6641 /* To skip prologues, I use this predicate. Returns either PC itself
6642 if the code at PC does not look like a function prologue; otherwise
6643 returns an address that (if we're lucky) follows the prologue. If
6644 LENIENT, then we must skip everything which is involved in setting
6645 up the frame (it's OK to skip more, just so long as we don't skip
6646 anything which might clobber the registers which are being saved.
6647 We must skip more in the case where part of the prologue is in the
6648 delay slot of a non-prologue instruction). */
6651 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6654 CORE_ADDR func_addr
;
6656 /* See if we can determine the end of the prologue via the symbol table.
6657 If so, then return either PC, or the PC after the prologue, whichever
6659 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6661 CORE_ADDR post_prologue_pc
6662 = skip_prologue_using_sal (gdbarch
, func_addr
);
6663 if (post_prologue_pc
!= 0)
6664 return std::max (pc
, post_prologue_pc
);
6667 /* Can't determine prologue from the symbol table, need to examine
6670 /* Find an upper limit on the function prologue using the debug
6671 information. If the debug information could not be used to provide
6672 that bound, then use an arbitrary large number as the upper bound. */
6673 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6675 limit_pc
= pc
+ 100; /* Magic. */
6677 if (mips_pc_is_mips16 (gdbarch
, pc
))
6678 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6679 else if (mips_pc_is_micromips (gdbarch
, pc
))
6680 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6682 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6685 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6686 This is a helper function for mips_stack_frame_destroyed_p. */
6689 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6691 CORE_ADDR func_addr
= 0, func_end
= 0;
6693 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6695 /* The MIPS epilogue is max. 12 bytes long. */
6696 CORE_ADDR addr
= func_end
- 12;
6698 if (addr
< func_addr
+ 4)
6699 addr
= func_addr
+ 4;
6703 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6705 unsigned long high_word
;
6708 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6709 high_word
= (inst
>> 16) & 0xffff;
6711 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6712 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6713 && inst
!= 0x03e00008 /* jr $ra */
6714 && inst
!= 0x00000000) /* nop */
6724 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6725 This is a helper function for mips_stack_frame_destroyed_p. */
6728 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6730 CORE_ADDR func_addr
= 0;
6731 CORE_ADDR func_end
= 0;
6739 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6742 /* The microMIPS epilogue is max. 12 bytes long. */
6743 addr
= func_end
- 12;
6745 if (addr
< func_addr
+ 2)
6746 addr
= func_addr
+ 2;
6750 for (; pc
< func_end
; pc
+= loc
)
6753 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6754 loc
+= MIPS_INSN16_SIZE
;
6755 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6757 /* 32-bit instructions. */
6758 case 2 * MIPS_INSN16_SIZE
:
6760 insn
|= mips_fetch_instruction (gdbarch
,
6761 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6762 loc
+= MIPS_INSN16_SIZE
;
6763 switch (micromips_op (insn
>> 16))
6765 case 0xc: /* ADDIU: bits 001100 */
6766 case 0x17: /* DADDIU: bits 010111 */
6767 sreg
= b0s5_reg (insn
>> 16);
6768 dreg
= b5s5_reg (insn
>> 16);
6769 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6770 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6771 /* (D)ADDIU $sp, imm */
6781 /* 16-bit instructions. */
6782 case MIPS_INSN16_SIZE
:
6783 switch (micromips_op (insn
))
6785 case 0x3: /* MOVE: bits 000011 */
6786 sreg
= b0s5_reg (insn
);
6787 dreg
= b5s5_reg (insn
);
6788 if (sreg
== 0 && dreg
== 0)
6789 /* MOVE $zero, $zero aka NOP */
6793 case 0x11: /* POOL16C: bits 010001 */
6794 if (b5s5_op (insn
) == 0x18
6795 /* JRADDIUSP: bits 010011 11000 */
6796 || (b5s5_op (insn
) == 0xd
6797 /* JRC: bits 010011 01101 */
6798 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6803 case 0x13: /* POOL16D: bits 010011 */
6804 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6805 if ((insn
& 0x1) == 0x1
6806 /* ADDIUSP: bits 010011 1 */
6820 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6821 This is a helper function for mips_stack_frame_destroyed_p. */
6824 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6826 CORE_ADDR func_addr
= 0, func_end
= 0;
6828 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6830 /* The MIPS epilogue is max. 12 bytes long. */
6831 CORE_ADDR addr
= func_end
- 12;
6833 if (addr
< func_addr
+ 4)
6834 addr
= func_addr
+ 4;
6838 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6840 unsigned short inst
;
6842 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6844 if ((inst
& 0xf800) == 0xf000) /* extend */
6847 if (inst
!= 0x6300 /* addiu $sp,offset */
6848 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6849 && inst
!= 0xe820 /* jr $ra */
6850 && inst
!= 0xe8a0 /* jrc $ra */
6851 && inst
!= 0x6500) /* nop */
6861 /* Implement the stack_frame_destroyed_p gdbarch method.
6863 The epilogue is defined here as the area at the end of a function,
6864 after an instruction which destroys the function's stack frame. */
6867 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6869 if (mips_pc_is_mips16 (gdbarch
, pc
))
6870 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6871 else if (mips_pc_is_micromips (gdbarch
, pc
))
6872 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6874 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6877 /* Commands to show/set the MIPS FPU type. */
6880 show_mipsfpu_command (const char *args
, int from_tty
)
6884 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6887 ("The MIPS floating-point coprocessor is unknown "
6888 "because the current architecture is not MIPS.\n");
6892 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6894 case MIPS_FPU_SINGLE
:
6895 fpu
= "single-precision";
6897 case MIPS_FPU_DOUBLE
:
6898 fpu
= "double-precision";
6901 fpu
= "absent (none)";
6904 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6906 if (mips_fpu_type_auto
)
6907 printf_unfiltered ("The MIPS floating-point coprocessor "
6908 "is set automatically (currently %s)\n",
6912 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6917 set_mipsfpu_single_command (const char *args
, int from_tty
)
6919 struct gdbarch_info info
;
6920 mips_fpu_type
= MIPS_FPU_SINGLE
;
6921 mips_fpu_type_auto
= 0;
6922 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6923 instead of relying on globals. Doing that would let generic code
6924 handle the search for this specific architecture. */
6925 if (!gdbarch_update_p (info
))
6926 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6930 set_mipsfpu_double_command (const char *args
, int from_tty
)
6932 struct gdbarch_info info
;
6933 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6934 mips_fpu_type_auto
= 0;
6935 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6936 instead of relying on globals. Doing that would let generic code
6937 handle the search for this specific architecture. */
6938 if (!gdbarch_update_p (info
))
6939 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6943 set_mipsfpu_none_command (const char *args
, int from_tty
)
6945 struct gdbarch_info info
;
6946 mips_fpu_type
= MIPS_FPU_NONE
;
6947 mips_fpu_type_auto
= 0;
6948 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6949 instead of relying on globals. Doing that would let generic code
6950 handle the search for this specific architecture. */
6951 if (!gdbarch_update_p (info
))
6952 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6956 set_mipsfpu_auto_command (const char *args
, int from_tty
)
6958 mips_fpu_type_auto
= 1;
6961 /* Just like reinit_frame_cache, but with the right arguments to be
6962 callable as an sfunc. */
6965 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
6966 struct cmd_list_element
*c
)
6968 reinit_frame_cache ();
6972 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6974 gdb_disassembler
*di
6975 = static_cast<gdb_disassembler
*>(info
->application_data
);
6976 struct gdbarch
*gdbarch
= di
->arch ();
6978 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6979 disassembler needs to be able to locally determine the ISA, and
6980 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6982 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6983 info
->mach
= bfd_mach_mips16
;
6984 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6985 info
->mach
= bfd_mach_mips_micromips
;
6987 /* Round down the instruction address to the appropriate boundary. */
6988 memaddr
&= (info
->mach
== bfd_mach_mips16
6989 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6991 return default_print_insn (memaddr
, info
);
6994 /* Implement the breakpoint_kind_from_pc gdbarch method. */
6997 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
6999 CORE_ADDR pc
= *pcptr
;
7001 if (mips_pc_is_mips16 (gdbarch
, pc
))
7003 *pcptr
= unmake_compact_addr (pc
);
7004 return MIPS_BP_KIND_MIPS16
;
7006 else if (mips_pc_is_micromips (gdbarch
, pc
))
7011 *pcptr
= unmake_compact_addr (pc
);
7012 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7013 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7014 return MIPS_BP_KIND_MICROMIPS16
;
7016 return MIPS_BP_KIND_MICROMIPS32
;
7019 return MIPS_BP_KIND_MIPS32
;
7022 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7024 static const gdb_byte
*
7025 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7027 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7031 case MIPS_BP_KIND_MIPS16
:
7033 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7034 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7037 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7038 return mips16_big_breakpoint
;
7040 return mips16_little_breakpoint
;
7042 case MIPS_BP_KIND_MICROMIPS16
:
7044 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7045 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7049 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7050 return micromips16_big_breakpoint
;
7052 return micromips16_little_breakpoint
;
7054 case MIPS_BP_KIND_MICROMIPS32
:
7056 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7057 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7060 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7061 return micromips32_big_breakpoint
;
7063 return micromips32_little_breakpoint
;
7065 case MIPS_BP_KIND_MIPS32
:
7067 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7068 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7071 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7072 return big_breakpoint
;
7074 return little_breakpoint
;
7077 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7081 /* Return non-zero if the standard MIPS instruction INST has a branch
7082 delay slot (i.e. it is a jump or branch instruction). This function
7083 is based on mips32_next_pc. */
7086 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7092 op
= itype_op (inst
);
7093 if ((inst
& 0xe0000000) != 0)
7095 rs
= itype_rs (inst
);
7096 rt
= itype_rt (inst
);
7097 return (is_octeon_bbit_op (op
, gdbarch
)
7098 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7099 || op
== 29 /* JALX: bits 011101 */
7102 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7103 || (rs
== 9 && (rt
& 0x2) == 0)
7104 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7105 || (rs
== 10 && (rt
& 0x2) == 0))));
7106 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7109 switch (op
& 0x07) /* extract bits 28,27,26 */
7111 case 0: /* SPECIAL */
7112 op
= rtype_funct (inst
);
7113 return (op
== 8 /* JR */
7114 || op
== 9); /* JALR */
7115 break; /* end SPECIAL */
7116 case 1: /* REGIMM */
7117 rs
= itype_rs (inst
);
7118 rt
= itype_rt (inst
); /* branch condition */
7119 return ((rt
& 0xc) == 0
7120 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7121 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7122 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7123 /* BPOSGE32, BPOSGE64: bits 1110x */
7124 break; /* end REGIMM */
7125 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7131 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7132 delay slot (i.e. it is a jump or branch instruction). */
7135 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7140 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7144 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7147 /* Return non-zero if the microMIPS instruction INSN, comprising the
7148 16-bit major opcode word in the high 16 bits and any second word
7149 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7150 jump or branch instruction). The instruction must be 32-bit if
7151 MUSTBE32 is set or can be any instruction otherwise. */
7154 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7156 ULONGEST major
= insn
>> 16;
7158 switch (micromips_op (major
))
7160 /* 16-bit instructions. */
7161 case 0x33: /* B16: bits 110011 */
7162 case 0x2b: /* BNEZ16: bits 101011 */
7163 case 0x23: /* BEQZ16: bits 100011 */
7165 case 0x11: /* POOL16C: bits 010001 */
7167 && ((b5s5_op (major
) == 0xc
7168 /* JR16: bits 010001 01100 */
7169 || (b5s5_op (major
) & 0x1e) == 0xe)));
7170 /* JALR16, JALRS16: bits 010001 0111x */
7171 /* 32-bit instructions. */
7172 case 0x3d: /* JAL: bits 111101 */
7173 case 0x3c: /* JALX: bits 111100 */
7174 case 0x35: /* J: bits 110101 */
7175 case 0x2d: /* BNE: bits 101101 */
7176 case 0x25: /* BEQ: bits 100101 */
7177 case 0x1d: /* JALS: bits 011101 */
7179 case 0x10: /* POOL32I: bits 010000 */
7180 return ((b5s5_op (major
) & 0x1c) == 0x0
7181 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7182 || (b5s5_op (major
) & 0x1d) == 0x4
7183 /* BLEZ, BGTZ: bits 010000 001x0 */
7184 || (b5s5_op (major
) & 0x1d) == 0x11
7185 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7186 || ((b5s5_op (major
) & 0x1e) == 0x14
7187 && (major
& 0x3) == 0x0)
7188 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7189 || (b5s5_op (major
) & 0x1e) == 0x1a
7190 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7191 || ((b5s5_op (major
) & 0x1e) == 0x1c
7192 && (major
& 0x3) == 0x0)
7193 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7194 || ((b5s5_op (major
) & 0x1c) == 0x1c
7195 && (major
& 0x3) == 0x1));
7196 /* BC1ANY*: bits 010000 111xx xxx01 */
7197 case 0x0: /* POOL32A: bits 000000 */
7198 return (b0s6_op (insn
) == 0x3c
7199 /* POOL32Axf: bits 000000 ... 111100 */
7200 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7201 /* JALR, JALR.HB: 000000 000x111100 111100 */
7202 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7208 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7209 slot (i.e. it is a non-compact jump instruction). The instruction
7210 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7213 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7214 CORE_ADDR addr
, int mustbe32
)
7220 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7223 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7225 if (size
== 2 * MIPS_INSN16_SIZE
)
7227 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7232 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7235 /* Return non-zero if the MIPS16 instruction INST, which must be
7236 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7237 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7238 instruction). This function is based on mips16_next_pc. */
7241 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7243 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7245 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7248 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7249 slot (i.e. it is a non-compact jump instruction). The instruction
7250 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7253 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7254 CORE_ADDR addr
, int mustbe32
)
7256 unsigned short insn
;
7259 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7263 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7266 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7267 This assumes KSSEG exists. */
7270 mips_segment_boundary (CORE_ADDR bpaddr
)
7272 CORE_ADDR mask
= CORE_ADDR_MAX
;
7275 if (sizeof (CORE_ADDR
) == 8)
7276 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7277 a compiler warning produced where CORE_ADDR is a 32-bit type even
7278 though in that case this is dead code). */
7279 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7282 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7283 segsize
= 29; /* 32-bit compatibility segment */
7285 segsize
= 62; /* xkseg */
7287 case 2: /* xkphys */
7290 default: /* xksseg (1), xkuseg/kuseg (0) */
7294 else if (bpaddr
& 0x80000000) /* kernel segment */
7297 segsize
= 31; /* user segment */
7299 return bpaddr
& mask
;
7302 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7303 it backwards if necessary. Return the address of the new location. */
7306 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7308 CORE_ADDR prev_addr
;
7310 CORE_ADDR func_addr
;
7312 /* If a breakpoint is set on the instruction in a branch delay slot,
7313 GDB gets confused. When the breakpoint is hit, the PC isn't on
7314 the instruction in the branch delay slot, the PC will point to
7315 the branch instruction. Since the PC doesn't match any known
7316 breakpoints, GDB reports a trap exception.
7318 There are two possible fixes for this problem.
7320 1) When the breakpoint gets hit, see if the BD bit is set in the
7321 Cause register (which indicates the last exception occurred in a
7322 branch delay slot). If the BD bit is set, fix the PC to point to
7323 the instruction in the branch delay slot.
7325 2) When the user sets the breakpoint, don't allow him to set the
7326 breakpoint on the instruction in the branch delay slot. Instead
7327 move the breakpoint to the branch instruction (which will have
7330 The problem with the first solution is that if the user then
7331 single-steps the processor, the branch instruction will get
7332 skipped (since GDB thinks the PC is on the instruction in the
7335 So, we'll use the second solution. To do this we need to know if
7336 the instruction we're trying to set the breakpoint on is in the
7337 branch delay slot. */
7339 boundary
= mips_segment_boundary (bpaddr
);
7341 /* Make sure we don't scan back before the beginning of the current
7342 function, since we may fetch constant data or insns that look like
7343 a jump. Of course we might do that anyway if the compiler has
7344 moved constants inline. :-( */
7345 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7346 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7347 boundary
= func_addr
;
7349 if (mips_pc_is_mips (bpaddr
))
7351 if (bpaddr
== boundary
)
7354 /* If the previous instruction has a branch delay slot, we have
7355 to move the breakpoint to the branch instruction. */
7356 prev_addr
= bpaddr
- 4;
7357 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7362 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7363 CORE_ADDR addr
, jmpaddr
;
7366 boundary
= unmake_compact_addr (boundary
);
7368 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7369 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7370 so try for that first, then try the 2 byte JALR/JR.
7371 The microMIPS ASE has a whole range of jumps and branches
7372 with delay slots, some of which take 4 bytes and some take
7373 2 bytes, so the idea is the same.
7374 FIXME: We have to assume that bpaddr is not the second half
7375 of an extended instruction. */
7376 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7377 ? micromips_insn_at_pc_has_delay_slot
7378 : mips16_insn_at_pc_has_delay_slot
);
7382 for (i
= 1; i
< 4; i
++)
7384 if (unmake_compact_addr (addr
) == boundary
)
7386 addr
-= MIPS_INSN16_SIZE
;
7387 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7388 /* Looks like a JR/JALR at [target-1], but it could be
7389 the second word of a previous JAL/JALX, so record it
7390 and check back one more. */
7392 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7395 /* Looks like a JAL/JALX at [target-2], but it could also
7396 be the second word of a previous JAL/JALX, record it,
7397 and check back one more. */
7400 /* Looks like a JAL/JALX at [target-3], so any previously
7401 recorded JAL/JALX or JR/JALR must be wrong, because:
7404 -2: JAL-ext (can't be JAL/JALX)
7405 -1: bdslot (can't be JR/JALR)
7408 Of course it could be another JAL-ext which looks
7409 like a JAL, but in that case we'd have broken out
7410 of this loop at [target-2]:
7414 -2: bdslot (can't be jmp)
7421 /* Not a jump instruction: if we're at [target-1] this
7422 could be the second word of a JAL/JALX, so continue;
7423 otherwise we're done. */
7436 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7437 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7440 mips_is_stub_suffix (const char *suffix
, int zero
)
7445 return zero
&& suffix
[1] == '\0';
7447 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7452 return suffix
[1] == '\0';
7458 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7459 call stubs, one of sf, df, sc, or dc. */
7462 mips_is_stub_mode (const char *mode
)
7464 return ((mode
[0] == 's' || mode
[0] == 'd')
7465 && (mode
[1] == 'f' || mode
[1] == 'c'));
7468 /* Code at PC is a compiler-generated stub. Such a stub for a function
7469 bar might have a name like __fn_stub_bar, and might look like this:
7476 followed by (or interspersed with):
7483 addiu $25, $25, %lo(bar)
7486 ($1 may be used in old code; for robustness we accept any register)
7489 lui $28, %hi(_gp_disp)
7490 addiu $28, $28, %lo(_gp_disp)
7493 addiu $25, $25, %lo(bar)
7496 In the case of a __call_stub_bar stub, the sequence to set up
7497 arguments might look like this:
7504 followed by (or interspersed with) one of the jump sequences above.
7506 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7507 of J or JR, respectively, followed by:
7513 We are at the beginning of the stub here, and scan down and extract
7514 the target address from the jump immediate instruction or, if a jump
7515 register instruction is used, from the register referred. Return
7516 the value of PC calculated or 0 if inconclusive.
7518 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7521 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7523 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7524 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7525 int addrreg
= MIPS_ZERO_REGNUM
;
7526 CORE_ADDR start_pc
= pc
;
7527 CORE_ADDR target_pc
= 0;
7534 status
== 0 && target_pc
== 0 && i
< 20;
7535 i
++, pc
+= MIPS_INSN32_SIZE
)
7537 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7543 switch (itype_op (inst
))
7545 case 0: /* SPECIAL */
7546 switch (rtype_funct (inst
))
7550 rs
= rtype_rs (inst
);
7551 if (rs
== MIPS_GP_REGNUM
)
7552 target_pc
= gp
; /* Hmm... */
7553 else if (rs
== addrreg
)
7557 case 0x21: /* ADDU */
7558 rt
= rtype_rt (inst
);
7559 rs
= rtype_rs (inst
);
7560 rd
= rtype_rd (inst
);
7561 if (rd
== MIPS_GP_REGNUM
7562 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7563 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7571 target_pc
= jtype_target (inst
) << 2;
7572 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7576 rt
= itype_rt (inst
);
7577 rs
= itype_rs (inst
);
7580 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7581 if (rt
== MIPS_GP_REGNUM
)
7583 else if (rt
== addrreg
)
7589 rt
= itype_rt (inst
);
7590 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7591 if (rt
== MIPS_GP_REGNUM
)
7593 else if (rt
!= MIPS_ZERO_REGNUM
)
7601 rt
= itype_rt (inst
);
7602 rs
= itype_rs (inst
);
7603 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7604 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7608 memset (buf
, 0, sizeof (buf
));
7609 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7611 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7620 /* If PC is in a MIPS16 call or return stub, return the address of the
7621 target PC, which is either the callee or the caller. There are several
7622 cases which must be handled:
7624 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7625 and the target PC is in $31 ($ra).
7626 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7627 and the target PC is in $2.
7628 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7629 i.e. before the JALR instruction, this is effectively a call stub
7630 and the target PC is in $2. Otherwise this is effectively
7631 a return stub and the target PC is in $18.
7632 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7633 JAL or JALR instruction, this is effectively a call stub and the
7634 target PC is buried in the instruction stream. Otherwise this
7635 is effectively a return stub and the target PC is in $18.
7636 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7637 stub and the target PC is buried in the instruction stream.
7639 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7640 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7644 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7646 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7647 CORE_ADDR start_addr
;
7651 /* Find the starting address and name of the function containing the PC. */
7652 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7655 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7656 and the target PC is in $31 ($ra). */
7657 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7658 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7659 && mips_is_stub_mode (name
+ prefixlen
)
7660 && name
[prefixlen
+ 2] == '\0')
7661 return get_frame_register_signed
7662 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7664 /* If the PC is in __mips16_call_stub_*, this is one of the call
7665 call/return stubs. */
7666 prefixlen
= strlen (mips_str_mips16_call_stub
);
7667 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7669 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7670 and the target PC is in $2. */
7671 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7672 return get_frame_register_signed
7673 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7675 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7676 i.e. before the JALR instruction, this is effectively a call stub
7677 and the target PC is in $2. Otherwise this is effectively
7678 a return stub and the target PC is in $18. */
7679 else if (mips_is_stub_mode (name
+ prefixlen
)
7680 && name
[prefixlen
+ 2] == '_'
7681 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7683 if (pc
== start_addr
)
7684 /* This is the 'call' part of a call stub. The return
7685 address is in $2. */
7686 return get_frame_register_signed
7687 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7689 /* This is the 'return' part of a call stub. The return
7690 address is in $18. */
7691 return get_frame_register_signed
7692 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7695 return 0; /* Not a stub. */
7698 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7699 compiler-generated call or call/return stubs. */
7700 if (startswith (name
, mips_str_fn_stub
)
7701 || startswith (name
, mips_str_call_stub
))
7703 if (pc
== start_addr
)
7704 /* This is the 'call' part of a call stub. Call this helper
7705 to scan through this code for interesting instructions
7706 and determine the final PC. */
7707 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7709 /* This is the 'return' part of a call stub. The return address
7711 return get_frame_register_signed
7712 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7715 return 0; /* Not a stub. */
7718 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7719 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7722 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7724 CORE_ADDR start_addr
;
7727 /* Find the starting address of the function containing the PC. */
7728 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7731 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7732 the start, i.e. after the JALR instruction, this is effectively
7734 prefixlen
= strlen (mips_str_mips16_call_stub
);
7735 if (pc
!= start_addr
7736 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7737 && mips_is_stub_mode (name
+ prefixlen
)
7738 && name
[prefixlen
+ 2] == '_'
7739 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7742 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7743 the JAL or JALR instruction, this is effectively a return stub. */
7744 prefixlen
= strlen (mips_str_call_fp_stub
);
7745 if (pc
!= start_addr
7746 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7749 /* Consume the .pic. prefix of any PIC stub, this function must return
7750 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7751 or the call stub path will trigger in handle_inferior_event causing
7753 prefixlen
= strlen (mips_str_pic
);
7754 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7757 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7758 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7759 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7760 && mips_is_stub_mode (name
+ prefixlen
)
7761 && name
[prefixlen
+ 2] == '\0')
7764 return 0; /* Not a stub. */
7767 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7768 PC of the stub target. The stub just loads $t9 and jumps to it,
7769 so that $t9 has the correct value at function entry. */
7772 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7774 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7775 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7776 struct bound_minimal_symbol msym
;
7778 gdb_byte stub_code
[16];
7779 int32_t stub_words
[4];
7781 /* The stub for foo is named ".pic.foo", and is either two
7782 instructions inserted before foo or a three instruction sequence
7783 which jumps to foo. */
7784 msym
= lookup_minimal_symbol_by_pc (pc
);
7785 if (msym
.minsym
== NULL
7786 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7787 || msym
.minsym
->linkage_name () == NULL
7788 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7791 /* A two-instruction header. */
7792 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7795 /* A three-instruction (plus delay slot) trampoline. */
7796 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7798 if (target_read_memory (pc
, stub_code
, 16) != 0)
7800 for (i
= 0; i
< 4; i
++)
7801 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7804 /* A stub contains these instructions:
7807 addiu t9, t9, %lo(target)
7810 This works even for N64, since stubs are only generated with
7812 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7813 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7814 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7815 && stub_words
[3] == 0x00000000)
7816 return ((((stub_words
[0] & 0x0000ffff) << 16)
7817 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7820 /* Not a recognized stub. */
7825 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7827 CORE_ADDR requested_pc
= pc
;
7828 CORE_ADDR target_pc
;
7835 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7839 new_pc
= find_solib_trampoline_target (frame
, pc
);
7843 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7847 while (pc
!= target_pc
);
7849 return pc
!= requested_pc
? pc
: 0;
7852 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7853 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7856 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7859 if (num
>= 0 && num
< 32)
7861 else if (num
>= 38 && num
< 70)
7862 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7864 regnum
= mips_regnum (gdbarch
)->hi
;
7866 regnum
= mips_regnum (gdbarch
)->lo
;
7867 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7868 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7871 return gdbarch_num_regs (gdbarch
) + regnum
;
7875 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7876 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7879 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7882 if (num
>= 0 && num
< 32)
7884 else if (num
>= 32 && num
< 64)
7885 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7887 regnum
= mips_regnum (gdbarch
)->hi
;
7889 regnum
= mips_regnum (gdbarch
)->lo
;
7890 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7891 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7894 return gdbarch_num_regs (gdbarch
) + regnum
;
7898 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7900 /* Only makes sense to supply raw registers. */
7901 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7902 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7903 decide if it is valid. Should instead define a standard sim/gdb
7904 register numbering scheme. */
7905 if (gdbarch_register_name (gdbarch
,
7906 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7907 && gdbarch_register_name (gdbarch
,
7908 gdbarch_num_regs (gdbarch
)
7909 + regnum
)[0] != '\0')
7912 return LEGACY_SIM_REGNO_IGNORE
;
7916 /* Convert an integer into an address. Extracting the value signed
7917 guarantees a correctly sign extended address. */
7920 mips_integer_to_address (struct gdbarch
*gdbarch
,
7921 struct type
*type
, const gdb_byte
*buf
)
7923 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7924 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7927 /* Dummy virtual frame pointer method. This is no more or less accurate
7928 than most other architectures; we just need to be explicit about it,
7929 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7930 an assertion failure. */
7933 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7934 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7936 *reg
= MIPS_SP_REGNUM
;
7941 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7943 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7944 const char *name
= bfd_section_name (sect
);
7946 if (*abip
!= MIPS_ABI_UNKNOWN
)
7949 if (!startswith (name
, ".mdebug."))
7952 if (strcmp (name
, ".mdebug.abi32") == 0)
7953 *abip
= MIPS_ABI_O32
;
7954 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7955 *abip
= MIPS_ABI_N32
;
7956 else if (strcmp (name
, ".mdebug.abi64") == 0)
7957 *abip
= MIPS_ABI_N64
;
7958 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7959 *abip
= MIPS_ABI_O64
;
7960 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7961 *abip
= MIPS_ABI_EABI32
;
7962 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7963 *abip
= MIPS_ABI_EABI64
;
7965 warning (_("unsupported ABI %s."), name
+ 8);
7969 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7971 int *lbp
= (int *) obj
;
7972 const char *name
= bfd_section_name (sect
);
7974 if (startswith (name
, ".gcc_compiled_long32"))
7976 else if (startswith (name
, ".gcc_compiled_long64"))
7978 else if (startswith (name
, ".gcc_compiled_long"))
7979 warning (_("unrecognized .gcc_compiled_longXX"));
7982 static enum mips_abi
7983 global_mips_abi (void)
7987 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
7988 if (mips_abi_strings
[i
] == mips_abi_string
)
7989 return (enum mips_abi
) i
;
7991 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
7994 /* Return the default compressed instruction set, either of MIPS16
7995 or microMIPS, selected when none could have been determined from
7996 the ELF header of the binary being executed (or no binary has been
7999 static enum mips_isa
8000 global_mips_compression (void)
8004 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8005 if (mips_compression_strings
[i
] == mips_compression_string
)
8006 return (enum mips_isa
) i
;
8008 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8012 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8014 /* If the size matches the set of 32-bit or 64-bit integer registers,
8015 assume that's what we've got. */
8016 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8017 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8019 /* If the size matches the full set of registers GDB traditionally
8020 knows about, including floating point, for either 32-bit or
8021 64-bit, assume that's what we've got. */
8022 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8023 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8025 /* Otherwise we don't have a useful guess. */
8028 static struct value
*
8029 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8031 const int *reg_p
= (const int *) baton
;
8032 return value_of_register (*reg_p
, frame
);
8035 static struct gdbarch
*
8036 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8038 struct gdbarch
*gdbarch
;
8039 struct gdbarch_tdep
*tdep
;
8041 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8043 enum mips_fpu_type fpu_type
;
8044 tdesc_arch_data_up tdesc_data
;
8045 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8046 const char * const *reg_names
;
8047 struct mips_regnum mips_regnum
, *regnum
;
8048 enum mips_isa mips_isa
;
8052 /* First of all, extract the elf_flags, if available. */
8053 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8054 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8055 else if (arches
!= NULL
)
8056 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8060 fprintf_unfiltered (gdb_stdlog
,
8061 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8063 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8064 switch ((elf_flags
& EF_MIPS_ABI
))
8066 case E_MIPS_ABI_O32
:
8067 found_abi
= MIPS_ABI_O32
;
8069 case E_MIPS_ABI_O64
:
8070 found_abi
= MIPS_ABI_O64
;
8072 case E_MIPS_ABI_EABI32
:
8073 found_abi
= MIPS_ABI_EABI32
;
8075 case E_MIPS_ABI_EABI64
:
8076 found_abi
= MIPS_ABI_EABI64
;
8079 if ((elf_flags
& EF_MIPS_ABI2
))
8080 found_abi
= MIPS_ABI_N32
;
8082 found_abi
= MIPS_ABI_UNKNOWN
;
8086 /* GCC creates a pseudo-section whose name describes the ABI. */
8087 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8088 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8090 /* If we have no useful BFD information, use the ABI from the last
8091 MIPS architecture (if there is one). */
8092 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8093 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8095 /* Try the architecture for any hint of the correct ABI. */
8096 if (found_abi
== MIPS_ABI_UNKNOWN
8097 && info
.bfd_arch_info
!= NULL
8098 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8100 switch (info
.bfd_arch_info
->mach
)
8102 case bfd_mach_mips3900
:
8103 found_abi
= MIPS_ABI_EABI32
;
8105 case bfd_mach_mips4100
:
8106 case bfd_mach_mips5000
:
8107 found_abi
= MIPS_ABI_EABI64
;
8109 case bfd_mach_mips8000
:
8110 case bfd_mach_mips10000
:
8111 /* On Irix, ELF64 executables use the N64 ABI. The
8112 pseudo-sections which describe the ABI aren't present
8113 on IRIX. (Even for executables created by gcc.) */
8114 if (info
.abfd
!= NULL
8115 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8116 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8117 found_abi
= MIPS_ABI_N64
;
8119 found_abi
= MIPS_ABI_N32
;
8124 /* Default 64-bit objects to N64 instead of O32. */
8125 if (found_abi
== MIPS_ABI_UNKNOWN
8126 && info
.abfd
!= NULL
8127 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8128 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8129 found_abi
= MIPS_ABI_N64
;
8132 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8135 /* What has the user specified from the command line? */
8136 wanted_abi
= global_mips_abi ();
8138 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8141 /* Now that we have found what the ABI for this binary would be,
8142 check whether the user is overriding it. */
8143 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8144 mips_abi
= wanted_abi
;
8145 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8146 mips_abi
= found_abi
;
8148 mips_abi
= MIPS_ABI_O32
;
8150 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8153 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8154 if (mips_abi
!= MIPS_ABI_EABI32
8155 && mips_abi
!= MIPS_ABI_O32
8156 && info
.bfd_arch_info
!= NULL
8157 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8158 && info
.bfd_arch_info
->bits_per_word
< 64)
8159 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8161 /* Determine the default compressed ISA. */
8162 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8163 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8164 mips_isa
= ISA_MICROMIPS
;
8165 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8166 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8167 mips_isa
= ISA_MIPS16
;
8169 mips_isa
= global_mips_compression ();
8170 mips_compression_string
= mips_compression_strings
[mips_isa
];
8172 /* Also used when doing an architecture lookup. */
8174 fprintf_unfiltered (gdb_stdlog
,
8175 "mips_gdbarch_init: "
8176 "mips64_transfers_32bit_regs_p = %d\n",
8177 mips64_transfers_32bit_regs_p
);
8179 /* Determine the MIPS FPU type. */
8182 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8183 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8184 Tag_GNU_MIPS_ABI_FP
);
8185 #endif /* HAVE_ELF */
8187 if (!mips_fpu_type_auto
)
8188 fpu_type
= mips_fpu_type
;
8189 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8191 switch (elf_fpu_type
)
8193 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8194 fpu_type
= MIPS_FPU_DOUBLE
;
8196 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8197 fpu_type
= MIPS_FPU_SINGLE
;
8199 case Val_GNU_MIPS_ABI_FP_SOFT
:
8201 /* Soft float or unknown. */
8202 fpu_type
= MIPS_FPU_NONE
;
8206 else if (info
.bfd_arch_info
!= NULL
8207 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8208 switch (info
.bfd_arch_info
->mach
)
8210 case bfd_mach_mips3900
:
8211 case bfd_mach_mips4100
:
8212 case bfd_mach_mips4111
:
8213 case bfd_mach_mips4120
:
8214 fpu_type
= MIPS_FPU_NONE
;
8216 case bfd_mach_mips4650
:
8217 fpu_type
= MIPS_FPU_SINGLE
;
8220 fpu_type
= MIPS_FPU_DOUBLE
;
8223 else if (arches
!= NULL
)
8224 fpu_type
= MIPS_FPU_TYPE (arches
->gdbarch
);
8226 fpu_type
= MIPS_FPU_DOUBLE
;
8228 fprintf_unfiltered (gdb_stdlog
,
8229 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8231 /* Check for blatant incompatibilities. */
8233 /* If we have only 32-bit registers, then we can't debug a 64-bit
8235 if (info
.target_desc
8236 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8237 && mips_abi
!= MIPS_ABI_EABI32
8238 && mips_abi
!= MIPS_ABI_O32
)
8241 /* Fill in the OS dependent register numbers and names. */
8242 if (info
.osabi
== GDB_OSABI_LINUX
)
8244 mips_regnum
.fp0
= 38;
8245 mips_regnum
.pc
= 37;
8246 mips_regnum
.cause
= 36;
8247 mips_regnum
.badvaddr
= 35;
8248 mips_regnum
.hi
= 34;
8249 mips_regnum
.lo
= 33;
8250 mips_regnum
.fp_control_status
= 70;
8251 mips_regnum
.fp_implementation_revision
= 71;
8252 mips_regnum
.dspacc
= -1;
8253 mips_regnum
.dspctl
= -1;
8257 reg_names
= mips_linux_reg_names
;
8261 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8262 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8263 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8264 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8265 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8266 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8267 mips_regnum
.fp_control_status
= 70;
8268 mips_regnum
.fp_implementation_revision
= 71;
8269 mips_regnum
.dspacc
= dspacc
= -1;
8270 mips_regnum
.dspctl
= dspctl
= -1;
8271 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8272 if (info
.bfd_arch_info
!= NULL
8273 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8274 reg_names
= mips_tx39_reg_names
;
8276 reg_names
= mips_generic_reg_names
;
8279 /* Check any target description for validity. */
8280 if (tdesc_has_registers (info
.target_desc
))
8282 static const char *const mips_gprs
[] = {
8283 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8284 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8285 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8286 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8288 static const char *const mips_fprs
[] = {
8289 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8290 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8291 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8292 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8295 const struct tdesc_feature
*feature
;
8298 feature
= tdesc_find_feature (info
.target_desc
,
8299 "org.gnu.gdb.mips.cpu");
8300 if (feature
== NULL
)
8303 tdesc_data
= tdesc_data_alloc ();
8306 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8307 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8311 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8312 mips_regnum
.lo
, "lo");
8313 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8314 mips_regnum
.hi
, "hi");
8315 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8316 mips_regnum
.pc
, "pc");
8321 feature
= tdesc_find_feature (info
.target_desc
,
8322 "org.gnu.gdb.mips.cp0");
8323 if (feature
== NULL
)
8327 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8328 mips_regnum
.badvaddr
, "badvaddr");
8329 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8330 MIPS_PS_REGNUM
, "status");
8331 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8332 mips_regnum
.cause
, "cause");
8337 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8338 backend is not prepared for that, though. */
8339 feature
= tdesc_find_feature (info
.target_desc
,
8340 "org.gnu.gdb.mips.fpu");
8341 if (feature
== NULL
)
8345 for (i
= 0; i
< 32; i
++)
8346 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8347 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8349 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8350 mips_regnum
.fp_control_status
,
8353 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8354 mips_regnum
.fp_implementation_revision
,
8360 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8364 feature
= tdesc_find_feature (info
.target_desc
,
8365 "org.gnu.gdb.mips.dsp");
8366 /* The DSP registers are optional; it's OK if they are absent. */
8367 if (feature
!= NULL
)
8371 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8372 dspacc
+ i
++, "hi1");
8373 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8374 dspacc
+ i
++, "lo1");
8375 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8376 dspacc
+ i
++, "hi2");
8377 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8378 dspacc
+ i
++, "lo2");
8379 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8380 dspacc
+ i
++, "hi3");
8381 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8382 dspacc
+ i
++, "lo3");
8384 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8390 mips_regnum
.dspacc
= dspacc
;
8391 mips_regnum
.dspctl
= dspctl
;
8393 num_regs
= mips_regnum
.dspctl
+ 1;
8397 /* It would be nice to detect an attempt to use a 64-bit ABI
8398 when only 32-bit registers are provided. */
8402 /* Try to find a pre-existing architecture. */
8403 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8405 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8407 /* MIPS needs to be pedantic about which ABI and the compressed
8408 ISA variation the object is using. */
8409 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8411 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8413 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8415 /* Need to be pedantic about which register virtual size is
8417 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8418 != mips64_transfers_32bit_regs_p
)
8420 /* Be pedantic about which FPU is selected. */
8421 if (MIPS_FPU_TYPE (arches
->gdbarch
) != fpu_type
)
8424 return arches
->gdbarch
;
8427 /* Need a new architecture. Fill in a target specific vector. */
8428 tdep
= XCNEW (struct gdbarch_tdep
);
8429 gdbarch
= gdbarch_alloc (&info
, tdep
);
8430 tdep
->elf_flags
= elf_flags
;
8431 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8432 tdep
->found_abi
= found_abi
;
8433 tdep
->mips_abi
= mips_abi
;
8434 tdep
->mips_isa
= mips_isa
;
8435 tdep
->mips_fpu_type
= fpu_type
;
8436 tdep
->register_size_valid_p
= 0;
8437 tdep
->register_size
= 0;
8439 if (info
.target_desc
)
8441 /* Some useful properties can be inferred from the target. */
8442 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8444 tdep
->register_size_valid_p
= 1;
8445 tdep
->register_size
= 4;
8447 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8449 tdep
->register_size_valid_p
= 1;
8450 tdep
->register_size
= 8;
8454 /* Initially set everything according to the default ABI/ISA. */
8455 set_gdbarch_short_bit (gdbarch
, 16);
8456 set_gdbarch_int_bit (gdbarch
, 32);
8457 set_gdbarch_float_bit (gdbarch
, 32);
8458 set_gdbarch_double_bit (gdbarch
, 64);
8459 set_gdbarch_long_double_bit (gdbarch
, 64);
8460 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8461 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8462 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8464 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8465 mips_ax_pseudo_register_collect
);
8466 set_gdbarch_ax_pseudo_register_push_stack
8467 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8469 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8470 mips_elf_make_msymbol_special
);
8471 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8472 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8473 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8475 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8476 *regnum
= mips_regnum
;
8477 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8478 set_gdbarch_num_regs (gdbarch
, num_regs
);
8479 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8480 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8481 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8482 tdep
->mips_processor_reg_names
= reg_names
;
8483 tdep
->regnum
= regnum
;
8488 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8489 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8490 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8491 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8492 tdep
->default_mask_address_p
= 0;
8493 set_gdbarch_long_bit (gdbarch
, 32);
8494 set_gdbarch_ptr_bit (gdbarch
, 32);
8495 set_gdbarch_long_long_bit (gdbarch
, 64);
8498 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8499 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8500 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8501 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8502 tdep
->default_mask_address_p
= 0;
8503 set_gdbarch_long_bit (gdbarch
, 32);
8504 set_gdbarch_ptr_bit (gdbarch
, 32);
8505 set_gdbarch_long_long_bit (gdbarch
, 64);
8507 case MIPS_ABI_EABI32
:
8508 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8509 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8510 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8511 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8512 tdep
->default_mask_address_p
= 0;
8513 set_gdbarch_long_bit (gdbarch
, 32);
8514 set_gdbarch_ptr_bit (gdbarch
, 32);
8515 set_gdbarch_long_long_bit (gdbarch
, 64);
8517 case MIPS_ABI_EABI64
:
8518 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8519 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8520 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8521 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8522 tdep
->default_mask_address_p
= 0;
8523 set_gdbarch_long_bit (gdbarch
, 64);
8524 set_gdbarch_ptr_bit (gdbarch
, 64);
8525 set_gdbarch_long_long_bit (gdbarch
, 64);
8528 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8529 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8530 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8531 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8532 tdep
->default_mask_address_p
= 0;
8533 set_gdbarch_long_bit (gdbarch
, 32);
8534 set_gdbarch_ptr_bit (gdbarch
, 32);
8535 set_gdbarch_long_long_bit (gdbarch
, 64);
8536 set_gdbarch_long_double_bit (gdbarch
, 128);
8537 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8540 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8541 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8542 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8543 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8544 tdep
->default_mask_address_p
= 0;
8545 set_gdbarch_long_bit (gdbarch
, 64);
8546 set_gdbarch_ptr_bit (gdbarch
, 64);
8547 set_gdbarch_long_long_bit (gdbarch
, 64);
8548 set_gdbarch_long_double_bit (gdbarch
, 128);
8549 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8552 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8555 /* GCC creates a pseudo-section whose name specifies the size of
8556 longs, since -mlong32 or -mlong64 may be used independent of
8557 other options. How those options affect pointer sizes is ABI and
8558 architecture dependent, so use them to override the default sizes
8559 set by the ABI. This table shows the relationship between ABI,
8560 -mlongXX, and size of pointers:
8562 ABI -mlongXX ptr bits
8563 --- -------- --------
8577 Note that for o32 and eabi32, pointers are always 32 bits
8578 regardless of any -mlongXX option. For all others, pointers and
8579 longs are the same, as set by -mlongXX or set by defaults. */
8581 if (info
.abfd
!= NULL
)
8585 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8588 set_gdbarch_long_bit (gdbarch
, long_bit
);
8592 case MIPS_ABI_EABI32
:
8597 case MIPS_ABI_EABI64
:
8598 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8601 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8606 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8607 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8610 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8611 flag in object files because to do so would make it impossible to
8612 link with libraries compiled without "-gp32". This is
8613 unnecessarily restrictive.
8615 We could solve this problem by adding "-gp32" multilibs to gcc,
8616 but to set this flag before gcc is built with such multilibs will
8617 break too many systems.''
8619 But even more unhelpfully, the default linker output target for
8620 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8621 for 64-bit programs - you need to change the ABI to change this,
8622 and not all gcc targets support that currently. Therefore using
8623 this flag to detect 32-bit mode would do the wrong thing given
8624 the current gcc - it would make GDB treat these 64-bit programs
8625 as 32-bit programs by default. */
8627 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8628 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8630 /* Add/remove bits from an address. The MIPS needs be careful to
8631 ensure that all 32 bit addresses are sign extended to 64 bits. */
8632 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8634 /* Unwind the frame. */
8635 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8636 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8637 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8639 /* Map debug register numbers onto internal register numbers. */
8640 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8641 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8642 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8643 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8644 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8645 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8647 /* MIPS version of CALL_DUMMY. */
8649 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8650 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8651 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8653 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8655 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8656 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8657 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8659 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8660 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8661 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8662 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8663 mips_adjust_breakpoint_address
);
8665 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8667 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8669 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8670 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8671 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8673 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8675 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8677 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8678 if (mips_abi
== MIPS_ABI_N64
)
8679 set_gdbarch_disassembler_options_implicit
8680 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8681 else if (mips_abi
== MIPS_ABI_N32
)
8682 set_gdbarch_disassembler_options_implicit
8683 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8685 set_gdbarch_disassembler_options_implicit
8686 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8687 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8688 set_gdbarch_valid_disassembler_options (gdbarch
,
8689 disassembler_options_mips ());
8691 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8692 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8693 need to all be folded into the target vector. Since they are
8694 being used as guards for target_stopped_by_watchpoint, why not have
8695 target_stopped_by_watchpoint return the type of watchpoint that the code
8697 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8699 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8701 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8702 to support MIPS16. This is a bad thing. Make sure not to do it
8703 if we have an OS ABI that actually supports shared libraries, since
8704 shared library support is more important. If we have an OS someday
8705 that supports both shared libraries and MIPS16, we'll have to find
8706 a better place for these.
8707 macro/2012-04-25: But that applies to return trampolines only and
8708 currently no MIPS OS ABI uses shared libraries that have them. */
8709 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8711 set_gdbarch_single_step_through_delay (gdbarch
,
8712 mips_single_step_through_delay
);
8714 /* Virtual tables. */
8715 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8717 mips_register_g_packet_guesses (gdbarch
);
8719 /* Hook in OS ABI-specific overrides, if they have been registered. */
8720 info
.tdesc_data
= tdesc_data
.get ();
8721 gdbarch_init_osabi (info
, gdbarch
);
8723 /* The hook may have adjusted num_regs, fetch the final value and
8724 set pc_regnum and sp_regnum now that it has been fixed. */
8725 num_regs
= gdbarch_num_regs (gdbarch
);
8726 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8727 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8729 /* Unwind the frame. */
8730 dwarf2_append_unwinders (gdbarch
);
8731 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8732 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8733 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8734 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8735 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8736 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8737 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8738 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8739 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8741 if (tdesc_data
!= nullptr)
8743 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8744 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8746 /* Override the normal target description methods to handle our
8747 dual real and pseudo registers. */
8748 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8749 set_gdbarch_register_reggroup_p (gdbarch
,
8750 mips_tdesc_register_reggroup_p
);
8752 num_regs
= gdbarch_num_regs (gdbarch
);
8753 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8754 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8755 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8758 /* Add ABI-specific aliases for the registers. */
8759 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8760 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8761 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8762 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8764 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8765 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8766 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8768 /* Add some other standard aliases. */
8769 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8770 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8771 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8773 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8774 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8775 value_of_mips_user_reg
,
8776 &mips_numeric_register_aliases
[i
].regnum
);
8782 mips_abi_update (const char *ignore_args
,
8783 int from_tty
, struct cmd_list_element
*c
)
8785 struct gdbarch_info info
;
8787 /* Force the architecture to update, and (if it's a MIPS architecture)
8788 mips_gdbarch_init will take care of the rest. */
8789 gdbarch_update_p (info
);
8792 /* Print out which MIPS ABI is in use. */
8795 show_mips_abi (struct ui_file
*file
,
8797 struct cmd_list_element
*ignored_cmd
,
8798 const char *ignored_value
)
8800 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8803 "The MIPS ABI is unknown because the current architecture "
8807 enum mips_abi global_abi
= global_mips_abi ();
8808 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8809 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8811 if (global_abi
== MIPS_ABI_UNKNOWN
)
8814 "The MIPS ABI is set automatically (currently \"%s\").\n",
8816 else if (global_abi
== actual_abi
)
8819 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8823 /* Probably shouldn't happen... */
8824 fprintf_filtered (file
,
8825 "The (auto detected) MIPS ABI \"%s\" is in use "
8826 "even though the user setting was \"%s\".\n",
8827 actual_abi_str
, mips_abi_strings
[global_abi
]);
8832 /* Print out which MIPS compressed ISA encoding is used. */
8835 show_mips_compression (struct ui_file
*file
, int from_tty
,
8836 struct cmd_list_element
*c
, const char *value
)
8838 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8842 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8845 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8851 case MIPS_FPU_SINGLE
:
8853 case MIPS_FPU_DOUBLE
:
8861 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8863 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8867 int ef_mips_32bitmode
;
8868 /* Determine the ISA. */
8869 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8887 /* Determine the size of a pointer. */
8888 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8889 fprintf_unfiltered (file
,
8890 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8892 fprintf_unfiltered (file
,
8893 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8895 fprintf_unfiltered (file
,
8896 "mips_dump_tdep: ef_mips_arch = %d\n",
8898 fprintf_unfiltered (file
,
8899 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8900 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8901 fprintf_unfiltered (file
,
8903 "mips_mask_address_p() %d (default %d)\n",
8904 mips_mask_address_p (tdep
),
8905 tdep
->default_mask_address_p
);
8907 fprintf_unfiltered (file
,
8908 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8909 MIPS_DEFAULT_FPU_TYPE
,
8910 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8911 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8912 MIPS_EABI (gdbarch
));
8913 fprintf_unfiltered (file
,
8914 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8915 MIPS_FPU_TYPE (gdbarch
),
8916 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch
)));
8919 void _initialize_mips_tdep ();
8921 _initialize_mips_tdep ()
8923 static struct cmd_list_element
*mipsfpulist
= NULL
;
8925 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8926 if (MIPS_ABI_LAST
+ 1
8927 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8928 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8930 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8932 /* Create feature sets with the appropriate properties. The values
8933 are not important. */
8934 mips_tdesc_gp32
= allocate_target_description ().release ();
8935 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8937 mips_tdesc_gp64
= allocate_target_description ().release ();
8938 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8940 /* Add root prefix command for all "set mips"/"show mips" commands. */
8941 add_basic_prefix_cmd ("mips", no_class
,
8942 _("Various MIPS specific commands."),
8943 &setmipscmdlist
, 0, &setlist
);
8945 add_show_prefix_cmd ("mips", no_class
,
8946 _("Various MIPS specific commands."),
8947 &showmipscmdlist
, 0, &showlist
);
8949 /* Allow the user to override the ABI. */
8950 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8951 &mips_abi_string
, _("\
8952 Set the MIPS ABI used by this program."), _("\
8953 Show the MIPS ABI used by this program."), _("\
8954 This option can be set to one of:\n\
8955 auto - the default ABI associated with the current binary\n\
8964 &setmipscmdlist
, &showmipscmdlist
);
8966 /* Allow the user to set the ISA to assume for compressed code if ELF
8967 file flags don't tell or there is no program file selected. This
8968 setting is updated whenever unambiguous ELF file flags are interpreted,
8969 and carried over to subsequent sessions. */
8970 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8971 &mips_compression_string
, _("\
8972 Set the compressed ISA encoding used by MIPS code."), _("\
8973 Show the compressed ISA encoding used by MIPS code."), _("\
8974 Select the compressed ISA encoding used in functions that have no symbol\n\
8975 information available. The encoding can be set to either of:\n\
8978 and is updated automatically from ELF file flags if available."),
8980 show_mips_compression
,
8981 &setmipscmdlist
, &showmipscmdlist
);
8983 /* Let the user turn off floating point and set the fence post for
8984 heuristic_proc_start. */
8986 add_basic_prefix_cmd ("mipsfpu", class_support
,
8987 _("Set use of MIPS floating-point coprocessor."),
8988 &mipsfpulist
, 0, &setlist
);
8989 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
8990 _("Select single-precision MIPS floating-point coprocessor."),
8992 cmd_list_element
*set_mipsfpu_double_cmd
8993 = add_cmd ("double", class_support
, set_mipsfpu_double_command
,
8994 _("Select double-precision MIPS floating-point coprocessor."),
8996 add_alias_cmd ("on", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
8997 add_alias_cmd ("yes", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
8998 add_alias_cmd ("1", set_mipsfpu_double_cmd
, class_support
, 1, &mipsfpulist
);
9000 cmd_list_element
*set_mipsfpu_none_cmd
9001 = add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9002 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9003 add_alias_cmd ("off", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9004 add_alias_cmd ("no", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9005 add_alias_cmd ("0", set_mipsfpu_none_cmd
, class_support
, 1, &mipsfpulist
);
9006 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9007 _("Select MIPS floating-point coprocessor automatically."),
9009 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9010 _("Show current use of MIPS floating-point coprocessor target."),
9013 /* We really would like to have both "0" and "unlimited" work, but
9014 command.c doesn't deal with that. So make it a var_zinteger
9015 because the user can always use "999999" or some such for unlimited. */
9016 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9017 &heuristic_fence_post
, _("\
9018 Set the distance searched for the start of a function."), _("\
9019 Show the distance searched for the start of a function."), _("\
9020 If you are debugging a stripped executable, GDB needs to search through the\n\
9021 program for the start of a function. This command sets the distance of the\n\
9022 search. The only need to set it is when debugging a stripped executable."),
9023 reinit_frame_cache_sfunc
,
9024 NULL
, /* FIXME: i18n: The distance searched for
9025 the start of a function is %s. */
9026 &setlist
, &showlist
);
9028 /* Allow the user to control whether the upper bits of 64-bit
9029 addresses should be zeroed. */
9030 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9031 &mask_address_var
, _("\
9032 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9033 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9034 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9035 allow GDB to determine the correct value."),
9036 NULL
, show_mask_address
,
9037 &setmipscmdlist
, &showmipscmdlist
);
9039 /* Allow the user to control the size of 32 bit registers within the
9040 raw remote packet. */
9041 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9042 &mips64_transfers_32bit_regs_p
, _("\
9043 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9045 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9047 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9048 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9049 64 bits for others. Use \"off\" to disable compatibility mode"),
9050 set_mips64_transfers_32bit_regs
,
9051 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9052 MIPS target that transfers 32-bit
9053 quantities is %s. */
9054 &setlist
, &showlist
);
9056 /* Debug this files internals. */
9057 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9059 Set mips debugging."), _("\
9060 Show mips debugging."), _("\
9061 When non-zero, mips specific debugging is enabled."),
9063 NULL
, /* FIXME: i18n: Mips debugging is
9065 &setdebuglist
, &showdebuglist
);