1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
8 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
10 This file is part of GDB.
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program. If not, see <http://www.gnu.org/licenses/>. */
26 #include "gdb_string.h"
27 #include "gdb_assert.h"
39 #include "arch-utils.h"
42 #include "mips-tdep.h"
44 #include "reggroups.h"
45 #include "opcode/mips.h"
49 #include "sim-regno.h"
51 #include "frame-unwind.h"
52 #include "frame-base.h"
53 #include "trad-frame.h"
55 #include "floatformat.h"
57 #include "target-descriptions.h"
58 #include "dwarf2-frame.h"
59 #include "user-regs.h"
61 static const struct objfile_data
*mips_pdr_data
;
63 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
67 #define ST0_FR (1 << 26)
69 /* The sizes of floating point registers. */
73 MIPS_FPU_SINGLE_REGSIZE
= 4,
74 MIPS_FPU_DOUBLE_REGSIZE
= 8
83 static const char *mips_abi_string
;
85 static const char *mips_abi_strings
[] = {
96 /* The standard register names, and all the valid aliases for them. */
103 /* Aliases for o32 and most other ABIs. */
104 const struct register_alias mips_o32_aliases
[] = {
111 /* Aliases for n32 and n64. */
112 const struct register_alias mips_n32_n64_aliases
[] = {
119 /* Aliases for ABI-independent registers. */
120 const struct register_alias mips_register_aliases
[] = {
121 /* The architecture manuals specify these ABI-independent names for
123 #define R(n) { "r" #n, n }
124 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
125 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
126 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
127 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
130 /* k0 and k1 are sometimes called these instead (for "kernel
135 /* This is the traditional GDB name for the CP0 status register. */
136 { "sr", MIPS_PS_REGNUM
},
138 /* This is the traditional GDB name for the CP0 BadVAddr register. */
139 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
141 /* This is the traditional GDB name for the FCSR. */
142 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
145 /* Some MIPS boards don't support floating point while others only
146 support single-precision floating-point operations. */
150 MIPS_FPU_DOUBLE
, /* Full double precision floating point. */
151 MIPS_FPU_SINGLE
, /* Single precision floating point (R4650). */
152 MIPS_FPU_NONE
/* No floating point. */
155 #ifndef MIPS_DEFAULT_FPU_TYPE
156 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
158 static int mips_fpu_type_auto
= 1;
159 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
161 static int mips_debug
= 0;
163 /* Properties (for struct target_desc) describing the g/G packet
165 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
166 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
168 struct target_desc
*mips_tdesc_gp32
;
169 struct target_desc
*mips_tdesc_gp64
;
171 /* MIPS specific per-architecture information */
174 /* from the elf header */
178 enum mips_abi mips_abi
;
179 enum mips_abi found_abi
;
180 enum mips_fpu_type mips_fpu_type
;
181 int mips_last_arg_regnum
;
182 int mips_last_fp_arg_regnum
;
183 int default_mask_address_p
;
184 /* Is the target using 64-bit raw integer registers but only
185 storing a left-aligned 32-bit value in each? */
186 int mips64_transfers_32bit_regs_p
;
187 /* Indexes for various registers. IRIX and embedded have
188 different values. This contains the "public" fields. Don't
189 add any that do not need to be public. */
190 const struct mips_regnum
*regnum
;
191 /* Register names table for the current register set. */
192 const char **mips_processor_reg_names
;
194 /* The size of register data available from the target, if known.
195 This doesn't quite obsolete the manual
196 mips64_transfers_32bit_regs_p, since that is documented to force
197 left alignment even for big endian (very strange). */
198 int register_size_valid_p
;
203 n32n64_floatformat_always_valid (const struct floatformat
*fmt
,
209 /* FIXME: brobecker/2004-08-08: Long Double values are 128 bit long.
210 They are implemented as a pair of 64bit doubles where the high
211 part holds the result of the operation rounded to double, and
212 the low double holds the difference between the exact result and
213 the rounded result. So "high" + "low" contains the result with
214 added precision. Unfortunately, the floatformat structure used
215 by GDB is not powerful enough to describe this format. As a temporary
216 measure, we define a 128bit floatformat that only uses the high part.
217 We lose a bit of precision but that's probably the best we can do
218 for now with the current infrastructure. */
220 static const struct floatformat floatformat_n32n64_long_double_big
=
222 floatformat_big
, 128, 0, 1, 11, 1023, 2047, 12, 52,
223 floatformat_intbit_no
,
224 "floatformat_n32n64_long_double_big",
225 n32n64_floatformat_always_valid
228 static const struct floatformat
*floatformats_n32n64_long
[BFD_ENDIAN_UNKNOWN
] =
230 &floatformat_n32n64_long_double_big
,
231 &floatformat_n32n64_long_double_big
234 const struct mips_regnum
*
235 mips_regnum (struct gdbarch
*gdbarch
)
237 return gdbarch_tdep (gdbarch
)->regnum
;
241 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
243 return mips_regnum (gdbarch
)->fp0
+ 12;
246 #define MIPS_EABI (gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI32 \
247 || gdbarch_tdep (current_gdbarch)->mips_abi == MIPS_ABI_EABI64)
249 #define MIPS_LAST_FP_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_fp_arg_regnum)
251 #define MIPS_LAST_ARG_REGNUM (gdbarch_tdep (current_gdbarch)->mips_last_arg_regnum)
253 #define MIPS_FPU_TYPE (gdbarch_tdep (current_gdbarch)->mips_fpu_type)
255 /* MIPS16 function addresses are odd (bit 0 is set). Here are some
256 functions to test, set, or clear bit 0 of addresses. */
259 is_mips16_addr (CORE_ADDR addr
)
265 unmake_mips16_addr (CORE_ADDR addr
)
267 return ((addr
) & ~(CORE_ADDR
) 1);
270 /* Return the MIPS ABI associated with GDBARCH. */
272 mips_abi (struct gdbarch
*gdbarch
)
274 return gdbarch_tdep (gdbarch
)->mips_abi
;
278 mips_isa_regsize (struct gdbarch
*gdbarch
)
280 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
282 /* If we know how big the registers are, use that size. */
283 if (tdep
->register_size_valid_p
)
284 return tdep
->register_size
;
286 /* Fall back to the previous behavior. */
287 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
288 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
291 /* Return the currently configured (or set) saved register size. */
294 mips_abi_regsize (struct gdbarch
*gdbarch
)
296 switch (mips_abi (gdbarch
))
298 case MIPS_ABI_EABI32
:
304 case MIPS_ABI_EABI64
:
306 case MIPS_ABI_UNKNOWN
:
309 internal_error (__FILE__
, __LINE__
, _("bad switch"));
313 /* Functions for setting and testing a bit in a minimal symbol that
314 marks it as 16-bit function. The MSB of the minimal symbol's
315 "info" field is used for this purpose.
317 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
318 i.e. refers to a 16-bit function, and sets a "special" bit in a
319 minimal symbol to mark it as a 16-bit function
321 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
324 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
326 if (((elf_symbol_type
*) (sym
))->internal_elf_sym
.st_other
== STO_MIPS16
)
328 MSYMBOL_INFO (msym
) = (char *)
329 (((long) MSYMBOL_INFO (msym
)) | 0x80000000);
330 SYMBOL_VALUE_ADDRESS (msym
) |= 1;
335 msymbol_is_special (struct minimal_symbol
*msym
)
337 return (((long) MSYMBOL_INFO (msym
) & 0x80000000) != 0);
340 /* XFER a value from the big/little/left end of the register.
341 Depending on the size of the value it might occupy the entire
342 register or just part of it. Make an allowance for this, aligning
343 things accordingly. */
346 mips_xfer_register (struct regcache
*regcache
, int reg_num
, int length
,
347 enum bfd_endian endian
, gdb_byte
*in
,
348 const gdb_byte
*out
, int buf_offset
)
351 gdb_assert (reg_num
>= gdbarch_num_regs (current_gdbarch
));
352 /* Need to transfer the left or right part of the register, based on
353 the targets byte order. */
357 reg_offset
= register_size (current_gdbarch
, reg_num
) - length
;
359 case BFD_ENDIAN_LITTLE
:
362 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
366 internal_error (__FILE__
, __LINE__
, _("bad switch"));
369 fprintf_unfiltered (gdb_stderr
,
370 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
371 reg_num
, reg_offset
, buf_offset
, length
);
372 if (mips_debug
&& out
!= NULL
)
375 fprintf_unfiltered (gdb_stdlog
, "out ");
376 for (i
= 0; i
< length
; i
++)
377 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
380 regcache_cooked_read_part (regcache
, reg_num
, reg_offset
, length
,
383 regcache_cooked_write_part (regcache
, reg_num
, reg_offset
, length
,
385 if (mips_debug
&& in
!= NULL
)
388 fprintf_unfiltered (gdb_stdlog
, "in ");
389 for (i
= 0; i
< length
; i
++)
390 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
393 fprintf_unfiltered (gdb_stdlog
, "\n");
396 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
397 compatiblity mode. A return value of 1 means that we have
398 physical 64-bit registers, but should treat them as 32-bit registers. */
401 mips2_fp_compat (struct frame_info
*frame
)
403 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
405 if (register_size (current_gdbarch
, mips_regnum (current_gdbarch
)->fp0
) ==
410 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
411 in all the places we deal with FP registers. PR gdb/413. */
412 /* Otherwise check the FR bit in the status register - it controls
413 the FP compatiblity mode. If it is clear we are in compatibility
415 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
422 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
424 static CORE_ADDR
heuristic_proc_start (CORE_ADDR
);
426 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element
*);
428 static struct type
*mips_float_register_type (void);
429 static struct type
*mips_double_register_type (void);
431 /* The list of available "set mips " and "show mips " commands */
433 static struct cmd_list_element
*setmipscmdlist
= NULL
;
434 static struct cmd_list_element
*showmipscmdlist
= NULL
;
436 /* Integer registers 0 thru 31 are handled explicitly by
437 mips_register_name(). Processor specific registers 32 and above
438 are listed in the following tables. */
441 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
445 static const char *mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
446 "sr", "lo", "hi", "bad", "cause", "pc",
447 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
448 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
449 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
450 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
451 "fsr", "fir", "" /*"fp" */ , "",
452 "", "", "", "", "", "", "", "",
453 "", "", "", "", "", "", "", "",
456 /* Names of IDT R3041 registers. */
458 static const char *mips_r3041_reg_names
[] = {
459 "sr", "lo", "hi", "bad", "cause", "pc",
460 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
461 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
462 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
463 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
464 "fsr", "fir", "", /*"fp" */ "",
465 "", "", "bus", "ccfg", "", "", "", "",
466 "", "", "port", "cmp", "", "", "epc", "prid",
469 /* Names of tx39 registers. */
471 static const char *mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
472 "sr", "lo", "hi", "bad", "cause", "pc",
473 "", "", "", "", "", "", "", "",
474 "", "", "", "", "", "", "", "",
475 "", "", "", "", "", "", "", "",
476 "", "", "", "", "", "", "", "",
478 "", "", "", "", "", "", "", "",
479 "", "", "config", "cache", "debug", "depc", "epc", ""
482 /* Names of IRIX registers. */
483 static const char *mips_irix_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
484 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
485 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
486 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
487 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
488 "pc", "cause", "bad", "hi", "lo", "fsr", "fir"
492 /* Return the name of the register corresponding to REGNO. */
494 mips_register_name (int regno
)
496 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
497 /* GPR names for all ABIs other than n32/n64. */
498 static char *mips_gpr_names
[] = {
499 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
500 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
501 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
502 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
505 /* GPR names for n32 and n64 ABIs. */
506 static char *mips_n32_n64_gpr_names
[] = {
507 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
508 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
509 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
510 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
513 enum mips_abi abi
= mips_abi (current_gdbarch
);
515 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
516 but then don't make the raw register names visible. */
517 int rawnum
= regno
% gdbarch_num_regs (current_gdbarch
);
518 if (regno
< gdbarch_num_regs (current_gdbarch
))
521 /* The MIPS integer registers are always mapped from 0 to 31. The
522 names of the registers (which reflects the conventions regarding
523 register use) vary depending on the ABI. */
524 if (0 <= rawnum
&& rawnum
< 32)
526 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
527 return mips_n32_n64_gpr_names
[rawnum
];
529 return mips_gpr_names
[rawnum
];
531 else if (tdesc_has_registers (gdbarch_target_desc (current_gdbarch
)))
532 return tdesc_register_name (rawnum
);
533 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (current_gdbarch
))
535 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
536 return tdep
->mips_processor_reg_names
[rawnum
- 32];
539 internal_error (__FILE__
, __LINE__
,
540 _("mips_register_name: bad register number %d"), rawnum
);
543 /* Return the groups that a MIPS register can be categorised into. */
546 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
547 struct reggroup
*reggroup
)
552 int rawnum
= regnum
% gdbarch_num_regs (current_gdbarch
);
553 int pseudo
= regnum
/ gdbarch_num_regs (current_gdbarch
);
554 if (reggroup
== all_reggroup
)
556 vector_p
= TYPE_VECTOR (register_type (gdbarch
, regnum
));
557 float_p
= TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
;
558 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
559 (gdbarch), as not all architectures are multi-arch. */
560 raw_p
= rawnum
< gdbarch_num_regs (current_gdbarch
);
561 if (gdbarch_register_name (current_gdbarch
, regnum
) == NULL
562 || gdbarch_register_name (current_gdbarch
, regnum
)[0] == '\0')
564 if (reggroup
== float_reggroup
)
565 return float_p
&& pseudo
;
566 if (reggroup
== vector_reggroup
)
567 return vector_p
&& pseudo
;
568 if (reggroup
== general_reggroup
)
569 return (!vector_p
&& !float_p
) && pseudo
;
570 /* Save the pseudo registers. Need to make certain that any code
571 extracting register values from a saved register cache also uses
573 if (reggroup
== save_reggroup
)
574 return raw_p
&& pseudo
;
575 /* Restore the same pseudo register. */
576 if (reggroup
== restore_reggroup
)
577 return raw_p
&& pseudo
;
581 /* Return the groups that a MIPS register can be categorised into.
582 This version is only used if we have a target description which
583 describes real registers (and their groups). */
586 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
587 struct reggroup
*reggroup
)
589 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
590 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
593 /* Only save, restore, and display the pseudo registers. Need to
594 make certain that any code extracting register values from a
595 saved register cache also uses pseudo registers.
597 Note: saving and restoring the pseudo registers is slightly
598 strange; if we have 64 bits, we should save and restore all
599 64 bits. But this is hard and has little benefit. */
603 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
607 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
610 /* Map the symbol table registers which live in the range [1 *
611 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
612 registers. Take care of alignment and size problems. */
615 mips_pseudo_register_read (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
616 int cookednum
, gdb_byte
*buf
)
618 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
619 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
620 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
621 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
622 regcache_raw_read (regcache
, rawnum
, buf
);
623 else if (register_size (gdbarch
, rawnum
) >
624 register_size (gdbarch
, cookednum
))
626 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
627 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
628 regcache_raw_read_part (regcache
, rawnum
, 0, 4, buf
);
630 regcache_raw_read_part (regcache
, rawnum
, 4, 4, buf
);
633 internal_error (__FILE__
, __LINE__
, _("bad register size"));
637 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
638 struct regcache
*regcache
, int cookednum
,
641 int rawnum
= cookednum
% gdbarch_num_regs (current_gdbarch
);
642 gdb_assert (cookednum
>= gdbarch_num_regs (current_gdbarch
)
643 && cookednum
< 2 * gdbarch_num_regs (current_gdbarch
));
644 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
645 regcache_raw_write (regcache
, rawnum
, buf
);
646 else if (register_size (gdbarch
, rawnum
) >
647 register_size (gdbarch
, cookednum
))
649 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
650 || gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_LITTLE
)
651 regcache_raw_write_part (regcache
, rawnum
, 0, 4, buf
);
653 regcache_raw_write_part (regcache
, rawnum
, 4, 4, buf
);
656 internal_error (__FILE__
, __LINE__
, _("bad register size"));
659 /* Table to translate MIPS16 register field to actual register number. */
660 static int mips16_to_32_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
662 /* Heuristic_proc_start may hunt through the text section for a long
663 time across a 2400 baud serial line. Allows the user to limit this
666 static unsigned int heuristic_fence_post
= 0;
668 /* Number of bytes of storage in the actual machine representation for
669 register N. NOTE: This defines the pseudo register type so need to
670 rebuild the architecture vector. */
672 static int mips64_transfers_32bit_regs_p
= 0;
675 set_mips64_transfers_32bit_regs (char *args
, int from_tty
,
676 struct cmd_list_element
*c
)
678 struct gdbarch_info info
;
679 gdbarch_info_init (&info
);
680 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
681 instead of relying on globals. Doing that would let generic code
682 handle the search for this specific architecture. */
683 if (!gdbarch_update_p (info
))
685 mips64_transfers_32bit_regs_p
= 0;
686 error (_("32-bit compatibility mode not supported"));
690 /* Convert to/from a register and the corresponding memory value. */
693 mips_convert_register_p (int regnum
, struct type
*type
)
695 return (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
696 && register_size (current_gdbarch
, regnum
) == 4
697 && (regnum
% gdbarch_num_regs (current_gdbarch
))
698 >= mips_regnum (current_gdbarch
)->fp0
699 && (regnum
% gdbarch_num_regs (current_gdbarch
))
700 < mips_regnum (current_gdbarch
)->fp0
+ 32
701 && TYPE_CODE (type
) == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
705 mips_register_to_value (struct frame_info
*frame
, int regnum
,
706 struct type
*type
, gdb_byte
*to
)
708 get_frame_register (frame
, regnum
+ 0, to
+ 4);
709 get_frame_register (frame
, regnum
+ 1, to
+ 0);
713 mips_value_to_register (struct frame_info
*frame
, int regnum
,
714 struct type
*type
, const gdb_byte
*from
)
716 put_frame_register (frame
, regnum
+ 0, from
+ 4);
717 put_frame_register (frame
, regnum
+ 1, from
+ 0);
720 /* Return the GDB type object for the "standard" data type of data in
724 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
726 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (current_gdbarch
));
727 if ((regnum
% gdbarch_num_regs (current_gdbarch
))
728 >= mips_regnum (current_gdbarch
)->fp0
729 && (regnum
% gdbarch_num_regs (current_gdbarch
))
730 < mips_regnum (current_gdbarch
)->fp0
+ 32)
732 /* The floating-point registers raw, or cooked, always match
733 mips_isa_regsize(), and also map 1:1, byte for byte. */
734 if (mips_isa_regsize (gdbarch
) == 4)
735 return builtin_type_ieee_single
;
737 return builtin_type_ieee_double
;
739 else if (regnum
< gdbarch_num_regs (current_gdbarch
))
741 /* The raw or ISA registers. These are all sized according to
743 if (mips_isa_regsize (gdbarch
) == 4)
744 return builtin_type_int32
;
746 return builtin_type_int64
;
750 /* The cooked or ABI registers. These are sized according to
751 the ABI (with a few complications). */
752 if (regnum
>= (gdbarch_num_regs (current_gdbarch
)
753 + mips_regnum (current_gdbarch
)->fp_control_status
)
754 && regnum
<= gdbarch_num_regs (current_gdbarch
)
755 + MIPS_LAST_EMBED_REGNUM
)
756 /* The pseudo/cooked view of the embedded registers is always
757 32-bit. The raw view is handled below. */
758 return builtin_type_int32
;
759 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
760 /* The target, while possibly using a 64-bit register buffer,
761 is only transfering 32-bits of each integer register.
762 Reflect this in the cooked/pseudo (ABI) register value. */
763 return builtin_type_int32
;
764 else if (mips_abi_regsize (gdbarch
) == 4)
765 /* The ABI is restricted to 32-bit registers (the ISA could be
767 return builtin_type_int32
;
770 return builtin_type_int64
;
774 /* Return the GDB type for the pseudo register REGNUM, which is the
775 ABI-level view. This function is only called if there is a target
776 description which includes registers, so we know precisely the
777 types of hardware registers. */
780 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
782 const int num_regs
= gdbarch_num_regs (gdbarch
);
783 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
784 int rawnum
= regnum
% num_regs
;
785 struct type
*rawtype
;
787 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
789 /* Absent registers are still absent. */
790 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
791 if (TYPE_LENGTH (rawtype
) == 0)
794 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
&& rawnum
< MIPS_EMBED_FP0_REGNUM
+ 32)
795 /* Present the floating point registers however the hardware did;
796 do not try to convert between FPU layouts. */
799 if (rawnum
>= MIPS_EMBED_FP0_REGNUM
+ 32 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
801 /* The pseudo/cooked view of embedded registers is always
802 32-bit, even if the target transfers 64-bit values for them.
803 New targets relying on XML descriptions should only transfer
804 the necessary 32 bits, but older versions of GDB expected 64,
805 so allow the target to provide 64 bits without interfering
806 with the displayed type. */
807 return builtin_type_int32
;
810 /* Use pointer types for registers if we can. For n32 we can not,
811 since we do not have a 64-bit pointer type. */
812 if (mips_abi_regsize (gdbarch
) == TYPE_LENGTH (builtin_type_void_data_ptr
))
814 if (rawnum
== MIPS_SP_REGNUM
|| rawnum
== MIPS_EMBED_BADVADDR_REGNUM
)
815 return builtin_type_void_data_ptr
;
816 else if (rawnum
== MIPS_EMBED_PC_REGNUM
)
817 return builtin_type_void_func_ptr
;
820 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
821 && rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_EMBED_PC_REGNUM
)
822 return builtin_type_int32
;
824 /* For all other registers, pass through the hardware type. */
828 /* Should the upper word of 64-bit addresses be zeroed? */
829 enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
832 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
834 switch (mask_address_var
)
836 case AUTO_BOOLEAN_TRUE
:
838 case AUTO_BOOLEAN_FALSE
:
841 case AUTO_BOOLEAN_AUTO
:
842 return tdep
->default_mask_address_p
;
844 internal_error (__FILE__
, __LINE__
, _("mips_mask_address_p: bad switch"));
850 show_mask_address (struct ui_file
*file
, int from_tty
,
851 struct cmd_list_element
*c
, const char *value
)
853 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
855 deprecated_show_value_hack (file
, from_tty
, c
, value
);
856 switch (mask_address_var
)
858 case AUTO_BOOLEAN_TRUE
:
859 printf_filtered ("The 32 bit mips address mask is enabled\n");
861 case AUTO_BOOLEAN_FALSE
:
862 printf_filtered ("The 32 bit mips address mask is disabled\n");
864 case AUTO_BOOLEAN_AUTO
:
866 ("The 32 bit address mask is set automatically. Currently %s\n",
867 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
870 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
875 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
878 mips_pc_is_mips16 (CORE_ADDR memaddr
)
880 struct minimal_symbol
*sym
;
882 /* If bit 0 of the address is set, assume this is a MIPS16 address. */
883 if (is_mips16_addr (memaddr
))
886 /* A flag indicating that this is a MIPS16 function is stored by elfread.c in
887 the high bit of the info field. Use this to decide if the function is
888 MIPS16 or normal MIPS. */
889 sym
= lookup_minimal_symbol_by_pc (memaddr
);
891 return msymbol_is_special (sym
);
896 /* MIPS believes that the PC has a sign extended value. Perhaps the
897 all registers should be sign extended for simplicity? */
900 mips_read_pc (struct regcache
*regcache
)
903 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
904 regcache_cooked_read_signed (regcache
, regnum
, &pc
);
909 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
911 return frame_unwind_register_signed (next_frame
,
912 gdbarch_num_regs (current_gdbarch
)
913 + mips_regnum (gdbarch
)->pc
);
917 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
919 return frame_unwind_register_signed (next_frame
,
920 gdbarch_num_regs (current_gdbarch
)
924 /* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that
925 dummy frame. The frame ID's base needs to match the TOS value
926 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
929 static struct frame_id
930 mips_unwind_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
932 return frame_id_build
933 (frame_unwind_register_signed (next_frame
,
934 gdbarch_num_regs (current_gdbarch
)
936 frame_pc_unwind (next_frame
));
940 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
942 int regnum
= mips_regnum (get_regcache_arch (regcache
))->pc
;
943 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
946 /* Fetch and return instruction from the specified location. If the PC
947 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */
950 mips_fetch_instruction (CORE_ADDR addr
)
952 gdb_byte buf
[MIPS_INSN32_SIZE
];
956 if (mips_pc_is_mips16 (addr
))
958 instlen
= MIPS_INSN16_SIZE
;
959 addr
= unmake_mips16_addr (addr
);
962 instlen
= MIPS_INSN32_SIZE
;
963 status
= read_memory_nobpt (addr
, buf
, instlen
);
965 memory_error (status
, addr
);
966 return extract_unsigned_integer (buf
, instlen
);
969 /* These the fields of 32 bit mips instructions */
970 #define mips32_op(x) (x >> 26)
971 #define itype_op(x) (x >> 26)
972 #define itype_rs(x) ((x >> 21) & 0x1f)
973 #define itype_rt(x) ((x >> 16) & 0x1f)
974 #define itype_immediate(x) (x & 0xffff)
976 #define jtype_op(x) (x >> 26)
977 #define jtype_target(x) (x & 0x03ffffff)
979 #define rtype_op(x) (x >> 26)
980 #define rtype_rs(x) ((x >> 21) & 0x1f)
981 #define rtype_rt(x) ((x >> 16) & 0x1f)
982 #define rtype_rd(x) ((x >> 11) & 0x1f)
983 #define rtype_shamt(x) ((x >> 6) & 0x1f)
984 #define rtype_funct(x) (x & 0x3f)
987 mips32_relative_offset (ULONGEST inst
)
989 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
992 /* Determine where to set a single step breakpoint while considering
993 branch prediction. */
995 mips32_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
999 inst
= mips_fetch_instruction (pc
);
1000 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch instruction */
1002 if (itype_op (inst
) >> 2 == 5)
1003 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1005 op
= (itype_op (inst
) & 0x03);
1015 goto greater_branch
;
1020 else if (itype_op (inst
) == 17 && itype_rs (inst
) == 8)
1021 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1023 int tf
= itype_rt (inst
) & 0x01;
1024 int cnum
= itype_rt (inst
) >> 2;
1026 get_frame_register_signed (frame
, mips_regnum (current_gdbarch
)->
1028 int cond
= ((fcrcs
>> 24) & 0x0e) | ((fcrcs
>> 23) & 0x01);
1030 if (((cond
>> cnum
) & 0x01) == tf
)
1031 pc
+= mips32_relative_offset (inst
) + 4;
1036 pc
+= 4; /* Not a branch, next instruction is easy */
1039 { /* This gets way messy */
1041 /* Further subdivide into SPECIAL, REGIMM and other */
1042 switch (op
= itype_op (inst
) & 0x07) /* extract bits 28,27,26 */
1044 case 0: /* SPECIAL */
1045 op
= rtype_funct (inst
);
1050 /* Set PC to that address */
1051 pc
= get_frame_register_signed (frame
, rtype_rs (inst
));
1057 break; /* end SPECIAL */
1058 case 1: /* REGIMM */
1060 op
= itype_rt (inst
); /* branch condition */
1065 case 16: /* BLTZAL */
1066 case 18: /* BLTZALL */
1068 if (get_frame_register_signed (frame
, itype_rs (inst
)) < 0)
1069 pc
+= mips32_relative_offset (inst
) + 4;
1071 pc
+= 8; /* after the delay slot */
1075 case 17: /* BGEZAL */
1076 case 19: /* BGEZALL */
1077 if (get_frame_register_signed (frame
, itype_rs (inst
)) >= 0)
1078 pc
+= mips32_relative_offset (inst
) + 4;
1080 pc
+= 8; /* after the delay slot */
1082 /* All of the other instructions in the REGIMM category */
1087 break; /* end REGIMM */
1092 reg
= jtype_target (inst
) << 2;
1093 /* Upper four bits get never changed... */
1094 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1097 /* FIXME case JALX : */
1100 reg
= jtype_target (inst
) << 2;
1101 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + 1; /* yes, +1 */
1102 /* Add 1 to indicate 16 bit mode - Invert ISA mode */
1104 break; /* The new PC will be alternate mode */
1105 case 4: /* BEQ, BEQL */
1107 if (get_frame_register_signed (frame
, itype_rs (inst
)) ==
1108 get_frame_register_signed (frame
, itype_rt (inst
)))
1109 pc
+= mips32_relative_offset (inst
) + 4;
1113 case 5: /* BNE, BNEL */
1115 if (get_frame_register_signed (frame
, itype_rs (inst
)) !=
1116 get_frame_register_signed (frame
, itype_rt (inst
)))
1117 pc
+= mips32_relative_offset (inst
) + 4;
1121 case 6: /* BLEZ, BLEZL */
1122 if (get_frame_register_signed (frame
, itype_rs (inst
)) <= 0)
1123 pc
+= mips32_relative_offset (inst
) + 4;
1129 greater_branch
: /* BGTZ, BGTZL */
1130 if (get_frame_register_signed (frame
, itype_rs (inst
)) > 0)
1131 pc
+= mips32_relative_offset (inst
) + 4;
1138 } /* mips32_next_pc */
1140 /* Decoding the next place to set a breakpoint is irregular for the
1141 mips 16 variant, but fortunately, there fewer instructions. We have to cope
1142 ith extensions for 16 bit instructions and a pair of actual 32 bit instructions.
1143 We dont want to set a single step instruction on the extend instruction
1147 /* Lots of mips16 instruction formats */
1148 /* Predicting jumps requires itype,ritype,i8type
1149 and their extensions extItype,extritype,extI8type
1151 enum mips16_inst_fmts
1153 itype
, /* 0 immediate 5,10 */
1154 ritype
, /* 1 5,3,8 */
1155 rrtype
, /* 2 5,3,3,5 */
1156 rritype
, /* 3 5,3,3,5 */
1157 rrrtype
, /* 4 5,3,3,3,2 */
1158 rriatype
, /* 5 5,3,3,1,4 */
1159 shifttype
, /* 6 5,3,3,3,2 */
1160 i8type
, /* 7 5,3,8 */
1161 i8movtype
, /* 8 5,3,3,5 */
1162 i8mov32rtype
, /* 9 5,3,5,3 */
1163 i64type
, /* 10 5,3,8 */
1164 ri64type
, /* 11 5,3,3,5 */
1165 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
1166 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
1167 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
1168 extRRItype
, /* 15 5,5,5,5,3,3,5 */
1169 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
1170 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
1171 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
1172 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
1173 extRi64type
, /* 20 5,6,5,5,3,3,5 */
1174 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
1176 /* I am heaping all the fields of the formats into one structure and
1177 then, only the fields which are involved in instruction extension */
1181 unsigned int regx
; /* Function in i8 type */
1186 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
1187 for the bits which make up the immediatate extension. */
1190 extended_offset (unsigned int extension
)
1193 value
= (extension
>> 21) & 0x3f; /* * extract 15:11 */
1195 value
|= (extension
>> 16) & 0x1f; /* extrace 10:5 */
1197 value
|= extension
& 0x01f; /* extract 4:0 */
1201 /* Only call this function if you know that this is an extendable
1202 instruction. It won't malfunction, but why make excess remote memory
1203 references? If the immediate operands get sign extended or something,
1204 do it after the extension is performed. */
1205 /* FIXME: Every one of these cases needs to worry about sign extension
1206 when the offset is to be used in relative addressing. */
1209 fetch_mips_16 (CORE_ADDR pc
)
1212 pc
&= 0xfffffffe; /* clear the low order bit */
1213 target_read_memory (pc
, buf
, 2);
1214 return extract_unsigned_integer (buf
, 2);
1218 unpack_mips16 (CORE_ADDR pc
,
1219 unsigned int extension
,
1221 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
1226 switch (insn_format
)
1233 value
= extended_offset (extension
);
1234 value
= value
<< 11; /* rom for the original value */
1235 value
|= inst
& 0x7ff; /* eleven bits from instruction */
1239 value
= inst
& 0x7ff;
1240 /* FIXME : Consider sign extension */
1249 { /* A register identifier and an offset */
1250 /* Most of the fields are the same as I type but the
1251 immediate value is of a different length */
1255 value
= extended_offset (extension
);
1256 value
= value
<< 8; /* from the original instruction */
1257 value
|= inst
& 0xff; /* eleven bits from instruction */
1258 regx
= (extension
>> 8) & 0x07; /* or i8 funct */
1259 if (value
& 0x4000) /* test the sign bit , bit 26 */
1261 value
&= ~0x3fff; /* remove the sign bit */
1267 value
= inst
& 0xff; /* 8 bits */
1268 regx
= (inst
>> 8) & 0x07; /* or i8 funct */
1269 /* FIXME: Do sign extension , this format needs it */
1270 if (value
& 0x80) /* THIS CONFUSES ME */
1272 value
&= 0xef; /* remove the sign bit */
1282 unsigned long value
;
1283 unsigned int nexthalf
;
1284 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
1285 value
= value
<< 16;
1286 nexthalf
= mips_fetch_instruction (pc
+ 2); /* low bit still set */
1294 internal_error (__FILE__
, __LINE__
, _("bad switch"));
1296 upk
->offset
= offset
;
1303 add_offset_16 (CORE_ADDR pc
, int offset
)
1305 return ((offset
<< 2) | ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)));
1309 extended_mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
,
1310 unsigned int extension
, unsigned int insn
)
1312 int op
= (insn
>> 11);
1315 case 2: /* Branch */
1318 struct upk_mips16 upk
;
1319 unpack_mips16 (pc
, extension
, insn
, itype
, &upk
);
1320 offset
= upk
.offset
;
1326 pc
+= (offset
<< 1) + 2;
1329 case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
1331 struct upk_mips16 upk
;
1332 unpack_mips16 (pc
, extension
, insn
, jalxtype
, &upk
);
1333 pc
= add_offset_16 (pc
, upk
.offset
);
1334 if ((insn
>> 10) & 0x01) /* Exchange mode */
1335 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode */
1342 struct upk_mips16 upk
;
1344 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1345 reg
= get_frame_register_signed (frame
, upk
.regx
);
1347 pc
+= (upk
.offset
<< 1) + 2;
1354 struct upk_mips16 upk
;
1356 unpack_mips16 (pc
, extension
, insn
, ritype
, &upk
);
1357 reg
= get_frame_register_signed (frame
, upk
.regx
);
1359 pc
+= (upk
.offset
<< 1) + 2;
1364 case 12: /* I8 Formats btez btnez */
1366 struct upk_mips16 upk
;
1368 unpack_mips16 (pc
, extension
, insn
, i8type
, &upk
);
1369 /* upk.regx contains the opcode */
1370 reg
= get_frame_register_signed (frame
, 24); /* Test register is 24 */
1371 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
1372 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
1373 /* pc = add_offset_16(pc,upk.offset) ; */
1374 pc
+= (upk
.offset
<< 1) + 2;
1379 case 29: /* RR Formats JR, JALR, JALR-RA */
1381 struct upk_mips16 upk
;
1382 /* upk.fmt = rrtype; */
1387 upk
.regx
= (insn
>> 8) & 0x07;
1388 upk
.regy
= (insn
>> 5) & 0x07;
1396 break; /* Function return instruction */
1402 break; /* BOGUS Guess */
1404 pc
= get_frame_register_signed (frame
, reg
);
1411 /* This is an instruction extension. Fetch the real instruction
1412 (which follows the extension) and decode things based on
1416 pc
= extended_mips16_next_pc (frame
, pc
, insn
, fetch_mips_16 (pc
));
1429 mips16_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1431 unsigned int insn
= fetch_mips_16 (pc
);
1432 return extended_mips16_next_pc (frame
, pc
, 0, insn
);
1435 /* The mips_next_pc function supports single_step when the remote
1436 target monitor or stub is not developed enough to do a single_step.
1437 It works by decoding the current instruction and predicting where a
1438 branch will go. This isnt hard because all the data is available.
1439 The MIPS32 and MIPS16 variants are quite different. */
1441 mips_next_pc (struct frame_info
*frame
, CORE_ADDR pc
)
1443 if (is_mips16_addr (pc
))
1444 return mips16_next_pc (frame
, pc
);
1446 return mips32_next_pc (frame
, pc
);
1449 struct mips_frame_cache
1452 struct trad_frame_saved_reg
*saved_regs
;
1455 /* Set a register's saved stack address in temp_saved_regs. If an
1456 address has already been set for this register, do nothing; this
1457 way we will only recognize the first save of a given register in a
1460 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
1461 [gdbarch_num_regs .. 2*gdbarch_num_regs).
1462 Strictly speaking, only the second range is used as it is only second
1463 range (the ABI instead of ISA registers) that comes into play when finding
1464 saved registers in a frame. */
1467 set_reg_offset (struct mips_frame_cache
*this_cache
, int regnum
,
1470 if (this_cache
!= NULL
1471 && this_cache
->saved_regs
[regnum
].addr
== -1)
1473 this_cache
->saved_regs
[regnum
1474 + 0 * gdbarch_num_regs (current_gdbarch
)].addr
1476 this_cache
->saved_regs
[regnum
1477 + 1 * gdbarch_num_regs (current_gdbarch
)].addr
1483 /* Fetch the immediate value from a MIPS16 instruction.
1484 If the previous instruction was an EXTEND, use it to extend
1485 the upper bits of the immediate value. This is a helper function
1486 for mips16_scan_prologue. */
1489 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
1490 unsigned short inst
, /* current instruction */
1491 int nbits
, /* number of bits in imm field */
1492 int scale
, /* scale factor to be applied to imm */
1493 int is_signed
) /* is the imm field signed? */
1497 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
1499 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
1500 if (offset
& 0x8000) /* check for negative extend */
1501 offset
= 0 - (0x10000 - (offset
& 0xffff));
1502 return offset
| (inst
& 0x1f);
1506 int max_imm
= 1 << nbits
;
1507 int mask
= max_imm
- 1;
1508 int sign_bit
= max_imm
>> 1;
1510 offset
= inst
& mask
;
1511 if (is_signed
&& (offset
& sign_bit
))
1512 offset
= 0 - (max_imm
- offset
);
1513 return offset
* scale
;
1518 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1519 the associated FRAME_CACHE if not null.
1520 Return the address of the first instruction past the prologue. */
1523 mips16_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1524 struct frame_info
*next_frame
,
1525 struct mips_frame_cache
*this_cache
)
1528 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer */
1530 long frame_offset
= 0; /* Size of stack frame. */
1531 long frame_adjust
= 0; /* Offset of FP from SP. */
1532 int frame_reg
= MIPS_SP_REGNUM
;
1533 unsigned short prev_inst
= 0; /* saved copy of previous instruction */
1534 unsigned inst
= 0; /* current instruction */
1535 unsigned entry_inst
= 0; /* the entry instruction */
1538 int extend_bytes
= 0;
1539 int prev_extend_bytes
;
1540 CORE_ADDR end_prologue_addr
= 0;
1542 /* Can be called when there's no process, and hence when there's no
1544 if (next_frame
!= NULL
)
1545 sp
= frame_unwind_register_signed (next_frame
,
1546 gdbarch_num_regs (current_gdbarch
)
1551 if (limit_pc
> start_pc
+ 200)
1552 limit_pc
= start_pc
+ 200;
1554 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
1556 /* Save the previous instruction. If it's an EXTEND, we'll extract
1557 the immediate offset extension from it in mips16_get_imm. */
1560 /* Fetch and decode the instruction. */
1561 inst
= (unsigned short) mips_fetch_instruction (cur_pc
);
1563 /* Normally we ignore extend instructions. However, if it is
1564 not followed by a valid prologue instruction, then this
1565 instruction is not part of the prologue either. We must
1566 remember in this case to adjust the end_prologue_addr back
1568 if ((inst
& 0xf800) == 0xf000) /* extend */
1570 extend_bytes
= MIPS_INSN16_SIZE
;
1574 prev_extend_bytes
= extend_bytes
;
1577 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
1578 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
1580 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
1581 if (offset
< 0) /* negative stack adjustment? */
1582 frame_offset
-= offset
;
1584 /* Exit loop if a positive stack adjustment is found, which
1585 usually means that the stack cleanup code in the function
1586 epilogue is reached. */
1589 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
1591 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1592 reg
= mips16_to_32_reg
[(inst
& 0x700) >> 8];
1593 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1595 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
1597 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1598 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1599 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1601 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
1603 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1604 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1606 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
1608 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
1609 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1611 else if (inst
== 0x673d) /* move $s1, $sp */
1616 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
1618 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
1619 frame_addr
= sp
+ offset
;
1621 frame_adjust
= offset
;
1623 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
1625 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
1626 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1627 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1629 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
1631 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
1632 reg
= mips16_to_32_reg
[(inst
& 0xe0) >> 5];
1633 set_reg_offset (this_cache
, reg
, frame_addr
+ offset
);
1635 else if ((inst
& 0xf81f) == 0xe809
1636 && (inst
& 0x700) != 0x700) /* entry */
1637 entry_inst
= inst
; /* save for later processing */
1638 else if ((inst
& 0xf800) == 0x1800) /* jal(x) */
1639 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
1640 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
1642 /* This instruction is part of the prologue, but we don't
1643 need to do anything special to handle it. */
1647 /* This instruction is not an instruction typically found
1648 in a prologue, so we must have reached the end of the
1650 if (end_prologue_addr
== 0)
1651 end_prologue_addr
= cur_pc
- prev_extend_bytes
;
1655 /* The entry instruction is typically the first instruction in a function,
1656 and it stores registers at offsets relative to the value of the old SP
1657 (before the prologue). But the value of the sp parameter to this
1658 function is the new SP (after the prologue has been executed). So we
1659 can't calculate those offsets until we've seen the entire prologue,
1660 and can calculate what the old SP must have been. */
1661 if (entry_inst
!= 0)
1663 int areg_count
= (entry_inst
>> 8) & 7;
1664 int sreg_count
= (entry_inst
>> 6) & 3;
1666 /* The entry instruction always subtracts 32 from the SP. */
1669 /* Now we can calculate what the SP must have been at the
1670 start of the function prologue. */
1673 /* Check if a0-a3 were saved in the caller's argument save area. */
1674 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
1676 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1677 offset
+= mips_abi_regsize (current_gdbarch
);
1680 /* Check if the ra register was pushed on the stack. */
1682 if (entry_inst
& 0x20)
1684 set_reg_offset (this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
1685 offset
-= mips_abi_regsize (current_gdbarch
);
1688 /* Check if the s0 and s1 registers were pushed on the stack. */
1689 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
1691 set_reg_offset (this_cache
, reg
, sp
+ offset
);
1692 offset
-= mips_abi_regsize (current_gdbarch
);
1696 if (this_cache
!= NULL
)
1699 (frame_unwind_register_signed (next_frame
,
1700 gdbarch_num_regs (current_gdbarch
)
1702 + frame_offset
- frame_adjust
);
1703 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
1704 be able to get rid of the assignment below, evetually. But it's
1705 still needed for now. */
1706 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1707 + mips_regnum (current_gdbarch
)->pc
]
1708 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
1712 /* If we didn't reach the end of the prologue when scanning the function
1713 instructions, then set end_prologue_addr to the address of the
1714 instruction immediately after the last one we scanned. */
1715 if (end_prologue_addr
== 0)
1716 end_prologue_addr
= cur_pc
;
1718 return end_prologue_addr
;
1721 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
1722 Procedures that use the 32-bit instruction set are handled by the
1723 mips_insn32 unwinder. */
1725 static struct mips_frame_cache
*
1726 mips_insn16_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
1728 struct mips_frame_cache
*cache
;
1730 if ((*this_cache
) != NULL
)
1731 return (*this_cache
);
1732 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
1733 (*this_cache
) = cache
;
1734 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
1736 /* Analyze the function prologue. */
1738 const CORE_ADDR pc
=
1739 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
1740 CORE_ADDR start_addr
;
1742 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
1743 if (start_addr
== 0)
1744 start_addr
= heuristic_proc_start (pc
);
1745 /* We can't analyze the prologue if we couldn't find the begining
1747 if (start_addr
== 0)
1750 mips16_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
1753 /* gdbarch_sp_regnum contains the value and not the address. */
1754 trad_frame_set_value (cache
->saved_regs
, gdbarch_num_regs (current_gdbarch
)
1755 + MIPS_SP_REGNUM
, cache
->base
);
1757 return (*this_cache
);
1761 mips_insn16_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
1762 struct frame_id
*this_id
)
1764 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1766 (*this_id
) = frame_id_build (info
->base
,
1767 frame_func_unwind (next_frame
, NORMAL_FRAME
));
1771 mips_insn16_frame_prev_register (struct frame_info
*next_frame
,
1773 int regnum
, int *optimizedp
,
1774 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
1775 int *realnump
, gdb_byte
*valuep
)
1777 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1779 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
1780 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
1783 static const struct frame_unwind mips_insn16_frame_unwind
=
1786 mips_insn16_frame_this_id
,
1787 mips_insn16_frame_prev_register
1790 static const struct frame_unwind
*
1791 mips_insn16_frame_sniffer (struct frame_info
*next_frame
)
1793 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
1794 if (mips_pc_is_mips16 (pc
))
1795 return &mips_insn16_frame_unwind
;
1800 mips_insn16_frame_base_address (struct frame_info
*next_frame
,
1803 struct mips_frame_cache
*info
= mips_insn16_frame_cache (next_frame
,
1808 static const struct frame_base mips_insn16_frame_base
=
1810 &mips_insn16_frame_unwind
,
1811 mips_insn16_frame_base_address
,
1812 mips_insn16_frame_base_address
,
1813 mips_insn16_frame_base_address
1816 static const struct frame_base
*
1817 mips_insn16_frame_base_sniffer (struct frame_info
*next_frame
)
1819 if (mips_insn16_frame_sniffer (next_frame
) != NULL
)
1820 return &mips_insn16_frame_base
;
1825 /* Mark all the registers as unset in the saved_regs array
1826 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
1829 reset_saved_regs (struct mips_frame_cache
*this_cache
)
1831 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
1835 const int num_regs
= gdbarch_num_regs (current_gdbarch
);
1838 for (i
= 0; i
< num_regs
; i
++)
1840 this_cache
->saved_regs
[i
].addr
= -1;
1845 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
1846 the associated FRAME_CACHE if not null.
1847 Return the address of the first instruction past the prologue. */
1850 mips32_scan_prologue (CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
1851 struct frame_info
*next_frame
,
1852 struct mips_frame_cache
*this_cache
)
1855 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for frame-pointer */
1858 int frame_reg
= MIPS_SP_REGNUM
;
1860 CORE_ADDR end_prologue_addr
= 0;
1861 int seen_sp_adjust
= 0;
1862 int load_immediate_bytes
= 0;
1864 /* Can be called when there's no process, and hence when there's no
1866 if (next_frame
!= NULL
)
1867 sp
= frame_unwind_register_signed (next_frame
,
1868 gdbarch_num_regs (current_gdbarch
)
1873 if (limit_pc
> start_pc
+ 200)
1874 limit_pc
= start_pc
+ 200;
1879 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
1881 unsigned long inst
, high_word
, low_word
;
1884 /* Fetch the instruction. */
1885 inst
= (unsigned long) mips_fetch_instruction (cur_pc
);
1887 /* Save some code by pre-extracting some useful fields. */
1888 high_word
= (inst
>> 16) & 0xffff;
1889 low_word
= inst
& 0xffff;
1890 reg
= high_word
& 0x1f;
1892 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
1893 || high_word
== 0x23bd /* addi $sp,$sp,-i */
1894 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
1896 if (low_word
& 0x8000) /* negative stack adjustment? */
1897 frame_offset
+= 0x10000 - low_word
;
1899 /* Exit loop if a positive stack adjustment is found, which
1900 usually means that the stack cleanup code in the function
1901 epilogue is reached. */
1905 else if ((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
1907 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1909 else if ((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
1911 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
1912 set_reg_offset (this_cache
, reg
, sp
+ low_word
);
1914 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
1916 /* Old gcc frame, r30 is virtual frame pointer. */
1917 if ((long) low_word
!= frame_offset
)
1918 frame_addr
= sp
+ low_word
;
1919 else if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1921 unsigned alloca_adjust
;
1924 frame_addr
= frame_unwind_register_signed
1926 gdbarch_num_regs (current_gdbarch
) + 30);
1928 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ low_word
));
1929 if (alloca_adjust
> 0)
1931 /* FP > SP + frame_size. This may be because of
1932 an alloca or somethings similar. Fix sp to
1933 "pre-alloca" value, and try again. */
1934 sp
+= alloca_adjust
;
1935 /* Need to reset the status of all registers. Otherwise,
1936 we will hit a guard that prevents the new address
1937 for each register to be recomputed during the second
1939 reset_saved_regs (this_cache
);
1944 /* move $30,$sp. With different versions of gas this will be either
1945 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
1946 Accept any one of these. */
1947 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
1949 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
1950 if (next_frame
&& frame_reg
== MIPS_SP_REGNUM
)
1952 unsigned alloca_adjust
;
1955 frame_addr
= frame_unwind_register_signed
1957 gdbarch_num_regs (current_gdbarch
) + 30);
1959 alloca_adjust
= (unsigned) (frame_addr
- sp
);
1960 if (alloca_adjust
> 0)
1962 /* FP > SP + frame_size. This may be because of
1963 an alloca or somethings similar. Fix sp to
1964 "pre-alloca" value, and try again. */
1966 /* Need to reset the status of all registers. Otherwise,
1967 we will hit a guard that prevents the new address
1968 for each register to be recomputed during the second
1970 reset_saved_regs (this_cache
);
1975 else if ((high_word
& 0xFFE0) == 0xafc0) /* sw reg,offset($30) */
1977 set_reg_offset (this_cache
, reg
, frame_addr
+ low_word
);
1979 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
1980 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
1981 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
1982 || high_word
== 0x3c1c /* lui $gp,n */
1983 || high_word
== 0x279c /* addiu $gp,$gp,n */
1984 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
1985 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
1988 /* These instructions are part of the prologue, but we don't
1989 need to do anything special to handle them. */
1991 /* The instructions below load $at or $t0 with an immediate
1992 value in preparation for a stack adjustment via
1993 subu $sp,$sp,[$at,$t0]. These instructions could also
1994 initialize a local variable, so we accept them only before
1995 a stack adjustment instruction was seen. */
1996 else if (!seen_sp_adjust
1997 && (high_word
== 0x3c01 /* lui $at,n */
1998 || high_word
== 0x3c08 /* lui $t0,n */
1999 || high_word
== 0x3421 /* ori $at,$at,n */
2000 || high_word
== 0x3508 /* ori $t0,$t0,n */
2001 || high_word
== 0x3401 /* ori $at,$zero,n */
2002 || high_word
== 0x3408 /* ori $t0,$zero,n */
2005 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
2009 /* This instruction is not an instruction typically found
2010 in a prologue, so we must have reached the end of the
2012 /* FIXME: brobecker/2004-10-10: Can't we just break out of this
2013 loop now? Why would we need to continue scanning the function
2015 if (end_prologue_addr
== 0)
2016 end_prologue_addr
= cur_pc
;
2020 if (this_cache
!= NULL
)
2023 (frame_unwind_register_signed (next_frame
,
2024 gdbarch_num_regs (current_gdbarch
)
2027 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
2028 this assignment below, eventually. But it's still needed
2030 this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
2031 + mips_regnum (current_gdbarch
)->pc
]
2032 = this_cache
->saved_regs
[gdbarch_num_regs (current_gdbarch
)
2036 /* If we didn't reach the end of the prologue when scanning the function
2037 instructions, then set end_prologue_addr to the address of the
2038 instruction immediately after the last one we scanned. */
2039 /* brobecker/2004-10-10: I don't think this would ever happen, but
2040 we may as well be careful and do our best if we have a null
2041 end_prologue_addr. */
2042 if (end_prologue_addr
== 0)
2043 end_prologue_addr
= cur_pc
;
2045 /* In a frameless function, we might have incorrectly
2046 skipped some load immediate instructions. Undo the skipping
2047 if the load immediate was not followed by a stack adjustment. */
2048 if (load_immediate_bytes
&& !seen_sp_adjust
)
2049 end_prologue_addr
-= load_immediate_bytes
;
2051 return end_prologue_addr
;
2054 /* Heuristic unwinder for procedures using 32-bit instructions (covers
2055 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
2056 instructions (a.k.a. MIPS16) are handled by the mips_insn16
2059 static struct mips_frame_cache
*
2060 mips_insn32_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2062 struct mips_frame_cache
*cache
;
2064 if ((*this_cache
) != NULL
)
2065 return (*this_cache
);
2067 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2068 (*this_cache
) = cache
;
2069 cache
->saved_regs
= trad_frame_alloc_saved_regs (next_frame
);
2071 /* Analyze the function prologue. */
2073 const CORE_ADDR pc
=
2074 frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2075 CORE_ADDR start_addr
;
2077 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2078 if (start_addr
== 0)
2079 start_addr
= heuristic_proc_start (pc
);
2080 /* We can't analyze the prologue if we couldn't find the begining
2082 if (start_addr
== 0)
2085 mips32_scan_prologue (start_addr
, pc
, next_frame
, *this_cache
);
2088 /* gdbarch_sp_regnum contains the value and not the address. */
2089 trad_frame_set_value (cache
->saved_regs
,
2090 gdbarch_num_regs (current_gdbarch
) + MIPS_SP_REGNUM
,
2093 return (*this_cache
);
2097 mips_insn32_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2098 struct frame_id
*this_id
)
2100 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2102 (*this_id
) = frame_id_build (info
->base
,
2103 frame_func_unwind (next_frame
, NORMAL_FRAME
));
2107 mips_insn32_frame_prev_register (struct frame_info
*next_frame
,
2109 int regnum
, int *optimizedp
,
2110 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2111 int *realnump
, gdb_byte
*valuep
)
2113 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2115 trad_frame_get_prev_register (next_frame
, info
->saved_regs
, regnum
,
2116 optimizedp
, lvalp
, addrp
, realnump
, valuep
);
2119 static const struct frame_unwind mips_insn32_frame_unwind
=
2122 mips_insn32_frame_this_id
,
2123 mips_insn32_frame_prev_register
2126 static const struct frame_unwind
*
2127 mips_insn32_frame_sniffer (struct frame_info
*next_frame
)
2129 CORE_ADDR pc
= frame_pc_unwind (next_frame
);
2130 if (! mips_pc_is_mips16 (pc
))
2131 return &mips_insn32_frame_unwind
;
2136 mips_insn32_frame_base_address (struct frame_info
*next_frame
,
2139 struct mips_frame_cache
*info
= mips_insn32_frame_cache (next_frame
,
2144 static const struct frame_base mips_insn32_frame_base
=
2146 &mips_insn32_frame_unwind
,
2147 mips_insn32_frame_base_address
,
2148 mips_insn32_frame_base_address
,
2149 mips_insn32_frame_base_address
2152 static const struct frame_base
*
2153 mips_insn32_frame_base_sniffer (struct frame_info
*next_frame
)
2155 if (mips_insn32_frame_sniffer (next_frame
) != NULL
)
2156 return &mips_insn32_frame_base
;
2161 static struct trad_frame_cache
*
2162 mips_stub_frame_cache (struct frame_info
*next_frame
, void **this_cache
)
2165 CORE_ADDR start_addr
;
2166 CORE_ADDR stack_addr
;
2167 struct trad_frame_cache
*this_trad_cache
;
2169 if ((*this_cache
) != NULL
)
2170 return (*this_cache
);
2171 this_trad_cache
= trad_frame_cache_zalloc (next_frame
);
2172 (*this_cache
) = this_trad_cache
;
2174 /* The return address is in the link register. */
2175 trad_frame_set_reg_realreg (this_trad_cache
,
2176 gdbarch_pc_regnum (current_gdbarch
),
2177 (gdbarch_num_regs (current_gdbarch
)
2180 /* Frame ID, since it's a frameless / stackless function, no stack
2181 space is allocated and SP on entry is the current SP. */
2182 pc
= frame_pc_unwind (next_frame
);
2183 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2184 stack_addr
= frame_unwind_register_signed (next_frame
, MIPS_SP_REGNUM
);
2185 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
2187 /* Assume that the frame's base is the same as the
2189 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
2191 return this_trad_cache
;
2195 mips_stub_frame_this_id (struct frame_info
*next_frame
, void **this_cache
,
2196 struct frame_id
*this_id
)
2198 struct trad_frame_cache
*this_trad_cache
2199 = mips_stub_frame_cache (next_frame
, this_cache
);
2200 trad_frame_get_id (this_trad_cache
, this_id
);
2204 mips_stub_frame_prev_register (struct frame_info
*next_frame
,
2206 int regnum
, int *optimizedp
,
2207 enum lval_type
*lvalp
, CORE_ADDR
*addrp
,
2208 int *realnump
, gdb_byte
*valuep
)
2210 struct trad_frame_cache
*this_trad_cache
2211 = mips_stub_frame_cache (next_frame
, this_cache
);
2212 trad_frame_get_register (this_trad_cache
, next_frame
, regnum
, optimizedp
,
2213 lvalp
, addrp
, realnump
, valuep
);
2216 static const struct frame_unwind mips_stub_frame_unwind
=
2219 mips_stub_frame_this_id
,
2220 mips_stub_frame_prev_register
2223 static const struct frame_unwind
*
2224 mips_stub_frame_sniffer (struct frame_info
*next_frame
)
2227 struct obj_section
*s
;
2228 CORE_ADDR pc
= frame_unwind_address_in_block (next_frame
, NORMAL_FRAME
);
2230 /* Use the stub unwinder for unreadable code. */
2231 if (target_read_memory (frame_pc_unwind (next_frame
), dummy
, 4) != 0)
2232 return &mips_stub_frame_unwind
;
2234 if (in_plt_section (pc
, NULL
))
2235 return &mips_stub_frame_unwind
;
2237 /* Binutils for MIPS puts lazy resolution stubs into .MIPS.stubs. */
2238 s
= find_pc_section (pc
);
2241 && strcmp (bfd_get_section_name (s
->objfile
->obfd
, s
->the_bfd_section
),
2242 ".MIPS.stubs") == 0)
2243 return &mips_stub_frame_unwind
;
2249 mips_stub_frame_base_address (struct frame_info
*next_frame
,
2252 struct trad_frame_cache
*this_trad_cache
2253 = mips_stub_frame_cache (next_frame
, this_cache
);
2254 return trad_frame_get_this_base (this_trad_cache
);
2257 static const struct frame_base mips_stub_frame_base
=
2259 &mips_stub_frame_unwind
,
2260 mips_stub_frame_base_address
,
2261 mips_stub_frame_base_address
,
2262 mips_stub_frame_base_address
2265 static const struct frame_base
*
2266 mips_stub_frame_base_sniffer (struct frame_info
*next_frame
)
2268 if (mips_stub_frame_sniffer (next_frame
) != NULL
)
2269 return &mips_stub_frame_base
;
2274 /* mips_addr_bits_remove - remove useless address bits */
2277 mips_addr_bits_remove (CORE_ADDR addr
)
2279 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
2280 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
2281 /* This hack is a work-around for existing boards using PMON, the
2282 simulator, and any other 64-bit targets that doesn't have true
2283 64-bit addressing. On these targets, the upper 32 bits of
2284 addresses are ignored by the hardware. Thus, the PC or SP are
2285 likely to have been sign extended to all 1s by instruction
2286 sequences that load 32-bit addresses. For example, a typical
2287 piece of code that loads an address is this:
2289 lui $r2, <upper 16 bits>
2290 ori $r2, <lower 16 bits>
2292 But the lui sign-extends the value such that the upper 32 bits
2293 may be all 1s. The workaround is simply to mask off these
2294 bits. In the future, gcc may be changed to support true 64-bit
2295 addressing, and this masking will have to be disabled. */
2296 return addr
&= 0xffffffffUL
;
2301 /* mips_software_single_step() is called just before we want to resume
2302 the inferior, if we want to single-step it but there is no hardware
2303 or kernel single-step support (MIPS on GNU/Linux for example). We find
2304 the target of the coming instruction and breakpoint it. */
2307 mips_software_single_step (struct frame_info
*frame
)
2309 CORE_ADDR pc
, next_pc
;
2311 pc
= get_frame_pc (frame
);
2312 next_pc
= mips_next_pc (frame
, pc
);
2314 insert_single_step_breakpoint (next_pc
);
2318 /* Test whether the PC points to the return instruction at the
2319 end of a function. */
2322 mips_about_to_return (CORE_ADDR pc
)
2324 if (mips_pc_is_mips16 (pc
))
2325 /* This mips16 case isn't necessarily reliable. Sometimes the compiler
2326 generates a "jr $ra"; other times it generates code to load
2327 the return address from the stack to an accessible register (such
2328 as $a3), then a "jr" using that register. This second case
2329 is almost impossible to distinguish from an indirect jump
2330 used for switch statements, so we don't even try. */
2331 return mips_fetch_instruction (pc
) == 0xe820; /* jr $ra */
2333 return mips_fetch_instruction (pc
) == 0x3e00008; /* jr $ra */
2337 /* This fencepost looks highly suspicious to me. Removing it also
2338 seems suspicious as it could affect remote debugging across serial
2342 heuristic_proc_start (CORE_ADDR pc
)
2349 pc
= gdbarch_addr_bits_remove (current_gdbarch
, pc
);
2351 fence
= start_pc
- heuristic_fence_post
;
2355 if (heuristic_fence_post
== UINT_MAX
|| fence
< VM_MIN_ADDRESS
)
2356 fence
= VM_MIN_ADDRESS
;
2358 instlen
= mips_pc_is_mips16 (pc
) ? MIPS_INSN16_SIZE
: MIPS_INSN32_SIZE
;
2360 /* search back for previous return */
2361 for (start_pc
-= instlen
;; start_pc
-= instlen
)
2362 if (start_pc
< fence
)
2364 /* It's not clear to me why we reach this point when
2365 stop_soon, but with this test, at least we
2366 don't print out warnings for every child forked (eg, on
2367 decstation). 22apr93 rich@cygnus.com. */
2368 if (stop_soon
== NO_STOP_QUIETLY
)
2370 static int blurb_printed
= 0;
2372 warning (_("GDB can't find the start of the function at 0x%s."),
2377 /* This actually happens frequently in embedded
2378 development, when you first connect to a board
2379 and your stack pointer and pc are nowhere in
2380 particular. This message needs to give people
2381 in that situation enough information to
2382 determine that it's no big deal. */
2383 printf_filtered ("\n\
2384 GDB is unable to find the start of the function at 0x%s\n\
2385 and thus can't determine the size of that function's stack frame.\n\
2386 This means that GDB may be unable to access that stack frame, or\n\
2387 the frames below it.\n\
2388 This problem is most likely caused by an invalid program counter or\n\
2390 However, if you think GDB should simply search farther back\n\
2391 from 0x%s for code which looks like the beginning of a\n\
2392 function, you can increase the range of the search using the `set\n\
2393 heuristic-fence-post' command.\n", paddr_nz (pc
), paddr_nz (pc
));
2400 else if (mips_pc_is_mips16 (start_pc
))
2402 unsigned short inst
;
2404 /* On MIPS16, any one of the following is likely to be the
2405 start of a function:
2411 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n' */
2412 inst
= mips_fetch_instruction (start_pc
);
2413 if ((inst
& 0xff80) == 0x6480) /* save */
2415 if (start_pc
- instlen
>= fence
)
2417 inst
= mips_fetch_instruction (start_pc
- instlen
);
2418 if ((inst
& 0xf800) == 0xf000) /* extend */
2419 start_pc
-= instlen
;
2423 else if (((inst
& 0xf81f) == 0xe809
2424 && (inst
& 0x700) != 0x700) /* entry */
2425 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
2426 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
2427 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
2429 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2430 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2435 else if (mips_about_to_return (start_pc
))
2437 /* Skip return and its delay slot. */
2438 start_pc
+= 2 * MIPS_INSN32_SIZE
;
2445 struct mips_objfile_private
2451 /* According to the current ABI, should the type be passed in a
2452 floating-point register (assuming that there is space)? When there
2453 is no FPU, FP are not even considered as possible candidates for
2454 FP registers and, consequently this returns false - forces FP
2455 arguments into integer registers. */
2458 fp_register_arg_p (enum type_code typecode
, struct type
*arg_type
)
2460 return ((typecode
== TYPE_CODE_FLT
2462 && (typecode
== TYPE_CODE_STRUCT
2463 || typecode
== TYPE_CODE_UNION
)
2464 && TYPE_NFIELDS (arg_type
) == 1
2465 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type
, 0)))
2467 && MIPS_FPU_TYPE
!= MIPS_FPU_NONE
);
2470 /* On o32, argument passing in GPRs depends on the alignment of the type being
2471 passed. Return 1 if this type must be aligned to a doubleword boundary. */
2474 mips_type_needs_double_align (struct type
*type
)
2476 enum type_code typecode
= TYPE_CODE (type
);
2478 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
2480 else if (typecode
== TYPE_CODE_STRUCT
)
2482 if (TYPE_NFIELDS (type
) < 1)
2484 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, 0));
2486 else if (typecode
== TYPE_CODE_UNION
)
2490 n
= TYPE_NFIELDS (type
);
2491 for (i
= 0; i
< n
; i
++)
2492 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type
, i
)))
2499 /* Adjust the address downward (direction of stack growth) so that it
2500 is correctly aligned for a new stack frame. */
2502 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
2504 return align_down (addr
, 16);
2508 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2509 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2510 int nargs
, struct value
**args
, CORE_ADDR sp
,
2511 int struct_return
, CORE_ADDR struct_addr
)
2517 int stack_offset
= 0;
2518 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2519 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2520 int regsize
= mips_abi_regsize (gdbarch
);
2522 /* For shared libraries, "t9" needs to point at the function
2524 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2526 /* Set the return address register to point to the entry point of
2527 the program, where a breakpoint lies in wait. */
2528 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2530 /* First ensure that the stack and structure return address (if any)
2531 are properly aligned. The stack has to be at least 64-bit
2532 aligned even on 32-bit machines, because doubles must be 64-bit
2533 aligned. For n32 and n64, stack frames need to be 128-bit
2534 aligned, so we round to this widest known alignment. */
2536 sp
= align_down (sp
, 16);
2537 struct_addr
= align_down (struct_addr
, 16);
2539 /* Now make space on the stack for the args. We allocate more
2540 than necessary for EABI, because the first few arguments are
2541 passed in registers, but that's OK. */
2542 for (argnum
= 0; argnum
< nargs
; argnum
++)
2543 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), regsize
);
2544 sp
-= align_up (len
, 16);
2547 fprintf_unfiltered (gdb_stdlog
,
2548 "mips_eabi_push_dummy_call: sp=0x%s allocated %ld\n",
2549 paddr_nz (sp
), (long) align_up (len
, 16));
2551 /* Initialize the integer and float register pointers. */
2552 argreg
= MIPS_A0_REGNUM
;
2553 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2555 /* The struct_return pointer occupies the first parameter-passing reg. */
2559 fprintf_unfiltered (gdb_stdlog
,
2560 "mips_eabi_push_dummy_call: struct_return reg=%d 0x%s\n",
2561 argreg
, paddr_nz (struct_addr
));
2562 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2565 /* Now load as many as possible of the first arguments into
2566 registers, and push the rest onto the stack. Loop thru args
2567 from first to last. */
2568 for (argnum
= 0; argnum
< nargs
; argnum
++)
2570 const gdb_byte
*val
;
2571 gdb_byte valbuf
[MAX_REGISTER_SIZE
];
2572 struct value
*arg
= args
[argnum
];
2573 struct type
*arg_type
= check_typedef (value_type (arg
));
2574 int len
= TYPE_LENGTH (arg_type
);
2575 enum type_code typecode
= TYPE_CODE (arg_type
);
2578 fprintf_unfiltered (gdb_stdlog
,
2579 "mips_eabi_push_dummy_call: %d len=%d type=%d",
2580 argnum
+ 1, len
, (int) typecode
);
2582 /* The EABI passes structures that do not fit in a register by
2585 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
2587 store_unsigned_integer (valbuf
, regsize
, VALUE_ADDRESS (arg
));
2588 typecode
= TYPE_CODE_PTR
;
2592 fprintf_unfiltered (gdb_stdlog
, " push");
2595 val
= value_contents (arg
);
2597 /* 32-bit ABIs always start floating point arguments in an
2598 even-numbered floating point register. Round the FP register
2599 up before the check to see if there are any FP registers
2600 left. Non MIPS_EABI targets also pass the FP in the integer
2601 registers so also round up normal registers. */
2602 if (regsize
< 8 && fp_register_arg_p (typecode
, arg_type
))
2604 if ((float_argreg
& 1))
2608 /* Floating point arguments passed in registers have to be
2609 treated specially. On 32-bit architectures, doubles
2610 are passed in register pairs; the even register gets
2611 the low word, and the odd register gets the high word.
2612 On non-EABI processors, the first two floating point arguments are
2613 also copied to general registers, because MIPS16 functions
2614 don't use float registers for arguments. This duplication of
2615 arguments in general registers can't hurt non-MIPS16 functions
2616 because those registers are normally skipped. */
2617 /* MIPS_EABI squeezes a struct that contains a single floating
2618 point value into an FP register instead of pushing it onto the
2620 if (fp_register_arg_p (typecode
, arg_type
)
2621 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
2623 /* EABI32 will pass doubles in consecutive registers, even on
2624 64-bit cores. At one time, we used to check the size of
2625 `float_argreg' to determine whether or not to pass doubles
2626 in consecutive registers, but this is not sufficient for
2627 making the ABI determination. */
2628 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
2630 int low_offset
= gdbarch_byte_order (current_gdbarch
)
2631 == BFD_ENDIAN_BIG
? 4 : 0;
2632 unsigned long regval
;
2634 /* Write the low word of the double to the even register(s). */
2635 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
2637 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2638 float_argreg
, phex (regval
, 4));
2639 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2641 /* Write the high word of the double to the odd register(s). */
2642 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
2644 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2645 float_argreg
, phex (regval
, 4));
2646 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2650 /* This is a floating point value that fits entirely
2651 in a single register. */
2652 /* On 32 bit ABI's the float_argreg is further adjusted
2653 above to ensure that it is even register aligned. */
2654 LONGEST regval
= extract_unsigned_integer (val
, len
);
2656 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2657 float_argreg
, phex (regval
, len
));
2658 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
2663 /* Copy the argument to general registers or the stack in
2664 register-sized pieces. Large arguments are split between
2665 registers and stack. */
2666 /* Note: structs whose size is not a multiple of regsize
2667 are treated specially: Irix cc passes
2668 them in registers where gcc sometimes puts them on the
2669 stack. For maximum compatibility, we will put them in
2671 int odd_sized_struct
= (len
> regsize
&& len
% regsize
!= 0);
2673 /* Note: Floating-point values that didn't fit into an FP
2674 register are only written to memory. */
2677 /* Remember if the argument was written to the stack. */
2678 int stack_used_p
= 0;
2679 int partial_len
= (len
< regsize
? len
: regsize
);
2682 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2685 /* Write this portion of the argument to the stack. */
2686 if (argreg
> MIPS_LAST_ARG_REGNUM
2688 || fp_register_arg_p (typecode
, arg_type
))
2690 /* Should shorter than int integer values be
2691 promoted to int before being stored? */
2692 int longword_offset
= 0;
2695 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2698 && (typecode
== TYPE_CODE_INT
2699 || typecode
== TYPE_CODE_PTR
2700 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
2701 longword_offset
= regsize
- len
;
2702 else if ((typecode
== TYPE_CODE_STRUCT
2703 || typecode
== TYPE_CODE_UNION
)
2704 && TYPE_LENGTH (arg_type
) < regsize
)
2705 longword_offset
= regsize
- len
;
2710 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2711 paddr_nz (stack_offset
));
2712 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2713 paddr_nz (longword_offset
));
2716 addr
= sp
+ stack_offset
+ longword_offset
;
2721 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2723 for (i
= 0; i
< partial_len
; i
++)
2725 fprintf_unfiltered (gdb_stdlog
, "%02x",
2729 write_memory (addr
, val
, partial_len
);
2732 /* Note!!! This is NOT an else clause. Odd sized
2733 structs may go thru BOTH paths. Floating point
2734 arguments will not. */
2735 /* Write this portion of the argument to a general
2736 purpose register. */
2737 if (argreg
<= MIPS_LAST_ARG_REGNUM
2738 && !fp_register_arg_p (typecode
, arg_type
))
2741 extract_unsigned_integer (val
, partial_len
);
2744 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
2746 phex (regval
, regsize
));
2747 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2754 /* Compute the the offset into the stack at which we
2755 will copy the next parameter.
2757 In the new EABI (and the NABI32), the stack_offset
2758 only needs to be adjusted when it has been used. */
2761 stack_offset
+= align_up (partial_len
, regsize
);
2765 fprintf_unfiltered (gdb_stdlog
, "\n");
2768 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
2770 /* Return adjusted stack pointer. */
2774 /* Determine the return value convention being used. */
2776 static enum return_value_convention
2777 mips_eabi_return_value (struct gdbarch
*gdbarch
,
2778 struct type
*type
, struct regcache
*regcache
,
2779 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
2781 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
2782 return RETURN_VALUE_STRUCT_CONVENTION
;
2784 memset (readbuf
, 0, TYPE_LENGTH (type
));
2785 return RETURN_VALUE_REGISTER_CONVENTION
;
2789 /* N32/N64 ABI stuff. */
2791 /* Search for a naturally aligned double at OFFSET inside a struct
2792 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
2796 mips_n32n64_fp_arg_chunk_p (struct type
*arg_type
, int offset
)
2800 if (TYPE_CODE (arg_type
) != TYPE_CODE_STRUCT
)
2803 if (MIPS_FPU_TYPE
!= MIPS_FPU_DOUBLE
)
2806 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
2809 for (i
= 0; i
< TYPE_NFIELDS (arg_type
); i
++)
2812 struct type
*field_type
;
2814 /* We're only looking at normal fields. */
2815 if (TYPE_FIELD_STATIC (arg_type
, i
)
2816 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
2819 /* If we have gone past the offset, there is no double to pass. */
2820 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
2824 field_type
= check_typedef (TYPE_FIELD_TYPE (arg_type
, i
));
2826 /* If this field is entirely before the requested offset, go
2827 on to the next one. */
2828 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
2831 /* If this is our special aligned double, we can stop. */
2832 if (TYPE_CODE (field_type
) == TYPE_CODE_FLT
2833 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
2836 /* This field starts at or before the requested offset, and
2837 overlaps it. If it is a structure, recurse inwards. */
2838 return mips_n32n64_fp_arg_chunk_p (field_type
, offset
- pos
);
2845 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2846 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2847 int nargs
, struct value
**args
, CORE_ADDR sp
,
2848 int struct_return
, CORE_ADDR struct_addr
)
2854 int stack_offset
= 0;
2855 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
2856 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
2858 /* For shared libraries, "t9" needs to point at the function
2860 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
2862 /* Set the return address register to point to the entry point of
2863 the program, where a breakpoint lies in wait. */
2864 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
2866 /* First ensure that the stack and structure return address (if any)
2867 are properly aligned. The stack has to be at least 64-bit
2868 aligned even on 32-bit machines, because doubles must be 64-bit
2869 aligned. For n32 and n64, stack frames need to be 128-bit
2870 aligned, so we round to this widest known alignment. */
2872 sp
= align_down (sp
, 16);
2873 struct_addr
= align_down (struct_addr
, 16);
2875 /* Now make space on the stack for the args. */
2876 for (argnum
= 0; argnum
< nargs
; argnum
++)
2877 len
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
2878 sp
-= align_up (len
, 16);
2881 fprintf_unfiltered (gdb_stdlog
,
2882 "mips_n32n64_push_dummy_call: sp=0x%s allocated %ld\n",
2883 paddr_nz (sp
), (long) align_up (len
, 16));
2885 /* Initialize the integer and float register pointers. */
2886 argreg
= MIPS_A0_REGNUM
;
2887 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
2889 /* The struct_return pointer occupies the first parameter-passing reg. */
2893 fprintf_unfiltered (gdb_stdlog
,
2894 "mips_n32n64_push_dummy_call: struct_return reg=%d 0x%s\n",
2895 argreg
, paddr_nz (struct_addr
));
2896 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
2899 /* Now load as many as possible of the first arguments into
2900 registers, and push the rest onto the stack. Loop thru args
2901 from first to last. */
2902 for (argnum
= 0; argnum
< nargs
; argnum
++)
2904 const gdb_byte
*val
;
2905 struct value
*arg
= args
[argnum
];
2906 struct type
*arg_type
= check_typedef (value_type (arg
));
2907 int len
= TYPE_LENGTH (arg_type
);
2908 enum type_code typecode
= TYPE_CODE (arg_type
);
2911 fprintf_unfiltered (gdb_stdlog
,
2912 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
2913 argnum
+ 1, len
, (int) typecode
);
2915 val
= value_contents (arg
);
2917 if (fp_register_arg_p (typecode
, arg_type
)
2918 && argreg
<= MIPS_LAST_ARG_REGNUM
)
2920 /* This is a floating point value that fits entirely
2921 in a single register. */
2922 LONGEST regval
= extract_unsigned_integer (val
, len
);
2924 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
2925 float_argreg
, phex (regval
, len
));
2926 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
2929 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
2930 argreg
, phex (regval
, len
));
2931 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
2937 /* Copy the argument to general registers or the stack in
2938 register-sized pieces. Large arguments are split between
2939 registers and stack. */
2940 /* For N32/N64, structs, unions, or other composite types are
2941 treated as a sequence of doublewords, and are passed in integer
2942 or floating point registers as though they were simple scalar
2943 parameters to the extent that they fit, with any excess on the
2944 stack packed according to the normal memory layout of the
2946 The caller does not reserve space for the register arguments;
2947 the callee is responsible for reserving it if required. */
2948 /* Note: Floating-point values that didn't fit into an FP
2949 register are only written to memory. */
2952 /* Remember if the argument was written to the stack. */
2953 int stack_used_p
= 0;
2954 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
2957 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
2960 if (fp_register_arg_p (typecode
, arg_type
))
2961 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM
);
2963 /* Write this portion of the argument to the stack. */
2964 if (argreg
> MIPS_LAST_ARG_REGNUM
)
2966 /* Should shorter than int integer values be
2967 promoted to int before being stored? */
2968 int longword_offset
= 0;
2971 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
2973 if ((typecode
== TYPE_CODE_INT
2974 || typecode
== TYPE_CODE_PTR
2975 || typecode
== TYPE_CODE_FLT
)
2977 longword_offset
= MIPS64_REGSIZE
- len
;
2982 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
2983 paddr_nz (stack_offset
));
2984 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
2985 paddr_nz (longword_offset
));
2988 addr
= sp
+ stack_offset
+ longword_offset
;
2993 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
2995 for (i
= 0; i
< partial_len
; i
++)
2997 fprintf_unfiltered (gdb_stdlog
, "%02x",
3001 write_memory (addr
, val
, partial_len
);
3004 /* Note!!! This is NOT an else clause. Odd sized
3005 structs may go thru BOTH paths. */
3006 /* Write this portion of the argument to a general
3007 purpose register. */
3008 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3011 extract_unsigned_integer (val
, partial_len
);
3013 /* A non-floating-point argument being passed in a
3014 general register. If a struct or union, and if
3015 the remaining length is smaller than the register
3016 size, we have to adjust the register value on
3019 It does not seem to be necessary to do the
3020 same for integral types. */
3022 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3023 && partial_len
< MIPS64_REGSIZE
3024 && (typecode
== TYPE_CODE_STRUCT
3025 || typecode
== TYPE_CODE_UNION
))
3026 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3030 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3032 phex (regval
, MIPS64_REGSIZE
));
3033 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3035 if (mips_n32n64_fp_arg_chunk_p (arg_type
,
3036 TYPE_LENGTH (arg_type
) - len
))
3039 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
3041 phex (regval
, MIPS64_REGSIZE
));
3042 regcache_cooked_write_unsigned (regcache
, float_argreg
,
3053 /* Compute the the offset into the stack at which we
3054 will copy the next parameter.
3056 In N32 (N64?), the stack_offset only needs to be
3057 adjusted when it has been used. */
3060 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3064 fprintf_unfiltered (gdb_stdlog
, "\n");
3067 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3069 /* Return adjusted stack pointer. */
3073 static enum return_value_convention
3074 mips_n32n64_return_value (struct gdbarch
*gdbarch
,
3075 struct type
*type
, struct regcache
*regcache
,
3076 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3078 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3080 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
3082 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
3083 if needed), as appropriate for the type. Composite results (struct,
3084 union, or array) are returned in $2/$f0 and $3/$f2 according to the
3087 * A struct with only one or two floating point fields is returned in $f0
3088 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
3091 * Any other struct or union results of at most 128 bits are returned in
3092 $2 (first 64 bits) and $3 (remainder, if necessary).
3094 * Larger composite results are handled by converting the function to a
3095 procedure with an implicit first parameter, which is a pointer to an area
3096 reserved by the caller to receive the result. [The o32-bit ABI requires
3097 that all composite results be handled by conversion to implicit first
3098 parameters. The MIPS/SGI Fortran implementation has always made a
3099 specific exception to return COMPLEX results in the floating point
3102 if (TYPE_CODE (type
) == TYPE_CODE_ARRAY
3103 || TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
3104 return RETURN_VALUE_STRUCT_CONVENTION
;
3105 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3106 && TYPE_LENGTH (type
) == 16
3107 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3109 /* A 128-bit floating-point value fills both $f0 and $f2. The
3110 two registers are used in the same as memory order, so the
3111 eight bytes with the lower memory address are in $f0. */
3113 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
3114 mips_xfer_register (regcache
,
3115 gdbarch_num_regs (current_gdbarch
)
3116 + mips_regnum (current_gdbarch
)->fp0
,
3117 8, gdbarch_byte_order (current_gdbarch
),
3118 readbuf
, writebuf
, 0);
3119 mips_xfer_register (regcache
,
3120 gdbarch_num_regs (current_gdbarch
)
3121 + mips_regnum (current_gdbarch
)->fp0
+ 2,
3122 8, gdbarch_byte_order (current_gdbarch
),
3123 readbuf
? readbuf
+ 8 : readbuf
,
3124 writebuf
? writebuf
+ 8 : writebuf
, 0);
3125 return RETURN_VALUE_REGISTER_CONVENTION
;
3127 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3128 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3130 /* A floating-point value belongs in the least significant part
3133 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3134 mips_xfer_register (regcache
,
3135 gdbarch_num_regs (current_gdbarch
)
3136 + mips_regnum (current_gdbarch
)->fp0
,
3138 gdbarch_byte_order (current_gdbarch
),
3139 readbuf
, writebuf
, 0);
3140 return RETURN_VALUE_REGISTER_CONVENTION
;
3142 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3143 && TYPE_NFIELDS (type
) <= 2
3144 && TYPE_NFIELDS (type
) >= 1
3145 && ((TYPE_NFIELDS (type
) == 1
3146 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3148 || (TYPE_NFIELDS (type
) == 2
3149 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 0)))
3151 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type
, 1)))
3153 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3155 /* A struct that contains one or two floats. Each value is part
3156 in the least significant part of their floating point
3160 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3161 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3163 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3166 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3168 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3170 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3171 gdbarch_byte_order (current_gdbarch
),
3172 readbuf
, writebuf
, offset
);
3174 return RETURN_VALUE_REGISTER_CONVENTION
;
3176 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3177 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3179 /* A structure or union. Extract the left justified value,
3180 regardless of the byte order. I.e. DO NOT USE
3184 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3185 offset
< TYPE_LENGTH (type
);
3186 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3188 int xfer
= register_size (current_gdbarch
, regnum
);
3189 if (offset
+ xfer
> TYPE_LENGTH (type
))
3190 xfer
= TYPE_LENGTH (type
) - offset
;
3192 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3193 offset
, xfer
, regnum
);
3194 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3196 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3198 return RETURN_VALUE_REGISTER_CONVENTION
;
3202 /* A scalar extract each part but least-significant-byte
3206 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3207 offset
< TYPE_LENGTH (type
);
3208 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3210 int xfer
= register_size (current_gdbarch
, regnum
);
3211 if (offset
+ xfer
> TYPE_LENGTH (type
))
3212 xfer
= TYPE_LENGTH (type
) - offset
;
3214 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3215 offset
, xfer
, regnum
);
3216 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3218 gdbarch_byte_order (current_gdbarch
),
3219 readbuf
, writebuf
, offset
);
3221 return RETURN_VALUE_REGISTER_CONVENTION
;
3225 /* O32 ABI stuff. */
3228 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3229 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3230 int nargs
, struct value
**args
, CORE_ADDR sp
,
3231 int struct_return
, CORE_ADDR struct_addr
)
3237 int stack_offset
= 0;
3238 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3239 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3241 /* For shared libraries, "t9" needs to point at the function
3243 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3245 /* Set the return address register to point to the entry point of
3246 the program, where a breakpoint lies in wait. */
3247 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3249 /* First ensure that the stack and structure return address (if any)
3250 are properly aligned. The stack has to be at least 64-bit
3251 aligned even on 32-bit machines, because doubles must be 64-bit
3252 aligned. For n32 and n64, stack frames need to be 128-bit
3253 aligned, so we round to this widest known alignment. */
3255 sp
= align_down (sp
, 16);
3256 struct_addr
= align_down (struct_addr
, 16);
3258 /* Now make space on the stack for the args. */
3259 for (argnum
= 0; argnum
< nargs
; argnum
++)
3261 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3262 int arglen
= TYPE_LENGTH (arg_type
);
3264 /* Align to double-word if necessary. */
3265 if (mips_type_needs_double_align (arg_type
))
3266 len
= align_up (len
, MIPS32_REGSIZE
* 2);
3267 /* Allocate space on the stack. */
3268 len
+= align_up (arglen
, MIPS32_REGSIZE
);
3270 sp
-= align_up (len
, 16);
3273 fprintf_unfiltered (gdb_stdlog
,
3274 "mips_o32_push_dummy_call: sp=0x%s allocated %ld\n",
3275 paddr_nz (sp
), (long) align_up (len
, 16));
3277 /* Initialize the integer and float register pointers. */
3278 argreg
= MIPS_A0_REGNUM
;
3279 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3281 /* The struct_return pointer occupies the first parameter-passing reg. */
3285 fprintf_unfiltered (gdb_stdlog
,
3286 "mips_o32_push_dummy_call: struct_return reg=%d 0x%s\n",
3287 argreg
, paddr_nz (struct_addr
));
3288 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3289 stack_offset
+= MIPS32_REGSIZE
;
3292 /* Now load as many as possible of the first arguments into
3293 registers, and push the rest onto the stack. Loop thru args
3294 from first to last. */
3295 for (argnum
= 0; argnum
< nargs
; argnum
++)
3297 const gdb_byte
*val
;
3298 struct value
*arg
= args
[argnum
];
3299 struct type
*arg_type
= check_typedef (value_type (arg
));
3300 int len
= TYPE_LENGTH (arg_type
);
3301 enum type_code typecode
= TYPE_CODE (arg_type
);
3304 fprintf_unfiltered (gdb_stdlog
,
3305 "mips_o32_push_dummy_call: %d len=%d type=%d",
3306 argnum
+ 1, len
, (int) typecode
);
3308 val
= value_contents (arg
);
3310 /* 32-bit ABIs always start floating point arguments in an
3311 even-numbered floating point register. Round the FP register
3312 up before the check to see if there are any FP registers
3313 left. O32/O64 targets also pass the FP in the integer
3314 registers so also round up normal registers. */
3315 if (fp_register_arg_p (typecode
, arg_type
))
3317 if ((float_argreg
& 1))
3321 /* Floating point arguments passed in registers have to be
3322 treated specially. On 32-bit architectures, doubles
3323 are passed in register pairs; the even register gets
3324 the low word, and the odd register gets the high word.
3325 On O32/O64, the first two floating point arguments are
3326 also copied to general registers, because MIPS16 functions
3327 don't use float registers for arguments. This duplication of
3328 arguments in general registers can't hurt non-MIPS16 functions
3329 because those registers are normally skipped. */
3331 if (fp_register_arg_p (typecode
, arg_type
)
3332 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3334 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
3336 int low_offset
= gdbarch_byte_order (current_gdbarch
)
3337 == BFD_ENDIAN_BIG
? 4 : 0;
3338 unsigned long regval
;
3340 /* Write the low word of the double to the even register(s). */
3341 regval
= extract_unsigned_integer (val
+ low_offset
, 4);
3343 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3344 float_argreg
, phex (regval
, 4));
3345 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3347 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3348 argreg
, phex (regval
, 4));
3349 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3351 /* Write the high word of the double to the odd register(s). */
3352 regval
= extract_unsigned_integer (val
+ 4 - low_offset
, 4);
3354 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3355 float_argreg
, phex (regval
, 4));
3356 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3359 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3360 argreg
, phex (regval
, 4));
3361 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
3365 /* This is a floating point value that fits entirely
3366 in a single register. */
3367 /* On 32 bit ABI's the float_argreg is further adjusted
3368 above to ensure that it is even register aligned. */
3369 LONGEST regval
= extract_unsigned_integer (val
, len
);
3371 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3372 float_argreg
, phex (regval
, len
));
3373 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3374 /* CAGNEY: 32 bit MIPS ABI's always reserve two FP
3375 registers for each argument. The below is (my
3376 guess) to ensure that the corresponding integer
3377 register has reserved the same space. */
3379 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3380 argreg
, phex (regval
, len
));
3381 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3384 /* Reserve space for the FP register. */
3385 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
3389 /* Copy the argument to general registers or the stack in
3390 register-sized pieces. Large arguments are split between
3391 registers and stack. */
3392 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
3393 are treated specially: Irix cc passes
3394 them in registers where gcc sometimes puts them on the
3395 stack. For maximum compatibility, we will put them in
3397 int odd_sized_struct
= (len
> MIPS32_REGSIZE
3398 && len
% MIPS32_REGSIZE
!= 0);
3399 /* Structures should be aligned to eight bytes (even arg registers)
3400 on MIPS_ABI_O32, if their first member has double precision. */
3401 if (mips_type_needs_double_align (arg_type
))
3406 stack_offset
+= MIPS32_REGSIZE
;
3411 /* Remember if the argument was written to the stack. */
3412 int stack_used_p
= 0;
3413 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
3416 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3419 /* Write this portion of the argument to the stack. */
3420 if (argreg
> MIPS_LAST_ARG_REGNUM
3421 || odd_sized_struct
)
3423 /* Should shorter than int integer values be
3424 promoted to int before being stored? */
3425 int longword_offset
= 0;
3431 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3432 paddr_nz (stack_offset
));
3433 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3434 paddr_nz (longword_offset
));
3437 addr
= sp
+ stack_offset
+ longword_offset
;
3442 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3444 for (i
= 0; i
< partial_len
; i
++)
3446 fprintf_unfiltered (gdb_stdlog
, "%02x",
3450 write_memory (addr
, val
, partial_len
);
3453 /* Note!!! This is NOT an else clause. Odd sized
3454 structs may go thru BOTH paths. */
3455 /* Write this portion of the argument to a general
3456 purpose register. */
3457 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3459 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3460 /* Value may need to be sign extended, because
3461 mips_isa_regsize() != mips_abi_regsize(). */
3463 /* A non-floating-point argument being passed in a
3464 general register. If a struct or union, and if
3465 the remaining length is smaller than the register
3466 size, we have to adjust the register value on
3469 It does not seem to be necessary to do the
3470 same for integral types.
3472 Also don't do this adjustment on O64 binaries.
3474 cagney/2001-07-23: gdb/179: Also, GCC, when
3475 outputting LE O32 with sizeof (struct) <
3476 mips_abi_regsize(), generates a left shift
3477 as part of storing the argument in a register
3478 (the left shift isn't generated when
3479 sizeof (struct) >= mips_abi_regsize()). Since
3480 it is quite possible that this is GCC
3481 contradicting the LE/O32 ABI, GDB has not been
3482 adjusted to accommodate this. Either someone
3483 needs to demonstrate that the LE/O32 ABI
3484 specifies such a left shift OR this new ABI gets
3485 identified as such and GDB gets tweaked
3488 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3489 && partial_len
< MIPS32_REGSIZE
3490 && (typecode
== TYPE_CODE_STRUCT
3491 || typecode
== TYPE_CODE_UNION
))
3492 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
3496 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3498 phex (regval
, MIPS32_REGSIZE
));
3499 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3502 /* Prevent subsequent floating point arguments from
3503 being passed in floating point registers. */
3504 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3510 /* Compute the the offset into the stack at which we
3511 will copy the next parameter.
3513 In older ABIs, the caller reserved space for
3514 registers that contained arguments. This was loosely
3515 refered to as their "home". Consequently, space is
3516 always allocated. */
3518 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
3522 fprintf_unfiltered (gdb_stdlog
, "\n");
3525 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3527 /* Return adjusted stack pointer. */
3531 static enum return_value_convention
3532 mips_o32_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
3533 struct regcache
*regcache
,
3534 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3536 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3538 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3539 || TYPE_CODE (type
) == TYPE_CODE_UNION
3540 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3541 return RETURN_VALUE_STRUCT_CONVENTION
;
3542 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3543 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3545 /* A single-precision floating-point value. It fits in the
3546 least significant part of FP0. */
3548 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3549 mips_xfer_register (regcache
,
3550 gdbarch_num_regs (current_gdbarch
)
3551 + mips_regnum (current_gdbarch
)->fp0
,
3553 gdbarch_byte_order (current_gdbarch
),
3554 readbuf
, writebuf
, 0);
3555 return RETURN_VALUE_REGISTER_CONVENTION
;
3557 else if (TYPE_CODE (type
) == TYPE_CODE_FLT
3558 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3560 /* A double-precision floating-point value. The most
3561 significant part goes in FP1, and the least significant in
3564 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
3565 switch (gdbarch_byte_order (current_gdbarch
))
3567 case BFD_ENDIAN_LITTLE
:
3568 mips_xfer_register (regcache
,
3569 gdbarch_num_regs (current_gdbarch
)
3570 + mips_regnum (current_gdbarch
)->fp0
+
3571 0, 4, gdbarch_byte_order (current_gdbarch
),
3572 readbuf
, writebuf
, 0);
3573 mips_xfer_register (regcache
,
3574 gdbarch_num_regs (current_gdbarch
)
3575 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3576 4, gdbarch_byte_order (current_gdbarch
),
3577 readbuf
, writebuf
, 4);
3579 case BFD_ENDIAN_BIG
:
3580 mips_xfer_register (regcache
,
3581 gdbarch_num_regs (current_gdbarch
)
3582 + mips_regnum (current_gdbarch
)->fp0
+ 1,
3583 4, gdbarch_byte_order (current_gdbarch
),
3584 readbuf
, writebuf
, 0);
3585 mips_xfer_register (regcache
,
3586 gdbarch_num_regs (current_gdbarch
)
3587 + mips_regnum (current_gdbarch
)->fp0
+ 0,
3588 4, gdbarch_byte_order (current_gdbarch
),
3589 readbuf
, writebuf
, 4);
3592 internal_error (__FILE__
, __LINE__
, _("bad switch"));
3594 return RETURN_VALUE_REGISTER_CONVENTION
;
3597 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3598 && TYPE_NFIELDS (type
) <= 2
3599 && TYPE_NFIELDS (type
) >= 1
3600 && ((TYPE_NFIELDS (type
) == 1
3601 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3603 || (TYPE_NFIELDS (type
) == 2
3604 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 0))
3606 && (TYPE_CODE (TYPE_FIELD_TYPE (type
, 1))
3608 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
3610 /* A struct that contains one or two floats. Each value is part
3611 in the least significant part of their floating point
3613 gdb_byte reg
[MAX_REGISTER_SIZE
];
3616 for (field
= 0, regnum
= mips_regnum (current_gdbarch
)->fp0
;
3617 field
< TYPE_NFIELDS (type
); field
++, regnum
+= 2)
3619 int offset
= (FIELD_BITPOS (TYPE_FIELDS (type
)[field
])
3622 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
3624 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3626 TYPE_LENGTH (TYPE_FIELD_TYPE (type
, field
)),
3627 gdbarch_byte_order (current_gdbarch
),
3628 readbuf
, writebuf
, offset
);
3630 return RETURN_VALUE_REGISTER_CONVENTION
;
3634 else if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3635 || TYPE_CODE (type
) == TYPE_CODE_UNION
)
3637 /* A structure or union. Extract the left justified value,
3638 regardless of the byte order. I.e. DO NOT USE
3642 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3643 offset
< TYPE_LENGTH (type
);
3644 offset
+= register_size (current_gdbarch
, regnum
), regnum
++)
3646 int xfer
= register_size (current_gdbarch
, regnum
);
3647 if (offset
+ xfer
> TYPE_LENGTH (type
))
3648 xfer
= TYPE_LENGTH (type
) - offset
;
3650 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
3651 offset
, xfer
, regnum
);
3652 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3654 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
3656 return RETURN_VALUE_REGISTER_CONVENTION
;
3661 /* A scalar extract each part but least-significant-byte
3662 justified. o32 thinks registers are 4 byte, regardless of
3666 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3667 offset
< TYPE_LENGTH (type
);
3668 offset
+= MIPS32_REGSIZE
, regnum
++)
3670 int xfer
= MIPS32_REGSIZE
;
3671 if (offset
+ xfer
> TYPE_LENGTH (type
))
3672 xfer
= TYPE_LENGTH (type
) - offset
;
3674 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3675 offset
, xfer
, regnum
);
3676 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3678 gdbarch_byte_order (current_gdbarch
),
3679 readbuf
, writebuf
, offset
);
3681 return RETURN_VALUE_REGISTER_CONVENTION
;
3685 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
3689 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
3690 struct regcache
*regcache
, CORE_ADDR bp_addr
,
3692 struct value
**args
, CORE_ADDR sp
,
3693 int struct_return
, CORE_ADDR struct_addr
)
3699 int stack_offset
= 0;
3700 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3701 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
3703 /* For shared libraries, "t9" needs to point at the function
3705 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
3707 /* Set the return address register to point to the entry point of
3708 the program, where a breakpoint lies in wait. */
3709 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
3711 /* First ensure that the stack and structure return address (if any)
3712 are properly aligned. The stack has to be at least 64-bit
3713 aligned even on 32-bit machines, because doubles must be 64-bit
3714 aligned. For n32 and n64, stack frames need to be 128-bit
3715 aligned, so we round to this widest known alignment. */
3717 sp
= align_down (sp
, 16);
3718 struct_addr
= align_down (struct_addr
, 16);
3720 /* Now make space on the stack for the args. */
3721 for (argnum
= 0; argnum
< nargs
; argnum
++)
3723 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
3724 int arglen
= TYPE_LENGTH (arg_type
);
3726 /* Allocate space on the stack. */
3727 len
+= align_up (arglen
, MIPS64_REGSIZE
);
3729 sp
-= align_up (len
, 16);
3732 fprintf_unfiltered (gdb_stdlog
,
3733 "mips_o64_push_dummy_call: sp=0x%s allocated %ld\n",
3734 paddr_nz (sp
), (long) align_up (len
, 16));
3736 /* Initialize the integer and float register pointers. */
3737 argreg
= MIPS_A0_REGNUM
;
3738 float_argreg
= mips_fpa0_regnum (current_gdbarch
);
3740 /* The struct_return pointer occupies the first parameter-passing reg. */
3744 fprintf_unfiltered (gdb_stdlog
,
3745 "mips_o64_push_dummy_call: struct_return reg=%d 0x%s\n",
3746 argreg
, paddr_nz (struct_addr
));
3747 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
3748 stack_offset
+= MIPS64_REGSIZE
;
3751 /* Now load as many as possible of the first arguments into
3752 registers, and push the rest onto the stack. Loop thru args
3753 from first to last. */
3754 for (argnum
= 0; argnum
< nargs
; argnum
++)
3756 const gdb_byte
*val
;
3757 struct value
*arg
= args
[argnum
];
3758 struct type
*arg_type
= check_typedef (value_type (arg
));
3759 int len
= TYPE_LENGTH (arg_type
);
3760 enum type_code typecode
= TYPE_CODE (arg_type
);
3763 fprintf_unfiltered (gdb_stdlog
,
3764 "mips_o64_push_dummy_call: %d len=%d type=%d",
3765 argnum
+ 1, len
, (int) typecode
);
3767 val
= value_contents (arg
);
3769 /* Floating point arguments passed in registers have to be
3770 treated specially. On 32-bit architectures, doubles
3771 are passed in register pairs; the even register gets
3772 the low word, and the odd register gets the high word.
3773 On O32/O64, the first two floating point arguments are
3774 also copied to general registers, because MIPS16 functions
3775 don't use float registers for arguments. This duplication of
3776 arguments in general registers can't hurt non-MIPS16 functions
3777 because those registers are normally skipped. */
3779 if (fp_register_arg_p (typecode
, arg_type
)
3780 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM
)
3782 LONGEST regval
= extract_unsigned_integer (val
, len
);
3784 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
3785 float_argreg
, phex (regval
, len
));
3786 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
3788 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
3789 argreg
, phex (regval
, len
));
3790 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3792 /* Reserve space for the FP register. */
3793 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
3797 /* Copy the argument to general registers or the stack in
3798 register-sized pieces. Large arguments are split between
3799 registers and stack. */
3800 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
3801 are treated specially: Irix cc passes them in registers
3802 where gcc sometimes puts them on the stack. For maximum
3803 compatibility, we will put them in both places. */
3804 int odd_sized_struct
= (len
> MIPS64_REGSIZE
3805 && len
% MIPS64_REGSIZE
!= 0);
3808 /* Remember if the argument was written to the stack. */
3809 int stack_used_p
= 0;
3810 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
3813 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
3816 /* Write this portion of the argument to the stack. */
3817 if (argreg
> MIPS_LAST_ARG_REGNUM
3818 || odd_sized_struct
)
3820 /* Should shorter than int integer values be
3821 promoted to int before being stored? */
3822 int longword_offset
= 0;
3825 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
3827 if ((typecode
== TYPE_CODE_INT
3828 || typecode
== TYPE_CODE_PTR
3829 || typecode
== TYPE_CODE_FLT
)
3831 longword_offset
= MIPS64_REGSIZE
- len
;
3836 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=0x%s",
3837 paddr_nz (stack_offset
));
3838 fprintf_unfiltered (gdb_stdlog
, " longword_offset=0x%s",
3839 paddr_nz (longword_offset
));
3842 addr
= sp
+ stack_offset
+ longword_offset
;
3847 fprintf_unfiltered (gdb_stdlog
, " @0x%s ",
3849 for (i
= 0; i
< partial_len
; i
++)
3851 fprintf_unfiltered (gdb_stdlog
, "%02x",
3855 write_memory (addr
, val
, partial_len
);
3858 /* Note!!! This is NOT an else clause. Odd sized
3859 structs may go thru BOTH paths. */
3860 /* Write this portion of the argument to a general
3861 purpose register. */
3862 if (argreg
<= MIPS_LAST_ARG_REGNUM
)
3864 LONGEST regval
= extract_signed_integer (val
, partial_len
);
3865 /* Value may need to be sign extended, because
3866 mips_isa_regsize() != mips_abi_regsize(). */
3868 /* A non-floating-point argument being passed in a
3869 general register. If a struct or union, and if
3870 the remaining length is smaller than the register
3871 size, we have to adjust the register value on
3874 It does not seem to be necessary to do the
3875 same for integral types. */
3877 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
3878 && partial_len
< MIPS64_REGSIZE
3879 && (typecode
== TYPE_CODE_STRUCT
3880 || typecode
== TYPE_CODE_UNION
))
3881 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
3885 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
3887 phex (regval
, MIPS64_REGSIZE
));
3888 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
3891 /* Prevent subsequent floating point arguments from
3892 being passed in floating point registers. */
3893 float_argreg
= MIPS_LAST_FP_ARG_REGNUM
+ 1;
3899 /* Compute the the offset into the stack at which we
3900 will copy the next parameter.
3902 In older ABIs, the caller reserved space for
3903 registers that contained arguments. This was loosely
3904 refered to as their "home". Consequently, space is
3905 always allocated. */
3907 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
3911 fprintf_unfiltered (gdb_stdlog
, "\n");
3914 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
3916 /* Return adjusted stack pointer. */
3920 static enum return_value_convention
3921 mips_o64_return_value (struct gdbarch
*gdbarch
,
3922 struct type
*type
, struct regcache
*regcache
,
3923 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
3925 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
3927 if (TYPE_CODE (type
) == TYPE_CODE_STRUCT
3928 || TYPE_CODE (type
) == TYPE_CODE_UNION
3929 || TYPE_CODE (type
) == TYPE_CODE_ARRAY
)
3930 return RETURN_VALUE_STRUCT_CONVENTION
;
3931 else if (fp_register_arg_p (TYPE_CODE (type
), type
))
3933 /* A floating-point value. It fits in the least significant
3936 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
3937 mips_xfer_register (regcache
,
3938 gdbarch_num_regs (current_gdbarch
)
3939 + mips_regnum (current_gdbarch
)->fp0
,
3941 gdbarch_byte_order (current_gdbarch
),
3942 readbuf
, writebuf
, 0);
3943 return RETURN_VALUE_REGISTER_CONVENTION
;
3947 /* A scalar extract each part but least-significant-byte
3951 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
3952 offset
< TYPE_LENGTH (type
);
3953 offset
+= MIPS64_REGSIZE
, regnum
++)
3955 int xfer
= MIPS64_REGSIZE
;
3956 if (offset
+ xfer
> TYPE_LENGTH (type
))
3957 xfer
= TYPE_LENGTH (type
) - offset
;
3959 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
3960 offset
, xfer
, regnum
);
3961 mips_xfer_register (regcache
, gdbarch_num_regs (current_gdbarch
)
3963 gdbarch_byte_order (current_gdbarch
),
3964 readbuf
, writebuf
, offset
);
3966 return RETURN_VALUE_REGISTER_CONVENTION
;
3970 /* Floating point register management.
3972 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
3973 64bit operations, these early MIPS cpus treat fp register pairs
3974 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
3975 registers and offer a compatibility mode that emulates the MIPS2 fp
3976 model. When operating in MIPS2 fp compat mode, later cpu's split
3977 double precision floats into two 32-bit chunks and store them in
3978 consecutive fp regs. To display 64-bit floats stored in this
3979 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
3980 Throw in user-configurable endianness and you have a real mess.
3982 The way this works is:
3983 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
3984 double-precision value will be split across two logical registers.
3985 The lower-numbered logical register will hold the low-order bits,
3986 regardless of the processor's endianness.
3987 - If we are on a 64-bit processor, and we are looking for a
3988 single-precision value, it will be in the low ordered bits
3989 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
3990 save slot in memory.
3991 - If we are in 64-bit mode, everything is straightforward.
3993 Note that this code only deals with "live" registers at the top of the
3994 stack. We will attempt to deal with saved registers later, when
3995 the raw/cooked register interface is in place. (We need a general
3996 interface that can deal with dynamic saved register sizes -- fp
3997 regs could be 32 bits wide in one frame and 64 on the frame above
4000 static struct type
*
4001 mips_float_register_type (void)
4003 return builtin_type_ieee_single
;
4006 static struct type
*
4007 mips_double_register_type (void)
4009 return builtin_type_ieee_double
;
4012 /* Copy a 32-bit single-precision value from the current frame
4013 into rare_buffer. */
4016 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
4017 gdb_byte
*rare_buffer
)
4019 int raw_size
= register_size (current_gdbarch
, regno
);
4020 gdb_byte
*raw_buffer
= alloca (raw_size
);
4022 if (!frame_register_read (frame
, regno
, raw_buffer
))
4023 error (_("can't read register %d (%s)"),
4024 regno
, gdbarch_register_name (current_gdbarch
, regno
));
4027 /* We have a 64-bit value for this register. Find the low-order
4031 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4036 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
4040 memcpy (rare_buffer
, raw_buffer
, 4);
4044 /* Copy a 64-bit double-precision value from the current frame into
4045 rare_buffer. This may include getting half of it from the next
4049 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
4050 gdb_byte
*rare_buffer
)
4052 int raw_size
= register_size (current_gdbarch
, regno
);
4054 if (raw_size
== 8 && !mips2_fp_compat (frame
))
4056 /* We have a 64-bit value for this register, and we should use
4058 if (!frame_register_read (frame
, regno
, rare_buffer
))
4059 error (_("can't read register %d (%s)"),
4060 regno
, gdbarch_register_name (current_gdbarch
, regno
));
4064 if ((regno
- mips_regnum (current_gdbarch
)->fp0
) & 1)
4065 internal_error (__FILE__
, __LINE__
,
4066 _("mips_read_fp_register_double: bad access to "
4067 "odd-numbered FP register"));
4069 /* mips_read_fp_register_single will find the correct 32 bits from
4071 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4073 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
4074 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
4078 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
4079 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
4085 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
4087 { /* do values for FP (float) regs */
4088 gdb_byte
*raw_buffer
;
4089 double doub
, flt1
; /* doubles extracted from raw hex data */
4092 raw_buffer
= alloca (2 * register_size (current_gdbarch
,
4093 mips_regnum (current_gdbarch
)->fp0
));
4095 fprintf_filtered (file
, "%s:",
4096 gdbarch_register_name (current_gdbarch
, regnum
));
4097 fprintf_filtered (file
, "%*s",
4098 4 - (int) strlen (gdbarch_register_name
4099 (current_gdbarch
, regnum
)),
4102 if (register_size (current_gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
4104 /* 4-byte registers: Print hex and floating. Also print even
4105 numbered registers as doubles. */
4106 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4107 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4109 print_scalar_formatted (raw_buffer
, builtin_type_uint32
, 'x', 'w',
4112 fprintf_filtered (file
, " flt: ");
4114 fprintf_filtered (file
, " <invalid float> ");
4116 fprintf_filtered (file
, "%-17.9g", flt1
);
4118 if (regnum
% 2 == 0)
4120 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4121 doub
= unpack_double (mips_double_register_type (), raw_buffer
,
4124 fprintf_filtered (file
, " dbl: ");
4126 fprintf_filtered (file
, "<invalid double>");
4128 fprintf_filtered (file
, "%-24.17g", doub
);
4133 /* Eight byte registers: print each one as hex, float and double. */
4134 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
4135 flt1
= unpack_double (mips_float_register_type (), raw_buffer
, &inv1
);
4137 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
4138 doub
= unpack_double (mips_double_register_type (), raw_buffer
, &inv2
);
4141 print_scalar_formatted (raw_buffer
, builtin_type_uint64
, 'x', 'g',
4144 fprintf_filtered (file
, " flt: ");
4146 fprintf_filtered (file
, "<invalid float>");
4148 fprintf_filtered (file
, "%-17.9g", flt1
);
4150 fprintf_filtered (file
, " dbl: ");
4152 fprintf_filtered (file
, "<invalid double>");
4154 fprintf_filtered (file
, "%-24.17g", doub
);
4159 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
4162 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4163 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4166 if (TYPE_CODE (register_type (gdbarch
, regnum
)) == TYPE_CODE_FLT
)
4168 mips_print_fp_register (file
, frame
, regnum
);
4172 /* Get the data in raw format. */
4173 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4175 fprintf_filtered (file
, "%s: [Invalid]",
4176 gdbarch_register_name (current_gdbarch
, regnum
));
4180 fputs_filtered (gdbarch_register_name (current_gdbarch
, regnum
), file
);
4182 /* The problem with printing numeric register names (r26, etc.) is that
4183 the user can't use them on input. Probably the best solution is to
4184 fix it so that either the numeric or the funky (a2, etc.) names
4185 are accepted on input. */
4186 if (regnum
< MIPS_NUMREGS
)
4187 fprintf_filtered (file
, "(r%d): ", regnum
);
4189 fprintf_filtered (file
, ": ");
4191 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4193 register_size (current_gdbarch
,
4194 regnum
) - register_size (current_gdbarch
, regnum
);
4198 print_scalar_formatted (raw_buffer
+ offset
,
4199 register_type (gdbarch
, regnum
), 'x', 0,
4203 /* Replacement for generic do_registers_info.
4204 Print regs in pretty columns. */
4207 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4210 fprintf_filtered (file
, " ");
4211 mips_print_fp_register (file
, frame
, regnum
);
4212 fprintf_filtered (file
, "\n");
4217 /* Print a row's worth of GP (int) registers, with name labels above */
4220 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
4223 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4224 /* do values for GP (int) regs */
4225 gdb_byte raw_buffer
[MAX_REGISTER_SIZE
];
4226 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols per row */
4230 /* For GP registers, we print a separate row of names above the vals */
4231 for (col
= 0, regnum
= start_regnum
;
4232 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4233 + gdbarch_num_pseudo_regs (current_gdbarch
);
4236 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4237 continue; /* unused register */
4238 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4240 break; /* end the row: reached FP register */
4241 /* Large registers are handled separately. */
4242 if (register_size (current_gdbarch
, regnum
)
4243 > mips_abi_regsize (current_gdbarch
))
4246 break; /* End the row before this register. */
4248 /* Print this register on a row by itself. */
4249 mips_print_register (file
, frame
, regnum
);
4250 fprintf_filtered (file
, "\n");
4254 fprintf_filtered (file
, " ");
4255 fprintf_filtered (file
,
4256 mips_abi_regsize (current_gdbarch
) == 8 ? "%17s" : "%9s",
4257 gdbarch_register_name (current_gdbarch
, regnum
));
4264 /* print the R0 to R31 names */
4265 if ((start_regnum
% gdbarch_num_regs (current_gdbarch
)) < MIPS_NUMREGS
)
4266 fprintf_filtered (file
, "\n R%-4d",
4267 start_regnum
% gdbarch_num_regs (current_gdbarch
));
4269 fprintf_filtered (file
, "\n ");
4271 /* now print the values in hex, 4 or 8 to the row */
4272 for (col
= 0, regnum
= start_regnum
;
4273 col
< ncols
&& regnum
< gdbarch_num_regs (current_gdbarch
)
4274 + gdbarch_num_pseudo_regs (current_gdbarch
);
4277 if (*gdbarch_register_name (current_gdbarch
, regnum
) == '\0')
4278 continue; /* unused register */
4279 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4281 break; /* end row: reached FP register */
4282 if (register_size (current_gdbarch
, regnum
)
4283 > mips_abi_regsize (current_gdbarch
))
4284 break; /* End row: large register. */
4286 /* OK: get the data in raw format. */
4287 if (!frame_register_read (frame
, regnum
, raw_buffer
))
4288 error (_("can't read register %d (%s)"),
4289 regnum
, gdbarch_register_name (current_gdbarch
, regnum
));
4290 /* pad small registers */
4292 byte
< (mips_abi_regsize (current_gdbarch
)
4293 - register_size (current_gdbarch
, regnum
)); byte
++)
4294 printf_filtered (" ");
4295 /* Now print the register value in hex, endian order. */
4296 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4298 register_size (current_gdbarch
,
4299 regnum
) - register_size (current_gdbarch
, regnum
);
4300 byte
< register_size (current_gdbarch
, regnum
); byte
++)
4301 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4303 for (byte
= register_size (current_gdbarch
, regnum
) - 1;
4305 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
4306 fprintf_filtered (file
, " ");
4309 if (col
> 0) /* ie. if we actually printed anything... */
4310 fprintf_filtered (file
, "\n");
4315 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command */
4318 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
4319 struct frame_info
*frame
, int regnum
, int all
)
4321 if (regnum
!= -1) /* do one specified register */
4323 gdb_assert (regnum
>= gdbarch_num_regs (current_gdbarch
));
4324 if (*(gdbarch_register_name (current_gdbarch
, regnum
)) == '\0')
4325 error (_("Not a valid register for the current processor type"));
4327 mips_print_register (file
, frame
, regnum
);
4328 fprintf_filtered (file
, "\n");
4331 /* do all (or most) registers */
4333 regnum
= gdbarch_num_regs (current_gdbarch
);
4334 while (regnum
< gdbarch_num_regs (current_gdbarch
)
4335 + gdbarch_num_pseudo_regs (current_gdbarch
))
4337 if (TYPE_CODE (register_type (gdbarch
, regnum
)) ==
4340 if (all
) /* true for "INFO ALL-REGISTERS" command */
4341 regnum
= print_fp_register_row (file
, frame
, regnum
);
4343 regnum
+= MIPS_NUMREGS
; /* skip floating point regs */
4346 regnum
= print_gp_register_row (file
, frame
, regnum
);
4351 /* Is this a branch with a delay slot? */
4354 is_delayed (unsigned long insn
)
4357 for (i
= 0; i
< NUMOPCODES
; ++i
)
4358 if (mips_opcodes
[i
].pinfo
!= INSN_MACRO
4359 && (insn
& mips_opcodes
[i
].mask
) == mips_opcodes
[i
].match
)
4361 return (i
< NUMOPCODES
4362 && (mips_opcodes
[i
].pinfo
& (INSN_UNCOND_BRANCH_DELAY
4363 | INSN_COND_BRANCH_DELAY
4364 | INSN_COND_BRANCH_LIKELY
)));
4368 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
4369 struct frame_info
*frame
)
4371 CORE_ADDR pc
= get_frame_pc (frame
);
4372 gdb_byte buf
[MIPS_INSN32_SIZE
];
4374 /* There is no branch delay slot on MIPS16. */
4375 if (mips_pc_is_mips16 (pc
))
4378 if (!breakpoint_here_p (pc
+ 4))
4381 if (!safe_frame_unwind_memory (frame
, pc
, buf
, sizeof buf
))
4382 /* If error reading memory, guess that it is not a delayed
4385 return is_delayed (extract_unsigned_integer (buf
, sizeof buf
));
4388 /* To skip prologues, I use this predicate. Returns either PC itself
4389 if the code at PC does not look like a function prologue; otherwise
4390 returns an address that (if we're lucky) follows the prologue. If
4391 LENIENT, then we must skip everything which is involved in setting
4392 up the frame (it's OK to skip more, just so long as we don't skip
4393 anything which might clobber the registers which are being saved.
4394 We must skip more in the case where part of the prologue is in the
4395 delay slot of a non-prologue instruction). */
4398 mips_skip_prologue (CORE_ADDR pc
)
4401 CORE_ADDR func_addr
;
4403 /* See if we can determine the end of the prologue via the symbol table.
4404 If so, then return either PC, or the PC after the prologue, whichever
4406 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
4408 CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (func_addr
);
4409 if (post_prologue_pc
!= 0)
4410 return max (pc
, post_prologue_pc
);
4413 /* Can't determine prologue from the symbol table, need to examine
4416 /* Find an upper limit on the function prologue using the debug
4417 information. If the debug information could not be used to provide
4418 that bound, then use an arbitrary large number as the upper bound. */
4419 limit_pc
= skip_prologue_using_sal (pc
);
4421 limit_pc
= pc
+ 100; /* Magic. */
4423 if (mips_pc_is_mips16 (pc
))
4424 return mips16_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4426 return mips32_scan_prologue (pc
, limit_pc
, NULL
, NULL
);
4429 /* Check whether the PC is in a function epilogue (32-bit version).
4430 This is a helper function for mips_in_function_epilogue_p. */
4432 mips32_in_function_epilogue_p (CORE_ADDR pc
)
4434 CORE_ADDR func_addr
= 0, func_end
= 0;
4436 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4438 /* The MIPS epilogue is max. 12 bytes long. */
4439 CORE_ADDR addr
= func_end
- 12;
4441 if (addr
< func_addr
+ 4)
4442 addr
= func_addr
+ 4;
4446 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
4448 unsigned long high_word
;
4451 inst
= mips_fetch_instruction (pc
);
4452 high_word
= (inst
>> 16) & 0xffff;
4454 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
4455 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
4456 && inst
!= 0x03e00008 /* jr $ra */
4457 && inst
!= 0x00000000) /* nop */
4467 /* Check whether the PC is in a function epilogue (16-bit version).
4468 This is a helper function for mips_in_function_epilogue_p. */
4470 mips16_in_function_epilogue_p (CORE_ADDR pc
)
4472 CORE_ADDR func_addr
= 0, func_end
= 0;
4474 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
4476 /* The MIPS epilogue is max. 12 bytes long. */
4477 CORE_ADDR addr
= func_end
- 12;
4479 if (addr
< func_addr
+ 4)
4480 addr
= func_addr
+ 4;
4484 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
4486 unsigned short inst
;
4488 inst
= mips_fetch_instruction (pc
);
4490 if ((inst
& 0xf800) == 0xf000) /* extend */
4493 if (inst
!= 0x6300 /* addiu $sp,offset */
4494 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
4495 && inst
!= 0xe820 /* jr $ra */
4496 && inst
!= 0xe8a0 /* jrc $ra */
4497 && inst
!= 0x6500) /* nop */
4507 /* The epilogue is defined here as the area at the end of a function,
4508 after an instruction which destroys the function's stack frame. */
4510 mips_in_function_epilogue_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4512 if (mips_pc_is_mips16 (pc
))
4513 return mips16_in_function_epilogue_p (pc
);
4515 return mips32_in_function_epilogue_p (pc
);
4518 /* Root of all "set mips "/"show mips " commands. This will eventually be
4519 used for all MIPS-specific commands. */
4522 show_mips_command (char *args
, int from_tty
)
4524 help_list (showmipscmdlist
, "show mips ", all_commands
, gdb_stdout
);
4528 set_mips_command (char *args
, int from_tty
)
4531 ("\"set mips\" must be followed by an appropriate subcommand.\n");
4532 help_list (setmipscmdlist
, "set mips ", all_commands
, gdb_stdout
);
4535 /* Commands to show/set the MIPS FPU type. */
4538 show_mipsfpu_command (char *args
, int from_tty
)
4541 switch (MIPS_FPU_TYPE
)
4543 case MIPS_FPU_SINGLE
:
4544 fpu
= "single-precision";
4546 case MIPS_FPU_DOUBLE
:
4547 fpu
= "double-precision";
4550 fpu
= "absent (none)";
4553 internal_error (__FILE__
, __LINE__
, _("bad switch"));
4555 if (mips_fpu_type_auto
)
4557 ("The MIPS floating-point coprocessor is set automatically (currently %s)\n",
4561 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
4566 set_mipsfpu_command (char *args
, int from_tty
)
4569 ("\"set mipsfpu\" must be followed by \"double\", \"single\",\"none\" or \"auto\".\n");
4570 show_mipsfpu_command (args
, from_tty
);
4574 set_mipsfpu_single_command (char *args
, int from_tty
)
4576 struct gdbarch_info info
;
4577 gdbarch_info_init (&info
);
4578 mips_fpu_type
= MIPS_FPU_SINGLE
;
4579 mips_fpu_type_auto
= 0;
4580 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4581 instead of relying on globals. Doing that would let generic code
4582 handle the search for this specific architecture. */
4583 if (!gdbarch_update_p (info
))
4584 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4588 set_mipsfpu_double_command (char *args
, int from_tty
)
4590 struct gdbarch_info info
;
4591 gdbarch_info_init (&info
);
4592 mips_fpu_type
= MIPS_FPU_DOUBLE
;
4593 mips_fpu_type_auto
= 0;
4594 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4595 instead of relying on globals. Doing that would let generic code
4596 handle the search for this specific architecture. */
4597 if (!gdbarch_update_p (info
))
4598 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4602 set_mipsfpu_none_command (char *args
, int from_tty
)
4604 struct gdbarch_info info
;
4605 gdbarch_info_init (&info
);
4606 mips_fpu_type
= MIPS_FPU_NONE
;
4607 mips_fpu_type_auto
= 0;
4608 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
4609 instead of relying on globals. Doing that would let generic code
4610 handle the search for this specific architecture. */
4611 if (!gdbarch_update_p (info
))
4612 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
4616 set_mipsfpu_auto_command (char *args
, int from_tty
)
4618 mips_fpu_type_auto
= 1;
4621 /* Attempt to identify the particular processor model by reading the
4622 processor id. NOTE: cagney/2003-11-15: Firstly it isn't clear that
4623 the relevant processor still exists (it dates back to '94) and
4624 secondly this is not the way to do this. The processor type should
4625 be set by forcing an architecture change. */
4628 deprecated_mips_set_processor_regs_hack (void)
4630 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4633 regcache_cooked_read_unsigned (get_current_regcache (),
4634 MIPS_PRID_REGNUM
, &prid
);
4635 if ((prid
& ~0xf) == 0x700)
4636 tdep
->mips_processor_reg_names
= mips_r3041_reg_names
;
4639 /* Just like reinit_frame_cache, but with the right arguments to be
4640 callable as an sfunc. */
4643 reinit_frame_cache_sfunc (char *args
, int from_tty
,
4644 struct cmd_list_element
*c
)
4646 reinit_frame_cache ();
4650 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
4652 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
4654 /* FIXME: cagney/2003-06-26: Is this even necessary? The
4655 disassembler needs to be able to locally determine the ISA, and
4656 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
4658 if (mips_pc_is_mips16 (memaddr
))
4659 info
->mach
= bfd_mach_mips16
;
4661 /* Round down the instruction address to the appropriate boundary. */
4662 memaddr
&= (info
->mach
== bfd_mach_mips16
? ~1 : ~3);
4664 /* Set the disassembler options. */
4665 if (tdep
->mips_abi
== MIPS_ABI_N32
|| tdep
->mips_abi
== MIPS_ABI_N64
)
4667 /* Set up the disassembler info, so that we get the right
4668 register names from libopcodes. */
4669 if (tdep
->mips_abi
== MIPS_ABI_N32
)
4670 info
->disassembler_options
= "gpr-names=n32";
4672 info
->disassembler_options
= "gpr-names=64";
4673 info
->flavour
= bfd_target_elf_flavour
;
4676 /* This string is not recognized explicitly by the disassembler,
4677 but it tells the disassembler to not try to guess the ABI from
4678 the bfd elf headers, such that, if the user overrides the ABI
4679 of a program linked as NewABI, the disassembly will follow the
4680 register naming conventions specified by the user. */
4681 info
->disassembler_options
= "gpr-names=32";
4683 /* Call the appropriate disassembler based on the target endian-ness. */
4684 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4685 return print_insn_big_mips (memaddr
, info
);
4687 return print_insn_little_mips (memaddr
, info
);
4690 /* This function implements gdbarch_breakpoint_from_pc. It uses the program
4691 counter value to determine whether a 16- or 32-bit breakpoint should be used.
4692 It returns a pointer to a string of bytes that encode a breakpoint
4693 instruction, stores the length of the string to *lenptr, and adjusts pc (if
4694 necessary) to point to the actual memory location where the breakpoint
4695 should be inserted. */
4697 static const gdb_byte
*
4698 mips_breakpoint_from_pc (CORE_ADDR
*pcptr
, int *lenptr
)
4700 if (gdbarch_byte_order (current_gdbarch
) == BFD_ENDIAN_BIG
)
4702 if (mips_pc_is_mips16 (*pcptr
))
4704 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
4705 *pcptr
= unmake_mips16_addr (*pcptr
);
4706 *lenptr
= sizeof (mips16_big_breakpoint
);
4707 return mips16_big_breakpoint
;
4711 /* The IDT board uses an unusual breakpoint value, and
4712 sometimes gets confused when it sees the usual MIPS
4713 breakpoint instruction. */
4714 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
4715 static gdb_byte pmon_big_breakpoint
[] = { 0, 0, 0, 0xd };
4716 static gdb_byte idt_big_breakpoint
[] = { 0, 0, 0x0a, 0xd };
4718 *lenptr
= sizeof (big_breakpoint
);
4720 if (strcmp (target_shortname
, "mips") == 0)
4721 return idt_big_breakpoint
;
4722 else if (strcmp (target_shortname
, "ddb") == 0
4723 || strcmp (target_shortname
, "pmon") == 0
4724 || strcmp (target_shortname
, "lsi") == 0)
4725 return pmon_big_breakpoint
;
4727 return big_breakpoint
;
4732 if (mips_pc_is_mips16 (*pcptr
))
4734 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
4735 *pcptr
= unmake_mips16_addr (*pcptr
);
4736 *lenptr
= sizeof (mips16_little_breakpoint
);
4737 return mips16_little_breakpoint
;
4741 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
4742 static gdb_byte pmon_little_breakpoint
[] = { 0xd, 0, 0, 0 };
4743 static gdb_byte idt_little_breakpoint
[] = { 0xd, 0x0a, 0, 0 };
4745 *lenptr
= sizeof (little_breakpoint
);
4747 if (strcmp (target_shortname
, "mips") == 0)
4748 return idt_little_breakpoint
;
4749 else if (strcmp (target_shortname
, "ddb") == 0
4750 || strcmp (target_shortname
, "pmon") == 0
4751 || strcmp (target_shortname
, "lsi") == 0)
4752 return pmon_little_breakpoint
;
4754 return little_breakpoint
;
4759 /* If PC is in a mips16 call or return stub, return the address of the target
4760 PC, which is either the callee or the caller. There are several
4761 cases which must be handled:
4763 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4764 target PC is in $31 ($ra).
4765 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4766 and the target PC is in $2.
4767 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4768 before the jal instruction, this is effectively a call stub
4769 and the the target PC is in $2. Otherwise this is effectively
4770 a return stub and the target PC is in $18.
4772 See the source code for the stubs in gcc/config/mips/mips16.S for
4776 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
4779 CORE_ADDR start_addr
;
4781 /* Find the starting address and name of the function containing the PC. */
4782 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
4785 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the
4786 target PC is in $31 ($ra). */
4787 if (strcmp (name
, "__mips16_ret_sf") == 0
4788 || strcmp (name
, "__mips16_ret_df") == 0)
4789 return get_frame_register_signed (frame
, MIPS_RA_REGNUM
);
4791 if (strncmp (name
, "__mips16_call_stub_", 19) == 0)
4793 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
4794 and the target PC is in $2. */
4795 if (name
[19] >= '0' && name
[19] <= '9')
4796 return get_frame_register_signed (frame
, 2);
4798 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e.
4799 before the jal instruction, this is effectively a call stub
4800 and the the target PC is in $2. Otherwise this is effectively
4801 a return stub and the target PC is in $18. */
4802 else if (name
[19] == 's' || name
[19] == 'd')
4804 if (pc
== start_addr
)
4806 /* Check if the target of the stub is a compiler-generated
4807 stub. Such a stub for a function bar might have a name
4808 like __fn_stub_bar, and might look like this:
4813 la $1,bar (becomes a lui/addiu pair)
4815 So scan down to the lui/addi and extract the target
4816 address from those two instructions. */
4818 CORE_ADDR target_pc
= get_frame_register_signed (frame
, 2);
4822 /* See if the name of the target function is __fn_stub_*. */
4823 if (find_pc_partial_function (target_pc
, &name
, NULL
, NULL
) ==
4826 if (strncmp (name
, "__fn_stub_", 10) != 0
4827 && strcmp (name
, "etext") != 0
4828 && strcmp (name
, "_etext") != 0)
4831 /* Scan through this _fn_stub_ code for the lui/addiu pair.
4832 The limit on the search is arbitrarily set to 20
4833 instructions. FIXME. */
4834 for (i
= 0, pc
= 0; i
< 20; i
++, target_pc
+= MIPS_INSN32_SIZE
)
4836 inst
= mips_fetch_instruction (target_pc
);
4837 if ((inst
& 0xffff0000) == 0x3c010000) /* lui $at */
4838 pc
= (inst
<< 16) & 0xffff0000; /* high word */
4839 else if ((inst
& 0xffff0000) == 0x24210000) /* addiu $at */
4840 return pc
| (inst
& 0xffff); /* low word */
4843 /* Couldn't find the lui/addui pair, so return stub address. */
4847 /* This is the 'return' part of a call stub. The return
4848 address is in $r18. */
4849 return get_frame_register_signed (frame
, 18);
4852 return 0; /* not a stub */
4855 /* Convert a dbx stab register number (from `r' declaration) to a GDB
4856 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4859 mips_stab_reg_to_regnum (int num
)
4862 if (num
>= 0 && num
< 32)
4864 else if (num
>= 38 && num
< 70)
4865 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 38;
4867 regnum
= mips_regnum (current_gdbarch
)->hi
;
4869 regnum
= mips_regnum (current_gdbarch
)->lo
;
4871 /* This will hopefully (eventually) provoke a warning. Should
4872 we be calling complaint() here? */
4873 return gdbarch_num_regs (current_gdbarch
)
4874 + gdbarch_num_pseudo_regs (current_gdbarch
);
4875 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4879 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
4880 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
4883 mips_dwarf_dwarf2_ecoff_reg_to_regnum (int num
)
4886 if (num
>= 0 && num
< 32)
4888 else if (num
>= 32 && num
< 64)
4889 regnum
= num
+ mips_regnum (current_gdbarch
)->fp0
- 32;
4891 regnum
= mips_regnum (current_gdbarch
)->hi
;
4893 regnum
= mips_regnum (current_gdbarch
)->lo
;
4895 /* This will hopefully (eventually) provoke a warning. Should we
4896 be calling complaint() here? */
4897 return gdbarch_num_regs (current_gdbarch
)
4898 + gdbarch_num_pseudo_regs (current_gdbarch
);
4899 return gdbarch_num_regs (current_gdbarch
) + regnum
;
4903 mips_register_sim_regno (int regnum
)
4905 /* Only makes sense to supply raw registers. */
4906 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (current_gdbarch
));
4907 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
4908 decide if it is valid. Should instead define a standard sim/gdb
4909 register numbering scheme. */
4910 if (gdbarch_register_name (current_gdbarch
,
4912 (current_gdbarch
) + regnum
) != NULL
4913 && gdbarch_register_name (current_gdbarch
,
4915 (current_gdbarch
) + regnum
)[0] != '\0')
4918 return LEGACY_SIM_REGNO_IGNORE
;
4922 /* Convert an integer into an address. Extracting the value signed
4923 guarantees a correctly sign extended address. */
4926 mips_integer_to_address (struct gdbarch
*gdbarch
,
4927 struct type
*type
, const gdb_byte
*buf
)
4929 return (CORE_ADDR
) extract_signed_integer (buf
, TYPE_LENGTH (type
));
4933 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
4935 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
4936 const char *name
= bfd_get_section_name (abfd
, sect
);
4938 if (*abip
!= MIPS_ABI_UNKNOWN
)
4941 if (strncmp (name
, ".mdebug.", 8) != 0)
4944 if (strcmp (name
, ".mdebug.abi32") == 0)
4945 *abip
= MIPS_ABI_O32
;
4946 else if (strcmp (name
, ".mdebug.abiN32") == 0)
4947 *abip
= MIPS_ABI_N32
;
4948 else if (strcmp (name
, ".mdebug.abi64") == 0)
4949 *abip
= MIPS_ABI_N64
;
4950 else if (strcmp (name
, ".mdebug.abiO64") == 0)
4951 *abip
= MIPS_ABI_O64
;
4952 else if (strcmp (name
, ".mdebug.eabi32") == 0)
4953 *abip
= MIPS_ABI_EABI32
;
4954 else if (strcmp (name
, ".mdebug.eabi64") == 0)
4955 *abip
= MIPS_ABI_EABI64
;
4957 warning (_("unsupported ABI %s."), name
+ 8);
4961 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
4963 int *lbp
= (int *) obj
;
4964 const char *name
= bfd_get_section_name (abfd
, sect
);
4966 if (strncmp (name
, ".gcc_compiled_long32", 20) == 0)
4968 else if (strncmp (name
, ".gcc_compiled_long64", 20) == 0)
4970 else if (strncmp (name
, ".gcc_compiled_long", 18) == 0)
4971 warning (_("unrecognized .gcc_compiled_longXX"));
4974 static enum mips_abi
4975 global_mips_abi (void)
4979 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
4980 if (mips_abi_strings
[i
] == mips_abi_string
)
4981 return (enum mips_abi
) i
;
4983 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
4987 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
4989 /* If the size matches the set of 32-bit or 64-bit integer registers,
4990 assume that's what we've got. */
4991 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
4992 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
4994 /* If the size matches the full set of registers GDB traditionally
4995 knows about, including floating point, for either 32-bit or
4996 64-bit, assume that's what we've got. */
4997 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
4998 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
5000 /* Otherwise we don't have a useful guess. */
5003 static struct value
*
5004 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
5006 const int *reg_p
= baton
;
5007 return value_of_register (*reg_p
, frame
);
5010 static struct gdbarch
*
5011 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
5013 struct gdbarch
*gdbarch
;
5014 struct gdbarch_tdep
*tdep
;
5016 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
5018 enum mips_fpu_type fpu_type
;
5019 struct tdesc_arch_data
*tdesc_data
= NULL
;
5020 int elf_fpu_type
= 0;
5022 /* Check any target description for validity. */
5023 if (tdesc_has_registers (info
.target_desc
))
5025 static const char *const mips_gprs
[] = {
5026 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5027 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5028 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5029 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5031 static const char *const mips_fprs
[] = {
5032 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5033 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5034 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5035 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5038 const struct tdesc_feature
*feature
;
5041 feature
= tdesc_find_feature (info
.target_desc
,
5042 "org.gnu.gdb.mips.cpu");
5043 if (feature
== NULL
)
5046 tdesc_data
= tdesc_data_alloc ();
5049 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
5050 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
, i
,
5054 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5055 MIPS_EMBED_LO_REGNUM
, "lo");
5056 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5057 MIPS_EMBED_HI_REGNUM
, "hi");
5058 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5059 MIPS_EMBED_PC_REGNUM
, "pc");
5063 tdesc_data_cleanup (tdesc_data
);
5067 feature
= tdesc_find_feature (info
.target_desc
,
5068 "org.gnu.gdb.mips.cp0");
5069 if (feature
== NULL
)
5071 tdesc_data_cleanup (tdesc_data
);
5076 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5077 MIPS_EMBED_BADVADDR_REGNUM
,
5079 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5080 MIPS_PS_REGNUM
, "status");
5081 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5082 MIPS_EMBED_CAUSE_REGNUM
, "cause");
5086 tdesc_data_cleanup (tdesc_data
);
5090 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
5091 backend is not prepared for that, though. */
5092 feature
= tdesc_find_feature (info
.target_desc
,
5093 "org.gnu.gdb.mips.fpu");
5094 if (feature
== NULL
)
5096 tdesc_data_cleanup (tdesc_data
);
5101 for (i
= 0; i
< 32; i
++)
5102 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5103 i
+ MIPS_EMBED_FP0_REGNUM
,
5106 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5107 MIPS_EMBED_FP0_REGNUM
+ 32, "fcsr");
5108 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
,
5109 MIPS_EMBED_FP0_REGNUM
+ 33, "fir");
5113 tdesc_data_cleanup (tdesc_data
);
5117 /* It would be nice to detect an attempt to use a 64-bit ABI
5118 when only 32-bit registers are provided. */
5121 /* First of all, extract the elf_flags, if available. */
5122 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5123 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
5124 else if (arches
!= NULL
)
5125 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
5129 fprintf_unfiltered (gdb_stdlog
,
5130 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
5132 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
5133 switch ((elf_flags
& EF_MIPS_ABI
))
5135 case E_MIPS_ABI_O32
:
5136 found_abi
= MIPS_ABI_O32
;
5138 case E_MIPS_ABI_O64
:
5139 found_abi
= MIPS_ABI_O64
;
5141 case E_MIPS_ABI_EABI32
:
5142 found_abi
= MIPS_ABI_EABI32
;
5144 case E_MIPS_ABI_EABI64
:
5145 found_abi
= MIPS_ABI_EABI64
;
5148 if ((elf_flags
& EF_MIPS_ABI2
))
5149 found_abi
= MIPS_ABI_N32
;
5151 found_abi
= MIPS_ABI_UNKNOWN
;
5155 /* GCC creates a pseudo-section whose name describes the ABI. */
5156 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
5157 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
5159 /* If we have no useful BFD information, use the ABI from the last
5160 MIPS architecture (if there is one). */
5161 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
5162 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
5164 /* Try the architecture for any hint of the correct ABI. */
5165 if (found_abi
== MIPS_ABI_UNKNOWN
5166 && info
.bfd_arch_info
!= NULL
5167 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5169 switch (info
.bfd_arch_info
->mach
)
5171 case bfd_mach_mips3900
:
5172 found_abi
= MIPS_ABI_EABI32
;
5174 case bfd_mach_mips4100
:
5175 case bfd_mach_mips5000
:
5176 found_abi
= MIPS_ABI_EABI64
;
5178 case bfd_mach_mips8000
:
5179 case bfd_mach_mips10000
:
5180 /* On Irix, ELF64 executables use the N64 ABI. The
5181 pseudo-sections which describe the ABI aren't present
5182 on IRIX. (Even for executables created by gcc.) */
5183 if (bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5184 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5185 found_abi
= MIPS_ABI_N64
;
5187 found_abi
= MIPS_ABI_N32
;
5192 /* Default 64-bit objects to N64 instead of O32. */
5193 if (found_abi
== MIPS_ABI_UNKNOWN
5194 && info
.abfd
!= NULL
5195 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
5196 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
5197 found_abi
= MIPS_ABI_N64
;
5200 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
5203 /* What has the user specified from the command line? */
5204 wanted_abi
= global_mips_abi ();
5206 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
5209 /* Now that we have found what the ABI for this binary would be,
5210 check whether the user is overriding it. */
5211 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
5212 mips_abi
= wanted_abi
;
5213 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
5214 mips_abi
= found_abi
;
5216 mips_abi
= MIPS_ABI_O32
;
5218 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
5221 /* Also used when doing an architecture lookup. */
5223 fprintf_unfiltered (gdb_stdlog
,
5224 "mips_gdbarch_init: mips64_transfers_32bit_regs_p = %d\n",
5225 mips64_transfers_32bit_regs_p
);
5227 /* Determine the MIPS FPU type. */
5230 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
5231 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
5232 Tag_GNU_MIPS_ABI_FP
);
5233 #endif /* HAVE_ELF */
5235 if (!mips_fpu_type_auto
)
5236 fpu_type
= mips_fpu_type
;
5237 else if (elf_fpu_type
!= 0)
5239 switch (elf_fpu_type
)
5242 fpu_type
= MIPS_FPU_DOUBLE
;
5245 fpu_type
= MIPS_FPU_SINGLE
;
5249 /* Soft float or unknown. */
5250 fpu_type
= MIPS_FPU_NONE
;
5254 else if (info
.bfd_arch_info
!= NULL
5255 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
5256 switch (info
.bfd_arch_info
->mach
)
5258 case bfd_mach_mips3900
:
5259 case bfd_mach_mips4100
:
5260 case bfd_mach_mips4111
:
5261 case bfd_mach_mips4120
:
5262 fpu_type
= MIPS_FPU_NONE
;
5264 case bfd_mach_mips4650
:
5265 fpu_type
= MIPS_FPU_SINGLE
;
5268 fpu_type
= MIPS_FPU_DOUBLE
;
5271 else if (arches
!= NULL
)
5272 fpu_type
= gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
;
5274 fpu_type
= MIPS_FPU_DOUBLE
;
5276 fprintf_unfiltered (gdb_stdlog
,
5277 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
5279 /* Check for blatant incompatibilities. */
5281 /* If we have only 32-bit registers, then we can't debug a 64-bit
5283 if (info
.target_desc
5284 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
5285 && mips_abi
!= MIPS_ABI_EABI32
5286 && mips_abi
!= MIPS_ABI_O32
)
5288 if (tdesc_data
!= NULL
)
5289 tdesc_data_cleanup (tdesc_data
);
5293 /* try to find a pre-existing architecture */
5294 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
5296 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
5298 /* MIPS needs to be pedantic about which ABI the object is
5300 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
5302 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
5304 /* Need to be pedantic about which register virtual size is
5306 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
5307 != mips64_transfers_32bit_regs_p
)
5309 /* Be pedantic about which FPU is selected. */
5310 if (gdbarch_tdep (arches
->gdbarch
)->mips_fpu_type
!= fpu_type
)
5313 if (tdesc_data
!= NULL
)
5314 tdesc_data_cleanup (tdesc_data
);
5315 return arches
->gdbarch
;
5318 /* Need a new architecture. Fill in a target specific vector. */
5319 tdep
= (struct gdbarch_tdep
*) xmalloc (sizeof (struct gdbarch_tdep
));
5320 gdbarch
= gdbarch_alloc (&info
, tdep
);
5321 tdep
->elf_flags
= elf_flags
;
5322 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
5323 tdep
->found_abi
= found_abi
;
5324 tdep
->mips_abi
= mips_abi
;
5325 tdep
->mips_fpu_type
= fpu_type
;
5326 tdep
->register_size_valid_p
= 0;
5327 tdep
->register_size
= 0;
5329 if (info
.target_desc
)
5331 /* Some useful properties can be inferred from the target. */
5332 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
5334 tdep
->register_size_valid_p
= 1;
5335 tdep
->register_size
= 4;
5337 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
5339 tdep
->register_size_valid_p
= 1;
5340 tdep
->register_size
= 8;
5344 /* Initially set everything according to the default ABI/ISA. */
5345 set_gdbarch_short_bit (gdbarch
, 16);
5346 set_gdbarch_int_bit (gdbarch
, 32);
5347 set_gdbarch_float_bit (gdbarch
, 32);
5348 set_gdbarch_double_bit (gdbarch
, 64);
5349 set_gdbarch_long_double_bit (gdbarch
, 64);
5350 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
5351 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
5352 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
5354 set_gdbarch_elf_make_msymbol_special (gdbarch
,
5355 mips_elf_make_msymbol_special
);
5357 /* Fill in the OS dependant register numbers and names. */
5359 const char **reg_names
;
5360 struct mips_regnum
*regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
,
5361 struct mips_regnum
);
5362 if (tdesc_has_registers (info
.target_desc
))
5364 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5365 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5366 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5367 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5368 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5369 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5370 regnum
->fp_control_status
= 70;
5371 regnum
->fp_implementation_revision
= 71;
5372 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
5375 else if (info
.osabi
== GDB_OSABI_IRIX
)
5380 regnum
->badvaddr
= 66;
5383 regnum
->fp_control_status
= 69;
5384 regnum
->fp_implementation_revision
= 70;
5386 reg_names
= mips_irix_reg_names
;
5390 regnum
->lo
= MIPS_EMBED_LO_REGNUM
;
5391 regnum
->hi
= MIPS_EMBED_HI_REGNUM
;
5392 regnum
->badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
5393 regnum
->cause
= MIPS_EMBED_CAUSE_REGNUM
;
5394 regnum
->pc
= MIPS_EMBED_PC_REGNUM
;
5395 regnum
->fp0
= MIPS_EMBED_FP0_REGNUM
;
5396 regnum
->fp_control_status
= 70;
5397 regnum
->fp_implementation_revision
= 71;
5399 if (info
.bfd_arch_info
!= NULL
5400 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
5401 reg_names
= mips_tx39_reg_names
;
5403 reg_names
= mips_generic_reg_names
;
5405 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been
5406 replaced by read_pc? */
5407 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
5408 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5409 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
5410 set_gdbarch_num_regs (gdbarch
, num_regs
);
5411 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5412 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5413 tdep
->mips_processor_reg_names
= reg_names
;
5414 tdep
->regnum
= regnum
;
5420 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
5421 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
5422 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5423 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5424 tdep
->default_mask_address_p
= 0;
5425 set_gdbarch_long_bit (gdbarch
, 32);
5426 set_gdbarch_ptr_bit (gdbarch
, 32);
5427 set_gdbarch_long_long_bit (gdbarch
, 64);
5430 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
5431 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
5432 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
5433 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
5434 tdep
->default_mask_address_p
= 0;
5435 set_gdbarch_long_bit (gdbarch
, 32);
5436 set_gdbarch_ptr_bit (gdbarch
, 32);
5437 set_gdbarch_long_long_bit (gdbarch
, 64);
5439 case MIPS_ABI_EABI32
:
5440 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5441 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5442 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5443 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5444 tdep
->default_mask_address_p
= 0;
5445 set_gdbarch_long_bit (gdbarch
, 32);
5446 set_gdbarch_ptr_bit (gdbarch
, 32);
5447 set_gdbarch_long_long_bit (gdbarch
, 64);
5449 case MIPS_ABI_EABI64
:
5450 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
5451 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
5452 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5453 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5454 tdep
->default_mask_address_p
= 0;
5455 set_gdbarch_long_bit (gdbarch
, 64);
5456 set_gdbarch_ptr_bit (gdbarch
, 64);
5457 set_gdbarch_long_long_bit (gdbarch
, 64);
5460 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5461 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5462 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5463 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5464 tdep
->default_mask_address_p
= 0;
5465 set_gdbarch_long_bit (gdbarch
, 32);
5466 set_gdbarch_ptr_bit (gdbarch
, 32);
5467 set_gdbarch_long_long_bit (gdbarch
, 64);
5468 set_gdbarch_long_double_bit (gdbarch
, 128);
5469 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5472 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
5473 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
5474 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
5475 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
5476 tdep
->default_mask_address_p
= 0;
5477 set_gdbarch_long_bit (gdbarch
, 64);
5478 set_gdbarch_ptr_bit (gdbarch
, 64);
5479 set_gdbarch_long_long_bit (gdbarch
, 64);
5480 set_gdbarch_long_double_bit (gdbarch
, 128);
5481 set_gdbarch_long_double_format (gdbarch
, floatformats_n32n64_long
);
5484 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5487 /* GCC creates a pseudo-section whose name specifies the size of
5488 longs, since -mlong32 or -mlong64 may be used independent of
5489 other options. How those options affect pointer sizes is ABI and
5490 architecture dependent, so use them to override the default sizes
5491 set by the ABI. This table shows the relationship between ABI,
5492 -mlongXX, and size of pointers:
5494 ABI -mlongXX ptr bits
5495 --- -------- --------
5509 Note that for o32 and eabi32, pointers are always 32 bits
5510 regardless of any -mlongXX option. For all others, pointers and
5511 longs are the same, as set by -mlongXX or set by defaults.
5514 if (info
.abfd
!= NULL
)
5518 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
5521 set_gdbarch_long_bit (gdbarch
, long_bit
);
5525 case MIPS_ABI_EABI32
:
5530 case MIPS_ABI_EABI64
:
5531 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
5534 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
5539 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
5540 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
5543 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
5544 flag in object files because to do so would make it impossible to
5545 link with libraries compiled without "-gp32". This is
5546 unnecessarily restrictive.
5548 We could solve this problem by adding "-gp32" multilibs to gcc,
5549 but to set this flag before gcc is built with such multilibs will
5550 break too many systems.''
5552 But even more unhelpfully, the default linker output target for
5553 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
5554 for 64-bit programs - you need to change the ABI to change this,
5555 and not all gcc targets support that currently. Therefore using
5556 this flag to detect 32-bit mode would do the wrong thing given
5557 the current gcc - it would make GDB treat these 64-bit programs
5558 as 32-bit programs by default. */
5560 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
5561 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
5563 /* Add/remove bits from an address. The MIPS needs be careful to
5564 ensure that all 32 bit addresses are sign extended to 64 bits. */
5565 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
5567 /* Unwind the frame. */
5568 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
5569 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
5570 set_gdbarch_unwind_dummy_id (gdbarch
, mips_unwind_dummy_id
);
5572 /* Map debug register numbers onto internal register numbers. */
5573 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
5574 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
5575 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5576 set_gdbarch_dwarf_reg_to_regnum (gdbarch
,
5577 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5578 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
5579 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
5580 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
5582 /* MIPS version of CALL_DUMMY */
5584 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be
5585 replaced by a command, and all targets will default to on stack
5586 (regardless of the stack's execute status). */
5587 set_gdbarch_call_dummy_location (gdbarch
, AT_SYMBOL
);
5588 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
5590 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
5591 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
5592 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
5594 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
5595 set_gdbarch_breakpoint_from_pc (gdbarch
, mips_breakpoint_from_pc
);
5597 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
5599 set_gdbarch_in_function_epilogue_p (gdbarch
, mips_in_function_epilogue_p
);
5601 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
5602 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
5603 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
5605 set_gdbarch_register_type (gdbarch
, mips_register_type
);
5607 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
5609 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
5611 /* FIXME: cagney/2003-08-29: The macros HAVE_STEPPABLE_WATCHPOINT,
5612 HAVE_NONSTEPPABLE_WATCHPOINT, and HAVE_CONTINUABLE_WATCHPOINT
5613 need to all be folded into the target vector. Since they are
5614 being used as guards for STOPPED_BY_WATCHPOINT, why not have
5615 STOPPED_BY_WATCHPOINT return the type of watchpoint that the code
5617 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
5619 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
5621 set_gdbarch_single_step_through_delay (gdbarch
, mips_single_step_through_delay
);
5623 /* Virtual tables. */
5624 set_gdbarch_vbit_in_delta (gdbarch
, 1);
5626 mips_register_g_packet_guesses (gdbarch
);
5628 /* Hook in OS ABI-specific overrides, if they have been registered. */
5629 info
.tdep_info
= (void *) tdesc_data
;
5630 gdbarch_init_osabi (info
, gdbarch
);
5632 /* Unwind the frame. */
5633 frame_unwind_append_sniffer (gdbarch
, dwarf2_frame_sniffer
);
5634 frame_unwind_append_sniffer (gdbarch
, mips_stub_frame_sniffer
);
5635 frame_unwind_append_sniffer (gdbarch
, mips_insn16_frame_sniffer
);
5636 frame_unwind_append_sniffer (gdbarch
, mips_insn32_frame_sniffer
);
5637 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
5638 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
5639 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
5640 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
5644 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
5645 tdesc_use_registers (gdbarch
, tdesc_data
);
5647 /* Override the normal target description methods to handle our
5648 dual real and pseudo registers. */
5649 set_gdbarch_register_name (gdbarch
, mips_register_name
);
5650 set_gdbarch_register_reggroup_p (gdbarch
, mips_tdesc_register_reggroup_p
);
5652 num_regs
= gdbarch_num_regs (gdbarch
);
5653 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
5654 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
5655 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
5658 /* Add ABI-specific aliases for the registers. */
5659 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
5660 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
5661 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
5662 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
5664 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
5665 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
5666 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
5668 /* Add some other standard aliases. */
5669 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
5670 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
5671 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
5677 mips_abi_update (char *ignore_args
, int from_tty
, struct cmd_list_element
*c
)
5679 struct gdbarch_info info
;
5681 /* Force the architecture to update, and (if it's a MIPS architecture)
5682 mips_gdbarch_init will take care of the rest. */
5683 gdbarch_info_init (&info
);
5684 gdbarch_update_p (info
);
5687 /* Print out which MIPS ABI is in use. */
5690 show_mips_abi (struct ui_file
*file
,
5692 struct cmd_list_element
*ignored_cmd
,
5693 const char *ignored_value
)
5695 if (gdbarch_bfd_arch_info (current_gdbarch
)->arch
!= bfd_arch_mips
)
5698 "The MIPS ABI is unknown because the current architecture "
5702 enum mips_abi global_abi
= global_mips_abi ();
5703 enum mips_abi actual_abi
= mips_abi (current_gdbarch
);
5704 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
5706 if (global_abi
== MIPS_ABI_UNKNOWN
)
5709 "The MIPS ABI is set automatically (currently \"%s\").\n",
5711 else if (global_abi
== actual_abi
)
5714 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
5718 /* Probably shouldn't happen... */
5721 "The (auto detected) MIPS ABI \"%s\" is in use even though the user setting was \"%s\".\n",
5722 actual_abi_str
, mips_abi_strings
[global_abi
]);
5728 mips_dump_tdep (struct gdbarch
*current_gdbarch
, struct ui_file
*file
)
5730 struct gdbarch_tdep
*tdep
= gdbarch_tdep (current_gdbarch
);
5734 int ef_mips_32bitmode
;
5735 /* Determine the ISA. */
5736 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
5754 /* Determine the size of a pointer. */
5755 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
5756 fprintf_unfiltered (file
,
5757 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
5759 fprintf_unfiltered (file
,
5760 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
5762 fprintf_unfiltered (file
,
5763 "mips_dump_tdep: ef_mips_arch = %d\n",
5765 fprintf_unfiltered (file
,
5766 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
5767 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
5768 fprintf_unfiltered (file
,
5769 "mips_dump_tdep: mips_mask_address_p() %d (default %d)\n",
5770 mips_mask_address_p (tdep
),
5771 tdep
->default_mask_address_p
);
5773 fprintf_unfiltered (file
,
5774 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
5775 MIPS_DEFAULT_FPU_TYPE
,
5776 (MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5777 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5778 : MIPS_DEFAULT_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5780 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n", MIPS_EABI
);
5781 fprintf_unfiltered (file
,
5782 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
5784 (MIPS_FPU_TYPE
== MIPS_FPU_NONE
? "none"
5785 : MIPS_FPU_TYPE
== MIPS_FPU_SINGLE
? "single"
5786 : MIPS_FPU_TYPE
== MIPS_FPU_DOUBLE
? "double"
5790 extern initialize_file_ftype _initialize_mips_tdep
; /* -Wmissing-prototypes */
5793 _initialize_mips_tdep (void)
5795 static struct cmd_list_element
*mipsfpulist
= NULL
;
5796 struct cmd_list_element
*c
;
5798 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
5799 if (MIPS_ABI_LAST
+ 1
5800 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
5801 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
5803 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
5805 mips_pdr_data
= register_objfile_data ();
5807 /* Create feature sets with the appropriate properties. The values
5808 are not important. */
5809 mips_tdesc_gp32
= allocate_target_description ();
5810 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
5812 mips_tdesc_gp64
= allocate_target_description ();
5813 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
5815 /* Add root prefix command for all "set mips"/"show mips" commands */
5816 add_prefix_cmd ("mips", no_class
, set_mips_command
,
5817 _("Various MIPS specific commands."),
5818 &setmipscmdlist
, "set mips ", 0, &setlist
);
5820 add_prefix_cmd ("mips", no_class
, show_mips_command
,
5821 _("Various MIPS specific commands."),
5822 &showmipscmdlist
, "show mips ", 0, &showlist
);
5824 /* Allow the user to override the ABI. */
5825 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
5826 &mips_abi_string
, _("\
5827 Set the MIPS ABI used by this program."), _("\
5828 Show the MIPS ABI used by this program."), _("\
5829 This option can be set to one of:\n\
5830 auto - the default ABI associated with the current binary\n\
5839 &setmipscmdlist
, &showmipscmdlist
);
5841 /* Let the user turn off floating point and set the fence post for
5842 heuristic_proc_start. */
5844 add_prefix_cmd ("mipsfpu", class_support
, set_mipsfpu_command
,
5845 _("Set use of MIPS floating-point coprocessor."),
5846 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
5847 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
5848 _("Select single-precision MIPS floating-point coprocessor."),
5850 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
5851 _("Select double-precision MIPS floating-point coprocessor."),
5853 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
5854 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
5855 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
5856 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
5857 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
5858 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
5859 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
5860 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
5861 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
5862 _("Select MIPS floating-point coprocessor automatically."),
5864 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
5865 _("Show current use of MIPS floating-point coprocessor target."),
5868 /* We really would like to have both "0" and "unlimited" work, but
5869 command.c doesn't deal with that. So make it a var_zinteger
5870 because the user can always use "999999" or some such for unlimited. */
5871 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
5872 &heuristic_fence_post
, _("\
5873 Set the distance searched for the start of a function."), _("\
5874 Show the distance searched for the start of a function."), _("\
5875 If you are debugging a stripped executable, GDB needs to search through the\n\
5876 program for the start of a function. This command sets the distance of the\n\
5877 search. The only need to set it is when debugging a stripped executable."),
5878 reinit_frame_cache_sfunc
,
5879 NULL
, /* FIXME: i18n: The distance searched for the start of a function is %s. */
5880 &setlist
, &showlist
);
5882 /* Allow the user to control whether the upper bits of 64-bit
5883 addresses should be zeroed. */
5884 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
5885 &mask_address_var
, _("\
5886 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
5887 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
5888 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to \n\
5889 allow GDB to determine the correct value."),
5890 NULL
, show_mask_address
,
5891 &setmipscmdlist
, &showmipscmdlist
);
5893 /* Allow the user to control the size of 32 bit registers within the
5894 raw remote packet. */
5895 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
5896 &mips64_transfers_32bit_regs_p
, _("\
5897 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5899 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
5901 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
5902 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
5903 64 bits for others. Use \"off\" to disable compatibility mode"),
5904 set_mips64_transfers_32bit_regs
,
5905 NULL
, /* FIXME: i18n: Compatibility with 64-bit MIPS target that transfers 32-bit quantities is %s. */
5906 &setlist
, &showlist
);
5908 /* Debug this files internals. */
5909 add_setshow_zinteger_cmd ("mips", class_maintenance
,
5911 Set mips debugging."), _("\
5912 Show mips debugging."), _("\
5913 When non-zero, mips specific debugging is enabled."),
5915 NULL
, /* FIXME: i18n: Mips debugging is currently %s. */
5916 &setdebuglist
, &showdebuglist
);