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1 /* Target-dependent code for GDB, the GNU debugger.
2
3 Copyright (C) 2000-2017 Free Software Foundation, Inc.
4
5 This file is part of GDB.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #ifndef PPC_TDEP_H
21 #define PPC_TDEP_H
22
23 struct gdbarch;
24 struct frame_info;
25 struct value;
26 struct regcache;
27 struct type;
28
29 /* From ppc-sysv-tdep.c ... */
30 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
31 struct value *function,
32 struct type *valtype,
33 struct regcache *regcache,
34 gdb_byte *readbuf,
35 const gdb_byte *writebuf);
36 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
37 struct value *function,
38 struct type *valtype,
39 struct regcache *regcache,
40 gdb_byte *readbuf,
41 const gdb_byte *writebuf);
42 CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
43 struct value *function,
44 struct regcache *regcache,
45 CORE_ADDR bp_addr, int nargs,
46 struct value **args, CORE_ADDR sp,
47 int struct_return,
48 CORE_ADDR struct_addr);
49 CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
50 struct value *function,
51 struct regcache *regcache,
52 CORE_ADDR bp_addr, int nargs,
53 struct value **args, CORE_ADDR sp,
54 int struct_return,
55 CORE_ADDR struct_addr);
56 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
57 struct value *function,
58 struct type *valtype,
59 struct regcache *regcache,
60 gdb_byte *readbuf,
61 const gdb_byte *writebuf);
62
63 /* From rs6000-tdep.c... */
64 int altivec_register_p (struct gdbarch *gdbarch, int regno);
65 int vsx_register_p (struct gdbarch *gdbarch, int regno);
66 int spe_register_p (struct gdbarch *gdbarch, int regno);
67
68 /* Return non-zero if the architecture described by GDBARCH has
69 floating-point registers (f0 --- f31 and fpscr). */
70 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
71
72 /* Return non-zero if the architecture described by GDBARCH has
73 Altivec registers (vr0 --- vr31, vrsave and vscr). */
74 int ppc_altivec_support_p (struct gdbarch *gdbarch);
75
76 /* Return non-zero if the architecture described by GDBARCH has
77 VSX registers (vsr0 --- vsr63). */
78 int vsx_support_p (struct gdbarch *gdbarch);
79 std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
80 (struct regcache *regcache);
81
82
83 /* Register set description. */
84
85 struct ppc_reg_offsets
86 {
87 /* General-purpose registers. */
88 int r0_offset;
89 int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
90 int xr_size; /* size for cr, xer, mq. */
91 int pc_offset;
92 int ps_offset;
93 int cr_offset;
94 int lr_offset;
95 int ctr_offset;
96 int xer_offset;
97 int mq_offset;
98
99 /* Floating-point registers. */
100 int f0_offset;
101 int fpscr_offset;
102 int fpscr_size;
103
104 /* AltiVec registers. */
105 int vr0_offset;
106 int vscr_offset;
107 int vrsave_offset;
108 };
109
110 extern void ppc_supply_reg (struct regcache *regcache, int regnum,
111 const gdb_byte *regs, size_t offset, int regsize);
112
113 extern void ppc_collect_reg (const struct regcache *regcache, int regnum,
114 gdb_byte *regs, size_t offset, int regsize);
115
116 /* Supply register REGNUM in the general-purpose register set REGSET
117 from the buffer specified by GREGS and LEN to register cache
118 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
119
120 extern void ppc_supply_gregset (const struct regset *regset,
121 struct regcache *regcache,
122 int regnum, const void *gregs, size_t len);
123
124 /* Supply register REGNUM in the floating-point register set REGSET
125 from the buffer specified by FPREGS and LEN to register cache
126 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
127
128 extern void ppc_supply_fpregset (const struct regset *regset,
129 struct regcache *regcache,
130 int regnum, const void *fpregs, size_t len);
131
132 /* Supply register REGNUM in the Altivec register set REGSET
133 from the buffer specified by VRREGS and LEN to register cache
134 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
135
136 extern void ppc_supply_vrregset (const struct regset *regset,
137 struct regcache *regcache,
138 int regnum, const void *vrregs, size_t len);
139
140 /* Supply register REGNUM in the VSX register set REGSET
141 from the buffer specified by VSXREGS and LEN to register cache
142 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
143
144 extern void ppc_supply_vsxregset (const struct regset *regset,
145 struct regcache *regcache,
146 int regnum, const void *vsxregs, size_t len);
147
148 /* Collect register REGNUM in the general-purpose register set
149 REGSET, from register cache REGCACHE into the buffer specified by
150 GREGS and LEN. If REGNUM is -1, do this for all registers in
151 REGSET. */
152
153 extern void ppc_collect_gregset (const struct regset *regset,
154 const struct regcache *regcache,
155 int regnum, void *gregs, size_t len);
156
157 /* Collect register REGNUM in the floating-point register set
158 REGSET, from register cache REGCACHE into the buffer specified by
159 FPREGS and LEN. If REGNUM is -1, do this for all registers in
160 REGSET. */
161
162 extern void ppc_collect_fpregset (const struct regset *regset,
163 const struct regcache *regcache,
164 int regnum, void *fpregs, size_t len);
165
166 /* Collect register REGNUM in the Altivec register set
167 REGSET from register cache REGCACHE into the buffer specified by
168 VRREGS and LEN. If REGNUM is -1, do this for all registers in
169 REGSET. */
170
171 extern void ppc_collect_vrregset (const struct regset *regset,
172 const struct regcache *regcache,
173 int regnum, void *vrregs, size_t len);
174
175 /* Collect register REGNUM in the VSX register set
176 REGSET from register cache REGCACHE into the buffer specified by
177 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
178 REGSET. */
179
180 extern void ppc_collect_vsxregset (const struct regset *regset,
181 const struct regcache *regcache,
182 int regnum, void *vsxregs, size_t len);
183
184 /* Private data that this module attaches to struct gdbarch. */
185
186 /* ELF ABI version used by the inferior. */
187 enum powerpc_elf_abi
188 {
189 POWERPC_ELF_AUTO,
190 POWERPC_ELF_V1,
191 POWERPC_ELF_V2,
192 POWERPC_ELF_LAST
193 };
194
195 /* Vector ABI used by the inferior. */
196 enum powerpc_vector_abi
197 {
198 POWERPC_VEC_AUTO,
199 POWERPC_VEC_GENERIC,
200 POWERPC_VEC_ALTIVEC,
201 POWERPC_VEC_SPE,
202 POWERPC_VEC_LAST
203 };
204
205 struct gdbarch_tdep
206 {
207 int wordsize; /* Size in bytes of fixed-point word. */
208 int soft_float; /* Avoid FP registers for arguments? */
209
210 enum powerpc_elf_abi elf_abi; /* ELF ABI version. */
211
212 /* How to pass vector arguments. Never set to AUTO or LAST. */
213 enum powerpc_vector_abi vector_abi;
214
215 int ppc_gp0_regnum; /* GPR register 0 */
216 int ppc_toc_regnum; /* TOC register */
217 int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
218 int ppc_cr_regnum; /* Condition register */
219 int ppc_lr_regnum; /* Link register */
220 int ppc_ctr_regnum; /* Count register */
221 int ppc_xer_regnum; /* Integer exception register */
222
223 /* Not all PPC and RS6000 variants will have the registers
224 represented below. A -1 is used to indicate that the register
225 is not present in this variant. */
226
227 /* Floating-point registers. */
228 int ppc_fp0_regnum; /* Floating-point register 0. */
229 int ppc_fpscr_regnum; /* fp status and condition register. */
230
231 /* Multiplier-Quotient Register (older POWER architectures only). */
232 int ppc_mq_regnum;
233
234 /* POWER7 VSX registers. */
235 int ppc_vsr0_regnum; /* First VSX register. */
236 int ppc_vsr0_upper_regnum; /* First right most dword vsx register. */
237 int ppc_efpr0_regnum; /* First Extended FP register. */
238
239 /* Altivec registers. */
240 int ppc_vr0_regnum; /* First AltiVec register. */
241 int ppc_vrsave_regnum; /* Last AltiVec register. */
242
243 /* SPE registers. */
244 int ppc_ev0_upper_regnum; /* First GPR upper half register. */
245 int ppc_ev0_regnum; /* First ev register. */
246 int ppc_acc_regnum; /* SPE 'acc' register. */
247 int ppc_spefscr_regnum; /* SPE 'spefscr' register. */
248
249 /* Decimal 128 registers. */
250 int ppc_dl0_regnum; /* First Decimal128 argument register pair. */
251
252 /* Offset to ABI specific location where link register is saved. */
253 int lr_frame_offset;
254
255 /* An array of integers, such that sim_regno[I] is the simulator
256 register number for GDB register number I, or -1 if the
257 simulator does not implement that register. */
258 int *sim_regno;
259
260 /* ISA-specific types. */
261 struct type *ppc_builtin_type_vec64;
262 struct type *ppc_builtin_type_vec128;
263
264 int (*ppc_syscall_record) (struct regcache *regcache);
265 };
266
267
268 /* Constants for register set sizes. */
269 enum
270 {
271 ppc_num_gprs = 32, /* 32 general-purpose registers. */
272 ppc_num_fprs = 32, /* 32 floating-point registers. */
273 ppc_num_srs = 16, /* 16 segment registers. */
274 ppc_num_vrs = 32, /* 32 Altivec vector registers. */
275 ppc_num_vshrs = 32, /* 32 doublewords (dword 1 of vs0~vs31). */
276 ppc_num_vsrs = 64, /* 64 VSX vector registers. */
277 ppc_num_efprs = 32 /* 32 Extended FP registers. */
278 };
279
280
281 /* Register number constants. These are GDB internal register
282 numbers; they are not used for the simulator or remote targets.
283 Extra SPRs (those other than MQ, CTR, LR, XER, SPEFSCR) are given
284 numbers above PPC_NUM_REGS. So are segment registers and other
285 target-defined registers. */
286 enum {
287 PPC_R0_REGNUM = 0,
288 PPC_F0_REGNUM = 32,
289 PPC_PC_REGNUM = 64,
290 PPC_MSR_REGNUM = 65,
291 PPC_CR_REGNUM = 66,
292 PPC_LR_REGNUM = 67,
293 PPC_CTR_REGNUM = 68,
294 PPC_XER_REGNUM = 69,
295 PPC_FPSCR_REGNUM = 70,
296 PPC_MQ_REGNUM = 71,
297 PPC_SPE_UPPER_GP0_REGNUM = 72,
298 PPC_SPE_ACC_REGNUM = 104,
299 PPC_SPE_FSCR_REGNUM = 105,
300 PPC_VR0_REGNUM = 106,
301 PPC_VSCR_REGNUM = 138,
302 PPC_VRSAVE_REGNUM = 139,
303 PPC_VSR0_UPPER_REGNUM = 140,
304 PPC_VSR31_UPPER_REGNUM = 171,
305 PPC_NUM_REGS
306 };
307
308 /* Big enough to hold the size of the largest register in bytes. */
309 #define PPC_MAX_REGISTER_SIZE 64
310
311 /* An instruction to match. */
312
313 struct ppc_insn_pattern
314 {
315 unsigned int mask; /* mask the insn with this... */
316 unsigned int data; /* ...and see if it matches this. */
317 int optional; /* If non-zero, this insn may be absent. */
318 };
319
320 extern int ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
321 struct ppc_insn_pattern *pattern,
322 unsigned int *insns);
323 extern CORE_ADDR ppc_insn_d_field (unsigned int insn);
324
325 extern CORE_ADDR ppc_insn_ds_field (unsigned int insn);
326
327 extern int ppc_process_record (struct gdbarch *gdbarch,
328 struct regcache *regcache, CORE_ADDR addr);
329
330 /* Instruction size. */
331 #define PPC_INSN_SIZE 4
332
333 /* Estimate for the maximum number of instrctions in a function epilogue. */
334 #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
335
336 #endif /* ppc-tdep.h */