2 * Copyright (c) 2013 Jean-Christophe Dubois <jcd@tribudubois.net>
4 * i.MX25 SOC emulation.
6 * Based on hw/arm/xlnx-zynqmp.c
8 * Copyright (C) 2015 Xilinx Inc
9 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "hw/arm/fsl-imx25.h"
28 #include "sysemu/sysemu.h"
29 #include "exec/address-spaces.h"
30 #include "hw/boards.h"
31 #include "sysemu/char.h"
33 static void fsl_imx25_init(Object
*obj
)
35 FslIMX25State
*s
= FSL_IMX25(obj
);
38 object_initialize(&s
->cpu
, sizeof(s
->cpu
), "arm926-" TYPE_ARM_CPU
);
40 object_initialize(&s
->avic
, sizeof(s
->avic
), TYPE_IMX_AVIC
);
41 qdev_set_parent_bus(DEVICE(&s
->avic
), sysbus_get_default());
43 object_initialize(&s
->ccm
, sizeof(s
->ccm
), TYPE_IMX25_CCM
);
44 qdev_set_parent_bus(DEVICE(&s
->ccm
), sysbus_get_default());
46 for (i
= 0; i
< FSL_IMX25_NUM_UARTS
; i
++) {
47 object_initialize(&s
->uart
[i
], sizeof(s
->uart
[i
]), TYPE_IMX_SERIAL
);
48 qdev_set_parent_bus(DEVICE(&s
->uart
[i
]), sysbus_get_default());
51 for (i
= 0; i
< FSL_IMX25_NUM_GPTS
; i
++) {
52 object_initialize(&s
->gpt
[i
], sizeof(s
->gpt
[i
]), TYPE_IMX_GPT
);
53 qdev_set_parent_bus(DEVICE(&s
->gpt
[i
]), sysbus_get_default());
56 for (i
= 0; i
< FSL_IMX25_NUM_EPITS
; i
++) {
57 object_initialize(&s
->epit
[i
], sizeof(s
->epit
[i
]), TYPE_IMX_EPIT
);
58 qdev_set_parent_bus(DEVICE(&s
->epit
[i
]), sysbus_get_default());
61 object_initialize(&s
->fec
, sizeof(s
->fec
), TYPE_IMX_FEC
);
62 qdev_set_parent_bus(DEVICE(&s
->fec
), sysbus_get_default());
64 for (i
= 0; i
< FSL_IMX25_NUM_I2CS
; i
++) {
65 object_initialize(&s
->i2c
[i
], sizeof(s
->i2c
[i
]), TYPE_IMX_I2C
);
66 qdev_set_parent_bus(DEVICE(&s
->i2c
[i
]), sysbus_get_default());
69 for (i
= 0; i
< FSL_IMX25_NUM_GPIOS
; i
++) {
70 object_initialize(&s
->gpio
[i
], sizeof(s
->gpio
[i
]), TYPE_IMX_GPIO
);
71 qdev_set_parent_bus(DEVICE(&s
->gpio
[i
]), sysbus_get_default());
75 static void fsl_imx25_realize(DeviceState
*dev
, Error
**errp
)
77 FslIMX25State
*s
= FSL_IMX25(dev
);
81 object_property_set_bool(OBJECT(&s
->cpu
), true, "realized", &err
);
83 error_propagate(errp
, err
);
87 object_property_set_bool(OBJECT(&s
->avic
), true, "realized", &err
);
89 error_propagate(errp
, err
);
92 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->avic
), 0, FSL_IMX25_AVIC_ADDR
);
93 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 0,
94 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_IRQ
));
95 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->avic
), 1,
96 qdev_get_gpio_in(DEVICE(&s
->cpu
), ARM_CPU_FIQ
));
98 object_property_set_bool(OBJECT(&s
->ccm
), true, "realized", &err
);
100 error_propagate(errp
, err
);
103 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->ccm
), 0, FSL_IMX25_CCM_ADDR
);
105 /* Initialize all UARTs */
106 for (i
= 0; i
< FSL_IMX25_NUM_UARTS
; i
++) {
107 static const struct {
110 } serial_table
[FSL_IMX25_NUM_UARTS
] = {
111 { FSL_IMX25_UART1_ADDR
, FSL_IMX25_UART1_IRQ
},
112 { FSL_IMX25_UART2_ADDR
, FSL_IMX25_UART2_IRQ
},
113 { FSL_IMX25_UART3_ADDR
, FSL_IMX25_UART3_IRQ
},
114 { FSL_IMX25_UART4_ADDR
, FSL_IMX25_UART4_IRQ
},
115 { FSL_IMX25_UART5_ADDR
, FSL_IMX25_UART5_IRQ
}
118 if (i
< MAX_SERIAL_PORTS
) {
119 CharDriverState
*chr
;
125 snprintf(label
, sizeof(label
), "imx31.uart%d", i
);
126 chr
= qemu_chr_new(label
, "null", NULL
);
129 qdev_prop_set_chr(DEVICE(&s
->uart
[i
]), "chardev", chr
);
132 object_property_set_bool(OBJECT(&s
->uart
[i
]), true, "realized", &err
);
134 error_propagate(errp
, err
);
137 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->uart
[i
]), 0, serial_table
[i
].addr
);
138 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->uart
[i
]), 0,
139 qdev_get_gpio_in(DEVICE(&s
->avic
),
140 serial_table
[i
].irq
));
143 /* Initialize all GPT timers */
144 for (i
= 0; i
< FSL_IMX25_NUM_GPTS
; i
++) {
145 static const struct {
148 } gpt_table
[FSL_IMX25_NUM_GPTS
] = {
149 { FSL_IMX25_GPT1_ADDR
, FSL_IMX25_GPT1_IRQ
},
150 { FSL_IMX25_GPT2_ADDR
, FSL_IMX25_GPT2_IRQ
},
151 { FSL_IMX25_GPT3_ADDR
, FSL_IMX25_GPT3_IRQ
},
152 { FSL_IMX25_GPT4_ADDR
, FSL_IMX25_GPT4_IRQ
}
155 s
->gpt
[i
].ccm
= IMX_CCM(&s
->ccm
);
157 object_property_set_bool(OBJECT(&s
->gpt
[i
]), true, "realized", &err
);
159 error_propagate(errp
, err
);
162 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpt
[i
]), 0, gpt_table
[i
].addr
);
163 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpt
[i
]), 0,
164 qdev_get_gpio_in(DEVICE(&s
->avic
),
168 /* Initialize all EPIT timers */
169 for (i
= 0; i
< FSL_IMX25_NUM_EPITS
; i
++) {
170 static const struct {
173 } epit_table
[FSL_IMX25_NUM_EPITS
] = {
174 { FSL_IMX25_EPIT1_ADDR
, FSL_IMX25_EPIT1_IRQ
},
175 { FSL_IMX25_EPIT2_ADDR
, FSL_IMX25_EPIT2_IRQ
}
178 s
->epit
[i
].ccm
= IMX_CCM(&s
->ccm
);
180 object_property_set_bool(OBJECT(&s
->epit
[i
]), true, "realized", &err
);
182 error_propagate(errp
, err
);
185 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->epit
[i
]), 0, epit_table
[i
].addr
);
186 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->epit
[i
]), 0,
187 qdev_get_gpio_in(DEVICE(&s
->avic
),
191 qdev_set_nic_properties(DEVICE(&s
->fec
), &nd_table
[0]);
192 object_property_set_bool(OBJECT(&s
->fec
), true, "realized", &err
);
194 error_propagate(errp
, err
);
197 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->fec
), 0, FSL_IMX25_FEC_ADDR
);
198 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->fec
), 0,
199 qdev_get_gpio_in(DEVICE(&s
->avic
), FSL_IMX25_FEC_IRQ
));
202 /* Initialize all I2C */
203 for (i
= 0; i
< FSL_IMX25_NUM_I2CS
; i
++) {
204 static const struct {
207 } i2c_table
[FSL_IMX25_NUM_I2CS
] = {
208 { FSL_IMX25_I2C1_ADDR
, FSL_IMX25_I2C1_IRQ
},
209 { FSL_IMX25_I2C2_ADDR
, FSL_IMX25_I2C2_IRQ
},
210 { FSL_IMX25_I2C3_ADDR
, FSL_IMX25_I2C3_IRQ
}
213 object_property_set_bool(OBJECT(&s
->i2c
[i
]), true, "realized", &err
);
215 error_propagate(errp
, err
);
218 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0, i2c_table
[i
].addr
);
219 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->i2c
[i
]), 0,
220 qdev_get_gpio_in(DEVICE(&s
->avic
),
224 /* Initialize all GPIOs */
225 for (i
= 0; i
< FSL_IMX25_NUM_GPIOS
; i
++) {
226 static const struct {
229 } gpio_table
[FSL_IMX25_NUM_GPIOS
] = {
230 { FSL_IMX25_GPIO1_ADDR
, FSL_IMX25_GPIO1_IRQ
},
231 { FSL_IMX25_GPIO2_ADDR
, FSL_IMX25_GPIO2_IRQ
},
232 { FSL_IMX25_GPIO3_ADDR
, FSL_IMX25_GPIO3_IRQ
},
233 { FSL_IMX25_GPIO4_ADDR
, FSL_IMX25_GPIO4_IRQ
}
236 object_property_set_bool(OBJECT(&s
->gpio
[i
]), true, "realized", &err
);
238 error_propagate(errp
, err
);
241 sysbus_mmio_map(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0, gpio_table
[i
].addr
);
242 /* Connect GPIO IRQ to PIC */
243 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->gpio
[i
]), 0,
244 qdev_get_gpio_in(DEVICE(&s
->avic
),
248 /* initialize 2 x 16 KB ROM */
249 memory_region_init_rom_device(&s
->rom
[0], NULL
, NULL
, NULL
,
250 "imx25.rom0", FSL_IMX25_ROM0_SIZE
, &err
);
252 error_propagate(errp
, err
);
255 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM0_ADDR
,
257 memory_region_init_rom_device(&s
->rom
[1], NULL
, NULL
, NULL
,
258 "imx25.rom1", FSL_IMX25_ROM1_SIZE
, &err
);
260 error_propagate(errp
, err
);
263 memory_region_add_subregion(get_system_memory(), FSL_IMX25_ROM1_ADDR
,
266 /* initialize internal RAM (128 KB) */
267 memory_region_init_ram(&s
->iram
, NULL
, "imx25.iram", FSL_IMX25_IRAM_SIZE
,
270 error_propagate(errp
, err
);
273 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ADDR
,
275 vmstate_register_ram_global(&s
->iram
);
277 /* internal RAM (128 KB) is aliased over 128 MB - 128 KB */
278 memory_region_init_alias(&s
->iram_alias
, NULL
, "imx25.iram_alias",
279 &s
->iram
, 0, FSL_IMX25_IRAM_ALIAS_SIZE
);
280 memory_region_add_subregion(get_system_memory(), FSL_IMX25_IRAM_ALIAS_ADDR
,
284 static void fsl_imx25_class_init(ObjectClass
*oc
, void *data
)
286 DeviceClass
*dc
= DEVICE_CLASS(oc
);
288 dc
->realize
= fsl_imx25_realize
;
291 * Reason: creates an ARM CPU, thus use after free(), see
292 * arm_cpu_class_init()
294 dc
->cannot_destroy_with_object_finalize_yet
= true;
295 dc
->desc
= "i.MX25 SOC";
298 static const TypeInfo fsl_imx25_type_info
= {
299 .name
= TYPE_FSL_IMX25
,
300 .parent
= TYPE_DEVICE
,
301 .instance_size
= sizeof(FslIMX25State
),
302 .instance_init
= fsl_imx25_init
,
303 .class_init
= fsl_imx25_class_init
,
306 static void fsl_imx25_register_types(void)
308 type_register_static(&fsl_imx25_type_info
);
311 type_init(fsl_imx25_register_types
)