1 /* Support for generating ACPI tables and passing them to Guests
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
7 * Author: Michael S. Tsirkin <mst@redhat.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
27 #include "qemu-common.h"
28 #include "qemu/bitmap.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
48 /* Supported chipsets: */
49 #include "hw/acpi/piix4.h"
50 #include "hw/acpi/pcihp.h"
51 #include "hw/i386/ich9.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/q35.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/timer/hpet.h"
57 #include "hw/acpi/aml-build.h"
59 #include "qapi/qmp/qint.h"
60 #include "qom/qom-qobject.h"
62 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
63 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
64 * a little bit, there should be plenty of free space since the DSDT
65 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
67 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
68 #define ACPI_BUILD_ALIGN_SIZE 0x1000
70 #define ACPI_BUILD_TABLE_SIZE 0x20000
72 /* #define DEBUG_ACPI_BUILD */
73 #ifdef DEBUG_ACPI_BUILD
74 #define ACPI_BUILD_DPRINTF(fmt, ...) \
75 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
77 #define ACPI_BUILD_DPRINTF(fmt, ...)
80 typedef struct AcpiMcfgInfo
{
85 typedef struct AcpiPmInfo
{
91 uint8_t acpi_enable_cmd
;
92 uint8_t acpi_disable_cmd
;
94 uint32_t gpe0_blk_len
;
96 uint16_t cpu_hp_io_base
;
97 uint16_t mem_hp_io_base
;
98 uint16_t mem_hp_io_len
;
99 uint16_t pcihp_io_base
;
100 uint16_t pcihp_io_len
;
103 typedef struct AcpiMiscInfo
{
106 TPMVersion tpm_version
;
107 const unsigned char *dsdt_code
;
109 uint16_t pvpanic_port
;
110 uint16_t applesmc_io_base
;
113 typedef struct AcpiBuildPciBusHotplugState
{
114 GArray
*device_table
;
115 GArray
*notify_table
;
116 struct AcpiBuildPciBusHotplugState
*parent
;
117 bool pcihp_bridge_en
;
118 } AcpiBuildPciBusHotplugState
;
120 static void acpi_get_pm_info(AcpiPmInfo
*pm
)
122 Object
*piix
= piix4_pm_find();
123 Object
*lpc
= ich9_lpc_find();
127 pm
->cpu_hp_io_base
= 0;
128 pm
->pcihp_io_base
= 0;
129 pm
->pcihp_io_len
= 0;
132 pm
->cpu_hp_io_base
= PIIX4_CPU_HOTPLUG_IO_BASE
;
134 object_property_get_int(obj
, ACPI_PCIHP_IO_BASE_PROP
, NULL
);
136 object_property_get_int(obj
, ACPI_PCIHP_IO_LEN_PROP
, NULL
);
140 pm
->cpu_hp_io_base
= ICH9_CPU_HOTPLUG_IO_BASE
;
144 pm
->mem_hp_io_base
= ACPI_MEMORY_HOTPLUG_BASE
;
145 pm
->mem_hp_io_len
= ACPI_MEMORY_HOTPLUG_IO_LEN
;
147 /* Fill in optional s3/s4 related properties */
148 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S3_DISABLED
, NULL
);
150 pm
->s3_disabled
= qint_get_int(qobject_to_qint(o
));
152 pm
->s3_disabled
= false;
155 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_DISABLED
, NULL
);
157 pm
->s4_disabled
= qint_get_int(qobject_to_qint(o
));
159 pm
->s4_disabled
= false;
162 o
= object_property_get_qobject(obj
, ACPI_PM_PROP_S4_VAL
, NULL
);
164 pm
->s4_val
= qint_get_int(qobject_to_qint(o
));
170 /* Fill in mandatory properties */
171 pm
->sci_int
= object_property_get_int(obj
, ACPI_PM_PROP_SCI_INT
, NULL
);
173 pm
->acpi_enable_cmd
= object_property_get_int(obj
,
174 ACPI_PM_PROP_ACPI_ENABLE_CMD
,
176 pm
->acpi_disable_cmd
= object_property_get_int(obj
,
177 ACPI_PM_PROP_ACPI_DISABLE_CMD
,
179 pm
->io_base
= object_property_get_int(obj
, ACPI_PM_PROP_PM_IO_BASE
,
181 pm
->gpe0_blk
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK
,
183 pm
->gpe0_blk_len
= object_property_get_int(obj
, ACPI_PM_PROP_GPE0_BLK_LEN
,
185 pm
->pcihp_bridge_en
=
186 object_property_get_bool(obj
, "acpi-pci-hotplug-with-bridge-support",
190 static void acpi_get_misc_info(AcpiMiscInfo
*info
)
192 Object
*piix
= piix4_pm_find();
193 Object
*lpc
= ich9_lpc_find();
194 assert(!!piix
!= !!lpc
);
197 info
->is_piix4
= true;
200 info
->is_piix4
= false;
203 info
->has_hpet
= hpet_find();
204 info
->tpm_version
= tpm_get_version();
205 info
->pvpanic_port
= pvpanic_port();
206 info
->applesmc_io_base
= applesmc_port();
210 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
211 * On i386 arch we only have two pci hosts, so we can look only for them.
213 static Object
*acpi_get_i386_pci_host(void)
217 host
= OBJECT_CHECK(PCIHostState
,
218 object_resolve_path("/machine/i440fx", NULL
),
219 TYPE_PCI_HOST_BRIDGE
);
221 host
= OBJECT_CHECK(PCIHostState
,
222 object_resolve_path("/machine/q35", NULL
),
223 TYPE_PCI_HOST_BRIDGE
);
229 static void acpi_get_pci_info(PcPciInfo
*info
)
234 pci_host
= acpi_get_i386_pci_host();
237 info
->w32
.begin
= object_property_get_int(pci_host
,
238 PCI_HOST_PROP_PCI_HOLE_START
,
240 info
->w32
.end
= object_property_get_int(pci_host
,
241 PCI_HOST_PROP_PCI_HOLE_END
,
243 info
->w64
.begin
= object_property_get_int(pci_host
,
244 PCI_HOST_PROP_PCI_HOLE64_START
,
246 info
->w64
.end
= object_property_get_int(pci_host
,
247 PCI_HOST_PROP_PCI_HOLE64_END
,
251 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
253 static void acpi_align_size(GArray
*blob
, unsigned align
)
255 /* Align size to multiple of given size. This reduces the chance
256 * we need to change size in the future (breaking cross version migration).
258 g_array_set_size(blob
, ROUND_UP(acpi_data_len(blob
), align
));
263 build_facs(GArray
*table_data
, BIOSLinker
*linker
)
265 AcpiFacsDescriptorRev1
*facs
= acpi_data_push(table_data
, sizeof *facs
);
266 memcpy(&facs
->signature
, "FACS", 4);
267 facs
->length
= cpu_to_le32(sizeof(*facs
));
270 /* Load chipset information in FADT */
271 static void fadt_setup(AcpiFadtDescriptorRev1
*fadt
, AcpiPmInfo
*pm
)
275 fadt
->sci_int
= cpu_to_le16(pm
->sci_int
);
276 fadt
->smi_cmd
= cpu_to_le32(ACPI_PORT_SMI_CMD
);
277 fadt
->acpi_enable
= pm
->acpi_enable_cmd
;
278 fadt
->acpi_disable
= pm
->acpi_disable_cmd
;
279 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
280 fadt
->pm1a_evt_blk
= cpu_to_le32(pm
->io_base
);
281 fadt
->pm1a_cnt_blk
= cpu_to_le32(pm
->io_base
+ 0x04);
282 fadt
->pm_tmr_blk
= cpu_to_le32(pm
->io_base
+ 0x08);
283 fadt
->gpe0_blk
= cpu_to_le32(pm
->gpe0_blk
);
284 /* EVT, CNT, TMR length matches hw/acpi/core.c */
285 fadt
->pm1_evt_len
= 4;
286 fadt
->pm1_cnt_len
= 2;
287 fadt
->pm_tmr_len
= 4;
288 fadt
->gpe0_blk_len
= pm
->gpe0_blk_len
;
289 fadt
->plvl2_lat
= cpu_to_le16(0xfff); /* C2 state not supported */
290 fadt
->plvl3_lat
= cpu_to_le16(0xfff); /* C3 state not supported */
291 fadt
->flags
= cpu_to_le32((1 << ACPI_FADT_F_WBINVD
) |
292 (1 << ACPI_FADT_F_PROC_C1
) |
293 (1 << ACPI_FADT_F_SLP_BUTTON
) |
294 (1 << ACPI_FADT_F_RTC_S4
));
295 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK
);
296 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
297 * For more than 8 CPUs, "Clustered Logical" mode has to be used
300 fadt
->flags
|= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL
);
302 fadt
->century
= RTC_CENTURY
;
308 build_fadt(GArray
*table_data
, BIOSLinker
*linker
, AcpiPmInfo
*pm
,
309 unsigned facs_tbl_offset
, unsigned dsdt_tbl_offset
,
310 const char *oem_id
, const char *oem_table_id
)
312 AcpiFadtDescriptorRev1
*fadt
= acpi_data_push(table_data
, sizeof(*fadt
));
313 unsigned fw_ctrl_offset
= (char *)&fadt
->firmware_ctrl
- table_data
->data
;
314 unsigned dsdt_entry_offset
= (char *)&fadt
->dsdt
- table_data
->data
;
316 /* FACS address to be filled by Guest linker */
317 bios_linker_loader_add_pointer(linker
,
318 ACPI_BUILD_TABLE_FILE
, fw_ctrl_offset
, sizeof(fadt
->firmware_ctrl
),
319 ACPI_BUILD_TABLE_FILE
, facs_tbl_offset
);
321 /* DSDT address to be filled by Guest linker */
322 fadt_setup(fadt
, pm
);
323 bios_linker_loader_add_pointer(linker
,
324 ACPI_BUILD_TABLE_FILE
, dsdt_entry_offset
, sizeof(fadt
->dsdt
),
325 ACPI_BUILD_TABLE_FILE
, dsdt_tbl_offset
);
327 build_header(linker
, table_data
,
328 (void *)fadt
, "FACP", sizeof(*fadt
), 1, oem_id
, oem_table_id
);
332 build_madt(GArray
*table_data
, BIOSLinker
*linker
, PCMachineState
*pcms
)
334 MachineClass
*mc
= MACHINE_GET_CLASS(pcms
);
335 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(MACHINE(pcms
));
336 int madt_start
= table_data
->len
;
338 AcpiMultipleApicTable
*madt
;
339 AcpiMadtIoApic
*io_apic
;
340 AcpiMadtIntsrcovr
*intsrcovr
;
341 AcpiMadtLocalNmi
*local_nmi
;
344 madt
= acpi_data_push(table_data
, sizeof *madt
);
345 madt
->local_apic_address
= cpu_to_le32(APIC_DEFAULT_ADDRESS
);
346 madt
->flags
= cpu_to_le32(1);
348 for (i
= 0; i
< apic_ids
->len
; i
++) {
349 AcpiMadtProcessorApic
*apic
= acpi_data_push(table_data
, sizeof *apic
);
350 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
352 apic
->type
= ACPI_APIC_PROCESSOR
;
353 apic
->length
= sizeof(*apic
);
354 apic
->processor_id
= i
;
355 apic
->local_apic_id
= apic_id
;
356 if (apic_ids
->cpus
[i
].cpu
!= NULL
) {
357 apic
->flags
= cpu_to_le32(1);
359 /* ACPI spec says that LAPIC entry for non present
360 * CPU may be omitted from MADT or it must be marked
361 * as disabled. However omitting non present CPU from
362 * MADT breaks hotplug on linux. So possible CPUs
363 * should be put in MADT but kept disabled.
365 apic
->flags
= cpu_to_le32(0);
370 io_apic
= acpi_data_push(table_data
, sizeof *io_apic
);
371 io_apic
->type
= ACPI_APIC_IO
;
372 io_apic
->length
= sizeof(*io_apic
);
373 #define ACPI_BUILD_IOAPIC_ID 0x0
374 io_apic
->io_apic_id
= ACPI_BUILD_IOAPIC_ID
;
375 io_apic
->address
= cpu_to_le32(IO_APIC_DEFAULT_ADDRESS
);
376 io_apic
->interrupt
= cpu_to_le32(0);
378 if (pcms
->apic_xrupt_override
) {
379 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
380 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
381 intsrcovr
->length
= sizeof(*intsrcovr
);
382 intsrcovr
->source
= 0;
383 intsrcovr
->gsi
= cpu_to_le32(2);
384 intsrcovr
->flags
= cpu_to_le16(0); /* conforms to bus specifications */
386 for (i
= 1; i
< 16; i
++) {
387 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
388 if (!(ACPI_BUILD_PCI_IRQS
& (1 << i
))) {
389 /* No need for a INT source override structure. */
392 intsrcovr
= acpi_data_push(table_data
, sizeof *intsrcovr
);
393 intsrcovr
->type
= ACPI_APIC_XRUPT_OVERRIDE
;
394 intsrcovr
->length
= sizeof(*intsrcovr
);
395 intsrcovr
->source
= i
;
396 intsrcovr
->gsi
= cpu_to_le32(i
);
397 intsrcovr
->flags
= cpu_to_le16(0xd); /* active high, level triggered */
400 local_nmi
= acpi_data_push(table_data
, sizeof *local_nmi
);
401 local_nmi
->type
= ACPI_APIC_LOCAL_NMI
;
402 local_nmi
->length
= sizeof(*local_nmi
);
403 local_nmi
->processor_id
= 0xff; /* all processors */
404 local_nmi
->flags
= cpu_to_le16(0);
405 local_nmi
->lint
= 1; /* ACPI_LINT1 */
407 build_header(linker
, table_data
,
408 (void *)(table_data
->data
+ madt_start
), "APIC",
409 table_data
->len
- madt_start
, 1, NULL
, NULL
);
412 /* Assign BSEL property to all buses. In the future, this can be changed
413 * to only assign to buses that support hotplug.
415 static void *acpi_set_bsel(PCIBus
*bus
, void *opaque
)
417 unsigned *bsel_alloc
= opaque
;
420 if (qbus_is_hotpluggable(BUS(bus
))) {
421 bus_bsel
= g_malloc(sizeof *bus_bsel
);
423 *bus_bsel
= (*bsel_alloc
)++;
424 object_property_add_uint32_ptr(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
,
431 static void acpi_set_pci_info(void)
433 PCIBus
*bus
= find_i440fx(); /* TODO: Q35 support */
434 unsigned bsel_alloc
= 0;
437 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
438 pci_for_each_bus_depth_first(bus
, acpi_set_bsel
, NULL
, &bsel_alloc
);
442 static void build_append_pcihp_notify_entry(Aml
*method
, int slot
)
445 int32_t devfn
= PCI_DEVFN(slot
, 0);
447 if_ctx
= aml_if(aml_and(aml_arg(0), aml_int(0x1U
<< slot
), NULL
));
448 aml_append(if_ctx
, aml_notify(aml_name("S%.02X", devfn
), aml_arg(1)));
449 aml_append(method
, if_ctx
);
452 static void build_append_pci_bus_devices(Aml
*parent_scope
, PCIBus
*bus
,
453 bool pcihp_bridge_en
)
455 Aml
*dev
, *notify_method
, *method
;
460 bsel
= object_property_get_qobject(OBJECT(bus
), ACPI_PCIHP_PROP_BSEL
, NULL
);
462 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
464 aml_append(parent_scope
, aml_name_decl("BSEL", aml_int(bsel_val
)));
465 notify_method
= aml_method("DVNT", 2, AML_NOTSERIALIZED
);
468 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); i
+= PCI_FUNC_MAX
) {
471 PCIDevice
*pdev
= bus
->devices
[i
];
472 int slot
= PCI_SLOT(i
);
473 bool hotplug_enabled_dev
;
477 if (bsel
) { /* add hotplug slots for non present devices */
478 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
479 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
480 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
481 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
483 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
485 aml_append(dev
, method
);
486 aml_append(parent_scope
, dev
);
488 build_append_pcihp_notify_entry(notify_method
, slot
);
493 pc
= PCI_DEVICE_GET_CLASS(pdev
);
494 dc
= DEVICE_GET_CLASS(pdev
);
496 /* When hotplug for bridges is enabled, bridges are
497 * described in ACPI separately (see build_pci_bus_end).
498 * In this case they aren't themselves hot-pluggable.
499 * Hotplugged bridges *are* hot-pluggable.
501 bridge_in_acpi
= pc
->is_bridge
&& pcihp_bridge_en
&&
502 !DEVICE(pdev
)->hotplugged
;
504 hotplug_enabled_dev
= bsel
&& dc
->hotpluggable
&& !bridge_in_acpi
;
506 if (pc
->class_id
== PCI_CLASS_BRIDGE_ISA
) {
510 /* start to compose PCI slot descriptor */
511 dev
= aml_device("S%.02X", PCI_DEVFN(slot
, 0));
512 aml_append(dev
, aml_name_decl("_ADR", aml_int(slot
<< 16)));
514 if (pc
->class_id
== PCI_CLASS_DISPLAY_VGA
) {
515 /* add VGA specific AML methods */
518 if (object_dynamic_cast(OBJECT(pdev
), "qxl-vga")) {
524 method
= aml_method("_S1D", 0, AML_NOTSERIALIZED
);
525 aml_append(method
, aml_return(aml_int(0)));
526 aml_append(dev
, method
);
528 method
= aml_method("_S2D", 0, AML_NOTSERIALIZED
);
529 aml_append(method
, aml_return(aml_int(0)));
530 aml_append(dev
, method
);
532 method
= aml_method("_S3D", 0, AML_NOTSERIALIZED
);
533 aml_append(method
, aml_return(aml_int(s3d
)));
534 aml_append(dev
, method
);
535 } else if (hotplug_enabled_dev
) {
536 /* add _SUN/_EJ0 to make slot hotpluggable */
537 aml_append(dev
, aml_name_decl("_SUN", aml_int(slot
)));
539 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
541 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
543 aml_append(dev
, method
);
546 build_append_pcihp_notify_entry(notify_method
, slot
);
548 } else if (bridge_in_acpi
) {
550 * device is coldplugged bridge,
551 * add child device descriptions into its scope
553 PCIBus
*sec_bus
= pci_bridge_get_sec_bus(PCI_BRIDGE(pdev
));
555 build_append_pci_bus_devices(dev
, sec_bus
, pcihp_bridge_en
);
557 /* slot descriptor has been composed, add it into parent context */
558 aml_append(parent_scope
, dev
);
562 aml_append(parent_scope
, notify_method
);
565 /* Append PCNT method to notify about events on local and child buses.
566 * Add unconditionally for root since DSDT expects it.
568 method
= aml_method("PCNT", 0, AML_NOTSERIALIZED
);
570 /* If bus supports hotplug select it and notify about local events */
572 int64_t bsel_val
= qint_get_int(qobject_to_qint(bsel
));
573 aml_append(method
, aml_store(aml_int(bsel_val
), aml_name("BNUM")));
575 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
578 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
582 /* Notify about child bus events in any case */
583 if (pcihp_bridge_en
) {
584 QLIST_FOREACH(sec
, &bus
->child
, sibling
) {
585 int32_t devfn
= sec
->parent_dev
->devfn
;
587 aml_append(method
, aml_name("^S%.02X.PCNT", devfn
));
590 aml_append(parent_scope
, method
);
591 qobject_decref(bsel
);
596 * @link_name: link name for PCI route entry
598 * build AML package containing a PCI route entry for @link_name
600 static Aml
*build_prt_entry(const char *link_name
)
602 Aml
*a_zero
= aml_int(0);
603 Aml
*pkg
= aml_package(4);
604 aml_append(pkg
, a_zero
);
605 aml_append(pkg
, a_zero
);
606 aml_append(pkg
, aml_name("%s", link_name
));
607 aml_append(pkg
, a_zero
);
612 * initialize_route - Initialize the interrupt routing rule
613 * through a specific LINK:
614 * if (lnk_idx == idx)
615 * route using link 'link_name'
617 static Aml
*initialize_route(Aml
*route
, const char *link_name
,
618 Aml
*lnk_idx
, int idx
)
620 Aml
*if_ctx
= aml_if(aml_equal(lnk_idx
, aml_int(idx
)));
621 Aml
*pkg
= build_prt_entry(link_name
);
623 aml_append(if_ctx
, aml_store(pkg
, route
));
629 * build_prt - Define interrupt rounting rules
631 * Returns an array of 128 routes, one for each device,
632 * based on device location.
633 * The main goal is to equaly distribute the interrupts
634 * over the 4 existing ACPI links (works only for i440fx).
635 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
638 static Aml
*build_prt(bool is_pci0_prt
)
640 Aml
*method
, *while_ctx
, *pin
, *res
;
642 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
645 aml_append(method
, aml_store(aml_package(128), res
));
646 aml_append(method
, aml_store(aml_int(0), pin
));
648 /* while (pin < 128) */
649 while_ctx
= aml_while(aml_lless(pin
, aml_int(128)));
651 Aml
*slot
= aml_local(2);
652 Aml
*lnk_idx
= aml_local(3);
653 Aml
*route
= aml_local(4);
655 /* slot = pin >> 2 */
656 aml_append(while_ctx
,
657 aml_store(aml_shiftright(pin
, aml_int(2), NULL
), slot
));
658 /* lnk_idx = (slot + pin) & 3 */
659 aml_append(while_ctx
,
660 aml_store(aml_and(aml_add(pin
, slot
, NULL
), aml_int(3), NULL
),
663 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
664 aml_append(while_ctx
, initialize_route(route
, "LNKD", lnk_idx
, 0));
666 Aml
*if_device_1
, *if_pin_4
, *else_pin_4
;
668 /* device 1 is the power-management device, needs SCI */
669 if_device_1
= aml_if(aml_equal(lnk_idx
, aml_int(1)));
671 if_pin_4
= aml_if(aml_equal(pin
, aml_int(4)));
674 aml_store(build_prt_entry("LNKS"), route
));
676 aml_append(if_device_1
, if_pin_4
);
677 else_pin_4
= aml_else();
679 aml_append(else_pin_4
,
680 aml_store(build_prt_entry("LNKA"), route
));
682 aml_append(if_device_1
, else_pin_4
);
684 aml_append(while_ctx
, if_device_1
);
686 aml_append(while_ctx
, initialize_route(route
, "LNKA", lnk_idx
, 1));
688 aml_append(while_ctx
, initialize_route(route
, "LNKB", lnk_idx
, 2));
689 aml_append(while_ctx
, initialize_route(route
, "LNKC", lnk_idx
, 3));
691 /* route[0] = 0x[slot]FFFF */
692 aml_append(while_ctx
,
693 aml_store(aml_or(aml_shiftleft(slot
, aml_int(16)), aml_int(0xFFFF),
695 aml_index(route
, aml_int(0))));
696 /* route[1] = pin & 3 */
697 aml_append(while_ctx
,
698 aml_store(aml_and(pin
, aml_int(3), NULL
),
699 aml_index(route
, aml_int(1))));
700 /* res[pin] = route */
701 aml_append(while_ctx
, aml_store(route
, aml_index(res
, pin
)));
703 aml_append(while_ctx
, aml_increment(pin
));
705 aml_append(method
, while_ctx
);
707 aml_append(method
, aml_return(res
));
712 typedef struct CrsRangeEntry
{
717 static void crs_range_insert(GPtrArray
*ranges
, uint64_t base
, uint64_t limit
)
719 CrsRangeEntry
*entry
;
721 entry
= g_malloc(sizeof(*entry
));
723 entry
->limit
= limit
;
725 g_ptr_array_add(ranges
, entry
);
728 static void crs_range_free(gpointer data
)
730 CrsRangeEntry
*entry
= (CrsRangeEntry
*)data
;
734 static gint
crs_range_compare(gconstpointer a
, gconstpointer b
)
736 CrsRangeEntry
*entry_a
= *(CrsRangeEntry
**)a
;
737 CrsRangeEntry
*entry_b
= *(CrsRangeEntry
**)b
;
739 return (int64_t)entry_a
->base
- (int64_t)entry_b
->base
;
743 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
744 * interval, computes the 'free' ranges from the same interval.
745 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
746 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
748 static void crs_replace_with_free_ranges(GPtrArray
*ranges
,
749 uint64_t start
, uint64_t end
)
751 GPtrArray
*free_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
752 uint64_t free_base
= start
;
755 g_ptr_array_sort(ranges
, crs_range_compare
);
756 for (i
= 0; i
< ranges
->len
; i
++) {
757 CrsRangeEntry
*used
= g_ptr_array_index(ranges
, i
);
759 if (free_base
< used
->base
) {
760 crs_range_insert(free_ranges
, free_base
, used
->base
- 1);
763 free_base
= used
->limit
+ 1;
766 if (free_base
< end
) {
767 crs_range_insert(free_ranges
, free_base
, end
);
770 g_ptr_array_set_size(ranges
, 0);
771 for (i
= 0; i
< free_ranges
->len
; i
++) {
772 g_ptr_array_add(ranges
, g_ptr_array_index(free_ranges
, i
));
775 g_ptr_array_free(free_ranges
, false);
779 * crs_range_merge - merges adjacent ranges in the given array.
780 * Array elements are deleted and replaced with the merged ranges.
782 static void crs_range_merge(GPtrArray
*range
)
784 GPtrArray
*tmp
= g_ptr_array_new_with_free_func(crs_range_free
);
785 CrsRangeEntry
*entry
;
786 uint64_t range_base
, range_limit
;
793 g_ptr_array_sort(range
, crs_range_compare
);
795 entry
= g_ptr_array_index(range
, 0);
796 range_base
= entry
->base
;
797 range_limit
= entry
->limit
;
798 for (i
= 1; i
< range
->len
; i
++) {
799 entry
= g_ptr_array_index(range
, i
);
800 if (entry
->base
- 1 == range_limit
) {
801 range_limit
= entry
->limit
;
803 crs_range_insert(tmp
, range_base
, range_limit
);
804 range_base
= entry
->base
;
805 range_limit
= entry
->limit
;
808 crs_range_insert(tmp
, range_base
, range_limit
);
810 g_ptr_array_set_size(range
, 0);
811 for (i
= 0; i
< tmp
->len
; i
++) {
812 entry
= g_ptr_array_index(tmp
, i
);
813 crs_range_insert(range
, entry
->base
, entry
->limit
);
815 g_ptr_array_free(tmp
, true);
818 static Aml
*build_crs(PCIHostState
*host
,
819 GPtrArray
*io_ranges
, GPtrArray
*mem_ranges
)
821 Aml
*crs
= aml_resource_template();
822 GPtrArray
*host_io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
823 GPtrArray
*host_mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
824 CrsRangeEntry
*entry
;
825 uint8_t max_bus
= pci_bus_num(host
->bus
);
830 for (devfn
= 0; devfn
< ARRAY_SIZE(host
->bus
->devices
); devfn
++) {
831 uint64_t range_base
, range_limit
;
832 PCIDevice
*dev
= host
->bus
->devices
[devfn
];
838 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
839 PCIIORegion
*r
= &dev
->io_regions
[i
];
841 range_base
= r
->addr
;
842 range_limit
= r
->addr
+ r
->size
- 1;
845 * Work-around for old bioses
846 * that do not support multiple root buses
848 if (!range_base
|| range_base
> range_limit
) {
852 if (r
->type
& PCI_BASE_ADDRESS_SPACE_IO
) {
853 crs_range_insert(host_io_ranges
, range_base
, range_limit
);
854 } else { /* "memory" */
855 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
859 type
= dev
->config
[PCI_HEADER_TYPE
] & ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
860 if (type
== PCI_HEADER_TYPE_BRIDGE
) {
861 uint8_t subordinate
= dev
->config
[PCI_SUBORDINATE_BUS
];
862 if (subordinate
> max_bus
) {
863 max_bus
= subordinate
;
866 range_base
= pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
867 range_limit
= pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_IO
);
870 * Work-around for old bioses
871 * that do not support multiple root buses
873 if (range_base
&& range_base
<= range_limit
) {
874 crs_range_insert(host_io_ranges
, range_base
, range_limit
);
878 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
880 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_SPACE_MEMORY
);
883 * Work-around for old bioses
884 * that do not support multiple root buses
886 if (range_base
&& range_base
<= range_limit
) {
887 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
891 pci_bridge_get_base(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
893 pci_bridge_get_limit(dev
, PCI_BASE_ADDRESS_MEM_PREFETCH
);
896 * Work-around for old bioses
897 * that do not support multiple root buses
899 if (range_base
&& range_base
<= range_limit
) {
900 crs_range_insert(host_mem_ranges
, range_base
, range_limit
);
905 crs_range_merge(host_io_ranges
);
906 for (i
= 0; i
< host_io_ranges
->len
; i
++) {
907 entry
= g_ptr_array_index(host_io_ranges
, i
);
909 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
910 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
911 0, entry
->base
, entry
->limit
, 0,
912 entry
->limit
- entry
->base
+ 1));
913 crs_range_insert(io_ranges
, entry
->base
, entry
->limit
);
915 g_ptr_array_free(host_io_ranges
, true);
917 crs_range_merge(host_mem_ranges
);
918 for (i
= 0; i
< host_mem_ranges
->len
; i
++) {
919 entry
= g_ptr_array_index(host_mem_ranges
, i
);
921 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
,
922 AML_MAX_FIXED
, AML_NON_CACHEABLE
,
924 0, entry
->base
, entry
->limit
, 0,
925 entry
->limit
- entry
->base
+ 1));
926 crs_range_insert(mem_ranges
, entry
->base
, entry
->limit
);
928 g_ptr_array_free(host_mem_ranges
, true);
931 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
933 pci_bus_num(host
->bus
),
936 max_bus
- pci_bus_num(host
->bus
) + 1));
941 static void build_memory_devices(Aml
*sb_scope
, int nr_mem
,
942 uint16_t io_base
, uint16_t io_len
)
952 /* build memory devices */
953 assert(nr_mem
<= ACPI_MAX_RAM_SLOTS
);
954 scope
= aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE
);
956 aml_name_decl(MEMORY_SLOTS_NUMBER
, aml_int(nr_mem
))
959 crs
= aml_resource_template();
961 aml_io(AML_DECODE16
, io_base
, io_base
, 0, io_len
)
963 aml_append(scope
, aml_name_decl("_CRS", crs
));
965 aml_append(scope
, aml_operation_region(
966 MEMORY_HOTPLUG_IO_REGION
, AML_SYSTEM_IO
,
967 aml_int(io_base
), io_len
)
970 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
971 AML_NOLOCK
, AML_PRESERVE
);
972 aml_append(field
, /* read only */
973 aml_named_field(MEMORY_SLOT_ADDR_LOW
, 32));
974 aml_append(field
, /* read only */
975 aml_named_field(MEMORY_SLOT_ADDR_HIGH
, 32));
976 aml_append(field
, /* read only */
977 aml_named_field(MEMORY_SLOT_SIZE_LOW
, 32));
978 aml_append(field
, /* read only */
979 aml_named_field(MEMORY_SLOT_SIZE_HIGH
, 32));
980 aml_append(field
, /* read only */
981 aml_named_field(MEMORY_SLOT_PROXIMITY
, 32));
982 aml_append(scope
, field
);
984 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_BYTE_ACC
,
985 AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
986 aml_append(field
, aml_reserved_field(160 /* bits, Offset(20) */));
987 aml_append(field
, /* 1 if enabled, read only */
988 aml_named_field(MEMORY_SLOT_ENABLED
, 1));
990 /*(read) 1 if has a insert event. (write) 1 to clear event */
991 aml_named_field(MEMORY_SLOT_INSERT_EVENT
, 1));
993 /* (read) 1 if has a remove event. (write) 1 to clear event */
994 aml_named_field(MEMORY_SLOT_REMOVE_EVENT
, 1));
996 /* initiates device eject, write only */
997 aml_named_field(MEMORY_SLOT_EJECT
, 1));
998 aml_append(scope
, field
);
1000 field
= aml_field(MEMORY_HOTPLUG_IO_REGION
, AML_DWORD_ACC
,
1001 AML_NOLOCK
, AML_PRESERVE
);
1002 aml_append(field
, /* DIMM selector, write only */
1003 aml_named_field(MEMORY_SLOT_SLECTOR
, 32));
1004 aml_append(field
, /* _OST event code, write only */
1005 aml_named_field(MEMORY_SLOT_OST_EVENT
, 32));
1006 aml_append(field
, /* _OST status code, write only */
1007 aml_named_field(MEMORY_SLOT_OST_STATUS
, 32));
1008 aml_append(scope
, field
);
1009 aml_append(sb_scope
, scope
);
1011 for (i
= 0; i
< nr_mem
; i
++) {
1012 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1015 dev
= aml_device("MP%02X", i
);
1016 aml_append(dev
, aml_name_decl("_UID", aml_string("0x%02X", i
)));
1017 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1019 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1020 s
= BASEPATH MEMORY_SLOT_CRS_METHOD
;
1021 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1022 aml_append(dev
, method
);
1024 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1025 s
= BASEPATH MEMORY_SLOT_STATUS_METHOD
;
1026 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1027 aml_append(dev
, method
);
1029 method
= aml_method("_PXM", 0, AML_NOTSERIALIZED
);
1030 s
= BASEPATH MEMORY_SLOT_PROXIMITY_METHOD
;
1031 aml_append(method
, aml_return(aml_call1(s
, aml_name("_UID"))));
1032 aml_append(dev
, method
);
1034 method
= aml_method("_OST", 3, AML_NOTSERIALIZED
);
1035 s
= BASEPATH MEMORY_SLOT_OST_METHOD
;
1037 aml_append(method
, aml_return(aml_call4(
1038 s
, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1040 aml_append(dev
, method
);
1042 method
= aml_method("_EJ0", 1, AML_NOTSERIALIZED
);
1043 s
= BASEPATH MEMORY_SLOT_EJECT_METHOD
;
1044 aml_append(method
, aml_return(aml_call2(
1045 s
, aml_name("_UID"), aml_arg(0))));
1046 aml_append(dev
, method
);
1048 aml_append(sb_scope
, dev
);
1051 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1052 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1054 method
= aml_method(MEMORY_SLOT_NOTIFY_METHOD
, 2, AML_NOTSERIALIZED
);
1055 for (i
= 0; i
< nr_mem
; i
++) {
1056 ifctx
= aml_if(aml_equal(aml_arg(0), aml_int(i
)));
1058 aml_notify(aml_name("MP%.02X", i
), aml_arg(1))
1060 aml_append(method
, ifctx
);
1062 aml_append(sb_scope
, method
);
1065 static void build_hpet_aml(Aml
*table
)
1071 Aml
*scope
= aml_scope("_SB");
1072 Aml
*dev
= aml_device("HPET");
1073 Aml
*zero
= aml_int(0);
1074 Aml
*id
= aml_local(0);
1075 Aml
*period
= aml_local(1);
1077 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1078 aml_append(dev
, aml_name_decl("_UID", zero
));
1081 aml_operation_region("HPTM", AML_SYSTEM_MEMORY
, aml_int(HPET_BASE
),
1083 field
= aml_field("HPTM", AML_DWORD_ACC
, AML_LOCK
, AML_PRESERVE
);
1084 aml_append(field
, aml_named_field("VEND", 32));
1085 aml_append(field
, aml_named_field("PRD", 32));
1086 aml_append(dev
, field
);
1088 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1089 aml_append(method
, aml_store(aml_name("VEND"), id
));
1090 aml_append(method
, aml_store(aml_name("PRD"), period
));
1091 aml_append(method
, aml_shiftright(id
, aml_int(16), id
));
1092 if_ctx
= aml_if(aml_lor(aml_equal(id
, zero
),
1093 aml_equal(id
, aml_int(0xffff))));
1095 aml_append(if_ctx
, aml_return(zero
));
1097 aml_append(method
, if_ctx
);
1099 if_ctx
= aml_if(aml_lor(aml_equal(period
, zero
),
1100 aml_lgreater(period
, aml_int(100000000))));
1102 aml_append(if_ctx
, aml_return(zero
));
1104 aml_append(method
, if_ctx
);
1106 aml_append(method
, aml_return(aml_int(0x0F)));
1107 aml_append(dev
, method
);
1109 crs
= aml_resource_template();
1110 aml_append(crs
, aml_memory32_fixed(HPET_BASE
, HPET_LEN
, AML_READ_ONLY
));
1111 aml_append(dev
, aml_name_decl("_CRS", crs
));
1113 aml_append(scope
, dev
);
1114 aml_append(table
, scope
);
1117 static Aml
*build_fdinfo_aml(int idx
, FloppyDriveType type
)
1120 uint8_t maxc
, maxh
, maxs
;
1122 isa_fdc_get_drive_max_chs(type
, &maxc
, &maxh
, &maxs
);
1124 dev
= aml_device("FLP%c", 'A' + idx
);
1126 aml_append(dev
, aml_name_decl("_ADR", aml_int(idx
)));
1128 fdi
= aml_package(16);
1129 aml_append(fdi
, aml_int(idx
)); /* Drive Number */
1131 aml_int(cmos_get_fd_drive_type(type
))); /* Device Type */
1133 * the values below are the limits of the drive, and are thus independent
1134 * of the inserted media
1136 aml_append(fdi
, aml_int(maxc
)); /* Maximum Cylinder Number */
1137 aml_append(fdi
, aml_int(maxs
)); /* Maximum Sector Number */
1138 aml_append(fdi
, aml_int(maxh
)); /* Maximum Head Number */
1140 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1141 * the drive type, so shall we
1143 aml_append(fdi
, aml_int(0xAF)); /* disk_specify_1 */
1144 aml_append(fdi
, aml_int(0x02)); /* disk_specify_2 */
1145 aml_append(fdi
, aml_int(0x25)); /* disk_motor_wait */
1146 aml_append(fdi
, aml_int(0x02)); /* disk_sector_siz */
1147 aml_append(fdi
, aml_int(0x12)); /* disk_eot */
1148 aml_append(fdi
, aml_int(0x1B)); /* disk_rw_gap */
1149 aml_append(fdi
, aml_int(0xFF)); /* disk_dtl */
1150 aml_append(fdi
, aml_int(0x6C)); /* disk_formt_gap */
1151 aml_append(fdi
, aml_int(0xF6)); /* disk_fill */
1152 aml_append(fdi
, aml_int(0x0F)); /* disk_head_sttl */
1153 aml_append(fdi
, aml_int(0x08)); /* disk_motor_strt */
1155 aml_append(dev
, aml_name_decl("_FDI", fdi
));
1159 static Aml
*build_fdc_device_aml(ISADevice
*fdc
)
1165 #define ACPI_FDE_MAX_FD 4
1166 uint32_t fde_buf
[5] = {
1167 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1168 cpu_to_le32(2) /* tape presence (2 == never present) */
1171 dev
= aml_device("FDC0");
1172 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1174 crs
= aml_resource_template();
1175 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F2, 0x03F2, 0x00, 0x04));
1176 aml_append(crs
, aml_io(AML_DECODE16
, 0x03F7, 0x03F7, 0x00, 0x01));
1177 aml_append(crs
, aml_irq_no_flags(6));
1179 aml_dma(AML_COMPATIBILITY
, AML_NOTBUSMASTER
, AML_TRANSFER8
, 2));
1180 aml_append(dev
, aml_name_decl("_CRS", crs
));
1182 for (i
= 0; i
< MIN(MAX_FD
, ACPI_FDE_MAX_FD
); i
++) {
1183 FloppyDriveType type
= isa_fdc_get_drive_type(fdc
, i
);
1185 if (type
< FLOPPY_DRIVE_TYPE_NONE
) {
1186 fde_buf
[i
] = cpu_to_le32(1); /* drive present */
1187 aml_append(dev
, build_fdinfo_aml(i
, type
));
1190 aml_append(dev
, aml_name_decl("_FDE",
1191 aml_buffer(sizeof(fde_buf
), (uint8_t *)fde_buf
)));
1196 static Aml
*build_rtc_device_aml(void)
1201 dev
= aml_device("RTC");
1202 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1203 crs
= aml_resource_template();
1204 aml_append(crs
, aml_io(AML_DECODE16
, 0x0070, 0x0070, 0x10, 0x02));
1205 aml_append(crs
, aml_irq_no_flags(8));
1206 aml_append(crs
, aml_io(AML_DECODE16
, 0x0072, 0x0072, 0x02, 0x06));
1207 aml_append(dev
, aml_name_decl("_CRS", crs
));
1212 static Aml
*build_kbd_device_aml(void)
1218 dev
= aml_device("KBD");
1219 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1221 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1222 aml_append(method
, aml_return(aml_int(0x0f)));
1223 aml_append(dev
, method
);
1225 crs
= aml_resource_template();
1226 aml_append(crs
, aml_io(AML_DECODE16
, 0x0060, 0x0060, 0x01, 0x01));
1227 aml_append(crs
, aml_io(AML_DECODE16
, 0x0064, 0x0064, 0x01, 0x01));
1228 aml_append(crs
, aml_irq_no_flags(1));
1229 aml_append(dev
, aml_name_decl("_CRS", crs
));
1234 static Aml
*build_mouse_device_aml(void)
1240 dev
= aml_device("MOU");
1241 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1243 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1244 aml_append(method
, aml_return(aml_int(0x0f)));
1245 aml_append(dev
, method
);
1247 crs
= aml_resource_template();
1248 aml_append(crs
, aml_irq_no_flags(12));
1249 aml_append(dev
, aml_name_decl("_CRS", crs
));
1254 static Aml
*build_lpt_device_aml(void)
1261 Aml
*zero
= aml_int(0);
1262 Aml
*is_present
= aml_local(0);
1264 dev
= aml_device("LPT");
1265 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1267 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1268 aml_append(method
, aml_store(aml_name("LPEN"), is_present
));
1269 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1271 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1273 aml_append(method
, if_ctx
);
1274 else_ctx
= aml_else();
1276 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1278 aml_append(method
, else_ctx
);
1279 aml_append(dev
, method
);
1281 crs
= aml_resource_template();
1282 aml_append(crs
, aml_io(AML_DECODE16
, 0x0378, 0x0378, 0x08, 0x08));
1283 aml_append(crs
, aml_irq_no_flags(7));
1284 aml_append(dev
, aml_name_decl("_CRS", crs
));
1289 static Aml
*build_com_device_aml(uint8_t uid
)
1296 Aml
*zero
= aml_int(0);
1297 Aml
*is_present
= aml_local(0);
1298 const char *enabled_field
= "CAEN";
1300 uint16_t io_port
= 0x03F8;
1302 assert(uid
== 1 || uid
== 2);
1304 enabled_field
= "CBEN";
1309 dev
= aml_device("COM%d", uid
);
1310 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1311 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1313 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1314 aml_append(method
, aml_store(aml_name("%s", enabled_field
), is_present
));
1315 if_ctx
= aml_if(aml_equal(is_present
, zero
));
1317 aml_append(if_ctx
, aml_return(aml_int(0x00)));
1319 aml_append(method
, if_ctx
);
1320 else_ctx
= aml_else();
1322 aml_append(else_ctx
, aml_return(aml_int(0x0f)));
1324 aml_append(method
, else_ctx
);
1325 aml_append(dev
, method
);
1327 crs
= aml_resource_template();
1328 aml_append(crs
, aml_io(AML_DECODE16
, io_port
, io_port
, 0x00, 0x08));
1329 aml_append(crs
, aml_irq_no_flags(irq
));
1330 aml_append(dev
, aml_name_decl("_CRS", crs
));
1335 static void build_isa_devices_aml(Aml
*table
)
1337 ISADevice
*fdc
= pc_find_fdc0();
1339 Aml
*scope
= aml_scope("_SB.PCI0.ISA");
1341 aml_append(scope
, build_rtc_device_aml());
1342 aml_append(scope
, build_kbd_device_aml());
1343 aml_append(scope
, build_mouse_device_aml());
1345 aml_append(scope
, build_fdc_device_aml(fdc
));
1347 aml_append(scope
, build_lpt_device_aml());
1348 aml_append(scope
, build_com_device_aml(1));
1349 aml_append(scope
, build_com_device_aml(2));
1351 aml_append(table
, scope
);
1354 static void build_dbg_aml(Aml
*table
)
1359 Aml
*scope
= aml_scope("\\");
1360 Aml
*buf
= aml_local(0);
1361 Aml
*len
= aml_local(1);
1362 Aml
*idx
= aml_local(2);
1365 aml_operation_region("DBG", AML_SYSTEM_IO
, aml_int(0x0402), 0x01));
1366 field
= aml_field("DBG", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1367 aml_append(field
, aml_named_field("DBGB", 8));
1368 aml_append(scope
, field
);
1370 method
= aml_method("DBUG", 1, AML_NOTSERIALIZED
);
1372 aml_append(method
, aml_to_hexstring(aml_arg(0), buf
));
1373 aml_append(method
, aml_to_buffer(buf
, buf
));
1374 aml_append(method
, aml_subtract(aml_sizeof(buf
), aml_int(1), len
));
1375 aml_append(method
, aml_store(aml_int(0), idx
));
1377 while_ctx
= aml_while(aml_lless(idx
, len
));
1378 aml_append(while_ctx
,
1379 aml_store(aml_derefof(aml_index(buf
, idx
)), aml_name("DBGB")));
1380 aml_append(while_ctx
, aml_increment(idx
));
1381 aml_append(method
, while_ctx
);
1383 aml_append(method
, aml_store(aml_int(0x0A), aml_name("DBGB")));
1384 aml_append(scope
, method
);
1386 aml_append(table
, scope
);
1389 static Aml
*build_link_dev(const char *name
, uint8_t uid
, Aml
*reg
)
1394 uint32_t irqs
[] = {5, 10, 11};
1396 dev
= aml_device("%s", name
);
1397 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1398 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1400 crs
= aml_resource_template();
1401 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1402 AML_SHARED
, irqs
, ARRAY_SIZE(irqs
)));
1403 aml_append(dev
, aml_name_decl("_PRS", crs
));
1405 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1406 aml_append(method
, aml_return(aml_call1("IQST", reg
)));
1407 aml_append(dev
, method
);
1409 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1410 aml_append(method
, aml_or(reg
, aml_int(0x80), reg
));
1411 aml_append(dev
, method
);
1413 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1414 aml_append(method
, aml_return(aml_call1("IQCR", reg
)));
1415 aml_append(dev
, method
);
1417 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1418 aml_append(method
, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1419 aml_append(method
, aml_store(aml_name("PRRI"), reg
));
1420 aml_append(dev
, method
);
1425 static Aml
*build_gsi_link_dev(const char *name
, uint8_t uid
, uint8_t gsi
)
1432 dev
= aml_device("%s", name
);
1433 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1434 aml_append(dev
, aml_name_decl("_UID", aml_int(uid
)));
1436 crs
= aml_resource_template();
1438 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
, AML_ACTIVE_HIGH
,
1439 AML_SHARED
, &irqs
, 1));
1440 aml_append(dev
, aml_name_decl("_PRS", crs
));
1442 aml_append(dev
, aml_name_decl("_CRS", crs
));
1445 * _DIS can be no-op because the interrupt cannot be disabled.
1447 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1448 aml_append(dev
, method
);
1450 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1451 aml_append(dev
, method
);
1456 /* _CRS method - get current settings */
1457 static Aml
*build_iqcr_method(bool is_piix4
)
1461 Aml
*method
= aml_method("IQCR", 1, AML_SERIALIZED
);
1462 Aml
*crs
= aml_resource_template();
1465 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1466 AML_ACTIVE_HIGH
, AML_SHARED
, &irqs
, 1));
1467 aml_append(method
, aml_name_decl("PRR0", crs
));
1470 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1473 if_ctx
= aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1474 aml_append(if_ctx
, aml_store(aml_arg(0), aml_name("PRRI")));
1475 aml_append(method
, if_ctx
);
1478 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL
),
1482 aml_append(method
, aml_return(aml_name("PRR0")));
1486 /* _STA method - get status */
1487 static Aml
*build_irq_status_method(void)
1490 Aml
*method
= aml_method("IQST", 1, AML_NOTSERIALIZED
);
1492 if_ctx
= aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL
));
1493 aml_append(if_ctx
, aml_return(aml_int(0x09)));
1494 aml_append(method
, if_ctx
);
1495 aml_append(method
, aml_return(aml_int(0x0B)));
1499 static void build_piix4_pci0_int(Aml
*table
)
1506 Aml
*sb_scope
= aml_scope("_SB");
1507 Aml
*pci0_scope
= aml_scope("PCI0");
1509 aml_append(pci0_scope
, build_prt(true));
1510 aml_append(sb_scope
, pci0_scope
);
1512 field
= aml_field("PCI0.ISA.P40C", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1513 aml_append(field
, aml_named_field("PRQ0", 8));
1514 aml_append(field
, aml_named_field("PRQ1", 8));
1515 aml_append(field
, aml_named_field("PRQ2", 8));
1516 aml_append(field
, aml_named_field("PRQ3", 8));
1517 aml_append(sb_scope
, field
);
1519 aml_append(sb_scope
, build_irq_status_method());
1520 aml_append(sb_scope
, build_iqcr_method(true));
1522 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1523 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1524 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1525 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1527 dev
= aml_device("LNKS");
1529 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1530 aml_append(dev
, aml_name_decl("_UID", aml_int(4)));
1532 crs
= aml_resource_template();
1534 aml_append(crs
, aml_interrupt(AML_CONSUMER
, AML_LEVEL
,
1535 AML_ACTIVE_HIGH
, AML_SHARED
,
1537 aml_append(dev
, aml_name_decl("_PRS", crs
));
1539 /* The SCI cannot be disabled and is always attached to GSI 9,
1540 * so these are no-ops. We only need this link to override the
1541 * polarity to active high and match the content of the MADT.
1543 method
= aml_method("_STA", 0, AML_NOTSERIALIZED
);
1544 aml_append(method
, aml_return(aml_int(0x0b)));
1545 aml_append(dev
, method
);
1547 method
= aml_method("_DIS", 0, AML_NOTSERIALIZED
);
1548 aml_append(dev
, method
);
1550 method
= aml_method("_CRS", 0, AML_NOTSERIALIZED
);
1551 aml_append(method
, aml_return(aml_name("_PRS")));
1552 aml_append(dev
, method
);
1554 method
= aml_method("_SRS", 1, AML_NOTSERIALIZED
);
1555 aml_append(dev
, method
);
1557 aml_append(sb_scope
, dev
);
1559 aml_append(table
, sb_scope
);
1562 static void append_q35_prt_entry(Aml
*ctx
, uint32_t nr
, const char *name
)
1567 char base
= name
[3] < 'E' ? 'A' : 'E';
1568 char *s
= g_strdup(name
);
1569 Aml
*a_nr
= aml_int((nr
<< 16) | 0xffff);
1571 assert(strlen(s
) == 4);
1573 head
= name
[3] - base
;
1574 for (i
= 0; i
< 4; i
++) {
1578 s
[3] = base
+ head
+ i
;
1579 pkg
= aml_package(4);
1580 aml_append(pkg
, a_nr
);
1581 aml_append(pkg
, aml_int(i
));
1582 aml_append(pkg
, aml_name("%s", s
));
1583 aml_append(pkg
, aml_int(0));
1584 aml_append(ctx
, pkg
);
1589 static Aml
*build_q35_routing_table(const char *str
)
1593 char *name
= g_strdup_printf("%s ", str
);
1595 pkg
= aml_package(128);
1596 for (i
= 0; i
< 0x18; i
++) {
1597 name
[3] = 'E' + (i
& 0x3);
1598 append_q35_prt_entry(pkg
, i
, name
);
1602 append_q35_prt_entry(pkg
, 0x18, name
);
1604 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1605 for (i
= 0x0019; i
< 0x1e; i
++) {
1607 append_q35_prt_entry(pkg
, i
, name
);
1610 /* PCIe->PCI bridge. use PIRQ[E-H] */
1612 append_q35_prt_entry(pkg
, 0x1e, name
);
1614 append_q35_prt_entry(pkg
, 0x1f, name
);
1620 static void build_q35_pci0_int(Aml
*table
)
1624 Aml
*sb_scope
= aml_scope("_SB");
1625 Aml
*pci0_scope
= aml_scope("PCI0");
1627 /* Zero => PIC mode, One => APIC Mode */
1628 aml_append(table
, aml_name_decl("PICF", aml_int(0)));
1629 method
= aml_method("_PIC", 1, AML_NOTSERIALIZED
);
1631 aml_append(method
, aml_store(aml_arg(0), aml_name("PICF")));
1633 aml_append(table
, method
);
1635 aml_append(pci0_scope
,
1636 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1637 aml_append(pci0_scope
,
1638 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1640 method
= aml_method("_PRT", 0, AML_NOTSERIALIZED
);
1645 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1647 /* Note: we provide the same info as the PCI routing
1648 table of the Bochs BIOS */
1649 if_ctx
= aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1650 aml_append(if_ctx
, aml_return(aml_name("PRTP")));
1651 aml_append(method
, if_ctx
);
1652 else_ctx
= aml_else();
1653 aml_append(else_ctx
, aml_return(aml_name("PRTA")));
1654 aml_append(method
, else_ctx
);
1656 aml_append(pci0_scope
, method
);
1657 aml_append(sb_scope
, pci0_scope
);
1659 field
= aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1660 aml_append(field
, aml_named_field("PRQA", 8));
1661 aml_append(field
, aml_named_field("PRQB", 8));
1662 aml_append(field
, aml_named_field("PRQC", 8));
1663 aml_append(field
, aml_named_field("PRQD", 8));
1664 aml_append(field
, aml_reserved_field(0x20));
1665 aml_append(field
, aml_named_field("PRQE", 8));
1666 aml_append(field
, aml_named_field("PRQF", 8));
1667 aml_append(field
, aml_named_field("PRQG", 8));
1668 aml_append(field
, aml_named_field("PRQH", 8));
1669 aml_append(sb_scope
, field
);
1671 aml_append(sb_scope
, build_irq_status_method());
1672 aml_append(sb_scope
, build_iqcr_method(false));
1674 aml_append(sb_scope
, build_link_dev("LNKA", 0, aml_name("PRQA")));
1675 aml_append(sb_scope
, build_link_dev("LNKB", 1, aml_name("PRQB")));
1676 aml_append(sb_scope
, build_link_dev("LNKC", 2, aml_name("PRQC")));
1677 aml_append(sb_scope
, build_link_dev("LNKD", 3, aml_name("PRQD")));
1678 aml_append(sb_scope
, build_link_dev("LNKE", 4, aml_name("PRQE")));
1679 aml_append(sb_scope
, build_link_dev("LNKF", 5, aml_name("PRQF")));
1680 aml_append(sb_scope
, build_link_dev("LNKG", 6, aml_name("PRQG")));
1681 aml_append(sb_scope
, build_link_dev("LNKH", 7, aml_name("PRQH")));
1683 aml_append(sb_scope
, build_gsi_link_dev("GSIA", 0x10, 0x10));
1684 aml_append(sb_scope
, build_gsi_link_dev("GSIB", 0x11, 0x11));
1685 aml_append(sb_scope
, build_gsi_link_dev("GSIC", 0x12, 0x12));
1686 aml_append(sb_scope
, build_gsi_link_dev("GSID", 0x13, 0x13));
1687 aml_append(sb_scope
, build_gsi_link_dev("GSIE", 0x14, 0x14));
1688 aml_append(sb_scope
, build_gsi_link_dev("GSIF", 0x15, 0x15));
1689 aml_append(sb_scope
, build_gsi_link_dev("GSIG", 0x16, 0x16));
1690 aml_append(sb_scope
, build_gsi_link_dev("GSIH", 0x17, 0x17));
1692 aml_append(table
, sb_scope
);
1695 static void build_q35_isa_bridge(Aml
*table
)
1701 scope
= aml_scope("_SB.PCI0");
1702 dev
= aml_device("ISA");
1703 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x001F0000)));
1705 /* ICH9 PCI to ISA irq remapping */
1706 aml_append(dev
, aml_operation_region("PIRQ", AML_PCI_CONFIG
,
1707 aml_int(0x60), 0x0C));
1709 aml_append(dev
, aml_operation_region("LPCD", AML_PCI_CONFIG
,
1710 aml_int(0x80), 0x02));
1711 field
= aml_field("LPCD", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1712 aml_append(field
, aml_named_field("COMA", 3));
1713 aml_append(field
, aml_reserved_field(1));
1714 aml_append(field
, aml_named_field("COMB", 3));
1715 aml_append(field
, aml_reserved_field(1));
1716 aml_append(field
, aml_named_field("LPTD", 2));
1717 aml_append(dev
, field
);
1719 aml_append(dev
, aml_operation_region("LPCE", AML_PCI_CONFIG
,
1720 aml_int(0x82), 0x02));
1722 field
= aml_field("LPCE", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1723 aml_append(field
, aml_named_field("CAEN", 1));
1724 aml_append(field
, aml_named_field("CBEN", 1));
1725 aml_append(field
, aml_named_field("LPEN", 1));
1726 aml_append(dev
, field
);
1728 aml_append(scope
, dev
);
1729 aml_append(table
, scope
);
1732 static void build_piix4_pm(Aml
*table
)
1737 scope
= aml_scope("_SB.PCI0");
1738 dev
= aml_device("PX13");
1739 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010003)));
1741 aml_append(dev
, aml_operation_region("P13C", AML_PCI_CONFIG
,
1742 aml_int(0x00), 0xff));
1743 aml_append(scope
, dev
);
1744 aml_append(table
, scope
);
1747 static void build_piix4_isa_bridge(Aml
*table
)
1753 scope
= aml_scope("_SB.PCI0");
1754 dev
= aml_device("ISA");
1755 aml_append(dev
, aml_name_decl("_ADR", aml_int(0x00010000)));
1757 /* PIIX PCI to ISA irq remapping */
1758 aml_append(dev
, aml_operation_region("P40C", AML_PCI_CONFIG
,
1759 aml_int(0x60), 0x04));
1761 field
= aml_field("^PX13.P13C", AML_ANY_ACC
, AML_NOLOCK
, AML_PRESERVE
);
1762 /* Offset(0x5f),, 7, */
1763 aml_append(field
, aml_reserved_field(0x2f8));
1764 aml_append(field
, aml_reserved_field(7));
1765 aml_append(field
, aml_named_field("LPEN", 1));
1766 /* Offset(0x67),, 3, */
1767 aml_append(field
, aml_reserved_field(0x38));
1768 aml_append(field
, aml_reserved_field(3));
1769 aml_append(field
, aml_named_field("CAEN", 1));
1770 aml_append(field
, aml_reserved_field(3));
1771 aml_append(field
, aml_named_field("CBEN", 1));
1772 aml_append(dev
, field
);
1774 aml_append(scope
, dev
);
1775 aml_append(table
, scope
);
1778 static void build_piix4_pci_hotplug(Aml
*table
)
1784 scope
= aml_scope("_SB.PCI0");
1787 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x08));
1788 field
= aml_field("PCST", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1789 aml_append(field
, aml_named_field("PCIU", 32));
1790 aml_append(field
, aml_named_field("PCID", 32));
1791 aml_append(scope
, field
);
1794 aml_operation_region("SEJ", AML_SYSTEM_IO
, aml_int(0xae08), 0x04));
1795 field
= aml_field("SEJ", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1796 aml_append(field
, aml_named_field("B0EJ", 32));
1797 aml_append(scope
, field
);
1800 aml_operation_region("BNMR", AML_SYSTEM_IO
, aml_int(0xae10), 0x04));
1801 field
= aml_field("BNMR", AML_DWORD_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1802 aml_append(field
, aml_named_field("BNUM", 32));
1803 aml_append(scope
, field
);
1805 aml_append(scope
, aml_mutex("BLCK", 0));
1807 method
= aml_method("PCEJ", 2, AML_NOTSERIALIZED
);
1808 aml_append(method
, aml_acquire(aml_name("BLCK"), 0xFFFF));
1809 aml_append(method
, aml_store(aml_arg(0), aml_name("BNUM")));
1811 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1812 aml_append(method
, aml_release(aml_name("BLCK")));
1813 aml_append(method
, aml_return(aml_int(0)));
1814 aml_append(scope
, method
);
1816 aml_append(table
, scope
);
1819 static Aml
*build_q35_osc_method(void)
1825 Aml
*a_cwd1
= aml_name("CDW1");
1826 Aml
*a_ctrl
= aml_name("CTRL");
1828 method
= aml_method("_OSC", 4, AML_NOTSERIALIZED
);
1829 aml_append(method
, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1831 if_ctx
= aml_if(aml_equal(
1832 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1833 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1834 aml_append(if_ctx
, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1836 aml_append(if_ctx
, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1837 aml_append(if_ctx
, aml_store(aml_name("CDW3"), a_ctrl
));
1840 * Always allow native PME, AER (no dependencies)
1841 * Never allow SHPC (no SHPC controller in this system)
1843 aml_append(if_ctx
, aml_and(a_ctrl
, aml_int(0x1D), a_ctrl
));
1845 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1846 /* Unknown revision */
1847 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x08), a_cwd1
));
1848 aml_append(if_ctx
, if_ctx2
);
1850 if_ctx2
= aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl
)));
1851 /* Capabilities bits were masked */
1852 aml_append(if_ctx2
, aml_or(a_cwd1
, aml_int(0x10), a_cwd1
));
1853 aml_append(if_ctx
, if_ctx2
);
1855 /* Update DWORD3 in the buffer */
1856 aml_append(if_ctx
, aml_store(a_ctrl
, aml_name("CDW3")));
1857 aml_append(method
, if_ctx
);
1859 else_ctx
= aml_else();
1860 /* Unrecognized UUID */
1861 aml_append(else_ctx
, aml_or(a_cwd1
, aml_int(4), a_cwd1
));
1862 aml_append(method
, else_ctx
);
1864 aml_append(method
, aml_return(aml_arg(3)));
1869 build_dsdt(GArray
*table_data
, BIOSLinker
*linker
,
1870 AcpiPmInfo
*pm
, AcpiMiscInfo
*misc
,
1871 PcPciInfo
*pci
, MachineState
*machine
)
1873 CrsRangeEntry
*entry
;
1874 Aml
*dsdt
, *sb_scope
, *scope
, *dev
, *method
, *field
, *pkg
, *crs
;
1875 GPtrArray
*mem_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
1876 GPtrArray
*io_ranges
= g_ptr_array_new_with_free_func(crs_range_free
);
1877 PCMachineState
*pcms
= PC_MACHINE(machine
);
1878 uint32_t nr_mem
= machine
->ram_slots
;
1879 int root_bus_limit
= 0xFF;
1883 dsdt
= init_aml_allocator();
1885 /* Reserve space for header */
1886 acpi_data_push(dsdt
->buf
, sizeof(AcpiTableHeader
));
1888 build_dbg_aml(dsdt
);
1889 if (misc
->is_piix4
) {
1890 sb_scope
= aml_scope("_SB");
1891 dev
= aml_device("PCI0");
1892 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1893 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1894 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1895 aml_append(sb_scope
, dev
);
1896 aml_append(dsdt
, sb_scope
);
1898 build_hpet_aml(dsdt
);
1899 build_piix4_pm(dsdt
);
1900 build_piix4_isa_bridge(dsdt
);
1901 build_isa_devices_aml(dsdt
);
1902 build_piix4_pci_hotplug(dsdt
);
1903 build_piix4_pci0_int(dsdt
);
1905 sb_scope
= aml_scope("_SB");
1906 aml_append(sb_scope
,
1907 aml_operation_region("PCST", AML_SYSTEM_IO
, aml_int(0xae00), 0x0c));
1908 aml_append(sb_scope
,
1909 aml_operation_region("PCSB", AML_SYSTEM_IO
, aml_int(0xae0c), 0x01));
1910 field
= aml_field("PCSB", AML_ANY_ACC
, AML_NOLOCK
, AML_WRITE_AS_ZEROS
);
1911 aml_append(field
, aml_named_field("PCIB", 8));
1912 aml_append(sb_scope
, field
);
1913 aml_append(dsdt
, sb_scope
);
1915 sb_scope
= aml_scope("_SB");
1916 dev
= aml_device("PCI0");
1917 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1918 aml_append(dev
, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1919 aml_append(dev
, aml_name_decl("_ADR", aml_int(0)));
1920 aml_append(dev
, aml_name_decl("_UID", aml_int(1)));
1921 aml_append(dev
, aml_name_decl("SUPP", aml_int(0)));
1922 aml_append(dev
, aml_name_decl("CTRL", aml_int(0)));
1923 aml_append(dev
, build_q35_osc_method());
1924 aml_append(sb_scope
, dev
);
1925 aml_append(dsdt
, sb_scope
);
1927 build_hpet_aml(dsdt
);
1928 build_q35_isa_bridge(dsdt
);
1929 build_isa_devices_aml(dsdt
);
1930 build_q35_pci0_int(dsdt
);
1933 build_legacy_cpu_hotplug_aml(dsdt
, machine
, pm
->cpu_hp_io_base
);
1934 build_memory_hotplug_aml(dsdt
, nr_mem
, pm
->mem_hp_io_base
,
1937 scope
= aml_scope("_GPE");
1939 aml_append(scope
, aml_name_decl("_HID", aml_string("ACPI0006")));
1941 if (misc
->is_piix4
) {
1942 method
= aml_method("_E01", 0, AML_NOTSERIALIZED
);
1944 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1945 aml_append(method
, aml_call0("\\_SB.PCI0.PCNT"));
1946 aml_append(method
, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1947 aml_append(scope
, method
);
1950 method
= aml_method("_E03", 0, AML_NOTSERIALIZED
);
1951 aml_append(method
, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH
));
1952 aml_append(scope
, method
);
1954 aml_append(dsdt
, scope
);
1956 bus
= PC_MACHINE(machine
)->bus
;
1958 QLIST_FOREACH(bus
, &bus
->child
, sibling
) {
1959 uint8_t bus_num
= pci_bus_num(bus
);
1960 uint8_t numa_node
= pci_bus_numa_node(bus
);
1962 /* look only for expander root buses */
1963 if (!pci_bus_is_root(bus
)) {
1967 if (bus_num
< root_bus_limit
) {
1968 root_bus_limit
= bus_num
- 1;
1971 scope
= aml_scope("\\_SB");
1972 dev
= aml_device("PC%.02X", bus_num
);
1973 aml_append(dev
, aml_name_decl("_UID", aml_int(bus_num
)));
1974 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1975 aml_append(dev
, aml_name_decl("_BBN", aml_int(bus_num
)));
1977 if (numa_node
!= NUMA_NODE_UNASSIGNED
) {
1978 aml_append(dev
, aml_name_decl("_PXM", aml_int(numa_node
)));
1981 aml_append(dev
, build_prt(false));
1982 crs
= build_crs(PCI_HOST_BRIDGE(BUS(bus
)->parent
),
1983 io_ranges
, mem_ranges
);
1984 aml_append(dev
, aml_name_decl("_CRS", crs
));
1985 aml_append(scope
, dev
);
1986 aml_append(dsdt
, scope
);
1990 scope
= aml_scope("\\_SB.PCI0");
1991 /* build PCI0._CRS */
1992 crs
= aml_resource_template();
1994 aml_word_bus_number(AML_MIN_FIXED
, AML_MAX_FIXED
, AML_POS_DECODE
,
1995 0x0000, 0x0, root_bus_limit
,
1996 0x0000, root_bus_limit
+ 1));
1997 aml_append(crs
, aml_io(AML_DECODE16
, 0x0CF8, 0x0CF8, 0x01, 0x08));
2000 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2001 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2002 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2004 crs_replace_with_free_ranges(io_ranges
, 0x0D00, 0xFFFF);
2005 for (i
= 0; i
< io_ranges
->len
; i
++) {
2006 entry
= g_ptr_array_index(io_ranges
, i
);
2008 aml_word_io(AML_MIN_FIXED
, AML_MAX_FIXED
,
2009 AML_POS_DECODE
, AML_ENTIRE_RANGE
,
2010 0x0000, entry
->base
, entry
->limit
,
2011 0x0000, entry
->limit
- entry
->base
+ 1));
2015 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2016 AML_CACHEABLE
, AML_READ_WRITE
,
2017 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2019 crs_replace_with_free_ranges(mem_ranges
, pci
->w32
.begin
, pci
->w32
.end
- 1);
2020 for (i
= 0; i
< mem_ranges
->len
; i
++) {
2021 entry
= g_ptr_array_index(mem_ranges
, i
);
2023 aml_dword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2024 AML_NON_CACHEABLE
, AML_READ_WRITE
,
2025 0, entry
->base
, entry
->limit
,
2026 0, entry
->limit
- entry
->base
+ 1));
2029 if (pci
->w64
.begin
) {
2031 aml_qword_memory(AML_POS_DECODE
, AML_MIN_FIXED
, AML_MAX_FIXED
,
2032 AML_CACHEABLE
, AML_READ_WRITE
,
2033 0, pci
->w64
.begin
, pci
->w64
.end
- 1, 0,
2034 pci
->w64
.end
- pci
->w64
.begin
));
2037 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2038 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2039 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2041 aml_append(scope
, aml_name_decl("_CRS", crs
));
2043 /* reserve GPE0 block resources */
2044 dev
= aml_device("GPE0");
2045 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2046 aml_append(dev
, aml_name_decl("_UID", aml_string("GPE0 resources")));
2047 /* device present, functioning, decoding, not shown in UI */
2048 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2049 crs
= aml_resource_template();
2051 aml_io(AML_DECODE16
, pm
->gpe0_blk
, pm
->gpe0_blk
, 1, pm
->gpe0_blk_len
)
2053 aml_append(dev
, aml_name_decl("_CRS", crs
));
2054 aml_append(scope
, dev
);
2056 g_ptr_array_free(io_ranges
, true);
2057 g_ptr_array_free(mem_ranges
, true);
2059 /* reserve PCIHP resources */
2060 if (pm
->pcihp_io_len
) {
2061 dev
= aml_device("PHPR");
2062 aml_append(dev
, aml_name_decl("_HID", aml_string("PNP0A06")));
2064 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2065 /* device present, functioning, decoding, not shown in UI */
2066 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2067 crs
= aml_resource_template();
2069 aml_io(AML_DECODE16
, pm
->pcihp_io_base
, pm
->pcihp_io_base
, 1,
2072 aml_append(dev
, aml_name_decl("_CRS", crs
));
2073 aml_append(scope
, dev
);
2075 aml_append(dsdt
, scope
);
2077 /* create S3_ / S4_ / S5_ packages if necessary */
2078 scope
= aml_scope("\\");
2079 if (!pm
->s3_disabled
) {
2080 pkg
= aml_package(4);
2081 aml_append(pkg
, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2082 aml_append(pkg
, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2083 aml_append(pkg
, aml_int(0)); /* reserved */
2084 aml_append(pkg
, aml_int(0)); /* reserved */
2085 aml_append(scope
, aml_name_decl("_S3", pkg
));
2088 if (!pm
->s4_disabled
) {
2089 pkg
= aml_package(4);
2090 aml_append(pkg
, aml_int(pm
->s4_val
)); /* PM1a_CNT.SLP_TYP */
2091 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2092 aml_append(pkg
, aml_int(pm
->s4_val
));
2093 aml_append(pkg
, aml_int(0)); /* reserved */
2094 aml_append(pkg
, aml_int(0)); /* reserved */
2095 aml_append(scope
, aml_name_decl("_S4", pkg
));
2098 pkg
= aml_package(4);
2099 aml_append(pkg
, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2100 aml_append(pkg
, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2101 aml_append(pkg
, aml_int(0)); /* reserved */
2102 aml_append(pkg
, aml_int(0)); /* reserved */
2103 aml_append(scope
, aml_name_decl("_S5", pkg
));
2104 aml_append(dsdt
, scope
);
2106 /* create fw_cfg node, unconditionally */
2108 /* when using port i/o, the 8-bit data register *always* overlaps
2109 * with half of the 16-bit control register. Hence, the total size
2110 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2111 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2112 uint8_t io_size
= object_property_get_bool(OBJECT(pcms
->fw_cfg
),
2113 "dma_enabled", NULL
) ?
2114 ROUND_UP(FW_CFG_CTL_SIZE
, 4) + sizeof(dma_addr_t
) :
2117 scope
= aml_scope("\\_SB.PCI0");
2118 dev
= aml_device("FWCF");
2120 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0002")));
2122 /* device present, functioning, decoding, not shown in UI */
2123 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2125 crs
= aml_resource_template();
2127 aml_io(AML_DECODE16
, FW_CFG_IO_BASE
, FW_CFG_IO_BASE
, 0x01, io_size
)
2129 aml_append(dev
, aml_name_decl("_CRS", crs
));
2131 aml_append(scope
, dev
);
2132 aml_append(dsdt
, scope
);
2135 if (misc
->applesmc_io_base
) {
2136 scope
= aml_scope("\\_SB.PCI0.ISA");
2137 dev
= aml_device("SMC");
2139 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("APP0001")));
2140 /* device present, functioning, decoding, not shown in UI */
2141 aml_append(dev
, aml_name_decl("_STA", aml_int(0xB)));
2143 crs
= aml_resource_template();
2145 aml_io(AML_DECODE16
, misc
->applesmc_io_base
, misc
->applesmc_io_base
,
2146 0x01, APPLESMC_MAX_DATA_LENGTH
)
2148 aml_append(crs
, aml_irq_no_flags(6));
2149 aml_append(dev
, aml_name_decl("_CRS", crs
));
2151 aml_append(scope
, dev
);
2152 aml_append(dsdt
, scope
);
2155 if (misc
->pvpanic_port
) {
2156 scope
= aml_scope("\\_SB.PCI0.ISA");
2158 dev
= aml_device("PEVT");
2159 aml_append(dev
, aml_name_decl("_HID", aml_string("QEMU0001")));
2161 crs
= aml_resource_template();
2163 aml_io(AML_DECODE16
, misc
->pvpanic_port
, misc
->pvpanic_port
, 1, 1)
2165 aml_append(dev
, aml_name_decl("_CRS", crs
));
2167 aml_append(dev
, aml_operation_region("PEOR", AML_SYSTEM_IO
,
2168 aml_int(misc
->pvpanic_port
), 1));
2169 field
= aml_field("PEOR", AML_BYTE_ACC
, AML_NOLOCK
, AML_PRESERVE
);
2170 aml_append(field
, aml_named_field("PEPT", 8));
2171 aml_append(dev
, field
);
2173 /* device present, functioning, decoding, shown in UI */
2174 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2176 method
= aml_method("RDPT", 0, AML_NOTSERIALIZED
);
2177 aml_append(method
, aml_store(aml_name("PEPT"), aml_local(0)));
2178 aml_append(method
, aml_return(aml_local(0)));
2179 aml_append(dev
, method
);
2181 method
= aml_method("WRPT", 1, AML_NOTSERIALIZED
);
2182 aml_append(method
, aml_store(aml_arg(0), aml_name("PEPT")));
2183 aml_append(dev
, method
);
2185 aml_append(scope
, dev
);
2186 aml_append(dsdt
, scope
);
2189 sb_scope
= aml_scope("\\_SB");
2191 build_memory_devices(sb_scope
, nr_mem
, pm
->mem_hp_io_base
,
2198 pci_host
= acpi_get_i386_pci_host();
2200 bus
= PCI_HOST_BRIDGE(pci_host
)->bus
;
2204 Aml
*scope
= aml_scope("PCI0");
2205 /* Scan all PCI buses. Generate tables to support hotplug. */
2206 build_append_pci_bus_devices(scope
, bus
, pm
->pcihp_bridge_en
);
2208 if (misc
->tpm_version
!= TPM_VERSION_UNSPEC
) {
2209 dev
= aml_device("ISA.TPM");
2210 aml_append(dev
, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2211 aml_append(dev
, aml_name_decl("_STA", aml_int(0xF)));
2212 crs
= aml_resource_template();
2213 aml_append(crs
, aml_memory32_fixed(TPM_TIS_ADDR_BASE
,
2214 TPM_TIS_ADDR_SIZE
, AML_READ_WRITE
));
2216 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2217 Rewrite to take IRQ from TPM device model and
2218 fix default IRQ value there to use some unused IRQ
2220 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2221 aml_append(dev
, aml_name_decl("_CRS", crs
));
2222 aml_append(scope
, dev
);
2225 aml_append(sb_scope
, scope
);
2228 aml_append(dsdt
, sb_scope
);
2231 /* copy AML table into ACPI tables blob and patch header there */
2232 g_array_append_vals(table_data
, dsdt
->buf
->data
, dsdt
->buf
->len
);
2233 build_header(linker
, table_data
,
2234 (void *)(table_data
->data
+ table_data
->len
- dsdt
->buf
->len
),
2235 "DSDT", dsdt
->buf
->len
, 1, NULL
, NULL
);
2236 free_aml_allocator();
2240 build_hpet(GArray
*table_data
, BIOSLinker
*linker
)
2244 hpet
= acpi_data_push(table_data
, sizeof(*hpet
));
2245 /* Note timer_block_id value must be kept in sync with value advertised by
2248 hpet
->timer_block_id
= cpu_to_le32(0x8086a201);
2249 hpet
->addr
.address
= cpu_to_le64(HPET_BASE
);
2250 build_header(linker
, table_data
,
2251 (void *)hpet
, "HPET", sizeof(*hpet
), 1, NULL
, NULL
);
2255 build_tpm_tcpa(GArray
*table_data
, BIOSLinker
*linker
, GArray
*tcpalog
)
2257 Acpi20Tcpa
*tcpa
= acpi_data_push(table_data
, sizeof *tcpa
);
2258 unsigned log_addr_size
= sizeof(tcpa
->log_area_start_address
);
2259 unsigned log_addr_offset
=
2260 (char *)&tcpa
->log_area_start_address
- table_data
->data
;
2262 tcpa
->platform_class
= cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT
);
2263 tcpa
->log_area_minimum_length
= cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE
);
2264 acpi_data_push(tcpalog
, le32_to_cpu(tcpa
->log_area_minimum_length
));
2266 bios_linker_loader_alloc(linker
, ACPI_BUILD_TPMLOG_FILE
, tcpalog
, 1,
2267 false /* high memory */);
2269 /* log area start address to be filled by Guest linker */
2270 bios_linker_loader_add_pointer(linker
,
2271 ACPI_BUILD_TABLE_FILE
, log_addr_offset
, log_addr_size
,
2272 ACPI_BUILD_TPMLOG_FILE
, 0);
2274 build_header(linker
, table_data
,
2275 (void *)tcpa
, "TCPA", sizeof(*tcpa
), 2, NULL
, NULL
);
2279 build_tpm2(GArray
*table_data
, BIOSLinker
*linker
)
2281 Acpi20TPM2
*tpm2_ptr
;
2283 tpm2_ptr
= acpi_data_push(table_data
, sizeof *tpm2_ptr
);
2285 tpm2_ptr
->platform_class
= cpu_to_le16(TPM2_ACPI_CLASS_CLIENT
);
2286 tpm2_ptr
->control_area_address
= cpu_to_le64(0);
2287 tpm2_ptr
->start_method
= cpu_to_le32(TPM2_START_METHOD_MMIO
);
2289 build_header(linker
, table_data
,
2290 (void *)tpm2_ptr
, "TPM2", sizeof(*tpm2_ptr
), 4, NULL
, NULL
);
2294 build_srat(GArray
*table_data
, BIOSLinker
*linker
, MachineState
*machine
)
2296 AcpiSystemResourceAffinityTable
*srat
;
2297 AcpiSratProcessorAffinity
*core
;
2298 AcpiSratMemoryAffinity
*numamem
;
2302 int srat_start
, numa_start
, slots
;
2303 uint64_t mem_len
, mem_base
, next_base
;
2304 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
2305 CPUArchIdList
*apic_ids
= mc
->possible_cpu_arch_ids(machine
);
2306 PCMachineState
*pcms
= PC_MACHINE(machine
);
2307 ram_addr_t hotplugabble_address_space_size
=
2308 object_property_get_int(OBJECT(pcms
), PC_MACHINE_MEMHP_REGION_SIZE
,
2311 srat_start
= table_data
->len
;
2313 srat
= acpi_data_push(table_data
, sizeof *srat
);
2314 srat
->reserved1
= cpu_to_le32(1);
2316 for (i
= 0; i
< apic_ids
->len
; i
++) {
2317 int apic_id
= apic_ids
->cpus
[i
].arch_id
;
2319 core
= acpi_data_push(table_data
, sizeof *core
);
2320 core
->type
= ACPI_SRAT_PROCESSOR_APIC
;
2321 core
->length
= sizeof(*core
);
2322 core
->local_apic_id
= apic_id
;
2323 curnode
= pcms
->node_cpu
[apic_id
];
2324 core
->proximity_lo
= curnode
;
2325 memset(core
->proximity_hi
, 0, 3);
2326 core
->local_sapic_eid
= 0;
2327 core
->flags
= cpu_to_le32(1);
2331 /* the memory map is a bit tricky, it contains at least one hole
2332 * from 640k-1M and possibly another one from 3.5G-4G.
2335 numa_start
= table_data
->len
;
2337 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2338 build_srat_memory(numamem
, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED
);
2339 next_base
= 1024 * 1024;
2340 for (i
= 1; i
< pcms
->numa_nodes
+ 1; ++i
) {
2341 mem_base
= next_base
;
2342 mem_len
= pcms
->node_mem
[i
- 1];
2344 mem_len
-= 1024 * 1024;
2346 next_base
= mem_base
+ mem_len
;
2348 /* Cut out the ACPI_PCI hole */
2349 if (mem_base
<= pcms
->below_4g_mem_size
&&
2350 next_base
> pcms
->below_4g_mem_size
) {
2351 mem_len
-= next_base
- pcms
->below_4g_mem_size
;
2353 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2354 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2355 MEM_AFFINITY_ENABLED
);
2357 mem_base
= 1ULL << 32;
2358 mem_len
= next_base
- pcms
->below_4g_mem_size
;
2359 next_base
+= (1ULL << 32) - pcms
->below_4g_mem_size
;
2361 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2362 build_srat_memory(numamem
, mem_base
, mem_len
, i
- 1,
2363 MEM_AFFINITY_ENABLED
);
2365 slots
= (table_data
->len
- numa_start
) / sizeof *numamem
;
2366 for (; slots
< pcms
->numa_nodes
+ 2; slots
++) {
2367 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2368 build_srat_memory(numamem
, 0, 0, 0, MEM_AFFINITY_NOFLAGS
);
2372 * Entry is required for Windows to enable memory hotplug in OS.
2373 * Memory devices may override proximity set by this entry,
2374 * providing _PXM method if necessary.
2376 if (hotplugabble_address_space_size
) {
2377 numamem
= acpi_data_push(table_data
, sizeof *numamem
);
2378 build_srat_memory(numamem
, pcms
->hotplug_memory
.base
,
2379 hotplugabble_address_space_size
, 0,
2380 MEM_AFFINITY_HOTPLUGGABLE
| MEM_AFFINITY_ENABLED
);
2383 build_header(linker
, table_data
,
2384 (void *)(table_data
->data
+ srat_start
),
2386 table_data
->len
- srat_start
, 1, NULL
, NULL
);
2391 build_mcfg_q35(GArray
*table_data
, BIOSLinker
*linker
, AcpiMcfgInfo
*info
)
2393 AcpiTableMcfg
*mcfg
;
2395 int len
= sizeof(*mcfg
) + 1 * sizeof(mcfg
->allocation
[0]);
2397 mcfg
= acpi_data_push(table_data
, len
);
2398 mcfg
->allocation
[0].address
= cpu_to_le64(info
->mcfg_base
);
2399 /* Only a single allocation so no need to play with segments */
2400 mcfg
->allocation
[0].pci_segment
= cpu_to_le16(0);
2401 mcfg
->allocation
[0].start_bus_number
= 0;
2402 mcfg
->allocation
[0].end_bus_number
= PCIE_MMCFG_BUS(info
->mcfg_size
- 1);
2404 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2405 * To avoid table size changes (which create migration issues),
2406 * always create the table even if there are no allocations,
2407 * but set the signature to a reserved value in this case.
2408 * ACPI spec requires OSPMs to ignore such tables.
2410 if (info
->mcfg_base
== PCIE_BASE_ADDR_UNMAPPED
) {
2411 /* Reserved signature: ignored by OSPM */
2416 build_header(linker
, table_data
, (void *)mcfg
, sig
, len
, 1, NULL
, NULL
);
2420 build_dmar_q35(GArray
*table_data
, BIOSLinker
*linker
)
2422 int dmar_start
= table_data
->len
;
2424 AcpiTableDmar
*dmar
;
2425 AcpiDmarHardwareUnit
*drhd
;
2427 dmar
= acpi_data_push(table_data
, sizeof(*dmar
));
2428 dmar
->host_address_width
= VTD_HOST_ADDRESS_WIDTH
- 1;
2429 dmar
->flags
= 0; /* No intr_remap for now */
2431 /* DMAR Remapping Hardware Unit Definition structure */
2432 drhd
= acpi_data_push(table_data
, sizeof(*drhd
));
2433 drhd
->type
= cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT
);
2434 drhd
->length
= cpu_to_le16(sizeof(*drhd
)); /* No device scope now */
2435 drhd
->flags
= ACPI_DMAR_INCLUDE_PCI_ALL
;
2436 drhd
->pci_segment
= cpu_to_le16(0);
2437 drhd
->address
= cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR
);
2439 build_header(linker
, table_data
, (void *)(table_data
->data
+ dmar_start
),
2440 "DMAR", table_data
->len
- dmar_start
, 1, NULL
, NULL
);
2444 build_rsdp(GArray
*rsdp_table
, BIOSLinker
*linker
, unsigned rsdt_tbl_offset
)
2446 AcpiRsdpDescriptor
*rsdp
= acpi_data_push(rsdp_table
, sizeof *rsdp
);
2447 unsigned rsdt_pa_size
= sizeof(rsdp
->rsdt_physical_address
);
2448 unsigned rsdt_pa_offset
=
2449 (char *)&rsdp
->rsdt_physical_address
- rsdp_table
->data
;
2451 bios_linker_loader_alloc(linker
, ACPI_BUILD_RSDP_FILE
, rsdp_table
, 16,
2452 true /* fseg memory */);
2454 memcpy(&rsdp
->signature
, "RSD PTR ", 8);
2455 memcpy(rsdp
->oem_id
, ACPI_BUILD_APPNAME6
, 6);
2456 /* Address to be filled by Guest linker */
2457 bios_linker_loader_add_pointer(linker
,
2458 ACPI_BUILD_RSDP_FILE
, rsdt_pa_offset
, rsdt_pa_size
,
2459 ACPI_BUILD_TABLE_FILE
, rsdt_tbl_offset
);
2461 /* Checksum to be filled by Guest linker */
2462 bios_linker_loader_add_checksum(linker
, ACPI_BUILD_RSDP_FILE
,
2463 (char *)rsdp
- rsdp_table
->data
, sizeof *rsdp
,
2464 (char *)&rsdp
->checksum
- rsdp_table
->data
);
2470 struct AcpiBuildState
{
2471 /* Copy of table in RAM (for patching). */
2472 MemoryRegion
*table_mr
;
2473 /* Is table patched? */
2476 MemoryRegion
*rsdp_mr
;
2477 MemoryRegion
*linker_mr
;
2480 static bool acpi_get_mcfg(AcpiMcfgInfo
*mcfg
)
2485 pci_host
= acpi_get_i386_pci_host();
2488 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_BASE
, NULL
);
2492 mcfg
->mcfg_base
= qint_get_int(qobject_to_qint(o
));
2495 o
= object_property_get_qobject(pci_host
, PCIE_HOST_MCFG_SIZE
, NULL
);
2497 mcfg
->mcfg_size
= qint_get_int(qobject_to_qint(o
));
2502 static bool acpi_has_iommu(void)
2505 Object
*intel_iommu
;
2507 intel_iommu
= object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE
,
2509 return intel_iommu
&& !ambiguous
;
2513 void acpi_build(AcpiBuildTables
*tables
, MachineState
*machine
)
2515 PCMachineState
*pcms
= PC_MACHINE(machine
);
2516 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2517 GArray
*table_offsets
;
2518 unsigned facs
, dsdt
, rsdt
, fadt
;
2525 GArray
*tables_blob
= tables
->table_data
;
2526 AcpiSlicOem slic_oem
= { .id
= NULL
, .table_id
= NULL
};
2528 acpi_get_pm_info(&pm
);
2529 acpi_get_misc_info(&misc
);
2530 acpi_get_pci_info(&pci
);
2531 acpi_get_slic_oem(&slic_oem
);
2533 table_offsets
= g_array_new(false, true /* clear */,
2535 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2537 bios_linker_loader_alloc(tables
->linker
,
2538 ACPI_BUILD_TABLE_FILE
, tables_blob
,
2539 64 /* Ensure FACS is aligned */,
2540 false /* high memory */);
2543 * FACS is pointed to by FADT.
2544 * We place it first since it's the only table that has alignment
2547 facs
= tables_blob
->len
;
2548 build_facs(tables_blob
, tables
->linker
);
2550 /* DSDT is pointed to by FADT */
2551 dsdt
= tables_blob
->len
;
2552 build_dsdt(tables_blob
, tables
->linker
, &pm
, &misc
, &pci
, machine
);
2554 /* Count the size of the DSDT and SSDT, we will need it for legacy
2555 * sizing of ACPI tables.
2557 aml_len
+= tables_blob
->len
- dsdt
;
2559 /* ACPI tables pointed to by RSDT */
2560 fadt
= tables_blob
->len
;
2561 acpi_add_table(table_offsets
, tables_blob
);
2562 build_fadt(tables_blob
, tables
->linker
, &pm
, facs
, dsdt
,
2563 slic_oem
.id
, slic_oem
.table_id
);
2564 aml_len
+= tables_blob
->len
- fadt
;
2566 acpi_add_table(table_offsets
, tables_blob
);
2567 build_madt(tables_blob
, tables
->linker
, pcms
);
2569 if (misc
.has_hpet
) {
2570 acpi_add_table(table_offsets
, tables_blob
);
2571 build_hpet(tables_blob
, tables
->linker
);
2573 if (misc
.tpm_version
!= TPM_VERSION_UNSPEC
) {
2574 acpi_add_table(table_offsets
, tables_blob
);
2575 build_tpm_tcpa(tables_blob
, tables
->linker
, tables
->tcpalog
);
2577 if (misc
.tpm_version
== TPM_VERSION_2_0
) {
2578 acpi_add_table(table_offsets
, tables_blob
);
2579 build_tpm2(tables_blob
, tables
->linker
);
2582 if (pcms
->numa_nodes
) {
2583 acpi_add_table(table_offsets
, tables_blob
);
2584 build_srat(tables_blob
, tables
->linker
, machine
);
2586 if (acpi_get_mcfg(&mcfg
)) {
2587 acpi_add_table(table_offsets
, tables_blob
);
2588 build_mcfg_q35(tables_blob
, tables
->linker
, &mcfg
);
2590 if (acpi_has_iommu()) {
2591 acpi_add_table(table_offsets
, tables_blob
);
2592 build_dmar_q35(tables_blob
, tables
->linker
);
2594 if (pcms
->acpi_nvdimm_state
.is_enabled
) {
2595 nvdimm_build_acpi(table_offsets
, tables_blob
, tables
->linker
,
2596 pcms
->acpi_nvdimm_state
.dsm_mem
);
2599 /* Add tables supplied by user (if any) */
2600 for (u
= acpi_table_first(); u
; u
= acpi_table_next(u
)) {
2601 unsigned len
= acpi_table_len(u
);
2603 acpi_add_table(table_offsets
, tables_blob
);
2604 g_array_append_vals(tables_blob
, u
, len
);
2607 /* RSDT is pointed to by RSDP */
2608 rsdt
= tables_blob
->len
;
2609 build_rsdt(tables_blob
, tables
->linker
, table_offsets
,
2610 slic_oem
.id
, slic_oem
.table_id
);
2612 /* RSDP is in FSEG memory, so allocate it separately */
2613 build_rsdp(tables
->rsdp
, tables
->linker
, rsdt
);
2615 /* We'll expose it all to Guest so we want to reduce
2616 * chance of size changes.
2618 * We used to align the tables to 4k, but of course this would
2619 * too simple to be enough. 4k turned out to be too small an
2620 * alignment very soon, and in fact it is almost impossible to
2621 * keep the table size stable for all (max_cpus, max_memory_slots)
2622 * combinations. So the table size is always 64k for pc-i440fx-2.1
2623 * and we give an error if the table grows beyond that limit.
2625 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2626 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2627 * than 2.0 and we can always pad the smaller tables with zeros. We can
2628 * then use the exact size of the 2.0 tables.
2630 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2632 if (pcmc
->legacy_acpi_table_size
) {
2633 /* Subtracting aml_len gives the size of fixed tables. Then add the
2634 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2636 int legacy_aml_len
=
2637 pcmc
->legacy_acpi_table_size
+
2638 ACPI_BUILD_LEGACY_CPU_AML_SIZE
* max_cpus
;
2639 int legacy_table_size
=
2640 ROUND_UP(tables_blob
->len
- aml_len
+ legacy_aml_len
,
2641 ACPI_BUILD_ALIGN_SIZE
);
2642 if (tables_blob
->len
> legacy_table_size
) {
2643 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2644 error_report("Warning: migration may not work.");
2646 g_array_set_size(tables_blob
, legacy_table_size
);
2648 /* Make sure we have a buffer in case we need to resize the tables. */
2649 if (tables_blob
->len
> ACPI_BUILD_TABLE_SIZE
/ 2) {
2650 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2651 error_report("Warning: ACPI tables are larger than 64k.");
2652 error_report("Warning: migration may not work.");
2653 error_report("Warning: please remove CPUs, NUMA nodes, "
2654 "memory slots or PCI bridges.");
2656 acpi_align_size(tables_blob
, ACPI_BUILD_TABLE_SIZE
);
2659 acpi_align_size(tables
->linker
->cmd_blob
, ACPI_BUILD_ALIGN_SIZE
);
2661 /* Cleanup memory that's no longer used. */
2662 g_array_free(table_offsets
, true);
2665 static void acpi_ram_update(MemoryRegion
*mr
, GArray
*data
)
2667 uint32_t size
= acpi_data_len(data
);
2669 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2670 memory_region_ram_resize(mr
, size
, &error_abort
);
2672 memcpy(memory_region_get_ram_ptr(mr
), data
->data
, size
);
2673 memory_region_set_dirty(mr
, 0, size
);
2676 static void acpi_build_update(void *build_opaque
)
2678 AcpiBuildState
*build_state
= build_opaque
;
2679 AcpiBuildTables tables
;
2681 /* No state to update or already patched? Nothing to do. */
2682 if (!build_state
|| build_state
->patched
) {
2685 build_state
->patched
= 1;
2687 acpi_build_tables_init(&tables
);
2689 acpi_build(&tables
, MACHINE(qdev_get_machine()));
2691 acpi_ram_update(build_state
->table_mr
, tables
.table_data
);
2693 if (build_state
->rsdp
) {
2694 memcpy(build_state
->rsdp
, tables
.rsdp
->data
, acpi_data_len(tables
.rsdp
));
2696 acpi_ram_update(build_state
->rsdp_mr
, tables
.rsdp
);
2699 acpi_ram_update(build_state
->linker_mr
, tables
.linker
->cmd_blob
);
2700 acpi_build_tables_cleanup(&tables
, true);
2703 static void acpi_build_reset(void *build_opaque
)
2705 AcpiBuildState
*build_state
= build_opaque
;
2706 build_state
->patched
= 0;
2709 static MemoryRegion
*acpi_add_rom_blob(AcpiBuildState
*build_state
,
2710 GArray
*blob
, const char *name
,
2713 return rom_add_blob(name
, blob
->data
, acpi_data_len(blob
), max_size
, -1,
2714 name
, acpi_build_update
, build_state
);
2717 static const VMStateDescription vmstate_acpi_build
= {
2718 .name
= "acpi_build",
2720 .minimum_version_id
= 1,
2721 .fields
= (VMStateField
[]) {
2722 VMSTATE_UINT8(patched
, AcpiBuildState
),
2723 VMSTATE_END_OF_LIST()
2727 void acpi_setup(void)
2729 PCMachineState
*pcms
= PC_MACHINE(qdev_get_machine());
2730 PCMachineClass
*pcmc
= PC_MACHINE_GET_CLASS(pcms
);
2731 AcpiBuildTables tables
;
2732 AcpiBuildState
*build_state
;
2734 if (!pcms
->fw_cfg
) {
2735 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2739 if (!pcmc
->has_acpi_build
) {
2740 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2744 if (!acpi_enabled
) {
2745 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2749 build_state
= g_malloc0(sizeof *build_state
);
2751 acpi_set_pci_info();
2753 acpi_build_tables_init(&tables
);
2754 acpi_build(&tables
, MACHINE(pcms
));
2756 /* Now expose it all to Guest */
2757 build_state
->table_mr
= acpi_add_rom_blob(build_state
, tables
.table_data
,
2758 ACPI_BUILD_TABLE_FILE
,
2759 ACPI_BUILD_TABLE_MAX_SIZE
);
2760 assert(build_state
->table_mr
!= NULL
);
2762 build_state
->linker_mr
=
2763 acpi_add_rom_blob(build_state
, tables
.linker
->cmd_blob
,
2764 "etc/table-loader", 0);
2766 fw_cfg_add_file(pcms
->fw_cfg
, ACPI_BUILD_TPMLOG_FILE
,
2767 tables
.tcpalog
->data
, acpi_data_len(tables
.tcpalog
));
2769 if (!pcmc
->rsdp_in_ram
) {
2771 * Keep for compatibility with old machine types.
2772 * Though RSDP is small, its contents isn't immutable, so
2773 * we'll update it along with the rest of tables on guest access.
2775 uint32_t rsdp_size
= acpi_data_len(tables
.rsdp
);
2777 build_state
->rsdp
= g_memdup(tables
.rsdp
->data
, rsdp_size
);
2778 fw_cfg_add_file_callback(pcms
->fw_cfg
, ACPI_BUILD_RSDP_FILE
,
2779 acpi_build_update
, build_state
,
2780 build_state
->rsdp
, rsdp_size
);
2781 build_state
->rsdp_mr
= NULL
;
2783 build_state
->rsdp
= NULL
;
2784 build_state
->rsdp_mr
= acpi_add_rom_blob(build_state
, tables
.rsdp
,
2785 ACPI_BUILD_RSDP_FILE
, 0);
2788 qemu_register_reset(acpi_build_reset
, build_state
);
2789 acpi_build_reset(build_state
);
2790 vmstate_register(NULL
, 0, &vmstate_acpi_build
, build_state
);
2792 /* Cleanup tables but don't free the memory: we track it
2795 acpi_build_tables_cleanup(&tables
, false);